diff --git a/llvm/lib/Target/X86/X86InstrExtension.td b/llvm/lib/Target/X86/X86InstrExtension.td
--- a/llvm/lib/Target/X86/X86InstrExtension.td
+++ b/llvm/lib/Target/X86/X86InstrExtension.td
@@ -136,6 +136,7 @@
 // operand, which makes it a rare instruction with an 8-bit register
 // operand that can never access an h register. If support for h registers
 // were generalized, this would require a special register class.
+let Predicates = [In64BitMode] in {
 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
                     "movs{bq|x}\t{$src, $dst|$dst, $src}",
                     [(set GR64:$dst, (sext GR8:$src))]>, TB,
@@ -155,11 +156,12 @@
 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
                     "movs{lq|xd}\t{$src, $dst|$dst, $src}",
                     [(set GR64:$dst, (sext GR32:$src))]>,
-                    Sched<[WriteALU]>, Requires<[In64BitMode]>;
+                    Sched<[WriteALU]>;
 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
                     "movs{lq|xd}\t{$src, $dst|$dst, $src}",
                     [(set GR64:$dst, (sextloadi64i32 addr:$src))]>,
-                    Sched<[WriteLoad]>, Requires<[In64BitMode]>;
+                    Sched<[WriteLoad]>;
+}
 
 // These instructions exist as a consequence of operand size prefix having
 // control of the destination size, but not the input size. Only support them
@@ -182,7 +184,7 @@
 } // isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0
 
 // movzbq and movzwq encodings for the disassembler
-let hasSideEffects = 0 in {
+let hasSideEffects = 0, Predicates = [In64BitMode] in {
 def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src),
                      "movz{bq|x}\t{$src, $dst|$dst, $src}", []>,
                      TB, Sched<[WriteALU]>;