Index: llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
+++ llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -26,6 +26,7 @@
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/Casting.h"
+#include <optional>
 
 using namespace llvm;
 
@@ -35,8 +36,9 @@
   const MCRegisterInfo &MRI;
 
   /// Encode an fp or int literal
-  uint32_t getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo,
-                          const MCSubtargetInfo &STI) const;
+  std::optional<uint32_t> getLitEncoding(const MCOperand &MO,
+                                         const MCOperandInfo &OpInfo,
+                                         const MCSubtargetInfo &STI) const;
 
 public:
   SIMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
@@ -216,9 +218,10 @@
   return 255;
 }
 
-uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
-                                         const MCOperandInfo &OpInfo,
-                                         const MCSubtargetInfo &STI) const {
+std::optional<uint32_t>
+SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
+                                const MCOperandInfo &OpInfo,
+                                const MCSubtargetInfo &STI) const {
   int64_t Imm;
   if (MO.isExpr()) {
     const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr());
@@ -231,7 +234,7 @@
     assert(!MO.isDFPImm());
 
     if (!MO.isImm())
-      return ~0;
+      return std::nullopt;
 
     Imm = MO.getImm();
   }
@@ -381,7 +384,8 @@
 
     // Is this operand a literal immediate?
     const MCOperand &Op = MI.getOperand(i);
-    if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255)
+    auto Enc = getLitEncoding(Op, Desc.OpInfo[i], STI);
+    if (!Enc || *Enc != 255)
       continue;
 
     // Yes! Encode it
@@ -452,9 +456,9 @@
     return;
   } else {
     const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
-    uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
-    if (Enc != ~0U && Enc != 255) {
-      Op = Enc | SDWA9EncValues::SRC_SGPR_MASK;
+    auto Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
+    if (Enc && *Enc != 255) {
+      Op = *Enc | SDWA9EncValues::SRC_SGPR_MASK;
       return;
     }
   }
@@ -571,9 +575,8 @@
 
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
-    uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI);
-    if (Enc != ~0U) {
-      Op = Enc;
+    if (auto Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI)) {
+      Op = *Enc;
       return;
     }
   } else if (MO.isImm()) {
Index: llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
===================================================================
--- llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
+++ llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
@@ -10342,6 +10342,9 @@
 v_fmaak_f32 v5, v1, v2, 0xa1b1c1d1
 // GFX10: encoding: [0x01,0x05,0x0a,0x5a,0xd1,0xc1,0xb1,0xa1]
 
+v_fmaak_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x01,0x05,0x0a,0x5a,0xff,0xff,0xff,0xff]
+
 v_cvt_pkrtz_f16_f32_e32 v5, v1, v2
 // GFX10: encoding: [0x01,0x05,0x0a,0x5e]