Index: include/llvm/MC/MCTargetMachine.h =================================================================== --- /dev/null +++ include/llvm/MC/MCTargetMachine.h @@ -0,0 +1,136 @@ +//===-- llvm/MC/MCTargetMachine.h - Target Information ----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the MCTargetMachine classes. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCTARGETMACHINE_H +#define LLVM_MC_MCTARGETMACHINE_H + +#include "llvm/ADT/Triple.h" +#include "llvm/Support/CodeGen.h" + +namespace llvm { +class MCAsmBackend; +class MCAsmInfo; +class MCAsmParser; +class MCCodeEmitter; +class MCCodeGenInfo; +class MCContext; +class MCDisassembler; +class MCInstPrinter; +class MCInstrAnalysis; +class MCInstrInfo; +class MCRegisterInfo; +class MCStreamer; +class MCSubtargetInfo; +class MCTargetAsmParser; +class MCTargetOptions; +class MCTargetStreamer; +class Target; +class Triple; +class formatted_raw_ostream; +class raw_pwrite_stream; + +//===----------------------------------------------------------------------===// +/// +/// Primary interface to the complete machine description for the target +/// machine. All target-specific information should be accessible through this +/// interface. +/// +class MCTargetMachine { + MCTargetMachine(const MCTargetMachine &) = delete; + void operator=(const MCTargetMachine &) = delete; + +protected: + /// The Target that this machine was created for. + const Target &TheTarget; + + /// The Triple used to configure this machine. + /// TODO: Gradually break this up into the actual machine description. + const Triple TheTriple; + +public: + MCTargetMachine(const Target &T, const Triple &TT); + + const Target &getTarget() const { return TheTarget; } + + /// Create a MCAsmInfo implementation. + MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI) const; + + /// Create a MCCodeGenInfo implementation. + MCCodeGenInfo *createMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) const; + + /// Create a MCInstrInfo implementation. + MCInstrInfo *createMCInstrInfo() const; + + /// Create a MCInstrAnalysis implementation. + MCInstrAnalysis *createMCInstrAnalysis(const MCInstrInfo *Info) const; + + /// Create a MCRegisterInfo implementation. + MCRegisterInfo *createMCRegisterInfo() const; + + MCSubtargetInfo *createMCSubtargetInfo(StringRef CPU, + StringRef Features) const; + + /// Create a target specific assembly parser. + MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI, + StringRef CPU) const; + + /// Create a target specific assembly parser. + /// + /// \param Parser The target independent parser implementation to use for + /// parsing and lexing. + MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI, + MCAsmParser &Parser, + const MCInstrInfo &MII, + const MCTargetOptions &Options) const; + + MCDisassembler *createMCDisassembler(const MCInstrInfo &MII, + const MCSubtargetInfo &STI, + MCContext &Ctx) const; + + MCInstPrinter *createMCInstPrinter(unsigned SyntaxVariant, + const MCAsmInfo &MAI, + const MCInstrInfo &MII, + const MCRegisterInfo &MRI) const; + + /// Create a target specific code emitter. + MCCodeEmitter *createMCCodeEmitter(const MCInstrInfo &II, + const MCRegisterInfo &MRI, + MCContext &Ctx) const; + + /// Create a target specific MCStreamer. + /// + /// \param Ctx The target context. + /// \param TAB The target assembler backend object. Takes ownership. + /// \param OS The stream object. + /// \param Emitter The target independent assembler object.Takes ownership. + /// \param RelaxAll Relax all fixups? + MCStreamer *createMCObjectStreamer(MCContext &Ctx, MCAsmBackend &TAB, + raw_pwrite_stream &OS, + MCCodeEmitter *Emitter, + const MCSubtargetInfo &STI, bool RelaxAll, + bool DWARFMustBeAtTheEnd) const; + + MCStreamer *createAsmStreamer(MCContext &Ctx, + std::unique_ptr OS, + bool IsVerboseAsm, bool UseDwarfDirectory, + MCInstPrinter *InstPrint, MCCodeEmitter *CE, + MCAsmBackend *TAB, bool ShowInst) const; + + MCStreamer *createNullStreamer(MCContext &Ctx) const; + MCTargetStreamer *createNullTargetStreamer(MCStreamer &S) const; +}; + +} // End llvm namespace + +#endif Index: include/llvm/Support/TargetRegistry.h =================================================================== --- include/llvm/Support/TargetRegistry.h +++ include/llvm/Support/TargetRegistry.h @@ -45,6 +45,7 @@ class MCSymbolizer; class MCRelocationInfo; class MCTargetAsmParser; +class MCTargetMachine; class MCTargetOptions; class MCTargetStreamer; class TargetMachine; @@ -87,6 +88,7 @@ class Target { public: friend struct TargetRegistry; + friend class MCTargetMachine; typedef bool (*ArchMatchFnTy)(Triple::ArchType Arch); @@ -106,18 +108,20 @@ const Target &T, const Triple &TT, StringRef CPU, StringRef Features, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + typedef MCTargetMachine *(*MCTargetMachineCtorTy)(const Target &T, + const Triple &TT); // If it weren't for layering issues (this header is in llvm/Support, but // depends on MC?) this should take the Streamer by value rather than rvalue // reference. typedef AsmPrinter *(*AsmPrinterCtorTy)( TargetMachine &TM, std::unique_ptr &&Streamer); - typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, + typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); typedef MCTargetAsmParser *(*MCAsmParserCtorTy)( MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII, const MCTargetOptions &Options); - typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T, + typedef MCDisassembler *(*MCDisassemblerCtorTy)(const MCInstrInfo &MII, const MCSubtargetInfo &STI, MCContext &Ctx); typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Triple &T, @@ -200,6 +204,10 @@ /// TargetMachine, if registered. TargetMachineCtorTy TargetMachineCtorFn; + /// MCTargetMachineCtorFn - Construction function for this target's + /// MCTargetMachine, if registered. + MCTargetMachineCtorTy MCTargetMachineCtorFn; + /// MCAsmBackendCtorFn - Construction function for this target's /// MCAsmBackend, if registered. MCAsmBackendCtorTy MCAsmBackendCtorFn; @@ -278,6 +286,9 @@ /// hasTargetMachine - Check if this target supports code generation. bool hasTargetMachine() const { return TargetMachineCtorFn != nullptr; } + /// hasMCTargetMachine - Check if this target supports machine code. + bool hasMCTargetMachine() const { return MCTargetMachineCtorFn != nullptr; } + /// hasMCAsmBackend - Check if this target supports .o generation. bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != nullptr; } @@ -285,6 +296,7 @@ /// @name Feature Constructors /// @{ +protected: /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified /// target triple. /// @@ -325,9 +337,9 @@ return MCInstrAnalysisCtorFn(Info); } - /// createMCRegInfo - Create a MCRegisterInfo implementation. + /// createMCRegisterInfo - Create a MCRegisterInfo implementation. /// - MCRegisterInfo *createMCRegInfo(StringRef TT) const { + MCRegisterInfo *createMCRegisterInfo(StringRef TT) const { if (!MCRegInfoCtorFn) return nullptr; return MCRegInfoCtorFn(Triple(TT)); @@ -349,6 +361,7 @@ return MCSubtargetInfoCtorFn(Triple(TheTriple), CPU, Features); } +public: /// createTargetMachine - Create a target specific machine implementation /// for the specified \p Triple. /// @@ -368,14 +381,29 @@ CM, OL); } + /// createMCTargetMachine - Create a target specific machine implementation + /// for the specified \p Triple. + /// + /// \param TT This argument is used to determine the target machine + /// feature set; it should always be provided. Generally this should be + /// either the target triple from the module, or the target triple of the + /// host if that does not exist. + MCTargetMachine *createMCTargetMachine(const Triple &TT) const { + if (!MCTargetMachineCtorFn) + return nullptr; + return MCTargetMachineCtorFn(*this, TT); + } + +protected: /// createMCAsmBackend - Create a target specific assembly parser. /// /// \param TheTriple The target triple string. - MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI, + MCAsmBackend *createMCAsmBackend(const MCTargetMachine &MTM, + const MCRegisterInfo &MRI, StringRef TheTriple, StringRef CPU) const { if (!MCAsmBackendCtorFn) return nullptr; - return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU); + return MCAsmBackendCtorFn(MTM, MRI, Triple(TheTriple), CPU); } /// createMCAsmParser - Create a target specific assembly parser. @@ -391,6 +419,7 @@ return MCAsmParserCtorFn(STI, Parser, MII, Options); } +public: /// createAsmPrinter - Create a target specific assembly printer pass. This /// takes ownership of the MCStreamer object. AsmPrinter *createAsmPrinter(TargetMachine &TM, @@ -400,11 +429,13 @@ return AsmPrinterCtorFn(TM, std::move(Streamer)); } - MCDisassembler *createMCDisassembler(const MCSubtargetInfo &STI, +protected: + MCDisassembler *createMCDisassembler(const MCInstrInfo &MII, + const MCSubtargetInfo &STI, MCContext &Ctx) const { if (!MCDisassemblerCtorFn) return nullptr; - return MCDisassemblerCtorFn(*this, STI, Ctx); + return MCDisassemblerCtorFn(MII, STI, Ctx); } MCInstPrinter *createMCInstPrinter(const Triple &T, unsigned SyntaxVariant, @@ -500,6 +531,7 @@ return nullptr; } +public: /// createMCRelocationInfo - Create a target specific MCRelocationInfo. /// /// \param TT The target triple. @@ -717,6 +749,20 @@ T.TargetMachineCtorFn = Fn; } + /// RegisterMCTargetMachine - Register a MCTargetMachine implementation for + /// the given target. + /// + /// Clients are responsible for ensuring that registration doesn't occur + /// while another thread is attempting to access the registry. Typically + /// this is done by initializing all targets at program startup. + /// + /// @param T - The target being registered. + /// @param Fn - A function to construct a MCTargetMachine for the target. + static void RegisterMCTargetMachine(Target &T, + Target::MCTargetMachineCtorTy Fn) { + T.MCTargetMachineCtorFn = Fn; + } + /// RegisterMCAsmBackend - Register a MCAsmBackend implementation for the /// given target. /// @@ -1100,6 +1146,25 @@ } }; +/// RegisterMCTargetMachine - Helper template for registering a target machine +/// implementation, for use in the target machine initialization +/// function. Usage: +/// +/// extern "C" void LLVMInitializeFooTarget() { +/// extern Target TheFooTarget; +/// RegisterMCTargetMachine X(TheFooTarget); +/// } +template struct RegisterMCTargetMachine { + RegisterMCTargetMachine(Target &T) { + TargetRegistry::RegisterMCTargetMachine(T, &Allocator); + } + +private: + static MCTargetMachine *Allocator(const Target &T, const Triple &TT) { + return new MCTargetMachineImpl(T, TT); + } +}; + /// RegisterMCAsmBackend - Helper template for registering a target specific /// assembler backend. Usage: /// @@ -1113,9 +1178,10 @@ } private: - static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI, + static MCAsmBackend *Allocator(const MCTargetMachine &MTM, + const MCRegisterInfo &MRI, const Triple &TheTriple, StringRef CPU) { - return new MCAsmBackendImpl(T, MRI, TheTriple, CPU); + return new MCAsmBackendImpl(MTM, MRI, TheTriple, CPU); } }; Index: include/llvm/Target/TargetMachine.h =================================================================== --- include/llvm/Target/TargetMachine.h +++ include/llvm/Target/TargetMachine.h @@ -36,6 +36,7 @@ class MCRegisterInfo; class MCSubtargetInfo; class MCSymbol; +class MCTargetMachine; class Target; class DataLayout; class TargetLibraryInfo; @@ -90,6 +91,9 @@ std::string TargetCPU; std::string TargetFS; + // The MC-level target machine + const MCTargetMachine *MTM; + /// Low level target information such as relocation model. Non-const to /// allow resetting optimization level per-function. MCCodeGenInfo *CodeGenInfo; @@ -160,6 +164,7 @@ /// Return target specific asm information. const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; } + const MCTargetMachine *getMCTargetMachine() const { return MTM; } const MCRegisterInfo *getMCRegisterInfo() const { return MRI; } const MCInstrInfo *getMCInstrInfo() const { return MII; } const MCSubtargetInfo *getMCSubtargetInfo() const { return STI; } Index: lib/CodeGen/AsmPrinter/AsmPrinter.cpp =================================================================== --- lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -40,6 +40,7 @@ #include "llvm/MC/MCSection.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbolELF.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MCValue.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Format.h" @@ -222,9 +223,9 @@ if (!M.getModuleInlineAsm().empty()) { // We're at the module level. Construct MCSubtarget from the default CPU // and target triple. - std::unique_ptr STI(TM.getTarget().createMCSubtargetInfo( - TM.getTargetTriple().str(), TM.getTargetCPU(), - TM.getTargetFeatureString())); + std::unique_ptr STI( + TM.getMCTargetMachine()->createMCSubtargetInfo( + TM.getTargetCPU(), TM.getTargetFeatureString())); OutStreamer->AddComment("Start of file scope inline assembly"); OutStreamer->AddBlankLine(); EmitInlineAsm(M.getModuleInlineAsm()+"\n", *STI, TM.Options.MCOptions); Index: lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp =================================================================== --- lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp +++ lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp @@ -27,6 +27,7 @@ #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCTargetAsmParser.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" @@ -137,9 +138,11 @@ // and not have a MachineFunction to initialize the TargetInstrInfo from and // we only need MCInstrInfo for asm parsing. We create one unconditionally // because it's not subtarget dependent. - std::unique_ptr MII(TM.getTarget().createMCInstrInfo()); - std::unique_ptr TAP(TM.getTarget().createMCAsmParser( - TmpSTI, *Parser, *MII, MCOptions)); + std::unique_ptr MII( + TM.getMCTargetMachine()->createMCInstrInfo()); + std::unique_ptr TAP( + TM.getMCTargetMachine()->createMCAsmParser(TmpSTI, *Parser, *MII, + MCOptions)); if (!TAP) report_fatal_error("Inline asm not supported by this streamer because" " we don't have an asm parser for this target\n"); Index: lib/CodeGen/LLVMTargetMachine.cpp =================================================================== --- lib/CodeGen/LLVMTargetMachine.cpp +++ lib/CodeGen/LLVMTargetMachine.cpp @@ -26,6 +26,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FormattedStream.h" @@ -43,17 +44,15 @@ cl::desc("Enable the \"fast\" instruction selector")); void LLVMTargetMachine::initAsmInfo() { - MRI = TheTarget.createMCRegInfo(getTargetTriple().str()); - MII = TheTarget.createMCInstrInfo(); + MRI = MTM->createMCRegisterInfo(); + MII = MTM->createMCInstrInfo(); // FIXME: Having an MCSubtargetInfo on the target machine is a hack due // to some backends having subtarget feature dependent module level // code generation. This is similar to the hack in the AsmPrinter for // module level assembly etc. - STI = TheTarget.createMCSubtargetInfo(getTargetTriple().str(), getTargetCPU(), - getTargetFeatureString()); + STI = MTM->createMCSubtargetInfo(getTargetCPU(), getTargetFeatureString()); - MCAsmInfo *TmpAsmInfo = - TheTarget.createMCAsmInfo(*MRI, getTargetTriple().str()); + MCAsmInfo *TmpAsmInfo = MTM->createMCAsmInfo(*MRI); // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0, // and if the old one gets included then MCAsmInfo will be NULL and // we'll crash later. @@ -78,7 +77,8 @@ Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) : TargetMachine(T, DataLayoutString, TT, CPU, FS, Options) { - CodeGenInfo = T.createMCCodeGenInfo(TT.str(), RM, CM, OL); + MTM = TheTarget.createMCTargetMachine(getTargetTriple()); + CodeGenInfo = MTM->createMCCodeGenInfo(RM, CM, OL); } TargetIRAnalysis LLVMTargetMachine::getTargetIRAnalysis() { @@ -169,18 +169,17 @@ switch (FileType) { case CGFT_AssemblyFile: { - MCInstPrinter *InstPrinter = getTarget().createMCInstPrinter( - getTargetTriple(), MAI.getAssemblerDialect(), MAI, MII, MRI); + MCInstPrinter *InstPrinter = + MTM->createMCInstPrinter(MAI.getAssemblerDialect(), MAI, MII, MRI); // Create a code emitter if asked to show the encoding. MCCodeEmitter *MCE = nullptr; if (Options.MCOptions.ShowMCEncoding) - MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context); + MCE = MTM->createMCCodeEmitter(MII, MRI, *Context); - MCAsmBackend *MAB = - getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU); + MCAsmBackend *MAB = MTM->createMCAsmBackend(MRI, TargetCPU); auto FOut = llvm::make_unique(Out); - MCStreamer *S = getTarget().createAsmStreamer( + MCStreamer *S = MTM->createAsmStreamer( *Context, std::move(FOut), Options.MCOptions.AsmVerbose, Options.MCOptions.MCUseDwarfDirectory, InstPrinter, MCE, MAB, Options.MCOptions.ShowMCInst); @@ -190,25 +189,23 @@ case CGFT_ObjectFile: { // Create the code emitter for the target if it exists. If not, .o file // emission fails. - MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, *Context); - MCAsmBackend *MAB = - getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU); + MCCodeEmitter *MCE = MTM->createMCCodeEmitter(MII, MRI, *Context); + MCAsmBackend *MAB = MTM->createMCAsmBackend(MRI, TargetCPU); if (!MCE || !MAB) return true; // Don't waste memory on names of temp labels. Context->setUseNamesOnTempLabels(false); - Triple T(getTargetTriple().str()); - AsmStreamer.reset(getTarget().createMCObjectStreamer( - T, *Context, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll, + AsmStreamer.reset(MTM->createMCObjectStreamer( + *Context, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll, /*DWARFMustBeAtTheEnd*/ true)); break; } case CGFT_Null: // The Null output is intended for use for performance analysis and testing, // not real users. - AsmStreamer.reset(getTarget().createNullStreamer(*Context)); + AsmStreamer.reset(MTM->createNullStreamer(*Context)); break; } @@ -243,17 +240,14 @@ // Create the code emitter for the target if it exists. If not, .o file // emission fails. const MCRegisterInfo &MRI = *getMCRegisterInfo(); - MCCodeEmitter *MCE = - getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx); - MCAsmBackend *MAB = - getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU); + MCCodeEmitter *MCE = MTM->createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx); + MCAsmBackend *MAB = MTM->createMCAsmBackend(MRI, TargetCPU); if (!MCE || !MAB) return true; - const Triple &T = getTargetTriple(); const MCSubtargetInfo &STI = *getMCSubtargetInfo(); - std::unique_ptr AsmStreamer(getTarget().createMCObjectStreamer( - T, *Ctx, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll, + std::unique_ptr AsmStreamer(MTM->createMCObjectStreamer( + *Ctx, *MAB, Out, MCE, STI, Options.MCOptions.MCRelaxAll, /*DWARFMustBeAtTheEnd*/ true)); // Create the AsmPrinter, which takes ownership of AsmStreamer if successful. Index: lib/MC/CMakeLists.txt =================================================================== --- lib/MC/CMakeLists.txt +++ lib/MC/CMakeLists.txt @@ -39,6 +39,7 @@ MCSymbolELF.cpp MCSymbolizer.cpp MCTargetOptions.cpp + MCTargetMachine.cpp MCValue.cpp MCWin64EH.cpp MCWinEH.cpp Index: lib/MC/MCDisassembler/Disassembler.h =================================================================== --- lib/MC/MCDisassembler/Disassembler.h +++ lib/MC/MCDisassembler/Disassembler.h @@ -30,6 +30,7 @@ class MCInstrInfo; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetMachine; class Target; // @@ -58,6 +59,8 @@ // FIXME: using std::unique_ptr causes a malloc error // when this LLVMDisasmContext is deleted. const Target *TheTarget; + // The target machine for the target architecture. + std::unique_ptr MTM; // The assembly information for the target architecture. std::unique_ptr MAI; // The register information for the target architecture. @@ -85,16 +88,15 @@ LLVMDisasmContext(std::string tripleName, void *disInfo, int tagType, LLVMOpInfoCallback getOpInfo, LLVMSymbolLookupCallback symbolLookUp, - const Target *theTarget, const MCAsmInfo *mAI, - const MCRegisterInfo *mRI, - const MCSubtargetInfo *mSI, - const MCInstrInfo *mII, + const Target *theTarget, const MCTargetMachine *mTM, + const MCAsmInfo *mAI, const MCRegisterInfo *mRI, + const MCSubtargetInfo *mSI, const MCInstrInfo *mII, llvm::MCContext *ctx, const MCDisassembler *disAsm, - MCInstPrinter *iP) : TripleName(tripleName), - DisInfo(disInfo), TagType(tagType), GetOpInfo(getOpInfo), - SymbolLookUp(symbolLookUp), TheTarget(theTarget), - Options(0), - CommentStream(CommentsToEmit) { + MCInstPrinter *iP) + : TripleName(tripleName), DisInfo(disInfo), TagType(tagType), + GetOpInfo(getOpInfo), SymbolLookUp(symbolLookUp), TheTarget(theTarget), + Options(0), CommentStream(CommentsToEmit) { + MTM.reset(mTM); MAI.reset(mAI); MRI.reset(mRI); MSI.reset(mSI); @@ -111,6 +113,7 @@ return SymbolLookUp; } const Target *getTarget() const { return TheTarget; } + const MCTargetMachine *getMCTargetMachine() { return MTM.get(); } const MCDisassembler *getDisAsm() const { return DisAsm.get(); } const MCAsmInfo *getAsmInfo() const { return MAI.get(); } const MCInstrInfo *getInstrInfo() const { return MII.get(); } Index: lib/MC/MCDisassembler/Disassembler.cpp =================================================================== --- lib/MC/MCDisassembler/Disassembler.cpp +++ lib/MC/MCDisassembler/Disassembler.cpp @@ -19,6 +19,7 @@ #include "llvm/MC/MCRelocationInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbolizer.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/TargetRegistry.h" @@ -33,31 +34,35 @@ // disassembler context. If not, it returns NULL. // LLVMDisasmContextRef -LLVMCreateDisasmCPUFeatures(const char *TT, const char *CPU, +LLVMCreateDisasmCPUFeatures(const char *TTStr, const char *CPU, const char *Features, void *DisInfo, int TagType, LLVMOpInfoCallback GetOpInfo, LLVMSymbolLookupCallback SymbolLookUp) { // Get the target. std::string Error; - const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); + const Target *TheTarget = TargetRegistry::lookupTarget(TTStr, Error); if (!TheTarget) return nullptr; - const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(TT); + Triple TT(TTStr); + const MCTargetMachine *MTM = TheTarget->createMCTargetMachine(TT); + if (!MTM) + return nullptr; + + const MCRegisterInfo *MRI = MTM->createMCRegisterInfo(); if (!MRI) return nullptr; // Get the assembler info needed to setup the MCContext. - const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, TT); + const MCAsmInfo *MAI = MTM->createMCAsmInfo(*MRI); if (!MAI) return nullptr; - const MCInstrInfo *MII = TheTarget->createMCInstrInfo(); + const MCInstrInfo *MII = MTM->createMCInstrInfo(); if (!MII) return nullptr; - const MCSubtargetInfo *STI = - TheTarget->createMCSubtargetInfo(TT, CPU, Features); + const MCSubtargetInfo *STI = MTM->createMCSubtargetInfo(CPU, Features); if (!STI) return nullptr; @@ -67,29 +72,29 @@ return nullptr; // Set up disassembler. - MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI, *Ctx); + MCDisassembler *DisAsm = MTM->createMCDisassembler(*MII, *STI, *Ctx); if (!DisAsm) return nullptr; std::unique_ptr RelInfo( - TheTarget->createMCRelocationInfo(TT, *Ctx)); + TheTarget->createMCRelocationInfo(TTStr, *Ctx)); if (!RelInfo) return nullptr; std::unique_ptr Symbolizer(TheTarget->createMCSymbolizer( - TT, GetOpInfo, SymbolLookUp, DisInfo, Ctx, std::move(RelInfo))); + TTStr, GetOpInfo, SymbolLookUp, DisInfo, Ctx, std::move(RelInfo))); DisAsm->setSymbolizer(std::move(Symbolizer)); // Set up the instruction printer. int AsmPrinterVariant = MAI->getAssemblerDialect(); - MCInstPrinter *IP = TheTarget->createMCInstPrinter( - Triple(TT), AsmPrinterVariant, *MAI, *MII, *MRI); + MCInstPrinter *IP = + MTM->createMCInstPrinter(AsmPrinterVariant, *MAI, *MII, *MRI); if (!IP) return nullptr; LLVMDisasmContext *DC = - new LLVMDisasmContext(TT, DisInfo, TagType, GetOpInfo, SymbolLookUp, - TheTarget, MAI, MRI, STI, MII, Ctx, DisAsm, IP); + new LLVMDisasmContext(TTStr, DisInfo, TagType, GetOpInfo, SymbolLookUp, + TheTarget, MTM, MAI, MRI, STI, MII, Ctx, DisAsm, IP); if (!DC) return nullptr; @@ -309,8 +314,8 @@ const MCRegisterInfo *MRI = DC->getRegisterInfo(); int AsmPrinterVariant = MAI->getAssemblerDialect(); AsmPrinterVariant = AsmPrinterVariant == 0 ? 1 : 0; - MCInstPrinter *IP = DC->getTarget()->createMCInstPrinter( - Triple(DC->getTripleName()), AsmPrinterVariant, *MAI, *MII, *MRI); + MCInstPrinter *IP = DC->getMCTargetMachine()->createMCInstPrinter( + AsmPrinterVariant, *MAI, *MII, *MRI); if (IP) { DC->setIP(IP); DC->addOptions(LLVMDisassembler_Option_AsmPrinterVariant); Index: lib/MC/MCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/MC/MCTargetMachine.cpp @@ -0,0 +1,103 @@ +//===-- MCTargetMachine.cpp - General Target Information -------------------==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the general parts of a MC Target machine. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCTargetMachine.h" +#include "llvm/Support/TargetRegistry.h" +using namespace llvm; + +MCTargetMachine::MCTargetMachine(const Target &T, const Triple &TT) + : TheTarget(T), TheTriple(TT) {} + +MCAsmInfo *MCTargetMachine::createMCAsmInfo(const MCRegisterInfo &MRI) const { + return TheTarget.createMCAsmInfo(MRI, TheTriple.str()); +} + +MCCodeGenInfo * +MCTargetMachine::createMCCodeGenInfo(Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) const { + return TheTarget.createMCCodeGenInfo(TheTriple.str(), RM, CM, OL); +} + +MCInstrInfo *MCTargetMachine::createMCInstrInfo() const { + return TheTarget.createMCInstrInfo(); +} + +MCInstrAnalysis * +MCTargetMachine::createMCInstrAnalysis(const MCInstrInfo *Info) const { + return TheTarget.createMCInstrAnalysis(Info); +} + +MCRegisterInfo *MCTargetMachine::createMCRegisterInfo() const { + return TheTarget.createMCRegisterInfo(TheTriple.str()); +} + +MCSubtargetInfo * +MCTargetMachine::createMCSubtargetInfo(StringRef CPU, + StringRef Features) const { + return TheTarget.createMCSubtargetInfo(TheTriple.str(), CPU, Features); +} + +MCAsmBackend *MCTargetMachine::createMCAsmBackend(const MCRegisterInfo &MRI, + StringRef CPU) const { + return TheTarget.createMCAsmBackend(*this, MRI, TheTriple.str(), CPU); +}; + +MCTargetAsmParser * +MCTargetMachine::createMCAsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser, + const MCInstrInfo &MII, + const MCTargetOptions &Options) const { + return TheTarget.createMCAsmParser(STI, Parser, MII, Options); +} + +MCDisassembler *MCTargetMachine::createMCDisassembler( + const MCInstrInfo &MII, const MCSubtargetInfo &STI, MCContext &Ctx) const { + return TheTarget.createMCDisassembler(MII, STI, Ctx); +} + +MCInstPrinter *MCTargetMachine::createMCInstPrinter( + unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, + const MCRegisterInfo &MRI) const { + return TheTarget.createMCInstPrinter(TheTriple, SyntaxVariant, MAI, MII, MRI); +} + +MCCodeEmitter *MCTargetMachine::createMCCodeEmitter(const MCInstrInfo &II, + const MCRegisterInfo &MRI, + MCContext &Ctx) const { + return TheTarget.createMCCodeEmitter(II, MRI, Ctx); +} + +MCStreamer *MCTargetMachine::createMCObjectStreamer( + MCContext &Ctx, MCAsmBackend &TAB, raw_pwrite_stream &OS, + MCCodeEmitter *Emitter, const MCSubtargetInfo &STI, bool RelaxAll, + bool DWARFMustBeAtTheEnd) const { + return TheTarget.createMCObjectStreamer(TheTriple, Ctx, TAB, OS, Emitter, STI, + RelaxAll, DWARFMustBeAtTheEnd); +} + +MCStreamer *MCTargetMachine::createAsmStreamer( + MCContext &Ctx, std::unique_ptr OS, + bool IsVerboseAsm, bool UseDwarfDirectory, MCInstPrinter *InstPrint, + MCCodeEmitter *CE, MCAsmBackend *TAB, bool ShowInst) const { + return TheTarget.createAsmStreamer(Ctx, std::move(OS), IsVerboseAsm, + UseDwarfDirectory, InstPrint, CE, TAB, + ShowInst); +} + +MCStreamer *MCTargetMachine::createNullStreamer(MCContext &Ctx) const { + return TheTarget.createNullStreamer(Ctx); +} + +MCTargetStreamer * +MCTargetMachine::createNullTargetStreamer(MCStreamer &S) const { + return TheTarget.createNullTargetStreamer(S); +} Index: lib/Object/IRObjectFile.cpp =================================================================== --- lib/Object/IRObjectFile.cpp +++ lib/Object/IRObjectFile.cpp @@ -27,6 +27,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCTargetAsmParser.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Object/ObjectFile.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" @@ -49,20 +50,23 @@ if (!T) return; - std::unique_ptr MRI(T->createMCRegInfo(TT.str())); + std::unique_ptr MTM(T->createMCTargetMachine(TT)); + if (!MTM) + return; + + std::unique_ptr MRI(MTM->createMCRegisterInfo()); if (!MRI) return; - std::unique_ptr MAI(T->createMCAsmInfo(*MRI, TT.str())); + std::unique_ptr MAI(MTM->createMCAsmInfo(*MRI)); if (!MAI) return; - std::unique_ptr STI( - T->createMCSubtargetInfo(TT.str(), "", "")); + std::unique_ptr STI(MTM->createMCSubtargetInfo("", "")); if (!STI) return; - std::unique_ptr MCII(T->createMCInstrInfo()); + std::unique_ptr MCII(MTM->createMCInstrInfo()); if (!MCII) return; @@ -70,7 +74,7 @@ MCContext MCCtx(MAI.get(), MRI.get(), &MOFI); MOFI.InitMCObjectFileInfo(TT, Reloc::Default, CodeModel::Default, MCCtx); std::unique_ptr Streamer(new RecordStreamer(MCCtx)); - T->createNullTargetStreamer(*Streamer); + MTM->createNullTargetStreamer(*Streamer); std::unique_ptr Buffer(MemoryBuffer::getMemBuffer(InlineAsm)); SourceMgr SrcMgr; @@ -80,7 +84,7 @@ MCTargetOptions MCOptions; std::unique_ptr TAP( - T->createMCAsmParser(*STI, *Parser, *MCII, MCOptions)); + MTM->createMCAsmParser(*STI, *Parser, *MCII, MCOptions)); if (!TAP) return; Index: lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp =================================================================== --- lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -200,9 +200,9 @@ #define Fail llvm::MCDisassembler::Fail #define SoftFail llvm::MCDisassembler::SoftFail -static MCDisassembler *createAArch64Disassembler(const Target &T, - const MCSubtargetInfo &STI, - MCContext &Ctx) { +static MCDisassembler *createAArch64Disassembler(const MCInstrInfo &, + const MCSubtargetInfo &STI, + MCContext &Ctx) { return new AArch64Disassembler(STI, Ctx); } Index: lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp @@ -30,7 +30,7 @@ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits | MCFixupKindInfo::FKF_IsPCRel; public: - AArch64AsmBackend(const Target &T) : MCAsmBackend() {} + AArch64AsmBackend() : MCAsmBackend() {} unsigned getNumFixupKinds() const override { return AArch64::NumTargetFixupKinds; @@ -307,8 +307,8 @@ } public: - DarwinAArch64AsmBackend(const Target &T, const MCRegisterInfo &MRI) - : AArch64AsmBackend(T), MRI(MRI) {} + DarwinAArch64AsmBackend(const MCRegisterInfo &MRI) + : AArch64AsmBackend(), MRI(MRI) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createAArch64MachObjectWriter(OS, MachO::CPU_TYPE_ARM64, @@ -455,8 +455,8 @@ uint8_t OSABI; bool IsLittleEndian; - ELFAArch64AsmBackend(const Target &T, uint8_t OSABI, bool IsLittleEndian) - : AArch64AsmBackend(T), OSABI(OSABI), IsLittleEndian(IsLittleEndian) {} + ELFAArch64AsmBackend(uint8_t OSABI, bool IsLittleEndian) + : AArch64AsmBackend(), OSABI(OSABI), IsLittleEndian(IsLittleEndian) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createAArch64ELFObjectWriter(OS, OSABI, IsLittleEndian); @@ -519,25 +519,25 @@ } } -MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T, +MCAsmBackend *llvm::createAArch64leAsmBackend(const MCTargetMachine &, const MCRegisterInfo &MRI, const Triple &TheTriple, StringRef CPU) { if (TheTriple.isOSBinFormatMachO()) - return new DarwinAArch64AsmBackend(T, MRI); + return new DarwinAArch64AsmBackend(MRI); assert(TheTriple.isOSBinFormatELF() && "Expect either MachO or ELF target"); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); - return new ELFAArch64AsmBackend(T, OSABI, /*IsLittleEndian=*/true); + return new ELFAArch64AsmBackend(OSABI, /*IsLittleEndian=*/true); } -MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T, +MCAsmBackend *llvm::createAArch64beAsmBackend(const MCTargetMachine &, const MCRegisterInfo &MRI, const Triple &TheTriple, StringRef CPU) { assert(TheTriple.isOSBinFormatELF() && "Big endian is only supported for ELF targets!"); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); - return new ELFAArch64AsmBackend(T, OSABI, + return new ELFAArch64AsmBackend(OSABI, /*IsLittleEndian=*/false); } Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h +++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h @@ -28,6 +28,7 @@ class MCObjectWriter; class MCStreamer; class MCSubtargetInfo; +class MCTargetMachine; class MCTargetStreamer; class StringRef; class Target; @@ -42,10 +43,10 @@ MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createAArch64leAsmBackend(const Target &T, +MCAsmBackend *createAArch64leAsmBackend(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); -MCAsmBackend *createAArch64beAsmBackend(const Target &T, +MCAsmBackend *createAArch64beAsmBackend(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp @@ -20,6 +20,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" @@ -136,6 +137,8 @@ extern "C" void LLVMInitializeAArch64TargetMC() { for (Target *T : {&TheAArch64leTarget, &TheAArch64beTarget, &TheARM64Target}) { + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -42,8 +42,7 @@ class AMDGPUAsmBackend : public MCAsmBackend { public: - AMDGPUAsmBackend(const Target &T) - : MCAsmBackend() {} + AMDGPUAsmBackend() : MCAsmBackend() {} unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; }; void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, @@ -162,8 +161,7 @@ bool Is64Bit; public: - ELFAMDGPUAsmBackend(const Target &T, bool Is64Bit) : - AMDGPUAsmBackend(T), Is64Bit(Is64Bit) { } + ELFAMDGPUAsmBackend(bool Is64Bit) : AMDGPUAsmBackend(), Is64Bit(Is64Bit) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createAMDGPUELFObjectWriter(Is64Bit, OS); @@ -172,11 +170,9 @@ } // end anonymous namespace -MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, +MCAsmBackend *llvm::createAMDGPUAsmBackend(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { - Triple TargetTriple(TT); - // Use 64-bit ELF for amdgcn - return new ELFAMDGPUAsmBackend(T, TargetTriple.getArch() == Triple::amdgcn); + return new ELFAMDGPUAsmBackend(TT.getArch() == Triple::amdgcn); } Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h @@ -27,6 +27,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetMachine; class Target; class Triple; class raw_pwrite_stream; @@ -43,7 +44,8 @@ const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, +MCAsmBackend *createAMDGPUAsmBackend(const MCTargetMachine &MTM, + const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit, Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp @@ -24,6 +24,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" @@ -97,6 +98,7 @@ extern "C" void LLVMInitializeAMDGPUTargetMC() { for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) { + RegisterMCTargetMachine Y(*T); RegisterMCAsmInfo X(*T); TargetRegistry::RegisterMCCodeGenInfo(*T, createAMDGPUMCCodeGenInfo); Index: lib/Target/ARM/Disassembler/ARMDisassembler.cpp =================================================================== --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -395,13 +395,13 @@ uint64_t Address, const void *Decoder); #include "ARMGenDisassemblerTables.inc" -static MCDisassembler *createARMDisassembler(const Target &T, +static MCDisassembler *createARMDisassembler(const MCInstrInfo &, const MCSubtargetInfo &STI, MCContext &Ctx) { return new ARMDisassembler(STI, Ctx); } -static MCDisassembler *createThumbDisassembler(const Target &T, +static MCDisassembler *createThumbDisassembler(const MCInstrInfo &, const MCSubtargetInfo &STI, MCContext &Ctx) { return new ThumbDisassembler(STI, Ctx); Index: lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h +++ lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h @@ -23,7 +23,7 @@ bool isThumbMode; // Currently emitting Thumb code. bool IsLittleEndian; // Big or little endian. public: - ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle) + ARMAsmBackend(const Triple &TT, bool IsLittle) : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), isThumbMode(TT.getArchName().startswith("thumb")), IsLittleEndian(IsLittle) {} Index: lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -812,8 +812,7 @@ } } -MCAsmBackend *llvm::createARMAsmBackend(const Target &T, - const MCRegisterInfo &MRI, +MCAsmBackend *llvm::createARMAsmBackend(const MCRegisterInfo &MRI, const Triple &TheTriple, StringRef CPU, bool isLittle) { switch (TheTriple.getObjectFormat()) { @@ -821,38 +820,38 @@ llvm_unreachable("unsupported object format"); case Triple::MachO: { MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName()); - return new ARMAsmBackendDarwin(T, TheTriple, CS); + return new ARMAsmBackendDarwin(TheTriple, CS); } case Triple::COFF: assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); - return new ARMAsmBackendWinCOFF(T, TheTriple); + return new ARMAsmBackendWinCOFF(TheTriple); case Triple::ELF: assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target"); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); - return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle); + return new ARMAsmBackendELF(TheTriple, OSABI, isLittle); } } -MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, +MCAsmBackend *llvm::createARMLEAsmBackend(const MCTargetMachine &, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { - return createARMAsmBackend(T, MRI, TT, CPU, true); + return createARMAsmBackend(MRI, TT, CPU, true); } -MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, +MCAsmBackend *llvm::createARMBEAsmBackend(const MCTargetMachine &, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { - return createARMAsmBackend(T, MRI, TT, CPU, false); + return createARMAsmBackend(MRI, TT, CPU, false); } -MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T, +MCAsmBackend *llvm::createThumbLEAsmBackend(const MCTargetMachine &, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { - return createARMAsmBackend(T, MRI, TT, CPU, true); + return createARMAsmBackend(MRI, TT, CPU, true); } -MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T, +MCAsmBackend *llvm::createThumbBEAsmBackend(const MCTargetMachine &, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { - return createARMAsmBackend(T, MRI, TT, CPU, false); + return createARMAsmBackend(MRI, TT, CPU, false); } Index: lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h +++ lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h @@ -18,9 +18,8 @@ class ARMAsmBackendDarwin : public ARMAsmBackend { public: const MachO::CPUSubTypeARM Subtype; - ARMAsmBackendDarwin(const Target &T, const Triple &TT, - MachO::CPUSubTypeARM st) - : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), Subtype(st) { + ARMAsmBackendDarwin(const Triple &TT, MachO::CPUSubTypeARM st) + : ARMAsmBackend(TT, /* IsLittleEndian */ true), Subtype(st) { HasDataInCodeSupport = true; } Index: lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h +++ lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h @@ -15,9 +15,8 @@ class ARMAsmBackendELF : public ARMAsmBackend { public: uint8_t OSABI; - ARMAsmBackendELF(const Target &T, const Triple &TT, uint8_t OSABI, - bool IsLittle) - : ARMAsmBackend(T, TT, IsLittle), OSABI(OSABI) {} + ARMAsmBackendELF(const Triple &TT, uint8_t OSABI, bool IsLittle) + : ARMAsmBackend(TT, IsLittle), OSABI(OSABI) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createARMELFObjectWriter(OS, OSABI, isLittle()); Index: lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h +++ lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h @@ -15,8 +15,8 @@ namespace { class ARMAsmBackendWinCOFF : public ARMAsmBackend { public: - ARMAsmBackendWinCOFF(const Target &T, const Triple &TheTriple) - : ARMAsmBackend(T, TheTriple, true) {} + ARMAsmBackendWinCOFF(const Triple &TheTriple) + : ARMAsmBackend(TheTriple, true) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createARMWinCOFFObjectWriter(OS, /*Is64Bit=*/false); } Index: lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h +++ lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h @@ -29,6 +29,7 @@ class MCSubtargetInfo; class MCStreamer; class MCRelocationInfo; +class MCTargetMachine; class MCTargetStreamer; class StringRef; class Target; @@ -64,21 +65,22 @@ const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU, - bool IsLittleEndian); +MCAsmBackend *createARMAsmBackend(const MCRegisterInfo &MRI, const Triple &TT, + StringRef CPU, bool IsLittleEndian); -MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); +MCAsmBackend *createARMLEAsmBackend(const MCTargetMachine &MTM, + const MCRegisterInfo &MRI, const Triple &TT, + StringRef CPU); -MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); +MCAsmBackend *createARMBEAsmBackend(const MCTargetMachine &MTM, + const MCRegisterInfo &MRI, const Triple &TT, + StringRef CPU); -MCAsmBackend *createThumbLEAsmBackend(const Target &T, +MCAsmBackend *createThumbLEAsmBackend(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); -MCAsmBackend *createThumbBEAsmBackend(const Target &T, +MCAsmBackend *createThumbBEAsmBackend(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); Index: lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -23,6 +23,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" @@ -377,6 +378,8 @@ extern "C" void LLVMInitializeARMTargetMC() { for (Target *T : {&TheARMLETarget, &TheARMBETarget, &TheThumbLETarget, &TheThumbBETarget}) { + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo); Index: lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp =================================================================== --- lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp +++ lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp @@ -93,13 +93,13 @@ } } -MCAsmBackend *llvm::createBPFAsmBackend(const Target &T, +MCAsmBackend *llvm::createBPFAsmBackend(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { return new BPFAsmBackend(/*IsLittleEndian=*/true); } -MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T, +MCAsmBackend *llvm::createBPFbeAsmBackend(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { return new BPFAsmBackend(/*IsLittleEndian=*/false); Index: lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h =================================================================== --- lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h +++ lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h @@ -25,6 +25,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetMachine; class StringRef; class Target; class Triple; @@ -42,10 +43,12 @@ const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); -MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); +MCAsmBackend *createBPFAsmBackend(const MCTargetMachine &MTM, + const MCRegisterInfo &MRI, const Triple &TT, + StringRef CPU); +MCAsmBackend *createBPFbeAsmBackend(const MCTargetMachine &MTM, + const MCRegisterInfo &MRI, const Triple &TT, + StringRef CPU); MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian); Index: lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp =================================================================== --- lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp +++ lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp @@ -20,6 +20,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" @@ -78,6 +79,8 @@ extern "C" void LLVMInitializeBPFTargetMC() { for (Target *T : {&TheBPFleTarget, &TheBPFbeTarget, &TheBPFTarget}) { + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. RegisterMCAsmInfo X(*T); Index: lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp =================================================================== --- lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -230,7 +230,7 @@ #include "HexagonGenDisassemblerTables.inc" -static MCDisassembler *createHexagonDisassembler(Target const &T, +static MCDisassembler *createHexagonDisassembler(const MCInstrInfo &, MCSubtargetInfo const &STI, MCContext &Ctx) { return new HexagonDisassembler(STI, Ctx); Index: lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -17,6 +17,7 @@ #include "llvm/MC/MCELFObjectWriter.h" #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/TargetRegistry.h" @@ -34,8 +35,9 @@ std::unique_ptr MCII; std::unique_ptr RelaxTarget; public: - HexagonAsmBackend(Target const &T, uint8_t OSABI, StringRef CPU) : - OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *){} + HexagonAsmBackend(const MCTargetMachine &MCTM, uint8_t OSABI, StringRef CPU) + : OSABI(OSABI), MCII(MCTM.createMCInstrInfo()), + RelaxTarget(new MCInst *) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createHexagonELFObjectWriter(OS, OSABI, CPU); @@ -307,10 +309,10 @@ } // end anonymous namespace namespace llvm { -MCAsmBackend *createHexagonAsmBackend(Target const &T, +MCAsmBackend *createHexagonAsmBackend(const MCTargetMachine &MTM, MCRegisterInfo const & /*MRI*/, const Triple &TT, StringRef CPU) { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); - return new HexagonAsmBackend(T, OSABI, CPU); + return new HexagonAsmBackend(MTM, OSABI, CPU); } } Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -26,6 +26,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetMachine; class Target; class Triple; class StringRef; @@ -42,7 +43,7 @@ MCRegisterInfo const &MRI, MCContext &MCT); -MCAsmBackend *createHexagonAsmBackend(Target const &T, +MCAsmBackend *createHexagonAsmBackend(const MCTargetMachine &MTM, MCRegisterInfo const &MRI, const Triple &TT, StringRef CPU); Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -24,6 +24,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" @@ -191,6 +192,8 @@ // Force static initialization. extern "C" void LLVMInitializeHexagonTargetMC() { + RegisterMCTargetMachine Y(TheHexagonTarget); + // Register the MC asm info. RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo); Index: lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp =================================================================== --- lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp +++ lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -18,6 +18,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -68,6 +69,8 @@ } extern "C" void LLVMInitializeMSP430TargetMC() { + RegisterMCTargetMachine Y(TheMSP430Target); + // Register the MC asm info. RegisterMCAsmInfo X(TheMSP430Target); Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -463,17 +463,15 @@ TheMips64elTarget; } -static MCDisassembler *createMipsDisassembler( - const Target &T, - const MCSubtargetInfo &STI, - MCContext &Ctx) { +static MCDisassembler *createMipsDisassembler(const MCInstrInfo &, + const MCSubtargetInfo &STI, + MCContext &Ctx) { return new MipsDisassembler(STI, Ctx, true); } -static MCDisassembler *createMipselDisassembler( - const Target &T, - const MCSubtargetInfo &STI, - MCContext &Ctx) { +static MCDisassembler *createMipselDisassembler(const MCInstrInfo &, + const MCSubtargetInfo &STI, + MCContext &Ctx) { return new MipsDisassembler(STI, Ctx, false); } Index: lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h +++ lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h @@ -32,8 +32,7 @@ bool Is64Bit; // 32 or 64 bit words public: - MipsAsmBackend(const Target &T, Triple::OSType OSType, bool IsLittle, - bool Is64Bit) + MipsAsmBackend(Triple::OSType OSType, bool IsLittle, bool Is64Bit) : MCAsmBackend(), OSType(OSType), IsLittle(IsLittle), Is64Bit(Is64Bit) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override; Index: lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -409,29 +409,29 @@ } // MCAsmBackend -MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, +MCAsmBackend *llvm::createMipsAsmBackendEL32(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { - return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, + return new MipsAsmBackend(TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ false); } -MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, +MCAsmBackend *llvm::createMipsAsmBackendEB32(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { - return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, + return new MipsAsmBackend(TT.getOS(), /*IsLittle*/ false, /*Is64Bit*/ false); } -MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, +MCAsmBackend *llvm::createMipsAsmBackendEL64(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { - return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true); + return new MipsAsmBackend(TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true); } -MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, +MCAsmBackend *llvm::createMipsAsmBackendEB64(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { - return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, + return new MipsAsmBackend(TT.getOS(), /*IsLittle*/ false, /*Is64Bit*/ true); } Index: lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -24,6 +24,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetMachine; class StringRef; class Target; class Triple; @@ -42,16 +43,16 @@ const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createMipsAsmBackendEB32(const Target &T, +MCAsmBackend *createMipsAsmBackendEB32(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); -MCAsmBackend *createMipsAsmBackendEL32(const Target &T, +MCAsmBackend *createMipsAsmBackendEL32(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); -MCAsmBackend *createMipsAsmBackendEB64(const Target &T, +MCAsmBackend *createMipsAsmBackendEB64(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); -MCAsmBackend *createMipsAsmBackendEL64(const Target &T, +MCAsmBackend *createMipsAsmBackendEL64(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); Index: lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -23,6 +23,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/CommandLine.h" @@ -132,6 +133,8 @@ extern "C" void LLVMInitializeMipsTargetMC() { for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target, &TheMips64elTarget}) { + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo); Index: lib/Target/Mips/MipsAsmPrinter.cpp =================================================================== --- lib/Target/Mips/MipsAsmPrinter.cpp +++ lib/Target/Mips/MipsAsmPrinter.cpp @@ -42,6 +42,7 @@ #include "llvm/MC/MCSection.h" #include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCSymbolELF.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ELF.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" @@ -896,9 +897,9 @@ // This is because the MachineFunction won't exist (but have not yet been // freed) and since we're at the global level we can use the default // constructed subtarget. - std::unique_ptr STI(TM.getTarget().createMCSubtargetInfo( - TM.getTargetTriple().str(), TM.getTargetCPU(), - TM.getTargetFeatureString())); + std::unique_ptr STI( + TM.getMCTargetMachine()->createMCSubtargetInfo( + TM.getTargetCPU(), TM.getTargetFeatureString())); // // .global xxxx Index: lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp =================================================================== --- lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp +++ lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp @@ -18,6 +18,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -74,6 +75,8 @@ // Force static initialization. extern "C" void LLVMInitializeNVPTXTargetMC() { for (Target *T : {&TheNVPTXTarget32, &TheNVPTXTarget64}) { + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. RegisterMCAsmInfo X(*T); Index: lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp =================================================================== --- lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -37,13 +37,13 @@ }; } // end anonymous namespace -static MCDisassembler *createPPCDisassembler(const Target &T, +static MCDisassembler *createPPCDisassembler(const MCInstrInfo &, const MCSubtargetInfo &STI, MCContext &Ctx) { return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false); } -static MCDisassembler *createPPCLEDisassembler(const Target &T, +static MCDisassembler *createPPCLEDisassembler(const MCInstrInfo &, const MCSubtargetInfo &STI, MCContext &Ctx) { return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true); Index: lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -17,6 +17,7 @@ #include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCSymbolELF.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MCValue.h" #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" @@ -228,13 +229,13 @@ } // end anonymous namespace -MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, +MCAsmBackend *llvm::createPPCAsmBackend(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { if (TT.isOSDarwin()) - return new DarwinPPCAsmBackend(T); + return new DarwinPPCAsmBackend(MTM.getTarget()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); bool IsLittleEndian = TT.getArch() == Triple::ppc64le; - return new ELFPPCAsmBackend(T, IsLittleEndian, OSABI); + return new ELFPPCAsmBackend(MTM.getTarget(), IsLittleEndian, OSABI); } Index: lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h +++ lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h @@ -28,6 +28,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetMachine; class Target; class Triple; class StringRef; @@ -42,8 +43,9 @@ const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); +MCAsmBackend *createPPCAsmBackend(const MCTargetMachine &MTM, + const MCRegisterInfo &MRI, const Triple &TT, + StringRef CPU); /// Construct an PPC ELF object writer. MCObjectWriter *createPPCELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, Index: lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -23,6 +23,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MCSymbolELF.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/ELF.h" @@ -241,6 +242,8 @@ extern "C" void LLVMInitializePowerPCTargetMC() { for (Target *T : {&ThePPC32Target, &ThePPC64Target, &ThePPC64LETarget}) { + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo); Index: lib/Target/PowerPC/PPCAsmPrinter.cpp =================================================================== --- lib/Target/PowerPC/PPCAsmPrinter.cpp +++ lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -50,6 +50,7 @@ #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbolELF.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ELF.h" @@ -1329,9 +1330,9 @@ // This is because the MachineFunction won't exist (but have not yet been // freed) and since we're at the global level we can use the default // constructed subtarget. - std::unique_ptr STI(TM.getTarget().createMCSubtargetInfo( - TM.getTargetTriple().str(), TM.getTargetCPU(), - TM.getTargetFeatureString())); + std::unique_ptr STI( + TM.getMCTargetMachine()->createMCSubtargetInfo( + TM.getTargetCPU(), TM.getTargetFeatureString())); auto EmitToStreamer = [&STI] (MCStreamer &S, const MCInst &Inst) { S.EmitInstruction(Inst, *STI); }; Index: lib/Target/Sparc/Disassembler/SparcDisassembler.cpp =================================================================== --- lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -47,7 +47,7 @@ extern Target TheSparcTarget, TheSparcV9Target, TheSparcelTarget; } -static MCDisassembler *createSparcDisassembler(const Target &T, +static MCDisassembler *createSparcDisassembler(const MCInstrInfo &, const MCSubtargetInfo &STI, MCContext &Ctx) { return new SparcDisassembler(STI, Ctx); Index: lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -14,6 +14,7 @@ #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCObjectWriter.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MCValue.h" #include "llvm/Support/TargetRegistry.h" @@ -297,8 +298,8 @@ } // end anonymous namespace -MCAsmBackend *llvm::createSparcAsmBackend(const Target &T, +MCAsmBackend *llvm::createSparcAsmBackend(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { - return new ELFSparcAsmBackend(T, TT.getOS()); + return new ELFSparcAsmBackend(MTM.getTarget(), TT.getOS()); } Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h +++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h @@ -24,6 +24,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetMachine; class Target; class Triple; class StringRef; @@ -37,8 +38,9 @@ MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); +MCAsmBackend *createSparcAsmBackend(const MCTargetMachine &MTM, + const MCRegisterInfo &MRI, const Triple &TT, + StringRef CPU); MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, bool IsLIttleEndian, uint8_t OSABI); } // End llvm namespace Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -19,6 +19,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" @@ -148,6 +149,8 @@ RegisterMCAsmInfoFn Z(TheSparcelTarget, createSparcMCAsmInfo); for (Target *T : {&TheSparcTarget, &TheSparcV9Target, &TheSparcelTarget}) { + RegisterMCTargetMachine Y(*T); + // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo); Index: lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp =================================================================== --- lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp +++ lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp @@ -34,7 +34,7 @@ }; } // end anonymous namespace -static MCDisassembler *createSystemZDisassembler(const Target &T, +static MCDisassembler *createSystemZDisassembler(const MCInstrInfo &, const MCSubtargetInfo &STI, MCContext &Ctx) { return new SystemZDisassembler(STI, Ctx); Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp @@ -109,7 +109,7 @@ return true; } -MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T, +MCAsmBackend *llvm::createSystemZMCAsmBackend(const MCTargetMachine &, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU) { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h @@ -21,6 +21,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetMachine; class StringRef; class Target; class Triple; @@ -83,7 +84,7 @@ const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createSystemZMCAsmBackend(const Target &T, +MCAsmBackend *createSystemZMCAsmBackend(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -15,6 +15,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -216,6 +217,8 @@ } extern "C" void LLVMInitializeSystemZTargetMC() { + RegisterMCTargetMachine Y(TheSystemZTarget); + // Register the MCAsmInfo. TargetRegistry::RegisterMCAsmInfo(TheSystemZTarget, createSystemZMCAsmInfo); Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h @@ -29,6 +29,7 @@ class MCObjectWriter; class MCStreamer; class MCSubtargetInfo; +class MCTargetMachine; class MCTargetStreamer; class StringRef; class Target; @@ -38,7 +39,7 @@ extern Target TheWebAssemblyTarget32; extern Target TheWebAssemblyTarget64; -MCAsmBackend *createWebAssemblyAsmBackend(const Target &T, +MCAsmBackend *createWebAssemblyAsmBackend(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU); Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp @@ -20,6 +20,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -51,6 +52,8 @@ // Force static initialization. extern "C" void LLVMInitializeWebAssemblyTargetMC() { for (Target *T : {&TheWebAssemblyTarget32, &TheWebAssemblyTarget64}) { + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createWebAssemblyMCAsmInfo); Index: lib/Target/X86/Disassembler/X86Disassembler.h =================================================================== --- lib/Target/X86/Disassembler/X86Disassembler.h +++ lib/Target/X86/Disassembler/X86Disassembler.h @@ -91,10 +91,12 @@ /// have to do is subclass the constructor, and provide a different /// disassemblerMode value. class X86GenericDisassembler : public MCDisassembler { - std::unique_ptr MII; + const MCInstrInfo &MII; + public: X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, - std::unique_ptr MII); + const MCInstrInfo &MII); + public: DecodeStatus getInstruction(MCInst &instr, uint64_t &size, ArrayRef Bytes, uint64_t Address, Index: lib/Target/X86/Disassembler/X86Disassembler.cpp =================================================================== --- lib/Target/X86/Disassembler/X86Disassembler.cpp +++ lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -22,6 +22,7 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" @@ -75,11 +76,10 @@ InternalInstruction &source, const MCDisassembler *Dis); -X86GenericDisassembler::X86GenericDisassembler( - const MCSubtargetInfo &STI, - MCContext &Ctx, - std::unique_ptr MII) - : MCDisassembler(STI, Ctx), MII(std::move(MII)) { +X86GenericDisassembler::X86GenericDisassembler(const MCSubtargetInfo &STI, + MCContext &Ctx, + const MCInstrInfo &MII) + : MCDisassembler(STI, Ctx), MII(MII) { const FeatureBitset &FB = STI.getFeatureBits(); if (FB[X86::Mode16Bit]) { fMode = MODE_16BIT; @@ -149,8 +149,8 @@ Region R(Bytes, Address); int Ret = decodeInstruction(&InternalInstr, regionReader, (const void *)&R, - LoggerFn, (void *)&VStream, - (const void *)MII.get(), Address, fMode); + LoggerFn, (void *)&VStream, (const void *)&MII, + Address, fMode); if (Ret) { Size = InternalInstr.readerCursor - Address; @@ -987,10 +987,9 @@ return false; } -static MCDisassembler *createX86Disassembler(const Target &T, +static MCDisassembler *createX86Disassembler(const MCInstrInfo &MII, const MCSubtargetInfo &STI, MCContext &Ctx) { - std::unique_ptr MII(T.createMCInstrInfo()); return new X86Disassembler::X86GenericDisassembler(STI, Ctx, std::move(MII)); } Index: lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp =================================================================== --- lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -71,7 +71,7 @@ bool HasNopl; const uint64_t MaxNopLength; public: - X86AsmBackend(const Target &T, StringRef CPU) + X86AsmBackend(StringRef CPU) : MCAsmBackend(), CPU(CPU), MaxNopLength(CPU == "slm" ? 7 : 15) { HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" && CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" && @@ -334,14 +334,14 @@ class ELFX86AsmBackend : public X86AsmBackend { public: uint8_t OSABI; - ELFX86AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) - : X86AsmBackend(T, CPU), OSABI(OSABI) {} + ELFX86AsmBackend(uint8_t OSABI, StringRef CPU) + : X86AsmBackend(CPU), OSABI(OSABI) {} }; class ELFX86_32AsmBackend : public ELFX86AsmBackend { public: - ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) - : ELFX86AsmBackend(T, OSABI, CPU) {} + ELFX86_32AsmBackend(uint8_t OSABI, StringRef CPU) + : ELFX86AsmBackend(OSABI, CPU) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, ELF::EM_386); @@ -350,8 +350,8 @@ class ELFX86_X32AsmBackend : public ELFX86AsmBackend { public: - ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) - : ELFX86AsmBackend(T, OSABI, CPU) {} + ELFX86_X32AsmBackend(uint8_t OSABI, StringRef CPU) + : ELFX86AsmBackend(OSABI, CPU) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createX86ELFObjectWriter(OS, /*IsELF64*/ false, OSABI, @@ -361,8 +361,8 @@ class ELFX86_64AsmBackend : public ELFX86AsmBackend { public: - ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) - : ELFX86AsmBackend(T, OSABI, CPU) {} + ELFX86_64AsmBackend(uint8_t OSABI, StringRef CPU) + : ELFX86AsmBackend(OSABI, CPU) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createX86ELFObjectWriter(OS, /*IsELF64*/ true, OSABI, ELF::EM_X86_64); @@ -373,10 +373,8 @@ bool Is64Bit; public: - WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU) - : X86AsmBackend(T, CPU) - , Is64Bit(is64Bit) { - } + WindowsX86AsmBackend(bool is64Bit, StringRef CPU) + : X86AsmBackend(CPU), Is64Bit(is64Bit) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createX86WinCOFFObjectWriter(OS, Is64Bit); @@ -719,9 +717,8 @@ } public: - DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU, - bool Is64Bit) - : X86AsmBackend(T, CPU), MRI(MRI), Is64Bit(Is64Bit) { + DarwinX86AsmBackend(const MCRegisterInfo &MRI, StringRef CPU, bool Is64Bit) + : X86AsmBackend(CPU), MRI(MRI), Is64Bit(Is64Bit) { memset(SavedRegs, 0, sizeof(SavedRegs)); OffsetSize = Is64Bit ? 8 : 4; MoveInstrSize = Is64Bit ? 3 : 2; @@ -731,9 +728,8 @@ class DarwinX86_32AsmBackend : public DarwinX86AsmBackend { public: - DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef CPU) - : DarwinX86AsmBackend(T, MRI, CPU, false) {} + DarwinX86_32AsmBackend(const MCRegisterInfo &MRI, StringRef CPU) + : DarwinX86AsmBackend(MRI, CPU, false) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createX86MachObjectWriter(OS, /*Is64Bit=*/false, @@ -751,9 +747,9 @@ class DarwinX86_64AsmBackend : public DarwinX86AsmBackend { const MachO::CPUSubTypeX86 Subtype; public: - DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef CPU, MachO::CPUSubTypeX86 st) - : DarwinX86AsmBackend(T, MRI, CPU, true), Subtype(st) {} + DarwinX86_64AsmBackend(const MCRegisterInfo &MRI, StringRef CPU, + MachO::CPUSubTypeX86 st) + : DarwinX86AsmBackend(MRI, CPU, true), Subtype(st) {} MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { return createX86MachObjectWriter(OS, /*Is64Bit=*/true, @@ -769,21 +765,21 @@ } // end anonymous namespace -MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, +MCAsmBackend *llvm::createX86_32AsmBackend(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TheTriple, StringRef CPU) { if (TheTriple.isOSBinFormatMachO()) - return new DarwinX86_32AsmBackend(T, MRI, CPU); + return new DarwinX86_32AsmBackend(MRI, CPU); if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF()) - return new WindowsX86AsmBackend(T, false, CPU); + return new WindowsX86AsmBackend(false, CPU); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); - return new ELFX86_32AsmBackend(T, OSABI, CPU); + return new ELFX86_32AsmBackend(OSABI, CPU); } -MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, +MCAsmBackend *llvm::createX86_64AsmBackend(const MCTargetMachine &MTM, const MCRegisterInfo &MRI, const Triple &TheTriple, StringRef CPU) { @@ -792,15 +788,15 @@ StringSwitch(TheTriple.getArchName()) .Case("x86_64h", MachO::CPU_SUBTYPE_X86_64_H) .Default(MachO::CPU_SUBTYPE_X86_64_ALL); - return new DarwinX86_64AsmBackend(T, MRI, CPU, CS); + return new DarwinX86_64AsmBackend(MRI, CPU, CS); } if (TheTriple.isOSWindows() && !TheTriple.isOSBinFormatELF()) - return new WindowsX86AsmBackend(T, true, CPU); + return new WindowsX86AsmBackend(true, CPU); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); if (TheTriple.getEnvironment() == Triple::GNUX32) - return new ELFX86_X32AsmBackend(T, OSABI, CPU); - return new ELFX86_64AsmBackend(T, OSABI, CPU); + return new ELFX86_X32AsmBackend(OSABI, CPU); + return new ELFX86_64AsmBackend(OSABI, CPU); } Index: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h +++ lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h @@ -27,6 +27,7 @@ class MCSubtargetInfo; class MCRelocationInfo; class MCStreamer; +class MCTargetMachine; class Target; class Triple; class StringRef; @@ -68,9 +69,11 @@ const MCRegisterInfo &MRI, MCContext &Ctx); -MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, +MCAsmBackend *createX86_32AsmBackend(const MCTargetMachine &MTM, + const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); -MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, +MCAsmBackend *createX86_64AsmBackend(const MCTargetMachine &MTM, + const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU); /// Construct an X86 Windows COFF machine code streamer which will generate Index: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -22,6 +22,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Host.h" @@ -230,6 +231,8 @@ // Force static initialization. extern "C" void LLVMInitializeX86TargetMC() { for (Target *T : {&TheX86_32Target, &TheX86_64Target}) { + RegisterMCTargetMachine Z(*T); + // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); Index: lib/Target/X86/X86MCInstLower.cpp =================================================================== --- lib/Target/X86/X86MCInstLower.cpp +++ lib/Target/X86/X86MCInstLower.cpp @@ -36,6 +36,7 @@ #include "llvm/MC/MCInstBuilder.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -80,7 +81,7 @@ void X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) { MF = &F; - CodeEmitter.reset(TM.getTarget().createMCCodeEmitter( + CodeEmitter.reset(TM.getMCTargetMachine()->createMCCodeEmitter( *MF->getSubtarget().getInstrInfo(), *MF->getSubtarget().getRegisterInfo(), MF->getContext())); } Index: lib/Target/XCore/Disassembler/XCoreDisassembler.cpp =================================================================== --- lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -772,7 +772,7 @@ extern Target TheXCoreTarget; } -static MCDisassembler *createXCoreDisassembler(const Target &T, +static MCDisassembler *createXCoreDisassembler(const MCInstrInfo &, const MCSubtargetInfo &STI, MCContext &Ctx) { return new XCoreDisassembler(STI, Ctx); Index: lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp =================================================================== --- lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -19,6 +19,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/TargetRegistry.h" @@ -133,6 +134,8 @@ // Force static initialization. extern "C" void LLVMInitializeXCoreTargetMC() { + RegisterMCTargetMachine Y(TheXCoreTarget); + // Register the MC asm info. RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo); Index: tools/dsymutil/DwarfLinker.cpp =================================================================== --- tools/dsymutil/DwarfLinker.cpp +++ tools/dsymutil/DwarfLinker.cpp @@ -31,6 +31,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Object/MachO.h" #include "llvm/Support/Dwarf.h" #include "llvm/Support/LEB128.h" @@ -464,6 +465,7 @@ class DwarfStreamer { /// \defgroup MCObjects MC layer objects constructed by the streamer /// @{ + std::unique_ptr MTM; std::unique_ptr MRI; std::unique_ptr MAI; std::unique_ptr MOFI; @@ -582,11 +584,15 @@ TripleName = TheTriple.getTriple(); // Create all the MC Objects. - MRI.reset(TheTarget->createMCRegInfo(TripleName)); + MTM.reset(TheTarget->createMCTargetMachine(TheTriple)); + if (!MTM) + return error(Twine("no MC target machine for target ") + TripleName, Context); + + MRI.reset(MTM->createMCRegisterInfo()); if (!MRI) return error(Twine("no register info for target ") + TripleName, Context); - MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName)); + MAI.reset(MTM->createMCAsmInfo(*MRI)); if (!MAI) return error("no asm info for target " + TripleName, Context); @@ -595,19 +601,19 @@ MOFI->InitMCObjectFileInfo(TheTriple, Reloc::Default, CodeModel::Default, *MC); - MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, ""); + MAB = MTM->createMCAsmBackend(*MRI, ""); if (!MAB) return error("no asm backend for target " + TripleName, Context); - MII.reset(TheTarget->createMCInstrInfo()); + MII.reset(MTM->createMCInstrInfo()); if (!MII) return error("no instr info info for target " + TripleName, Context); - MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", "")); + MSTI.reset(MTM->createMCSubtargetInfo("", "")); if (!MSTI) return error("no subtarget info for target " + TripleName, Context); - MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC); + MCE = MTM->createMCCodeEmitter(*MII, *MRI, *MC); if (!MCE) return error("no code emitter for target " + TripleName, Context); @@ -618,9 +624,8 @@ if (EC) return error(Twine(OutputFilename) + ": " + EC.message(), Context); - MS = TheTarget->createMCObjectStreamer(TheTriple, *MC, *MAB, *OutFile, MCE, - *MSTI, false, - /*DWARFMustBeAtTheEnd*/ false); + MS = MTM->createMCObjectStreamer(*MC, *MAB, *OutFile, MCE, *MSTI, false, + /*DWARFMustBeAtTheEnd*/ false); if (!MS) return error("no object streamer for target " + TripleName, Context); Index: tools/llvm-mc/Disassembler.cpp =================================================================== --- tools/llvm-mc/Disassembler.cpp +++ tools/llvm-mc/Disassembler.cpp @@ -18,9 +18,11 @@ #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/TargetRegistry.h" @@ -131,22 +133,34 @@ } int Disassembler::disassemble(const Target &T, - const std::string &Triple, + const std::string &TripleStr, MCSubtargetInfo &STI, MCStreamer &Streamer, MemoryBuffer &Buffer, SourceMgr &SM, raw_ostream &Out) { + Triple TT(TripleStr); + std::unique_ptr MTM(T.createMCTargetMachine(TT)); + if (!MTM) { + errs() << "error: no register info for target " << TripleStr << "\n"; + return -1; + } - std::unique_ptr MRI(T.createMCRegInfo(Triple)); + std::unique_ptr MRI(MTM->createMCRegisterInfo()); if (!MRI) { - errs() << "error: no register info for target " << Triple << "\n"; + errs() << "error: no register info for target " << TripleStr << "\n"; return -1; } - std::unique_ptr MAI(T.createMCAsmInfo(*MRI, Triple)); + std::unique_ptr MAI(MTM->createMCAsmInfo(*MRI)); if (!MAI) { - errs() << "error: no assembly info for target " << Triple << "\n"; + errs() << "error: no assembly info for target " << TripleStr << "\n"; + return -1; + } + + std::unique_ptr MII(MTM->createMCInstrInfo()); + if (!MII) { + errs() << "error: no instruction info for target " << TripleStr << "\n"; return -1; } @@ -154,9 +168,9 @@ MCContext Ctx(MAI.get(), MRI.get(), nullptr); std::unique_ptr DisAsm( - T.createMCDisassembler(STI, Ctx)); + MTM->createMCDisassembler(*MII, STI, Ctx)); if (!DisAsm) { - errs() << "error: no disassembler for target " << Triple << "\n"; + errs() << "error: no disassembler for target " << TripleStr << "\n"; return -1; } Index: tools/llvm-mc/llvm-mc.cpp =================================================================== --- tools/llvm-mc/llvm-mc.cpp +++ tools/llvm-mc/llvm-mc.cpp @@ -26,6 +26,7 @@ #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCTargetAsmParser.h" #include "llvm/MC/MCTargetOptionsCommandFlags.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Compression.h" #include "llvm/Support/FileUtilities.h" @@ -340,13 +341,14 @@ } static int AssembleInput(const char *ProgName, const Target *TheTarget, - SourceMgr &SrcMgr, MCContext &Ctx, MCStreamer &Str, - MCAsmInfo &MAI, MCSubtargetInfo &STI, - MCInstrInfo &MCII, MCTargetOptions &MCOptions) { + const MCTargetMachine &MTM, SourceMgr &SrcMgr, + MCContext &Ctx, MCStreamer &Str, MCAsmInfo &MAI, + MCSubtargetInfo &STI, MCInstrInfo &MCII, + MCTargetOptions &MCOptions) { std::unique_ptr Parser( createMCAsmParser(SrcMgr, Ctx, Str, MAI)); std::unique_ptr TAP( - TheTarget->createMCAsmParser(STI, *Parser, MCII, MCOptions)); + MTM.createMCAsmParser(STI, *Parser, MCII, MCOptions)); if (!TAP) { errs() << ProgName @@ -412,10 +414,14 @@ // it later. SrcMgr.setIncludeDirs(IncludeDirs); - std::unique_ptr MRI(TheTarget->createMCRegInfo(TripleName)); + Triple TT(TripleName); + std::unique_ptr MTM(TheTarget->createMCTargetMachine(TT)); + assert(MTM && "Unable to create target register info!"); + + std::unique_ptr MRI(MTM->createMCRegisterInfo()); assert(MRI && "Unable to create target register info!"); - std::unique_ptr MAI(TheTarget->createMCAsmInfo(*MRI, TripleName)); + std::unique_ptr MAI(MTM->createMCAsmInfo(*MRI)); assert(MAI && "Unable to create target asm info!"); if (CompressDebugSections) { @@ -471,14 +477,13 @@ raw_pwrite_stream *OS = &Out->os(); std::unique_ptr Str; - std::unique_ptr MCII(TheTarget->createMCInstrInfo()); + std::unique_ptr MCII(MTM->createMCInstrInfo()); std::unique_ptr STI( - TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); + MTM->createMCSubtargetInfo(MCPU, FeaturesStr)); MCInstPrinter *IP = nullptr; if (FileType == OFT_AssemblyFile) { - IP = TheTarget->createMCInstPrinter(Triple(TripleName), OutputAsmVariant, - *MAI, *MCII, *MRI); + IP = MTM->createMCInstPrinter(OutputAsmVariant, *MAI, *MCII, *MRI); // Set the display preference for hex vs. decimal immediates. IP->setPrintImmHex(PrintImmHex); @@ -487,16 +492,16 @@ MCCodeEmitter *CE = nullptr; MCAsmBackend *MAB = nullptr; if (ShowEncoding) { - CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx); - MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU); + CE = MTM->createMCCodeEmitter(*MCII, *MRI, Ctx); + MAB = MTM->createMCAsmBackend(*MRI, MCPU); } auto FOut = llvm::make_unique(*OS); - Str.reset(TheTarget->createAsmStreamer( - Ctx, std::move(FOut), /*asmverbose*/ true, - /*useDwarfDirectory*/ true, IP, CE, MAB, ShowInst)); + Str.reset(MTM->createAsmStreamer(Ctx, std::move(FOut), /*asmverbose*/ true, + /*useDwarfDirectory*/ true, IP, CE, MAB, + ShowInst)); } else if (FileType == OFT_Null) { - Str.reset(TheTarget->createNullStreamer(Ctx)); + Str.reset(MTM->createNullStreamer(Ctx)); } else { assert(FileType == OFT_ObjectFile && "Invalid file type!"); @@ -508,11 +513,10 @@ OS = BOS.get(); } - MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx); - MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU); - Str.reset(TheTarget->createMCObjectStreamer(TheTriple, Ctx, *MAB, *OS, CE, - *STI, RelaxAll, - /*DWARFMustBeAtTheEnd*/ false)); + MCCodeEmitter *CE = MTM->createMCCodeEmitter(*MCII, *MRI, Ctx); + MCAsmBackend *MAB = MTM->createMCAsmBackend(*MRI, MCPU); + Str.reset(MTM->createMCObjectStreamer(Ctx, *MAB, *OS, CE, *STI, RelaxAll, + /*DWARFMustBeAtTheEnd*/ false)); if (NoExecStack) Str->InitSections(true); } @@ -524,8 +528,8 @@ Res = AsLexInput(SrcMgr, *MAI, Out->os()); break; case AC_Assemble: - Res = AssembleInput(ProgName, TheTarget, SrcMgr, Ctx, *Str, *MAI, *STI, - *MCII, MCOptions); + Res = AssembleInput(ProgName, TheTarget, *MTM, SrcMgr, Ctx, *Str, *MAI, + *STI, *MCII, MCOptions); break; case AC_MDisassemble: assert(IP && "Expected assembly output"); Index: tools/llvm-objdump/MachODump.cpp =================================================================== --- tools/llvm-objdump/MachODump.cpp +++ tools/llvm-objdump/MachODump.cpp @@ -28,6 +28,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Object/MachO.h" #include "llvm/Object/MachOUniversal.h" #include "llvm/Support/Casting.h" @@ -5914,11 +5915,6 @@ if (MCPU.empty() && McpuDefault) MCPU = McpuDefault; - std::unique_ptr InstrInfo(TheTarget->createMCInstrInfo()); - std::unique_ptr ThumbInstrInfo; - if (ThumbTarget) - ThumbInstrInfo.reset(ThumbTarget->createMCInstrInfo()); - // Package up features to be passed to target/subtarget std::string FeaturesStr; if (MAttrs.size()) { @@ -5929,15 +5925,17 @@ } // Set up disassembler. - std::unique_ptr MRI( - TheTarget->createMCRegInfo(TripleName)); - std::unique_ptr AsmInfo( - TheTarget->createMCAsmInfo(*MRI, TripleName)); + Triple TT(TripleName); + std::unique_ptr MTM( + TheTarget->createMCTargetMachine(TT)); + std::unique_ptr InstrInfo(MTM->createMCInstrInfo()); + std::unique_ptr MRI(MTM->createMCRegisterInfo()); + std::unique_ptr AsmInfo(MTM->createMCAsmInfo(*MRI)); std::unique_ptr STI( - TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); + MTM->createMCSubtargetInfo(MCPU, FeaturesStr)); MCContext Ctx(AsmInfo.get(), MRI.get(), nullptr); std::unique_ptr DisAsm( - TheTarget->createMCDisassembler(*STI, Ctx)); + MTM->createMCDisassembler(*InstrInfo, *STI, Ctx)); std::unique_ptr Symbolizer; struct DisassembleInfo SymbolizerInfo; std::unique_ptr RelInfo( @@ -5949,8 +5947,8 @@ DisAsm->setSymbolizer(std::move(Symbolizer)); } int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); - std::unique_ptr IP(TheTarget->createMCInstPrinter( - Triple(TripleName), AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI)); + std::unique_ptr IP( + MTM->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI)); // Set the display preference for hex vs. decimal immediates. IP->setPrintImmHex(PrintImmHex); // Comment stream and backing vector. @@ -5970,6 +5968,8 @@ } // Set up thumb disassembler. + std::unique_ptr ThumbMTM; + std::unique_ptr ThumbInstrInfo; std::unique_ptr ThumbMRI; std::unique_ptr ThumbAsmInfo; std::unique_ptr ThumbSTI; @@ -5980,13 +5980,14 @@ struct DisassembleInfo ThumbSymbolizerInfo; std::unique_ptr ThumbRelInfo; if (ThumbTarget) { - ThumbMRI.reset(ThumbTarget->createMCRegInfo(ThumbTripleName)); - ThumbAsmInfo.reset( - ThumbTarget->createMCAsmInfo(*ThumbMRI, ThumbTripleName)); - ThumbSTI.reset( - ThumbTarget->createMCSubtargetInfo(ThumbTripleName, MCPU, FeaturesStr)); + Triple ThumbTT(ThumbTripleName); + ThumbMTM.reset(ThumbTarget->createMCTargetMachine(ThumbTT)); + ThumbMRI.reset(ThumbMTM->createMCRegisterInfo()); + ThumbAsmInfo.reset(ThumbMTM->createMCAsmInfo(*ThumbMRI)); + ThumbSTI.reset(ThumbMTM->createMCSubtargetInfo(MCPU, FeaturesStr)); ThumbCtx.reset(new MCContext(ThumbAsmInfo.get(), ThumbMRI.get(), nullptr)); - ThumbDisAsm.reset(ThumbTarget->createMCDisassembler(*ThumbSTI, *ThumbCtx)); + ThumbDisAsm.reset( + ThumbMTM->createMCDisassembler(*ThumbInstrInfo, *ThumbSTI, *ThumbCtx)); MCContext *PtrThumbCtx = ThumbCtx.get(); ThumbRelInfo.reset( ThumbTarget->createMCRelocationInfo(ThumbTripleName, *PtrThumbCtx)); @@ -5997,9 +5998,9 @@ ThumbDisAsm->setSymbolizer(std::move(ThumbSymbolizer)); } int ThumbAsmPrinterVariant = ThumbAsmInfo->getAssemblerDialect(); - ThumbIP.reset(ThumbTarget->createMCInstPrinter( - Triple(ThumbTripleName), ThumbAsmPrinterVariant, *ThumbAsmInfo, - *ThumbInstrInfo, *ThumbMRI)); + ThumbInstrInfo.reset(ThumbMTM->createMCInstrInfo()); + ThumbIP.reset(ThumbMTM->createMCInstPrinter( + ThumbAsmPrinterVariant, *ThumbAsmInfo, *ThumbInstrInfo, *ThumbMRI)); // Set the display preference for hex vs. decimal immediates. ThumbIP->setPrintImmHex(PrintImmHex); } Index: tools/llvm-objdump/llvm-objdump.cpp =================================================================== --- tools/llvm-objdump/llvm-objdump.cpp +++ tools/llvm-objdump/llvm-objdump.cpp @@ -33,6 +33,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCRelocationInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Object/Archive.h" #include "llvm/Object/ELFObjectFile.h" #include "llvm/Object/COFF.h" @@ -818,29 +819,35 @@ FeaturesStr = Features.getString(); } - std::unique_ptr MRI( - TheTarget->createMCRegInfo(TripleName)); + Triple TT(TripleName); + std::unique_ptr MTM( + TheTarget->createMCTargetMachine(TT)); + if (!MTM) { + errs() << "error: no MC target machine for target " << TripleName << "\n"; + return; + } + + std::unique_ptr MRI(MTM->createMCRegisterInfo()); if (!MRI) { errs() << "error: no register info for target " << TripleName << "\n"; return; } // Set up disassembler. - std::unique_ptr AsmInfo( - TheTarget->createMCAsmInfo(*MRI, TripleName)); + std::unique_ptr AsmInfo(MTM->createMCAsmInfo(*MRI)); if (!AsmInfo) { errs() << "error: no assembly info for target " << TripleName << "\n"; return; } std::unique_ptr STI( - TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); + MTM->createMCSubtargetInfo(MCPU, FeaturesStr)); if (!STI) { errs() << "error: no subtarget info for target " << TripleName << "\n"; return; } - std::unique_ptr MII(TheTarget->createMCInstrInfo()); + std::unique_ptr MII(MTM->createMCInstrInfo()); if (!MII) { errs() << "error: no instruction info for target " << TripleName << "\n"; return; @@ -850,7 +857,7 @@ MCContext Ctx(AsmInfo.get(), MRI.get(), MOFI.get()); std::unique_ptr DisAsm( - TheTarget->createMCDisassembler(*STI, Ctx)); + MTM->createMCDisassembler(*MII, *STI, Ctx)); if (!DisAsm) { errs() << "error: no disassembler for target " << TripleName << "\n"; @@ -858,18 +865,18 @@ } std::unique_ptr MIA( - TheTarget->createMCInstrAnalysis(MII.get())); + MTM->createMCInstrAnalysis(MII.get())); int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); - std::unique_ptr IP(TheTarget->createMCInstPrinter( - Triple(TripleName), AsmPrinterVariant, *AsmInfo, *MII, *MRI)); + std::unique_ptr IP( + MTM->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *MII, *MRI)); if (!IP) { errs() << "error: no instruction printer for target " << TripleName << '\n'; return; } IP->setPrintImmHex(PrintImmHex); - PrettyPrinter &PIP = selectPrettyPrinter(Triple(TripleName)); + PrettyPrinter &PIP = selectPrettyPrinter(TT); StringRef Fmt = Obj->getBytesInAddress() > 4 ? "\t\t%016" PRIx64 ": " : "\t\t\t%08" PRIx64 ": "; Index: tools/llvm-rtdyld/llvm-rtdyld.cpp =================================================================== --- tools/llvm-rtdyld/llvm-rtdyld.cpp +++ tools/llvm-rtdyld/llvm-rtdyld.cpp @@ -24,6 +24,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Object/MachO.h" #include "llvm/Object/SymbolSize.h" #include "llvm/Support/CommandLine.h" @@ -587,26 +588,28 @@ } TripleName = TheTriple.getTriple(); - std::unique_ptr STI( - TheTarget->createMCSubtargetInfo(TripleName, MCPU, "")); + std::unique_ptr MTM(TheTarget->createMCTargetMachine(TheTriple)); + assert(MTM && "Unable to create MC target machine!"); + + std::unique_ptr STI(MTM->createMCSubtargetInfo(MCPU, "")); assert(STI && "Unable to create subtarget info!"); - std::unique_ptr MRI(TheTarget->createMCRegInfo(TripleName)); + std::unique_ptr MRI(MTM->createMCRegisterInfo()); assert(MRI && "Unable to create target register info!"); - std::unique_ptr MAI(TheTarget->createMCAsmInfo(*MRI, TripleName)); + std::unique_ptr MAI(MTM->createMCAsmInfo(*MRI)); assert(MAI && "Unable to create target asm info!"); MCContext Ctx(MAI.get(), MRI.get(), nullptr); + std::unique_ptr MII(MTM->createMCInstrInfo()); + std::unique_ptr Disassembler( - TheTarget->createMCDisassembler(*STI, Ctx)); + MTM->createMCDisassembler(*MII, *STI, Ctx)); assert(Disassembler && "Unable to create disassembler!"); - std::unique_ptr MII(TheTarget->createMCInstrInfo()); - std::unique_ptr InstPrinter( - TheTarget->createMCInstPrinter(Triple(TripleName), 0, *MAI, *MII, *MRI)); + MTM->createMCInstPrinter(0, *MAI, *MII, *MRI)); // Load any dylibs requested on the command line. loadDylibs();