Index: lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- lib/Target/ARM/ARMInstrInfo.td
+++ lib/Target/ARM/ARMInstrInfo.td
@@ -3678,10 +3678,10 @@
   let Inst{3-0} = Rn;
 }
 
-def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
-               (SSAT imm:$pos, GPRnopc:$a, 0)>;
-def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
-               (USAT imm:$pos, GPRnopc:$a, 0)>;
+def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm1_32:$pos),
+               (SSAT imm1_32:$pos, GPRnopc:$a, 0)>;
+def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm0_31:$pos),
+               (USAT imm0_31:$pos, GPRnopc:$a, 0)>;
 
 //===----------------------------------------------------------------------===//
 //  Bitwise Instructions.
Index: test/CodeGen/ARM/sat-arith.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/sat-arith.ll
@@ -0,0 +1,40 @@
+; RUN: llc -O1 -mtriple=armv6-none-none-eabi %s -o - | FileCheck %s
+
+; CHECK-LABEL: qadd
+define i32 @qadd() nounwind {
+; CHECK: mov [[R0:.*]], #8
+; CHECK: mov [[R1:.*]], #128
+; CHECK: qadd [[R0]], [[R1]], [[R0]]
+  %tmp = call i32 @llvm.arm.qadd(i32 128, i32 8)
+  ret i32 %tmp
+}
+
+; CHECK-LABEL: qsub
+define i32 @qsub() nounwind {
+; CHECK: mov [[R0:.*]], #8
+; CHECK: mov [[R1:.*]], #128
+; CHECK: qsub [[R0]], [[R1]], [[R0]]
+  %tmp = call i32 @llvm.arm.qsub(i32 128, i32 8)
+  ret i32 %tmp
+}
+
+; CHECK-LABEL: ssat
+define i32 @ssat() nounwind {
+; CHECK: mov [[R0:.*]], #128
+; CHECK: ssat [[R1:.*]], #8, [[R0]]
+  %tmp = call i32 @llvm.arm.ssat(i32 128, i32 8)
+  ret i32 %tmp
+}
+
+; CHECK-LABEL: usat
+define i32 @usat() nounwind {
+; CHECK: mov [[R0:.*]], #128
+; CHECK: usat [[R1:.*]], #8, [[R0]]
+  %tmp = call i32 @llvm.arm.usat(i32 128, i32 8)
+  ret i32 %tmp
+}
+
+declare i32 @llvm.arm.qadd(i32, i32) nounwind
+declare i32 @llvm.arm.qsub(i32, i32) nounwind
+declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
+declare i32 @llvm.arm.usat(i32, i32) nounwind readnone