diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -692,6 +692,7 @@ let Requires = [{ {AArch64::FeatureSpecRestrict} }]; } def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>; +def : ROSysReg<"ID_DFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b101>; def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>; def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>; def : ROSysReg<"ID_MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b101>; @@ -1632,6 +1633,8 @@ // v8.6a Activity Monitors Virtualization Support let Requires = [{ {AArch64::FeatureAMVS} }] in { +// Name Op0 Op1 CRn CRm Op2 +def : ROSysReg<"AMCG1IDR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b110>; foreach n = 0-15 in { foreach x = 0-1 in { def : RWSysReg<"AMEVCNTVOFF"#x#n#"_EL2", @@ -1651,6 +1654,7 @@ def : RWSysReg<"HFGITR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b110>; def : RWSysReg<"HDFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b100>; def : RWSysReg<"HDFGWTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b101>; +def : RWSysReg<"HAFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b110>; // v8.9a/v9.4a additions to Fine Grained Traps (FEAT_FGT2) // Op0 Op1 CRn CRm Op2 diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s --- a/llvm/test/MC/AArch64/arm64-system-encoding.s +++ b/llvm/test/MC/AArch64/arm64-system-encoding.s @@ -609,6 +609,7 @@ mrs x0, ID_PFR0_EL1 mrs x0, ID_PFR1_EL1 mrs x0, ID_DFR0_EL1 + mrs x0, ID_DFR1_EL1 mrs x0, ID_AFR0_EL1 mrs x0, ID_ISAR0_EL1 mrs x0, ID_ISAR1_EL1 @@ -622,6 +623,7 @@ ; CHECK: mrs x0, ID_PFR0_EL1 ; encoding: [0x00,0x01,0x38,0xd5] ; CHECK: mrs x0, ID_PFR1_EL1 ; encoding: [0x20,0x01,0x38,0xd5] ; CHECK: mrs x0, ID_DFR0_EL1 ; encoding: [0x40,0x01,0x38,0xd5] +; CHECK: mrs x0, ID_DFR1_EL1 ; encoding: [0xa0,0x03,0x38,0xd5] ; CHECK: mrs x0, ID_AFR0_EL1 ; encoding: [0x60,0x01,0x38,0xd5] ; CHECK: mrs x0, ID_ISAR0_EL1 ; encoding: [0x00,0x02,0x38,0xd5] ; CHECK: mrs x0, ID_ISAR1_EL1 ; encoding: [0x20,0x02,0x38,0xd5] diff --git a/llvm/test/MC/AArch64/armv8.6a-amvs.s b/llvm/test/MC/AArch64/armv8.6a-amvs.s --- a/llvm/test/MC/AArch64/armv8.6a-amvs.s +++ b/llvm/test/MC/AArch64/armv8.6a-amvs.s @@ -1,6 +1,7 @@ // RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+amvs -o - %s | FileCheck %s // RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a -o - %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding -o - %p/armv8.6a-amvs.s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: not llvm-mc -triple aarch64 -show-encoding -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR +mrs x0, AMCG1IDR_EL0 msr AMEVCNTVOFF00_EL2, x0 msr AMEVCNTVOFF01_EL2, x0 msr AMEVCNTVOFF02_EL2, x0 @@ -67,6 +68,7 @@ mrs x0, AMEVCNTVOFF115_EL2 // CHECK: .text +// CHECK-NEXT: mrs x0, AMCG1IDR_EL0 // encoding: [0xc0,0xd2,0x3b,0xd5] // CHECK-NEXT: msr AMEVCNTVOFF00_EL2, x0 // encoding: [0x00,0xd8,0x1c,0xd5] // CHECK-NEXT: msr AMEVCNTVOFF01_EL2, x0 // encoding: [0x20,0xd8,0x1c,0xd5] // CHECK-NEXT: msr AMEVCNTVOFF02_EL2, x0 // encoding: [0x40,0xd8,0x1c,0xd5] diff --git a/llvm/test/MC/AArch64/armv8.6a-fgt.s b/llvm/test/MC/AArch64/armv8.6a-fgt.s --- a/llvm/test/MC/AArch64/armv8.6a-fgt.s +++ b/llvm/test/MC/AArch64/armv8.6a-fgt.s @@ -7,11 +7,14 @@ msr HFGITR_EL2, x10 msr HDFGRTR_EL2, x15 msr HDFGWTR_EL2, x20 +msr HAFGRTR_EL2, x25 // CHECK: msr HFGRTR_EL2, x0 // encoding: [0x80,0x11,0x1c,0xd5] // CHECK: msr HFGWTR_EL2, x5 // encoding: [0xa5,0x11,0x1c,0xd5] // CHECK: msr HFGITR_EL2, x10 // encoding: [0xca,0x11,0x1c,0xd5] // CHECK: msr HDFGRTR_EL2, x15 // encoding: [0x8f,0x31,0x1c,0xd5] // CHECK: msr HDFGWTR_EL2, x20 // encoding: [0xb4,0x31,0x1c,0xd5] +// CHECK: msr HAFGRTR_EL2, x25 // encoding: [0xd9,0x31,0x1c,0xd5] +// NOFGT: error: expected writable system register or pstate // NOFGT: error: expected writable system register or pstate // NOFGT: error: expected writable system register or pstate // NOFGT: error: expected writable system register or pstate @@ -23,11 +26,14 @@ mrs x20, HFGITR_EL2 mrs x15, HDFGRTR_EL2 mrs x10, HDFGWTR_EL2 +mrs x5, HAFGRTR_EL2 // CHECK: mrs x30, HFGRTR_EL2 // encoding: [0x9e,0x11,0x3c,0xd5] // CHECK: mrs x25, HFGWTR_EL2 // encoding: [0xb9,0x11,0x3c,0xd5] // CHECK: mrs x20, HFGITR_EL2 // encoding: [0xd4,0x11,0x3c,0xd5] // CHECK: mrs x15, HDFGRTR_EL2 // encoding: [0x8f,0x31,0x3c,0xd5] // CHECK: mrs x10, HDFGWTR_EL2 // encoding: [0xaa,0x31,0x3c,0xd5] +// CHECK: mrs x5, HAFGRTR_EL2 // encoding: [0xc5,0x31,0x3c,0xd5] +// NOFGT: error: expected readable system register // NOFGT: error: expected readable system register // NOFGT: error: expected readable system register // NOFGT: error: expected readable system register diff --git a/llvm/test/MC/AArch64/basic-a64-diagnostics.s b/llvm/test/MC/AArch64/basic-a64-diagnostics.s --- a/llvm/test/MC/AArch64/basic-a64-diagnostics.s +++ b/llvm/test/MC/AArch64/basic-a64-diagnostics.s @@ -3577,6 +3577,7 @@ msr ID_PFR0_EL1, x12 msr ID_PFR1_EL1, x12 msr ID_DFR0_EL1, x12 + msr ID_DFR1_EL1, x12 msr ID_AFR0_EL1, x12 msr ID_MMFR0_EL1, x12 msr ID_MMFR1_EL1, x12 @@ -3666,6 +3667,9 @@ // CHECK-ERROR-NEXT: msr ID_DFR0_EL1, x12 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: expected writable system register or pstate +// CHECK-ERROR-NEXT: msr ID_DFR1_EL1, x12 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: msr ID_AFR0_EL1, x12 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: expected writable system register or pstate diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s --- a/llvm/test/MC/AArch64/basic-a64-instructions.s +++ b/llvm/test/MC/AArch64/basic-a64-instructions.s @@ -4289,6 +4289,7 @@ mrs x9, ID_PFR0_EL1 mrs x9, ID_PFR1_EL1 mrs x9, ID_DFR0_EL1 + mrs x9, ID_DFR1_EL1 mrs x9, ID_AFR0_EL1 mrs x9, ID_MMFR0_EL1 mrs x9, ID_MMFR1_EL1 @@ -4592,6 +4593,7 @@ // CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}} // encoding: [0x09,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} // encoding: [0x29,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} // encoding: [0x49,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_dfr1_el1|ID_DFR1_EL1}} // encoding: [0xa9,0x03,0x38,0xd5] // CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} // encoding: [0x69,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} // encoding: [0x89,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} // encoding: [0xa9,0x01,0x38,0xd5] diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s b/llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s --- a/llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s +++ b/llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s @@ -1,6 +1,8 @@ // RUN: llvm-mc -triple aarch64 -show-encoding -disassemble -mattr=+amvs %s | FileCheck %s // RUN: llvm-mc -triple aarch64 -show-encoding -disassemble -mattr=+v8.6a -o - %s | FileCheck %s // RUN: llvm-mc -triple aarch64 -show-encoding -disassemble -o - %s | FileCheck --check-prefix=NOAMVS %s +[0xc0,0xd2,0x1b,0xd5] +[0xc0,0xd2,0x3b,0xd5] [0x00,0xd8,0x1c,0xd5] [0x20,0xd8,0x1c,0xd5] [0x40,0xd8,0x1c,0xd5] @@ -66,6 +68,8 @@ [0xc0,0xdb,0x3c,0xd5] [0xe0,0xdb,0x3c,0xd5] // CHECK: .text +// CHECK-NEXT: msr S3_3_C13_C2_6, x0 // encoding: [0xc0,0xd2,0x1b,0xd5] +// CHECK-NEXT: mrs x0, AMCG1IDR_EL0 // encoding: [0xc0,0xd2,0x3b,0xd5] // CHECK-NEXT: msr AMEVCNTVOFF00_EL2, x0 // encoding: [0x00,0xd8,0x1c,0xd5] // CHECK-NEXT: msr AMEVCNTVOFF01_EL2, x0 // encoding: [0x20,0xd8,0x1c,0xd5] // CHECK-NEXT: msr AMEVCNTVOFF02_EL2, x0 // encoding: [0x40,0xd8,0x1c,0xd5] @@ -131,6 +135,8 @@ // CHECK-NEXT: mrs x0, AMEVCNTVOFF114_EL2 // encoding: [0xc0,0xdb,0x3c,0xd5] // CHECK-NEXT: mrs x0, AMEVCNTVOFF115_EL2 // encoding: [0xe0,0xdb,0x3c,0xd5] // NOAMVS: .text +// NOAMVS-NEXT: msr S3_3_C13_C2_6, x0 // encoding: [0xc0,0xd2,0x1b,0xd5] +// NOAMVS-NEXT: mrs x0, S3_3_C13_C2_6 // encoding: [0xc0,0xd2,0x3b,0xd5] // NOAMVS-NEXT: msr S3_4_C13_C8_0, x0 // encoding: [0x00,0xd8,0x1c,0xd5] // NOAMVS-NEXT: msr S3_4_C13_C8_1, x0 // encoding: [0x20,0xd8,0x1c,0xd5] // NOAMVS-NEXT: msr S3_4_C13_C8_2, x0 // encoding: [0x40,0xd8,0x1c,0xd5] diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt b/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt --- a/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt +++ b/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt @@ -6,34 +6,40 @@ [0xc0,0x11,0x1c,0xd5] [0x80,0x31,0x1c,0xd5] [0xa0,0x31,0x1c,0xd5] +[0xc0,0x31,0x1c,0xd5] # CHECK: msr HFGRTR_EL2, x0 # CHECK: msr HFGWTR_EL2, x0 # CHECK: msr HFGITR_EL2, x0 # CHECK: msr HDFGRTR_EL2, x0 # CHECK: msr HDFGWTR_EL2, x0 +# CHECK: msr HAFGRTR_EL2, x0 # NOFGT: msr S3_4_C1_C1_4, x0 # NOFGT: msr S3_4_C1_C1_5, x0 # NOFGT: msr S3_4_C1_C1_6, x0 # NOFGT: msr S3_4_C3_C1_4, x0 # NOFGT: msr S3_4_C3_C1_5, x0 +# NOFGT: msr S3_4_C3_C1_6, x0 [0x80,0x11,0x3c,0xd5] [0xa0,0x11,0x3c,0xd5] [0xc0,0x11,0x3c,0xd5] [0x80,0x31,0x3c,0xd5] [0xa0,0x31,0x3c,0xd5] +[0xc0,0x31,0x3c,0xd5] # CHECK: mrs x0, HFGRTR_EL2 # CHECK: mrs x0, HFGWTR_EL2 # CHECK: mrs x0, HFGITR_EL2 # CHECK: mrs x0, HDFGRTR_EL2 # CHECK: mrs x0, HDFGWTR_EL2 +# CHECK: mrs x0, HAFGRTR_EL2 # NOFGT: mrs x0, S3_4_C1_C1_4 # NOFGT: mrs x0, S3_4_C1_C1_5 # NOFGT: mrs x0, S3_4_C1_C1_6 # NOFGT: mrs x0, S3_4_C3_C1_4 # NOFGT: mrs x0, S3_4_C3_C1_5 +# NOFGT: mrs x0, S3_4_C3_C1_6 [0x03,0x31,0x3c,0xd5] [0x23,0x31,0x3c,0xd5] diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt --- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -3509,6 +3509,7 @@ # CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}} # CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} # CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} +# CHECK: mrs x9, {{id_dfr1_el1|ID_DFR1_EL1}} # CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} # CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} # CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} @@ -4068,6 +4069,7 @@ 0x9 0x1 0x38 0xd5 0x29 0x1 0x38 0xd5 0x49 0x1 0x38 0xd5 +0xa9 0x3 0x38 0xd5 0x69 0x1 0x38 0xd5 0x89 0x1 0x38 0xd5 0xa9 0x1 0x38 0xd5