diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -1470,7 +1470,7 @@ default: break; case ISD::ROTL: if (isa(V.getOperand(1))) { - unsigned RotAmt = V.getConstantOperandVal(1); + unsigned RotAmt = V.getConstantOperandVal(1) & (NumBits - 1); const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second; @@ -1483,15 +1483,20 @@ case ISD::SHL: case PPCISD::SHL: if (isa(V.getOperand(1))) { - unsigned ShiftAmt = V.getConstantOperandVal(1); + // sld takes 7 bits, slw takes 6. + unsigned ShiftAmt = V.getConstantOperandVal(1) & ((NumBits << 1) - 1); const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second; - for (unsigned i = ShiftAmt; i < NumBits; ++i) - Bits[i] = LHSBits[i - ShiftAmt]; - - for (unsigned i = 0; i < ShiftAmt; ++i) - Bits[i] = ValueBit(ValueBit::ConstZero); + if (ShiftAmt >= NumBits) { + for (unsigned i = 0; i < NumBits; ++i) + Bits[i] = ValueBit(ValueBit::ConstZero); + } else { + for (unsigned i = ShiftAmt; i < NumBits; ++i) + Bits[i] = LHSBits[i - ShiftAmt]; + for (unsigned i = 0; i < ShiftAmt; ++i) + Bits[i] = ValueBit(ValueBit::ConstZero); + } return std::make_pair(Interesting = true, &Bits); } @@ -1499,15 +1504,20 @@ case ISD::SRL: case PPCISD::SRL: if (isa(V.getOperand(1))) { - unsigned ShiftAmt = V.getConstantOperandVal(1); + // srd takes lowest 7 bits, srw takes 6. + unsigned ShiftAmt = V.getConstantOperandVal(1) & ((NumBits << 1) - 1); const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second; - for (unsigned i = 0; i < NumBits - ShiftAmt; ++i) - Bits[i] = LHSBits[i + ShiftAmt]; - - for (unsigned i = NumBits - ShiftAmt; i < NumBits; ++i) - Bits[i] = ValueBit(ValueBit::ConstZero); + if (ShiftAmt >= NumBits) { + for (unsigned i = 0; i < NumBits; ++i) + Bits[i] = ValueBit(ValueBit::ConstZero); + } else { + for (unsigned i = 0; i < NumBits - ShiftAmt; ++i) + Bits[i] = LHSBits[i + ShiftAmt]; + for (unsigned i = NumBits - ShiftAmt; i < NumBits; ++i) + Bits[i] = ValueBit(ValueBit::ConstZero); + } return std::make_pair(Interesting = true, &Bits); } diff --git a/llvm/test/CodeGen/PowerPC/pr59074.ll b/llvm/test/CodeGen/PowerPC/pr59074.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr59074.ll @@ -0,0 +1,109 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=LE64 +; RUN: llc -mtriple=powerpcle-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=LE32 +; RUN: llc -mtriple=powerpc64-ibm-aix -mcpu=pwr7 < %s | FileCheck %s --check-prefix=BE64 +; RUN: llc -mtriple=powerpc-ibm-aix -mcpu=pwr7 < %s | FileCheck %s --check-prefix=BE32 + +; To verify this doesn't crash due to array out of bound. +define void @pr59074(ptr %0) { +; LE64-LABEL: pr59074: +; LE64: # %bb.0: # %entry +; LE64-NEXT: lwz 5, 0(3) +; LE64-NEXT: li 4, 12 +; LE64-NEXT: ld 6, 16(3) +; LE64-NEXT: li 7, 0 +; LE64-NEXT: std 7, 8(3) +; LE64-NEXT: addi 5, 5, -12 +; LE64-NEXT: std 6, 16(3) +; LE64-NEXT: srd 4, 4, 5 +; LE64-NEXT: ld 5, 24(3) +; LE64-NEXT: std 4, 0(3) +; LE64-NEXT: std 5, 24(3) +; LE64-NEXT: blr +; +; LE32-LABEL: pr59074: +; LE32: # %bb.0: # %entry +; LE32-NEXT: lwz 5, 0(3) +; LE32-NEXT: li 4, 12 +; LE32-NEXT: lwz 6, 4(3) +; LE32-NEXT: li 7, 0 +; LE32-NEXT: lwz 8, 8(3) +; LE32-NEXT: lwz 9, 12(3) +; LE32-NEXT: subc 5, 5, 4 +; LE32-NEXT: stw 7, 8(3) +; LE32-NEXT: subfe. 6, 7, 6 +; LE32-NEXT: cmplwi 1, 5, 64 +; LE32-NEXT: subfe 8, 7, 8 +; LE32-NEXT: crand 20, 2, 4 +; LE32-NEXT: stw 7, 12(3) +; LE32-NEXT: subfe 9, 7, 9 +; LE32-NEXT: stw 7, 4(3) +; LE32-NEXT: or. 10, 8, 9 +; LE32-NEXT: or 8, 5, 8 +; LE32-NEXT: or 6, 6, 9 +; LE32-NEXT: lwz 9, 24(3) +; LE32-NEXT: crnand 20, 2, 20 +; LE32-NEXT: srw 5, 4, 5 +; LE32-NEXT: or. 6, 8, 6 +; LE32-NEXT: lwz 6, 28(3) +; LE32-NEXT: stw 9, 24(3) +; LE32-NEXT: isel 5, 0, 5, 20 +; LE32-NEXT: stw 6, 28(3) +; LE32-NEXT: iseleq 4, 4, 5 +; LE32-NEXT: stw 4, 0(3) +; LE32-NEXT: blr +; +; BE64-LABEL: pr59074: +; BE64: # %bb.0: # %entry +; BE64-NEXT: lwz 5, 12(3) +; BE64-NEXT: li 4, 12 +; BE64-NEXT: ld 6, 24(3) +; BE64-NEXT: li 7, 0 +; BE64-NEXT: std 7, 0(3) +; BE64-NEXT: addi 5, 5, -12 +; BE64-NEXT: std 6, 24(3) +; BE64-NEXT: srd 4, 4, 5 +; BE64-NEXT: ld 5, 16(3) +; BE64-NEXT: std 4, 8(3) +; BE64-NEXT: std 5, 16(3) +; BE64-NEXT: blr +; +; BE32-LABEL: pr59074: +; BE32: # %bb.0: # %entry +; BE32-NEXT: lwz 5, 12(3) +; BE32-NEXT: li 4, 12 +; BE32-NEXT: lwz 6, 8(3) +; BE32-NEXT: li 7, 0 +; BE32-NEXT: lwz 8, 4(3) +; BE32-NEXT: lwz 9, 0(3) +; BE32-NEXT: subc 5, 5, 4 +; BE32-NEXT: stw 7, 8(3) +; BE32-NEXT: subfe. 6, 7, 6 +; BE32-NEXT: cmplwi 1, 5, 64 +; BE32-NEXT: subfe 8, 7, 8 +; BE32-NEXT: crand 20, 2, 4 +; BE32-NEXT: stw 7, 0(3) +; BE32-NEXT: subfe 9, 7, 9 +; BE32-NEXT: stw 7, 4(3) +; BE32-NEXT: or. 10, 8, 9 +; BE32-NEXT: or 8, 5, 8 +; BE32-NEXT: or 6, 6, 9 +; BE32-NEXT: lwz 9, 20(3) +; BE32-NEXT: crnand 20, 2, 20 +; BE32-NEXT: srw 5, 4, 5 +; BE32-NEXT: or. 6, 8, 6 +; BE32-NEXT: lwz 6, 16(3) +; BE32-NEXT: stw 9, 20(3) +; BE32-NEXT: isel 5, 0, 5, 20 +; BE32-NEXT: stw 6, 16(3) +; BE32-NEXT: iseleq 4, 4, 5 +; BE32-NEXT: stw 4, 12(3) +; BE32-NEXT: blr +entry: + %v1 = load <2 x i128>, <2 x i128>* %0 + %v2 = insertelement <2 x i128> %v1, i128 12, i32 0 + %v3 = sub <2 x i128> %v1, %v2 + %v4 = lshr <2 x i128> %v2, %v3 + store <2 x i128> %v4, <2 x i128>* %0 + ret void +}