diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h --- a/llvm/include/llvm/ADT/Triple.h +++ b/llvm/include/llvm/ADT/Triple.h @@ -220,7 +220,8 @@ WASI, // Experimental WebAssembly OS Emscripten, ShaderModel, // DirectX ShaderModel - LastOSType = ShaderModel + LiteOS, + LastOSType = LiteOS }; enum EnvironmentType { UnknownEnvironment, @@ -247,7 +248,7 @@ CoreCLR, Simulator, // Simulator variants of other systems, e.g., Apple's iOS MacABI, // Mac Catalyst variant of Apple's iOS deployment target. - + // Shader Stages // The order of these values matters, and must be kept in sync with the // language options enum in Clang. The ordering is enforced in @@ -267,8 +268,8 @@ Callable, Mesh, Amplification, - - LastEnvironmentType = Amplification + OpenHOS, + LastEnvironmentType = OpenHOS }; enum ObjectFormatType { UnknownObjectFormat, @@ -732,9 +733,18 @@ return getEnvironment() == Triple::Musl || getEnvironment() == Triple::MuslEABI || getEnvironment() == Triple::MuslEABIHF || - getEnvironment() == Triple::MuslX32; + getEnvironment() == Triple::MuslX32 || + getEnvironment() == Triple::OpenHOS || isOSLiteOS(); } + /// Tests whether the target is OHOS + /// LiteOS default enviroment is also OHOS, but omited on triple. + bool isOHOSFamily() const { return isOpenHOS() || isOSLiteOS(); } + + bool isOpenHOS() const { return getEnvironment() == Triple::OpenHOS; } + + bool isOSLiteOS() const { return getOS() == Triple::LiteOS; } + /// Tests whether the target is DXIL. bool isDXIL() const { return getArch() == Triple::dxil; @@ -781,6 +791,7 @@ getEnvironment() == Triple::MuslEABI || getEnvironment() == Triple::EABIHF || getEnvironment() == Triple::GNUEABIHF || + getEnvironment() == Triple::OpenHOS || getEnvironment() == Triple::MuslEABIHF || isAndroid()) && isOSBinFormatELF(); } diff --git a/llvm/include/llvm/BinaryFormat/MinidumpConstants.def b/llvm/include/llvm/BinaryFormat/MinidumpConstants.def --- a/llvm/include/llvm/BinaryFormat/MinidumpConstants.def +++ b/llvm/include/llvm/BinaryFormat/MinidumpConstants.def @@ -115,6 +115,7 @@ HANDLE_MDMP_PLATFORM(0x8203, Android) // Android HANDLE_MDMP_PLATFORM(0x8204, PS3) // PS3 HANDLE_MDMP_PLATFORM(0x8205, NaCl) // Native Client (NaCl) +HANDLE_MDMP_PLATFORM(0x8207, OpenHOS) HANDLE_MDMP_PROTECT(0x01, NoAccess, PAGE_NO_ACCESS) HANDLE_MDMP_PROTECT(0x02, ReadOnly, PAGE_READ_ONLY) diff --git a/llvm/lib/Support/AArch64TargetParser.cpp b/llvm/lib/Support/AArch64TargetParser.cpp --- a/llvm/lib/Support/AArch64TargetParser.cpp +++ b/llvm/lib/Support/AArch64TargetParser.cpp @@ -179,7 +179,7 @@ bool AArch64::isX18ReservedByDefault(const Triple &TT) { return TT.isAndroid() || TT.isOSDarwin() || TT.isOSFuchsia() || - TT.isOSWindows(); + TT.isOSWindows() || TT.isOHOSFamily(); } // Allows partial match, ex. "v8a" matches "armv8a". diff --git a/llvm/lib/Support/ARMTargetParser.cpp b/llvm/lib/Support/ARMTargetParser.cpp --- a/llvm/lib/Support/ARMTargetParser.cpp +++ b/llvm/lib/Support/ARMTargetParser.cpp @@ -638,7 +638,7 @@ default: if (TT.isOSNetBSD()) return "apcs-gnu"; - if (TT.isOSOpenBSD()) + if (TT.isOSOpenBSD() || TT.isOHOSFamily()) return "aapcs-linux"; return "aapcs"; } diff --git a/llvm/lib/Support/Triple.cpp b/llvm/lib/Support/Triple.cpp --- a/llvm/lib/Support/Triple.cpp +++ b/llvm/lib/Support/Triple.cpp @@ -239,6 +239,7 @@ case Win32: return "windows"; case ZOS: return "zos"; case ShaderModel: return "shadermodel"; + case LiteOS: return "liteos"; } llvm_unreachable("Invalid OSType"); @@ -283,6 +284,7 @@ case Callable: return "callable"; case Mesh: return "mesh"; case Amplification: return "amplification"; + case OpenHOS: return "ohos"; } llvm_unreachable("Invalid EnvironmentType!"); @@ -587,6 +589,7 @@ .StartsWith("wasi", Triple::WASI) .StartsWith("emscripten", Triple::Emscripten) .StartsWith("shadermodel", Triple::ShaderModel) + .StartsWith("liteos", Triple::LiteOS) .Default(Triple::UnknownOS); } @@ -628,6 +631,7 @@ .StartsWith("callable", Triple::Callable) .StartsWith("mesh", Triple::Mesh) .StartsWith("amplification", Triple::Amplification) + .StartsWith("ohos", Triple::OpenHOS) .Default(Triple::UnknownEnvironment); } diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -389,7 +389,8 @@ } bool isTargetMuslAEABI() const { return (TargetTriple.getEnvironment() == Triple::MuslEABI || - TargetTriple.getEnvironment() == Triple::MuslEABIHF) && + TargetTriple.getEnvironment() == Triple::MuslEABIHF || + TargetTriple.getEnvironment() == Triple::OpenHOS) && !isTargetDarwin() && !isTargetWindows(); } diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -240,7 +240,8 @@ if ((TargetTriple.getEnvironment() == Triple::GNUEABI || TargetTriple.getEnvironment() == Triple::GNUEABIHF || TargetTriple.getEnvironment() == Triple::MuslEABI || - TargetTriple.getEnvironment() == Triple::MuslEABIHF) && + TargetTriple.getEnvironment() == Triple::MuslEABIHF || + TargetTriple.getEnvironment() == Triple::OpenHOS) && !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin())) this->Options.EABIVersion = EABI::GNU; else diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -4285,6 +4285,8 @@ SelectionDAG &DAG) const { GlobalAddressSDNode *N = cast(Op); assert(N->getOffset() == 0 && "unexpected offset in global node"); + if (DAG.getTarget().useEmulatedTLS()) + return LowerToTLSEmulatedModel(N, DAG); TLSModel::Model Model = getTargetMachine().getTLSModel(N->getGlobal()); diff --git a/llvm/test/CodeGen/AArch64/arm64-platform-reg.ll b/llvm/test/CodeGen/AArch64/arm64-platform-reg.ll --- a/llvm/test/CodeGen/AArch64/arm64-platform-reg.ll +++ b/llvm/test/CodeGen/AArch64/arm64-platform-reg.ll @@ -2,6 +2,7 @@ ; RUN: llc -mtriple=arm64-freebsd-gnu -mattr=+reserve-x18 -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE --check-prefix=CHECK-RESERVE-X18 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-android -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE --check-prefix=CHECK-RESERVE-X18 +; RUN: llc -mtriple=aarch64-linux-ohos -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE --check-prefix=CHECK-RESERVE-X18 ; RUN: llc -mtriple=aarch64-fuchsia -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE --check-prefix=CHECK-RESERVE-X18 ; RUN: llc -mtriple=aarch64-windows -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE --check-prefix=CHECK-RESERVE-X18 diff --git a/llvm/test/CodeGen/RISCV/emutls.ll b/llvm/test/CodeGen/RISCV/emutls.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/emutls.ll @@ -0,0 +1,307 @@ +; RUN: llc < %s -emulated-tls -mtriple=riscv64-linux-gnu | FileCheck -check-prefix=RISCV64 %s +; RUN: llc < %s -emulated-tls -mtriple=riscv64-linux-ohos | FileCheck -check-prefix=RISCV64 %s + +; RUN: llc < %s -mtriple=riscv64-linux-gnu | FileCheck -check-prefix=NoEMU %s +; RUN: llc < %s -mtriple=riscv64-linux-ohos | FileCheck -check-prefix=RISCV64 %s + +; Copied from X86/emutls.ll + +; NoEMU-NOT: __emutls + +; Use my_emutls_get_address like __emutls_get_address. +@my_emutls_v_xyz = external global i8*, align 4 +declare i8* @my_emutls_get_address(i8*) + +define dso_local i32 @my_get_xyz() { +; RISCV64-LABEL: my_get_xyz: +; RISCV64: lui a0, %hi(my_emutls_v_xyz) +; RISCV64-NEXT: addi a0, a0, %lo(my_emutls_v_xyz) +; RISCV64-NEXT: call my_emutls_get_address@plt +; RISCV64-NEXT: lw a0, 0(a0) +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + %call = call i8* @my_emutls_get_address(i8* bitcast (i8** @my_emutls_v_xyz to i8*)) + %0 = bitcast i8* %call to i32* + %1 = load i32, i32* %0, align 4 + ret i32 %1 +} + +@i1 = dso_local thread_local global i32 15 +@i2 = external thread_local global i32 +@i3 = internal thread_local global i32 15 +@i4 = hidden thread_local global i32 15 +@i5 = external hidden thread_local global i32 +@s1 = dso_local thread_local global i16 15 +@b1 = dso_local thread_local global i8 0 + +define dso_local i32 @f1() { +; RISCV64-LABEL: f1: +; RISCV64: lui a0, %hi(__emutls_v.i1) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.i1) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: lw a0, 0(a0) +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + %tmp1 = load i32, i32* @i1 + ret i32 %tmp1 +} + +define dso_local i32* @f2() { +; RISCV64-LABEL: f2: +; RISCV64: lui a0, %hi(__emutls_v.i1) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.i1) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + ret i32* @i1 +} + +define dso_local i32 @f3() nounwind { +; RISCV64-LABEL: f3: +; RISCV64: lui a0, %hi(__emutls_v.i2) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.i2) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: lw a0, 0(a0) +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + %tmp1 = load i32, i32* @i2 + ret i32 %tmp1 +} + +define dso_local i32* @f4() { +; RISCV64-LABEL: f4: +; RISCV64: lui a0, %hi(__emutls_v.i2) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.i2) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + ret i32* @i2 +} + +define dso_local i32 @f5() nounwind { +; RISCV64-LABEL: f5: +; RISCV64: lui a0, %hi(__emutls_v.i3) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.i3) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: lw a0, 0(a0) +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + %tmp1 = load i32, i32* @i3 + ret i32 %tmp1 +} + +define dso_local i32* @f6() { +; RISCV64-LABEL: f6: +; RISCV64: lui a0, %hi(__emutls_v.i3) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.i3) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + ret i32* @i3 +} + +define dso_local i32 @f7() { +; RISCV64-LABEL: f7: +; RISCV64: lui a0, %hi(__emutls_v.i4) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.i4) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: lw a0, 0(a0) +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + %tmp1 = load i32, i32* @i4 + ret i32 %tmp1 +} + +define dso_local i32* @f8() { +; RISCV64-LABEL: f8: +; RISCV64: lui a0, %hi(__emutls_v.i4) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.i4) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + ret i32* @i4 +} + +define dso_local i32 @f9() { +; RISCV64-LABEL: f9: +; RISCV64: lui a0, %hi(__emutls_v.i5) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.i5) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: lw a0, 0(a0) +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + %tmp1 = load i32, i32* @i5 + ret i32 %tmp1 +} + +define dso_local i32* @f10() { +; RISCV64-LABEL: f10: +; RISCV64: lui a0, %hi(__emutls_v.i5) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.i5) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + ret i32* @i5 +} + +define dso_local i16 @f11() { +; RISCV64-LABEL: f11: +; RISCV64: lui a0, %hi(__emutls_v.s1) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.s1) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: lh a0, 0(a0) +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + %tmp1 = load i16, i16* @s1 + ret i16 %tmp1 +} + +define dso_local i32 @f12sext() { +; RISCV64-LABEL: f12sext: +; RISCV64: lui a0, %hi(__emutls_v.s1) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.s1) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: lh a0, 0(a0) +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + %tmp1 = load i16, i16* @s1 + %tmp2 = sext i16 %tmp1 to i32 + ret i32 %tmp2 +} + +define dso_local i32 @f12zext() { +; RISCV64-LABEL: f12zext: +; RISCV64: lui a0, %hi(__emutls_v.s1) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.s1) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: lhu a0, 0(a0) +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + %tmp1 = load i16, i16* @s1 + %tmp2 = zext i16 %tmp1 to i32 + ret i32 %tmp2 +} + +define dso_local i8 @f13() { +; RISCV64-LABEL: f13: +; RISCV64: lui a0, %hi(__emutls_v.b1) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.b1) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: lb a0, 0(a0) +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + %tmp1 = load i8, i8* @b1 + ret i8 %tmp1 +} + +define dso_local i32 @f14sext() { +; RISCV64-LABEL: f14sext: +; RISCV64: lui a0, %hi(__emutls_v.b1) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.b1) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: lb a0, 0(a0) +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + %tmp1 = load i8, i8* @b1 + %tmp2 = sext i8 %tmp1 to i32 + ret i32 %tmp2 +} + +define dso_local i32 @f14zext() { +; RISCV64-LABEL: f14zext: +; RISCV64: lui a0, %hi(__emutls_v.b1) +; RISCV64-NEXT: addi a0, a0, %lo(__emutls_v.b1) +; RISCV64-NEXT: call __emutls_get_address@plt +; RISCV64-NEXT: lbu a0, 0(a0) +; RISCV64-NEXT: ld ra, 8(sp) +; RISCV64-NEXT: addi sp, sp, 16 +; RISCV64-NEXT: ret +entry: + %tmp1 = load i8, i8* @b1 + %tmp2 = zext i8 %tmp1 to i32 + ret i32 %tmp2 +} + +;;;;;;;;;;;;;; 64-bit __emutls_v. and __emutls_t. + +; RISCV64-LABEL: __emutls_v.i1: +; RISCV64-NEXT: .quad 4 +; RISCV64-NEXT: .quad 4 +; RISCV64-NEXT: .quad 0 +; RISCV64-NEXT: .quad __emutls_t.i1 + +; RISCV64-LABEL: __emutls_t.i1: +; RISCV64-NEXT: .word 15 + +; RISCV64-NOT: __emutls_v.i2 + +; RISCV64-LABEL: __emutls_v.i3: +; RISCV64-NEXT: .quad 4 +; RISCV64-NEXT: .quad 4 +; RISCV64-NEXT: .quad 0 +; RISCV64-NEXT: .quad __emutls_t.i3 + +; RISCV64-LABEL: __emutls_t.i3: +; RISCV64-NEXT: .word 15 + +; RISCV64-LABEL: __emutls_v.i4: +; RISCV64-NEXT: .quad 4 +; RISCV64-NEXT: .quad 4 +; RISCV64-NEXT: .quad 0 +; RISCV64-NEXT: .quad __emutls_t.i4 + +; RISCV64-LABEL: __emutls_t.i4: +; RISCV64-NEXT: .word 15 + +; RISCV64-NOT: __emutls_v.i5: +; RISCV64: .hidden __emutls_v.i5 +; RISCV64-NOT: __emutls_v.i5: + +; RISCV64-LABEL: __emutls_v.s1: +; RISCV64-NEXT: .quad 2 +; RISCV64-NEXT: .quad 2 +; RISCV64-NEXT: .quad 0 +; RISCV64-NEXT: .quad __emutls_t.s1 + +; RISCV64-LABEL: __emutls_t.s1: +; RISCV64-NEXT: .half 15 + +; RISCV64-LABEL: __emutls_v.b1: +; RISCV64-NEXT: .quad 1 +; RISCV64-NEXT: .quad 1 +; RISCV64-NEXT: .quad 0 +; RISCV64-NEXT: .quad 0 + +; RISCV64-NOT: __emutls_t.b1 diff --git a/llvm/test/CodeGen/RISCV/emutls_generic.ll b/llvm/test/CodeGen/RISCV/emutls_generic.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/emutls_generic.ll @@ -0,0 +1,75 @@ +; RUN: llc < %s -emulated-tls -mtriple=riscv64-linux-gnu -O3 \ +; RUN: | FileCheck -check-prefix=RISCV64 %s +; RUN: llc < %s -emulated-tls -mtriple=riscv64-linux-ohos -relocation-model=pic \ +; RUN: | FileCheck -check-prefix=RISCV64 %s +; RUN: llc < %s -emulated-tls -mtriple=riscv64-linux-ohos -relocation-model=pic -O3 \ +; RUN: | FileCheck -check-prefix=RISCV64 %s +; RUN: llc < %s -emulated-tls -mtriple=riscv64-linux-ohos -O3 \ +; RUN: | FileCheck -check-prefix=RISCV64 %s + +; RUN: llc < %s -mtriple=riscv64-linux-gnu -O3 \ +; RUN: | FileCheck -check-prefix=NoEMU %s +; RUN: llc < %s -mtriple=riscv64-linux-ohos -relocation-model=pic \ +; RUN: | FileCheck -check-prefix=RISCV64 %s +; RUN: llc < %s -mtriple=riscv64-linux-ohos -relocation-model=pic -O3 \ +; RUN: | FileCheck -check-prefix=RISCV64 %s +; RUN: llc < %s -mtriple=riscv64-linux-ohos -O3 \ +; RUN: | FileCheck -check-prefix=RISCV64 %s + +; NoEMU-NOT: __emutls + +; Make sure that TLS symbols are emitted in expected order. + +@external_x = external thread_local global i32, align 8 +@external_y = thread_local global i8 7, align 2 +@internal_y = internal thread_local global i64 9, align 16 + +define i32* @get_external_x() { +entry: + ret i32* @external_x +} + +define i8* @get_external_y() { +entry: + ret i8* @external_y +} + +define i64* @get_internal_y() { +entry: + ret i64* @internal_y +} + +; RISCV64-LABEL: get_external_x: +; RISCV64: __emutls_v.external_x +; RISCV64: __emutls_get_address +; RISCV64-LABEL: get_external_y: +; RISCV64: __emutls_v.external_y +; RISCV64: __emutls_get_address +; RISCV64-LABEL: get_internal_y: +; RISCV64: __emutls_v.internal_y +; RISCV64: __emutls_get_address +; RISCV64-NOT: __emutls_t.external_x +; RISCV64-NOT: __emutls_v.external_x: +; RISCV64: .data{{$}} +; RISCV64: .globl __emutls_v.external_y +; RISCV64: .p2align 3 +; RISCV64-LABEL: __emutls_v.external_y: +; RISCV64-NEXT: .quad 1 +; RISCV64-NEXT: .quad 2 +; RISCV64-NEXT: .quad 0 +; RISCV64-NEXT: .quad __emutls_t.external_y +; RISCV64-NOT: __emutls_v.external_x: +; RISCV64: .section .r{{o?}}data, +; RISCV64-LABEL: __emutls_t.external_y: +; RISCV64-NEXT: .byte 7 +; RISCV64: .data{{$}} +; RISCV64-NOT: .globl __emutls_v +; RISCV64: .p2align 3 +; RISCV64-LABEL: __emutls_v.internal_y: +; RISCV64-NEXT: .quad 8 +; RISCV64-NEXT: .quad 16 +; RISCV64-NEXT: .quad 0 +; RISCV64-NEXT: .quad __emutls_t.internal_y +; RISCV64: .section .r{{o?}}data, +; RISCV64-LABEL: __emutls_t.internal_y: +; RISCV64-NEXT: .quad 9 diff --git a/llvm/test/Transforms/SafeStack/AArch64/abi.ll b/llvm/test/Transforms/SafeStack/AArch64/abi.ll --- a/llvm/test/Transforms/SafeStack/AArch64/abi.ll +++ b/llvm/test/Transforms/SafeStack/AArch64/abi.ll @@ -1,8 +1,10 @@ ; RUN: opt -safe-stack -S -mtriple=aarch64-linux-android < %s -o - | FileCheck %s +; RUN: opt -safe-stack -S -mtriple=aarch64-linux-ohos < %s -o - | FileCheck %s --check-prefix=OHOS define void @foo() nounwind uwtable safestack { entry: +; OHOS-NOT: call i8* @llvm.thread.pointer() ; CHECK: %[[TP:.*]] = call i8* @llvm.thread.pointer() ; CHECK: %[[SPA0:.*]] = getelementptr i8, i8* %[[TP]], i32 72 ; CHECK: %[[SPA:.*]] = bitcast i8* %[[SPA0]] to i8** diff --git a/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll b/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll --- a/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll +++ b/llvm/test/Transforms/SafeStack/AArch64/abi_ssp.ll @@ -1,4 +1,5 @@ ; RUN: opt -safe-stack -S -mtriple=aarch64-linux-android < %s -o - | FileCheck --check-prefixes=TLS,ANDROID %s +; RUN: opt -safe-stack -S -mtriple=aarch64-linux-ohos < %s -o - | FileCheck --check-prefix=OHOS %s ; RUN: opt -safe-stack -S -mtriple=aarch64-unknown-fuchsia < %s -o - | FileCheck --check-prefixes=TLS,FUCHSIA %s define void @foo() nounwind uwtable safestack sspreq { @@ -6,6 +7,7 @@ ; The first @llvm.thread.pointer is for the unsafe stack pointer, skip it. ; TLS: call i8* @llvm.thread.pointer() +; OHOS-NOT: call i8* @llvm.thread.pointer() ; TLS: %[[TP2:.*]] = call i8* @llvm.thread.pointer() ; ANDROID: %[[B:.*]] = getelementptr i8, i8* %[[TP2]], i32 40 ; FUCHSIA: %[[B:.*]] = getelementptr i8, i8* %[[TP2]], i32 -16 diff --git a/llvm/test/Transforms/SafeStack/AArch64/unreachable.ll b/llvm/test/Transforms/SafeStack/AArch64/unreachable.ll --- a/llvm/test/Transforms/SafeStack/AArch64/unreachable.ll +++ b/llvm/test/Transforms/SafeStack/AArch64/unreachable.ll @@ -1,7 +1,9 @@ ; RUN: opt -safe-stack -safe-stack-coloring -S -mtriple=aarch64-linux-android < %s -o - | FileCheck %s +; RUN: opt -safe-stack -safe-stack-coloring -S -mtriple=aarch64-linux-ohos < %s -o - | FileCheck %s --check-prefix=OHOSMUSL define void @foo() nounwind uwtable safestack { entry: +; OHOSMUSL-NOT: call i8* @llvm.thread.pointer() ; CHECK: %[[TP:.*]] = call i8* @llvm.thread.pointer() ; CHECK: %[[SPA0:.*]] = getelementptr i8, i8* %[[TP]], i32 72 ; CHECK: %[[SPA:.*]] = bitcast i8* %[[SPA0]] to i8** diff --git a/llvm/unittests/ADT/TripleTest.cpp b/llvm/unittests/ADT/TripleTest.cpp --- a/llvm/unittests/ADT/TripleTest.cpp +++ b/llvm/unittests/ADT/TripleTest.cpp @@ -804,6 +804,18 @@ EXPECT_EQ(Triple::Amplification, T.getEnvironment()); EXPECT_FALSE(T.supportsCOMDAT()); + T = Triple("arm-unknown-linux-ohos"); + EXPECT_EQ(Triple::arm, T.getArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::Linux, T.getOS()); + EXPECT_EQ(Triple::OpenHOS, T.getEnvironment()); + + T = Triple("arm-unknown-liteos"); + EXPECT_EQ(Triple::arm, T.getArch()); + EXPECT_EQ(Triple::UnknownVendor, T.getVendor()); + EXPECT_EQ(Triple::LiteOS, T.getOS()); + EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment()); + T = Triple("huh"); EXPECT_EQ(Triple::UnknownArch, T.getArch()); }