diff --git a/bolt/include/bolt/Core/BinaryBasicBlock.h b/bolt/include/bolt/Core/BinaryBasicBlock.h --- a/bolt/include/bolt/Core/BinaryBasicBlock.h +++ b/bolt/include/bolt/Core/BinaryBasicBlock.h @@ -570,6 +570,7 @@ } /// Return required alignment for the block. + Align getAlign() const { return Align(Alignment); } uint32_t getAlignment() const { return Alignment; } /// Set the maximum number of bytes to use for the block alignment. diff --git a/bolt/include/bolt/Core/BinaryFunction.h b/bolt/include/bolt/Core/BinaryFunction.h --- a/bolt/include/bolt/Core/BinaryFunction.h +++ b/bolt/include/bolt/Core/BinaryFunction.h @@ -1785,6 +1785,7 @@ return *this; } + Align getAlign() const { return Align(Alignment); } uint16_t getAlignment() const { return Alignment; } BinaryFunction &setMaxAlignmentBytes(uint16_t MaxAlignBytes) { diff --git a/bolt/include/bolt/Core/BinarySection.h b/bolt/include/bolt/Core/BinarySection.h --- a/bolt/include/bolt/Core/BinarySection.h +++ b/bolt/include/bolt/Core/BinarySection.h @@ -254,6 +254,7 @@ uint64_t getEndAddress() const { return Address + Size; } uint64_t getSize() const { return Size; } uint64_t getInputFileOffset() const { return InputFileOffset; } + Align getAlign() const { return Align(Alignment); } uint64_t getAlignment() const { return Alignment; } bool isText() const { if (isELF()) diff --git a/bolt/lib/Core/BinaryEmitter.cpp b/bolt/lib/Core/BinaryEmitter.cpp --- a/bolt/lib/Core/BinaryEmitter.cpp +++ b/bolt/lib/Core/BinaryEmitter.cpp @@ -300,18 +300,16 @@ // Set section alignment to at least maximum possible object alignment. // We need this to support LongJmp and other passes that calculates // tentative layout. - if (Section->getAlignment() < opts::AlignFunctions) - Section->setAlignment(Align(opts::AlignFunctions)); + Section->ensureMinAlignment(Align(opts::AlignFunctions)); - Streamer.emitCodeAlignment(BinaryFunction::MinAlign, &*BC.STI); + Streamer.emitCodeAlignment(Align(BinaryFunction::MinAlign), &*BC.STI); uint16_t MaxAlignBytes = FF.isSplitFragment() ? Function.getMaxColdAlignmentBytes() : Function.getMaxAlignmentBytes(); if (MaxAlignBytes > 0) - Streamer.emitCodeAlignment(Function.getAlignment(), &*BC.STI, - MaxAlignBytes); + Streamer.emitCodeAlignment(Function.getAlign(), &*BC.STI, MaxAlignBytes); } else { - Streamer.emitCodeAlignment(Function.getAlignment(), &*BC.STI); + Streamer.emitCodeAlignment(Function.getAlign(), &*BC.STI); } MCContext &Context = Streamer.getContext(); @@ -427,7 +425,7 @@ for (BinaryBasicBlock *const BB : FF) { if ((opts::AlignBlocks || opts::PreserveBlocksAlignment) && BB->getAlignment() > 1) - Streamer.emitCodeAlignment(BB->getAlignment(), &*BC.STI, + Streamer.emitCodeAlignment(BB->getAlign(), &*BC.STI, BB->getAlignmentMaxBytes()); Streamer.emitLabel(BB->getLabel()); if (!EmitCodeOnly) { @@ -516,7 +514,7 @@ const uint16_t Alignment = OnBehalfOf ? OnBehalfOf->getConstantIslandAlignment() : BF.getConstantIslandAlignment(); - Streamer.emitCodeAlignment(Alignment, &*BC.STI); + Streamer.emitCodeAlignment(Align(Alignment), &*BC.STI); if (!OnBehalfOf) { if (!EmitColdPart) @@ -796,7 +794,7 @@ LabelCounts[CurrentLabel] = CurrentLabelCount; } else { Streamer.switchSection(JT.Count > 0 ? HotSection : ColdSection); - Streamer.emitValueToAlignment(JT.EntrySize); + Streamer.emitValueToAlignment(Align(JT.EntrySize)); } MCSymbol *LastLabel = nullptr; uint64_t Offset = 0; @@ -816,7 +814,7 @@ Streamer.switchSection(HotSection); else Streamer.switchSection(ColdSection); - Streamer.emitValueToAlignment(JT.EntrySize); + Streamer.emitValueToAlignment(Align(JT.EntrySize)); } // Emit all labels registered at the address of this jump table // to sync with our global symbol table. We may have two labels @@ -926,7 +924,7 @@ const uint16_t TTypeAlignment = 4; // Type tables have to be aligned at 4 bytes. - Streamer.emitValueToAlignment(TTypeAlignment); + Streamer.emitValueToAlignment(Align(TTypeAlignment)); // Emit the LSDA label. MCSymbol *LSDASymbol = BF.getLSDASymbol(FF.getFragmentNum()); diff --git a/bolt/lib/Core/BinarySection.cpp b/bolt/lib/Core/BinarySection.cpp --- a/bolt/lib/Core/BinarySection.cpp +++ b/bolt/lib/Core/BinarySection.cpp @@ -74,7 +74,7 @@ BC.Ctx->getELFSection(SectionName, getELFType(), getELFFlags()); Streamer.switchSection(ELFSection); - Streamer.emitValueToAlignment(getAlignment()); + Streamer.emitValueToAlignment(getAlign()); if (BC.HasRelocations && opts::HotData && isReordered()) Streamer.emitLabel(BC.Ctx->getOrCreateSymbol("__hot_data_start")); diff --git a/bolt/lib/Profile/DataAggregator.cpp b/bolt/lib/Profile/DataAggregator.cpp --- a/bolt/lib/Profile/DataAggregator.cpp +++ b/bolt/lib/Profile/DataAggregator.cpp @@ -2233,7 +2233,7 @@ OutFile << "boltedcollection\n"; if (opts::BasicAggregation) { OutFile << "no_lbr"; - for (const StringMapEntry &Entry : EventNames) + for (const StringMapEntry &Entry : EventNames) OutFile << " " << Entry.getKey(); OutFile << "\n"; diff --git a/bolt/lib/Profile/YAMLProfileWriter.cpp b/bolt/lib/Profile/YAMLProfileWriter.cpp --- a/bolt/lib/Profile/YAMLProfileWriter.cpp +++ b/bolt/lib/Profile/YAMLProfileWriter.cpp @@ -161,7 +161,7 @@ StringSet<> EventNames = RI.getProfileReader()->getEventNames(); if (!EventNames.empty()) { std::string Sep; - for (const StringMapEntry &EventEntry : EventNames) { + for (const StringMapEntry &EventEntry : EventNames) { BP.Header.EventNames += Sep + EventEntry.first().str(); Sep = ","; } diff --git a/clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.cpp b/clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.cpp --- a/clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.cpp +++ b/clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.cpp @@ -62,7 +62,9 @@ ImplicitCastToNull, hasAncestor(cxxRewrittenBinaryOperator().bind( "checkBinopOperands"))) - .bind(CastSequence)))))); + .bind(CastSequence))), + // Skip defaulted comparison operators. + unless(hasAncestor(functionDecl(isDefaulted())))))); } bool isReplaceableRange(SourceLocation StartLoc, SourceLocation EndLoc, diff --git a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp --- a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp +++ b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp @@ -214,7 +214,7 @@ public: explicit NameLookup(const NamedDecl *ND) : Data(ND, false) {} - explicit NameLookup(llvm::NoneType) : Data(nullptr, true) {} + explicit NameLookup(std::nullopt_t) : Data(nullptr, true) {} explicit NameLookup(std::nullptr_t) : Data(nullptr, false) {} NameLookup() : NameLookup(nullptr) {} diff --git a/clang-tools-extra/clangd/Headers.h b/clang-tools-extra/clangd/Headers.h --- a/clang-tools-extra/clangd/Headers.h +++ b/clang-tools-extra/clangd/Headers.h @@ -35,12 +35,6 @@ /// Returns true if \p Include is literal include like "path" or . bool isLiteralInclude(llvm::StringRef Include); -/// If Text begins an Include-What-You-Use directive, returns it. -/// Given "// IWYU pragma: keep", returns "keep". -/// Input is a null-terminated char* as provided by SM.getCharacterData(). -/// (This should not be StringRef as we do *not* want to scan for its length). -llvm::Optional parseIWYUPragma(const char *Text); - /// Represents a header file to be #include'd. struct HeaderFile { std::string File; diff --git a/clang-tools-extra/clangd/Headers.cpp b/clang-tools-extra/clangd/Headers.cpp --- a/clang-tools-extra/clangd/Headers.cpp +++ b/clang-tools-extra/clangd/Headers.cpp @@ -23,18 +23,6 @@ namespace clang { namespace clangd { -llvm::Optional parseIWYUPragma(const char *Text) { - // This gets called for every comment seen in the preamble, so it's quite hot. - constexpr llvm::StringLiteral IWYUPragma = "// IWYU pragma: "; - if (strncmp(Text, IWYUPragma.data(), IWYUPragma.size())) - return llvm::None; - Text += IWYUPragma.size(); - const char *End = Text; - while (*End != 0 && *End != '\n') - ++End; - return StringRef(Text, End - Text); -} - class IncludeStructure::RecordHeaders : public PPCallbacks, public CommentHandler { public: @@ -136,7 +124,8 @@ } bool HandleComment(Preprocessor &PP, SourceRange Range) override { - auto Pragma = parseIWYUPragma(SM.getCharacterData(Range.getBegin())); + auto Pragma = + tooling::parseIWYUPragma(SM.getCharacterData(Range.getBegin())); if (!Pragma) return false; diff --git a/clang-tools-extra/clangd/TidyFastChecks.inc b/clang-tools-extra/clangd/TidyFastChecks.inc new file mode 100644 --- /dev/null +++ b/clang-tools-extra/clangd/TidyFastChecks.inc @@ -0,0 +1,378 @@ +// This file is generated, do not edit it directly! +// Deltas are percentage regression in parsing clang/lib/Sema/Sema.cpp +#ifndef FAST +#define FAST(CHECK, DELTA) +#endif +#ifndef SLOW +#define SLOW(CHECK, DELTA) +#endif + +FAST(abseil-cleanup-ctad, -1.0) +FAST(abseil-duration-addition, 0.0) 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+FAST(hicpp-signed-bitwise, 0.0) +FAST(hicpp-special-member-functions, 0.0) +FAST(hicpp-static-assert, 1.0) +FAST(hicpp-undelegated-constructor, 3.0) +FAST(hicpp-uppercase-literal-suffix, 3.0) +FAST(hicpp-use-auto, 3.0) +FAST(hicpp-use-emplace, 1.0) +FAST(hicpp-use-equals-default, 1.0) +FAST(hicpp-use-equals-delete, 0.0) +FAST(hicpp-use-noexcept, -1.0) +FAST(hicpp-use-nullptr, 2.0) +FAST(hicpp-use-override, -0.0) +FAST(hicpp-vararg, -2.0) +FAST(linuxkernel-must-check-errs, 1.0) +FAST(llvm-else-after-return, 0.0) +FAST(llvm-header-guard, 2.0) +FAST(llvm-include-order, 3.0) +FAST(llvm-namespace-comment, 1.0) +FAST(llvm-prefer-isa-or-dyn-cast-in-conditionals, 0.0) +FAST(llvm-prefer-register-over-unsigned, 1.0) +FAST(llvm-qualified-auto, 0.0) +FAST(llvm-twine-local, -2.0) +FAST(llvmlibc-callee-namespace, 2.0) +FAST(llvmlibc-implementation-in-namespace, 2.0) +FAST(llvmlibc-restrict-system-libc-headers, -0.0) +FAST(misc-confusable-identifiers, 1.0) +SLOW(misc-const-correctness, 261.0) +FAST(misc-definitions-in-headers, -1.0) +FAST(misc-misleading-bidirectional, -0.0) +FAST(misc-misleading-identifier, -1.0) +FAST(misc-misplaced-const, 1.0) +FAST(misc-new-delete-overloads, -1.0) +FAST(misc-no-recursion, -2.0) +FAST(misc-non-copyable-objects, 1.0) +FAST(misc-non-private-member-variables-in-classes, 2.0) +FAST(misc-redundant-expression, 0.0) +FAST(misc-static-assert, 1.0) +FAST(misc-throw-by-value-catch-by-reference, -1.0) +FAST(misc-unconventional-assign-operator, 1.0) +FAST(misc-uniqueptr-reset-release, 0.0) +FAST(misc-unused-alias-decls, 1.0) +FAST(misc-unused-parameters, 0.0) +FAST(misc-unused-using-decls, 4.0) +FAST(modernize-avoid-bind, 1.0) +FAST(modernize-avoid-c-arrays, 2.0) +FAST(modernize-concat-nested-namespaces, -1.0) +FAST(modernize-deprecated-headers, -0.0) +FAST(modernize-deprecated-ios-base-aliases, 1.0) +FAST(modernize-loop-convert, 2.0) +FAST(modernize-macro-to-enum, 1.0) +FAST(modernize-make-shared, -0.0) +FAST(modernize-make-unique, 0.0) +FAST(modernize-pass-by-value, 1.0) +FAST(modernize-raw-string-literal, 1.0) +FAST(modernize-redundant-void-arg, -1.0) +FAST(modernize-replace-auto-ptr, -1.0) +FAST(modernize-replace-disallow-copy-and-assign-macro, -2.0) +FAST(modernize-replace-random-shuffle, 0.0) +FAST(modernize-return-braced-init-list, -1.0) +FAST(modernize-shrink-to-fit, 2.0) +FAST(modernize-unary-static-assert, -1.0) +FAST(modernize-use-auto, 2.0) +FAST(modernize-use-bool-literals, 1.0) +FAST(modernize-use-default-member-init, 2.0) +FAST(modernize-use-emplace, 1.0) +FAST(modernize-use-equals-default, 2.0) +FAST(modernize-use-equals-delete, 0.0) +FAST(modernize-use-nodiscard, 1.0) +FAST(modernize-use-noexcept, 1.0) +FAST(modernize-use-nullptr, 2.0) +FAST(modernize-use-override, 1.0) +FAST(modernize-use-trailing-return-type, -0.0) +FAST(modernize-use-transparent-functors, -1.0) +FAST(modernize-use-uncaught-exceptions, 1.0) +FAST(modernize-use-using, 1.0) +FAST(objc-assert-equals, -1.0) +FAST(objc-avoid-nserror-init, -2.0) +FAST(objc-dealloc-in-category, -0.0) +FAST(objc-forbidden-subclassing, 0.0) +FAST(objc-missing-hash, 1.0) +FAST(objc-nsdate-formatter, 1.0) +FAST(objc-nsinvocation-argument-lifetime, -2.0) +FAST(objc-property-declaration, -1.0) +FAST(objc-super-self, -0.0) +FAST(openmp-exception-escape, 1.0) +FAST(openmp-use-default-none, 1.0) +FAST(performance-faster-string-find, 2.0) +FAST(performance-for-range-copy, 2.0) +FAST(performance-implicit-conversion-in-loop, 1.0) +FAST(performance-inefficient-algorithm, 0.0) +FAST(performance-inefficient-string-concatenation, -0.0) +FAST(performance-inefficient-vector-operation, 1.0) +FAST(performance-move-const-arg, 3.0) +FAST(performance-move-constructor-init, 1.0) +FAST(performance-no-automatic-move, -1.0) +FAST(performance-no-int-to-ptr, 2.0) +FAST(performance-noexcept-move-constructor, 1.0) +FAST(performance-trivially-destructible, -1.0) +FAST(performance-type-promotion-in-math-fn, 4.0) +FAST(performance-unnecessary-copy-initialization, 4.0) +FAST(performance-unnecessary-value-param, 2.0) +FAST(portability-restrict-system-includes, 2.0) +FAST(portability-simd-intrinsics, 2.0) +FAST(portability-std-allocator-const, 2.0) +FAST(readability-avoid-const-params-in-decls, -0.0) +FAST(readability-braces-around-statements, 2.0) +FAST(readability-const-return-type, -0.0) +FAST(readability-container-contains, -0.0) +FAST(readability-container-data-pointer, 0.0) +SLOW(readability-container-size-empty, 16.0) +FAST(readability-convert-member-functions-to-static, 0.0) +FAST(readability-delete-null-pointer, 0.0) +FAST(readability-duplicate-include, -0.0) +FAST(readability-else-after-return, 1.0) +FAST(readability-function-cognitive-complexity, 0.0) +FAST(readability-function-size, 3.0) +FAST(readability-identifier-length, -1.0) +FAST(readability-identifier-naming, 5.0) +FAST(readability-implicit-bool-conversion, 2.0) +FAST(readability-inconsistent-declaration-parameter-name, 1.0) +FAST(readability-isolate-declaration, 1.0) +FAST(readability-magic-numbers, -1.0) +FAST(readability-make-member-function-const, 2.0) +FAST(readability-misleading-indentation, 0.0) +FAST(readability-misplaced-array-index, -0.0) +FAST(readability-named-parameter, -0.0) +FAST(readability-non-const-parameter, 1.0) +FAST(readability-qualified-auto, -0.0) +FAST(readability-redundant-access-specifiers, -1.0) +FAST(readability-redundant-control-flow, -1.0) +FAST(readability-redundant-declaration, -0.0) +FAST(readability-redundant-function-ptr-dereference, -1.0) +FAST(readability-redundant-member-init, 0.0) +FAST(readability-redundant-preprocessor, 0.0) +FAST(readability-redundant-smartptr-get, 6.0) +FAST(readability-redundant-string-cstr, 0.0) +FAST(readability-redundant-string-init, 1.0) +FAST(readability-simplify-boolean-expr, 1.0) +FAST(readability-simplify-subscript-expr, -0.0) +FAST(readability-static-accessed-through-instance, 1.0) +FAST(readability-static-definition-in-anonymous-namespace, -0.0) +FAST(readability-string-compare, -0.0) +FAST(readability-suspicious-call-argument, 0.0) +FAST(readability-uniqueptr-delete-release, 1.0) +FAST(readability-uppercase-literal-suffix, 3.0) +FAST(readability-use-anyofallof, 1.0) +FAST(zircon-temporary-objects, 1.0) + +#undef FAST +#undef SLOW diff --git a/clang-tools-extra/clangd/TidyFastChecks.py b/clang-tools-extra/clangd/TidyFastChecks.py new file mode 100755 --- /dev/null +++ b/clang-tools-extra/clangd/TidyFastChecks.py @@ -0,0 +1,95 @@ +#!/usr/bin/env python3 +# +# Determines which clang-tidy checks are "fast enough" to run in clangd. +# This runs clangd --check --check-tidy-time and parses the output. +# This program outputs a header fragment specifying which checks are fast: +# FAST(bugprone-argument-comment, 5) +# SLOW(misc-const-correctness, 200) +# If given the old header fragment as input, we lean to preserve its choices. +# +# This is not deterministic or hermetic, but should be run occasionally to +# update the list of allowed checks. From llvm-project: +# clang-tools-extra/clangd/TidyFastChecks.py --clangd=build-opt/bin/clangd +# Be sure to use an optimized, no-asserts, tidy-enabled build of clangd! + +import argparse +import os +import re +import subprocess +import sys + +# Checks faster than FAST_THRESHOLD are fast, slower than SLOW_THRESHOLD slow. +# If a check is in between, we stick with our previous decision. This avoids +# enabling/disabling checks between releases due to random measurement jitter. +FAST_THRESHOLD = 8 # percent +SLOW_THRESHOLD = 15 + +parser = argparse.ArgumentParser() +parser.add_argument('--target', help='X-macro output file. ' + 'If it exists, existing contents will be used for hysteresis', + default='clang-tools-extra/clangd/TidyFastChecks.inc') +parser.add_argument('--source', help='Source file to benchmark tidy checks', + default='clang/lib/Sema/Sema.cpp') +parser.add_argument('--clangd', help='clangd binary to invoke', + default='build/bin/clangd') +parser.add_argument('--checks', help='check glob to run', default='*') +parser.add_argument('--verbose', help='log clangd output', action='store_true') +args = parser.parse_args() + +# Use the preprocessor to extract the list of previously-fast checks. +def read_old_fast(path): + text = subprocess.check_output(["cpp", + "-P", # Omit GNU line markers + "-nostdinc", # Don't include stdc-predef.h + "-DFAST(C,T)=C", # Print fast checks only + path]) + for line in text.splitlines(): + if line.strip(): + yield line.strip().decode('utf-8') +old_fast = list(read_old_fast(args.target)) if os.path.exists(args.target) else [] +print(f"Old fast checks: {old_fast}", file=sys.stderr) + +# Runs clangd --check --check-tidy-time. +# Yields (check, percent-overhead) pairs. +def measure(): + process = subprocess.Popen([args.clangd, + "--check=" + args.source, + "--check-locations=0", # Skip useless slow steps. + "--check-tidy-time=" + args.checks], + stderr=subprocess.PIPE) + recording = False + for line in iter(process.stderr.readline, b""): + if args.verbose: + print("clangd> ", line, file=sys.stderr) + if not recording: + if b'Timing AST build with individual clang-tidy checks' in line: + recording = True + continue + if b'Finished individual clang-tidy checks' in line: + return + match = re.search(rb'(\S+) = (\S+)%', line) + if match: + yield (match.group(1).decode('utf-8'), float(match.group(2))) + +with open(args.target, 'w', buffering=1) as target: + # Produce an includable X-macros fragment with our decisions. + print(f"""// This file is generated, do not edit it directly! +// Deltas are percentage regression in parsing {args.source} +#ifndef FAST +#define FAST(CHECK, DELTA) +#endif +#ifndef SLOW +#define SLOW(CHECK, DELTA) +#endif +""", file=target) + + for check, time in measure(): + threshold = SLOW_THRESHOLD if check in old_fast else FAST_THRESHOLD + decision = "FAST" if time <= threshold else "SLOW" + print(f"{decision} {check} {time}% <= {threshold}%", file=sys.stderr) + print(f"{decision}({check}, {time})", file=target) + + print(""" +#undef FAST +#undef SLOW +""", file=target) diff --git a/clang-tools-extra/clangd/index/CanonicalIncludes.cpp b/clang-tools-extra/clangd/index/CanonicalIncludes.cpp --- a/clang-tools-extra/clangd/index/CanonicalIncludes.cpp +++ b/clang-tools-extra/clangd/index/CanonicalIncludes.cpp @@ -9,6 +9,7 @@ #include "CanonicalIncludes.h" #include "Headers.h" #include "clang/Basic/FileEntry.h" +#include "clang/Tooling/Inclusions/HeaderAnalysis.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/FileSystem/UniqueID.h" #include "llvm/Support/Path.h" @@ -710,7 +711,7 @@ PragmaCommentHandler(CanonicalIncludes *Includes) : Includes(Includes) {} bool HandleComment(Preprocessor &PP, SourceRange Range) override { - auto Pragma = parseIWYUPragma( + auto Pragma = tooling::parseIWYUPragma( PP.getSourceManager().getCharacterData(Range.getBegin())); if (!Pragma || !Pragma->consume_front("private, include ")) return false; diff --git a/clang-tools-extra/clangd/support/ThreadsafeFS.h b/clang-tools-extra/clangd/support/ThreadsafeFS.h --- a/clang-tools-extra/clangd/support/ThreadsafeFS.h +++ b/clang-tools-extra/clangd/support/ThreadsafeFS.h @@ -30,7 +30,7 @@ /// Obtain a vfs::FileSystem with an arbitrary initial working directory. llvm::IntrusiveRefCntPtr - view(llvm::NoneType CWD) const { + view(std::nullopt_t CWD) const { return viewImpl(); } diff --git a/clang-tools-extra/clangd/tool/Check.cpp b/clang-tools-extra/clangd/tool/Check.cpp --- a/clang-tools-extra/clangd/tool/Check.cpp +++ b/clang-tools-extra/clangd/tool/Check.cpp @@ -241,6 +241,9 @@ elog("-{0} requires -DCLANGD_TIDY_CHECKS!", CheckTidyTime.ArgStr); return false; } + #ifndef NDEBUG + elog("Timing clang-tidy checks in asserts-mode is not representative!"); + #endif checkTidyTimes(); } diff --git a/clang-tools-extra/clangd/unittests/HeadersTests.cpp b/clang-tools-extra/clangd/unittests/HeadersTests.cpp --- a/clang-tools-extra/clangd/unittests/HeadersTests.cpp +++ b/clang-tools-extra/clangd/unittests/HeadersTests.cpp @@ -447,18 +447,6 @@ EXPECT_FALSE(Includes.hasIWYUExport(getID("none.h", Includes))); } -TEST(Headers, ParseIWYUPragma) { - EXPECT_THAT(parseIWYUPragma("// IWYU pragma: keep"), HasValue(Eq("keep"))); - EXPECT_THAT(parseIWYUPragma("// IWYU pragma: keep\netc"), - HasValue(Eq("keep"))); - EXPECT_EQ(parseIWYUPragma("/* IWYU pragma: keep"), llvm::None) - << "Only // comments supported!"; - EXPECT_EQ(parseIWYUPragma("// IWYU pragma: keep"), llvm::None) - << "Sensitive to whitespace"; - EXPECT_EQ(parseIWYUPragma("// IWYU pragma:keep"), llvm::None) - << "Sensitive to whitespace"; -} - } // namespace } // namespace clangd } // namespace clang diff --git a/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Record.h b/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Record.h --- a/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Record.h +++ b/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Record.h @@ -17,16 +17,15 @@ #ifndef CLANG_INCLUDE_CLEANER_RECORD_H #define CLANG_INCLUDE_CLEANER_RECORD_H +#include "clang-include-cleaner/Types.h" +#include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseSet.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/FileSystem/UniqueID.h" -#include "clang-include-cleaner/Types.h" -#include "llvm/ADT/ArrayRef.h" -#include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/StringMap.h" #include #include @@ -73,6 +72,9 @@ /// Returns true if the given file is a self-contained file. bool isSelfContained(const FileEntry *File) const; + /// Returns true if the given file is marked with the IWYU private pragma. + bool isPrivate(const FileEntry *File) const; + private: class RecordPragma; /// 1-based Line numbers for the #include directives of the main file that @@ -80,7 +82,8 @@ /// export` right after). llvm::DenseSet ShouldKeep; - /// The public header mapping by the IWYU private pragma. + /// The public header mapping by the IWYU private pragma. For private pragmas + // without public mapping an empty StringRef is stored. // // !!NOTE: instead of using a FileEntry* to identify the physical file, we // deliberately use the UniqueID to ensure the result is stable across @@ -147,11 +150,15 @@ /// - for a logical file like , we check Spelled llvm::SmallVector match(Header H) const; + /// Finds the include written on the specified line. + const Include *atLine(unsigned OneBasedIndex) const; + private: std::vector All; // Lookup structures for match(), values are index into All. llvm::StringMap> BySpelling; llvm::DenseMap> ByFile; + llvm::DenseMap ByLine; } Includes; }; diff --git a/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Types.h b/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Types.h --- a/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Types.h +++ b/clang-tools-extra/include-cleaner/include/clang-include-cleaner/Types.h @@ -64,9 +64,11 @@ struct Macro macro() const { return std::get(Storage); } private: - // FIXME: Add support for macros. // Order must match Kind enum! std::variant Storage; + + Symbol(decltype(Storage) Sentinel) : Storage(std::move(Sentinel)) {} + friend llvm::DenseMapInfo; }; llvm::raw_ostream &operator<<(llvm::raw_ostream &, const Symbol &); @@ -137,4 +139,36 @@ } // namespace include_cleaner } // namespace clang +namespace llvm { + +template <> struct DenseMapInfo { + using Outer = clang::include_cleaner::Symbol; + using Base = DenseMapInfo; + + static inline Outer getEmptyKey() { return {Base::getEmptyKey()}; } + static inline Outer getTombstoneKey() { return {Base::getTombstoneKey()}; } + static unsigned getHashValue(const Outer &Val) { + return Base::getHashValue(Val.Storage); + } + static bool isEqual(const Outer &LHS, const Outer &RHS) { + return Base::isEqual(LHS.Storage, RHS.Storage); + } +}; +template <> struct DenseMapInfo { + using Outer = clang::include_cleaner::Macro; + using Base = DenseMapInfo; + + static inline Outer getEmptyKey() { return {nullptr, Base::getEmptyKey()}; } + static inline Outer getTombstoneKey() { + return {nullptr, Base::getTombstoneKey()}; + } + static unsigned getHashValue(const Outer &Val) { + return Base::getHashValue(Val.Definition); + } + static bool isEqual(const Outer &LHS, const Outer &RHS) { + return Base::isEqual(LHS.Definition, RHS.Definition); + } +}; +} // namespace llvm + #endif diff --git a/clang-tools-extra/include-cleaner/lib/Analysis.cpp b/clang-tools-extra/include-cleaner/lib/Analysis.cpp --- a/clang-tools-extra/include-cleaner/lib/Analysis.cpp +++ b/clang-tools-extra/include-cleaner/lib/Analysis.cpp @@ -38,8 +38,7 @@ } for (const SymbolReference &MacroRef : MacroRefs) { assert(MacroRef.Target.kind() == Symbol::Macro); - return CB(MacroRef, - findHeaders(MacroRef.Target.macro().Definition, SM, PI)); + CB(MacroRef, findHeaders(MacroRef.Target.macro().Definition, SM, PI)); } } diff --git a/clang-tools-extra/include-cleaner/lib/AnalysisInternal.h b/clang-tools-extra/include-cleaner/lib/AnalysisInternal.h --- a/clang-tools-extra/include-cleaner/lib/AnalysisInternal.h +++ b/clang-tools-extra/include-cleaner/lib/AnalysisInternal.h @@ -29,6 +29,7 @@ namespace clang { class ASTContext; class Decl; +class HeaderSearch; class NamedDecl; namespace include_cleaner { @@ -87,7 +88,8 @@ void writeHTMLReport(FileID File, const RecordedPP::RecordedIncludes &Includes, llvm::ArrayRef Roots, llvm::ArrayRef MacroRefs, ASTContext &Ctx, - PragmaIncludes *PI, llvm::raw_ostream &OS); + HeaderSearch &HS, PragmaIncludes *PI, + llvm::raw_ostream &OS); } // namespace include_cleaner } // namespace clang diff --git a/clang-tools-extra/include-cleaner/lib/HTMLReport.cpp b/clang-tools-extra/include-cleaner/lib/HTMLReport.cpp --- a/clang-tools-extra/include-cleaner/lib/HTMLReport.cpp +++ b/clang-tools-extra/include-cleaner/lib/HTMLReport.cpp @@ -18,10 +18,12 @@ #include "clang/AST/ASTContext.h" #include "clang/AST/PrettyPrinter.h" #include "clang/Basic/SourceManager.h" +#include "clang/Lex/HeaderSearch.h" #include "clang/Lex/Lexer.h" #include "clang/Tooling/Inclusions/StandardLibrary.h" #include "llvm/Support/ScopedPrinter.h" #include "llvm/Support/raw_ostream.h" +#include namespace clang::include_cleaner { namespace { @@ -29,7 +31,7 @@ constexpr llvm::StringLiteral CSS = R"css( body { margin: 0; } pre { line-height: 1.5em; counter-reset: line; margin: 0; } - pre .line { counter-increment: line; } + pre .line:not(.added) { counter-increment: line; } pre .line::before { content: counter(line); display: inline-block; @@ -37,7 +39,8 @@ text-align: right; width: 3em; padding-right: 0.5em; margin-right: 0.5em; } - .ref { text-decoration: underline; color: #008; } + pre .line.added::before { content: '+' } + .ref, .inc { text-decoration: underline; color: #008; } .sel { position: relative; cursor: pointer; } .ref.implicit { background-color: #ff8; } #hover { @@ -49,15 +52,19 @@ padding: 0.5em; } #hover p, #hover pre { margin: 0; } - #hover .target.implicit { background-color: #bbb; } - #hover .target.ambiguous { background-color: #caf; } + #hover .target.implicit, .provides .implicit { background-color: #bbb; } + #hover .target.ambiguous, .provides .ambiguous { background-color: #caf; } .missing, .unused { background-color: #faa !important; } + .inserted { background-color: #bea !important; } + .semiused { background-color: #888 !important; } #hover th { color: #008; text-align: right; padding-right: 0.5em; } #hover .target:not(:first-child) { margin-top: 1em; padding-top: 1em; border-top: 1px solid #444; } + .ref.missing #hover .insert { background-color: #bea; } + .ref:not(.missing) #hover .insert { font-style: italic; } )css"; constexpr llvm::StringLiteral JS = R"js( @@ -95,6 +102,22 @@ llvm_unreachable("unhandled symbol kind"); } +// Return detailed symbol description (declaration), if we have any. +std::string printDetails(const Symbol &Sym) { + std::string S; + if (Sym.kind() == Symbol::Declaration) { + // Print the declaration of the symbol, e.g. to disambiguate overloads. + const auto &D = Sym.declaration(); + PrintingPolicy PP = D.getASTContext().getPrintingPolicy(); + PP.FullyQualifiedName = true; + PP.TerseOutput = true; + PP.SuppressInitializers = true; + llvm::raw_string_ostream SS(S); + D.print(SS, PP); + } + return S; +} + llvm::StringRef refType(RefType T) { switch (T) { case RefType::Explicit: @@ -111,76 +134,97 @@ llvm::raw_ostream &OS; const ASTContext &Ctx; const SourceManager &SM; + HeaderSearch &HS; const RecordedPP::RecordedIncludes &Includes; const PragmaIncludes *PI; FileID MainFile; const FileEntry *MainFE; - // References to symbols from the main file. - // FIXME: should we deduplicate these? - struct Target { - Symbol Sym; - RefType Type; - SmallVector Locations; - SmallVector
Headers; - SmallVector Includes; - bool Satisfied = false; // Is the include present? - }; - std::vector Targets; - // Points within the main file that reference a Target. + // Points within the main file that reference a Symbol. // Implicit refs will be marked with a symbol just before the token. struct Ref { unsigned Offset; - bool Implicit; - size_t TargetIndex; - bool operator<(const Ref &Other) const { - return std::forward_as_tuple(Offset, !Implicit, TargetIndex) < - std::forward_as_tuple(Other.Offset, !Other.Implicit, TargetIndex); - } + RefType Type; + Symbol Sym; + SmallVector Locations = {}; + SmallVector
Headers = {}; + SmallVector Includes = {}; + bool Satisfied = false; // Is the include present? + std::string Insert = {}; // If we had no includes, what would we insert? }; std::vector Refs; + llvm::DenseMap> IncludeRefs; + llvm::StringMap> Insertion; + + llvm::StringRef includeType(const Include *I) { + auto &List = IncludeRefs[I]; + if (List.empty()) + return "unused"; + if (llvm::any_of(List, [&](unsigned I) { + return Refs[I].Type == RefType::Explicit; + })) + return "used"; + return "semiused"; + } - Target makeTarget(const SymbolReference &SR) { - Target T{SR.Target, SR.RT, {}, {}, {}}; + std::string spellHeader(const Header &H) { + switch (H.kind()) { + case Header::Physical: { + bool IsSystem = false; + std::string Path = HS.suggestPathToFileForDiagnostics( + H.physical(), MainFE->tryGetRealPathName(), &IsSystem); + return IsSystem ? "<" + Path + ">" : "\"" + Path + "\""; + } + case Header::Standard: + return H.standard().name().str(); + case Header::Verbatim: + return H.verbatim().str(); + } + llvm_unreachable("Unknown Header kind"); + } + void fillTarget(Ref &R) { // Duplicates logic from walkUsed(), which doesn't expose SymbolLocations. // FIXME: use locateDecl and friends once implemented. // This doesn't use stdlib::Recognizer, but locateDecl will soon do that. - switch (SR.Target.kind()) { + switch (R.Sym.kind()) { case Symbol::Declaration: - T.Locations.push_back(SR.Target.declaration().getLocation()); + R.Locations.push_back(R.Sym.declaration().getLocation()); break; case Symbol::Macro: - T.Locations.push_back(SR.Target.macro().Definition); + R.Locations.push_back(R.Sym.macro().Definition); break; } - for (const auto &Loc : T.Locations) - T.Headers.append(findHeaders(Loc, SM, PI)); + for (const auto &Loc : R.Locations) + R.Headers.append(findHeaders(Loc, SM, PI)); - for (const auto &H : T.Headers) { - T.Includes.append(Includes.match(H)); + for (const auto &H : R.Headers) { + R.Includes.append(Includes.match(H)); // FIXME: library should signal main-file refs somehow. // Non-physical refs to the main-file should be possible. if (H.kind() == Header::Physical && H.physical() == MainFE) - T.Satisfied = true; + R.Satisfied = true; } - if (!T.Includes.empty()) - T.Satisfied = true; + if (!R.Includes.empty()) + R.Satisfied = true; // Include pointers are meaningfully ordered as they are backed by a vector. - llvm::sort(T.Includes); - T.Includes.erase(std::unique(T.Includes.begin(), T.Includes.end()), - T.Includes.end()); + llvm::sort(R.Includes); + R.Includes.erase(std::unique(R.Includes.begin(), R.Includes.end()), + R.Includes.end()); - return T; + if (!R.Headers.empty()) + // FIXME: library should tell us which header to use. + R.Insert = spellHeader(R.Headers.front()); } public: - Reporter(llvm::raw_ostream &OS, ASTContext &Ctx, + Reporter(llvm::raw_ostream &OS, ASTContext &Ctx, HeaderSearch &HS, const RecordedPP::RecordedIncludes &Includes, const PragmaIncludes *PI, FileID MainFile) - : OS(OS), Ctx(Ctx), SM(Ctx.getSourceManager()), Includes(Includes), - PI(PI), MainFile(MainFile), MainFE(SM.getFileEntryForID(MainFile)) {} + : OS(OS), Ctx(Ctx), SM(Ctx.getSourceManager()), HS(HS), + Includes(Includes), PI(PI), MainFile(MainFile), + MainFE(SM.getFileEntryForID(MainFile)) {} void addRef(const SymbolReference &SR) { auto [File, Offset] = SM.getDecomposedLoc(SM.getFileLoc(SR.RefLocation)); @@ -192,8 +236,14 @@ return; } - Refs.push_back({Offset, SR.RT == RefType::Implicit, Targets.size()}); - Targets.push_back(makeTarget(SR)); + int RefIndex = Refs.size(); + Refs.emplace_back(Ref{Offset, SR.RT, SR.Target}); + Ref &R = Refs.back(); + fillTarget(R); + for (const auto *I : R.Includes) + IncludeRefs[I].push_back(RefIndex); + if (R.Type == RefType::Explicit && !R.Satisfied && !R.Insert.empty()) + Insertion[R.Insert].push_back(RefIndex); } void write() { @@ -202,9 +252,21 @@ OS << "\n"; OS << "\n"; OS << "\n"; - for (unsigned I = 0; I < Targets.size(); ++I) { + for (const auto &Ins : Insertion) { + OS << "\n"; + } + for (auto &Inc : Includes.all()) { + OS << "\n"; + } + for (unsigned I = 0; I < Refs.size(); ++I) { OS << "\n"; } OS << "\n"; @@ -259,32 +321,74 @@ printFilename(SM.getSpellingLoc(Loc).printToString(SM)); OS << ">"; } + + // Write "Provides: " rows of an include or include-insertion table. + // These describe the symbols the header provides, referenced by RefIndices. + void writeProvides(llvm::ArrayRef RefIndices) { + // We show one ref for each symbol: first by (RefType != Explicit, Sequence) + llvm::DenseMap FirstRef; + for (unsigned RefIndex : RefIndices) { + const Ref &R = Refs[RefIndex]; + auto I = FirstRef.try_emplace(R.Sym, RefIndex); + if (!I.second && R.Type == RefType::Explicit && + Refs[I.first->second].Type != RefType::Explicit) + I.first->second = RefIndex; + } + std::vector> Sorted = {FirstRef.begin(), + FirstRef.end()}; + llvm::stable_sort(Sorted, llvm::less_second{}); + for (auto &[S, RefIndex] : Sorted) { + auto &R = Refs[RefIndex]; + OS << "Provides"; + std::string Details = printDetails(S); + if (!Details.empty()) { + OS << ""; + } + escapeString(llvm::to_string(S)); + if (!Details.empty()) + OS << ""; - void writeTarget(const Target &T) { - OS << ""; + unsigned Line = SM.getLineNumber(MainFile, R.Offset); + OS << ", line " << Line << ""; + OS << ""; + } + } + + void writeInclude(const Include &Inc) { + OS << "
"; + if (Inc.Resolved) { + OS << "\n"; + writeProvides(IncludeRefs[&Inc]); + } + OS << "
Resolved"; + escapeString(Inc.Resolved->getName()); + OS << "
"; + } + + void writeInsertion(llvm::StringRef Text, llvm::ArrayRef Refs) { + OS << ""; + writeProvides(Refs); + OS << "
"; + } + + void writeTarget(const Ref &R) { + OS << ""; OS << "\n"; - if (T.Sym.kind() == Symbol::Declaration) { - // Print the declaration of the symbol, e.g. to disambiguate overloads. - const auto &D = T.Sym.declaration(); - PrintingPolicy PP = D.getASTContext().getPrintingPolicy(); - PP.FullyQualifiedName = true; - PP.TerseOutput = true; - PP.SuppressInitializers = true; - std::string S; - llvm::raw_string_ostream SS(S); - D.print(SS, PP); - + std::string Details = printDetails(R.Sym); + if (!Details.empty()) { OS << "\n"; } - for (const auto &Loc : T.Locations) { + for (const auto &Loc : R.Locations) { OS << "\n"; } - for (const auto &H : T.Headers) { + for (const auto &H : R.Headers) { OS << "\n"; } - for (const auto *I : T.Includes) { + for (const auto *I : R.Includes) { OS << ""; } + if (!R.Insert.empty()) { + OS << ""; + } + OS << "
Symbol"; - OS << describeSymbol(T.Sym) << " "; - escapeString(llvm::to_string(T.Sym)); + OS << describeSymbol(R.Sym) << " "; + escapeString(llvm::to_string(R.Sym)); OS << "
"; - escapeString(S); + escapeString(Details); OS << "
Location"; if (Loc.kind() == SymbolLocation::Physical) // needs SM to print properly. printSourceLocation(Loc.physical()); @@ -293,7 +397,7 @@ OS << "
Header"; switch (H.kind()) { case Header::Physical: @@ -310,25 +414,64 @@ OS << "
Included"; escapeString(I->Spelled); OS << ", line " << I->Line << ""; OS << "
Insert"; + escapeString(R.Insert); + OS << "
"; } void writeCode() { - llvm::sort(Refs); llvm::StringRef Code = SM.getBufferData(MainFile); OS << "
";
-    OS << "";
-    unsigned LineNum = 1;
-    auto Rest = llvm::makeArrayRef(Refs);
+
+    std::vector Insertions{Insertion.keys().begin(),
+                                            Insertion.keys().end()};
+    llvm::sort(Insertions);
+    for (llvm::StringRef Insertion : Insertions) {
+      OS << ""
+          << "#include ";
+      escapeString(Insertion);
+      OS << "\n";
+    }
+
+    const Include *Inc = nullptr;
+    unsigned LineNum = 0;
+    // Lines are , include lines have an inner .
+    auto StartLine = [&] {
+      ++LineNum;
+      OS << "";
+      if ((Inc = Includes.atLine(LineNum)))
+        OS << "";
+    };
+    auto EndLine = [&] {
+      if (Inc)
+        OS << "";
+      OS << "\n";
+    };
+
+    std::vector RefOrder(Refs.size());
+    std::iota(RefOrder.begin(), RefOrder.end(), 0);
+    llvm::stable_sort(RefOrder, [&](unsigned A, unsigned B) {
+      return std::make_pair(Refs[A].Offset, Refs[A].Type != RefType::Implicit) <
+             std::make_pair(Refs[B].Offset, Refs[B].Type != RefType::Implicit);
+    });
+    auto Rest = llvm::makeArrayRef(RefOrder);
     unsigned End = 0;
+    StartLine();
     for (unsigned I = 0; I < Code.size(); ++I) {
       // Finish refs early at EOL to avoid dealing with splitting the span.
       if (End && (End == I || Code[I] == '\n')) {
@@ -336,25 +479,26 @@
         End = 0;
       }
       // Handle implicit refs, which are rendered *before* the token.
-      while (!Rest.empty() && Rest.front().Offset == I &&
-             Rest.front().Implicit) {
-        const Ref &R = Rest.front();
-        OS << "◊";
+      while (!Rest.empty() && Refs[Rest.front()].Offset == I &&
+             Refs[Rest.front()].Type == RefType::Implicit) {
+        const Ref &R = Refs[Rest.front()];
+        OS << "◊";
         Rest = Rest.drop_front();
       };
       // Accumulate all explicit refs that appear on the same token.
       std::string TargetList;
       bool Unsatisfied = false;
-      Rest = Rest.drop_while([&](const Ref &R) {
+      Rest = Rest.drop_while([&](unsigned RefIndex) {
+        const Ref &R = Refs[RefIndex];
         if (R.Offset != I)
           return false;
         if (!TargetList.empty())
           TargetList.push_back(',');
         TargetList.push_back('t');
-        TargetList.append(std::to_string(R.TargetIndex));
-        Unsatisfied = Unsatisfied || !Targets[R.TargetIndex].Satisfied;
+        TargetList.append(std::to_string(RefIndex));
+        Unsatisfied = Unsatisfied || !R.Satisfied;
         return true;
       });
       if (!TargetList.empty()) {
@@ -364,12 +508,14 @@
         End = I + Lexer::MeasureTokenLength(SM.getComposedLoc(MainFile, I), SM,
                                             Ctx.getLangOpts());
       }
-      if (Code[I] == '\n')
-        OS << "\n";
-      else
+      if (Code[I] == '\n') {
+        EndLine();
+        StartLine();
+      } else
         escapeChar(Code[I]);
     }
-    OS << "
\n"; + EndLine(); + OS << "\n"; } }; @@ -378,8 +524,9 @@ void writeHTMLReport(FileID File, const RecordedPP::RecordedIncludes &Includes, llvm::ArrayRef Roots, llvm::ArrayRef MacroRefs, ASTContext &Ctx, - PragmaIncludes *PI, llvm::raw_ostream &OS) { - Reporter R(OS, Ctx, Includes, PI, File); + HeaderSearch &HS, PragmaIncludes *PI, + llvm::raw_ostream &OS) { + Reporter R(OS, Ctx, HS, Includes, PI, File); for (Decl *Root : Roots) walkAST(*Root, [&](SourceLocation Loc, const NamedDecl &D, RefType T) { R.addRef(SymbolReference{Loc, D, T}); diff --git a/clang-tools-extra/include-cleaner/lib/Record.cpp b/clang-tools-extra/include-cleaner/lib/Record.cpp --- a/clang-tools-extra/include-cleaner/lib/Record.cpp +++ b/clang-tools-extra/include-cleaner/lib/Record.cpp @@ -83,14 +83,54 @@ recordMacroRef(MacroName, *MI); } + void Ifdef(SourceLocation Loc, const Token &MacroNameTok, + const MacroDefinition &MD) override { + if (!Active) + return; + if (const auto *MI = MD.getMacroInfo()) + recordMacroRef(MacroNameTok, *MI, RefType::Ambiguous); + } + + void Ifndef(SourceLocation Loc, const Token &MacroNameTok, + const MacroDefinition &MD) override { + if (!Active) + return; + if (const auto *MI = MD.getMacroInfo()) + recordMacroRef(MacroNameTok, *MI, RefType::Ambiguous); + } + + void Elifdef(SourceLocation Loc, const Token &MacroNameTok, + const MacroDefinition &MD) override { + if (!Active) + return; + if (const auto *MI = MD.getMacroInfo()) + recordMacroRef(MacroNameTok, *MI, RefType::Ambiguous); + } + + void Elifndef(SourceLocation Loc, const Token &MacroNameTok, + const MacroDefinition &MD) override { + if (!Active) + return; + if (const auto *MI = MD.getMacroInfo()) + recordMacroRef(MacroNameTok, *MI, RefType::Ambiguous); + } + + void Defined(const Token &MacroNameTok, const MacroDefinition &MD, + SourceRange Range) override { + if (!Active) + return; + if (const auto *MI = MD.getMacroInfo()) + recordMacroRef(MacroNameTok, *MI, RefType::Ambiguous); + } + private: - void recordMacroRef(const Token &Tok, const MacroInfo &MI) { + void recordMacroRef(const Token &Tok, const MacroInfo &MI, + RefType RT = RefType::Explicit) { if (MI.isBuiltinMacro()) return; // __FILE__ is not a reference. - Recorded.MacroReferences.push_back( - SymbolReference{Tok.getLocation(), - Macro{Tok.getIdentifierInfo(), MI.getDefinitionLoc()}, - RefType::Explicit}); + Recorded.MacroReferences.push_back(SymbolReference{ + Tok.getLocation(), + Macro{Tok.getIdentifierInfo(), MI.getDefinitionLoc()}, RT}); } bool Active = false; @@ -101,21 +141,6 @@ } // namespace -// FIXME: this is a mirror of clang::clangd::parseIWYUPragma, move to libTooling -// to share the code? -static llvm::Optional parseIWYUPragma(const char *Text) { - assert(strncmp(Text, "//", 2) || strncmp(Text, "/*", 2)); - constexpr llvm::StringLiteral IWYUPragma = " IWYU pragma: "; - Text += 2; // Skip the comment start, // or /*. - if (strncmp(Text, IWYUPragma.data(), IWYUPragma.size())) - return llvm::None; - Text += IWYUPragma.size(); - const char *End = Text; - while (*End != 0 && *End != '\n') - ++End; - return StringRef(Text, End - Text); -} - class PragmaIncludes::RecordPragma : public PPCallbacks, public CommentHandler { public: RecordPragma(const CompilerInstance &CI, PragmaIncludes *Out) @@ -189,18 +214,23 @@ bool HandleComment(Preprocessor &PP, SourceRange Range) override { auto &SM = PP.getSourceManager(); - auto Pragma = parseIWYUPragma(SM.getCharacterData(Range.getBegin())); + auto Pragma = + tooling::parseIWYUPragma(SM.getCharacterData(Range.getBegin())); if (!Pragma) return false; - if (Pragma->consume_front("private, include ")) { - // We always insert using the spelling from the pragma. - if (auto *FE = SM.getFileEntryForID(SM.getFileID(Range.getBegin()))) - Out->IWYUPublic.insert( - {FE->getLastRef().getUniqueID(), - save(Pragma->startswith("<") || Pragma->startswith("\"") - ? (*Pragma) - : ("\"" + *Pragma + "\"").str())}); + if (Pragma->consume_front("private")) { + auto *FE = SM.getFileEntryForID(SM.getFileID(Range.getBegin())); + if (!FE) + return false; + StringRef PublicHeader; + if (Pragma->consume_front(", include ")) { + // We always insert using the spelling from the pragma. + PublicHeader = save(Pragma->startswith("<") || Pragma->startswith("\"") + ? (*Pragma) + : ("\"" + *Pragma + "\"").str()); + } + Out->IWYUPublic.insert({FE->getLastRef().getUniqueID(), PublicHeader}); return false; } FileID CommentFID = SM.getFileID(Range.getBegin()); @@ -306,6 +336,10 @@ return !NonSelfContainedFiles.contains(FE->getUniqueID()); } +bool PragmaIncludes::isPrivate(const FileEntry *FE) const { + return IWYUPublic.find(FE->getUniqueID()) != IWYUPublic.end(); +} + std::unique_ptr RecordedAST::record() { class Recorder : public ASTConsumer { RecordedAST *Out; @@ -337,6 +371,13 @@ BySpellingIt->second.push_back(Index); if (I.Resolved) ByFile[I.Resolved].push_back(Index); + ByLine[I.Line] = Index; +} + +const Include * +RecordedPP::RecordedIncludes::atLine(unsigned OneBasedIndex) const { + auto It = ByLine.find(OneBasedIndex); + return (It == ByLine.end()) ? nullptr : &All[It->second]; } llvm::SmallVector diff --git a/clang-tools-extra/include-cleaner/tool/IncludeCleaner.cpp b/clang-tools-extra/include-cleaner/tool/IncludeCleaner.cpp --- a/clang-tools-extra/include-cleaner/tool/IncludeCleaner.cpp +++ b/clang-tools-extra/include-cleaner/tool/IncludeCleaner.cpp @@ -71,8 +71,10 @@ << ": " << EC.message() << "\n"; exit(1); } - writeHTMLReport(AST.Ctx->getSourceManager().getMainFileID(), PP.Includes, - AST.Roots, PP.MacroReferences, *AST.Ctx, &PI, OS); + writeHTMLReport( + AST.Ctx->getSourceManager().getMainFileID(), PP.Includes, AST.Roots, + PP.MacroReferences, *AST.Ctx, + getCompilerInstance().getPreprocessor().getHeaderSearchInfo(), &PI, OS); } }; diff --git a/clang-tools-extra/include-cleaner/unittests/RecordTest.cpp b/clang-tools-extra/include-cleaner/unittests/RecordTest.cpp --- a/clang-tools-extra/include-cleaner/unittests/RecordTest.cpp +++ b/clang-tools-extra/include-cleaner/unittests/RecordTest.cpp @@ -7,12 +7,13 @@ //===----------------------------------------------------------------------===// #include "clang-include-cleaner/Record.h" +#include "clang/Basic/SourceLocation.h" #include "clang/Frontend/FrontendAction.h" #include "clang/Frontend/FrontendActions.h" #include "clang/Testing/TestAST.h" #include "clang/Tooling/Inclusions/StandardLibrary.h" -#include "llvm/Support/VirtualFileSystem.h" #include "llvm/ADT/ArrayRef.h" +#include "llvm/Support/VirtualFileSystem.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Testing/Support/Annotations.h" #include "gmock/gmock.h" @@ -199,7 +200,6 @@ std::vector RefOffsets; std::vector ExpOffsets; // Expansion locs of refs in macro locs. - std::vector RefMacroLocs; for (const auto &Ref : Recorded.MacroReferences) { if (Ref.Target == OrigX) { auto [FID, Off] = SM.getDecomposedLoc(Ref.RefLocation); @@ -218,6 +218,44 @@ EXPECT_THAT(ExpOffsets, ElementsAreArray(MainFile.points("exp"))); } +TEST_F(RecordPPTest, CapturesConditionalMacroRefs) { + llvm::Annotations MainFile(R"cpp( + #define X 1 + + #ifdef ^X + #endif + + #if defined(^X) + #endif + + #ifndef ^X + #endif + + #ifdef Y + #elifdef ^X + #endif + + #ifndef ^X + #elifndef ^X + #endif + )cpp"); + + Inputs.Code = MainFile.code(); + Inputs.ExtraArgs.push_back("-std=c++2b"); + auto AST = build(); + + std::vector RefOffsets; + SourceManager &SM = AST.sourceManager(); + for (const auto &Ref : Recorded.MacroReferences) { + auto [FID, Off] = SM.getDecomposedLoc(Ref.RefLocation); + ASSERT_EQ(FID, SM.getMainFileID()); + EXPECT_EQ(Ref.RT, RefType::Ambiguous); + EXPECT_EQ("X", Ref.Target.macro().Name->getName()); + RefOffsets.push_back(Off); + } + EXPECT_THAT(RefOffsets, ElementsAreArray(MainFile.points())); +} + // Matches an Include* on the specified line; MATCHER_P(line, N, "") { return arg->Line == (unsigned)N; } @@ -308,18 +346,30 @@ Inputs.Code = R"cpp( #include "public.h" )cpp"; - Inputs.ExtraFiles["public.h"] = "#include \"private.h\""; + Inputs.ExtraFiles["public.h"] = R"cpp( + #include "private.h" + #include "private2.h" + )cpp"; Inputs.ExtraFiles["private.h"] = R"cpp( // IWYU pragma: private, include "public2.h" - class Private {}; + )cpp"; + Inputs.ExtraFiles["private2.h"] = R"cpp( + // IWYU pragma: private )cpp"; TestAST Processed = build(); auto PrivateFE = Processed.fileManager().getFile("private.h"); assert(PrivateFE); + EXPECT_TRUE(PI.isPrivate(PrivateFE.get())); EXPECT_EQ(PI.getPublic(PrivateFE.get()), "\"public2.h\""); + auto PublicFE = Processed.fileManager().getFile("public.h"); assert(PublicFE); EXPECT_EQ(PI.getPublic(PublicFE.get()), ""); // no mapping. + EXPECT_FALSE(PI.isPrivate(PublicFE.get())); + + auto Private2FE = Processed.fileManager().getFile("private2.h"); + assert(Private2FE); + EXPECT_TRUE(PI.isPrivate(Private2FE.get())); } TEST_F(PragmaIncludeTest, IWYUExport) { diff --git a/clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr-cxx20.cpp b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr-cxx20.cpp --- a/clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr-cxx20.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr-cxx20.cpp @@ -1,9 +1,33 @@ // RUN: %check_clang_tidy -std=c++20 %s modernize-use-nullptr %t namespace std { +class strong_ordering; + +// Mock how STD defined unspecified parameters for the operators below. +struct _CmpUnspecifiedParam { + consteval + _CmpUnspecifiedParam(int _CmpUnspecifiedParam::*) noexcept {} +}; + struct strong_ordering { - int n; - constexpr operator int() const { return n; } + signed char value; + + friend constexpr bool operator==(strong_ordering v, + _CmpUnspecifiedParam) noexcept { + return v.value == 0; + } + friend constexpr bool operator<(strong_ordering v, + _CmpUnspecifiedParam) noexcept { + return v.value < 0; + } + friend constexpr bool operator>(strong_ordering v, + _CmpUnspecifiedParam) noexcept { + return v.value > 0; + } + friend constexpr bool operator>=(strong_ordering v, + _CmpUnspecifiedParam) noexcept { + return v.value >= 0; + } static const strong_ordering equal, greater, less; }; constexpr strong_ordering strong_ordering::equal = {0}; @@ -12,8 +36,10 @@ } // namespace std class A { + int a; public: auto operator<=>(const A &other) const = default; + // CHECK-FIXES: auto operator<=>(const A &other) const = default; }; void test_cxx_rewritten_binary_ops() { @@ -32,3 +58,14 @@ result = (a1 > ((a1 > (ptr == 0 ? a1 : a2)) ? a1 : a2)); // CHECK-FIXES: result = (a1 > ((a1 > (ptr == nullptr ? a1 : a2)) ? a1 : a2)); } + +template +struct P { + T1 x1; + T2 x2; + friend auto operator<=>(const P&, const P&) = default; + // CHECK-FIXES: friend auto operator<=>(const P&, const P&) = default; +}; + +bool foo(P x, P y) { return x < y; } +// CHECK-FIXES: bool foo(P x, P y) { return x < y; } diff --git a/clang/cmake/modules/ClangConfig.cmake.in b/clang/cmake/modules/ClangConfig.cmake.in --- a/clang/cmake/modules/ClangConfig.cmake.in +++ b/clang/cmake/modules/ClangConfig.cmake.in @@ -2,8 +2,8 @@ @CLANG_CONFIG_CODE@ -set(LLVM_VERSION ${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}.${LLVM_VERSION_PATCH}) -find_package(LLVM @LLVM_VERSION@ EXACT REQUIRED CONFIG +set(LLVM_VERSION @LLVM_VERSION_MAJOR@.@LLVM_VERSION_MINOR@.@LLVM_VERSION_PATCH@) +find_package(LLVM ${LLVM_VERSION} EXACT REQUIRED CONFIG HINTS "@CLANG_CONFIG_LLVM_CMAKE_DIR@") set(CLANG_EXPORTED_TARGETS "@CLANG_EXPORTS@") diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -827,6 +827,16 @@ ``scanbuild`` was also updated accordingly. Passing these flags will result in a hard error. +- Deprecate the ``consider-single-element-arrays-as-flexible-array-members`` + analyzer-config option. + This option will be still accepted, but a warning will be displayed. + This option will be rejected, thus turned into a hard error starting with + ``clang-17``. Use ``-fstrict-flex-array=`` instead if necessary. + +- Trailing array objects of structs with single elements will be considered + as flexible-array-members. Use ``-fstrict-flex-array=`` to define + what should be considered as flexible-array-member if needed. + .. _release-notes-sanitizers: Sanitizers diff --git a/clang/docs/tools/clang-formatted-files.txt b/clang/docs/tools/clang-formatted-files.txt --- a/clang/docs/tools/clang-formatted-files.txt +++ b/clang/docs/tools/clang-formatted-files.txt @@ -230,7 +230,6 @@ clang/include/clang/Serialization/ASTBitCodes.h clang/include/clang/Serialization/InMemoryModuleCache.h clang/include/clang/Serialization/SerializationDiagnostic.h -clang/include/clang/StaticAnalyzer/Checkers/LocalCheckers.h clang/include/clang/StaticAnalyzer/Core/CheckerRegistryData.h clang/include/clang/StaticAnalyzer/Core/BugReporter/CommonBugCategories.h clang/include/clang/StaticAnalyzer/Core/PathSensitive/DynamicCastInfo.h diff --git a/clang/include/clang/AST/Decl.h b/clang/include/clang/AST/Decl.h --- a/clang/include/clang/AST/Decl.h +++ b/clang/include/clang/AST/Decl.h @@ -542,6 +542,9 @@ class NamespaceDecl : public NamedDecl, public DeclContext, public Redeclarable { + + enum Flags : unsigned { F_Inline = 1 << 0, F_Nested = 1 << 1 }; + /// The starting location of the source range, pointing /// to either the namespace or the inline keyword. SourceLocation LocStart; @@ -553,11 +556,12 @@ /// this namespace or to the first namespace in the chain (the latter case /// only when this is not the first in the chain), along with a /// boolean value indicating whether this is an inline namespace. - llvm::PointerIntPair AnonOrFirstNamespaceAndInline; + llvm::PointerIntPair + AnonOrFirstNamespaceAndFlags; NamespaceDecl(ASTContext &C, DeclContext *DC, bool Inline, SourceLocation StartLoc, SourceLocation IdLoc, - IdentifierInfo *Id, NamespaceDecl *PrevDecl); + IdentifierInfo *Id, NamespaceDecl *PrevDecl, bool Nested); using redeclarable_base = Redeclarable; @@ -569,10 +573,10 @@ friend class ASTDeclReader; friend class ASTDeclWriter; - static NamespaceDecl *Create(ASTContext &C, DeclContext *DC, - bool Inline, SourceLocation StartLoc, - SourceLocation IdLoc, IdentifierInfo *Id, - NamespaceDecl *PrevDecl); + static NamespaceDecl *Create(ASTContext &C, DeclContext *DC, bool Inline, + SourceLocation StartLoc, SourceLocation IdLoc, + IdentifierInfo *Id, NamespaceDecl *PrevDecl, + bool Nested); static NamespaceDecl *CreateDeserialized(ASTContext &C, unsigned ID); @@ -601,12 +605,33 @@ /// Returns true if this is an inline namespace declaration. bool isInline() const { - return AnonOrFirstNamespaceAndInline.getInt(); + return AnonOrFirstNamespaceAndFlags.getInt() & F_Inline; } /// Set whether this is an inline namespace declaration. void setInline(bool Inline) { - AnonOrFirstNamespaceAndInline.setInt(Inline); + unsigned F = AnonOrFirstNamespaceAndFlags.getInt(); + if (Inline) + AnonOrFirstNamespaceAndFlags.setInt(F | F_Inline); + else + AnonOrFirstNamespaceAndFlags.setInt(F & ~F_Inline); + } + + /// Returns true if this is a nested namespace declaration. + /// \code + /// namespace outer::nested { } + /// \endcode + bool isNested() const { + return AnonOrFirstNamespaceAndFlags.getInt() & F_Nested; + } + + /// Set whether this is a nested namespace declaration. + void setNested(bool Nested) { + unsigned F = AnonOrFirstNamespaceAndFlags.getInt(); + if (Nested) + AnonOrFirstNamespaceAndFlags.setInt(F | F_Nested); + else + AnonOrFirstNamespaceAndFlags.setInt(F & ~F_Nested); } /// Returns true if the inline qualifier for \c Name is redundant. @@ -635,11 +660,11 @@ /// Retrieve the anonymous namespace nested inside this namespace, /// if any. NamespaceDecl *getAnonymousNamespace() const { - return getOriginalNamespace()->AnonOrFirstNamespaceAndInline.getPointer(); + return getOriginalNamespace()->AnonOrFirstNamespaceAndFlags.getPointer(); } void setAnonymousNamespace(NamespaceDecl *D) { - getOriginalNamespace()->AnonOrFirstNamespaceAndInline.setPointer(D); + getOriginalNamespace()->AnonOrFirstNamespaceAndFlags.setPointer(D); } /// Retrieves the canonical declaration of this namespace. diff --git a/clang/include/clang/Analysis/Analyses/PostOrderCFGView.h b/clang/include/clang/Analysis/Analyses/PostOrderCFGView.h --- a/clang/include/clang/Analysis/Analyses/PostOrderCFGView.h +++ b/clang/include/clang/Analysis/Analyses/PostOrderCFGView.h @@ -48,7 +48,7 @@ /// Set the bit associated with a particular CFGBlock. /// This is the important method for the SetType template parameter. - std::pair insert(const CFGBlock *Block) { + std::pair insert(const CFGBlock *Block) { // Note that insert() is called by po_iterator, which doesn't check to // make sure that Block is non-null. Moreover, the CFGBlock iterator will // occasionally hand out null pointers for pruned edges, so we catch those diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def b/clang/include/clang/Basic/BuiltinsAMDGPU.def --- a/clang/include/clang/Basic/BuiltinsAMDGPU.def +++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def @@ -261,6 +261,7 @@ // TODO: This is a no-op in wave32. Should the builtin require wavefrontsize64? TARGET_BUILTIN(__builtin_amdgcn_permlane64, "UiUi", "nc", "gfx11-insts") +TARGET_BUILTIN(__builtin_amdgcn_s_wait_event_export_ready, "v", "n", "gfx11-insts") //===----------------------------------------------------------------------===// // WMMA builtins. diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td --- a/clang/include/clang/Basic/DiagnosticDriverKinds.td +++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -458,6 +458,10 @@ "analyzer option '%0' is deprecated. This flag will be removed in %1, and " "passing this option will be an error.">, InGroup; +def warn_analyzer_deprecated_option_with_alternative : Warning< + "analyzer option '%0' is deprecated. This flag will be removed in %1, and " + "passing this option will be an error. Use '%2' instead.">, + InGroup; def warn_drv_needs_hvx : Warning< "%0 requires HVX, use -mhvx/-mhvx= to enable it">, diff --git a/clang/include/clang/Basic/DirectoryEntry.h b/clang/include/clang/Basic/DirectoryEntry.h --- a/clang/include/clang/Basic/DirectoryEntry.h +++ b/clang/include/clang/Basic/DirectoryEntry.h @@ -264,13 +264,14 @@ OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr & operator=(const OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr &) = default; - OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr(llvm::NoneType) {} + OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr(std::nullopt_t) {} OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr(DirectoryEntryRef Ref) : Optional(Ref) {} OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr(Optional MaybeRef) : Optional(MaybeRef) {} - OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr &operator=(llvm::NoneType) { + OptionalDirectoryEntryRefDegradesToDirectoryEntryPtr & + operator=(std::nullopt_t) { Optional::operator=(None); return *this; } diff --git a/clang/include/clang/Basic/FileEntry.h b/clang/include/clang/Basic/FileEntry.h --- a/clang/include/clang/Basic/FileEntry.h +++ b/clang/include/clang/Basic/FileEntry.h @@ -308,13 +308,13 @@ OptionalFileEntryRefDegradesToFileEntryPtr & operator=(const OptionalFileEntryRefDegradesToFileEntryPtr &) = default; - OptionalFileEntryRefDegradesToFileEntryPtr(llvm::NoneType) {} + OptionalFileEntryRefDegradesToFileEntryPtr(std::nullopt_t) {} OptionalFileEntryRefDegradesToFileEntryPtr(FileEntryRef Ref) : Optional(Ref) {} OptionalFileEntryRefDegradesToFileEntryPtr(Optional MaybeRef) : Optional(MaybeRef) {} - OptionalFileEntryRefDegradesToFileEntryPtr &operator=(llvm::NoneType) { + OptionalFileEntryRefDegradesToFileEntryPtr &operator=(std::nullopt_t) { Optional::operator=(None); return *this; } diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -6041,7 +6041,7 @@ SourceLocation IdentLoc, IdentifierInfo *Ident, SourceLocation LBrace, const ParsedAttributesView &AttrList, - UsingDirectiveDecl *&UsingDecl); + UsingDirectiveDecl *&UsingDecl, bool IsNested); void ActOnFinishNamespaceDef(Decl *Dcl, SourceLocation RBrace); NamespaceDecl *getStdNamespace() const; diff --git a/clang/include/clang/Sema/Template.h b/clang/include/clang/Sema/Template.h --- a/clang/include/clang/Sema/Template.h +++ b/clang/include/clang/Sema/Template.h @@ -222,7 +222,7 @@ TemplateArgumentLists.push_back({{}, Args}); } - void addOuterTemplateArguments(llvm::NoneType) { + void addOuterTemplateArguments(std::nullopt_t) { assert(!NumRetainedOuterLevels && "substituted args outside retained args?"); TemplateArgumentLists.push_back({}); diff --git a/clang/include/clang/Serialization/ASTBitCodes.h b/clang/include/clang/Serialization/ASTBitCodes.h --- a/clang/include/clang/Serialization/ASTBitCodes.h +++ b/clang/include/clang/Serialization/ASTBitCodes.h @@ -41,7 +41,7 @@ /// Version 4 of AST files also requires that the version control branch and /// revision match exactly, since there is no backward compatibility of /// AST files at this time. -const unsigned VERSION_MAJOR = 24; +const unsigned VERSION_MAJOR = 23; /// AST file minor version number supported by this version of /// Clang. diff --git a/clang/include/clang/StaticAnalyzer/Checkers/LocalCheckers.h b/clang/include/clang/StaticAnalyzer/Checkers/LocalCheckers.h deleted file mode 100644 --- a/clang/include/clang/StaticAnalyzer/Checkers/LocalCheckers.h +++ /dev/null @@ -1,27 +0,0 @@ -//==- LocalCheckers.h - Intra-Procedural+Flow-Sensitive Checkers -*- C++ -*-==// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// This file defines the interface to call a set of intra-procedural (local) -// checkers that use flow/path-sensitive analyses to find bugs. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CLANG_STATICANALYZER_CHECKERS_LOCALCHECKERS_H -#define LLVM_CLANG_STATICANALYZER_CHECKERS_LOCALCHECKERS_H - -namespace clang { -namespace ento { - -class ExprEngine; - -void RegisterCallInliner(ExprEngine &Eng); - -} // end namespace ento -} // end namespace clang - -#endif diff --git a/clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def b/clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def --- a/clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def +++ b/clang/include/clang/StaticAnalyzer/Core/AnalyzerOptions.def @@ -331,8 +331,9 @@ "consider-single-element-arrays-as-flexible-array-members", "Consider single element arrays as flexible array member candidates. " "This will prevent the analyzer from assuming that a single element array " - "holds a single element.", - false) + "holds a single element. [DEPRECATED, removing in clang-17; " + "use '-fstrict-flex-arrays=' instead]", + true) ANALYZER_OPTION( bool, ShouldAssumeControlledEnvironment, "assume-controlled-environment", diff --git a/clang/include/clang/Tooling/Inclusions/HeaderAnalysis.h b/clang/include/clang/Tooling/Inclusions/HeaderAnalysis.h --- a/clang/include/clang/Tooling/Inclusions/HeaderAnalysis.h +++ b/clang/include/clang/Tooling/Inclusions/HeaderAnalysis.h @@ -9,6 +9,8 @@ #ifndef LLVM_CLANG_TOOLING_INCLUSIONS_HEADER_ANALYSIS_H #define LLVM_CLANG_TOOLING_INCLUSIONS_HEADER_ANALYSIS_H +#include "llvm/ADT/Optional.h" +#include "llvm/ADT/StringRef.h" namespace clang { class FileEntry; class SourceManager; @@ -27,6 +29,13 @@ bool isSelfContainedHeader(const FileEntry *FE, const SourceManager &SM, HeaderSearch &HeaderInfo); +/// If Text begins an Include-What-You-Use directive, returns it. +/// Given "// IWYU pragma: keep", returns "keep". +/// Input is a null-terminated char* as provided by SM.getCharacterData(). +/// (This should not be StringRef as we do *not* want to scan for its length). +/// For multi-line comments, we return only the first line. +llvm::Optional parseIWYUPragma(const char *Text); + } // namespace tooling } // namespace clang diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp --- a/clang/lib/AST/ASTContext.cpp +++ b/clang/lib/AST/ASTContext.cpp @@ -8765,9 +8765,9 @@ // namespace std { struct __va_list { auto *NS = NamespaceDecl::Create( const_cast(*Context), Context->getTranslationUnitDecl(), - /*Inline*/ false, SourceLocation(), SourceLocation(), + /*Inline=*/false, SourceLocation(), SourceLocation(), &Context->Idents.get("std"), - /*PrevDecl*/ nullptr); + /*PrevDecl=*/nullptr, /*Nested=*/false); NS->setImplicit(); VaListTagDecl->setDeclContext(NS); } @@ -8954,9 +8954,9 @@ NamespaceDecl *NS; NS = NamespaceDecl::Create(const_cast(*Context), Context->getTranslationUnitDecl(), - /*Inline*/false, SourceLocation(), + /*Inline=*/false, SourceLocation(), SourceLocation(), &Context->Idents.get("std"), - /*PrevDecl*/ nullptr); + /*PrevDecl=*/nullptr, /*Nested=*/false); NS->setImplicit(); VaListDecl->setDeclContext(NS); } @@ -12277,14 +12277,14 @@ } template , bool> = true> -T *getCommonDecl(T *X, T *Y) { +static T *getCommonDecl(T *X, T *Y) { return cast_or_null( getCommonDecl(const_cast(cast_or_null(X)), const_cast(cast_or_null(Y)))); } template , bool> = true> -T *getCommonDeclChecked(T *X, T *Y) { +static T *getCommonDeclChecked(T *X, T *Y) { return cast(getCommonDecl(const_cast(cast(X)), const_cast(cast(Y)))); } diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp --- a/clang/lib/AST/ASTImporter.cpp +++ b/clang/lib/AST/ASTImporter.cpp @@ -2412,10 +2412,10 @@ // Create the "to" namespace, if needed. NamespaceDecl *ToNamespace = MergeWithNamespace; if (!ToNamespace) { - if (GetImportedOrCreateDecl( - ToNamespace, D, Importer.getToContext(), DC, D->isInline(), - *BeginLocOrErr, Loc, Name.getAsIdentifierInfo(), - /*PrevDecl=*/nullptr)) + if (GetImportedOrCreateDecl(ToNamespace, D, Importer.getToContext(), DC, + D->isInline(), *BeginLocOrErr, Loc, + Name.getAsIdentifierInfo(), + /*PrevDecl=*/nullptr, D->isNested())) return ToNamespace; ToNamespace->setRBraceLoc(*RBraceLocOrErr); ToNamespace->setLexicalDeclContext(LexicalDC); diff --git a/clang/lib/AST/DeclCXX.cpp b/clang/lib/AST/DeclCXX.cpp --- a/clang/lib/AST/DeclCXX.cpp +++ b/clang/lib/AST/DeclCXX.cpp @@ -2880,41 +2880,47 @@ NamespaceDecl::NamespaceDecl(ASTContext &C, DeclContext *DC, bool Inline, SourceLocation StartLoc, SourceLocation IdLoc, - IdentifierInfo *Id, NamespaceDecl *PrevDecl) + IdentifierInfo *Id, NamespaceDecl *PrevDecl, + bool Nested) : NamedDecl(Namespace, DC, IdLoc, Id), DeclContext(Namespace), - redeclarable_base(C), LocStart(StartLoc), - AnonOrFirstNamespaceAndInline(nullptr, Inline) { + redeclarable_base(C), LocStart(StartLoc) { + unsigned Flags = 0; + if (Inline) + Flags |= F_Inline; + if (Nested) + Flags |= F_Nested; + AnonOrFirstNamespaceAndFlags = {nullptr, Flags}; setPreviousDecl(PrevDecl); if (PrevDecl) - AnonOrFirstNamespaceAndInline.setPointer(PrevDecl->getOriginalNamespace()); + AnonOrFirstNamespaceAndFlags.setPointer(PrevDecl->getOriginalNamespace()); } NamespaceDecl *NamespaceDecl::Create(ASTContext &C, DeclContext *DC, bool Inline, SourceLocation StartLoc, SourceLocation IdLoc, IdentifierInfo *Id, - NamespaceDecl *PrevDecl) { - return new (C, DC) NamespaceDecl(C, DC, Inline, StartLoc, IdLoc, Id, - PrevDecl); + NamespaceDecl *PrevDecl, bool Nested) { + return new (C, DC) + NamespaceDecl(C, DC, Inline, StartLoc, IdLoc, Id, PrevDecl, Nested); } NamespaceDecl *NamespaceDecl::CreateDeserialized(ASTContext &C, unsigned ID) { return new (C, ID) NamespaceDecl(C, nullptr, false, SourceLocation(), - SourceLocation(), nullptr, nullptr); + SourceLocation(), nullptr, nullptr, false); } NamespaceDecl *NamespaceDecl::getOriginalNamespace() { if (isFirstDecl()) return this; - return AnonOrFirstNamespaceAndInline.getPointer(); + return AnonOrFirstNamespaceAndFlags.getPointer(); } const NamespaceDecl *NamespaceDecl::getOriginalNamespace() const { if (isFirstDecl()) return this; - return AnonOrFirstNamespaceAndInline.getPointer(); + return AnonOrFirstNamespaceAndFlags.getPointer(); } bool NamespaceDecl::isOriginalNamespace() const { return isFirstDecl(); } diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp --- a/clang/lib/AST/ExprConstant.cpp +++ b/clang/lib/AST/ExprConstant.cpp @@ -7044,14 +7044,14 @@ // Emit an unsupported bit_cast type error. Sema refuses to build a bit_cast // with an invalid type, so anything left is a deficiency on our part (FIXME). // Ideally this will be unreachable. - llvm::NoneType unsupportedType(QualType Ty) { + std::nullopt_t unsupportedType(QualType Ty) { Info.FFDiag(BCE->getBeginLoc(), diag::note_constexpr_bit_cast_unsupported_type) << Ty; return None; } - llvm::NoneType unrepresentableValue(QualType Ty, const APSInt &Val) { + std::nullopt_t unrepresentableValue(QualType Ty, const APSInt &Val) { Info.FFDiag(BCE->getBeginLoc(), diag::note_constexpr_bit_cast_unrepresentable_value) << Ty << toString(Val, /*Radix=*/10); diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp --- a/clang/lib/AST/ItaniumMangle.cpp +++ b/clang/lib/AST/ItaniumMangle.cpp @@ -602,9 +602,9 @@ if (!StdNamespace) { StdNamespace = NamespaceDecl::Create( getASTContext(), getASTContext().getTranslationUnitDecl(), - /*Inline*/ false, SourceLocation(), SourceLocation(), + /*Inline=*/false, SourceLocation(), SourceLocation(), &getASTContext().Idents.get("std"), - /*PrevDecl*/ nullptr); + /*PrevDecl=*/nullptr, /*Nested=*/false); StdNamespace->setImplicit(); } return StdNamespace; diff --git a/clang/lib/AST/JSONNodeDumper.cpp b/clang/lib/AST/JSONNodeDumper.cpp --- a/clang/lib/AST/JSONNodeDumper.cpp +++ b/clang/lib/AST/JSONNodeDumper.cpp @@ -794,6 +794,7 @@ void JSONNodeDumper::VisitNamespaceDecl(const NamespaceDecl *ND) { VisitNamedDecl(ND); attributeOnlyIfTrue("isInline", ND->isInline()); + attributeOnlyIfTrue("isNested", ND->isNested()); if (!ND->isOriginalNamespace()) JOS.attribute("originalNamespace", createBareDeclRef(ND->getOriginalNamespace())); diff --git a/clang/lib/AST/TextNodeDumper.cpp b/clang/lib/AST/TextNodeDumper.cpp --- a/clang/lib/AST/TextNodeDumper.cpp +++ b/clang/lib/AST/TextNodeDumper.cpp @@ -1931,6 +1931,8 @@ dumpName(D); if (D->isInline()) OS << " inline"; + if (D->isNested()) + OS << " nested"; if (!D->isOriginalNamespace()) dumpDeclRef(D->getOriginalNamespace(), "original"); } diff --git a/clang/lib/Basic/Targets/AArch64.h b/clang/lib/Basic/Targets/AArch64.h --- a/clang/lib/Basic/Targets/AArch64.h +++ b/clang/lib/Basic/Targets/AArch64.h @@ -16,7 +16,6 @@ #include "OSTargets.h" #include "clang/Basic/TargetBuiltins.h" #include "llvm/Support/AArch64TargetParser.h" -#include "llvm/Support/TargetParser.h" namespace clang { namespace targets { diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -18,6 +18,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/Support/AArch64TargetParser.h" +#include "llvm/Support/ARMTargetParserCommon.h" using namespace clang; using namespace clang::targets; diff --git a/clang/lib/Basic/Targets/ARM.h b/clang/lib/Basic/Targets/ARM.h --- a/clang/lib/Basic/Targets/ARM.h +++ b/clang/lib/Basic/Targets/ARM.h @@ -17,9 +17,9 @@ #include "clang/Basic/TargetInfo.h" #include "clang/Basic/TargetOptions.h" #include "llvm/ADT/Triple.h" -#include "llvm/Support/Compiler.h" #include "llvm/Support/ARMTargetParser.h" -#include "llvm/Support/TargetParser.h" +#include "llvm/Support/ARMTargetParserCommon.h" +#include "llvm/Support/Compiler.h" namespace clang { namespace targets { diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -851,9 +851,10 @@ PrintPassOptions PrintPassOpts; PrintPassOpts.Indent = DebugPassStructure; PrintPassOpts.SkipAnalyses = DebugPassStructure; - StandardInstrumentations SI(CodeGenOpts.DebugPassManager || - DebugPassStructure, - /*VerifyEach*/ false, PrintPassOpts); + StandardInstrumentations SI( + TheModule->getContext(), + (CodeGenOpts.DebugPassManager || DebugPassStructure), + /*VerifyEach*/ false, PrintPassOpts); SI.registerCallbacks(PIC, &FAM); PassBuilder PB(TM.get(), PTO, PGOOpt, &PIC); diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.h b/clang/lib/CodeGen/CGOpenMPRuntime.h --- a/clang/lib/CodeGen/CGOpenMPRuntime.h +++ b/clang/lib/CodeGen/CGOpenMPRuntime.h @@ -306,15 +306,10 @@ protected: CodeGenModule &CGM; - StringRef FirstSeparator, Separator; /// An OpenMP-IR-Builder instance. llvm::OpenMPIRBuilder OMPBuilder; - /// Constructor allowing to redefine the name separator for the variables. - explicit CGOpenMPRuntime(CodeGenModule &CGM, StringRef FirstSeparator, - StringRef Separator); - /// Helper to emit outlined function for 'target' directive. /// \param D Directive to emit. /// \param ParentName Name of the function that encloses the target region. @@ -691,8 +686,7 @@ Address DependenciesArray); public: - explicit CGOpenMPRuntime(CodeGenModule &CGM) - : CGOpenMPRuntime(CGM, ".", ".") {} + explicit CGOpenMPRuntime(CodeGenModule &CGM); virtual ~CGOpenMPRuntime() {} virtual void clear(); diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -1057,14 +1057,11 @@ return Field; } -CGOpenMPRuntime::CGOpenMPRuntime(CodeGenModule &CGM, StringRef FirstSeparator, - StringRef Separator) - : CGM(CGM), FirstSeparator(FirstSeparator), Separator(Separator), - OMPBuilder(CGM.getModule()), OffloadEntriesInfoManager() { +CGOpenMPRuntime::CGOpenMPRuntime(CodeGenModule &CGM) + : CGM(CGM), OMPBuilder(CGM.getModule()), OffloadEntriesInfoManager() { KmpCriticalNameTy = llvm::ArrayType::get(CGM.Int32Ty, /*NumElements*/ 8); llvm::OpenMPIRBuilderConfig Config(CGM.getLangOpts().OpenMPIsDevice, false, hasRequiresUnifiedSharedMemory()); - // Initialize Types used in OpenMPIRBuilder from OMPKinds.def OMPBuilder.initialize(); OMPBuilder.setConfig(Config); @@ -1088,14 +1085,7 @@ } std::string CGOpenMPRuntime::getName(ArrayRef Parts) const { - SmallString<128> Buffer; - llvm::raw_svector_ostream OS(Buffer); - StringRef Sep = FirstSeparator; - for (StringRef Part : Parts) { - OS << Sep << Part; - Sep = Separator; - } - return std::string(OS.str()); + return OMPBuilder.createPlatformSpecificName(Parts); } static llvm::Function * diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp --- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp @@ -889,7 +889,7 @@ } CGOpenMPRuntimeGPU::CGOpenMPRuntimeGPU(CodeGenModule &CGM) - : CGOpenMPRuntime(CGM, "_", "$") { + : CGOpenMPRuntime(CGM) { llvm::OpenMPIRBuilderConfig Config(CGM.getLangOpts().OpenMPIsDevice, true, hasRequiresUnifiedSharedMemory()); OMPBuilder.setConfig(Config); diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -4002,7 +4002,8 @@ // (If function is requested for a definition, we always need to create a new // function, not just return a bitcast.) if (!IsForDefinition) - return llvm::ConstantExpr::getBitCast(Entry, Ty->getPointerTo()); + return llvm::ConstantExpr::getBitCast( + Entry, Ty->getPointerTo(Entry->getAddressSpace())); } // This function doesn't have a complete type (for example, the return diff --git a/clang/lib/CodeGen/ItaniumCXXABI.cpp b/clang/lib/CodeGen/ItaniumCXXABI.cpp --- a/clang/lib/CodeGen/ItaniumCXXABI.cpp +++ b/clang/lib/CodeGen/ItaniumCXXABI.cpp @@ -2385,13 +2385,15 @@ } // Create the guard variable with a zero-initializer. - // Just absorb linkage and visibility from the guarded variable. + // Just absorb linkage, visibility and dll storage class from the guarded + // variable. guard = new llvm::GlobalVariable(CGM.getModule(), guardTy, false, var->getLinkage(), llvm::ConstantInt::get(guardTy, 0), guardName.str()); guard->setDSOLocal(var->isDSOLocal()); guard->setVisibility(var->getVisibility()); + guard->setDLLStorageClass(var->getDLLStorageClass()); // If the variable is thread-local, so is its guard variable. guard->setThreadLocalMode(var->getThreadLocalMode()); guard->setAlignment(guardAlignment.getAsAlign()); diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -44,6 +44,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/Config/llvm-config.h" #include "llvm/Option/ArgList.h" +#include "llvm/Support/ARMTargetParserCommon.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Compression.h" @@ -51,7 +52,6 @@ #include "llvm/Support/Host.h" #include "llvm/Support/Path.h" #include "llvm/Support/Process.h" -#include "llvm/Support/TargetParser.h" #include "llvm/Support/YAMLParser.h" #include diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -2837,7 +2837,7 @@ if (!Current.is(TT_StartOfName) || Current.NestingLevel != 0) return false; for (; Next; Next = Next->Next) { - if (Next->is(TT_TemplateOpener)) { + if (Next->is(TT_TemplateOpener) && Next->MatchingParen) { Next = Next->MatchingParen; } else if (Next->is(tok::coloncolon)) { Next = Next->Next; diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -43,12 +43,6 @@ // getNextToken(). virtual FormatToken *peekNextToken() = 0; - // Returns the token that would be returned after the next N calls to - // getNextToken(). N needs to be greater than zero, and small enough that - // there are still tokens. Check for tok::eof with N-1 before calling it with - // N. - virtual FormatToken *peekNextToken(int N) = 0; - // Returns whether we are at the end of the file. // This can be different from whether getNextToken() returned an eof token // when the FormatTokenSource is a view on a part of the token stream. @@ -64,6 +58,39 @@ namespace { +void printLine(llvm::raw_ostream &OS, const UnwrappedLine &Line, + StringRef Prefix = "", bool PrintText = false) { + OS << Prefix << "Line(" << Line.Level << ", FSC=" << Line.FirstStartColumn + << ")" << (Line.InPPDirective ? " MACRO" : "") << ": "; + bool NewLine = false; + for (std::list::const_iterator I = Line.Tokens.begin(), + E = Line.Tokens.end(); + I != E; ++I) { + if (NewLine) { + OS << Prefix; + NewLine = false; + } + OS << I->Tok->Tok.getName() << "[" + << "T=" << (unsigned)I->Tok->getType() + << ", OC=" << I->Tok->OriginalColumn << ", \"" << I->Tok->TokenText + << "\"] "; + for (SmallVectorImpl::const_iterator + CI = I->Children.begin(), + CE = I->Children.end(); + CI != CE; ++CI) { + OS << "\n"; + printLine(OS, *CI, (Prefix + " ").str()); + NewLine = true; + } + } + if (!NewLine) + OS << "\n"; +} + +LLVM_ATTRIBUTE_UNUSED static void printDebugInfo(const UnwrappedLine &Line) { + printLine(llvm::dbgs(), Line); +} + class ScopedDeclarationState { public: ScopedDeclarationState(UnwrappedLine &Line, llvm::BitVector &Stack, @@ -148,13 +175,6 @@ return PreviousTokenSource->peekNextToken(); } - FormatToken *peekNextToken(int N) override { - assert(N > 0); - if (eof()) - return &FakeEOF; - return PreviousTokenSource->peekNextToken(N); - } - bool isEOF() override { return PreviousTokenSource->isEOF(); } unsigned getPosition() override { return PreviousTokenSource->getPosition(); } @@ -277,16 +297,6 @@ return Tokens[Next]; } - FormatToken *peekNextToken(int N) override { - assert(N > 0); - int Next = Position + N; - LLVM_DEBUG({ - llvm::dbgs() << "Peeking (+" << (N - 1) << ") "; - dbgToken(Next); - }); - return Tokens[Next]; - } - bool isEOF() override { return Tokens[Position]->is(tok::eof); } unsigned getPosition() override { @@ -3356,37 +3366,41 @@ // So we want basically to check for TYPE NAME, but TYPE can contain all kinds // of stuff: typename, const, *, &, &&, ::, identifiers. - int NextTokenOffset = 1; - auto NextToken = Tokens->peekNextToken(NextTokenOffset); - auto PeekNext = [&NextTokenOffset, &NextToken, this] { - ++NextTokenOffset; - NextToken = Tokens->peekNextToken(NextTokenOffset); + unsigned StoredPosition = Tokens->getPosition(); + FormatToken *NextToken = Tokens->getNextToken(); + int Lookahead = 0; + auto PeekNext = [&Lookahead, &NextToken, this] { + ++Lookahead; + NextToken = Tokens->getNextToken(); }; bool FoundType = false; bool LastWasColonColon = false; int OpenAngles = 0; - for (; NextTokenOffset < 50; PeekNext()) { + for (; Lookahead < 50; PeekNext()) { switch (NextToken->Tok.getKind()) { case tok::kw_volatile: case tok::kw_const: case tok::comma: + FormatTok = Tokens->setPosition(StoredPosition); parseRequiresExpression(RequiresToken); return false; case tok::r_paren: case tok::pipepipe: + FormatTok = Tokens->setPosition(StoredPosition); parseRequiresClause(RequiresToken); return true; case tok::eof: // Break out of the loop. - NextTokenOffset = 50; + Lookahead = 50; break; case tok::coloncolon: LastWasColonColon = true; break; case tok::identifier: if (FoundType && !LastWasColonColon && OpenAngles == 0) { + FormatTok = Tokens->setPosition(StoredPosition); parseRequiresExpression(RequiresToken); return false; } @@ -3401,14 +3415,15 @@ break; default: if (NextToken->isSimpleTypeSpecifier()) { + FormatTok = Tokens->setPosition(StoredPosition); parseRequiresExpression(RequiresToken); return false; } break; } } - // This seems to be a complicated expression, just assume it's a clause. + FormatTok = Tokens->setPosition(StoredPosition); parseRequiresClause(RequiresToken); return true; } @@ -4314,23 +4329,6 @@ Line->Level = OrigLevel; } -LLVM_ATTRIBUTE_UNUSED static void printDebugInfo(const UnwrappedLine &Line, - StringRef Prefix = "") { - llvm::dbgs() << Prefix << "Line(" << Line.Level - << ", FSC=" << Line.FirstStartColumn << ")" - << (Line.InPPDirective ? " MACRO" : "") << ": "; - for (const auto &Node : Line.Tokens) { - llvm::dbgs() << Node.Tok->Tok.getName() << "[" - << "T=" << static_cast(Node.Tok->getType()) - << ", OC=" << Node.Tok->OriginalColumn << "] "; - } - for (const auto &Node : Line.Tokens) - for (const auto &ChildNode : Node.Children) - printDebugInfo(ChildNode, "\nChild: "); - - llvm::dbgs() << "\n"; -} - void UnwrappedLineParser::addUnwrappedLine(LineLevel AdjustLevel) { if (Line->Tokens.empty()) return; diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp --- a/clang/lib/Frontend/CompilerInvocation.cpp +++ b/clang/lib/Frontend/CompilerInvocation.cpp @@ -1018,6 +1018,15 @@ A->claim(); Opts.Config[key] = std::string(val); + + // FIXME: Remove this hunk after clang-17 released. + constexpr auto SingleFAM = + "consider-single-element-arrays-as-flexible-array-members"; + if (key == SingleFAM) { + Diags.Report(diag::warn_analyzer_deprecated_option_with_alternative) + << SingleFAM << "clang-17" + << "-fstrict-flex-arrays="; + } } } diff --git a/clang/lib/Headers/amxfp16intrin.h b/clang/lib/Headers/amxfp16intrin.h --- a/clang/lib/Headers/amxfp16intrin.h +++ b/clang/lib/Headers/amxfp16intrin.h @@ -20,7 +20,7 @@ /// floating-point elements with elements in \a dst, and store the 32-bit /// result back to tile \a dst. /// -/// \headerfile +/// \headerfile /// /// \code /// void _tile_dpfp16ps (__tile dst, __tile a, __tile b) diff --git a/clang/lib/Lex/HeaderSearch.cpp b/clang/lib/Lex/HeaderSearch.cpp --- a/clang/lib/Lex/HeaderSearch.cpp +++ b/clang/lib/Lex/HeaderSearch.cpp @@ -1928,32 +1928,28 @@ llvm::StringRef File, llvm::StringRef WorkingDir, llvm::StringRef MainFile, bool *IsSystem) { using namespace llvm::sys; + + llvm::SmallString<32> FilePath = File; + // remove_dots switches to backslashes on windows as a side-effect! + // We always want to suggest forward slashes for includes. + // (not remove_dots(..., posix) as that misparses windows paths). + path::remove_dots(FilePath, /*remove_dot_dot=*/true); + path::native(FilePath, path::Style::posix); + File = FilePath; unsigned BestPrefixLength = 0; // Checks whether `Dir` is a strict path prefix of `File`. If so and that's // the longest prefix we've seen so for it, returns true and updates the // `BestPrefixLength` accordingly. - auto CheckDir = [&](llvm::StringRef Dir) -> bool { - llvm::SmallString<32> DirPath(Dir.begin(), Dir.end()); + auto CheckDir = [&](llvm::SmallString<32> Dir) -> bool { if (!WorkingDir.empty() && !path::is_absolute(Dir)) - fs::make_absolute(WorkingDir, DirPath); - path::remove_dots(DirPath, /*remove_dot_dot=*/true); - Dir = DirPath; + fs::make_absolute(WorkingDir, Dir); + path::remove_dots(Dir, /*remove_dot_dot=*/true); for (auto NI = path::begin(File), NE = path::end(File), DI = path::begin(Dir), DE = path::end(Dir); - /*termination condition in loop*/; ++NI, ++DI) { - // '.' components in File are ignored. - while (NI != NE && *NI == ".") - ++NI; - if (NI == NE) - break; - - // '.' components in Dir are ignored. - while (DI != DE && *DI == ".") - ++DI; + NI != NE; ++NI, ++DI) { if (DI == DE) { - // Dir is a prefix of File, up to '.' components and choice of path - // separators. + // Dir is a prefix of File, up to choice of path separators. unsigned PrefixLength = NI - path::begin(File); if (PrefixLength > BestPrefixLength) { BestPrefixLength = PrefixLength; diff --git a/clang/lib/Parse/ParseDeclCXX.cpp b/clang/lib/Parse/ParseDeclCXX.cpp --- a/clang/lib/Parse/ParseDeclCXX.cpp +++ b/clang/lib/Parse/ParseDeclCXX.cpp @@ -227,7 +227,7 @@ UsingDirectiveDecl *ImplicitUsingDirectiveDecl = nullptr; Decl *NamespcDecl = Actions.ActOnStartNamespaceDef( getCurScope(), InlineLoc, NamespaceLoc, IdentLoc, Ident, - T.getOpenLocation(), attrs, ImplicitUsingDirectiveDecl); + T.getOpenLocation(), attrs, ImplicitUsingDirectiveDecl, false); PrettyDeclStackTraceEntry CrashInfo(Actions.Context, NamespcDecl, NamespaceLoc, "parsing namespace"); @@ -275,7 +275,7 @@ Decl *NamespcDecl = Actions.ActOnStartNamespaceDef( getCurScope(), InnerNSs[index].InlineLoc, InnerNSs[index].NamespaceLoc, InnerNSs[index].IdentLoc, InnerNSs[index].Ident, - Tracker.getOpenLocation(), attrs, ImplicitUsingDirectiveDecl); + Tracker.getOpenLocation(), attrs, ImplicitUsingDirectiveDecl, true); assert(!ImplicitUsingDirectiveDecl && "nested namespace definition cannot define anonymous namespace"); diff --git a/clang/lib/Sema/HLSLExternalSemaSource.cpp b/clang/lib/Sema/HLSLExternalSemaSource.cpp --- a/clang/lib/Sema/HLSLExternalSemaSource.cpp +++ b/clang/lib/Sema/HLSLExternalSemaSource.cpp @@ -385,9 +385,9 @@ NamespaceDecl *PrevDecl = nullptr; if (S.LookupQualifiedName(Result, AST.getTranslationUnitDecl())) PrevDecl = Result.getAsSingle(); - HLSLNamespace = NamespaceDecl::Create(AST, AST.getTranslationUnitDecl(), - false, SourceLocation(), - SourceLocation(), &HLSL, PrevDecl); + HLSLNamespace = NamespaceDecl::Create( + AST, AST.getTranslationUnitDecl(), /*Inline=*/false, SourceLocation(), + SourceLocation(), &HLSL, PrevDecl, /*Nested=*/false); HLSLNamespace->setImplicit(true); HLSLNamespace->setHasExternalLexicalStorage(); AST.getTranslationUnitDecl()->addDecl(HLSLNamespace); diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp --- a/clang/lib/Sema/SemaDeclCXX.cpp +++ b/clang/lib/Sema/SemaDeclCXX.cpp @@ -11171,10 +11171,13 @@ /// ActOnStartNamespaceDef - This is called at the start of a namespace /// definition. -Decl *Sema::ActOnStartNamespaceDef( - Scope *NamespcScope, SourceLocation InlineLoc, SourceLocation NamespaceLoc, - SourceLocation IdentLoc, IdentifierInfo *II, SourceLocation LBrace, - const ParsedAttributesView &AttrList, UsingDirectiveDecl *&UD) { +Decl *Sema::ActOnStartNamespaceDef(Scope *NamespcScope, + SourceLocation InlineLoc, + SourceLocation NamespaceLoc, + SourceLocation IdentLoc, IdentifierInfo *II, + SourceLocation LBrace, + const ParsedAttributesView &AttrList, + UsingDirectiveDecl *&UD, bool IsNested) { SourceLocation StartLoc = InlineLoc.isValid() ? InlineLoc : NamespaceLoc; // For anonymous namespace, take the location of the left brace. SourceLocation Loc = II ? IdentLoc : LBrace; @@ -11244,8 +11247,8 @@ &IsInline, PrevNS); } - NamespaceDecl *Namespc = NamespaceDecl::Create(Context, CurContext, IsInline, - StartLoc, Loc, II, PrevNS); + NamespaceDecl *Namespc = NamespaceDecl::Create( + Context, CurContext, IsInline, StartLoc, Loc, II, PrevNS, IsNested); if (IsInvalid) Namespc->setInvalidDecl(); @@ -11506,12 +11509,11 @@ NamespaceDecl *Sema::getOrCreateStdNamespace() { if (!StdNamespace) { // The "std" namespace has not yet been defined, so build one implicitly. - StdNamespace = NamespaceDecl::Create(Context, - Context.getTranslationUnitDecl(), - /*Inline=*/false, - SourceLocation(), SourceLocation(), - &PP.getIdentifierTable().get("std"), - /*PrevDecl=*/nullptr); + StdNamespace = NamespaceDecl::Create( + Context, Context.getTranslationUnitDecl(), + /*Inline=*/false, SourceLocation(), SourceLocation(), + &PP.getIdentifierTable().get("std"), + /*PrevDecl=*/nullptr, /*Nested=*/false); getStdNamespace()->setImplicit(true); } diff --git a/clang/lib/Sema/SemaDeclObjC.cpp b/clang/lib/Sema/SemaDeclObjC.cpp --- a/clang/lib/Sema/SemaDeclObjC.cpp +++ b/clang/lib/Sema/SemaDeclObjC.cpp @@ -4438,6 +4438,11 @@ ResultTypeCompatibilityKind RTC) { if (!ObjCMethod) return; + auto IsMethodInCurrentClass = [CurrentClass](const ObjCMethodDecl *M) { + // Checking canonical decl works across modules. + return M->getClassInterface()->getCanonicalDecl() == + CurrentClass->getCanonicalDecl(); + }; // Search for overridden methods and merge information down from them. OverrideSearch overrides(*this, ObjCMethod); // Keep track if the method overrides any method in the class's base classes, @@ -4449,8 +4454,7 @@ for (ObjCMethodDecl *overridden : overrides) { if (!hasOverriddenMethodsInBaseOrProtocol) { if (isa(overridden->getDeclContext()) || - CurrentClass != overridden->getClassInterface() || - overridden->isOverriding()) { + !IsMethodInCurrentClass(overridden) || overridden->isOverriding()) { CheckObjCMethodDirectOverrides(ObjCMethod, overridden); hasOverriddenMethodsInBaseOrProtocol = true; } else if (isa(ObjCMethod->getDeclContext())) { @@ -4475,7 +4479,7 @@ OverrideSearch overrides(*this, overridden); for (ObjCMethodDecl *SuperOverridden : overrides) { if (isa(SuperOverridden->getDeclContext()) || - CurrentClass != SuperOverridden->getClassInterface()) { + !IsMethodInCurrentClass(SuperOverridden)) { CheckObjCMethodDirectOverrides(ObjCMethod, SuperOverridden); hasOverriddenMethodsInBaseOrProtocol = true; overridden->setOverriding(true); diff --git a/clang/lib/Sema/SemaFixItUtils.cpp b/clang/lib/Sema/SemaFixItUtils.cpp --- a/clang/lib/Sema/SemaFixItUtils.cpp +++ b/clang/lib/Sema/SemaFixItUtils.cpp @@ -124,7 +124,7 @@ // Check if the pointer to the argument needs to be passed: // (type -> type *) or (type & -> type *). - if (isa(ToQTy)) { + if (const auto *ToPtrTy = dyn_cast(ToQTy)) { bool CanConvert = false; OverloadFixItKind FixKind = OFIK_TakeAddress; @@ -132,6 +132,10 @@ if (!Expr->isLValue() || Expr->getObjectKind() != OK_Ordinary) return false; + // Do no take address of const pointer to get void* + if (isa(FromQTy) && ToPtrTy->isVoidPointerType()) + return false; + CanConvert = CompareTypes(S.Context.getPointerType(FromQTy), ToQTy, S, Begin, VK_PRValue); if (CanConvert) { diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp --- a/clang/lib/Serialization/ASTReader.cpp +++ b/clang/lib/Serialization/ASTReader.cpp @@ -1452,19 +1452,25 @@ unsigned RecCode = MaybeRecCode.get(); if (RecCode == SM_SLOC_BUFFER_BLOB_COMPRESSED) { - if (!llvm::compression::zlib::isAvailable()) { - Error("zlib is not available"); + // Inspect the first byte to differentiate zlib (\x78) and zstd + // (little-endian 0xFD2FB528). + const llvm::compression::Format F = + Blob.size() > 0 && Blob.data()[0] == 0x78 + ? llvm::compression::Format::Zlib + : llvm::compression::Format::Zstd; + if (const char *Reason = llvm::compression::getReasonIfUnsupported(F)) { + Error(Reason); return nullptr; } - SmallVector Uncompressed; - if (llvm::Error E = llvm::compression::zlib::decompress( - llvm::arrayRefFromStringRef(Blob), Uncompressed, Record[0])) { + SmallVector Decompressed; + if (llvm::Error E = llvm::compression::decompress( + F, llvm::arrayRefFromStringRef(Blob), Decompressed, Record[0])) { Error("could not decompress embedded file contents: " + llvm::toString(std::move(E))); return nullptr; } return llvm::MemoryBuffer::getMemBufferCopy( - llvm::toStringRef(Uncompressed), Name); + llvm::toStringRef(Decompressed), Name); } else if (RecCode == SM_SLOC_BUFFER_BLOB) { return llvm::MemoryBuffer::getMemBuffer(Blob.drop_back(1), Name, true); } else { @@ -6355,15 +6361,17 @@ while (NumLocations--) { assert(Idx < Record.size() && "Invalid data, missing pragma diagnostic states"); - FileID FID = ReadFileID(F, Record, Idx); - assert(FID.isValid() && "invalid FileID for transition"); + SourceLocation Loc = ReadSourceLocation(F, Record[Idx++]); + auto IDAndOffset = SourceMgr.getDecomposedLoc(Loc); + assert(IDAndOffset.first.isValid() && "invalid FileID for transition"); + assert(IDAndOffset.second == 0 && "not a start location for a FileID"); unsigned Transitions = Record[Idx++]; // Note that we don't need to set up Parent/ParentOffset here, because // we won't be changing the diagnostic state within imported FileIDs // (other than perhaps appending to the main source file, which has no // parent). - auto &F = Diag.DiagStatesByLoc.Files[FID]; + auto &F = Diag.DiagStatesByLoc.Files[IDAndOffset.first]; F.StateTransitions.reserve(F.StateTransitions.size() + Transitions); for (unsigned I = 0; I != Transitions; ++I) { unsigned Offset = Record[Idx++]; diff --git a/clang/lib/Serialization/ASTReaderDecl.cpp b/clang/lib/Serialization/ASTReaderDecl.cpp --- a/clang/lib/Serialization/ASTReaderDecl.cpp +++ b/clang/lib/Serialization/ASTReaderDecl.cpp @@ -1745,6 +1745,7 @@ RedeclarableResult Redecl = VisitRedeclarable(D); VisitNamedDecl(D); D->setInline(Record.readInt()); + D->setNested(Record.readInt()); D->LocStart = readSourceLocation(); D->RBraceLoc = readSourceLocation(); @@ -1758,7 +1759,7 @@ } else { // Link this namespace back to the first declaration, which has already // been deserialized. - D->AnonOrFirstNamespaceAndInline.setPointer(D->getFirstDecl()); + D->AnonOrFirstNamespaceAndFlags.setPointer(D->getFirstDecl()); } mergeRedeclarable(D, Redecl); @@ -2784,8 +2785,8 @@ // We cannot have loaded any redeclarations of this declaration yet, so // there's nothing else that needs to be updated. if (auto *Namespace = dyn_cast(D)) - Namespace->AnonOrFirstNamespaceAndInline.setPointer( - assert_cast(ExistingCanon)); + Namespace->AnonOrFirstNamespaceAndFlags.setPointer( + assert_cast(ExistingCanon)); // When we merge a template, merge its pattern. if (auto *DTemplate = dyn_cast(D)) diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -1979,6 +1979,14 @@ // Compress the buffer if possible. We expect that almost all PCM // consumers will not want its contents. SmallVector CompressedBuffer; + if (llvm::compression::zstd::isAvailable()) { + llvm::compression::zstd::compress( + llvm::arrayRefFromStringRef(Blob.drop_back(1)), CompressedBuffer, 9); + RecordDataType Record[] = {SM_SLOC_BUFFER_BLOB_COMPRESSED, Blob.size() - 1}; + Stream.EmitRecordWithBlob(SLocBufferBlobCompressedAbbrv, Record, + llvm::toStringRef(CompressedBuffer)); + return; + } if (llvm::compression::zlib::isAvailable()) { llvm::compression::zlib::compress( llvm::arrayRefFromStringRef(Blob.drop_back(1)), CompressedBuffer); @@ -2998,7 +3006,9 @@ continue; ++NumLocations; - AddFileID(FileIDAndFile.first, Record); + SourceLocation Loc = Diag.SourceMgr->getComposedLoc(FileIDAndFile.first, 0); + assert(!Loc.isInvalid() && "start loc for valid FileID is invalid"); + AddSourceLocation(Loc, Record); Record.push_back(FileIDAndFile.second.StateTransitions.size()); for (auto &StatePoint : FileIDAndFile.second.StateTransitions) { diff --git a/clang/lib/Serialization/ASTWriterDecl.cpp b/clang/lib/Serialization/ASTWriterDecl.cpp --- a/clang/lib/Serialization/ASTWriterDecl.cpp +++ b/clang/lib/Serialization/ASTWriterDecl.cpp @@ -1252,6 +1252,7 @@ VisitRedeclarable(D); VisitNamedDecl(D); Record.push_back(D->isInline()); + Record.push_back(D->isNested()); Record.AddSourceLocation(D->getBeginLoc()); Record.AddSourceLocation(D->getRBraceLoc()); diff --git a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp --- a/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp +++ b/clang/lib/StaticAnalyzer/Core/ExprEngine.cpp @@ -480,9 +480,8 @@ Optional ExprEngine::getPendingInitLoop(ProgramStateRef State, const CXXConstructExpr *E, const LocationContext *LCtx) { - - return Optional::create( - State->get({E, LCtx->getStackFrame()})); + const unsigned *V = State->get({E, LCtx->getStackFrame()}); + return V ? Optional(*V) : std::nullopt; } ProgramStateRef ExprEngine::removePendingInitLoop(ProgramStateRef State, @@ -509,9 +508,9 @@ ExprEngine::getIndexOfElementToConstruct(ProgramStateRef State, const CXXConstructExpr *E, const LocationContext *LCtx) { - - return Optional::create( - State->get({E, LCtx->getStackFrame()})); + const unsigned *V = + State->get({E, LCtx->getStackFrame()}); + return V ? Optional(*V) : std::nullopt; } ProgramStateRef @@ -529,8 +528,9 @@ const LocationContext *LCtx) { assert(LCtx && "LocationContext shouldn't be null!"); - return Optional::create( - State->get(LCtx->getStackFrame())); + const unsigned *V = + State->get(LCtx->getStackFrame()); + return V ? Optional(*V) : std::nullopt; } ProgramStateRef ExprEngine::setPendingArrayDestruction( @@ -599,7 +599,8 @@ const ConstructionContextItem &Item, const LocationContext *LC) { ConstructedObjectKey Key(Item, LC->getStackFrame()); - return Optional::create(State->get(Key)); + const SVal *V = State->get(Key); + return V ? Optional(*V) : std::nullopt; } ProgramStateRef diff --git a/clang/lib/StaticAnalyzer/Core/MemRegion.cpp b/clang/lib/StaticAnalyzer/Core/MemRegion.cpp --- a/clang/lib/StaticAnalyzer/Core/MemRegion.cpp +++ b/clang/lib/StaticAnalyzer/Core/MemRegion.cpp @@ -790,22 +790,30 @@ return true; if (const auto *CAT = dyn_cast(AT)) { - const llvm::APInt &Size = CAT->getSize(); - if (Size.isZero()) - return true; - using FAMKind = LangOptions::StrictFlexArraysLevelKind; const FAMKind StrictFlexArraysLevel = Ctx.getLangOpts().getStrictFlexArraysLevel(); - if (StrictFlexArraysLevel == FAMKind::ZeroOrIncomplete || - StrictFlexArraysLevel == FAMKind::IncompleteOnly) - return false; - const AnalyzerOptions &Opts = SVB.getAnalyzerOptions(); - // FIXME: this option is probably redundant with -fstrict-flex-arrays=1. - if (Opts.ShouldConsiderSingleElementArraysAsFlexibleArrayMembers && - Size.isOne()) + const llvm::APInt &Size = CAT->getSize(); + + if (StrictFlexArraysLevel <= FAMKind::ZeroOrIncomplete && Size.isZero()) return true; + + // The "-fstrict-flex-arrays" should have precedence over + // consider-single-element-arrays-as-flexible-array-members + // analyzer-config when checking single element arrays. + if (StrictFlexArraysLevel == FAMKind::Default) { + // FIXME: After clang-17 released, we should remove this branch. + if (Opts.ShouldConsiderSingleElementArraysAsFlexibleArrayMembers && + Size.isOne()) + return true; + } else { + // -fstrict-flex-arrays was specified, since it's not the default, so + // ignore analyzer-config. + if (StrictFlexArraysLevel <= FAMKind::OneZeroOrIncomplete && + Size.isOne()) + return true; + } } return false; }; diff --git a/clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp b/clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp --- a/clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp +++ b/clang/lib/StaticAnalyzer/Frontend/AnalysisConsumer.cpp @@ -27,7 +27,6 @@ #include "clang/Frontend/CompilerInstance.h" #include "clang/Lex/Preprocessor.h" #include "clang/Rewrite/Core/Rewriter.h" -#include "clang/StaticAnalyzer/Checkers/LocalCheckers.h" #include "clang/StaticAnalyzer/Core/AnalyzerOptions.h" #include "clang/StaticAnalyzer/Core/BugReporter/BugReporter.h" #include "clang/StaticAnalyzer/Core/CheckerManager.h" diff --git a/clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp b/clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp --- a/clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp +++ b/clang/lib/Tooling/Inclusions/HeaderAnalysis.cpp @@ -64,4 +64,28 @@ const_cast(SM).getMemoryBufferForFileOrNone(FE).value_or( llvm::MemoryBufferRef())); } + +llvm::Optional parseIWYUPragma(const char *Text) { + // Skip the comment start, // or /*. + if (Text[0] != '/' || (Text[1] != '/' && Text[1] != '*')) + return llvm::None; + bool BlockComment = Text[1] == '*'; + Text += 2; + + // Per spec, direcitves are whitespace- and case-sensitive. + constexpr llvm::StringLiteral IWYUPragma = " IWYU pragma: "; + if (strncmp(Text, IWYUPragma.data(), IWYUPragma.size())) + return llvm::None; + Text += IWYUPragma.size(); + const char *End = Text; + while (*End != 0 && *End != '\n') + ++End; + StringRef Rest(Text, End - Text); + // Strip off whitespace and comment markers to avoid confusion. This isn't + // fully-compatible with IWYU, which splits into whitespace-delimited tokens. + if (BlockComment) + Rest.consume_back("*/"); + return Rest.trim(); +} + } // namespace clang::tooling diff --git a/clang/lib/Tooling/Transformer/Parsing.cpp b/clang/lib/Tooling/Transformer/Parsing.cpp --- a/clang/lib/Tooling/Transformer/Parsing.cpp +++ b/clang/lib/Tooling/Transformer/Parsing.cpp @@ -152,7 +152,7 @@ // Parses a single expected character \c c from \c State, skipping preceding // whitespace. Error if the expected character isn't found. -static ExpectedProgress parseChar(char c, ParseState State) { +static ExpectedProgress parseChar(char c, ParseState State) { State.Input = consumeWhitespace(State.Input); if (State.Input.empty() || State.Input.front() != c) return makeParseError(State, diff --git a/clang/test/AST/ast-dump-decl.cpp b/clang/test/AST/ast-dump-decl.cpp --- a/clang/test/AST/ast-dump-decl.cpp +++ b/clang/test/AST/ast-dump-decl.cpp @@ -53,6 +53,23 @@ } // CHECK: NamespaceDecl{{.*}} TestNamespaceDeclInline inline +namespace TestNestedNameSpace::Nested { +} +// CHECK: NamespaceDecl{{.*}} TestNestedNameSpace +// CHECK: NamespaceDecl{{.*}} Nested nested{{\s*$}} + +namespace TestMultipleNested::SecondLevelNested::Nested { +} +// CHECK: NamespaceDecl{{.*}} TestMultipleNested +// CHECK: NamespaceDecl{{.*}} SecondLevelNested nested +// CHECK: NamespaceDecl{{.*}} Nested nested{{\s*$}} + +namespace TestInlineNested::inline SecondLevel::inline Nested { +} +// CHECK: NamespaceDecl{{.*}} TestInlineNested +// CHECK: NamespaceDecl{{.*}} SecondLevel inline nested +// CHECK: NamespaceDecl{{.*}} Nested inline nested{{\s*$}} + namespace testUsingDirectiveDecl { namespace A { } diff --git a/clang/test/AST/ast-dump-namespace-json.cpp b/clang/test/AST/ast-dump-namespace-json.cpp --- a/clang/test/AST/ast-dump-namespace-json.cpp +++ b/clang/test/AST/ast-dump-namespace-json.cpp @@ -170,6 +170,7 @@ // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "name": "quux" +// CHECK-NEXT: "isNested": true // CHECK-NEXT: } // CHECK-NEXT: ] // CHECK-NEXT: } @@ -195,7 +196,7 @@ // CHECK-NEXT: "tokLen": 1 // CHECK-NEXT: } // CHECK-NEXT: }, -// CHECK-NEXT: "name": "quux", +// CHECK-NEXT: "name": "quux" // CHECK-NEXT: "inner": [ // CHECK-NEXT: { // CHECK-NEXT: "id": "0x{{.*}}", @@ -220,7 +221,8 @@ // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "name": "frobble", -// CHECK-NEXT: "isInline": true +// CHECK-NEXT: "isInline": true, +// CHECK-NEXT: "isNested": true // CHECK-NEXT: } // CHECK-NEXT: ] // CHECK-NEXT: } diff --git a/clang/test/Analysis/analyzer-config.c b/clang/test/Analysis/analyzer-config.c --- a/clang/test/Analysis/analyzer-config.c +++ b/clang/test/Analysis/analyzer-config.c @@ -33,7 +33,7 @@ // CHECK-NEXT: cfg-rich-constructors = true // CHECK-NEXT: cfg-scopes = false // CHECK-NEXT: cfg-temporary-dtors = true -// CHECK-NEXT: consider-single-element-arrays-as-flexible-array-members = false +// CHECK-NEXT: consider-single-element-arrays-as-flexible-array-members = true // CHECK-NEXT: core.CallAndMessage:ArgInitializedness = true // CHECK-NEXT: core.CallAndMessage:ArgPointeeInitializedness = false // CHECK-NEXT: core.CallAndMessage:CXXDeallocationArg = true diff --git a/clang/test/Analysis/deprecated-flags-and-options.cpp b/clang/test/Analysis/deprecated-flags-and-options.cpp --- a/clang/test/Analysis/deprecated-flags-and-options.cpp +++ b/clang/test/Analysis/deprecated-flags-and-options.cpp @@ -9,6 +9,15 @@ // RUN: | FileCheck %s --check-prefixes=DEPRECATED-NESTED-BLOCKS // DEPRECATED-NESTED-BLOCKS: error: unknown argument: '-analyzer-opt-analyze-nested-blocks' +// RUN: %clang_analyze_cc1 -analyzer-checker=core -analyzer-config consider-single-element-arrays-as-flexible-array-members=true %s 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK,DEPRECATED-SINGLE-ELEM-FAM +// DEPRECATED-SINGLE-ELEM-FAM: warning: analyzer option 'consider-single-element-arrays-as-flexible-array-members' is deprecated. This flag will be removed in clang-17, and passing this option will be an error. Use '-fstrict-flex-arrays=' instead. + +// RUN: %clang_analyze_cc1 -analyzer-config-help 2>&1 \ +// RUN: | FileCheck %s --check-prefixes=CHECK-HELP +// CHECK-HELP: [DEPRECATED, removing in clang-17; use '-fstrict-flex-arrays=' +// CHECK-HELP-NEXT: instead] (default: true) + int empty(int x) { // CHECK: warning: Division by zero return x ? 0 : 0 / x; diff --git a/clang/test/Analysis/flexible-array-members.c b/clang/test/Analysis/flexible-array-members.c --- a/clang/test/Analysis/flexible-array-members.c +++ b/clang/test/Analysis/flexible-array-members.c @@ -1,18 +1,30 @@ -// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c90 -// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c99 -// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c11 -// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c17 - -// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c++98 -x c++ -// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c++03 -x c++ -// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c++11 -x c++ -// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c++14 -x c++ -// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c++17 -x c++ +// -fstrict-flex-arrays=2 means that only undefined or zero element arrays are considered as FAMs. + +// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c90 \ +// RUN: -fstrict-flex-arrays=2 +// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c99 \ +// RUN: -fstrict-flex-arrays=2 +// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c11 \ +// RUN: -fstrict-flex-arrays=2 +// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c17 \ +// RUN: -fstrict-flex-arrays=2 + +// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c++98 -x c++ \ +// RUN: -fstrict-flex-arrays=2 +// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c++03 -x c++ \ +// RUN: -fstrict-flex-arrays=2 +// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c++11 -x c++ \ +// RUN: -fstrict-flex-arrays=2 +// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c++14 -x c++ \ +// RUN: -fstrict-flex-arrays=2 +// RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c++17 -x c++ \ +// RUN: -fstrict-flex-arrays=2 +// By default, -fstrict-flex-arrays=0, which means that even single element arrays are considered as FAMs. // RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c17 \ -// RUN: -analyzer-config consider-single-element-arrays-as-flexible-array-members=true -DSINGLE_ELEMENT_FAMS +// RUN: -DSINGLE_ELEMENT_FAMS // RUN: %clang_analyze_cc1 -triple x86_64-linux-gnu -analyzer-checker=core,unix,debug.ExprInspection %s -verify -std=c++17 -x c++ \ -// RUN: -analyzer-config consider-single-element-arrays-as-flexible-array-members=true -DSINGLE_ELEMENT_FAMS +// RUN: -DSINGLE_ELEMENT_FAMS typedef __typeof(sizeof(int)) size_t; size_t clang_analyzer_getExtent(void *); diff --git a/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c b/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c --- a/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c +++ b/clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -O0 -ffreestanding -triple=x86_64-apple-darwin -target-cpu skylake-avx512 -emit-llvm -o - -Wall -Werror | opt -passes=instnamer -S | FileCheck %s +// RUN: %clang_cc1 %s -O0 -ffreestanding -triple=x86_64-apple-darwin -target-cpu skylake-avx512 -emit-llvm -o - -Wall -Werror | FileCheck %s // This test checks validity of att\gcc style inline assmebly for avx512 k and Yk constraints. // Also checks mask register allows flexible type (size <= 64 bit) diff --git a/clang/test/CodeGen/aarch64-neon-dot-product.c b/clang/test/CodeGen/aarch64-neon-dot-product.c --- a/clang/test/CodeGen/aarch64-neon-dot-product.c +++ b/clang/test/CodeGen/aarch64-neon-dot-product.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -instcombine | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=instcombine | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c b/clang/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c --- a/clang/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c +++ b/clang/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg -dce \ +// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg,dce \ // RUN: | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abs.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abs.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abs.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abs.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acge.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acge.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acge.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acge.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acgt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acgt.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acgt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acgt.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acle.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acle.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acle.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_acle.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_aclt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_aclt.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_aclt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_aclt.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_add.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adda.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adda.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adda.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adda.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_addv.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_addv.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_addv.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_addv.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrd.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrd.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrh.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrh.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_adrw.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_and.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_andv.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_andv.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_andv.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_andv.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asr.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asr.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asrd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asrd.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asrd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_asrd.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfdot.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfdot.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfdot.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfdot.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalb.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalt.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmlalt.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bic.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brka.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brka.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brka.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brka.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkn.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkn.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkn.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkn.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpa.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpa.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpa.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpa.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_brkpb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cadd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cadd.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cadd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cadd.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cls.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cls.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cls.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cls.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clz.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clz.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clz.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clz.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmla.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmla.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmla.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmla.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpeq.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpeq.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpeq.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpeq.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpge.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpge.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpge.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpge.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpgt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpgt.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpgt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpgt.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmple.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmple.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmple.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmple.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmplt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmplt.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmplt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmplt.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpne.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpne.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpne.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpne.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpuo.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpuo.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpuo.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpuo.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnot.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnot.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnot.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnot.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntb.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntd.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntd.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnth.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnth.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnth.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnth.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntp.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntp.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntp.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntp.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_compact.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_compact.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_compact.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_compact.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvtnt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvtnt.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvtnt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvtnt.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_div.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_divr.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dot.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dot.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dot.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dot.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dup.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_dupq.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eor.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eorv.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eorv.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eorv.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_eorv.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_expa.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_expa.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_expa.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_expa.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_exth.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_exth.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_exth.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_exth.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_extw.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_index.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_index.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_index.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_index.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_insr-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_insr-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_insr-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_insr-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_insr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_insr.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_insr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_insr.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lasta-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lasta-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lasta-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lasta-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lasta.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lasta.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lasta.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lasta.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lastb-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lastb-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lastb-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lastb-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lastb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lastb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lastb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lastb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +f64mm -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1rq-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1rq-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1rq-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1rq-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1rq.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1rq.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1rq.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1rq.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sh.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1sw.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ub.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uh.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1uw.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld2.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld3.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld4.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sh.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sh.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1sw.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1ub.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1ub.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1ub.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1ub.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uh.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uh.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldff1uw.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1sb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1sb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1sb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1sb.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1sh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1sh.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1sh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1sh.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1sw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1sw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1sw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1sw.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1ub.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1ub.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1ub.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1ub.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1uh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1uh.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1uh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1uh.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1uw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1uw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1uw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1uw.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnt1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnt1-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnt1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnt1-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnt1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnt1.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnt1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnt1.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsl.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsl.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsl.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsl.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsr.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_lsr.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mad.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mad.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mad.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mad.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp32.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp32.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp32.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp32.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f32mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f32mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f32mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f32mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f32mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f32mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f32mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f32mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp64.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_matmul_fp64.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_max.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnm.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnm.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnm.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnm.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnmv.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnmv.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnmv.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxnmv.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxv.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxv.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxv.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_maxv.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_min.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnm.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnm.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnm.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnm.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnmv.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnmv.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnmv.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minnmv.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minv.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minv.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minv.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_minv.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mla.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mla.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mla.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mla.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mls.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mls.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mls.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mls.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mmla.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mmla.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mmla.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mmla.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +i8mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +i8mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +i8mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +i8mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mov.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mov.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mov.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mov.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_msb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_msb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_msb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_msb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mul.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulh.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulx.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulx.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulx.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_mulx.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nand.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nand.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nand.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nand.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_neg.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_neg.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_neg.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_neg.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmad.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmad.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmad.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmad.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmla.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmla.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmla.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmla.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmls.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmls.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmls.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmls.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmsb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmsb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmsb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nmsb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nor.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nor.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nor.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_nor.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_not.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orn.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orn.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orn.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orn.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orr.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orv.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orv.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orv.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_orv.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfalse.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfirst.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfirst.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfirst.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pfirst.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pnext.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pnext.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pnext.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_pnext.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfd.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfd.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfh.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfh.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_prfw.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptest.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptest.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptest.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptest.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptrue.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptrue.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptrue.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ptrue.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qadd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qadd.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qadd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qadd.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecd.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecd.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdech.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdech.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdech.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdech.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecp.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecp.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecp.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecp.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qdecw.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincd.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincd.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincd.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincd.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qinch.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qinch.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qinch.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qinch.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincp.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincp.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincp.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincp.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qincw.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qsub.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qsub.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qsub.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_qsub.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rbit.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rbit.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rbit.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rbit.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rdffr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rdffr.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rdffr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rdffr.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recpe.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recpe.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recpe.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recpe.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recps.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recps.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recps.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recps.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recpx.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recpx.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recpx.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_recpx.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revb.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revb.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revb.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revb.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revh.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revh.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revh.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revh.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revw.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revw.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revw.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_revw.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinta.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinta.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinta.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinta.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinti.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinti.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinti.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rinti.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintm.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintm.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintm.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintm.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintn.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintn.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintn.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintn.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintp.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintp.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintp.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintp.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintx.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintx.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintx.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintx.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintz.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintz.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintz.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rintz.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rsqrte.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rsqrte.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rsqrte.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rsqrte.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rsqrts.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rsqrts.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rsqrts.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rsqrts.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_scale.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_scale.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_scale.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_scale.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_setffr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_setffr.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_setffr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_setffr.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sqrt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sqrt.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sqrt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sqrt.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1b.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o - -emit-llvm %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o - -emit-llvm %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o - -emit-llvm %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o - -emit-llvm %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1h.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1h.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1h.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1h.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o - -emit-llvm %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o - -emit-llvm %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o - -emit-llvm %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o - -emit-llvm %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1w.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1w.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1w.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st1w.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o - -emit-llvm %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o - -emit-llvm %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o - -emit-llvm %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o - -emit-llvm %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st2.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st3.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_st4.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_stnt1.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sub.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_subr.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sudot.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sudot.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sudot.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sudot.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -target-feature +i8mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +i8mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +i8mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +i8mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl-bfloat.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tbl.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tmad.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tmad.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tmad.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tmad.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tsmul.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tsmul.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tsmul.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tsmul.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tssel.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tssel.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tssel.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_tssel.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef-bfloat.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2-bfloat.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -O2 -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -O2 -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -O2 -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -O2 -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3-bfloat.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -O2 -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -O2 -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -O2 -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -O2 -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4-bfloat.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -O2 -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -O2 -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -O2 -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -O2 -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_unpkhi.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_unpkhi.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_unpkhi.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_unpkhi.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_unpklo.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_unpklo.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_unpklo.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_unpklo.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_usdot.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_usdot.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_usdot.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_usdot.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -target-feature +i8mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +i8mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +i8mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +i8mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +i8mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilele.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilele.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilele.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilele.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilelt.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilelt.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilelt.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_whilelt.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_wrffr.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_wrffr.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_wrffr.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_wrffr.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64-bfloat.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64-bfloat.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64-bfloat.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64-bfloat.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -target-feature +f64mm -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2.c b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2.c --- a/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2.c +++ b/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -mem2reg -instcombine -tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sve-vector-arith-ops.c b/clang/test/CodeGen/aarch64-sve-vector-arith-ops.c --- a/clang/test/CodeGen/aarch64-sve-vector-arith-ops.c +++ b/clang/test/CodeGen/aarch64-sve-vector-arith-ops.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ // RUN: -disable-O0-optnone \ -// RUN: -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-vector-bitwise-ops.c b/clang/test/CodeGen/aarch64-sve-vector-bitwise-ops.c --- a/clang/test/CodeGen/aarch64-sve-vector-bitwise-ops.c +++ b/clang/test/CodeGen/aarch64-sve-vector-bitwise-ops.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ // RUN: -disable-O0-optnone \ -// RUN: -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-vector-compare-ops.c b/clang/test/CodeGen/aarch64-sve-vector-compare-ops.c --- a/clang/test/CodeGen/aarch64-sve-vector-compare-ops.c +++ b/clang/test/CodeGen/aarch64-sve-vector-compare-ops.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ // RUN: -disable-O0-optnone \ -// RUN: -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-vector-shift-ops.c b/clang/test/CodeGen/aarch64-sve-vector-shift-ops.c --- a/clang/test/CodeGen/aarch64-sve-vector-shift-ops.c +++ b/clang/test/CodeGen/aarch64-sve-vector-shift-ops.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ // RUN: -disable-O0-optnone \ -// RUN: -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-vector-subscript-ops.c b/clang/test/CodeGen/aarch64-sve-vector-subscript-ops.c --- a/clang/test/CodeGen/aarch64-sve-vector-subscript-ops.c +++ b/clang/test/CodeGen/aarch64-sve-vector-subscript-ops.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ // RUN: -disable-O0-optnone \ -// RUN: -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-vls-arith-ops.c b/clang/test/CodeGen/aarch64-sve-vls-arith-ops.c --- a/clang/test/CodeGen/aarch64-sve-vls-arith-ops.c +++ b/clang/test/CodeGen/aarch64-sve-vls-arith-ops.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ // RUN: -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 \ -// RUN: -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-vls-bitwise-ops.c b/clang/test/CodeGen/aarch64-sve-vls-bitwise-ops.c --- a/clang/test/CodeGen/aarch64-sve-vls-bitwise-ops.c +++ b/clang/test/CodeGen/aarch64-sve-vls-bitwise-ops.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ // RUN: -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 \ -// RUN: -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-vls-compare-ops.c b/clang/test/CodeGen/aarch64-sve-vls-compare-ops.c --- a/clang/test/CodeGen/aarch64-sve-vls-compare-ops.c +++ b/clang/test/CodeGen/aarch64-sve-vls-compare-ops.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ // RUN: -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 \ -// RUN: -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-vls-shift-ops.c b/clang/test/CodeGen/aarch64-sve-vls-shift-ops.c --- a/clang/test/CodeGen/aarch64-sve-vls-shift-ops.c +++ b/clang/test/CodeGen/aarch64-sve-vls-shift-ops.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ // RUN: -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 \ -// RUN: -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-sve-vls-subscript-ops.c b/clang/test/CodeGen/aarch64-sve-vls-subscript-ops.c --- a/clang/test/CodeGen/aarch64-sve-vls-subscript-ops.c +++ b/clang/test/CodeGen/aarch64-sve-vls-subscript-ops.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ // RUN: -disable-O0-optnone -mvscale-min=4 -mvscale-max=4 \ -// RUN: -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c b/clang/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c --- a/clang/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c +++ b/clang/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ -// RUN: -target-feature +v8.1a -S -emit-llvm -disable-O0-optnone -o - %s | opt -mem2reg -dce -S | FileCheck %s +// RUN: -target-feature +v8.1a -S -emit-llvm -disable-O0-optnone -o - %s | opt -passes=mem2reg,dce -S | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/aarch64-v8.6a-neon-intrinsics.c b/clang/test/CodeGen/aarch64-v8.6a-neon-intrinsics.c --- a/clang/test/CodeGen/aarch64-v8.6a-neon-intrinsics.c +++ b/clang/test/CodeGen/aarch64-v8.6a-neon-intrinsics.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.6a -target-feature +i8mm \ // RUN: -S -disable-O0-optnone -emit-llvm -o - %s \ -// RUN: | opt -S -mem2reg -sroa \ +// RUN: | opt -S -passes=mem2reg,sroa \ // RUN: | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGen/arm-bf16-params-returns.c b/clang/test/CodeGen/arm-bf16-params-returns.c --- a/clang/test/CodeGen/arm-bf16-params-returns.c +++ b/clang/test/CodeGen/arm-bf16-params-returns.c @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-HARD -// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-SOFTFP -// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefixes=CHECK64,CHECK64NEON -// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -target-feature -bf16 -target-feature +neon -DNONEON -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK64 +// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefix=CHECK32-HARD +// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefix=CHECK32-SOFTFP +// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefixes=CHECK64,CHECK64NEON +// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -target-feature -bf16 -target-feature +neon -DNONEON -emit-llvm -O2 -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefix=CHECK64 // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c b/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c --- a/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c +++ b/clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \ // RUN: -disable-O0-optnone -S -emit-llvm -o - %s \ -// RUN: | opt -S -instcombine \ +// RUN: | opt -S -passes=instcombine \ // RUN: | FileCheck %s // REQUIRES: arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/admin.c b/clang/test/CodeGen/arm-mve-intrinsics/admin.c --- a/clang/test/CodeGen/arm-mve-intrinsics/admin.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/admin.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-LE -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-LE -// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-BE -// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefixes=CHECK,CHECK-BE +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s --check-prefixes=CHECK,CHECK-LE +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s --check-prefixes=CHECK,CHECK-LE +// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s --check-prefixes=CHECK,CHECK-BE +// RUN: %clang_cc1 -triple thumbebv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s --check-prefixes=CHECK,CHECK-BE // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/compare.c b/clang/test/CodeGen/arm-mve-intrinsics/compare.c --- a/clang/test/CodeGen/arm-mve-intrinsics/compare.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/compare.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/dup.c b/clang/test/CodeGen/arm-mve-intrinsics/dup.c --- a/clang/test/CodeGen/arm-mve-intrinsics/dup.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/dup.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c b/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c --- a/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/get-set-lane.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/predicates.c b/clang/test/CodeGen/arm-mve-intrinsics/predicates.c --- a/clang/test/CodeGen/arm-mve-intrinsics/predicates.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/predicates.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c b/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c --- a/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/reinterpret.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=BOTH --check-prefix=LE -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=BOTH --check-prefix=LE -// RUN: %clang_cc1 -triple thumbebv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=BOTH --check-prefix=BE -// RUN: %clang_cc1 -triple thumbebv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s --check-prefix=BOTH --check-prefix=BE +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s --check-prefix=BOTH --check-prefix=LE +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s --check-prefix=BOTH --check-prefix=LE +// RUN: %clang_cc1 -triple thumbebv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s --check-prefix=BOTH --check-prefix=BE +// RUN: %clang_cc1 -triple thumbebv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s --check-prefix=BOTH --check-prefix=BE // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/ternary.c b/clang/test/CodeGen/arm-mve-intrinsics/ternary.c --- a/clang/test/CodeGen/arm-mve-intrinsics/ternary.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/ternary.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c b/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c --- a/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vabavq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c b/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c --- a/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vaddq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vld24.c b/clang/test/CodeGen/arm-mve-intrinsics/vld24.c --- a/clang/test/CodeGen/arm-mve-intrinsics/vld24.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vld24.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c b/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c --- a/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vminvq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c b/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c --- a/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmldav.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c b/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c --- a/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmlldav.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c b/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c --- a/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vmulq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vrev.c b/clang/test/CodeGen/arm-mve-intrinsics/vrev.c --- a/clang/test/CodeGen/arm-mve-intrinsics/vrev.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vrev.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c b/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c --- a/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vrnd.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes=mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg -sroa -early-cse | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes='mem2reg,sroa,early-cse<>' | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c b/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c --- a/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c +++ b/clang/test/CodeGen/arm-mve-intrinsics/vsubq.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s -// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target diff --git a/clang/test/CodeGen/arm-neon-dot-product.c b/clang/test/CodeGen/arm-neon-dot-product.c --- a/clang/test/CodeGen/arm-neon-dot-product.c +++ b/clang/test/CodeGen/arm-neon-dot-product.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -instcombine | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=instcombine | FileCheck %s // REQUIRES: arm-registered-target diff --git a/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c b/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c --- a/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c +++ b/clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon \ -// RUN: -S -emit-llvm -o - %s -disable-O0-optnone | opt -mem2reg -dce -S \ +// RUN: -S -emit-llvm -o - %s -disable-O0-optnone | opt -passes=mem2reg,dce -S \ // RUN: | FileCheck %s --check-prefix=CHECK-ARM // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ -// RUN: -target-feature +v8.1a -S -emit-llvm -o - %s -disable-O0-optnone | opt -mem2reg -dce -S \ +// RUN: -target-feature +v8.1a -S -emit-llvm -o - %s -disable-O0-optnone | opt -passes=mem2reg,dce -S \ // RUN: | FileCheck %s --check-prefix=CHECK-AARCH64 // REQUIRES: arm-registered-target,aarch64-registered-target diff --git a/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c b/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c --- a/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c +++ b/clang/test/CodeGen/arm-v8.6a-neon-intrinsics.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +fullfp16 -target-feature +i8mm \ // RUN: -S -disable-O0-optnone -emit-llvm -o - %s \ -// RUN: | opt -S -mem2reg -sroa \ +// RUN: | opt -S -passes=mem2reg,sroa \ // RUN: | FileCheck %s // REQUIRES: arm-registered-target diff --git a/clang/test/CodeGen/avr/alias-avr.c b/clang/test/CodeGen/avr/alias-avr.c --- a/clang/test/CodeGen/avr/alias-avr.c +++ b/clang/test/CodeGen/avr/alias-avr.c @@ -6,3 +6,8 @@ // CHECK: @multiply ={{.*}} alias i16 (i16, i16), ptr addrspace(1) @mul int multiply(int x, int y) __attribute__((alias("mul"))); + +// Make sure the correct address space is used when creating an alias that needs +// a pointer cast. +// CHECK: @smallmul = alias i8 (i16, i16), ptr addrspace(1) @mul +char smallmul(int a, int b) __attribute__((alias("mul"))); diff --git a/clang/test/CodeGen/builtin-align.c b/clang/test/CodeGen/builtin-align.c --- a/clang/test/CodeGen/builtin-align.c +++ b/clang/test/CodeGen/builtin-align.c @@ -2,20 +2,20 @@ /// Check the code generation for the alignment builtins /// To make the test case easier to read, run SROA after generating IR to remove the alloca instructions. // RUN: %clang_cc1 -triple=x86_64-unknown-unknown -DTEST_VOID_PTR \ -// RUN: -o - -emit-llvm %s -disable-O0-optnone | opt -S -sroa | \ +// RUN: -o - -emit-llvm %s -disable-O0-optnone | opt -S -passes=sroa | \ // RUN: FileCheck %s -check-prefixes CHECK,CHECK-VOID_PTR \ // RUN: -enable-var-scope '-D$PTRTYPE=i8' // RUN: %clang_cc1 -triple=x86_64-unknown-unknown -DTEST_FLOAT_PTR \ -// RUN: -o - -emit-llvm %s -disable-O0-optnone | opt -S -sroa | \ +// RUN: -o - -emit-llvm %s -disable-O0-optnone | opt -S -passes=sroa | \ // RUN: FileCheck %s -check-prefixes CHECK,CHECK-FLOAT_PTR \ // RUN: -enable-var-scope '-D$PTRTYPE=f32' // RUN: %clang_cc1 -triple=x86_64-unknown-unknown -DTEST_LONG \ -// RUN: -o - -emit-llvm %s -disable-O0-optnone | opt -S -sroa | \ +// RUN: -o - -emit-llvm %s -disable-O0-optnone | opt -S -passes=sroa | \ // RUN: FileCheck %s -check-prefixes CHECK,CHECK-LONG -enable-var-scope /// Check that we can handle the case where the alignment parameter is wider /// than the source type (generate a trunc on alignment instead of zext) // RUN: %clang_cc1 -triple=x86_64-unknown-unknown -DTEST_USHORT \ -// RUN: -o - -emit-llvm %s -disable-O0-optnone | opt -S -sroa | \ +// RUN: -o - -emit-llvm %s -disable-O0-optnone | opt -S -passes=sroa | \ // RUN: FileCheck %s -check-prefixes CHECK,CHECK-USHORT -enable-var-scope diff --git a/clang/test/CodeGen/catch-undef-behavior.c b/clang/test/CodeGen/catch-undef-behavior.c --- a/clang/test/CodeGen/catch-undef-behavior.c +++ b/clang/test/CodeGen/catch-undef-behavior.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -no-opaque-pointers -fsanitize=alignment,null,object-size,shift-base,shift-exponent,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift-base,shift-exponent,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -emit-llvm %s -o - -triple x86_64-linux-gnu | opt -passes=instnamer -S | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-UBSAN -// RUN: %clang_cc1 -no-opaque-pointers -fsanitize-trap=alignment,null,object-size,shift-base,shift-exponent,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift-base,shift-exponent,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize=alignment,null,object-size,shift-base,shift-exponent,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift-base,shift-exponent,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -emit-llvm %s -o - -triple x86_64-linux-gnu | opt -passes=instnamer -S | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-TRAP +// RUN: %clang_cc1 -no-opaque-pointers -fsanitize=alignment,null,object-size,shift-base,shift-exponent,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift-base,shift-exponent,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-UBSAN +// RUN: %clang_cc1 -no-opaque-pointers -fsanitize-trap=alignment,null,object-size,shift-base,shift-exponent,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift-base,shift-exponent,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize=alignment,null,object-size,shift-base,shift-exponent,return,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -fsanitize-recover=alignment,null,object-size,shift-base,shift-exponent,signed-integer-overflow,vla-bound,float-cast-overflow,integer-divide-by-zero,bool,returns-nonnull-attribute,nonnull-attribute -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-COMMON --check-prefix=CHECK-TRAP // RUN: %clang_cc1 -no-opaque-pointers -fsanitize=signed-integer-overflow -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-OVERFLOW // CHECK-UBSAN: @[[INT:.*]] = private unnamed_addr constant { i16, i16, [6 x i8] } { i16 0, i16 11, [6 x i8] c"'int'\00" } diff --git a/clang/test/CodeGen/exceptions-seh-leave.c b/clang/test/CodeGen/exceptions-seh-leave.c --- a/clang/test/CodeGen/exceptions-seh-leave.c +++ b/clang/test/CodeGen/exceptions-seh-leave.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -triple x86_64-pc-win32 -fms-extensions -emit-llvm -o - | opt -passes=instnamer -S | FileCheck %s +// RUN: %clang_cc1 %s -triple x86_64-pc-win32 -fms-extensions -emit-llvm -o - | FileCheck %s void g(void); diff --git a/clang/test/CodeGen/fp-atomic-ops.c b/clang/test/CodeGen/fp-atomic-ops.c --- a/clang/test/CodeGen/fp-atomic-ops.c +++ b/clang/test/CodeGen/fp-atomic-ops.c @@ -1,23 +1,23 @@ // RUN: %clang_cc1 %s -emit-llvm -DDOUBLE -O0 -o - -triple=amdgcn-amd-amdhsa \ -// RUN: | opt -passes=instnamer -S | FileCheck -check-prefixes=FLOAT,DOUBLE %s +// RUN: | FileCheck -check-prefixes=FLOAT,DOUBLE %s // RUN: %clang_cc1 %s -emit-llvm -DDOUBLE -O0 -o - -triple=aarch64-linux-gnu \ -// RUN: | opt -passes=instnamer -S | FileCheck -check-prefixes=FLOAT,DOUBLE %s +// RUN: | FileCheck -check-prefixes=FLOAT,DOUBLE %s // RUN: %clang_cc1 %s -emit-llvm -O0 -o - -triple=armv8-apple-ios7.0 \ -// RUN: | opt -passes=instnamer -S | FileCheck -check-prefixes=FLOAT %s +// RUN: | FileCheck -check-prefixes=FLOAT %s // RUN: %clang_cc1 %s -emit-llvm -DDOUBLE -O0 -o - -triple=hexagon \ -// RUN: | opt -passes=instnamer -S | FileCheck -check-prefixes=FLOAT,DOUBLE %s +// RUN: | FileCheck -check-prefixes=FLOAT,DOUBLE %s // RUN: %clang_cc1 %s -emit-llvm -DDOUBLE -O0 -o - -triple=mips64-mti-linux-gnu \ -// RUN: | opt -passes=instnamer -S | FileCheck -check-prefixes=FLOAT,DOUBLE %s +// RUN: | FileCheck -check-prefixes=FLOAT,DOUBLE %s // RUN: %clang_cc1 %s -emit-llvm -O0 -o - -triple=i686-linux-gnu \ -// RUN: | opt -passes=instnamer -S | FileCheck -check-prefixes=FLOAT %s +// RUN: | FileCheck -check-prefixes=FLOAT %s // RUN: %clang_cc1 %s -emit-llvm -DDOUBLE -O0 -o - -triple=x86_64-linux-gnu \ -// RUN: | opt -passes=instnamer -S | FileCheck -check-prefixes=FLOAT,DOUBLE %s +// RUN: | FileCheck -check-prefixes=FLOAT,DOUBLE %s typedef enum memory_order { memory_order_relaxed = __ATOMIC_RELAXED, diff --git a/clang/test/CodeGen/mozilla-ms-inline-asm.c b/clang/test/CodeGen/mozilla-ms-inline-asm.c --- a/clang/test/CodeGen/mozilla-ms-inline-asm.c +++ b/clang/test/CodeGen/mozilla-ms-inline-asm.c @@ -1,5 +1,5 @@ // REQUIRES: x86-registered-target -// RUN: %clang_cc1 %s -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | opt -strip -S | FileCheck %s +// RUN: %clang_cc1 %s -triple i386-apple-darwin10 -fasm-blocks -emit-llvm -o - | opt -passes=strip -S | FileCheck %s // Some test cases for MS inline asm support from Mozilla code base. diff --git a/clang/test/CodeGen/packed-structure.c b/clang/test/CodeGen/packed-structure.c --- a/clang/test/CodeGen/packed-structure.c +++ b/clang/test/CodeGen/packed-structure.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple x86_64 -emit-llvm -o - %s | opt -S -strip -o %t +// RUN: %clang_cc1 -triple x86_64 -emit-llvm -o - %s | opt -S -passes=strip -o %t // RUN: FileCheck --check-prefix=CHECK-GLOBAL < %t %s // RUN: FileCheck --check-prefix=CHECK-FUNCTIONS < %t %s diff --git a/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp b/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp --- a/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp +++ b/clang/test/CodeGenCXX/aarch64-sve-vector-conditional-op.cpp @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \ // RUN: -disable-O0-optnone \ -// RUN: -emit-llvm -o - %s | opt -S -sroa | FileCheck %s +// RUN: -emit-llvm -o - %s | opt -S -passes=sroa | FileCheck %s // REQUIRES: aarch64-registered-target diff --git a/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp b/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp --- a/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp +++ b/clang/test/CodeGenCXX/attr-likelihood-if-vs-builtin-expect.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -O1 -disable-llvm-passes -emit-llvm %s -o - -triple=x86_64-linux-gnu | opt --lower-expect -S | FileCheck %s +// RUN: %clang_cc1 -O1 -disable-llvm-passes -emit-llvm %s -o - -triple=x86_64-linux-gnu | opt -passes=lower-expect -S | FileCheck %s // Verifies the output of __builtin_expect versus the output of the likelihood // attributes. They should generate the same probabilities for the branches. diff --git a/clang/test/CodeGenCXX/catch-undef-behavior.cpp b/clang/test/CodeGenCXX/catch-undef-behavior.cpp --- a/clang/test/CodeGenCXX/catch-undef-behavior.cpp +++ b/clang/test/CodeGenCXX/catch-undef-behavior.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -std=c++11 -fsanitize=signed-integer-overflow,integer-divide-by-zero,float-divide-by-zero,shift-base,shift-exponent,unreachable,return,vla-bound,alignment,null,vptr,object-size,float-cast-overflow,bool,enum,array-bounds,function -fsanitize-recover=signed-integer-overflow,integer-divide-by-zero,float-divide-by-zero,shift-base,shift-exponent,vla-bound,alignment,null,vptr,object-size,float-cast-overflow,bool,enum,array-bounds,function -emit-llvm %s -o - -triple x86_64-linux-gnu | opt -passes=instnamer -S | FileCheck %s --check-prefixes=CHECK,CHECK-FUNCSAN +// RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -std=c++11 -fsanitize=signed-integer-overflow,integer-divide-by-zero,float-divide-by-zero,shift-base,shift-exponent,unreachable,return,vla-bound,alignment,null,vptr,object-size,float-cast-overflow,bool,enum,array-bounds,function -fsanitize-recover=signed-integer-overflow,integer-divide-by-zero,float-divide-by-zero,shift-base,shift-exponent,vla-bound,alignment,null,vptr,object-size,float-cast-overflow,bool,enum,array-bounds,function -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-FUNCSAN // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -std=c++11 -fsanitize=vptr,address -fsanitize-recover=vptr,address -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=CHECK-ASAN // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -std=c++11 -fsanitize=vptr -fsanitize-recover=vptr -emit-llvm %s -o - -triple x86_64-linux-gnu | FileCheck %s --check-prefix=DOWNCAST-NULL // RUN: %clang_cc1 -no-opaque-pointers -no-enable-noundef-analysis -std=c++11 -fsanitize=function -emit-llvm %s -o - -triple x86_64-linux-gnux32 | FileCheck %s --check-prefix=CHECK-FUNCSAN diff --git a/clang/test/CodeGenCXX/ctor-globalopt.cpp b/clang/test/CodeGenCXX/ctor-globalopt.cpp --- a/clang/test/CodeGenCXX/ctor-globalopt.cpp +++ b/clang/test/CodeGenCXX/ctor-globalopt.cpp @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -triple %itanium_abi_triple -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -triple %itanium_abi_triple -emit-llvm -o - %s -O2 | opt - -S -globalopt -o - | FileCheck %s --check-prefix=O1 +// RUN: %clang_cc1 -triple %itanium_abi_triple -emit-llvm -o - %s -O2 | opt - -S -passes=globalopt -o - | FileCheck %s --check-prefix=O1 // RUN: %clang_cc1 -triple %ms_abi_triple -emit-llvm -o - %s | FileCheck %s -// RUN: %clang_cc1 -triple %ms_abi_triple -emit-llvm -o - %s -O2 | opt - -S -globalopt -o - | FileCheck %s --check-prefix=O1 +// RUN: %clang_cc1 -triple %ms_abi_triple -emit-llvm -o - %s -O2 | opt - -S -passes=globalopt -o - | FileCheck %s --check-prefix=O1 // Check that GlobalOpt can eliminate static constructors for simple implicit // constructors. This is a targeted integration test to make sure that LLVM's diff --git a/clang/test/CodeGenCXX/for-range-temporaries.cpp b/clang/test/CodeGenCXX/for-range-temporaries.cpp --- a/clang/test/CodeGenCXX/for-range-temporaries.cpp +++ b/clang/test/CodeGenCXX/for-range-temporaries.cpp @@ -1,9 +1,9 @@ -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -std=c++11 -emit-llvm -o - -UDESUGAR %s | opt -passes=instnamer -S | FileCheck %s -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -std=c++11 -emit-llvm -o - -DDESUGAR %s | opt -passes=instnamer -S | FileCheck %s -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -std=c++11 -emit-llvm -o - -UDESUGAR -DTEMPLATE %s | opt -passes=instnamer -S | FileCheck %s -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -std=c++11 -emit-llvm -o - -DDESUGAR -DTEMPLATE %s | opt -passes=instnamer -S | FileCheck %s -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -std=c++11 -emit-llvm -o - -UDESUGAR -DTEMPLATE -DDEPENDENT %s | opt -passes=instnamer -S | FileCheck %s -// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -std=c++11 -emit-llvm -o - -DDESUGAR -DTEMPLATE -DDEPENDENT %s | opt -passes=instnamer -S | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -std=c++11 -emit-llvm -o - -UDESUGAR %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -std=c++11 -emit-llvm -o - -DDESUGAR %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -std=c++11 -emit-llvm -o - -UDESUGAR -DTEMPLATE %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -std=c++11 -emit-llvm -o - -DDESUGAR -DTEMPLATE %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -std=c++11 -emit-llvm -o - -UDESUGAR -DTEMPLATE -DDEPENDENT %s | FileCheck %s +// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -std=c++11 -emit-llvm -o - -DDESUGAR -DTEMPLATE -DDEPENDENT %s | FileCheck %s struct A { A(); diff --git a/clang/test/CodeGenCXX/virtual-base-ctor.cpp b/clang/test/CodeGenCXX/virtual-base-ctor.cpp --- a/clang/test/CodeGenCXX/virtual-base-ctor.cpp +++ b/clang/test/CodeGenCXX/virtual-base-ctor.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 %s -emit-llvm -triple %itanium_abi_triple -o - -O2 | opt - -S -globalopt -o - | FileCheck %s +// RUN: %clang_cc1 %s -emit-llvm -triple %itanium_abi_triple -o - -O2 | opt - -S -passes=globalopt -o - | FileCheck %s struct B; extern B x; diff --git a/clang/test/CodeGenCXX/windows-itanium-init-guard.cpp b/clang/test/CodeGenCXX/windows-itanium-init-guard.cpp new file mode 100644 --- /dev/null +++ b/clang/test/CodeGenCXX/windows-itanium-init-guard.cpp @@ -0,0 +1,32 @@ +// Initialisation Guard Variables should take their DLL storage class from +// the guarded variable. Otherwise, there will be a link error if the compiler +// inlines a reference to the guard variable into another module but that +// guard variable is not exported from the defining module. + +// RUN: %clang_cc1 -emit-llvm -triple i686-windows-itanium -fdeclspec %s -O1 -disable-llvm-passes -o - -DAPI= | FileCheck %s --check-prefixes=NONE +// RUN: %clang_cc1 -emit-llvm -triple i686-windows-itanium -fdeclspec %s -O1 -disable-llvm-passes -o - -DAPI="__declspec(dllexport)" | FileCheck %s --check-prefixes=EXPORT +// RUN: %clang_cc1 -emit-llvm -triple i686-windows-itanium -fdeclspec %s -O1 -disable-llvm-passes -o - -DAPI="__declspec(dllimport)" | FileCheck %s --check-prefixes=IMPORT + +// RUN: %clang_cc1 -emit-llvm -triple x86_64-scei-ps4 -fdeclspec %s -O1 -disable-llvm-passes -o - -DAPI= | FileCheck %s --check-prefixes=NONE +// RUN: %clang_cc1 -emit-llvm -triple x86_64-scei-ps4 -fdeclspec %s -O1 -disable-llvm-passes -o - -DAPI="__declspec(dllexport)" | FileCheck %s --check-prefixes=EXPORT +// RUN: %clang_cc1 -emit-llvm -triple x86_64-scei-ps4 -fdeclspec %s -O1 -disable-llvm-passes -o - -DAPI="__declspec(dllimport)" | FileCheck %s --check-prefixes=IMPORT + +// RUN: %clang_cc1 -emit-llvm -triple x86_64-scei-ps5 -fdeclspec %s -O1 -disable-llvm-passes -o - -DAPI= | FileCheck %s --check-prefixes=NONE +// RUN: %clang_cc1 -emit-llvm -triple x86_64-scei-ps5 -fdeclspec %s -O1 -disable-llvm-passes -o - -DAPI="__declspec(dllexport)" | FileCheck %s --check-prefixes=EXPORT +// RUN: %clang_cc1 -emit-llvm -triple x86_64-scei-ps5 -fdeclspec %s -O1 -disable-llvm-passes -o - -DAPI="__declspec(dllimport)" | FileCheck %s --check-prefixes=IMPORT + +//NONE: @_ZZN3foo3GetEvE9Singleton = linkonce_odr {{(dso_local )?}}global +//NONE: @_ZGVZN3foo3GetEvE9Singleton = linkonce_odr {{(dso_local )?}}global + +//EXPORT: @_ZZN3foo3GetEvE9Singleton = weak_odr {{(dso_local )?}}dllexport global +//EXPORT: @_ZGVZN3foo3GetEvE9Singleton = weak_odr {{(dso_local )?}}dllexport global + +//IMPORT: @_ZZN3foo3GetEvE9Singleton = available_externally dllimport global +//IMPORT: @_ZGVZN3foo3GetEvE9Singleton = available_externally dllimport global + +struct API foo { + foo() {} + static void Get() { static foo Singleton; } +}; + +void f() { foo::Get(); } diff --git a/clang/test/CodeGenOpenCL/atomic-ops.cl b/clang/test/CodeGenOpenCL/atomic-ops.cl --- a/clang/test/CodeGenOpenCL/atomic-ops.cl +++ b/clang/test/CodeGenOpenCL/atomic-ops.cl @@ -1,10 +1,10 @@ // RUN: %clang_cc1 -no-opaque-pointers %s -cl-std=CL2.0 -emit-llvm -O0 -o - -triple=amdgcn-amd-amdhsa \ -// RUN: | opt -passes=instnamer -S | FileCheck %s +// RUN: | FileCheck %s // Also test serialization of atomic operations here, to avoid duplicating the test. // RUN: %clang_cc1 -no-opaque-pointers %s -cl-std=CL2.0 -emit-pch -O0 -o %t -triple=amdgcn-amd-amdhsa // RUN: %clang_cc1 -no-opaque-pointers %s -cl-std=CL2.0 -include-pch %t -O0 -triple=amdgcn-amd-amdhsa \ -// RUN: -emit-llvm -o - | opt -passes=instnamer -S | FileCheck %s +// RUN: -emit-llvm -o - | FileCheck %s #ifndef ALREADY_INCLUDED #define ALREADY_INCLUDED diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11.cl @@ -37,3 +37,9 @@ void test_permlane64(global uint* out, uint a) { *out = __builtin_amdgcn_permlane64(a); } + +// CHECK-LABEL: @test_s_wait_event_export_ready +// CHECK: call void @llvm.amdgcn.s.wait.event.export.ready +void test_s_wait_event_export_ready() { + __builtin_amdgcn_s_wait_event_export_ready(); +} diff --git a/clang/test/CodeGenOpenCL/convergent.cl b/clang/test/CodeGenOpenCL/convergent.cl --- a/clang/test/CodeGenOpenCL/convergent.cl +++ b/clang/test/CodeGenOpenCL/convergent.cl @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple spir-unknown-unknown -emit-llvm %s -o - | opt -passes=instnamer -S | FileCheck -enable-var-scope %s +// RUN: %clang_cc1 -triple spir-unknown-unknown -emit-llvm %s -o - | FileCheck -enable-var-scope %s // This is initially assumed convergent, but can be deduced to not require it. diff --git a/clang/test/Driver/aarch64-lrcpc3.c b/clang/test/Driver/aarch64-lrcpc3.c new file mode 100644 --- /dev/null +++ b/clang/test/Driver/aarch64-lrcpc3.c @@ -0,0 +1,26 @@ +// Test that target feature FEAT_RCPC3 is implemented and available correctly + +// FEAT_RCPC3 is optional for v8.2a onwards, and can be enabled with +rcpc3 +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+rcpc3 %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.9-a+norcpc3 %s 2>&1 | FileCheck %s --check-prefix=DISABLED +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+rcpc3 %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9.4-a+norcpc3 %s 2>&1 | FileCheck %s --check-prefix=DISABLED + +// FEAT_RCPC3 is optional (off by default) for v8.8a/9.3a and older, and can be enabled using +rcpc3 +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.2-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.2-a+rcpc3 %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.2-a+norcpc3 %s 2>&1 | FileCheck %s --check-prefix=DISABLED +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9-a %s 2>&1 | FileCheck %s --check-prefix=NOT_ENABLED +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9-a+rcpc3 %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv9-a+norcpc3 %s 2>&1 | FileCheck %s --check-prefix=DISABLED + +// FEAT_RCPC3 is invalid before v8 +// RUN: %clang -### -target arm-none-none-eabi -march=armv7-a+rcpc3 %s 2>&1 | FileCheck %s --check-prefix=INVALID + +// INVALID: error: unsupported argument 'armv7-a+rcpc3' to option '-march=' +// ENABLED: "-target-feature" "+rcpc3" +// NOT_ENABLED-NOT: "-target-feature" "+rcpc3" +// DISABLED: "-target-feature" "-rcpc3" + diff --git a/clang/test/FixIt/fixit-function-call.cpp b/clang/test/FixIt/fixit-function-call.cpp --- a/clang/test/FixIt/fixit-function-call.cpp +++ b/clang/test/FixIt/fixit-function-call.cpp @@ -115,4 +115,25 @@ u(c); } +void accept_void(void*); + +void issue58958(const char* a, volatile char * v, const volatile char * cv) { +// CHECK: no matching function for call to 'accept_void' +// CHECK-NOT: take the address of the argument with & + accept_void(a); +// CHECK: no matching function for call to 'accept_void' +// CHECK-NOT: take the address of the argument with & + accept_void(v); +// CHECK: no matching function for call to 'accept_void' +// CHECK-NOT: take the address of the argument with & + accept_void(cv); + char b; +// CHECK: no matching function for call to 'accept_void' +// CHECK: take the address of the argument with & + accept_void(b); +// CHECK-NOT: no matching function for call to 'accept_void' +// CHECK-NOT: take the address of the argument with & + accept_void(&b); +} + // CHECK: errors generated diff --git a/clang/test/Modules/embed-files-compressed.cpp b/clang/test/Modules/embed-files-compressed.cpp --- a/clang/test/Modules/embed-files-compressed.cpp +++ b/clang/test/Modules/embed-files-compressed.cpp @@ -1,4 +1,4 @@ -// REQUIRES: zlib +// REQUIRES: zlib || zstd // REQUIRES: shell // // RUN: rm -rf %t diff --git a/clang/test/Modules/override.m b/clang/test/Modules/override.m new file mode 100644 --- /dev/null +++ b/clang/test/Modules/override.m @@ -0,0 +1,69 @@ +// UNSUPPORTED: -aix +// RUN: rm -rf %t +// RUN: split-file %s %t +// RUN: %clang_cc1 -fsyntax-only -I%t/include %t/test.m \ +// RUN: -fmodules -fimplicit-module-maps -fmodules-cache-path=%t/modules.cache -fmodule-name=CheckOverride + +// Test that if we have the same method in a different module, it's not an +// override as it is the same method and it has the same DeclContext but a +// different object in the memory. + + +//--- include/CheckOverride.h +@interface NSObject +@end + +@interface CheckOverrideInterfaceOnly: NSObject +- (void)potentialOverrideInterfaceOnly; +@end + +@interface CheckOverrideCategoryOnly: NSObject +@end +@interface CheckOverrideCategoryOnly(CategoryOnly) +- (void)potentialOverrideCategoryOnly; +@end + +@interface CheckOverrideImplementationOfInterface: NSObject +- (void)potentialOverrideImplementationOfInterface; +@end + +@interface CheckOverrideImplementationOfCategory: NSObject +@end +@interface CheckOverrideImplementationOfCategory(CategoryImpl) +- (void)potentialOverrideImplementationOfCategory; +@end + +//--- include/Redirect.h +// Ensure CheckOverride is imported as the module despite all `-fmodule-name` flags. +#import + +//--- include/module.modulemap +module CheckOverride { + header "CheckOverride.h" +} +module Redirect { + header "Redirect.h" + export * +} + +//--- test.m +#import +#import + +@implementation CheckOverrideImplementationOfInterface +- (void)potentialOverrideImplementationOfInterface {} +@end + +@implementation CheckOverrideImplementationOfCategory +- (void)potentialOverrideImplementationOfCategory {} +@end + +void triggerOverrideCheck(CheckOverrideInterfaceOnly *intfOnly, + CheckOverrideCategoryOnly *catOnly, + CheckOverrideImplementationOfInterface *intfImpl, + CheckOverrideImplementationOfCategory *catImpl) { + [intfOnly potentialOverrideInterfaceOnly]; + [catOnly potentialOverrideCategoryOnly]; + [intfImpl potentialOverrideImplementationOfInterface]; + [catImpl potentialOverrideImplementationOfCategory]; +} diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -42,6 +42,7 @@ // CHECK-NOT: __riscv_svnapot // CHECK-NOT: __riscv_svinval // CHECK-NOT: __riscv_xventanacondops +// CHECK-NOT: __riscv_zcd // CHECK-NOT: __riscv_zcf // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \ @@ -439,6 +440,12 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-XVENTANACONDOPS-EXT %s // CHECK-XVENTANACONDOPS-EXT: __riscv_xventanacondops 1000000{{$}} +// RUN: %clang -target riscv32 -march=rv32izcd0p70 -menable-experimental-extensions \ +// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s +// RUN: %clang -target riscv64 -march=rv64izcd0p70 -menable-experimental-extensions \ +// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s +// CHECK-ZCD-EXT: __riscv_zcd 70000{{$}} + // RUN: %clang -target riscv32 -march=rv32izcf0p70 -menable-experimental-extensions \ // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCF-EXT %s // CHECK-ZCF-EXT: __riscv_zcf 70000{{$}} diff --git a/clang/tools/clang-fuzzer/handle-llvm/CMakeLists.txt b/clang/tools/clang-fuzzer/handle-llvm/CMakeLists.txt --- a/clang/tools/clang-fuzzer/handle-llvm/CMakeLists.txt +++ b/clang/tools/clang-fuzzer/handle-llvm/CMakeLists.txt @@ -4,10 +4,12 @@ Core ExecutionEngine IPO + IRPrinter IRReader MC MCJIT Object + Passes RuntimeDyld SelectionDAG Support diff --git a/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp b/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp --- a/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp +++ b/clang/tools/clang-fuzzer/handle-llvm/handle_llvm.cpp @@ -30,34 +30,28 @@ #include "llvm/ExecutionEngine/SectionMemoryManager.h" #include "llvm/IR/IRPrintingPasses.h" #include "llvm/IR/LLVMContext.h" -#include "llvm/IR/LegacyPassManager.h" -#include "llvm/IR/LegacyPassNameParser.h" #include "llvm/IR/Module.h" #include "llvm/IR/Verifier.h" +#include "llvm/IRPrinter/IRPrintingPasses.h" #include "llvm/IRReader/IRReader.h" #include "llvm/MC/TargetRegistry.h" -#include "llvm/Pass.h" -#include "llvm/PassRegistry.h" +#include "llvm/Passes/OptimizationLevel.h" +#include "llvm/Passes/PassBuilder.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/TargetSelect.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Transforms/IPO.h" -#include "llvm/Transforms/IPO/PassManagerBuilder.h" -#include "llvm/Transforms/Vectorize.h" using namespace llvm; -static codegen::RegisterCodeGenFlags CGF; - // Define a type for the functions that are compiled and executed typedef void (*LLVMFunc)(int*, int*, int*, int); // Helper function to parse command line args and find the optimization level -static void getOptLevel(const std::vector &ExtraArgs, - CodeGenOpt::Level &OLvl) { +static CodeGenOpt::Level +getOptLevel(const std::vector &ExtraArgs) { // Find the optimization level from the command line args - OLvl = CodeGenOpt::Default; + CodeGenOpt::Level OLvl = CodeGenOpt::Default; for (auto &A : ExtraArgs) { if (A[0] == '-' && A[1] == 'O') { switch(A[2]) { @@ -71,6 +65,7 @@ } } } + return OLvl; } static void ErrorAndExit(std::string message) { @@ -80,16 +75,45 @@ // Helper function to add optimization passes to the TargetMachine at the // specified optimization level, OptLevel -static void AddOptimizationPasses(legacy::PassManagerBase &MPM, - CodeGenOpt::Level OptLevel, - unsigned SizeLevel) { - // Create and initialize a PassManagerBuilder - PassManagerBuilder Builder; - Builder.OptLevel = OptLevel; - Builder.SizeLevel = SizeLevel; - Builder.Inliner = createFunctionInliningPass(OptLevel, SizeLevel, false); - Builder.LoopVectorize = true; - Builder.populateModulePassManager(MPM); +static void RunOptimizationPasses(raw_ostream &OS, Module &M, + CodeGenOpt::Level OptLevel) { + llvm::OptimizationLevel OL; + switch (OptLevel) { + case CodeGenOpt::None: + OL = OptimizationLevel::O0; + break; + case CodeGenOpt::Less: + OL = OptimizationLevel::O1; + break; + case CodeGenOpt::Default: + OL = OptimizationLevel::O2; + break; + case CodeGenOpt::Aggressive: + OL = OptimizationLevel::O3; + break; + } + + LoopAnalysisManager LAM; + FunctionAnalysisManager FAM; + CGSCCAnalysisManager CGAM; + ModuleAnalysisManager MAM; + + PassBuilder PB; + + PB.registerModuleAnalyses(MAM); + PB.registerCGSCCAnalyses(CGAM); + PB.registerFunctionAnalyses(FAM); + PB.registerLoopAnalyses(LAM); + PB.crossRegisterProxies(LAM, FAM, CGAM, MAM); + + ModulePassManager MPM; + if (OL == OptimizationLevel::O0) + MPM = PB.buildO0DefaultPipeline(OL); + else + MPM = PB.buildPerModuleDefaultPipeline(OL); + MPM.addPass(PrintModulePass(OS)); + + MPM.run(M, MAM); } // Mimics the opt tool to run an optimization pass over the provided IR @@ -120,24 +144,10 @@ codegen::setFunctionAttributes(codegen::getCPUStr(), codegen::getFeaturesStr(), *M); - legacy::PassManager Passes; - - Passes.add(new TargetLibraryInfoWrapperPass(ModuleTriple)); - Passes.add(createTargetTransformInfoWrapperPass(TM->getTargetIRAnalysis())); - - LLVMTargetMachine <M = static_cast(*TM); - Passes.add(LTM.createPassConfig(Passes)); - - Passes.add(createVerifierPass()); - - AddOptimizationPasses(Passes, OLvl, 0); - // Add a pass that writes the optimized IR to an output stream std::string outString; raw_string_ostream OS(outString); - Passes.add(createPrintModulePass(OS, "", false)); - - Passes.run(*M); + RunOptimizationPasses(OS, *M, OLvl); return outString; } @@ -216,8 +226,7 @@ memcpy(UnoptArrays, InputArrays, kTotalSize); // Parse ExtraArgs to set the optimization level - CodeGenOpt::Level OLvl; - getOptLevel(ExtraArgs, OLvl); + CodeGenOpt::Level OLvl = getOptLevel(ExtraArgs); // First we optimize the IR by running a loop vectorizer pass std::string OptIR = OptLLVM(IR, OLvl); diff --git a/clang/unittests/Format/FormatTestCSharp.cpp b/clang/unittests/Format/FormatTestCSharp.cpp --- a/clang/unittests/Format/FormatTestCSharp.cpp +++ b/clang/unittests/Format/FormatTestCSharp.cpp @@ -1600,5 +1600,9 @@ Style); } +TEST_F(FormatTestCSharp, BrokenBrackets) { + EXPECT_NE("", format("int where b <")); // reduced from crasher +} + } // namespace format } // end namespace clang diff --git a/clang/unittests/Format/MacroCallReconstructorTest.cpp b/clang/unittests/Format/MacroCallReconstructorTest.cpp --- a/clang/unittests/Format/MacroCallReconstructorTest.cpp +++ b/clang/unittests/Format/MacroCallReconstructorTest.cpp @@ -97,12 +97,20 @@ Matcher(const TokenList &Tokens, TestLexer &Lex) : Tokens(Tokens), It(this->Tokens.begin()), Lex(Lex) {} + bool tokenMatches(const FormatToken *Left, const FormatToken *Right) { + if (Left->getType() == Right->getType() && + Left->TokenText == Right->TokenText) { + return true; + } + llvm::dbgs() << Left->TokenText << " != " << Right->TokenText << "\n"; + return false; + } + Chunk consume(StringRef Tokens) { TokenList Result; for (const FormatToken *Token : uneof(Lex.lex(Tokens))) { (void)Token; // Fix unused variable warning when asserts are disabled. - assert((*It)->getType() == Token->getType() && - (*It)->TokenText == Token->TokenText); + assert(tokenMatches(*It, Token)); Result.push_back(*It); ++It; } diff --git a/clang/unittests/Lex/HeaderSearchTest.cpp b/clang/unittests/Lex/HeaderSearchTest.cpp --- a/clang/unittests/Lex/HeaderSearchTest.cpp +++ b/clang/unittests/Lex/HeaderSearchTest.cpp @@ -150,6 +150,14 @@ "z"); } +TEST_F(HeaderSearchTest, BothDotDots) { + addSearchDir("/x/../y/"); + EXPECT_EQ(Search.suggestPathToFileForDiagnostics("/x/../y/z", + /*WorkingDir=*/"", + /*MainFile=*/""), + "z"); +} + TEST_F(HeaderSearchTest, IncludeFromSameDirectory) { EXPECT_EQ(Search.suggestPathToFileForDiagnostics("/y/z/t.h", /*WorkingDir=*/"", diff --git a/clang/unittests/Sema/ExternalSemaSourceTest.cpp b/clang/unittests/Sema/ExternalSemaSourceTest.cpp --- a/clang/unittests/Sema/ExternalSemaSourceTest.cpp +++ b/clang/unittests/Sema/ExternalSemaSourceTest.cpp @@ -121,7 +121,7 @@ CurrentSema->getPreprocessor().getIdentifierInfo(CorrectTo); NamespaceDecl *NewNamespace = NamespaceDecl::Create(Context, DestContext, false, Typo.getBeginLoc(), - Typo.getLoc(), ToIdent, nullptr); + Typo.getLoc(), ToIdent, nullptr, false); DestContext->addDecl(NewNamespace); TypoCorrection Correction(ToIdent); Correction.addCorrectionDecl(NewNamespace); diff --git a/clang/unittests/Tooling/CompilationDatabaseTest.cpp b/clang/unittests/Tooling/CompilationDatabaseTest.cpp --- a/clang/unittests/Tooling/CompilationDatabaseTest.cpp +++ b/clang/unittests/Tooling/CompilationDatabaseTest.cpp @@ -642,7 +642,7 @@ TEST(ParseFixedCompilationDatabase, HandlesPositionalArgs) { const char *Argv[] = {"1", "2", "--", "-c", "somefile.cpp", "-DDEF3"}; - int Argc = sizeof(Argv) / sizeof(char*); + int Argc = std::size(Argv); std::string ErrorMsg; std::unique_ptr Database = FixedCompilationDatabase::loadFromCommandLine(Argc, Argv, ErrorMsg); @@ -677,7 +677,7 @@ TEST(ParseFixedCompilationDatabase, HandlesArgv0) { const char *Argv[] = {"1", "2", "--", "mytool", "somefile.cpp"}; - int Argc = sizeof(Argv) / sizeof(char*); + int Argc = std::size(Argv); std::string ErrorMsg; std::unique_ptr Database = FixedCompilationDatabase::loadFromCommandLine(Argc, Argv, ErrorMsg); diff --git a/clang/unittests/Tooling/HeaderAnalysisTest.cpp b/clang/unittests/Tooling/HeaderAnalysisTest.cpp --- a/clang/unittests/Tooling/HeaderAnalysisTest.cpp +++ b/clang/unittests/Tooling/HeaderAnalysisTest.cpp @@ -9,11 +9,14 @@ #include "clang/Tooling/Inclusions/HeaderAnalysis.h" #include "clang/Lex/Preprocessor.h" #include "clang/Testing/TestAST.h" +#include "llvm/Testing/Support/SupportHelpers.h" #include "gtest/gtest.h" namespace clang { namespace tooling { namespace { +using llvm::ValueIs; +using testing::Eq; TEST(HeaderAnalysisTest, IsSelfContained) { TestInputs Inputs; @@ -58,6 +61,19 @@ EXPECT_FALSE(isSelfContainedHeader(FM.getFile("bad.h").get(), SM, HI)); } +TEST(HeaderAnalysisTest, ParseIWYUPragma) { + EXPECT_THAT(parseIWYUPragma("// IWYU pragma: keep"), ValueIs(Eq("keep"))); + EXPECT_THAT(parseIWYUPragma("// IWYU pragma: keep me\netc"), + ValueIs(Eq("keep me"))); + EXPECT_THAT(parseIWYUPragma("/* IWYU pragma: keep */"), ValueIs(Eq("keep"))); + EXPECT_EQ(parseIWYUPragma("// IWYU pragma: keep"), llvm::None) + << "Prefix is sensitive to whitespace"; + EXPECT_EQ(parseIWYUPragma("// IWYU pragma:keep"), llvm::None) + << "Prefix is sensitive to whitespace"; + EXPECT_EQ(parseIWYUPragma("/\n* IWYU pragma: keep */"), llvm::None) + << "Must start with /* or //"; +} + } // namespace } // namespace tooling } // namespace clang diff --git a/clang/unittests/libclang/LibclangTest.cpp b/clang/unittests/libclang/LibclangTest.cpp --- a/clang/unittests/libclang/LibclangTest.cpp +++ b/clang/unittests/libclang/LibclangTest.cpp @@ -517,7 +517,7 @@ std::string ModulesCache = std::string("-fmodules-cache-path=") + TestDir; const char *Args[] = { "-fmodules", ModulesCache.c_str(), "-I", TestDir.c_str() }; - int NumArgs = sizeof(Args) / sizeof(Args[0]); + int NumArgs = std::size(Args); ClangTU = clang_parseTranslationUnit(Index, MName.c_str(), Args, NumArgs, nullptr, 0, TUFlags); EXPECT_EQ(1U, clang_getNumDiagnostics(ClangTU)); @@ -557,7 +557,7 @@ EXPECT_EQ(CXError_Success, clang_parseTranslationUnit2FullArgv(Index, Filename.c_str(), Argv, - sizeof(Argv) / sizeof(Argv[0]), + std::size(Argv), nullptr, 0, TUFlags, &ClangTU)); EXPECT_EQ(0U, clang_getNumDiagnostics(ClangTU)); DisplayDiagnostics(); @@ -706,7 +706,7 @@ const char *Argv[] = {"-xc++-header", "-std=c++11"}; ClangTU = clang_parseTranslationUnit(Index, HeaderName.c_str(), Argv, - sizeof(Argv) / sizeof(Argv[0]), nullptr, + std::size(Argv), nullptr, 0, TUFlags); auto CheckTokenKinds = [=]() { diff --git a/clang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp b/clang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp --- a/clang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp +++ b/clang/utils/TableGen/ClangOpenCLBuiltinEmitter.cpp @@ -598,7 +598,7 @@ } unsigned VersionIDs[] = {100, 110, 120, 200, 300}; - for (unsigned I = 0; I < sizeof(VersionIDs) / sizeof(VersionIDs[0]); I++) { + for (unsigned I = 0; I < std::size(VersionIDs); I++) { if (VersionIDs[I] >= MinVersion && VersionIDs[I] < MaxVersion) { Encoded |= 1 << I; } diff --git a/compiler-rt/lib/asan/asan_poisoning.cpp b/compiler-rt/lib/asan/asan_poisoning.cpp --- a/compiler-rt/lib/asan/asan_poisoning.cpp +++ b/compiler-rt/lib/asan/asan_poisoning.cpp @@ -370,6 +370,37 @@ PoisonAlignedStackMemory(addr, size, false); } +static void FixUnalignedStorage(uptr storage_beg, uptr storage_end, + uptr &old_end, uptr &new_end) { + constexpr uptr granularity = ASAN_SHADOW_GRANULARITY; + if (UNLIKELY(!AddrIsAlignedByGranularity(storage_end))) { + uptr end_down = RoundDownTo(storage_end, granularity); + // Ignore the last unaligned granule if the storage is followed by + // unpoisoned byte, because we can't poison the prefix anyway. Don't call + // AddressIsPoisoned at all if container changes does not affect the last + // granule at all. + if (Max(old_end, new_end) > end_down && !AddressIsPoisoned(storage_end)) { + old_end = Min(end_down, old_end); + new_end = Min(end_down, new_end); + } + } + + // Handle misaligned begin and cut it off. + if (UNLIKELY(!AddrIsAlignedByGranularity(storage_beg))) { + uptr beg_up = RoundUpTo(storage_beg, granularity); + // The first unaligned granule needs special handling only if we had bytes + // there before and will have none after. + if (storage_beg == new_end && storage_beg != old_end && + storage_beg < beg_up) { + // Keep granule prefix outside of the storage unpoisoned. + uptr beg_down = RoundDownTo(storage_beg, granularity); + *(u8 *)MemToShadow(beg_down) = storage_beg - beg_down; + old_end = Max(beg_up, old_end); + new_end = Max(beg_up, new_end); + } + } +} + void __sanitizer_annotate_contiguous_container(const void *beg_p, const void *end_p, const void *old_mid_p, @@ -378,71 +409,28 @@ return; VPrintf(2, "contiguous_container: %p %p %p %p\n", beg_p, end_p, old_mid_p, new_mid_p); - uptr beg = reinterpret_cast(beg_p); - uptr end = reinterpret_cast(end_p); - uptr old_mid = reinterpret_cast(old_mid_p); - uptr new_mid = reinterpret_cast(new_mid_p); + uptr storage_beg = reinterpret_cast(beg_p); + uptr storage_end = reinterpret_cast(end_p); + uptr old_end = reinterpret_cast(old_mid_p); + uptr new_end = reinterpret_cast(new_mid_p); uptr granularity = ASAN_SHADOW_GRANULARITY; - if (!(beg <= old_mid && beg <= new_mid && old_mid <= end && new_mid <= end)) { + if (!(storage_beg <= old_end && storage_beg <= new_end && + old_end <= storage_end && new_end <= storage_end)) { GET_STACK_TRACE_FATAL_HERE; - ReportBadParamsToAnnotateContiguousContainer(beg, end, old_mid, new_mid, - &stack); + ReportBadParamsToAnnotateContiguousContainer(storage_beg, storage_end, + old_end, new_end, &stack); } - CHECK_LE(end - beg, + CHECK_LE(storage_end - storage_beg, FIRST_32_SECOND_64(1UL << 30, 1ULL << 40)); // Sanity check. - if (old_mid == new_mid) + if (old_end == new_end) return; // Nothing to do here. - // Handle misaligned end and cut it off. - if (UNLIKELY(!AddrIsAlignedByGranularity(end))) { - uptr end_down = RoundDownTo(end, granularity); - // Either new or old mid must be in the granule to affect it. - if (new_mid > end_down || old_mid > end_down) { - // Do nothing if the byte after the container is unpoisoned. Asan can't - // poison only the begining of the granule. - if (AddressIsPoisoned(end)) { - *(u8 *)MemToShadow(end_down) = new_mid > end_down - ? static_cast(new_mid - end_down) - : kAsanContiguousContainerOOBMagic; - } - old_mid = Min(end_down, old_mid); - new_mid = Min(end_down, new_mid); - - if (old_mid == new_mid) - return; - } - - if (beg >= end_down) - return; // Same granule. - - end = end_down; - } - - // Handle misaligned begin and cut it off. - if (UNLIKELY(!AddrIsAlignedByGranularity(beg))) { - uptr beg_up = RoundUpTo(beg, granularity); - // As soon as we add first byte into container we will not be able to - // determine the state of the byte before the container. So we assume it's - // always unpoison. - - // Either new or old mid must be in the granule to affect it. - if (new_mid < beg_up || old_mid < beg_up) { - uptr beg_down = RoundDownTo(beg, granularity); - *(u8 *)MemToShadow(beg_down) = - new_mid < beg_up ? static_cast(new_mid - beg_down) : 0; - old_mid = Max(beg_up, old_mid); - new_mid = Max(beg_up, new_mid); - if (old_mid == new_mid) - return; - } + FixUnalignedStorage(storage_beg, storage_end, old_end, new_end); - beg = beg_up; - } - - uptr a = RoundDownTo(Min(old_mid, new_mid), granularity); - uptr c = RoundUpTo(Max(old_mid, new_mid), granularity); - uptr d1 = RoundDownTo(old_mid, granularity); + uptr a = RoundDownTo(Min(old_end, new_end), granularity); + uptr c = RoundUpTo(Max(old_end, new_end), granularity); + uptr d1 = RoundDownTo(old_end, granularity); // uptr d2 = RoundUpTo(old_mid, granularity); // Currently we should be in this state: // [a, d1) is good, [d2, c) is bad, [d1, d2) is partially good. @@ -458,8 +446,8 @@ // CHECK_EQ(*(u8 *)MemToShadow(c - granularity), // kAsanContiguousContainerOOBMagic); - uptr b1 = RoundDownTo(new_mid, granularity); - uptr b2 = RoundUpTo(new_mid, granularity); + uptr b1 = RoundDownTo(new_end, granularity); + uptr b2 = RoundUpTo(new_end, granularity); // New state: // [a, b1) is good, [b2, c) is bad, [b1, b2) is partially good. if (b1 > a) @@ -468,7 +456,7 @@ PoisonShadow(b2, c - b2, kAsanContiguousContainerOOBMagic); if (b1 != b2) { CHECK_EQ(b2 - b1, granularity); - *(u8 *)MemToShadow(b1) = static_cast(new_mid - b1); + *(u8 *)MemToShadow(b1) = static_cast(new_end - b1); } } @@ -504,6 +492,12 @@ ReportBadParamsToAnnotateDoubleEndedContiguousContainer( storage_beg, storage_end, old_beg, old_end, new_beg, new_end, &stack); } + CHECK_LE(storage_end - storage_beg, + FIRST_32_SECOND_64(1UL << 30, 1ULL << 40)); // Sanity check. + + if ((old_beg == old_end && new_beg == new_end) || + (old_beg == new_beg && old_end == new_end)) + return; // Nothing to do here. // Right now, the function does not support: // - unaligned storage beginning @@ -525,9 +519,6 @@ } if (old_beg != new_beg) { - CHECK_LE(storage_end - storage_beg, - FIRST_32_SECOND_64(1UL << 30, 1ULL << 40)); // Sanity check. - // There are two situations: we are poisoning or unpoisoning. // WARNING: at the moment we do not poison prefixes of blocks described by // one byte in shadow memory, so we have to unpoison prefixes of blocks with @@ -578,9 +569,6 @@ } if (old_end != new_end) { - CHECK_LE(storage_end - storage_beg, - FIRST_32_SECOND_64(1UL << 30, 1ULL << 40)); // Sanity check. - if (old_end < new_end) { // We are unpoisoning memory uptr a = RoundDownTo(old_end, granularity); uptr c = RoundDownTo(new_end, granularity); @@ -614,6 +602,22 @@ } } +static const void *FindBadAddress(uptr begin, uptr end, bool poisoned) { + CHECK_LE(begin, end); + constexpr uptr kMaxRangeToCheck = 32; + if (end - begin > kMaxRangeToCheck * 2) { + if (auto *bad = FindBadAddress(begin, begin + kMaxRangeToCheck, poisoned)) + return bad; + if (auto *bad = FindBadAddress(end - kMaxRangeToCheck, end, poisoned)) + return bad; + } + + for (uptr i = begin; i < end; ++i) + if (AddressIsPoisoned(i) != poisoned) + return reinterpret_cast(i); + return nullptr; +} + const void *__sanitizer_contiguous_container_find_bad_address( const void *beg_p, const void *mid_p, const void *end_p) { if (!flags()->detect_container_overflow) @@ -621,35 +625,22 @@ uptr granularity = ASAN_SHADOW_GRANULARITY; uptr beg = reinterpret_cast(beg_p); uptr end = reinterpret_cast(end_p); + uptr mid = reinterpret_cast(mid_p); + CHECK_LE(beg, mid); + CHECK_LE(mid, end); + // If the byte after the storage is unpoisoned, everything in the granule + // before must stay unpoisoned. uptr annotations_end = (!AddrIsAlignedByGranularity(end) && !AddressIsPoisoned(end)) ? RoundDownTo(end, granularity) : end; - uptr mid = reinterpret_cast(mid_p); - CHECK_LE(beg, mid); - CHECK_LE(mid, end); - // Check some bytes starting from storage_beg, some bytes around mid, and some - // bytes ending with end. - uptr kMaxRangeToCheck = 32; - uptr r1_beg = beg; - uptr r1_end = Min(beg + kMaxRangeToCheck, mid); - uptr r2_beg = Max(beg, mid - kMaxRangeToCheck); - uptr r2_end = Min(annotations_end, mid + kMaxRangeToCheck); - uptr r3_beg = Max(annotations_end - kMaxRangeToCheck, mid); - uptr r3_end = annotations_end; - for (uptr i = r1_beg; i < r1_end; i++) - if (AddressIsPoisoned(i)) - return reinterpret_cast(i); - for (uptr i = r2_beg; i < mid; i++) - if (AddressIsPoisoned(i)) - return reinterpret_cast(i); - for (uptr i = mid; i < r2_end; i++) - if (!AddressIsPoisoned(i)) - return reinterpret_cast(i); - for (uptr i = r3_beg; i < r3_end; i++) - if (!AddressIsPoisoned(i)) - return reinterpret_cast(i); - return nullptr; + beg = Min(beg, annotations_end); + mid = Min(mid, annotations_end); + if (auto *bad = FindBadAddress(beg, mid, false)) + return bad; + if (auto *bad = FindBadAddress(mid, annotations_end, true)) + return bad; + return FindBadAddress(annotations_end, end, false); } int __sanitizer_verify_contiguous_container(const void *beg_p, @@ -662,58 +653,35 @@ const void *__sanitizer_double_ended_contiguous_container_find_bad_address( const void *storage_beg_p, const void *container_beg_p, const void *container_end_p, const void *storage_end_p) { + if (!flags()->detect_container_overflow) + return nullptr; uptr granularity = ASAN_SHADOW_GRANULARITY; - // This exists to verify double ended containers. - // We assume that such collection's internal memory layout - // consists of contiguous blocks: - // [a; b) [b; c) [c; d) - // where - // a - beginning address of contiguous memory block, - // b - beginning address of contiguous memory in use - // (address of the first element in the block) - // c - end address of contiguous memory in use - // (address just after the last element in the block) - // d - end address of contiguous memory block - // [a; b) - poisoned - // [b; c) - accessible - // [c; d) - poisoned - // WARNING: We can't poison [a; b) fully in all cases. - // This is because the current shadow memory encoding - // does not allow for marking/poisoning that a prefix - // of an 8-byte block (or, ASAN_SHADOW_GRANULARITY sized block) - // cannot be used by the instrumented program. It only has the - // 01, 02, 03, 04, 05, 06, 07 and 00 encodings - // for usable/addressable memory - // (where 00 means that the whole 8-byte block can be used). - // - // This means that there are cases where not whole of the [a; b) - // region is poisoned and instead only the [a; RoundDown(b)) - // region is poisoned and we may not detect invalid memory accesses on - // [RegionDown(b), b). - // This is an inherent design limitation of how AddressSanitizer granularity - // and shadow memory encoding works at the moment. - - // If empty, storage_beg_p == container_beg_p == container_end_p - - const void *a = storage_beg_p; - // We do not suport poisoning prefixes of blocks, so - // memory in the first block with data in us, - // just before container beginning cannot be poisoned, as described above. - const void *b = reinterpret_cast( - RoundDownTo(reinterpret_cast(container_beg_p), granularity)); - const void *c = container_end_p; - const void *d = storage_end_p; - if (container_beg_p == container_end_p) - return __sanitizer_contiguous_container_find_bad_address(a, a, d); - const void *result; - if (a < b && - (result = __sanitizer_contiguous_container_find_bad_address(a, a, b))) - return result; - if (b < d && - (result = __sanitizer_contiguous_container_find_bad_address(b, c, d))) - return result; - - return nullptr; + uptr storage_beg = reinterpret_cast(storage_beg_p); + uptr storage_end = reinterpret_cast(storage_end_p); + uptr beg = reinterpret_cast(container_beg_p); + uptr end = reinterpret_cast(container_end_p); + + // The prefix of the firs granule of the container is unpoisoned. + if (beg != end) + beg = Max(storage_beg, RoundDownTo(beg, granularity)); + + // If the byte after the storage is unpoisoned, the prefix of the last granule + // is unpoisoned. + uptr annotations_end = (!AddrIsAlignedByGranularity(storage_end) && + !AddressIsPoisoned(storage_end)) + ? RoundDownTo(storage_end, granularity) + : storage_end; + storage_beg = Min(storage_beg, annotations_end); + beg = Min(beg, annotations_end); + end = Min(end, annotations_end); + + if (auto *bad = FindBadAddress(storage_beg, beg, true)) + return bad; + if (auto *bad = FindBadAddress(beg, end, false)) + return bad; + if (auto *bad = FindBadAddress(end, annotations_end, true)) + return bad; + return FindBadAddress(annotations_end, storage_end, false); } int __sanitizer_verify_double_ended_contiguous_container( diff --git a/compiler-rt/lib/memprof/memprof_allocator.cpp b/compiler-rt/lib/memprof/memprof_allocator.cpp --- a/compiler-rt/lib/memprof/memprof_allocator.cpp +++ b/compiler-rt/lib/memprof/memprof_allocator.cpp @@ -26,19 +26,13 @@ #include "sanitizer_common/sanitizer_errno.h" #include "sanitizer_common/sanitizer_file.h" #include "sanitizer_common/sanitizer_flags.h" -#include "sanitizer_common/sanitizer_interface_internal.h" #include "sanitizer_common/sanitizer_internal_defs.h" -#include "sanitizer_common/sanitizer_list.h" #include "sanitizer_common/sanitizer_procmaps.h" #include "sanitizer_common/sanitizer_stackdepot.h" -#include "sanitizer_common/sanitizer_vector.h" #include #include -// Allow the user to specify a profile output file via the binary. -SANITIZER_WEAK_ATTRIBUTE char __memprof_profile_filename[1]; - namespace __memprof { namespace { using ::llvm::memprof::MemInfoBlock; @@ -279,17 +273,11 @@ static void PrintCallback(const uptr Key, LockedMemInfoBlock *const &Value, void *Arg) { - SpinMutexLock(&Value->mutex); + SpinMutexLock l(&Value->mutex); Print(Value->mib, Key, bool(Arg)); } void FinishAndWrite() { - // Use profile name specified via the binary itself if it exists, and hasn't - // been overrriden by a flag at runtime. - if (__memprof_profile_filename[0] != 0 && !common_flags()->log_path) - __sanitizer_set_report_path(__memprof_profile_filename); - else - __sanitizer_set_report_path(common_flags()->log_path); if (print_text && common_flags()->print_module_map) DumpProcessMap(); @@ -314,11 +302,6 @@ } allocator.ForceUnlock(); - - // Set the report back to the default stderr now that we have dumped the - // profile, in case there are later errors or stats dumping on exit has been - // enabled. - __sanitizer_set_report_path("stderr"); } // Inserts any blocks which have been allocated but not yet deallocated. diff --git a/compiler-rt/lib/memprof/memprof_rtl.cpp b/compiler-rt/lib/memprof/memprof_rtl.cpp --- a/compiler-rt/lib/memprof/memprof_rtl.cpp +++ b/compiler-rt/lib/memprof/memprof_rtl.cpp @@ -29,6 +29,9 @@ uptr __memprof_shadow_memory_dynamic_address; // Global interface symbol. +// Allow the user to specify a profile output file via the binary. +SANITIZER_WEAK_ATTRIBUTE char __memprof_profile_filename[1]; + namespace __memprof { static void MemprofDie() { @@ -166,6 +169,13 @@ AddDieCallback(MemprofDie); SetCheckUnwindCallback(CheckUnwind); + // Use profile name specified via the binary itself if it exists, and hasn't + // been overrriden by a flag at runtime. + if (__memprof_profile_filename[0] != 0 && !common_flags()->log_path) + __sanitizer_set_report_path(__memprof_profile_filename); + else + __sanitizer_set_report_path(common_flags()->log_path); + __sanitizer::InitializePlatformEarly(); // Setup internal allocator callback. diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc b/compiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc --- a/compiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc +++ b/compiler-rt/lib/sanitizer_common/sanitizer_common_syscalls.inc @@ -2106,6 +2106,7 @@ POST_SYSCALL(epoll_wait) (long res, long epfd, void *events, long maxevents, long timeout) { if (res >= 0) { + COMMON_SYSCALL_FD_ACQUIRE(epfd); if (events) POST_WRITE(events, res * struct_epoll_event_sz); } @@ -2122,6 +2123,7 @@ (long res, long epfd, void *events, long maxevents, long timeout, const void *sigmask, long sigsetsize) { if (res >= 0) { + COMMON_SYSCALL_FD_ACQUIRE(epfd); if (events) POST_WRITE(events, res * struct_epoll_event_sz); } @@ -2142,6 +2144,7 @@ const sanitizer_kernel_timespec *timeout, const void *sigmask, long sigsetsize) { if (res >= 0) { + COMMON_SYSCALL_FD_ACQUIRE(epfd); if (events) POST_WRITE(events, res * struct_epoll_event_sz); } diff --git a/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp b/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp --- a/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp +++ b/compiler-rt/lib/tsan/rtl/tsan_interceptors_posix.cpp @@ -1943,12 +1943,24 @@ return res; } -#define TSAN_MAYBE_INTERCEPT_EPOLL \ - TSAN_INTERCEPT(epoll_create); \ - TSAN_INTERCEPT(epoll_create1); \ - TSAN_INTERCEPT(epoll_ctl); \ - TSAN_INTERCEPT(epoll_wait); \ - TSAN_INTERCEPT(epoll_pwait) +TSAN_INTERCEPTOR(int, epoll_pwait2, int epfd, void *ev, int cnt, void *timeout, + void *sigmask) { + SCOPED_TSAN_INTERCEPTOR(epoll_pwait2, epfd, ev, cnt, timeout, sigmask); + if (epfd >= 0) + FdAccess(thr, pc, epfd); + int res = BLOCK_REAL(epoll_pwait2)(epfd, ev, cnt, timeout, sigmask); + if (res > 0 && epfd >= 0) + FdAcquire(thr, pc, epfd); + return res; +} + +# define TSAN_MAYBE_INTERCEPT_EPOLL \ + TSAN_INTERCEPT(epoll_create); \ + TSAN_INTERCEPT(epoll_create1); \ + TSAN_INTERCEPT(epoll_ctl); \ + TSAN_INTERCEPT(epoll_wait); \ + TSAN_INTERCEPT(epoll_pwait); \ + TSAN_INTERCEPT(epoll_pwait2) #else #define TSAN_MAYBE_INTERCEPT_EPOLL #endif diff --git a/compiler-rt/test/asan/TestCases/contiguous_container.cpp b/compiler-rt/test/asan/TestCases/contiguous_container.cpp --- a/compiler-rt/test/asan/TestCases/contiguous_container.cpp +++ b/compiler-rt/test/asan/TestCases/contiguous_container.cpp @@ -3,6 +3,9 @@ // Test __sanitizer_annotate_contiguous_container. #include +#include +#include + #include #include #include @@ -16,6 +19,28 @@ ~(kGranularity - 1)); } +static std::vector GetPoisonedState(char *begin, char *end) { + std::vector result; + for (; begin != end;) { + int poisoned = 0; + for (; begin != end && __asan_address_is_poisoned(begin); ++begin) + ++poisoned; + result.push_back(poisoned); + int unpoisoned = 0; + for (; begin != end && !__asan_address_is_poisoned(begin); ++begin) + ++unpoisoned; + result.push_back(unpoisoned); + } + return result; +} + +static int GetFirstMismatch(const std::vector &a, + const std::vector &b) { + auto mismatch = std::mismatch(a.begin(), a.end(), b.begin(), b.end()); + return std::accumulate(a.begin(), mismatch.first, 0) + + std::min(*mismatch.first, *mismatch.second); +} + void TestContainer(size_t capacity, size_t off_begin, bool poison_buffer) { size_t buffer_size = capacity + off_begin + kGranularity * 2; char *buffer = new char[buffer_size]; @@ -33,11 +58,11 @@ __sanitizer_annotate_contiguous_container(st_beg, st_end, old_end, end); char *cur = buffer; - for (; cur < buffer + RoundDown(off_begin); ++cur) + for (; cur < RoundDown(st_beg); ++cur) assert(__asan_address_is_poisoned(cur) == poison_buffer); // The prefix of the first incomplete granule can switch from poisoned to // unpoisoned but not otherwise. - for (; cur < buffer + off_begin; ++cur) + for (; cur < st_beg; ++cur) assert(poison_buffer || !__asan_address_is_poisoned(cur)); for (; cur < end; ++cur) assert(!__asan_address_is_poisoned(cur)); @@ -49,29 +74,39 @@ assert(__asan_address_is_poisoned(cur) == poison_buffer); } + // Precalculate masks. + std::vector> masks(capacity + 1); + for (int i = 0; i <= capacity; i++) { + char *old_end = end; + end = st_beg + i; + __sanitizer_annotate_contiguous_container(st_beg, st_end, old_end, end); + masks[i] = GetPoisonedState(st_beg, st_end); + } for (int i = 0; i <= capacity; i++) { char *old_end = end; end = st_beg + i; __sanitizer_annotate_contiguous_container(st_beg, st_end, old_end, end); - for (char *cur = std::max(st_beg, st_end - 2 * kGranularity); - cur <= std::min(st_end, end + 2 * kGranularity); ++cur) { + char *cur_first = std::max(end - 2 * kGranularity, st_beg); + char *cur_last = std::min(end + 2 * kGranularity, st_end); + for (char *cur = cur_first; cur <= cur_last; ++cur) { + bool is_valid = + __sanitizer_verify_contiguous_container(st_beg, cur, st_end); + const void *bad_address = + __sanitizer_contiguous_container_find_bad_address(st_beg, cur, + st_end); if (cur == end || - // Any end in the last unaligned granule is OK, if bytes after the - // storage are not poisoned. + // The last unaligned granule of the storage followed by unpoisoned + // bytes looks the same. (!poison_buffer && RoundDown(st_end) <= std::min(cur, end))) { - assert(__sanitizer_verify_contiguous_container(st_beg, cur, st_end)); - assert(NULL == __sanitizer_contiguous_container_find_bad_address( - st_beg, cur, st_end)); - } else if (cur < end) { - assert(!__sanitizer_verify_contiguous_container(st_beg, cur, st_end)); - assert(cur == __sanitizer_contiguous_container_find_bad_address( - st_beg, cur, st_end)); - } else { - assert(!__sanitizer_verify_contiguous_container(st_beg, cur, st_end)); - assert(end == __sanitizer_contiguous_container_find_bad_address( - st_beg, cur, st_end)); + assert(is_valid); + assert(!bad_address); + continue; } + assert(!is_valid); + assert(bad_address == std::min(cur, end)); + assert(bad_address == + st_beg + GetFirstMismatch(masks[i], masks[cur - st_beg])); } } @@ -79,13 +114,18 @@ delete[] buffer; } -void TestDoubleEndedContainer(size_t capacity) { - char *st_beg = new char[capacity]; +void TestDoubleEndedContainer(size_t capacity, size_t off_begin, + bool poison_buffer) { + size_t buffer_size = capacity + off_begin + kGranularity * 2; + char *buffer = new char[buffer_size]; + if (poison_buffer) + __asan_poison_memory_region(buffer, buffer_size); + char *st_beg = buffer + off_begin; char *st_end = st_beg + capacity; char *beg = st_beg; - char *end = st_beg + capacity; + char *end = poison_buffer ? st_beg : st_end; - for (int i = 0; i < 10000; i++) { + for (int i = 0; i < 1000; i++) { size_t size = rand() % (capacity + 1); size_t skipped = rand() % (capacity - size + 1); assert(size <= capacity); @@ -96,19 +136,108 @@ __sanitizer_annotate_double_ended_contiguous_container( st_beg, st_end, old_beg, old_end, beg, end); - for (size_t idx = 0; idx < RoundDown(skipped); idx++) - assert(__asan_address_is_poisoned(st_beg + idx)); - for (size_t idx = 0; idx < size; idx++) - assert(!__asan_address_is_poisoned(st_beg + skipped + idx)); - for (size_t idx = skipped + size; idx < capacity; idx++) - assert(__asan_address_is_poisoned(st_beg + idx)); - - assert(__sanitizer_verify_double_ended_contiguous_container(st_beg, beg, - end, st_end)); + + char *cur = buffer; + for (; cur < RoundDown(st_beg); ++cur) + assert(__asan_address_is_poisoned(cur) == poison_buffer); + // The prefix of the first incomplete granule can switch from poisoned to + // unpoisoned but not otherwise. + for (; cur < st_beg; ++cur) + assert(poison_buffer || !__asan_address_is_poisoned(cur)); + if (beg != end) { + for (; cur < RoundDown(beg); ++cur) + assert(__asan_address_is_poisoned(cur)); + + for (; cur < end; ++cur) + assert(!__asan_address_is_poisoned(cur)); + } + for (; cur < RoundDown(st_end); ++cur) + assert(__asan_address_is_poisoned(cur)); + // The suffix of the last incomplete granule must be poisoned the same as + // bytes after the end. + for (; cur != st_end + kGranularity; ++cur) + assert(__asan_address_is_poisoned(cur) == poison_buffer); } - __asan_unpoison_memory_region(st_beg, st_end - st_beg); - delete[] st_beg; + if (capacity < 32) { + + // Precalculate masks. + std::vector>> masks( + capacity + 1, std::vector>(capacity + 1)); + for (int i = 0; i <= capacity; i++) { + for (int j = i; j <= capacity; j++) { + char *old_beg = beg; + char *old_end = end; + beg = st_beg + i; + end = st_beg + j; + __sanitizer_annotate_double_ended_contiguous_container( + st_beg, st_end, old_beg, old_end, beg, end); + masks[i][j] = GetPoisonedState(st_beg, st_end); + } + } + + for (int i = 0; i <= capacity; i++) { + for (int j = i; j <= capacity; j++) { + char *old_beg = beg; + char *old_end = end; + beg = st_beg + i; + end = st_beg + j; + __sanitizer_annotate_double_ended_contiguous_container( + st_beg, st_end, old_beg, old_end, beg, end); + + // Try to mismatch the end of the container. + char *cur_first = std::max(end - 2 * kGranularity, beg); + char *cur_last = std::min(end + 2 * kGranularity, st_end); + for (char *cur = cur_first; cur <= cur_last; ++cur) { + bool is_valid = __sanitizer_verify_double_ended_contiguous_container( + st_beg, beg, cur, st_end); + const void *bad_address = + __sanitizer_double_ended_contiguous_container_find_bad_address( + st_beg, beg, cur, st_end); + + if (cur == end) { + assert(is_valid); + assert(!bad_address); + continue; + } + + assert(!is_valid); + assert(bad_address); + assert(bad_address == + st_beg + + GetFirstMismatch(masks[i][j], masks[i][cur - st_beg])); + } + + // Try to mismatch the begin of the container. + cur_first = std::max(beg - 2 * kGranularity, st_beg); + cur_last = std::min(beg + 2 * kGranularity, end); + for (char *cur = cur_first; cur <= cur_last; ++cur) { + bool is_valid = __sanitizer_verify_double_ended_contiguous_container( + st_beg, cur, end, st_end); + const void *bad_address = + __sanitizer_double_ended_contiguous_container_find_bad_address( + st_beg, cur, end, st_end); + + if (cur == beg || + // The first unaligned granule of non-empty container looks the + // same. + (std::max(beg, cur) < end && RoundDown(beg) == RoundDown(cur))) { + assert(is_valid); + assert(!bad_address); + continue; + } + assert(!is_valid); + assert(bad_address); + assert(bad_address == + st_beg + + GetFirstMismatch(masks[i][j], masks[cur - st_beg][j])); + } + } + } + } + + __asan_unpoison_memory_region(buffer, buffer_size); + delete[] buffer; } __attribute__((noinline)) void Throw() { throw 1; } @@ -139,9 +268,9 @@ for (int j = 0; j < kGranularity * 2; j++) { for (int poison = 0; poison < 2; ++poison) { TestContainer(i, j, poison); + TestDoubleEndedContainer(i, 0, true); } } - TestDoubleEndedContainer(i); } TestThrow(); } diff --git a/compiler-rt/test/memprof/TestCases/atexit_stats.cpp b/compiler-rt/test/memprof/TestCases/atexit_stats.cpp --- a/compiler-rt/test/memprof/TestCases/atexit_stats.cpp +++ b/compiler-rt/test/memprof/TestCases/atexit_stats.cpp @@ -2,9 +2,6 @@ // RUN: %clangxx_memprof -O0 %s -o %t // RUN: %env_memprof_opts=print_text=true:log_path=stderr:atexit=1 %run %t 2>&1 | FileCheck %s -// Stats should be dumped to stderr even if the profile log path set to a file. -// RUN: rm -f %t.log.* -// RUN: %env_memprof_opts=print_text=true:log_path=%t.log:atexit=1 %run %t 2>&1 | FileCheck %s // RUN: %env_memprof_opts=print_text=true:log_path=stderr:atexit=0 %run %t 2>&1 | FileCheck %s --check-prefix=NOATEXIT // CHECK: MemProfiler exit stats: diff --git a/compiler-rt/test/memprof/TestCases/malloc-size-too-big.cpp b/compiler-rt/test/memprof/TestCases/malloc-size-too-big.cpp --- a/compiler-rt/test/memprof/TestCases/malloc-size-too-big.cpp +++ b/compiler-rt/test/memprof/TestCases/malloc-size-too-big.cpp @@ -1,8 +1,5 @@ // RUN: %clangxx_memprof -O0 %s -o %t // RUN: %env_memprof_opts=print_text=true:log_path=stderr:allocator_may_return_null=0 not %run %t 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SUMMARY -// Errors should be printed to stderr even if the log_path set to a file. -// RUN: rm -f %t.log.* -// RUN: %env_memprof_opts=print_text=true:log_path=%t.log:allocator_may_return_null=0 not %run %t 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-SUMMARY // RUN: %env_memprof_opts=print_text=true:log_path=stderr:allocator_may_return_null=1 %run %t 2>&1 | FileCheck %s --check-prefix=CHECK-NULL // Test print_summary // RUN: %env_memprof_opts=print_text=true:log_path=stderr:allocator_may_return_null=0:print_summary=0 not %run %t 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOSUMMARY diff --git a/flang/CMakeLists.txt b/flang/CMakeLists.txt --- a/flang/CMakeLists.txt +++ b/flang/CMakeLists.txt @@ -153,23 +153,7 @@ set(UNITTEST_DIR ${LLVM_THIRD_PARTY_DIR}/unittest) if(EXISTS ${UNITTEST_DIR}/googletest/include/gtest/gtest.h) if (NOT TARGET llvm_gtest) - add_library(llvm_gtest - ${UNITTEST_DIR}/googletest/src/gtest-all.cc - ${UNITTEST_DIR}/googlemock/src/gmock-all.cc - ) - target_include_directories(llvm_gtest - PUBLIC - "${UNITTEST_DIR}/googletest/include" - "${UNITTEST_DIR}/googlemock/include" - - PRIVATE - "${UNITTEST_DIR}/googletest" - "${UNITTEST_DIR}/googlemock" - ) - find_package(Threads) - target_link_libraries(llvm_gtest PUBLIC Threads::Threads) - add_library(llvm_gtest_main ${UNITTEST_DIR}/UnitTestMain/TestMain.cpp) - target_link_libraries(llvm_gtest_main PUBLIC llvm_gtest) + add_subdirectory(${UNITTEST_DIR} third-party/unittest) endif() set(FLANG_GTEST_AVAIL 1) else() diff --git a/flang/cmake/modules/FlangConfig.cmake.in b/flang/cmake/modules/FlangConfig.cmake.in --- a/flang/cmake/modules/FlangConfig.cmake.in +++ b/flang/cmake/modules/FlangConfig.cmake.in @@ -2,8 +2,8 @@ @FLANG_CONFIG_CODE@ -set(LLVM_VERSION ${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}.${LLVM_VERSION_PATCH}) -find_package(LLVM @LLVM_VERSION@ EXACT REQUIRED CONFIG +set(LLVM_VERSION @LLVM_VERSION_MAJOR@.@LLVM_VERSION_MINOR@.@LLVM_VERSION_PATCH@) +find_package(LLVM ${LLVM_VERSION} EXACT REQUIRED CONFIG HINTS "@FLANG_CONFIG_LLVM_CMAKE_DIR@") set(FLANG_EXPORTED_TARGETS "@FLANG_EXPORTS@") diff --git a/flang/docs/Intrinsics.md b/flang/docs/Intrinsics.md --- a/flang/docs/Intrinsics.md +++ b/flang/docs/Intrinsics.md @@ -749,7 +749,7 @@ | Coarray intrinsic functions | IMAGE_INDEX, COSHAPE | | Object characteristic inquiry functions | ALLOCATED, ASSOCIATED, EXTENDS_TYPE_OF, IS_CONTIGUOUS, PRESENT, RANK, SAME_TYPE, STORAGE_SIZE | | Type inquiry intrinsic functions | BIT_SIZE, DIGITS, EPSILON, HUGE, KIND, MAXEXPONENT, MINEXPONENT, NEW_LINE, PRECISION, RADIX, RANGE, TINY| -| Non-standard intrinsic functions | AND, OR, XOR, LSHIFT, RSHIFT, SHIFT, ZEXT, IZEXT, COSD, SIND, TAND, ACOSD, ASIND, ATAND, ATAN2D, COMPL, DCMPLX, EQV, NEQV, INT8, JINT, JNINT, KNINT, LOC, QCMPLX, DREAL, DFLOAT, QEXT, QFLOAT, QREAL, DNUM, NUM, JNUM, KNUM, QNUM, RNUM, RAN, RANF, ILEN, SIZEOF, MCLOCK, SECNDS, COTAN, IBCHNG, ISHA, ISHC, ISHL, IXOR, IARG, IARGC, NARGS, NUMARG, BADDRESS, IADDR, CACHESIZE, EOF, FP_CLASS, INT_PTR_KIND, ISNAN, MALLOC | +| Non-standard intrinsic functions | AND, OR, XOR, LSHIFT, RSHIFT, SHIFT, ZEXT, IZEXT, COSD, SIND, TAND, ACOSD, ASIND, ATAND, ATAN2D, COMPL, DCMPLX, EQV, NEQV, INT8, JINT, JNINT, KNINT, QCMPLX, DREAL, DFLOAT, QEXT, QFLOAT, QREAL, DNUM, NUM, JNUM, KNUM, QNUM, RNUM, RAN, RANF, ILEN, SIZEOF, MCLOCK, SECNDS, COTAN, IBCHNG, ISHA, ISHC, ISHL, IXOR, IARG, IARGC, NARGS, NUMARG, BADDRESS, IADDR, CACHESIZE, EOF, FP_CLASS, INT_PTR_KIND, ISNAN, MALLOC | | Intrinsic subroutines |MVBITS (elemental), CPU_TIME, DATE_AND_TIME, EVENT_QUERY, EXECUTE_COMMAND_LINE, GET_COMMAND, GET_COMMAND_ARGUMENT, GET_ENVIRONMENT_VARIABLE, MOVE_ALLOC, RANDOM_INIT, RANDOM_NUMBER, RANDOM_SEED, SYSTEM_CLOCK | | Atomic intrinsic subroutines | ATOMIC_ADD | | Collective intrinsic subroutines | CO_REDUCE | diff --git a/flang/include/flang/Lower/ConvertCall.h b/flang/include/flang/Lower/ConvertCall.h new file mode 100644 --- /dev/null +++ b/flang/include/flang/Lower/ConvertCall.h @@ -0,0 +1,42 @@ +//===-- ConvertCall.h -- lowering of calls ----------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Coding style: https://mlir.llvm.org/getting_started/DeveloperGuide/ +// +//===----------------------------------------------------------------------===// +/// +/// Implements the conversion from evaluate::ProcedureRef to FIR. +/// +//===----------------------------------------------------------------------===// + +#ifndef FORTRAN_LOWER_CONVERTCALL_H +#define FORTRAN_LOWER_CONVERTCALL_H + +#include "flang/Lower/AbstractConverter.h" +#include "flang/Lower/CallInterface.h" + +namespace Fortran::lower { + +/// Given a call site for which the arguments were already lowered, generate +/// the call and return the result. This function deals with explicit result +/// allocation and lowering if needed. It also deals with passing the host +/// link to internal procedures. +fir::ExtendedValue genCallOpAndResult( + mlir::Location loc, Fortran::lower::AbstractConverter &converter, + Fortran::lower::SymMap &symMap, Fortran::lower::StatementContext &stmtCtx, + Fortran::lower::CallerInterface &caller, mlir::FunctionType callSiteType, + llvm::Optional resultType); + +/// If \p arg is the address of a function with a denoted host-association tuple +/// argument, then return the host-associations tuple value of the current +/// procedure. Otherwise, return nullptr. +mlir::Value argumentHostAssocs(Fortran::lower::AbstractConverter &converter, + mlir::Value arg); + +} // namespace Fortran::lower +#endif // FORTRAN_LOWER_CONVERTCALL_H diff --git a/flang/include/flang/Optimizer/Dialect/FIRType.h b/flang/include/flang/Optimizer/Dialect/FIRType.h --- a/flang/include/flang/Optimizer/Dialect/FIRType.h +++ b/flang/include/flang/Optimizer/Dialect/FIRType.h @@ -288,6 +288,9 @@ /// value. bool isUnlimitedPolymorphicType(mlir::Type ty); +/// Return the inner type of the given type. +mlir::Type unwrapInnerType(mlir::Type ty); + /// Return true iff `ty` is a RecordType with members that are allocatable. bool isRecordWithAllocatableMember(mlir::Type ty); diff --git a/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h b/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h --- a/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h +++ b/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h @@ -20,6 +20,8 @@ namespace hlfir { /// Is this a type that can be used for an HLFIR variable ? bool isFortranVariableType(mlir::Type); +bool isFortranScalarCharacterType(mlir::Type); +bool isFortranScalarCharacterExprType(mlir::Type); } // namespace hlfir #include "flang/Optimizer/HLFIR/HLFIRDialect.h.inc" diff --git a/flang/include/flang/Optimizer/HLFIR/HLFIROpBase.td b/flang/include/flang/Optimizer/HLFIR/HLFIROpBase.td --- a/flang/include/flang/Optimizer/HLFIR/HLFIROpBase.td +++ b/flang/include/flang/Optimizer/HLFIR/HLFIROpBase.td @@ -63,7 +63,8 @@ let extraClassDeclaration = [{ using Shape = llvm::SmallVector; mlir::Type getEleTy() const {return getElementType();} - bool isArray() const { return !getShape().empty(); } + bool isScalar() const { return getShape().empty(); } + bool isArray() const { return !isScalar(); } bool isPolymorphic() const { return getPolymorphic(); } }]; @@ -85,5 +86,14 @@ def AnyFortranEntity : TypeConstraint, "any Fortran value or variable type">; +def IsFortranScalarCharacterPred + : CPred<"::hlfir::isFortranScalarCharacterType($_self)">; +def AnyScalarCharacterEntity : Type; + +def IsFortranScalarCharacterExprPred + : CPred<"::hlfir::isFortranScalarCharacterExprType($_self)">; +def AnyScalarCharacterExpr : Type; #endif // FORTRAN_DIALECT_HLFIR_OP_BASE diff --git a/flang/include/flang/Optimizer/HLFIR/HLFIROps.td b/flang/include/flang/Optimizer/HLFIR/HLFIROps.td --- a/flang/include/flang/Optimizer/HLFIR/HLFIROps.td +++ b/flang/include/flang/Optimizer/HLFIR/HLFIROps.td @@ -208,4 +208,25 @@ let hasVerifier = 1; } +def hlfir_ConcatOp : hlfir_Op<"concat", []> { + let summary = "concatenate characters"; + let description = [{ + Concatenate two or more character strings of a same character kind. + }]; + + let arguments = (ins Variadic:$strings, + AnyIntegerType:$length); + + let results = (outs AnyScalarCharacterExpr); + + let assemblyFormat = [{ + $strings `len` $length + attr-dict `:` functional-type(operands, results) + }]; + + let builders = [OpBuilder<(ins "mlir::ValueRange":$strings,"mlir::Value":$len)>]; + + let hasVerifier = 1; +} + #endif // FORTRAN_DIALECT_HLFIR_OPS diff --git a/flang/include/flang/Optimizer/HLFIR/Passes.h b/flang/include/flang/Optimizer/HLFIR/Passes.h --- a/flang/include/flang/Optimizer/HLFIR/Passes.h +++ b/flang/include/flang/Optimizer/HLFIR/Passes.h @@ -22,6 +22,7 @@ #include "flang/Optimizer/HLFIR/Passes.h.inc" std::unique_ptr createConvertHLFIRtoFIRPass(); +std::unique_ptr createBufferizeHLFIRPass(); #define GEN_PASS_REGISTRATION #include "flang/Optimizer/HLFIR/Passes.h.inc" diff --git a/flang/include/flang/Optimizer/HLFIR/Passes.td b/flang/include/flang/Optimizer/HLFIR/Passes.td --- a/flang/include/flang/Optimizer/HLFIR/Passes.td +++ b/flang/include/flang/Optimizer/HLFIR/Passes.td @@ -15,4 +15,9 @@ let constructor = "hlfir::createConvertHLFIRtoFIRPass()"; } +def BufferizeHLFIR : Pass<"bufferize-hlfir", "::mlir::ModuleOp"> { + let summary = "Convert HLFIR operations operating on hlfir.expr into operations on memory"; + let constructor = "hlfir::createBufferizeHLFIRPass()"; +} + #endif //FORTRAN_DIALECT_HLFIR_PASSES diff --git a/flang/lib/Evaluate/intrinsics.cpp b/flang/lib/Evaluate/intrinsics.cpp --- a/flang/lib/Evaluate/intrinsics.cpp +++ b/flang/lib/Evaluate/intrinsics.cpp @@ -574,8 +574,8 @@ DefaultLogical}, {"llt", {{"string_a", SameCharNoLen}, {"string_b", SameCharNoLen}}, DefaultLogical}, - {"loc", {{"loc_argument", Addressable, Rank::anyOrAssumedRank}}, - SubscriptInt, Rank::scalar}, + {"loc", {{"x", Addressable, Rank::anyOrAssumedRank}}, SubscriptInt, + Rank::scalar}, {"log", {{"x", SameFloating}}, SameFloating}, {"log10", {{"x", SameReal}}, SameReal}, {"logical", {{"l", AnyLogical}, DefaultingKIND}, KINDLogical}, diff --git a/flang/lib/Frontend/FrontendActions.cpp b/flang/lib/Frontend/FrontendActions.cpp --- a/flang/lib/Frontend/FrontendActions.cpp +++ b/flang/lib/Frontend/FrontendActions.cpp @@ -694,7 +694,8 @@ llvm::PassInstrumentationCallbacks pic; llvm::PipelineTuningOptions pto; llvm::Optional pgoOpt; - llvm::StandardInstrumentations si(opts.DebugPassManager); + llvm::StandardInstrumentations si( + llvmModule->getContext(), opts.DebugPassManager); si.registerCallbacks(pic, &fam); llvm::PassBuilder pb(tm.get(), pto, pgoOpt, &pic); diff --git a/flang/lib/Lower/CMakeLists.txt b/flang/lib/Lower/CMakeLists.txt --- a/flang/lib/Lower/CMakeLists.txt +++ b/flang/lib/Lower/CMakeLists.txt @@ -5,6 +5,7 @@ Bridge.cpp CallInterface.cpp Coarray.cpp + ConvertCall.cpp ConvertConstant.cpp ConvertExpr.cpp ConvertExprToHLFIR.cpp diff --git a/flang/lib/Lower/CallInterface.cpp b/flang/lib/Lower/CallInterface.cpp --- a/flang/lib/Lower/CallInterface.cpp +++ b/flang/lib/Lower/CallInterface.cpp @@ -115,6 +115,17 @@ } ++passArgIdx; } + if (!passArg) + return passArg; + // Take into account result inserted as arguments. + if (std::optional::PassedEntity> + resultArg = getPassedResult()) { + if (resultArg->passBy == PassEntityBy::AddressAndLength) + passArg = *passArg + 2; + else if (resultArg->passBy == PassEntityBy::BaseAddress) + passArg = *passArg + 1; + } return passArg; } @@ -251,7 +262,8 @@ if (std::optional length = dynamicType.GetCharLength()) visitor(toEvExpr(*length)); - } else if (dynamicType.category() == common::TypeCategory::Derived) { + } else if (dynamicType.category() == common::TypeCategory::Derived && + !dynamicType.IsUnlimitedPolymorphic()) { const Fortran::semantics::DerivedTypeSpec &derivedTypeSpec = dynamicType.GetDerivedTypeSpec(); if (Fortran::semantics::CountLenParameters(derivedTypeSpec) > 0) diff --git a/flang/lib/Lower/ConvertCall.cpp b/flang/lib/Lower/ConvertCall.cpp new file mode 100644 --- /dev/null +++ b/flang/lib/Lower/ConvertCall.cpp @@ -0,0 +1,402 @@ +//===-- ConvertCall.cpp ---------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Coding style: https://mlir.llvm.org/getting_started/DeveloperGuide/ +// +//===----------------------------------------------------------------------===// + +#include "flang/Lower/ConvertCall.h" +#include "flang/Lower/ConvertVariable.h" +#include "flang/Lower/StatementContext.h" +#include "flang/Lower/SymbolMap.h" +#include "flang/Optimizer/Builder/BoxValue.h" +#include "flang/Optimizer/Builder/Character.h" +#include "flang/Optimizer/Builder/FIRBuilder.h" +#include "flang/Optimizer/Builder/LowLevelIntrinsics.h" +#include "flang/Optimizer/Builder/MutableBox.h" +#include "flang/Optimizer/Builder/Todo.h" +#include "flang/Optimizer/Dialect/FIROpsSupport.h" +#include "llvm/Support/Debug.h" + +#define DEBUG_TYPE "flang-lower-expr" + +/// Helper to package a Value and its properties into an ExtendedValue. +static fir::ExtendedValue toExtendedValue(mlir::Location loc, mlir::Value base, + llvm::ArrayRef extents, + llvm::ArrayRef lengths) { + mlir::Type type = base.getType(); + if (type.isa()) + return fir::BoxValue(base, /*lbounds=*/{}, lengths, extents); + type = fir::unwrapRefType(type); + if (type.isa()) + return fir::MutableBoxValue(base, lengths, /*mutableProperties*/ {}); + if (auto seqTy = type.dyn_cast()) { + if (seqTy.getDimension() != extents.size()) + fir::emitFatalError(loc, "incorrect number of extents for array"); + if (seqTy.getEleTy().isa()) { + if (lengths.empty()) + fir::emitFatalError(loc, "missing length for character"); + assert(lengths.size() == 1); + return fir::CharArrayBoxValue(base, lengths[0], extents); + } + return fir::ArrayBoxValue(base, extents); + } + if (type.isa()) { + if (lengths.empty()) + fir::emitFatalError(loc, "missing length for character"); + assert(lengths.size() == 1); + return fir::CharBoxValue(base, lengths[0]); + } + return base; +} + +/// Lower a type(C_PTR/C_FUNPTR) argument with VALUE attribute into a +/// reference. A C pointer can correspond to a Fortran dummy argument of type +/// C_PTR with the VALUE attribute. (see 18.3.6 note 3). +static mlir::Value +genRecordCPtrValueArg(Fortran::lower::AbstractConverter &converter, + mlir::Value rec, mlir::Type ty) { + fir::FirOpBuilder &builder = converter.getFirOpBuilder(); + mlir::Location loc = converter.getCurrentLocation(); + mlir::Value cAddr = fir::factory::genCPtrOrCFunptrAddr(builder, loc, rec, ty); + mlir::Value cVal = builder.create(loc, cAddr); + return builder.createConvert(loc, cAddr.getType(), cVal); +} + +// Find the argument that corresponds to the host associations. +// Verify some assumptions about how the signature was built here. +[[maybe_unused]] static unsigned findHostAssocTuplePos(mlir::func::FuncOp fn) { + // Scan the argument list from last to first as the host associations are + // appended for now. + for (unsigned i = fn.getNumArguments(); i > 0; --i) + if (fn.getArgAttr(i - 1, fir::getHostAssocAttrName())) { + // Host assoc tuple must be last argument (for now). + assert(i == fn.getNumArguments() && "tuple must be last"); + return i - 1; + } + llvm_unreachable("anyFuncArgsHaveAttr failed"); +} + +mlir::Value +Fortran::lower::argumentHostAssocs(Fortran::lower::AbstractConverter &converter, + mlir::Value arg) { + if (auto addr = mlir::dyn_cast_or_null(arg.getDefiningOp())) { + auto &builder = converter.getFirOpBuilder(); + if (auto funcOp = builder.getNamedFunction(addr.getSymbol())) + if (fir::anyFuncArgsHaveAttr(funcOp, fir::getHostAssocAttrName())) + return converter.hostAssocTupleValue(); + } + return {}; +} + +fir::ExtendedValue Fortran::lower::genCallOpAndResult( + mlir::Location loc, Fortran::lower::AbstractConverter &converter, + Fortran::lower::SymMap &symMap, Fortran::lower::StatementContext &stmtCtx, + Fortran::lower::CallerInterface &caller, mlir::FunctionType callSiteType, + llvm::Optional resultType) { + fir::FirOpBuilder &builder = converter.getFirOpBuilder(); + using PassBy = Fortran::lower::CallerInterface::PassEntityBy; + // Handle cases where caller must allocate the result or a fir.box for it. + bool mustPopSymMap = false; + if (caller.mustMapInterfaceSymbols()) { + symMap.pushScope(); + mustPopSymMap = true; + Fortran::lower::mapCallInterfaceSymbols(converter, caller, symMap); + } + // If this is an indirect call, retrieve the function address. Also retrieve + // the result length if this is a character function (note that this length + // will be used only if there is no explicit length in the local interface). + mlir::Value funcPointer; + mlir::Value charFuncPointerLength; + if (const Fortran::semantics::Symbol *sym = + caller.getIfIndirectCallSymbol()) { + funcPointer = symMap.lookupSymbol(*sym).getAddr(); + if (!funcPointer) + fir::emitFatalError(loc, "failed to find indirect call symbol address"); + if (fir::isCharacterProcedureTuple(funcPointer.getType(), + /*acceptRawFunc=*/false)) + std::tie(funcPointer, charFuncPointerLength) = + fir::factory::extractCharacterProcedureTuple(builder, loc, + funcPointer); + } + + mlir::IndexType idxTy = builder.getIndexType(); + auto lowerSpecExpr = [&](const auto &expr) -> mlir::Value { + mlir::Value convertExpr = builder.createConvert( + loc, idxTy, fir::getBase(converter.genExprValue(expr, stmtCtx))); + return fir::factory::genMaxWithZero(builder, loc, convertExpr); + }; + llvm::SmallVector resultLengths; + auto allocatedResult = [&]() -> llvm::Optional { + llvm::SmallVector extents; + llvm::SmallVector lengths; + if (!caller.callerAllocateResult()) + return {}; + mlir::Type type = caller.getResultStorageType(); + if (type.isa()) + caller.walkResultExtents([&](const Fortran::lower::SomeExpr &e) { + extents.emplace_back(lowerSpecExpr(e)); + }); + caller.walkResultLengths([&](const Fortran::lower::SomeExpr &e) { + lengths.emplace_back(lowerSpecExpr(e)); + }); + + // Result length parameters should not be provided to box storage + // allocation and save_results, but they are still useful information to + // keep in the ExtendedValue if non-deferred. + if (!type.isa()) { + if (fir::isa_char(fir::unwrapSequenceType(type)) && lengths.empty()) { + // Calling an assumed length function. This is only possible if this + // is a call to a character dummy procedure. + if (!charFuncPointerLength) + fir::emitFatalError(loc, "failed to retrieve character function " + "length while calling it"); + lengths.push_back(charFuncPointerLength); + } + resultLengths = lengths; + } + + if (!extents.empty() || !lengths.empty()) { + auto *bldr = &converter.getFirOpBuilder(); + auto stackSaveFn = fir::factory::getLlvmStackSave(builder); + auto stackSaveSymbol = bldr->getSymbolRefAttr(stackSaveFn.getName()); + mlir::Value sp = bldr->create( + loc, stackSaveFn.getFunctionType().getResults(), + stackSaveSymbol, mlir::ValueRange{}) + .getResult(0); + stmtCtx.attachCleanup([bldr, loc, sp]() { + auto stackRestoreFn = fir::factory::getLlvmStackRestore(*bldr); + auto stackRestoreSymbol = + bldr->getSymbolRefAttr(stackRestoreFn.getName()); + bldr->create(loc, + stackRestoreFn.getFunctionType().getResults(), + stackRestoreSymbol, mlir::ValueRange{sp}); + }); + } + mlir::Value temp = + builder.createTemporary(loc, type, ".result", extents, resultLengths); + return toExtendedValue(loc, temp, extents, lengths); + }(); + + if (mustPopSymMap) + symMap.popScope(); + + // Place allocated result or prepare the fir.save_result arguments. + mlir::Value arrayResultShape; + if (allocatedResult) { + if (std::optional::PassedEntity> + resultArg = caller.getPassedResult()) { + if (resultArg->passBy == PassBy::AddressAndLength) + caller.placeAddressAndLengthInput(*resultArg, + fir::getBase(*allocatedResult), + fir::getLen(*allocatedResult)); + else if (resultArg->passBy == PassBy::BaseAddress) + caller.placeInput(*resultArg, fir::getBase(*allocatedResult)); + else + fir::emitFatalError( + loc, "only expect character scalar result to be passed by ref"); + } else { + assert(caller.mustSaveResult()); + arrayResultShape = allocatedResult->match( + [&](const fir::CharArrayBoxValue &) { + return builder.createShape(loc, *allocatedResult); + }, + [&](const fir::ArrayBoxValue &) { + return builder.createShape(loc, *allocatedResult); + }, + [&](const auto &) { return mlir::Value{}; }); + } + } + + // In older Fortran, procedure argument types are inferred. This may lead + // different view of what the function signature is in different locations. + // Casts are inserted as needed below to accommodate this. + + // The mlir::func::FuncOp type prevails, unless it has a different number of + // arguments which can happen in legal program if it was passed as a dummy + // procedure argument earlier with no further type information. + mlir::SymbolRefAttr funcSymbolAttr; + bool addHostAssociations = false; + if (!funcPointer) { + mlir::FunctionType funcOpType = caller.getFuncOp().getFunctionType(); + mlir::SymbolRefAttr symbolAttr = + builder.getSymbolRefAttr(caller.getMangledName()); + if (callSiteType.getNumResults() == funcOpType.getNumResults() && + callSiteType.getNumInputs() + 1 == funcOpType.getNumInputs() && + fir::anyFuncArgsHaveAttr(caller.getFuncOp(), + fir::getHostAssocAttrName())) { + // The number of arguments is off by one, and we're lowering a function + // with host associations. Modify call to include host associations + // argument by appending the value at the end of the operands. + assert(funcOpType.getInput(findHostAssocTuplePos(caller.getFuncOp())) == + converter.hostAssocTupleValue().getType()); + addHostAssociations = true; + } + if (!addHostAssociations && + (callSiteType.getNumResults() != funcOpType.getNumResults() || + callSiteType.getNumInputs() != funcOpType.getNumInputs())) { + // Deal with argument number mismatch by making a function pointer so + // that function type cast can be inserted. Do not emit a warning here + // because this can happen in legal program if the function is not + // defined here and it was first passed as an argument without any more + // information. + funcPointer = builder.create(loc, funcOpType, symbolAttr); + } else if (callSiteType.getResults() != funcOpType.getResults()) { + // Implicit interface result type mismatch are not standard Fortran, but + // some compilers are not complaining about it. The front end is not + // protecting lowering from this currently. Support this with a + // discouraging warning. + LLVM_DEBUG(mlir::emitWarning( + loc, "a return type mismatch is not standard compliant and may " + "lead to undefined behavior.")); + // Cast the actual function to the current caller implicit type because + // that is the behavior we would get if we could not see the definition. + funcPointer = builder.create(loc, funcOpType, symbolAttr); + } else { + funcSymbolAttr = symbolAttr; + } + } + + mlir::FunctionType funcType = + funcPointer ? callSiteType : caller.getFuncOp().getFunctionType(); + llvm::SmallVector operands; + // First operand of indirect call is the function pointer. Cast it to + // required function type for the call to handle procedures that have a + // compatible interface in Fortran, but that have different signatures in + // FIR. + if (funcPointer) { + operands.push_back( + funcPointer.getType().isa() + ? builder.create(loc, funcType, funcPointer) + : builder.createConvert(loc, funcType, funcPointer)); + } + + // Deal with potential mismatches in arguments types. Passing an array to a + // scalar argument should for instance be tolerated here. + bool callingImplicitInterface = caller.canBeCalledViaImplicitInterface(); + for (auto [fst, snd] : llvm::zip(caller.getInputs(), funcType.getInputs())) { + // When passing arguments to a procedure that can be called by implicit + // interface, allow any character actual arguments to be passed to dummy + // arguments of any type and vice versa. + mlir::Value cast; + auto *context = builder.getContext(); + if (snd.isa() && + fst.getType().isa()) { + auto funcTy = mlir::FunctionType::get(context, llvm::None, llvm::None); + auto boxProcTy = builder.getBoxProcType(funcTy); + if (mlir::Value host = argumentHostAssocs(converter, fst)) { + cast = builder.create( + loc, boxProcTy, llvm::ArrayRef{fst, host}); + } else { + cast = builder.create(loc, boxProcTy, fst); + } + } else { + mlir::Type fromTy = fir::unwrapRefType(fst.getType()); + if (fir::isa_builtin_cptr_type(fromTy) && + Fortran::lower::isCPtrArgByValueType(snd)) { + cast = genRecordCPtrValueArg(converter, fst, fromTy); + } else if (fir::isa_derived(snd)) { + // FIXME: This seems like a serious bug elsewhere in lowering. Paper + // over the problem for now. + TODO(loc, "derived type argument passed by value"); + } else { + cast = builder.convertWithSemantics(loc, snd, fst, + callingImplicitInterface); + } + } + operands.push_back(cast); + } + + // Add host associations as necessary. + if (addHostAssociations) + operands.push_back(converter.hostAssocTupleValue()); + + mlir::Value callResult; + unsigned callNumResults; + if (caller.requireDispatchCall()) { + // Procedure call requiring a dynamic dispatch. Call is created with + // fir.dispatch. + + // Get the raw procedure name. The procedure name is not mangled in the + // binding table. + const auto &ultimateSymbol = + caller.getCallDescription().proc().GetSymbol()->GetUltimate(); + auto procName = toStringRef(ultimateSymbol.name()); + + fir::DispatchOp dispatch; + if (std::optional passArg = caller.getPassArgIndex()) { + // PASS, PASS(arg-name) + dispatch = builder.create( + loc, funcType.getResults(), builder.getStringAttr(procName), + operands[*passArg], operands, builder.getI32IntegerAttr(*passArg)); + } else { + // NOPASS + const Fortran::evaluate::Component *component = + caller.getCallDescription().proc().GetComponent(); + assert(component && "expect component for type-bound procedure call."); + fir::ExtendedValue pass = + symMap.lookupSymbol(component->GetFirstSymbol()).toExtendedValue(); + mlir::Value passObject = fir::getBase(pass); + if (fir::isa_ref_type(passObject.getType())) + passObject = builder.create( + loc, passObject.getType().dyn_cast().getEleTy(), + passObject); + dispatch = builder.create( + loc, funcType.getResults(), builder.getStringAttr(procName), + passObject, operands, nullptr); + } + callResult = dispatch.getResult(0); + callNumResults = dispatch.getNumResults(); + } else { + // Standard procedure call with fir.call. + auto call = builder.create(loc, funcType.getResults(), + funcSymbolAttr, operands); + callResult = call.getResult(0); + callNumResults = call.getNumResults(); + } + + if (caller.mustSaveResult()) + builder.create(loc, callResult, + fir::getBase(allocatedResult.value()), + arrayResultShape, resultLengths); + + if (allocatedResult) { + allocatedResult->match( + [&](const fir::MutableBoxValue &box) { + if (box.isAllocatable()) { + // 9.7.3.2 point 4. Finalize allocatables. + fir::FirOpBuilder *bldr = &converter.getFirOpBuilder(); + stmtCtx.attachCleanup([bldr, loc, box]() { + fir::factory::genFinalization(*bldr, loc, box); + }); + } + }, + [](const auto &) {}); + return *allocatedResult; + } + + if (!resultType) + return mlir::Value{}; // subroutine call + // For now, Fortran return values are implemented with a single MLIR + // function return value. + assert(callNumResults == 1 && "Expected exactly one result in FUNCTION call"); + (void)callNumResults; + + // Call a BIND(C) function that return a char. + if (caller.characterize().IsBindC() && + funcType.getResults()[0].isa()) { + fir::CharacterType charTy = + funcType.getResults()[0].dyn_cast(); + mlir::Value len = builder.createIntegerConstant( + loc, builder.getCharacterLengthType(), charTy.getLen()); + return fir::CharBoxValue{callResult, len}; + } + + return callResult; +} diff --git a/flang/lib/Lower/ConvertExpr.cpp b/flang/lib/Lower/ConvertExpr.cpp --- a/flang/lib/Lower/ConvertExpr.cpp +++ b/flang/lib/Lower/ConvertExpr.cpp @@ -22,6 +22,7 @@ #include "flang/Lower/CallInterface.h" #include "flang/Lower/Coarray.h" #include "flang/Lower/ComponentPath.h" +#include "flang/Lower/ConvertCall.h" #include "flang/Lower/ConvertConstant.h" #include "flang/Lower/ConvertType.h" #include "flang/Lower/ConvertVariable.h" @@ -517,21 +518,6 @@ return false; } -/// If \p arg is the address of a function with a denoted host-association tuple -/// argument, then return the host-associations tuple value of the current -/// procedure. Otherwise, return nullptr. -static mlir::Value -argumentHostAssocs(Fortran::lower::AbstractConverter &converter, - mlir::Value arg) { - if (auto addr = mlir::dyn_cast_or_null(arg.getDefiningOp())) { - auto &builder = converter.getFirOpBuilder(); - if (auto funcOp = builder.getNamedFunction(addr.getSymbol())) - if (fir::anyFuncArgsHaveAttr(funcOp, fir::getHostAssocAttrName())) - return converter.hostAssocTupleValue(); - } - return {}; -} - /// \p argTy must be a tuple (pair) of boxproc and integral types. Convert the /// \p funcAddr argument to a boxproc value, with the host-association as /// required. Call the factory function to finish creating the tuple value. @@ -544,7 +530,7 @@ mlir::Location loc = converter.getCurrentLocation(); auto &builder = converter.getFirOpBuilder(); auto boxProc = [&]() -> mlir::Value { - if (auto host = argumentHostAssocs(converter, funcAddr)) + if (auto host = Fortran::lower::argumentHostAssocs(converter, funcAddr)) return builder.create( loc, boxTy, llvm::ArrayRef{funcAddr, host}); return builder.create(loc, boxTy, funcAddr); @@ -2108,51 +2094,6 @@ return result; } - /// Helper to package a Value and its properties into an ExtendedValue. - static ExtValue toExtendedValue(mlir::Location loc, mlir::Value base, - llvm::ArrayRef extents, - llvm::ArrayRef lengths) { - mlir::Type type = base.getType(); - if (type.isa()) - return fir::BoxValue(base, /*lbounds=*/{}, lengths, extents); - type = fir::unwrapRefType(type); - if (type.isa()) - return fir::MutableBoxValue(base, lengths, /*mutableProperties*/ {}); - if (auto seqTy = type.dyn_cast()) { - if (seqTy.getDimension() != extents.size()) - fir::emitFatalError(loc, "incorrect number of extents for array"); - if (seqTy.getEleTy().isa()) { - if (lengths.empty()) - fir::emitFatalError(loc, "missing length for character"); - assert(lengths.size() == 1); - return fir::CharArrayBoxValue(base, lengths[0], extents); - } - return fir::ArrayBoxValue(base, extents); - } - if (type.isa()) { - if (lengths.empty()) - fir::emitFatalError(loc, "missing length for character"); - assert(lengths.size() == 1); - return fir::CharBoxValue(base, lengths[0]); - } - return base; - } - - // Find the argument that corresponds to the host associations. - // Verify some assumptions about how the signature was built here. - [[maybe_unused]] static unsigned - findHostAssocTuplePos(mlir::func::FuncOp fn) { - // Scan the argument list from last to first as the host associations are - // appended for now. - for (unsigned i = fn.getNumArguments(); i > 0; --i) - if (fn.getArgAttr(i - 1, fir::getHostAssocAttrName())) { - // Host assoc tuple must be last argument (for now). - assert(i == fn.getNumArguments() && "tuple must be last"); - return i - 1; - } - llvm_unreachable("anyFuncArgsHaveAttr failed"); - } - /// Create a contiguous temporary array with the same shape, /// length parameters and type as mold. It is up to the caller to deallocate /// the temporary. @@ -2204,335 +2145,6 @@ return res; } - /// Lower a type(C_PTR/C_FUNPTR) argument with VALUE attribute into a - /// reference. A C pointer can correspond to a Fortran dummy argument of type - /// C_PTR with the VALUE attribute. (see 18.3.6 note 3). - static mlir::Value - genRecordCPtrValueArg(Fortran::lower::AbstractConverter &converter, - mlir::Value rec, mlir::Type ty) { - fir::FirOpBuilder &builder = converter.getFirOpBuilder(); - mlir::Location loc = converter.getCurrentLocation(); - mlir::Value cAddr = - fir::factory::genCPtrOrCFunptrAddr(builder, loc, rec, ty); - mlir::Value cVal = builder.create(loc, cAddr); - return builder.createConvert(loc, cAddr.getType(), cVal); - } - - /// Given a call site for which the arguments were already lowered, generate - /// the call and return the result. This function deals with explicit result - /// allocation and lowering if needed. It also deals with passing the host - /// link to internal procedures. - ExtValue genCallOpAndResult(Fortran::lower::CallerInterface &caller, - mlir::FunctionType callSiteType, - llvm::Optional resultType) { - mlir::Location loc = getLoc(); - using PassBy = Fortran::lower::CallerInterface::PassEntityBy; - // Handle cases where caller must allocate the result or a fir.box for it. - bool mustPopSymMap = false; - if (caller.mustMapInterfaceSymbols()) { - symMap.pushScope(); - mustPopSymMap = true; - Fortran::lower::mapCallInterfaceSymbols(converter, caller, symMap); - } - // If this is an indirect call, retrieve the function address. Also retrieve - // the result length if this is a character function (note that this length - // will be used only if there is no explicit length in the local interface). - mlir::Value funcPointer; - mlir::Value charFuncPointerLength; - if (const Fortran::semantics::Symbol *sym = - caller.getIfIndirectCallSymbol()) { - funcPointer = symMap.lookupSymbol(*sym).getAddr(); - if (!funcPointer) - fir::emitFatalError(loc, "failed to find indirect call symbol address"); - if (fir::isCharacterProcedureTuple(funcPointer.getType(), - /*acceptRawFunc=*/false)) - std::tie(funcPointer, charFuncPointerLength) = - fir::factory::extractCharacterProcedureTuple(builder, loc, - funcPointer); - } - - mlir::IndexType idxTy = builder.getIndexType(); - auto lowerSpecExpr = [&](const auto &expr) -> mlir::Value { - mlir::Value convertExpr = builder.createConvert( - loc, idxTy, fir::getBase(converter.genExprValue(expr, stmtCtx))); - return fir::factory::genMaxWithZero(builder, loc, convertExpr); - }; - llvm::SmallVector resultLengths; - auto allocatedResult = [&]() -> llvm::Optional { - llvm::SmallVector extents; - llvm::SmallVector lengths; - if (!caller.callerAllocateResult()) - return {}; - mlir::Type type = caller.getResultStorageType(); - if (type.isa()) - caller.walkResultExtents([&](const Fortran::lower::SomeExpr &e) { - extents.emplace_back(lowerSpecExpr(e)); - }); - caller.walkResultLengths([&](const Fortran::lower::SomeExpr &e) { - lengths.emplace_back(lowerSpecExpr(e)); - }); - - // Result length parameters should not be provided to box storage - // allocation and save_results, but they are still useful information to - // keep in the ExtendedValue if non-deferred. - if (!type.isa()) { - if (fir::isa_char(fir::unwrapSequenceType(type)) && lengths.empty()) { - // Calling an assumed length function. This is only possible if this - // is a call to a character dummy procedure. - if (!charFuncPointerLength) - fir::emitFatalError(loc, "failed to retrieve character function " - "length while calling it"); - lengths.push_back(charFuncPointerLength); - } - resultLengths = lengths; - } - - if (!extents.empty() || !lengths.empty()) { - auto *bldr = &converter.getFirOpBuilder(); - auto stackSaveFn = fir::factory::getLlvmStackSave(builder); - auto stackSaveSymbol = bldr->getSymbolRefAttr(stackSaveFn.getName()); - mlir::Value sp = - bldr->create( - loc, stackSaveFn.getFunctionType().getResults(), - stackSaveSymbol, mlir::ValueRange{}) - .getResult(0); - stmtCtx.attachCleanup([bldr, loc, sp]() { - auto stackRestoreFn = fir::factory::getLlvmStackRestore(*bldr); - auto stackRestoreSymbol = - bldr->getSymbolRefAttr(stackRestoreFn.getName()); - bldr->create( - loc, stackRestoreFn.getFunctionType().getResults(), - stackRestoreSymbol, mlir::ValueRange{sp}); - }); - } - mlir::Value temp = - builder.createTemporary(loc, type, ".result", extents, resultLengths); - return toExtendedValue(loc, temp, extents, lengths); - }(); - - if (mustPopSymMap) - symMap.popScope(); - - // Place allocated result or prepare the fir.save_result arguments. - mlir::Value arrayResultShape; - if (allocatedResult) { - if (std::optional::PassedEntity> - resultArg = caller.getPassedResult()) { - if (resultArg->passBy == PassBy::AddressAndLength) - caller.placeAddressAndLengthInput(*resultArg, - fir::getBase(*allocatedResult), - fir::getLen(*allocatedResult)); - else if (resultArg->passBy == PassBy::BaseAddress) - caller.placeInput(*resultArg, fir::getBase(*allocatedResult)); - else - fir::emitFatalError( - loc, "only expect character scalar result to be passed by ref"); - } else { - assert(caller.mustSaveResult()); - arrayResultShape = allocatedResult->match( - [&](const fir::CharArrayBoxValue &) { - return builder.createShape(loc, *allocatedResult); - }, - [&](const fir::ArrayBoxValue &) { - return builder.createShape(loc, *allocatedResult); - }, - [&](const auto &) { return mlir::Value{}; }); - } - } - - // In older Fortran, procedure argument types are inferred. This may lead - // different view of what the function signature is in different locations. - // Casts are inserted as needed below to accommodate this. - - // The mlir::func::FuncOp type prevails, unless it has a different number of - // arguments which can happen in legal program if it was passed as a dummy - // procedure argument earlier with no further type information. - mlir::SymbolRefAttr funcSymbolAttr; - bool addHostAssociations = false; - if (!funcPointer) { - mlir::FunctionType funcOpType = caller.getFuncOp().getFunctionType(); - mlir::SymbolRefAttr symbolAttr = - builder.getSymbolRefAttr(caller.getMangledName()); - if (callSiteType.getNumResults() == funcOpType.getNumResults() && - callSiteType.getNumInputs() + 1 == funcOpType.getNumInputs() && - fir::anyFuncArgsHaveAttr(caller.getFuncOp(), - fir::getHostAssocAttrName())) { - // The number of arguments is off by one, and we're lowering a function - // with host associations. Modify call to include host associations - // argument by appending the value at the end of the operands. - assert(funcOpType.getInput(findHostAssocTuplePos(caller.getFuncOp())) == - converter.hostAssocTupleValue().getType()); - addHostAssociations = true; - } - if (!addHostAssociations && - (callSiteType.getNumResults() != funcOpType.getNumResults() || - callSiteType.getNumInputs() != funcOpType.getNumInputs())) { - // Deal with argument number mismatch by making a function pointer so - // that function type cast can be inserted. Do not emit a warning here - // because this can happen in legal program if the function is not - // defined here and it was first passed as an argument without any more - // information. - funcPointer = - builder.create(loc, funcOpType, symbolAttr); - } else if (callSiteType.getResults() != funcOpType.getResults()) { - // Implicit interface result type mismatch are not standard Fortran, but - // some compilers are not complaining about it. The front end is not - // protecting lowering from this currently. Support this with a - // discouraging warning. - LLVM_DEBUG(mlir::emitWarning( - loc, "a return type mismatch is not standard compliant and may " - "lead to undefined behavior.")); - // Cast the actual function to the current caller implicit type because - // that is the behavior we would get if we could not see the definition. - funcPointer = - builder.create(loc, funcOpType, symbolAttr); - } else { - funcSymbolAttr = symbolAttr; - } - } - - mlir::FunctionType funcType = - funcPointer ? callSiteType : caller.getFuncOp().getFunctionType(); - llvm::SmallVector operands; - // First operand of indirect call is the function pointer. Cast it to - // required function type for the call to handle procedures that have a - // compatible interface in Fortran, but that have different signatures in - // FIR. - if (funcPointer) { - operands.push_back( - funcPointer.getType().isa() - ? builder.create(loc, funcType, funcPointer) - : builder.createConvert(loc, funcType, funcPointer)); - } - - // Deal with potential mismatches in arguments types. Passing an array to a - // scalar argument should for instance be tolerated here. - bool callingImplicitInterface = caller.canBeCalledViaImplicitInterface(); - for (auto [fst, snd] : - llvm::zip(caller.getInputs(), funcType.getInputs())) { - // When passing arguments to a procedure that can be called by implicit - // interface, allow any character actual arguments to be passed to dummy - // arguments of any type and vice versa. - mlir::Value cast; - auto *context = builder.getContext(); - if (snd.isa() && - fst.getType().isa()) { - auto funcTy = mlir::FunctionType::get(context, llvm::None, llvm::None); - auto boxProcTy = builder.getBoxProcType(funcTy); - if (mlir::Value host = argumentHostAssocs(converter, fst)) { - cast = builder.create( - loc, boxProcTy, llvm::ArrayRef{fst, host}); - } else { - cast = builder.create(loc, boxProcTy, fst); - } - } else { - mlir::Type fromTy = fir::unwrapRefType(fst.getType()); - if (fir::isa_builtin_cptr_type(fromTy) && - Fortran::lower::isCPtrArgByValueType(snd)) { - cast = genRecordCPtrValueArg(converter, fst, fromTy); - } else if (fir::isa_derived(snd)) { - // FIXME: This seems like a serious bug elsewhere in lowering. Paper - // over the problem for now. - TODO(loc, "derived type argument passed by value"); - } else { - cast = builder.convertWithSemantics(loc, snd, fst, - callingImplicitInterface); - } - } - operands.push_back(cast); - } - - // Add host associations as necessary. - if (addHostAssociations) - operands.push_back(converter.hostAssocTupleValue()); - - mlir::Value callResult; - unsigned callNumResults; - if (caller.requireDispatchCall()) { - // Procedure call requiring a dynamic dispatch. Call is created with - // fir.dispatch. - - // Get the raw procedure name. The procedure name is not mangled in the - // binding table. - const auto &ultimateSymbol = - caller.getCallDescription().proc().GetSymbol()->GetUltimate(); - auto procName = toStringRef(ultimateSymbol.name()); - - fir::DispatchOp dispatch; - if (std::optional passArg = caller.getPassArgIndex()) { - // PASS, PASS(arg-name) - dispatch = builder.create( - loc, funcType.getResults(), builder.getStringAttr(procName), - operands[*passArg], operands, builder.getI32IntegerAttr(*passArg)); - } else { - // NOPASS - const Fortran::evaluate::Component *component = - caller.getCallDescription().proc().GetComponent(); - assert(component && "expect component for type-bound procedure call."); - fir::ExtendedValue pass = - symMap.lookupSymbol(component->GetFirstSymbol()).toExtendedValue(); - mlir::Value passObject = fir::getBase(pass); - if (fir::isa_ref_type(passObject.getType())) - passObject = builder.create( - loc, - passObject.getType().dyn_cast().getEleTy(), - passObject); - dispatch = builder.create( - loc, funcType.getResults(), builder.getStringAttr(procName), - passObject, operands, nullptr); - } - callResult = dispatch.getResult(0); - callNumResults = dispatch.getNumResults(); - } else { - // Standard procedure call with fir.call. - auto call = builder.create(loc, funcType.getResults(), - funcSymbolAttr, operands); - callResult = call.getResult(0); - callNumResults = call.getNumResults(); - } - - if (caller.mustSaveResult()) - builder.create(loc, callResult, - fir::getBase(allocatedResult.value()), - arrayResultShape, resultLengths); - - if (allocatedResult) { - allocatedResult->match( - [&](const fir::MutableBoxValue &box) { - if (box.isAllocatable()) { - // 9.7.3.2 point 4. Finalize allocatables. - fir::FirOpBuilder *bldr = &converter.getFirOpBuilder(); - stmtCtx.attachCleanup([bldr, loc, box]() { - fir::factory::genFinalization(*bldr, loc, box); - }); - } - }, - [](const auto &) {}); - return *allocatedResult; - } - - if (!resultType) - return mlir::Value{}; // subroutine call - // For now, Fortran return values are implemented with a single MLIR - // function return value. - assert(callNumResults == 1 && - "Expected exactly one result in FUNCTION call"); - (void)callNumResults; - - // Call a BIND(C) function that return a char. - if (caller.characterize().IsBindC() && - funcType.getResults()[0].isa()) { - fir::CharacterType charTy = - funcType.getResults()[0].dyn_cast(); - mlir::Value len = builder.createIntegerConstant( - loc, builder.getCharacterLengthType(), charTy.getLen()); - return fir::CharBoxValue{callResult, len}; - } - - return callResult; - } - /// Like genExtAddr, but ensure the address returned is a temporary even if \p /// expr is variable inside parentheses. ExtValue genTempExtAddr(const Fortran::lower::SomeExpr &expr) { @@ -3155,7 +2767,8 @@ } } - ExtValue result = genCallOpAndResult(caller, callSiteType, resultType); + ExtValue result = Fortran::lower::genCallOpAndResult( + loc, converter, symMap, stmtCtx, caller, callSiteType, resultType); // Sync pointers and allocatables that may have been modified during the // call. @@ -5033,22 +4646,22 @@ fir::emitFatalError(loc, "cannot be indirect call"); // The lambda is mutable so that `caller` copy can be modified inside it. - return - [=, caller = std::move(caller)](IterSpace iters) mutable -> ExtValue { - for (const auto &[cc, argIface] : - llvm::zip(operands, caller.getPassedArguments())) { - auto exv = cc(iters); - auto arg = exv.match( - [&](const fir::CharBoxValue &cb) -> mlir::Value { - return fir::factory::CharacterExprHelper{builder, loc} - .createEmbox(cb); - }, - [&](const auto &) { return fir::getBase(exv); }); - caller.placeInput(argIface, arg); - } - return ScalarExprLowering{loc, converter, symMap, getElementCtx()} - .genCallOpAndResult(caller, callSiteType, retTy); - }; + return [=, + caller = std::move(caller)](IterSpace iters) mutable -> ExtValue { + for (const auto &[cc, argIface] : + llvm::zip(operands, caller.getPassedArguments())) { + auto exv = cc(iters); + auto arg = exv.match( + [&](const fir::CharBoxValue &cb) -> mlir::Value { + return fir::factory::CharacterExprHelper{builder, loc} + .createEmbox(cb); + }, + [&](const auto &) { return fir::getBase(exv); }); + caller.placeInput(argIface, arg); + } + return Fortran::lower::genCallOpAndResult( + loc, converter, symMap, getElementCtx(), caller, callSiteType, retTy); + }; } /// Lower TRANSPOSE call without using runtime TRANSPOSE. diff --git a/flang/lib/Lower/ConvertExprToHLFIR.cpp b/flang/lib/Lower/ConvertExprToHLFIR.cpp --- a/flang/lib/Lower/ConvertExprToHLFIR.cpp +++ b/flang/lib/Lower/ConvertExprToHLFIR.cpp @@ -334,6 +334,25 @@ TODO(getLoc(), "lowering binary op to HLFIR"); } + template + hlfir::EntityWithAttributes gen(const Fortran::evaluate::Concat &op) { + auto lhs = gen(op.left()); + auto rhs = gen(op.right()); + llvm::SmallVector lengths; + auto &builder = getBuilder(); + mlir::Location loc = getLoc(); + hlfir::genLengthParameters(loc, builder, lhs, lengths); + hlfir::genLengthParameters(loc, builder, rhs, lengths); + assert(lengths.size() == 2 && "lacks rhs or lhs length"); + mlir::Type idxType = builder.getIndexType(); + mlir::Value lhsLen = builder.createConvert(loc, idxType, lengths[0]); + mlir::Value rhsLen = builder.createConvert(loc, idxType, lengths[1]); + mlir::Value len = builder.create(loc, lhsLen, rhsLen); + auto concat = + builder.create(loc, mlir::ValueRange{lhs, rhs}, len); + return hlfir::EntityWithAttributes{concat.getResult()}; + } + hlfir::EntityWithAttributes gen(const Fortran::evaluate::Relational &op) { return std::visit([&](const auto &x) { return gen(x); }, op.u); diff --git a/flang/lib/Lower/ConvertType.cpp b/flang/lib/Lower/ConvertType.cpp --- a/flang/lib/Lower/ConvertType.cpp +++ b/flang/lib/Lower/ConvertType.cpp @@ -142,7 +142,9 @@ Fortran::common::TypeCategory category = dynamicType->category(); mlir::Type baseType; - if (category == Fortran::common::TypeCategory::Derived) { + if (dynamicType->IsUnlimitedPolymorphic()) { + baseType = mlir::NoneType::get(context); + } else if (category == Fortran::common::TypeCategory::Derived) { baseType = genDerivedType(dynamicType->GetDerivedTypeSpec()); } else { // LOGICAL, INTEGER, REAL, COMPLEX, CHARACTER diff --git a/flang/lib/Lower/IntrinsicCall.cpp b/flang/lib/Lower/IntrinsicCall.cpp --- a/flang/lib/Lower/IntrinsicCall.cpp +++ b/flang/lib/Lower/IntrinsicCall.cpp @@ -530,6 +530,7 @@ mlir::Value genLeadz(mlir::Type, llvm::ArrayRef); fir::ExtendedValue genLen(mlir::Type, llvm::ArrayRef); fir::ExtendedValue genLenTrim(mlir::Type, llvm::ArrayRef); + fir::ExtendedValue genLoc(mlir::Type, llvm::ArrayRef); template mlir::Value genMask(mlir::Type, llvm::ArrayRef); fir::ExtendedValue genMatmul(mlir::Type, llvm::ArrayRef); @@ -879,6 +880,7 @@ {"lgt", &I::genCharacterCompare}, {"lle", &I::genCharacterCompare}, {"llt", &I::genCharacterCompare}, + {"loc", &I::genLoc, {{{"x", asBox}}}, /*isElemental=*/false}, {"maskl", &I::genMask}, {"maskr", &I::genMask}, {"matmul", @@ -2672,6 +2674,22 @@ return builder.createConvert(loc, resultType, res); } +static mlir::Value getAddrFromBox(fir::FirOpBuilder &builder, + mlir::Location loc, fir::ExtendedValue arg, + bool isFunc) { + mlir::Value argValue = fir::getBase(arg); + mlir::Value addr{nullptr}; + if (isFunc) { + auto funcTy = argValue.getType().cast().getEleTy(); + addr = builder.create(loc, funcTy, argValue); + } else { + const auto *box = arg.getBoxOf(); + addr = builder.create(loc, box->getMemTy(), + fir::getBase(*box)); + } + return addr; +} + static fir::ExtendedValue genCLocOrCFunLoc(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type resultType, llvm::ArrayRef args, @@ -2680,19 +2698,9 @@ mlir::Value res = builder.create(loc, resultType); mlir::Value resAddr = fir::factory::genCPtrOrCFunptrAddr(builder, loc, res, resultType); - mlir::Value argAddr; - if (isFunc) { - mlir::Value argValue = fir::getBase(args[0]); - assert(argValue.getType().isa() && - "c_funloc argument must have been lowered to a fir.boxproc"); - auto funcTy = argValue.getType().cast().getEleTy(); - argAddr = builder.create(loc, funcTy, argValue); - } else { - const auto *box = args[0].getBoxOf(); - assert(box && "c_loc argument must have been lowered to a fir.box"); - argAddr = builder.create(loc, box->getMemTy(), - fir::getBase(*box)); - } + assert(fir::isa_box_type(fir::getBase(args[0]).getType()) && + "argument must have been lowered to box type"); + mlir::Value argAddr = getAddrFromBox(builder, loc, args[0], isFunc); mlir::Value argAddrVal = builder.createConvert( loc, fir::unwrapRefType(resAddr.getType()), argAddr); builder.create(loc, argAddrVal, resAddr); @@ -3748,6 +3756,19 @@ fir::getBase(args[1]), fir::getLen(args[1])); } +// LOC +fir::ExtendedValue +IntrinsicLibrary::genLoc(mlir::Type resultType, + llvm::ArrayRef args) { + assert(args.size() == 1); + mlir::Value argValue = fir::getBase(args[0]); + assert(fir::isa_box_type(argValue.getType()) && + "argument must have been lowered to box type"); + bool isFunc = argValue.getType().isa(); + mlir::Value argAddr = getAddrFromBox(builder, loc, args[0], isFunc); + return builder.createConvert(loc, fir::unwrapRefType(resultType), argAddr); +} + // MASKL, MASKR template mlir::Value IntrinsicLibrary::genMask(mlir::Type resultType, diff --git a/flang/lib/Optimizer/Builder/HLFIRTools.cpp b/flang/lib/Optimizer/Builder/HLFIRTools.cpp --- a/flang/lib/Optimizer/Builder/HLFIRTools.cpp +++ b/flang/lib/Optimizer/Builder/HLFIRTools.cpp @@ -212,10 +212,16 @@ llvm::SmallVectorImpl &result) { if (!entity.hasLengthParameters()) return; - if (entity.getType().isa()) + if (entity.getType().isa()) { // Going through fir::ExtendedValue would create a temp, // which is not desired for an inquiry. + // TODO: make this an interface when adding further character producing ops. + if (auto concat = entity.getDefiningOp()) { + result.push_back(concat.getLength()); + return; + } TODO(loc, "inquire type parameters of hlfir.expr"); + } if (entity.isCharacter()) { auto [exv, cleanup] = translateToExtendedValue(loc, builder, entity); diff --git a/flang/lib/Optimizer/CodeGen/CodeGen.cpp b/flang/lib/Optimizer/CodeGen/CodeGen.cpp --- a/flang/lib/Optimizer/CodeGen/CodeGen.cpp +++ b/flang/lib/Optimizer/CodeGen/CodeGen.cpp @@ -1468,21 +1468,19 @@ /// Get the address of the type descriptor global variable that was created by /// lowering for derived type \p recType. - template - mlir::Value - getTypeDescriptor(BOX box, mlir::ConversionPatternRewriter &rewriter, - mlir::Location loc, fir::RecordType recType) const { + mlir::Value getTypeDescriptor(mlir::ModuleOp mod, + mlir::ConversionPatternRewriter &rewriter, + mlir::Location loc, + fir::RecordType recType) const { std::string name = fir::NameUniquer::getTypeDescriptorName(recType.getName()); - auto module = box->template getParentOfType(); - if (auto global = module.template lookupSymbol(name)) { + if (auto global = mod.template lookupSymbol(name)) { auto ty = mlir::LLVM::LLVMPointerType::get( this->lowerTy().convertType(global.getType())); return rewriter.create(loc, ty, global.getSymName()); } - if (auto global = - module.template lookupSymbol(name)) { + if (auto global = mod.template lookupSymbol(name)) { // The global may have already been translated to LLVM. auto ty = mlir::LLVM::LLVMPointerType::get(global.getType()); return rewriter.create(loc, ty, @@ -1496,31 +1494,21 @@ fir::emitFatalError( loc, "runtime derived type info descriptor was not generated"); return rewriter.create( - loc, ::getVoidPtrType(box.getContext())); + loc, ::getVoidPtrType(mod.getContext())); } - template - std::tuple - consDescriptorPrefix(BOX box, mlir::ConversionPatternRewriter &rewriter, - unsigned rank, mlir::ValueRange lenParams, - mlir::Value typeDesc = {}) const { - auto loc = box.getLoc(); - auto boxTy = box.getType().template dyn_cast(); + mlir::Value populateDescriptor(mlir::Location loc, mlir::ModuleOp mod, + fir::BaseBoxType boxTy, mlir::Type inputType, + mlir::ConversionPatternRewriter &rewriter, + unsigned rank, mlir::Value eleSize, + mlir::Value cfiTy, + mlir::Value typeDesc) const { auto convTy = this->lowerTy().convertBoxType(boxTy, rank); auto llvmBoxPtrTy = convTy.template cast(); auto llvmBoxTy = llvmBoxPtrTy.getElementType(); + bool isUnlimitedPolymorphic = fir::isUnlimitedPolymorphicType(boxTy); mlir::Value descriptor = rewriter.create(loc, llvmBoxTy); - - llvm::SmallVector typeparams = lenParams; - if constexpr (!std::is_same_v) { - if (!box.getSubstr().empty() && fir::hasDynamicSize(boxTy.getEleTy())) - typeparams.push_back(box.getSubstr()[1]); - } - - // Write each of the fields with the appropriate values - auto [eleSize, cfiTy] = - getSizeAndTypeCode(loc, rewriter, boxTy.getEleTy(), typeparams); descriptor = insertField(rewriter, loc, descriptor, {kElemLenPosInBox}, eleSize); descriptor = insertField(rewriter, loc, descriptor, {kVersionPosInBox}, @@ -1531,20 +1519,98 @@ descriptor = insertField(rewriter, loc, descriptor, {kAttributePosInBox}, this->genI32Constant(loc, rewriter, getCFIAttr(boxTy))); - const bool hasAddendum = isDerivedType(boxTy); + const bool hasAddendum = isDerivedType(boxTy) || isUnlimitedPolymorphic; descriptor = insertField(rewriter, loc, descriptor, {kF18AddendumPosInBox}, this->genI32Constant(loc, rewriter, hasAddendum ? 1 : 0)); if (hasAddendum) { unsigned typeDescFieldId = getTypeDescFieldId(boxTy); - if (!typeDesc) - typeDesc = - getTypeDescriptor(box, rewriter, loc, unwrapIfDerived(boxTy)); - descriptor = - insertField(rewriter, loc, descriptor, {typeDescFieldId}, typeDesc, - /*bitCast=*/true); + if (!typeDesc) { + if (isUnlimitedPolymorphic) { + mlir::Type innerType = fir::unwrapInnerType(inputType); + if (innerType && innerType.template isa()) { + auto recTy = innerType.template dyn_cast(); + typeDesc = getTypeDescriptor(mod, rewriter, loc, recTy); + } else { + // Unlimited polymorphic type descriptor with no record type. Set + // type descriptor address to a clean state. + typeDesc = rewriter.create( + loc, ::getVoidPtrType(mod.getContext())); + } + } else { + typeDesc = + getTypeDescriptor(mod, rewriter, loc, unwrapIfDerived(boxTy)); + } + } + if (typeDesc) + descriptor = + insertField(rewriter, loc, descriptor, {typeDescFieldId}, typeDesc, + /*bitCast=*/true); } + return descriptor; + } + + // Template used for fir::EmboxOp and fir::cg::XEmboxOp + template + std::tuple + consDescriptorPrefix(BOX box, mlir::Type inputType, + mlir::ConversionPatternRewriter &rewriter, unsigned rank, + mlir::ValueRange lenParams, + mlir::Value typeDesc = {}) const { + auto loc = box.getLoc(); + auto boxTy = box.getType().template dyn_cast(); + bool isUnlimitedPolymorphic = fir::isUnlimitedPolymorphicType(boxTy); + bool useInputType = + isUnlimitedPolymorphic && !fir::isUnlimitedPolymorphicType(inputType); + llvm::SmallVector typeparams = lenParams; + if constexpr (!std::is_same_v) { + if (!box.getSubstr().empty() && fir::hasDynamicSize(boxTy.getEleTy())) + typeparams.push_back(box.getSubstr()[1]); + } + + // Write each of the fields with the appropriate values. + // When emboxing an element to a unlimited polymorphic descriptor, use the + // input type since the destination descriptor type as no type information. + auto [eleSize, cfiTy] = getSizeAndTypeCode( + loc, rewriter, useInputType ? inputType : boxTy.getEleTy(), typeparams); + auto mod = box->template getParentOfType(); + mlir::Value descriptor = populateDescriptor( + loc, mod, boxTy, inputType, rewriter, rank, eleSize, cfiTy, typeDesc); + + return {boxTy, descriptor, eleSize}; + } + + std::tuple + consDescriptorPrefix(fir::cg::XReboxOp box, mlir::Value loweredBox, + mlir::ConversionPatternRewriter &rewriter, unsigned rank, + mlir::ValueRange lenParams, + mlir::Value typeDesc = {}) const { + auto loc = box.getLoc(); + auto boxTy = box.getType().dyn_cast(); + llvm::SmallVector typeparams = lenParams; + if (!box.getSubstr().empty() && fir::hasDynamicSize(boxTy.getEleTy())) + typeparams.push_back(box.getSubstr()[1]); + + auto [eleSize, cfiTy] = + getSizeAndTypeCode(loc, rewriter, boxTy.getEleTy(), typeparams); + + // Reboxing an unlimited polymorphic entities. eleSize and type code need to + // be retrived from the initial box. + if (fir::isUnlimitedPolymorphicType(boxTy) && + fir::isUnlimitedPolymorphicType(box.getBox().getType())) { + mlir::Type idxTy = this->lowerTy().indexType(); + eleSize = this->loadElementSizeFromBox(loc, idxTy, loweredBox, rewriter); + cfiTy = this->getValueFromBox(loc, loweredBox, cfiTy.getType(), rewriter, + kTypePosInBox); + typeDesc = this->loadTypeDescAddress(loc, box.getBox().getType(), + loweredBox, rewriter); + } + + auto mod = box->template getParentOfType(); + mlir::Value descriptor = + populateDescriptor(loc, mod, boxTy, box.getBox().getType(), rewriter, + rank, eleSize, cfiTy, typeDesc); return {boxTy, descriptor, eleSize}; } @@ -1674,7 +1740,7 @@ tdesc = operands[embox.getTdescOffset()]; assert(!embox.getShape() && "There should be no dims on this embox op"); auto [boxTy, dest, eleSize] = consDescriptorPrefix( - embox, rewriter, + embox, fir::unwrapRefType(embox.getMemref().getType()), rewriter, /*rank=*/0, /*lenParams=*/operands.drop_front(1), tdesc); dest = insertBaseAddress(rewriter, embox.getLoc(), dest, operands[0]); if (isDerivedTypeWithLenParams(boxTy)) { @@ -1699,9 +1765,9 @@ mlir::Value tdesc; if (xbox.getTdesc()) tdesc = operands[xbox.getTdescOffset()]; - auto [boxTy, dest, eleSize] = - consDescriptorPrefix(xbox, rewriter, xbox.getOutRank(), - operands.drop_front(xbox.lenParamOffset()), tdesc); + auto [boxTy, dest, eleSize] = consDescriptorPrefix( + xbox, fir::unwrapRefType(xbox.getMemref().getType()), rewriter, + xbox.getOutRank(), operands.drop_front(xbox.lenParamOffset()), tdesc); // Generate the triples in the dims field of the descriptor auto i64Ty = mlir::IntegerType::get(xbox.getContext(), 64); mlir::Value base = operands[0]; @@ -1908,8 +1974,9 @@ typeDescAddr = loadTypeDescAddress(loc, rebox.getBox().getType(), loweredBox, rewriter); - auto [boxTy, dest, eleSize] = consDescriptorPrefix( - rebox, rewriter, rebox.getOutRank(), lenParams, typeDescAddr); + auto [boxTy, dest, eleSize] = + consDescriptorPrefix(rebox, loweredBox, rewriter, rebox.getOutRank(), + lenParams, typeDescAddr); // Read input extents, strides, and base address llvm::SmallVector inputExtents; diff --git a/flang/lib/Optimizer/CodeGen/TypeConverter.h b/flang/lib/Optimizer/CodeGen/TypeConverter.h --- a/flang/lib/Optimizer/CodeGen/TypeConverter.h +++ b/flang/lib/Optimizer/CodeGen/TypeConverter.h @@ -244,7 +244,7 @@ dataDescFields.push_back(mlir::LLVM::LLVMArrayType::get(rowTy, rank)); } // opt-type-ptr: i8* (see fir.tdesc) - if (requiresExtendedDesc(ele)) { + if (requiresExtendedDesc(ele) || fir::isUnlimitedPolymorphicType(box)) { dataDescFields.push_back( getExtendedDescFieldTypeModel()(&getContext())); auto rowTy = diff --git a/flang/lib/Optimizer/Dialect/FIROps.cpp b/flang/lib/Optimizer/Dialect/FIROps.cpp --- a/flang/lib/Optimizer/Dialect/FIROps.cpp +++ b/flang/lib/Optimizer/Dialect/FIROps.cpp @@ -2302,7 +2302,7 @@ // the types is a character with dynamic length, the other type can be any // character type. const bool typeCanMismatch = - inputEleTy.isa() || + inputEleTy.isa() || outEleTy.isa() || (getSlice() && inputEleTy.isa()) || areCompatibleCharacterTypes(inputEleTy, outEleTy); if (!typeCanMismatch) diff --git a/flang/lib/Optimizer/Dialect/FIRType.cpp b/flang/lib/Optimizer/Dialect/FIRType.cpp --- a/flang/lib/Optimizer/Dialect/FIRType.cpp +++ b/flang/lib/Optimizer/Dialect/FIRType.cpp @@ -308,6 +308,17 @@ return isAssumedType(ty); } +mlir::Type unwrapInnerType(mlir::Type ty) { + return llvm::TypeSwitch(ty) + .Case([](auto t) { + mlir::Type eleTy = t.getEleTy(); + if (auto seqTy = eleTy.dyn_cast()) + return seqTy.getEleTy(); + return eleTy; + }) + .Default([](mlir::Type) { return mlir::Type{}; }); +} + bool isRecordWithAllocatableMember(mlir::Type ty) { if (auto recTy = ty.dyn_cast()) for (auto [field, memTy] : recTy.getTypeList()) { @@ -987,14 +998,7 @@ } mlir::Type BaseBoxType::unwrapInnerType() const { - return llvm::TypeSwitch(getEleTy()) - .Case([](auto ty) { - mlir::Type eleTy = ty.getEleTy(); - if (auto seqTy = eleTy.dyn_cast()) - return seqTy.getEleTy(); - return eleTy; - }) - .Default([](mlir::Type) { return mlir::Type{}; }); + return fir::unwrapInnerType(getEleTy()); } //===----------------------------------------------------------------------===// diff --git a/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp b/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp --- a/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp +++ b/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp @@ -85,3 +85,17 @@ .Case([](auto) { return true; }) .Default([](mlir::Type) { return false; }); } + +bool hlfir::isFortranScalarCharacterType(mlir::Type type) { + return isFortranScalarCharacterExprType(type) || + type.isa() || + fir::unwrapPassByRefType(fir::unwrapRefType(type)) + .isa(); +} + +bool hlfir::isFortranScalarCharacterExprType(mlir::Type type) { + if (auto exprType = type.dyn_cast()) + return exprType.isScalar() && + exprType.getElementType().isa(); + return false; +} diff --git a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp --- a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp +++ b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp @@ -337,5 +337,52 @@ return mlir::success(); } +//===----------------------------------------------------------------------===// +// ConcatOp +//===----------------------------------------------------------------------===// + +static unsigned getCharacterKind(mlir::Type t) { + return hlfir::getFortranElementType(t).cast().getFKind(); +} + +static llvm::Optional +getCharacterLengthIfStatic(mlir::Type t) { + if (auto charType = + hlfir::getFortranElementType(t).dyn_cast()) + if (charType.hasConstantLen()) + return charType.getLen(); + return llvm::None; +} + +mlir::LogicalResult hlfir::ConcatOp::verify() { + if (getStrings().size() < 2) + return emitOpError("must be provided at least two string operands"); + unsigned kind = getCharacterKind(getResult().getType()); + for (auto string : getStrings()) + if (kind != getCharacterKind(string.getType())) + return emitOpError("strings must have the same KIND as the result type"); + return mlir::success(); +} + +void hlfir::ConcatOp::build(mlir::OpBuilder &builder, + mlir::OperationState &result, + mlir::ValueRange strings, mlir::Value len) { + fir::CharacterType::LenType resultTypeLen = 0; + assert(!strings.empty() && "must contain operands"); + unsigned kind = getCharacterKind(strings[0].getType()); + for (auto string : strings) + if (auto cstLen = getCharacterLengthIfStatic(string.getType())) { + resultTypeLen += *cstLen; + } else { + resultTypeLen = fir::CharacterType::unknownLen(); + break; + } + auto resultType = hlfir::ExprType::get( + builder.getContext(), hlfir::ExprType::Shape{}, + fir::CharacterType::get(builder.getContext(), kind, resultTypeLen), + false); + build(builder, result, resultType, strings, len); +} + #define GET_OP_CLASSES #include "flang/Optimizer/HLFIR/HLFIROps.cpp.inc" diff --git a/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp b/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp new file mode 100644 --- /dev/null +++ b/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp @@ -0,0 +1,114 @@ +//===- BufferizeHLFIR.cpp - Bufferize HLFIR ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// This file defines a pass that bufferize hlfir.expr. It translates operations +// producing or consuming hlfir.expr into operations operating on memory. +//===----------------------------------------------------------------------===// + +#include "flang/Optimizer/Builder/Character.h" +#include "flang/Optimizer/Builder/FIRBuilder.h" +#include "flang/Optimizer/Builder/HLFIRTools.h" +#include "flang/Optimizer/Builder/MutableBox.h" +#include "flang/Optimizer/Builder/Runtime/Assign.h" +#include "flang/Optimizer/Builder/Todo.h" +#include "flang/Optimizer/Dialect/FIRDialect.h" +#include "flang/Optimizer/Dialect/FIROps.h" +#include "flang/Optimizer/Dialect/FIRType.h" +#include "flang/Optimizer/HLFIR/HLFIROps.h" +#include "flang/Optimizer/HLFIR/Passes.h" +#include "flang/Optimizer/Support/FIRContext.h" +#include "mlir/IR/PatternMatch.h" +#include "mlir/Pass/Pass.h" +#include "mlir/Pass/PassManager.h" +#include "mlir/Transforms/DialectConversion.h" + +namespace hlfir { +#define GEN_PASS_DEF_BUFFERIZEHLFIR +#include "flang/Optimizer/HLFIR/Passes.h.inc" +} // namespace hlfir + +namespace { + +struct AssignOpConversion : public mlir::OpConversionPattern { + using mlir::OpConversionPattern::OpConversionPattern; + explicit AssignOpConversion(mlir::MLIRContext *ctx) + : mlir::OpConversionPattern{ctx} {} + mlir::LogicalResult + matchAndRewrite(hlfir::AssignOp assign, OpAdaptor adaptor, + mlir::ConversionPatternRewriter &rewriter) const override { + rewriter.replaceOpWithNewOp( + assign, adaptor.getOperands()[0], adaptor.getOperands()[1]); + return mlir::success(); + } +}; + +struct ConcatOpConversion : public mlir::OpConversionPattern { + using mlir::OpConversionPattern::OpConversionPattern; + explicit ConcatOpConversion(mlir::MLIRContext *ctx) + : mlir::OpConversionPattern{ctx} {} + mlir::LogicalResult + matchAndRewrite(hlfir::ConcatOp concat, OpAdaptor adaptor, + mlir::ConversionPatternRewriter &rewriter) const override { + mlir::Location loc = concat->getLoc(); + auto module = concat->getParentOfType(); + fir::FirOpBuilder builder(rewriter, fir::getKindMapping(module)); + assert(adaptor.getStrings().size() >= 2 && + "must have at least two strings operands"); + if (adaptor.getStrings().size() > 2) + TODO(loc, "codegen of optimized chained concatenation of more than two " + "strings"); + hlfir::Entity lhs{adaptor.getStrings()[0]}; + hlfir::Entity rhs{adaptor.getStrings()[1]}; + auto [lhsExv, c1] = hlfir::translateToExtendedValue(loc, builder, lhs); + auto [rhsExv, c2] = hlfir::translateToExtendedValue(loc, builder, rhs); + assert(!c1 && !c2 && "expected variables"); + fir::ExtendedValue res = + fir::factory::CharacterExprHelper{builder, loc}.createConcatenate( + *lhsExv.getCharBox(), *rhsExv.getCharBox()); + auto hlfirTempRes = hlfir::genDeclare(loc, builder, res, "tmp", + fir::FortranVariableFlagsAttr{}); + rewriter.replaceOp(concat, hlfirTempRes); + return mlir::success(); + } +}; + +class BufferizeHLFIR : public hlfir::impl::BufferizeHLFIRBase { +public: + void runOnOperation() override { + // TODO: make this a pass operating on FuncOp. The issue is that + // FirOpBuilder helpers may generate new FuncOp because of runtime/llvm + // intrinsics calls creation. This may create race conflict if the pass is + // scheduleed on FuncOp. A solution could be to provide an optional mutex + // when building a FirOpBuilder and locking around FuncOp and GlobalOp + // creation, but this needs a bit more thinking, so at this point the pass + // is scheduled on the moduleOp. + auto module = this->getOperation(); + auto *context = &getContext(); + mlir::RewritePatternSet patterns(context); + patterns.insert(context); + mlir::ConversionTarget target(*context); + target.markUnknownOpDynamicallyLegal([](mlir::Operation *op) { + return llvm::all_of( + op->getResultTypes(), + [](mlir::Type ty) { return !ty.isa(); }) && + llvm::all_of(op->getOperandTypes(), [](mlir::Type ty) { + return !ty.isa(); + }); + }); + if (mlir::failed( + mlir::applyFullConversion(module, target, std::move(patterns)))) { + mlir::emitError(mlir::UnknownLoc::get(context), + "failure in HLFIR bufferization pass"); + signalPassFailure(); + } + } +}; +} // namespace + +std::unique_ptr hlfir::createBufferizeHLFIRPass() { + return std::make_unique(); +} diff --git a/flang/lib/Optimizer/HLFIR/Transforms/CMakeLists.txt b/flang/lib/Optimizer/HLFIR/Transforms/CMakeLists.txt --- a/flang/lib/Optimizer/HLFIR/Transforms/CMakeLists.txt +++ b/flang/lib/Optimizer/HLFIR/Transforms/CMakeLists.txt @@ -1,6 +1,7 @@ get_property(dialect_libs GLOBAL PROPERTY MLIR_DIALECT_LIBS) add_flang_library(HLFIRTransforms + BufferizeHLFIR.cpp ConvertToFIR.cpp DEPENDS diff --git a/flang/test/Driver/pass-plugin-not-found.f90 b/flang/test/Driver/pass-plugin-not-found.f90 --- a/flang/test/Driver/pass-plugin-not-found.f90 +++ b/flang/test/Driver/pass-plugin-not-found.f90 @@ -5,4 +5,5 @@ ! RUN: not %flang -fpass-plugin=X.Y %s 2>&1 | FileCheck %s --check-prefix=ERROR ! RUN: not %flang_fc1 -emit-llvm -o /dev/null -fpass-plugin=X.Y %s 2>&1 | FileCheck %s --check-prefix=ERROR -! ERROR: error: unable to load plugin 'X.Y': 'Could not load library 'X.Y': X.Y: cannot open shared object file: No such file or directory' +! The exact wording of the error message depends on the system dlerror. +! ERROR: error: unable to load plugin 'X.Y': 'Could not load library 'X.Y': {{.*}}: No such file or directory' diff --git a/flang/test/Fir/convert-to-llvm.fir b/flang/test/Fir/convert-to-llvm.fir --- a/flang/test/Fir/convert-to-llvm.fir +++ b/flang/test/Fir/convert-to-llvm.fir @@ -1514,11 +1514,11 @@ // CHECK-SAME: %[[ARG0:.*]]: !llvm.ptr> // CHECK: %[[C1:.*]] = llvm.mlir.constant(1 : i32) : i32 // CHECK: %[[ALLOCA:.*]] = llvm.alloca %[[C1]] x !llvm.struct<(ptr>, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}})> {alignment = 8 : i64} : (i32) -> !llvm.ptr>, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}})>> -// CHECK: %[[DESC:.*]] = llvm.mlir.undef : !llvm.struct<(ptr>, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}})> // CHECK: %[[NULL:.*]] = llvm.mlir.null : !llvm.ptr // CHECK: %[[GEP:.*]] = llvm.getelementptr %[[NULL]][1] // CHECK: %[[I64_ELEM_SIZE:.*]] = llvm.ptrtoint %[[GEP]] : !llvm.ptr to i64 // CHECK: %[[TYPE_CODE:.*]] = llvm.mlir.constant(9 : i32) : i32 +// CHECK: %[[DESC:.*]] = llvm.mlir.undef : !llvm.struct<(ptr>, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}})> // CHECK: %[[DESC0:.*]] = llvm.insertvalue %[[I64_ELEM_SIZE]], %[[DESC]][1] : !llvm.struct<(ptr>, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}})> // CHECK: %[[CFI_VERSION:.*]] = llvm.mlir.constant(20180515 : i32) : i32 // CHECK: %[[DESC1:.*]] = llvm.insertvalue %[[CFI_VERSION]], %[[DESC0]][2] : !llvm.struct<(ptr>, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}})> @@ -1737,11 +1737,11 @@ // CHECK: %[[ALLOCA_SIZE:.*]] = llvm.mlir.constant(1 : i32) : i32 // CHECK: %[[ALLOCA:.*]] = llvm.alloca %[[ALLOCA_SIZE]] x !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<1 x array<3 x i64>>)> {alignment = 8 : i64} : (i32) -> !llvm.ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<1 x array<3 x i64>>)>> // CHECK: %[[C0:.*]] = llvm.mlir.constant(0 : i64) : i64 -// CHECK: %[[BOX0:.*]] = llvm.mlir.undef : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<1 x array<3 x i64>>)> // CHECK: %[[NULL:.*]] = llvm.mlir.null : !llvm.ptr // CHECK: %[[GEP:.*]] = llvm.getelementptr %[[NULL]][1] // CHECK: %[[ELEM_LEN_I64:.*]] = llvm.ptrtoint %[[GEP]] : !llvm.ptr to i64 // CHECK: %[[TYPE:.*]] = llvm.mlir.constant(9 : i32) : i32 +// CHECK: %[[BOX0:.*]] = llvm.mlir.undef : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<1 x array<3 x i64>>)> // CHECK: %[[BOX1:.*]] = llvm.insertvalue %[[ELEM_LEN_I64]], %[[BOX0]][1] : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<1 x array<3 x i64>>)> // CHECK: %[[VERSION:.*]] = llvm.mlir.constant(20180515 : i32) : i32 // CHECK: %[[BOX2:.*]] = llvm.insertvalue %[[VERSION]], %[[BOX1]][2] : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<1 x array<3 x i64>>)> @@ -1836,11 +1836,11 @@ // CHECK: %[[ARR_SIZE_TMP1:.*]] = llvm.mul %[[C1_0]], %[[N1]] : i64 // CHECK: %[[ARR_SIZE:.*]] = llvm.mul %[[ARR_SIZE_TMP1]], %[[N2]] : i64 // CHECK: %[[ARR:.*]] = llvm.alloca %[[ARR_SIZE]] x f64 {bindc_name = "arr", in_type = !fir.array, operand_segment_sizes = array, uniq_name = "_QFsbEarr"} : (i64) -> !llvm.ptr -// CHECK: %[[BOX0:.*]] = llvm.mlir.undef : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<2 x array<3 x i64>>)> // CHECK: %[[NULL:.*]] = llvm.mlir.null : !llvm.ptr // CHECK: %[[GEP:.*]] = llvm.getelementptr %[[NULL]][1] // CHECK: %[[ELEM_LEN_I64:.*]] = llvm.ptrtoint %[[GEP]] : !llvm.ptr to i64 // CHECK: %[[TYPE_CODE:.*]] = llvm.mlir.constant(28 : i32) : i32 +// CHECK: %[[BOX0:.*]] = llvm.mlir.undef : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<2 x array<3 x i64>>)> // CHECK: %[[BOX1:.*]] = llvm.insertvalue %[[ELEM_LEN_I64]], %[[BOX0]][1] : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<2 x array<3 x i64>>)> // CHECK: %[[VERSION:.*]] = llvm.mlir.constant(20180515 : i32) : i32 // CHECK: %[[BOX2:.*]] = llvm.insertvalue %[[VERSION]], %[[BOX1]][2] : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<2 x array<3 x i64>>)> @@ -1915,11 +1915,11 @@ // CHECK: %[[V:.*]] = llvm.alloca %[[ALLOCA_SIZE_V]] x i32 {bindc_name = "v", in_type = i32, operand_segment_sizes = array, uniq_name = "_QFtest_dt_sliceEv"} : (i64) -> !llvm.ptr // CHECK: %[[ALLOCA_SIZE_X:.*]] = llvm.mlir.constant(1 : i64) : i64 // CHECK: %[[X:.*]] = llvm.alloca %[[ALLOCA_SIZE_X]] x !llvm.array<20 x struct<"_QFtest_dt_sliceTt", (i32, i32)>> {bindc_name = "x", in_type = !fir.array<20x!fir.type<_QFtest_dt_sliceTt{i:i32,j:i32}>>, operand_segment_sizes = array, uniq_name = "_QFtest_dt_sliceEx"} : (i64) -> !llvm.ptr>> -// CHECK: %[[BOX0:.*]] = llvm.mlir.undef : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<1 x array<3 x i64>>)> // CHECK: %[[NULL:.*]] = llvm.mlir.null : !llvm.ptr // CHECK: %[[GEP:.*]] = llvm.getelementptr %[[NULL]][1] // CHECK: %[[ELEM_LEN_I64:.*]] = llvm.ptrtoint %[[GEP]] : !llvm.ptr to i64 // CHECK: %[[TYPE_CODE:.*]] = llvm.mlir.constant(9 : i32) : i32 +// CHECK: %[[BOX0:.*]] = llvm.mlir.undef : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<1 x array<3 x i64>>)> // CHECK: %[[BOX1:.*]] = llvm.insertvalue %[[ELEM_LEN_I64]], %[[BOX0]][1] : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<1 x array<3 x i64>>)> // CHECK: %[[VERSION:.*]] = llvm.mlir.constant(20180515 : i32) : i32 // CHECK: %[[BOX2:.*]] = llvm.insertvalue %[[VERSION]], %[[BOX1]][2] : !llvm.struct<(ptr, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, i{{.*}}, array<1 x array<3 x i64>>)> @@ -2192,11 +2192,11 @@ //CHECK: %[[FIVE:.*]] = llvm.mlir.constant(5 : index) : i64 //CHECK: %[[SIX:.*]] = llvm.mlir.constant(6 : index) : i64 //CHECK: %[[EIGHTY:.*]] = llvm.mlir.constant(80 : index) : i64 -//CHECK: %[[RBOX:.*]] = llvm.mlir.undef : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> //CHECK: %[[NULL:.*]] = llvm.mlir.null : !llvm.ptr //CHECK: %[[GEP:.*]] = llvm.getelementptr %[[NULL]][1] //CHECK: %[[ELEM_SIZE_I64:.*]] = llvm.ptrtoint %[[GEP]] : !llvm.ptr to i64 //CHECK: %[[FLOAT_TYPE:.*]] = llvm.mlir.constant(27 : i32) : i32 +//CHECK: %[[RBOX:.*]] = llvm.mlir.undef : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> //CHECK: %[[RBOX_TMP1:.*]] = llvm.insertvalue %[[ELEM_SIZE_I64]], %[[RBOX]][1] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> //CHECK: %[[CFI_VERSION:.*]] = llvm.mlir.constant(20180515 : i32) : i32 //CHECK: %[[RBOX_TMP2:.*]] = llvm.insertvalue %[[CFI_VERSION]], %[[RBOX_TMP1]][2] : !llvm.struct<(ptr, i64, i32, i8, i8, i8, i8, array<1 x array<3 x i64>>)> diff --git a/flang/test/Fir/polymorphic.fir b/flang/test/Fir/polymorphic.fir --- a/flang/test/Fir/polymorphic.fir +++ b/flang/test/Fir/polymorphic.fir @@ -11,10 +11,81 @@ } // CHECK-LABEL: define void @_QMpolymorphic_testPtest_allocate_unlimited_polymorphic_non_derived() { -// CHECK: %[[MEM:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8 } -// CHECK: %[[DESC:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8 }, i64 1 -// CHECK: store { ptr, i64, i32, i8, i8, i8, i8 } { ptr null, i64 0, i32 20180515, i8 0, i8 -1, i8 1, i8 0 }, ptr %[[MEM]] -// CHECK: %[[LOADED:.*]] = load { ptr, i64, i32, i8, i8, i8, i8 }, ptr %[[MEM]], align 8 -// CHECK: store { ptr, i64, i32, i8, i8, i8, i8 } %[[LOADED]], ptr %[[DESC]] +// CHECK: %[[MEM:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } +// CHECK: %[[DESC:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, i64 1 +// CHECK: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } { ptr null, i64 0, i32 20180515, i8 0, i8 -1, i8 1, i8 1, ptr null, [1 x i64] undef }, ptr %[[MEM]] +// CHECK: %[[LOADED:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] }, ptr %[[MEM]], align 8 +// CHECK: store { ptr, i64, i32, i8, i8, i8, i8, ptr, [1 x i64] } %[[LOADED]], ptr %[[DESC]] // CHECK: ret void // CHECK: } + + +// Test rebox of unlimited polymoprhic descriptor + +func.func @_QMpolymorphic_testPtest_rebox() { + %0 = fir.address_of(@_QFEx) : !fir.ref>>> + %c-1_i32 = arith.constant -1 : i32 + %9 = fir.address_of(@_QQcl.2E2F64756D6D792E66393000) : !fir.ref> + %10 = fir.convert %9 : (!fir.ref>) -> !fir.ref + %c8_i32 = arith.constant 8 : i32 + %11 = fir.call @_FortranAioBeginExternalListOutput(%c-1_i32, %10, %c8_i32) fastmath : (i32, !fir.ref, i32) -> !fir.ref + %12 = fir.load %0 : !fir.ref>>> + %c0_1 = arith.constant 0 : index + %13:3 = fir.box_dims %12, %c0_1 : (!fir.class>>, index) -> (index, index, index) + %14 = fir.shift %13#0 : (index) -> !fir.shift<1> + %15 = fir.rebox %12(%14) : (!fir.class>>, !fir.shift<1>) -> !fir.class> + %16 = fir.convert %15 : (!fir.class>) -> !fir.box + %17 = fir.call @_FortranAioOutputDescriptor(%11, %16) fastmath : (!fir.ref, !fir.box) -> i1 + %18 = fir.call @_FortranAioEndIoStatement(%11) fastmath : (!fir.ref) -> i32 + return +} + +// CHECK-LABEL: @_QMpolymorphic_testPtest_rebox +// CHECK: %[[ELE_SIZE_GEP:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] }, ptr %{{.*}}, i32 0, i32 1 +// CHECK: %[[ELE_SIZE:.*]] = load i64, ptr %[[ELE_SIZE_GEP]] +// CHECK: %[[TYPE_CODE_GEP:.*]] = getelementptr { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] }, ptr %{{.*}}, i32 0, i32 4 +// CHECK: %[[TYPE_CODE:.*]] = load i32, ptr %[[TYPE_CODE_GEP]] +// CHECK: %{{.*}} = insertvalue { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] } undef, i64 %[[ELE_SIZE]], 1 +// CHECK: %[[TYPE_CODE_I8:.*]] = trunc i32 %[[TYPE_CODE]] to i8 +// CHECK: %{{.*}} = insertvalue { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] } %{{.*}}, i8 %[[TYPE_CODE_I8]], 4 + +// Test emboxing to a unlimited polymorphic descriptor + +func.func @_QMpolymorphic_testPtest_embox() { + %0 = fir.address_of(@_QFEx) : !fir.ref>>> + %1 = fir.address_of(@_QFEy) : !fir.ref> + %c1 = arith.constant 1 : index + %2 = fir.alloca i32 {bindc_name = "z", uniq_name = "_QFEz"} + %3 = fir.shape %c1 : (index) -> !fir.shape<1> + %4 = fir.embox %1(%3) : (!fir.ref>, !fir.shape<1>) -> !fir.class>> + fir.store %4 to %0 : !fir.ref>>> + return +} + +// CHECK-LABEL: @_QMpolymorphic_testPtest_embox() +// CHECK: %[[ALLOCA_DESC:.*]] = alloca { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] } +// CHECK: store { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] } { ptr @_QFEy, i64 ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64), i32 20180515, i8 1, i8 9, {{.*}}, ptr %[[ALLOCA_DESC]] +// CHECK: %[[LOADED_DESC:.*]] = load { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] }, ptr %[[ALLOCA_DESC]], align 8 +// CHECK: store { ptr, i64, i32, i8, i8, i8, i8, [1 x [3 x i64]], ptr, [1 x i64] } %[[LOADED_DESC]], ptr @_QFEx, align 8 + + +fir.global internal @_QFEx : !fir.class>> { + %0 = fir.zero_bits !fir.ptr> + %c0 = arith.constant 0 : index + %1 = fir.shape %c0 : (index) -> !fir.shape<1> + %2 = fir.embox %0(%1) : (!fir.ptr>, !fir.shape<1>) -> !fir.class>> + fir.has_value %2 : !fir.class>> +} + +fir.global internal @_QFEy target : !fir.array<1xi32> { + %0 = fir.undefined !fir.array<1xi32> + fir.has_value %0 : !fir.array<1xi32> +} + +func.func private @_FortranAioBeginExternalListOutput(i32, !fir.ref, i32) -> !fir.ref attributes {fir.io, fir.runtime} +func.func private @_FortranAioOutputDescriptor(!fir.ref, !fir.box) -> i1 attributes {fir.io, fir.runtime} +func.func private @_FortranAioEndIoStatement(!fir.ref) -> i32 attributes {fir.io, fir.runtime} +fir.global linkonce @_QQcl.2E2F64756D6D792E66393000 constant : !fir.char<1,12> { + %0 = fir.string_lit "./dummy.f90\00"(12) : !fir.char<1,12> + fir.has_value %0 : !fir.char<1,12> +} diff --git a/flang/test/HLFIR/concat-bufferization.fir b/flang/test/HLFIR/concat-bufferization.fir new file mode 100644 --- /dev/null +++ b/flang/test/HLFIR/concat-bufferization.fir @@ -0,0 +1,127 @@ +// Test hlfir.concat operation lowering to operations operating on memory. + +// RUN: fir-opt %s -bufferize-hlfir | FileCheck %s + + +func.func @concat(%arg0: !fir.boxchar<1>, %arg1: !fir.boxchar<1>, %arg2: !fir.boxchar<1>) { + %0:2 = fir.unboxchar %arg0 : (!fir.boxchar<1>) -> (!fir.ref>, index) + %1:2 = hlfir.declare %0#0 typeparams %0#1 {uniq_name = "c1"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) + %2:2 = fir.unboxchar %arg1 : (!fir.boxchar<1>) -> (!fir.ref>, index) + %3:2 = hlfir.declare %2#0 typeparams %2#1 {uniq_name = "c2"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) + %4:2 = fir.unboxchar %arg2 : (!fir.boxchar<1>) -> (!fir.ref>, index) + %5:2 = hlfir.declare %4#0 typeparams %4#1 {uniq_name = "c3"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) + %6 = arith.addi %2#1, %4#1 : index + %7 = hlfir.concat %3#0, %5#0 len %6 : (!fir.boxchar<1>, !fir.boxchar<1>, index) -> !hlfir.expr> + hlfir.assign %7 to %1#0 : !hlfir.expr>, !fir.boxchar<1> + return +} +// CHECK-LABEL: func.func @concat( +// CHECK-SAME: %[[VAL_0:[^:]*]]: !fir.boxchar<1>, +// CHECK-SAME: %[[VAL_1:[^:]*]]: !fir.boxchar<1>, +// CHECK-SAME: %[[VAL_2:[^:]*]]: !fir.boxchar<1>) { +// CHECK: %[[VAL_3:.*]]:2 = fir.unboxchar %[[VAL_0]] : (!fir.boxchar<1>) -> (!fir.ref>, index) +// CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]]#0 typeparams %[[VAL_3]]#1 {uniq_name = "c1"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +// CHECK: %[[VAL_5:.*]]:2 = fir.unboxchar %[[VAL_1]] : (!fir.boxchar<1>) -> (!fir.ref>, index) +// CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_5]]#0 typeparams %[[VAL_5]]#1 {uniq_name = "c2"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +// CHECK: %[[VAL_7:.*]]:2 = fir.unboxchar %[[VAL_2]] : (!fir.boxchar<1>) -> (!fir.ref>, index) +// CHECK: %[[VAL_8:.*]]:2 = hlfir.declare %[[VAL_7]]#0 typeparams %[[VAL_7]]#1 {uniq_name = "c3"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +// CHECK: %[[VAL_9:.*]] = arith.addi %[[VAL_5]]#1, %[[VAL_7]]#1 : index +// CHECK: %[[VAL_10:.*]] = arith.addi %[[VAL_5]]#1, %[[VAL_7]]#1 : index +// CHECK: %[[VAL_11:.*]] = fir.alloca !fir.char<1,?>(%[[VAL_10]] : index) {bindc_name = ".chrtmp"} +// CHECK: %[[VAL_12:.*]] = arith.constant 1 : i64 +// CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_5]]#1 : (index) -> i64 +// CHECK: %[[VAL_14:.*]] = arith.muli %[[VAL_12]], %[[VAL_13]] : i64 +// CHECK: %[[VAL_15:.*]] = arith.constant false +// CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_11]] : (!fir.ref>) -> !fir.ref +// CHECK: %[[VAL_17:.*]] = fir.convert %[[VAL_6]]#1 : (!fir.ref>) -> !fir.ref +// CHECK: fir.call @llvm.memmove.p0.p0.i64(%[[VAL_16]], %[[VAL_17]], %[[VAL_14]], %[[VAL_15]]) : (!fir.ref, !fir.ref, i64, i1) -> () +// CHECK: %[[VAL_18:.*]] = arith.constant 1 : index +// CHECK: %[[VAL_19:.*]] = arith.subi %[[VAL_10]], %[[VAL_18]] : index +// CHECK: fir.do_loop %[[VAL_20:.*]] = %[[VAL_5]]#1 to %[[VAL_19]] step %[[VAL_18]] { +// CHECK: %[[VAL_21:.*]] = arith.subi %[[VAL_20]], %[[VAL_5]]#1 : index +// CHECK: %[[VAL_22:.*]] = fir.convert %[[VAL_8]]#1 : (!fir.ref>) -> !fir.ref>> +// CHECK: %[[VAL_23:.*]] = fir.coordinate_of %[[VAL_22]], %[[VAL_21]] : (!fir.ref>>, index) -> !fir.ref> +// CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_23]] : !fir.ref> +// CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_11]] : (!fir.ref>) -> !fir.ref>> +// CHECK: %[[VAL_26:.*]] = fir.coordinate_of %[[VAL_25]], %[[VAL_20]] : (!fir.ref>>, index) -> !fir.ref> +// CHECK: fir.store %[[VAL_24]] to %[[VAL_26]] : !fir.ref> +// CHECK: } +// CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_11]] typeparams %[[VAL_10]] {uniq_name = "tmp"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +// CHECK: hlfir.assign %[[VAL_27]]#0 to %[[VAL_4]]#0 : !fir.boxchar<1>, !fir.boxchar<1> + + +func.func @concat_chained(%arg0: !fir.boxchar<1>, %arg1: !fir.boxchar<1>, %arg2: !fir.boxchar<1>, %arg3: !fir.boxchar<1>) { + %0:2 = fir.unboxchar %arg0 : (!fir.boxchar<1>) -> (!fir.ref>, index) + %1:2 = hlfir.declare %0#0 typeparams %0#1 {uniq_name = "c1"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) + %2:2 = fir.unboxchar %arg1 : (!fir.boxchar<1>) -> (!fir.ref>, index) + %3:2 = hlfir.declare %2#0 typeparams %2#1 {uniq_name = "c2"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) + %4:2 = fir.unboxchar %arg2 : (!fir.boxchar<1>) -> (!fir.ref>, index) + %5:2 = hlfir.declare %4#0 typeparams %4#1 {uniq_name = "c3"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) + %6:2 = fir.unboxchar %arg3 : (!fir.boxchar<1>) -> (!fir.ref>, index) + %7:2 = hlfir.declare %6#0 typeparams %6#1 {uniq_name = "c4"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) + %8 = arith.addi %2#1, %4#1 : index + %9 = hlfir.concat %3#0, %5#0 len %8 : (!fir.boxchar<1>, !fir.boxchar<1>, index) -> !hlfir.expr> + %10 = arith.addi %8, %6#1 : index + %11 = hlfir.concat %9, %7#0 len %10 : (!hlfir.expr>, !fir.boxchar<1>, index) -> !hlfir.expr> + hlfir.assign %11 to %1#0 : !hlfir.expr>, !fir.boxchar<1> + return +} +// CHECK-LABEL: func.func @concat_chained( +// CHECK-SAME: %[[VAL_0:[^:]*]]: !fir.boxchar<1>, +// CHECK-SAME: %[[VAL_1:[^:]*]]: !fir.boxchar<1>, +// CHECK-SAME: %[[VAL_2:[^:]*]]: !fir.boxchar<1>, +// CHECK-SAME: %[[VAL_3:[^:]*]]: !fir.boxchar<1>) { +// CHECK: %[[VAL_4:.*]]:2 = fir.unboxchar %[[VAL_0]] : (!fir.boxchar<1>) -> (!fir.ref>, index) +// CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_4]]#0 typeparams %[[VAL_4]]#1 {uniq_name = "c1"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +// CHECK: %[[VAL_6:.*]]:2 = fir.unboxchar %[[VAL_1]] : (!fir.boxchar<1>) -> (!fir.ref>, index) +// CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]]#0 typeparams %[[VAL_6]]#1 {uniq_name = "c2"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +// CHECK: %[[VAL_8:.*]]:2 = fir.unboxchar %[[VAL_2]] : (!fir.boxchar<1>) -> (!fir.ref>, index) +// CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_8]]#0 typeparams %[[VAL_8]]#1 {uniq_name = "c3"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +// CHECK: %[[VAL_10:.*]]:2 = fir.unboxchar %[[VAL_3]] : (!fir.boxchar<1>) -> (!fir.ref>, index) +// CHECK: %[[VAL_11:.*]]:2 = hlfir.declare %[[VAL_10]]#0 typeparams %[[VAL_10]]#1 {uniq_name = "c4"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +// CHECK: %[[VAL_12:.*]] = arith.addi %[[VAL_6]]#1, %[[VAL_8]]#1 : index +// CHECK: %[[VAL_13:.*]] = arith.addi %[[VAL_6]]#1, %[[VAL_8]]#1 : index +// CHECK: %[[VAL_14:.*]] = fir.alloca !fir.char<1,?>(%[[VAL_13]] : index) {bindc_name = ".chrtmp"} +// CHECK: %[[VAL_15:.*]] = arith.constant 1 : i64 +// CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_6]]#1 : (index) -> i64 +// CHECK: %[[VAL_17:.*]] = arith.muli %[[VAL_15]], %[[VAL_16]] : i64 +// CHECK: %[[VAL_18:.*]] = arith.constant false +// CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_14]] : (!fir.ref>) -> !fir.ref +// CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_7]]#1 : (!fir.ref>) -> !fir.ref +// CHECK: fir.call @llvm.memmove.p0.p0.i64(%[[VAL_19]], %[[VAL_20]], %[[VAL_17]], %[[VAL_18]]) : (!fir.ref, !fir.ref, i64, i1) -> () +// CHECK: %[[VAL_21:.*]] = arith.constant 1 : index +// CHECK: %[[VAL_22:.*]] = arith.subi %[[VAL_13]], %[[VAL_21]] : index +// CHECK: fir.do_loop %[[VAL_23:.*]] = %[[VAL_6]]#1 to %[[VAL_22]] step %[[VAL_21]] { +// CHECK: %[[VAL_24:.*]] = arith.subi %[[VAL_23]], %[[VAL_6]]#1 : index +// CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_9]]#1 : (!fir.ref>) -> !fir.ref>> +// CHECK: %[[VAL_26:.*]] = fir.coordinate_of %[[VAL_25]], %[[VAL_24]] : (!fir.ref>>, index) -> !fir.ref> +// CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_26]] : !fir.ref> +// CHECK: %[[VAL_28:.*]] = fir.convert %[[VAL_14]] : (!fir.ref>) -> !fir.ref>> +// CHECK: %[[VAL_29:.*]] = fir.coordinate_of %[[VAL_28]], %[[VAL_23]] : (!fir.ref>>, index) -> !fir.ref> +// CHECK: fir.store %[[VAL_27]] to %[[VAL_29]] : !fir.ref> +// CHECK: } +// CHECK: %[[VAL_30:.*]]:2 = hlfir.declare %[[VAL_14]] typeparams %[[VAL_13]] {uniq_name = "tmp"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +// CHECK: %[[VAL_31:.*]] = arith.addi %[[VAL_12]], %[[VAL_10]]#1 : index +// CHECK: %[[VAL_32:.*]] = arith.addi %[[VAL_13]], %[[VAL_10]]#1 : index +// CHECK: %[[VAL_33:.*]] = fir.alloca !fir.char<1,?>(%[[VAL_32]] : index) {bindc_name = ".chrtmp"} +// CHECK: %[[VAL_34:.*]] = arith.constant 1 : i64 +// CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_13]] : (index) -> i64 +// CHECK: %[[VAL_36:.*]] = arith.muli %[[VAL_34]], %[[VAL_35]] : i64 +// CHECK: %[[VAL_37:.*]] = arith.constant false +// CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_33]] : (!fir.ref>) -> !fir.ref +// CHECK: %[[VAL_39:.*]] = fir.convert %[[VAL_30]]#1 : (!fir.ref>) -> !fir.ref +// CHECK: fir.call @llvm.memmove.p0.p0.i64(%[[VAL_38]], %[[VAL_39]], %[[VAL_36]], %[[VAL_37]]) : (!fir.ref, !fir.ref, i64, i1) -> () +// CHECK: %[[VAL_40:.*]] = arith.constant 1 : index +// CHECK: %[[VAL_41:.*]] = arith.subi %[[VAL_32]], %[[VAL_40]] : index +// CHECK: fir.do_loop %[[VAL_42:.*]] = %[[VAL_13]] to %[[VAL_41]] step %[[VAL_40]] { +// CHECK: %[[VAL_43:.*]] = arith.subi %[[VAL_42]], %[[VAL_13]] : index +// CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_11]]#1 : (!fir.ref>) -> !fir.ref>> +// CHECK: %[[VAL_45:.*]] = fir.coordinate_of %[[VAL_44]], %[[VAL_43]] : (!fir.ref>>, index) -> !fir.ref> +// CHECK: %[[VAL_46:.*]] = fir.load %[[VAL_45]] : !fir.ref> +// CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_33]] : (!fir.ref>) -> !fir.ref>> +// CHECK: %[[VAL_48:.*]] = fir.coordinate_of %[[VAL_47]], %[[VAL_42]] : (!fir.ref>>, index) -> !fir.ref> +// CHECK: fir.store %[[VAL_46]] to %[[VAL_48]] : !fir.ref> +// CHECK: } +// CHECK: %[[VAL_49:.*]]:2 = hlfir.declare %[[VAL_33]] typeparams %[[VAL_32]] {uniq_name = "tmp"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) +// CHECK: hlfir.assign %[[VAL_49]]#0 to %[[VAL_5]]#0 : !fir.boxchar<1>, !fir.boxchar<1> + diff --git a/flang/test/HLFIR/concat.fir b/flang/test/HLFIR/concat.fir new file mode 100644 --- /dev/null +++ b/flang/test/HLFIR/concat.fir @@ -0,0 +1,62 @@ +// Test hlfir.concat operation parse, verify (no errors), and unparse. + +// RUN: fir-opt %s | fir-opt | FileCheck %s + +func.func @concat_var(%arg0: !fir.ref>, %arg1: !fir.ref>) { + %c30 = arith.constant 30 : index + %0 = hlfir.concat %arg0, %arg1 len %c30 : (!fir.ref>, !fir.ref>, index) -> (!hlfir.expr>) + return +} +// CHECK-LABEL: func.func @concat_var( +// CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>, +// CHECK-SAME: %[[VAL_1:.*]]: !fir.ref>) { +// CHECK: %[[VAL_2:.*]] = arith.constant 30 : index +// CHECK: %[[VAL_3:.*]] = hlfir.concat %[[VAL_0]], %[[VAL_1]] len %[[VAL_2]] : (!fir.ref>, !fir.ref>, index) -> !hlfir.expr> + + +func.func @concat_boxchar(%arg0: !fir.boxchar<1>, %arg1: !fir.boxchar<1>) { + %c30 = arith.constant 30 : index + %0 = hlfir.concat %arg0, %arg1 len %c30 : (!fir.boxchar<1>, !fir.boxchar<1>, index) -> (!hlfir.expr>) + return +} +// CHECK-LABEL: func.func @concat_boxchar( +// CHECK-SAME: %[[VAL_0:.*]]: !fir.boxchar<1>, +// CHECK-SAME: %[[VAL_1:.*]]: !fir.boxchar<1>) { +// CHECK: %[[VAL_2:.*]] = arith.constant 30 : index +// CHECK: %[[VAL_3:.*]] = hlfir.concat %[[VAL_0]], %[[VAL_1]] len %[[VAL_2]] : (!fir.boxchar<1>, !fir.boxchar<1>, index) -> !hlfir.expr> + + +func.func @concat_boxchar_kind2(%arg0: !fir.boxchar<2>, %arg1: !fir.boxchar<2>) { + %c30 = arith.constant 30 : index + %0 = hlfir.concat %arg0, %arg1 len %c30 : (!fir.boxchar<2>, !fir.boxchar<2>, index) -> (!hlfir.expr>) + return +} +// CHECK-LABEL: func.func @concat_boxchar_kind2( +// CHECK-SAME: %[[VAL_0:.*]]: !fir.boxchar<2>, +// CHECK-SAME: %[[VAL_1:.*]]: !fir.boxchar<2>) { +// CHECK: %[[VAL_2:.*]] = arith.constant 30 : index +// CHECK: %[[VAL_3:.*]] = hlfir.concat %[[VAL_0]], %[[VAL_1]] len %[[VAL_2]] : (!fir.boxchar<2>, !fir.boxchar<2>, index) -> !hlfir.expr> + + +func.func @concat_expr(%arg0: !hlfir.expr>, %arg1: !hlfir.expr>) { + %c30 = arith.constant 30 : index + %0 = hlfir.concat %arg0, %arg1 len %c30 : (!hlfir.expr>, !hlfir.expr>, index) -> (!hlfir.expr>) + return +} +// CHECK-LABEL: func.func @concat_expr( +// CHECK-SAME: %[[VAL_0:.*]]: !hlfir.expr>, +// CHECK-SAME: %[[VAL_1:.*]]: !hlfir.expr>) { +// CHECK: %[[VAL_2:.*]] = arith.constant 30 : index +// CHECK: %[[VAL_3:.*]] = hlfir.concat %[[VAL_0]], %[[VAL_1]] len %[[VAL_2]] : (!hlfir.expr>, !hlfir.expr>, index) -> !hlfir.expr> + + +func.func @concat_several_args(%arg0: !fir.boxchar<1>, %arg1: !fir.boxchar<1>) { + %c30 = arith.constant 30 : index + %0 = hlfir.concat %arg0, %arg1, %arg1 len %c30 : (!fir.boxchar<1>, !fir.boxchar<1>, !fir.boxchar<1>, index) -> (!hlfir.expr>) + return +} +// CHECK-LABEL: func.func @concat_several_args( +// CHECK-SAME: %[[VAL_0:.*]]: !fir.boxchar<1>, +// CHECK-SAME: %[[VAL_1:.*]]: !fir.boxchar<1>) { +// CHECK: %[[VAL_2:.*]] = arith.constant 30 : index +// CHECK: %[[VAL_3:.*]] = hlfir.concat %[[VAL_0]], %[[VAL_1]], %[[VAL_1]] len %[[VAL_2]] : (!fir.boxchar<1>, !fir.boxchar<1>, !fir.boxchar<1>, index) -> !hlfir.expr> diff --git a/flang/test/HLFIR/invalid.fir b/flang/test/HLFIR/invalid.fir --- a/flang/test/HLFIR/invalid.fir +++ b/flang/test/HLFIR/invalid.fir @@ -255,3 +255,43 @@ %0 = hlfir.designate %arg0(%c1) typeparams %c1 : (!fir.box>, index, index) -> !fir.ref return } + +// ----- +func.func @bad_concat(%arg0: !fir.ref>, %arg1: !fir.ref>) { + %c30 = arith.constant 30 : index + // expected-error@+1 {{'hlfir.concat' op result #0 must be any character scalar expression type, but got '!fir.ref>'}} + %0 = hlfir.concat %arg0, %arg1 len %c30 : (!fir.ref>, !fir.ref>, index) -> (!fir.ref>) + return +} + +// ----- +func.func @bad_concat_2(%arg0: !fir.ref>>, %arg1: !fir.ref>>) { + %c30 = arith.constant 30 : index + // expected-error@+1 {{'hlfir.concat' op operand #0 must be any character scalar type, but got '!fir.ref>>'}} + %0 = hlfir.concat %arg0, %arg1 len %c30 : (!fir.ref>>, !fir.ref>>, index) -> (!hlfir.expr<100x!fir.char<1,30>>) + return +} + +// ----- +func.func @bad_concat_3(%arg0: !fir.ref>, %arg1: !fir.ref) { + %c30 = arith.constant 30 : index + // expected-error@+1 {{'hlfir.concat' op operand #1 must be any character scalar type, but got '!fir.ref'}} + %0 = hlfir.concat %arg0, %arg1 len %c30 : (!fir.ref>, !fir.ref, index) -> (!hlfir.expr>) + return +} + +// ----- +func.func @bad_concat_4(%arg0: !fir.ref>, %arg1: !fir.ref>) { + %c30 = arith.constant 30 : index + // expected-error@+1 {{'hlfir.concat' op strings must have the same KIND as the result type}} + %0 = hlfir.concat %arg0, %arg1 len %c30 : (!fir.ref>, !fir.ref>, index) -> (!hlfir.expr>) + return +} + +// ----- +func.func @bad_concat_4(%arg0: !fir.ref>) { + %c30 = arith.constant 30 : index + // expected-error@+1 {{'hlfir.concat' op must be provided at least two string operands}} + %0 = hlfir.concat %arg0 len %c30 : (!fir.ref>, index) -> (!hlfir.expr>) + return +} diff --git a/flang/test/Lower/HLFIR/concat.f90 b/flang/test/Lower/HLFIR/concat.f90 new file mode 100644 --- /dev/null +++ b/flang/test/Lower/HLFIR/concat.f90 @@ -0,0 +1,47 @@ +! Test lowering of character concatenation to HLFIR +! RUN: bbc -emit-fir -hlfir -o - %s 2>&1 | FileCheck %s + +subroutine concat(c1, c2, c3) + character(*) :: c1, c2, c3 + c1 = c2 // c3 +end subroutine +! CHECK-LABEL: func.func @_QPconcat +! CHECK: hlfir.declare {{.*}}c1 +! CHECK: %[[VAL_5:.*]]:2 = fir.unboxchar %{{.*}} : (!fir.boxchar<1>) -> (!fir.ref>, index) +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare {{.*}}c2 +! CHECK: %[[VAL_7:.*]]:2 = fir.unboxchar %{{.*}} : (!fir.boxchar<1>) -> (!fir.ref>, index) +! CHECK: %[[VAL_8:.*]]:2 = hlfir.declare {{.*}}c3 +! CHECK: %[[VAL_9:.*]] = arith.addi %[[VAL_5]]#1, %[[VAL_7]]#1 : index +! CHECK: %[[VAL_10:.*]] = hlfir.concat %[[VAL_6]]#0, %[[VAL_8]]#0 len %[[VAL_9]] : (!fir.boxchar<1>, !fir.boxchar<1>, index) -> !hlfir.expr> + +subroutine concat_2(c1, c2, c3) + character(*) :: c1(100) + character :: c2(100)*10, c3(100)*20 + c1(1) = c2(1) // c3(1) +end subroutine +! CHECK-LABEL: func.func @_QPconcat_2 +! CHECK: %[[VAL_9:.*]] = arith.constant 10 : index +! CHECK: %[[VAL_13:.*]]:2 = hlfir.declare %{{.*}}c2 +! CHECK: %[[VAL_15:.*]] = arith.constant 20 : index +! CHECK: %[[VAL_19:.*]]:2 = hlfir.declare {{.*}}c3 +! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_13]]#0 (%{{.*}}) typeparams %[[VAL_9]] : (!fir.ref>>, index, index) -> !fir.ref> +! CHECK: %[[VAL_23:.*]] = hlfir.designate %[[VAL_19]]#0 (%{{.*}}) typeparams %[[VAL_15]] : (!fir.ref>>, index, index) -> !fir.ref> +! CHECK: %[[VAL_24:.*]] = arith.addi %[[VAL_9]], %[[VAL_15]] : index +! CHECK: %[[VAL_25:.*]] = hlfir.concat %[[VAL_21]], %[[VAL_23]] len %[[VAL_24]] : (!fir.ref>, !fir.ref>, index) -> !hlfir.expr> + +subroutine concat3(c1, c2, c3, c4) + character(*) :: c1, c2, c3, c4 + c1 = c2 // c3 // c4 +end subroutine +! CHECK-LABEL: func.func @_QPconcat3 +! CHECK: hlfir.declare {{.*}}c1 +! CHECK: %[[VAL_5:.*]]:2 = fir.unboxchar %{{.*}} +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare {{.*}}c2 +! CHECK: %[[VAL_7:.*]]:2 = fir.unboxchar %{{.*}} +! CHECK: %[[VAL_8:.*]]:2 = hlfir.declare {{.*}}c3 +! CHECK: %[[VAL_9:.*]]:2 = fir.unboxchar %{{.*}} +! CHECK: %[[VAL_10:.*]]:2 = hlfir.declare {{.*}}c4 +! CHECK: %[[VAL_11:.*]] = arith.addi %[[VAL_5]]#1, %[[VAL_7]]#1 : index +! CHECK: %[[VAL_12:.*]] = hlfir.concat %[[VAL_6]]#0, %[[VAL_8]]#0 len %[[VAL_11]] : (!fir.boxchar<1>, !fir.boxchar<1>, index) -> !hlfir.expr> +! CHECK: %[[VAL_13:.*]] = arith.addi %[[VAL_11]], %[[VAL_9]]#1 : index +! CHECK: %[[VAL_14:.*]] = hlfir.concat %[[VAL_12]], %[[VAL_10]]#0 len %[[VAL_13]] : (!hlfir.expr>, !fir.boxchar<1>, index) -> !hlfir.expr> diff --git a/flang/test/Lower/Intrinsics/loc.f90 b/flang/test/Lower/Intrinsics/loc.f90 new file mode 100644 --- /dev/null +++ b/flang/test/Lower/Intrinsics/loc.f90 @@ -0,0 +1,250 @@ +! RUN: bbc -emit-fir %s -o - | FileCheck %s +! RUN: %flang_fc1 -emit-fir %s -o - | FileCheck %s + +! Test LOC intrinsic + +! CHECK-LABEL: func.func @_QPloc_scalar() { +subroutine loc_scalar() + integer(8) :: p + integer :: x + p = loc(x) +! CHECK: %[[p:.*]] = fir.alloca i64 {{.*}} +! CHECK: %[[x:.*]] = fir.alloca i32 {{.*}} +! CHECK: %[[xbox:.*]] = fir.embox %[[x]] : (!fir.ref) -> !fir.box +! CHECK: %[[xaddr:.*]] = fir.box_addr %[[xbox]] : (!fir.box) -> !fir.ref +! CHECK: %[[xaddrval:.*]] = fir.convert %[[xaddr]] : (!fir.ref) -> i64 +! CHECK: fir.store %[[xaddrval]] to %[[p]] : !fir.ref +end + +! CHECK-LABEL: func.func @_QPloc_char() { +subroutine loc_char() + integer(8) :: p + character(5) :: x = "abcde" + p = loc(x) +! CHECK: %[[p:.*]] = fir.alloca i64 {{.*}} +! CHECK: %[[x:.*]] = fir.address_of(@_QFloc_charEx) : !fir.ref> +! CHECK: %[[xbox:.*]] = fir.embox %[[x]] : (!fir.ref>) -> !fir.box> +! CHECK: %[[xaddr:.*]] = fir.box_addr %[[xbox]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[xaddrval:.*]] = fir.convert %[[xaddr]] : (!fir.ref>) -> i64 +! CHECK: fir.store %[[xaddrval]] to %[[p]] : !fir.ref +end + +! CHECK-LABEL: func.func @_QPloc_substring() { +subroutine loc_substring() + integer(8) :: p + character(5) :: x = "abcde" + p = loc(x(2:)) +! CHECK: %[[p:.*]] = fir.alloca i64 {{.*}} +! CHECK: %[[x:.*]] = fir.address_of(@_QFloc_substringEx) : !fir.ref> +! CHECK: %[[sslb:.*]] = arith.constant 2 : i64 +! CHECK: %[[ssub:.*]] = arith.constant 5 : i64 +! CHECK: %[[sslbidx:.*]] = fir.convert %[[sslb]] : (i64) -> index +! CHECK: %[[ssubidx:.*]] = fir.convert %[[ssub]] : (i64) -> index +! CHECK: %[[one:.*]] = arith.constant 1 : index +! CHECK: %[[lboffset:.*]] = arith.subi %[[sslbidx]], %c1 : index +! CHECK: %[[xarr:.*]] = fir.convert %[[x]] : (!fir.ref>) -> !fir.ref>> +! CHECK: %[[xarrcoord:.*]] = fir.coordinate_of %[[xarr]], %[[lboffset]] : (!fir.ref>>, index) -> !fir.ref> +! CHECK: %[[xss:.*]] = fir.convert %[[xarrcoord]] : (!fir.ref>) -> !fir.ref> +! CHECK: %[[rng:.*]] = arith.subi %[[ssubidx]], %[[sslbidx]] : index +! CHECK: %[[rngp1:.*]] = arith.addi %[[rng]], %[[one]] : index +! CHECK: %[[zero:.*]] = arith.constant 0 : index +! CHECK: %[[cmpval:.*]] = arith.cmpi slt, %[[rngp1]], %[[zero]] : index +! CHECK: %[[sltval:.*]] = arith.select %[[cmpval]], %[[zero]], %[[rngp1]] : index +! CHECK: %[[xssbox:.*]] = fir.embox %[[xss]] typeparams %[[sltval]] : (!fir.ref>, index) -> !fir.box> +! CHECK: %[[xssaddr:.*]] = fir.box_addr %[[xssbox]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[xssaddrval:.*]] = fir.convert %[[xssaddr]] : (!fir.ref>) -> i64 +! CHECK: fir.store %[[xssaddrval]] to %[[p]] : !fir.ref +end + +! CHECK-LABEL: func.func @_QPloc_array() { +subroutine loc_array + integer(8) :: p + integer :: x(10) + p = loc(x) +! CHECK: %[[p:.*]] = fir.alloca i64 {{.*}} +! CHECK: %[[ten:.*]] = arith.constant 10 : index +! CHECK: %[[x:.*]] = fir.alloca !fir.array<10xi32> {{.*}} +! CHECK: %[[xshp:.*]] = fir.shape %[[ten]] : (index) -> !fir.shape<1> +! CHECK: %[[xbox:.*]] = fir.embox %[[x]](%[[xshp]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box> +! CHECK: %[[xaddr:.*]] = fir.box_addr %[[xbox]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[xaddrval:.*]] = fir.convert %[[xaddr]] : (!fir.ref>) -> i64 +! CHECK: fir.store %[[xaddrval]] to %[[p]] : !fir.ref +end + +! CHECK-LABEL: func.func @_QPloc_chararray() { +subroutine loc_chararray() + integer(8) :: p + character(5) :: x(2) + p = loc(x) +! CHECK: %[[p:.*]] = fir.alloca i64 {{.*}} +! CHECK: %[[two:.*]] = arith.constant 2 : index +! CHECK: %[[x:.*]] = fir.alloca !fir.array<2x!fir.char<1,5>> {{.*}} +! CHECK: %[[xshp:.*]] = fir.shape %[[two]] : (index) -> !fir.shape<1> +! CHECK: %[[xbox:.*]] = fir.embox %[[x]](%[[xshp]]) : (!fir.ref>>, !fir.shape<1>) -> !fir.box>> +! CHECK: %[[xaddr:.*]] = fir.box_addr %[[xbox]] : (!fir.box>>) -> !fir.ref>> +! CHECK: %[[xaddrval:.*]] = fir.convert %[[xaddr]] : (!fir.ref>>) -> i64 +! CHECK: fir.store %[[xaddrval]] to %[[p]] : !fir.ref +end + +! CHECK-LABEL: func.func @_QPloc_arrayelement() { +subroutine loc_arrayelement() + integer(8) :: p + integer :: x(10) + p = loc(x(7)) +! CHECK: %[[p:.*]] = fir.alloca i64 {{.*}} +! CHECK: %[[x:.*]] = fir.alloca !fir.array<10xi32> {{.*}} +! CHECK: %[[idx:.*]] = arith.constant 7 : i64 +! CHECK: %[[lb:.*]] = arith.constant 1 : i64 +! CHECK: %[[offset:.*]] = arith.subi %[[idx]], %[[lb]] : i64 +! CHECK: %[[xelemcoord:.*]] = fir.coordinate_of %[[x]], %[[offset]] : (!fir.ref>, i64) -> !fir.ref +! CHECK: %[[xelembox:.*]] = fir.embox %[[xelemcoord]] : (!fir.ref) -> !fir.box +! CHECK: %[[xelemaddr:.*]] = fir.box_addr %[[xelembox]] : (!fir.box) -> !fir.ref +! CHECK: %[[xelemaddrval:.*]] = fir.convert %[[xelemaddr]] : (!fir.ref) -> i64 +! CHECK: fir.store %[[xelemaddrval]] to %[[p]] : !fir.ref +end + +! CHECK-LABEL: func.func @_QPloc_arraysection( +! CHECK-SAME: %[[arg:.*]]: !fir.ref {{.*}}) { +subroutine loc_arraysection(i) + integer(8) :: p + integer :: i + real :: x(11) + p = loc(x(i:)) +! CHECK: %[[p:.*]] = fir.alloca i64 {{.*}} +! CHECK: %[[eleven:.*]] = arith.constant 11 : index +! CHECK: %[[x:.*]] = fir.alloca !fir.array<11xf32> {{.*}} +! CHECK: %[[one:.*]] = arith.constant 1 : index +! CHECK: %[[i:.*]] = fir.load %[[arg]] : !fir.ref +! CHECK: %[[il:.*]] = fir.convert %[[i]] : (i32) -> i64 +! CHECK: %[[iidx:.*]] = fir.convert %[[il]] : (i64) -> index +! CHECK: %[[onel:.*]] = arith.constant 1 : i64 +! CHECK: %[[stpidx:.*]] = fir.convert %[[onel]] : (i64) -> index +! CHECK: %[[xrng:.*]] = arith.addi %[[one]], %[[eleven]] : index +! CHECK: %[[xub:.*]] = arith.subi %[[xrng]], %[[one]] : index +! CHECK: %[[xshp:.*]] = fir.shape %[[eleven]] : (index) -> !fir.shape<1> +! CHECK: %[[xslice:.*]] = fir.slice %[[iidx]], %[[xub]], %[[stpidx]] : (index, index, index) -> !fir.slice<1> +! CHECK: %[[xbox:.*]] = fir.embox %[[x]](%[[xshp]]) [%[[xslice]]] : (!fir.ref>, !fir.shape<1>, !fir.slice<1>) -> !fir.box> +! CHECK: %[[xaddr:.*]] = fir.box_addr %[[xbox]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[xaddrval:.*]] = fir.convert %[[xaddr]] : (!fir.ref>) -> i64 +! CHECK: fir.store %[[xaddrval]] to %[[p]] : !fir.ref +end + +! CHECK-LABEL: func.func @_QPloc_non_save_pointer_scalar() { +subroutine loc_non_save_pointer_scalar() + integer(8) :: p + real, pointer :: x + real, target :: t + x => t + p = loc(x) +! CHECK: %[[p:.*]] = fir.alloca i64 {{.*}} +! CHECK: %[[t:.*]] = fir.alloca f32 {{.*}} +! CHECK: %2 = fir.alloca !fir.box> {{.*}} +! CHECK: %[[xa:.*]] = fir.alloca !fir.ptr {{.*}} +! CHECK: %[[zero:.*]] = fir.zero_bits !fir.ptr +! CHECK: fir.store %[[zero]] to %[[xa]] : !fir.ref> +! CHECK: %[[taddr:.*]] = fir.convert %[[t]] : (!fir.ref) -> !fir.ptr +! CHECK: fir.store %[[taddr]] to %[[xa]] : !fir.ref> +! CHECK: %[[x:.*]] = fir.load %[[xa]] : !fir.ref> +! CHECK: %[[xbox:.*]] = fir.embox %[[x]] : (!fir.ptr) -> !fir.box +! CHECK: %[[xaddr:.*]] = fir.box_addr %[[xbox]] : (!fir.box) -> !fir.ref +! CHECK: %[[xaddrval:.*]] = fir.convert %[[xaddr]] : (!fir.ref) -> i64 +! CHECK: fir.store %[[xaddrval]] to %[[p]] : !fir.ref +end + +! CHECK-LABEL: func.func @_QPloc_save_pointer_scalar() { +subroutine loc_save_pointer_scalar() + integer :: p + real, pointer, save :: x + p = loc(x) +! CHECK: %[[p:.*]] = fir.alloca i32 {{.*}} +! CHECK: %[[x:.*]] = fir.address_of(@_QFloc_save_pointer_scalarEx) : !fir.ref>> +! CHECK: %[[xref:.*]] = fir.load %[[x]] : !fir.ref>> +! CHECK: %[[xaddr:.*]] = fir.box_addr %[[xref]] : (!fir.box>) -> !fir.ptr +! CHECK: %[[xbox:.*]] = fir.embox %[[xaddr]] : (!fir.ptr) -> !fir.box +! CHECK: %[[xaddr2:.*]] = fir.box_addr %[[xbox]] : (!fir.box) -> !fir.ref +! CHECK: %[[xaddr2vall:.*]] = fir.convert %[[xaddr2]] : (!fir.ref) -> i64 +! CHECK: %[[xaddr2val:.*]] = fir.convert %[[xaddr2vall]] : (i64) -> i32 +! CHECK: fir.store %[[xaddr2val]] to %[[p]] : !fir.ref +end + +! CHECK-LABEL: func.func @_QPloc_derived_type() { +subroutine loc_derived_type + integer(8) :: p + type dt + integer :: i + end type + type(dt) :: xdt + p = loc(xdt) +! CHECK: %[[p:.*]] = fir.alloca i64 {{.*}} +! CHECK: %[[xdt:.*]] = fir.alloca !fir.type<_QFloc_derived_typeTdt{i:i32}> {{.*}} +! CHECK: %[[xdtbox:.*]] = fir.embox %[[xdt]] : (!fir.ref>) -> !fir.box> +! CHECK: %[[xdtaddr:.*]] = fir.box_addr %[[xdtbox]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[xdtaddrval:.*]] = fir.convert %[[xdtaddr]] : (!fir.ref>) -> i64 +! CHECK: fir.store %[[xdtaddrval]] to %[[p]] : !fir.ref +end + +! CHECK-LABEL: func.func @_QPloc_pointer_array() { +subroutine loc_pointer_array + integer(8) :: p + integer, pointer :: x(:) + p = loc(x) +! CHECK: %[[p:.*]] = fir.alloca i64 {{.*}} +! CHECK: %[[x:.*]] = fir.alloca !fir.box>> {{.*}} +! CHECK: %2 = fir.zero_bits !fir.ptr> +! CHECK: %[[zero:.*]] = arith.constant 0 : index +! CHECK: %[[xshp:.*]] = fir.shape %[[zero]] : (index) -> !fir.shape<1> +! CHECK: %[[xbox0:.*]] = fir.embox %2(%[[xshp]]) : (!fir.ptr>, !fir.shape<1>) -> !fir.box>> +! CHECK: fir.store %[[xbox0]] to %[[x]] : !fir.ref>>> +! CHECK: %[[xbox:.*]] = fir.load %[[x]] : !fir.ref>>> +! CHECK: %[[xaddr:.*]] = fir.box_addr %[[xbox]] : (!fir.box>>) -> !fir.ptr> +! CHECK: %[[xaddrval:.*]] = fir.convert %[[xaddr]] : (!fir.ptr>) -> i64 +! CHECK: fir.store %[[xaddrval]] to %[[p]] : !fir.ref +end + +! CHECK-LABEL: func.func @_QPloc_allocatable_array() { +subroutine loc_allocatable_array + integer(8) :: p + integer, allocatable :: x(:) + p = loc(x) +! CHECK: %[[p:.*]] = fir.alloca i64 {{.*}} +! CHECK: %1 = fir.alloca !fir.box>> {{.*}} +! CHECK: %[[stg:.*]] = fir.alloca !fir.heap> {{.*}} +! CHECK: %[[lb:.*]] = fir.alloca index {{.*}} +! CHECK: %[[ext:.*]] = fir.alloca index {{.*}} +! CHECK: %[[zstg:.*]] = fir.zero_bits !fir.heap> +! CHECK: fir.store %[[zstg]] to %[[stg]] : !fir.ref>> +! CHECK: %[[lbval:.*]] = fir.load %[[lb]] : !fir.ref +! CHECK: %[[extval:.*]] = fir.load %[[ext]] : !fir.ref +! CHECK: %[[stgaddr:.*]] = fir.load %[[stg]] : !fir.ref>> +! CHECK: %[[ss:.*]] = fir.shape_shift %[[lbval]], %[[extval]] : (index, index) -> !fir.shapeshift<1> +! CHECK: %[[xbox:.*]] = fir.embox %[[stgaddr]](%[[ss]]) : (!fir.heap>, !fir.shapeshift<1>) -> !fir.box> +! CHECK: %[[xaddr:.*]] = fir.box_addr %[[xbox]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[xaddrval:.*]] = fir.convert %[[xaddr]] : (!fir.ref>) -> i64 +! CHECK: fir.store %[[xaddrval]] to %[[p]] : !fir.ref +end + +! CHECK-LABEL: func.func @_QPtest_external() { +subroutine test_external() + integer(8) :: p + integer, external :: f + p = loc(x=f) +! CHECK: %[[p:.*]] = fir.alloca i64 {{.*}} +! CHECK: %[[f:.*]] = fir.address_of(@_QPf) : () -> i32 +! CHECK: %[[fbox:.*]] = fir.emboxproc %[[f]] : (() -> i32) -> !fir.boxproc<() -> i32> +! CHECK: %[[faddr:.*]] = fir.box_addr %[[fbox]] : (!fir.boxproc<() -> i32>) -> (() -> i32) +! CHECK: %[[faddrval:.*]] = fir.convert %[[faddr]] : (() -> i32) -> i64 +! CHECK: fir.store %[[faddrval]] to %[[p]] : !fir.ref +end + +! CHECK-LABEL: func.func @_QPtest_proc() { +subroutine test_proc() + integer(8) :: p + procedure() :: g + p = loc(x=g) +! CHECK: %[[p:.*]] = fir.alloca i64 {{.*}} +! CHECK: %[[g:.*]] = fir.address_of(@_QPg) : () -> () +! CHECK: %[[gbox:.*]] = fir.emboxproc %[[g]] : (() -> ()) -> !fir.boxproc<() -> ()> +! CHECK: %[[gaddr:.*]] = fir.box_addr %[[gbox]] : (!fir.boxproc<() -> ()>) -> (() -> ()) +! CHECK: %[[gaddrval:.*]] = fir.convert %[[gaddr]] : (() -> ()) -> i64 +! CHECK: fir.store %[[gaddrval]] to %[[p]] : !fir.ref +end diff --git a/flang/test/Lower/polymorphic.f90 b/flang/test/Lower/polymorphic.f90 --- a/flang/test/Lower/polymorphic.f90 +++ b/flang/test/Lower/polymorphic.f90 @@ -14,6 +14,16 @@ real :: c end type + type r1 + real, pointer :: rp(:) => null() + end type + + type c1 + character(2) :: tmp = 'c1' + contains + procedure :: get_tmp + end type + contains ! Test correct access to polymorphic entity component. @@ -99,4 +109,60 @@ ! CHECK-LABEL: func.func @_QMpolymorphic_testPpolymorphic_to_nonpolymorphic ! Just checking that FIR is generated without error. +! Test that lowering does not crash for function return with unlimited +! polymoprhic value. + + function up_ret() + class(*), pointer :: up_ret(:) + end function + +! CHECK-LABEL: func.func @_QMpolymorphic_testPup_ret() -> !fir.class>> { + + subroutine call_up_ret() + class(*), pointer :: p(:) + p => up_ret() + end subroutine + +! CHECK-LABEL: func.func @_QMpolymorphic_testPcall_up_ret() { +! CHECK: %{{.*}} = fir.call @_QMpolymorphic_testPup_ret() {{.*}} : () -> !fir.class>> + + subroutine rebox_f32_to_none(r) + class(r1) :: r + class(*), pointer :: p(:) + p => r%rp + end subroutine + +! CHECK-LABEL: func.func @_QMpolymorphic_testPrebox_f32_to_none( +! CHECK-SAME: %[[ARG0:.*]]: !fir.class>>}>> {fir.bindc_name = "r"}) { +! CHECK: %[[P:.*]] = fir.alloca !fir.class>> {bindc_name = "p", uniq_name = "_QMpolymorphic_testFrebox_f32_to_noneEp"} +! CHECK: %[[FIELD_RP:.*]] = fir.field_index rp, !fir.type<_QMpolymorphic_testTr1{rp:!fir.box>>}> +! CHECK: %[[COORD_RP:.*]] = fir.coordinate_of %[[ARG0]], %[[FIELD_RP]] : (!fir.class>>}>>, !fir.field) -> !fir.ref>>> +! CHECK: %[[LOADED_RP:.*]] = fir.load %[[COORD_RP]] : !fir.ref>>> +! CHECK: %[[C0:.*]] = arith.constant 0 : index +! CHECK: %[[RP_DIMS:.*]]:3 = fir.box_dims %[[LOADED_RP]], %[[C0]] : (!fir.box>>, index) -> (index, index, index) +! CHECK: %[[SHIFT:.*]] = fir.shift %[[RP_DIMS]]#0 : (index) -> !fir.shift<1> +! CHECK: %[[REBOX_TO_BOX:.*]] = fir.rebox %[[LOADED_RP]](%[[SHIFT]]) : (!fir.box>>, !fir.shift<1>) -> !fir.box> +! CHECK: %[[REBOX_TO_UP:.*]] = fir.rebox %[[REBOX_TO_BOX]] : (!fir.box>) -> !fir.class>> +! CHECK: fir.store %[[REBOX_TO_UP]] to %[[P]] : !fir.ref>>> +! CHECK: return + +! Test that the fir.dispatch operation is created with the correct pass object +! and the pass_arg_pos attribute is incremented correctly when character +! function result is added as argument. + + function get_tmp(this) + class(c1) :: this + character(2) :: get_tmp + get_tmp = this%tmp + end function + + subroutine call_get_tmp(c) + class(c1) :: c + print*, c%get_tmp() + end subroutine + +! CHECK-LABEL: func.func @_QMpolymorphic_testPcall_get_tmp( +! CHECK-SAME: %[[ARG0:.*]]: !fir.class}>> {fir.bindc_name = "c"}) { +! CHECK: %{{.*}} = fir.dispatch "get_tmp"(%[[ARG0]] : !fir.class}>>) (%{{.*}}, %{{.*}}, %[[ARG0]] : !fir.ref>, index, !fir.class}>>) -> !fir.boxchar<1> {pass_arg_pos = 2 : i32} + end module diff --git a/libc/src/string/memory_utils/bcmp_implementations.h b/libc/src/string/memory_utils/bcmp_implementations.h --- a/libc/src/string/memory_utils/bcmp_implementations.h +++ b/libc/src/string/memory_utils/bcmp_implementations.h @@ -116,7 +116,7 @@ inline_bcmp_aarch64(CPtr p1, CPtr p2, size_t count) { if (likely(count <= 32)) { if (unlikely(count >= 16)) { - return generic::Bcmp<16>::head_tail(p1, p2, count); + return aarch64::Bcmp<16>::head_tail(p1, p2, count); } switch (count) { case 0: @@ -147,15 +147,15 @@ } if (count <= 64) - return generic::Bcmp<32>::head_tail(p1, p2, count); + return aarch64::Bcmp<32>::head_tail(p1, p2, count); // Aligned loop if > 256, otherwise normal loop - if (count > 256) { - if (auto value = generic::Bcmp<32>::block(p1, p2)) + if (unlikely(count > 256)) { + if (auto value = aarch64::Bcmp<32>::block(p1, p2)) return value; align_to_next_boundary<16, Arg::P1>(p1, p2, count); } - return generic::Bcmp<32>::loop_and_tail(p1, p2, count); + return aarch64::Bcmp<32>::loop_and_tail(p1, p2, count); } #endif // defined(LLVM_LIBC_ARCH_AARCH64) diff --git a/libcxx/.clang-tidy b/libcxx/.clang-tidy --- a/libcxx/.clang-tidy +++ b/libcxx/.clang-tidy @@ -25,6 +25,7 @@ readability-redundant-control-flow, readability-redundant-function-ptr-dereference, readability-redundant-preprocessor, + readability-simplify-boolean-expr, readability-simplify-subscript-expr, readability-uniqueptr-delete-release, @@ -63,4 +64,4 @@ # readability-redundant-access-specifiers, # readability-redundant-declaration, # readability-redundant-member-init, -# readability-simplify-boolean-expr, +# diff --git a/libcxx/docs/ReleaseNotes.rst b/libcxx/docs/ReleaseNotes.rst --- a/libcxx/docs/ReleaseNotes.rst +++ b/libcxx/docs/ReleaseNotes.rst @@ -100,19 +100,14 @@ - The ``_LIBCPP_DEBUG`` macro is not honored anymore, and it is an error to try to use it. Please migrate to ``_LIBCPP_ENABLE_DEBUG_MODE`` instead. -- A base template for ``std::char_traits`` is not provided anymore. The Standard mandates that the library - provides specializations for several types like ``char`` and ``wchar_t``, which libc++ does. However, libc++ - used to additionally provide a default implementation for ``std::char_traits`` for arbitrary ``T``. Not - only does the Standard not mandate that one is provided, but such an implementation is bound to be incorrect - for some types, so it has been removed. As an exception, ``std::char_traits`` and - ``std::char_traits`` are kept for a limited period of time and marked as deprecated to let people - move off of those, since we know there were some users of those. They will be removed in LLVM 18. - Upcoming Deprecations and Removals ---------------------------------- -- The specializations of ``std::char_traits`` for ``unsigned char`` and ``signed char`` are provided until - LLVM 18. Those non-standard specializations are provided for a transition period and marked as deprecated - but will be removed in the future. +- The base template for ``std::char_traits`` has been marked as deprecated and will be removed in LLVM 18. If + you are using ``std::char_traits`` with types other than ``char``, ``wchar_t``, ``char8_t``, ``char16_t``, + ``char32_t`` or a custom character type for which you specialized ``std::char_traits``, your code will stop + working when we remove the base template. The Standard does not mandate that a base template is provided, + and such a base template is bound to be incorrect for some types, which could currently cause unexpected + behavior while going undetected. API Changes ----------- diff --git a/libcxx/docs/Status/Cxx20Papers.csv b/libcxx/docs/Status/Cxx20Papers.csv --- a/libcxx/docs/Status/Cxx20Papers.csv +++ b/libcxx/docs/Status/Cxx20Papers.csv @@ -171,7 +171,6 @@ "`P1739R4 `__","LWG","Avoid template bloat for safe_ranges in combination with ""subrange-y"" view adaptors","Prague","|Complete|","15.0" "`P1831R1 `__","LWG","Deprecating volatile: library","Prague","* *","" "`P1868R2 `__","LWG","width: clarifying units of width and precision in std::format","Prague","|Complete|","14.0" -"`P1908R1 `__","CWG","Reserving Attribute Namespaces for Future Use","Prague","* *","" "`P1937R2 `__","CWG","Fixing inconsistencies between constexpr and consteval functions","Prague","* *","" "`P1956R1 `__","LWG","On the names of low-level bit manipulation functions","Prague","|Complete|","12.0" "`P1957R2 `__","CWG","Converting from ``T*``\ to bool should be considered narrowing (re: US 212)","Prague","* *","" diff --git a/libcxx/docs/index.rst b/libcxx/docs/index.rst --- a/libcxx/docs/index.rst +++ b/libcxx/docs/index.rst @@ -106,7 +106,7 @@ Compiler Versions Restrictions Support policy ============ =============== ========================== ===================== Clang 14, 15 latest two stable releases per `LLVM's release page `_ -AppleClang 13 latest stable release per `Xcode's release page `_ +AppleClang 14 latest stable release per `Xcode's release page `_ Open XL 17.1 (AIX) latest stable release per `Open XL's documentation page `_ GCC 12 In C++11 or later only latest stable release per `GCC's release page `_ ============ =============== ========================== ===================== diff --git a/libcxx/include/__chrono/convert_to_timespec.h b/libcxx/include/__chrono/convert_to_timespec.h --- a/libcxx/include/__chrono/convert_to_timespec.h +++ b/libcxx/include/__chrono/convert_to_timespec.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___CHRONO_CONVERT_TO_TIMESPEC_H #define _LIBCPP___CHRONO_CONVERT_TO_TIMESPEC_H diff --git a/libcxx/include/__format/unicode.h b/libcxx/include/__format/unicode.h --- a/libcxx/include/__format/unicode.h +++ b/libcxx/include/__format/unicode.h @@ -369,10 +369,7 @@ if (__prev == __property::__Regional_Indicator && __next == __property::__Regional_Indicator) { // GB12 + GB13 __ri_break_allowed = !__ri_break_allowed; - if (__ri_break_allowed) - return true; - - return false; + return __ri_break_allowed; } // *** Otherwise, break everywhere. *** diff --git a/libcxx/include/__iterator/counted_iterator.h b/libcxx/include/__iterator/counted_iterator.h --- a/libcxx/include/__iterator/counted_iterator.h +++ b/libcxx/include/__iterator/counted_iterator.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___ITERATOR_COUNTED_ITERATOR_H #define _LIBCPP___ITERATOR_COUNTED_ITERATOR_H diff --git a/libcxx/include/__iterator/iter_swap.h b/libcxx/include/__iterator/iter_swap.h --- a/libcxx/include/__iterator/iter_swap.h +++ b/libcxx/include/__iterator/iter_swap.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___ITERATOR_ITER_SWAP_H #define _LIBCPP___ITERATOR_ITER_SWAP_H diff --git a/libcxx/include/__iterator/projected.h b/libcxx/include/__iterator/projected.h --- a/libcxx/include/__iterator/projected.h +++ b/libcxx/include/__iterator/projected.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___ITERATOR_PROJECTED_H #define _LIBCPP___ITERATOR_PROJECTED_H diff --git a/libcxx/include/__locale b/libcxx/include/__locale --- a/libcxx/include/__locale +++ b/libcxx/include/__locale @@ -701,7 +701,7 @@ const char_type* scan_not(mask __m, const char_type* __low, const char_type* __high) const { for (; __low != __high; ++__low) - if (!(isascii(*__low) && (__tab_[static_cast(*__low)] & __m))) + if (!isascii(*__low) || !(__tab_[static_cast(*__low)] & __m)) break; return __low; } diff --git a/libcxx/include/__ranges/access.h b/libcxx/include/__ranges/access.h --- a/libcxx/include/__ranges/access.h +++ b/libcxx/include/__ranges/access.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_ACCESS_H #define _LIBCPP___RANGES_ACCESS_H diff --git a/libcxx/include/__ranges/all.h b/libcxx/include/__ranges/all.h --- a/libcxx/include/__ranges/all.h +++ b/libcxx/include/__ranges/all.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_ALL_H #define _LIBCPP___RANGES_ALL_H diff --git a/libcxx/include/__ranges/common_view.h b/libcxx/include/__ranges/common_view.h --- a/libcxx/include/__ranges/common_view.h +++ b/libcxx/include/__ranges/common_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_COMMON_VIEW_H #define _LIBCPP___RANGES_COMMON_VIEW_H diff --git a/libcxx/include/__ranges/concepts.h b/libcxx/include/__ranges/concepts.h --- a/libcxx/include/__ranges/concepts.h +++ b/libcxx/include/__ranges/concepts.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_CONCEPTS_H #define _LIBCPP___RANGES_CONCEPTS_H diff --git a/libcxx/include/__ranges/counted.h b/libcxx/include/__ranges/counted.h --- a/libcxx/include/__ranges/counted.h +++ b/libcxx/include/__ranges/counted.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_COUNTED_H #define _LIBCPP___RANGES_COUNTED_H diff --git a/libcxx/include/__ranges/data.h b/libcxx/include/__ranges/data.h --- a/libcxx/include/__ranges/data.h +++ b/libcxx/include/__ranges/data.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_DATA_H #define _LIBCPP___RANGES_DATA_H diff --git a/libcxx/include/__ranges/drop_view.h b/libcxx/include/__ranges/drop_view.h --- a/libcxx/include/__ranges/drop_view.h +++ b/libcxx/include/__ranges/drop_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_DROP_VIEW_H #define _LIBCPP___RANGES_DROP_VIEW_H diff --git a/libcxx/include/__ranges/empty.h b/libcxx/include/__ranges/empty.h --- a/libcxx/include/__ranges/empty.h +++ b/libcxx/include/__ranges/empty.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_EMPTY_H #define _LIBCPP___RANGES_EMPTY_H diff --git a/libcxx/include/__ranges/empty_view.h b/libcxx/include/__ranges/empty_view.h --- a/libcxx/include/__ranges/empty_view.h +++ b/libcxx/include/__ranges/empty_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_EMPTY_VIEW_H #define _LIBCPP___RANGES_EMPTY_VIEW_H diff --git a/libcxx/include/__ranges/filter_view.h b/libcxx/include/__ranges/filter_view.h --- a/libcxx/include/__ranges/filter_view.h +++ b/libcxx/include/__ranges/filter_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_FILTER_VIEW_H #define _LIBCPP___RANGES_FILTER_VIEW_H diff --git a/libcxx/include/__ranges/iota_view.h b/libcxx/include/__ranges/iota_view.h --- a/libcxx/include/__ranges/iota_view.h +++ b/libcxx/include/__ranges/iota_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_IOTA_VIEW_H #define _LIBCPP___RANGES_IOTA_VIEW_H diff --git a/libcxx/include/__ranges/istream_view.h b/libcxx/include/__ranges/istream_view.h --- a/libcxx/include/__ranges/istream_view.h +++ b/libcxx/include/__ranges/istream_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_ISTREAM_VIEW_H #define _LIBCPP___RANGES_ISTREAM_VIEW_H diff --git a/libcxx/include/__ranges/join_view.h b/libcxx/include/__ranges/join_view.h --- a/libcxx/include/__ranges/join_view.h +++ b/libcxx/include/__ranges/join_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_JOIN_VIEW_H #define _LIBCPP___RANGES_JOIN_VIEW_H diff --git a/libcxx/include/__ranges/non_propagating_cache.h b/libcxx/include/__ranges/non_propagating_cache.h --- a/libcxx/include/__ranges/non_propagating_cache.h +++ b/libcxx/include/__ranges/non_propagating_cache.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_NON_PROPAGATING_CACHE_H #define _LIBCPP___RANGES_NON_PROPAGATING_CACHE_H diff --git a/libcxx/include/__ranges/owning_view.h b/libcxx/include/__ranges/owning_view.h --- a/libcxx/include/__ranges/owning_view.h +++ b/libcxx/include/__ranges/owning_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_OWNING_VIEW_H #define _LIBCPP___RANGES_OWNING_VIEW_H diff --git a/libcxx/include/__ranges/rbegin.h b/libcxx/include/__ranges/rbegin.h --- a/libcxx/include/__ranges/rbegin.h +++ b/libcxx/include/__ranges/rbegin.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_RBEGIN_H #define _LIBCPP___RANGES_RBEGIN_H diff --git a/libcxx/include/__ranges/ref_view.h b/libcxx/include/__ranges/ref_view.h --- a/libcxx/include/__ranges/ref_view.h +++ b/libcxx/include/__ranges/ref_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_REF_VIEW_H #define _LIBCPP___RANGES_REF_VIEW_H diff --git a/libcxx/include/__ranges/rend.h b/libcxx/include/__ranges/rend.h --- a/libcxx/include/__ranges/rend.h +++ b/libcxx/include/__ranges/rend.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_REND_H #define _LIBCPP___RANGES_REND_H diff --git a/libcxx/include/__ranges/reverse_view.h b/libcxx/include/__ranges/reverse_view.h --- a/libcxx/include/__ranges/reverse_view.h +++ b/libcxx/include/__ranges/reverse_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_REVERSE_VIEW_H #define _LIBCPP___RANGES_REVERSE_VIEW_H diff --git a/libcxx/include/__ranges/single_view.h b/libcxx/include/__ranges/single_view.h --- a/libcxx/include/__ranges/single_view.h +++ b/libcxx/include/__ranges/single_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_SINGLE_VIEW_H #define _LIBCPP___RANGES_SINGLE_VIEW_H diff --git a/libcxx/include/__ranges/size.h b/libcxx/include/__ranges/size.h --- a/libcxx/include/__ranges/size.h +++ b/libcxx/include/__ranges/size.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_SIZE_H #define _LIBCPP___RANGES_SIZE_H diff --git a/libcxx/include/__ranges/subrange.h b/libcxx/include/__ranges/subrange.h --- a/libcxx/include/__ranges/subrange.h +++ b/libcxx/include/__ranges/subrange.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_SUBRANGE_H #define _LIBCPP___RANGES_SUBRANGE_H diff --git a/libcxx/include/__ranges/take_view.h b/libcxx/include/__ranges/take_view.h --- a/libcxx/include/__ranges/take_view.h +++ b/libcxx/include/__ranges/take_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_TAKE_VIEW_H #define _LIBCPP___RANGES_TAKE_VIEW_H diff --git a/libcxx/include/__ranges/transform_view.h b/libcxx/include/__ranges/transform_view.h --- a/libcxx/include/__ranges/transform_view.h +++ b/libcxx/include/__ranges/transform_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_TRANSFORM_VIEW_H #define _LIBCPP___RANGES_TRANSFORM_VIEW_H diff --git a/libcxx/include/__ranges/view_interface.h b/libcxx/include/__ranges/view_interface.h --- a/libcxx/include/__ranges/view_interface.h +++ b/libcxx/include/__ranges/view_interface.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_VIEW_INTERFACE_H #define _LIBCPP___RANGES_VIEW_INTERFACE_H diff --git a/libcxx/include/__ranges/zip_view.h b/libcxx/include/__ranges/zip_view.h --- a/libcxx/include/__ranges/zip_view.h +++ b/libcxx/include/__ranges/zip_view.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___RANGES_ZIP_VIEW_H #define _LIBCPP___RANGES_ZIP_VIEW_H diff --git a/libcxx/include/__string/char_traits.h b/libcxx/include/__string/char_traits.h --- a/libcxx/include/__string/char_traits.h +++ b/libcxx/include/__string/char_traits.h @@ -60,7 +60,7 @@ static size_t length(const char_type*); static const char_type* find(const char_type*, size_t, const char_type&); static char_type* move(char_type*, const char_type*, size_t); - static char_type* copy(char_type*, const char_type* __s2, size_t); + static char_type* copy(char_type*, const char_type*, size_t); static char_type* assign(char_type*, size_t, char_type); static int_type not_eof(int_type); @@ -71,6 +71,105 @@ }; */ +// +// Temporary extension to provide a base template for std::char_traits. +// TODO: Remove in LLVM 18. +// +template +struct _LIBCPP_DEPRECATED_("char_traits for T not equal to char, wchar_t, char8_t, char16_t or char32_t is non-standard and is provided for a temporary period. It will be removed in LLVM 18, so please migrate off of it.") + char_traits +{ + using char_type = _CharT; + using int_type = int; + using off_type = streamoff; + using pos_type = streampos; + using state_type = mbstate_t; + + static inline void _LIBCPP_CONSTEXPR_SINCE_CXX17 + assign(char_type& __c1, const char_type& __c2) _NOEXCEPT {__c1 = __c2;} + static inline _LIBCPP_CONSTEXPR bool eq(char_type __c1, char_type __c2) _NOEXCEPT + {return __c1 == __c2;} + static inline _LIBCPP_CONSTEXPR bool lt(char_type __c1, char_type __c2) _NOEXCEPT + {return __c1 < __c2;} + + static _LIBCPP_CONSTEXPR_SINCE_CXX17 + int compare(const char_type* __s1, const char_type* __s2, size_t __n) { + for (; __n; --__n, ++__s1, ++__s2) + { + if (lt(*__s1, *__s2)) + return -1; + if (lt(*__s2, *__s1)) + return 1; + } + return 0; + } + _LIBCPP_INLINE_VISIBILITY static _LIBCPP_CONSTEXPR_SINCE_CXX17 + size_t length(const char_type* __s) { + size_t __len = 0; + for (; !eq(*__s, char_type(0)); ++__s) + ++__len; + return __len; + } + _LIBCPP_INLINE_VISIBILITY static _LIBCPP_CONSTEXPR_SINCE_CXX17 + const char_type* find(const char_type* __s, size_t __n, const char_type& __a) { + for (; __n; --__n) + { + if (eq(*__s, __a)) + return __s; + ++__s; + } + return nullptr; + } + static _LIBCPP_CONSTEXPR_SINCE_CXX20 + char_type* move(char_type* __s1, const char_type* __s2, size_t __n) { + if (__n == 0) return __s1; + char_type* __r = __s1; + if (__s1 < __s2) + { + for (; __n; --__n, ++__s1, ++__s2) + assign(*__s1, *__s2); + } + else if (__s2 < __s1) + { + __s1 += __n; + __s2 += __n; + for (; __n; --__n) + assign(*--__s1, *--__s2); + } + return __r; + } + _LIBCPP_INLINE_VISIBILITY + static _LIBCPP_CONSTEXPR_SINCE_CXX20 + char_type* copy(char_type* __s1, const char_type* __s2, size_t __n) { + if (!__libcpp_is_constant_evaluated()) { + _LIBCPP_ASSERT(__s2 < __s1 || __s2 >= __s1+__n, "char_traits::copy overlapped range"); + } + char_type* __r = __s1; + for (; __n; --__n, ++__s1, ++__s2) + assign(*__s1, *__s2); + return __r; + } + _LIBCPP_INLINE_VISIBILITY + static _LIBCPP_CONSTEXPR_SINCE_CXX20 + char_type* assign(char_type* __s, size_t __n, char_type __a) { + char_type* __r = __s; + for (; __n; --__n, ++__s) + assign(*__s, __a); + return __r; + } + + static inline _LIBCPP_CONSTEXPR int_type not_eof(int_type __c) _NOEXCEPT + {return eq_int_type(__c, eof()) ? ~eof() : __c;} + static inline _LIBCPP_CONSTEXPR char_type to_char_type(int_type __c) _NOEXCEPT + {return char_type(__c);} + static inline _LIBCPP_CONSTEXPR int_type to_int_type(char_type __c) _NOEXCEPT + {return int_type(__c);} + static inline _LIBCPP_CONSTEXPR bool eq_int_type(int_type __c1, int_type __c2) _NOEXCEPT + {return __c1 == __c2;} + static inline _LIBCPP_CONSTEXPR int_type eof() _NOEXCEPT + {return int_type(EOF);} +}; + template _LIBCPP_HIDE_FROM_ABI static inline _LIBCPP_CONSTEXPR_SINCE_CXX20 _CharT* __char_traits_move(_CharT* __dest, const _CharT* __source, size_t __n) _NOEXCEPT @@ -617,202 +716,6 @@ return nullptr; } -// -// Temporary extensions for std::char_traits and std::char_traits. -// TODO: Remove those in LLVM 18. -// -template <> -struct _LIBCPP_TEMPLATE_VIS - _LIBCPP_DEPRECATED_("char_traits is non-standard and is provided for a temporary period. It will be removed in LLVM 18, so please migrate off of it.") - char_traits -{ - using char_type = unsigned char; - using int_type = int; - using off_type = streamoff; - using pos_type = streampos; - using state_type = mbstate_t; - - static inline void _LIBCPP_CONSTEXPR_SINCE_CXX17 - assign(char_type& __c1, const char_type& __c2) _NOEXCEPT {__c1 = __c2;} - static inline _LIBCPP_CONSTEXPR bool eq(char_type __c1, char_type __c2) _NOEXCEPT - {return __c1 == __c2;} - static inline _LIBCPP_CONSTEXPR bool lt(char_type __c1, char_type __c2) _NOEXCEPT - {return __c1 < __c2;} - - static _LIBCPP_CONSTEXPR_SINCE_CXX17 - int compare(const char_type* __s1, const char_type* __s2, size_t __n) { - for (; __n; --__n, ++__s1, ++__s2) - { - if (lt(*__s1, *__s2)) - return -1; - if (lt(*__s2, *__s1)) - return 1; - } - return 0; - } - _LIBCPP_INLINE_VISIBILITY static _LIBCPP_CONSTEXPR_SINCE_CXX17 - size_t length(const char_type* __s) { - size_t __len = 0; - for (; !eq(*__s, char_type(0)); ++__s) - ++__len; - return __len; - } - _LIBCPP_INLINE_VISIBILITY static _LIBCPP_CONSTEXPR_SINCE_CXX17 - const char_type* find(const char_type* __s, size_t __n, const char_type& __a) { - for (; __n; --__n) - { - if (eq(*__s, __a)) - return __s; - ++__s; - } - return nullptr; - } - static _LIBCPP_CONSTEXPR_SINCE_CXX20 - char_type* move(char_type* __s1, const char_type* __s2, size_t __n) { - if (__n == 0) return __s1; - char_type* __r = __s1; - if (__s1 < __s2) - { - for (; __n; --__n, ++__s1, ++__s2) - assign(*__s1, *__s2); - } - else if (__s2 < __s1) - { - __s1 += __n; - __s2 += __n; - for (; __n; --__n) - assign(*--__s1, *--__s2); - } - return __r; - } - _LIBCPP_INLINE_VISIBILITY - static _LIBCPP_CONSTEXPR_SINCE_CXX20 - char_type* copy(char_type* __s1, const char_type* __s2, size_t __n) { - if (!__libcpp_is_constant_evaluated()) { - _LIBCPP_ASSERT(__s2 < __s1 || __s2 >= __s1+__n, "char_traits::copy overlapped range"); - } - char_type* __r = __s1; - for (; __n; --__n, ++__s1, ++__s2) - assign(*__s1, *__s2); - return __r; - } - _LIBCPP_INLINE_VISIBILITY - static _LIBCPP_CONSTEXPR_SINCE_CXX20 - char_type* assign(char_type* __s, size_t __n, char_type __a) { - char_type* __r = __s; - for (; __n; --__n, ++__s) - assign(*__s, __a); - return __r; - } - - static inline _LIBCPP_CONSTEXPR int_type not_eof(int_type __c) _NOEXCEPT - {return eq_int_type(__c, eof()) ? ~eof() : __c;} - static inline _LIBCPP_CONSTEXPR char_type to_char_type(int_type __c) _NOEXCEPT - {return char_type(__c);} - static inline _LIBCPP_CONSTEXPR int_type to_int_type(char_type __c) _NOEXCEPT - {return int_type(__c);} - static inline _LIBCPP_CONSTEXPR bool eq_int_type(int_type __c1, int_type __c2) _NOEXCEPT - {return __c1 == __c2;} - static inline _LIBCPP_CONSTEXPR int_type eof() _NOEXCEPT - {return int_type(EOF);} -}; - -template <> -struct _LIBCPP_TEMPLATE_VIS - _LIBCPP_DEPRECATED_("char_traits is non-standard and is provided for a temporary period. It will be removed in LLVM 18, so please migrate off of it.") - char_traits -{ - using char_type = signed char; - using int_type = int; - using off_type = streamoff; - using pos_type = streampos; - using state_type = mbstate_t; - - static inline void _LIBCPP_CONSTEXPR_SINCE_CXX17 - assign(char_type& __c1, const char_type& __c2) _NOEXCEPT {__c1 = __c2;} - static inline _LIBCPP_CONSTEXPR bool eq(char_type __c1, char_type __c2) _NOEXCEPT - {return __c1 == __c2;} - static inline _LIBCPP_CONSTEXPR bool lt(char_type __c1, char_type __c2) _NOEXCEPT - {return __c1 < __c2;} - - static _LIBCPP_CONSTEXPR_SINCE_CXX17 - int compare(const char_type* __s1, const char_type* __s2, size_t __n) { - for (; __n; --__n, ++__s1, ++__s2) - { - if (lt(*__s1, *__s2)) - return -1; - if (lt(*__s2, *__s1)) - return 1; - } - return 0; - } - _LIBCPP_INLINE_VISIBILITY static _LIBCPP_CONSTEXPR_SINCE_CXX17 - size_t length(const char_type* __s) { - size_t __len = 0; - for (; !eq(*__s, char_type(0)); ++__s) - ++__len; - return __len; - } - _LIBCPP_INLINE_VISIBILITY static _LIBCPP_CONSTEXPR_SINCE_CXX17 - const char_type* find(const char_type* __s, size_t __n, const char_type& __a) { - for (; __n; --__n) - { - if (eq(*__s, __a)) - return __s; - ++__s; - } - return nullptr; - } - static _LIBCPP_CONSTEXPR_SINCE_CXX20 - char_type* move(char_type* __s1, const char_type* __s2, size_t __n) { - if (__n == 0) return __s1; - char_type* __r = __s1; - if (__s1 < __s2) - { - for (; __n; --__n, ++__s1, ++__s2) - assign(*__s1, *__s2); - } - else if (__s2 < __s1) - { - __s1 += __n; - __s2 += __n; - for (; __n; --__n) - assign(*--__s1, *--__s2); - } - return __r; - } - _LIBCPP_INLINE_VISIBILITY - static _LIBCPP_CONSTEXPR_SINCE_CXX20 - char_type* copy(char_type* __s1, const char_type* __s2, size_t __n) { - if (!__libcpp_is_constant_evaluated()) { - _LIBCPP_ASSERT(__s2 < __s1 || __s2 >= __s1+__n, "char_traits::copy overlapped range"); - } - char_type* __r = __s1; - for (; __n; --__n, ++__s1, ++__s2) - assign(*__s1, *__s2); - return __r; - } - _LIBCPP_INLINE_VISIBILITY - static _LIBCPP_CONSTEXPR_SINCE_CXX20 - char_type* assign(char_type* __s, size_t __n, char_type __a) { - char_type* __r = __s; - for (; __n; --__n, ++__s) - assign(*__s, __a); - return __r; - } - - static inline _LIBCPP_CONSTEXPR int_type not_eof(int_type __c) _NOEXCEPT - {return eq_int_type(__c, eof()) ? ~eof() : __c;} - static inline _LIBCPP_CONSTEXPR char_type to_char_type(int_type __c) _NOEXCEPT - {return char_type(__c);} - static inline _LIBCPP_CONSTEXPR int_type to_int_type(char_type __c) _NOEXCEPT - {return int_type(__c);} - static inline _LIBCPP_CONSTEXPR bool eq_int_type(int_type __c1, int_type __c2) _NOEXCEPT - {return __c1 == __c2;} - static inline _LIBCPP_CONSTEXPR int_type eof() _NOEXCEPT - {return int_type(EOF);} -}; - // helper fns for basic_string and string_view // __str_find diff --git a/libcxx/include/__support/android/locale_bionic.h b/libcxx/include/__support/android/locale_bionic.h --- a/libcxx/include/__support/android/locale_bionic.h +++ b/libcxx/include/__support/android/locale_bionic.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef _LIBCPP_SUPPORT_ANDROID_LOCALE_BIONIC_H -#define _LIBCPP_SUPPORT_ANDROID_LOCALE_BIONIC_H +#ifndef _LIBCPP___SUPPORT_ANDROID_LOCALE_BIONIC_H +#define _LIBCPP___SUPPORT_ANDROID_LOCALE_BIONIC_H #if defined(__BIONIC__) @@ -72,4 +72,4 @@ #endif // defined(__ANDROID__) #endif // defined(__BIONIC__) -#endif // _LIBCPP_SUPPORT_ANDROID_LOCALE_BIONIC_H +#endif // _LIBCPP___SUPPORT_ANDROID_LOCALE_BIONIC_H diff --git a/libcxx/include/__support/fuchsia/xlocale.h b/libcxx/include/__support/fuchsia/xlocale.h --- a/libcxx/include/__support/fuchsia/xlocale.h +++ b/libcxx/include/__support/fuchsia/xlocale.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef _LIBCPP_SUPPORT_FUCHSIA_XLOCALE_H -#define _LIBCPP_SUPPORT_FUCHSIA_XLOCALE_H +#ifndef _LIBCPP___SUPPORT_FUCHSIA_XLOCALE_H +#define _LIBCPP___SUPPORT_FUCHSIA_XLOCALE_H #if defined(__Fuchsia__) @@ -19,4 +19,4 @@ #endif // defined(__Fuchsia__) -#endif // _LIBCPP_SUPPORT_FUCHSIA_XLOCALE_H +#endif // _LIBCPP___SUPPORT_FUCHSIA_XLOCALE_H diff --git a/libcxx/include/__support/ibm/gettod_zos.h b/libcxx/include/__support/ibm/gettod_zos.h --- a/libcxx/include/__support/ibm/gettod_zos.h +++ b/libcxx/include/__support/ibm/gettod_zos.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef _LIBCPP_SUPPORT_IBM_GETTOD_ZOS_H -#define _LIBCPP_SUPPORT_IBM_GETTOD_ZOS_H +#ifndef _LIBCPP___SUPPORT_IBM_GETTOD_ZOS_H +#define _LIBCPP___SUPPORT_IBM_GETTOD_ZOS_H #include @@ -51,4 +51,4 @@ return 0; } -#endif // _LIBCPP_SUPPORT_IBM_GETTOD_ZOS_H +#endif // _LIBCPP___SUPPORT_IBM_GETTOD_ZOS_H diff --git a/libcxx/include/__support/ibm/locale_mgmt_zos.h b/libcxx/include/__support/ibm/locale_mgmt_zos.h --- a/libcxx/include/__support/ibm/locale_mgmt_zos.h +++ b/libcxx/include/__support/ibm/locale_mgmt_zos.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef _LIBCPP_SUPPORT_IBM_LOCALE_MGMT_ZOS_H -#define _LIBCPP_SUPPORT_IBM_LOCALE_MGMT_ZOS_H +#ifndef _LIBCPP___SUPPORT_IBM_LOCALE_MGMT_ZOS_H +#define _LIBCPP___SUPPORT_IBM_LOCALE_MGMT_ZOS_H #if defined(__MVS__) #include @@ -50,4 +50,4 @@ } #endif #endif // defined(__MVS__) -#endif // _LIBCPP_SUPPORT_IBM_LOCALE_MGMT_ZOS_H +#endif // _LIBCPP___SUPPORT_IBM_LOCALE_MGMT_ZOS_H diff --git a/libcxx/include/__support/ibm/nanosleep.h b/libcxx/include/__support/ibm/nanosleep.h --- a/libcxx/include/__support/ibm/nanosleep.h +++ b/libcxx/include/__support/ibm/nanosleep.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef _LIBCPP_SUPPORT_IBM_NANOSLEEP_H -#define _LIBCPP_SUPPORT_IBM_NANOSLEEP_H +#ifndef _LIBCPP___SUPPORT_IBM_NANOSLEEP_H +#define _LIBCPP___SUPPORT_IBM_NANOSLEEP_H #include @@ -52,4 +52,4 @@ return 0; } -#endif // _LIBCPP_SUPPORT_IBM_NANOSLEEP_H +#endif // _LIBCPP___SUPPORT_IBM_NANOSLEEP_H diff --git a/libcxx/include/__support/ibm/xlocale.h b/libcxx/include/__support/ibm/xlocale.h --- a/libcxx/include/__support/ibm/xlocale.h +++ b/libcxx/include/__support/ibm/xlocale.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef _LIBCPP_SUPPORT_IBM_XLOCALE_H -#define _LIBCPP_SUPPORT_IBM_XLOCALE_H +#ifndef _LIBCPP___SUPPORT_IBM_XLOCALE_H +#define _LIBCPP___SUPPORT_IBM_XLOCALE_H #if defined(__MVS__) #include <__support/ibm/locale_mgmt_zos.h> @@ -126,4 +126,4 @@ #ifdef __cplusplus } #endif -#endif // _LIBCPP_SUPPORT_IBM_XLOCALE_H +#endif // _LIBCPP___SUPPORT_IBM_XLOCALE_H diff --git a/libcxx/include/__support/musl/xlocale.h b/libcxx/include/__support/musl/xlocale.h --- a/libcxx/include/__support/musl/xlocale.h +++ b/libcxx/include/__support/musl/xlocale.h @@ -14,8 +14,8 @@ // in Musl. //===----------------------------------------------------------------------===// -#ifndef _LIBCPP_SUPPORT_MUSL_XLOCALE_H -#define _LIBCPP_SUPPORT_MUSL_XLOCALE_H +#ifndef _LIBCPP___SUPPORT_MUSL_XLOCALE_H +#define _LIBCPP___SUPPORT_MUSL_XLOCALE_H #include #include @@ -53,4 +53,4 @@ } #endif -#endif // _LIBCPP_SUPPORT_MUSL_XLOCALE_H +#endif // _LIBCPP___SUPPORT_MUSL_XLOCALE_H diff --git a/libcxx/include/__support/newlib/xlocale.h b/libcxx/include/__support/newlib/xlocale.h --- a/libcxx/include/__support/newlib/xlocale.h +++ b/libcxx/include/__support/newlib/xlocale.h @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#ifndef _LIBCPP_SUPPORT_NEWLIB_XLOCALE_H -#define _LIBCPP_SUPPORT_NEWLIB_XLOCALE_H +#ifndef _LIBCPP___SUPPORT_NEWLIB_XLOCALE_H +#define _LIBCPP___SUPPORT_NEWLIB_XLOCALE_H #if defined(_NEWLIB_VERSION) diff --git a/libcxx/include/__support/openbsd/xlocale.h b/libcxx/include/__support/openbsd/xlocale.h --- a/libcxx/include/__support/openbsd/xlocale.h +++ b/libcxx/include/__support/openbsd/xlocale.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef _LIBCPP_SUPPORT_OPENBSD_XLOCALE_H -#define _LIBCPP_SUPPORT_OPENBSD_XLOCALE_H +#ifndef _LIBCPP___SUPPORT_OPENBSD_XLOCALE_H +#define _LIBCPP___SUPPORT_OPENBSD_XLOCALE_H #include <__support/xlocale/__strtonum_fallback.h> #include diff --git a/libcxx/include/__support/win32/locale_win32.h b/libcxx/include/__support/win32/locale_win32.h --- a/libcxx/include/__support/win32/locale_win32.h +++ b/libcxx/include/__support/win32/locale_win32.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef _LIBCPP_SUPPORT_WIN32_LOCALE_WIN32_H -#define _LIBCPP_SUPPORT_WIN32_LOCALE_WIN32_H +#ifndef _LIBCPP___SUPPORT_WIN32_LOCALE_WIN32_H +#define _LIBCPP___SUPPORT_WIN32_LOCALE_WIN32_H #include <__config> #include @@ -279,4 +279,4 @@ return ( __c == L' ' || __c == L'\t' ); } -#endif // _LIBCPP_SUPPORT_WIN32_LOCALE_WIN32_H +#endif // _LIBCPP___SUPPORT_WIN32_LOCALE_WIN32_H diff --git a/libcxx/include/__support/xlocale/__nop_locale_mgmt.h b/libcxx/include/__support/xlocale/__nop_locale_mgmt.h --- a/libcxx/include/__support/xlocale/__nop_locale_mgmt.h +++ b/libcxx/include/__support/xlocale/__nop_locale_mgmt.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef _LIBCPP_SUPPORT_XLOCALE_NOP_LOCALE_MGMT_H -#define _LIBCPP_SUPPORT_XLOCALE_NOP_LOCALE_MGMT_H +#ifndef _LIBCPP___SUPPORT_XLOCALE_NOP_LOCALE_MGMT_H +#define _LIBCPP___SUPPORT_XLOCALE_NOP_LOCALE_MGMT_H #include <__config> @@ -55,4 +55,4 @@ } // extern "C" #endif -#endif // _LIBCPP_SUPPORT_XLOCALE_NOP_LOCALE_MGMT_H +#endif // _LIBCPP___SUPPORT_XLOCALE_NOP_LOCALE_MGMT_H diff --git a/libcxx/include/__support/xlocale/__posix_l_fallback.h b/libcxx/include/__support/xlocale/__posix_l_fallback.h --- a/libcxx/include/__support/xlocale/__posix_l_fallback.h +++ b/libcxx/include/__support/xlocale/__posix_l_fallback.h @@ -12,8 +12,8 @@ // Android's bionic and Newlib). //===----------------------------------------------------------------------===// -#ifndef _LIBCPP_SUPPORT_XLOCALE_POSIX_L_FALLBACK_H -#define _LIBCPP_SUPPORT_XLOCALE_POSIX_L_FALLBACK_H +#ifndef _LIBCPP___SUPPORT_XLOCALE_POSIX_L_FALLBACK_H +#define _LIBCPP___SUPPORT_XLOCALE_POSIX_L_FALLBACK_H #include <__config> #include @@ -173,4 +173,4 @@ } #endif -#endif // _LIBCPP_SUPPORT_XLOCALE_POSIX_L_FALLBACK_H +#endif // _LIBCPP___SUPPORT_XLOCALE_POSIX_L_FALLBACK_H diff --git a/libcxx/include/__support/xlocale/__strtonum_fallback.h b/libcxx/include/__support/xlocale/__strtonum_fallback.h --- a/libcxx/include/__support/xlocale/__strtonum_fallback.h +++ b/libcxx/include/__support/xlocale/__strtonum_fallback.h @@ -12,8 +12,8 @@ // convert strings to some numeric type. //===----------------------------------------------------------------------===// -#ifndef _LIBCPP_SUPPORT_XLOCALE_STRTONUM_FALLBACK_H -#define _LIBCPP_SUPPORT_XLOCALE_STRTONUM_FALLBACK_H +#ifndef _LIBCPP___SUPPORT_XLOCALE_STRTONUM_FALLBACK_H +#define _LIBCPP___SUPPORT_XLOCALE_STRTONUM_FALLBACK_H #include <__config> #include @@ -72,4 +72,4 @@ } #endif -#endif // _LIBCPP_SUPPORT_XLOCALE_STRTONUM_FALLBACK_H +#endif // _LIBCPP___SUPPORT_XLOCALE_STRTONUM_FALLBACK_H diff --git a/libcxx/include/__thread/poll_with_backoff.h b/libcxx/include/__thread/poll_with_backoff.h --- a/libcxx/include/__thread/poll_with_backoff.h +++ b/libcxx/include/__thread/poll_with_backoff.h @@ -6,16 +6,14 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___THREAD_POLL_WITH_BACKOFF_H #define _LIBCPP___THREAD_POLL_WITH_BACKOFF_H #include <__availability> #include <__chrono/duration.h> #include <__chrono/high_resolution_clock.h> -#include <__chrono/steady_clock.h> -#include <__chrono/time_point.h> #include <__config> -#include <__filesystem/file_time_type.h> #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header diff --git a/libcxx/include/__thread/timed_backoff_policy.h b/libcxx/include/__thread/timed_backoff_policy.h --- a/libcxx/include/__thread/timed_backoff_policy.h +++ b/libcxx/include/__thread/timed_backoff_policy.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP___THREAD_TIMED_BACKOFF_POLICY_H #define _LIBCPP___THREAD_TIMED_BACKOFF_POLICY_H diff --git a/libcxx/include/__type_traits/is_unsigned.h b/libcxx/include/__type_traits/is_unsigned.h --- a/libcxx/include/__type_traits/is_unsigned.h +++ b/libcxx/include/__type_traits/is_unsigned.h @@ -20,8 +20,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD -// Before AppleClang 14, __is_unsigned returned true for enums with signed underlying type. -#if __has_builtin(__is_unsigned) && !(defined(_LIBCPP_APPLE_CLANG_VER) && _LIBCPP_APPLE_CLANG_VER < 1400) +#if __has_builtin(__is_unsigned) template struct _LIBCPP_TEMPLATE_VIS is_unsigned : _BoolConstant<__is_unsigned(_Tp)> { }; diff --git a/libcxx/include/charconv b/libcxx/include/charconv --- a/libcxx/include/charconv +++ b/libcxx/include/charconv @@ -250,7 +250,7 @@ int __i = digits; do { - if (!('0' <= *__p && *__p <= '9')) + if (*__p < '0' || *__p > '9') break; __cprod[--__i] = *__p++ - '0'; } while (__p != __ep && __i != 0); diff --git a/libcxx/include/experimental/simd b/libcxx/include/experimental/simd --- a/libcxx/include/experimental/simd +++ b/libcxx/include/experimental/simd @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP_EXPERIMENTAL_SIMD #define _LIBCPP_EXPERIMENTAL_SIMD diff --git a/libcxx/include/ext/__hash b/libcxx/include/ext/__hash --- a/libcxx/include/ext/__hash +++ b/libcxx/include/ext/__hash @@ -14,6 +14,7 @@ #include <__config> #include +#include #include namespace __gnu_cxx { diff --git a/libcxx/include/filesystem b/libcxx/include/filesystem --- a/libcxx/include/filesystem +++ b/libcxx/include/filesystem @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP_FILESYSTEM #define _LIBCPP_FILESYSTEM diff --git a/libcxx/include/fstream b/libcxx/include/fstream --- a/libcxx/include/fstream +++ b/libcxx/include/fstream @@ -753,9 +753,10 @@ } else { - _LIBCPP_ASSERT ( !(__extbufnext_ == NULL && (__extbufend_ != __extbufnext_)), "underflow moving from NULL" ); - if (__extbufend_ != __extbufnext_) + if (__extbufend_ != __extbufnext_) { + _LIBCPP_ASSERT(__extbufnext_ != nullptr, "underflow moving from NULL" ); _VSTD::memmove(__extbuf_, __extbufnext_, __extbufend_ - __extbufnext_); + } __extbufnext_ = __extbuf_ + (__extbufend_ - __extbufnext_); __extbufend_ = __extbuf_ + (__extbuf_ == __extbuf_min_ ? sizeof(__extbuf_min_) : __ebs_); size_t __nmemb = _VSTD::min(static_cast(__ibs_ - __unget_sz), diff --git a/libcxx/include/locale b/libcxx/include/locale --- a/libcxx/include/locale +++ b/libcxx/include/locale @@ -4013,9 +4013,10 @@ } else { - _LIBCPP_ASSERT(!(__extbufnext_ == NULL && (__extbufend_ != __extbufnext_)), "underflow moving from NULL" ); - if (__extbufend_ != __extbufnext_) + if (__extbufend_ != __extbufnext_) { + _LIBCPP_ASSERT(__extbufnext_ != NULL, "underflow moving from NULL" ); _VSTD::memmove(__extbuf_, __extbufnext_, __extbufend_ - __extbufnext_); + } __extbufnext_ = __extbuf_ + (__extbufend_ - __extbufnext_); __extbufend_ = __extbuf_ + (__extbuf_ == __extbuf_min_ ? sizeof(__extbuf_min_) : __ebs_); streamsize __nmemb = _VSTD::min(static_cast(this->egptr() - this->eback() - __unget_sz), diff --git a/libcxx/include/module.modulemap.in b/libcxx/include/module.modulemap.in --- a/libcxx/include/module.modulemap.in +++ b/libcxx/include/module.modulemap.in @@ -672,6 +672,7 @@ private header "__chrono/high_resolution_clock.h" export steady_clock export system_clock + export time_point } module literals { private header "__chrono/literals.h" } module month { private header "__chrono/month.h" } diff --git a/libcxx/include/stdbool.h b/libcxx/include/stdbool.h --- a/libcxx/include/stdbool.h +++ b/libcxx/include/stdbool.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP_STDBOOL_H #define _LIBCPP_STDBOOL_H diff --git a/libcxx/include/string.h b/libcxx/include/string.h --- a/libcxx/include/string.h +++ b/libcxx/include/string.h @@ -71,41 +71,41 @@ #if defined(__cplusplus) && !defined(_LIBCPP_STRING_H_HAS_CONST_OVERLOADS) && defined(_LIBCPP_PREFERRED_OVERLOAD) extern "C++" { -inline _LIBCPP_INLINE_VISIBILITY -char* __libcpp_strchr(const char* __s, int __c) {return (char*)strchr(__s, __c);} -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_PREFERRED_OVERLOAD -const char* strchr(const char* __s, int __c) {return __libcpp_strchr(__s, __c);} -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_PREFERRED_OVERLOAD - char* strchr( char* __s, int __c) {return __libcpp_strchr(__s, __c);} - -inline _LIBCPP_INLINE_VISIBILITY -char* __libcpp_strpbrk(const char* __s1, const char* __s2) {return (char*)strpbrk(__s1, __s2);} -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_PREFERRED_OVERLOAD -const char* strpbrk(const char* __s1, const char* __s2) {return __libcpp_strpbrk(__s1, __s2);} -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_PREFERRED_OVERLOAD - char* strpbrk( char* __s1, const char* __s2) {return __libcpp_strpbrk(__s1, __s2);} - -inline _LIBCPP_INLINE_VISIBILITY -char* __libcpp_strrchr(const char* __s, int __c) {return (char*)strrchr(__s, __c);} -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_PREFERRED_OVERLOAD -const char* strrchr(const char* __s, int __c) {return __libcpp_strrchr(__s, __c);} -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_PREFERRED_OVERLOAD - char* strrchr( char* __s, int __c) {return __libcpp_strrchr(__s, __c);} - -inline _LIBCPP_INLINE_VISIBILITY -void* __libcpp_memchr(const void* __s, int __c, size_t __n) {return (void*)memchr(__s, __c, __n);} -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_PREFERRED_OVERLOAD -const void* memchr(const void* __s, int __c, size_t __n) {return __libcpp_memchr(__s, __c, __n);} -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_PREFERRED_OVERLOAD - void* memchr( void* __s, int __c, size_t __n) {return __libcpp_memchr(__s, __c, __n);} - -inline _LIBCPP_INLINE_VISIBILITY -char* __libcpp_strstr(const char* __s1, const char* __s2) {return (char*)strstr(__s1, __s2);} -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_PREFERRED_OVERLOAD -const char* strstr(const char* __s1, const char* __s2) {return __libcpp_strstr(__s1, __s2);} -inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_PREFERRED_OVERLOAD - char* strstr( char* __s1, const char* __s2) {return __libcpp_strstr(__s1, __s2);} +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_PREFERRED_OVERLOAD const char* strchr(const char* __s, int __c) { + return __builtin_strchr(__s, __c); } +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_PREFERRED_OVERLOAD char* strchr(char* __s, int __c) { + return __builtin_strchr(__s, __c); +} + +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_PREFERRED_OVERLOAD const char* strpbrk(const char* __s1, const char* __s2) { + return __builtin_strpbrk(__s1, __s2); +} +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_PREFERRED_OVERLOAD char* strpbrk(char* __s1, const char* __s2) { + return __builtin_strpbrk(__s1, __s2); +} + +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_PREFERRED_OVERLOAD const char* strrchr(const char* __s, int __c) { + return __builtin_strrchr(__s, __c); +} +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_PREFERRED_OVERLOAD char* strrchr(char* __s, int __c) { + return __builtin_strrchr(__s, __c); +} + +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_PREFERRED_OVERLOAD const void* memchr(const void* __s, int __c, size_t __n) { + return __builtin_memchr(__s, __c, __n); +} +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_PREFERRED_OVERLOAD void* memchr(void* __s, int __c, size_t __n) { + return __builtin_memchr(__s, __c, __n); +} + +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_PREFERRED_OVERLOAD const char* strstr(const char* __s1, const char* __s2) { + return __builtin_strstr(__s1, __s2); +} +inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_PREFERRED_OVERLOAD char* strstr(char* __s1, const char* __s2) { + return __builtin_strstr(__s1, __s2); +} +} // extern "C++" #endif #endif // _LIBCPP_STRING_H diff --git a/libcxx/include/string_view b/libcxx/include/string_view --- a/libcxx/include/string_view +++ b/libcxx/include/string_view @@ -191,11 +191,11 @@ template <> struct hash; template <> struct hash; - constexpr basic_string_view operator "" sv( const char *str, size_t len ) noexcept; - constexpr basic_string_view operator "" sv( const wchar_t *str, size_t len ) noexcept; - constexpr basic_string_view operator "" sv( const char8_t *str, size_t len ) noexcept; // C++20 - constexpr basic_string_view operator "" sv( const char16_t *str, size_t len ) noexcept; - constexpr basic_string_view operator "" sv( const char32_t *str, size_t len ) noexcept; + constexpr basic_string_view operator "" sv(const char *str, size_t len) noexcept; + constexpr basic_string_view operator "" sv(const wchar_t *str, size_t len) noexcept; + constexpr basic_string_view operator "" sv(const char8_t *str, size_t len) noexcept; // C++20 + constexpr basic_string_view operator "" sv(const char16_t *str, size_t len) noexcept; + constexpr basic_string_view operator "" sv(const char32_t *str, size_t len) noexcept; } // namespace std @@ -259,18 +259,18 @@ class basic_string_view { public: // types - typedef _Traits traits_type; - typedef _CharT value_type; - typedef _CharT* pointer; - typedef const _CharT* const_pointer; - typedef _CharT& reference; - typedef const _CharT& const_reference; - typedef const_pointer const_iterator; // See [string.view.iterators] - typedef const_iterator iterator; - typedef _VSTD::reverse_iterator const_reverse_iterator; - typedef const_reverse_iterator reverse_iterator; - typedef size_t size_type; - typedef ptrdiff_t difference_type; + using traits_type = _Traits; + using value_type = _CharT; + using pointer = _CharT*; + using const_pointer = const _CharT*; + using reference = _CharT&; + using const_reference = const _CharT&; + using const_iterator = const_pointer; // See [string.view.iterators] + using iterator = const_iterator; + using const_reverse_iterator = _VSTD::reverse_iterator; + using reverse_iterator = const_reverse_iterator; + using size_type = size_t; + using difference_type = ptrdiff_t; static _LIBCPP_CONSTEXPR const size_type npos = -1; // size_type(-1); static_assert((!is_array::value), "Character type of basic_string_view must not be an array"); @@ -281,7 +281,7 @@ // [string.view.cons], construct/copy _LIBCPP_CONSTEXPR _LIBCPP_INLINE_VISIBILITY - basic_string_view() _NOEXCEPT : __data_ (nullptr), __size_(0) {} + basic_string_view() _NOEXCEPT : __data_(nullptr), __size_(0) {} _LIBCPP_INLINE_VISIBILITY basic_string_view(const basic_string_view&) _NOEXCEPT = default; @@ -450,10 +450,10 @@ _LIBCPP_CONSTEXPR_SINCE_CXX14 int compare(basic_string_view __sv) const _NOEXCEPT { - size_type __rlen = _VSTD::min( size(), __sv.size()); + size_type __rlen = _VSTD::min(size(), __sv.size()); int __retval = _Traits::compare(data(), __sv.data(), __rlen); - if ( __retval == 0 ) // first __rlen chars matched - __retval = size() == __sv.size() ? 0 : ( size() < __sv.size() ? -1 : 1 ); + if (__retval == 0) // first __rlen chars matched + __retval = size() == __sv.size() ? 0 : (size() < __sv.size() ? -1 : 1); return __retval; } @@ -748,7 +748,7 @@ bool operator==(basic_string_view<_CharT, _Traits> __lhs, basic_string_view<_CharT, _Traits> __rhs) _NOEXCEPT { - if ( __lhs.size() != __rhs.size()) return false; + if (__lhs.size() != __rhs.size()) return false; return __lhs.compare(__rhs) == 0; } @@ -759,7 +759,7 @@ bool operator==(basic_string_view<_CharT, _Traits> __lhs, __type_identity_t > __rhs) _NOEXCEPT { - if ( __lhs.size() != __rhs.size()) return false; + if (__lhs.size() != __rhs.size()) return false; return __lhs.compare(__rhs) == 0; } @@ -770,7 +770,7 @@ bool operator==(__type_identity_t > __lhs, basic_string_view<_CharT, _Traits> __rhs) _NOEXCEPT { - if ( __lhs.size() != __rhs.size()) return false; + if (__lhs.size() != __rhs.size()) return false; return __lhs.compare(__rhs) == 0; } #endif // _LIBCPP_STD_VER > 17 @@ -814,7 +814,7 @@ _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_INLINE_VISIBILITY bool operator!=(basic_string_view<_CharT, _Traits> __lhs, basic_string_view<_CharT, _Traits> __rhs) _NOEXCEPT { - if ( __lhs.size() != __rhs.size()) + if (__lhs.size() != __rhs.size()) return true; return __lhs.compare(__rhs) != 0; } @@ -824,7 +824,7 @@ bool operator!=(basic_string_view<_CharT, _Traits> __lhs, __type_identity_t > __rhs) _NOEXCEPT { - if ( __lhs.size() != __rhs.size()) + if (__lhs.size() != __rhs.size()) return true; return __lhs.compare(__rhs) != 0; } @@ -834,7 +834,7 @@ bool operator!=(__type_identity_t > __lhs, basic_string_view<_CharT, _Traits> __rhs) _NOEXCEPT { - if ( __lhs.size() != __rhs.size()) + if (__lhs.size() != __rhs.size()) return true; return __lhs.compare(__rhs) != 0; } diff --git a/libcxx/src/include/apple_availability.h b/libcxx/src/include/apple_availability.h --- a/libcxx/src/include/apple_availability.h +++ b/libcxx/src/include/apple_availability.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef _LIBCPP_SRC_INCLUDE_APPLE_AVAILABILITY_H #define _LIBCPP_SRC_INCLUDE_APPLE_AVAILABILITY_H diff --git a/libcxx/test/libcxx/atomics/bit-int.verify.cpp b/libcxx/test/libcxx/atomics/bit-int.verify.cpp --- a/libcxx/test/libcxx/atomics/bit-int.verify.cpp +++ b/libcxx/test/libcxx/atomics/bit-int.verify.cpp @@ -12,7 +12,7 @@ // disable them for now until their behavior can be designed better later. // See https://reviews.llvm.org/D84049 for details. -// UNSUPPORTED: apple-clang-13, apple-clang-14 +// UNSUPPORTED: apple-clang-14 // UNSUPPORTED: c++03 diff --git a/libcxx/test/libcxx/experimental/fexperimental-library.compile.pass.cpp b/libcxx/test/libcxx/experimental/fexperimental-library.compile.pass.cpp --- a/libcxx/test/libcxx/experimental/fexperimental-library.compile.pass.cpp +++ b/libcxx/test/libcxx/experimental/fexperimental-library.compile.pass.cpp @@ -16,7 +16,7 @@ // UNSUPPORTED: clang-14 // AppleClang does not support the -fexperimental-library flag yet -// UNSUPPORTED: apple-clang-13, apple-clang-14.0 +// UNSUPPORTED: apple-clang-14.0 // Clang on AIX currently pretends that it is Clang 15, even though it is not (as of writing // this, LLVM 15 hasn't even been branched yet). diff --git a/libcxx/test/libcxx/strings/char.traits/char.traits.specializations/arbitrary_char_type.deprecated.verify.cpp b/libcxx/test/libcxx/strings/char.traits/char.traits.specializations/arbitrary_char_type.deprecated.verify.cpp new file mode 100644 --- /dev/null +++ b/libcxx/test/libcxx/strings/char.traits/char.traits.specializations/arbitrary_char_type.deprecated.verify.cpp @@ -0,0 +1,21 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// template<> struct char_traits for arbitrary T + +// Make sure we issue deprecation warnings. + +#include + +void f() { + std::char_traits t1; (void)t1; // expected-warning{{'char_traits' is deprecated}} + std::char_traits t2; (void)t2; // expected-warning{{'char_traits' is deprecated}} + std::char_traits t3; (void)t3; // expected-warning{{'char_traits' is deprecated}} +} diff --git a/libcxx/test/libcxx/strings/char.traits/char.traits.specializations/arbitrary_char_type.pass.cpp b/libcxx/test/libcxx/strings/char.traits/char.traits.specializations/arbitrary_char_type.pass.cpp new file mode 100644 --- /dev/null +++ b/libcxx/test/libcxx/strings/char.traits/char.traits.specializations/arbitrary_char_type.pass.cpp @@ -0,0 +1,146 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// + +// template<> struct char_traits for arbitrary T + +// Non-standard but provided temporarily for users to migrate. + +// ADDITIONAL_COMPILE_FLAGS: -Wno-deprecated + +#include +#include +#include + +#include "test_macros.h" + +template +TEST_CONSTEXPR_CXX20 bool test() { + static_assert(std::is_same::char_type, Char>::value, ""); + static_assert(std::is_same::int_type, int>::value, ""); + static_assert(std::is_same::off_type, std::streamoff>::value, ""); + static_assert(std::is_same::pos_type, std::streampos>::value, ""); + static_assert(std::is_same::state_type, std::mbstate_t>::value, ""); + + assert(std::char_traits::to_int_type(Char('a')) == Char('a')); + assert(std::char_traits::to_int_type(Char('A')) == Char('A')); + assert(std::char_traits::to_int_type(0) == 0); + + assert(std::char_traits::to_char_type(Char('a')) == Char('a')); + assert(std::char_traits::to_char_type(Char('A')) == Char('A')); + assert(std::char_traits::to_char_type(0) == 0); + + assert(std::char_traits::eof() == EOF); + + assert(std::char_traits::not_eof(Char('a')) == Char('a')); + assert(std::char_traits::not_eof(Char('A')) == Char('A')); + assert(std::char_traits::not_eof(0) == 0); + assert(std::char_traits::not_eof(std::char_traits::eof()) != + std::char_traits::eof()); + + assert(std::char_traits::lt(Char('\0'), Char('A')) == (Char('\0') < Char('A'))); + assert(std::char_traits::lt(Char('A'), Char('\0')) == (Char('A') < Char('\0'))); + assert(std::char_traits::lt(Char('a'), Char('a')) == (Char('a') < Char('a'))); + assert(std::char_traits::lt(Char('A'), Char('a')) == (Char('A') < Char('a'))); + assert(std::char_traits::lt(Char('a'), Char('A')) == (Char('a') < Char('A'))); + + assert( std::char_traits::eq(Char('a'), Char('a'))); + assert(!std::char_traits::eq(Char('a'), Char('A'))); + + assert( std::char_traits::eq_int_type(Char('a'), Char('a'))); + assert(!std::char_traits::eq_int_type(Char('a'), Char('A'))); + assert(!std::char_traits::eq_int_type(std::char_traits::eof(), Char('A'))); + assert( std::char_traits::eq_int_type(std::char_traits::eof(), std::char_traits::eof())); + + { + Char s1[] = {1, 2, 3, 0}; + Char s2[] = {0}; + assert(std::char_traits::length(s1) == 3); + assert(std::char_traits::length(s2) == 0); + } + + { + Char s1[] = {1, 2, 3}; + assert(std::char_traits::find(s1, 3, Char(1)) == s1); + assert(std::char_traits::find(s1, 3, Char(2)) == s1+1); + assert(std::char_traits::find(s1, 3, Char(3)) == s1+2); + assert(std::char_traits::find(s1, 3, Char(4)) == 0); + assert(std::char_traits::find(s1, 3, Char(0)) == 0); + assert(std::char_traits::find(NULL, 0, Char(0)) == 0); + } + + { + Char s1[] = {1, 2, 3}; + Char s2[3] = {0}; + assert(std::char_traits::copy(s2, s1, 3) == s2); + assert(s2[0] == Char(1)); + assert(s2[1] == Char(2)); + assert(s2[2] == Char(3)); + assert(std::char_traits::copy(NULL, s1, 0) == NULL); + assert(std::char_traits::copy(s1, NULL, 0) == s1); + } + + { + Char s1[] = {1, 2, 3}; + assert(std::char_traits::move(s1, s1+1, 2) == s1); + assert(s1[0] == Char(2)); + assert(s1[1] == Char(3)); + assert(s1[2] == Char(3)); + s1[2] = Char(0); + assert(std::char_traits::move(s1+1, s1, 2) == s1+1); + assert(s1[0] == Char(2)); + assert(s1[1] == Char(2)); + assert(s1[2] == Char(3)); + assert(std::char_traits::move(NULL, s1, 0) == NULL); + assert(std::char_traits::move(s1, NULL, 0) == s1); + } + + { + Char s1[] = {0}; + assert(std::char_traits::compare(s1, s1, 0) == 0); + assert(std::char_traits::compare(NULL, NULL, 0) == 0); + + Char s2[] = {1, 0}; + Char s3[] = {2, 0}; + assert(std::char_traits::compare(s2, s2, 1) == 0); + assert(std::char_traits::compare(s2, s3, 1) < 0); + assert(std::char_traits::compare(s3, s2, 1) > 0); + } + + { + Char s2[3] = {0}; + assert(std::char_traits::assign(s2, 3, Char(5)) == s2); + assert(s2[0] == Char(5)); + assert(s2[1] == Char(5)); + assert(s2[2] == Char(5)); + assert(std::char_traits::assign(NULL, 0, Char(5)) == NULL); + } + + { + Char c = Char('\0'); + std::char_traits::assign(c, Char('a')); + assert(c == Char('a')); + } + + return true; +} + +int main(int, char**) { + test(); + test(); + test(); + +#if TEST_STD_VER > 17 + static_assert(test()); + static_assert(test()); + static_assert(test()); +#endif + + return 0; +} diff --git a/libcxx/test/libcxx/strings/char.traits/char.traits.specializations/signed_unsigned_char.deprecated.verify.cpp b/libcxx/test/libcxx/strings/char.traits/char.traits.specializations/signed_unsigned_char.deprecated.verify.cpp deleted file mode 100644 --- a/libcxx/test/libcxx/strings/char.traits/char.traits.specializations/signed_unsigned_char.deprecated.verify.cpp +++ /dev/null @@ -1,24 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -// - -// template<> struct char_traits -// template<> struct char_traits - -// Make sure we issue deprecation warnings. - -#include - -void f() { - std::char_traits uc; // expected-warning{{'char_traits' is deprecated}} - std::char_traits sc; // expected-warning{{'char_traits' is deprecated}} - - (void)uc; - (void)sc; -} diff --git a/libcxx/test/libcxx/strings/char.traits/char.traits.specializations/signed_unsigned_char.pass.cpp b/libcxx/test/libcxx/strings/char.traits/char.traits.specializations/signed_unsigned_char.pass.cpp deleted file mode 100644 --- a/libcxx/test/libcxx/strings/char.traits/char.traits.specializations/signed_unsigned_char.pass.cpp +++ /dev/null @@ -1,145 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -// - -// template<> struct char_traits -// template<> struct char_traits - -// Non-standard but provided temporarily for users to migrate. - -// ADDITIONAL_COMPILE_FLAGS: -Wno-deprecated - -#include -#include -#include - -#include "test_macros.h" - -template -TEST_CONSTEXPR_CXX20 bool test() { - static_assert(std::is_same::char_type, Char>::value, ""); - static_assert(std::is_same::int_type, int>::value, ""); - static_assert(std::is_same::off_type, std::streamoff>::value, ""); - static_assert(std::is_same::pos_type, std::streampos>::value, ""); - static_assert(std::is_same::state_type, std::mbstate_t>::value, ""); - - assert(std::char_traits::to_int_type(Char('a')) == Char('a')); - assert(std::char_traits::to_int_type(Char('A')) == Char('A')); - assert(std::char_traits::to_int_type(0) == 0); - - assert(std::char_traits::to_char_type(Char('a')) == Char('a')); - assert(std::char_traits::to_char_type(Char('A')) == Char('A')); - assert(std::char_traits::to_char_type(0) == 0); - - assert(std::char_traits::eof() == EOF); - - assert(std::char_traits::not_eof(Char('a')) == Char('a')); - assert(std::char_traits::not_eof(Char('A')) == Char('A')); - assert(std::char_traits::not_eof(0) == 0); - assert(std::char_traits::not_eof(std::char_traits::eof()) != - std::char_traits::eof()); - - assert(std::char_traits::lt(Char('\0'), Char('A')) == (Char('\0') < Char('A'))); - assert(std::char_traits::lt(Char('A'), Char('\0')) == (Char('A') < Char('\0'))); - assert(std::char_traits::lt(Char('a'), Char('a')) == (Char('a') < Char('a'))); - assert(std::char_traits::lt(Char('A'), Char('a')) == (Char('A') < Char('a'))); - assert(std::char_traits::lt(Char('a'), Char('A')) == (Char('a') < Char('A'))); - - assert( std::char_traits::eq(Char('a'), Char('a'))); - assert(!std::char_traits::eq(Char('a'), Char('A'))); - - assert( std::char_traits::eq_int_type(Char('a'), Char('a'))); - assert(!std::char_traits::eq_int_type(Char('a'), Char('A'))); - assert(!std::char_traits::eq_int_type(std::char_traits::eof(), Char('A'))); - assert( std::char_traits::eq_int_type(std::char_traits::eof(), std::char_traits::eof())); - - { - Char s1[] = {1, 2, 3, 0}; - Char s2[] = {0}; - assert(std::char_traits::length(s1) == 3); - assert(std::char_traits::length(s2) == 0); - } - - { - Char s1[] = {1, 2, 3}; - assert(std::char_traits::find(s1, 3, Char(1)) == s1); - assert(std::char_traits::find(s1, 3, Char(2)) == s1+1); - assert(std::char_traits::find(s1, 3, Char(3)) == s1+2); - assert(std::char_traits::find(s1, 3, Char(4)) == 0); - assert(std::char_traits::find(s1, 3, Char(0)) == 0); - assert(std::char_traits::find(NULL, 0, Char(0)) == 0); - } - - { - Char s1[] = {1, 2, 3}; - Char s2[3] = {0}; - assert(std::char_traits::copy(s2, s1, 3) == s2); - assert(s2[0] == Char(1)); - assert(s2[1] == Char(2)); - assert(s2[2] == Char(3)); - assert(std::char_traits::copy(NULL, s1, 0) == NULL); - assert(std::char_traits::copy(s1, NULL, 0) == s1); - } - - { - Char s1[] = {1, 2, 3}; - assert(std::char_traits::move(s1, s1+1, 2) == s1); - assert(s1[0] == Char(2)); - assert(s1[1] == Char(3)); - assert(s1[2] == Char(3)); - s1[2] = Char(0); - assert(std::char_traits::move(s1+1, s1, 2) == s1+1); - assert(s1[0] == Char(2)); - assert(s1[1] == Char(2)); - assert(s1[2] == Char(3)); - assert(std::char_traits::move(NULL, s1, 0) == NULL); - assert(std::char_traits::move(s1, NULL, 0) == s1); - } - - { - Char s1[] = {0}; - assert(std::char_traits::compare(s1, s1, 0) == 0); - assert(std::char_traits::compare(NULL, NULL, 0) == 0); - - Char s2[] = {1, 0}; - Char s3[] = {2, 0}; - assert(std::char_traits::compare(s2, s2, 1) == 0); - assert(std::char_traits::compare(s2, s3, 1) < 0); - assert(std::char_traits::compare(s3, s2, 1) > 0); - } - - { - Char s2[3] = {0}; - assert(std::char_traits::assign(s2, 3, Char(5)) == s2); - assert(s2[0] == Char(5)); - assert(s2[1] == Char(5)); - assert(s2[2] == Char(5)); - assert(std::char_traits::assign(NULL, 0, Char(5)) == NULL); - } - - { - Char c = Char('\0'); - std::char_traits::assign(c, Char('a')); - assert(c == Char('a')); - } - - return true; -} - -int main(int, char**) { - test(); - test(); - -#if TEST_STD_VER > 17 - static_assert(test()); - static_assert(test()); -#endif - - return 0; -} diff --git a/libcxx/test/libcxx/transitive_includes.sh.cpp b/libcxx/test/libcxx/transitive_includes.sh.cpp --- a/libcxx/test/libcxx/transitive_includes.sh.cpp +++ b/libcxx/test/libcxx/transitive_includes.sh.cpp @@ -27,9 +27,6 @@ // This test uses --trace-includes, which is not supported by GCC. // UNSUPPORTED: gcc -// This test uses -fshow-skipped-includes, which isn't supported on older Clangs -// UNSUPPORTED: apple-clang-13 - // This test doesn't work on AIX, but it should. Needs investigation. // XFAIL: buildhost=aix diff --git a/libcxx/test/std/algorithms/alg.sorting/alg.clamp/ranges.clamp.pass.cpp b/libcxx/test/std/algorithms/alg.sorting/alg.clamp/ranges.clamp.pass.cpp --- a/libcxx/test/std/algorithms/alg.sorting/alg.clamp/ranges.clamp.pass.cpp +++ b/libcxx/test/std/algorithms/alg.sorting/alg.clamp/ranges.clamp.pass.cpp @@ -10,9 +10,6 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 -// Older Clangs don't properly deduce decltype(auto) with a concept constraint -// XFAIL: apple-clang-13.0 - // template> Comp = ranges::less> // constexpr const T& diff --git a/libcxx/test/std/concepts/concepts.lang/concepts.arithmetic/arithmetic.h b/libcxx/test/std/concepts/concepts.lang/concepts.arithmetic/arithmetic.h --- a/libcxx/test/std/concepts/concepts.lang/concepts.arithmetic/arithmetic.h +++ b/libcxx/test/std/concepts/concepts.lang/concepts.arithmetic/arithmetic.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef LIBCXX_TEST_CONCEPTS_LANG_CONCEPTS_ARITHMETIC_H_ #define LIBCXX_TEST_CONCEPTS_LANG_CONCEPTS_ARITHMETIC_H_ diff --git a/libcxx/test/std/containers/check_consecutive.h b/libcxx/test/std/containers/check_consecutive.h --- a/libcxx/test/std/containers/check_consecutive.h +++ b/libcxx/test/std/containers/check_consecutive.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef CHECK_CONSECUTIVE_H #define CHECK_CONSECUTIVE_H diff --git a/libcxx/test/std/containers/map_allocator_requirement_test_templates.h b/libcxx/test/std/containers/map_allocator_requirement_test_templates.h --- a/libcxx/test/std/containers/map_allocator_requirement_test_templates.h +++ b/libcxx/test/std/containers/map_allocator_requirement_test_templates.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef MAP_ALLOCATOR_REQUIREMENT_TEST_TEMPLATES_H #define MAP_ALLOCATOR_REQUIREMENT_TEST_TEMPLATES_H diff --git a/libcxx/test/std/containers/set_allocator_requirement_test_templates.h b/libcxx/test/std/containers/set_allocator_requirement_test_templates.h --- a/libcxx/test/std/containers/set_allocator_requirement_test_templates.h +++ b/libcxx/test/std/containers/set_allocator_requirement_test_templates.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef SET_ALLOCATOR_REQUIREMENT_TEST_TEMPLATES_H #define SET_ALLOCATOR_REQUIREMENT_TEST_TEMPLATES_H diff --git a/libcxx/test/std/depr/depr.c.headers/string_h.pass.cpp b/libcxx/test/std/depr/depr.c.headers/string_h.pass.cpp --- a/libcxx/test/std/depr/depr.c.headers/string_h.pass.cpp +++ b/libcxx/test/std/depr/depr.c.headers/string_h.pass.cpp @@ -9,6 +9,7 @@ // #include +#include #include #include "test_macros.h" @@ -19,38 +20,119 @@ int main(int, char**) { - size_t s = 0; - void* vp = 0; - const void* vpc = 0; - char* cp = 0; - const char* cpc = 0; - ASSERT_SAME_TYPE(void*, decltype(memcpy(vp, vpc, s))); - ASSERT_SAME_TYPE(void*, decltype(memmove(vp, vpc, s))); - ASSERT_SAME_TYPE(char*, decltype(strcpy(cp, cpc))); - ASSERT_SAME_TYPE(char*, decltype(strncpy(cp, cpc, s))); - ASSERT_SAME_TYPE(char*, decltype(strcat(cp, cpc))); - ASSERT_SAME_TYPE(char*, decltype(strncat(cp, cpc, s))); - ASSERT_SAME_TYPE(int, decltype(memcmp(vpc, vpc, s))); - ASSERT_SAME_TYPE(int, decltype(strcmp(cpc, cpc))); - ASSERT_SAME_TYPE(int, decltype(strncmp(cpc, cpc, s))); - ASSERT_SAME_TYPE(int, decltype(strcoll(cpc, cpc))); - ASSERT_SAME_TYPE(size_t, decltype(strxfrm(cp, cpc, s))); - ASSERT_SAME_TYPE(void*, decltype(memchr(vp, 0, s))); - ASSERT_SAME_TYPE(const void*, decltype(memchr(vpc, 0, s))); - ASSERT_SAME_TYPE(char*, decltype(strchr(cp, 0))); - ASSERT_SAME_TYPE(const char*, decltype(strchr(cpc, 0))); - ASSERT_SAME_TYPE(size_t, decltype(strcspn(cpc, cpc))); - ASSERT_SAME_TYPE(char*, decltype(strpbrk(cp, cpc))); - ASSERT_SAME_TYPE(const char*, decltype(strpbrk(cpc, cpc))); - ASSERT_SAME_TYPE(char*, decltype(strrchr(cp, 0))); - ASSERT_SAME_TYPE(const char*, decltype(strrchr(cpc, 0))); - ASSERT_SAME_TYPE(size_t, decltype(strspn(cpc, cpc))); - ASSERT_SAME_TYPE(char*, decltype(strstr(cp, cpc))); - ASSERT_SAME_TYPE(const char*, decltype(strstr(cpc, cpc))); - ASSERT_SAME_TYPE(char*, decltype(strtok(cp, cpc))); - ASSERT_SAME_TYPE(void*, decltype(memset(vp, 0, s))); - ASSERT_SAME_TYPE(char*, decltype(strerror(0))); - ASSERT_SAME_TYPE(size_t, decltype(strlen(cpc))); + // Functions we get directly from the C library (just check the signature) + { + size_t s = 0; + void* vp = 0; + const void* vpc = 0; + char* cp = 0; + const char* cpc = 0; + ASSERT_SAME_TYPE(void*, decltype(memcpy(vp, vpc, s))); + ASSERT_SAME_TYPE(void*, decltype(memmove(vp, vpc, s))); + ASSERT_SAME_TYPE(char*, decltype(strcpy(cp, cpc))); + ASSERT_SAME_TYPE(char*, decltype(strncpy(cp, cpc, s))); + ASSERT_SAME_TYPE(char*, decltype(strcat(cp, cpc))); + ASSERT_SAME_TYPE(char*, decltype(strncat(cp, cpc, s))); + ASSERT_SAME_TYPE(int, decltype(memcmp(vpc, vpc, s))); + ASSERT_SAME_TYPE(int, decltype(strcmp(cpc, cpc))); + ASSERT_SAME_TYPE(int, decltype(strncmp(cpc, cpc, s))); + ASSERT_SAME_TYPE(int, decltype(strcoll(cpc, cpc))); + ASSERT_SAME_TYPE(size_t, decltype(strxfrm(cp, cpc, s))); + ASSERT_SAME_TYPE(size_t, decltype(strcspn(cpc, cpc))); + ASSERT_SAME_TYPE(size_t, decltype(strspn(cpc, cpc))); + ASSERT_SAME_TYPE(char*, decltype(strtok(cp, cpc))); + ASSERT_SAME_TYPE(void*, decltype(memset(vp, 0, s))); + ASSERT_SAME_TYPE(char*, decltype(strerror(0))); + ASSERT_SAME_TYPE(size_t, decltype(strlen(cpc))); + } + + // Functions we (may) reimplement + { + // const char* strchr(const char*, int) + char storage[] = "hello world"; + const char* s = storage; + ASSERT_SAME_TYPE(const char*, decltype(strchr(s, 'l'))); + const char* res = strchr(s, 'l'); + assert(res == &s[2]); + } + { + // char* strchr(char*, int) + char storage[] = "hello world"; + char* s = storage; + ASSERT_SAME_TYPE(char*, decltype(strchr(s, 'l'))); + char* res = strchr(s, 'l'); + assert(res == &s[2]); + } + + { + // const char* strpbrk(const char*, const char*) + char storage[] = "hello world"; + const char* s = storage; + ASSERT_SAME_TYPE(const char*, decltype(strpbrk(s, "el"))); + const char* res = strpbrk(s, "el"); + assert(res == &s[1]); + } + { + // char* strpbrk(char*, const char*) + char storage[] = "hello world"; + char* s = storage; + ASSERT_SAME_TYPE(char*, decltype(strpbrk(s, "el"))); + char* res = strpbrk(s, "el"); + assert(res == &s[1]); + } + + { + // const char* strrchr(const char*, int) + char storage[] = "hello world"; + const char* s = storage; + ASSERT_SAME_TYPE(const char*, decltype(strrchr(s, 'l'))); + const char* res = strrchr(s, 'l'); + assert(res == &s[9]); + } + { + // char* strrchr(char*, int) + char storage[] = "hello world"; + char* s = storage; + ASSERT_SAME_TYPE(char*, decltype(strrchr(s, 'l'))); + char* res = strrchr(s, 'l'); + assert(res == &s[9]); + } + + { + // const void* memchr(const void*, int, size_t) + char storage[] = "hello world"; + size_t count = 11; + const void* s = storage; + ASSERT_SAME_TYPE(const void*, decltype(memchr(s, 'l', count))); + const void* res = memchr(s, 'l', count); + assert(res == &storage[2]); + } + { + // void* memchr(void*, int, size_t) + char storage[] = "hello world"; + size_t count = 11; + void* s = storage; + ASSERT_SAME_TYPE(void*, decltype(memchr(s, 'l', count))); + void* res = memchr(s, 'l', count); + assert(res == &storage[2]); + } + + { + // const char* strstr(const char*, const char*) + char storage[] = "hello world"; + const char* s = storage; + ASSERT_SAME_TYPE(const char*, decltype(strstr(s, "wor"))); + const char* res = strstr(s, "wor"); + assert(res == &storage[6]); + } + { + // char* strstr(char*, const char*) + char storage[] = "hello world"; + char* s = storage; + ASSERT_SAME_TYPE(char*, decltype(strstr(s, "wor"))); + char* res = strstr(s, "wor"); + assert(res == &storage[6]); + } return 0; } diff --git a/libcxx/test/std/input.output/iostream.forward/iosfwd.pass.cpp b/libcxx/test/std/input.output/iostream.forward/iosfwd.pass.cpp --- a/libcxx/test/std/input.output/iostream.forward/iosfwd.pass.cpp +++ b/libcxx/test/std/input.output/iostream.forward/iosfwd.pass.cpp @@ -28,7 +28,6 @@ #ifndef TEST_HAS_NO_WIDE_CHARACTERS test* >(); #endif - test*>(); test* >(); #ifndef TEST_HAS_NO_WIDE_CHARACTERS diff --git a/libcxx/test/std/iterators/iterator.requirements/iterator.concepts/incrementable.h b/libcxx/test/std/iterators/iterator.requirements/iterator.concepts/incrementable.h --- a/libcxx/test/std/iterators/iterator.requirements/iterator.concepts/incrementable.h +++ b/libcxx/test/std/iterators/iterator.requirements/iterator.concepts/incrementable.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef LIBCPP_TEST_STD_ITERATORS_ITERATOR_REQUIREMENTS_ITERATOR_CONCEPTS_INCREMENTABLE_H #define LIBCPP_TEST_STD_ITERATORS_ITERATOR_REQUIREMENTS_ITERATOR_CONCEPTS_INCREMENTABLE_H diff --git a/libcxx/test/std/iterators/iterator.requirements/iterator.cust/unqualified_lookup_wrapper.h b/libcxx/test/std/iterators/iterator.requirements/iterator.cust/unqualified_lookup_wrapper.h --- a/libcxx/test/std/iterators/iterator.requirements/iterator.cust/unqualified_lookup_wrapper.h +++ b/libcxx/test/std/iterators/iterator.requirements/iterator.cust/unqualified_lookup_wrapper.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef LIBCPP_TEST_STD_ITERATOR_UNQUALIFIED_LOOKUP_WRAPPER #define LIBCPP_TEST_STD_ITERATOR_UNQUALIFIED_LOOKUP_WRAPPER diff --git a/libcxx/test/std/ranges/range.adaptors/range.filter/pred.pass.cpp b/libcxx/test/std/ranges/range.adaptors/range.filter/pred.pass.cpp --- a/libcxx/test/std/ranges/range.adaptors/range.filter/pred.pass.cpp +++ b/libcxx/test/std/ranges/range.adaptors/range.filter/pred.pass.cpp @@ -8,9 +8,6 @@ // UNSUPPORTED: c++03, c++11, c++14, c++17 -// Older Clangs don't properly deduce decltype(auto) with a concept constraint -// XFAIL: apple-clang-13.0 - // constexpr Pred const& pred() const; #include diff --git a/libcxx/test/std/strings/basic.string.hash/enabled_hashes.pass.cpp b/libcxx/test/std/strings/basic.string.hash/enabled_hashes.pass.cpp --- a/libcxx/test/std/strings/basic.string.hash/enabled_hashes.pass.cpp +++ b/libcxx/test/std/strings/basic.string.hash/enabled_hashes.pass.cpp @@ -24,6 +24,32 @@ char c; }; +template <> +struct std::char_traits { + using char_type = MyChar; + using int_type = std::char_traits::int_type; + using off_type = std::char_traits::off_type; + using pos_type = std::char_traits::pos_type; + using state_type = std::char_traits::state_type; + + static void assign(char_type&, const char_type&); + static bool eq(char_type, char_type); + static bool lt(char_type, char_type); + + static int compare(const char_type*, const char_type*, size_t); + static size_t length(const char_type*); + static const char_type* find(const char_type*, size_t, const char_type&); + static char_type* move(char_type*, const char_type*, size_t); + static char_type* copy(char_type*, const char_type*, size_t); + static char_type* assign(char_type*, size_t, char_type); + + static int_type not_eof(int_type); + static char_type to_char_type(int_type); + static int_type to_int_type(char_type); + static bool eq_int_type(int_type, int_type); + static int_type eof(); +}; + int main(int, char**) { test_library_hash_specializations_available(); { diff --git a/libcxx/test/std/strings/c.strings/cstring.pass.cpp b/libcxx/test/std/strings/c.strings/cstring.pass.cpp --- a/libcxx/test/std/strings/c.strings/cstring.pass.cpp +++ b/libcxx/test/std/strings/c.strings/cstring.pass.cpp @@ -9,6 +9,7 @@ // #include +#include #include #include "test_macros.h" @@ -19,39 +20,119 @@ int main(int, char**) { - std::size_t s = 0; - void* vp = 0; - const void* vpc = 0; - char* cp = 0; - const char* cpc = 0; - - ASSERT_SAME_TYPE(void*, decltype(std::memcpy(vp, vpc, s))); - ASSERT_SAME_TYPE(void*, decltype(std::memmove(vp, vpc, s))); - ASSERT_SAME_TYPE(char*, decltype(std::strcpy(cp, cpc))); - ASSERT_SAME_TYPE(char*, decltype(std::strncpy(cp, cpc, s))); - ASSERT_SAME_TYPE(char*, decltype(std::strcat(cp, cpc))); - ASSERT_SAME_TYPE(char*, decltype(std::strncat(cp, cpc, s))); - ASSERT_SAME_TYPE(int, decltype(std::memcmp(vpc, vpc, s))); - ASSERT_SAME_TYPE(int, decltype(std::strcmp(cpc, cpc))); - ASSERT_SAME_TYPE(int, decltype(std::strncmp(cpc, cpc, s))); - ASSERT_SAME_TYPE(int, decltype(std::strcoll(cpc, cpc))); - ASSERT_SAME_TYPE(std::size_t, decltype(std::strxfrm(cp, cpc, s))); - ASSERT_SAME_TYPE(void*, decltype(std::memchr(vp, 0, s))); - ASSERT_SAME_TYPE(const void*, decltype(std::memchr(vpc, 0, s))); - ASSERT_SAME_TYPE(char*, decltype(std::strchr(cp, 0))); - ASSERT_SAME_TYPE(const char*, decltype(std::strchr(cpc, 0))); - ASSERT_SAME_TYPE(std::size_t, decltype(std::strcspn(cpc, cpc))); - ASSERT_SAME_TYPE(char*, decltype(std::strpbrk(cp, cpc))); - ASSERT_SAME_TYPE(const char*, decltype(std::strpbrk(cpc, cpc))); - ASSERT_SAME_TYPE(char*, decltype(std::strrchr(cp, 0))); - ASSERT_SAME_TYPE(const char*, decltype(std::strrchr(cpc, 0))); - ASSERT_SAME_TYPE(std::size_t, decltype(std::strspn(cpc, cpc))); - ASSERT_SAME_TYPE(char*, decltype(std::strstr(cp, cpc))); - ASSERT_SAME_TYPE(const char*, decltype(std::strstr(cpc, cpc))); - ASSERT_SAME_TYPE(char*, decltype(std::strtok(cp, cpc))); - ASSERT_SAME_TYPE(void*, decltype(std::memset(vp, 0, s))); - ASSERT_SAME_TYPE(char*, decltype(std::strerror(0))); - ASSERT_SAME_TYPE(std::size_t, decltype(std::strlen(cpc))); + // Functions we get directly from the C library (just check the signature) + { + std::size_t s = 0; + void* vp = 0; + const void* vpc = 0; + char* cp = 0; + const char* cpc = 0; + ASSERT_SAME_TYPE(void*, decltype(std::memcpy(vp, vpc, s))); + ASSERT_SAME_TYPE(void*, decltype(std::memmove(vp, vpc, s))); + ASSERT_SAME_TYPE(char*, decltype(std::strcpy(cp, cpc))); + ASSERT_SAME_TYPE(char*, decltype(std::strncpy(cp, cpc, s))); + ASSERT_SAME_TYPE(char*, decltype(std::strcat(cp, cpc))); + ASSERT_SAME_TYPE(char*, decltype(std::strncat(cp, cpc, s))); + ASSERT_SAME_TYPE(int, decltype(std::memcmp(vpc, vpc, s))); + ASSERT_SAME_TYPE(int, decltype(std::strcmp(cpc, cpc))); + ASSERT_SAME_TYPE(int, decltype(std::strncmp(cpc, cpc, s))); + ASSERT_SAME_TYPE(int, decltype(std::strcoll(cpc, cpc))); + ASSERT_SAME_TYPE(std::size_t, decltype(std::strxfrm(cp, cpc, s))); + ASSERT_SAME_TYPE(std::size_t, decltype(std::strcspn(cpc, cpc))); + ASSERT_SAME_TYPE(std::size_t, decltype(std::strspn(cpc, cpc))); + ASSERT_SAME_TYPE(char*, decltype(std::strtok(cp, cpc))); + ASSERT_SAME_TYPE(void*, decltype(std::memset(vp, 0, s))); + ASSERT_SAME_TYPE(char*, decltype(std::strerror(0))); + ASSERT_SAME_TYPE(std::size_t, decltype(std::strlen(cpc))); + } + + // Functions we (may) reimplement + { + // const char* strchr(const char*, int) + char storage[] = "hello world"; + const char* s = storage; + ASSERT_SAME_TYPE(const char*, decltype(std::strchr(s, 'l'))); + const char* res = std::strchr(s, 'l'); + assert(res == &s[2]); + } + { + // char* strchr(char*, int) + char storage[] = "hello world"; + char* s = storage; + ASSERT_SAME_TYPE(char*, decltype(std::strchr(s, 'l'))); + char* res = std::strchr(s, 'l'); + assert(res == &s[2]); + } + + { + // const char* strpbrk(const char*, const char*) + char storage[] = "hello world"; + const char* s = storage; + ASSERT_SAME_TYPE(const char*, decltype(std::strpbrk(s, "el"))); + const char* res = std::strpbrk(s, "el"); + assert(res == &s[1]); + } + { + // char* strpbrk(char*, const char*) + char storage[] = "hello world"; + char* s = storage; + ASSERT_SAME_TYPE(char*, decltype(std::strpbrk(s, "el"))); + char* res = std::strpbrk(s, "el"); + assert(res == &s[1]); + } + + { + // const char* strrchr(const char*, int) + char storage[] = "hello world"; + const char* s = storage; + ASSERT_SAME_TYPE(const char*, decltype(std::strrchr(s, 'l'))); + const char* res = std::strrchr(s, 'l'); + assert(res == &s[9]); + } + { + // char* strrchr(char*, int) + char storage[] = "hello world"; + char* s = storage; + ASSERT_SAME_TYPE(char*, decltype(std::strrchr(s, 'l'))); + char* res = std::strrchr(s, 'l'); + assert(res == &s[9]); + } + + { + // const void* memchr(const void*, int, size_t) + char storage[] = "hello world"; + std::size_t count = 11; + const void* s = storage; + ASSERT_SAME_TYPE(const void*, decltype(std::memchr(s, 'l', count))); + const void* res = std::memchr(s, 'l', count); + assert(res == &storage[2]); + } + { + // void* memchr(void*, int, size_t) + char storage[] = "hello world"; + std::size_t count = 11; + void* s = storage; + ASSERT_SAME_TYPE(void*, decltype(std::memchr(s, 'l', count))); + void* res = std::memchr(s, 'l', count); + assert(res == &storage[2]); + } + + { + // const char* strstr(const char*, const char*) + char storage[] = "hello world"; + const char* s = storage; + ASSERT_SAME_TYPE(const char*, decltype(std::strstr(s, "wor"))); + const char* res = std::strstr(s, "wor"); + assert(res == &storage[6]); + } + { + // char* strstr(char*, const char*) + char storage[] = "hello world"; + char* s = storage; + ASSERT_SAME_TYPE(char*, decltype(std::strstr(s, "wor"))); + char* res = std::strstr(s, "wor"); + assert(res == &storage[6]); + } return 0; } diff --git a/libcxx/test/std/strings/string.view/string.view.hash/enabled_hashes.pass.cpp b/libcxx/test/std/strings/string.view/string.view.hash/enabled_hashes.pass.cpp --- a/libcxx/test/std/strings/string.view/string.view.hash/enabled_hashes.pass.cpp +++ b/libcxx/test/std/strings/string.view/string.view.hash/enabled_hashes.pass.cpp @@ -24,6 +24,32 @@ char c; }; +template <> +struct std::char_traits { + using char_type = MyChar; + using int_type = std::char_traits::int_type; + using off_type = std::char_traits::off_type; + using pos_type = std::char_traits::pos_type; + using state_type = std::char_traits::state_type; + + static void assign(char_type&, const char_type&); + static bool eq(char_type, char_type); + static bool lt(char_type, char_type); + + static int compare(const char_type*, const char_type*, size_t); + static size_t length(const char_type*); + static const char_type* find(const char_type*, size_t, const char_type&); + static char_type* move(char_type*, const char_type*, size_t); + static char_type* copy(char_type*, const char_type*, size_t); + static char_type* assign(char_type*, size_t, char_type); + + static int_type not_eof(int_type); + static char_type to_char_type(int_type); + static int_type to_int_type(char_type); + static bool eq_int_type(int_type, int_type); + static int_type eof(); +}; + int main(int, char**) { test_library_hash_specializations_available(); { diff --git a/libcxx/test/std/utilities/format/format.formattable/concept.formattable.compile.pass.cpp b/libcxx/test/std/utilities/format/format.formattable/concept.formattable.compile.pass.cpp --- a/libcxx/test/std/utilities/format/format.formattable/concept.formattable.compile.pass.cpp +++ b/libcxx/test/std/utilities/format/format.formattable/concept.formattable.compile.pass.cpp @@ -81,8 +81,10 @@ assert_is_formattable(); assert_is_formattable(); assert_is_formattable(); - assert_is_formattable, CharT>(); - assert_is_formattable, CharT>(); + if constexpr (!std::same_as) { // string and string_view only work with proper character types + assert_is_formattable, CharT>(); + assert_is_formattable, CharT>(); + } assert_is_formattable(); diff --git a/libcxx/test/std/utilities/format/format.functions/format.locale.pass.cpp b/libcxx/test/std/utilities/format/format.functions/format.locale.pass.cpp --- a/libcxx/test/std/utilities/format/format.functions/format.locale.pass.cpp +++ b/libcxx/test/std/utilities/format/format.functions/format.locale.pass.cpp @@ -10,8 +10,6 @@ // UNSUPPORTED: libcpp-has-no-incomplete-format // TODO FMT Evaluate gcc-12 status // UNSUPPORTED:gcc-12 -// TODO FMT Investigate AppleClang ICE -// UNSUPPORTED: apple-clang-13 // diff --git a/libcxx/test/std/utilities/format/format.functions/format.pass.cpp b/libcxx/test/std/utilities/format/format.functions/format.pass.cpp --- a/libcxx/test/std/utilities/format/format.functions/format.pass.cpp +++ b/libcxx/test/std/utilities/format/format.functions/format.pass.cpp @@ -9,8 +9,6 @@ // UNSUPPORTED: libcpp-has-no-incomplete-format // TODO FMT Evaluate gcc-12 status // UNSUPPORTED: gcc-12 -// TODO FMT Investigate AppleClang ICE -// UNSUPPORTED: apple-clang-13 // Note this formatter shows additional information when tests are failing. // This aids the development. Since other formatters fail in the same fashion diff --git a/libcxx/test/std/utilities/format/format.functions/format_to.locale.pass.cpp b/libcxx/test/std/utilities/format/format.functions/format_to.locale.pass.cpp --- a/libcxx/test/std/utilities/format/format.functions/format_to.locale.pass.cpp +++ b/libcxx/test/std/utilities/format/format.functions/format_to.locale.pass.cpp @@ -10,8 +10,6 @@ // UNSUPPORTED: libcpp-has-no-incomplete-format // TODO FMT Evaluate gcc-12 status // UNSUPPORTED: gcc-12 -// TODO FMT Investigate AppleClang ICE -// UNSUPPORTED: apple-clang-13 // diff --git a/libcxx/test/std/utilities/format/format.functions/format_to.pass.cpp b/libcxx/test/std/utilities/format/format.functions/format_to.pass.cpp --- a/libcxx/test/std/utilities/format/format.functions/format_to.pass.cpp +++ b/libcxx/test/std/utilities/format/format.functions/format_to.pass.cpp @@ -9,8 +9,6 @@ // UNSUPPORTED: libcpp-has-no-incomplete-format // TODO FMT Evaluate gcc-12 status // UNSUPPORTED: gcc-12 -// TODO FMT Investigate AppleClang ICE -// UNSUPPORTED: apple-clang-13 // diff --git a/libcxx/test/std/utilities/format/format.functions/format_to_n.locale.pass.cpp b/libcxx/test/std/utilities/format/format.functions/format_to_n.locale.pass.cpp --- a/libcxx/test/std/utilities/format/format.functions/format_to_n.locale.pass.cpp +++ b/libcxx/test/std/utilities/format/format.functions/format_to_n.locale.pass.cpp @@ -10,8 +10,6 @@ // UNSUPPORTED: libcpp-has-no-incomplete-format // TODO FMT Evaluate gcc-12 status // UNSUPPORTED: gcc-12 -// TODO FMT Investigate AppleClang ICE -// UNSUPPORTED: apple-clang-13 // diff --git a/libcxx/test/std/utilities/format/format.functions/format_to_n.pass.cpp b/libcxx/test/std/utilities/format/format.functions/format_to_n.pass.cpp --- a/libcxx/test/std/utilities/format/format.functions/format_to_n.pass.cpp +++ b/libcxx/test/std/utilities/format/format.functions/format_to_n.pass.cpp @@ -9,8 +9,6 @@ // UNSUPPORTED: libcpp-has-no-incomplete-format // TODO FMT Evaluate gcc-12 status // UNSUPPORTED: gcc-12 -// TODO FMT Investigate AppleClang ICE -// UNSUPPORTED: apple-clang-13 // diff --git a/libcxx/test/std/utilities/format/format.functions/formatted_size.locale.pass.cpp b/libcxx/test/std/utilities/format/format.functions/formatted_size.locale.pass.cpp --- a/libcxx/test/std/utilities/format/format.functions/formatted_size.locale.pass.cpp +++ b/libcxx/test/std/utilities/format/format.functions/formatted_size.locale.pass.cpp @@ -10,8 +10,6 @@ // UNSUPPORTED: libcpp-has-no-incomplete-format // TODO FMT Evaluate gcc-12 status // UNSUPPORTED: gcc-12 -// TODO FMT Investigate AppleClang ICE -// UNSUPPORTED: apple-clang-13 // diff --git a/libcxx/test/std/utilities/format/format.functions/formatted_size.pass.cpp b/libcxx/test/std/utilities/format/format.functions/formatted_size.pass.cpp --- a/libcxx/test/std/utilities/format/format.functions/formatted_size.pass.cpp +++ b/libcxx/test/std/utilities/format/format.functions/formatted_size.pass.cpp @@ -9,8 +9,6 @@ // UNSUPPORTED: libcpp-has-no-incomplete-format // TODO FMT Evaluate gcc-12 status // UNSUPPORTED: gcc-12 -// TODO FMT Investigate AppleClang ICE -// UNSUPPORTED: apple-clang-13 // diff --git a/libcxx/test/std/utilities/format/format.functions/vformat.locale.pass.cpp b/libcxx/test/std/utilities/format/format.functions/vformat.locale.pass.cpp --- a/libcxx/test/std/utilities/format/format.functions/vformat.locale.pass.cpp +++ b/libcxx/test/std/utilities/format/format.functions/vformat.locale.pass.cpp @@ -10,8 +10,6 @@ // UNSUPPORTED: libcpp-has-no-incomplete-format // TODO FMT Evaluate gcc-12 status // UNSUPPORTED: gcc-12 -// TODO FMT Investigate AppleClang ICE -// UNSUPPORTED: apple-clang-13 // diff --git a/libcxx/test/std/utilities/format/format.functions/vformat.pass.cpp b/libcxx/test/std/utilities/format/format.functions/vformat.pass.cpp --- a/libcxx/test/std/utilities/format/format.functions/vformat.pass.cpp +++ b/libcxx/test/std/utilities/format/format.functions/vformat.pass.cpp @@ -9,8 +9,6 @@ // UNSUPPORTED: libcpp-has-no-incomplete-format // TODO FMT Evaluate gcc-12 status // UNSUPPORTED: gcc-12 -// TODO FMT Investigate AppleClang ICE -// UNSUPPORTED: apple-clang-13 // diff --git a/libcxx/test/std/utilities/format/format.functions/vformat_to.locale.pass.cpp b/libcxx/test/std/utilities/format/format.functions/vformat_to.locale.pass.cpp --- a/libcxx/test/std/utilities/format/format.functions/vformat_to.locale.pass.cpp +++ b/libcxx/test/std/utilities/format/format.functions/vformat_to.locale.pass.cpp @@ -10,8 +10,6 @@ // UNSUPPORTED: libcpp-has-no-incomplete-format // TODO FMT Evaluate gcc-12 status // UNSUPPORTED: gcc-12 -// TODO FMT Investigate AppleClang ICE -// UNSUPPORTED: apple-clang-13 // diff --git a/libcxx/test/std/utilities/format/format.functions/vformat_to.pass.cpp b/libcxx/test/std/utilities/format/format.functions/vformat_to.pass.cpp --- a/libcxx/test/std/utilities/format/format.functions/vformat_to.pass.cpp +++ b/libcxx/test/std/utilities/format/format.functions/vformat_to.pass.cpp @@ -9,8 +9,6 @@ // UNSUPPORTED: libcpp-has-no-incomplete-format // TODO FMT Evaluate gcc-12 status // UNSUPPORTED: gcc-12 -// TODO FMT Investigate AppleClang ICE -// UNSUPPORTED: apple-clang-13 // diff --git a/libcxx/test/std/utilities/template.bitset/bitset_test_cases.h b/libcxx/test/std/utilities/template.bitset/bitset_test_cases.h --- a/libcxx/test/std/utilities/template.bitset/bitset_test_cases.h +++ b/libcxx/test/std/utilities/template.bitset/bitset_test_cases.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef LIBCPP_TEST_BITSET_TEST_CASES_H #define LIBCPP_TEST_BITSET_TEST_CASES_H diff --git a/libcxx/test/support/any_helpers.h b/libcxx/test/support/any_helpers.h --- a/libcxx/test/support/any_helpers.h +++ b/libcxx/test/support/any_helpers.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef ANY_HELPERS_H #define ANY_HELPERS_H diff --git a/libcxx/test/support/compare_types.h b/libcxx/test/support/compare_types.h --- a/libcxx/test/support/compare_types.h +++ b/libcxx/test/support/compare_types.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef TEST_SUPPORT_COMPARE_TYPES_H #define TEST_SUPPORT_COMPARE_TYPES_H diff --git a/libcxx/test/support/container_test_types.h b/libcxx/test/support/container_test_types.h --- a/libcxx/test/support/container_test_types.h +++ b/libcxx/test/support/container_test_types.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef SUPPORT_CONTAINER_TEST_TYPES_H #define SUPPORT_CONTAINER_TEST_TYPES_H diff --git a/libcxx/test/support/copy_move_types.h b/libcxx/test/support/copy_move_types.h --- a/libcxx/test/support/copy_move_types.h +++ b/libcxx/test/support/copy_move_types.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef LIBCXX_TEST_STD_UTILITIES_TUPLE_CNSTR_TYPES_H #define LIBCXX_TEST_STD_UTILITIES_TUPLE_CNSTR_TYPES_H diff --git a/libcxx/test/support/experimental_any_helpers.h b/libcxx/test/support/experimental_any_helpers.h --- a/libcxx/test/support/experimental_any_helpers.h +++ b/libcxx/test/support/experimental_any_helpers.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef EXPERIMENTAL_ANY_HELPERS_H #define EXPERIMENTAL_ANY_HELPERS_H diff --git a/libcxx/test/support/fp_compare.h b/libcxx/test/support/fp_compare.h --- a/libcxx/test/support/fp_compare.h +++ b/libcxx/test/support/fp_compare.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef SUPPORT_FP_COMPARE_H #define SUPPORT_FP_COMPARE_H diff --git a/libcxx/test/support/indirectly_readable.h b/libcxx/test/support/indirectly_readable.h --- a/libcxx/test/support/indirectly_readable.h +++ b/libcxx/test/support/indirectly_readable.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef LIBCXX_TEST_SUPPORT_INDIRECTLY_READABLE_H #define LIBCXX_TEST_SUPPORT_INDIRECTLY_READABLE_H diff --git a/libcxx/test/support/locale_helpers.h b/libcxx/test/support/locale_helpers.h --- a/libcxx/test/support/locale_helpers.h +++ b/libcxx/test/support/locale_helpers.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef LIBCXX_TEST_SUPPORT_LOCALE_HELPERS_H #define LIBCXX_TEST_SUPPORT_LOCALE_HELPERS_H diff --git a/libcxx/test/support/make_test_thread.h b/libcxx/test/support/make_test_thread.h --- a/libcxx/test/support/make_test_thread.h +++ b/libcxx/test/support/make_test_thread.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef TEST_SUPPORT_MAKE_TEST_THREAD_H #define TEST_SUPPORT_MAKE_TEST_THREAD_H diff --git a/libcxx/test/support/pointer_comparison_test_helper.h b/libcxx/test/support/pointer_comparison_test_helper.h --- a/libcxx/test/support/pointer_comparison_test_helper.h +++ b/libcxx/test/support/pointer_comparison_test_helper.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef POINTER_COMPARISON_TEST_HELPER_H #define POINTER_COMPARISON_TEST_HELPER_H diff --git a/libcxx/test/support/poisoned_hash_helper.h b/libcxx/test/support/poisoned_hash_helper.h --- a/libcxx/test/support/poisoned_hash_helper.h +++ b/libcxx/test/support/poisoned_hash_helper.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef SUPPORT_POISONED_HASH_HELPER_H #define SUPPORT_POISONED_HASH_HELPER_H diff --git a/libcxx/test/support/read_write.h b/libcxx/test/support/read_write.h --- a/libcxx/test/support/read_write.h +++ b/libcxx/test/support/read_write.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef LIBCPP_TEST_SUPPORT_READ_WRITE_H #define LIBCPP_TEST_SUPPORT_READ_WRITE_H diff --git a/libcxx/test/support/set_windows_crt_report_mode.h b/libcxx/test/support/set_windows_crt_report_mode.h --- a/libcxx/test/support/set_windows_crt_report_mode.h +++ b/libcxx/test/support/set_windows_crt_report_mode.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef SUPPORT_SET_WINDOWS_CRT_REPORT_MODE_H #define SUPPORT_SET_WINDOWS_CRT_REPORT_MODE_H diff --git a/libcxx/test/support/template_cost_testing.h b/libcxx/test/support/template_cost_testing.h --- a/libcxx/test/support/template_cost_testing.h +++ b/libcxx/test/support/template_cost_testing.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef TEST_SUPPORT_TEMPLATE_COST_TESTING_H #define TEST_SUPPORT_TEMPLATE_COST_TESTING_H diff --git a/libcxx/test/support/test_constexpr_container.h b/libcxx/test/support/test_constexpr_container.h --- a/libcxx/test/support/test_constexpr_container.h +++ b/libcxx/test/support/test_constexpr_container.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef SUPPORT_TEST_CONSTEXPR_CONTAINER_H #define SUPPORT_TEST_CONSTEXPR_CONTAINER_H diff --git a/libcxx/test/support/test_range.h b/libcxx/test/support/test_range.h --- a/libcxx/test/support/test_range.h +++ b/libcxx/test/support/test_range.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef LIBCXX_TEST_SUPPORT_TEST_RANGE_H #define LIBCXX_TEST_SUPPORT_TEST_RANGE_H diff --git a/libcxx/test/support/type_classification/copyable.h b/libcxx/test/support/type_classification/copyable.h --- a/libcxx/test/support/type_classification/copyable.h +++ b/libcxx/test/support/type_classification/copyable.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef TEST_SUPPORT_TYPE_CLASSIFICATION_COPYABLE_H #define TEST_SUPPORT_TYPE_CLASSIFICATION_COPYABLE_H diff --git a/libcxx/test/support/type_classification/movable.h b/libcxx/test/support/type_classification/movable.h --- a/libcxx/test/support/type_classification/movable.h +++ b/libcxx/test/support/type_classification/movable.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef TEST_SUPPORT_TYPE_CLASSIFICATION_MOVABLE_H #define TEST_SUPPORT_TYPE_CLASSIFICATION_MOVABLE_H diff --git a/libcxx/test/support/type_classification/moveconstructible.h b/libcxx/test/support/type_classification/moveconstructible.h --- a/libcxx/test/support/type_classification/moveconstructible.h +++ b/libcxx/test/support/type_classification/moveconstructible.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef TEST_SUPPORT_TYPE_CLASSIFICATION_MOVECONSTRUCTIBLE_H #define TEST_SUPPORT_TYPE_CLASSIFICATION_MOVECONSTRUCTIBLE_H diff --git a/libcxx/test/support/type_classification/semiregular.h b/libcxx/test/support/type_classification/semiregular.h --- a/libcxx/test/support/type_classification/semiregular.h +++ b/libcxx/test/support/type_classification/semiregular.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef TEST_SUPPORT_TYPE_CLASSIFICATION_H #define TEST_SUPPORT_TYPE_CLASSIFICATION_H diff --git a/libcxx/test/support/type_classification/swappable.h b/libcxx/test/support/type_classification/swappable.h --- a/libcxx/test/support/type_classification/swappable.h +++ b/libcxx/test/support/type_classification/swappable.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef TEST_SUPPORT_TYPE_CLASSIFICATION_SWAPPABLE_H #define TEST_SUPPORT_TYPE_CLASSIFICATION_SWAPPABLE_H diff --git a/libcxx/test/support/type_id.h b/libcxx/test/support/type_id.h --- a/libcxx/test/support/type_id.h +++ b/libcxx/test/support/type_id.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef SUPPORT_TYPE_ID_H #define SUPPORT_TYPE_ID_H diff --git a/libcxx/test/support/user_defined_integral.h b/libcxx/test/support/user_defined_integral.h --- a/libcxx/test/support/user_defined_integral.h +++ b/libcxx/test/support/user_defined_integral.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef SUPPORT_USER_DEFINED_INTEGRAL_H #define SUPPORT_USER_DEFINED_INTEGRAL_H diff --git a/libcxx/test/support/variant_test_helpers.h b/libcxx/test/support/variant_test_helpers.h --- a/libcxx/test/support/variant_test_helpers.h +++ b/libcxx/test/support/variant_test_helpers.h @@ -6,6 +6,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef SUPPORT_VARIANT_TEST_HELPERS_H #define SUPPORT_VARIANT_TEST_HELPERS_H diff --git a/libcxx/utils/ci/BOT_OWNERS.txt b/libcxx/utils/ci/BOT_OWNERS.txt --- a/libcxx/utils/ci/BOT_OWNERS.txt +++ b/libcxx/utils/ci/BOT_OWNERS.txt @@ -11,3 +11,7 @@ N: Linaro Toolchain Working Group E: linaro-toolchain@lists.linaro.org D: Armv7, Armv8, AArch64 + +N: LLVM on Power +E: powerllvm@ca.ibm.com +D: AIX, ppc64le diff --git a/libcxxabi/src/cxa_exception_storage.cpp b/libcxxabi/src/cxa_exception_storage.cpp --- a/libcxxabi/src/cxa_exception_storage.cpp +++ b/libcxxabi/src/cxa_exception_storage.cpp @@ -12,18 +12,21 @@ #include "cxa_exception.h" -namespace __cxxabiv1 { +#include <__threading_support> #if defined(_LIBCXXABI_HAS_NO_THREADS) +namespace __cxxabiv1 { extern "C" { static __cxa_eh_globals eh_globals; __cxa_eh_globals *__cxa_get_globals() { return &eh_globals; } __cxa_eh_globals *__cxa_get_globals_fast() { return &eh_globals; } } // extern "C" +} // namespace __cxxabiv1 -#else +#elif defined(HAS_THREAD_LOCAL) +namespace __cxxabiv1 { namespace { __cxa_eh_globals *__globals() { static thread_local __cxa_eh_globals eh_globals; @@ -35,7 +38,66 @@ __cxa_eh_globals *__cxa_get_globals() { return __globals(); } __cxa_eh_globals *__cxa_get_globals_fast() { return __globals(); } } // extern "C" +} // namespace __cxxabiv1 +#else + +#include "abort_message.h" +#include "fallback_malloc.h" + +#if defined(__ELF__) && defined(_LIBCXXABI_LINK_PTHREAD_LIB) +#pragma comment(lib, "pthread") #endif +// In general, we treat all threading errors as fatal. +// We cannot call std::terminate() because that will in turn +// call __cxa_get_globals() and cause infinite recursion. + +namespace __cxxabiv1 { +namespace { + std::__libcpp_tls_key key_; + std::__libcpp_exec_once_flag flag_ = _LIBCPP_EXEC_ONCE_INITIALIZER; + + void _LIBCPP_TLS_DESTRUCTOR_CC destruct_(void *p) { + __free_with_fallback(p); + if (0 != std::__libcpp_tls_set(key_, NULL)) + abort_message("cannot zero out thread value for __cxa_get_globals()"); + } + + void construct_() { + if (0 != std::__libcpp_tls_create(&key_, destruct_)) + abort_message("cannot create thread specific key for __cxa_get_globals()"); + } +} // namespace + +extern "C" { + __cxa_eh_globals *__cxa_get_globals() { + // Try to get the globals for this thread + __cxa_eh_globals *retVal = __cxa_get_globals_fast(); + + // If this is the first time we've been asked for these globals, create them + if (NULL == retVal) { + retVal = static_cast<__cxa_eh_globals*>( + __calloc_with_fallback(1, sizeof(__cxa_eh_globals))); + if (NULL == retVal) + abort_message("cannot allocate __cxa_eh_globals"); + if (0 != std::__libcpp_tls_set(key_, retVal)) + abort_message("std::__libcpp_tls_set failure in __cxa_get_globals()"); + } + return retVal; + } + + // Note that this implementation will reliably return NULL if not + // preceded by a call to __cxa_get_globals(). This is an extension + // to the Itanium ABI and is taken advantage of in several places in + // libc++abi. + __cxa_eh_globals *__cxa_get_globals_fast() { + // First time through, create the key. + if (0 != std::__libcpp_execute_once(&flag_, construct_)) + abort_message("execute once failure in __cxa_get_globals_fast()"); + return static_cast<__cxa_eh_globals*>(std::__libcpp_tls_get(key_)); + } +} // extern "C" } // namespace __cxxabiv1 + +#endif diff --git a/libcxxabi/src/cxa_guard_impl.h b/libcxxabi/src/cxa_guard_impl.h --- a/libcxxabi/src/cxa_guard_impl.h +++ b/libcxxabi/src/cxa_guard_impl.h @@ -5,6 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// + #ifndef LIBCXXABI_SRC_INCLUDE_CXA_GUARD_IMPL_H #define LIBCXXABI_SRC_INCLUDE_CXA_GUARD_IMPL_H diff --git a/libcxxabi/src/fallback_malloc.h b/libcxxabi/src/fallback_malloc.h --- a/libcxxabi/src/fallback_malloc.h +++ b/libcxxabi/src/fallback_malloc.h @@ -17,6 +17,9 @@ // Allocate some memory from _somewhere_ _LIBCXXABI_HIDDEN void * __aligned_malloc_with_fallback(size_t size); +// Allocate and zero-initialize memory from _somewhere_ +_LIBCXXABI_HIDDEN void * __calloc_with_fallback(size_t count, size_t size); + _LIBCXXABI_HIDDEN void __aligned_free_with_fallback(void *ptr); _LIBCXXABI_HIDDEN void __free_with_fallback(void *ptr); diff --git a/libcxxabi/src/fallback_malloc.cpp b/libcxxabi/src/fallback_malloc.cpp --- a/libcxxabi/src/fallback_malloc.cpp +++ b/libcxxabi/src/fallback_malloc.cpp @@ -270,6 +270,17 @@ return fallback_malloc(size); } +void* __calloc_with_fallback(size_t count, size_t size) { + void* ptr = ::calloc(count, size); + if (NULL != ptr) + return ptr; + // if calloc fails, fall back to emergency stash + ptr = fallback_malloc(size * count); + if (NULL != ptr) + ::memset(ptr, 0, size * count); + return ptr; +} + void __aligned_free_with_fallback(void* ptr) { if (is_fallback_ptr(ptr)) fallback_free(ptr); diff --git a/lld/COFF/DebugTypes.cpp b/lld/COFF/DebugTypes.cpp --- a/lld/COFF/DebugTypes.cpp +++ b/lld/COFF/DebugTypes.cpp @@ -284,14 +284,14 @@ (debugH.size() % 8 == 0); } -static Optional> getDebugH(ObjFile *file) { +static std::optional> getDebugH(ObjFile *file) { SectionChunk *sec = SectionChunk::findByName(file->getDebugChunks(), ".debug$H"); if (!sec) return llvm::None; ArrayRef contents = sec->getContents(); if (!canUseDebugH(contents)) - return None; + return std::nullopt; return contents; } @@ -579,7 +579,7 @@ //===----------------------------------------------------------------------===// void TpiSource::loadGHashes() { - if (Optional> debugH = getDebugH(file)) { + if (std::optional> debugH = getDebugH(file)) { ghashes = getHashesFromDebugH(*debugH); ownedGHashes = false; } else { diff --git a/lld/COFF/Driver.h b/lld/COFF/Driver.h --- a/lld/COFF/Driver.h +++ b/lld/COFF/Driver.h @@ -14,7 +14,6 @@ #include "SymbolTable.h" #include "lld/Common/LLVM.h" #include "lld/Common/Reproduce.h" -#include "llvm/ADT/Optional.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringSet.h" #include "llvm/Object/Archive.h" @@ -25,6 +24,7 @@ #include "llvm/Support/TarWriter.h" #include "llvm/WindowsDriver/MSVCPaths.h" #include +#include #include #include @@ -34,7 +34,7 @@ using llvm::COFF::MachineTypes; using llvm::COFF::WindowsSubsystem; -using llvm::Optional; +using std::optional; class COFFOptTable : public llvm::opt::OptTable { public: @@ -104,8 +104,8 @@ private: // Searches a file from search paths. - Optional findFile(StringRef filename); - Optional findLib(StringRef filename); + std::optional findFile(StringRef filename); + std::optional findLib(StringRef filename); StringRef doFindFile(StringRef filename); StringRef doFindLib(StringRef filename); StringRef doFindLibMinGW(StringRef filename); diff --git a/lld/COFF/Driver.cpp b/lld/COFF/Driver.cpp --- a/lld/COFF/Driver.cpp +++ b/lld/COFF/Driver.cpp @@ -23,7 +23,6 @@ #include "lld/Common/Timer.h" #include "lld/Common/Version.h" #include "llvm/ADT/IntrusiveRefCntPtr.h" -#include "llvm/ADT/Optional.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Triple.h" #include "llvm/BinaryFormat/Magic.h" @@ -52,6 +51,7 @@ #include #include #include +#include using namespace llvm; using namespace llvm::object; @@ -393,7 +393,7 @@ parseAlternateName(arg->getValue()); break; case OPT_defaultlib: - if (Optional path = findLib(arg->getValue())) + if (std::optional path = findLib(arg->getValue())) enqueuePath(*path, false, false); break; case OPT_entry: @@ -474,22 +474,22 @@ return filename; } -static Optional getUniqueID(StringRef path) { +static std::optional getUniqueID(StringRef path) { sys::fs::UniqueID ret; if (sys::fs::getUniqueID(path, ret)) - return None; + return std::nullopt; return ret; } // Resolves a file path. This never returns the same path // (in that case, it returns None). -Optional LinkerDriver::findFile(StringRef filename) { +std::optional LinkerDriver::findFile(StringRef filename) { StringRef path = doFindFile(filename); - if (Optional id = getUniqueID(path)) { + if (std::optional id = getUniqueID(path)) { bool seen = !visitedFiles.insert(*id).second; if (seen) - return None; + return std::nullopt; } if (path.endswith_insensitive(".lib")) @@ -526,19 +526,19 @@ // Resolves a library path. /nodefaultlib options are taken into // consideration. This never returns the same path (in that case, // it returns None). -Optional LinkerDriver::findLib(StringRef filename) { +std::optional LinkerDriver::findLib(StringRef filename) { if (config->noDefaultLibAll) - return None; + return std::nullopt; if (!visitedLibs.insert(filename.lower()).second) - return None; + return std::nullopt; StringRef path = doFindLib(filename); if (config->noDefaultLibs.count(path.lower())) - return None; + return std::nullopt; - if (Optional id = getUniqueID(path)) + if (std::optional id = getUniqueID(path)) if (!visitedFiles.insert(*id).second) - return None; + return std::nullopt; return path; } @@ -1320,7 +1320,7 @@ AutoExporter exporter(excludedSymbols); for (auto *arg : args.filtered(OPT_wholearchive_file)) - if (Optional path = doFindFile(arg->getValue())) + if (std::optional path = doFindFile(arg->getValue())) exporter.addWholeArchive(*path); for (auto *arg : args.filtered(OPT_exclude_symbols)) { @@ -1358,7 +1358,7 @@ // /linkrepro and /reproduce are very similar, but /linkrepro takes a directory // name while /reproduce takes a full path. We have /linkrepro for compatibility // with Microsoft link.exe. -Optional getReproduceFile(const opt::InputArgList &args) { +std::optional getReproduceFile(const opt::InputArgList &args) { if (auto *arg = args.getLastArg(OPT_reproduce)) return std::string(arg->getValue()); @@ -1373,7 +1373,7 @@ if (auto *path = getenv("LLD_REPRODUCE")) return std::string(path); - return None; + return std::nullopt; } static std::unique_ptr @@ -1482,7 +1482,7 @@ " (use --error-limit=0 to see all errors)"; // Handle /linkrepro and /reproduce. - if (Optional path = getReproduceFile(args)) { + if (std::optional path = getReproduceFile(args)) { Expected> errOrWriter = TarWriter::create(*path, sys::path::stem(*path)); @@ -1733,7 +1733,7 @@ // Handle /opt. bool doGC = debug == DebugKind::None || args.hasArg(OPT_profile); - Optional icfLevel; + std::optional icfLevel; if (args.hasArg(OPT_profile)) icfLevel = ICFLevel::None; unsigned tailMerge = 1; @@ -1951,8 +1951,8 @@ std::set wholeArchives; for (auto *arg : args.filtered(OPT_wholearchive_file)) - if (Optional path = doFindFile(arg->getValue())) - if (Optional id = getUniqueID(*path)) + if (std::optional path = doFindFile(arg->getValue())) + if (std::optional id = getUniqueID(*path)) wholeArchives.insert(*id); // A predicate returning true if a given path is an argument for @@ -1962,7 +1962,7 @@ auto isWholeArchive = [&](StringRef path) -> bool { if (args.hasArg(OPT_wholearchive_flag)) return true; - if (Optional id = getUniqueID(path)) + if (std::optional id = getUniqueID(path)) return wholeArchives.count(*id); return false; }; @@ -1984,11 +1984,11 @@ inLib = true; break; case OPT_wholearchive_file: - if (Optional path = findFile(arg->getValue())) + if (std::optional path = findFile(arg->getValue())) enqueuePath(*path, true, inLib); break; case OPT_INPUT: - if (Optional path = findFile(arg->getValue())) + if (std::optional path = findFile(arg->getValue())) enqueuePath(*path, isWholeArchive(*path), inLib); break; default: @@ -2014,7 +2014,7 @@ // Process files specified as /defaultlib. These must be processed after // addWinSysRootLibSearchPaths(), which is why they are in a separate loop. for (auto *arg : args.filtered(OPT_defaultlib)) - if (Optional path = findLib(arg->getValue())) + if (std::optional path = findLib(arg->getValue())) enqueuePath(*path, false, false); run(); if (errorCount()) diff --git a/lld/COFF/DriverUtils.cpp b/lld/COFF/DriverUtils.cpp --- a/lld/COFF/DriverUtils.cpp +++ b/lld/COFF/DriverUtils.cpp @@ -17,7 +17,6 @@ #include "Symbols.h" #include "lld/Common/ErrorHandler.h" #include "lld/Common/Memory.h" -#include "llvm/ADT/Optional.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/BinaryFormat/COFF.h" diff --git a/lld/COFF/InputFiles.h b/lld/COFF/InputFiles.h --- a/lld/COFF/InputFiles.h +++ b/lld/COFF/InputFiles.h @@ -192,7 +192,7 @@ // When using Microsoft precompiled headers, this is the PCH's key. // The same key is used by both the precompiled object, and objects using the // precompiled object. Any difference indicates out-of-date objects. - llvm::Optional pchSignature; + std::optional pchSignature; // Whether this file was compiled with /hotpatch. bool hotPatchable = false; @@ -206,11 +206,11 @@ // The .debug$P or .debug$T section data if present. Empty otherwise. ArrayRef debugTypes; - llvm::Optional> + std::optional> getVariableLocation(StringRef var); - llvm::Optional getDILineInfo(uint32_t offset, - uint32_t sectionIndex); + std::optional getDILineInfo(uint32_t offset, + uint32_t sectionIndex); private: const coff_section* getSection(uint32_t i); @@ -258,7 +258,7 @@ bool &prevailing, DefinedRegular *leader, const llvm::object::coff_aux_section_definition *def); - llvm::Optional + std::optional createDefined(COFFSymbolRef sym, std::vector &comdatDefs, @@ -319,7 +319,7 @@ StringRef path, ObjFile *fromFile); // Record possible errors while opening the PDB file - llvm::Optional loadErr; + std::optional loadErr; // This is the actual interface to the PDB (if it was opened successfully) std::unique_ptr session; diff --git a/lld/COFF/InputFiles.cpp b/lld/COFF/InputFiles.cpp --- a/lld/COFF/InputFiles.cpp +++ b/lld/COFF/InputFiles.cpp @@ -37,6 +37,7 @@ #include "llvm/Support/Path.h" #include "llvm/Target/TargetOptions.h" #include +#include #include #include @@ -396,7 +397,7 @@ symbols[i] = createUndefined(coffSym); uint32_t tagIndex = coffSym.getAux()->TagIndex; weakAliases.emplace_back(symbols[i], tagIndex); - } else if (Optional optSym = + } else if (std::optional optSym = createDefined(coffSym, comdatDefs, prevailingComdat)) { symbols[i] = *optSym; if (config->mingw && prevailingComdat) @@ -581,7 +582,7 @@ } } -Optional ObjFile::createDefined( +std::optional ObjFile::createDefined( COFFSymbolRef sym, std::vector &comdatDefs, bool &prevailing) { @@ -676,7 +677,7 @@ if (def->Selection != IMAGE_COMDAT_SELECT_ASSOCIATIVE) comdatDefs[sectionNumber] = def; } - return None; + return std::nullopt; } return createRegular(sym); @@ -840,8 +841,8 @@ } // If existing, return the actual PDB path on disk. -static Optional findPdbPath(StringRef pdbPath, - ObjFile *dependentFile) { +static std::optional findPdbPath(StringRef pdbPath, + ObjFile *dependentFile) { // Ensure the file exists before anything else. In some cases, if the path // points to a removable device, Driver::enqueuePath() would fail with an // error (EAGAIN, "resource unavailable try again") which we want to skip @@ -851,7 +852,7 @@ std::string ret = getPdbBaseName(dependentFile, pdbPath); if (llvm::sys::fs::exists(ret)) return normalizePdbPath(ret); - return None; + return std::nullopt; } PDBInputFile::PDBInputFile(COFFLinkerContext &ctx, MemoryBufferRef m) @@ -896,29 +897,30 @@ // Used only for DWARF debug info, which is not common (except in MinGW // environments). This returns an optional pair of file name and line // number for where the variable was defined. -Optional> +std::optional> ObjFile::getVariableLocation(StringRef var) { if (!dwarf) { dwarf = make(DWARFContext::create(*getCOFFObj())); if (!dwarf) - return None; + return std::nullopt; } if (config->machine == I386) var.consume_front("_"); - Optional> ret = dwarf->getVariableLoc(var); + std::optional> ret = + dwarf->getVariableLoc(var); if (!ret) - return None; + return std::nullopt; return std::make_pair(saver().save(ret->first), ret->second); } // Used only for DWARF debug info, which is not common (except in MinGW // environments). -Optional ObjFile::getDILineInfo(uint32_t offset, - uint32_t sectionIndex) { +std::optional ObjFile::getDILineInfo(uint32_t offset, + uint32_t sectionIndex) { if (!dwarf) { dwarf = make(DWARFContext::create(*getCOFFObj())); if (!dwarf) - return None; + return std::nullopt; } return dwarf->getDILineInfo(offset, sectionIndex); diff --git a/lld/COFF/PDB.h b/lld/COFF/PDB.h --- a/lld/COFF/PDB.h +++ b/lld/COFF/PDB.h @@ -10,8 +10,8 @@ #define LLD_COFF_PDB_H #include "llvm/ADT/ArrayRef.h" -#include "llvm/ADT/Optional.h" #include "llvm/ADT/StringRef.h" +#include namespace llvm::codeview { union DebugInfo; @@ -27,7 +27,7 @@ void createPDB(COFFLinkerContext &ctx, llvm::ArrayRef sectionTable, llvm::codeview::DebugInfo *buildId); -llvm::Optional> +std::optional> getFileLineCodeView(const SectionChunk *c, uint32_t addr); } // namespace coff diff --git a/lld/COFF/PDB.cpp b/lld/COFF/PDB.cpp --- a/lld/COFF/PDB.cpp +++ b/lld/COFF/PDB.cpp @@ -57,6 +57,7 @@ #include "llvm/Support/Path.h" #include "llvm/Support/ScopedPrinter.h" #include +#include using namespace llvm; using namespace llvm::codeview; @@ -1776,7 +1777,7 @@ // Use CodeView line tables to resolve a file and line number for the given // offset into the given chunk and return them, or None if a line table was // not found. -Optional> +std::optional> lld::coff::getFileLineCodeView(const SectionChunk *c, uint32_t addr) { ExitOnError exitOnErr; @@ -1786,10 +1787,10 @@ uint32_t offsetInLinetable; if (!findLineTable(c, addr, cvStrTab, checksums, lines, offsetInLinetable)) - return None; + return std::nullopt; - Optional nameIndex; - Optional lineNumber; + std::optional nameIndex; + std::optional lineNumber; for (const LineColumnEntry &entry : lines) { for (const LineNumberEntry &ln : entry.LineNumbers) { LineInfo li(ln.Flags); @@ -1807,7 +1808,7 @@ } } if (!nameIndex) - return None; + return std::nullopt; StringRef filename = exitOnErr(getFileName(cvStrTab, checksums, *nameIndex)); return std::make_pair(filename, *lineNumber); } diff --git a/lld/COFF/SymbolTable.cpp b/lld/COFF/SymbolTable.cpp --- a/lld/COFF/SymbolTable.cpp +++ b/lld/COFF/SymbolTable.cpp @@ -125,22 +125,22 @@ return {res}; } -static Optional> +static std::optional> getFileLineDwarf(const SectionChunk *c, uint32_t addr) { - Optional optionalLineInfo = + std::optional optionalLineInfo = c->file->getDILineInfo(addr, c->getSectionNumber() - 1); if (!optionalLineInfo) - return None; + return std::nullopt; const DILineInfo &lineInfo = *optionalLineInfo; if (lineInfo.FileName == DILineInfo::BadString) - return None; + return std::nullopt; return std::make_pair(saver().save(lineInfo.FileName), lineInfo.Line); } -static Optional> +static std::optional> getFileLine(const SectionChunk *c, uint32_t addr) { // MinGW can optionally use codeview, even if the default is dwarf. - Optional> fileLine = + std::optional> fileLine = getFileLineCodeView(c, addr); // If codeview didn't yield any result, check dwarf in MinGW mode. if (!fileLine && config->mingw) @@ -174,7 +174,7 @@ if (locations.size() >= maxStrings) continue; - Optional> fileLine = + std::optional> fileLine = getFileLine(sc, r.VirtualAddress); Symbol *sym = getSymbol(sc, r.VirtualAddress); if (fileLine) @@ -604,7 +604,7 @@ static std::string getSourceLocationObj(ObjFile *file, SectionChunk *sc, uint32_t offset, StringRef name) { - Optional> fileLine; + std::optional> fileLine; if (sc) fileLine = getFileLine(sc, offset); if (!fileLine) diff --git a/lld/COFF/Writer.cpp b/lld/COFF/Writer.cpp --- a/lld/COFF/Writer.cpp +++ b/lld/COFF/Writer.cpp @@ -240,7 +240,7 @@ PartialSection *createPartialSection(StringRef name, uint32_t outChars); PartialSection *findPartialSection(StringRef name, uint32_t outChars); - llvm::Optional createSymbol(Defined *d); + std::optional createSymbol(Defined *d); size_t addEntryToStringTable(StringRef str); OutputSection *findSection(StringRef name); @@ -1137,7 +1137,7 @@ return offsetOfEntry; } -Optional Writer::createSymbol(Defined *def) { +std::optional Writer::createSymbol(Defined *def) { coff_symbol16 sym; switch (def->kind()) { case Symbol::DefinedAbsoluteKind: { @@ -1156,10 +1156,10 @@ // like __ImageBase are outside of sections and thus cannot be represented. Chunk *c = def->getChunk(); if (!c) - return None; + return std::nullopt; OutputSection *os = ctx.getOutputSection(c); if (!os) - return None; + return std::nullopt; sym.Value = def->getRVA() - os->getRVA(); sym.SectionNumber = os->sectionIndex; @@ -1172,7 +1172,7 @@ // instead. Avoid emitting them to the symbol table, as they can confuse // debuggers. if (def->isRuntimePseudoReloc) - return None; + return std::nullopt; StringRef name = def->getName(); if (name.size() > COFF::NameSize) { @@ -1235,13 +1235,14 @@ continue; } - if (Optional sym = createSymbol(d)) + if (std::optional sym = createSymbol(d)) outputSymtab.push_back(*sym); if (auto *dthunk = dyn_cast(d)) { if (!dthunk->wrappedSym->writtenToSymtab) { dthunk->wrappedSym->writtenToSymtab = true; - if (Optional sym = createSymbol(dthunk->wrappedSym)) + if (std::optional sym = + createSymbol(dthunk->wrappedSym)) outputSymtab.push_back(*sym); } } diff --git a/lld/Common/DWARF.cpp b/lld/Common/DWARF.cpp --- a/lld/Common/DWARF.cpp +++ b/lld/Common/DWARF.cpp @@ -69,27 +69,27 @@ // Returns the pair of file name and line number describing location of data // object (variable, array, etc) definition. -Optional> +std::optional> DWARFCache::getVariableLoc(StringRef name) { // Return if we have no debug information about data object. auto it = variableLoc.find(name); if (it == variableLoc.end()) - return None; + return std::nullopt; // Take file name string from line table. std::string fileName; if (!it->second.lt->getFileNameByIndex( it->second.file, {}, DILineInfoSpecifier::FileLineInfoKind::AbsoluteFilePath, fileName)) - return None; + return std::nullopt; return std::make_pair(fileName, it->second.line); } // Returns source line information for a given offset // using DWARF debug info. -Optional DWARFCache::getDILineInfo(uint64_t offset, - uint64_t sectionIndex) { +std::optional DWARFCache::getDILineInfo(uint64_t offset, + uint64_t sectionIndex) { DILineInfo info; for (const llvm::DWARFDebugLine::LineTable *lt : lineTables) { if (lt->getFileLineInfoForAddress( @@ -97,7 +97,7 @@ DILineInfoSpecifier::FileLineInfoKind::AbsoluteFilePath, info)) return info; } - return None; + return std::nullopt; } } // namespace lld diff --git a/lld/ELF/Config.h b/lld/ELF/Config.h --- a/lld/ELF/Config.h +++ b/lld/ELF/Config.h @@ -27,6 +27,7 @@ #include "llvm/Support/PrettyStackTrace.h" #include #include +#include #include namespace lld::elf { @@ -310,7 +311,7 @@ SeparateSegmentKind zSeparate; ELFKind ekind = ELFNoneKind; uint16_t emachine = llvm::ELF::EM_NONE; - llvm::Optional imageBase; + std::optional imageBase; uint64_t commonPageSize; uint64_t maxPageSize; uint64_t mipsGotSize; diff --git a/lld/ELF/DWARF.h b/lld/ELF/DWARF.h --- a/lld/ELF/DWARF.h +++ b/lld/ELF/DWARF.h @@ -76,14 +76,14 @@ return ELFT::TargetEndianness == llvm::support::little; } - llvm::Optional find(const llvm::DWARFSection &sec, - uint64_t pos) const override; + std::optional find(const llvm::DWARFSection &sec, + uint64_t pos) const override; private: template - llvm::Optional findAux(const InputSectionBase &sec, - uint64_t pos, - ArrayRef rels) const; + std::optional findAux(const InputSectionBase &sec, + uint64_t pos, + ArrayRef rels) const; LLDDWARFSection gnuPubnamesSection; LLDDWARFSection gnuPubtypesSection; diff --git a/lld/ELF/DWARF.cpp b/lld/ELF/DWARF.cpp --- a/lld/ELF/DWARF.cpp +++ b/lld/ELF/DWARF.cpp @@ -101,13 +101,13 @@ // to llvm since it has no idea about InputSection. template template -Optional +std::optional LLDDwarfObj::findAux(const InputSectionBase &sec, uint64_t pos, ArrayRef rels) const { auto it = partition_point(rels, [=](const RelTy &a) { return a.r_offset < pos; }); if (it == rels.end() || it->r_offset != pos) - return None; + return std::nullopt; const RelTy &rel = *it; const ObjFile *file = sec.getFile(); @@ -132,8 +132,8 @@ } template -Optional LLDDwarfObj::find(const llvm::DWARFSection &s, - uint64_t pos) const { +std::optional +LLDDwarfObj::find(const llvm::DWARFSection &s, uint64_t pos) const { auto &sec = static_cast(s); const RelsOrRelas rels = sec.sec->template relsOrRelas(); if (rels.areRelocsRel()) diff --git a/lld/ELF/Driver.h b/lld/ELF/Driver.h --- a/lld/ELF/Driver.h +++ b/lld/ELF/Driver.h @@ -10,9 +10,9 @@ #define LLD_ELF_DRIVER_H #include "lld/Common/LLVM.h" -#include "llvm/ADT/Optional.h" #include "llvm/ADT/StringRef.h" #include "llvm/Option/ArgList.h" +#include namespace lld::elf { // Parses command line options. @@ -33,10 +33,10 @@ void printHelp(); std::string createResponseFile(const llvm::opt::InputArgList &args); -llvm::Optional findFromSearchPaths(StringRef path); -llvm::Optional searchScript(StringRef path); -llvm::Optional searchLibraryBaseName(StringRef path); -llvm::Optional searchLibrary(StringRef path); +std::optional findFromSearchPaths(StringRef path); +std::optional searchScript(StringRef path); +std::optional searchLibraryBaseName(StringRef path); +std::optional searchLibrary(StringRef path); } // namespace lld::elf diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp --- a/lld/ELF/Driver.cpp +++ b/lld/ELF/Driver.cpp @@ -227,7 +227,7 @@ void LinkerDriver::addFile(StringRef path, bool withLOption) { using namespace sys::fs; - Optional buffer = readFile(path); + std::optional buffer = readFile(path); if (!buffer) return; MemoryBufferRef mbref = *buffer; @@ -314,7 +314,7 @@ // Add a given library by searching it from input search paths. void LinkerDriver::addLibrary(StringRef name) { - if (Optional path = searchLibrary(name)) + if (std::optional path = searchLibrary(name)) addFile(saver().save(*path), /*withLOption=*/true); else error("unable to find library -l" + name, ErrorTag::LibNotFound, {name}); @@ -1460,7 +1460,7 @@ if (args.hasArg(OPT_call_graph_ordering_file)) error("--symbol-ordering-file and --call-graph-order-file " "may not be used together"); - if (Optional buffer = readFile(arg->getValue())){ + if (std::optional buffer = readFile(arg->getValue())) { config->symbolOrderingFile = getSymbolOrderingFile(*buffer); // Also need to disable CallGraphProfileSort to prevent // LLD order symbols with CGProfile @@ -1479,7 +1479,7 @@ if (auto *arg = args.getLastArg(OPT_retain_symbols_file)) { config->versionDefinitions[VER_NDX_LOCAL].nonLocalPatterns.push_back( {"*", /*isExternCpp=*/false, /*hasWildcard=*/true}); - if (Optional buffer = readFile(arg->getValue())) + if (std::optional buffer = readFile(arg->getValue())) for (StringRef s : args::getLines(*buffer)) config->versionDefinitions[VER_NDX_GLOBAL].nonLocalPatterns.push_back( {s, /*isExternCpp=*/false, /*hasWildcard=*/false}); @@ -1510,12 +1510,12 @@ config->bsymbolic == BsymbolicKind::All || args.hasArg(OPT_dynamic_list); for (auto *arg : args.filtered(OPT_dynamic_list, OPT_export_dynamic_symbol_list)) - if (Optional buffer = readFile(arg->getValue())) + if (std::optional buffer = readFile(arg->getValue())) readDynamicList(*buffer); for (auto *arg : args.filtered(OPT_version_script)) - if (Optional path = searchScript(arg->getValue())) { - if (Optional buffer = readFile(*path)) + if (std::optional path = searchScript(arg->getValue())) { + if (std::optional buffer = readFile(*path)) readVersionScript(*buffer); } else { error(Twine("cannot find version script ") + arg->getValue()); @@ -1622,8 +1622,8 @@ break; } case OPT_script: - if (Optional path = searchScript(arg->getValue())) { - if (Optional mb = readFile(*path)) + if (std::optional path = searchScript(arg->getValue())) { + if (std::optional mb = readFile(*path)) readLinkerScript(*mb); break; } @@ -1653,7 +1653,7 @@ inWholeArchive = false; break; case OPT_just_symbols: - if (Optional mb = readFile(arg->getValue())) { + if (std::optional mb = readFile(arg->getValue())) { files.push_back(createObjFile(*mb)); files.back()->justSymbols = true; } @@ -1757,12 +1757,12 @@ } // Parses --image-base option. -static Optional getImageBase(opt::InputArgList &args) { +static std::optional getImageBase(opt::InputArgList &args) { // Because we are using "Config->maxPageSize" here, this function has to be // called after the variable is initialized. auto *arg = args.getLastArg(OPT_image_base); if (!arg) - return None; + return std::nullopt; StringRef s = arg->getValue(); uint64_t v; @@ -2855,7 +2855,7 @@ // Read the callgraph now that we know what was gced or icfed if (config->callGraphProfileSort) { if (auto *arg = args.getLastArg(OPT_call_graph_ordering_file)) - if (Optional buffer = readFile(arg->getValue())) + if (std::optional buffer = readFile(arg->getValue())) readCallGraph(*buffer); invokeELFT(readCallGraphsFromObjectFiles); } diff --git a/lld/ELF/DriverUtils.cpp b/lld/ELF/DriverUtils.cpp --- a/lld/ELF/DriverUtils.cpp +++ b/lld/ELF/DriverUtils.cpp @@ -16,7 +16,6 @@ #include "Driver.h" #include "lld/Common/CommonLinkerContext.h" #include "lld/Common/Reproduce.h" -#include "llvm/ADT/Optional.h" #include "llvm/ADT/Triple.h" #include "llvm/Option/Option.h" #include "llvm/Support/CommandLine.h" @@ -24,6 +23,7 @@ #include "llvm/Support/Host.h" #include "llvm/Support/Path.h" #include "llvm/Support/TimeProfiler.h" +#include using namespace llvm; using namespace llvm::sys; @@ -207,7 +207,8 @@ // Find a file by concatenating given paths. If a resulting path // starts with "=", the character is replaced with a --sysroot value. -static Optional findFile(StringRef path1, const Twine &path2) { +static std::optional findFile(StringRef path1, + const Twine &path2) { SmallString<128> s; if (path1.startswith("=")) path::append(s, config->sysroot, path1.substr(1), path2); @@ -216,31 +217,31 @@ if (fs::exists(s)) return std::string(s); - return None; + return std::nullopt; } -Optional elf::findFromSearchPaths(StringRef path) { +std::optional elf::findFromSearchPaths(StringRef path) { for (StringRef dir : config->searchPaths) - if (Optional s = findFile(dir, path)) + if (std::optional s = findFile(dir, path)) return s; - return None; + return std::nullopt; } // This is for -l. We'll look for lib.so or lib.a from // search paths. -Optional elf::searchLibraryBaseName(StringRef name) { +std::optional elf::searchLibraryBaseName(StringRef name) { for (StringRef dir : config->searchPaths) { if (!config->isStatic) - if (Optional s = findFile(dir, "lib" + name + ".so")) + if (std::optional s = findFile(dir, "lib" + name + ".so")) return s; - if (Optional s = findFile(dir, "lib" + name + ".a")) + if (std::optional s = findFile(dir, "lib" + name + ".a")) return s; } - return None; + return std::nullopt; } // This is for -l. -Optional elf::searchLibrary(StringRef name) { +std::optional elf::searchLibrary(StringRef name) { llvm::TimeTraceScope timeScope("Locate library", name); if (name.startswith(":")) return findFromSearchPaths(name.substr(1)); @@ -250,7 +251,7 @@ // If a linker/version script doesn't exist in the current directory, we also // look for the script in the '-L' search paths. This matches the behaviour of // '-T', --version-script=, and linker script INPUT() command in ld.bfd. -Optional elf::searchScript(StringRef name) { +std::optional elf::searchScript(StringRef name) { if (fs::exists(name)) return name.str(); return findFromSearchPaths(name); diff --git a/lld/ELF/InputFiles.h b/lld/ELF/InputFiles.h --- a/lld/ELF/InputFiles.h +++ b/lld/ELF/InputFiles.h @@ -43,7 +43,7 @@ extern std::unique_ptr tar; // Opens a given file. -llvm::Optional readFile(StringRef path); +std::optional readFile(StringRef path); // Add symbols in File to the symbol table. void parseFile(InputFile *file); @@ -248,8 +248,9 @@ return getSymbol(symIndex); } - llvm::Optional getDILineInfo(InputSectionBase *, uint64_t); - llvm::Optional> getVariableLoc(StringRef name); + std::optional getDILineInfo(InputSectionBase *, uint64_t); + std::optional> + getVariableLoc(StringRef name); // Name of source file obtained from STT_FILE symbol value, // or empty string if there is no such symbol in object file diff --git a/lld/ELF/InputFiles.cpp b/lld/ELF/InputFiles.cpp --- a/lld/ELF/InputFiles.cpp +++ b/lld/ELF/InputFiles.cpp @@ -187,7 +187,7 @@ ++nextGroupId; } -Optional elf::readFile(StringRef path) { +std::optional elf::readFile(StringRef path) { llvm::TimeTraceScope timeScope("Load input files", path); // The --chroot option changes our virtual root directory. @@ -202,7 +202,7 @@ /*RequiresNullTerminator=*/false); if (auto ec = mbOrErr.getError()) { error("cannot open " + path + ": " + ec.message()); - return None; + return std::nullopt; } MemoryBufferRef mbref = (*mbOrErr)->getMemBufferRef(); @@ -308,11 +308,11 @@ InputSectionBase &sec, uint64_t offset) { // In DWARF, functions and variables are stored to different places. // First, look up a function for a given offset. - if (Optional info = file.getDILineInfo(&sec, offset)) + if (std::optional info = file.getDILineInfo(&sec, offset)) return createFileLineMsg(info->FileName, info->Line); // If it failed, look up again as a variable. - if (Optional> fileLine = + if (std::optional> fileLine = file.getVariableLoc(sym.getName())) return createFileLineMsg(fileLine->first, fileLine->second); @@ -357,9 +357,9 @@ static void addDependentLibrary(StringRef specifier, const InputFile *f) { if (!config->dependentLibraries) return; - if (Optional s = searchLibraryBaseName(specifier)) + if (std::optional s = searchLibraryBaseName(specifier)) ctx.driver.addFile(saver().save(*s), /*withLOption=*/true); - else if (Optional s = findFromSearchPaths(specifier)) + else if (std::optional s = findFromSearchPaths(specifier)) ctx.driver.addFile(saver().save(*s), /*withLOption=*/true); else if (fs::exists(specifier)) ctx.driver.addFile(specifier, /*withLOption=*/false); @@ -423,7 +423,7 @@ // Returns the pair of file name and line number describing location of data // object (variable, array, etc) definition. template -Optional> +std::optional> ObjFile::getVariableLoc(StringRef name) { return getDwarf()->getVariableLoc(name); } @@ -431,8 +431,8 @@ // Returns source line information for a given offset // using DWARF debug info. template -Optional ObjFile::getDILineInfo(InputSectionBase *s, - uint64_t offset) { +std::optional ObjFile::getDILineInfo(InputSectionBase *s, + uint64_t offset) { // Detect SectionIndex for specified section. uint64_t sectionIndex = object::SectionedAddress::UndefSection; ArrayRef sections = s->file->getSections(); @@ -1775,21 +1775,18 @@ const ArrayRef eSyms = this->getELFSyms(); numSymbols = eSyms.size(); symbols = std::make_unique(numSymbols); - for (size_t i = firstGlobal, end = eSyms.size(); i != end; ++i) - if (eSyms[i].st_shndx != SHN_UNDEF) - symbols[i] = symtab.insert(CHECK(eSyms[i].getName(stringTable), this)); - // Replace existing symbols with LazyObject symbols. - // // resolve() may trigger this->extract() if an existing symbol is an undefined // symbol. If that happens, this function has served its purpose, and we can // exit from the loop early. - for (Symbol *sym : getGlobalSymbols()) - if (sym) { - sym->resolve(LazyObject{*this}); - if (!lazy) - return; - } + for (size_t i = firstGlobal, end = eSyms.size(); i != end; ++i) { + if (eSyms[i].st_shndx == SHN_UNDEF) + continue; + symbols[i] = symtab.insert(CHECK(eSyms[i].getName(stringTable), this)); + symbols[i]->resolve(LazyObject{*this}); + if (!lazy) + break; + } } bool InputFile::shouldExtractForCommon(StringRef name) { diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp --- a/lld/ELF/InputSection.cpp +++ b/lld/ELF/InputSection.cpp @@ -834,7 +834,7 @@ const bool isDebugLocOrRanges = isDebug && (name == ".debug_loc" || name == ".debug_ranges"); const bool isDebugLine = isDebug && name == ".debug_line"; - Optional tombstone; + std::optional tombstone; for (const auto &patAndValue : llvm::reverse(config->deadRelocInNonAlloc)) if (patAndValue.first.match(this->name)) { tombstone = patAndValue.second; diff --git a/lld/ELF/LinkerScript.h b/lld/ELF/LinkerScript.h --- a/lld/ELF/LinkerScript.h +++ b/lld/ELF/LinkerScript.h @@ -165,7 +165,7 @@ StringMatcher excludedFilePat; // Cache of the most recent input argument and result of excludesFile(). - mutable llvm::Optional> excludesFileCache; + mutable std::optional> excludesFileCache; public: SectionPattern(StringMatcher &&pat1, StringMatcher &&pat2) @@ -184,7 +184,7 @@ SingleStringMatcher filePat; // Cache of the most recent input argument and result of matchesFile(). - mutable llvm::Optional> matchesFileCache; + mutable std::optional> matchesFileCache; public: InputSectionDescription(StringRef filePattern, uint64_t withFlags = 0, @@ -251,7 +251,7 @@ unsigned type = llvm::ELF::PT_NULL; bool hasFilehdr = false; bool hasPhdrs = false; - llvm::Optional flags; + std::optional flags; Expr lmaExpr = nullptr; }; diff --git a/lld/ELF/LinkerScript.cpp b/lld/ELF/LinkerScript.cpp --- a/lld/ELF/LinkerScript.cpp +++ b/lld/ELF/LinkerScript.cpp @@ -1405,12 +1405,12 @@ } // Returns the index of the segment named Name. -static Optional getPhdrIndex(ArrayRef vec, - StringRef name) { +static std::optional getPhdrIndex(ArrayRef vec, + StringRef name) { for (size_t i = 0; i < vec.size(); ++i) if (vec[i].name == name) return i; - return None; + return std::nullopt; } // Returns indices of ELF headers containing specific section. Each index is a @@ -1419,7 +1419,7 @@ SmallVector ret; for (StringRef s : cmd->phdrs) { - if (Optional idx = getPhdrIndex(phdrsCommands, s)) + if (std::optional idx = getPhdrIndex(phdrsCommands, s)) ret.push_back(*idx); else if (s != "NONE") error(cmd->location + ": program header '" + s + diff --git a/lld/ELF/OutputSections.h b/lld/ELF/OutputSections.h --- a/lld/ELF/OutputSections.h +++ b/lld/ELF/OutputSections.h @@ -85,7 +85,7 @@ Expr subalignExpr; SmallVector commands; SmallVector phdrs; - llvm::Optional> filler; + std::optional> filler; ConstraintKind constraint = ConstraintKind::NoConstraint; std::string location; std::string memoryRegionName; diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp --- a/lld/ELF/Relocations.cpp +++ b/lld/ELF/Relocations.cpp @@ -64,19 +64,19 @@ using namespace lld; using namespace lld::elf; -static Optional getLinkerScriptLocation(const Symbol &sym) { +static std::optional getLinkerScriptLocation(const Symbol &sym) { for (SectionCommand *cmd : script->sectionCommands) if (auto *assign = dyn_cast(cmd)) if (assign->sym == &sym) return assign->location; - return None; + return std::nullopt; } static std::string getDefinedLocation(const Symbol &sym) { const char msg[] = "\n>>> defined in "; if (sym.file) return msg + toString(sym.file); - if (Optional loc = getLinkerScriptLocation(sym)) + if (std::optional loc = getLinkerScriptLocation(sym)) return msg + *loc; return ""; } diff --git a/lld/ELF/ScriptParser.cpp b/lld/ELF/ScriptParser.cpp --- a/lld/ELF/ScriptParser.cpp +++ b/lld/ELF/ScriptParser.cpp @@ -330,7 +330,7 @@ ctx.driver.addFile(s, /*withLOption=*/false); } else { // Finally, search in the list of library paths. - if (Optional path = findFromSearchPaths(s)) + if (std::optional path = findFromSearchPaths(s)) ctx.driver.addFile(saver().save(*path), /*withLOption=*/true); else setError("unable to find " + s); @@ -379,8 +379,8 @@ return; } - if (Optional path = searchScript(tok)) { - if (Optional mb = readFile(*path)) + if (std::optional path = searchScript(tok)) { + if (std::optional mb = readFile(*path)) tokenize(*mb); return; } @@ -1221,33 +1221,33 @@ // Parses Tok as an integer. It recognizes hexadecimal (prefixed with // "0x" or suffixed with "H") and decimal numbers. Decimal numbers may // have "K" (Ki) or "M" (Mi) suffixes. -static Optional parseInt(StringRef tok) { +static std::optional parseInt(StringRef tok) { // Hexadecimal uint64_t val; if (tok.startswith_insensitive("0x")) { if (!to_integer(tok.substr(2), val, 16)) - return None; + return std::nullopt; return val; } if (tok.endswith_insensitive("H")) { if (!to_integer(tok.drop_back(), val, 16)) - return None; + return std::nullopt; return val; } // Decimal if (tok.endswith_insensitive("K")) { if (!to_integer(tok.drop_back(), val, 10)) - return None; + return std::nullopt; return val * 1024; } if (tok.endswith_insensitive("M")) { if (!to_integer(tok.drop_back(), val, 10)) - return None; + return std::nullopt; return val * 1024 * 1024; } if (!to_integer(tok, val, 10)) - return None; + return std::nullopt; return val; } @@ -1269,11 +1269,11 @@ return make(e, size, commandString); } -static llvm::Optional parseFlag(StringRef tok) { - if (llvm::Optional asInt = parseInt(tok)) +static std::optional parseFlag(StringRef tok) { + if (std::optional asInt = parseInt(tok)) return asInt; #define CASE_ENT(enum) #enum, ELF::enum - return StringSwitch>(tok) + return StringSwitch>(tok) .Case(CASE_ENT(SHF_WRITE)) .Case(CASE_ENT(SHF_ALLOC)) .Case(CASE_ENT(SHF_EXECINSTR)) @@ -1308,7 +1308,7 @@ while (!errorCount()) { StringRef tok = unquote(next()); bool without = tok.consume_front("!"); - if (llvm::Optional flag = parseFlag(tok)) { + if (std::optional flag = parseFlag(tok)) { if (without) withoutFlags |= *flag; else @@ -1521,7 +1521,7 @@ return [=] { return script->getSymbolValue(tok, location); }; // Tok is a literal number. - if (Optional val = parseInt(tok)) + if (std::optional val = parseInt(tok)) return [=] { return *val; }; // Tok is a symbol name. @@ -1560,7 +1560,7 @@ // name of a program header type or a constant (e.g. "0x3"). unsigned ScriptParser::readPhdrType() { StringRef tok = next(); - if (Optional val = parseInt(tok)) + if (std::optional val = parseInt(tok)) return *val; unsigned ret = StringSwitch(tok) diff --git a/lld/ELF/SymbolTable.h b/lld/ELF/SymbolTable.h --- a/lld/ELF/SymbolTable.h +++ b/lld/ELF/SymbolTable.h @@ -85,7 +85,7 @@ // This mapping is 1:N because two symbols with different versions // can have the same name. We use this map to handle "extern C++ {}" // directive in version scripts. - llvm::Optional>> demangledSyms; + std::optional>> demangledSyms; }; LLVM_LIBRARY_VISIBILITY extern SymbolTable symtab; diff --git a/lld/ELF/SyntheticSections.h b/lld/ELF/SyntheticSections.h --- a/lld/ELF/SyntheticSections.h +++ b/lld/ELF/SyntheticSections.h @@ -500,7 +500,7 @@ /// Add a dynamic relocation against \p sym with an optional addend. void addSymbolReloc(RelType dynType, InputSectionBase &isec, uint64_t offsetInSec, Symbol &sym, int64_t addend = 0, - llvm::Optional addendRelType = llvm::None); + std::optional addendRelType = {}); /// Add a relative dynamic relocation that uses the target address of \p sym /// (i.e. InputSection::getRelocTargetVA()) + \p addend as the addend. /// This function should only be called for non-preemptible symbols or @@ -1163,7 +1163,7 @@ public: PPC64LongBranchTargetSection(); uint64_t getEntryVA(const Symbol *sym, int64_t addend); - llvm::Optional addEntry(const Symbol *sym, int64_t addend); + std::optional addEntry(const Symbol *sym, int64_t addend); size_t getSize() const override; void writeTo(uint8_t *buf) override; bool isNeeded() const override; diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp --- a/lld/ELF/SyntheticSections.cpp +++ b/lld/ELF/SyntheticSections.cpp @@ -1580,11 +1580,9 @@ dynamicTag(dynamicTag), sizeDynamicTag(sizeDynamicTag), relocsVec(concurrency), combreloc(combreloc) {} -void RelocationBaseSection::addSymbolReloc(RelType dynType, - InputSectionBase &isec, - uint64_t offsetInSec, Symbol &sym, - int64_t addend, - Optional addendRelType) { +void RelocationBaseSection::addSymbolReloc( + RelType dynType, InputSectionBase &isec, uint64_t offsetInSec, Symbol &sym, + int64_t addend, std::optional addendRelType) { addReloc(DynamicReloc::AgainstSymbol, dynType, isec, offsetInSec, sym, addend, R_ADDEND, addendRelType ? *addendRelType : target->noneRel); } @@ -3432,11 +3430,11 @@ } // The .ARM.exidx table must be sorted in ascending order of the address of the -// functions the table describes. Optionally duplicate adjacent table entries -// can be removed. At the end of the function the executableSections must be -// sorted in ascending order of address, Sentinel is set to the InputSection -// with the highest address and any InputSections that have mergeable -// .ARM.exidx table entries are removed from it. +// functions the table describes. std::optionally duplicate adjacent table +// entries can be removed. At the end of the function the executableSections +// must be sorted in ascending order of address, Sentinel is set to the +// InputSection with the highest address and any InputSections that have +// mergeable .ARM.exidx table entries are removed from it. void ARMExidxSyntheticSection::finalizeContents() { // The executableSections and exidxSections that we use to derive the final // contents of this SyntheticSection are populated before @@ -3472,7 +3470,7 @@ }; llvm::stable_sort(executableSections, compareByFilePosition); sentinel = executableSections.back(); - // Optionally merge adjacent duplicate entries. + // std::optionally merge adjacent duplicate entries. if (config->mergeArmExidx) { SmallVector selectedSections; selectedSections.reserve(executableSections.size()); @@ -3638,12 +3636,12 @@ return getVA() + entry_index.find({sym, addend})->second * 8; } -Optional PPC64LongBranchTargetSection::addEntry(const Symbol *sym, - int64_t addend) { +std::optional +PPC64LongBranchTargetSection::addEntry(const Symbol *sym, int64_t addend) { auto res = entry_index.try_emplace(std::make_pair(sym, addend), entries.size()); if (!res.second) - return None; + return std::nullopt; entries.emplace_back(sym, addend); return res.first->second; } diff --git a/lld/ELF/Target.h b/lld/ELF/Target.h --- a/lld/ELF/Target.h +++ b/lld/ELF/Target.h @@ -148,7 +148,7 @@ // Stores the NOP instructions of different sizes for the target and is used // to pad sections that are relaxed. - llvm::Optional>> nopInstrs; + std::optional>> nopInstrs; // If a target needs to rewrite calls to __morestack to instead call // __morestack_non_split when a split-stack enabled caller calls a diff --git a/lld/ELF/Thunks.cpp b/lld/ELF/Thunks.cpp --- a/lld/ELF/Thunks.cpp +++ b/lld/ELF/Thunks.cpp @@ -380,7 +380,7 @@ PPC64PILongBranchThunk(Symbol &dest, int64_t addend) : PPC64LongBranchThunk(dest, addend) { assert(!dest.isPreemptible); - if (Optional index = + if (std::optional index = in.ppc64LongBranchTarget->addEntry(&dest, addend)) { mainPart->relaDyn->addRelativeReloc( target->relativeRel, *in.ppc64LongBranchTarget, *index * UINT64_C(8), diff --git a/lld/MachO/Config.h b/lld/MachO/Config.h --- a/lld/MachO/Config.h +++ b/lld/MachO/Config.h @@ -175,7 +175,7 @@ // they can't easily fix them. llvm::StringSet<> ignoreAutoLinkOptions; PlatformInfo platformInfo; - llvm::Optional secondaryPlatformInfo; + std::optional secondaryPlatformInfo; NamespaceKind namespaceKind = NamespaceKind::twolevel; UndefinedSymbolTreatment undefinedSymbolTreatment = UndefinedSymbolTreatment::error; diff --git a/lld/MachO/Driver.h b/lld/MachO/Driver.h --- a/lld/MachO/Driver.h +++ b/lld/MachO/Driver.h @@ -10,12 +10,12 @@ #define LLD_MACHO_DRIVER_H #include "lld/Common/LLVM.h" -#include "llvm/ADT/Optional.h" #include "llvm/ADT/SetVector.h" #include "llvm/ADT/StringRef.h" #include "llvm/BinaryFormat/MachO.h" #include "llvm/Option/OptTable.h" #include "llvm/Support/MemoryBuffer.h" +#include #include #include @@ -45,7 +45,7 @@ std::string createResponseFile(const llvm::opt::InputArgList &args); // Check for both libfoo.dylib and libfoo.tbd (in that order). -llvm::Optional resolveDylibPath(llvm::StringRef path); +std::optional resolveDylibPath(llvm::StringRef path); DylibFile *loadDylib(llvm::MemoryBufferRef mbref, DylibFile *umbrella = nullptr, bool isBundleLoader = false, @@ -54,7 +54,7 @@ // Search for all possible combinations of `{root}/{name}.{extension}`. // If \p extensions are not specified, then just search for `{root}/{name}`. -llvm::Optional +std::optional findPathCombination(const llvm::Twine &name, const std::vector &roots, ArrayRef extensions = {""}); diff --git a/lld/MachO/Driver.cpp b/lld/MachO/Driver.cpp --- a/lld/MachO/Driver.cpp +++ b/lld/MachO/Driver.cpp @@ -82,7 +82,7 @@ } static DenseMap resolvedLibraries; -static Optional findLibrary(StringRef name) { +static std::optional findLibrary(StringRef name) { CachedHashStringRef key(name); auto entry = resolvedLibraries.find(key); if (entry != resolvedLibraries.end()) @@ -90,7 +90,7 @@ auto doFind = [&] { if (config->searchDylibsFirst) { - if (Optional path = findPathCombination( + if (std::optional path = findPathCombination( "lib" + name, config->librarySearchPaths, {".tbd", ".dylib"})) return path; return findPathCombination("lib" + name, config->librarySearchPaths, @@ -100,7 +100,7 @@ {".tbd", ".dylib", ".a"}); }; - Optional path = doFind(); + std::optional path = doFind(); if (path) resolvedLibraries[key] = *path; @@ -108,7 +108,7 @@ } static DenseMap resolvedFrameworks; -static Optional findFramework(StringRef name) { +static std::optional findFramework(StringRef name) { CachedHashStringRef key(name); auto entry = resolvedFrameworks.find(key); if (entry != resolvedFrameworks.end()) @@ -134,7 +134,7 @@ // Suffix lookup failed, fall through to the no-suffix case. } - if (Optional path = resolveDylibPath(symlink.str())) + if (std::optional path = resolveDylibPath(symlink.str())) return resolvedFrameworks[key] = *path; } return {}; @@ -268,7 +268,7 @@ bool isLazy = false, bool isExplicit = true, bool isBundleLoader = false, bool isForceHidden = false) { - Optional buffer = readFile(path); + std::optional buffer = readFile(path); if (!buffer) return nullptr; MemoryBufferRef mbref = *buffer; @@ -309,7 +309,7 @@ path::filename(path).startswith("libswift"); if ((isCommandLineLoad && config->allLoad) || loadType == LoadType::CommandLineForce || isLCLinkerForceLoad) { - if (Optional buffer = readFile(path)) { + if (std::optional buffer = readFile(path)) { Error e = Error::success(); for (const object::Archive::Child &c : file->getArchive().children(e)) { StringRef reason; @@ -339,7 +339,7 @@ // TODO: no need to look for ObjC sections for a given archive member if // we already found that it contains an ObjC symbol. - if (Optional buffer = readFile(path)) { + if (std::optional buffer = readFile(path)) { Error e = Error::success(); for (const object::Archive::Child &c : file->getArchive().children(e)) { Expected mb = c.getMemoryBufferRef(); @@ -409,7 +409,7 @@ static void addLibrary(StringRef name, bool isNeeded, bool isWeak, bool isReexport, bool isHidden, bool isExplicit, LoadType loadType) { - if (Optional path = findLibrary(name)) { + if (std::optional path = findLibrary(name)) { if (auto *dylibFile = dyn_cast_or_null( addFile(*path, loadType, /*isLazy=*/false, isExplicit, /*isBundleLoader=*/false, isHidden))) { @@ -430,7 +430,7 @@ static DenseSet loadedObjectFrameworks; static void addFramework(StringRef name, bool isNeeded, bool isWeak, bool isReexport, bool isExplicit, LoadType loadType) { - if (Optional path = findFramework(name)) { + if (std::optional path = findFramework(name)) { if (loadedObjectFrameworks.contains(*path)) return; @@ -496,7 +496,7 @@ } static void addFileList(StringRef path, bool isLazy) { - Optional buffer = readFile(path); + std::optional buffer = readFile(path); if (!buffer) return; MemoryBufferRef mbref = *buffer; @@ -1037,7 +1037,7 @@ static void parseSymbolPatternsFile(const Arg *arg, SymbolPatterns &symbolPatterns) { StringRef path = arg->getValue(); - Optional buffer = readFile(path); + std::optional buffer = readFile(path); if (!buffer) { error("Could not read symbol file: " + path); return; @@ -1820,7 +1820,7 @@ StringRef segName = arg->getValue(0); StringRef sectName = arg->getValue(1); StringRef fileName = arg->getValue(2); - Optional buffer = readFile(fileName); + std::optional buffer = readFile(fileName); if (buffer) inputFiles.insert(make(*buffer, segName, sectName)); } diff --git a/lld/MachO/DriverUtils.cpp b/lld/MachO/DriverUtils.cpp --- a/lld/MachO/DriverUtils.cpp +++ b/lld/MachO/DriverUtils.cpp @@ -144,7 +144,7 @@ os << "-o " << quote(path::filename(arg->getValue())) << "\n"; break; case OPT_filelist: - if (Optional buffer = readFile(arg->getValue())) + if (std::optional buffer = readFile(arg->getValue())) for (StringRef path : args::getLines(*buffer)) os << quote(rewriteInputPath(path)) << "\n"; break; @@ -184,7 +184,7 @@ depTracker->logFileNotFound(path); } -Optional macho::resolveDylibPath(StringRef dylibPath) { +std::optional macho::resolveDylibPath(StringRef dylibPath) { // TODO: if a tbd and dylib are both present, we should check to make sure // they are consistent. SmallString<261> tbdPath = dylibPath; @@ -253,7 +253,7 @@ void macho::resetLoadedDylibs() { loadedDylibs.clear(); } -Optional +std::optional macho::findPathCombination(const Twine &name, const std::vector &roots, ArrayRef extensions) { @@ -276,7 +276,7 @@ if (!path::is_absolute(path, path::Style::posix) || path.endswith(".o")) return path; - if (Optional rerootedPath = + if (std::optional rerootedPath = findPathCombination(path, config->systemLibraryRoots)) return *rerootedPath; diff --git a/lld/MachO/Dwarf.h b/lld/MachO/Dwarf.h --- a/lld/MachO/Dwarf.h +++ b/lld/MachO/Dwarf.h @@ -22,10 +22,10 @@ public: bool isLittleEndian() const override { return true; } - llvm::Optional find(const llvm::DWARFSection &sec, - uint64_t pos) const override { + std::optional find(const llvm::DWARFSection &sec, + uint64_t pos) const override { // TODO: implement this - return llvm::None; + return std::nullopt; } void forEachInfoSections( diff --git a/lld/MachO/EhFrame.h b/lld/MachO/EhFrame.h --- a/lld/MachO/EhFrame.h +++ b/lld/MachO/EhFrame.h @@ -46,8 +46,8 @@ * 1. Length of the entry (4 or 12 bytes) * 2. CIE offset (4 bytes pcrel offset that points backwards to this FDE's CIE) * 3. Function address (pointer-sized pcrel offset) - * 4. (Optional) Augmentation data length - * 5. (Optional) LSDA address (pointer-sized pcrel offset) + * 4. (std::optional) Augmentation data length + * 5. (std::optional) LSDA address (pointer-sized pcrel offset) * 6. DWARF instructions (ignored by LLD) */ namespace lld::macho { diff --git a/lld/MachO/ExportTrie.cpp b/lld/MachO/ExportTrie.cpp --- a/lld/MachO/ExportTrie.cpp +++ b/lld/MachO/ExportTrie.cpp @@ -39,9 +39,9 @@ #include "lld/Common/ErrorHandler.h" #include "lld/Common/Memory.h" -#include "llvm/ADT/Optional.h" #include "llvm/BinaryFormat/MachO.h" #include "llvm/Support/LEB128.h" +#include using namespace llvm; using namespace lld; @@ -81,7 +81,7 @@ struct macho::TrieNode { std::vector edges; - Optional info; + std::optional info; // Estimated offset from the start of the serialized trie to the current node. // This will converge to the true offset when updateOffset() is run to a // fixpoint. diff --git a/lld/MachO/InputFiles.h b/lld/MachO/InputFiles.h --- a/lld/MachO/InputFiles.h +++ b/lld/MachO/InputFiles.h @@ -313,7 +313,7 @@ extern llvm::SetVector inputFiles; extern llvm::DenseMap cachedReads; -llvm::Optional readFile(StringRef path); +std::optional readFile(StringRef path); void extract(InputFile &file, StringRef reason); diff --git a/lld/MachO/InputFiles.cpp b/lld/MachO/InputFiles.cpp --- a/lld/MachO/InputFiles.cpp +++ b/lld/MachO/InputFiles.cpp @@ -73,6 +73,7 @@ #include "llvm/TextAPI/Architecture.h" #include "llvm/TextAPI/InterfaceFile.h" +#include #include using namespace llvm; @@ -190,7 +191,7 @@ // would require altering many callers to track the state. DenseMap macho::cachedReads; // Open a given file path and return it as a memory-mapped file. -Optional macho::readFile(StringRef path) { +std::optional macho::readFile(StringRef path) { CachedHashStringRef key(path); auto entry = cachedReads.find(key); if (entry != cachedReads.end()) @@ -258,7 +259,7 @@ // // Note that "record" is a term I came up with. In contrast, "literal" is a term // used by the Mach-O format. -static Optional getRecordSize(StringRef segname, StringRef name) { +static std::optional getRecordSize(StringRef segname, StringRef name) { if (name == section_names::compactUnwind) { if (segname == segment_names::ld) return target->wordSize == 8 ? 32 : 20; @@ -1401,7 +1402,7 @@ ehFrameSection.addr + isecOff + funcAddrOff; uint32_t funcLength = reader.readPointer(&dataOff, cie.funcPtrSize); size_t lsdaAddrOff = 0; // Offset of the LSDA address within the EH frame. - Optional lsdaAddrOpt; + std::optional lsdaAddrOpt; if (cie.fdesHaveAug) { reader.skipLeb128(&dataOff); lsdaAddrOff = dataOff; @@ -1497,7 +1498,7 @@ } // The path can point to either a dylib or a .tbd file. static DylibFile *loadDylib(StringRef path, DylibFile *umbrella) { - Optional mbref = readFile(path); + std::optional mbref = readFile(path); if (!mbref) { error("could not read dylib file at " + path); return nullptr; @@ -1527,10 +1528,11 @@ for (StringRef dir : config->frameworkSearchPaths) { SmallString<128> candidate = dir; path::append(candidate, frameworkName); - if (Optional dylibPath = resolveDylibPath(candidate.str())) + if (std::optional dylibPath = + resolveDylibPath(candidate.str())) return loadDylib(*dylibPath, umbrella); } - } else if (Optional dylibPath = findPathCombination( + } else if (std::optional dylibPath = findPathCombination( stem, config->librarySearchPaths, {".tbd", ".dylib"})) return loadDylib(*dylibPath, umbrella); } @@ -1538,7 +1540,8 @@ // 2. As absolute path. if (path::is_absolute(path, path::Style::posix)) for (StringRef root : config->systemLibraryRoots) - if (Optional dylibPath = resolveDylibPath((root + path).str())) + if (std::optional dylibPath = + resolveDylibPath((root + path).str())) return loadDylib(*dylibPath, umbrella); // 3. As relative path. @@ -1567,7 +1570,7 @@ path::remove_filename(newPath); } path::append(newPath, rpath, path.drop_front(strlen("@rpath/"))); - if (Optional dylibPath = resolveDylibPath(newPath.str())) + if (std::optional dylibPath = resolveDylibPath(newPath.str())) return loadDylib(*dylibPath, umbrella); } } @@ -1586,7 +1589,7 @@ } } - if (Optional dylibPath = resolveDylibPath(path)) + if (std::optional dylibPath = resolveDylibPath(path)) return loadDylib(*dylibPath, umbrella); return nullptr; diff --git a/lld/MachO/InputSection.cpp b/lld/MachO/InputSection.cpp --- a/lld/MachO/InputSection.cpp +++ b/lld/MachO/InputSection.cpp @@ -111,7 +111,7 @@ }; // First, look up a function for a given offset. - if (Optional li = dwarf->getDILineInfo( + if (std::optional li = dwarf->getDILineInfo( section.addr + off, object::SectionedAddress::UndefSection)) return createMsg(li->FileName, li->Line); @@ -123,7 +123,7 @@ if (!symName.empty() && symName[0] == '_') symName = symName.substr(1); - if (Optional> fileLine = + if (std::optional> fileLine = dwarf->getVariableLoc(symName)) return createMsg(fileLine->first, fileLine->second); } diff --git a/lld/MachO/LTO.cpp b/lld/MachO/LTO.cpp --- a/lld/MachO/LTO.cpp +++ b/lld/MachO/LTO.cpp @@ -57,7 +57,7 @@ // If `originalPath` exists, hardlinks `path` to `originalPath`. If that fails, // or `originalPath` is not set, saves `buffer` to `path`. static void saveOrHardlinkBuffer(StringRef buffer, const Twine &path, - Optional originalPath) { + std::optional originalPath) { if (originalPath) { auto err = fs::create_hard_link(*originalPath, path); if (!err) @@ -168,7 +168,7 @@ // not use the cached MemoryBuffer directly to ensure dsymutil does not // race with the cache pruner. StringRef objBuf; - Optional cachePath = llvm::None; + std::optional cachePath = llvm::None; if (files[i]) { objBuf = files[i]->getBuffer(); cachePath = files[i]->getBufferIdentifier(); diff --git a/lld/MachO/SectionPriorities.h b/lld/MachO/SectionPriorities.h --- a/lld/MachO/SectionPriorities.h +++ b/lld/MachO/SectionPriorities.h @@ -69,7 +69,7 @@ llvm::DenseMap objectFiles; }; - llvm::Optional getSymbolPriority(const Defined *sym); + std::optional getSymbolPriority(const Defined *sym); llvm::DenseMap priorities; llvm::MapVector callGraphProfile; }; diff --git a/lld/MachO/SectionPriorities.cpp b/lld/MachO/SectionPriorities.cpp --- a/lld/MachO/SectionPriorities.cpp +++ b/lld/MachO/SectionPriorities.cpp @@ -22,7 +22,6 @@ #include "lld/Common/ErrorHandler.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/MapVector.h" -#include "llvm/ADT/Optional.h" #include "llvm/Support/Path.h" #include "llvm/Support/TimeProfiler.h" #include "llvm/Support/raw_ostream.h" @@ -250,7 +249,8 @@ return orderMap; } -Optional macho::PriorityBuilder::getSymbolPriority(const Defined *sym) { +std::optional +macho::PriorityBuilder::getSymbolPriority(const Defined *sym) { if (sym->isAbsolute()) return None; @@ -295,7 +295,7 @@ void macho::PriorityBuilder::parseOrderFile(StringRef path) { assert(callGraphProfile.empty() && "Order file must be parsed before call graph profile is processed"); - Optional buffer = readFile(path); + std::optional buffer = readFile(path); if (!buffer) { error("Could not read order file at " + path); return; @@ -367,7 +367,7 @@ return sectionPriorities; auto addSym = [&](const Defined *sym) { - Optional symbolPriority = getSymbolPriority(sym); + std::optional symbolPriority = getSymbolPriority(sym); if (!symbolPriority) return; size_t &priority = sectionPriorities[sym->isec]; diff --git a/lld/cmake/modules/LLDConfig.cmake.in b/lld/cmake/modules/LLDConfig.cmake.in --- a/lld/cmake/modules/LLDConfig.cmake.in +++ b/lld/cmake/modules/LLDConfig.cmake.in @@ -2,8 +2,8 @@ @LLD_CONFIG_CODE@ -set(LLVM_VERSION ${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}.${LLVM_VERSION_PATCH}) -find_package(LLVM @LLVM_VERSION@ EXACT REQUIRED CONFIG +set(LLVM_VERSION @LLVM_VERSION_MAJOR@.@LLVM_VERSION_MINOR@.@LLVM_VERSION_PATCH@) +find_package(LLVM ${LLVM_VERSION} EXACT REQUIRED CONFIG HINTS "@LLD_CONFIG_LLVM_CMAKE_DIR@") set(LLD_EXPORTED_TARGETS "@LLD_EXPORTS@") diff --git a/lld/include/lld/Common/DWARF.h b/lld/include/lld/Common/DWARF.h --- a/lld/include/lld/Common/DWARF.h +++ b/lld/include/lld/Common/DWARF.h @@ -26,9 +26,9 @@ class DWARFCache { public: DWARFCache(std::unique_ptr dwarf); - llvm::Optional getDILineInfo(uint64_t offset, - uint64_t sectionIndex); - llvm::Optional> + std::optional getDILineInfo(uint64_t offset, + uint64_t sectionIndex); + std::optional> getVariableLoc(StringRef name); llvm::DWARFContext *getContext() { return dwarf.get(); } diff --git a/lld/test/COFF/Inputs/failmismatch2.ll b/lld/test/COFF/Inputs/failmismatch2.ll --- a/lld/test/COFF/Inputs/failmismatch2.ll +++ b/lld/test/COFF/Inputs/failmismatch2.ll @@ -3,7 +3,7 @@ ; Function Attrs: noinline norecurse nounwind optnone sspstrong uwtable define dso_local i32 @main() #0 { %1 = alloca i32, align 4 - store i32 0, i32* %1, align 4 + store i32 0, ptr %1, align 4 %2 = call i32 @"?f@@YAHXZ"() ret i32 %2 } diff --git a/lld/test/COFF/Inputs/thinlto-mangled-qux.ll b/lld/test/COFF/Inputs/thinlto-mangled-qux.ll --- a/lld/test/COFF/Inputs/thinlto-mangled-qux.ll +++ b/lld/test/COFF/Inputs/thinlto-mangled-qux.ll @@ -2,7 +2,7 @@ target triple = "x86_64-pc-windows-msvc19.0.24215" %class.baz = type { %class.bar } -%class.bar = type { i32 (...)** } +%class.bar = type { ptr } $"\01?x@bar@@UEBA_NXZ" = comdat any @@ -10,17 +10,17 @@ $"\01??_Gbaz@@UEAAPEAXI@Z" = comdat any -@"\01??_7baz@@6B@" = linkonce_odr unnamed_addr constant { [2 x i8*] } { [2 x i8*] [i8* bitcast (i8* (%class.baz*, i32)* @"\01??_Gbaz@@UEAAPEAXI@Z" to i8*), i8* bitcast (i1 (%class.bar*)* @"\01?x@bar@@UEBA_NXZ" to i8*)] }, comdat, !type !0, !type !1 +@"\01??_7baz@@6B@" = linkonce_odr unnamed_addr constant { [2 x ptr] } { [2 x ptr] [ptr @"\01??_Gbaz@@UEAAPEAXI@Z", ptr @"\01?x@bar@@UEBA_NXZ"] }, comdat, !type !0, !type !1 define void @"\01?qux@@YAXXZ"() local_unnamed_addr { ret void } -define linkonce_odr i8* @"\01??_Gbaz@@UEAAPEAXI@Z"(%class.baz* %this, i32 %should_call_delete) unnamed_addr comdat { - ret i8* null +define linkonce_odr ptr @"\01??_Gbaz@@UEAAPEAXI@Z"(ptr %this, i32 %should_call_delete) unnamed_addr comdat { + ret ptr null } -define linkonce_odr zeroext i1 @"\01?x@bar@@UEBA_NXZ"(%class.bar* %this) unnamed_addr comdat { +define linkonce_odr zeroext i1 @"\01?x@bar@@UEBA_NXZ"(ptr %this) unnamed_addr comdat { ret i1 false } diff --git a/lld/test/COFF/Inputs/tlssup-32.ll b/lld/test/COFF/Inputs/tlssup-32.ll --- a/lld/test/COFF/Inputs/tlssup-32.ll +++ b/lld/test/COFF/Inputs/tlssup-32.ll @@ -17,9 +17,9 @@ @_tls_index = global i32 0 @_tls_used = global %IMAGE_TLS_DIRECTORY32 { - i32 ptrtoint (i8* @_tls_start to i32), - i32 ptrtoint (i8* @_tls_end to i32), - i32 ptrtoint (i32* @_tls_index to i32), + i32 ptrtoint (ptr @_tls_start to i32), + i32 ptrtoint (ptr @_tls_end to i32), + i32 ptrtoint (ptr @_tls_index to i32), i32 0, i32 0, i32 0 diff --git a/lld/test/COFF/Inputs/tlssup-64.ll b/lld/test/COFF/Inputs/tlssup-64.ll --- a/lld/test/COFF/Inputs/tlssup-64.ll +++ b/lld/test/COFF/Inputs/tlssup-64.ll @@ -17,10 +17,10 @@ @_tls_index = global i64 0 @_tls_used = global %IMAGE_TLS_DIRECTORY64 { - i64 ptrtoint (i8* @_tls_start to i64), - i64 ptrtoint (i8* @_tls_end to i64), - i64 ptrtoint (i64* @_tls_index to i64), + i64 ptrtoint (ptr @_tls_start to i64), + i64 ptrtoint (ptr @_tls_end to i64), + i64 ptrtoint (ptr @_tls_index to i64), i64 0, i32 0, i32 0 }, section ".rdata$T" \ No newline at end of file diff --git a/lld/test/COFF/Inputs/undefined-symbol-lto-a.ll b/lld/test/COFF/Inputs/undefined-symbol-lto-a.ll --- a/lld/test/COFF/Inputs/undefined-symbol-lto-a.ll +++ b/lld/test/COFF/Inputs/undefined-symbol-lto-a.ll @@ -4,9 +4,9 @@ target triple = "x86_64-pc-windows-msvc19.21.27702" %struct.Init = type { %struct.S } -%struct.S = type { i32 (...)** } +%struct.S = type { ptr } %rtti.CompleteObjectLocator = type { i32, i32, i32, i32, i32, i32 } -%rtti.TypeDescriptor7 = type { i8**, i8*, [8 x i8] } +%rtti.TypeDescriptor7 = type { ptr, ptr, [8 x i8] } %rtti.ClassHierarchyDescriptor = type { i32, i32, i32, i32 } %rtti.BaseClassDescriptor = type { i32, i32, i32, i32, i32, i32, i32 } @@ -23,26 +23,26 @@ $"??_R1A@?0A@EA@S@@8" = comdat any @"?d@@3UInit@@A" = dso_local local_unnamed_addr global %struct.Init zeroinitializer, align 8 -@anon.bcb2691509de99310dddb690fcdb4cdc.0 = private unnamed_addr constant { [2 x i8*] } { [2 x i8*] [i8* bitcast (%rtti.CompleteObjectLocator* @"??_R4S@@6B@" to i8*), i8* bitcast (void (%struct.S*)* @"?foo@S@@UEAAXXZ" to i8*)] }, comdat($"??_SS@@6B@"), !type !0 -@"??_R4S@@6B@" = linkonce_odr constant %rtti.CompleteObjectLocator { i32 1, i32 0, i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor7* @"??_R0?AUS@@@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.ClassHierarchyDescriptor* @"??_R3S@@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.CompleteObjectLocator* @"??_R4S@@6B@" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, comdat -@"??_7type_info@@6B@" = external constant i8* -@"??_R0?AUS@@@8" = linkonce_odr global %rtti.TypeDescriptor7 { i8** @"??_7type_info@@6B@", i8* null, [8 x i8] c".?AUS@@\00" }, comdat +@anon.bcb2691509de99310dddb690fcdb4cdc.0 = private unnamed_addr constant { [2 x ptr] } { [2 x ptr] [ptr @"??_R4S@@6B@", ptr @"?foo@S@@UEAAXXZ"] }, comdat($"??_SS@@6B@"), !type !0 +@"??_R4S@@6B@" = linkonce_odr constant %rtti.CompleteObjectLocator { i32 1, i32 0, i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (ptr @"??_R0?AUS@@@8" to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32), i32 trunc (i64 sub nuw nsw (i64 ptrtoint (ptr @"??_R3S@@8" to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32), i32 trunc (i64 sub nuw nsw (i64 ptrtoint (ptr @"??_R4S@@6B@" to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32) }, comdat +@"??_7type_info@@6B@" = external constant ptr +@"??_R0?AUS@@@8" = linkonce_odr global %rtti.TypeDescriptor7 { ptr @"??_7type_info@@6B@", ptr null, [8 x i8] c".?AUS@@\00" }, comdat @__ImageBase = external dso_local constant i8 -@"??_R3S@@8" = linkonce_odr constant %rtti.ClassHierarchyDescriptor { i32 0, i32 0, i32 1, i32 trunc (i64 sub nuw nsw (i64 ptrtoint ([2 x i32]* @"??_R2S@@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, comdat -@"??_R2S@@8" = linkonce_odr constant [2 x i32] [i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.BaseClassDescriptor* @"??_R1A@?0A@EA@S@@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 0], comdat -@"??_R1A@?0A@EA@S@@8" = linkonce_odr constant %rtti.BaseClassDescriptor { i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor7* @"??_R0?AUS@@@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 0, i32 0, i32 -1, i32 0, i32 64, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.ClassHierarchyDescriptor* @"??_R3S@@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, comdat -@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @_GLOBAL__sub_I_t.cpp, i8* null }] +@"??_R3S@@8" = linkonce_odr constant %rtti.ClassHierarchyDescriptor { i32 0, i32 0, i32 1, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (ptr @"??_R2S@@8" to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32) }, comdat +@"??_R2S@@8" = linkonce_odr constant [2 x i32] [i32 trunc (i64 sub nuw nsw (i64 ptrtoint (ptr @"??_R1A@?0A@EA@S@@8" to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32), i32 0], comdat +@"??_R1A@?0A@EA@S@@8" = linkonce_odr constant %rtti.BaseClassDescriptor { i32 trunc (i64 sub nuw nsw (i64 ptrtoint (ptr @"??_R0?AUS@@@8" to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32), i32 0, i32 0, i32 -1, i32 0, i32 64, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (ptr @"??_R3S@@8" to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32) }, comdat +@llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_t.cpp, ptr null }] -@"??_SS@@6B@" = unnamed_addr alias i8*, getelementptr inbounds ({ [2 x i8*] }, { [2 x i8*] }* @anon.bcb2691509de99310dddb690fcdb4cdc.0, i32 0, i32 0, i32 1) +@"??_SS@@6B@" = unnamed_addr alias ptr, getelementptr inbounds ({ [2 x ptr] }, ptr @anon.bcb2691509de99310dddb690fcdb4cdc.0, i32 0, i32 0, i32 1) declare dso_local void @"?undefined_ref@@YAXXZ"() local_unnamed_addr #0 -declare dllimport void @"?foo@S@@UEAAXXZ"(%struct.S*) unnamed_addr #0 +declare dllimport void @"?foo@S@@UEAAXXZ"(ptr) unnamed_addr #0 ; Function Attrs: nounwind sspstrong uwtable define internal void @_GLOBAL__sub_I_t.cpp() #1 { entry: - store i32 (...)** bitcast (i8** @"??_SS@@6B@" to i32 (...)**), i32 (...)*** getelementptr inbounds (%struct.Init, %struct.Init* @"?d@@3UInit@@A", i64 0, i32 0, i32 0), align 8 + store ptr @"??_SS@@6B@", ptr @"?d@@3UInit@@A", align 8 tail call void @"?undefined_ref@@YAXXZ"() #2 ret void } diff --git a/lld/test/COFF/Inputs/undefined-symbol-lto-b.ll b/lld/test/COFF/Inputs/undefined-symbol-lto-b.ll --- a/lld/test/COFF/Inputs/undefined-symbol-lto-b.ll +++ b/lld/test/COFF/Inputs/undefined-symbol-lto-b.ll @@ -3,10 +3,10 @@ target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-windows-msvc19.21.27702" -%struct.S = type { i32 (...)** } +%struct.S = type { ptr } ; Function Attrs: norecurse nounwind readnone sspstrong uwtable -define dso_local void @"?foo@S@@UEAAXXZ"(%struct.S* nocapture %this) unnamed_addr #0 align 2 { +define dso_local void @"?foo@S@@UEAAXXZ"(ptr nocapture %this) unnamed_addr #0 align 2 { entry: ret void } diff --git a/lld/test/COFF/Inputs/weak-external3.ll b/lld/test/COFF/Inputs/weak-external3.ll --- a/lld/test/COFF/Inputs/weak-external3.ll +++ b/lld/test/COFF/Inputs/weak-external3.ll @@ -1,7 +1,7 @@ target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-windows-msvc" -@f = weak alias void(), void()* @g +@f = weak alias void(), ptr @g define void @g() { ret void diff --git a/lld/test/COFF/autoimport-lto.ll b/lld/test/COFF/autoimport-lto.ll --- a/lld/test/COFF/autoimport-lto.ll +++ b/lld/test/COFF/autoimport-lto.ll @@ -23,6 +23,6 @@ define i32 @entry() { entry: - %0 = load i32, i32* @variable + %0 = load i32, ptr @variable ret i32 %0 } diff --git a/lld/test/COFF/guardcf-lto.ll b/lld/test/COFF/guardcf-lto.ll --- a/lld/test/COFF/guardcf-lto.ll +++ b/lld/test/COFF/guardcf-lto.ll @@ -30,11 +30,11 @@ target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-windows-msvc19.12.25835" -declare dllimport void @do_indirect_call(void ()*) +declare dllimport void @do_indirect_call(ptr) define dso_local i32 @main() local_unnamed_addr { entry: - tail call void @do_indirect_call(void ()* nonnull @my_handler) + tail call void @do_indirect_call(ptr nonnull @my_handler) ret i32 0 } diff --git a/lld/test/COFF/libcall-archive.ll b/lld/test/COFF/libcall-archive.ll --- a/lld/test/COFF/libcall-archive.ll +++ b/lld/test/COFF/libcall-archive.ll @@ -13,10 +13,10 @@ target datalayout = "e-m:x-p:32:32-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:32-n8:16:32-a:0:32-S32" target triple = "i686-unknown-windows" -define void @start(i8* %a, i8* %b) { +define void @start(ptr %a, ptr %b) { entry: - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 1024, i1 false) + call void @llvm.memcpy.p0.p0.i64(ptr %a, ptr %b, i64 1024, i1 false) ret void } -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) +declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) diff --git a/lld/test/COFF/lto-chkstk.ll b/lld/test/COFF/lto-chkstk.ll --- a/lld/test/COFF/lto-chkstk.ll +++ b/lld/test/COFF/lto-chkstk.ll @@ -12,8 +12,8 @@ define void @main() { entry: %array4096 = alloca [4096 x i8] - call void @foo([4096 x i8]* %array4096) + call void @foo(ptr %array4096) ret void } -declare void @foo([4096 x i8]*) +declare void @foo(ptr) diff --git a/lld/test/COFF/lto-icf.ll b/lld/test/COFF/lto-icf.ll --- a/lld/test/COFF/lto-icf.ll +++ b/lld/test/COFF/lto-icf.ll @@ -15,9 +15,9 @@ target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-windows-msvc19.12.25835" -define dllexport i8* @icf_ptr() { +define dllexport ptr @icf_ptr() { entry: - ret i8* null + ret ptr null } define dllexport i64 @icf_int() { diff --git a/lld/test/COFF/lto-new-pass-manager.ll b/lld/test/COFF/lto-new-pass-manager.ll --- a/lld/test/COFF/lto-new-pass-manager.ll +++ b/lld/test/COFF/lto-new-pass-manager.ll @@ -7,7 +7,7 @@ target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-windows-msvc19.11.0" -define dso_local i32 @main(i32 %argc, i8** nocapture readnone %0) local_unnamed_addr { +define dso_local i32 @main(i32 %argc, ptr nocapture readnone %0) local_unnamed_addr { entry: ret i32 %argc } diff --git a/lld/test/COFF/lto-new-symbol.ll b/lld/test/COFF/lto-new-symbol.ll --- a/lld/test/COFF/lto-new-symbol.ll +++ b/lld/test/COFF/lto-new-symbol.ll @@ -9,12 +9,12 @@ ; using floats. @_fltused = dllexport global i32 0, align 4 -define void @foo(<4 x i32>* %p, <4 x float>* %q, i1 %t) nounwind { +define void @foo(ptr %p, ptr %q, i1 %t) nounwind { entry: br label %loop loop: - store <4 x i32>, <4 x i32>* %p - store <4 x float>, <4 x float>* %q + store <4 x i32>, ptr %p + store <4 x float>, ptr %q br i1 %t, label %loop, label %ret ret: ret void diff --git a/lld/test/COFF/lto-reloc-model.ll b/lld/test/COFF/lto-reloc-model.ll --- a/lld/test/COFF/lto-reloc-model.ll +++ b/lld/test/COFF/lto-reloc-model.ll @@ -11,10 +11,10 @@ module asm "__tls_index = 1" module asm "__tls_array = 2" -define i8* @main() { +define ptr @main() { ; CHECK: movl 1, %eax ; CHECK: movl %fs:2, %ecx ; CHECK: movl (%ecx,%eax,4), %eax ; CHECK: leal (%eax), %eax - ret i8* @foo + ret ptr @foo } diff --git a/lld/test/COFF/pdb_char8_t.ll b/lld/test/COFF/pdb_char8_t.ll --- a/lld/test/COFF/pdb_char8_t.ll +++ b/lld/test/COFF/pdb_char8_t.ll @@ -8,10 +8,10 @@ define dso_local i32 @main() #0 !dbg !9 { %1 = alloca i32, align 4 %2 = alloca i8, align 1 - store i32 0, i32* %1, align 4 - call void @llvm.dbg.declare(metadata i8* %2, metadata !13, metadata !DIExpression()), !dbg !15 - store i8 0, i8* %2, align 1, !dbg !15 - %3 = load i8, i8* %2, align 1, !dbg !16 + store i32 0, ptr %1, align 4 + call void @llvm.dbg.declare(metadata ptr %2, metadata !13, metadata !DIExpression()), !dbg !15 + store i8 0, ptr %2, align 1, !dbg !15 + %3 = load i8, ptr %2, align 1, !dbg !16 %4 = zext i8 %3 to i32, !dbg !16 ret i32 %4, !dbg !16 } diff --git a/lld/test/COFF/thinlto-mangled.ll b/lld/test/COFF/thinlto-mangled.ll --- a/lld/test/COFF/thinlto-mangled.ll +++ b/lld/test/COFF/thinlto-mangled.ll @@ -6,12 +6,12 @@ target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-windows-msvc19.0.24215" -%"class.bar" = type { i32 (...)**, i8*, i8*, i8*, i32 } +%"class.bar" = type { ptr, ptr, ptr, ptr, i32 } define i32 @main() { ret i32 0 } -define available_externally zeroext i1 @"\01?x@bar@@UEBA_NXZ"(%"class.bar"* %this) unnamed_addr align 2 { +define available_externally zeroext i1 @"\01?x@bar@@UEBA_NXZ"(ptr %this) unnamed_addr align 2 { ret i1 false } diff --git a/lld/test/COFF/tls-alignment-32.ll b/lld/test/COFF/tls-alignment-32.ll --- a/lld/test/COFF/tls-alignment-32.ll +++ b/lld/test/COFF/tls-alignment-32.ll @@ -21,6 +21,6 @@ @aligned_thread_local = thread_local global i32 42, align 32 define i32 @main() { - %t = load i32, i32* @aligned_thread_local + %t = load i32, ptr @aligned_thread_local ret i32 %t } diff --git a/lld/test/COFF/tls-alignment-64.ll b/lld/test/COFF/tls-alignment-64.ll --- a/lld/test/COFF/tls-alignment-64.ll +++ b/lld/test/COFF/tls-alignment-64.ll @@ -21,6 +21,6 @@ @aligned_thread_local = thread_local global i32 42, align 64 define i32 @main() { - %t = load i32, i32* @aligned_thread_local + %t = load i32, ptr @aligned_thread_local ret i32 %t } diff --git a/lld/test/COFF/used-lto.ll b/lld/test/COFF/used-lto.ll --- a/lld/test/COFF/used-lto.ll +++ b/lld/test/COFF/used-lto.ll @@ -8,7 +8,7 @@ target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-windows-msvc" -@llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @foo to i8*)], section "llvm.metadata" +@llvm.used = appending global [1 x ptr] [ptr @foo], section "llvm.metadata" define void @foo() { ret void diff --git a/lld/test/ELF/Inputs/exclude-libs.ll b/lld/test/ELF/Inputs/exclude-libs.ll --- a/lld/test/ELF/Inputs/exclude-libs.ll +++ b/lld/test/ELF/Inputs/exclude-libs.ll @@ -1,3 +1,3 @@ target triple = "x86_64-unknown-linux" -@fn2 = global void()* null; +@fn2 = global ptr null; diff --git a/lld/test/ELF/common-archive-lookup.s b/lld/test/ELF/common-archive-lookup.s --- a/lld/test/ELF/common-archive-lookup.s +++ b/lld/test/ELF/common-archive-lookup.s @@ -193,7 +193,7 @@ define dso_local i32 @bar(i32 signext %i) local_unnamed_addr { entry: %idxprom = sext i32 %i to i64 - %arrayidx = getelementptr inbounds [5 x i32], [5 x i32]* @block, i64 0, i64 %idxprom - %0 = load i32, i32* %arrayidx, align 8 + %arrayidx = getelementptr inbounds [5 x i32], ptr @block, i64 0, i64 %idxprom + %0 = load i32, ptr %arrayidx, align 8 ret i32 %0 } diff --git a/lld/test/ELF/lto/Inputs/devirt_vcall_vis_shared_def.ll b/lld/test/ELF/lto/Inputs/devirt_vcall_vis_shared_def.ll --- a/lld/test/ELF/lto/Inputs/devirt_vcall_vis_shared_def.ll +++ b/lld/test/ELF/lto/Inputs/devirt_vcall_vis_shared_def.ll @@ -1,15 +1,15 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } -@_ZTV1A = unnamed_addr constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !vcall_visibility !1 +@_ZTV1A = unnamed_addr constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1A1fEi, ptr @_ZN1A1nEi] }, !type !0, !vcall_visibility !1 -define i32 @_ZN1A1fEi(%struct.A* %this, i32 %a) #0 { +define i32 @_ZN1A1fEi(ptr %this, i32 %a) #0 { ret i32 0; } -define i32 @_ZN1A1nEi(%struct.A* %this, i32 %a) #0 { +define i32 @_ZN1A1nEi(ptr %this, i32 %a) #0 { ret i32 0; } diff --git a/lld/test/ELF/lto/Inputs/thin1.ll b/lld/test/ELF/lto/Inputs/thin1.ll --- a/lld/test/ELF/lto/Inputs/thin1.ll +++ b/lld/test/ELF/lto/Inputs/thin1.ll @@ -4,9 +4,9 @@ define i32 @foo(i32 %goo) { entry: %goo.addr = alloca i32, align 4 - store i32 %goo, i32* %goo.addr, align 4 - %0 = load i32, i32* %goo.addr, align 4 - %1 = load i32, i32* %goo.addr, align 4 + store i32 %goo, ptr %goo.addr, align 4 + %0 = load i32, ptr %goo.addr, align 4 + %1 = load i32, ptr %goo.addr, align 4 %mul = mul nsw i32 %0, %1 ret i32 %mul } diff --git a/lld/test/ELF/lto/Inputs/thin2.ll b/lld/test/ELF/lto/Inputs/thin2.ll --- a/lld/test/ELF/lto/Inputs/thin2.ll +++ b/lld/test/ELF/lto/Inputs/thin2.ll @@ -4,8 +4,8 @@ define i32 @blah(i32 %meh) #0 { entry: %meh.addr = alloca i32, align 4 - store i32 %meh, i32* %meh.addr, align 4 - %0 = load i32, i32* %meh.addr, align 4 + store i32 %meh, ptr %meh.addr, align 4 + %0 = load i32, ptr %meh.addr, align 4 %sub = sub nsw i32 %0, 48 ret i32 %sub } diff --git a/lld/test/ELF/lto/Inputs/type-merge2.ll b/lld/test/ELF/lto/Inputs/type-merge2.ll --- a/lld/test/ELF/lto/Inputs/type-merge2.ll +++ b/lld/test/ELF/lto/Inputs/type-merge2.ll @@ -2,7 +2,7 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" %zed = type { i16 } -define void @bar(%zed* %this) { - store %zed* %this, %zed** null +define void @bar(ptr %this) { + store ptr %this, ptr null ret void } diff --git a/lld/test/ELF/lto/Inputs/weakodr-visibility.ll b/lld/test/ELF/lto/Inputs/weakodr-visibility.ll --- a/lld/test/ELF/lto/Inputs/weakodr-visibility.ll +++ b/lld/test/ELF/lto/Inputs/weakodr-visibility.ll @@ -1,6 +1,6 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define weak_odr protected i32 @foo(i8* %this) { +define weak_odr protected i32 @foo(ptr %this) { ret i32 42 } diff --git a/lld/test/ELF/lto/abs-resol.ll b/lld/test/ELF/lto/abs-resol.ll --- a/lld/test/ELF/lto/abs-resol.ll +++ b/lld/test/ELF/lto/abs-resol.ll @@ -12,6 +12,6 @@ @blah = external global i8, align 1 -define i8* @_start() { - ret i8* @blah +define ptr @_start() { + ret ptr @blah } diff --git a/lld/test/ELF/lto/arm-wrap-personality.ll b/lld/test/ELF/lto/arm-wrap-personality.ll --- a/lld/test/ELF/lto/arm-wrap-personality.ll +++ b/lld/test/ELF/lto/arm-wrap-personality.ll @@ -22,13 +22,13 @@ ret i32 0 } -define void @dummy() optnone noinline personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +define void @dummy() optnone noinline personality ptr @__gxx_personality_v0 { invoke void @dummy() to label %cont unwind label %lpad cont: ret void lpad: - %lp = landingpad { i8*, i32 } cleanup - resume { i8*, i32 } %lp + %lp = landingpad { ptr, i32 } cleanup + resume { ptr, i32 } %lp } diff --git a/lld/test/ELF/lto/codemodel.ll b/lld/test/ELF/lto/codemodel.ll --- a/lld/test/ELF/lto/codemodel.ll +++ b/lld/test/ELF/lto/codemodel.ll @@ -10,11 +10,11 @@ @data = internal constant [0 x i32] [] -define i32* @_start() nounwind readonly { +define ptr @_start() nounwind readonly { entry: ; CHECK-SMALL-LABEL: <_start>: ; CHECK-SMALL: movl $2097440, %eax ; CHECK-LARGE-LABEL: <_start>: ; CHECK-LARGE: movabsq $2097440, %rax - ret i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0) + ret ptr @data } diff --git a/lld/test/ELF/lto/comdat-nodeduplicate.ll b/lld/test/ELF/lto/comdat-nodeduplicate.ll --- a/lld/test/ELF/lto/comdat-nodeduplicate.ll +++ b/lld/test/ELF/lto/comdat-nodeduplicate.ll @@ -72,14 +72,14 @@ $__profc_foo = comdat nodeduplicate @__profc_foo = private global i64 1, comdat, align 8 -@__profd_foo = private global i64* @__profc_foo, comdat($__profc_foo), align 8 +@__profd_foo = private global ptr @__profc_foo, comdat($__profc_foo), align 8 declare void @b() define i64 @foo() { - %v = load i64, i64* @__profc_foo + %v = load i64, ptr @__profc_foo %inc = add i64 1, %v - store i64 %inc, i64* @__profc_foo + store i64 %inc, ptr @__profc_foo ret i64 %inc } @@ -94,12 +94,12 @@ $__profc_foo = comdat nodeduplicate @__profc_foo = weak hidden global i64 2, comdat, align 8 -@__profd_foo = private global i64* @__profc_foo, comdat($__profc_foo) +@__profd_foo = private global ptr @__profc_foo, comdat($__profc_foo) define weak i64 @foo() { - %v = load i64, i64* @__profc_foo + %v = load i64, ptr @__profc_foo %inc = add i64 1, %v - store i64 %inc, i64* @__profc_foo + store i64 %inc, ptr @__profc_foo ret i64 %inc } @@ -113,12 +113,12 @@ $__profc_foo = comdat nodeduplicate @__profc_foo = weak hidden global i64 3, comdat, align 8 -@__profd_foo = private global i64* @__profc_foo, comdat($__profc_foo) +@__profd_foo = private global ptr @__profc_foo, comdat($__profc_foo) define weak i64 @foo() { - %v = load i64, i64* @__profc_foo + %v = load i64, ptr @__profc_foo %inc = add i64 1, %v - store i64 %inc, i64* @__profc_foo + store i64 %inc, ptr @__profc_foo ret i64 %inc } diff --git a/lld/test/ELF/lto/common2.ll b/lld/test/ELF/lto/common2.ll --- a/lld/test/ELF/lto/common2.ll +++ b/lld/test/ELF/lto/common2.ll @@ -12,7 +12,7 @@ @b = common hidden global i32 0, align 4 define i32 @f() { - %t = load i32, i32* @b, align 4 + %t = load i32, ptr @b, align 4 ret i32 %t } ; CHECK-DAG: @b = internal global i32 0, align 4 diff --git a/lld/test/ELF/lto/common3.ll b/lld/test/ELF/lto/common3.ll --- a/lld/test/ELF/lto/common3.ll +++ b/lld/test/ELF/lto/common3.ll @@ -8,7 +8,7 @@ target triple = "x86_64-unknown-linux-gnu" @a = common hidden global i32 0, align 8 define i32 @f() { - %t = load i32, i32* @a, align 4 + %t = load i32, ptr @a, align 4 ret i32 %t } diff --git a/lld/test/ELF/lto/ctors.ll b/lld/test/ELF/lto/ctors.ll --- a/lld/test/ELF/lto/ctors.ll +++ b/lld/test/ELF/lto/ctors.ll @@ -6,7 +6,7 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @ctor, i8* null }] +@llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @ctor, ptr null }] define void @ctor() { call void asm "nop", ""() ret void diff --git a/lld/test/ELF/lto/devirt_split_unit_localize.ll b/lld/test/ELF/lto/devirt_split_unit_localize.ll --- a/lld/test/ELF/lto/devirt_split_unit_localize.ll +++ b/lld/test/ELF/lto/devirt_split_unit_localize.ll @@ -23,50 +23,47 @@ target triple = "x86_64-unknown-linux-gnu" %struct.Cat = type { %struct.Animal } -%struct.Animal = type { i32 (...)** } +%struct.Animal = type { ptr } $_ZTS6Animal = comdat any $_ZTI6Animal = comdat any @.str = private unnamed_addr constant [5 x i8] c"Meow\00", align 1 -@_ZTV3Cat = dso_local unnamed_addr constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* bitcast ({ i8*, i8*, i8* }* @_ZTI3Cat to i8*), i8* bitcast (void (%struct.Cat*)* @_ZNK3Cat9makeNoiseEv to i8*)] }, align 8, !type !0, !type !1, !type !2, !type !3 -@_ZTVN10__cxxabiv120__si_class_type_infoE = external dso_local global i8* +@_ZTV3Cat = dso_local unnamed_addr constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr @_ZTI3Cat, ptr @_ZNK3Cat9makeNoiseEv] }, align 8, !type !0, !type !1, !type !2, !type !3 +@_ZTVN10__cxxabiv120__si_class_type_infoE = external dso_local global ptr @_ZTS3Cat = dso_local constant [5 x i8] c"3Cat\00", align 1 -@_ZTVN10__cxxabiv117__class_type_infoE = external dso_local global i8* +@_ZTVN10__cxxabiv117__class_type_infoE = external dso_local global ptr @_ZTS6Animal = linkonce_odr dso_local constant [8 x i8] c"6Animal\00", comdat, align 1 -@_ZTI6Animal = linkonce_odr dso_local constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([8 x i8], [8 x i8]* @_ZTS6Animal, i32 0, i32 0) }, comdat, align 8 -@_ZTI3Cat = dso_local constant { i8*, i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv120__si_class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @_ZTS3Cat, i32 0, i32 0), i8* bitcast ({ i8*, i8* }* @_ZTI6Animal to i8*) }, align 8 +@_ZTI6Animal = linkonce_odr dso_local constant { ptr, ptr } { ptr getelementptr inbounds (ptr, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 2), ptr @_ZTS6Animal }, comdat, align 8 +@_ZTI3Cat = dso_local constant { ptr, ptr, ptr } { ptr getelementptr inbounds (ptr, ptr @_ZTVN10__cxxabiv120__si_class_type_infoE, i64 2), ptr @_ZTS3Cat, ptr @_ZTI6Animal }, align 8 -define dso_local void @_ZNK3Cat9makeNoiseEv(%struct.Cat* nocapture nonnull readnone dereferenceable(8) %this) unnamed_addr align 2 { +define dso_local void @_ZNK3Cat9makeNoiseEv(ptr nocapture nonnull readnone dereferenceable(8) %this) unnamed_addr align 2 { entry: - %call = tail call i32 @puts(i8* nonnull dereferenceable(1) getelementptr inbounds ([5 x i8], [5 x i8]* @.str, i64 0, i64 0)) + %call = tail call i32 @puts(ptr nonnull dereferenceable(1) @.str) ret void } -declare dso_local noundef i32 @puts(i8* nocapture noundef readonly) local_unnamed_addr +declare dso_local noundef i32 @puts(ptr nocapture noundef readonly) local_unnamed_addr -define dso_local void @_Z14doThingWithCatP6Animal(%struct.Animal* %a) local_unnamed_addr { +define dso_local void @_Z14doThingWithCatP6Animal(ptr %a) local_unnamed_addr { entry: - %tobool.not = icmp eq %struct.Animal* %a, null + %tobool.not = icmp eq ptr %a, null br i1 %tobool.not, label %if.end, label %if.then if.then: ; preds = %entry - %0 = bitcast %struct.Animal* %a to %struct.Cat* - %1 = bitcast %struct.Animal* %a to void (%struct.Cat*)*** - %vtable = load void (%struct.Cat*)**, void (%struct.Cat*)*** %1, align 8, !tbaa !4 - %2 = bitcast void (%struct.Cat*)** %vtable to i8* - %3 = tail call i1 @llvm.type.test(i8* %2, metadata !"_ZTS3Cat") - tail call void @llvm.assume(i1 %3) - %4 = load void (%struct.Cat*)*, void (%struct.Cat*)** %vtable, align 8 - tail call void %4(%struct.Cat* nonnull dereferenceable(8) %0) + %vtable = load ptr, ptr %a, align 8, !tbaa !4 + %0 = tail call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS3Cat") + tail call void @llvm.assume(i1 %0) + %1 = load ptr, ptr %vtable, align 8 + tail call void %1(ptr nonnull dereferenceable(8) %a) br label %if.end if.end: ; preds = %if.then, %entry ret void } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1 noundef) @@ -82,28 +79,26 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -%struct.Animal = type { i32 (...)** } +%struct.Animal = type { ptr } %struct.Cat = type { %struct.Animal } -@_ZTV3Cat = available_externally dso_local unnamed_addr constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* bitcast (i8** @_ZTI3Cat to i8*), i8* bitcast (void (%struct.Cat*)* @_ZNK3Cat9makeNoiseEv to i8*)] }, align 8, !type !0, !type !1, !type !2, !type !3 -@_ZTI3Cat = external dso_local constant i8* -@llvm.compiler.used = appending global [1 x i8*] [i8* bitcast ({ [3 x i8*] }* @_ZTV3Cat to i8*)], section "llvm.metadata" +@_ZTV3Cat = available_externally dso_local unnamed_addr constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr @_ZTI3Cat, ptr @_ZNK3Cat9makeNoiseEv] }, align 8, !type !0, !type !1, !type !2, !type !3 +@_ZTI3Cat = external dso_local constant ptr +@llvm.compiler.used = appending global [1 x ptr] [ptr @_ZTV3Cat], section "llvm.metadata" -declare dso_local void @_ZNK3Cat9makeNoiseEv(%struct.Cat* nonnull dereferenceable(8)) unnamed_addr +declare dso_local void @_ZNK3Cat9makeNoiseEv(ptr nonnull dereferenceable(8)) unnamed_addr define dso_local void @_Z17useDoThingWithCatv() local_unnamed_addr { entry: - %call = tail call noalias nonnull dereferenceable(8) i8* @_Znwm(i64 8) - %0 = bitcast i8* %call to i32 (...)*** - store i32 (...)** bitcast (i8** getelementptr inbounds ({ [3 x i8*] }, { [3 x i8*] }* @_ZTV3Cat, i64 0, inrange i32 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 8, !tbaa !4 - %1 = bitcast i8* %call to %struct.Animal* - tail call void @_Z14doThingWithCatP6Animal(%struct.Animal* nonnull %1) + %call = tail call noalias nonnull dereferenceable(8) ptr @_Znwm(i64 8) + store ptr getelementptr inbounds ({ [3 x ptr] }, ptr @_ZTV3Cat, i64 0, inrange i32 0, i64 2), ptr %call, align 8, !tbaa !4 + tail call void @_Z14doThingWithCatP6Animal(ptr nonnull %call) ret void } -declare dso_local nonnull i8* @_Znwm(i64) local_unnamed_addr +declare dso_local nonnull ptr @_Znwm(i64) local_unnamed_addr -declare dso_local void @_Z14doThingWithCatP6Animal(%struct.Animal*) local_unnamed_addr +declare dso_local void @_Z14doThingWithCatP6Animal(ptr) local_unnamed_addr !0 = !{i64 16, !"_ZTS3Cat"} !1 = !{i64 16, !"_ZTSM3CatKFvvE.virtual"} diff --git a/lld/test/ELF/lto/devirt_vcall_vis_export_dynamic.ll b/lld/test/ELF/lto/devirt_vcall_vis_export_dynamic.ll --- a/lld/test/ELF/lto/devirt_vcall_vis_export_dynamic.ll +++ b/lld/test/ELF/lto/devirt_vcall_vis_export_dynamic.ll @@ -118,80 +118,73 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } %struct.B = type { %struct.A } %struct.C = type { %struct.A } -%struct.D = type { i32 (...)** } +%struct.D = type { ptr } -@_ZTV1B = linkonce_odr unnamed_addr constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !type !1, !vcall_visibility !5 -@_ZTV1C = linkonce_odr unnamed_addr constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.C*, i32)* @_ZN1C1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !type !2, !vcall_visibility !5 -@_ZTV1D = linkonce_odr unnamed_addr constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.D*, i32)* @_ZN1D1mEi to i8*)] }, !type !3, !vcall_visibility !5 +@_ZTV1B = linkonce_odr unnamed_addr constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B1fEi, ptr @_ZN1A1nEi] }, !type !0, !type !1, !vcall_visibility !5 +@_ZTV1C = linkonce_odr unnamed_addr constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1C1fEi, ptr @_ZN1A1nEi] }, !type !0, !type !2, !vcall_visibility !5 +@_ZTV1D = linkonce_odr unnamed_addr constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr undef, ptr @_ZN1D1mEi] }, !type !3, !vcall_visibility !5 ;; Prevent the vtables from being dead code eliminated. -@llvm.used = appending global [3 x i8*] [ i8* bitcast ( { [4 x i8*] }* @_ZTV1B to i8*), i8* bitcast ( { [4 x i8*] }* @_ZTV1C to i8*), i8* bitcast ( { [3 x i8*] }* @_ZTV1D to i8*)] +@llvm.used = appending global [3 x ptr] [ ptr @_ZTV1B, ptr @_ZTV1C, ptr @_ZTV1D] ; CHECK-IR-LABEL: define dso_local i32 @_start -define i32 @_start(%struct.A* %obj, %struct.D* %obj2, i32 %a) { +define i32 @_start(ptr %obj, ptr %obj2, i32 %a) { entry: - %0 = bitcast %struct.A* %obj to i8*** - %vtable = load i8**, i8*** %0 - %1 = bitcast i8** %vtable to i8* - %p = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1A") + %vtable = load ptr, ptr %obj + %p = call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1A") call void @llvm.assume(i1 %p) - %fptrptr = getelementptr i8*, i8** %vtable, i32 1 - %2 = bitcast i8** %fptrptr to i32 (%struct.A*, i32)** - %fptr1 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %2, align 8 + %fptrptr = getelementptr ptr, ptr %vtable, i32 1 + %fptr1 = load ptr, ptr %fptrptr, align 8 ;; Check that the call was devirtualized. ; CHECK-IR: %call = tail call i32 @_ZN1A1nEi ; CHECK-AONLY-IR: %call = tail call i32 @_ZN1A1nEi ; CHECK-NODEVIRT-IR: %call = tail call i32 %fptr1 - %call = tail call i32 %fptr1(%struct.A* nonnull %obj, i32 %a) + %call = tail call i32 %fptr1(ptr nonnull %obj, i32 %a) - %3 = bitcast i8** %vtable to i32 (%struct.A*, i32)** - %fptr22 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %3, align 8 + %fptr22 = load ptr, ptr %vtable, align 8 ;; We still have to call it as virtual. ; CHECK-IR: %call3 = tail call i32 %fptr22 ; CHECK-AONLY-IR: %call3 = tail call i32 %fptr22 ; CHECK-NODEVIRT-IR: %call3 = tail call i32 %fptr22 - %call3 = tail call i32 %fptr22(%struct.A* nonnull %obj, i32 %call) + %call3 = tail call i32 %fptr22(ptr nonnull %obj, i32 %call) - %4 = bitcast %struct.D* %obj2 to i8*** - %vtable2 = load i8**, i8*** %4 - %5 = bitcast i8** %vtable2 to i8* - %p2 = call i1 @llvm.type.test(i8* %5, metadata !4) + %vtable2 = load ptr, ptr %obj2 + %p2 = call i1 @llvm.type.test(ptr %vtable2, metadata !4) call void @llvm.assume(i1 %p2) - %6 = bitcast i8** %vtable2 to i32 (%struct.D*, i32)** - %fptr33 = load i32 (%struct.D*, i32)*, i32 (%struct.D*, i32)** %6, align 8 + %fptr33 = load ptr, ptr %vtable2, align 8 ;; Check that the call was devirtualized. ; CHECK-IR: %call4 = tail call i32 @_ZN1D1mEi ; CHECK-AONLY-IR: %call4 = tail call i32 %fptr33 ; CHECK-NODEVIRT-IR: %call4 = tail call i32 %fptr33 - %call4 = tail call i32 %fptr33(%struct.D* nonnull %obj2, i32 %call3) + %call4 = tail call i32 %fptr33(ptr nonnull %obj2, i32 %call3) ret i32 %call4 } ; CHECK-IR-LABEL: ret i32 ; CHECK-IR-LABEL: } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) -define i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) #0 { +define i32 @_ZN1B1fEi(ptr %this, i32 %a) #0 { ret i32 0; } -define i32 @_ZN1A1nEi(%struct.A* %this, i32 %a) #0 { +define i32 @_ZN1A1nEi(ptr %this, i32 %a) #0 { ret i32 0; } -define i32 @_ZN1C1fEi(%struct.C* %this, i32 %a) #0 { +define i32 @_ZN1C1fEi(ptr %this, i32 %a) #0 { ret i32 0; } -define i32 @_ZN1D1mEi(%struct.D* %this, i32 %a) #0 { +define i32 @_ZN1D1mEi(ptr %this, i32 %a) #0 { ret i32 0; } diff --git a/lld/test/ELF/lto/devirt_vcall_vis_localize.ll b/lld/test/ELF/lto/devirt_vcall_vis_localize.ll --- a/lld/test/ELF/lto/devirt_vcall_vis_localize.ll +++ b/lld/test/ELF/lto/devirt_vcall_vis_localize.ll @@ -18,48 +18,45 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } %struct.B = type { %struct.A } -@_ZTV1A = available_externally unnamed_addr constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !vcall_visibility !2 -@_ZTV1B = linkonce_odr unnamed_addr constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !type !1, !vcall_visibility !2 +@_ZTV1A = available_externally unnamed_addr constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1A1fEi, ptr @_ZN1A1nEi] }, !type !0, !vcall_visibility !2 +@_ZTV1B = linkonce_odr unnamed_addr constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B1fEi, ptr @_ZN1A1nEi] }, !type !0, !type !1, !vcall_visibility !2 ;; Prevent the vtables from being dead code eliminated. -@llvm.used = appending global [2 x i8*] [ i8* bitcast ( { [4 x i8*] }* @_ZTV1A to i8*), i8* bitcast ( { [4 x i8*] }* @_ZTV1B to i8*)] +@llvm.used = appending global [2 x ptr] [ ptr @_ZTV1A, ptr @_ZTV1B] ; CHECK-IR-LABEL: @_start( -define i32 @_start(%struct.A* %obj, i32 %a) { +define i32 @_start(ptr %obj, i32 %a) { entry: - %0 = bitcast %struct.A* %obj to i8*** - %vtable = load i8**, i8*** %0 - %1 = bitcast i8** %vtable to i8* - %p = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1A") + %vtable = load ptr, ptr %obj + %p = call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1A") call void @llvm.assume(i1 %p) - %fptrptr = getelementptr i8*, i8** %vtable, i32 1 - %2 = bitcast i8** %fptrptr to i32 (%struct.A*, i32)** - %fptr1 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %2, align 8 + %fptrptr = getelementptr ptr, ptr %vtable, i32 1 + %fptr1 = load ptr, ptr %fptrptr, align 8 ;; Check that the call was devirtualized. ; CHECK-IR: %call = tail call i32 @_ZN1A1nEi - %call = tail call i32 %fptr1(%struct.A* nonnull %obj, i32 %a) + %call = tail call i32 %fptr1(ptr nonnull %obj, i32 %a) ret i32 %call } ; CHECK-IR-LABEL: ret i32 ; CHECK-IR-LABEL: } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) -define available_externally i32 @_ZN1A1fEi(%struct.A* %this, i32 %a) #0 { +define available_externally i32 @_ZN1A1fEi(ptr %this, i32 %a) #0 { ret i32 0 } -define available_externally i32 @_ZN1A1nEi(%struct.A* %this, i32 %a) #0 { +define available_externally i32 @_ZN1A1nEi(ptr %this, i32 %a) #0 { ret i32 0 } -define linkonce_odr i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) #0 { +define linkonce_odr i32 @_ZN1B1fEi(ptr %this, i32 %a) #0 { ret i32 0 } diff --git a/lld/test/ELF/lto/devirt_vcall_vis_shared_def.ll b/lld/test/ELF/lto/devirt_vcall_vis_shared_def.ll --- a/lld/test/ELF/lto/devirt_vcall_vis_shared_def.ll +++ b/lld/test/ELF/lto/devirt_vcall_vis_shared_def.ll @@ -48,49 +48,46 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } %struct.B = type { %struct.A } -@_ZTV1A = available_externally unnamed_addr constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !vcall_visibility !2 -@_ZTV1B = linkonce_odr unnamed_addr constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !type !1, !vcall_visibility !2 +@_ZTV1A = available_externally unnamed_addr constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1A1fEi, ptr @_ZN1A1nEi] }, !type !0, !vcall_visibility !2 +@_ZTV1B = linkonce_odr unnamed_addr constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B1fEi, ptr @_ZN1A1nEi] }, !type !0, !type !1, !vcall_visibility !2 ;; Prevent the vtables from being dead code eliminated. -@llvm.used = appending global [2 x i8*] [ i8* bitcast ( { [4 x i8*] }* @_ZTV1A to i8*), i8* bitcast ( { [4 x i8*] }* @_ZTV1B to i8*)] +@llvm.used = appending global [2 x ptr] [ ptr @_ZTV1A, ptr @_ZTV1B] ; CHECK-IR-LABEL: define dso_local i32 @_start -define i32 @_start(%struct.A* %obj, i32 %a) { +define i32 @_start(ptr %obj, i32 %a) { entry: - %0 = bitcast %struct.A* %obj to i8*** - %vtable = load i8**, i8*** %0 - %1 = bitcast i8** %vtable to i8* - %p = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1A") + %vtable = load ptr, ptr %obj + %p = call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1A") call void @llvm.assume(i1 %p) - %fptrptr = getelementptr i8*, i8** %vtable, i32 1 - %2 = bitcast i8** %fptrptr to i32 (%struct.A*, i32)** - %fptr1 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %2, align 8 + %fptrptr = getelementptr ptr, ptr %vtable, i32 1 + %fptr1 = load ptr, ptr %fptrptr, align 8 ;; Check that the call was devirtualized. ; CHECK-IR: %call = tail call i32 @_ZN1A1nEi ; CHECK-NODEVIRT-IR: %call = tail call i32 %fptr1 - %call = tail call i32 %fptr1(%struct.A* nonnull %obj, i32 %a) + %call = tail call i32 %fptr1(ptr nonnull %obj, i32 %a) ret i32 %call } ; CHECK-IR-LABEL: ret i32 ; CHECK-IR-LABEL: } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) -define available_externally i32 @_ZN1A1fEi(%struct.A* %this, i32 %a) #0 { +define available_externally i32 @_ZN1A1fEi(ptr %this, i32 %a) #0 { ret i32 0 } -define available_externally i32 @_ZN1A1nEi(%struct.A* %this, i32 %a) #0 { +define available_externally i32 @_ZN1A1nEi(ptr %this, i32 %a) #0 { ret i32 0 } -define linkonce_odr i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) #0 { +define linkonce_odr i32 @_ZN1B1fEi(ptr %this, i32 %a) #0 { ret i32 0 } diff --git a/lld/test/ELF/lto/discard-value-names.ll b/lld/test/ELF/lto/discard-value-names.ll --- a/lld/test/ELF/lto/discard-value-names.ll +++ b/lld/test/ELF/lto/discard-value-names.ll @@ -18,7 +18,7 @@ define i32 @foo(i32 %in) { somelabel: - %GV = load i32, i32* @GlobalValueName + %GV = load i32, ptr @GlobalValueName %add = add i32 %in, %GV ret i32 %add } diff --git a/lld/test/ELF/lto/internalize-exportdyn.ll b/lld/test/ELF/lto/internalize-exportdyn.ll --- a/lld/test/ELF/lto/internalize-exportdyn.ll +++ b/lld/test/ELF/lto/internalize-exportdyn.ll @@ -35,7 +35,7 @@ ret void } -@use_baz = global void ()* @baz +@use_baz = global ptr @baz ; Check what gets internalized. ; CHECK: define dso_local void @_start() diff --git a/lld/test/ELF/lto/internalize-llvmused.ll b/lld/test/ELF/lto/internalize-llvmused.ll --- a/lld/test/ELF/lto/internalize-llvmused.ll +++ b/lld/test/ELF/lto/internalize-llvmused.ll @@ -14,7 +14,7 @@ ret void } -@llvm.used = appending global [1 x i8*] [ i8* bitcast (void ()* @f to i8*)] +@llvm.used = appending global [1 x ptr] [ ptr @f] ; Check that f is not internalized. ; CHECK: define hidden void @f() diff --git a/lld/test/ELF/lto/libcall-archive.ll b/lld/test/ELF/lto/libcall-archive.ll --- a/lld/test/ELF/lto/libcall-archive.ll +++ b/lld/test/ELF/lto/libcall-archive.ll @@ -16,10 +16,10 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define void @_start(i8* %a, i8* %b) { +define void @_start(ptr %a, ptr %b) { entry: - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 1024, i1 false) + call void @llvm.memcpy.p0.p0.i64(ptr %a, ptr %b, i64 1024, i1 false) ret void } -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) +declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) diff --git a/lld/test/ELF/lto/linkage.ll b/lld/test/ELF/lto/linkage.ll --- a/lld/test/ELF/lto/linkage.ll +++ b/lld/test/ELF/lto/linkage.ll @@ -10,7 +10,7 @@ @.str = private unnamed_addr constant [4 x i8] c"Hey\00", align 1 ; Should not encounter a duplicate symbol error for @llvm.global_ctors -@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @ctor, i8* null }] +@llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @ctor, ptr null }] define internal void @ctor() { ret void } diff --git a/lld/test/ELF/lto/linker-script-symbols-assign.ll b/lld/test/ELF/lto/linker-script-symbols-assign.ll --- a/lld/test/ELF/lto/linker-script-symbols-assign.ll +++ b/lld/test/ELF/lto/linker-script-symbols-assign.ll @@ -1,7 +1,7 @@ ; REQUIRES: x86 ; RUN: llvm-as %s -o %t.o -; RUN: rm -f %t2.* +; RUN: rm -f ptr ; RUN: echo "foo = 1;" > %t.script ; RUN: ld.lld %t.o -o %t2 --script %t.script -save-temps ;; Combined module is not empty, but it will be empty after optimization. diff --git a/lld/test/ELF/lto/ltopasses-basic.ll b/lld/test/ELF/lto/ltopasses-basic.ll --- a/lld/test/ELF/lto/ltopasses-basic.ll +++ b/lld/test/ELF/lto/ltopasses-basic.ll @@ -6,7 +6,7 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @ctor, i8* null }] +@llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @ctor, ptr null }] define void @ctor() { ret void } diff --git a/lld/test/ELF/lto/ltopasses-extension.ll b/lld/test/ELF/lto/ltopasses-extension.ll --- a/lld/test/ELF/lto/ltopasses-extension.ll +++ b/lld/test/ELF/lto/ltopasses-extension.ll @@ -8,6 +8,6 @@ target triple = "x86_64-unknown-linux-gnu" @junk = global i32 0 -define i32* @somefunk() { - ret i32* @junk +define ptr @somefunk() { + ret ptr @junk } diff --git a/lld/test/ELF/lto/metadata.ll b/lld/test/ELF/lto/metadata.ll --- a/lld/test/ELF/lto/metadata.ll +++ b/lld/test/ELF/lto/metadata.ll @@ -5,8 +5,8 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define weak void @foo(i32* %p) { - store i32 5, i32* %p, align 4, !tbaa !0 +define weak void @foo(ptr %p) { + store i32 5, ptr %p, align 4, !tbaa !0 ret void } diff --git a/lld/test/ELF/lto/pseudo-probe-lto.ll b/lld/test/ELF/lto/pseudo-probe-lto.ll --- a/lld/test/ELF/lto/pseudo-probe-lto.ll +++ b/lld/test/ELF/lto/pseudo-probe-lto.ll @@ -7,14 +7,14 @@ @g = dso_local global i32 3, align 4 -define void @foo(void (i32)* %f) !dbg !4 { +define void @foo(ptr %f) !dbg !4 { entry: ; CHECK: .pseudoprobe [[#GUID:]] 1 0 0 ; CHECK: .pseudoprobe [[#GUID]] 2 1 0 call void %f(i32 1), !dbg !13 - %0 = load i32, i32* @g, align 4 + %0 = load i32, ptr @g, align 4 %inc = add nsw i32 %0, 1 - store i32 %inc, i32* @g, align 4 + store i32 %inc, ptr @g, align 4 ret void } diff --git a/lld/test/ELF/lto/relax-relocs.ll b/lld/test/ELF/lto/relax-relocs.ll --- a/lld/test/ELF/lto/relax-relocs.ll +++ b/lld/test/ELF/lto/relax-relocs.ll @@ -11,6 +11,6 @@ @foo = external global i32 define i32 @bar() { - %t = load i32, i32* @foo + %t = load i32, ptr @foo ret i32 %t } diff --git a/lld/test/ELF/lto/relocation-model-pic.ll b/lld/test/ELF/lto/relocation-model-pic.ll --- a/lld/test/ELF/lto/relocation-model-pic.ll +++ b/lld/test/ELF/lto/relocation-model-pic.ll @@ -17,7 +17,7 @@ @foo = external global i32 define i32 @main() { - %t = load i32, i32* @foo + %t = load i32, ptr @foo ret i32 %t } diff --git a/lld/test/ELF/lto/relocation-model-static.ll b/lld/test/ELF/lto/relocation-model-static.ll --- a/lld/test/ELF/lto/relocation-model-static.ll +++ b/lld/test/ELF/lto/relocation-model-static.ll @@ -14,6 +14,6 @@ @foo = external dso_local global i32 define i32 @main() { - %t = load i32, i32* @foo + %t = load i32, ptr @foo ret i32 %t } diff --git a/lld/test/ELF/lto/section-name.ll b/lld/test/ELF/lto/section-name.ll --- a/lld/test/ELF/lto/section-name.ll +++ b/lld/test/ELF/lto/section-name.ll @@ -15,12 +15,12 @@ @__start_foo_section = external global i32 @__stop_bar_section = external global i32 -define hidden i32* @use1() { - ret i32* @__start_foo_section +define hidden ptr @use1() { + ret ptr @__start_foo_section } -define i32* @use2() { - ret i32* @__stop_bar_section +define ptr @use2() { + ret ptr @__stop_bar_section } ; CHECK-NOT: zed_section diff --git a/lld/test/ELF/lto/setting-dso-local.ll b/lld/test/ELF/lto/setting-dso-local.ll --- a/lld/test/ELF/lto/setting-dso-local.ll +++ b/lld/test/ELF/lto/setting-dso-local.ll @@ -10,6 +10,6 @@ target triple = "x86_64-unknown-linux-gnu" @foobar = external hidden global i32 -define i32* @_start() { - ret i32* @foobar +define ptr @_start() { + ret ptr @foobar } diff --git a/lld/test/ELF/lto/slp-vectorize-pm.ll b/lld/test/ELF/lto/slp-vectorize-pm.ll --- a/lld/test/ELF/lto/slp-vectorize-pm.ll +++ b/lld/test/ELF/lto/slp-vectorize-pm.ll @@ -26,15 +26,15 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define i32 @foo(i32* %a) { +define i32 @foo(ptr %a) { entry: br label %for.body for.body: %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %red.05 = phi i32 [ 0, %entry ], [ %add, %for.body ] - %arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv - %0 = load i32, i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, ptr %a, i64 %indvars.iv + %0 = load i32, ptr %arrayidx, align 4 %add = add nsw i32 %0, %red.05 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %exitcond = icmp eq i64 %indvars.iv.next, 255 diff --git a/lld/test/ELF/lto/tls-preserve.ll b/lld/test/ELF/lto/tls-preserve.ll --- a/lld/test/ELF/lto/tls-preserve.ll +++ b/lld/test/ELF/lto/tls-preserve.ll @@ -10,7 +10,7 @@ @tsp_int = thread_local global i32 1 define void @_start() { - %val = load i32, i32* @tsp_int + %val = load i32, ptr @tsp_int ret void } diff --git a/lld/test/ELF/lto/type-merge.ll b/lld/test/ELF/lto/type-merge.ll --- a/lld/test/ELF/lto/type-merge.ll +++ b/lld/test/ELF/lto/type-merge.ll @@ -8,10 +8,10 @@ target triple = "x86_64-unknown-linux-gnu" define void @foo() { - call void @bar(i8* null) + call void @bar(ptr null) ret void } -declare void @bar(i8*) +declare void @bar(ptr) ; CHECK: define void @foo() { ; CHECK-NEXT: call void @bar(ptr null) diff --git a/lld/test/ELF/lto/type-merge2.ll b/lld/test/ELF/lto/type-merge2.ll --- a/lld/test/ELF/lto/type-merge2.ll +++ b/lld/test/ELF/lto/type-merge2.ll @@ -9,10 +9,10 @@ %zed = type { i8 } define void @foo() { - call void @bar(%zed* null) + call void @bar(ptr null) ret void } -declare void @bar(%zed*) +declare void @bar(ptr) ; CHECK: define void @foo() { ; CHECK-NEXT: call void @bar(ptr null) diff --git a/lld/test/ELF/lto/undefined-puts.ll b/lld/test/ELF/lto/undefined-puts.ll --- a/lld/test/ELF/lto/undefined-puts.ll +++ b/lld/test/ELF/lto/undefined-puts.ll @@ -11,11 +11,11 @@ @.str = private unnamed_addr constant [6 x i8] c"blah\0A\00", align 1 define i32 @_start() { - %str = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str, i32 0, i32 0)) + %str = call i32 (ptr, ...) @printf(ptr @.str) ret i32 0 } -declare i32 @printf(i8*, ...) +declare i32 @printf(ptr, ...) ; Check that puts symbol is present in the dynamic symbol table and ; there's a relocation for it. diff --git a/lld/test/ELF/lto/unnamed-addr.ll b/lld/test/ELF/lto/unnamed-addr.ll --- a/lld/test/ELF/lto/unnamed-addr.ll +++ b/lld/test/ELF/lto/unnamed-addr.ll @@ -8,8 +8,8 @@ @a = internal unnamed_addr constant i8 42 -define i8* @f() { - ret i8* @a +define ptr @f() { + ret ptr @a } ; CHECK: @a = internal unnamed_addr constant i8 42 diff --git a/lld/test/ELF/lto/weakodr-visibility.ll b/lld/test/ELF/lto/weakodr-visibility.ll --- a/lld/test/ELF/lto/weakodr-visibility.ll +++ b/lld/test/ELF/lto/weakodr-visibility.ll @@ -35,6 +35,6 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define weak_odr i32 @foo(i8* %this) { +define weak_odr i32 @foo(ptr %this) { ret i32 41 } diff --git a/lld/test/ELF/lto/wrap-unreferenced-before-codegen.test b/lld/test/ELF/lto/wrap-unreferenced-before-codegen.test --- a/lld/test/ELF/lto/wrap-unreferenced-before-codegen.test +++ b/lld/test/ELF/lto/wrap-unreferenced-before-codegen.test @@ -59,13 +59,13 @@ #--- resume.ll target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define dso_local void @_Z1fv() optnone noinline personality i8* bitcast (void ()* @throw to i8*) { +define dso_local void @_Z1fv() optnone noinline personality ptr @throw { invoke void @throw() to label %unreachable unwind label %lpad lpad: - %1 = landingpad { i8*, i32 } + %1 = landingpad { ptr, i32 } cleanup - resume { i8*, i32 } %1 + resume { ptr, i32 } %1 unreachable: unreachable } diff --git a/lld/test/MachO/lc-linker-option.ll b/lld/test/MachO/lc-linker-option.ll --- a/lld/test/MachO/lc-linker-option.ll +++ b/lld/test/MachO/lc-linker-option.ll @@ -144,7 +144,7 @@ declare void @_CFBigNumGetInt128(...) define void @main() { - call void bitcast (void (...)* @_CFBigNumGetInt128 to void ()*)() + call void @_CFBigNumGetInt128() ret void } @@ -157,11 +157,11 @@ !llvm.linker.options = !{!0, !0, !1} declare void @_CFBigNumGetInt128(...) -declare i8* @__cxa_allocate_exception(i64) +declare ptr @__cxa_allocate_exception(i64) define void @main() { - call void bitcast (void (...)* @_CFBigNumGetInt128 to void ()*)() - call i8* @__cxa_allocate_exception(i64 4) + call void @_CFBigNumGetInt128() + call ptr @__cxa_allocate_exception(i64 4) ret void } diff --git a/lld/test/MachO/lto-archive.ll b/lld/test/MachO/lto-archive.ll --- a/lld/test/MachO/lto-archive.ll +++ b/lld/test/MachO/lto-archive.ll @@ -51,12 +51,12 @@ @"_OBJC_$_CATEGORY_Foo_$_Bar" = internal global %struct._category_t { i8 123 }, section "__DATA, __objc_const", align 8 -@"OBJC_LABEL_CATEGORY_$" = private global [1 x i8*] [ - i8* bitcast (%struct._category_t* @"_OBJC_$_CATEGORY_Foo_$_Bar" to i8*) +@"OBJC_LABEL_CATEGORY_$" = private global [1 x ptr] [ + ptr @"_OBJC_$_CATEGORY_Foo_$_Bar" ], section "__DATA,__objc_catlist,regular,no_dead_strip", align 8 -@llvm.compiler.used = appending global [1 x i8*] [ - i8* bitcast ([1 x i8*]* @"OBJC_LABEL_CATEGORY_$" to i8*) +@llvm.compiler.used = appending global [1 x ptr] [ + ptr @"OBJC_LABEL_CATEGORY_$" ], section "llvm.metadata" ;--- main.s diff --git a/lld/test/MachO/lto-codemodel.ll b/lld/test/MachO/lto-codemodel.ll --- a/lld/test/MachO/lto-codemodel.ll +++ b/lld/test/MachO/lto-codemodel.ll @@ -10,11 +10,11 @@ @data = internal constant [0 x i32] [] -define i32* @main() nounwind readonly { +define ptr @main() nounwind readonly { entry: ; CHECK-SMALL-LABEL: <_main>: ; CHECK-SMALL: leaq [[#]](%rip), %rax ; CHECK-LARGE-LABEL: <_main>: ; CHECK-LARGE: movabsq $[[#]], %rax - ret i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0) + ret ptr @data } diff --git a/lld/test/MachO/lto-common-symbol-resolution.ll b/lld/test/MachO/lto-common-symbol-resolution.ll --- a/lld/test/MachO/lto-common-symbol-resolution.ll +++ b/lld/test/MachO/lto-common-symbol-resolution.ll @@ -106,6 +106,6 @@ @foo = external global i8 define void @f() { - %1 = load i8, i8* @foo + %1 = load i8, ptr @foo ret void } diff --git a/lld/test/MachO/lto-internalize-unnamed-addr.ll b/lld/test/MachO/lto-internalize-unnamed-addr.ll --- a/lld/test/MachO/lto-internalize-unnamed-addr.ll +++ b/lld/test/MachO/lto-internalize-unnamed-addr.ll @@ -95,11 +95,11 @@ @local_unnamed_always_const = linkonce_odr local_unnamed_addr constant i8 42 @local_unnamed_sometimes_const = linkonce_odr local_unnamed_addr constant i8 42 @local_unnamed = linkonce_odr local_unnamed_addr global i8 42 -@used = hidden constant [6 x i8*] [i8* @global_unnamed, - i8* @global_unnamed_sometimes_linkonce, i8* @local_unnamed, - i8* @local_unnamed_const, i8* @local_unnamed_always_const, - i8* @local_unnamed_sometimes_const] -@llvm.used = appending global [1 x [6 x i8*]*] [[6 x i8*]* @used] +@used = hidden constant [6 x ptr] [ptr @global_unnamed, + ptr @global_unnamed_sometimes_linkonce, ptr @local_unnamed, + ptr @local_unnamed_const, ptr @local_unnamed_always_const, + ptr @local_unnamed_sometimes_const] +@llvm.used = appending global [1 x ptr] [ptr @used] define void @main() { ret void diff --git a/lld/test/MachO/lto-objc-arc-contract.ll b/lld/test/MachO/lto-objc-arc-contract.ll --- a/lld/test/MachO/lto-objc-arc-contract.ll +++ b/lld/test/MachO/lto-objc-arc-contract.ll @@ -18,8 +18,8 @@ target triple = "x86_64-apple-darwin" target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" -define void @foo(i8* %a, i8* %b) { - call void (...) @llvm.objc.clang.arc.use(i8* %a, i8* %b) nounwind +define void @foo(ptr %a, ptr %b) { + call void (...) @llvm.objc.clang.arc.use(ptr %a, ptr %b) nounwind ret void } diff --git a/lld/test/MachO/start-lib.s b/lld/test/MachO/start-lib.s --- a/lld/test/MachO/start-lib.s +++ b/lld/test/MachO/start-lib.s @@ -1,83 +1,86 @@ # REQUIRES: x86 -# RUN: rm -rf %t; split-file %s %t && cd %t -# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin main.s -o main.o -# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin calls-foo.s -o calls-foo.o -# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin 1.s -o 1.o -# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin 2.s -o 2.o -# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin common.s -o common.o +# RUN: rm -rf %t; split-file %s %t +# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/main.s -o %t/main.o +# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/calls-foo.s -o %t/calls-foo.o +# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/1.s -o %t/1.o +# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/2.s -o %t/2.o +# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/common.s -o %t/common.o -# RUN: llvm-as 1.ll -o 1.bc -# RUN: llvm-as 2.ll -o 2.bc +# RUN: echo "%t/1.o" > %t/filelist +# RUN: echo "%t/2.o" >> %t/filelist + +# RUN: llvm-as %t/1.ll -o %t/1.bc +# RUN: llvm-as %t/2.ll -o %t/2.bc ## Neither 1.o nor 2.o is loaded. -# RUN: %lld main.o --start-lib 1.o 2.o --end-lib -why_load | count 0 -# RUN: %lld main.o --start-lib -filelist filelist --end-lib -why_load | count 0 -# RUN: llvm-readobj -s a.out | FileCheck %s +# RUN: %lld %t/main.o -o %t/out --start-lib %t/1.o %t/2.o --end-lib -why_load | count 0 +# RUN: %lld %t/main.o -o %t/out --start-lib -filelist %t/filelist --end-lib -why_load | count 0 +# RUN: llvm-readobj -s %t/out | FileCheck %s # CHECK-NOT: Name: _foo # CHECK-NOT: Name: _bar ## _bar loads 2.o. The last --end-lib can be omitted. -# RUN: %lld main.o -u _bar --start-lib 1.o 2.o -t -why_load | FileCheck %s --check-prefix=CHECK2WHY -# RUN: %lld main.o -u _bar --start-lib -filelist filelist -t -why_load | FileCheck %s --check-prefix=CHECK2WHY -# RUN: llvm-readobj -s a.out | FileCheck --check-prefix=CHECK2 %s -# CHECK2WHY: main.o -# CHECK2WHY-NEXT: 2.o -# CHECK2WHY-NEXT: _bar forced load of 2.o +# RUN: %lld %t/main.o -o %t/out -u _bar --start-lib %t/1.o %t/2.o -t -why_load | FileCheck %s --check-prefix=CHECK2WHY +# RUN: %lld %t/main.o -o %t/out -u _bar --start-lib -filelist %t/filelist -t -why_load | FileCheck %s --check-prefix=CHECK2WHY +# RUN: llvm-readobj -s %t/out | FileCheck --check-prefix=CHECK2 %s +# CHECK2WHY: {{.*}}main.o +# CHECK2WHY-NEXT: {{.*}}2.o +# CHECK2WHY-NEXT: _bar forced load of {{.*}}2.o # CHECK2WHY-EMPTY: # CHECK2-NOT: Name: _foo # CHECK2: Name: _bar # CHECK2-NOT: Name: _foo ## _foo loads 1.o. 1.o loads 2.o. -# RUN: %lld main.o -u _foo --start-lib 1.o 2.o -why_load | FileCheck %s --check-prefix=CHECK3WHY -# RUN: llvm-readobj -s a.out | FileCheck --check-prefix=CHECK3 %s -# RUN: %lld main.o -u _foo --start-lib 2.o --end-lib --start-lib 1.o -why_load | FileCheck %s --check-prefix=CHECK3WHY -# RUN: llvm-readobj -s a.out | FileCheck --check-prefix=CHECK3 %s -# CHECK3WHY: _foo forced load of 1.o -# CHECK3WHY-NEXT: _bar forced load of 2.o +# RUN: %lld %t/main.o -o %t/out -u _foo --start-lib %t/1.o %t/2.o -why_load | FileCheck %s --check-prefix=CHECK3WHY +# RUN: llvm-readobj -s %t/out | FileCheck --check-prefix=CHECK3 %s +# RUN: %lld %t/main.o -o %t/out -u _foo --start-lib %t/2.o --end-lib --start-lib %t/1.o -why_load | FileCheck %s --check-prefix=CHECK3WHY +# RUN: llvm-readobj -s %t/out | FileCheck --check-prefix=CHECK3 %s +# CHECK3WHY: _foo forced load of {{.*}}1.o +# CHECK3WHY-NEXT: _bar forced load of {{.*}}2.o # CHECK3WHY-EMPTY: # CHECK3-DAG: Name: _foo # CHECK3-DAG: Name: _bar ## Don't treat undefined _bar in 1.o as a lazy definition. -# RUN: not %lld main.o -u _bar --start-lib 1.o 2>&1 | FileCheck %s --check-prefix=CHECK4 +# RUN: not %lld %t/main.o -u _bar --start-lib %t/1.o 2>&1 | FileCheck %s --check-prefix=CHECK4 # CHECK4: error: undefined symbol: _bar -# RUN: %lld main.o -u _common --start-lib common.o -# RUN: llvm-readobj -s a.out | FileCheck %s --check-prefix=COMMON1 +# RUN: %lld %t/main.o -o %t/out -u _common --start-lib %t/common.o +# RUN: llvm-readobj -s %t/out | FileCheck %s --check-prefix=COMMON1 # COMMON1: Name: _common -# RUN: %lld main.o --start-lib common.o -# RUN: llvm-readobj -s a.out | FileCheck %s --check-prefix=COMMON2 +# RUN: %lld %t/main.o -o %t/out --start-lib %t/common.o +# RUN: llvm-readobj -s %t/out | FileCheck %s --check-prefix=COMMON2 # COMMON2-NOT: Name: _common ## Neither 1.bc nor 2.bc is loaded. -# RUN: %lld main.o --start-lib 1.bc 2.bc -why_load | count 0 -# RUN: llvm-readobj -s a.out | FileCheck %s --check-prefix=BITCODE +# RUN: %lld %t/main.o -o %t/out --start-lib %t/1.bc %t/2.bc -why_load | count 0 +# RUN: llvm-readobj -s %t/out | FileCheck %s --check-prefix=BITCODE # BITCODE-NOT: Name: _foo # BITCODE-NOT: Name: _bar ## _bar loads 2.bc. -# RUN: %lld main.o -u _bar --start-lib 1.bc 2.bc -why_load | FileCheck %s --check-prefix=BITCODE2WHY -# RUN: llvm-readobj -s a.out | FileCheck %s --check-prefix=BITCODE2 -# BITCODE2WHY: _bar forced load of 2.bc +# RUN: %lld %t/main.o -o %t/out -u _bar --start-lib %t/1.bc %t/2.bc -why_load | FileCheck %s --check-prefix=BITCODE2WHY +# RUN: llvm-readobj -s %t/out | FileCheck %s --check-prefix=BITCODE2 +# BITCODE2WHY: _bar forced load of {{.*}}2.bc # BITCODE2WHY-EMPTY: # BITCODE2-NOT: Name: _foo # BITCODE2: Name: _bar # BITCODE2-NOT: Name: _foo ## calls-foo.o loads 1.bc. 1.bc loads 2.bc. -# RUN: %lld calls-foo.o --start-lib 1.bc 2.bc -why_load | FileCheck %s --check-prefix=BITCODE3WHY -# RUN: llvm-readobj -s a.out | FileCheck --check-prefix=BITCODE3 %s -# RUN: %lld calls-foo.o --start-lib 2.bc --end-lib --start-lib 1.bc -why_load | FileCheck %s --check-prefix=BITCODE3WHY -# RUN: llvm-readobj -s a.out | FileCheck --check-prefix=BITCODE3 %s -# BITCODE3WHY: _foo forced load of 1.bc -# BITCODE3WHY-NEXT: _bar forced load of 2.bc +# RUN: %lld %t/calls-foo.o -o %t/out --start-lib %t/1.bc %t/2.bc -why_load | FileCheck %s --check-prefix=BITCODE3WHY +# RUN: llvm-readobj -s %t/out | FileCheck --check-prefix=BITCODE3 %s +# RUN: %lld %t/calls-foo.o -o %t/out --start-lib %t/2.bc --end-lib --start-lib %t/1.bc -why_load | FileCheck %s --check-prefix=BITCODE3WHY +# RUN: llvm-readobj -s %t/out | FileCheck --check-prefix=BITCODE3 %s +# BITCODE3WHY: _foo forced load of {{.*}}1.bc +# BITCODE3WHY-NEXT: _bar forced load of {{.*}}2.bc # BITCODE3WHY-EMPTY: # BITCODE3-DAG: Name: _foo -# RUN: not %lld main.o --start-lib --start-lib 2>&1 | FileCheck -check-prefix=NESTED-LIB %s +# RUN: not %lld %t/main.o --start-lib --start-lib 2>&1 | FileCheck -check-prefix=NESTED-LIB %s # NESTED-LIB: error: nested --start-lib # RUN: not %lld --end-lib 2>&1 | FileCheck %s --check-prefix=STRAY @@ -123,7 +126,3 @@ define void @bar() { ret void } - -#--- filelist -1.o -2.o diff --git a/lld/test/wasm/Inputs/comdat1.ll b/lld/test/wasm/Inputs/comdat1.ll --- a/lld/test/wasm/Inputs/comdat1.ll +++ b/lld/test/wasm/Inputs/comdat1.ll @@ -5,18 +5,18 @@ @constantData = constant [3 x i8] c"abc", comdat($foo) define i32 @comdatFn() comdat($foo) { - ret i32 ptrtoint ([3 x i8]* @constantData to i32) + ret i32 ptrtoint (ptr @constantData to i32) } define internal void @do_init() comdat($foo) { ret void } -%0 = type { i32, void ()*, i8* } -@llvm.global_ctors = appending global [1 x %0 ] [%0 { i32 65535, void ()* @do_init, i8* null }] +%0 = type { i32, ptr, ptr } +@llvm.global_ctors = appending global [1 x %0 ] [%0 { i32 65535, ptr @do_init, ptr null }] ; Everything above this is part of the `foo` comdat group define i32 @callComdatFn1() { - ret i32 ptrtoint (i32 ()* @comdatFn to i32) + ret i32 ptrtoint (ptr @comdatFn to i32) } diff --git a/lld/test/wasm/Inputs/comdat2.ll b/lld/test/wasm/Inputs/comdat2.ll --- a/lld/test/wasm/Inputs/comdat2.ll +++ b/lld/test/wasm/Inputs/comdat2.ll @@ -5,18 +5,18 @@ @constantData = constant [3 x i8] c"abc", comdat($foo) define i32 @comdatFn() comdat($foo) { - ret i32 ptrtoint ([3 x i8]* @constantData to i32) + ret i32 ptrtoint (ptr @constantData to i32) } define internal void @do_init() comdat($foo) { ret void } -%0 = type { i32, void ()*, i8* } -@llvm.global_ctors = appending global [1 x %0] [ %0 { i32 65535, void ()* @do_init, i8* getelementptr inbounds ([3 x i8], [3 x i8]* @constantData, i32 0, i32 0) }] +%0 = type { i32, ptr, ptr } +@llvm.global_ctors = appending global [1 x %0] [ %0 { i32 65535, ptr @do_init, ptr @constantData }] ; Everything above this is part of the `foo` comdat group define i32 @callComdatFn2() { - ret i32 ptrtoint (i32 ()* @comdatFn to i32) + ret i32 ptrtoint (ptr @comdatFn to i32) } diff --git a/lld/test/wasm/Inputs/debuginfo2.ll b/lld/test/wasm/Inputs/debuginfo2.ll --- a/lld/test/wasm/Inputs/debuginfo2.ll +++ b/lld/test/wasm/Inputs/debuginfo2.ll @@ -21,10 +21,10 @@ entry: call void @llvm.dbg.value(metadata i32 %p, metadata !20, metadata !DIExpression()), !dbg !21 %and = and i32 %p, 1, !dbg !22 - %arrayidx = getelementptr inbounds [2 x i32], [2 x i32]* @y, i32 0, i32 %and, !dbg !23 - %0 = load i32, i32* %arrayidx, align 4, !dbg !24, !tbaa !25 + %arrayidx = getelementptr inbounds [2 x i32], ptr @y, i32 0, i32 %and, !dbg !23 + %0 = load i32, ptr %arrayidx, align 4, !dbg !24, !tbaa !25 %inc = add nsw i32 %0, 1, !dbg !24 - store i32 %inc, i32* %arrayidx, align 4, !dbg !24, !tbaa !25 + store i32 %inc, ptr %arrayidx, align 4, !dbg !24, !tbaa !25 ret void, !dbg !29 } diff --git a/lld/test/wasm/Inputs/global-ctor-dtor.ll b/lld/test/wasm/Inputs/global-ctor-dtor.ll --- a/lld/test/wasm/Inputs/global-ctor-dtor.ll +++ b/lld/test/wasm/Inputs/global-ctor-dtor.ll @@ -11,14 +11,14 @@ ret void } -@llvm.global_ctors = appending global [3 x { i32, void ()*, i8* }] [ - { i32, void ()*, i8* } { i32 2002, void ()* @myctor, i8* null }, - { i32, void ()*, i8* } { i32 101, void ()* @myctor, i8* null }, - { i32, void ()*, i8* } { i32 202, void ()* @myctor, i8* null } +@llvm.global_ctors = appending global [3 x { i32, ptr, ptr }] [ + { i32, ptr, ptr } { i32 2002, ptr @myctor, ptr null }, + { i32, ptr, ptr } { i32 101, ptr @myctor, ptr null }, + { i32, ptr, ptr } { i32 202, ptr @myctor, ptr null } ] -@llvm.global_dtors = appending global [3 x { i32, void ()*, i8* }] [ - { i32, void ()*, i8* } { i32 2002, void ()* @mydtor, i8* null }, - { i32, void ()*, i8* } { i32 101, void ()* @mydtor, i8* null }, - { i32, void ()*, i8* } { i32 202, void ()* @mydtor, i8* null } +@llvm.global_dtors = appending global [3 x { i32, ptr, ptr }] [ + { i32, ptr, ptr } { i32 2002, ptr @mydtor, ptr null }, + { i32, ptr, ptr } { i32 101, ptr @mydtor, ptr null }, + { i32, ptr, ptr } { i32 202, ptr @mydtor, ptr null } ] diff --git a/lld/test/wasm/Inputs/locals-duplicate1.ll b/lld/test/wasm/Inputs/locals-duplicate1.ll --- a/lld/test/wasm/Inputs/locals-duplicate1.ll +++ b/lld/test/wasm/Inputs/locals-duplicate1.ll @@ -24,28 +24,28 @@ } -define i32* @get_global1A() { +define ptr @get_global1A() { entry: - ret i32* @colliding_global1 + ret ptr @colliding_global1 } -define i32* @get_global2A() { +define ptr @get_global2A() { entry: - ret i32* @colliding_global2 + ret ptr @colliding_global2 } -define i32* @get_global3A() { +define ptr @get_global3A() { entry: - ret i32* @colliding_global3 + ret ptr @colliding_global3 } -define i32 ()* @get_func1A() { +define ptr @get_func1A() { entry: - ret i32 ()* @colliding_func1 + ret ptr @colliding_func1 } -define i32 ()* @get_func2A() { +define ptr @get_func2A() { entry: - ret i32 ()* @colliding_func2 + ret ptr @colliding_func2 } -define i32 ()* @get_func3A() { +define ptr @get_func3A() { entry: - ret i32 ()* @colliding_func3 + ret ptr @colliding_func3 } diff --git a/lld/test/wasm/Inputs/locals-duplicate2.ll b/lld/test/wasm/Inputs/locals-duplicate2.ll --- a/lld/test/wasm/Inputs/locals-duplicate2.ll +++ b/lld/test/wasm/Inputs/locals-duplicate2.ll @@ -24,28 +24,28 @@ } -define i32* @get_global1B() { +define ptr @get_global1B() { entry: - ret i32* @colliding_global1 + ret ptr @colliding_global1 } -define i32* @get_global2B() { +define ptr @get_global2B() { entry: - ret i32* @colliding_global2 + ret ptr @colliding_global2 } -define i32* @get_global3B() { +define ptr @get_global3B() { entry: - ret i32* @colliding_global3 + ret ptr @colliding_global3 } -define i32 ()* @get_func1B() { +define ptr @get_func1B() { entry: - ret i32 ()* @colliding_func1 + ret ptr @colliding_func1 } -define i32 ()* @get_func2B() { +define ptr @get_func2B() { entry: - ret i32 ()* @colliding_func2 + ret ptr @colliding_func2 } -define i32 ()* @get_func3B() { +define ptr @get_func3B() { entry: - ret i32 ()* @colliding_func3 + ret ptr @colliding_func3 } diff --git a/lld/test/wasm/Inputs/many-funcs.ll b/lld/test/wasm/Inputs/many-funcs.ll --- a/lld/test/wasm/Inputs/many-funcs.ll +++ b/lld/test/wasm/Inputs/many-funcs.ll @@ -5,774 +5,774 @@ define i32 @f1() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f2() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f3() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f4() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f5() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f6() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f7() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f8() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f9() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f10() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f11() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f12() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f13() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f14() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f15() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f16() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f17() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f18() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f19() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f20() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f21() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f22() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f23() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f24() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f25() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f26() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f27() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f28() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f29() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f30() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f31() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f32() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f33() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f34() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f35() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f36() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f37() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f38() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f39() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f40() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f41() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f42() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f43() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f44() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f45() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f46() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f47() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f48() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f49() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f50() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f51() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f52() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f53() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f54() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f55() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f56() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f57() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f58() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f59() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f60() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f61() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f62() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f63() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f64() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f65() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f66() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f67() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f68() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f69() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f70() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f71() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f72() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f73() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f74() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f75() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f76() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f77() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f78() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f79() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f80() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f81() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f82() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f83() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f84() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f85() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f86() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f87() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f88() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f89() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f90() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f91() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f92() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f93() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f94() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f95() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f96() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f97() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f98() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f99() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f100() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f101() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f102() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f103() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f104() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f105() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f106() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f107() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f108() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f109() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f110() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f111() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f112() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f113() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f114() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f115() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f116() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f117() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f118() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f119() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f120() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f121() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f122() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f123() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f124() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f125() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f126() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f127() { entry: - %0 = load i32, i32* @foo, align 4 + %0 = load i32, ptr @foo, align 4 ret i32 %0 } define i32 @f128() { entry: - %0 = load i32, i32* @g0, align 4 + %0 = load i32, ptr @g0, align 4 ret i32 %0 } define i32 @f129() { entry: - %0 = load i32, i32* @g0, align 4 + %0 = load i32, ptr @g0, align 4 ret i32 %0 } diff --git a/lld/test/wasm/Inputs/tag-section1.ll b/lld/test/wasm/Inputs/tag-section1.ll --- a/lld/test/wasm/Inputs/tag-section1.ll +++ b/lld/test/wasm/Inputs/tag-section1.ll @@ -1,9 +1,9 @@ target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target triple = "wasm32-unknown-emscripten" -declare void @llvm.wasm.throw(i32, i8*) +declare void @llvm.wasm.throw(i32, ptr) -define void @foo(i8* %p) { - call void @llvm.wasm.throw(i32 0, i8* %p) +define void @foo(ptr %p) { + call void @llvm.wasm.throw(i32 0, ptr %p) ret void } diff --git a/lld/test/wasm/Inputs/tag-section2.ll b/lld/test/wasm/Inputs/tag-section2.ll --- a/lld/test/wasm/Inputs/tag-section2.ll +++ b/lld/test/wasm/Inputs/tag-section2.ll @@ -1,9 +1,9 @@ target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target triple = "wasm32-unknown-emscripten" -declare void @llvm.wasm.throw(i32, i8*) +declare void @llvm.wasm.throw(i32, ptr) -define void @bar(i8* %p) { - call void @llvm.wasm.throw(i32 0, i8* %p) +define void @bar(ptr %p) { + call void @llvm.wasm.throw(i32 0, ptr %p) ret void } diff --git a/lld/test/wasm/Inputs/weak-alias.ll b/lld/test/wasm/Inputs/weak-alias.ll --- a/lld/test/wasm/Inputs/weak-alias.ll +++ b/lld/test/wasm/Inputs/weak-alias.ll @@ -6,7 +6,7 @@ ret i32 0 } -@alias_fn = weak alias i32 (), i32 ()* @direct_fn +@alias_fn = weak alias i32 (), ptr @direct_fn define i32 @call_direct() #0 { entry: @@ -22,18 +22,18 @@ define i32 @call_alias_ptr() #0 { entry: - %fnptr = alloca i32 ()*, align 8 - store i32 ()* @alias_fn, i32 ()** %fnptr, align 8 - %0 = load i32 ()*, i32 ()** %fnptr, align 8 + %fnptr = alloca ptr, align 8 + store ptr @alias_fn, ptr %fnptr, align 8 + %0 = load ptr, ptr %fnptr, align 8 %call = call i32 %0() ret i32 %call } define i32 @call_direct_ptr() #0 { entry: - %fnptr = alloca i32 ()*, align 8 - store i32 ()* @direct_fn, i32 ()** %fnptr, align 8 - %0 = load i32 ()*, i32 ()** %fnptr, align 8 + %fnptr = alloca ptr, align 8 + store ptr @direct_fn, ptr %fnptr, align 8 + %0 = load ptr, ptr %fnptr, align 8 %call = call i32 %0() ret i32 %call } diff --git a/lld/test/wasm/gc-sections.ll b/lld/test/wasm/gc-sections.ll --- a/lld/test/wasm/gc-sections.ll +++ b/lld/test/wasm/gc-sections.ll @@ -15,12 +15,12 @@ @used_data = hidden global i32 2, align 4 define hidden i64 @unused_function(i64 %arg) { - %1 = load i64, i64* @unused_data, align 4 + %1 = load i64, ptr @unused_data, align 4 ret i64 %1 } define hidden i32 @used_function() { - %1 = load i32, i32* @used_data, align 4 + %1 = load i32, ptr @used_data, align 4 ret i32 %1 } diff --git a/lld/test/wasm/init-fini-no-gc.ll b/lld/test/wasm/init-fini-no-gc.ll --- a/lld/test/wasm/init-fini-no-gc.ll +++ b/lld/test/wasm/init-fini-no-gc.ll @@ -28,12 +28,12 @@ ret i32 0 } -@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [ - { i32, void ()*, i8* } { i32 1, void ()* @func1, i8* null } +@llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [ + { i32, ptr, ptr } { i32 1, ptr @func1, ptr null } ] -@llvm.global_dtors = appending global [1 x { i32, void ()*, i8* }] [ - { i32, void ()*, i8* } { i32 1, void ()* @func2, i8* null } +@llvm.global_dtors = appending global [1 x { i32, ptr, ptr }] [ + { i32, ptr, ptr } { i32 1, ptr @func2, ptr null } ] ; Check that we have exactly the needed exports: `memory` because that's diff --git a/lld/test/wasm/init-fini.ll b/lld/test/wasm/init-fini.ll --- a/lld/test/wasm/init-fini.ll +++ b/lld/test/wasm/init-fini.ll @@ -37,18 +37,18 @@ ret void } -@llvm.global_ctors = appending global [4 x { i32, void ()*, i8* }] [ - { i32, void ()*, i8* } { i32 1001, void ()* @func1, i8* null }, - { i32, void ()*, i8* } { i32 101, void ()* @func1, i8* null }, - { i32, void ()*, i8* } { i32 101, void ()* @func2, i8* null }, - { i32, void ()*, i8* } { i32 4000, void ()* @externCtor, i8* null } +@llvm.global_ctors = appending global [4 x { i32, ptr, ptr }] [ + { i32, ptr, ptr } { i32 1001, ptr @func1, ptr null }, + { i32, ptr, ptr } { i32 101, ptr @func1, ptr null }, + { i32, ptr, ptr } { i32 101, ptr @func2, ptr null }, + { i32, ptr, ptr } { i32 4000, ptr @externCtor, ptr null } ] -@llvm.global_dtors = appending global [4 x { i32, void ()*, i8* }] [ - { i32, void ()*, i8* } { i32 1001, void ()* @func3, i8* null }, - { i32, void ()*, i8* } { i32 101, void ()* @func3, i8* null }, - { i32, void ()*, i8* } { i32 101, void ()* @func4, i8* null }, - { i32, void ()*, i8* } { i32 4000, void ()* @externDtor, i8* null } +@llvm.global_dtors = appending global [4 x { i32, ptr, ptr }] [ + { i32, ptr, ptr } { i32 1001, ptr @func3, ptr null }, + { i32, ptr, ptr } { i32 101, ptr @func3, ptr null }, + { i32, ptr, ptr } { i32 101, ptr @func4, ptr null }, + { i32, ptr, ptr } { i32 4000, ptr @externDtor, ptr null } ] ; RUN: wasm-ld --allow-undefined %t.o %t.global-ctor-dtor.o -o %t.wasm diff --git a/lld/test/wasm/local-symbols.ll b/lld/test/wasm/local-symbols.ll --- a/lld/test/wasm/local-symbols.ll +++ b/lld/test/wasm/local-symbols.ll @@ -10,7 +10,7 @@ define internal i32 @baz() local_unnamed_addr { entry: - %0 = load i32, i32* @bar, align 4 + %0 = load i32, ptr @bar, align 4 ret i32 %0 } diff --git a/lld/test/wasm/lto/Inputs/thin1.ll b/lld/test/wasm/lto/Inputs/thin1.ll --- a/lld/test/wasm/lto/Inputs/thin1.ll +++ b/lld/test/wasm/lto/Inputs/thin1.ll @@ -6,9 +6,9 @@ define i32 @foo(i32 %goo) { entry: %goo.addr = alloca i32, align 4 - store i32 %goo, i32* %goo.addr, align 4 - %0 = load i32, i32* %goo.addr, align 4 - %1 = load i32, i32* %goo.addr, align 4 + store i32 %goo, ptr %goo.addr, align 4 + %0 = load i32, ptr %goo.addr, align 4 + %1 = load i32, ptr %goo.addr, align 4 %mul = mul nsw i32 %0, %1 ret i32 %mul } diff --git a/lld/test/wasm/lto/Inputs/thin2.ll b/lld/test/wasm/lto/Inputs/thin2.ll --- a/lld/test/wasm/lto/Inputs/thin2.ll +++ b/lld/test/wasm/lto/Inputs/thin2.ll @@ -6,8 +6,8 @@ define i32 @blah(i32 %meh) #0 { entry: %meh.addr = alloca i32, align 4 - store i32 %meh, i32* %meh.addr, align 4 - %0 = load i32, i32* %meh.addr, align 4 + store i32 %meh, ptr %meh.addr, align 4 + %0 = load i32, ptr %meh.addr, align 4 %sub = sub nsw i32 %0, 48 ret i32 %sub } diff --git a/lld/test/wasm/lto/atomics.ll b/lld/test/wasm/lto/atomics.ll --- a/lld/test/wasm/lto/atomics.ll +++ b/lld/test/wasm/lto/atomics.ll @@ -10,6 +10,6 @@ @foo = hidden global i32 1 define void @_start() { - %1 = load atomic i32, i32* @foo unordered, align 4 + %1 = load atomic i32, ptr @foo unordered, align 4 ret void } diff --git a/lld/test/wasm/lto/diagnostics.ll b/lld/test/wasm/lto/diagnostics.ll --- a/lld/test/wasm/lto/diagnostics.ll +++ b/lld/test/wasm/lto/diagnostics.ll @@ -8,15 +8,15 @@ target triple = "wasm32-unknown-unknown" define void @_start() { - call i8* @foo() + call ptr @foo() ret void } -define i8* @foo() { - %1 = call i8* @llvm.returnaddress(i32 0) - ret i8* %1 +define ptr @foo() { + %1 = call ptr @llvm.returnaddress(i32 0) + ret ptr %1 } -declare i8* @llvm.returnaddress(i32) +declare ptr @llvm.returnaddress(i32) ; CHECK: error: {{.*}} WebAssembly hasn't implemented __builtin_return_address diff --git a/lld/test/wasm/lto/libcall-archive.ll b/lld/test/wasm/lto/libcall-archive.ll --- a/lld/test/wasm/lto/libcall-archive.ll +++ b/lld/test/wasm/lto/libcall-archive.ll @@ -8,13 +8,13 @@ target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-n32:64-S128" target triple = "wasm32-unknown-unknown" -define void @_start(i8* %a, i8* %b) { +define void @_start(ptr %a, ptr %b) { entry: - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 1024, i1 false) + call void @llvm.memcpy.p0.p0.i64(ptr %a, ptr %b, i64 1024, i1 false) ret void } -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) +declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) ; CHECK: - Type: CUSTOM ; CHECK-NEXT: Name: name diff --git a/lld/test/wasm/lto/libcall-truncsfhf2.ll b/lld/test/wasm/lto/libcall-truncsfhf2.ll --- a/lld/test/wasm/lto/libcall-truncsfhf2.ll +++ b/lld/test/wasm/lto/libcall-truncsfhf2.ll @@ -11,9 +11,9 @@ @g_half = global half 0.0 define void @_start() { - %val1 = load float, float* @g_float + %val1 = load float, ptr @g_float %v0 = fptrunc float %val1 to half - store half %v0, half* @g_half + store half %v0, ptr @g_half ret void } diff --git a/lld/test/wasm/lto/relocatable-undefined.ll b/lld/test/wasm/lto/relocatable-undefined.ll --- a/lld/test/wasm/lto/relocatable-undefined.ll +++ b/lld/test/wasm/lto/relocatable-undefined.ll @@ -11,7 +11,7 @@ define i32 @foo() { entry: %0 = call i32 @missing_func() - %1 = load i32, i32* @missing_data, align 4 + %1 = load i32, ptr @missing_data, align 4 ret i32 %1 } diff --git a/lld/test/wasm/lto/tls.ll b/lld/test/wasm/lto/tls.ll --- a/lld/test/wasm/lto/tls.ll +++ b/lld/test/wasm/lto/tls.ll @@ -13,7 +13,7 @@ @tls_int = dso_local thread_local global i32 99 define i32 @get_tls() #0 { - %val = load i32, i32* @tls_int + %val = load i32, ptr @tls_int ret i32 %val } diff --git a/lld/test/wasm/lto/undef.ll b/lld/test/wasm/lto/undef.ll --- a/lld/test/wasm/lto/undef.ll +++ b/lld/test/wasm/lto/undef.ll @@ -11,14 +11,14 @@ ; differently with respect to signature checking. declare i32 @foo() -@ptr = global i8* bitcast (i32 ()* @foo to i8*), align 8 +@ptr = global ptr @foo, align 8 ; Ensure access to ptr is not inlined below, even under LTO -@llvm.used = appending global [1 x i8**] [i8** @ptr], section "llvm.metadata" +@llvm.used = appending global [1 x ptr] [ptr @ptr], section "llvm.metadata" define void @_start() { call i32 @bar() - %addr = load i32 ()*, i32 ()** bitcast (i8** @ptr to i32 ()**), align 8 + %addr = load ptr, ptr @ptr, align 8 call i32 %addr() ret void diff --git a/lld/test/wasm/lto/used.ll b/lld/test/wasm/lto/used.ll --- a/lld/test/wasm/lto/used.ll +++ b/lld/test/wasm/lto/used.ll @@ -13,7 +13,7 @@ @foo = external global i32 define void @_start() { - %val = load i32, i32* @foo, align 4 + %val = load i32, ptr @foo, align 4 %tobool = icmp ne i32 %val, 0 br i1 %tobool, label %callbar, label %return diff --git a/lld/test/wasm/pic-static.ll b/lld/test/wasm/pic-static.ll --- a/lld/test/wasm/pic-static.ll +++ b/lld/test/wasm/pic-static.ll @@ -14,22 +14,22 @@ @hidden_float = hidden global float 2.0 @missing_float = extern_weak global float -@ret32_ptr = global i32 (float)* @ret32, align 4 +@ret32_ptr = global ptr @ret32, align 4 -define i32 (float)* @getaddr_external() { - ret i32 (float)* @ret32; +define ptr @getaddr_external() { + ret ptr @ret32; } -define i32 (float)* @getaddr_missing_function() { - ret i32 (float)* @missing_function; +define ptr @getaddr_missing_function() { + ret ptr @missing_function; } -define i32 ()* @getaddr_hidden() { - ret i32 ()* @hidden_func; +define ptr @getaddr_hidden() { + ret ptr @hidden_func; } -define float* @getaddr_missing_float() { - ret float* @missing_float +define ptr @getaddr_missing_float() { + ret ptr @missing_float } define hidden i32 @hidden_func() { @@ -38,16 +38,16 @@ define void @_start() { entry: - %f = load float, float* @hidden_float, align 4 - %addr = load i32 (float)*, i32 (float)** @ret32_ptr, align 4 - %arg = load float, float* @global_float, align 4 + %f = load float, ptr @hidden_float, align 4 + %addr = load ptr, ptr @ret32_ptr, align 4 + %arg = load float, ptr @global_float, align 4 call i32 %addr(float %arg) - %addr2 = call i32 (float)* @getaddr_external() - %arg2 = load float, float* @hidden_float, align 4 + %addr2 = call ptr @getaddr_external() + %arg2 = load float, ptr @hidden_float, align 4 call i32 %addr2(float %arg2) - %addr3 = call i32 ()* @getaddr_hidden() + %addr3 = call ptr @getaddr_hidden() call i32 %addr3() ret void diff --git a/lld/test/wasm/pie.ll b/lld/test/wasm/pie.ll --- a/lld/test/wasm/pie.ll +++ b/lld/test/wasm/pie.ll @@ -7,24 +7,24 @@ @data = global i32 2, align 4 @data_external = external global i32 -@indirect_func = local_unnamed_addr global i32 ()* @foo, align 4 +@indirect_func = local_unnamed_addr global ptr @foo, align 4 -@data_addr = local_unnamed_addr global i32* @data, align 4 -@data_addr_external = local_unnamed_addr global i32* @data_external, align 4 +@data_addr = local_unnamed_addr global ptr @data, align 4 +@data_addr_external = local_unnamed_addr global ptr @data_external, align 4 define hidden i32 @foo() { entry: ; To ensure we use __stack_pointer %ptr = alloca i32 - %0 = load i32, i32* @data, align 4 - %1 = load i32 ()*, i32 ()** @indirect_func, align 4 + %0 = load i32, ptr @data, align 4 + %1 = load ptr, ptr @indirect_func, align 4 call i32 %1() ret i32 %0 } -define default i32** @get_data_address() { +define default ptr @get_data_address() { entry: - ret i32** @data_addr_external + ret ptr @data_addr_external } define void @_start() { diff --git a/lld/test/wasm/relocatable.ll b/lld/test/wasm/relocatable.ll --- a/lld/test/wasm/relocatable.ll +++ b/lld/test/wasm/relocatable.ll @@ -20,20 +20,20 @@ declare extern_weak i32 @bar_import() local_unnamed_addr @data_import = external global i64 -@func_addr1 = hidden global i32()* @my_func, align 4 -@func_addr2 = hidden global i32()* @foo_import, align 4 -@func_addr3 = hidden global i32()* @bar_import, align 4 -@data_addr1 = hidden global i64* @data_import, align 8 +@func_addr1 = hidden global ptr @my_func, align 4 +@func_addr2 = hidden global ptr @foo_import, align 4 +@func_addr3 = hidden global ptr @bar_import, align 4 +@data_addr1 = hidden global ptr @data_import, align 8 $func_comdat = comdat any @data_comdat = weak_odr constant [3 x i8] c"abc", comdat($func_comdat) define linkonce_odr i32 @func_comdat() comdat { entry: - ret i32 ptrtoint ([3 x i8]* @data_comdat to i32) + ret i32 ptrtoint (ptr @data_comdat to i32) } ; Test that __attribute__(used) (i.e NO_STRIP) is preserved in the relocated symbol table -@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @my_func to i8*)], section "llvm.metadata" +@llvm.used = appending global [1 x ptr] [ptr @my_func], section "llvm.metadata" define void @_start() { ret void diff --git a/lld/test/wasm/shared.s b/lld/test/wasm/shared.s --- a/lld/test/wasm/shared.s +++ b/lld/test/wasm/shared.s @@ -52,8 +52,8 @@ .section .text,"",@ foo: # %ptr = alloca i32 - # %0 = load i32, i32* @data, align 4 - # %1 = load i32 ()*, i32 ()** @indirect_func, align 4 + # %0 = load i32, ptr @data, align 4 + # %1 = load ptr, ptr @indirect_func, align 4 # call i32 %1() # ret i32 %0 .functype foo () -> (i32) diff --git a/lld/test/wasm/shared64.s b/lld/test/wasm/shared64.s --- a/lld/test/wasm/shared64.s +++ b/lld/test/wasm/shared64.s @@ -52,8 +52,8 @@ .section .text,"",@ foo: # %ptr = alloca i32 - # %0 = load i32, i32* @data, align 4 - # %1 = load i32 ()*, i32 ()** @indirect_func, align 4 + # %0 = load i32, ptr @data, align 4 + # %1 = load ptr, ptr @indirect_func, align 4 # call i32 %1() # ret i32 %0 .functype foo () -> (i32) diff --git a/lld/test/wasm/signature-mismatch-unknown.ll b/lld/test/wasm/signature-mismatch-unknown.ll --- a/lld/test/wasm/signature-mismatch-unknown.ll +++ b/lld/test/wasm/signature-mismatch-unknown.ll @@ -18,10 +18,10 @@ ; Simply taking the address of the function should *not* generate the ; the signature mismatch warning. -@ptr = dso_local global i8* bitcast (void ()* @ret32 to i8*), align 8 +@ptr = dso_local global ptr @ret32, align 8 define hidden void @_start() local_unnamed_addr { - %addr = load i32 ()*, i32 ()** bitcast (i8** @ptr to i32 ()**), align 8 + %addr = load ptr, ptr @ptr, align 8 call i32 %addr() ret void } diff --git a/lld/test/wasm/startstop.ll b/lld/test/wasm/startstop.ll --- a/lld/test/wasm/startstop.ll +++ b/lld/test/wasm/startstop.ll @@ -9,15 +9,15 @@ @foo = global i32 3, section "mysection", align 4 @bar = global i32 4, section "mysection", align 4 -@__start_mysection = external global i8* -@__stop_mysection = external global i8* +@__start_mysection = external global ptr +@__stop_mysection = external global ptr -define i8** @get_start() { - ret i8** @__start_mysection +define ptr @get_start() { + ret ptr @__start_mysection } -define i8** @get_end() { - ret i8** @__stop_mysection +define ptr @get_end() { + ret ptr @__stop_mysection } define void @_start() { diff --git a/lld/test/wasm/tag-section.ll b/lld/test/wasm/tag-section.ll --- a/lld/test/wasm/tag-section.ll +++ b/lld/test/wasm/tag-section.ll @@ -17,12 +17,12 @@ target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" target triple = "wasm32-unknown-emscripten" -declare void @foo(i8*) -declare void @bar(i8*) +declare void @foo(ptr) +declare void @bar(ptr) define void @_start() { - call void @foo(i8* null) - call void @bar(i8* null) + call void @foo(ptr null) + call void @bar(ptr null) ret void } diff --git a/lld/test/wasm/undefined.ll b/lld/test/wasm/undefined.ll --- a/lld/test/wasm/undefined.ll +++ b/lld/test/wasm/undefined.ll @@ -16,8 +16,8 @@ target triple = "wasm32-unknown-unknown" ; Takes the address of the external foo() resulting in undefined external -@bar = global i8* bitcast (i32 ()* @foo to i8*), align 4 -@llvm.used = appending global [1 x i8**] [i8** @bar], section "llvm.metadata" +@bar = global ptr @foo, align 4 +@llvm.used = appending global [1 x ptr] [ptr @bar], section "llvm.metadata" declare i32 @foo() #0 diff --git a/lld/tools/lld/lld.cpp b/lld/tools/lld/lld.cpp --- a/lld/tools/lld/lld.cpp +++ b/lld/tools/lld/lld.cpp @@ -41,6 +41,7 @@ #include "llvm/Support/PluginLoader.h" #include "llvm/Support/Process.h" #include +#include using namespace lld; using namespace llvm; @@ -228,7 +229,7 @@ return lldMain(argc, const_cast(argv), llvm::outs(), llvm::errs()); - Optional mainRet; + std::optional mainRet; CrashRecoveryContext::Enable(); for (unsigned i = inTestVerbosity(); i > 0; --i) { diff --git a/lldb/include/lldb/Symbol/CompilerType.h b/lldb/include/lldb/Symbol/CompilerType.h --- a/lldb/include/lldb/Symbol/CompilerType.h +++ b/lldb/include/lldb/Symbol/CompilerType.h @@ -203,6 +203,8 @@ bool GetCompleteType() const; /// \} + bool IsForcefullyCompleted() const; + /// AST related queries. /// \{ size_t GetPointerByteSize() const; diff --git a/lldb/include/lldb/Symbol/TypeSystem.h b/lldb/include/lldb/Symbol/TypeSystem.h --- a/lldb/include/lldb/Symbol/TypeSystem.h +++ b/lldb/include/lldb/Symbol/TypeSystem.h @@ -202,6 +202,10 @@ virtual bool GetCompleteType(lldb::opaque_compiler_type_t type) = 0; + virtual bool IsForcefullyCompleted(lldb::opaque_compiler_type_t type) { + return false; + } + // AST related queries virtual uint32_t GetPointerByteSize() = 0; diff --git a/lldb/include/lldb/Utility/Timeout.h b/lldb/include/lldb/Utility/Timeout.h --- a/lldb/include/lldb/Utility/Timeout.h +++ b/lldb/include/lldb/Utility/Timeout.h @@ -36,7 +36,7 @@ using Base = llvm::Optional>; public: - Timeout(llvm::NoneType none) : Base(none) {} + Timeout(std::nullopt_t none) : Base(none) {} template ::type> diff --git a/lldb/packages/Python/lldbsuite/test/lldbtest.py b/lldb/packages/Python/lldbsuite/test/lldbtest.py --- a/lldb/packages/Python/lldbsuite/test/lldbtest.py +++ b/lldb/packages/Python/lldbsuite/test/lldbtest.py @@ -246,7 +246,7 @@ class ValueCheck: def __init__(self, name=None, value=None, type=None, summary=None, - children=None, dereference=None): + children=None): """ :param name: The name that the SBValue should have. None if the summary should not be checked. @@ -261,15 +261,12 @@ The order of checks is the order of the checks in the list. The number of checks has to match the number of children. - :param dereference: A ValueCheck for the SBValue returned by the - `Dereference` function. """ self.expect_name = name self.expect_value = value self.expect_type = type self.expect_summary = summary self.children = children - self.dereference = dereference def check_value(self, test_base, val, error_msg=None): """ @@ -311,9 +308,6 @@ if self.children is not None: self.check_value_children(test_base, val, error_msg) - if self.dereference is not None: - self.dereference.check_value(test_base, val.Dereference(), error_msg) - def check_value_children(self, test_base, val, error_msg=None): """ Checks that the children of a SBValue match a certain structure and diff --git a/lldb/source/API/SBType.cpp b/lldb/source/API/SBType.cpp --- a/lldb/source/API/SBType.cpp +++ b/lldb/source/API/SBType.cpp @@ -490,7 +490,12 @@ if (!IsValid()) return false; - return m_opaque_sp->GetCompilerType(false).IsCompleteType(); + CompilerType compiler_type = m_opaque_sp->GetCompilerType(false); + // Only return true if we have a complete type and it wasn't forcefully + // completed. + if (compiler_type.IsCompleteType()) + return !compiler_type.IsForcefullyCompleted(); + return false; } uint32_t SBType::GetTypeFlags() { diff --git a/lldb/source/Core/ValueObject.cpp b/lldb/source/Core/ValueObject.cpp --- a/lldb/source/Core/ValueObject.cpp +++ b/lldb/source/Core/ValueObject.cpp @@ -594,6 +594,14 @@ const TypeSummaryOptions &options) { destination.clear(); + // If we have a forcefully completed type, don't try and show a summary from + // a valid summary string or function because the type is not complete and + // no member variables or member functions will be available. + if (GetCompilerType().IsForcefullyCompleted()) { + destination = ""; + return true; + } + // ideally we would like to bail out if passing NULL, but if we do so we end // up not providing the summary for function pointers anymore if (/*summary_ptr == NULL ||*/ m_flags.m_is_getting_summary) diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp --- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp +++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp @@ -102,7 +102,7 @@ } static uint32_t FPREncodingToLLDB(uint32_t reg_encode) { - if (reg_encode >= 0 && reg_encode <= 31) + if (reg_encode <= 31) return fpr_f0_riscv + reg_encode; return LLDB_INVALID_REGNUM; } diff --git a/lldb/source/Plugins/JITLoader/GDB/JITLoaderGDB.cpp b/lldb/source/Plugins/JITLoader/GDB/JITLoaderGDB.cpp --- a/lldb/source/Plugins/JITLoader/GDB/JITLoaderGDB.cpp +++ b/lldb/source/Plugins/JITLoader/GDB/JITLoaderGDB.cpp @@ -190,7 +190,7 @@ __FUNCTION__); addr_t jit_addr = GetSymbolAddress( - module_list, ConstString("__jit_debug_register_code"), eSymbolTypeAny); + module_list, ConstString("__jit_debug_register_code"), eSymbolTypeCode); if (jit_addr == LLDB_INVALID_ADDRESS) return; diff --git a/lldb/source/Plugins/Language/CPlusPlus/Coroutines.h b/lldb/source/Plugins/Language/CPlusPlus/Coroutines.h --- a/lldb/source/Plugins/Language/CPlusPlus/Coroutines.h +++ b/lldb/source/Plugins/Language/CPlusPlus/Coroutines.h @@ -47,9 +47,7 @@ size_t GetIndexOfChildWithName(ConstString name) override; private: - lldb::ValueObjectSP m_resume_ptr_sp; - lldb::ValueObjectSP m_destroy_ptr_sp; - lldb::ValueObjectSP m_promise_ptr_sp; + lldb::ValueObjectSP m_frame_ptr_sp; std::unique_ptr m_ast_importer; }; diff --git a/lldb/source/Plugins/Language/CPlusPlus/Coroutines.cpp b/lldb/source/Plugins/Language/CPlusPlus/Coroutines.cpp --- a/lldb/source/Plugins/Language/CPlusPlus/Coroutines.cpp +++ b/lldb/source/Plugins/Language/CPlusPlus/Coroutines.cpp @@ -17,97 +17,54 @@ using namespace lldb_private; using namespace lldb_private::formatters; -static lldb::addr_t GetCoroFramePtrFromHandle(ValueObjectSP valobj_sp) { +static ValueObjectSP GetCoroFramePtrFromHandle(ValueObject &valobj) { + ValueObjectSP valobj_sp(valobj.GetNonSyntheticValue()); if (!valobj_sp) - return LLDB_INVALID_ADDRESS; + return nullptr; // We expect a single pointer in the `coroutine_handle` class. // We don't care about its name. if (valobj_sp->GetNumChildren() != 1) - return LLDB_INVALID_ADDRESS; + return nullptr; ValueObjectSP ptr_sp(valobj_sp->GetChildAtIndex(0, true)); if (!ptr_sp) - return LLDB_INVALID_ADDRESS; + return nullptr; if (!ptr_sp->GetCompilerType().IsPointerType()) - return LLDB_INVALID_ADDRESS; - - AddressType addr_type; - lldb::addr_t frame_ptr_addr = ptr_sp->GetPointerValue(&addr_type); - if (!frame_ptr_addr || frame_ptr_addr == LLDB_INVALID_ADDRESS) - return LLDB_INVALID_ADDRESS; - lldbassert(addr_type == AddressType::eAddressTypeLoad); - if (addr_type != AddressType::eAddressTypeLoad) - return LLDB_INVALID_ADDRESS; + return nullptr; - return frame_ptr_addr; + return ptr_sp; } -static Function *ExtractFunction(lldb::TargetSP target_sp, - lldb::addr_t frame_ptr_addr, int offset) { - lldb::ProcessSP process_sp = target_sp->GetProcessSP(); +static Function *ExtractDestroyFunction(ValueObjectSP &frame_ptr_sp) { + lldb::TargetSP target_sp = frame_ptr_sp->GetTargetSP(); + lldb::ProcessSP process_sp = frame_ptr_sp->GetProcessSP(); auto ptr_size = process_sp->GetAddressByteSize(); + AddressType addr_type; + lldb::addr_t frame_ptr_addr = frame_ptr_sp->GetPointerValue(&addr_type); + if (!frame_ptr_addr || frame_ptr_addr == LLDB_INVALID_ADDRESS) + return nullptr; + lldbassert(addr_type == AddressType::eAddressTypeLoad); + Status error; - auto func_ptr_addr = frame_ptr_addr + offset * ptr_size; - lldb::addr_t func_addr = - process_sp->ReadPointerFromMemory(func_ptr_addr, error); + // The destroy pointer is the 2nd pointer inside the compiler-generated + // `pair`. + auto destroy_func_ptr_addr = frame_ptr_addr + ptr_size; + lldb::addr_t destroy_func_addr = + process_sp->ReadPointerFromMemory(destroy_func_ptr_addr, error); if (error.Fail()) return nullptr; - Address func_address; - if (!target_sp->ResolveLoadAddress(func_addr, func_address)) + Address destroy_func_address; + if (!target_sp->ResolveLoadAddress(destroy_func_addr, destroy_func_address)) return nullptr; - return func_address.CalculateSymbolContextFunction(); -} - -static Function *ExtractResumeFunction(lldb::TargetSP target_sp, - lldb::addr_t frame_ptr_addr) { - return ExtractFunction(target_sp, frame_ptr_addr, 0); -} - -static Function *ExtractDestroyFunction(lldb::TargetSP target_sp, - lldb::addr_t frame_ptr_addr) { - return ExtractFunction(target_sp, frame_ptr_addr, 1); -} - -static bool IsNoopCoroFunction(Function *f) { - if (!f) - return false; - - // clang's `__builtin_coro_noop` gets lowered to - // `_NoopCoro_ResumeDestroy`. This is used by libc++ - // on clang. - auto mangledName = f->GetMangled().GetMangledName(); - if (mangledName == "__NoopCoro_ResumeDestroy") - return true; - - // libc++ uses the following name as a fallback on - // compilers without `__builtin_coro_noop`. - auto name = f->GetNameNoArguments(); - static RegularExpression libcxxRegex( - "^std::coroutine_handle::" - "__noop_coroutine_frame_ty_::__dummy_resume_destroy_func$"); - lldbassert(libcxxRegex.IsValid()); - if (libcxxRegex.Execute(name.GetStringRef())) - return true; - static RegularExpression libcxxRegexAbiNS( - "^std::__[[:alnum:]]+::coroutine_handle::__noop_coroutine_frame_ty_::" - "__dummy_resume_destroy_func$"); - lldbassert(libcxxRegexAbiNS.IsValid()); - if (libcxxRegexAbiNS.Execute(name.GetStringRef())) - return true; - - // libstdc++ uses the following name on both gcc and clang. - static RegularExpression libstdcppRegex( - "^std::__[[:alnum:]]+::coroutine_handle::__frame::__dummy_resume_destroy$"); - lldbassert(libstdcppRegex.IsValid()); - if (libstdcppRegex.Execute(name.GetStringRef())) - return true; + Function *destroy_func = + destroy_func_address.CalculateSymbolContextFunction(); + if (!destroy_func) + return nullptr; - return false; + return destroy_func; } static CompilerType InferPromiseType(Function &destroy_func) { @@ -128,26 +85,37 @@ return promise_type->GetForwardCompilerType(); } +static CompilerType GetCoroutineFrameType(TypeSystemClang &ast_ctx, + CompilerType promise_type) { + CompilerType void_type = ast_ctx.GetBasicType(lldb::eBasicTypeVoid); + CompilerType coro_func_type = ast_ctx.CreateFunctionType( + /*result_type=*/void_type, /*args=*/&void_type, /*num_args=*/1, + /*is_variadic=*/false, /*qualifiers=*/0); + CompilerType coro_abi_type; + if (promise_type.IsVoidType()) { + coro_abi_type = ast_ctx.CreateStructForIdentifier( + ConstString(), {{"resume", coro_func_type.GetPointerType()}, + {"destroy", coro_func_type.GetPointerType()}}); + } else { + coro_abi_type = ast_ctx.CreateStructForIdentifier( + ConstString(), {{"resume", coro_func_type.GetPointerType()}, + {"destroy", coro_func_type.GetPointerType()}, + {"promise", promise_type}}); + } + return coro_abi_type; +} + bool lldb_private::formatters::StdlibCoroutineHandleSummaryProvider( ValueObject &valobj, Stream &stream, const TypeSummaryOptions &options) { - lldb::addr_t frame_ptr_addr = - GetCoroFramePtrFromHandle(valobj.GetNonSyntheticValue()); - if (frame_ptr_addr == LLDB_INVALID_ADDRESS) + ValueObjectSP ptr_sp(GetCoroFramePtrFromHandle(valobj)); + if (!ptr_sp) return false; - if (frame_ptr_addr == 0) { + if (!ptr_sp->GetValueAsUnsigned(0)) { stream << "nullptr"; - return true; - } - - lldb::TargetSP target_sp = valobj.GetTargetSP(); - if (IsNoopCoroFunction(ExtractResumeFunction(target_sp, frame_ptr_addr)) && - IsNoopCoroFunction(ExtractDestroyFunction(target_sp, frame_ptr_addr))) { - stream << "noop_coroutine"; - return true; + } else { + stream.Printf("coro frame = 0x%" PRIx64, ptr_sp->GetValueAsUnsigned(0)); } - - stream.Printf("coro frame = 0x%" PRIx64, frame_ptr_addr); return true; } @@ -164,68 +132,32 @@ size_t lldb_private::formatters::StdlibCoroutineHandleSyntheticFrontEnd:: CalculateNumChildren() { - if (!m_resume_ptr_sp || !m_destroy_ptr_sp) + if (!m_frame_ptr_sp) return 0; - return m_promise_ptr_sp ? 3 : 2; + return m_frame_ptr_sp->GetNumChildren(); } lldb::ValueObjectSP lldb_private::formatters:: StdlibCoroutineHandleSyntheticFrontEnd::GetChildAtIndex(size_t idx) { - switch (idx) { - case 0: - return m_resume_ptr_sp; - case 1: - return m_destroy_ptr_sp; - case 2: - return m_promise_ptr_sp; - } - return lldb::ValueObjectSP(); + if (!m_frame_ptr_sp) + return lldb::ValueObjectSP(); + + return m_frame_ptr_sp->GetChildAtIndex(idx, true); } bool lldb_private::formatters::StdlibCoroutineHandleSyntheticFrontEnd:: Update() { - m_resume_ptr_sp.reset(); - m_destroy_ptr_sp.reset(); - m_promise_ptr_sp.reset(); + m_frame_ptr_sp.reset(); - ValueObjectSP valobj_sp = m_backend.GetNonSyntheticValue(); + ValueObjectSP valobj_sp = m_backend.GetSP(); if (!valobj_sp) return false; - lldb::addr_t frame_ptr_addr = GetCoroFramePtrFromHandle(valobj_sp); - if (frame_ptr_addr == 0 || frame_ptr_addr == LLDB_INVALID_ADDRESS) - return false; - - lldb::TargetSP target_sp = m_backend.GetTargetSP(); - Function *resume_func = ExtractResumeFunction(target_sp, frame_ptr_addr); - Function *destroy_func = ExtractDestroyFunction(target_sp, frame_ptr_addr); - - // For `std::noop_coroutine()`, we don't want to display any child nodes. - if (IsNoopCoroFunction(resume_func) && IsNoopCoroFunction(destroy_func)) + ValueObjectSP ptr_sp(GetCoroFramePtrFromHandle(m_backend)); + if (!ptr_sp) return false; - auto ts = valobj_sp->GetCompilerType().GetTypeSystem(); - auto ast_ctx = ts.dyn_cast_or_null(); - if (!ast_ctx) - return {}; - - // Create the `resume` and `destroy` children - auto &exe_ctx = m_backend.GetExecutionContextRef(); - lldb::ProcessSP process_sp = target_sp->GetProcessSP(); - auto ptr_size = process_sp->GetAddressByteSize(); - CompilerType void_type = ast_ctx->GetBasicType(lldb::eBasicTypeVoid); - CompilerType coro_func_type = ast_ctx->CreateFunctionType( - /*result_type=*/void_type, /*args=*/&void_type, /*num_args=*/1, - /*is_variadic=*/false, /*qualifiers=*/0); - CompilerType coro_func_ptr_type = coro_func_type.GetPointerType(); - m_resume_ptr_sp = CreateValueObjectFromAddress( - "resume", frame_ptr_addr + 0 * ptr_size, exe_ctx, coro_func_ptr_type); - lldbassert(m_resume_ptr_sp); - m_destroy_ptr_sp = CreateValueObjectFromAddress( - "destroy", frame_ptr_addr + 1 * ptr_size, exe_ctx, coro_func_ptr_type); - lldbassert(m_destroy_ptr_sp); - // Get the `promise_type` from the template argument CompilerType promise_type( valobj_sp->GetCompilerType().GetTypeTemplateArgument(0)); @@ -233,23 +165,23 @@ return false; // Try to infer the promise_type if it was type-erased - if (promise_type.IsVoidType() && destroy_func) { - if (CompilerType inferred_type = InferPromiseType(*destroy_func)) { - // Copy the type over to the correct `TypeSystemClang` instance - promise_type = m_ast_importer->CopyType(*ast_ctx, inferred_type); + auto ts = valobj_sp->GetCompilerType().GetTypeSystem(); + auto ast_ctx = ts.dyn_cast_or_null(); + if (!ast_ctx) + return false; + if (promise_type.IsVoidType()) { + if (Function *destroy_func = ExtractDestroyFunction(ptr_sp)) { + if (CompilerType inferred_type = InferPromiseType(*destroy_func)) { + // Copy the type over to the correct `TypeSystemClang` instance + promise_type = m_ast_importer->CopyType(*ast_ctx, inferred_type); + } } } - // Add the `promise` member. We intentionally add `promise` as a pointer type - // instead of a value type, and don't automatically dereference this pointer. - // We do so to avoid potential very deep recursion in case there is a cycle in - // formed between `std::coroutine_handle`s and their promises. - lldb::ValueObjectSP promise = CreateValueObjectFromAddress( - "promise", frame_ptr_addr + 2 * ptr_size, exe_ctx, promise_type); - Status error; - lldb::ValueObjectSP promisePtr = promise->AddressOf(error); - if (error.Success()) - m_promise_ptr_sp = promisePtr->Clone(ConstString("promise")); + // Build the coroutine frame type + CompilerType coro_frame_type = GetCoroutineFrameType(*ast_ctx, promise_type); + + m_frame_ptr_sp = ptr_sp->Cast(coro_frame_type.GetPointerType()); return false; } @@ -261,17 +193,10 @@ size_t StdlibCoroutineHandleSyntheticFrontEnd::GetIndexOfChildWithName( ConstString name) { - if (!m_resume_ptr_sp || !m_destroy_ptr_sp) + if (!m_frame_ptr_sp) return UINT32_MAX; - if (name == ConstString("resume")) - return 0; - if (name == ConstString("destroy")) - return 1; - if (name == ConstString("promise_ptr") && m_promise_ptr_sp) - return 2; - - return UINT32_MAX; + return m_frame_ptr_sp->GetIndexOfChildWithName(name); } SyntheticChildrenFrontEnd * diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86_64.cpp b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86_64.cpp --- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86_64.cpp +++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86_64.cpp @@ -434,7 +434,7 @@ return error; } - RegSetKind set = opt_set.getValue(); + RegSetKind set = opt_set.value(); error = ReadRegisterSet(set); if (error.Fail()) return error; @@ -500,7 +500,7 @@ return error; } - RegSetKind set = opt_set.getValue(); + RegSetKind set = opt_set.value(); error = ReadRegisterSet(set); if (error.Fail()) return error; diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h --- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h +++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h @@ -30,6 +30,8 @@ uint32_t GetRegisterSetCount() const override; + uint32_t GetUserRegisterCount() const override; + const RegisterSet *GetRegisterSet(uint32_t set_index) const override; Status ReadRegister(const RegisterInfo *reg_info, @@ -42,7 +44,22 @@ Status WriteAllRegisterValues(const lldb::DataBufferSP &data_sp) override; + void InvalidateAllRegisters() override; + + std::vector + GetExpeditedRegisters(ExpeditedRegs expType) const override; + + bool RegisterOffsetIsDynamic() const override { return true; } + protected: + Status ReadGPR() override; + + Status WriteGPR() override; + + Status ReadFPR() override; + + Status WriteFPR() override; + void *GetGPRBuffer() override { return &m_gpr; } void *GetFPRBuffer() override { return &m_fpr; } @@ -52,10 +69,19 @@ size_t GetFPRSize() override { return GetRegisterInfo().GetFPRSize(); } private: + bool m_gpr_is_valid; + bool m_fpu_is_valid; + RegisterInfoPOSIX_loongarch64::GPR m_gpr; RegisterInfoPOSIX_loongarch64::FPR m_fpr; + bool IsGPR(unsigned reg) const; + + bool IsFPR(unsigned reg) const; + + uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const; + const RegisterInfoPOSIX_loongarch64 &GetRegisterInfo() const; }; diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp --- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp +++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp @@ -18,6 +18,15 @@ #include "Plugins/Process/Linux/NativeProcessLinux.h" #include "Plugins/Process/Linux/Procfs.h" +#include "Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h" +#include "Plugins/Process/Utility/lldb-loongarch-register-enums.h" + +// NT_PRSTATUS and NT_FPREGSET definition +#include +// struct iovec definition +#include + +#define REG_CONTEXT_SIZE (GetGPRSize() + GetFPRSize()) using namespace lldb; using namespace lldb_private; @@ -52,6 +61,9 @@ NativeRegisterContextLinux(native_thread) { ::memset(&m_fpr, 0, sizeof(m_fpr)); ::memset(&m_gpr, 0, sizeof(m_gpr)); + + m_gpr_is_valid = false; + m_fpu_is_valid = false; } const RegisterInfoPOSIX_loongarch64 & @@ -69,24 +81,258 @@ return GetRegisterInfo().GetRegisterSet(set_index); } +uint32_t NativeRegisterContextLinux_loongarch64::GetUserRegisterCount() const { + uint32_t count = 0; + for (uint32_t set_index = 0; set_index < GetRegisterSetCount(); ++set_index) + count += GetRegisterSet(set_index)->num_registers; + return count; +} + Status NativeRegisterContextLinux_loongarch64::ReadRegister( const RegisterInfo *reg_info, RegisterValue ®_value) { - return Status("Failed to read register value"); + Status error; + + if (!reg_info) { + error.SetErrorString("reg_info NULL"); + return error; + } + + const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB]; + + if (reg == LLDB_INVALID_REGNUM) + return Status("no lldb regnum for %s", reg_info && reg_info->name + ? reg_info->name + : ""); + + uint8_t *src = nullptr; + uint32_t offset = LLDB_INVALID_INDEX32; + + if (IsGPR(reg)) { + error = ReadGPR(); + if (error.Fail()) + return error; + + offset = reg_info->byte_offset; + assert(offset < GetGPRSize()); + src = (uint8_t *)GetGPRBuffer() + offset; + + } else if (IsFPR(reg)) { + error = ReadFPR(); + if (error.Fail()) + return error; + + offset = CalculateFprOffset(reg_info); + assert(offset < GetFPRSize()); + src = (uint8_t *)GetFPRBuffer() + offset; + } else + return Status("failed - register wasn't recognized to be a GPR or an FPR, " + "write strategy unknown"); + + reg_value.SetFromMemoryData(*reg_info, src, reg_info->byte_size, + eByteOrderLittle, error); + + return error; } Status NativeRegisterContextLinux_loongarch64::WriteRegister( const RegisterInfo *reg_info, const RegisterValue ®_value) { + Status error; + + if (!reg_info) + return Status("reg_info NULL"); + + const uint32_t reg = reg_info->kinds[lldb::eRegisterKindLLDB]; + + if (reg == LLDB_INVALID_REGNUM) + return Status("no lldb regnum for %s", reg_info->name != nullptr + ? reg_info->name + : ""); + + uint8_t *dst = nullptr; + uint32_t offset = LLDB_INVALID_INDEX32; + + if (IsGPR(reg)) { + error = ReadGPR(); + if (error.Fail()) + return error; + + assert(reg_info->byte_offset < GetGPRSize()); + dst = (uint8_t *)GetGPRBuffer() + reg_info->byte_offset; + ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size); + + return WriteGPR(); + } else if (IsFPR(reg)) { + error = ReadFPR(); + if (error.Fail()) + return error; + + offset = CalculateFprOffset(reg_info); + assert(offset < GetFPRSize()); + dst = (uint8_t *)GetFPRBuffer() + offset; + ::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size); + + return WriteFPR(); + } + return Status("Failed to write register value"); } Status NativeRegisterContextLinux_loongarch64::ReadAllRegisterValues( lldb::WritableDataBufferSP &data_sp) { - return Status("Failed to read all register values"); + Status error; + + data_sp.reset(new DataBufferHeap(REG_CONTEXT_SIZE, 0)); + + error = ReadGPR(); + if (error.Fail()) + return error; + + error = ReadFPR(); + if (error.Fail()) + return error; + + uint8_t *dst = data_sp->GetBytes(); + ::memcpy(dst, GetGPRBuffer(), GetGPRSize()); + dst += GetGPRSize(); + ::memcpy(dst, GetFPRBuffer(), GetFPRSize()); + + return error; } Status NativeRegisterContextLinux_loongarch64::WriteAllRegisterValues( const lldb::DataBufferSP &data_sp) { - return Status("Failed to write all register values"); + Status error; + + if (!data_sp) { + error.SetErrorStringWithFormat( + "NativeRegisterContextLinux_loongarch64::%s invalid data_sp provided", + __FUNCTION__); + return error; + } + + if (data_sp->GetByteSize() != REG_CONTEXT_SIZE) { + error.SetErrorStringWithFormat( + "NativeRegisterContextLinux_loongarch64::%s data_sp contained " + "mismatched data size, expected %" PRIu64 ", actual %" PRIu64, + __FUNCTION__, REG_CONTEXT_SIZE, data_sp->GetByteSize()); + return error; + } + + const uint8_t *src = data_sp->GetBytes(); + if (src == nullptr) { + error.SetErrorStringWithFormat("NativeRegisterContextLinux_loongarch64::%s " + "DataBuffer::GetBytes() returned a null " + "pointer", + __FUNCTION__); + return error; + } + ::memcpy(GetGPRBuffer(), src, GetRegisterInfoInterface().GetGPRSize()); + + error = WriteGPR(); + if (error.Fail()) + return error; + + src += GetRegisterInfoInterface().GetGPRSize(); + ::memcpy(GetFPRBuffer(), src, GetFPRSize()); + + error = WriteFPR(); + if (error.Fail()) + return error; + + return error; +} + +bool NativeRegisterContextLinux_loongarch64::IsGPR(unsigned reg) const { + return GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) == + RegisterInfoPOSIX_loongarch64::GPRegSet; +} + +bool NativeRegisterContextLinux_loongarch64::IsFPR(unsigned reg) const { + return GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) == + RegisterInfoPOSIX_loongarch64::FPRegSet; +} + +Status NativeRegisterContextLinux_loongarch64::ReadGPR() { + Status error; + + if (m_gpr_is_valid) + return error; + + struct iovec ioVec; + ioVec.iov_base = GetGPRBuffer(); + ioVec.iov_len = GetGPRSize(); + + error = ReadRegisterSet(&ioVec, GetGPRSize(), NT_PRSTATUS); + + if (error.Success()) + m_gpr_is_valid = true; + + return error; +} + +Status NativeRegisterContextLinux_loongarch64::WriteGPR() { + Status error = ReadGPR(); + if (error.Fail()) + return error; + + struct iovec ioVec; + ioVec.iov_base = GetGPRBuffer(); + ioVec.iov_len = GetGPRSize(); + + m_gpr_is_valid = false; + + return WriteRegisterSet(&ioVec, GetGPRSize(), NT_PRSTATUS); +} + +Status NativeRegisterContextLinux_loongarch64::ReadFPR() { + Status error; + + if (m_fpu_is_valid) + return error; + + struct iovec ioVec; + ioVec.iov_base = GetFPRBuffer(); + ioVec.iov_len = GetFPRSize(); + + error = ReadRegisterSet(&ioVec, GetFPRSize(), NT_FPREGSET); + + if (error.Success()) + m_fpu_is_valid = true; + + return error; +} + +Status NativeRegisterContextLinux_loongarch64::WriteFPR() { + Status error = ReadFPR(); + if (error.Fail()) + return error; + + struct iovec ioVec; + ioVec.iov_base = GetFPRBuffer(); + ioVec.iov_len = GetFPRSize(); + + m_fpu_is_valid = false; + + return WriteRegisterSet(&ioVec, GetFPRSize(), NT_FPREGSET); +} + +void NativeRegisterContextLinux_loongarch64::InvalidateAllRegisters() { + m_gpr_is_valid = false; + m_fpu_is_valid = false; +} + +uint32_t NativeRegisterContextLinux_loongarch64::CalculateFprOffset( + const RegisterInfo *reg_info) const { + return reg_info->byte_offset - GetGPRSize(); +} + +std::vector +NativeRegisterContextLinux_loongarch64::GetExpeditedRegisters( + ExpeditedRegs expType) const { + std::vector expedited_reg_nums = + NativeRegisterContext::GetExpeditedRegisters(expType); + + return expedited_reg_nums; } #endif // defined(__loongarch__) && __loongarch_grlen == 64 diff --git a/lldb/source/Plugins/Process/Utility/CMakeLists.txt b/lldb/source/Plugins/Process/Utility/CMakeLists.txt --- a/lldb/source/Plugins/Process/Utility/CMakeLists.txt +++ b/lldb/source/Plugins/Process/Utility/CMakeLists.txt @@ -38,6 +38,7 @@ RegisterContextOpenBSD_x86_64.cpp RegisterContextPOSIX_arm.cpp RegisterContextPOSIX_arm64.cpp + RegisterContextPOSIX_loongarch64.cpp RegisterContextPOSIX_mips64.cpp RegisterContextPOSIX_powerpc.cpp RegisterContextPOSIX_ppc64le.cpp diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h new file mode 100644 --- /dev/null +++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h @@ -0,0 +1,63 @@ +//===-- RegisterContextPOSIX_loongarch64.h ----------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_LOONGARCH64_H +#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_LOONGARCH64_H + +#include "RegisterInfoInterface.h" +#include "RegisterInfoPOSIX_loongarch64.h" +#include "lldb-loongarch-register-enums.h" +#include "lldb/Target/RegisterContext.h" +#include "lldb/Utility/Log.h" + +class RegisterContextPOSIX_loongarch64 : public lldb_private::RegisterContext { +public: + RegisterContextPOSIX_loongarch64( + lldb_private::Thread &thread, + std::unique_ptr register_info); + + ~RegisterContextPOSIX_loongarch64() override; + + void invalidate(); + + void InvalidateAllRegisters() override; + + size_t GetRegisterCount() override; + + virtual size_t GetGPRSize(); + + virtual unsigned GetRegisterSize(unsigned reg); + + virtual unsigned GetRegisterOffset(unsigned reg); + + const lldb_private::RegisterInfo *GetRegisterInfoAtIndex(size_t reg) override; + + size_t GetRegisterSetCount() override; + + const lldb_private::RegisterSet *GetRegisterSet(size_t set) override; + +protected: + std::unique_ptr m_register_info_up; + + virtual const lldb_private::RegisterInfo *GetRegisterInfo(); + + bool IsGPR(unsigned reg); + + bool IsFPR(unsigned reg); + + size_t GetFPRSize() { return sizeof(RegisterInfoPOSIX_loongarch64::FPR); } + + uint32_t GetRegNumFCSR() const { return fpr_fcsr_loongarch; } + + virtual bool ReadGPR() = 0; + virtual bool ReadFPR() = 0; + virtual bool WriteGPR() = 0; + virtual bool WriteFPR() = 0; +}; + +#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_LOONGARCH64_H diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp new file mode 100644 --- /dev/null +++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp @@ -0,0 +1,82 @@ +//===-- RegisterContextPOSIX_loongarch64.cpp --------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "lldb/Target/Process.h" +#include "lldb/Target/Target.h" +#include "lldb/Target/Thread.h" +#include "lldb/Utility/DataBufferHeap.h" +#include "lldb/Utility/DataExtractor.h" +#include "lldb/Utility/Endian.h" +#include "lldb/Utility/RegisterValue.h" +#include "lldb/Utility/Scalar.h" +#include "llvm/Support/Compiler.h" + +#include "RegisterContextPOSIX_loongarch64.h" + +using namespace lldb; +using namespace lldb_private; + +RegisterContextPOSIX_loongarch64::RegisterContextPOSIX_loongarch64( + lldb_private::Thread &thread, + std::unique_ptr register_info) + : lldb_private::RegisterContext(thread, 0), + m_register_info_up(std::move(register_info)) {} + +RegisterContextPOSIX_loongarch64::~RegisterContextPOSIX_loongarch64() = default; + +void RegisterContextPOSIX_loongarch64::invalidate() {} + +void RegisterContextPOSIX_loongarch64::InvalidateAllRegisters() {} + +size_t RegisterContextPOSIX_loongarch64::GetRegisterCount() { + return m_register_info_up->GetRegisterCount(); +} + +size_t RegisterContextPOSIX_loongarch64::GetGPRSize() { + return m_register_info_up->GetGPRSize(); +} + +unsigned RegisterContextPOSIX_loongarch64::GetRegisterSize(unsigned int reg) { + return m_register_info_up->GetRegisterInfo()[reg].byte_size; +} + +unsigned RegisterContextPOSIX_loongarch64::GetRegisterOffset(unsigned int reg) { + return m_register_info_up->GetRegisterInfo()[reg].byte_offset; +} + +const lldb_private::RegisterInfo * +RegisterContextPOSIX_loongarch64::GetRegisterInfoAtIndex(size_t reg) { + if (reg < GetRegisterCount()) + return &GetRegisterInfo()[reg]; + + return nullptr; +} + +size_t RegisterContextPOSIX_loongarch64::GetRegisterSetCount() { + return m_register_info_up->GetRegisterCount(); +} + +const lldb_private::RegisterSet * +RegisterContextPOSIX_loongarch64::GetRegisterSet(size_t set) { + return m_register_info_up->GetRegisterSet(set); +} + +const lldb_private::RegisterInfo * +RegisterContextPOSIX_loongarch64::GetRegisterInfo() { + return m_register_info_up->GetRegisterInfo(); +} + +bool RegisterContextPOSIX_loongarch64::IsGPR(unsigned int reg) { + return m_register_info_up->GetRegisterSetFromRegisterIndex(reg) == + RegisterInfoPOSIX_loongarch64::GPRegSet; +} + +bool RegisterContextPOSIX_loongarch64::IsFPR(unsigned int reg) { + return m_register_info_up->GetRegisterSetFromRegisterIndex(reg) == + RegisterInfoPOSIX_loongarch64::FPRegSet; +} diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h --- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h +++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h @@ -23,6 +23,11 @@ GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch); public: + enum RegSetKind { + GPRegSet, + FPRegSet, + }; + struct GPR { uint64_t gpr[32]; diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.cpp --- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.cpp +++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.cpp @@ -15,10 +15,25 @@ #include "RegisterInfoPOSIX_loongarch64.h" +#define GPR_OFFSET(idx) ((idx)*8 + 0) +#define FPR_OFFSET(idx) ((idx)*8 + sizeof(RegisterInfoPOSIX_loongarch64::GPR)) +#define FCC_OFFSET(idx) ((idx)*1 + 32 * 8 + sizeof(RegisterInfoPOSIX_loongarch64::GPR)) +#define FCSR_OFFSET (8 * 1 + 32 * 8 + sizeof(RegisterInfoPOSIX_loongarch64::GPR)) + +#define REG_CONTEXT_SIZE \ + (sizeof(RegisterInfoPOSIX_loongarch64::GPR) + \ + sizeof(RegisterInfoPOSIX_loongarch64::FPR)) + +#define DECLARE_REGISTER_INFOS_LOONGARCH64_STRUCT +#include "RegisterInfos_loongarch64.h" +#undef DECLARE_REGISTER_INFOS_LOONGARCH64_STRUCT + const lldb_private::RegisterInfo * RegisterInfoPOSIX_loongarch64::GetRegisterInfoPtr( const lldb_private::ArchSpec &target_arch) { switch (target_arch.GetMachine()) { + case llvm::Triple::loongarch64: + return g_register_infos_loongarch64; default: assert(false && "Unhandled target architecture."); return nullptr; @@ -28,19 +43,85 @@ uint32_t RegisterInfoPOSIX_loongarch64::GetRegisterInfoCount( const lldb_private::ArchSpec &target_arch) { switch (target_arch.GetMachine()) { + case llvm::Triple::loongarch64: + return static_cast(sizeof(g_register_infos_loongarch64) / + sizeof(g_register_infos_loongarch64[0])); default: assert(false && "Unhandled target architecture."); return 0; } } +// Number of register sets provided by this context. +enum { + k_num_gpr_registers = gpr_last_loongarch - gpr_first_loongarch + 1, + k_num_fpr_registers = fpr_last_loongarch - fpr_first_loongarch + 1, + k_num_register_sets = 2 +}; + +// LoongArch64 general purpose registers. +static const uint32_t g_gpr_regnums_loongarch64[] = { + gpr_r0_loongarch, gpr_r1_loongarch, gpr_r2_loongarch, + gpr_r3_loongarch, gpr_r4_loongarch, gpr_r5_loongarch, + gpr_r6_loongarch, gpr_r7_loongarch, gpr_r8_loongarch, + gpr_r9_loongarch, gpr_r10_loongarch, gpr_r11_loongarch, + gpr_r12_loongarch, gpr_r13_loongarch, gpr_r14_loongarch, + gpr_r15_loongarch, gpr_r16_loongarch, gpr_r17_loongarch, + gpr_r18_loongarch, gpr_r19_loongarch, gpr_r20_loongarch, + gpr_r21_loongarch, gpr_r22_loongarch, gpr_r23_loongarch, + gpr_r24_loongarch, gpr_r25_loongarch, gpr_r26_loongarch, + gpr_r27_loongarch, gpr_r28_loongarch, gpr_r29_loongarch, + gpr_r30_loongarch, gpr_r31_loongarch, gpr_orig_a0_loongarch, + gpr_pc_loongarch, gpr_badv_loongarch, gpr_reserved0_loongarch, + gpr_reserved1_loongarch, gpr_reserved2_loongarch, gpr_reserved3_loongarch, + gpr_reserved4_loongarch, gpr_reserved5_loongarch, gpr_reserved6_loongarch, + gpr_reserved7_loongarch, gpr_reserved8_loongarch, gpr_reserved9_loongarch, + LLDB_INVALID_REGNUM}; + +static_assert(((sizeof g_gpr_regnums_loongarch64 / + sizeof g_gpr_regnums_loongarch64[0]) - + 1) == k_num_gpr_registers, + "g_gpr_regnums_loongarch64 has wrong number of register infos"); + +// LoongArch64 floating point registers. +static const uint32_t g_fpr_regnums_loongarch64[] = { + fpr_f0_loongarch, fpr_f1_loongarch, fpr_f2_loongarch, + fpr_f3_loongarch, fpr_f4_loongarch, fpr_f5_loongarch, + fpr_f6_loongarch, fpr_f7_loongarch, fpr_f8_loongarch, + fpr_f9_loongarch, fpr_f10_loongarch, fpr_f11_loongarch, + fpr_f12_loongarch, fpr_f13_loongarch, fpr_f14_loongarch, + fpr_f15_loongarch, fpr_f16_loongarch, fpr_f17_loongarch, + fpr_f18_loongarch, fpr_f19_loongarch, fpr_f20_loongarch, + fpr_f21_loongarch, fpr_f22_loongarch, fpr_f23_loongarch, + fpr_f24_loongarch, fpr_f25_loongarch, fpr_f26_loongarch, + fpr_f27_loongarch, fpr_f28_loongarch, fpr_f29_loongarch, + fpr_f30_loongarch, fpr_f31_loongarch, fpr_fcc0_loongarch, + fpr_fcc1_loongarch, fpr_fcc2_loongarch, fpr_fcc3_loongarch, + fpr_fcc4_loongarch, fpr_fcc5_loongarch, fpr_fcc6_loongarch, + fpr_fcc7_loongarch, fpr_fcsr_loongarch, LLDB_INVALID_REGNUM}; + +static_assert(((sizeof g_fpr_regnums_loongarch64 / + sizeof g_fpr_regnums_loongarch64[0]) - + 1) == k_num_fpr_registers, + "g_fpr_regnums_loongarch64 has wrong number of register infos"); + +// Register sets for LoongArch64. +static const lldb_private::RegisterSet + g_reg_sets_loongarch64[k_num_register_sets] = { + {"General Purpose Registers", "gpr", k_num_gpr_registers, + g_gpr_regnums_loongarch64}, + {"Floating Point Registers", "fpr", k_num_fpr_registers, + g_fpr_regnums_loongarch64}}; + RegisterInfoPOSIX_loongarch64::RegisterInfoPOSIX_loongarch64( const lldb_private::ArchSpec &target_arch, lldb_private::Flags flags) : lldb_private::RegisterInfoAndSetInterface(target_arch), m_register_info_p(GetRegisterInfoPtr(target_arch)), m_register_info_count(GetRegisterInfoCount(target_arch)) {} -uint32_t RegisterInfoPOSIX_loongarch64::GetRegisterCount() const { return 0; } +uint32_t RegisterInfoPOSIX_loongarch64::GetRegisterCount() const { + return m_register_info_count; +} size_t RegisterInfoPOSIX_loongarch64::GetGPRSize() const { return sizeof(struct RegisterInfoPOSIX_loongarch64::GPR); @@ -55,14 +136,23 @@ return m_register_info_p; } -size_t RegisterInfoPOSIX_loongarch64::GetRegisterSetCount() const { return 0; } +size_t RegisterInfoPOSIX_loongarch64::GetRegisterSetCount() const { + return k_num_register_sets; +} size_t RegisterInfoPOSIX_loongarch64::GetRegisterSetFromRegisterIndex( uint32_t reg_index) const { + // coverity[unsigned_compare] + if (reg_index >= gpr_first_loongarch && reg_index <= gpr_last_loongarch) + return GPRegSet; + if (reg_index >= fpr_first_loongarch && reg_index <= fpr_last_loongarch) + return FPRegSet; return LLDB_INVALID_REGNUM; } const lldb_private::RegisterSet * RegisterInfoPOSIX_loongarch64::GetRegisterSet(size_t set_index) const { + if (set_index < GetRegisterSetCount()) + return &g_reg_sets_loongarch64[set_index]; return nullptr; } diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_loongarch64.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_loongarch64.h new file mode 100644 --- /dev/null +++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_loongarch64.h @@ -0,0 +1,172 @@ +//===-- RegisterInfos_loongarch64.h -----------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifdef DECLARE_REGISTER_INFOS_LOONGARCH64_STRUCT + +#include + +#include "lldb/lldb-defines.h" +#include "lldb/lldb-enumerations.h" +#include "lldb/lldb-private.h" + +#include "Utility/LoongArch_DWARF_Registers.h" +#include "lldb-loongarch-register-enums.h" + +#ifndef GPR_OFFSET +#error GPR_OFFSET must be defined before including this header file +#endif + +#ifndef FPR_OFFSET +#error FPR_OFFSET must be defined before including this header file +#endif + +using namespace loongarch_dwarf; + +// clang-format off + +// I suppose EHFrame and DWARF are the same. +#define KIND_HELPER(reg, generic_kind) \ + { \ + loongarch_dwarf::dwarf_##reg, loongarch_dwarf::dwarf_##reg, generic_kind, \ + LLDB_INVALID_REGNUM, reg##_loongarch \ + } + +// Generates register kinds array for generic purpose registers +#define GPR64_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind) + +// Generates register kinds array for floating point registers +#define FPR64_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind) + +// Defines a 64-bit general purpose register +#define DEFINE_GPR64(reg, generic_kind) DEFINE_GPR64_ALT(reg, reg, generic_kind) +#define DEFINE_GPR64_ALT(reg, alt, generic_kind) \ + { \ + #reg, #alt, 8, GPR_OFFSET(gpr_##reg##_loongarch - gpr_first_loongarch), \ + lldb::eEncodingUint, lldb::eFormatHex, \ + GPR64_KIND(gpr_##reg, generic_kind), nullptr, nullptr \ + } + +// Defines a 64-bit floating point register +#define DEFINE_FPR64(reg, generic_kind) DEFINE_FPR64_ALT(reg, reg, generic_kind) +#define DEFINE_FPR64_ALT(reg, alt, generic_kind) \ + { \ + #reg, #alt, 8, FPR_OFFSET(fpr_##reg##_loongarch - fpr_first_loongarch), \ + lldb::eEncodingUint, lldb::eFormatHex, \ + FPR64_KIND(fpr_##reg, generic_kind), nullptr, nullptr \ + } + +#define DEFINE_FCC(reg, generic_kind) \ + { \ + #reg, nullptr, 1, FCC_OFFSET(fpr_##reg##_loongarch - fpr_fcc0_loongarch), \ + lldb::eEncodingUint, lldb::eFormatHex, \ + FPR64_KIND(fpr_##reg, generic_kind), nullptr, nullptr \ + } + +#define DEFINE_FCSR(reg, generic_kind) \ + { \ + #reg, nullptr, 4, FCSR_OFFSET, \ + lldb::eEncodingUint, lldb::eFormatHex, \ + FPR64_KIND(fpr_##reg, generic_kind), nullptr, nullptr \ + } + +// clang-format on + +static lldb_private::RegisterInfo g_register_infos_loongarch64[] = { + DEFINE_GPR64_ALT(r0, zero, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r1, ra, LLDB_REGNUM_GENERIC_RA), + DEFINE_GPR64_ALT(r2, tp, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r3, sp, LLDB_REGNUM_GENERIC_SP), + DEFINE_GPR64_ALT(r4, a0, LLDB_REGNUM_GENERIC_ARG1), + DEFINE_GPR64_ALT(r5, a1, LLDB_REGNUM_GENERIC_ARG2), + DEFINE_GPR64_ALT(r6, a2, LLDB_REGNUM_GENERIC_ARG3), + DEFINE_GPR64_ALT(r7, a3, LLDB_REGNUM_GENERIC_ARG4), + DEFINE_GPR64_ALT(r8, a4, LLDB_REGNUM_GENERIC_ARG5), + DEFINE_GPR64_ALT(r9, a5, LLDB_REGNUM_GENERIC_ARG6), + DEFINE_GPR64_ALT(r10, a6, LLDB_REGNUM_GENERIC_ARG7), + DEFINE_GPR64_ALT(r11, a7, LLDB_REGNUM_GENERIC_ARG8), + DEFINE_GPR64_ALT(r12, t0, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r13, t1, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r14, t2, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r15, t3, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r16, t4, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r17, t5, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r18, t6, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r19, t7, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r20, t8, LLDB_INVALID_REGNUM), + DEFINE_GPR64(r21, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r22, fp, LLDB_REGNUM_GENERIC_FP), + DEFINE_GPR64_ALT(r22, s9, LLDB_REGNUM_GENERIC_FP), + DEFINE_GPR64_ALT(r23, s0, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r24, s1, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r25, s2, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r26, s3, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r27, s4, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r28, s5, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r29, s6, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r30, s7, LLDB_INVALID_REGNUM), + DEFINE_GPR64_ALT(r31, s8, LLDB_INVALID_REGNUM), + + DEFINE_GPR64(orig_a0, LLDB_INVALID_REGNUM), + DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC), + DEFINE_GPR64(badv, LLDB_INVALID_REGNUM), + DEFINE_GPR64(reserved0, LLDB_INVALID_REGNUM), + DEFINE_GPR64(reserved1, LLDB_INVALID_REGNUM), + DEFINE_GPR64(reserved2, LLDB_INVALID_REGNUM), + DEFINE_GPR64(reserved3, LLDB_INVALID_REGNUM), + DEFINE_GPR64(reserved4, LLDB_INVALID_REGNUM), + DEFINE_GPR64(reserved5, LLDB_INVALID_REGNUM), + DEFINE_GPR64(reserved6, LLDB_INVALID_REGNUM), + DEFINE_GPR64(reserved7, LLDB_INVALID_REGNUM), + DEFINE_GPR64(reserved8, LLDB_INVALID_REGNUM), + DEFINE_GPR64(reserved9, LLDB_INVALID_REGNUM), + + DEFINE_FPR64_ALT(f0, fa0, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f1, fa1, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f2, fa2, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f3, fa3, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f4, fa4, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f5, fa5, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f6, fa6, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f7, fa7, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f8, ft0, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f9, ft1, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f10, ft2, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f11, ft3, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f12, ft4, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f13, ft5, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f14, ft6, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f15, ft7, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f16, ft8, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f17, ft9, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f18, ft10, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f19, ft11, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f20, ft12, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f21, ft13, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f22, ft14, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f23, ft15, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f24, fs0, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f25, fs1, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f26, fs2, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f27, fs3, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f28, fs4, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f29, fs5, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f30, fs6, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(f31, fs7, LLDB_INVALID_REGNUM), + + DEFINE_FCC(fcc0, LLDB_INVALID_REGNUM), + DEFINE_FCC(fcc1, LLDB_INVALID_REGNUM), + DEFINE_FCC(fcc2, LLDB_INVALID_REGNUM), + DEFINE_FCC(fcc3, LLDB_INVALID_REGNUM), + DEFINE_FCC(fcc4, LLDB_INVALID_REGNUM), + DEFINE_FCC(fcc5, LLDB_INVALID_REGNUM), + DEFINE_FCC(fcc6, LLDB_INVALID_REGNUM), + DEFINE_FCC(fcc7, LLDB_INVALID_REGNUM), + DEFINE_FCSR(fcsr, LLDB_INVALID_REGNUM), +}; + +#endif // DECLARE_REGISTER_INFOS_LOONGARCH64_STRUCT diff --git a/lldb/source/Plugins/Process/Utility/lldb-loongarch-register-enums.h b/lldb/source/Plugins/Process/Utility/lldb-loongarch-register-enums.h new file mode 100644 --- /dev/null +++ b/lldb/source/Plugins/Process/Utility/lldb-loongarch-register-enums.h @@ -0,0 +1,179 @@ +//===-- lldb-loongarch-register-enums.h -------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_LOONGARCH_REGISTER_ENUMS_H +#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_LOONGARCH_REGISTER_ENUMS_H + +// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB) + +// Internal codes for all loongarch registers. +enum { + // The same order as user_regs_struct in + // note: these enum values are used as byte_offset + gpr_first_loongarch = 0, + gpr_r0_loongarch = gpr_first_loongarch, + gpr_r1_loongarch, + gpr_r2_loongarch, + gpr_r3_loongarch, + gpr_r4_loongarch, + gpr_r5_loongarch, + gpr_r6_loongarch, + gpr_r7_loongarch, + gpr_r8_loongarch, + gpr_r9_loongarch, + gpr_r10_loongarch, + gpr_r11_loongarch, + gpr_r12_loongarch, + gpr_r13_loongarch, + gpr_r14_loongarch, + gpr_r15_loongarch, + gpr_r16_loongarch, + gpr_r17_loongarch, + gpr_r18_loongarch, + gpr_r19_loongarch, + gpr_r20_loongarch, + gpr_r21_loongarch, + gpr_r22_loongarch, + gpr_r23_loongarch, + gpr_r24_loongarch, + gpr_r25_loongarch, + gpr_r26_loongarch, + gpr_r27_loongarch, + gpr_r28_loongarch, + gpr_r29_loongarch, + gpr_r30_loongarch, + gpr_r31_loongarch, + gpr_orig_a0_loongarch, + gpr_pc_loongarch, + gpr_badv_loongarch, + gpr_reserved0_loongarch, + gpr_reserved1_loongarch, + gpr_reserved2_loongarch, + gpr_reserved3_loongarch, + gpr_reserved4_loongarch, + gpr_reserved5_loongarch, + gpr_reserved6_loongarch, + gpr_reserved7_loongarch, + gpr_reserved8_loongarch, + gpr_reserved9_loongarch, + gpr_last_loongarch = 44, + + gpr_zero_loongarch = gpr_r0_loongarch, + gpr_ra_loongarch = gpr_r1_loongarch, + gpr_tp_loongarch = gpr_r2_loongarch, + gpr_sp_loongarch = gpr_r3_loongarch, + gpr_a0_loongarch = gpr_r4_loongarch, + gpr_a1_loongarch = gpr_r5_loongarch, + gpr_a2_loongarch = gpr_r6_loongarch, + gpr_a3_loongarch = gpr_r7_loongarch, + gpr_a4_loongarch = gpr_r8_loongarch, + gpr_a5_loongarch = gpr_r9_loongarch, + gpr_a6_loongarch = gpr_r10_loongarch, + gpr_a7_loongarch = gpr_r11_loongarch, + gpr_t0_loongarch = gpr_r12_loongarch, + gpr_t1_loongarch = gpr_r13_loongarch, + gpr_t2_loongarch = gpr_r14_loongarch, + gpr_t3_loongarch = gpr_r15_loongarch, + gpr_t4_loongarch = gpr_r16_loongarch, + gpr_t5_loongarch = gpr_r17_loongarch, + gpr_t6_loongarch = gpr_r18_loongarch, + gpr_t7_loongarch = gpr_r19_loongarch, + gpr_t8_loongarch = gpr_r20_loongarch, + gpr_fp_loongarch = gpr_r22_loongarch, + gpr_s9_loongarch = gpr_r22_loongarch, + gpr_s0_loongarch = gpr_r23_loongarch, + gpr_s1_loongarch = gpr_r24_loongarch, + gpr_s2_loongarch = gpr_r25_loongarch, + gpr_s3_loongarch = gpr_r26_loongarch, + gpr_s4_loongarch = gpr_r27_loongarch, + gpr_s5_loongarch = gpr_r28_loongarch, + gpr_s6_loongarch = gpr_r29_loongarch, + gpr_s7_loongarch = gpr_r30_loongarch, + gpr_s8_loongarch = gpr_r31_loongarch, + + fpr_first_loongarch = 45, + fpr_f0_loongarch = fpr_first_loongarch, + fpr_f1_loongarch, + fpr_f2_loongarch, + fpr_f3_loongarch, + fpr_f4_loongarch, + fpr_f5_loongarch, + fpr_f6_loongarch, + fpr_f7_loongarch, + fpr_f8_loongarch, + fpr_f9_loongarch, + fpr_f10_loongarch, + fpr_f11_loongarch, + fpr_f12_loongarch, + fpr_f13_loongarch, + fpr_f14_loongarch, + fpr_f15_loongarch, + fpr_f16_loongarch, + fpr_f17_loongarch, + fpr_f18_loongarch, + fpr_f19_loongarch, + fpr_f20_loongarch, + fpr_f21_loongarch, + fpr_f22_loongarch, + fpr_f23_loongarch, + fpr_f24_loongarch, + fpr_f25_loongarch, + fpr_f26_loongarch, + fpr_f27_loongarch, + fpr_f28_loongarch, + fpr_f29_loongarch, + fpr_f30_loongarch, + fpr_f31_loongarch, + fpr_fcc0_loongarch, + fpr_fcc1_loongarch, + fpr_fcc2_loongarch, + fpr_fcc3_loongarch, + fpr_fcc4_loongarch, + fpr_fcc5_loongarch, + fpr_fcc6_loongarch, + fpr_fcc7_loongarch, + fpr_fcsr_loongarch, + fpr_last_loongarch = fpr_fcsr_loongarch, + + fpr_fa0_loongarch = fpr_f0_loongarch, + fpr_fa1_loongarch = fpr_f1_loongarch, + fpr_fa2_loongarch = fpr_f2_loongarch, + fpr_fa3_loongarch = fpr_f3_loongarch, + fpr_fa4_loongarch = fpr_f4_loongarch, + fpr_fa5_loongarch = fpr_f5_loongarch, + fpr_fa6_loongarch = fpr_f6_loongarch, + fpr_fa7_loongarch = fpr_f7_loongarch, + fpr_ft0_loongarch = fpr_f8_loongarch, + fpr_ft1_loongarch = fpr_f9_loongarch, + fpr_ft2_loongarch = fpr_f10_loongarch, + fpr_ft3_loongarch = fpr_f11_loongarch, + fpr_ft4_loongarch = fpr_f12_loongarch, + fpr_ft5_loongarch = fpr_f13_loongarch, + fpr_ft6_loongarch = fpr_f14_loongarch, + fpr_ft7_loongarch = fpr_f15_loongarch, + fpr_ft8_loongarch = fpr_f16_loongarch, + fpr_ft9_loongarch = fpr_f17_loongarch, + fpr_ft10_loongarch = fpr_f18_loongarch, + fpr_ft11_loongarch = fpr_f19_loongarch, + fpr_ft12_loongarch = fpr_f20_loongarch, + fpr_ft13_loongarch = fpr_f21_loongarch, + fpr_ft14_loongarch = fpr_f22_loongarch, + fpr_ft15_loongarch = fpr_f23_loongarch, + fpr_fs0_loongarch = fpr_f24_loongarch, + fpr_fs1_loongarch = fpr_f25_loongarch, + fpr_fs2_loongarch = fpr_f26_loongarch, + fpr_fs3_loongarch = fpr_f27_loongarch, + fpr_fs4_loongarch = fpr_f28_loongarch, + fpr_fs5_loongarch = fpr_f29_loongarch, + fpr_fs6_loongarch = fpr_f30_loongarch, + fpr_fs7_loongarch = fpr_f31_loongarch, + + k_num_registers_loongarch +}; + +#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_LOONGARCH_REGISTER_ENUMS_H diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp --- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp @@ -1527,8 +1527,14 @@ if (!value.getAsInteger(16, addr_value)) region_info.GetRange().SetRangeBase(addr_value); } else if (name.equals("size")) { - if (!value.getAsInteger(16, addr_value)) + if (!value.getAsInteger(16, addr_value)) { region_info.GetRange().SetByteSize(addr_value); + if (region_info.GetRange().GetRangeEnd() < + region_info.GetRange().GetRangeBase()) { + // Range size overflowed, truncate it. + region_info.GetRange().SetRangeEnd(LLDB_INVALID_ADDRESS); + } + } } else if (name.equals("permissions") && region_info.GetRange().IsValid()) { saw_permissions = true; diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp --- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp @@ -1607,289 +1607,276 @@ // queue_serial are valid LazyBool associated_with_dispatch_queue, addr_t dispatch_queue_t, std::string &queue_name, QueueKind queue_kind, uint64_t queue_serial) { - ThreadSP thread_sp; - if (tid != LLDB_INVALID_THREAD_ID) { - // Scope for "locker" below - { - // m_thread_list_real does have its own mutex, but we need to hold onto - // the mutex between the call to m_thread_list_real.FindThreadByID(...) - // and the m_thread_list_real.AddThread(...) so it doesn't change on us - std::lock_guard guard( - m_thread_list_real.GetMutex()); - thread_sp = m_thread_list_real.FindThreadByProtocolID(tid, false); - - if (!thread_sp) { - // Create the thread if we need to - thread_sp = std::make_shared(*this, tid); - m_thread_list_real.AddThread(thread_sp); - } - } - - if (thread_sp) { - ThreadGDBRemote *gdb_thread = - static_cast(thread_sp.get()); - RegisterContextSP gdb_reg_ctx_sp(gdb_thread->GetRegisterContext()); - gdb_reg_ctx_sp->InvalidateIfNeeded(true); - - auto iter = std::find(m_thread_ids.begin(), m_thread_ids.end(), tid); - if (iter != m_thread_ids.end()) { - SetThreadPc(thread_sp, iter - m_thread_ids.begin()); - } - - for (const auto &pair : expedited_register_map) { - StringExtractor reg_value_extractor(pair.second); - WritableDataBufferSP buffer_sp(new DataBufferHeap( - reg_value_extractor.GetStringRef().size() / 2, 0)); - reg_value_extractor.GetHexBytes(buffer_sp->GetData(), '\xcc'); - uint32_t lldb_regnum = - gdb_reg_ctx_sp->ConvertRegisterKindToRegisterNumber( - eRegisterKindProcessPlugin, pair.first); - gdb_thread->PrivateSetRegisterValue(lldb_regnum, buffer_sp->GetData()); - } + if (tid == LLDB_INVALID_THREAD_ID) + return nullptr; - // AArch64 SVE specific code below calls AArch64SVEReconfigure to update - // SVE register sizes and offsets if value of VG register has changed - // since last stop. - const ArchSpec &arch = GetTarget().GetArchitecture(); - if (arch.IsValid() && arch.GetTriple().isAArch64()) { - GDBRemoteRegisterContext *reg_ctx_sp = - static_cast( - gdb_thread->GetRegisterContext().get()); - - if (reg_ctx_sp) - reg_ctx_sp->AArch64SVEReconfigure(); - } + ThreadSP thread_sp; + // Scope for "locker" below + { + // m_thread_list_real does have its own mutex, but we need to hold onto the + // mutex between the call to m_thread_list_real.FindThreadByID(...) and the + // m_thread_list_real.AddThread(...) so it doesn't change on us + std::lock_guard guard(m_thread_list_real.GetMutex()); + thread_sp = m_thread_list_real.FindThreadByProtocolID(tid, false); + + if (!thread_sp) { + // Create the thread if we need to + thread_sp = std::make_shared(*this, tid); + m_thread_list_real.AddThread(thread_sp); + } + } - thread_sp->SetName(thread_name.empty() ? nullptr : thread_name.c_str()); + ThreadGDBRemote *gdb_thread = static_cast(thread_sp.get()); + RegisterContextSP gdb_reg_ctx_sp(gdb_thread->GetRegisterContext()); - gdb_thread->SetThreadDispatchQAddr(thread_dispatch_qaddr); - // Check if the GDB server was able to provide the queue name, kind and - // serial number - if (queue_vars_valid) - gdb_thread->SetQueueInfo(std::move(queue_name), queue_kind, - queue_serial, dispatch_queue_t, - associated_with_dispatch_queue); - else - gdb_thread->ClearQueueInfo(); + gdb_reg_ctx_sp->InvalidateIfNeeded(true); - gdb_thread->SetAssociatedWithLibdispatchQueue( - associated_with_dispatch_queue); + auto iter = std::find(m_thread_ids.begin(), m_thread_ids.end(), tid); + if (iter != m_thread_ids.end()) + SetThreadPc(thread_sp, iter - m_thread_ids.begin()); - if (dispatch_queue_t != LLDB_INVALID_ADDRESS) - gdb_thread->SetQueueLibdispatchQueueAddress(dispatch_queue_t); + for (const auto &pair : expedited_register_map) { + StringExtractor reg_value_extractor(pair.second); + WritableDataBufferSP buffer_sp( + new DataBufferHeap(reg_value_extractor.GetStringRef().size() / 2, 0)); + reg_value_extractor.GetHexBytes(buffer_sp->GetData(), '\xcc'); + uint32_t lldb_regnum = gdb_reg_ctx_sp->ConvertRegisterKindToRegisterNumber( + eRegisterKindProcessPlugin, pair.first); + gdb_thread->PrivateSetRegisterValue(lldb_regnum, buffer_sp->GetData()); + } - // Make sure we update our thread stop reason just once, but don't - // overwrite the stop info for threads that haven't moved: - StopInfoSP current_stop_info_sp = thread_sp->GetPrivateStopInfo(false); - if (thread_sp->GetTemporaryResumeState() == eStateSuspended && - current_stop_info_sp) { - thread_sp->SetStopInfo(current_stop_info_sp); - return thread_sp; - } + // AArch64 SVE specific code below calls AArch64SVEReconfigure to update + // SVE register sizes and offsets if value of VG register has changed + // since last stop. + const ArchSpec &arch = GetTarget().GetArchitecture(); + if (arch.IsValid() && arch.GetTriple().isAArch64()) { + GDBRemoteRegisterContext *reg_ctx_sp = + static_cast( + gdb_thread->GetRegisterContext().get()); - if (!thread_sp->StopInfoIsUpToDate()) { - thread_sp->SetStopInfo(StopInfoSP()); - // If there's a memory thread backed by this thread, we need to use it - // to calculate StopInfo. - if (ThreadSP memory_thread_sp = - m_thread_list.GetBackingThread(thread_sp)) - thread_sp = memory_thread_sp; + if (reg_ctx_sp) + reg_ctx_sp->AArch64SVEReconfigure(); + } - if (exc_type != 0) { - const size_t exc_data_size = exc_data.size(); + thread_sp->SetName(thread_name.empty() ? nullptr : thread_name.c_str()); - thread_sp->SetStopInfo( - StopInfoMachException::CreateStopReasonWithMachException( - *thread_sp, exc_type, exc_data_size, - exc_data_size >= 1 ? exc_data[0] : 0, - exc_data_size >= 2 ? exc_data[1] : 0, - exc_data_size >= 3 ? exc_data[2] : 0)); - } else { - bool handled = false; - bool did_exec = false; - if (!reason.empty()) { - if (reason == "trace") { - addr_t pc = thread_sp->GetRegisterContext()->GetPC(); - lldb::BreakpointSiteSP bp_site_sp = thread_sp->GetProcess() - ->GetBreakpointSiteList() - .FindByAddress(pc); - - // If the current pc is a breakpoint site then the StopInfo - // should be set to Breakpoint Otherwise, it will be set to - // Trace. - if (bp_site_sp && bp_site_sp->ValidForThisThread(*thread_sp)) { - thread_sp->SetStopInfo( - StopInfo::CreateStopReasonWithBreakpointSiteID( - *thread_sp, bp_site_sp->GetID())); - } else - thread_sp->SetStopInfo( - StopInfo::CreateStopReasonToTrace(*thread_sp)); - handled = true; - } else if (reason == "breakpoint") { - addr_t pc = thread_sp->GetRegisterContext()->GetPC(); - lldb::BreakpointSiteSP bp_site_sp = thread_sp->GetProcess() - ->GetBreakpointSiteList() - .FindByAddress(pc); - if (bp_site_sp) { - // If the breakpoint is for this thread, then we'll report the - // hit, but if it is for another thread, we can just report no - // reason. We don't need to worry about stepping over the - // breakpoint here, that will be taken care of when the thread - // resumes and notices that there's a breakpoint under the pc. - handled = true; - if (bp_site_sp->ValidForThisThread(*thread_sp)) { - thread_sp->SetStopInfo( - StopInfo::CreateStopReasonWithBreakpointSiteID( - *thread_sp, bp_site_sp->GetID())); - } else { - StopInfoSP invalid_stop_info_sp; - thread_sp->SetStopInfo(invalid_stop_info_sp); - } - } - } else if (reason == "trap") { - // Let the trap just use the standard signal stop reason below... - } else if (reason == "watchpoint") { - StringExtractor desc_extractor(description.c_str()); - addr_t wp_addr = desc_extractor.GetU64(LLDB_INVALID_ADDRESS); - uint32_t wp_index = desc_extractor.GetU32(LLDB_INVALID_INDEX32); - addr_t wp_hit_addr = desc_extractor.GetU64(LLDB_INVALID_ADDRESS); - watch_id_t watch_id = LLDB_INVALID_WATCH_ID; - if (wp_addr != LLDB_INVALID_ADDRESS) { - WatchpointSP wp_sp; - ArchSpec::Core core = GetTarget().GetArchitecture().GetCore(); - if ((core >= ArchSpec::kCore_mips_first && - core <= ArchSpec::kCore_mips_last) || - (core >= ArchSpec::eCore_arm_generic && - core <= ArchSpec::eCore_arm_aarch64)) - wp_sp = GetTarget().GetWatchpointList().FindByAddress( - wp_hit_addr); - if (!wp_sp) - wp_sp = - GetTarget().GetWatchpointList().FindByAddress(wp_addr); - if (wp_sp) { - wp_sp->SetHardwareIndex(wp_index); - watch_id = wp_sp->GetID(); - } - } - if (watch_id == LLDB_INVALID_WATCH_ID) { - Log *log(GetLog(GDBRLog::Watchpoints)); - LLDB_LOGF(log, "failed to find watchpoint"); - } - thread_sp->SetStopInfo(StopInfo::CreateStopReasonWithWatchpointID( - *thread_sp, watch_id, wp_hit_addr)); - handled = true; - } else if (reason == "exception") { - thread_sp->SetStopInfo(StopInfo::CreateStopReasonWithException( - *thread_sp, description.c_str())); - handled = true; - } else if (reason == "exec") { - did_exec = true; - thread_sp->SetStopInfo( - StopInfo::CreateStopReasonWithExec(*thread_sp)); - handled = true; - } else if (reason == "processor trace") { - thread_sp->SetStopInfo(StopInfo::CreateStopReasonProcessorTrace( - *thread_sp, description.c_str())); - } else if (reason == "fork") { - StringExtractor desc_extractor(description.c_str()); - lldb::pid_t child_pid = desc_extractor.GetU64( - LLDB_INVALID_PROCESS_ID); - lldb::tid_t child_tid = desc_extractor.GetU64( - LLDB_INVALID_THREAD_ID); - thread_sp->SetStopInfo(StopInfo::CreateStopReasonFork( - *thread_sp, child_pid, child_tid)); - handled = true; - } else if (reason == "vfork") { - StringExtractor desc_extractor(description.c_str()); - lldb::pid_t child_pid = desc_extractor.GetU64( - LLDB_INVALID_PROCESS_ID); - lldb::tid_t child_tid = desc_extractor.GetU64( - LLDB_INVALID_THREAD_ID); - thread_sp->SetStopInfo(StopInfo::CreateStopReasonVFork( - *thread_sp, child_pid, child_tid)); - handled = true; - } else if (reason == "vforkdone") { - thread_sp->SetStopInfo( - StopInfo::CreateStopReasonVForkDone(*thread_sp)); - handled = true; - } - } else if (!signo) { - addr_t pc = thread_sp->GetRegisterContext()->GetPC(); - lldb::BreakpointSiteSP bp_site_sp = - thread_sp->GetProcess()->GetBreakpointSiteList().FindByAddress( - pc); - - // If the current pc is a breakpoint site then the StopInfo should - // be set to Breakpoint even though the remote stub did not set it - // as such. This can happen when the thread is involuntarily - // interrupted (e.g. due to stops on other threads) just as it is - // about to execute the breakpoint instruction. - if (bp_site_sp && bp_site_sp->ValidForThisThread(*thread_sp)) { + gdb_thread->SetThreadDispatchQAddr(thread_dispatch_qaddr); + // Check if the GDB server was able to provide the queue name, kind and serial + // number + if (queue_vars_valid) + gdb_thread->SetQueueInfo(std::move(queue_name), queue_kind, queue_serial, + dispatch_queue_t, associated_with_dispatch_queue); + else + gdb_thread->ClearQueueInfo(); + + gdb_thread->SetAssociatedWithLibdispatchQueue(associated_with_dispatch_queue); + + if (dispatch_queue_t != LLDB_INVALID_ADDRESS) + gdb_thread->SetQueueLibdispatchQueueAddress(dispatch_queue_t); + + // Make sure we update our thread stop reason just once, but don't overwrite + // the stop info for threads that haven't moved: + StopInfoSP current_stop_info_sp = thread_sp->GetPrivateStopInfo(false); + if (thread_sp->GetTemporaryResumeState() == eStateSuspended && + current_stop_info_sp) { + thread_sp->SetStopInfo(current_stop_info_sp); + return thread_sp; + } + + if (!thread_sp->StopInfoIsUpToDate()) { + thread_sp->SetStopInfo(StopInfoSP()); + // If there's a memory thread backed by this thread, we need to use it to + // calculate StopInfo. + if (ThreadSP memory_thread_sp = m_thread_list.GetBackingThread(thread_sp)) + thread_sp = memory_thread_sp; + + if (exc_type != 0) { + const size_t exc_data_size = exc_data.size(); + + thread_sp->SetStopInfo( + StopInfoMachException::CreateStopReasonWithMachException( + *thread_sp, exc_type, exc_data_size, + exc_data_size >= 1 ? exc_data[0] : 0, + exc_data_size >= 2 ? exc_data[1] : 0, + exc_data_size >= 3 ? exc_data[2] : 0)); + } else { + bool handled = false; + bool did_exec = false; + if (!reason.empty()) { + if (reason == "trace") { + addr_t pc = thread_sp->GetRegisterContext()->GetPC(); + lldb::BreakpointSiteSP bp_site_sp = + thread_sp->GetProcess()->GetBreakpointSiteList().FindByAddress( + pc); + + // If the current pc is a breakpoint site then the StopInfo should be + // set to Breakpoint Otherwise, it will be set to Trace. + if (bp_site_sp && bp_site_sp->ValidForThisThread(*thread_sp)) { + thread_sp->SetStopInfo( + StopInfo::CreateStopReasonWithBreakpointSiteID( + *thread_sp, bp_site_sp->GetID())); + } else + thread_sp->SetStopInfo( + StopInfo::CreateStopReasonToTrace(*thread_sp)); + handled = true; + } else if (reason == "breakpoint") { + addr_t pc = thread_sp->GetRegisterContext()->GetPC(); + lldb::BreakpointSiteSP bp_site_sp = + thread_sp->GetProcess()->GetBreakpointSiteList().FindByAddress( + pc); + if (bp_site_sp) { + // If the breakpoint is for this thread, then we'll report the hit, + // but if it is for another thread, we can just report no reason. + // We don't need to worry about stepping over the breakpoint here, + // that will be taken care of when the thread resumes and notices + // that there's a breakpoint under the pc. + handled = true; + if (bp_site_sp->ValidForThisThread(*thread_sp)) { thread_sp->SetStopInfo( StopInfo::CreateStopReasonWithBreakpointSiteID( *thread_sp, bp_site_sp->GetID())); - handled = true; + } else { + StopInfoSP invalid_stop_info_sp; + thread_sp->SetStopInfo(invalid_stop_info_sp); } } - - if (!handled && signo && !did_exec) { - if (signo == SIGTRAP) { - // Currently we are going to assume SIGTRAP means we are either - // hitting a breakpoint or hardware single stepping. - handled = true; - addr_t pc = thread_sp->GetRegisterContext()->GetPC() + - m_breakpoint_pc_offset; - lldb::BreakpointSiteSP bp_site_sp = thread_sp->GetProcess() - ->GetBreakpointSiteList() - .FindByAddress(pc); - - if (bp_site_sp) { - // If the breakpoint is for this thread, then we'll report the - // hit, but if it is for another thread, we can just report no - // reason. We don't need to worry about stepping over the - // breakpoint here, that will be taken care of when the thread - // resumes and notices that there's a breakpoint under the pc. - if (bp_site_sp->ValidForThisThread(*thread_sp)) { - if (m_breakpoint_pc_offset != 0) - thread_sp->GetRegisterContext()->SetPC(pc); - thread_sp->SetStopInfo( - StopInfo::CreateStopReasonWithBreakpointSiteID( - *thread_sp, bp_site_sp->GetID())); - } else { - StopInfoSP invalid_stop_info_sp; - thread_sp->SetStopInfo(invalid_stop_info_sp); - } - } else { - // If we were stepping then assume the stop was the result of - // the trace. If we were not stepping then report the SIGTRAP. - // FIXME: We are still missing the case where we single step - // over a trap instruction. - if (thread_sp->GetTemporaryResumeState() == eStateStepping) - thread_sp->SetStopInfo( - StopInfo::CreateStopReasonToTrace(*thread_sp)); - else - thread_sp->SetStopInfo(StopInfo::CreateStopReasonWithSignal( - *thread_sp, signo, description.c_str())); - } + } else if (reason == "trap") { + // Let the trap just use the standard signal stop reason below... + } else if (reason == "watchpoint") { + StringExtractor desc_extractor(description.c_str()); + addr_t wp_addr = desc_extractor.GetU64(LLDB_INVALID_ADDRESS); + uint32_t wp_index = desc_extractor.GetU32(LLDB_INVALID_INDEX32); + addr_t wp_hit_addr = desc_extractor.GetU64(LLDB_INVALID_ADDRESS); + watch_id_t watch_id = LLDB_INVALID_WATCH_ID; + if (wp_addr != LLDB_INVALID_ADDRESS) { + WatchpointSP wp_sp; + ArchSpec::Core core = GetTarget().GetArchitecture().GetCore(); + if ((core >= ArchSpec::kCore_mips_first && + core <= ArchSpec::kCore_mips_last) || + (core >= ArchSpec::eCore_arm_generic && + core <= ArchSpec::eCore_arm_aarch64)) + wp_sp = + GetTarget().GetWatchpointList().FindByAddress(wp_hit_addr); + if (!wp_sp) + wp_sp = GetTarget().GetWatchpointList().FindByAddress(wp_addr); + if (wp_sp) { + wp_sp->SetHardwareIndex(wp_index); + watch_id = wp_sp->GetID(); } - if (!handled) - thread_sp->SetStopInfo(StopInfo::CreateStopReasonWithSignal( - *thread_sp, signo, description.c_str())); } + if (watch_id == LLDB_INVALID_WATCH_ID) { + Log *log(GetLog(GDBRLog::Watchpoints)); + LLDB_LOGF(log, "failed to find watchpoint"); + } + thread_sp->SetStopInfo(StopInfo::CreateStopReasonWithWatchpointID( + *thread_sp, watch_id, wp_hit_addr)); + handled = true; + } else if (reason == "exception") { + thread_sp->SetStopInfo(StopInfo::CreateStopReasonWithException( + *thread_sp, description.c_str())); + handled = true; + } else if (reason == "exec") { + did_exec = true; + thread_sp->SetStopInfo( + StopInfo::CreateStopReasonWithExec(*thread_sp)); + handled = true; + } else if (reason == "processor trace") { + thread_sp->SetStopInfo(StopInfo::CreateStopReasonProcessorTrace( + *thread_sp, description.c_str())); + } else if (reason == "fork") { + StringExtractor desc_extractor(description.c_str()); + lldb::pid_t child_pid = + desc_extractor.GetU64(LLDB_INVALID_PROCESS_ID); + lldb::tid_t child_tid = desc_extractor.GetU64(LLDB_INVALID_THREAD_ID); + thread_sp->SetStopInfo( + StopInfo::CreateStopReasonFork(*thread_sp, child_pid, child_tid)); + handled = true; + } else if (reason == "vfork") { + StringExtractor desc_extractor(description.c_str()); + lldb::pid_t child_pid = + desc_extractor.GetU64(LLDB_INVALID_PROCESS_ID); + lldb::tid_t child_tid = desc_extractor.GetU64(LLDB_INVALID_THREAD_ID); + thread_sp->SetStopInfo(StopInfo::CreateStopReasonVFork( + *thread_sp, child_pid, child_tid)); + handled = true; + } else if (reason == "vforkdone") { + thread_sp->SetStopInfo( + StopInfo::CreateStopReasonVForkDone(*thread_sp)); + handled = true; + } + } else if (!signo) { + addr_t pc = thread_sp->GetRegisterContext()->GetPC(); + lldb::BreakpointSiteSP bp_site_sp = + thread_sp->GetProcess()->GetBreakpointSiteList().FindByAddress(pc); + + // If the current pc is a breakpoint site then the StopInfo should be + // set to Breakpoint even though the remote stub did not set it as such. + // This can happen when the thread is involuntarily interrupted (e.g. + // due to stops on other threads) just as it is about to execute the + // breakpoint instruction. + if (bp_site_sp && bp_site_sp->ValidForThisThread(*thread_sp)) { + thread_sp->SetStopInfo(StopInfo::CreateStopReasonWithBreakpointSiteID( + *thread_sp, bp_site_sp->GetID())); + handled = true; + } + } - if (!description.empty()) { - lldb::StopInfoSP stop_info_sp(thread_sp->GetStopInfo()); - if (stop_info_sp) { - const char *stop_info_desc = stop_info_sp->GetDescription(); - if (!stop_info_desc || !stop_info_desc[0]) - stop_info_sp->SetDescription(description.c_str()); + if (!handled && signo && !did_exec) { + if (signo == SIGTRAP) { + // Currently we are going to assume SIGTRAP means we are either + // hitting a breakpoint or hardware single stepping. + handled = true; + addr_t pc = + thread_sp->GetRegisterContext()->GetPC() + m_breakpoint_pc_offset; + lldb::BreakpointSiteSP bp_site_sp = + thread_sp->GetProcess()->GetBreakpointSiteList().FindByAddress( + pc); + + if (bp_site_sp) { + // If the breakpoint is for this thread, then we'll report the hit, + // but if it is for another thread, we can just report no reason. + // We don't need to worry about stepping over the breakpoint here, + // that will be taken care of when the thread resumes and notices + // that there's a breakpoint under the pc. + if (bp_site_sp->ValidForThisThread(*thread_sp)) { + if (m_breakpoint_pc_offset != 0) + thread_sp->GetRegisterContext()->SetPC(pc); + thread_sp->SetStopInfo( + StopInfo::CreateStopReasonWithBreakpointSiteID( + *thread_sp, bp_site_sp->GetID())); } else { - thread_sp->SetStopInfo(StopInfo::CreateStopReasonWithException( - *thread_sp, description.c_str())); + StopInfoSP invalid_stop_info_sp; + thread_sp->SetStopInfo(invalid_stop_info_sp); } + } else { + // If we were stepping then assume the stop was the result of the + // trace. If we were not stepping then report the SIGTRAP. + // FIXME: We are still missing the case where we single step over a + // trap instruction. + if (thread_sp->GetTemporaryResumeState() == eStateStepping) + thread_sp->SetStopInfo( + StopInfo::CreateStopReasonToTrace(*thread_sp)); + else + thread_sp->SetStopInfo(StopInfo::CreateStopReasonWithSignal( + *thread_sp, signo, description.c_str())); } } + if (!handled) + thread_sp->SetStopInfo(StopInfo::CreateStopReasonWithSignal( + *thread_sp, signo, description.c_str())); + } + + if (!description.empty()) { + lldb::StopInfoSP stop_info_sp(thread_sp->GetStopInfo()); + if (stop_info_sp) { + const char *stop_info_desc = stop_info_sp->GetDescription(); + if (!stop_info_desc || !stop_info_desc[0]) + stop_info_sp->SetDescription(description.c_str()); + } else { + thread_sp->SetStopInfo(StopInfo::CreateStopReasonWithException( + *thread_sp, description.c_str())); + } } } } diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h @@ -303,8 +303,16 @@ static clang::AccessSpecifier UnifyAccessSpecifiers(clang::AccessSpecifier lhs, clang::AccessSpecifier rhs); - static uint32_t GetNumBaseClasses(const clang::CXXRecordDecl *cxx_record_decl, - bool omit_empty_base_classes); + uint32_t GetNumBaseClasses(const clang::CXXRecordDecl *cxx_record_decl, + bool omit_empty_base_classes); + + uint32_t GetIndexForRecordChild(const clang::RecordDecl *record_decl, + clang::NamedDecl *canonical_decl, + bool omit_empty_base_classes); + + uint32_t GetIndexForRecordBase(const clang::RecordDecl *record_decl, + const clang::CXXBaseSpecifier *base_spec, + bool omit_empty_base_classes); /// Synthesize a clang::Module and return its ID or a default-constructed ID. OptionalClangModuleID GetOrCreateClangModule(llvm::StringRef name, @@ -374,7 +382,9 @@ bool FieldIsBitfield(clang::FieldDecl *field, uint32_t &bitfield_bit_size); - static bool RecordHasFields(const clang::RecordDecl *record_decl); + bool RecordHasFields(const clang::RecordDecl *record_decl); + + bool BaseSpecifierIsEmpty(const clang::CXXBaseSpecifier *b); CompilerType CreateObjCClass(llvm::StringRef name, clang::DeclContext *decl_ctx, @@ -641,6 +651,8 @@ bool GetCompleteType(lldb::opaque_compiler_type_t type) override; + bool IsForcefullyCompleted(lldb::opaque_compiler_type_t type) override; + // Accessors ConstString GetTypeName(lldb::opaque_compiler_type_t type, @@ -1145,7 +1157,7 @@ /// Alias for requesting the default scratch TypeSystemClang in GetForTarget. // This isn't constexpr as gtest/llvm::Optional comparison logic is trying // to get the address of this for pretty-printing. - static const llvm::NoneType DefaultAST; + static const std::nullopt_t DefaultAST; /// Infers the appropriate sub-AST from Clang's LangOptions. static llvm::Optional diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp @@ -1802,6 +1802,17 @@ return true; } } + + // We always want forcefully completed types to show up so we can print a + // message in the summary that indicates that the type is incomplete. + // This will help users know when they are running into issues with + // -flimit-debug-info instead of just seeing nothing if this is a base class + // (since we were hiding empty base classes), or nothing when you turn open + // an valiable whose type was incomplete. + ClangASTMetadata *meta_data = GetMetadata(record_decl); + if (meta_data && meta_data->IsForcefullyCompleted()) + return true; + return false; } @@ -1829,7 +1840,7 @@ return GetType(ast.getObjCInterfaceType(decl)); } -static inline bool BaseSpecifierIsEmpty(const CXXBaseSpecifier *b) { +bool TypeSystemClang::BaseSpecifierIsEmpty(const CXXBaseSpecifier *b) { return !TypeSystemClang::RecordHasFields(b->getType()->getAsCXXRecordDecl()); } @@ -1875,9 +1886,9 @@ return namespace_decl; } - namespace_decl = - NamespaceDecl::Create(ast, decl_ctx, is_inline, SourceLocation(), - SourceLocation(), &identifier_info, nullptr); + namespace_decl = NamespaceDecl::Create(ast, decl_ctx, is_inline, + SourceLocation(), SourceLocation(), + &identifier_info, nullptr, false); decl_ctx->addDecl(namespace_decl); } else { @@ -1888,7 +1899,7 @@ namespace_decl = NamespaceDecl::Create(ast, decl_ctx, false, SourceLocation(), - SourceLocation(), nullptr, nullptr); + SourceLocation(), nullptr, nullptr, false); translation_unit_decl->setAnonymousNamespace(namespace_decl); translation_unit_decl->addDecl(namespace_decl); assert(namespace_decl == translation_unit_decl->getAnonymousNamespace()); @@ -1900,7 +1911,7 @@ return namespace_decl; namespace_decl = NamespaceDecl::Create(ast, decl_ctx, false, SourceLocation(), - SourceLocation(), nullptr, nullptr); + SourceLocation(), nullptr, nullptr, false); parent_namespace_decl->setAnonymousNamespace(namespace_decl); parent_namespace_decl->addDecl(namespace_decl); assert(namespace_decl == @@ -6608,9 +6619,10 @@ return CompilerType(); } -static uint32_t GetIndexForRecordBase(const clang::RecordDecl *record_decl, - const clang::CXXBaseSpecifier *base_spec, - bool omit_empty_base_classes) { +uint32_t TypeSystemClang::GetIndexForRecordBase( + const clang::RecordDecl *record_decl, + const clang::CXXBaseSpecifier *base_spec, + bool omit_empty_base_classes) { uint32_t child_idx = 0; const clang::CXXRecordDecl *cxx_record_decl = @@ -6635,9 +6647,9 @@ return UINT32_MAX; } -static uint32_t GetIndexForRecordChild(const clang::RecordDecl *record_decl, - clang::NamedDecl *canonical_decl, - bool omit_empty_base_classes) { +uint32_t TypeSystemClang::GetIndexForRecordChild( + const clang::RecordDecl *record_decl, clang::NamedDecl *canonical_decl, + bool omit_empty_base_classes) { uint32_t child_idx = TypeSystemClang::GetNumBaseClasses( llvm::dyn_cast(record_decl), omit_empty_base_classes); @@ -9878,7 +9890,7 @@ } // namespace char ScratchTypeSystemClang::ID; -const llvm::NoneType ScratchTypeSystemClang::DefaultAST = llvm::None; +const std::nullopt_t ScratchTypeSystemClang::DefaultAST = llvm::None; ScratchTypeSystemClang::ScratchTypeSystemClang(Target &target, llvm::Triple triple) @@ -10034,3 +10046,19 @@ m_isolated_asts.insert({feature, new_ast_sp}); return *new_ast_sp; } + +bool TypeSystemClang::IsForcefullyCompleted(lldb::opaque_compiler_type_t type) { + if (type) { + clang::QualType qual_type(GetQualType(type)); + const clang::RecordType *record_type = + llvm::dyn_cast(qual_type.getTypePtr()); + if (record_type) { + const clang::RecordDecl *record_decl = record_type->getDecl(); + assert(record_decl); + ClangASTMetadata *metadata = GetMetadata(record_decl); + if (metadata) + return metadata->IsForcefullyCompleted(); + } + } + return false; +} diff --git a/lldb/source/Symbol/CompilerType.cpp b/lldb/source/Symbol/CompilerType.cpp --- a/lldb/source/Symbol/CompilerType.cpp +++ b/lldb/source/Symbol/CompilerType.cpp @@ -94,6 +94,13 @@ return false; } +bool CompilerType::IsForcefullyCompleted() const { + if (IsValid()) + if (auto type_system_sp = GetTypeSystem()) + return type_system_sp->IsForcefullyCompleted(m_type); + return false; +} + bool CompilerType::IsConst() const { if (IsValid()) if (auto type_system_sp = GetTypeSystem()) diff --git a/lldb/source/Utility/LoongArch_DWARF_Registers.h b/lldb/source/Utility/LoongArch_DWARF_Registers.h new file mode 100644 --- /dev/null +++ b/lldb/source/Utility/LoongArch_DWARF_Registers.h @@ -0,0 +1,178 @@ +//===-- LoongArch_DWARF_Registers.h -----------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLDB_SOURCE_UTILITY_LOONGARCH_DWARF_REGISTERS_H +#define LLDB_SOURCE_UTILITY_LOONGARCH_DWARF_REGISTERS_H + +#include "lldb/lldb-private.h" + +namespace loongarch_dwarf { + +enum { + dwarf_gpr_r0 = 0, + dwarf_gpr_r1, + dwarf_gpr_r2, + dwarf_gpr_r3, + dwarf_gpr_r4, + dwarf_gpr_r5, + dwarf_gpr_r6, + dwarf_gpr_r7, + dwarf_gpr_r8, + dwarf_gpr_r9, + dwarf_gpr_r10, + dwarf_gpr_r11, + dwarf_gpr_r12, + dwarf_gpr_r13, + dwarf_gpr_r14, + dwarf_gpr_r15, + dwarf_gpr_r16, + dwarf_gpr_r17, + dwarf_gpr_r18, + dwarf_gpr_r19, + dwarf_gpr_r20, + dwarf_gpr_r21, + dwarf_gpr_r22, + dwarf_gpr_r23, + dwarf_gpr_r24, + dwarf_gpr_r25, + dwarf_gpr_r26, + dwarf_gpr_r27, + dwarf_gpr_r28, + dwarf_gpr_r29, + dwarf_gpr_r30, + dwarf_gpr_r31 = 31, + + dwarf_gpr_orig_a0, + dwarf_gpr_pc, + dwarf_gpr_badv, + + dwarf_gpr_reserved0 = 35, + dwarf_gpr_reserved1, + dwarf_gpr_reserved2, + dwarf_gpr_reserved3, + dwarf_gpr_reserved4, + dwarf_gpr_reserved5, + dwarf_gpr_reserved6, + dwarf_gpr_reserved7, + dwarf_gpr_reserved8, + dwarf_gpr_reserved9, + + dwarf_fpr_f0 = 45, + dwarf_fpr_f1, + dwarf_fpr_f2, + dwarf_fpr_f3, + dwarf_fpr_f4, + dwarf_fpr_f5, + dwarf_fpr_f6, + dwarf_fpr_f7, + dwarf_fpr_f8, + dwarf_fpr_f9, + dwarf_fpr_f10, + dwarf_fpr_f11, + dwarf_fpr_f12, + dwarf_fpr_f13, + dwarf_fpr_f14, + dwarf_fpr_f15, + dwarf_fpr_f16, + dwarf_fpr_f17, + dwarf_fpr_f18, + dwarf_fpr_f19, + dwarf_fpr_f20, + dwarf_fpr_f21, + dwarf_fpr_f22, + dwarf_fpr_f23, + dwarf_fpr_f24, + dwarf_fpr_f25, + dwarf_fpr_f26, + dwarf_fpr_f27, + dwarf_fpr_f28, + dwarf_fpr_f29, + dwarf_fpr_f30, + dwarf_fpr_f31 = 76, + + dwarf_fpr_fcc0, + dwarf_fpr_fcc1, + dwarf_fpr_fcc2, + dwarf_fpr_fcc3, + dwarf_fpr_fcc4, + dwarf_fpr_fcc5, + dwarf_fpr_fcc6, + dwarf_fpr_fcc7, + dwarf_fpr_fcsr, + + // register name alias + dwarf_gpr_zero = dwarf_gpr_r0, + dwarf_gpr_ra = dwarf_gpr_r1, + dwarf_gpr_tp = dwarf_gpr_r2, + dwarf_gpr_sp = dwarf_gpr_r3, + dwarf_gpr_a0 = dwarf_gpr_r4, + dwarf_gpr_a1 = dwarf_gpr_r5, + dwarf_gpr_a2 = dwarf_gpr_r6, + dwarf_gpr_a3 = dwarf_gpr_r7, + dwarf_gpr_a4 = dwarf_gpr_r8, + dwarf_gpr_a5 = dwarf_gpr_r9, + dwarf_gpr_a6 = dwarf_gpr_r10, + dwarf_gpr_a7 = dwarf_gpr_r11, + dwarf_gpr_t0 = dwarf_gpr_r12, + dwarf_gpr_t1 = dwarf_gpr_r13, + dwarf_gpr_t2 = dwarf_gpr_r14, + dwarf_gpr_t3 = dwarf_gpr_r15, + dwarf_gpr_t4 = dwarf_gpr_r16, + dwarf_gpr_t5 = dwarf_gpr_r17, + dwarf_gpr_t6 = dwarf_gpr_r18, + dwarf_gpr_t7 = dwarf_gpr_r19, + dwarf_gpr_t8 = dwarf_gpr_r20, + dwarf_gpr_fp = dwarf_gpr_r22, + dwarf_gpr_s9 = dwarf_gpr_r22, + dwarf_gpr_s0 = dwarf_gpr_r23, + dwarf_gpr_s1 = dwarf_gpr_r24, + dwarf_gpr_s2 = dwarf_gpr_r25, + dwarf_gpr_s3 = dwarf_gpr_r26, + dwarf_gpr_s4 = dwarf_gpr_r27, + dwarf_gpr_s5 = dwarf_gpr_r28, + dwarf_gpr_s6 = dwarf_gpr_r29, + dwarf_gpr_s7 = dwarf_gpr_r30, + dwarf_gpr_s8 = dwarf_gpr_r31, + + dwarf_fpr_fa0 = dwarf_fpr_f0, + dwarf_fpr_fa1 = dwarf_fpr_f1, + dwarf_fpr_fa2 = dwarf_fpr_f2, + dwarf_fpr_fa3 = dwarf_fpr_f3, + dwarf_fpr_fa4 = dwarf_fpr_f4, + dwarf_fpr_fa5 = dwarf_fpr_f5, + dwarf_fpr_fa6 = dwarf_fpr_f6, + dwarf_fpr_fa7 = dwarf_fpr_f7, + dwarf_fpr_ft0 = dwarf_fpr_f8, + dwarf_fpr_ft1 = dwarf_fpr_f9, + dwarf_fpr_ft2 = dwarf_fpr_f10, + dwarf_fpr_ft3 = dwarf_fpr_f11, + dwarf_fpr_ft4 = dwarf_fpr_f12, + dwarf_fpr_ft5 = dwarf_fpr_f13, + dwarf_fpr_ft6 = dwarf_fpr_f14, + dwarf_fpr_ft7 = dwarf_fpr_f15, + dwarf_fpr_ft8 = dwarf_fpr_f16, + dwarf_fpr_ft9 = dwarf_fpr_f17, + dwarf_fpr_ft10 = dwarf_fpr_f18, + dwarf_fpr_ft11 = dwarf_fpr_f19, + dwarf_fpr_ft12 = dwarf_fpr_f20, + dwarf_fpr_ft13 = dwarf_fpr_f21, + dwarf_fpr_ft14 = dwarf_fpr_f22, + dwarf_fpr_ft15 = dwarf_fpr_f23, + dwarf_fpr_fs0 = dwarf_fpr_f24, + dwarf_fpr_fs1 = dwarf_fpr_f25, + dwarf_fpr_fs2 = dwarf_fpr_f26, + dwarf_fpr_fs3 = dwarf_fpr_f27, + dwarf_fpr_fs4 = dwarf_fpr_f28, + dwarf_fpr_fs5 = dwarf_fpr_f29, + dwarf_fpr_fs6 = dwarf_fpr_f30, + dwarf_fpr_fs7 = dwarf_fpr_f31, +}; + +} // namespace loongarch_dwarf + +#endif // LLDB_SOURCE_UTILITY_LOONGARCH_DWARF_REGISTERS_H diff --git a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/coroutine_handle/TestCoroutineHandle.py b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/coroutine_handle/TestCoroutineHandle.py --- a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/coroutine_handle/TestCoroutineHandle.py +++ b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/coroutine_handle/TestCoroutineHandle.py @@ -38,13 +38,6 @@ ValueCheck(name="current_value", value = "-1"), ]) ]) - # We recognize and pretty-print `std::noop_coroutine`. We don't display - # any children as those are irrelevant for the noop coroutine. - # clang version < 16 did not yet write debug info for the noop coroutines. - if not (is_clang and self.expectedCompilerVersion(["<", "16"])): - self.expect_expr("noop_hdl", - result_summary="noop_coroutine", - result_children=[]) if is_clang: # For a type-erased `coroutine_handle<>`, we can still devirtualize # the promise call and display the correctly typed promise. @@ -68,7 +61,7 @@ result_children=[ ValueCheck(name="resume", summary = test_generator_func_ptr_re), ValueCheck(name="destroy", summary = test_generator_func_ptr_re), - ValueCheck(name="promise", dereference=ValueCheck(value="-1")) + ValueCheck(name="promise", value="-1") ]) # Run until after the `co_yield` diff --git a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/coroutine_handle/main.cpp b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/coroutine_handle/main.cpp --- a/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/coroutine_handle/main.cpp +++ b/lldb/test/API/functionalities/data-formatter/data-formatter-stl/generic/coroutine_handle/main.cpp @@ -45,7 +45,6 @@ std::coroutine_handle<> type_erased_hdl = gen.hdl; std::coroutine_handle incorrectly_typed_hdl = std::coroutine_handle::from_address(gen.hdl.address()); - std::coroutine_handle<> noop_hdl = std::noop_coroutine(); gen.hdl.resume(); // Break at initial_suspend gen.hdl.resume(); // Break after co_yield empty_function_so_we_can_set_a_breakpoint(); // Break at final_suspend diff --git a/lldb/test/API/functionalities/gdb_remote_client/TestGdbClientMemoryRegions.py b/lldb/test/API/functionalities/gdb_remote_client/TestGdbClientMemoryRegions.py new file mode 100644 --- /dev/null +++ b/lldb/test/API/functionalities/gdb_remote_client/TestGdbClientMemoryRegions.py @@ -0,0 +1,44 @@ +import lldb +from lldbsuite.test.lldbtest import * +from lldbsuite.test.decorators import * +from lldbsuite.test.gdbclientutils import * +from lldbsuite.test.lldbgdbclient import GDBRemoteTestBase + + +class TestGdbClientMemoryRegions(GDBRemoteTestBase): + + def test(self): + """ + Test handling of overflowing memory regions. In particular, make sure + they don't trigger an infinite loop. + """ + class MyResponder(MockGDBServerResponder): + + def qHostInfo(self): + return "ptrsize:8;endian:little;" + + def qMemoryRegionInfo(self, addr): + if addr == 0: + return "start:0;size:8000000000000000;permissions:rw;" + if addr == 0x8000000000000000: + return "start:8000000000000000;size:8000000000000000;permissions:r;" + + self.runCmd("log enable gdb-remote packets") + self.runCmd("log enable lldb temp") + self.server.responder = MyResponder() + target = self.dbg.CreateTarget('') + process = self.connect(target) + + regions = process.GetMemoryRegions() + self.assertEqual(regions.GetSize(), 2) + + region = lldb.SBMemoryRegionInfo() + self.assertTrue(regions.GetMemoryRegionAtIndex(0, region)) + self.assertEqual(region.GetRegionBase(), 0) + self.assertEqual(region.GetRegionEnd(), 0x8000000000000000) + self.assertTrue(region.IsWritable()) + + self.assertTrue(regions.GetMemoryRegionAtIndex(1, region)) + self.assertEqual(region.GetRegionBase(), 0x8000000000000000) + self.assertEqual(region.GetRegionEnd(), 0xffffffffffffffff) + self.assertFalse(region.IsWritable()) diff --git a/lldb/test/API/functionalities/limit-debug-info/TestLimitDebugInfo.py b/lldb/test/API/functionalities/limit-debug-info/TestLimitDebugInfo.py --- a/lldb/test/API/functionalities/limit-debug-info/TestLimitDebugInfo.py +++ b/lldb/test/API/functionalities/limit-debug-info/TestLimitDebugInfo.py @@ -16,10 +16,12 @@ type_ = exe.FindFirstType(name) self.trace("type_: %s"%type_) self.assertTrue(type_) + self.assertTrue(type_.IsTypeComplete()) base = type_.GetDirectBaseClassAtIndex(0).GetType() self.trace("base:%s"%base) self.assertTrue(base) self.assertEquals(base.GetNumberOfFields(), 0) + self.assertFalse(base.IsTypeComplete()) def _check_debug_info_is_limited(self, target): # Without other shared libraries we should only see the member declared @@ -28,6 +30,100 @@ self._check_type(target, "InheritsFromOne") self._check_type(target, "InheritsFromTwo") + def _check_incomplete_frame_variable_output(self): + # Check that the display of the "frame variable" output identifies the + # incomplete types. Currently the expression parser will find the real + # definition for a type when running an expression for any forcefully + # completed types, but "frame variable" won't. I hope to fix this with + # a follow up patch, but if we don't find the actual definition we + # should clearly show this to the user by showing which types were + # incomplete. So this will test verifies the expected output for such + # types. We also need to verify the standard "frame variable" output + # which will inline all of the members on one line, versus the full + # output from "frame variable --raw" and a few other options. + # self.expect("frame variable two_as_member", error=True, + # substrs=["no member named 'one' in 'InheritsFromOne'"]) + + command_expect_pairs = [ + # Test standard "frame variable" output for types to make sure + # "" shows up where we expect it to + ["var two_as_member", [ + "(TwoAsMember) ::two_as_member = (two = , member = 47)"] + ], + ["var inherits_from_one", [ + "(InheritsFromOne) ::inherits_from_one = (One = , member = 47)"] + ], + ["var inherits_from_two", [ + "(InheritsFromTwo) ::inherits_from_two = (Two = , member = 47)"] + ], + ["var one_as_member", [ + "(OneAsMember) ::one_as_member = (one = , member = 47)"] + ], + ["var two_as_member", [ + "(TwoAsMember) ::two_as_member = (two = , member = 47)"] + ], + ["var array_of_one", [ + "(array::One[3]) ::array_of_one = ([0] = , [1] = , [2] = )"] + ], + ["var array_of_two", [ + "(array::Two[3]) ::array_of_two = ([0] = , [1] = , [2] = )"] + ], + ["var shadowed_one", [ + "(ShadowedOne) ::shadowed_one = (func_shadow::One = , member = 47)"] + ], + + # Now test "frame variable --show-types output" which has multi-line + # output and should not always show classes that were forcefully + # completed to the user to let them know they have a type that should + # have been complete but wasn't. + ["var --show-types inherits_from_one", [ + "(InheritsFromOne) ::inherits_from_one = {", + " (One) One = {}", + " (int) member = 47", + "}"] + ], + ["var --show-types inherits_from_two", [ + "(InheritsFromTwo) ::inherits_from_two = {", + " (Two) Two = {}", + " (int) member = 47", + "}"] + ], + ["var --show-types one_as_member", [ + "(OneAsMember) ::one_as_member = {", + " (member::One) one = {}", + " (int) member = 47", + "}"] + ], + ["var --show-types two_as_member", [ + "(TwoAsMember) ::two_as_member = {", + " (member::Two) two = {}", + " (int) member = 47", + "}"] + ], + ["var --show-types array_of_one", [ + "(array::One[3]) ::array_of_one = {", + " (array::One) [0] = {}", + " (array::One) [1] = {}", + " (array::One) [2] = {}", + "}"] + ], + ["var --show-types array_of_two", [ + "(array::Two[3]) ::array_of_two = {", + " (array::Two) [0] = {}", + " (array::Two) [1] = {}", + " (array::Two) [2] = {}", + "}"] + ], + ["var --show-types shadowed_one", [ + "(ShadowedOne) ::shadowed_one = {", + " (func_shadow::One) func_shadow::One = {}", + " (int) member = 47", + "}"] + ], + ] + for command, expect_items in command_expect_pairs: + self.expect(command, substrs=expect_items) + @skipIf(bugnumber="pr46284", debug_info="gmodules") @skipIfWindows # Clang emits type info even with -flimit-debug-info # Requires DW_CC_pass_by_* attributes from Clang 7 to correctly call @@ -40,7 +136,7 @@ self._check_debug_info_is_limited(target) lldbutil.run_to_name_breakpoint(self, "main", - extra_images=["one", "two"]) + extra_images=["one", "two"]) # But when other shared libraries are loaded, we should be able to see # all members. @@ -67,6 +163,8 @@ self.expect_expr("shadowed_one.member", result_value="47") self.expect_expr("shadowed_one.one", result_value="142") + self._check_incomplete_frame_variable_output() + @skipIf(bugnumber="pr46284", debug_info="gmodules") @skipIfWindows # Clang emits type info even with -flimit-debug-info # Requires DW_CC_pass_by_* attributes from Clang 7 to correctly call @@ -110,6 +208,8 @@ substrs=["calling 'one' with incomplete return type 'result::One'"]) self.expect_expr("get_two().member", result_value="224") + self._check_incomplete_frame_variable_output() + @skipIf(bugnumber="pr46284", debug_info="gmodules") @skipIfWindows # Clang emits type info even with -flimit-debug-info # Requires DW_CC_pass_by_* attributes from Clang 7 to correctly call @@ -155,3 +255,5 @@ substrs=["calling 'get_two' with incomplete return type 'result::Two'"]) self.expect("expr get_two().member", error=True, substrs=["calling 'get_two' with incomplete return type 'result::Two'"]) + + self._check_incomplete_frame_variable_output() diff --git a/lldb/test/Shell/Breakpoint/jit-loader_jitlink_elf.test b/lldb/test/Shell/Breakpoint/jit-loader_jitlink_elf.test --- a/lldb/test/Shell/Breakpoint/jit-loader_jitlink_elf.test +++ b/lldb/test/Shell/Breakpoint/jit-loader_jitlink_elf.test @@ -1,6 +1,4 @@ # REQUIRES: target-x86_64 -# https://github.com/llvm/llvm-project/issues/56085 -# XFAIL: system-freebsd # XFAIL: system-windows # JITLink is the Orc-specific JIT linker implementation. diff --git a/lldb/test/Shell/Breakpoint/jit-loader_rtdyld_elf.test b/lldb/test/Shell/Breakpoint/jit-loader_rtdyld_elf.test --- a/lldb/test/Shell/Breakpoint/jit-loader_rtdyld_elf.test +++ b/lldb/test/Shell/Breakpoint/jit-loader_rtdyld_elf.test @@ -1,6 +1,4 @@ # REQUIRES: target-x86_64 -# https://github.com/llvm/llvm-project/issues/56085 -# XFAIL: system-freebsd # XFAIL: system-windows # RuntimeDyld can be used to link and load emitted code for both, MCJIT and Orc. diff --git a/lldb/test/Shell/SymbolFile/DWARF/x86/module-ownership.mm b/lldb/test/Shell/SymbolFile/DWARF/x86/module-ownership.mm --- a/lldb/test/Shell/SymbolFile/DWARF/x86/module-ownership.mm +++ b/lldb/test/Shell/SymbolFile/DWARF/x86/module-ownership.mm @@ -1,3 +1,4 @@ +// RUN: rm -rf %t.cache // RUN: %clang --target=x86_64-apple-macosx -g -gmodules -Wno-objc-root-class \ // RUN: -fmodules -fmodules-cache-path=%t.cache \ // RUN: -c -o %t.o %s -I%S/Inputs diff --git a/lldb/tools/debugserver/source/MacOSX/MachProcess.mm b/lldb/tools/debugserver/source/MacOSX/MachProcess.mm --- a/lldb/tools/debugserver/source/MacOSX/MachProcess.mm +++ b/lldb/tools/debugserver/source/MacOSX/MachProcess.mm @@ -3307,7 +3307,7 @@ return INVALID_NUB_PROCESS; flags = POSIX_SPAWN_START_SUSPENDED | POSIX_SPAWN_SETSIGDEF | - POSIX_SPAWN_SETSIGMASK; + POSIX_SPAWN_SETSIGMASK | POSIX_SPAWN_SETPGROUP; if (disable_aslr) flags |= _POSIX_SPAWN_DISABLE_ASLR; diff --git a/lldb/unittests/Symbol/TestTypeSystemClang.cpp b/lldb/unittests/Symbol/TestTypeSystemClang.cpp --- a/lldb/unittests/Symbol/TestTypeSystemClang.cpp +++ b/lldb/unittests/Symbol/TestTypeSystemClang.cpp @@ -405,7 +405,7 @@ RecordDecl *empty_base_decl = TypeSystemClang::GetAsRecordDecl(empty_base); EXPECT_NE(nullptr, empty_base_decl); - EXPECT_FALSE(TypeSystemClang::RecordHasFields(empty_base_decl)); + EXPECT_FALSE(m_ast->RecordHasFields(empty_base_decl)); // Test that a record with direct fields returns true CompilerType non_empty_base = m_ast->CreateRecordType( @@ -419,7 +419,7 @@ TypeSystemClang::GetAsRecordDecl(non_empty_base); EXPECT_NE(nullptr, non_empty_base_decl); EXPECT_NE(nullptr, non_empty_base_field_decl); - EXPECT_TRUE(TypeSystemClang::RecordHasFields(non_empty_base_decl)); + EXPECT_TRUE(m_ast->RecordHasFields(non_empty_base_decl)); std::vector> bases; @@ -440,10 +440,9 @@ m_ast->GetAsCXXRecordDecl(empty_derived.GetOpaqueQualType()); RecordDecl *empty_derived_non_empty_base_decl = TypeSystemClang::GetAsRecordDecl(empty_derived); - EXPECT_EQ(1u, TypeSystemClang::GetNumBaseClasses( + EXPECT_EQ(1u, m_ast->GetNumBaseClasses( empty_derived_non_empty_base_cxx_decl, false)); - EXPECT_TRUE( - TypeSystemClang::RecordHasFields(empty_derived_non_empty_base_decl)); + EXPECT_TRUE(m_ast->RecordHasFields(empty_derived_non_empty_base_decl)); // Test that a record with no direct fields, but fields in a virtual base // returns true @@ -463,10 +462,10 @@ m_ast->GetAsCXXRecordDecl(empty_derived2.GetOpaqueQualType()); RecordDecl *empty_derived_non_empty_vbase_decl = TypeSystemClang::GetAsRecordDecl(empty_derived2); - EXPECT_EQ(1u, TypeSystemClang::GetNumBaseClasses( + EXPECT_EQ(1u, m_ast->GetNumBaseClasses( empty_derived_non_empty_vbase_cxx_decl, false)); EXPECT_TRUE( - TypeSystemClang::RecordHasFields(empty_derived_non_empty_vbase_decl)); + m_ast->RecordHasFields(empty_derived_non_empty_vbase_decl)); } TEST_F(TestTypeSystemClang, TemplateArguments) { @@ -980,4 +979,3 @@ ModuleSP module = t.GetExeModule(); EXPECT_EQ(module.get(), nullptr); } - diff --git a/lldb/unittests/Target/PathMappingListTest.cpp b/lldb/unittests/Target/PathMappingListTest.cpp --- a/lldb/unittests/Target/PathMappingListTest.cpp +++ b/lldb/unittests/Target/PathMappingListTest.cpp @@ -40,7 +40,8 @@ map.RemapPath(ConstString(match.original.GetPath()), actual_remapped)); EXPECT_EQ(FileSpec(actual_remapped.GetStringRef()), match.remapped); FileSpec unmapped_spec; - EXPECT_TRUE(map.ReverseRemapPath(match.remapped, unmapped_spec).hasValue()); + EXPECT_TRUE( + map.ReverseRemapPath(match.remapped, unmapped_spec).has_value()); std::string unmapped_path = unmapped_spec.GetPath(); EXPECT_EQ(unmapped_path, orig_normalized); } diff --git a/llvm/docs/NVPTXUsage.rst b/llvm/docs/NVPTXUsage.rst --- a/llvm/docs/NVPTXUsage.rst +++ b/llvm/docs/NVPTXUsage.rst @@ -328,14 +328,16 @@ The NVPTX TargetMachine knows how to schedule ``NVVMReflect`` at the beginning of your pass manager; just use the following code when setting up your pass -manager: +manager and the PassBuilder will use ``registerPassBuilderCallbacks`` to let +NVPTXTargetMachine::registerPassBuilderCallbacks add the the pass to the +pass manager: .. code-block:: c++ std::unique_ptr TM = ...; - PassManagerBuilder PMBuilder(...); - if (TM) - TM->adjustPassManager(PMBuilder); + PassBuilder PB(TM); + ModulePassManager MPM; + PB.parsePassPipeline(MPM, ...); Reflection Parameters --------------------- diff --git a/llvm/docs/NewPassManager.rst b/llvm/docs/NewPassManager.rst --- a/llvm/docs/NewPassManager.rst +++ b/llvm/docs/NewPassManager.rst @@ -171,8 +171,7 @@ If a ``PassBuilder`` has a corresponding ``TargetMachine`` for a backend, it will call ``TargetMachine::registerPassBuilderCallbacks()`` to allow the -backend to inject passes into the pipeline. This is equivalent to the legacy -PM's ``TargetMachine::adjustPassManager()``. +backend to inject passes into the pipeline. Clang's ``BackendUtil.cpp`` shows examples of a frontend adding (mostly sanitizer) passes to various parts of the pipeline. @@ -518,10 +517,13 @@ Some IR passes are considered part of the backend codegen pipeline even if they are LLVM IR passes (whereas all MIR passes are codegen passes). This includes anything added via ``TargetPassConfig`` hooks, e.g. -``TargetPassConfig::addCodeGenPrepare()``. As mentioned before, passes added -in ``TargetMachine::adjustPassManager()`` are part of the optimization -pipeline, and should have a corresponding line in -``TargetMachine::registerPassBuilderCallbacks()``. +``TargetPassConfig::addCodeGenPrepare()``. + +The ``TargetMachine::adjustPassManager()`` function that was used to extend a +legacy PM with passes on a per target basis has been removed. It was mainly +used from opt, but since support for using the default pipelines has been +removed in opt the function isn't needed any longer. In the new PM such +adjustments are done by using ``TargetMachine::registerPassBuilderCallbacks()``. Currently there are efforts to make the codegen pipeline work with the new PM. diff --git a/llvm/docs/TestingGuide.rst b/llvm/docs/TestingGuide.rst --- a/llvm/docs/TestingGuide.rst +++ b/llvm/docs/TestingGuide.rst @@ -282,7 +282,8 @@ In that case to reduce the human work we can use the scripts available in llvm/utils/ to generate the assertions. -For example to generate assertions in an :program:`llc`-based test, run: +For example to generate assertions in an :program:`llc`-based test, after +adding RUN line use: .. code-block:: bash diff --git a/llvm/include/llvm/ADT/ArrayRef.h b/llvm/include/llvm/ADT/ArrayRef.h --- a/llvm/include/llvm/ADT/ArrayRef.h +++ b/llvm/include/llvm/ADT/ArrayRef.h @@ -68,7 +68,7 @@ /*implicit*/ ArrayRef() = default; /// Construct an empty ArrayRef from None. - /*implicit*/ ArrayRef(NoneType) {} + /*implicit*/ ArrayRef(std::nullopt_t) {} /// Construct an ArrayRef from a single element. /*implicit*/ ArrayRef(const T &OneElt) @@ -321,7 +321,7 @@ /*implicit*/ MutableArrayRef() = default; /// Construct an empty MutableArrayRef from None. - /*implicit*/ MutableArrayRef(NoneType) : ArrayRef() {} + /*implicit*/ MutableArrayRef(std::nullopt_t) : ArrayRef() {} /// Construct a MutableArrayRef from a single element. /*implicit*/ MutableArrayRef(T &OneElt) : ArrayRef(OneElt) {} diff --git a/llvm/include/llvm/ADT/None.h b/llvm/include/llvm/ADT/None.h --- a/llvm/include/llvm/ADT/None.h +++ b/llvm/include/llvm/ADT/None.h @@ -16,12 +16,14 @@ #ifndef LLVM_ADT_NONE_H #define LLVM_ADT_NONE_H +#include "llvm/Support/Compiler.h" #include namespace llvm { /// A simple null object to allow implicit construction of Optional /// and similar types without having to spell out the specialization's name. -using NoneType = std::nullopt_t; +LLVM_DEPRECATED("Use std::nullopt_t instead", "std::nullopt_t") +typedef std::nullopt_t NoneType; inline constexpr std::nullopt_t None = std::nullopt; } diff --git a/llvm/include/llvm/ADT/Optional.h b/llvm/include/llvm/ADT/Optional.h --- a/llvm/include/llvm/ADT/Optional.h +++ b/llvm/include/llvm/ADT/Optional.h @@ -239,7 +239,7 @@ using value_type = T; constexpr Optional() = default; - constexpr Optional(NoneType) {} + constexpr Optional(std::nullopt_t) {} constexpr Optional(const T &y) : Storage(std::in_place, y) {} constexpr Optional(const Optional &O) = default; @@ -274,37 +274,23 @@ void reset() { Storage.reset(); } + LLVM_DEPRECATED("Use &*X instead.", "&*X") constexpr const T *getPointer() const { return &Storage.value(); } + LLVM_DEPRECATED("Use &*X instead.", "&*X") T *getPointer() { return &Storage.value(); } constexpr const T &value() const & { return Storage.value(); } - LLVM_DEPRECATED("Use value instead.", "value") - constexpr const T &getValue() const & { - return Storage.value(); - } T &value() & { return Storage.value(); } - LLVM_DEPRECATED("Use value instead.", "value") T &getValue() & { - return Storage.value(); - } constexpr explicit operator bool() const { return has_value(); } constexpr bool has_value() const { return Storage.has_value(); } - LLVM_DEPRECATED("Use has_value instead.", "has_value") - constexpr bool hasValue() const { - return Storage.has_value(); - } - constexpr const T *operator->() const { return getPointer(); } - T *operator->() { return getPointer(); } + constexpr const T *operator->() const { return &Storage.value(); } + T *operator->() { return &Storage.value(); } constexpr const T &operator*() const & { return value(); } T &operator*() & { return value(); } template constexpr T value_or(U &&alt) const & { return has_value() ? value() : std::forward(alt); } - template - LLVM_DEPRECATED("Use value_or instead.", "value_or") - constexpr T getValueOr(U &&alt) const & { - return has_value() ? value() : std::forward(alt); - } /// Apply a function to the value if present; otherwise return None. template @@ -313,28 +299,13 @@ return F(value()); return None; } - template - LLVM_DEPRECATED("Use transform instead.", "transform") - auto map(const Function &F) const & -> Optional { - if (*this) - return F(value()); - return None; - } T &&value() && { return std::move(Storage.value()); } - LLVM_DEPRECATED("Use value instead.", "value") T &&getValue() && { - return std::move(Storage.value()); - } T &&operator*() && { return std::move(Storage.value()); } template T value_or(U &&alt) && { return has_value() ? std::move(value()) : std::forward(alt); } - template - LLVM_DEPRECATED("Use value_or instead.", "value_or") - T getValueOr(U &&alt) && { - return has_value() ? std::move(value()) : std::forward(alt); - } /// Apply a function to the value if present; otherwise return None. template @@ -344,14 +315,6 @@ return F(std::move(*this).value()); return None; } - template - LLVM_DEPRECATED("Use transform instead.", "transform") - auto map(const Function &F) - && -> Optional { - if (*this) - return F(std::move(*this).value()); - return None; - } }; template @@ -396,58 +359,62 @@ } template -constexpr bool operator==(const Optional &X, NoneType) { +constexpr bool operator==(const Optional &X, std::nullopt_t) { return !X; } template -constexpr bool operator==(NoneType, const Optional &X) { +constexpr bool operator==(std::nullopt_t, const Optional &X) { return X == None; } template -constexpr bool operator!=(const Optional &X, NoneType) { +constexpr bool operator!=(const Optional &X, std::nullopt_t) { return !(X == None); } template -constexpr bool operator!=(NoneType, const Optional &X) { +constexpr bool operator!=(std::nullopt_t, const Optional &X) { return X != None; } -template constexpr bool operator<(const Optional &, NoneType) { +template +constexpr bool operator<(const Optional &, std::nullopt_t) { return false; } -template constexpr bool operator<(NoneType, const Optional &X) { +template +constexpr bool operator<(std::nullopt_t, const Optional &X) { return X.has_value(); } template -constexpr bool operator<=(const Optional &X, NoneType) { +constexpr bool operator<=(const Optional &X, std::nullopt_t) { return !(None < X); } template -constexpr bool operator<=(NoneType, const Optional &X) { +constexpr bool operator<=(std::nullopt_t, const Optional &X) { return !(X < None); } -template constexpr bool operator>(const Optional &X, NoneType) { +template +constexpr bool operator>(const Optional &X, std::nullopt_t) { return None < X; } -template constexpr bool operator>(NoneType, const Optional &X) { +template +constexpr bool operator>(std::nullopt_t, const Optional &X) { return X < None; } template -constexpr bool operator>=(const Optional &X, NoneType) { +constexpr bool operator>=(const Optional &X, std::nullopt_t) { return None <= X; } template -constexpr bool operator>=(NoneType, const Optional &X) { +constexpr bool operator>=(std::nullopt_t, const Optional &X) { return X <= None; } @@ -511,7 +478,7 @@ return !(X < Y); } -raw_ostream &operator<<(raw_ostream &OS, NoneType); +raw_ostream &operator<<(raw_ostream &OS, std::nullopt_t); template () << std::declval())> diff --git a/llvm/include/llvm/ADT/StringMapEntry.h b/llvm/include/llvm/ADT/StringMapEntry.h --- a/llvm/include/llvm/ADT/StringMapEntry.h +++ b/llvm/include/llvm/ADT/StringMapEntry.h @@ -85,13 +85,14 @@ void setValue(const ValueTy &V) { second = V; } }; -template <> class StringMapEntryStorage : public StringMapEntryBase { +template <> +class StringMapEntryStorage : public StringMapEntryBase { public: - explicit StringMapEntryStorage(size_t keyLength, NoneType = None) + explicit StringMapEntryStorage(size_t keyLength, std::nullopt_t = None) : StringMapEntryBase(keyLength) {} StringMapEntryStorage(StringMapEntryStorage &entry) = delete; - NoneType getValue() const { return None; } + std::nullopt_t getValue() const { return None; } }; /// StringMapEntry - This is used to represent one value that is inserted into diff --git a/llvm/include/llvm/ADT/StringSet.h b/llvm/include/llvm/ADT/StringSet.h --- a/llvm/include/llvm/ADT/StringSet.h +++ b/llvm/include/llvm/ADT/StringSet.h @@ -20,8 +20,8 @@ /// StringSet - A wrapper for StringMap that provides set-like functionality. template -class StringSet : public StringMap { - using Base = StringMap; +class StringSet : public StringMap { + using Base = StringMap; public: StringSet() = default; diff --git a/llvm/include/llvm/ADT/StringSwitch.h b/llvm/include/llvm/ADT/StringSwitch.h --- a/llvm/include/llvm/ADT/StringSwitch.h +++ b/llvm/include/llvm/ADT/StringSwitch.h @@ -18,6 +18,7 @@ #include "llvm/Support/Compiler.h" #include #include +#include namespace llvm { @@ -47,7 +48,7 @@ /// The pointer to the result of this switch statement, once known, /// null before that. - Optional Result; + std::optional Result; public: explicit StringSwitch(StringRef S) diff --git a/llvm/include/llvm/ADT/TypeSwitch.h b/llvm/include/llvm/ADT/TypeSwitch.h --- a/llvm/include/llvm/ADT/TypeSwitch.h +++ b/llvm/include/llvm/ADT/TypeSwitch.h @@ -18,6 +18,7 @@ #include "llvm/ADT/Optional.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Casting.h" +#include namespace llvm { namespace detail { @@ -145,7 +146,7 @@ private: /// The pointer to the result of this switch statement, once known, /// null before that. - Optional result; + std::optional result; }; /// Specialization of TypeSwitch for void returning callables. diff --git a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h --- a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h +++ b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h @@ -19,6 +19,7 @@ #include "llvm/IR/PassManager.h" #include "llvm/Pass.h" #include +#include #include namespace llvm { @@ -187,8 +188,8 @@ /// they live long enough to be queried, but we re-use them each time. class LegacyAARGetter { Pass &P; - Optional BAR; - Optional AAR; + std::optional BAR; + std::optional AAR; public: LegacyAARGetter(Pass &P) : P(P) {} diff --git a/llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h b/llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h --- a/llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h +++ b/llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -1262,7 +1263,7 @@ LLVM_DEBUG(dbgs() << "isIrreducible = true\n"); Distribution Dist; unsigned NumHeadersWithWeight = 0; - Optional MinHeaderWeight; + std::optional MinHeaderWeight; DenseSet HeadersWithoutWeight; HeadersWithoutWeight.reserve(Loop.NumHeaders); for (uint32_t H = 0; H < Loop.NumHeaders; ++H) { diff --git a/llvm/include/llvm/Analysis/DemandedBits.h b/llvm/include/llvm/Analysis/DemandedBits.h --- a/llvm/include/llvm/Analysis/DemandedBits.h +++ b/llvm/include/llvm/Analysis/DemandedBits.h @@ -27,6 +27,7 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/IR/PassManager.h" #include "llvm/Pass.h" +#include namespace llvm { @@ -101,7 +102,7 @@ class DemandedBitsWrapperPass : public FunctionPass { private: - mutable Optional DB; + mutable std::optional DB; public: static char ID; // Pass identification, replacement for typeid diff --git a/llvm/include/llvm/Analysis/IRSimilarityIdentifier.h b/llvm/include/llvm/Analysis/IRSimilarityIdentifier.h --- a/llvm/include/llvm/Analysis/IRSimilarityIdentifier.h +++ b/llvm/include/llvm/Analysis/IRSimilarityIdentifier.h @@ -54,6 +54,7 @@ #include "llvm/IR/PassManager.h" #include "llvm/Pass.h" #include "llvm/Support/Allocator.h" +#include namespace llvm { class Module; @@ -127,7 +128,7 @@ /// This is only relevant if we are wrapping a CmpInst where we needed to /// change the predicate of a compare instruction from a greater than form /// to a less than form. It is None otherwise. - Optional RevisedPredicate; + std::optional RevisedPredicate; /// This is only relevant if we are wrapping a CallInst. If we are requiring /// that the function calls have matching names as well as types, and the @@ -137,7 +138,7 @@ /// function call type. The value held here is used to create the hash of the /// instruction, and check to make sure two instructions are close to one /// another. - Optional CalleeName; + std::optional CalleeName; /// This structure holds the distances of how far "ahead of" or "behind" the /// target blocks of a branch, or the incoming blocks of a phi nodes are. diff --git a/llvm/include/llvm/Analysis/InlineCost.h b/llvm/include/llvm/Analysis/InlineCost.h --- a/llvm/include/llvm/Analysis/InlineCost.h +++ b/llvm/include/llvm/Analysis/InlineCost.h @@ -20,6 +20,7 @@ #include "llvm/IR/PassManager.h" #include #include +#include namespace llvm { class AssumptionCache; @@ -227,13 +228,13 @@ Optional ColdCallSiteThreshold; /// Compute inline cost even when the cost has exceeded the threshold. - Optional ComputeFullInlineCost; + std::optional ComputeFullInlineCost; /// Indicate whether we should allow inline deferral. - Optional EnableDeferral; + std::optional EnableDeferral; /// Indicate whether we allow inlining for recursive call. - Optional AllowRecursiveCall = false; + std::optional AllowRecursiveCall = false; }; Optional getStringFnAttrAsInt(CallBase &CB, StringRef AttrKind); diff --git a/llvm/include/llvm/Analysis/LazyCallGraph.h b/llvm/include/llvm/Analysis/LazyCallGraph.h --- a/llvm/include/llvm/Analysis/LazyCallGraph.h +++ b/llvm/include/llvm/Analysis/LazyCallGraph.h @@ -49,6 +49,7 @@ #include "llvm/Support/raw_ostream.h" #include #include +#include #include #include @@ -311,7 +312,7 @@ /// The node works much like an optional in order to lazily populate the /// edges of each node. Until populated, there are no edges. Once populated, /// you can access the edges by dereferencing the node or using the `->` - /// operator as if the node was an `Optional`. + /// operator as if the node was an `std::optional`. class Node { friend class LazyCallGraph; friend class LazyCallGraph::RefSCC; @@ -378,7 +379,7 @@ int DFSNumber = 0; int LowLink = 0; - Optional Edges; + std::optional Edges; /// Basic constructor implements the scanning of F into Edges and /// EdgeIndexMap. diff --git a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h --- a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h +++ b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h @@ -19,6 +19,7 @@ #include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/IR/DiagnosticInfo.h" #include "llvm/Pass.h" +#include namespace llvm { @@ -452,7 +453,7 @@ // dependencies at runtime. There are is a vectorization-preventing dependency // if any pointer-difference is > getDiffChecks() const { + std::optional> getDiffChecks() const { if (!CanUseDiffCheck) return None; return {DiffChecks}; diff --git a/llvm/include/llvm/Analysis/LoopCacheAnalysis.h b/llvm/include/llvm/Analysis/LoopCacheAnalysis.h --- a/llvm/include/llvm/Analysis/LoopCacheAnalysis.h +++ b/llvm/include/llvm/Analysis/LoopCacheAnalysis.h @@ -16,6 +16,7 @@ #include "llvm/Analysis/LoopAnalysisManager.h" #include "llvm/IR/PassManager.h" +#include namespace llvm { @@ -269,7 +270,7 @@ /// The max. distance between array elements accessed in a loop so that the /// elements are classified to have temporal reuse. - Optional TRT; + std::optional TRT; const LoopInfo &LI; ScalarEvolution &SE; diff --git a/llvm/include/llvm/Analysis/MLInlineAdvisor.h b/llvm/include/llvm/Analysis/MLInlineAdvisor.h --- a/llvm/include/llvm/Analysis/MLInlineAdvisor.h +++ b/llvm/include/llvm/Analysis/MLInlineAdvisor.h @@ -18,6 +18,7 @@ #include #include #include +#include namespace llvm { class DiagnosticInfoOptimizationBase; @@ -117,7 +118,7 @@ // Make a copy of the FPI of the caller right before inlining. If inlining // fails, we can just update the cache with that value. const FunctionPropertiesInfo PreInlineCallerFPI; - Optional FPU; + std::optional FPU; }; } // namespace llvm diff --git a/llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h b/llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h --- a/llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h +++ b/llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h @@ -24,6 +24,7 @@ #include "llvm/IR/PredIteratorCache.h" #include "llvm/IR/ValueHandle.h" #include "llvm/Pass.h" +#include namespace llvm { @@ -470,7 +471,7 @@ void releaseMemory(); /// Return the clobber offset to dependent instruction. - Optional getClobberOffset(LoadInst *DepInst) const { + std::optional getClobberOffset(LoadInst *DepInst) const { const auto Off = ClobberOffsets.find(DepInst); if (Off != ClobberOffsets.end()) return Off->getSecond(); @@ -524,7 +525,7 @@ /// A wrapper analysis pass for the legacy pass manager that exposes a \c /// MemoryDepnedenceResults instance. class MemoryDependenceWrapperPass : public FunctionPass { - Optional MemDep; + std::optional MemDep; public: static char ID; diff --git a/llvm/include/llvm/Analysis/ModuleSummaryAnalysis.h b/llvm/include/llvm/Analysis/ModuleSummaryAnalysis.h --- a/llvm/include/llvm/Analysis/ModuleSummaryAnalysis.h +++ b/llvm/include/llvm/Analysis/ModuleSummaryAnalysis.h @@ -18,6 +18,7 @@ #include "llvm/IR/PassManager.h" #include "llvm/Pass.h" #include +#include namespace llvm { @@ -55,7 +56,7 @@ /// Legacy wrapper pass to provide the ModuleSummaryIndex object. class ModuleSummaryIndexWrapperPass : public ModulePass { - Optional Index; + std::optional Index; public: static char ID; diff --git a/llvm/include/llvm/Analysis/ObjCARCAnalysisUtils.h b/llvm/include/llvm/Analysis/ObjCARCAnalysisUtils.h --- a/llvm/include/llvm/Analysis/ObjCARCAnalysisUtils.h +++ b/llvm/include/llvm/Analysis/ObjCARCAnalysisUtils.h @@ -28,6 +28,7 @@ #include "llvm/IR/Constants.h" #include "llvm/IR/Module.h" #include "llvm/IR/ValueHandle.h" +#include namespace llvm { @@ -229,13 +230,13 @@ Module *M; /// The Metadata Kind for clang.imprecise_release metadata. - llvm::Optional ImpreciseReleaseMDKind; + std::optional ImpreciseReleaseMDKind; /// The Metadata Kind for clang.arc.copy_on_escape metadata. - llvm::Optional CopyOnEscapeMDKind; + std::optional CopyOnEscapeMDKind; /// The Metadata Kind for clang.arc.no_objc_arc_exceptions metadata. - llvm::Optional NoObjCARCExceptionsMDKind; + std::optional NoObjCARCExceptionsMDKind; public: void init(Module *Mod) { diff --git a/llvm/include/llvm/Analysis/ProfileSummaryInfo.h b/llvm/include/llvm/Analysis/ProfileSummaryInfo.h --- a/llvm/include/llvm/Analysis/ProfileSummaryInfo.h +++ b/llvm/include/llvm/Analysis/ProfileSummaryInfo.h @@ -19,6 +19,7 @@ #include "llvm/IR/ProfileSummary.h" #include "llvm/Pass.h" #include +#include namespace llvm { class BasicBlock; @@ -42,15 +43,15 @@ std::unique_ptr Summary; void computeThresholds(); // Count thresholds to answer isHotCount and isColdCount queries. - Optional HotCountThreshold, ColdCountThreshold; + std::optional HotCountThreshold, ColdCountThreshold; // True if the working set size of the code is considered huge, // because the number of profile counts required to reach the hot // percentile is above a huge threshold. - Optional HasHugeWorkingSetSize; + std::optional HasHugeWorkingSetSize; // True if the working set size of the code is considered large, // because the number of profile counts required to reach the hot // percentile is above a large threshold. - Optional HasLargeWorkingSetSize; + std::optional HasLargeWorkingSetSize; // Compute the threshold for a given cutoff. Optional computeThreshold(int PercentileCutoff) const; // The map that caches the threshold values. The keys are the percentile diff --git a/llvm/include/llvm/Analysis/ScalarEvolution.h b/llvm/include/llvm/Analysis/ScalarEvolution.h --- a/llvm/include/llvm/Analysis/ScalarEvolution.h +++ b/llvm/include/llvm/Analysis/ScalarEvolution.h @@ -1312,9 +1312,11 @@ /// ExitNotTakenInfo and BackedgeTakenInfo. struct ExitLimit { const SCEV *ExactNotTaken; // The exit is not taken exactly this many times - const SCEV *MaxNotTaken; // The exit is not taken at most this many times + const SCEV *ConstantMaxNotTaken; // The exit is not taken at most this many + // times + const SCEV *SymbolicMaxNotTaken; - // Not taken either exactly MaxNotTaken or zero times + // Not taken either exactly ConstantMaxNotTaken or zero times bool MaxOrZero = false; /// A set of predicate guards for this ExitLimit. The result is only valid @@ -1333,19 +1335,18 @@ /*implicit*/ ExitLimit(const SCEV *E); ExitLimit( - const SCEV *E, const SCEV *M, bool MaxOrZero, - ArrayRef *> PredSetList); + const SCEV *E, const SCEV *ConstantMaxNotTaken, bool MaxOrZero, + ArrayRef *> PredSetList = + None); - ExitLimit(const SCEV *E, const SCEV *M, bool MaxOrZero, + ExitLimit(const SCEV *E, const SCEV *ConstantMaxNotTaken, bool MaxOrZero, const SmallPtrSetImpl &PredSet); - ExitLimit(const SCEV *E, const SCEV *M, bool MaxOrZero); - /// Test whether this ExitLimit contains any computed information, or /// whether it's all SCEVCouldNotCompute values. bool hasAnyInfo() const { return !isa(ExactNotTaken) || - !isa(MaxNotTaken); + !isa(ConstantMaxNotTaken); } /// Test whether this ExitLimit contains all information. @@ -1359,15 +1360,17 @@ struct ExitNotTakenInfo { PoisoningVH ExitingBlock; const SCEV *ExactNotTaken; - const SCEV *MaxNotTaken; + const SCEV *ConstantMaxNotTaken; + const SCEV *SymbolicMaxNotTaken; SmallPtrSet Predicates; - explicit ExitNotTakenInfo(PoisoningVH ExitingBlock, - const SCEV *ExactNotTaken, - const SCEV *MaxNotTaken, - const SmallPtrSet &Predicates) - : ExitingBlock(ExitingBlock), ExactNotTaken(ExactNotTaken), - MaxNotTaken(ExactNotTaken), Predicates(Predicates) {} + explicit ExitNotTakenInfo( + PoisoningVH ExitingBlock, const SCEV *ExactNotTaken, + const SCEV *ConstantMaxNotTaken, const SCEV *SymbolicMaxNotTaken, + const SmallPtrSet &Predicates) + : ExitingBlock(ExitingBlock), ExactNotTaken(ExactNotTaken), + ConstantMaxNotTaken(ConstantMaxNotTaken), + SymbolicMaxNotTaken(SymbolicMaxNotTaken), Predicates(Predicates) {} bool hasAlwaysTruePredicate() const { return Predicates.empty(); diff --git a/llvm/include/llvm/Analysis/TargetLibraryInfo.h b/llvm/include/llvm/Analysis/TargetLibraryInfo.h --- a/llvm/include/llvm/Analysis/TargetLibraryInfo.h +++ b/llvm/include/llvm/Analysis/TargetLibraryInfo.h @@ -15,6 +15,7 @@ #include "llvm/IR/InstrTypes.h" #include "llvm/IR/PassManager.h" #include "llvm/Pass.h" +#include namespace llvm { @@ -235,7 +236,7 @@ public: explicit TargetLibraryInfo(const TargetLibraryInfoImpl &Impl, - Optional F = None) + std::optional F = None) : Impl(&Impl), OverrideAsUnavailable(NumLibFuncs) { if (!F) return; @@ -468,12 +469,12 @@ friend AnalysisInfoMixin; static AnalysisKey Key; - Optional BaselineInfoImpl; + std::optional BaselineInfoImpl; }; class TargetLibraryInfoWrapperPass : public ImmutablePass { TargetLibraryAnalysis TLA; - Optional TLI; + std::optional TLI; virtual void anchor(); diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -30,6 +30,7 @@ #include "llvm/Support/BranchProbability.h" #include "llvm/Support/InstructionCost.h" #include +#include #include namespace llvm { @@ -2640,7 +2641,7 @@ /// and is queried by passes. class TargetTransformInfoWrapperPass : public ImmutablePass { TargetIRAnalysis TIRA; - Optional TTI; + std::optional TTI; virtual void anchor(); diff --git a/llvm/include/llvm/Analysis/TensorSpec.h b/llvm/include/llvm/Analysis/TensorSpec.h --- a/llvm/include/llvm/Analysis/TensorSpec.h +++ b/llvm/include/llvm/Analysis/TensorSpec.h @@ -16,6 +16,7 @@ #include "llvm/Support/JSON.h" #include +#include #include namespace llvm { @@ -107,7 +108,7 @@ struct LoggedFeatureSpec { TensorSpec Spec; - Optional LoggingName; + std::optional LoggingName; const std::string &getLoggingName() const { return LoggingName ? *LoggingName : Spec.name(); } diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -758,6 +758,7 @@ use_iterator() = default; use_iterator(const use_iterator &I) = default; + use_iterator &operator=(const use_iterator &) = default; bool operator==(const use_iterator &x) const { return Op == x.Op; } bool operator!=(const use_iterator &x) const { diff --git a/llvm/include/llvm/DebugInfo/DWARF/DWARFObject.h b/llvm/include/llvm/DebugInfo/DWARF/DWARFObject.h --- a/llvm/include/llvm/DebugInfo/DWARF/DWARFObject.h +++ b/llvm/include/llvm/DebugInfo/DWARF/DWARFObject.h @@ -12,6 +12,7 @@ #include "llvm/DebugInfo/DWARF/DWARFRelocMap.h" #include "llvm/DebugInfo/DWARF/DWARFSection.h" #include "llvm/Object/ObjectFile.h" +#include namespace llvm { // This is responsible for low level access to the object file. It @@ -81,8 +82,8 @@ virtual StringRef getCUIndexSection() const { return ""; } virtual StringRef getGdbIndexSection() const { return ""; } virtual StringRef getTUIndexSection() const { return ""; } - virtual Optional find(const DWARFSection &Sec, - uint64_t Pos) const = 0; + virtual std::optional find(const DWARFSection &Sec, + uint64_t Pos) const = 0; }; } // namespace llvm diff --git a/llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h b/llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h --- a/llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h +++ b/llvm/include/llvm/ExecutionEngine/JITLink/JITLink.h @@ -530,7 +530,7 @@ return *Base; } - /// Return the addressable that thsi symbol points to. + /// Return the addressable that this symbol points to. const Addressable &getAddressable() const { assert(Base && "Cannot get underlying addressable for null symbol"); return *Base; diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h --- a/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h +++ b/llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h @@ -92,34 +92,61 @@ /// directive is present or not. Optional HasRequiresUnifiedSharedMemory; + /// First separator used between the initial two parts of a name. + Optional FirstSeparator; + /// Separator used between all of the rest consecutive parts of s name + Optional Separator; + OpenMPIRBuilderConfig() {} OpenMPIRBuilderConfig(bool IsEmbedded, bool IsTargetCodegen, bool HasRequiresUnifiedSharedMemory) : IsEmbedded(IsEmbedded), IsTargetCodegen(IsTargetCodegen), HasRequiresUnifiedSharedMemory(HasRequiresUnifiedSharedMemory) {} - // Convenience getter functions that assert if the value is not present. - bool isEmbedded() { + // Getters functions that assert if the required values are not present. + bool isEmbedded() const { assert(IsEmbedded.has_value() && "IsEmbedded is not set"); return IsEmbedded.value(); } - bool isTargetCodegen() { + bool isTargetCodegen() const { assert(IsTargetCodegen.has_value() && "IsTargetCodegen is not set"); return IsTargetCodegen.value(); } - bool hasRequiresUnifiedSharedMemory() { + bool hasRequiresUnifiedSharedMemory() const { assert(HasRequiresUnifiedSharedMemory.has_value() && "HasUnifiedSharedMemory is not set"); return HasRequiresUnifiedSharedMemory.value(); } + // Returns the FirstSeparator if set, otherwise use the default + // separator depending on isTargetCodegen + StringRef firstSeparator() const { + if (FirstSeparator.has_value()) + return FirstSeparator.value(); + if (isTargetCodegen()) + return "_"; + return "."; + } + + // Returns the Separator if set, otherwise use the default + // separator depending on isTargetCodegen + StringRef separator() const { + if (Separator.has_value()) + return Separator.value(); + if (isTargetCodegen()) + return "$"; + return "."; + } + void setIsEmbedded(bool Value) { IsEmbedded = Value; } void setIsTargetCodegen(bool Value) { IsTargetCodegen = Value; } void setHasRequiresUnifiedSharedMemory(bool Value) { HasRequiresUnifiedSharedMemory = Value; } + void setFirstSeparator(StringRef FS) { FirstSeparator = FS; } + void setSeparator(StringRef S) { Separator = S; } }; /// An interface to create LLVM-IR for OpenMP directives. @@ -150,6 +177,16 @@ /// Type used throughout for insertion points. using InsertPointTy = IRBuilder<>::InsertPoint; + /// Get the create a name using the platform specific separators. + /// \param Parts parts of the final name that needs separation + /// The created name has a first separator between the first and second part + /// and a second separator between all other parts. + /// E.g. with FirstSeparator "$" and Separator "." and + /// parts: "p1", "p2", "p3", "p4" + /// The resulting name is "p1$p2.p3.p4" + /// The separators are retrieved from the OpenMPIRBuilderConfig. + std::string createPlatformSpecificName(ArrayRef Parts) const; + /// Callback type for variable finalization (think destructors). /// /// \param CodeGenIP is the insertion point at which the finalization code diff --git a/llvm/include/llvm/FuzzMutate/OpDescriptor.h b/llvm/include/llvm/FuzzMutate/OpDescriptor.h --- a/llvm/include/llvm/FuzzMutate/OpDescriptor.h +++ b/llvm/include/llvm/FuzzMutate/OpDescriptor.h @@ -57,7 +57,7 @@ public: /// Create a fully general source predicate. SourcePred(PredT Pred, MakeT Make) : Pred(Pred), Make(Make) {} - SourcePred(PredT Pred, NoneType) : Pred(Pred) { + SourcePred(PredT Pred, std::nullopt_t) : Pred(Pred) { Make = [Pred](ArrayRef Cur, ArrayRef BaseTypes) { // Default filter just calls Pred on each of the base types. std::vector Result; diff --git a/llvm/include/llvm/IR/InstrTypes.h b/llvm/include/llvm/IR/InstrTypes.h --- a/llvm/include/llvm/IR/InstrTypes.h +++ b/llvm/include/llvm/IR/InstrTypes.h @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -2014,7 +2015,7 @@ /// /// It is an error to call this for operand bundle types that may have /// multiple instances of them on the same instruction. - Optional getOperandBundle(StringRef Name) const { + std::optional getOperandBundle(StringRef Name) const { assert(countOperandBundlesOfType(Name) < 2 && "Precondition violated!"); for (unsigned i = 0, e = getNumOperandBundles(); i != e; ++i) { diff --git a/llvm/include/llvm/IR/Instructions.h b/llvm/include/llvm/IR/Instructions.h --- a/llvm/include/llvm/IR/Instructions.h +++ b/llvm/include/llvm/IR/Instructions.h @@ -38,6 +38,7 @@ #include #include #include +#include namespace llvm { @@ -3618,7 +3619,7 @@ /// their prof branch_weights metadata. class SwitchInstProfUpdateWrapper { SwitchInst &SI; - Optional > Weights = None; + std::optional> Weights = None; bool Changed = false; protected: @@ -3629,7 +3630,7 @@ void init(); public: - using CaseWeightOpt = Optional; + using CaseWeightOpt = std::optional; SwitchInst *operator->() { return &SI; } SwitchInst &operator*() { return SI; } operator SwitchInst *() { return &SI; } @@ -5412,7 +5413,7 @@ /// A helper function that returns an atomic operation's sync scope; returns /// None if it is not an atomic operation. -inline Optional getAtomicSyncScopeID(const Instruction *I) { +inline std::optional getAtomicSyncScopeID(const Instruction *I) { if (!I->isAtomic()) return None; if (auto *AI = dyn_cast(I)) diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -2067,6 +2067,10 @@ def int_amdgcn_wmma_i32_16x16x16_iu8 : AMDGPUWmmaIntrinsicIU; def int_amdgcn_wmma_i32_16x16x16_iu4 : AMDGPUWmmaIntrinsicIU; +def int_amdgcn_s_wait_event_export_ready : + ClangBuiltin<"__builtin_amdgcn_s_wait_event_export_ready">, + Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrWillReturn] +>; //===----------------------------------------------------------------------===// // Deep learning intrinsics. diff --git a/llvm/include/llvm/IR/ModuleSummaryIndex.h b/llvm/include/llvm/IR/ModuleSummaryIndex.h --- a/llvm/include/llvm/IR/ModuleSummaryIndex.h +++ b/llvm/include/llvm/IR/ModuleSummaryIndex.h @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include @@ -1700,7 +1701,7 @@ /// For the given \p TypeId, this returns the TypeIdCompatibleVtableMap /// entry if present in the summary map. This may be used when importing. - Optional + std::optional getTypeIdCompatibleVtableSummary(StringRef TypeId) const { auto I = TypeIdCompatibleVtableMap.find(TypeId); if (I == TypeIdCompatibleVtableMap.end()) diff --git a/llvm/include/llvm/IR/OptBisect.h b/llvm/include/llvm/IR/OptBisect.h --- a/llvm/include/llvm/IR/OptBisect.h +++ b/llvm/include/llvm/IR/OptBisect.h @@ -29,7 +29,8 @@ /// IRDescription is a textual description of the IR unit the pass is running /// over. - virtual bool shouldRunPass(const Pass *P, StringRef IRDescription) { + virtual bool shouldRunPass(const StringRef PassName, + StringRef IRDescription) { return true; } @@ -55,7 +56,8 @@ /// Checks the bisect limit to determine if the specified pass should run. /// /// This forwards to checkPass(). - bool shouldRunPass(const Pass *P, StringRef IRDescription) override; + bool shouldRunPass(const StringRef PassName, + StringRef IRDescription) override; /// isEnabled() should return true before calling shouldRunPass(). bool isEnabled() const override { return BisectLimit != Disabled; } @@ -89,7 +91,7 @@ /// Singleton instance of the OptBisect class, so multiple pass managers don't /// need to coordinate their uses of OptBisect. -OptBisect &getOptBisector(); +OptPassGate &getGlobalPassGate(); } // end namespace llvm diff --git a/llvm/include/llvm/IR/Statepoint.h b/llvm/include/llvm/IR/Statepoint.h --- a/llvm/include/llvm/IR/Statepoint.h +++ b/llvm/include/llvm/IR/Statepoint.h @@ -30,6 +30,7 @@ #include #include #include +#include #include namespace llvm { @@ -233,8 +234,8 @@ /// have attributes that describe properties of gc.statepoint call they will be /// eventually be wrapped in. This struct is used represent such directives. struct StatepointDirectives { - Optional NumPatchBytes; - Optional StatepointID; + std::optional NumPatchBytes; + std::optional StatepointID; static const uint64_t DefaultStatepointID = 0xABCDEF00; static const uint64_t DeoptBundleStatepointID = 0xABCDEF0F; diff --git a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h --- a/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h +++ b/llvm/include/llvm/LTO/legacy/LTOCodeGenerator.h @@ -24,6 +24,7 @@ // As of this writing, we don't separate IPO and the Post-IPO SOPT. They // are intermingled together, and are driven by a single pass manager (see // PassManagerBuilder::populateLTOPassManager()). +// FIXME: populateLTOPassManager no longer exists. // // The "LTOCodeGenerator" is the driver for the IPO and Post-IPO stages. // The "CodeGenerator" here is bit confusing. Don't confuse the "CodeGenerator" @@ -51,9 +52,6 @@ #include #include -/// Enable global value internalization in LTO. -extern llvm::cl::opt EnableLTOInternalization; - namespace llvm { template class ArrayRef; class LLVMContext; @@ -66,6 +64,9 @@ class raw_ostream; class raw_pwrite_stream; +/// Enable global value internalization in LTO. +extern cl::opt EnableLTOInternalization; + //===----------------------------------------------------------------------===// /// C++ class which implements the opaque lto_code_gen_t type. /// diff --git a/llvm/include/llvm/MC/MCELFStreamer.h b/llvm/include/llvm/MC/MCELFStreamer.h --- a/llvm/include/llvm/MC/MCELFStreamer.h +++ b/llvm/include/llvm/MC/MCELFStreamer.h @@ -76,14 +76,14 @@ void emitIdent(StringRef IdentString) override; - void emitValueToAlignment(unsigned, int64_t, unsigned, unsigned) override; + void emitValueToAlignment(Align, int64_t, unsigned, unsigned) override; void emitCGProfileEntry(const MCSymbolRefExpr *From, const MCSymbolRefExpr *To, uint64_t Count) override; void finishImpl() override; - void emitBundleAlignMode(unsigned AlignPow2) override; + void emitBundleAlignMode(Align Alignment) override; void emitBundleLock(bool AlignToEnd) override; void emitBundleUnlock() override; diff --git a/llvm/include/llvm/MC/MCObjectFileInfo.h b/llvm/include/llvm/MC/MCObjectFileInfo.h --- a/llvm/include/llvm/MC/MCObjectFileInfo.h +++ b/llvm/include/llvm/MC/MCObjectFileInfo.h @@ -27,10 +27,6 @@ class MCObjectFileInfo { protected: - /// True if .comm supports alignment. This is a hack for as long as we - /// support 10.4 Tiger, whose assembler doesn't support alignment on comm. - bool CommDirectiveSupportsAlignment = false; - /// True if target object file supports a weak_definition of constant 0 for an /// omitted EH frame. bool SupportsWeakOmittedEHFrame = false; @@ -257,10 +253,6 @@ return OmitDwarfIfHaveCompactUnwind; } - bool getCommDirectiveSupportsAlignment() const { - return CommDirectiveSupportsAlignment; - } - unsigned getFDEEncoding() const { return FDECFIEncoding; } unsigned getCompactUnwindDwarfEHFrameOnly() const { diff --git a/llvm/include/llvm/MC/MCObjectStreamer.h b/llvm/include/llvm/MC/MCObjectStreamer.h --- a/llvm/include/llvm/MC/MCObjectStreamer.h +++ b/llvm/include/llvm/MC/MCObjectStreamer.h @@ -148,14 +148,14 @@ /// can change its size during relaxation. virtual void emitInstToFragment(const MCInst &Inst, const MCSubtargetInfo &); - void emitBundleAlignMode(unsigned AlignPow2) override; + void emitBundleAlignMode(Align Alignment) override; void emitBundleLock(bool AlignToEnd) override; void emitBundleUnlock() override; void emitBytes(StringRef Data) override; - void emitValueToAlignment(unsigned ByteAlignment, int64_t Value = 0, + void emitValueToAlignment(Align Alignment, int64_t Value = 0, unsigned ValueSize = 1, unsigned MaxBytesToEmit = 0) override; - void emitCodeAlignment(unsigned ByteAlignment, const MCSubtargetInfo *STI, + void emitCodeAlignment(Align ByteAlignment, const MCSubtargetInfo *STI, unsigned MaxBytesToEmit = 0) override; void emitValueToOffset(const MCExpr *Offset, unsigned char Value, SMLoc Loc) override; diff --git a/llvm/include/llvm/MC/MCSection.h b/llvm/include/llvm/MC/MCSection.h --- a/llvm/include/llvm/MC/MCSection.h +++ b/llvm/include/llvm/MC/MCSection.h @@ -137,9 +137,15 @@ MCSymbol *getEndSymbol(MCContext &Ctx); bool hasEnded() const; - unsigned getAlignment() const { return Alignment.value(); } + Align getAlign() const { return Alignment; } void setAlignment(Align Value) { Alignment = Value; } + /// Makes sure that Alignment is at least MinAlignment. + void ensureMinAlignment(Align MinAlignment) { + if (Alignment < MinAlignment) + Alignment = MinAlignment; + } + unsigned getOrdinal() const { return Ordinal; } void setOrdinal(unsigned Value) { Ordinal = Value; } diff --git a/llvm/include/llvm/MC/MCStreamer.h b/llvm/include/llvm/MC/MCStreamer.h --- a/llvm/include/llvm/MC/MCStreamer.h +++ b/llvm/include/llvm/MC/MCStreamer.h @@ -603,11 +603,9 @@ /// \param LabelSym - Label on the block of storage. /// \param Size - The size of the block of storage. /// \param CsectSym - Csect name for the block of storage. - /// \param ByteAlignment - The alignment of the symbol in bytes. Must be a - /// power of 2. + /// \param Alignment - The alignment of the symbol in bytes. virtual void emitXCOFFLocalCommonSymbol(MCSymbol *LabelSym, uint64_t Size, - MCSymbol *CsectSym, - unsigned ByteAlignment); + MCSymbol *CsectSym, Align Alignment); /// Emit a symbol's linkage and visibility with a linkage directive for XCOFF. /// @@ -856,15 +854,14 @@ /// /// This used to implement the .align assembler directive. /// - /// \param ByteAlignment - The alignment to reach. This must be a power of - /// two on some targets. + /// \param Alignment - The alignment to reach. /// \param Value - The value to use when filling bytes. /// \param ValueSize - The size of the integer (in bytes) to emit for /// \p Value. This must match a native machine width. /// \param MaxBytesToEmit - The maximum numbers of bytes to emit, or 0. If /// the alignment cannot be reached in this many bytes, no bytes are /// emitted. - virtual void emitValueToAlignment(unsigned ByteAlignment, int64_t Value = 0, + virtual void emitValueToAlignment(Align Alignment, int64_t Value = 0, unsigned ValueSize = 1, unsigned MaxBytesToEmit = 0); @@ -873,14 +870,12 @@ /// This used to align code where the alignment bytes may be executed. This /// can emit different bytes for different sizes to optimize execution. /// - /// \param ByteAlignment - The alignment to reach. This must be a power of - /// two on some targets. + /// \param Alignment - The alignment to reach. /// \param STI - The MCSubtargetInfo in operation when padding is emitted. /// \param MaxBytesToEmit - The maximum numbers of bytes to emit, or 0. If /// the alignment cannot be reached in this many bytes, no bytes are /// emitted. - virtual void emitCodeAlignment(unsigned ByteAlignment, - const MCSubtargetInfo *STI, + virtual void emitCodeAlignment(Align Alignment, const MCSubtargetInfo *STI, unsigned MaxBytesToEmit = 0); /// Emit some number of copies of \p Value until the byte offset \p @@ -1110,9 +1105,8 @@ MCSymbol *FnSym); /// Set the bundle alignment mode from now on in the section. - /// The argument is the power of 2 to which the alignment is set. The - /// value 0 means turn the bundle alignment off. - virtual void emitBundleAlignMode(unsigned AlignPow2); + /// The value 1 means turn the bundle alignment off. + virtual void emitBundleAlignMode(Align Alignment); /// The following instructions are a bundle-locked group. /// diff --git a/llvm/include/llvm/MC/MCXCOFFStreamer.h b/llvm/include/llvm/MC/MCXCOFFStreamer.h --- a/llvm/include/llvm/MC/MCXCOFFStreamer.h +++ b/llvm/include/llvm/MC/MCXCOFFStreamer.h @@ -27,8 +27,7 @@ SMLoc Loc = SMLoc()) override; void emitInstToData(const MCInst &Inst, const MCSubtargetInfo &) override; void emitXCOFFLocalCommonSymbol(MCSymbol *LabelSym, uint64_t Size, - MCSymbol *CsectSym, - unsigned ByteAlign) override; + MCSymbol *CsectSym, Align Alignment) override; void emitXCOFFSymbolLinkageWithVisibility(MCSymbol *Symbol, MCSymbolAttr Linkage, MCSymbolAttr Visibility) override; diff --git a/llvm/include/llvm/Passes/StandardInstrumentations.h b/llvm/include/llvm/Passes/StandardInstrumentations.h --- a/llvm/include/llvm/Passes/StandardInstrumentations.h +++ b/llvm/include/llvm/Passes/StandardInstrumentations.h @@ -74,11 +74,12 @@ bool shouldRun(StringRef PassID, Any IR); }; -class OptBisectInstrumentation { +class OptPassGateInstrumentation { + LLVMContext &Context; bool HasWrittenIR = false; - public: - OptBisectInstrumentation() = default; + OptPassGateInstrumentation(LLVMContext &Context) : Context(Context) {} + bool shouldRun(StringRef PassName, Any IR); void registerCallbacks(PassInstrumentationCallbacks &PIC); }; @@ -528,7 +529,7 @@ TimePassesHandler TimePasses; TimeProfilingPassesHandler TimeProfilingPasses; OptNoneInstrumentation OptNone; - OptBisectInstrumentation OptBisect; + OptPassGateInstrumentation OptPassGate; PreservedCFGCheckerInstrumentation PreservedCFGChecker; IRChangedPrinter PrintChangedIR; PseudoProbeVerifier PseudoProbeVerification; @@ -540,7 +541,8 @@ bool VerifyEach; public: - StandardInstrumentations(bool DebugLogging, bool VerifyEach = false, + StandardInstrumentations(LLVMContext &Context, bool DebugLogging, + bool VerifyEach = false, PrintPassOptions PrintPassOpts = PrintPassOptions()); // Register all the standard instrumentation callbacks. If \p FAM is nullptr diff --git a/llvm/include/llvm/ProfileData/MemProf.h b/llvm/include/llvm/ProfileData/MemProf.h --- a/llvm/include/llvm/ProfileData/MemProf.h +++ b/llvm/include/llvm/ProfileData/MemProf.h @@ -11,6 +11,7 @@ #include "llvm/Support/raw_ostream.h" #include +#include namespace llvm { namespace memprof { @@ -144,7 +145,7 @@ GlobalValue::GUID Function; // The symbol name for the function. Only populated in the Frame by the reader // if requested during initialization. This field should not be serialized. - llvm::Optional SymbolName; + std::optional SymbolName; // The source line offset of the call from the beginning of parent function. uint32_t LineOffset; // The source column number of the call to help distinguish multiple calls diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h b/llvm/include/llvm/Support/AArch64TargetParser.h --- a/llvm/include/llvm/Support/AArch64TargetParser.h +++ b/llvm/include/llvm/Support/AArch64TargetParser.h @@ -77,6 +77,7 @@ AEK_B16B16 = 1ULL << 46, // FEAT_B16B16 AEK_SMEF16F16 = 1ULL << 47, // FEAT_SMEF16F16 AEK_CSSC = 1ULL << 48, // FEAT_CSSC + AEK_RCPC3 = 1ULL << 49, // FEAT_LRCPC3 }; enum class ArchKind { diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def b/llvm/include/llvm/Support/AArch64TargetParser.def --- a/llvm/include/llvm/Support/AArch64TargetParser.def +++ b/llvm/include/llvm/Support/AArch64TargetParser.def @@ -152,6 +152,7 @@ AARCH64_ARCH_EXT_NAME("mops", AArch64::AEK_MOPS, "+mops", "-mops") AARCH64_ARCH_EXT_NAME("pmuv3", AArch64::AEK_PERFMON, "+perfmon", "-perfmon") AARCH64_ARCH_EXT_NAME("cssc", AArch64::AEK_CSSC, "+cssc", "-cssc") +AARCH64_ARCH_EXT_NAME("rcpc3", AArch64::AEK_RCPC3, "+rcpc3", "-rcpc3") #undef AARCH64_ARCH_EXT_NAME #ifndef AARCH64_CPU_NAME diff --git a/llvm/include/llvm/Support/ARMTargetParserCommon.h b/llvm/include/llvm/Support/ARMTargetParserCommon.h --- a/llvm/include/llvm/Support/ARMTargetParserCommon.h +++ b/llvm/include/llvm/Support/ARMTargetParserCommon.h @@ -37,6 +37,15 @@ // Little/Big endian EndianKind parseArchEndian(StringRef Arch); +struct ParsedBranchProtection { + StringRef Scope; + StringRef Key; + bool BranchTargetEnforcement; +}; + +bool parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP, + StringRef &Err); + } // namespace ARM } // namespace llvm #endif diff --git a/llvm/include/llvm/Support/CachePruning.h b/llvm/include/llvm/Support/CachePruning.h --- a/llvm/include/llvm/Support/CachePruning.h +++ b/llvm/include/llvm/Support/CachePruning.h @@ -17,6 +17,7 @@ #include "llvm/ADT/Optional.h" #include "llvm/Support/MemoryBuffer.h" #include +#include namespace llvm { @@ -30,7 +31,7 @@ /// directory too often. It does not impact the decision of which file to /// prune. A value of 0 forces the scan to occur. A value of None disables /// pruning. - llvm::Optional Interval = std::chrono::seconds(1200); + std::optional Interval = std::chrono::seconds(1200); /// The expiration for a file. When a file hasn't been accessed for Expiration /// seconds, it is removed from the cache. A value of 0 disables the diff --git a/llvm/include/llvm/Support/GenericDomTreeConstruction.h b/llvm/include/llvm/Support/GenericDomTreeConstruction.h --- a/llvm/include/llvm/Support/GenericDomTreeConstruction.h +++ b/llvm/include/llvm/Support/GenericDomTreeConstruction.h @@ -44,6 +44,7 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/Support/Debug.h" #include "llvm/Support/GenericDomTree.h" +#include #include #define DEBUG_TYPE "dom-tree-builder" @@ -403,7 +404,7 @@ // immune to swap successors transformation (e.g. canonicalizing branch // predicates). SuccOrder is initialized lazily only for successors of // reverse unreachable nodes. - Optional SuccOrder; + std::optional SuccOrder; auto InitSuccOrderOnce = [&]() { SuccOrder = NodeOrderMap(); for (const auto Node : nodes(DT.Parent)) diff --git a/llvm/include/llvm/Support/GlobPattern.h b/llvm/include/llvm/Support/GlobPattern.h --- a/llvm/include/llvm/Support/GlobPattern.h +++ b/llvm/include/llvm/Support/GlobPattern.h @@ -17,6 +17,7 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/Optional.h" #include "llvm/Support/Error.h" +#include #include // This class represents a glob pattern. Supported metacharacters @@ -48,9 +49,9 @@ std::vector Tokens; // The following members are for optimization. - Optional Exact; - Optional Prefix; - Optional Suffix; + std::optional Exact; + std::optional Prefix; + std::optional Suffix; }; } diff --git a/llvm/include/llvm/Support/HashBuilder.h b/llvm/include/llvm/Support/HashBuilder.h --- a/llvm/include/llvm/Support/HashBuilder.h +++ b/llvm/include/llvm/Support/HashBuilder.h @@ -23,6 +23,7 @@ #include "llvm/Support/type_traits.h" #include +#include #include namespace llvm { @@ -80,7 +81,7 @@ Hasher(*OptionalHasher) {} private: - Optional OptionalHasher; + std::optional OptionalHasher; HasherT &Hasher; }; diff --git a/llvm/include/llvm/Support/InitLLVM.h b/llvm/include/llvm/Support/InitLLVM.h --- a/llvm/include/llvm/Support/InitLLVM.h +++ b/llvm/include/llvm/Support/InitLLVM.h @@ -13,6 +13,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/Support/Allocator.h" #include "llvm/Support/PrettyStackTrace.h" +#include // The main() functions in typical LLVM tools start with InitLLVM which does // the following one-time initializations: @@ -45,7 +46,7 @@ private: BumpPtrAllocator Alloc; SmallVector Args; - Optional StackPrinter; + std::optional StackPrinter; }; } // namespace llvm diff --git a/llvm/include/llvm/Support/InstructionCost.h b/llvm/include/llvm/Support/InstructionCost.h --- a/llvm/include/llvm/Support/InstructionCost.h +++ b/llvm/include/llvm/Support/InstructionCost.h @@ -21,6 +21,7 @@ #include "llvm/ADT/Optional.h" #include "llvm/Support/MathExtras.h" #include +#include namespace llvm { @@ -84,7 +85,7 @@ /// This function is intended to be used as sparingly as possible, since the /// class provides the full range of operator support required for arithmetic /// and comparisons. - Optional getValue() const { + std::optional getValue() const { if (isValid()) return Value; return None; diff --git a/llvm/include/llvm/Support/SMLoc.h b/llvm/include/llvm/Support/SMLoc.h --- a/llvm/include/llvm/Support/SMLoc.h +++ b/llvm/include/llvm/Support/SMLoc.h @@ -50,7 +50,7 @@ SMLoc Start, End; SMRange() = default; - SMRange(NoneType) {} + SMRange(std::nullopt_t) {} SMRange(SMLoc St, SMLoc En) : Start(St), End(En) { assert(Start.isValid() == End.isValid() && "Start and End should either both be valid or both be invalid!"); diff --git a/llvm/include/llvm/Support/TargetParser.h b/llvm/include/llvm/Support/TargetParser.h --- a/llvm/include/llvm/Support/TargetParser.h +++ b/llvm/include/llvm/Support/TargetParser.h @@ -182,19 +182,6 @@ bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector &Features); } // namespace RISCV - -namespace ARM { -struct ParsedBranchProtection { - StringRef Scope; - StringRef Key; - bool BranchTargetEnforcement; -}; - -bool parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP, - StringRef &Err); - -} // namespace ARM - } // namespace llvm #endif diff --git a/llvm/include/llvm/Support/ToolOutputFile.h b/llvm/include/llvm/Support/ToolOutputFile.h --- a/llvm/include/llvm/Support/ToolOutputFile.h +++ b/llvm/include/llvm/Support/ToolOutputFile.h @@ -15,6 +15,7 @@ #include "llvm/ADT/Optional.h" #include "llvm/Support/raw_ostream.h" +#include namespace llvm { @@ -43,7 +44,7 @@ /// Storage for the stream, if we're owning our own stream. This is /// intentionally declared after Installer. - Optional OSHolder; + std::optional OSHolder; /// The actual stream to use. raw_fd_ostream *OS; diff --git a/llvm/include/llvm/Support/raw_ostream.h b/llvm/include/llvm/Support/raw_ostream.h --- a/llvm/include/llvm/Support/raw_ostream.h +++ b/llvm/include/llvm/Support/raw_ostream.h @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -442,7 +443,7 @@ bool ShouldClose; bool SupportsSeeking = false; bool IsRegularFile = false; - mutable Optional HasColors; + mutable std::optional HasColors; #ifdef _WIN32 /// True if this fd refers to a Windows console device. Mintty and other diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h --- a/llvm/include/llvm/Target/CGPassBuilderOption.h +++ b/llvm/include/llvm/Target/CGPassBuilderOption.h @@ -17,6 +17,7 @@ #include "llvm/ADT/Optional.h" #include "llvm/ADT/StringRef.h" #include "llvm/Target/TargetOptions.h" +#include namespace llvm { @@ -27,8 +28,8 @@ // Not one-on-one but mostly corresponding to commandline options in // TargetPassConfig.cpp. struct CGPassBuilderOption { - Optional OptimizeRegAlloc; - Optional EnableIPRA; + std::optional OptimizeRegAlloc; + std::optional EnableIPRA; bool DebugPM = false; bool DisableVerify = false; bool EnableImplicitNullChecks = false; @@ -50,11 +51,11 @@ RunOutliner EnableMachineOutliner = RunOutliner::TargetDefault; RegAllocType RegAlloc = RegAllocType::Default; CFLAAType UseCFLAA = CFLAAType::None; - Optional EnableGlobalISelAbort; + std::optional EnableGlobalISelAbort; - Optional VerifyMachineCode; - Optional EnableFastISelOption; - Optional EnableGlobalISelOption; + std::optional VerifyMachineCode; + std::optional EnableFastISelOption; + std::optional EnableGlobalISelOption; }; CGPassBuilderOption getCGPassBuilderOption(); diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td --- a/llvm/include/llvm/Target/Target.td +++ b/llvm/include/llvm/Target/Target.td @@ -1479,6 +1479,16 @@ // to matching the parsed instruction, so to allow more detailed error // messages. bit ReportMultipleNearMisses = false; + + // OperandParserMethod - If non-empty, this is the name of a custom + // member function of the AsmParser class to call for every instruction + // operand to be parsed. + string OperandParserMethod = ""; + + // CallCustomParserForAllOperands - Set to true if the custom parser + // method shall be called for all operands as opposed to only those + // that have their own specified custom parsers. + bit CallCustomParserForAllOperands = false; } def DefaultAsmParser : AsmParser; diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -46,7 +46,6 @@ class MCSymbol; class raw_pwrite_stream; class PassBuilder; -class PassManagerBuilder; struct PerFunctionMIParsingState; class SMDiagnostic; class SMRange; @@ -347,12 +346,7 @@ /// corresponding to \p F. virtual TargetTransformInfo getTargetTransformInfo(const Function &F) const; - /// Allow the target to modify the pass manager, e.g. by calling - /// PassManagerBuilder::addExtension. - virtual void adjustPassManager(PassManagerBuilder &) {} - - /// Allow the target to modify the pass pipeline with New Pass Manager - /// (similar to adjustPassManager for Legacy Pass manager). + /// Allow the target to modify the pass pipeline. virtual void registerPassBuilderCallbacks(PassBuilder &) {} /// Allow the target to register alias analyses with the AAManager for use diff --git a/llvm/include/llvm/Transforms/IPO/Attributor.h b/llvm/include/llvm/Transforms/IPO/Attributor.h --- a/llvm/include/llvm/Transforms/IPO/Attributor.h +++ b/llvm/include/llvm/Transforms/IPO/Attributor.h @@ -129,6 +129,7 @@ #include "llvm/Transforms/Utils/CallGraphUpdater.h" #include +#include namespace llvm { @@ -1347,7 +1348,7 @@ DenseSet *Allowed = nullptr; /// Maximum number of iterations to run until fixpoint. - Optional MaxFixpointIterations = None; + std::optional MaxFixpointIterations = None; /// A callback function that returns an ORE object from a Function pointer. ///{ @@ -3142,11 +3143,6 @@ : public IRAttribute { AAReturnedValues(const IRPosition &IRP, Attributor &A) : IRAttribute(IRP) {} - /// Return an assumed unique return value if a single candidate is found. If - /// there cannot be one, return a nullptr. If it is not clear yet, return the - /// Optional::NoneType. - Optional getAssumedUniqueReturnValue(Attributor &A) const; - /// Check \p Pred on all returned values. /// /// This method will evaluate \p Pred on returned values and return diff --git a/llvm/include/llvm/Transforms/Scalar/GVN.h b/llvm/include/llvm/Transforms/Scalar/GVN.h --- a/llvm/include/llvm/Transforms/Scalar/GVN.h +++ b/llvm/include/llvm/Transforms/Scalar/GVN.h @@ -26,6 +26,7 @@ #include "llvm/Support/Allocator.h" #include "llvm/Support/Compiler.h" #include +#include #include #include @@ -71,11 +72,11 @@ /// Intended use is to create a default object, modify parameters with /// additional setters and then pass it to GVN. struct GVNOptions { - Optional AllowPRE = None; - Optional AllowLoadPRE = None; - Optional AllowLoadInLoopPRE = None; - Optional AllowLoadPRESplitBackedge = None; - Optional AllowMemDep = None; + std::optional AllowPRE = None; + std::optional AllowLoadPRE = None; + std::optional AllowLoadInLoopPRE = None; + std::optional AllowLoadPRESplitBackedge = None; + std::optional AllowMemDep = None; GVNOptions() = default; diff --git a/llvm/include/llvm/Transforms/Utils/LoopPeel.h b/llvm/include/llvm/Transforms/Utils/LoopPeel.h --- a/llvm/include/llvm/Transforms/Utils/LoopPeel.h +++ b/llvm/include/llvm/Transforms/Utils/LoopPeel.h @@ -18,7 +18,7 @@ namespace llvm { -bool canPeel(Loop *L); +bool canPeel(const Loop *L); bool peelLoop(Loop *L, unsigned PeelCount, LoopInfo *LI, ScalarEvolution *SE, DominatorTree &DT, AssumptionCache *AC, bool PreserveLCSSA); diff --git a/llvm/lib/Analysis/BasicAliasAnalysis.cpp b/llvm/lib/Analysis/BasicAliasAnalysis.cpp --- a/llvm/lib/Analysis/BasicAliasAnalysis.cpp +++ b/llvm/lib/Analysis/BasicAliasAnalysis.cpp @@ -58,6 +58,7 @@ #include #include #include +#include #include #define DEBUG_TYPE "basicaa" @@ -484,7 +485,7 @@ SmallVector VarIndices; // Are all operations inbounds GEPs or non-indexing operations? // (None iff expression doesn't involve any geps) - Optional InBounds; + std::optional InBounds; void dump() const { print(dbgs()); @@ -1182,7 +1183,7 @@ // Try to determine the range of values for VarIndex such that // VarIndex <= -MinAbsVarIndex || MinAbsVarIndex <= VarIndex. - Optional MinAbsVarIndex; + std::optional MinAbsVarIndex; if (DecompGEP1.VarIndices.size() == 1) { // VarIndex = Scale*V. const VariableGEPIndex &Var = DecompGEP1.VarIndices[0]; @@ -1306,7 +1307,7 @@ // on corresponding edges. if (const PHINode *PN2 = dyn_cast(V2)) if (PN2->getParent() == PN->getParent()) { - Optional Alias; + std::optional Alias; for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { AliasResult ThisAlias = AAQI.AAR.alias( MemoryLocation(PN->getIncomingValue(i), PNSize), diff --git a/llvm/lib/Analysis/CFLAndersAliasAnalysis.cpp b/llvm/lib/Analysis/CFLAndersAliasAnalysis.cpp --- a/llvm/lib/Analysis/CFLAndersAliasAnalysis.cpp +++ b/llvm/lib/Analysis/CFLAndersAliasAnalysis.cpp @@ -81,6 +81,7 @@ #include #include #include +#include #include #include @@ -351,12 +352,12 @@ return (Set & StateSet(WriteOnlyStateMask)).any(); } -static Optional +static std::optional getInterfaceValue(InstantiatedValue IValue, const SmallVectorImpl &RetVals) { auto Val = IValue.Val; - Optional Index; + std::optional Index; if (auto Arg = dyn_cast(Val)) Index = Arg->getArgNo() + 1; else if (is_contained(RetVals, Val)) @@ -625,7 +626,7 @@ } } -static Optional getNodeBelow(const CFLGraph &Graph, +static std::optional getNodeBelow(const CFLGraph &Graph, InstantiatedValue V) { auto NodeBelow = InstantiatedValue{V.Val, V.DerefLevel + 1}; if (Graph.getNode(NodeBelow)) diff --git a/llvm/lib/Analysis/CGSCCPassManager.cpp b/llvm/lib/Analysis/CGSCCPassManager.cpp --- a/llvm/lib/Analysis/CGSCCPassManager.cpp +++ b/llvm/lib/Analysis/CGSCCPassManager.cpp @@ -30,6 +30,7 @@ #include "llvm/Support/raw_ostream.h" #include #include +#include #define DEBUG_TYPE "cgscc" @@ -613,7 +614,7 @@ G->buildRefSCCs(); for (auto &RC : G->postorder_ref_sccs()) for (auto &C : RC) { - Optional InnerPA; + std::optional InnerPA; // Check to see whether the preserved set needs to be adjusted based on // module-level analysis invalidation triggering deferred invalidation @@ -716,7 +717,7 @@ // necessary. for (LazyCallGraph::Node &N : C) { Function &F = N.getFunction(); - Optional FunctionPA; + std::optional FunctionPA; // Check to see whether the preserved set needs to be pruned based on // SCC-level analysis invalidation that triggers deferred invalidation diff --git a/llvm/lib/Analysis/CallGraphSCCPass.cpp b/llvm/lib/Analysis/CallGraphSCCPass.cpp --- a/llvm/lib/Analysis/CallGraphSCCPass.cpp +++ b/llvm/lib/Analysis/CallGraphSCCPass.cpp @@ -751,7 +751,8 @@ bool CallGraphSCCPass::skipSCC(CallGraphSCC &SCC) const { OptPassGate &Gate = SCC.getCallGraph().getModule().getContext().getOptPassGate(); - return Gate.isEnabled() && !Gate.shouldRunPass(this, getDescription(SCC)); + return Gate.isEnabled() && + !Gate.shouldRunPass(this->getPassName(), getDescription(SCC)); } char DummyCGSCCPass::ID = 0; diff --git a/llvm/lib/Analysis/DomTreeUpdater.cpp b/llvm/lib/Analysis/DomTreeUpdater.cpp --- a/llvm/lib/Analysis/DomTreeUpdater.cpp +++ b/llvm/lib/Analysis/DomTreeUpdater.cpp @@ -106,8 +106,7 @@ // validateDeleteBB() removes all instructions of DelBB and adds an // UnreachableInst as its terminator. So we check whether the BasicBlock to // delete only has an UnreachableInst inside. - assert(BB->getInstList().size() == 1 && - isa(BB->getTerminator()) && + assert(BB->size() == 1 && isa(BB->getTerminator()) && "DelBB has been modified while awaiting deletion."); BB->removeFromParent(); eraseDelBBNode(BB); @@ -221,7 +220,7 @@ // Replace used instructions with an arbitrary value (poison). if (!I.use_empty()) I.replaceAllUsesWith(PoisonValue::get(I.getType())); - DelBB->getInstList().pop_back(); + DelBB->back().eraseFromParent(); } // Make sure DelBB has a valid terminator instruction. As long as DelBB is a // Child of Function F it must contain valid IR. diff --git a/llvm/lib/Analysis/ImportedFunctionsInliningStatistics.cpp b/llvm/lib/Analysis/ImportedFunctionsInliningStatistics.cpp --- a/llvm/lib/Analysis/ImportedFunctionsInliningStatistics.cpp +++ b/llvm/lib/Analysis/ImportedFunctionsInliningStatistics.cpp @@ -23,6 +23,7 @@ using namespace llvm; +namespace llvm { cl::opt InlinerFunctionImportStats( "inliner-function-import-stats", cl::init(InlinerFunctionImportStatsOpts::No), @@ -31,6 +32,7 @@ clEnumValN(InlinerFunctionImportStatsOpts::Verbose, "verbose", "printing of statistics for each inlined function")), cl::Hidden, cl::desc("Enable inliner stats for imported functions")); +} ImportedFunctionsInliningStatistics::InlineGraphNode & ImportedFunctionsInliningStatistics::createInlineGraphNode(const Function &F) { diff --git a/llvm/lib/Analysis/InlineAdvisor.cpp b/llvm/lib/Analysis/InlineAdvisor.cpp --- a/llvm/lib/Analysis/InlineAdvisor.cpp +++ b/llvm/lib/Analysis/InlineAdvisor.cpp @@ -61,7 +61,9 @@ cl::desc("If true, annotate inline advisor remarks " "with LTO and pass information.")); +namespace llvm { extern cl::opt InlinerFunctionImportStats; +} namespace { using namespace llvm::ore; @@ -217,7 +219,7 @@ Advisor = llvm::getDevelopmentModeAdvisor(M, MAM, [&FAM, Params](CallBase &CB) { auto OIC = getDefaultInlineAdvice(CB, FAM, Params); - return OIC.hasValue(); + return OIC.has_value(); }); #endif break; diff --git a/llvm/lib/Analysis/InlineCost.cpp b/llvm/lib/Analysis/InlineCost.cpp --- a/llvm/lib/Analysis/InlineCost.cpp +++ b/llvm/lib/Analysis/InlineCost.cpp @@ -44,6 +44,7 @@ #include "llvm/Support/raw_ostream.h" #include #include +#include using namespace llvm; @@ -489,7 +490,7 @@ InlineResult analyze(); - Optional getSimplifiedValue(Instruction *I) { + std::optional getSimplifiedValue(Instruction *I) { if (SimplifiedValues.find(I) != SimplifiedValues.end()) return SimplifiedValues[I]; return None; @@ -814,7 +815,7 @@ // Determine whether we should inline the given call site, taking into account // both the size cost and the cycle savings. Return None if we don't have // suficient profiling information to determine. - Optional costBenefitAnalysis() { + std::optional costBenefitAnalysis() { if (!CostBenefitAnalysisEnabled) return None; diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -741,6 +741,42 @@ return Res; } +/// Test if there is a dominating equivalence condition for the +/// two operands. If there is, try to reduce the binary operation +/// between the two operands. +/// Example: Op0 - Op1 --> 0 when Op0 == Op1 +static Value *simplifyByDomEq(unsigned Opcode, Value *Op0, Value *Op1, + const SimplifyQuery &Q, unsigned MaxRecurse) { + // Recursive run it can not get any benefit + if (MaxRecurse != RecursionLimit) + return nullptr; + + Optional Imp = + isImpliedByDomCondition(CmpInst::ICMP_EQ, Op0, Op1, Q.CxtI, Q.DL); + if (Imp && *Imp) { + Type *Ty = Op0->getType(); + switch (Opcode) { + case Instruction::Sub: + case Instruction::Xor: + case Instruction::URem: + case Instruction::SRem: + return Constant::getNullValue(Ty); + + case Instruction::SDiv: + case Instruction::UDiv: + return ConstantInt::get(Ty, 1); + + case Instruction::And: + case Instruction::Or: + // Could be either one - choose Op1 since that's more likely a constant. + return Op1; + default: + break; + } + } + return nullptr; +} + /// Given operands for a Sub, see if we can fold the result. /// If not, this returns null. static Value *simplifySubInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW, @@ -872,6 +908,9 @@ // "A-B" and "A-C" thus gains nothing, but costs compile time. Similarly // for threading over phi nodes. + if (Value *V = simplifyByDomEq(Instruction::Sub, Op0, Op1, Q, MaxRecurse)) + return V; + return nullptr; } @@ -947,7 +986,8 @@ /// Check for common or similar folds of integer division or integer remainder. /// This applies to all 4 opcodes (sdiv/udiv/srem/urem). static Value *simplifyDivRem(Instruction::BinaryOps Opcode, Value *Op0, - Value *Op1, const SimplifyQuery &Q) { + Value *Op1, const SimplifyQuery &Q, + unsigned MaxRecurse) { bool IsDiv = (Opcode == Instruction::SDiv || Opcode == Instruction::UDiv); bool IsSigned = (Opcode == Instruction::SDiv || Opcode == Instruction::SRem); @@ -1022,6 +1062,9 @@ } } + if (Value *V = simplifyByDomEq(Opcode, Op0, Op1, Q, MaxRecurse)) + return V; + return nullptr; } @@ -1103,7 +1146,7 @@ if (Constant *C = foldOrCommuteConstant(Opcode, Op0, Op1, Q)) return C; - if (Value *V = simplifyDivRem(Opcode, Op0, Op1, Q)) + if (Value *V = simplifyDivRem(Opcode, Op0, Op1, Q, MaxRecurse)) return V; bool IsSigned = Opcode == Instruction::SDiv; @@ -1147,7 +1190,7 @@ if (Constant *C = foldOrCommuteConstant(Opcode, Op0, Op1, Q)) return C; - if (Value *V = simplifyDivRem(Opcode, Op0, Op1, Q)) + if (Value *V = simplifyDivRem(Opcode, Op0, Op1, Q, MaxRecurse)) return V; // (X % Y) % Y -> X % Y @@ -2191,6 +2234,9 @@ } } + if (Value *V = simplifyByDomEq(Instruction::And, Op0, Op1, Q, MaxRecurse)) + return V; + return nullptr; } @@ -2450,6 +2496,9 @@ } } + if (Value *V = simplifyByDomEq(Instruction::Or, Op0, Op1, Q, MaxRecurse)) + return V; + return nullptr; } @@ -2525,6 +2574,9 @@ // "A^B" and "A^C" thus gains nothing, but costs compile time. Similarly // for threading over phi nodes. + if (Value *V = simplifyByDomEq(Instruction::Xor, Op0, Op1, Q, MaxRecurse)) + return V; + return nullptr; } diff --git a/llvm/lib/Analysis/LazyValueInfo.cpp b/llvm/lib/Analysis/LazyValueInfo.cpp --- a/llvm/lib/Analysis/LazyValueInfo.cpp +++ b/llvm/lib/Analysis/LazyValueInfo.cpp @@ -38,6 +38,7 @@ #include "llvm/Support/FormattedStream.h" #include "llvm/Support/KnownBits.h" #include "llvm/Support/raw_ostream.h" +#include using namespace llvm; using namespace PatternMatch; @@ -164,7 +165,7 @@ SmallDenseSet, 4> OverDefined; // None indicates that the nonnull pointers for this basic block // block have not been computed yet. - Optional NonNullPointers; + std::optional NonNullPointers; }; /// Cached information per basic block. @@ -1296,7 +1297,7 @@ /// Compute the value of Val on the edge BBFrom -> BBTo. Returns false if /// Val is not constrained on the edge. Result is unspecified if return value /// is false. -static Optional getEdgeValueLocal(Value *Val, +static std::optional getEdgeValueLocal(Value *Val, BasicBlock *BBFrom, BasicBlock *BBTo) { // TODO: Handle more complex conditionals. If (v == 0 || v2 < 1) is false, we diff --git a/llvm/lib/Analysis/LoopAnalysisManager.cpp b/llvm/lib/Analysis/LoopAnalysisManager.cpp --- a/llvm/lib/Analysis/LoopAnalysisManager.cpp +++ b/llvm/lib/Analysis/LoopAnalysisManager.cpp @@ -13,6 +13,7 @@ #include "llvm/Analysis/ScalarEvolution.h" #include "llvm/IR/Dominators.h" #include "llvm/IR/PassManagerImpl.h" +#include using namespace llvm; @@ -90,7 +91,7 @@ // cache and so we walk the preorder list in reverse to form a valid // postorder. for (Loop *L : reverse(PreOrderLoops)) { - Optional InnerPA; + std::optional InnerPA; // Check to see whether the preserved set needs to be adjusted based on // function-level analysis invalidation triggering deferred invalidation diff --git a/llvm/lib/Analysis/LoopNestAnalysis.cpp b/llvm/lib/Analysis/LoopNestAnalysis.cpp --- a/llvm/lib/Analysis/LoopNestAnalysis.cpp +++ b/llvm/lib/Analysis/LoopNestAnalysis.cpp @@ -295,7 +295,7 @@ return *From; auto IsEmpty = [](const BasicBlock *BB) { - return (BB->getInstList().size() == 1); + return (BB->size() == 1); }; // Visited is used to avoid running into an infinite loop. @@ -379,7 +379,7 @@ // Ensure the inner loop guard successor is empty before skipping // blocks. - if (Succ->getInstList().size() == 1) { + if (Succ->size() == 1) { PotentialInnerPreHeader = &LoopNest::skipEmptyBlockUntil(Succ, InnerLoopPreHeader); PotentialOuterLatch = diff --git a/llvm/lib/Analysis/LoopPass.cpp b/llvm/lib/Analysis/LoopPass.cpp --- a/llvm/lib/Analysis/LoopPass.cpp +++ b/llvm/lib/Analysis/LoopPass.cpp @@ -373,7 +373,8 @@ return false; // Check the opt bisect limit. OptPassGate &Gate = F->getContext().getOptPassGate(); - if (Gate.isEnabled() && !Gate.shouldRunPass(this, getDescription(*L))) + if (Gate.isEnabled() && + !Gate.shouldRunPass(this->getPassName(), getDescription(*L))) return true; // Check for the OptimizeNone attribute. if (F->hasOptNone()) { diff --git a/llvm/lib/Analysis/MemoryLocation.cpp b/llvm/lib/Analysis/MemoryLocation.cpp --- a/llvm/lib/Analysis/MemoryLocation.cpp +++ b/llvm/lib/Analysis/MemoryLocation.cpp @@ -14,6 +14,7 @@ #include "llvm/IR/IntrinsicsARM.h" #include "llvm/IR/Module.h" #include "llvm/IR/Type.h" +#include using namespace llvm; void LocationSize::print(raw_ostream &OS) const { @@ -126,7 +127,7 @@ return None; Value *UsedV = nullptr; - Optional UsedIdx; + std::optional UsedIdx; for (unsigned i = 0; i < CB->arg_size(); i++) { if (!CB->getArgOperand(i)->getType()->isPointerTy()) continue; @@ -253,12 +254,17 @@ assert((ArgIdx == 0 || ArgIdx == 1) && "Invalid argument index for str function"); return MemoryLocation::getAfter(Arg, AATags); - case LibFunc_memset_chk: { + case LibFunc_memset_chk: assert(ArgIdx == 0 && "Invalid argument index for memset_chk"); + LLVM_FALLTHROUGH; + case LibFunc_memcpy_chk: { + assert((ArgIdx == 0 || ArgIdx == 1) && + "Invalid argument index for memcpy_chk"); LocationSize Size = LocationSize::afterPointer(); if (const auto *Len = dyn_cast(Call->getArgOperand(2))) { - // memset_chk writes at most Len bytes. It may write less, if Len - // exceeds the specified max size and aborts. + // memset_chk writes at most Len bytes, memcpy_chk reads/writes at most + // Len bytes. They may read/write less, if Len exceeds the specified max + // size and aborts. Size = LocationSize::upperBound(Len->getZExtValue()); } return MemoryLocation(Arg, Size, AATags); diff --git a/llvm/lib/Analysis/ModelUnderTrainingRunner.cpp b/llvm/lib/Analysis/ModelUnderTrainingRunner.cpp --- a/llvm/lib/Analysis/ModelUnderTrainingRunner.cpp +++ b/llvm/lib/Analysis/ModelUnderTrainingRunner.cpp @@ -40,7 +40,7 @@ void *ModelUnderTrainingRunner::evaluateUntyped() { LastEvaluationResult = Evaluator->evaluate(); - if (!LastEvaluationResult.hasValue()) { + if (!LastEvaluationResult.has_value()) { Ctx.emitError("Error evaluating model."); return nullptr; } diff --git a/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp b/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp --- a/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp +++ b/llvm/lib/Analysis/ModuleSummaryAnalysis.cpp @@ -63,9 +63,12 @@ // Option to force edges cold which will block importing when the // -import-cold-multiplier is set to 0. Useful for debugging. +namespace llvm { FunctionSummary::ForceSummaryHotnessType ForceSummaryEdgesCold = FunctionSummary::FSHT_None; -cl::opt FSEC( +} // namespace llvm + +static cl::opt FSEC( "force-summary-edges-cold", cl::Hidden, cl::location(ForceSummaryEdgesCold), cl::desc("Force all edges in the function summary to cold"), cl::values(clEnumValN(FunctionSummary::FSHT_None, "none", "None."), @@ -73,10 +76,9 @@ "all-non-critical", "All non-critical edges."), clEnumValN(FunctionSummary::FSHT_All, "all", "All edges."))); -cl::opt ModuleSummaryDotFile( - "module-summary-dot-file", cl::init(""), cl::Hidden, - cl::value_desc("filename"), - cl::desc("File to emit dot graph of new summary into.")); +static cl::opt ModuleSummaryDotFile( + "module-summary-dot-file", cl::Hidden, cl::value_desc("filename"), + cl::desc("File to emit dot graph of new summary into")); // Walk through the operands of a given User via worklist iteration and populate // the set of GlobalValue references encountered. Invoked either on an diff --git a/llvm/lib/Analysis/ProfileSummaryInfo.cpp b/llvm/lib/Analysis/ProfileSummaryInfo.cpp --- a/llvm/lib/Analysis/ProfileSummaryInfo.cpp +++ b/llvm/lib/Analysis/ProfileSummaryInfo.cpp @@ -23,12 +23,14 @@ using namespace llvm; // Knobs for profile summary based thresholds. +namespace llvm { extern cl::opt ProfileSummaryCutoffHot; extern cl::opt ProfileSummaryCutoffCold; extern cl::opt ProfileSummaryHugeWorkingSetSizeThreshold; extern cl::opt ProfileSummaryLargeWorkingSetSizeThreshold; extern cl::opt ProfileSummaryHotCount; extern cl::opt ProfileSummaryColdCount; +} // namespace llvm static cl::opt PartialProfile( "partial-profile", cl::Hidden, cl::init(false), diff --git a/llvm/lib/Analysis/RegionPass.cpp b/llvm/lib/Analysis/RegionPass.cpp --- a/llvm/lib/Analysis/RegionPass.cpp +++ b/llvm/lib/Analysis/RegionPass.cpp @@ -283,7 +283,8 @@ bool RegionPass::skipRegion(Region &R) const { Function &F = *R.getEntry()->getParent(); OptPassGate &Gate = F.getContext().getOptPassGate(); - if (Gate.isEnabled() && !Gate.shouldRunPass(this, getDescription(R))) + if (Gate.isEnabled() && + !Gate.shouldRunPass(this->getPassName(), getDescription(R))) return true; if (F.hasOptNone()) { diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp --- a/llvm/lib/Analysis/ScalarEvolution.cpp +++ b/llvm/lib/Analysis/ScalarEvolution.cpp @@ -126,6 +126,7 @@ #include #include #include +#include #include #include #include @@ -713,7 +714,7 @@ // more efficient. // If the max analysis depth was reached, return None, assuming we do not know // if they are equivalent for sure. -static Optional +static std::optional CompareSCEVComplexity(EquivalenceClasses &EqCacheSCEV, EquivalenceClasses &EqCacheValue, const LoopInfo *const LI, const SCEV *LHS, @@ -5126,7 +5127,7 @@ } // end anonymous namespace /// Try to map \p V into a BinaryOp, and return \c None on failure. -static Optional MatchBinaryOp(Value *V, DominatorTree &DT) { +static std::optional MatchBinaryOp(Value *V, DominatorTree &DT) { auto *Op = dyn_cast(V); if (!Op) return None; @@ -6954,7 +6955,7 @@ explicit SelectPattern(ScalarEvolution &SE, unsigned BitWidth, const SCEV *S) { - Optional CastOp; + std::optional CastOp; APInt Offset(BitWidth, 0); assert(SE.getTypeSizeInBits(S->getType()) == BitWidth && @@ -8158,7 +8159,7 @@ SmallVector ExitingBlocks; L->getExitingBlocks(ExitingBlocks); - Optional Res; + std::optional Res; for (auto *ExitingBB : ExitingBlocks) { unsigned Multiple = getSmallConstantTripMultiple(L, ExitingBB); if (!Res) @@ -8552,15 +8553,18 @@ const BasicBlock *ExitingBlock, ScalarEvolution *SE) const { for (const auto &ENT : ExitNotTaken) if (ENT.ExitingBlock == ExitingBlock && ENT.hasAlwaysTruePredicate()) - return ENT.MaxNotTaken; + return ENT.ConstantMaxNotTaken; return SE->getCouldNotCompute(); } const SCEV *ScalarEvolution::BackedgeTakenInfo::getSymbolicMax( const BasicBlock *ExitingBlock, ScalarEvolution *SE) const { - // FIXME: Need to implement this. Return exact for now. - return getExact(ExitingBlock, SE); + for (const auto &ENT : ExitNotTaken) + if (ENT.ExitingBlock == ExitingBlock && ENT.hasAlwaysTruePredicate()) + return ENT.SymbolicMaxNotTaken; + + return SE->getCouldNotCompute(); } /// getConstantMax - Get the constant max backedge taken count for the loop. @@ -8600,40 +8604,43 @@ } ScalarEvolution::ExitLimit::ExitLimit( - const SCEV *E, const SCEV *M, bool MaxOrZero, + const SCEV *E, const SCEV *ConstantMaxNotTaken, bool MaxOrZero, ArrayRef *> PredSetList) - : ExactNotTaken(E), MaxNotTaken(M), MaxOrZero(MaxOrZero) { + : ExactNotTaken(E), ConstantMaxNotTaken(ConstantMaxNotTaken), + MaxOrZero(MaxOrZero) { // If we prove the max count is zero, so is the symbolic bound. This happens // in practice due to differences in a) how context sensitive we've chosen // to be and b) how we reason about bounds implied by UB. - if (MaxNotTaken->isZero()) - ExactNotTaken = MaxNotTaken; + if (ConstantMaxNotTaken->isZero()) + ExactNotTaken = ConstantMaxNotTaken; + + // FIXME: For now, SymbolicMaxNotTaken is either exact (if available) or + // constant max. In the future, we are planning to make it more powerful. + if (isa(ExactNotTaken)) + SymbolicMaxNotTaken = ConstantMaxNotTaken; + else + SymbolicMaxNotTaken = ExactNotTaken; assert((isa(ExactNotTaken) || - !isa(MaxNotTaken)) && + !isa(ConstantMaxNotTaken)) && "Exact is not allowed to be less precise than Max"); - assert((isa(MaxNotTaken) || - isa(MaxNotTaken)) && + assert((isa(ConstantMaxNotTaken) || + isa(ConstantMaxNotTaken)) && "No point in having a non-constant max backedge taken count!"); for (const auto *PredSet : PredSetList) for (const auto *P : *PredSet) addPredicate(P); assert((isa(E) || !E->getType()->isPointerTy()) && "Backedge count should be int"); - assert((isa(M) || !M->getType()->isPointerTy()) && + assert((isa(ConstantMaxNotTaken) || + !ConstantMaxNotTaken->getType()->isPointerTy()) && "Max backedge count should be int"); } ScalarEvolution::ExitLimit::ExitLimit( - const SCEV *E, const SCEV *M, bool MaxOrZero, + const SCEV *E, const SCEV *ConstantMaxNotTaken, bool MaxOrZero, const SmallPtrSetImpl &PredSet) - : ExitLimit(E, M, MaxOrZero, {&PredSet}) { -} - -ScalarEvolution::ExitLimit::ExitLimit(const SCEV *E, const SCEV *M, - bool MaxOrZero) - : ExitLimit(E, M, MaxOrZero, None) { -} + : ExitLimit(E, ConstantMaxNotTaken, MaxOrZero, { &PredSet }) {} /// Allocate memory for BackedgeTakenInfo and copy the not-taken count of each /// computable exit into a persistent ExitNotTakenInfo array. @@ -8644,14 +8651,15 @@ using EdgeExitInfo = ScalarEvolution::BackedgeTakenInfo::EdgeExitInfo; ExitNotTaken.reserve(ExitCounts.size()); - std::transform( - ExitCounts.begin(), ExitCounts.end(), std::back_inserter(ExitNotTaken), - [&](const EdgeExitInfo &EEI) { + std::transform(ExitCounts.begin(), ExitCounts.end(), + std::back_inserter(ExitNotTaken), + [&](const EdgeExitInfo &EEI) { BasicBlock *ExitBB = EEI.first; const ExitLimit &EL = EEI.second; - return ExitNotTakenInfo(ExitBB, EL.ExactNotTaken, EL.MaxNotTaken, + return ExitNotTakenInfo(ExitBB, EL.ExactNotTaken, + EL.ConstantMaxNotTaken, EL.SymbolicMaxNotTaken, EL.Predicates); - }); + }); assert((isa(ConstantMax) || isa(ConstantMax)) && "No point in having a non-constant max backedge taken count!"); @@ -8709,25 +8717,26 @@ // // If the exit dominates the loop latch, it is a LoopMustExit otherwise it // is a LoopMayExit. If any computable LoopMustExit is found, then - // MaxBECount is the minimum EL.MaxNotTaken of computable + // MaxBECount is the minimum EL.ConstantMaxNotTaken of computable // LoopMustExits. Otherwise, MaxBECount is conservatively the maximum - // EL.MaxNotTaken, where CouldNotCompute is considered greater than any - // computable EL.MaxNotTaken. - if (EL.MaxNotTaken != getCouldNotCompute() && Latch && + // EL.ConstantMaxNotTaken, where CouldNotCompute is considered greater than + // any + // computable EL.ConstantMaxNotTaken. + if (EL.ConstantMaxNotTaken != getCouldNotCompute() && Latch && DT.dominates(ExitBB, Latch)) { if (!MustExitMaxBECount) { - MustExitMaxBECount = EL.MaxNotTaken; + MustExitMaxBECount = EL.ConstantMaxNotTaken; MustExitMaxOrZero = EL.MaxOrZero; } else { - MustExitMaxBECount = - getUMinFromMismatchedTypes(MustExitMaxBECount, EL.MaxNotTaken); + MustExitMaxBECount = getUMinFromMismatchedTypes(MustExitMaxBECount, + EL.ConstantMaxNotTaken); } } else if (MayExitMaxBECount != getCouldNotCompute()) { - if (!MayExitMaxBECount || EL.MaxNotTaken == getCouldNotCompute()) - MayExitMaxBECount = EL.MaxNotTaken; + if (!MayExitMaxBECount || EL.ConstantMaxNotTaken == getCouldNotCompute()) + MayExitMaxBECount = EL.ConstantMaxNotTaken; else { - MayExitMaxBECount = - getUMaxFromMismatchedTypes(MayExitMaxBECount, EL.MaxNotTaken); + MayExitMaxBECount = getUMaxFromMismatchedTypes(MayExitMaxBECount, + EL.ConstantMaxNotTaken); } } } @@ -8738,7 +8747,8 @@ bool MaxOrZero = (MustExitMaxOrZero && ExitingBlocks.size() == 1); // Remember which SCEVs are used in exit limits for invalidation purposes. - // We only care about non-constant SCEVs here, so we can ignore EL.MaxNotTaken + // We only care about non-constant SCEVs here, so we can ignore + // EL.ConstantMaxNotTaken // and MaxBECount, which must be SCEVConstant. for (const auto &Pair : ExitCounts) if (!isa(Pair.second.ExactNotTaken)) @@ -8945,12 +8955,13 @@ EL0.ExactNotTaken, EL1.ExactNotTaken, /*Sequential=*/!isa(ExitCond)); } - if (EL0.MaxNotTaken == getCouldNotCompute()) - MaxBECount = EL1.MaxNotTaken; - else if (EL1.MaxNotTaken == getCouldNotCompute()) - MaxBECount = EL0.MaxNotTaken; + if (EL0.ConstantMaxNotTaken == getCouldNotCompute()) + MaxBECount = EL1.ConstantMaxNotTaken; + else if (EL1.ConstantMaxNotTaken == getCouldNotCompute()) + MaxBECount = EL0.ConstantMaxNotTaken; else - MaxBECount = getUMinFromMismatchedTypes(EL0.MaxNotTaken, EL1.MaxNotTaken); + MaxBECount = getUMinFromMismatchedTypes(EL0.ConstantMaxNotTaken, + EL1.ConstantMaxNotTaken); } else { // Both conditions must be same at the same time for the loop to exit. // For now, be conservative. @@ -8961,8 +8972,8 @@ // There are cases (e.g. PR26207) where computeExitLimitFromCond is able // to be more aggressive when computing BECount than when computing // MaxBECount. In these cases it is possible for EL0.ExactNotTaken and - // EL1.ExactNotTaken to match, but for EL0.MaxNotTaken and EL1.MaxNotTaken - // to not. + // EL1.ExactNotTaken to match, but for EL0.ConstantMaxNotTaken and + // EL1.ConstantMaxNotTaken to not. if (isa(MaxBECount) && !isa(BECount)) MaxBECount = getConstant(getUnsignedRangeMax(BECount)); @@ -9200,7 +9211,7 @@ // above) in PNOut and the opcode of the shift operation in OpCodeOut. auto MatchShiftRecurrence = [&](Value *V, PHINode *&PNOut, Instruction::BinaryOps &OpCodeOut) { - Optional PostShiftOpCode; + std::optional PostShiftOpCode; { Instruction::BinaryOps OpC; @@ -9997,7 +10008,7 @@ /// coefficients. /// This function returns None if the addrec coefficients are not compile- /// time constants. -static Optional> +static std::optional> GetQuadraticEquation(const SCEVAddRecExpr *AddRec) { assert(AddRec->getNumOperands() == 3 && "This is not a quadratic chrec!"); const SCEVConstant *LC = dyn_cast(AddRec->getOperand(0)); @@ -13365,12 +13376,13 @@ L->getHeader()->printAsOperand(OS, /*PrintType=*/false); OS << ": "; - if (!isa(SE->getConstantMaxBackedgeTakenCount(L))) { - OS << "max backedge-taken count is " << *SE->getConstantMaxBackedgeTakenCount(L); + auto *ConstantBTC = SE->getConstantMaxBackedgeTakenCount(L); + if (!isa(ConstantBTC)) { + OS << "constant max backedge-taken count is " << *ConstantBTC; if (SE->isBackedgeTakenCountMaxOrZero(L)) OS << ", actual taken count either this or zero."; } else { - OS << "Unpredictable max backedge-taken count. "; + OS << "Unpredictable constant max backedge-taken count. "; } OS << "\n" @@ -13378,6 +13390,27 @@ L->getHeader()->printAsOperand(OS, /*PrintType=*/false); OS << ": "; + auto *SymbolicBTC = SE->getSymbolicMaxBackedgeTakenCount(L); + if (!isa(SymbolicBTC)) { + OS << "symbolic max backedge-taken count is " << *SymbolicBTC; + if (SE->isBackedgeTakenCountMaxOrZero(L)) + OS << ", actual taken count either this or zero."; + } else { + OS << "Unpredictable symbolic max backedge-taken count. "; + } + + OS << "\n"; + if (ExitingBlocks.size() > 1) + for (BasicBlock *ExitingBlock : ExitingBlocks) { + OS << " symbolic max exit count for " << ExitingBlock->getName() << ": " + << *SE->getExitCount(L, ExitingBlock, ScalarEvolution::SymbolicMaximum) + << "\n"; + } + + OS << "Loop "; + L->getHeader()->printAsOperand(OS, /*PrintType=*/false); + OS << ": "; + SmallVector Preds; auto PBT = SE->getPredicatedBackedgeTakenCount(L, Preds); if (!isa(PBT)) { @@ -14730,9 +14763,6 @@ for (BasicBlock *ExitingBB : ExitingBlocks) { const SCEV *ExitCount = getExitCount(L, ExitingBB, ScalarEvolution::SymbolicMaximum); - if (isa(ExitCount)) - ExitCount = getExitCount(L, ExitingBB, - ScalarEvolution::ConstantMaximum); if (!isa(ExitCount)) { assert(DT.dominates(ExitingBB, L->getLoopLatch()) && "We should only have known counts for exiting blocks that " diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -74,6 +74,7 @@ #include #include #include +#include #include using namespace llvm; @@ -1016,7 +1017,7 @@ // If we know the shifter operand is nonzero, we can sometimes infer more // known bits. However this is expensive to compute, so be lazy about it and // only compute it when absolutely necessary. - Optional ShifterOperandIsNonZero; + std::optional ShifterOperandIsNonZero; // Early exit if we can't constrain any well-defined shift amount. if (!(ShiftAmtKZ & (PowerOf2Ceil(BitWidth) - 1)) && @@ -2745,7 +2746,7 @@ /// every input value to exactly one output value. This is equivalent to /// saying that Op1 and Op2 are equal exactly when the specified pair of /// operands are equal, (except that Op1 and Op2 may be poison more often.) -static Optional> +static std::optional> getInvertibleOperands(const Operator *Op1, const Operator *Op2) { if (Op1->getOpcode() != Op2->getOpcode()) @@ -7322,7 +7323,7 @@ return CR; } -static Optional +static std::optional getOffsetFromIndex(const GEPOperator *GEP, unsigned Idx, const DataLayout &DL) { // Skip over the first indices. gep_type_iterator GTI = gep_type_begin(GEP); diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -80,6 +80,7 @@ #include #include #include +#include #include #include #include @@ -593,7 +594,7 @@ /// ValueList must be destroyed before Alloc. BumpPtrAllocator Alloc; BitcodeReaderValueList ValueList; - Optional MDLoader; + std::optional MDLoader; std::vector ComdatList; DenseSet ImplicitComdatObjects; SmallVector InstructionList; @@ -3205,7 +3206,7 @@ PointeeType = getTypeByID(Record[OpNum++]); bool InBounds = false; - Optional InRangeIndex; + std::optional InRangeIndex; if (BitCode == bitc::CST_CODE_CE_GEP_WITH_INRANGE_INDEX) { uint64_t Op = Record[OpNum++]; InBounds = Op & 1; diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp --- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -96,7 +96,9 @@ "write-relbf-to-summary", cl::Hidden, cl::init(false), cl::desc("Write relative block frequency to function summary ")); +namespace llvm { extern FunctionSummary::ForceSummaryHotnessType ForceSummaryEdgesCold; +} namespace { diff --git a/llvm/lib/CodeGen/AsmPrinter/AIXException.cpp b/llvm/lib/CodeGen/AsmPrinter/AIXException.cpp --- a/llvm/lib/CodeGen/AsmPrinter/AIXException.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AIXException.cpp @@ -69,7 +69,7 @@ const unsigned PointerSize = DL.getPointerSize(); // Add necessary paddings in 64 bit mode. - Asm->OutStreamer->emitValueToAlignment(PointerSize); + Asm->OutStreamer->emitValueToAlignment(Align(PointerSize)); // LSDA location. Asm->OutStreamer->emitValue(MCSymbolRefExpr::create(LSDA, Asm->OutContext), diff --git a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp --- a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp @@ -531,7 +531,7 @@ emitOffsets(EntryPool); emitAbbrevs(); emitData(); - Asm->OutStreamer->emitValueToAlignment(4, 0); + Asm->OutStreamer->emitValueToAlignment(Align(4), 0); Asm->OutStreamer->emitLabel(ContributionEnd); } diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -119,6 +119,7 @@ #include #include #include +#include #include #include #include @@ -743,10 +744,7 @@ if (GVKind.isCommon()) { if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it. // .comm _foo, 42, 4 - const bool SupportsAlignment = - getObjFileLowering().getCommDirectiveSupportsAlignment(); - OutStreamer->emitCommonSymbol(GVSym, Size, - SupportsAlignment ? Alignment.value() : 0); + OutStreamer->emitCommonSymbol(GVSym, Size, Alignment.value()); return; } @@ -787,10 +785,7 @@ // .local _foo OutStreamer->emitSymbolAttribute(GVSym, MCSA_Local); // .comm _foo, 42, 4 - const bool SupportsAlignment = - getObjFileLowering().getCommDirectiveSupportsAlignment(); - OutStreamer->emitCommonSymbol(GVSym, Size, - SupportsAlignment ? Alignment.value() : 0); + OutStreamer->emitCommonSymbol(GVSym, Size, Alignment.value()); return; } @@ -1191,7 +1186,7 @@ case MachineOperand::MO_Register: case MachineOperand::MO_FrameIndex: { Register Reg; - Optional Offset; + std::optional Offset; if (Op.isReg()) { Reg = Op.getReg(); } else { @@ -2045,7 +2040,7 @@ remarks::RemarkSerializer &RemarkSerializer = RS.getSerializer(); - Optional> Filename; + std::optional> Filename; if (Optional FilenameRef = RS.getFilename()) { Filename = *FilenameRef; sys::fs::make_absolute(*Filename); @@ -2835,9 +2830,9 @@ STI = &getSubtargetInfo(); else STI = TM.getMCSubtargetInfo(); - OutStreamer->emitCodeAlignment(Alignment.value(), STI, MaxBytesToEmit); + OutStreamer->emitCodeAlignment(Alignment, STI, MaxBytesToEmit); } else - OutStreamer->emitValueToAlignment(Alignment.value(), 0, 1, MaxBytesToEmit); + OutStreamer->emitValueToAlignment(Alignment, 0, 1, MaxBytesToEmit); } //===----------------------------------------------------------------------===// @@ -3961,7 +3956,8 @@ // pointers. This should work for both 32-bit and 64-bit platforms. if (FnSledIndex) { OutStreamer->switchSection(FnSledIndex); - OutStreamer->emitCodeAlignment(2 * WordSizeBytes, &getSubtargetInfo()); + OutStreamer->emitCodeAlignment(Align(2 * WordSizeBytes), + &getSubtargetInfo()); OutStreamer->emitSymbolValue(SledsStart, WordSizeBytes, false); OutStreamer->emitSymbolValue(SledsEnd, WordSizeBytes, false); OutStreamer->switchSection(PrevSection); diff --git a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp --- a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp @@ -560,7 +560,7 @@ } void CodeViewDebug::emitCodeViewMagicVersion() { - OS.emitValueToAlignment(4); + OS.emitValueToAlignment(Align(4)); OS.AddComment("Debug section magic"); OS.emitInt32(COFF::DEBUG_SECTION_MAGIC); } @@ -754,7 +754,7 @@ // hardcoded to version 0, SHA1. OS.switchSection(Asm->getObjFileLowering().getCOFFGlobalTypeHashesSection()); - OS.emitValueToAlignment(4); + OS.emitValueToAlignment(Align(4)); OS.AddComment("Magic"); OS.emitInt32(COFF::DEBUG_HASHES_SECTION_MAGIC); OS.AddComment("Section Version"); @@ -3109,7 +3109,7 @@ void CodeViewDebug::endCVSubsection(MCSymbol *EndLabel) { OS.emitLabel(EndLabel); // Every subsection must be aligned to a 4-byte boundary. - OS.emitValueToAlignment(4); + OS.emitValueToAlignment(Align(4)); } static StringRef getSymbolName(SymbolKind SymKind) { @@ -3136,7 +3136,7 @@ // an extra copy of every symbol record in LLD. This increases object file // size by less than 1% in the clang build, and is compatible with the Visual // C++ linker. - OS.emitValueToAlignment(4); + OS.emitValueToAlignment(Align(4)); OS.emitLabel(SymEnd); } diff --git a/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp b/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp --- a/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp @@ -26,6 +26,7 @@ #include "llvm/Support/raw_ostream.h" #include #include +#include #include using namespace llvm; @@ -110,7 +111,7 @@ /// range in Ranges. EndMI can be nullptr to indicate that the range is /// unbounded. Assumes Ranges is ordered and disjoint. Returns true and points /// to the first intersecting scope range if one exists. -static Optional::iterator> +static std::optional::iterator> intersects(const MachineInstr *StartMI, const MachineInstr *EndMI, const ArrayRef &Ranges, const InstructionOrdering &Ordering) { diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp --- a/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp @@ -36,6 +36,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include +#include #include #include @@ -203,7 +204,7 @@ DIE *VariableDIE, const DIGlobalVariable *GV, ArrayRef GlobalExprs) { bool addToAccelTable = false; DIELoc *Loc = nullptr; - Optional NVPTXAddressSpace; + std::optional NVPTXAddressSpace; std::unique_ptr DwarfExpr; for (const auto &GE : GlobalExprs) { const GlobalVariable *Global = GE.Var; @@ -340,7 +341,7 @@ // correctly interpret address space of the variable address. const unsigned NVPTX_ADDR_global_space = 5; addUInt(*VariableDIE, dwarf::DW_AT_address_class, dwarf::DW_FORM_data1, - NVPTXAddressSpace ? *NVPTXAddressSpace : NVPTX_ADDR_global_space); + NVPTXAddressSpace.value_or(NVPTX_ADDR_global_space)); } if (Loc) addBlock(*VariableDIE, dwarf::DW_AT_location, DwarfExpr->finalize()); @@ -847,7 +848,7 @@ if (!DV.hasFrameIndexExprs()) return VariableDie; - Optional NVPTXAddressSpace; + std::optional NVPTXAddressSpace; DIELoc *Loc = new (DIEValueAllocator) DIELoc; DIEDwarfExpression DwarfExpr(*Asm, *this, *Loc); for (const auto &Fragment : DV.getFrameIndexExprs()) { @@ -895,7 +896,7 @@ // correctly interpret address space of the variable address. const unsigned NVPTX_ADDR_local_space = 6; addUInt(*VariableDie, dwarf::DW_AT_address_class, dwarf::DW_FORM_data1, - NVPTXAddressSpace ? *NVPTXAddressSpace : NVPTX_ADDR_local_space); + NVPTXAddressSpace.value_or(NVPTX_ADDR_local_space)); } addBlock(*VariableDie, dwarf::DW_AT_location, DwarfExpr.finalize()); if (DwarfExpr.TagOffset) diff --git a/llvm/lib/CodeGen/AsmPrinter/WinException.cpp b/llvm/lib/CodeGen/AsmPrinter/WinException.cpp --- a/llvm/lib/CodeGen/AsmPrinter/WinException.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/WinException.cpp @@ -736,7 +736,7 @@ // EHFlags & 1 -> Synchronous exceptions only, no async exceptions. // EHFlags & 2 -> ??? // EHFlags & 4 -> The function is noexcept(true), unwinding can't continue. - OS.emitValueToAlignment(4); + OS.emitValueToAlignment(Align(4)); OS.emitLabel(FuncInfoXData); AddComment("MagicNumber"); @@ -1010,7 +1010,7 @@ // Emit the __ehtable label that we use for llvm.x86.seh.lsda. MCSymbol *LSDALabel = Asm->OutContext.getOrCreateLSDASymbol(FLinkageName); - OS.emitValueToAlignment(4); + OS.emitValueToAlignment(Align(4)); OS.emitLabel(LSDALabel); const auto *Per = cast(F.getPersonalityFn()->stripPointerCasts()); diff --git a/llvm/lib/CodeGen/AtomicExpandPass.cpp b/llvm/lib/CodeGen/AtomicExpandPass.cpp --- a/llvm/lib/CodeGen/AtomicExpandPass.cpp +++ b/llvm/lib/CodeGen/AtomicExpandPass.cpp @@ -1030,7 +1030,7 @@ Builder.SetInsertPoint(CI); Value *FinalOldVal = extractMaskedValue(Builder, OldVal, PMV); - Value *Res = UndefValue::get(CI->getType()); + Value *Res = PoisonValue::get(CI->getType()); Res = Builder.CreateInsertValue(Res, FinalOldVal, 0); Res = Builder.CreateInsertValue(Res, Success, 1); @@ -1094,7 +1094,7 @@ Builder, CI, PMV.AlignedAddr, CmpVal_Shifted, NewVal_Shifted, PMV.Mask, CI->getMergedOrdering()); Value *FinalOldVal = extractMaskedValue(Builder, OldVal, PMV); - Value *Res = UndefValue::get(CI->getType()); + Value *Res = PoisonValue::get(CI->getType()); Res = Builder.CreateInsertValue(Res, FinalOldVal, 0); Value *Success = Builder.CreateICmpEQ( CmpVal_Shifted, Builder.CreateAnd(OldVal, PMV.Mask), "Success"); @@ -1186,7 +1186,7 @@ OldVal = Builder.CreateIntToPtr(OldVal, CI->getCompareOperand()->getType()); - Value *Res = UndefValue::get(CI->getType()); + Value *Res = PoisonValue::get(CI->getType()); Res = Builder.CreateInsertValue(Res, OldVal, 0); Res = Builder.CreateInsertValue(Res, Succ, 1); @@ -1430,7 +1430,7 @@ // Some use of the full struct return that we don't understand has happened, // so we've got to reconstruct it properly. Value *Res; - Res = Builder.CreateInsertValue(UndefValue::get(CI->getType()), Loaded, 0); + Res = Builder.CreateInsertValue(PoisonValue::get(CI->getType()), Loaded, 0); Res = Builder.CreateInsertValue(Res, Success, 1); CI->replaceAllUsesWith(Res); @@ -1923,7 +1923,7 @@ // The final result from the CAS is {load of 'expected' alloca, bool result // from call} Type *FinalResultTy = I->getType(); - Value *V = UndefValue::get(FinalResultTy); + Value *V = PoisonValue::get(FinalResultTy); Value *ExpectedOut = Builder.CreateAlignedLoad( CASExpected->getType(), AllocaCASExpected, AllocaAlignment); Builder.CreateLifetimeEnd(AllocaCASExpected_i8, SizeVal64); diff --git a/llvm/lib/CodeGen/BasicBlockSections.cpp b/llvm/lib/CodeGen/BasicBlockSections.cpp --- a/llvm/lib/CodeGen/BasicBlockSections.cpp +++ b/llvm/lib/CodeGen/BasicBlockSections.cpp @@ -79,6 +79,7 @@ #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/InitializePasses.h" #include "llvm/Target/TargetMachine.h" +#include using namespace llvm; @@ -208,7 +209,7 @@ // This variable stores the section ID of the cluster containing eh_pads (if // all eh_pads are one cluster). If more than one cluster contain eh_pads, we // set it equal to ExceptionSectionID. - Optional EHPadsSectionID; + std::optional EHPadsSectionID; for (auto &MBB : MF) { // With the 'all' option, every basic block is placed in a unique section. diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -98,6 +98,7 @@ #include #include #include +#include #include #include @@ -1433,7 +1434,7 @@ /// If given \p PN is an inductive variable with value IVInc coming from the /// backedge, and on each iteration it gets increased by Step, return pair /// . Otherwise, return None. -static Optional> +static std::optional> getIVIncrement(const PHINode *PN, const LoopInfo *LI) { const Loop *L = LI->getLoopFor(PN->getParent()); if (!L || L->getHeader() != PN->getParent() || !L->getLoopLatch()) @@ -4016,7 +4017,7 @@ // If this is an add recurrence with a constant step, return the increment // instruction and the canonicalized step. auto GetConstantStep = - [this](const Value *V) -> Optional> { + [this](const Value *V) -> std::optional> { auto *PN = dyn_cast(V); if (!PN) return None; diff --git a/llvm/lib/CodeGen/ExpandMemCmp.cpp b/llvm/lib/CodeGen/ExpandMemCmp.cpp --- a/llvm/lib/CodeGen/ExpandMemCmp.cpp +++ b/llvm/lib/CodeGen/ExpandMemCmp.cpp @@ -28,6 +28,7 @@ #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Utils/SizeOpts.h" +#include using namespace llvm; @@ -877,7 +878,7 @@ const TargetTransformInfo *TTI, const TargetLowering *TL, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI, DominatorTree *DT) { - Optional DTU; + std::optional DTU; if (DT) DTU.emplace(DT, DomTreeUpdater::UpdateStrategy::Lazy); diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -33,6 +33,7 @@ #include "llvm/Support/MathExtras.h" #include "llvm/Target/TargetMachine.h" #include +#include #include #define DEBUG_TYPE "gi-combiner" @@ -3274,7 +3275,7 @@ /// e.g. x[i] << 24 /// /// \returns The load instruction and the byte offset it is moved into. -static Optional> +static std::optional> matchLoadAndBytePosition(Register Reg, unsigned MemSizeInBits, const MachineRegisterInfo &MRI) { assert(MRI.hasOneNonDBGUse(Reg) && @@ -3554,8 +3555,9 @@ /// value found. /// On match, returns the start byte offset of the \p SrcVal that is being /// stored. -static Optional getTruncStoreByteOffset(GStore &Store, Register &SrcVal, - MachineRegisterInfo &MRI) { +static std::optional +getTruncStoreByteOffset(GStore &Store, Register &SrcVal, + MachineRegisterInfo &MRI) { Register TruncVal; if (!mi_match(Store.getValueReg(), MRI, m_GTrunc(m_Reg(TruncVal)))) return None; diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -34,6 +34,7 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetMachine.h" #include +#include #define DEBUG_TYPE "legalizer" @@ -1842,7 +1843,7 @@ LLT WideTy) { unsigned Opcode; unsigned ExtOpcode; - Optional CarryIn; + std::optional CarryIn; switch (MI.getOpcode()) { default: llvm_unreachable("Unexpected opcode!"); diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp --- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp @@ -34,6 +34,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Transforms/Utils/SizeOpts.h" #include +#include #define DEBUG_TYPE "globalisel-utils" @@ -792,7 +793,7 @@ llvm::ConstantFoldCTLZ(Register Src, const MachineRegisterInfo &MRI) { LLT Ty = MRI.getType(Src); SmallVector FoldedCTLZs; - auto tryFoldScalar = [&](Register R) -> Optional { + auto tryFoldScalar = [&](Register R) -> std::optional { auto MaybeCst = getIConstantVRegVal(R, MRI); if (!MaybeCst) return None; diff --git a/llvm/lib/CodeGen/IndirectBrExpandPass.cpp b/llvm/lib/CodeGen/IndirectBrExpandPass.cpp --- a/llvm/lib/CodeGen/IndirectBrExpandPass.cpp +++ b/llvm/lib/CodeGen/IndirectBrExpandPass.cpp @@ -40,6 +40,7 @@ #include "llvm/Pass.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetMachine.h" +#include using namespace llvm; @@ -90,7 +91,7 @@ return false; TLI = STI.getTargetLowering(); - Optional DTU; + std::optional DTU; if (auto *DTWP = getAnalysisIfAvailable()) DTU.emplace(DTWP->getDomTree(), DomTreeUpdater::UpdateStrategy::Lazy); diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp --- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp +++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp @@ -127,6 +127,7 @@ #include "InstrRefBasedImpl.h" #include "LiveDebugValues.h" +#include using namespace llvm; using namespace LiveDebugValues; @@ -740,7 +741,7 @@ // Examine the remaining variable locations: if we can find the same value // again, we can recover the location. - Optional NewLoc; + std::optional NewLoc; for (auto Loc : MTracker->locations()) if (Loc.Value == OldValue) NewLoc = Loc.Idx; @@ -1560,7 +1561,7 @@ // Pick a location for the machine value number, if such a location exists. // (This information could be stored in TransferTracker to make it faster). - Optional FoundLoc; + std::optional FoundLoc; for (auto Location : MTracker->locations()) { LocIdx CurL = Location.Idx; ValueIDNum ID = MTracker->readMLoc(CurL); @@ -1913,7 +1914,7 @@ // continue past this store. for (unsigned SlotIdx = 0; SlotIdx < MTracker->NumSlotIdxes; ++SlotIdx) { unsigned SpillID = MTracker->getSpillIDWithIdx(*Loc, SlotIdx); - Optional MLoc = MTracker->getSpillMLoc(SpillID); + std::optional MLoc = MTracker->getSpillMLoc(SpillID); if (!MLoc) continue; diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp --- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp +++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp @@ -33,7 +33,7 @@ const char *End = nullptr; public: - Cursor(NoneType) {} + Cursor(std::nullopt_t) {} explicit Cursor(StringRef Str) { Ptr = Str.data(); diff --git a/llvm/lib/CodeGen/MachineDebugify.cpp b/llvm/lib/CodeGen/MachineDebugify.cpp --- a/llvm/lib/CodeGen/MachineDebugify.cpp +++ b/llvm/lib/CodeGen/MachineDebugify.cpp @@ -153,10 +153,15 @@ NMD->setOperand(Idx, MDNode::get(Ctx, ValueAsMetadata::getConstant( ConstantInt::get(Int32Ty, N)))); }; + auto getDebugifyOperand = [&](unsigned Idx) { + return mdconst::extract(NMD->getOperand(Idx)->getOperand(0)) + ->getZExtValue(); + }; // Set number of lines. setDebugifyOperand(0, NextLine - 1); // Set number of variables. - setDebugifyOperand(1, VarSet.size()); + auto OldNumVars = getDebugifyOperand(1); + setDebugifyOperand(1, OldNumVars + VarSet.size()); } return true; @@ -166,6 +171,9 @@ /// legacy module pass manager. struct DebugifyMachineModule : public ModulePass { bool runOnModule(Module &M) override { + // We will insert new debugify metadata, so erasing the old one. + assert(!M.getNamedMetadata("llvm.mir.debugify") && + "llvm.mir.debugify metadata already exists! Strip it first"); MachineModuleInfo &MMI = getAnalysis().getMMI(); return applyDebugifyMetadata( diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp --- a/llvm/lib/CodeGen/MachineOperand.cpp +++ b/llvm/lib/CodeGen/MachineOperand.cpp @@ -29,6 +29,7 @@ #include "llvm/MC/MCDwarf.h" #include "llvm/Target/TargetIntrinsicInfo.h" #include "llvm/Target/TargetMachine.h" +#include using namespace llvm; @@ -470,7 +471,7 @@ printLLVMNameWithoutPrefix(OS, BB.getName()); return; } - Optional Slot; + std::optional Slot; if (const Function *F = BB.getParent()) { if (F == MST.getCurrentFunction()) { Slot = MST.getLocalSlot(&BB); diff --git a/llvm/lib/CodeGen/SafeStack.cpp b/llvm/lib/CodeGen/SafeStack.cpp --- a/llvm/lib/CodeGen/SafeStack.cpp +++ b/llvm/lib/CodeGen/SafeStack.cpp @@ -67,6 +67,7 @@ #include #include #include +#include #include #include @@ -896,7 +897,7 @@ DominatorTree *DT; bool ShouldPreserveDominatorTree; - Optional LazilyComputedDomTree; + std::optional LazilyComputedDomTree; // Do we already have a DominatorTree avaliable from the previous pass? // Note that we should *NOT* require it, to avoid the case where we end up diff --git a/llvm/lib/CodeGen/SelectOptimize.cpp b/llvm/lib/CodeGen/SelectOptimize.cpp --- a/llvm/lib/CodeGen/SelectOptimize.cpp +++ b/llvm/lib/CodeGen/SelectOptimize.cpp @@ -515,12 +515,27 @@ } } +static bool isSpecialSelect(SelectInst *SI) { + using namespace llvm::PatternMatch; + + // If the select is a logical-and/logical-or then it is better treated as a + // and/or by the backend. + if (match(SI, m_CombineOr(m_LogicalAnd(m_Value(), m_Value()), + m_LogicalOr(m_Value(), m_Value())))) + return true; + + return false; +} + void SelectOptimize::collectSelectGroups(BasicBlock &BB, SelectGroups &SIGroups) { BasicBlock::iterator BBIt = BB.begin(); while (BBIt != BB.end()) { Instruction *I = &*BBIt++; if (SelectInst *SI = dyn_cast(I)) { + if (isSpecialSelect(SI)) + continue; + SelectGroup SIGroup; SIGroup.push_back(SI); while (BBIt != BB.end()) { diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -69,6 +69,7 @@ #include #include #include +#include #include #include #include @@ -7914,7 +7915,7 @@ /// *ExtractVectorElement static const Optional calculateByteProvider(SDValue Op, unsigned Index, unsigned Depth, - Optional VectorIndex, + std::optional VectorIndex, unsigned StartingIndex = 0) { // Typical i64 by i8 pattern requires recursion up to 8 calls depth @@ -8160,7 +8161,7 @@ SmallVector OffsetMap(NumStores, INT64_MAX); int64_t FirstOffset = INT64_MAX; StoreSDNode *FirstStore = nullptr; - Optional Base; + std::optional Base; for (auto *Store : Stores) { // All the stores store different parts of the CombinedValue. A truncate is // required to get the partial value. @@ -8342,7 +8343,7 @@ : littleEndianByteAt(LoadByteWidth, P.ByteOffset); }; - Optional Base; + std::optional Base; SDValue Chain; SmallPtrSet Loads; @@ -18308,7 +18309,7 @@ unsigned SizeInBits = NumStores * ElementSizeBits; unsigned NumMemElts = MemVT.isVector() ? MemVT.getVectorNumElements() : 1; - Optional Flags; + std::optional Flags; AAMDNodes AAInfo; for (unsigned I = 0; I != NumStores; ++I) { StoreSDNode *St = cast(StoreNodes[I].MemNode); diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -105,6 +105,7 @@ #include #include #include +#include #include using namespace llvm; @@ -1228,7 +1229,7 @@ if (Arg && FuncInfo.getArgumentFrameIndex(Arg) != INT_MAX) return true; - Optional Op; + std::optional Op; if (Register Reg = lookUpRegForValue(Address)) Op = MachineOperand::CreateReg(Reg, false); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -735,7 +735,7 @@ assert(IntermediateVT.isScalableVector() == ValueVT.isScalableVector() && "Mixing scalable and fixed vectors when copying in parts"); - Optional DestEltCnt; + std::optional DestEltCnt; if (IntermediateVT.isVector()) DestEltCnt = IntermediateVT.getVectorElementCount() * NumIntermediates; @@ -5633,7 +5633,7 @@ } bool IsIndirect = false; - Optional Op; + std::optional Op; // Some arguments' frame index is recorded during argument lowering. int FI = FuncInfo.getArgumentFrameIndex(Arg); if (FI != std::numeric_limits::max()) @@ -7393,7 +7393,7 @@ } static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin) { - Optional ResOPC; + std::optional ResOPC; switch (VPIntrin.getIntrinsicID()) { #define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \ case Intrinsic::VPID: \ @@ -9147,7 +9147,7 @@ SDValue AsmOp = InOperandVal; if (isFunction(InOperandVal)) { - auto *GA = dyn_cast(InOperandVal); + auto *GA = cast(InOperandVal); ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Func, 1); AsmOp = DAG.getTargetGlobalAddress(GA->getGlobal(), getCurSDLoc(), InOperandVal.getValueType(), diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -102,6 +102,7 @@ #include #include #include +#include #include #include #include @@ -2263,7 +2264,7 @@ // Cache arguments that will be moved to the end in the target node. SDValue Chain = *It++; - Optional Glue; + std::optional Glue; if (It->getValueType() == MVT::Glue) Glue = *It++; SDValue RegMask = *It++; diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2677,7 +2677,9 @@ [[fallthrough]]; } default: - if (Op.getOpcode() >= ISD::BUILTIN_OP_END) { + // We also ask the target about intrinsics (which could be specific to it). + if (Op.getOpcode() >= ISD::BUILTIN_OP_END || + Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN) { if (SimplifyDemandedBitsForTargetNode(Op, DemandedBits, DemandedElts, Known, TLO, Depth)) return true; diff --git a/llvm/lib/CodeGen/ShadowStackGCLowering.cpp b/llvm/lib/CodeGen/ShadowStackGCLowering.cpp --- a/llvm/lib/CodeGen/ShadowStackGCLowering.cpp +++ b/llvm/lib/CodeGen/ShadowStackGCLowering.cpp @@ -39,6 +39,7 @@ #include "llvm/Support/Casting.h" #include "llvm/Transforms/Utils/EscapeEnumerator.h" #include +#include #include #include #include @@ -305,7 +306,7 @@ if (Roots.empty()) return false; - Optional DTU; + std::optional DTU; if (auto *DTWP = getAnalysisIfAvailable()) DTU.emplace(DTWP->getDomTree(), DomTreeUpdater::UpdateStrategy::Lazy); diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp --- a/llvm/lib/CodeGen/StackMaps.cpp +++ b/llvm/lib/CodeGen/StackMaps.cpp @@ -688,7 +688,7 @@ } // Emit alignment to 8 byte. - OS.emitValueToAlignment(8); + OS.emitValueToAlignment(Align(8)); // Num live-out registers and padding to align to 4 byte. OS.emitInt16(0); @@ -700,7 +700,7 @@ OS.emitIntValue(LO.Size, 1); } // Emit alignment to 8 byte. - OS.emitValueToAlignment(8); + OS.emitValueToAlignment(Align(8)); } } diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp --- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp +++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp @@ -434,7 +434,7 @@ ELF::SHT_PROGBITS, Flags, 0); unsigned Size = DL.getPointerSize(); Streamer.switchSection(Sec); - Streamer.emitValueToAlignment(DL.getPointerABIAlignment(0).value()); + Streamer.emitValueToAlignment(DL.getPointerABIAlignment(0)); Streamer.emitSymbolAttribute(Label, MCSA_ELF_TypeObject); const MCExpr *E = MCConstantExpr::create(Size, getContext()); Streamer.emitELFSize(Label, E); diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -49,6 +49,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils.h" #include +#include #include using namespace llvm; @@ -548,7 +549,7 @@ PIC.registerShouldRunOptionalPassCallback( [=, EnableCurrent = StartBefore.empty() && StartAfter.empty(), - EnableNext = Optional(), StartBeforeCount = 0u, + EnableNext = std::optional(), StartBeforeCount = 0u, StartAfterCount = 0u, StopBeforeCount = 0u, StopAfterCount = 0u](StringRef P, Any) mutable { bool StartBeforePass = !StartBefore.empty() && P.contains(StartBefore); diff --git a/llvm/lib/DebugInfo/CodeView/TypeStreamMerger.cpp b/llvm/lib/DebugInfo/CodeView/TypeStreamMerger.cpp --- a/llvm/lib/DebugInfo/CodeView/TypeStreamMerger.cpp +++ b/llvm/lib/DebugInfo/CodeView/TypeStreamMerger.cpp @@ -17,6 +17,7 @@ #include "llvm/DebugInfo/CodeView/TypeRecord.h" #include "llvm/DebugInfo/CodeView/TypeRecordHelpers.h" #include "llvm/Support/Error.h" +#include using namespace llvm; using namespace llvm::codeview; @@ -167,7 +168,7 @@ Expected shouldRemapType(const CVType &Type); - Optional LastError; + std::optional LastError; bool UseGlobalHashes = false; diff --git a/llvm/lib/DebugInfo/DWARF/DWARFContext.cpp b/llvm/lib/DebugInfo/DWARF/DWARFContext.cpp --- a/llvm/lib/DebugInfo/DWARF/DWARFContext.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFContext.cpp @@ -1877,12 +1877,12 @@ S.IsNameUnique = false; } - Optional find(const DWARFSection &S, - uint64_t Pos) const override { + std::optional find(const DWARFSection &S, + uint64_t Pos) const override { auto &Sec = static_cast(S); RelocAddrMap::const_iterator AI = Sec.Relocs.find(Pos); if (AI == Sec.Relocs.end()) - return None; + return std::nullopt; return AI->second; } diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDataExtractor.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDataExtractor.cpp --- a/llvm/lib/DebugInfo/DWARF/DWARFDataExtractor.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFDataExtractor.cpp @@ -54,7 +54,7 @@ return getUnsigned(Off, Size, Err); ErrorAsOutParameter ErrAsOut(Err); - Optional E = Obj->find(*Section, *Off); + std::optional E = Obj->find(*Section, *Off); uint64_t LocData = getUnsigned(Off, Size, Err); if (!E || (Err && *Err)) return LocData; diff --git a/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp b/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp --- a/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFDebugFrame.cpp @@ -25,6 +25,7 @@ #include #include #include +#include using namespace llvm; using namespace dwarf; @@ -1091,7 +1092,7 @@ Optional Personality; Optional PersonalityEncoding; if (IsEH) { - Optional AugmentationLength; + std::optional AugmentationLength; uint64_t StartAugmentationOffset; uint64_t EndAugmentationOffset; diff --git a/llvm/lib/DebugInfo/DWARF/DWARFFormValue.cpp b/llvm/lib/DebugInfo/DWARF/DWARFFormValue.cpp --- a/llvm/lib/DebugInfo/DWARF/DWARFFormValue.cpp +++ b/llvm/lib/DebugInfo/DWARF/DWARFFormValue.cpp @@ -25,6 +25,7 @@ #include #include #include +#include using namespace llvm; using namespace dwarf; @@ -635,7 +636,7 @@ return make_error("Unsupported form for string attribute", inconvertibleErrorCode()); uint64_t Offset = Value.uval; - Optional Index; + std::optional Index; if (Form == DW_FORM_GNU_str_index || Form == DW_FORM_strx || Form == DW_FORM_strx1 || Form == DW_FORM_strx2 || Form == DW_FORM_strx3 || Form == DW_FORM_strx4) { diff --git a/llvm/lib/DebugInfo/GSYM/DwarfTransformer.cpp b/llvm/lib/DebugInfo/GSYM/DwarfTransformer.cpp --- a/llvm/lib/DebugInfo/GSYM/DwarfTransformer.cpp +++ b/llvm/lib/DebugInfo/GSYM/DwarfTransformer.cpp @@ -21,6 +21,7 @@ #include "llvm/DebugInfo/GSYM/GsymCreator.h" #include "llvm/DebugInfo/GSYM/GsymReader.h" #include "llvm/DebugInfo/GSYM/InlineInfo.h" +#include using namespace llvm; using namespace gsym; @@ -128,9 +129,8 @@ /// .debug_info. If we create a qualified name string in this function by /// combining multiple strings in the DWARF string table or info, we will make /// a copy of the string when we add it to the string table. -static Optional getQualifiedNameIndex(DWARFDie &Die, - uint64_t Language, - GsymCreator &Gsym) { +static std::optional +getQualifiedNameIndex(DWARFDie &Die, uint64_t Language, GsymCreator &Gsym) { // If the dwarf has mangled name, use mangled name if (auto LinkageName = dwarf::toString(Die.findRecursively({dwarf::DW_AT_MIPS_linkage_name, diff --git a/llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp b/llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp --- a/llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp +++ b/llvm/lib/DebugInfo/GSYM/FunctionInfo.cpp @@ -12,6 +12,7 @@ #include "llvm/DebugInfo/GSYM/LineTable.h" #include "llvm/DebugInfo/GSYM/InlineInfo.h" #include "llvm/Support/DataExtractor.h" +#include using namespace llvm; using namespace gsym; @@ -178,8 +179,8 @@ Offset - 4); LR.FuncName = GR.getString(NameOffset); bool Done = false; - Optional LineEntry; - Optional InlineInfoData; + std::optional LineEntry; + std::optional InlineInfoData; while (!Done) { if (!Data.isValidOffsetForDataOfSize(Offset, 8)) return createStringError(std::errc::io_error, diff --git a/llvm/lib/DebugInfo/PDB/Native/NativeTypeEnum.cpp b/llvm/lib/DebugInfo/PDB/Native/NativeTypeEnum.cpp --- a/llvm/lib/DebugInfo/PDB/Native/NativeTypeEnum.cpp +++ b/llvm/lib/DebugInfo/PDB/Native/NativeTypeEnum.cpp @@ -20,6 +20,7 @@ #include "llvm/DebugInfo/PDB/PDBSymbolTypeBuiltin.h" #include +#include using namespace llvm; using namespace llvm::codeview; @@ -54,7 +55,7 @@ NativeSession &Session; const NativeTypeEnum &ClassParent; std::vector Enumerators; - Optional ContinuationIndex; + std::optional ContinuationIndex; uint32_t Index = 0; }; } // namespace diff --git a/llvm/lib/DebugInfo/Symbolize/MarkupFilter.cpp b/llvm/lib/DebugInfo/Symbolize/MarkupFilter.cpp --- a/llvm/lib/DebugInfo/Symbolize/MarkupFilter.cpp +++ b/llvm/lib/DebugInfo/Symbolize/MarkupFilter.cpp @@ -31,6 +31,7 @@ #include "llvm/Support/FormatVariadic.h" #include "llvm/Support/WithColor.h" #include "llvm/Support/raw_ostream.h" +#include using namespace llvm; using namespace llvm::symbolize; @@ -411,7 +412,7 @@ OS.changeColor(raw_ostream::Colors::SAVEDCOLOR, Bold); return true; } - auto SGRColor = StringSwitch>(Node.Text) + auto SGRColor = StringSwitch>(Node.Text) .Case("\033[30m", raw_ostream::Colors::BLACK) .Case("\033[31m", raw_ostream::Colors::RED) .Case("\033[32m", raw_ostream::Colors::GREEN) diff --git a/llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp b/llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp --- a/llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp +++ b/llvm/lib/ExecutionEngine/JITLink/MachOLinkGraphBuilder.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "MachOLinkGraphBuilder.h" +#include #define DEBUG_TYPE "jitlink" @@ -260,7 +261,7 @@ if (Type & MachO::N_STAB) continue; - Optional Name; + std::optional Name; if (NStrX) { if (auto NameOrErr = SymRef.getName()) Name = *NameOrErr; @@ -537,7 +538,7 @@ BlockStart, NSec.Alignment, BlockStart % NSec.Alignment); - Optional LastCanonicalAddr; + std::optional LastCanonicalAddr; auto SymEnd = BlockEnd; while (!BlockSyms.empty()) { auto &NSym = *BlockSyms.back(); diff --git a/llvm/lib/ExecutionEngine/Orc/Core.cpp b/llvm/lib/ExecutionEngine/Orc/Core.cpp --- a/llvm/lib/ExecutionEngine/Orc/Core.cpp +++ b/llvm/lib/ExecutionEngine/Orc/Core.cpp @@ -17,6 +17,7 @@ #include #include +#include #define DEBUG_TYPE "orc" @@ -2243,8 +2244,8 @@ void ExecutionSession::dispatchOutstandingMUs() { LLVM_DEBUG(dbgs() << "Dispatching MaterializationUnits...\n"); while (true) { - Optional, - std::unique_ptr>> + std::optional, + std::unique_ptr>> JMU; { diff --git a/llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp b/llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp --- a/llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp +++ b/llvm/lib/ExecutionEngine/Orc/ELFNixPlatform.cpp @@ -16,6 +16,7 @@ #include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" #include "llvm/Support/BinaryByteStream.h" #include "llvm/Support/Debug.h" +#include #define DEBUG_TYPE "orc" @@ -850,7 +851,7 @@ auto *TLSInfoEntrySection = G.findSectionByName("$__TLSINFO"); if (TLSInfoEntrySection) { - Optional Key; + std::optional Key; { std::lock_guard Lock(MP.PlatformMutex); auto I = MP.JITDylibToPThreadKey.find(&JD); diff --git a/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp b/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp --- a/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp +++ b/llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp @@ -15,6 +15,7 @@ #include "llvm/ExecutionEngine/Orc/LookupAndRecordAddrs.h" #include "llvm/Support/BinaryByteStream.h" #include "llvm/Support/Debug.h" +#include #define DEBUG_TYPE "orc" @@ -820,7 +821,7 @@ // Store key in __thread_vars struct fields. if (auto *ThreadDataSec = G.findSectionByName(ThreadVarsSectionName)) { - Optional Key; + std::optional Key; { std::lock_guard Lock(MP.PlatformMutex); auto I = MP.JITDylibToPThreadKey.find(&JD); @@ -945,7 +946,7 @@ } if (!MachOPlatformSecs.empty()) { - Optional HeaderAddr; + std::optional HeaderAddr; { std::lock_guard Lock(MP.PlatformMutex); auto I = MP.JITDylibToHeaderAddr.find(&JD); diff --git a/llvm/lib/ExecutionEngine/Orc/ObjectFileInterface.cpp b/llvm/lib/ExecutionEngine/Orc/ObjectFileInterface.cpp --- a/llvm/lib/ExecutionEngine/Orc/ObjectFileInterface.cpp +++ b/llvm/lib/ExecutionEngine/Orc/ObjectFileInterface.cpp @@ -15,6 +15,7 @@ #include "llvm/Object/MachO.h" #include "llvm/Object/ObjectFile.h" #include "llvm/Support/Debug.h" +#include #define DEBUG_TYPE "orc" @@ -151,7 +152,7 @@ getCOFFObjectFileSymbolInfo(ExecutionSession &ES, const object::COFFObjectFile &Obj) { MaterializationUnit::Interface I; - std::vector> ComdatDefs( + std::vector> ComdatDefs( Obj.getNumberOfSections() + 1); for (auto &Sym : Obj.symbols()) { Expected SymFlagsOrErr = Sym.getFlags(); diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp --- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp +++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp @@ -3963,6 +3963,12 @@ return OS.str().str(); } +std::string +OpenMPIRBuilder::createPlatformSpecificName(ArrayRef Parts) const { + return OpenMPIRBuilder::getNameWithSeparators(Parts, Config.firstSeparator(), + Config.separator()); +} + GlobalVariable * OpenMPIRBuilder::getOrCreateInternalVariable(Type *Ty, const StringRef &Name, unsigned AddressSpace) { diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -82,6 +82,7 @@ #include #include #include +#include #include #include #include @@ -4607,7 +4608,7 @@ void NamedMDNode::print(raw_ostream &ROS, ModuleSlotTracker &MST, bool IsForDebug) const { - Optional LocalST; + std::optional LocalST; SlotTracker *SlotTable; if (auto *ST = MST.getMachine()) SlotTable = ST; diff --git a/llvm/lib/IR/Attributes.cpp b/llvm/lib/IR/Attributes.cpp --- a/llvm/lib/IR/Attributes.cpp +++ b/llvm/lib/IR/Attributes.cpp @@ -600,8 +600,7 @@ static bool hasAttributeProperty(Attribute::AttrKind Kind, AttributeProperty Prop) { unsigned Index = Kind - 1; - assert(Index < sizeof(AttrPropTable) / sizeof(AttrPropTable[0]) && - "Invalid attribute kind"); + assert(Index < std::size(AttrPropTable) && "Invalid attribute kind"); return AttrPropTable[Index] & Prop; } diff --git a/llvm/lib/IR/IntrinsicInst.cpp b/llvm/lib/IR/IntrinsicInst.cpp --- a/llvm/lib/IR/IntrinsicInst.cpp +++ b/llvm/lib/IR/IntrinsicInst.cpp @@ -29,6 +29,7 @@ #include "llvm/IR/Operator.h" #include "llvm/IR/PatternMatch.h" #include "llvm/IR/Statepoint.h" +#include using namespace llvm; @@ -682,7 +683,7 @@ CmpInst::Predicate VPCmpIntrinsic::getPredicate() const { bool IsFP = true; - Optional CCArgIdx; + std::optional CCArgIdx; switch (getIntrinsicID()) { default: break; diff --git a/llvm/lib/IR/LLVMContextImpl.cpp b/llvm/lib/IR/LLVMContextImpl.cpp --- a/llvm/lib/IR/LLVMContextImpl.cpp +++ b/llvm/lib/IR/LLVMContextImpl.cpp @@ -240,7 +240,7 @@ /// singleton OptBisect if not explicitly set. OptPassGate &LLVMContextImpl::getOptPassGate() const { if (!OPG) - OPG = &getOptBisector(); + OPG = &getGlobalPassGate(); return *OPG; } diff --git a/llvm/lib/IR/Module.cpp b/llvm/lib/IR/Module.cpp --- a/llvm/lib/IR/Module.cpp +++ b/llvm/lib/IR/Module.cpp @@ -49,6 +49,7 @@ #include #include #include +#include #include #include @@ -775,7 +776,7 @@ auto *Arr = dyn_cast_or_null(CM->getValue()); if (!Arr) return {}; - auto getVersionComponent = [&](unsigned Index) -> Optional { + auto getVersionComponent = [&](unsigned Index) -> std::optional { if (Index >= Arr->getNumElements()) return None; return (unsigned)Arr->getElementAsInteger(Index); diff --git a/llvm/lib/IR/ModuleSummaryIndex.cpp b/llvm/lib/IR/ModuleSummaryIndex.cpp --- a/llvm/lib/IR/ModuleSummaryIndex.cpp +++ b/llvm/lib/IR/ModuleSummaryIndex.cpp @@ -570,8 +570,7 @@ " [color=brown]; // call (hotness : Hot)", " [style=bold,color=red]; // call (hotness : Critical)"}; - assert(static_cast(TypeOrHotness) < - sizeof(EdgeAttrs) / sizeof(EdgeAttrs[0])); + assert(static_cast(TypeOrHotness) < std::size(EdgeAttrs)); OS << Pfx << NodeId(SrcMod, SrcId) << " -> " << NodeId(DstMod, DstId) << EdgeAttrs[TypeOrHotness] << "\n"; }; diff --git a/llvm/lib/IR/OptBisect.cpp b/llvm/lib/IR/OptBisect.cpp --- a/llvm/lib/IR/OptBisect.cpp +++ b/llvm/lib/IR/OptBisect.cpp @@ -20,10 +20,15 @@ using namespace llvm; +static OptBisect &getOptBisector() { + static OptBisect OptBisector; + return OptBisector; +} + static cl::opt OptBisectLimit("opt-bisect-limit", cl::Hidden, cl::init(OptBisect::Disabled), cl::Optional, cl::cb([](int Limit) { - llvm::getOptBisector().setLimit(Limit); + getOptBisector().setLimit(Limit); }), cl::desc("Maximum optimization to perform")); @@ -34,25 +39,16 @@ << "(" << PassNum << ") " << Name << " on " << TargetDesc << "\n"; } -bool OptBisect::shouldRunPass(const Pass *P, StringRef IRDescription) { - assert(isEnabled()); - - return checkPass(P->getPassName(), IRDescription); -} - -bool OptBisect::checkPass(const StringRef PassName, - const StringRef TargetDesc) { +bool OptBisect::shouldRunPass(const StringRef PassName, + StringRef IRDescription) { assert(isEnabled()); int CurBisectNum = ++LastBisectNum; bool ShouldRun = (BisectLimit == -1 || CurBisectNum <= BisectLimit); - printPassMessage(PassName, CurBisectNum, TargetDesc, ShouldRun); + printPassMessage(PassName, CurBisectNum, IRDescription, ShouldRun); return ShouldRun; } const int OptBisect::Disabled; -OptBisect &llvm::getOptBisector() { - static OptBisect OptBisector; - return OptBisector; -} +OptPassGate &llvm::getGlobalPassGate() { return getOptBisector(); } diff --git a/llvm/lib/IR/Pass.cpp b/llvm/lib/IR/Pass.cpp --- a/llvm/lib/IR/Pass.cpp +++ b/llvm/lib/IR/Pass.cpp @@ -62,7 +62,8 @@ bool ModulePass::skipModule(Module &M) const { OptPassGate &Gate = M.getContext().getOptPassGate(); - return Gate.isEnabled() && !Gate.shouldRunPass(this, getDescription(M)); + return Gate.isEnabled() && + !Gate.shouldRunPass(this->getPassName(), getDescription(M)); } bool Pass::mustPreserveAnalysisID(char &AID) const { @@ -172,7 +173,8 @@ bool FunctionPass::skipFunction(const Function &F) const { OptPassGate &Gate = F.getContext().getOptPassGate(); - if (Gate.isEnabled() && !Gate.shouldRunPass(this, getDescription(F))) + if (Gate.isEnabled() && + !Gate.shouldRunPass(this->getPassName(), getDescription(F))) return true; if (F.hasOptNone()) { diff --git a/llvm/lib/IR/PassManager.cpp b/llvm/lib/IR/PassManager.cpp --- a/llvm/lib/IR/PassManager.cpp +++ b/llvm/lib/IR/PassManager.cpp @@ -10,6 +10,7 @@ #include "llvm/ADT/DenseMapInfo.h" #include "llvm/ADT/Optional.h" #include "llvm/IR/PassManagerImpl.h" +#include using namespace llvm; @@ -54,7 +55,7 @@ // Now walk all the functions to see if any inner analysis invalidation is // necessary. for (Function &F : M) { - Optional FunctionPA; + std::optional FunctionPA; // Check to see whether the preserved set needs to be pruned based on // module-level analysis invalidation that triggers deferred invalidation diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -109,6 +109,7 @@ #include #include #include +#include #include #include @@ -742,7 +743,7 @@ "wrong type for intrinsic global variable", &GV); Check(STy->getNumElements() == 3, "the third field of the element type is mandatory, " - "specify i8* null to migrate from the obsoleted 2-field form"); + "specify ptr null to migrate from the obsoleted 2-field form"); Type *ETy = STy->getTypeAtIndex(2); Type *Int8Ty = Type::getInt8Ty(ETy->getContext()); Check(ETy->isPointerTy() && @@ -887,6 +888,10 @@ // Check that the immediate resolver operand (prior to any bitcasts) has the // correct type. const Type *ResolverTy = GI.getResolver()->getType(); + + Check(isa(Resolver->getFunctionType()->getReturnType()), + "IFunc resolver must return a pointer", &GI); + const Type *ResolverFuncTy = GlobalIFunc::getResolverFunctionType(GI.getValueType()); Check(ResolverTy == ResolverFuncTy->getPointerTo(GI.getAddressSpace()), @@ -6470,7 +6475,7 @@ bool Failed = false; - Optional PrevOffset; + std::optional PrevOffset; unsigned BitWidth = ~0u; // We've already checked that BaseNode is not a degenerate root node with one diff --git a/llvm/lib/InterfaceStub/ELFObjHandler.cpp b/llvm/lib/InterfaceStub/ELFObjHandler.cpp --- a/llvm/lib/InterfaceStub/ELFObjHandler.cpp +++ b/llvm/lib/InterfaceStub/ELFObjHandler.cpp @@ -17,6 +17,7 @@ #include "llvm/Support/FileOutputBuffer.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/MemoryBuffer.h" +#include using llvm::object::ELFObjectFile; @@ -31,13 +32,13 @@ struct DynamicEntries { uint64_t StrTabAddr = 0; uint64_t StrSize = 0; - Optional SONameOffset; + std::optional SONameOffset; std::vector NeededLibNames; // Symbol table: uint64_t DynSymAddr = 0; // Hash tables: - Optional ElfHash; - Optional GnuHash; + std::optional ElfHash; + std::optional GnuHash; }; /// This initializes an ELF file header with information specific to a binary diff --git a/llvm/lib/LTO/LTO.cpp b/llvm/lib/LTO/LTO.cpp --- a/llvm/lib/LTO/LTO.cpp +++ b/llvm/lib/LTO/LTO.cpp @@ -49,14 +49,13 @@ #include "llvm/Support/ToolOutputFile.h" #include "llvm/Support/VCSRevision.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Transforms/IPO.h" -#include "llvm/Transforms/IPO/PassManagerBuilder.h" #include "llvm/Transforms/IPO/WholeProgramDevirt.h" #include "llvm/Transforms/Utils/FunctionImportUtils.h" #include "llvm/Transforms/Utils/SplitModule.h" +#include #include using namespace llvm; @@ -69,10 +68,12 @@ DumpThinCGSCCs("dump-thin-cg-sccs", cl::init(false), cl::Hidden, cl::desc("Dump the SCCs in the ThinLTO index's callgraph")); +namespace llvm { /// Enable global value internalization in LTO. cl::opt EnableLTOInternalization( "enable-lto-internalization", cl::init(true), cl::Hidden, cl::desc("Enable global value internalization in LTO")); +} // Computes a unique hash for the Module considering the current list of // export/import and other global analysis results. @@ -1252,7 +1253,7 @@ std::set CfiFunctionDefs; std::set CfiFunctionDecls; - Optional Err; + std::optional Err; std::mutex ErrMu; bool ShouldEmitIndexFiles; diff --git a/llvm/lib/LTO/LTOBackend.cpp b/llvm/lib/LTO/LTOBackend.cpp --- a/llvm/lib/LTO/LTOBackend.cpp +++ b/llvm/lib/LTO/LTOBackend.cpp @@ -256,7 +256,7 @@ ModuleAnalysisManager MAM; PassInstrumentationCallbacks PIC; - StandardInstrumentations SI(Conf.DebugPassManager); + StandardInstrumentations SI(Mod.getContext(), Conf.DebugPassManager); SI.registerCallbacks(PIC, &FAM); PassBuilder PB(TM, Conf.PTO, PGOOpt, &PIC); diff --git a/llvm/lib/LTO/LTOCodeGenerator.cpp b/llvm/lib/LTO/LTOCodeGenerator.cpp --- a/llvm/lib/LTO/LTOCodeGenerator.cpp +++ b/llvm/lib/LTO/LTOCodeGenerator.cpp @@ -36,7 +36,6 @@ #include "llvm/IR/Module.h" #include "llvm/IR/PassTimingInfo.h" #include "llvm/IR/Verifier.h" -#include "llvm/InitializePasses.h" #include "llvm/LTO/LTO.h" #include "llvm/LTO/LTOBackend.h" #include "llvm/LTO/legacy/LTOModule.h" @@ -60,7 +59,6 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/Transforms/IPO.h" #include "llvm/Transforms/IPO/Internalize.h" -#include "llvm/Transforms/IPO/PassManagerBuilder.h" #include "llvm/Transforms/IPO/WholeProgramDevirt.h" #include "llvm/Transforms/ObjCARC.h" #include "llvm/Transforms/Utils/ModuleUtils.h" @@ -118,7 +116,7 @@ cl::opt AIXSystemAssemblerPath( "lto-aix-system-assembler", - cl::desc("Absolute path to the system assembler, picked up on AIX only"), + cl::desc("Path to a system assembler, picked up on AIX only"), cl::value_desc("path")); } @@ -253,9 +251,15 @@ "Runing AIX system assembler when integrated assembler is available!"); // Set the system assembler path. - std::string AssemblerPath(llvm::AIXSystemAssemblerPath.empty() - ? "/usr/bin/as" - : llvm::AIXSystemAssemblerPath.c_str()); + SmallString<256> AssemblerPath("/usr/bin/as"); + if (!llvm::AIXSystemAssemblerPath.empty()) { + if (llvm::sys::fs::real_path(llvm::AIXSystemAssemblerPath, AssemblerPath, + /* expand_tilde */ true)) { + emitError( + "Cannot find the assembler specified by lto-aix-system-assembler"); + return false; + } + } // Prepare inputs for the assember. const auto &Triple = TargetMach->getTargetTriple(); diff --git a/llvm/lib/LTO/ThinLTOCodeGenerator.cpp b/llvm/lib/LTO/ThinLTOCodeGenerator.cpp --- a/llvm/lib/LTO/ThinLTOCodeGenerator.cpp +++ b/llvm/lib/LTO/ThinLTOCodeGenerator.cpp @@ -244,7 +244,7 @@ ModuleAnalysisManager MAM; PassInstrumentationCallbacks PIC; - StandardInstrumentations SI(DebugPassManager); + StandardInstrumentations SI(TheModule.getContext(), DebugPassManager); SI.registerCallbacks(PIC, &FAM); PipelineTuningOptions PTO; PTO.LoopVectorization = true; diff --git a/llvm/lib/Linker/IRMover.cpp b/llvm/lib/Linker/IRMover.cpp --- a/llvm/lib/Linker/IRMover.cpp +++ b/llvm/lib/Linker/IRMover.cpp @@ -27,6 +27,7 @@ #include "llvm/Support/Error.h" #include "llvm/Support/Path.h" #include "llvm/Transforms/Utils/ValueMapper.h" +#include #include using namespace llvm; @@ -425,7 +426,7 @@ /// The Error encountered during materialization. We use an Optional here to /// avoid needing to manage an unconsumed success value. - Optional FoundError; + std::optional FoundError; void setError(Error E) { if (E) FoundError = std::move(E); diff --git a/llvm/lib/MC/ConstantPools.cpp b/llvm/lib/MC/ConstantPools.cpp --- a/llvm/lib/MC/ConstantPools.cpp +++ b/llvm/lib/MC/ConstantPools.cpp @@ -28,7 +28,7 @@ return; Streamer.emitDataRegion(MCDR_DataRegion); for (const ConstantPoolEntry &Entry : Entries) { - Streamer.emitValueToAlignment(Entry.Size); // align naturally + Streamer.emitValueToAlignment(Align(Entry.Size)); // align naturally Streamer.emitLabel(Entry.Label); Streamer.emitValue(Entry.Value, Entry.Size, Entry.Loc); } diff --git a/llvm/lib/MC/ELFObjectWriter.cpp b/llvm/lib/MC/ELFObjectWriter.cpp --- a/llvm/lib/MC/ELFObjectWriter.cpp +++ b/llvm/lib/MC/ELFObjectWriter.cpp @@ -142,11 +142,11 @@ bool is64Bit() const; bool usesRela(const MCSectionELF &Sec) const; - uint64_t align(unsigned Alignment); + uint64_t align(Align Alignment); bool maybeWriteCompression(uint32_t ChType, uint64_t Size, SmallVectorImpl &CompressedContents, - unsigned Alignment); + Align Alignment); public: ELFWriter(ELFObjectWriter &OWriter, raw_pwrite_stream &OS, @@ -201,7 +201,7 @@ void WriteSecHdrEntry(uint32_t Name, uint32_t Type, uint64_t Flags, uint64_t Address, uint64_t Offset, uint64_t Size, - uint32_t Link, uint32_t Info, uint64_t Alignment, + uint32_t Link, uint32_t Info, MaybeAlign Alignment, uint64_t EntrySize); void writeRelocations(const MCAssembler &Asm, const MCSectionELF &Sec); @@ -317,8 +317,9 @@ } // end anonymous namespace -uint64_t ELFWriter::align(unsigned Alignment) { - uint64_t Offset = W.OS.tell(), NewOffset = alignTo(Offset, Alignment); +uint64_t ELFWriter::align(Align Alignment) { + uint64_t Offset = W.OS.tell(); + uint64_t NewOffset = alignTo(Offset, Alignment); W.OS.write_zeros(NewOffset - Offset); return NewOffset; } @@ -622,7 +623,7 @@ SymtabSection->setAlignment(is64Bit() ? Align(8) : Align(4)); SymbolTableIndex = addToSectionTable(SymtabSection); - uint64_t SecStart = align(SymtabSection->getAlignment()); + uint64_t SecStart = align(SymtabSection->getAlign()); // The first entry is the undefined symbol entry. Writer.writeSymbol(0, 0, 0, 0, 0, 0, false); @@ -820,7 +821,7 @@ // Include the debug info compression header. bool ELFWriter::maybeWriteCompression( uint32_t ChType, uint64_t Size, - SmallVectorImpl &CompressedContents, unsigned Alignment) { + SmallVectorImpl &CompressedContents, Align Alignment) { uint64_t HdrSize = is64Bit() ? sizeof(ELF::Elf32_Chdr) : sizeof(ELF::Elf64_Chdr); if (Size <= HdrSize + CompressedContents.size()) @@ -831,12 +832,12 @@ write(static_cast(ChType)); write(static_cast(0)); // ch_reserved field. write(static_cast(Size)); - write(static_cast(Alignment)); + write(static_cast(Alignment.value())); } else { // Write Elf32_Chdr header otherwise. write(static_cast(ChType)); write(static_cast(Size)); - write(static_cast(Alignment)); + write(static_cast(Alignment.value())); } return true; } @@ -878,7 +879,7 @@ compression::compress(compression::Params(CompressionType), Uncompressed, Compressed); if (!maybeWriteCompression(ChType, UncompressedData.size(), Compressed, - Sec.getAlignment())) { + Sec.getAlign())) { W.OS << UncompressedData; return; } @@ -893,7 +894,7 @@ void ELFWriter::WriteSecHdrEntry(uint32_t Name, uint32_t Type, uint64_t Flags, uint64_t Address, uint64_t Offset, uint64_t Size, uint32_t Link, uint32_t Info, - uint64_t Alignment, uint64_t EntrySize) { + MaybeAlign Alignment, uint64_t EntrySize) { W.write(Name); // sh_name: index into string table W.write(Type); // sh_type WriteWord(Flags); // sh_flags @@ -902,7 +903,7 @@ WriteWord(Size); // sh_size W.write(Link); // sh_link W.write(Info); // sh_info - WriteWord(Alignment); // sh_addralign + WriteWord(Alignment ? Alignment->value() : 0); // sh_addralign WriteWord(EntrySize); // sh_entsize } @@ -1024,7 +1025,7 @@ WriteSecHdrEntry(StrTabBuilder.getOffset(Section.getName()), Section.getType(), Section.getFlags(), 0, Offset, Size, - sh_link, sh_info, Section.getAlignment(), + sh_link, sh_info, Section.getAlign(), Section.getEntrySize()); } @@ -1036,7 +1037,7 @@ // Null section first. uint64_t FirstSectionSize = (NumSections + 1) >= ELF::SHN_LORESERVE ? NumSections + 1 : 0; - WriteSecHdrEntry(0, 0, 0, 0, 0, FirstSectionSize, 0, 0, 0, 0); + WriteSecHdrEntry(0, 0, 0, 0, 0, FirstSectionSize, 0, 0, None, 0); for (const MCSectionELF *Section : SectionTable) { uint32_t GroupSymbolIndex; @@ -1087,7 +1088,7 @@ continue; // Remember the offset into the file for this section. - const uint64_t SecStart = align(Section.getAlignment()); + const uint64_t SecStart = align(Section.getAlign()); const MCSymbolELF *SignatureSymbol = Section.getGroup(); writeSectionData(Asm, Section, Layout); @@ -1124,7 +1125,7 @@ for (MCSectionELF *Group : Groups) { // Remember the offset into the file for this section. - const uint64_t SecStart = align(Group->getAlignment()); + const uint64_t SecStart = align(Group->getAlign()); const MCSymbol *SignatureSymbol = Group->getGroup(); assert(SignatureSymbol); @@ -1156,7 +1157,7 @@ for (MCSectionELF *RelSection : Relocations) { // Remember the offset into the file for this section. - const uint64_t SecStart = align(RelSection->getAlignment()); + const uint64_t SecStart = align(RelSection->getAlign()); writeRelocations(Asm, cast(*RelSection->getLinkedToSection())); @@ -1179,7 +1180,7 @@ SectionOffsets[StrtabSection] = std::make_pair(SecStart, W.OS.tell()); } - const uint64_t SectionHeaderOffset = align(is64Bit() ? 8 : 4); + const uint64_t SectionHeaderOffset = align(is64Bit() ? Align(8) : Align(4)); // ... then the section header table ... writeSectionHeader(Layout, SectionIndexMap, SectionOffsets); diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp --- a/llvm/lib/MC/MCAsmStreamer.cpp +++ b/llvm/lib/MC/MCAsmStreamer.cpp @@ -187,8 +187,7 @@ void emitCOFFSecRel32(MCSymbol const *Symbol, uint64_t Offset) override; void emitCOFFImgRel32(MCSymbol const *Symbol, int64_t Offset) override; void emitXCOFFLocalCommonSymbol(MCSymbol *LabelSym, uint64_t Size, - MCSymbol *CsectSym, - unsigned ByteAlign) override; + MCSymbol *CsectSym, Align Alignment) override; void emitXCOFFSymbolLinkageWithVisibility(MCSymbol *Symbol, MCSymbolAttr Linakge, MCSymbolAttr Visibility) override; @@ -253,11 +252,11 @@ void emitAlignmentDirective(unsigned ByteAlignment, Optional Value, unsigned ValueSize, unsigned MaxBytesToEmit); - void emitValueToAlignment(unsigned ByteAlignment, int64_t Value = 0, + void emitValueToAlignment(Align Alignment, int64_t Value = 0, unsigned ValueSize = 1, unsigned MaxBytesToEmit = 0) override; - void emitCodeAlignment(unsigned ByteAlignment, const MCSubtargetInfo *STI, + void emitCodeAlignment(Align Alignment, const MCSubtargetInfo *STI, unsigned MaxBytesToEmit = 0) override; void emitValueToOffset(const MCExpr *Offset, @@ -381,7 +380,7 @@ uint64_t Attr, const MCPseudoProbeInlineStack &InlineStack, MCSymbol *FnSym) override; - void emitBundleAlignMode(unsigned AlignPow2) override; + void emitBundleAlignMode(Align Alignment) override; void emitBundleLock(bool AlignToEnd) override; void emitBundleUnlock() override; @@ -859,16 +858,15 @@ void MCAsmStreamer::emitXCOFFLocalCommonSymbol(MCSymbol *LabelSym, uint64_t Size, MCSymbol *CsectSym, - unsigned ByteAlignment) { + Align Alignment) { assert(MAI->getLCOMMDirectiveAlignmentType() == LCOMM::Log2Alignment && "We only support writing log base-2 alignment format with XCOFF."); - assert(isPowerOf2_32(ByteAlignment) && "Alignment must be a power of 2."); OS << "\t.lcomm\t"; LabelSym->print(OS, MAI); OS << ',' << Size << ','; CsectSym->print(OS, MAI); - OS << ',' << Log2_32(ByteAlignment); + OS << ',' << Log2(Alignment); EmitEOL(); @@ -1484,21 +1482,21 @@ EmitEOL(); } -void MCAsmStreamer::emitValueToAlignment(unsigned ByteAlignment, int64_t Value, +void MCAsmStreamer::emitValueToAlignment(Align Alignment, int64_t Value, unsigned ValueSize, unsigned MaxBytesToEmit) { - emitAlignmentDirective(ByteAlignment, Value, ValueSize, MaxBytesToEmit); + emitAlignmentDirective(Alignment.value(), Value, ValueSize, MaxBytesToEmit); } -void MCAsmStreamer::emitCodeAlignment(unsigned ByteAlignment, +void MCAsmStreamer::emitCodeAlignment(Align Alignment, const MCSubtargetInfo *STI, unsigned MaxBytesToEmit) { // Emit with a text fill value. if (MAI->getTextAlignFillValue()) - emitAlignmentDirective(ByteAlignment, MAI->getTextAlignFillValue(), 1, + emitAlignmentDirective(Alignment.value(), MAI->getTextAlignFillValue(), 1, MaxBytesToEmit); else - emitAlignmentDirective(ByteAlignment, None, 1, MaxBytesToEmit); + emitAlignmentDirective(Alignment.value(), None, 1, MaxBytesToEmit); } void MCAsmStreamer::emitValueToOffset(const MCExpr *Offset, @@ -2353,8 +2351,8 @@ EmitEOL(); } -void MCAsmStreamer::emitBundleAlignMode(unsigned AlignPow2) { - OS << "\t.bundle_align_mode " << AlignPow2; +void MCAsmStreamer::emitBundleAlignMode(Align Alignment) { + OS << "\t.bundle_align_mode " << Log2(Alignment); EmitEOL(); } diff --git a/llvm/lib/MC/MCCodeView.cpp b/llvm/lib/MC/MCCodeView.cpp --- a/llvm/lib/MC/MCCodeView.cpp +++ b/llvm/lib/MC/MCCodeView.cpp @@ -185,7 +185,7 @@ InsertedStrTabFragment = true; } - OS.emitValueToAlignment(4, 0); + OS.emitValueToAlignment(Align(4), 0); OS.emitLabel(StringEnd); } @@ -233,7 +233,7 @@ OS.emitInt8(static_cast(File.Checksum.size())); OS.emitInt8(File.ChecksumKind); OS.emitBytes(toStringRef(File.Checksum)); - OS.emitValueToAlignment(4); + OS.emitValueToAlignment(Align(4)); } OS.emitLabel(FileEnd); diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp --- a/llvm/lib/MC/MCDwarf.cpp +++ b/llvm/lib/MC/MCDwarf.cpp @@ -1686,7 +1686,7 @@ InitialCFAOffset = CFAOffset; // Padding - Streamer.emitValueToAlignment(IsEH ? 4 : MAI->getCodePointerSize()); + Streamer.emitValueToAlignment(Align(IsEH ? 4 : MAI->getCodePointerSize())); Streamer.emitLabel(sectionEnd); return *sectionStart; @@ -1763,8 +1763,8 @@ // The size of a .eh_frame section has to be a multiple of the alignment // since a null CIE is interpreted as the end. Old systems overaligned // .eh_frame, so we do too and account for it in the last FDE. - unsigned Align = LastInSection ? asmInfo->getCodePointerSize() : PCSize; - Streamer.emitValueToAlignment(Align); + unsigned Alignment = LastInSection ? asmInfo->getCodePointerSize() : PCSize; + Streamer.emitValueToAlignment(Align(Alignment)); Streamer.emitLabel(fdeEnd); } @@ -1869,7 +1869,7 @@ if (Frame.CompactUnwindEncoding == 0) continue; if (!SectionEmitted) { Streamer.switchSection(MOFI->getCompactUnwindSection()); - Streamer.emitValueToAlignment(AsmInfo->getCodePointerSize()); + Streamer.emitValueToAlignment(Align(AsmInfo->getCodePointerSize())); SectionEmitted = true; } NeedsEHFrameSection |= diff --git a/llvm/lib/MC/MCELFStreamer.cpp b/llvm/lib/MC/MCELFStreamer.cpp --- a/llvm/lib/MC/MCELFStreamer.cpp +++ b/llvm/lib/MC/MCELFStreamer.cpp @@ -91,7 +91,8 @@ void MCELFStreamer::initSections(bool NoExecStack, const MCSubtargetInfo &STI) { MCContext &Ctx = getContext(); switchSection(Ctx.getObjectFileInfo()->getTextSection()); - emitCodeAlignment(Ctx.getObjectFileInfo()->getTextSectionAlignment(), &STI); + emitCodeAlignment(Align(Ctx.getObjectFileInfo()->getTextSectionAlignment()), + &STI); if (NoExecStack) switchSection(Ctx.getAsmInfo()->getNonexecutableStackSection(Ctx)); @@ -139,9 +140,8 @@ // needs to be aligned to at least the bundle size. static void setSectionAlignmentForBundling(const MCAssembler &Assembler, MCSection *Section) { - if (Section && Assembler.isBundlingEnabled() && Section->hasInstructions() && - Section->getAlignment() < Assembler.getBundleAlignSize()) - Section->setAlignment(Align(Assembler.getBundleAlignSize())); + if (Section && Assembler.isBundlingEnabled() && Section->hasInstructions()) + Section->ensureMinAlignment(Align(Assembler.getBundleAlignSize())); } void MCELFStreamer::changeSection(MCSection *Section, @@ -321,7 +321,7 @@ MCSectionSubPair P = getCurrentSection(); switchSection(&Section); - emitValueToAlignment(ByteAlignment, 0, 1, 0); + emitValueToAlignment(Align(ByteAlignment), 0, 1, 0); emitLabel(Symbol); emitZeros(Size); @@ -364,14 +364,13 @@ MCObjectStreamer::emitValueImpl(Value, Size, Loc); } -void MCELFStreamer::emitValueToAlignment(unsigned ByteAlignment, - int64_t Value, +void MCELFStreamer::emitValueToAlignment(Align Alignment, int64_t Value, unsigned ValueSize, unsigned MaxBytesToEmit) { if (isBundleLocked()) report_fatal_error("Emitting values inside a locked bundle is forbidden"); - MCObjectStreamer::emitValueToAlignment(ByteAlignment, Value, - ValueSize, MaxBytesToEmit); + MCObjectStreamer::emitValueToAlignment(Alignment, Value, ValueSize, + MaxBytesToEmit); } void MCELFStreamer::emitCGProfileEntry(const MCSymbolRefExpr *From, @@ -635,12 +634,12 @@ } } -void MCELFStreamer::emitBundleAlignMode(unsigned AlignPow2) { - assert(AlignPow2 <= 30 && "Invalid bundle alignment"); +void MCELFStreamer::emitBundleAlignMode(Align Alignment) { + assert(Log2(Alignment) <= 30 && "Invalid bundle alignment"); MCAssembler &Assembler = getAssembler(); - if (AlignPow2 > 0 && (Assembler.getBundleAlignSize() == 0 || - Assembler.getBundleAlignSize() == 1U << AlignPow2)) - Assembler.setBundleAlignSize(1U << AlignPow2); + if (Alignment > 1 && (Assembler.getBundleAlignSize() == 0 || + Assembler.getBundleAlignSize() == Alignment.value())) + Assembler.setBundleAlignSize(Alignment.value()); else report_fatal_error(".bundle_align_mode cannot be changed once set"); } diff --git a/llvm/lib/MC/MCMachOStreamer.cpp b/llvm/lib/MC/MCMachOStreamer.cpp --- a/llvm/lib/MC/MCMachOStreamer.cpp +++ b/llvm/lib/MC/MCMachOStreamer.cpp @@ -465,7 +465,7 @@ // The symbol may not be present, which only creates the section. if (Symbol) { - emitValueToAlignment(ByteAlignment, 0, 1, 0); + emitValueToAlignment(Align(ByteAlignment), 0, 1, 0); emitLabel(Symbol); emitZeros(Size); } diff --git a/llvm/lib/MC/MCObjectFileInfo.cpp b/llvm/lib/MC/MCObjectFileInfo.cpp --- a/llvm/lib/MC/MCObjectFileInfo.cpp +++ b/llvm/lib/MC/MCObjectFileInfo.cpp @@ -80,10 +80,6 @@ FDECFIEncoding = dwarf::DW_EH_PE_pcrel; - // .comm doesn't support alignment before Leopard. - if (T.isMacOSX() && T.isMacOSXVersionLT(10, 5)) - CommDirectiveSupportsAlignment = false; - TextSection // .text = Ctx->getMachOSection("__TEXT", "__text", MachO::S_ATTR_PURE_INSTRUCTIONS, @@ -556,8 +552,6 @@ // and to set the ISA selection bit for calls accordingly. const bool IsThumb = T.getArch() == Triple::thumb; - CommDirectiveSupportsAlignment = true; - // COFF BSSSection = Ctx->getCOFFSection( ".bss", COFF::IMAGE_SCN_CNT_UNINITIALIZED_DATA | @@ -1035,7 +1029,6 @@ Ctx = &MCCtx; // Common. - CommDirectiveSupportsAlignment = true; SupportsWeakOmittedEHFrame = true; SupportsCompactUnwindWithoutEHFrame = false; OmitDwarfIfHaveCompactUnwind = false; diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp --- a/llvm/lib/MC/MCObjectStreamer.cpp +++ b/llvm/lib/MC/MCObjectStreamer.cpp @@ -480,7 +480,7 @@ "Aligned bundling is not implemented for this object format"; #endif -void MCObjectStreamer::emitBundleAlignMode(unsigned AlignPow2) { +void MCObjectStreamer::emitBundleAlignMode(Align Alignment) { llvm_unreachable(BundlingNotImplementedMsg); } @@ -641,25 +641,22 @@ DF->getContents().append(Data.begin(), Data.end()); } -void MCObjectStreamer::emitValueToAlignment(unsigned ByteAlignment, - int64_t Value, +void MCObjectStreamer::emitValueToAlignment(Align Alignment, int64_t Value, unsigned ValueSize, unsigned MaxBytesToEmit) { if (MaxBytesToEmit == 0) - MaxBytesToEmit = ByteAlignment; - insert(new MCAlignFragment(Align(ByteAlignment), Value, ValueSize, - MaxBytesToEmit)); + MaxBytesToEmit = Alignment.value(); + insert(new MCAlignFragment(Alignment, Value, ValueSize, MaxBytesToEmit)); // Update the maximum alignment on the current section if necessary. MCSection *CurSec = getCurrentSectionOnly(); - if (ByteAlignment > CurSec->getAlignment()) - CurSec->setAlignment(Align(ByteAlignment)); + CurSec->ensureMinAlignment(Alignment); } -void MCObjectStreamer::emitCodeAlignment(unsigned ByteAlignment, +void MCObjectStreamer::emitCodeAlignment(Align Alignment, const MCSubtargetInfo *STI, unsigned MaxBytesToEmit) { - emitValueToAlignment(ByteAlignment, 0, 1, MaxBytesToEmit); + emitValueToAlignment(Alignment, 0, 1, MaxBytesToEmit); cast(getCurrentFragment())->setEmitNops(true, STI); } diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp --- a/llvm/lib/MC/MCParser/AsmParser.cpp +++ b/llvm/lib/MC/MCParser/AsmParser.cpp @@ -74,8 +74,6 @@ MCAsmParserSemaCallback::~MCAsmParserSemaCallback() = default; -extern cl::opt AsmMacroMaxNestingDepth; - namespace { /// Helper types for tracking macro definitions. @@ -753,6 +751,8 @@ namespace llvm { +extern cl::opt AsmMacroMaxNestingDepth; + extern MCAsmParserExtension *createDarwinAsmParser(); extern MCAsmParserExtension *createELFAsmParser(); extern MCAsmParserExtension *createCOFFAsmParser(); @@ -3485,11 +3485,11 @@ bool useCodeAlign = Section->useCodeAlign(); if ((!HasFillExpr || Lexer.getMAI().getTextAlignFillValue() == FillExpr) && ValueSize == 1 && useCodeAlign) { - getStreamer().emitCodeAlignment(Alignment, &getTargetParser().getSTI(), - MaxBytesToFill); + getStreamer().emitCodeAlignment( + Align(Alignment), &getTargetParser().getSTI(), MaxBytesToFill); } else { // FIXME: Target specific behavior about how the "extra" bytes are filled. - getStreamer().emitValueToAlignment(Alignment, FillExpr, ValueSize, + getStreamer().emitValueToAlignment(Align(Alignment), FillExpr, ValueSize, MaxBytesToFill); } @@ -4808,9 +4808,7 @@ "invalid bundle alignment size (expected between 0 and 30)")) return true; - // Because of AlignSizePow2's verified range we can safely truncate it to - // unsigned. - getStreamer().emitBundleAlignMode(static_cast(AlignSizePow2)); + getStreamer().emitBundleAlignMode(Align(1ULL << AlignSizePow2)); return false; } diff --git a/llvm/lib/MC/MCParser/DarwinAsmParser.cpp b/llvm/lib/MC/MCParser/DarwinAsmParser.cpp --- a/llvm/lib/MC/MCParser/DarwinAsmParser.cpp +++ b/llvm/lib/MC/MCParser/DarwinAsmParser.cpp @@ -472,7 +472,7 @@ } // end anonymous namespace bool DarwinAsmParser::parseSectionSwitch(StringRef Segment, StringRef Section, - unsigned TAA, unsigned Align, + unsigned TAA, unsigned Alignment, unsigned StubSize) { if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in section switching directive"); @@ -492,8 +492,8 @@ // the section. However, this is arguably more reasonable behavior, and there // is no good reason for someone to intentionally emit incorrectly sized // values into the implicitly aligned sections. - if (Align) - getStreamer().emitValueToAlignment(Align); + if (Alignment) + getStreamer().emitValueToAlignment(Align(Alignment)); return false; } diff --git a/llvm/lib/MC/MCParser/ELFAsmParser.cpp b/llvm/lib/MC/MCParser/ELFAsmParser.cpp --- a/llvm/lib/MC/MCParser/ELFAsmParser.cpp +++ b/llvm/lib/MC/MCParser/ELFAsmParser.cpp @@ -868,7 +868,7 @@ getStreamer().emitInt32(1); // type = NT_VERSION getStreamer().emitBytes(Data); // name getStreamer().emitInt8(0); // NUL - getStreamer().emitValueToAlignment(4); + getStreamer().emitValueToAlignment(Align(4)); getStreamer().popSection(); return false; } diff --git a/llvm/lib/MC/MCParser/MCAsmParser.cpp b/llvm/lib/MC/MCParser/MCAsmParser.cpp --- a/llvm/lib/MC/MCParser/MCAsmParser.cpp +++ b/llvm/lib/MC/MCParser/MCAsmParser.cpp @@ -21,9 +21,11 @@ using namespace llvm; +namespace llvm { cl::opt AsmMacroMaxNestingDepth( "asm-macro-max-nesting-depth", cl::init(20), cl::Hidden, cl::desc("The maximum nesting depth allowed for assembly macros.")); +} MCAsmParser::MCAsmParser() = default; diff --git a/llvm/lib/MC/MCParser/MasmParser.cpp b/llvm/lib/MC/MCParser/MasmParser.cpp --- a/llvm/lib/MC/MCParser/MasmParser.cpp +++ b/llvm/lib/MC/MCParser/MasmParser.cpp @@ -67,6 +67,7 @@ #include #include #include +#include #include #include #include @@ -75,8 +76,6 @@ using namespace llvm; -extern cl::opt AsmMacroMaxNestingDepth; - namespace { /// Helper types for tracking macro definitions. @@ -109,7 +108,7 @@ bool ParseError = false; /// The value associated with a macro exit. - Optional ExitValue; + std::optional ExitValue; SmallVectorImpl *AsmRewrites = nullptr; @@ -1082,6 +1081,8 @@ namespace llvm { +extern cl::opt AsmMacroMaxNestingDepth; + extern MCAsmParserExtension *createCOFFMasmParser(); } // end namespace llvm @@ -2883,7 +2884,7 @@ Name.clear(); } - Optional CurrentQuote; + std::optional CurrentQuote; while (!Body.empty()) { // Scan for the next substitution. std::size_t End = Body.size(), Pos = 0; @@ -4214,7 +4215,7 @@ StructInitializer &Initializer) { const AsmToken FirstToken = getTok(); - Optional EndToken; + std::optional EndToken; if (parseOptionalToken(AsmToken::LCurly)) { EndToken = AsmToken::RCurly; } else if (parseOptionalAngleBracketOpen()) { @@ -4742,11 +4743,12 @@ const MCSection *Section = getStreamer().getCurrentSectionOnly(); assert(Section && "must have section to emit alignment"); if (Section->useCodeAlign()) { - getStreamer().emitCodeAlignment(Alignment, &getTargetParser().getSTI(), + getStreamer().emitCodeAlignment(Align(Alignment), + &getTargetParser().getSTI(), /*MaxBytesToEmit=*/0); } else { // FIXME: Target specific behavior about how the "extra" bytes are filled. - getStreamer().emitValueToAlignment(Alignment, /*Value=*/0, + getStreamer().emitValueToAlignment(Align(Alignment), /*Value=*/0, /*ValueSize=*/1, /*MaxBytesToEmit=*/0); } diff --git a/llvm/lib/MC/MCParser/WasmAsmParser.cpp b/llvm/lib/MC/MCParser/WasmAsmParser.cpp --- a/llvm/lib/MC/MCParser/WasmAsmParser.cpp +++ b/llvm/lib/MC/MCParser/WasmAsmParser.cpp @@ -26,6 +26,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbolWasm.h" #include "llvm/Support/Casting.h" +#include using namespace llvm; @@ -152,7 +153,7 @@ if (Lexer->isNot(AsmToken::String)) return error("expected string in directive, instead got: ", Lexer->getTok()); - auto Kind = StringSwitch>(Name) + auto Kind = StringSwitch>(Name) .StartsWith(".data", SectionKind::getData()) .StartsWith(".tdata", SectionKind::getThreadData()) .StartsWith(".tbss", SectionKind::getThreadBSS()) diff --git a/llvm/lib/MC/MCSchedule.cpp b/llvm/lib/MC/MCSchedule.cpp --- a/llvm/lib/MC/MCSchedule.cpp +++ b/llvm/lib/MC/MCSchedule.cpp @@ -15,6 +15,7 @@ #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include #include using namespace llvm; @@ -87,7 +88,7 @@ double MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI, const MCSchedClassDesc &SCDesc) { - Optional Throughput; + std::optional Throughput; const MCSchedModel &SM = STI.getSchedModel(); const MCWriteProcResEntry *I = STI.getWriteProcResBegin(&SCDesc); const MCWriteProcResEntry *E = STI.getWriteProcResEnd(&SCDesc); @@ -133,7 +134,7 @@ double MCSchedModel::getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID) { - Optional Throughput; + std::optional Throughput; const InstrStage *I = IID.beginStage(SchedClass); const InstrStage *E = IID.endStage(SchedClass); for (; I != E; ++I) { diff --git a/llvm/lib/MC/MCSectionXCOFF.cpp b/llvm/lib/MC/MCSectionXCOFF.cpp --- a/llvm/lib/MC/MCSectionXCOFF.cpp +++ b/llvm/lib/MC/MCSectionXCOFF.cpp @@ -20,8 +20,7 @@ MCSectionXCOFF::~MCSectionXCOFF() = default; void MCSectionXCOFF::printCsectDirective(raw_ostream &OS) const { - OS << "\t.csect " << QualName->getName() << "," << Log2_32(getAlignment()) - << '\n'; + OS << "\t.csect " << QualName->getName() << "," << Log2(getAlign()) << '\n'; } void MCSectionXCOFF::printSwitchToSection(const MCAsmInfo &MAI, const Triple &T, diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp --- a/llvm/lib/MC/MCStreamer.cpp +++ b/llvm/lib/MC/MCStreamer.cpp @@ -1170,7 +1170,7 @@ } void MCStreamer::emitXCOFFLocalCommonSymbol(MCSymbol *LabelSym, uint64_t Size, MCSymbol *CsectSym, - unsigned ByteAlign) { + Align Alignment) { llvm_unreachable("this directive only supported on XCOFF targets"); } @@ -1219,15 +1219,14 @@ void MCStreamer::emitFill(const MCExpr &NumBytes, uint64_t Value, SMLoc Loc) {} void MCStreamer::emitFill(const MCExpr &NumValues, int64_t Size, int64_t Expr, SMLoc Loc) {} -void MCStreamer::emitValueToAlignment(unsigned ByteAlignment, int64_t Value, +void MCStreamer::emitValueToAlignment(Align Alignment, int64_t Value, unsigned ValueSize, unsigned MaxBytesToEmit) {} -void MCStreamer::emitCodeAlignment(unsigned ByteAlignment, - const MCSubtargetInfo *STI, +void MCStreamer::emitCodeAlignment(Align Alignment, const MCSubtargetInfo *STI, unsigned MaxBytesToEmit) {} void MCStreamer::emitValueToOffset(const MCExpr *Offset, unsigned char Value, SMLoc Loc) {} -void MCStreamer::emitBundleAlignMode(unsigned AlignPow2) {} +void MCStreamer::emitBundleAlignMode(Align Alignment) {} void MCStreamer::emitBundleLock(bool AlignToEnd) {} void MCStreamer::finishImpl() {} void MCStreamer::emitBundleUnlock() {} diff --git a/llvm/lib/MC/MCWin64EH.cpp b/llvm/lib/MC/MCWin64EH.cpp --- a/llvm/lib/MC/MCWin64EH.cpp +++ b/llvm/lib/MC/MCWin64EH.cpp @@ -156,7 +156,7 @@ const WinEH::FrameInfo *info) { MCContext &context = streamer.getContext(); - streamer.emitValueToAlignment(4); + streamer.emitValueToAlignment(Align(4)); EmitSymbolRefWithOfs(streamer, info->Begin, info->Begin); EmitSymbolRefWithOfs(streamer, info->Begin, info->End); streamer.emitValue(MCSymbolRefExpr::create(info->Symbol, @@ -172,7 +172,7 @@ MCContext &context = streamer.getContext(); MCSymbol *Label = context.createTempSymbol(); - streamer.emitValueToAlignment(4); + streamer.emitValueToAlignment(Align(4)); streamer.emitLabel(Label); info->Symbol = Label; @@ -1169,7 +1169,7 @@ MCContext &context = streamer.getContext(); MCSymbol *Label = context.createTempSymbol(); - streamer.emitValueToAlignment(4); + streamer.emitValueToAlignment(Align(4)); streamer.emitLabel(Label); Seg.Symbol = Label; // Use the 1st segemnt's label as function's. @@ -2253,7 +2253,7 @@ MCContext &context = streamer.getContext(); MCSymbol *Label = context.createTempSymbol(); - streamer.emitValueToAlignment(4); + streamer.emitValueToAlignment(Align(4)); streamer.emitLabel(Label); info->Symbol = Label; @@ -2465,7 +2465,7 @@ const WinEH::FrameInfo *info) { MCContext &context = streamer.getContext(); - streamer.emitValueToAlignment(4); + streamer.emitValueToAlignment(Align(4)); for (const auto &S : info->Segments) { EmitSymbolRefWithOfs(streamer, info->Begin, S.Offset); if (info->PackedInfo) @@ -2483,7 +2483,7 @@ const WinEH::FrameInfo *info) { MCContext &context = streamer.getContext(); - streamer.emitValueToAlignment(4); + streamer.emitValueToAlignment(Align(4)); EmitSymbolRefWithOfs(streamer, info->Begin, info->Begin); if (info->PackedInfo) streamer.emitInt32(info->PackedInfo); diff --git a/llvm/lib/MC/MCWinCOFFStreamer.cpp b/llvm/lib/MC/MCWinCOFFStreamer.cpp --- a/llvm/lib/MC/MCWinCOFFStreamer.cpp +++ b/llvm/lib/MC/MCWinCOFFStreamer.cpp @@ -71,13 +71,13 @@ // This emulates the same behavior of GNU as. This makes it easier // to compare the output as the major sections are in the same order. switchSection(getContext().getObjectFileInfo()->getTextSection()); - emitCodeAlignment(4, &STI); + emitCodeAlignment(Align(4), &STI); switchSection(getContext().getObjectFileInfo()->getDataSection()); - emitCodeAlignment(4, &STI); + emitCodeAlignment(Align(4), &STI); switchSection(getContext().getObjectFileInfo()->getBSSSection()); - emitCodeAlignment(4, &STI); + emitCodeAlignment(Align(4), &STI); switchSection(getContext().getObjectFileInfo()->getTextSection()); } @@ -190,8 +190,7 @@ MCSection *SXData = getContext().getObjectFileInfo()->getSXDataSection(); getAssembler().registerSection(*SXData); - if (SXData->getAlignment() < 4) - SXData->setAlignment(Align(4)); + SXData->ensureMinAlignment(Align(4)); new MCSymbolIdFragment(Symbol, SXData); @@ -207,8 +206,7 @@ void MCWinCOFFStreamer::emitCOFFSymbolIndex(MCSymbol const *Symbol) { MCSection *Sec = getCurrentSectionOnly(); getAssembler().registerSection(*Sec); - if (Sec->getAlignment() < 4) - Sec->setAlignment(Align(4)); + Sec->ensureMinAlignment(Align(4)); new MCSymbolIdFragment(Symbol, getCurrentSectionOnly()); @@ -300,7 +298,7 @@ MCSection *Section = getContext().getObjectFileInfo()->getBSSSection(); pushSection(); switchSection(Section); - emitValueToAlignment(ByteAlignment, 0, 1, 0); + emitValueToAlignment(Align(ByteAlignment), 0, 1, 0); emitLabel(Symbol); Symbol->setExternal(false); emitZeros(Size); diff --git a/llvm/lib/MC/MCXCOFFStreamer.cpp b/llvm/lib/MC/MCXCOFFStreamer.cpp --- a/llvm/lib/MC/MCXCOFFStreamer.cpp +++ b/llvm/lib/MC/MCXCOFFStreamer.cpp @@ -103,7 +103,7 @@ Align(ByteAlignment)); // Emit the alignment and storage for the variable to the section. - emitValueToAlignment(ByteAlignment); + emitValueToAlignment(Align(ByteAlignment)); emitZeros(Size); } @@ -149,6 +149,6 @@ void MCXCOFFStreamer::emitXCOFFLocalCommonSymbol(MCSymbol *LabelSym, uint64_t Size, MCSymbol *CsectSym, - unsigned ByteAlignment) { - emitCommonSymbol(CsectSym, Size, ByteAlignment); + Align Alignment) { + emitCommonSymbol(CsectSym, Size, Alignment.value()); } diff --git a/llvm/lib/MC/MachObjectWriter.cpp b/llvm/lib/MC/MachObjectWriter.cpp --- a/llvm/lib/MC/MachObjectWriter.cpp +++ b/llvm/lib/MC/MachObjectWriter.cpp @@ -129,7 +129,7 @@ const MCSection &NextSec = *Layout.getSectionOrder()[Next]; if (NextSec.isVirtualSection()) return 0; - return offsetToAlignment(EndAddr, Align(NextSec.getAlignment())); + return offsetToAlignment(EndAddr, NextSec.getAlign()); } void MachObjectWriter::writeHeader(MachO::HeaderFileType Type, @@ -244,8 +244,7 @@ } W.write(FileOffset); - assert(isPowerOf2_32(Section.getAlignment()) && "Invalid alignment!"); - W.write(Log2_32(Section.getAlignment())); + W.write(Log2(Section.getAlign())); W.write(NumRelocations ? RelocationsStart : 0); W.write(NumRelocations); W.write(Flags); @@ -645,7 +644,7 @@ const MCAsmLayout &Layout) { uint64_t StartAddress = 0; for (const MCSection *Sec : Layout.getSectionOrder()) { - StartAddress = alignTo(StartAddress, Sec->getAlignment()); + StartAddress = alignTo(StartAddress, Sec->getAlign()); SectionAddress[Sec] = StartAddress; StartAddress += Layout.getSectionAddressSize(Sec); diff --git a/llvm/lib/MC/WasmObjectWriter.cpp b/llvm/lib/MC/WasmObjectWriter.cpp --- a/llvm/lib/MC/WasmObjectWriter.cpp +++ b/llvm/lib/MC/WasmObjectWriter.cpp @@ -716,7 +716,7 @@ MCSectionWasm &DataSection) { LLVM_DEBUG(errs() << "addData: " << DataSection.getName() << "\n"); - DataBytes.resize(alignTo(DataBytes.size(), DataSection.getAlignment())); + DataBytes.resize(alignTo(DataBytes.size(), DataSection.getAlign())); for (const MCFragment &Frag : DataSection) { if (Frag.hasInstructions()) @@ -1498,7 +1498,7 @@ if (Section.isWasmData()) { uint32_t SegmentIndex = DataSegments.size(); - DataSize = alignTo(DataSize, Section.getAlignment()); + DataSize = alignTo(DataSize, Section.getAlign()); DataSegments.emplace_back(); WasmDataSegment &Segment = DataSegments.back(); Segment.Name = SectionName; @@ -1508,7 +1508,7 @@ Segment.Offset = DataSize; Segment.Section = &Section; addData(Segment.Data, Section); - Segment.Alignment = Log2_32(Section.getAlignment()); + Segment.Alignment = Log2(Section.getAlign()); Segment.LinkingFlags = Section.getSegmentFlags(); DataSize += Segment.Data.size(); Section.setSegmentIndex(SegmentIndex); diff --git a/llvm/lib/MC/WinCOFFObjectWriter.cpp b/llvm/lib/MC/WinCOFFObjectWriter.cpp --- a/llvm/lib/MC/WinCOFFObjectWriter.cpp +++ b/llvm/lib/MC/WinCOFFObjectWriter.cpp @@ -267,7 +267,7 @@ } static uint32_t getAlignment(const MCSectionCOFF &Sec) { - switch (Sec.getAlignment()) { + switch (Sec.getAlign().value()) { case 1: return COFF::IMAGE_SCN_ALIGN_1BYTES; case 2: diff --git a/llvm/lib/MC/XCOFFObjectWriter.cpp b/llvm/lib/MC/XCOFFObjectWriter.cpp --- a/llvm/lib/MC/XCOFFObjectWriter.cpp +++ b/llvm/lib/MC/XCOFFObjectWriter.cpp @@ -1192,7 +1192,7 @@ for (auto &Csect : *Group) { const MCSectionXCOFF *MCSec = Csect.MCSec; - Csect.Address = alignTo(Address, MCSec->getAlignment()); + Csect.Address = alignTo(Address, MCSec->getAlign()); Csect.Size = Layout.getSectionAddressSize(MCSec); Address = Csect.Address + Csect.Size; Csect.SymbolTableIndex = SymbolTableIndex; @@ -1247,7 +1247,7 @@ if (!DwarfSections.empty()) PaddingsBeforeDwarf = alignTo(Address, - (*DwarfSections.begin()).DwarfSect->MCSec->getAlignment()) - + (*DwarfSections.begin()).DwarfSect->MCSec->getAlign()) - Address; DwarfSectionEntry *LastDwarfSection = nullptr; @@ -1273,7 +1273,7 @@ // This address is used to tell where is the section in the final object. // See writeSectionForDwarfSectionEntry(). DwarfSection.Address = DwarfSect.Address = - alignTo(Address, MCSec->getAlignment()); + alignTo(Address, MCSec->getAlign()); // Section size. // For DWARF section, we must use the real size which may be not aligned. @@ -1448,9 +1448,7 @@ // significant bits of a byte, then or's in the csect type into the least // significant 3 bits. uint8_t getEncodedType(const MCSectionXCOFF *Sec) { - unsigned Align = Sec->getAlignment(); - assert(isPowerOf2_32(Align) && "Alignment must be a power of 2."); - unsigned Log2Align = Log2_32(Align); + unsigned Log2Align = Log2(Sec->getAlign()); // Result is a number in the range [0, 31] which fits in the 5 least // significant bits. Shift this value into the 5 most significant bits, and // bitwise-or in the csect type. diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp --- a/llvm/lib/Object/ELFObjectFile.cpp +++ b/llvm/lib/Object/ELFObjectFile.cpp @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -624,7 +625,7 @@ T->createMCInstrAnalysis(MII.get())); if (!MIA) return {}; - Optional Plt, RelaPlt, GotPlt; + std::optional Plt, RelaPlt, GotPlt; for (const SectionRef &Section : sections()) { Expected NameOrErr = Section.getName(); if (!NameOrErr) { @@ -673,9 +674,8 @@ } template -Expected> -readBBAddrMapImpl(const ELFFile &EF, - Optional TextSectionIndex) { +Expected> static readBBAddrMapImpl( + const ELFFile &EF, Optional TextSectionIndex) { using Elf_Shdr = typename ELFT::Shdr; std::vector BBAddrMaps; const auto &Sections = cantFail(EF.sections()); diff --git a/llvm/lib/ObjectYAML/COFFEmitter.cpp b/llvm/lib/ObjectYAML/COFFEmitter.cpp --- a/llvm/lib/ObjectYAML/COFFEmitter.cpp +++ b/llvm/lib/ObjectYAML/COFFEmitter.cpp @@ -456,8 +456,7 @@ ++I) { const Optional *DataDirectories = CP.Obj.OptionalHeader->DataDirectories; - uint32_t NumDataDir = sizeof(CP.Obj.OptionalHeader->DataDirectories) / - sizeof(Optional); + uint32_t NumDataDir = std::size(CP.Obj.OptionalHeader->DataDirectories); if (I >= NumDataDir || !DataDirectories[I]) { OS << zeros(uint32_t(0)); OS << zeros(uint32_t(0)); diff --git a/llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp b/llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp --- a/llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp +++ b/llvm/lib/ObjectYAML/CodeViewYAMLSymbols.cpp @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -151,7 +152,7 @@ const auto *Header = static_cast(io.getContext()); assert(Header && "The IO context is not initialized"); - Optional CpuType; + std::optional CpuType; ArrayRef> RegNames; switch (Header->Machine) { diff --git a/llvm/lib/ObjectYAML/MinidumpEmitter.cpp b/llvm/lib/ObjectYAML/MinidumpEmitter.cpp --- a/llvm/lib/ObjectYAML/MinidumpEmitter.cpp +++ b/llvm/lib/ObjectYAML/MinidumpEmitter.cpp @@ -10,6 +10,7 @@ #include "llvm/ObjectYAML/yaml2obj.h" #include "llvm/Support/ConvertUTF.h" #include "llvm/Support/raw_ostream.h" +#include using namespace llvm; using namespace llvm::minidump; @@ -173,7 +174,7 @@ Directory Result; Result.Type = S.Type; Result.Location.RVA = File.tell(); - Optional DataEnd; + std::optional DataEnd; switch (S.Kind) { case Stream::StreamKind::Exception: DataEnd = layout(File, cast(S)); diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -253,6 +253,7 @@ #include "llvm/Transforms/Vectorize/LoopVectorize.h" #include "llvm/Transforms/Vectorize/SLPVectorizer.h" #include "llvm/Transforms/Vectorize/VectorCombine.h" +#include using namespace llvm; @@ -471,7 +472,7 @@ C(LAM); } -static Optional parseRepeatPassName(StringRef Name) { +static std::optional parseRepeatPassName(StringRef Name) { if (!Name.consume_front("repeat<") || !Name.consume_back(">")) return None; int Count; @@ -480,7 +481,7 @@ return Count; } -static Optional parseDevirtPassName(StringRef Name) { +static std::optional parseDevirtPassName(StringRef Name) { if (!Name.consume_front("devirt<") || !Name.consume_back(">")) return None; int Count; diff --git a/llvm/lib/Passes/PassBuilderBindings.cpp b/llvm/lib/Passes/PassBuilderBindings.cpp --- a/llvm/lib/Passes/PassBuilderBindings.cpp +++ b/llvm/lib/Passes/PassBuilderBindings.cpp @@ -65,7 +65,7 @@ PB.registerModuleAnalyses(MAM); PB.crossRegisterProxies(LAM, FAM, CGAM, MAM); - StandardInstrumentations SI(Debug, VerifyEach); + StandardInstrumentations SI(Mod->getContext(), Debug, VerifyEach); SI.registerCallbacks(PIC, &FAM); ModulePassManager MPM; if (VerifyEach) { diff --git a/llvm/lib/Passes/StandardInstrumentations.cpp b/llvm/lib/Passes/StandardInstrumentations.cpp --- a/llvm/lib/Passes/StandardInstrumentations.cpp +++ b/llvm/lib/Passes/StandardInstrumentations.cpp @@ -71,22 +71,23 @@ // An option that determines the colour used for elements that are only // in the before part. Must be a colour named in appendix J of // https://graphviz.org/pdf/dotguide.pdf -cl::opt +static cl::opt BeforeColour("dot-cfg-before-color", - cl::desc("Color for dot-cfg before elements."), cl::Hidden, + cl::desc("Color for dot-cfg before elements"), cl::Hidden, cl::init("red")); // An option that determines the colour used for elements that are only // in the after part. Must be a colour named in appendix J of // https://graphviz.org/pdf/dotguide.pdf -cl::opt AfterColour("dot-cfg-after-color", - cl::desc("Color for dot-cfg after elements."), - cl::Hidden, cl::init("forestgreen")); +static cl::opt + AfterColour("dot-cfg-after-color", + cl::desc("Color for dot-cfg after elements"), cl::Hidden, + cl::init("forestgreen")); // An option that determines the colour used for elements that are in both // the before and after parts. Must be a colour named in appendix J of // https://graphviz.org/pdf/dotguide.pdf -cl::opt +static cl::opt CommonColour("dot-cfg-common-color", - cl::desc("Color for dot-cfg common elements."), cl::Hidden, + cl::desc("Color for dot-cfg common elements"), cl::Hidden, cl::init("black")); // An option that determines where the generated website file (named @@ -100,7 +101,7 @@ static cl::opt PrintCrashIR("print-on-crash", cl::desc("Print the last form of the IR before crash"), - cl::init(false), cl::Hidden); + cl::Hidden); static cl::opt OptBisectPrintIRPath( "opt-bisect-print-ir-path", @@ -766,27 +767,35 @@ return ShouldRun; } -void OptBisectInstrumentation::registerCallbacks( +bool OptPassGateInstrumentation::shouldRun(StringRef PassName, Any IR) { + if (isIgnored(PassName)) + return true; + + bool ShouldRun = + Context.getOptPassGate().shouldRunPass(PassName, getIRName(IR)); + if (!ShouldRun && !this->HasWrittenIR && !OptBisectPrintIRPath.empty()) { + // FIXME: print IR if limit is higher than number of opt-bisect + // invocations + this->HasWrittenIR = true; + const Module *M = unwrapModule(IR, /*Force=*/true); + assert((M && &M->getContext() == &Context) && "Missing/Mismatching Module"); + std::error_code EC; + raw_fd_ostream OS(OptBisectPrintIRPath, EC); + if (EC) + report_fatal_error(errorCodeToError(EC)); + M->print(OS, nullptr); + } + return ShouldRun; +} + +void OptPassGateInstrumentation::registerCallbacks( PassInstrumentationCallbacks &PIC) { - if (!getOptBisector().isEnabled()) + OptPassGate &PassGate = Context.getOptPassGate(); + if (!PassGate.isEnabled()) return; - PIC.registerShouldRunOptionalPassCallback([this](StringRef PassID, Any IR) { - if (isIgnored(PassID)) - return true; - bool ShouldRun = getOptBisector().checkPass(PassID, getIRName(IR)); - if (!ShouldRun && !this->HasWrittenIR && !OptBisectPrintIRPath.empty()) { - // FIXME: print IR if limit is higher than number of opt-bisect - // invocations - this->HasWrittenIR = true; - const Module *M = unwrapModule(IR, /*Force=*/true); - assert(M && "expected Module"); - std::error_code EC; - raw_fd_ostream OS(OptBisectPrintIRPath, EC); - if (EC) - report_fatal_error(errorCodeToError(EC)); - M->print(OS, nullptr); - } - return ShouldRun; + + PIC.registerShouldRunOptionalPassCallback([this](StringRef PassName, Any IR) { + return this->shouldRun(PassName, IR); }); } @@ -2036,8 +2045,11 @@ } StandardInstrumentations::StandardInstrumentations( - bool DebugLogging, bool VerifyEach, PrintPassOptions PrintPassOpts) - : PrintPass(DebugLogging, PrintPassOpts), OptNone(DebugLogging), + LLVMContext &Context, bool DebugLogging, bool VerifyEach, + PrintPassOptions PrintPassOpts) + : PrintPass(DebugLogging, PrintPassOpts), + OptNone(DebugLogging), + OptPassGate(Context), PrintChangedIR(PrintChanged == ChangePrinter::Verbose), PrintChangedDiff(PrintChanged == ChangePrinter::DiffVerbose || PrintChanged == ChangePrinter::ColourDiffVerbose, @@ -2098,7 +2110,7 @@ PrintPass.registerCallbacks(PIC); TimePasses.registerCallbacks(PIC); OptNone.registerCallbacks(PIC); - OptBisect.registerCallbacks(PIC); + OptPassGate.registerCallbacks(PIC); if (FAM) PreservedCFGChecker.registerCallbacks(PIC, *FAM); PrintChangedIR.registerCallbacks(PIC); diff --git a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp --- a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp +++ b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -458,7 +459,7 @@ /// \p Loc: The start location of the next region. If None, all active /// regions are completed. /// \p FirstCompletedRegion: Index of the first completed region. - void completeRegionsUntil(Optional Loc, + void completeRegionsUntil(std::optional Loc, unsigned FirstCompletedRegion) { // Sort the completed regions by end location. This makes it simple to // emit closing segments in sorted order. diff --git a/llvm/lib/ProfileData/GCOV.cpp b/llvm/lib/ProfileData/GCOV.cpp --- a/llvm/lib/ProfileData/GCOV.cpp +++ b/llvm/lib/ProfileData/GCOV.cpp @@ -23,6 +23,7 @@ #include "llvm/Support/Path.h" #include "llvm/Support/raw_ostream.h" #include +#include #include using namespace llvm; @@ -878,7 +879,7 @@ if (options.NoOutput || options.Intermediate) continue; - Optional os; + std::optional os; if (!options.UseStdout) { std::error_code ec; os.emplace(gcovName, ec, sys::fs::OF_TextWithCRLF); diff --git a/llvm/lib/ProfileData/InstrProfWriter.cpp b/llvm/lib/ProfileData/InstrProfWriter.cpp --- a/llvm/lib/ProfileData/InstrProfWriter.cpp +++ b/llvm/lib/ProfileData/InstrProfWriter.cpp @@ -490,7 +490,7 @@ {CSSummaryOffset, reinterpret_cast(TheCSSummary.get()), (int)CSSummarySize}}; - OS.patch(PatchItems, sizeof(PatchItems) / sizeof(*PatchItems)); + OS.patch(PatchItems, std::size(PatchItems)); for (const auto &I : FunctionData) for (const auto &F : I.getValue()) diff --git a/llvm/lib/ProfileData/ProfileSummaryBuilder.cpp b/llvm/lib/ProfileData/ProfileSummaryBuilder.cpp --- a/llvm/lib/ProfileData/ProfileSummaryBuilder.cpp +++ b/llvm/lib/ProfileData/ProfileSummaryBuilder.cpp @@ -18,6 +18,7 @@ using namespace llvm; +namespace llvm { cl::opt UseContextLessSummary( "profile-summary-contextless", cl::Hidden, cl::desc("Merge context profiles before calculating thresholds.")); @@ -64,6 +65,7 @@ "profile-summary-cold-count", cl::ReallyHidden, cl::desc("A fixed cold count that overrides the count derived from" " profile-summary-cutoff-cold")); +} // namespace llvm // A set of cutoff values. Each value, when divided by ProfileSummary::Scale // (which is 1000000) is a desired percentile of total counts. diff --git a/llvm/lib/Remarks/RemarkParser.cpp b/llvm/lib/Remarks/RemarkParser.cpp --- a/llvm/lib/Remarks/RemarkParser.cpp +++ b/llvm/lib/Remarks/RemarkParser.cpp @@ -16,6 +16,7 @@ #include "YAMLRemarkParser.h" #include "llvm-c/Remarks.h" #include "llvm/Support/CBindingWrapping.h" +#include using namespace llvm; using namespace llvm::remarks; @@ -109,10 +110,10 @@ // Wrapper that holds the state needed to interact with the C API. struct CParser { std::unique_ptr TheParser; - Optional Err; + std::optional Err; CParser(Format ParserFormat, StringRef Buf, - Optional StrTab = None) + std::optional StrTab = None) : TheParser(cantFail( StrTab ? createRemarkParser(ParserFormat, Buf, std::move(*StrTab)) : createRemarkParser(ParserFormat, Buf))) {} diff --git a/llvm/lib/Remarks/YAMLRemarkParser.cpp b/llvm/lib/Remarks/YAMLRemarkParser.cpp --- a/llvm/lib/Remarks/YAMLRemarkParser.cpp +++ b/llvm/lib/Remarks/YAMLRemarkParser.cpp @@ -15,6 +15,7 @@ #include "llvm/ADT/StringSwitch.h" #include "llvm/Support/Endian.h" #include "llvm/Support/Path.h" +#include using namespace llvm; using namespace llvm::remarks; @@ -322,9 +323,9 @@ if (!DebugLoc) return error("expected a value of mapping type.", Node); - Optional File; - Optional Line; - Optional Column; + std::optional File; + std::optional Line; + std::optional Column; for (yaml::KeyValueNode &DLNode : *DebugLoc) { Expected MaybeKey = parseKey(DLNode); @@ -364,8 +365,8 @@ if (!ArgMap) return error("expected a value of mapping type.", Node); - Optional KeyStr; - Optional ValueStr; + std::optional KeyStr; + std::optional ValueStr; Optional Loc; for (yaml::KeyValueNode &ArgEntry : *ArgMap) { diff --git a/llvm/lib/Remarks/YAMLRemarkSerializer.cpp b/llvm/lib/Remarks/YAMLRemarkSerializer.cpp --- a/llvm/lib/Remarks/YAMLRemarkSerializer.cpp +++ b/llvm/lib/Remarks/YAMLRemarkSerializer.cpp @@ -14,6 +14,7 @@ #include "llvm/Remarks/YAMLRemarkSerializer.h" #include "llvm/Remarks/Remark.h" #include "llvm/Support/FileSystem.h" +#include using namespace llvm; using namespace llvm::remarks; @@ -216,7 +217,8 @@ OS.write(Version.data(), Version.size()); } -static void emitStrTab(raw_ostream &OS, Optional StrTab) { +static void emitStrTab(raw_ostream &OS, + std::optional StrTab) { // Emit the string table in the section. uint64_t StrTabSize = StrTab ? (*StrTab)->SerializedSize : 0; // Emit the total size of the string table (the size itself excluded): diff --git a/llvm/lib/Support/ARMAttributeParser.cpp b/llvm/lib/Support/ARMAttributeParser.cpp --- a/llvm/lib/Support/ARMAttributeParser.cpp +++ b/llvm/lib/Support/ARMAttributeParser.cpp @@ -11,6 +11,7 @@ #include "llvm/Support/ARMBuildAttributes.h" #include "llvm/Support/Errc.h" #include "llvm/Support/ScopedPrinter.h" +#include using namespace llvm; using namespace llvm::ARMBuildAttrs; @@ -385,7 +386,7 @@ Error ARMAttributeParser::also_compatible_with(AttrType tag) { // Parse value as a C string first in order to print it in escaped form later. // Then, parse it again to catch errors or to pretty print if Tag_CPU_arch. - Optional returnValue; + std::optional returnValue; SmallString<8> Description; raw_svector_ostream DescStream(Description); diff --git a/llvm/lib/Support/ARMTargetParserCommon.cpp b/llvm/lib/Support/ARMTargetParserCommon.cpp --- a/llvm/lib/Support/ARMTargetParserCommon.cpp +++ b/llvm/lib/Support/ARMTargetParserCommon.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "llvm/Support/ARMTargetParserCommon.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringSwitch.h" using namespace llvm; @@ -130,3 +131,51 @@ return EndianKind::INVALID; } + +// Parse a branch protection specification, which has the form +// standard | none | [bti,pac-ret[+b-key,+leaf]*] +// Returns true on success, with individual elements of the specification +// returned in `PBP`. Returns false in error, with `Err` containing +// an erroneous part of the spec. +bool ARM::parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP, + StringRef &Err) { + PBP = {"none", "a_key", false}; + if (Spec == "none") + return true; // defaults are ok + + if (Spec == "standard") { + PBP.Scope = "non-leaf"; + PBP.BranchTargetEnforcement = true; + return true; + } + + SmallVector Opts; + Spec.split(Opts, "+"); + for (int I = 0, E = Opts.size(); I != E; ++I) { + StringRef Opt = Opts[I].trim(); + if (Opt == "bti") { + PBP.BranchTargetEnforcement = true; + continue; + } + if (Opt == "pac-ret") { + PBP.Scope = "non-leaf"; + for (; I + 1 != E; ++I) { + StringRef PACOpt = Opts[I + 1].trim(); + if (PACOpt == "leaf") + PBP.Scope = "all"; + else if (PACOpt == "b-key") + PBP.Key = "b_key"; + else + break; + } + continue; + } + if (Opt == "") + Err = ""; + else + Err = Opt; + return false; + } + + return true; +} diff --git a/llvm/lib/Support/FormatVariadic.cpp b/llvm/lib/Support/FormatVariadic.cpp --- a/llvm/lib/Support/FormatVariadic.cpp +++ b/llvm/lib/Support/FormatVariadic.cpp @@ -7,10 +7,11 @@ #include "llvm/Support/FormatVariadic.h" #include +#include using namespace llvm; -static Optional translateLocChar(char C) { +static std::optional translateLocChar(char C) { switch (C) { case '-': return AlignStyle::Left; diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp --- a/llvm/lib/Support/Host.cpp +++ b/llvm/lib/Support/Host.cpp @@ -1580,7 +1580,7 @@ // On Linux, the number of physical cores can be computed from /proc/cpuinfo, // using the number of unique physical/core id pairs. The following // implementation reads the /proc/cpuinfo format on an x86_64 system. -int computeHostNumPhysicalCores() { +static int computeHostNumPhysicalCores() { // Enabled represents the number of physical id/core id pairs with at least // one processor id enabled by the CPU affinity mask. cpu_set_t Affinity, Enabled; @@ -1625,9 +1625,11 @@ return CPU_COUNT(&Enabled); } #elif defined(__linux__) && defined(__s390x__) -int computeHostNumPhysicalCores() { return sysconf(_SC_NPROCESSORS_ONLN); } +static int computeHostNumPhysicalCores() { + return sysconf(_SC_NPROCESSORS_ONLN); +} #elif defined(__linux__) && !defined(__ANDROID__) -int computeHostNumPhysicalCores() { +static int computeHostNumPhysicalCores() { cpu_set_t Affinity; if (sched_getaffinity(0, sizeof(Affinity), &Affinity) == 0) return CPU_COUNT(&Affinity); @@ -1647,7 +1649,7 @@ } #elif defined(__APPLE__) // Gets the number of *physical cores* on the machine. -int computeHostNumPhysicalCores() { +static int computeHostNumPhysicalCores() { uint32_t count; size_t len = sizeof(count); sysctlbyname("hw.physicalcpu", &count, &len, NULL, 0); @@ -1662,7 +1664,7 @@ return count; } #elif defined(__MVS__) -int computeHostNumPhysicalCores() { +static int computeHostNumPhysicalCores() { enum { // Byte offset of the pointer to the Communications Vector Table (CVT) in // the Prefixed Save Area (PSA). The table entry is a 31-bit pointer and diff --git a/llvm/lib/Support/JSON.cpp b/llvm/lib/Support/JSON.cpp --- a/llvm/lib/Support/JSON.cpp +++ b/llvm/lib/Support/JSON.cpp @@ -14,6 +14,7 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/Support/NativeFormatting.h" #include +#include namespace llvm { namespace json { @@ -408,7 +409,7 @@ C == 'e' || C == 'E' || C == '+' || C == '-' || C == '.'; } - Optional Err; + std::optional Err; const char *Start, *P, *End; }; diff --git a/llvm/lib/Support/Optional.cpp b/llvm/lib/Support/Optional.cpp --- a/llvm/lib/Support/Optional.cpp +++ b/llvm/lib/Support/Optional.cpp @@ -9,6 +9,6 @@ #include "llvm/ADT/Optional.h" #include "llvm/Support/raw_ostream.h" -llvm::raw_ostream &llvm::operator<<(raw_ostream &OS, NoneType) { +llvm::raw_ostream &llvm::operator<<(raw_ostream &OS, std::nullopt_t) { return OS << "None"; } diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -17,6 +17,7 @@ #include "llvm/Support/raw_ostream.h" #include +#include #include #include @@ -111,6 +112,7 @@ {"zihintntl", RISCVExtensionVersion{0, 2}}, {"zca", RISCVExtensionVersion{0, 70}}, + {"zcd", RISCVExtensionVersion{0, 70}}, {"zcf", RISCVExtensionVersion{0, 70}}, {"zvfh", RISCVExtensionVersion{0, 1}}, {"zawrs", RISCVExtensionVersion{1, 0}}, @@ -143,6 +145,7 @@ return Pos; } +namespace { struct FindByName { FindByName(StringRef Ext) : Ext(Ext){}; StringRef Ext; @@ -150,8 +153,10 @@ return ExtInfo.Name == Ext; } }; +} // namespace -static Optional findDefaultVersion(StringRef ExtName) { +static std::optional +findDefaultVersion(StringRef ExtName) { // Find default version of an extension. // TODO: We might set default version based on profile or ISA spec. for (auto &ExtInfo : {makeArrayRef(SupportedExtensions), @@ -199,7 +204,8 @@ return StringRef(); } -static Optional isExperimentalExtension(StringRef Ext) { +static std::optional +isExperimentalExtension(StringRef Ext) { auto ExtIterator = llvm::find_if(SupportedExperimentalExtensions, FindByName(Ext)); if (ExtIterator == std::end(SupportedExperimentalExtensions)) diff --git a/llvm/lib/Support/TargetParser.cpp b/llvm/lib/Support/TargetParser.cpp --- a/llvm/lib/Support/TargetParser.cpp +++ b/llvm/lib/Support/TargetParser.cpp @@ -337,51 +337,3 @@ } // namespace RISCV } // namespace llvm - -// Parse a branch protection specification, which has the form -// standard | none | [bti,pac-ret[+b-key,+leaf]*] -// Returns true on success, with individual elements of the specification -// returned in `PBP`. Returns false in error, with `Err` containing -// an erroneous part of the spec. -bool ARM::parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP, - StringRef &Err) { - PBP = {"none", "a_key", false}; - if (Spec == "none") - return true; // defaults are ok - - if (Spec == "standard") { - PBP.Scope = "non-leaf"; - PBP.BranchTargetEnforcement = true; - return true; - } - - SmallVector Opts; - Spec.split(Opts, "+"); - for (int I = 0, E = Opts.size(); I != E; ++I) { - StringRef Opt = Opts[I].trim(); - if (Opt == "bti") { - PBP.BranchTargetEnforcement = true; - continue; - } - if (Opt == "pac-ret") { - PBP.Scope = "non-leaf"; - for (; I + 1 != E; ++I) { - StringRef PACOpt = Opts[I + 1].trim(); - if (PACOpt == "leaf") - PBP.Scope = "all"; - else if (PACOpt == "b-key") - PBP.Key = "b_key"; - else - break; - } - continue; - } - if (Opt == "") - Err = ""; - else - Err = Opt; - return false; - } - - return true; -} diff --git a/llvm/lib/Support/Threading.cpp b/llvm/lib/Support/Threading.cpp --- a/llvm/lib/Support/Threading.cpp +++ b/llvm/lib/Support/Threading.cpp @@ -47,7 +47,7 @@ #else -int computeHostNumHardwareThreads(); +static int computeHostNumHardwareThreads(); unsigned llvm::ThreadPoolStrategy::compute_thread_count() const { int MaxThreadCount = UseHyperThreads ? computeHostNumHardwareThreads() diff --git a/llvm/lib/Support/Unicode.cpp b/llvm/lib/Support/Unicode.cpp --- a/llvm/lib/Support/Unicode.cpp +++ b/llvm/lib/Support/Unicode.cpp @@ -300,8 +300,7 @@ /// * 0 for non-spacing and enclosing combining marks; /// * 2 for CJK characters excluding halfwidth forms; /// * 1 for all remaining characters. -static inline int charWidth(int UCS) -{ +static inline int charWidth(int UCS) { if (!isPrintable(UCS)) return ErrorNonPrintableCharacter; @@ -430,26 +429,45 @@ if (CombiningCharacters.contains(UCS)) return 0; + // We consider double width codepoints any codepoint with + // the property East_Asian_Width=F|W + // + Misc Symbols and Pictographs (U+1F300...U+1F5FF) + // + Supplemental Symbols and Pictographs (U+1F900...U+1F9FF) static const UnicodeCharRange DoubleWidthCharacterRanges[] = { - // Hangul Jamo - { 0x1100, 0x11FF }, - // Deprecated fullwidth angle brackets - { 0x2329, 0x232A }, - // CJK Misc, CJK Unified Ideographs, Yijing Hexagrams, Yi - // excluding U+303F (IDEOGRAPHIC HALF FILL SPACE) - { 0x2E80, 0x303E }, { 0x3040, 0xA4CF }, - // Hangul - { 0xAC00, 0xD7A3 }, { 0xD7B0, 0xD7C6 }, { 0xD7CB, 0xD7FB }, - // CJK Unified Ideographs - { 0xF900, 0xFAFF }, - // Vertical forms - { 0xFE10, 0xFE19 }, - // CJK Compatibility Forms + Small Form Variants - { 0xFE30, 0xFE6F }, - // Fullwidth forms - { 0xFF01, 0xFF60 }, { 0xFFE0, 0xFFE6 }, - // CJK Unified Ideographs - { 0x20000, 0x2A6DF }, { 0x2A700, 0x2B81F }, { 0x2F800, 0x2FA1F } + {0x1100, 0x115F}, {0x231A, 0x231B}, {0x2329, 0x232A}, + {0x23E9, 0x23EC}, {0x23F0, 0x23F0}, {0x23F3, 0x23F3}, + {0x25FD, 0x25FE}, {0x2614, 0x2615}, {0x2648, 0x2653}, + {0x267F, 0x267F}, {0x2693, 0x2693}, {0x26A1, 0x26A1}, + {0x26AA, 0x26AB}, {0x26BD, 0x26BE}, {0x26C4, 0x26C5}, + {0x26CE, 0x26CE}, {0x26D4, 0x26D4}, {0x26EA, 0x26EA}, + {0x26F2, 0x26F3}, {0x26F5, 0x26F5}, {0x26FA, 0x26FA}, + {0x26FD, 0x26FD}, {0x2705, 0x2705}, {0x270A, 0x270B}, + {0x2728, 0x2728}, {0x274C, 0x274C}, {0x274E, 0x274E}, + {0x2753, 0x2755}, {0x2757, 0x2757}, {0x2795, 0x2797}, + {0x27B0, 0x27B0}, {0x27BF, 0x27BF}, {0x2B1B, 0x2B1C}, + {0x2B50, 0x2B50}, {0x2B55, 0x2B55}, {0x2E80, 0x2E99}, + {0x2E9B, 0x2EF3}, {0x2F00, 0x2FD5}, {0x2FF0, 0x2FFB}, + {0x3000, 0x303E}, {0x3041, 0x3096}, {0x3099, 0x30FF}, + {0x3105, 0x312F}, {0x3131, 0x318E}, {0x3190, 0x31E3}, + {0x31F0, 0x321E}, {0x3220, 0x3247}, {0x3250, 0xA48C}, + {0xA490, 0xA4C6}, {0xA960, 0xA97C}, {0xAC00, 0xD7A3}, + {0xF900, 0xFAFF}, {0xFE10, 0xFE19}, {0xFE30, 0xFE52}, + {0xFE54, 0xFE66}, {0xFE68, 0xFE6B}, {0xFF01, 0xFF60}, + {0xFFE0, 0xFFE6}, {0x16FE0, 0x16FE4}, {0x16FF0, 0x16FF1}, + {0x17000, 0x187F7}, {0x18800, 0x18CD5}, {0x18D00, 0x18D08}, + {0x1AFF0, 0x1AFF3}, {0x1AFF5, 0x1AFFB}, {0x1AFFD, 0x1AFFE}, + {0x1B000, 0x1B122}, {0x1B132, 0x1B132}, {0x1B150, 0x1B152}, + {0x1B155, 0x1B155}, {0x1B164, 0x1B167}, {0x1B170, 0x1B2FB}, + {0x1F004, 0x1F004}, {0x1F0CF, 0x1F0CF}, {0x1F18E, 0x1F18E}, + {0x1F191, 0x1F19A}, {0x1F200, 0x1F202}, {0x1F210, 0x1F23B}, + {0x1F240, 0x1F248}, {0x1F250, 0x1F251}, {0x1F260, 0x1F265}, + {0x1F300, 0x1F64F}, {0x1F680, 0x1F6C5}, {0x1F6CC, 0x1F6CC}, + {0x1F6D0, 0x1F6D2}, {0x1F6D5, 0x1F6D7}, {0x1F6DC, 0x1F6DF}, + {0x1F6EB, 0x1F6EC}, {0x1F6F4, 0x1F6FC}, {0x1F7E0, 0x1F7EB}, + {0x1F7F0, 0x1F7F0}, {0x1F900, 0x1F9FF}, {0x1FA70, 0x1FA7C}, + {0x1FA80, 0x1FA88}, {0x1FA90, 0x1FABD}, {0x1FABF, 0x1FAC5}, + {0x1FACE, 0x1FADB}, {0x1FAE0, 0x1FAE8}, {0x1FAF0, 0x1FAF8}, + {0x20000, 0x2FFFD}, {0x30000, 0x3FFFD} }; static const UnicodeCharSet DoubleWidthCharacters(DoubleWidthCharacterRanges); @@ -493,4 +511,3 @@ } // namespace unicode } // namespace sys } // namespace llvm - diff --git a/llvm/lib/Support/Unix/COM.inc b/llvm/lib/Support/Unix/COM.inc --- a/llvm/lib/Support/Unix/COM.inc +++ b/llvm/lib/Support/Unix/COM.inc @@ -22,5 +22,5 @@ bool SpeedOverMemory) {} InitializeCOMRAII::~InitializeCOMRAII() = default; -} -} +} // namespace sys +} // namespace llvm diff --git a/llvm/lib/Support/Unix/DynamicLibrary.inc b/llvm/lib/Support/Unix/DynamicLibrary.inc --- a/llvm/lib/Support/Unix/DynamicLibrary.inc +++ b/llvm/lib/Support/Unix/DynamicLibrary.inc @@ -25,9 +25,10 @@ } void *DynamicLibrary::HandleSet::DLOpen(const char *File, std::string *Err) { - void *Handle = ::dlopen(File, RTLD_LAZY|RTLD_GLOBAL); + void *Handle = ::dlopen(File, RTLD_LAZY | RTLD_GLOBAL); if (!Handle) { - if (Err) *Err = ::dlerror(); + if (Err) + *Err = ::dlerror(); return &DynamicLibrary::Invalid; } @@ -41,9 +42,7 @@ return Handle; } -void DynamicLibrary::HandleSet::DLClose(void *Handle) { - ::dlclose(Handle); -} +void DynamicLibrary::HandleSet::DLClose(void *Handle) { ::dlclose(Handle); } void *DynamicLibrary::HandleSet::DLSym(void *Handle, const char *Symbol) { return ::dlsym(Handle, Symbol); @@ -54,12 +53,12 @@ DynamicLibrary::HandleSet::~HandleSet() {} void *DynamicLibrary::HandleSet::DLOpen(const char *File, std::string *Err) { - if (Err) *Err = "dlopen() not supported on this platform"; + if (Err) + *Err = "dlopen() not supported on this platform"; return &Invalid; } -void DynamicLibrary::HandleSet::DLClose(void *Handle) { -} +void DynamicLibrary::HandleSet::DLClose(void *Handle) {} void *DynamicLibrary::HandleSet::DLSym(void *Handle, const char *Symbol) { return nullptr; @@ -68,9 +67,11 @@ #endif // Must declare the symbols in the global namespace. -static void *DoSearch(const char* SymbolName) { -#define EXPLICIT_SYMBOL(SYM) \ - extern void *SYM; if (!strcmp(SymbolName, #SYM)) return (void*)&SYM +static void *DoSearch(const char *SymbolName) { +#define EXPLICIT_SYMBOL(SYM) \ + extern void *SYM; \ + if (!strcmp(SymbolName, #SYM)) \ + return (void *)&SYM // If this is darwin, it has some funky issues, try to solve them here. Some // important symbols are marked 'private external' which doesn't allow @@ -101,8 +102,9 @@ #undef EXPLICIT_SYMBOL // This macro returns the address of a well-known, explicit symbol -#define EXPLICIT_SYMBOL(SYM) \ - if (!strcmp(SymbolName, #SYM)) return &SYM +#define EXPLICIT_SYMBOL(SYM) \ + if (!strcmp(SymbolName, #SYM)) \ + return &SYM // Under glibc we have a weird situation. The stderr/out/in symbols are both // macros and global variables because of standards requirements. So, we diff --git a/llvm/lib/Support/Unix/Memory.inc b/llvm/lib/Support/Unix/Memory.inc --- a/llvm/lib/Support/Unix/Memory.inc +++ b/llvm/lib/Support/Unix/Memory.inc @@ -33,7 +33,7 @@ #if defined(__APPLE__) extern "C" void sys_icache_invalidate(const void *Addr, size_t len); #else -extern "C" void __clear_cache(void *, void*); +extern "C" void __clear_cache(void *, void *); #endif static int getPosixProtectionFlags(unsigned Flags) { @@ -42,9 +42,9 @@ return PROT_READ; case llvm::sys::Memory::MF_WRITE: return PROT_WRITE; - case llvm::sys::Memory::MF_READ|llvm::sys::Memory::MF_WRITE: + case llvm::sys::Memory::MF_READ | llvm::sys::Memory::MF_WRITE: return PROT_READ | PROT_WRITE; - case llvm::sys::Memory::MF_READ|llvm::sys::Memory::MF_EXEC: + case llvm::sys::Memory::MF_READ | llvm::sys::Memory::MF_EXEC: return PROT_READ | PROT_EXEC; case llvm::sys::Memory::MF_READ | llvm::sys::Memory::MF_WRITE | llvm::sys::Memory::MF_EXEC: @@ -70,11 +70,9 @@ namespace llvm { namespace sys { -MemoryBlock -Memory::allocateMappedMemory(size_t NumBytes, - const MemoryBlock *const NearBlock, - unsigned PFlags, - std::error_code &EC) { +MemoryBlock Memory::allocateMappedMemory(size_t NumBytes, + const MemoryBlock *const NearBlock, + unsigned PFlags, std::error_code &EC) { EC = std::error_code(); if (NumBytes == 0) return MemoryBlock(); @@ -105,18 +103,19 @@ // Use any near hint and the page size to set a page-aligned starting address uintptr_t Start = NearBlock ? reinterpret_cast(NearBlock->base()) + - NearBlock->allocatedSize() : 0; + NearBlock->allocatedSize() + : 0; static const size_t PageSize = Process::getPageSizeEstimate(); - const size_t NumPages = (NumBytes+PageSize-1)/PageSize; + const size_t NumPages = (NumBytes + PageSize - 1) / PageSize; if (Start && Start % PageSize) Start += PageSize - Start % PageSize; // FIXME: Handle huge page requests (MF_HUGE_HINT). - void *Addr = ::mmap(reinterpret_cast(Start), PageSize*NumPages, Protect, - MMFlags, fd, 0); + void *Addr = ::mmap(reinterpret_cast(Start), PageSize * NumPages, + Protect, MMFlags, fd, 0); if (Addr == MAP_FAILED) { - if (NearBlock) { //Try again without a near hint + if (NearBlock) { // Try again without a near hint #if !defined(MAP_ANON) close(fd); #endif @@ -136,12 +135,12 @@ MemoryBlock Result; Result.Address = Addr; - Result.AllocatedSize = PageSize*NumPages; + Result.AllocatedSize = PageSize * NumPages; Result.Flags = PFlags; // Rely on protectMappedMemory to invalidate instruction cache. if (PFlags & MF_EXEC) { - EC = Memory::protectMappedMemory (Result, PFlags); + EC = Memory::protectMappedMemory(Result, PFlags); if (EC != std::error_code()) return MemoryBlock(); } @@ -149,8 +148,7 @@ return Result; } -std::error_code -Memory::releaseMappedMemory(MemoryBlock &M) { +std::error_code Memory::releaseMappedMemory(MemoryBlock &M) { if (M.Address == nullptr || M.AllocatedSize == 0) return std::error_code(); @@ -163,8 +161,8 @@ return std::error_code(); } -std::error_code -Memory::protectMappedMemory(const MemoryBlock &M, unsigned Flags) { +std::error_code Memory::protectMappedMemory(const MemoryBlock &M, + unsigned Flags) { static const Align PageSize = Align(Process::getPageSizeEstimate()); if (M.Address == nullptr || M.AllocatedSize == 0) return std::error_code(); @@ -173,15 +171,18 @@ return std::error_code(EINVAL, std::generic_category()); int Protect = getPosixProtectionFlags(Flags); - uintptr_t Start = alignAddr((const uint8_t *)M.Address - PageSize.value() + 1, PageSize); - uintptr_t End = alignAddr((const uint8_t *)M.Address + M.AllocatedSize, PageSize); + uintptr_t Start = + alignAddr((const uint8_t *)M.Address - PageSize.value() + 1, PageSize); + uintptr_t End = + alignAddr((const uint8_t *)M.Address + M.AllocatedSize, PageSize); bool InvalidateCache = (Flags & MF_EXEC); #if defined(__arm__) || defined(__aarch64__) - // Certain ARM implementations treat icache clear instruction as a memory read, - // and CPU segfaults on trying to clear cache on !PROT_READ page. Therefore we need - // to temporarily add PROT_READ for the sake of flushing the instruction caches. + // Certain ARM implementations treat icache clear instruction as a memory + // read, and CPU segfaults on trying to clear cache on !PROT_READ page. + // Therefore we need to temporarily add PROT_READ for the sake of flushing the + // instruction caches. if (InvalidateCache && !(Protect & PROT_READ)) { int Result = ::mprotect((void *)Start, End - Start, Protect | PROT_READ); if (Result != 0) @@ -206,15 +207,14 @@ /// InvalidateInstructionCache - Before the JIT can run a block of code /// that has been emitted it must invalidate the instruction cache on some /// platforms. -void Memory::InvalidateInstructionCache(const void *Addr, - size_t Len) { +void Memory::InvalidateInstructionCache(const void *Addr, size_t Len) { // icache invalidation for PPC and ARM. #if defined(__APPLE__) -# if (defined(__powerpc__) || defined(__arm__) || defined(__arm64__)) +#if (defined(__powerpc__) || defined(__arm__) || defined(__arm64__)) sys_icache_invalidate(const_cast(Addr), Len); -# endif +#endif #elif defined(__Fuchsia__) @@ -223,12 +223,12 @@ #else -# if defined(__powerpc__) && defined(__GNUC__) +#if defined(__powerpc__) && defined(__GNUC__) const size_t LineSize = 32; const intptr_t Mask = ~(LineSize - 1); - const intptr_t StartLine = ((intptr_t) Addr) & Mask; - const intptr_t EndLine = ((intptr_t) Addr + Len + LineSize - 1) & Mask; + const intptr_t StartLine = ((intptr_t)Addr) & Mask; + const intptr_t EndLine = ((intptr_t)Addr + Len + LineSize - 1) & Mask; for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize) asm volatile("dcbf 0, %0" : : "r"(Line)); @@ -237,15 +237,15 @@ for (intptr_t Line = StartLine; Line < EndLine; Line += LineSize) asm volatile("icbi 0, %0" : : "r"(Line)); asm volatile("isync"); -# elif (defined(__arm__) || defined(__aarch64__) || defined(__mips__)) && \ - defined(__GNUC__) +#elif (defined(__arm__) || defined(__aarch64__) || defined(__mips__)) && \ + defined(__GNUC__) // FIXME: Can we safely always call this for __GNUC__ everywhere? const char *Start = static_cast(Addr); const char *End = Start + Len; __clear_cache(const_cast(Start), const_cast(End)); -# endif +#endif -#endif // end apple +#endif // end apple ValgrindDiscardTranslations(Addr, Len); } diff --git a/llvm/lib/Support/Unix/Path.inc b/llvm/lib/Support/Unix/Path.inc --- a/llvm/lib/Support/Unix/Path.inc +++ b/llvm/lib/Support/Unix/Path.inc @@ -36,9 +36,9 @@ #include #ifdef __APPLE__ +#include #include #include -#include #if __has_include() #include #endif @@ -111,7 +111,7 @@ #define STATVFS_F_FRSIZE(vfs) static_cast(vfs.f_bsize) #endif -#if defined(__NetBSD__) || defined(__DragonFly__) || defined(__GNU__) || \ +#if defined(__NetBSD__) || defined(__DragonFly__) || defined(__GNU__) || \ defined(__MVS__) #define STATVFS_F_FLAG(vfs) (vfs).f_flag #else @@ -121,18 +121,16 @@ using namespace llvm; namespace llvm { -namespace sys { +namespace sys { namespace fs { const file_t kInvalidFile = -1; #if defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__) || \ defined(__minix) || defined(__FreeBSD_kernel__) || defined(__linux__) || \ - defined(__CYGWIN__) || defined(__DragonFly__) || defined(_AIX) || defined(__GNU__) || \ - (defined(__sun__) && defined(__svr4__)) -static int -test_dir(char ret[PATH_MAX], const char *dir, const char *bin) -{ + defined(__CYGWIN__) || defined(__DragonFly__) || defined(_AIX) || \ + defined(__GNU__) || (defined(__sun__) && defined(__svr4__)) +static int test_dir(char ret[PATH_MAX], const char *dir, const char *bin) { struct stat sb; char fullpath[PATH_MAX]; @@ -149,9 +147,7 @@ return 0; } -static char * -getprogpath(char ret[PATH_MAX], const char *bin) -{ +static char *getprogpath(char ret[PATH_MAX], const char *bin) { if (bin == nullptr) return nullptr; @@ -319,7 +315,7 @@ char real_path[PATH_MAX]; if (realpath(exe_path, real_path)) return std::string(real_path); - break; // Found entry, but realpath failed. + break; // Found entry, but realpath failed. } #elif defined(HAVE_DLFCN_H) && defined(HAVE_DLADDR) // Use dladdr to get executable path if available. @@ -351,9 +347,7 @@ return UniqueID(fs_st_dev, fs_st_ino); } -uint32_t file_status::getLinkCount() const { - return fs_st_nlinks; -} +uint32_t file_status::getLinkCount() const { return fs_st_nlinks; } ErrorOr disk_space(const Twine &Path) { struct STATVFS Vfs; @@ -513,7 +507,8 @@ // Haiku doesn't expose this information. return false; #elif defined(__sun) - // statvfs::f_basetype contains a null-terminated FSType name of the mounted target + // statvfs::f_basetype contains a null-terminated FSType name of the mounted + // target StringRef fstype(Vfs.f_basetype); // NFS is the only non-local fstype?? return !fstype.equals("nfs"); @@ -637,8 +632,7 @@ bool equivalent(file_status A, file_status B) { assert(status_known(A) && status_known(B)); - return A.fs_st_dev == B.fs_st_dev && - A.fs_st_ino == B.fs_st_ino; + return A.fs_st_dev == B.fs_st_dev && A.fs_st_ino == B.fs_st_ino; } std::error_code equivalent(const Twine &A, const Twine &B, bool &result) { @@ -697,7 +691,6 @@ llvm::sys::path::append(Path, Storage); } - void expand_tilde(const Twine &path, SmallVectorImpl &dest) { dest.clear(); if (path.isTriviallyEmpty()) @@ -749,9 +742,9 @@ perms Perms = static_cast(Status.st_mode) & all_perms; Result = file_status(typeForMode(Status.st_mode), Perms, Status.st_dev, - Status.st_nlink, Status.st_ino, - Status.st_atime, atime_nsec, Status.st_mtime, mtime_nsec, - Status.st_uid, Status.st_gid, Status.st_size); + Status.st_nlink, Status.st_ino, Status.st_atime, + atime_nsec, Status.st_mtime, mtime_nsec, Status.st_uid, + Status.st_gid, Status.st_size); return std::error_code(); } @@ -775,7 +768,7 @@ // Chose arbitary new mask and reset the umask to the old mask. // umask(2) never fails so ignore the return of the second call. unsigned Mask = ::umask(0); - (void) ::umask(Mask); + (void)::umask(Mask); return Mask; } @@ -881,9 +874,9 @@ void mapped_file_region::dontNeedImpl() { assert(Mode == mapped_file_region::readonly); if (!Mapping) - return; + return; #if defined(__MVS__) || defined(_AIX) - // If we don't have madvise, or it isn't beneficial, treat this as a no-op. + // If we don't have madvise, or it isn't beneficial, treat this as a no-op. #elif defined(POSIX_MADV_DONTNEED) ::posix_madvise(Mapping, Size, POSIX_MADV_DONTNEED); #else @@ -891,9 +884,7 @@ #endif } -int mapped_file_region::alignment() { - return Process::getPageSizeEstimate(); -} +int mapped_file_region::alignment() { return Process::getPageSizeEstimate(); } std::error_code detail::directory_iterator_construct(detail::DirIterState &it, StringRef path, @@ -918,7 +909,7 @@ return std::error_code(); } -static file_type direntType(dirent* Entry) { +static file_type direntType(dirent *Entry) { // Most platforms provide the file type in the dirent: Linux/BSD/Mac. // The DTTOIF macro lets us reuse our status -> type conversion. // Note that while glibc provides a macro to see if this is supported, @@ -1140,7 +1131,7 @@ return EC; // Attempt to get the real name of the file, if the user asked - if(!RealPath) + if (!RealPath) return std::error_code(); RealPath->clear(); #if defined(F_GETPATH) @@ -1192,8 +1183,7 @@ #else size_t Size = Buf.size(); #endif - ssize_t NumRead = - sys::RetryAfterSignal(-1, ::read, FD, Buf.data(), Size); + ssize_t NumRead = sys::RetryAfterSignal(-1, ::read, FD, Buf.data(), Size); if (ssize_t(NumRead) == -1) return errorCodeToError(std::error_code(errno, std::generic_category())); return NumRead; @@ -1212,8 +1202,7 @@ #else if (lseek(FD, Offset, SEEK_SET) == -1) return errorCodeToError(std::error_code(errno, std::generic_category())); - ssize_t NumRead = - sys::RetryAfterSignal(-1, ::read, FD, Buf.data(), Size); + ssize_t NumRead = sys::RetryAfterSignal(-1, ::read, FD, Buf.data(), Size); #endif if (NumRead == -1) return errorCodeToError(std::error_code(errno, std::generic_category())); @@ -1367,11 +1356,10 @@ } static bool getDarwinConfDir(bool TempDir, SmallVectorImpl &Result) { - #if defined(_CS_DARWIN_USER_TEMP_DIR) && defined(_CS_DARWIN_USER_CACHE_DIR) +#if defined(_CS_DARWIN_USER_TEMP_DIR) && defined(_CS_DARWIN_USER_CACHE_DIR) // On Darwin, use DARWIN_USER_TEMP_DIR or DARWIN_USER_CACHE_DIR. // macros defined in on darwin >= 9 - int ConfName = TempDir ? _CS_DARWIN_USER_TEMP_DIR - : _CS_DARWIN_USER_CACHE_DIR; + int ConfName = TempDir ? _CS_DARWIN_USER_TEMP_DIR : _CS_DARWIN_USER_CACHE_DIR; size_t ConfLen = confstr(ConfName, nullptr, 0); if (ConfLen > 0) { do { @@ -1387,7 +1375,7 @@ Result.clear(); } - #endif +#endif return false; } @@ -1417,7 +1405,7 @@ bool cache_directory(SmallVectorImpl &result) { #ifdef __APPLE__ - if (getDarwinConfDir(false/*tempDir*/, result)) { + if (getDarwinConfDir(false /*tempDir*/, result)) { return true; } #else @@ -1503,13 +1491,13 @@ auto Errno = errno; switch (Errno) { - case EEXIST: // To already exists. - case ENOTSUP: // Device does not support cloning. - case EXDEV: // From and To are on different devices. - break; - default: - // Anything else will also break copyfile(). - return std::error_code(Errno, std::generic_category()); + case EEXIST: // To already exists. + case ENOTSUP: // Device does not support cloning. + case EXDEV: // From and To are on different devices. + break; + default: + // Anything else will also break copyfile(). + return std::error_code(Errno, std::generic_category()); } // TODO: For EEXIST, profile calling fs::generateUniqueName() and diff --git a/llvm/lib/Support/Unix/Process.inc b/llvm/lib/Support/Unix/Process.inc --- a/llvm/lib/Support/Unix/Process.inc +++ b/llvm/lib/Support/Unix/Process.inc @@ -40,10 +40,10 @@ #include #endif #ifdef HAVE_SYS_IOCTL_H -# include +#include #endif #ifdef HAVE_TERMIOS_H -# include +#include #endif //===----------------------------------------------------------------------===// @@ -54,14 +54,15 @@ using namespace llvm; using namespace sys; -static std::pair getRUsageTimes() { +static std::pair +getRUsageTimes() { #if defined(HAVE_GETRUSAGE) struct rusage RU; ::getrusage(RUSAGE_SELF, &RU); - return { toDuration(RU.ru_utime), toDuration(RU.ru_stime) }; + return {toDuration(RU.ru_utime), toDuration(RU.ru_stime)}; #else #warning Cannot get usage times on this platform - return { std::chrono::microseconds::zero(), std::chrono::microseconds::zero() }; + return {std::chrono::microseconds::zero(), std::chrono::microseconds::zero()}; #endif } @@ -99,7 +100,7 @@ #elif defined(HAVE_MALLOC_ZONE_STATISTICS) && defined(HAVE_MALLOC_MALLOC_H) malloc_statistics_t Stats; malloc_zone_statistics(malloc_default_zone(), &Stats); - return Stats.size_in_use; // darwin + return Stats.size_in_use; // darwin #elif defined(HAVE_MALLCTL) size_t alloc, sz; sz = sizeof(size_t); @@ -109,9 +110,9 @@ #elif defined(HAVE_SBRK) // Note this is only an approximation and more closely resembles // the value returned by mallinfo in the arena field. - static char *StartOfMemory = reinterpret_cast(::sbrk(0)); - char *EndOfMemory = (char*)sbrk(0); - if (EndOfMemory != ((char*)-1) && StartOfMemory != ((char*)-1)) + static char *StartOfMemory = reinterpret_cast(::sbrk(0)); + char *EndOfMemory = (char *)sbrk(0); + if (EndOfMemory != ((char *)-1) && StartOfMemory != ((char *)-1)) return EndOfMemory - StartOfMemory; return 0; #else @@ -120,7 +121,8 @@ #endif } -void Process::GetTimeUsage(TimePoint<> &elapsed, std::chrono::nanoseconds &user_time, +void Process::GetTimeUsage(TimePoint<> &elapsed, + std::chrono::nanoseconds &user_time, std::chrono::nanoseconds &sys_time) { elapsed = std::chrono::system_clock::now(); std::tie(user_time, sys_time) = getRUsageTimes(); @@ -149,10 +151,9 @@ exception_port_t OriginalPorts[EXC_TYPES_COUNT]; exception_behavior_t OriginalBehaviors[EXC_TYPES_COUNT]; thread_state_flavor_t OriginalFlavors[EXC_TYPES_COUNT]; - kern_return_t err = - task_get_exception_ports(mach_task_self(), EXC_MASK_ALL, OriginalMasks, - &Count, OriginalPorts, OriginalBehaviors, - OriginalFlavors); + kern_return_t err = task_get_exception_ports( + mach_task_self(), EXC_MASK_ALL, OriginalMasks, &Count, OriginalPorts, + OriginalBehaviors, OriginalFlavors); if (err == KERN_SUCCESS) { // replace each with MACH_PORT_NULL. for (unsigned i = 0; i != Count; ++i) @@ -163,10 +164,10 @@ // Disable crash reporting on Mac OS X 10.5 signal(SIGABRT, _exit); - signal(SIGILL, _exit); - signal(SIGFPE, _exit); + signal(SIGILL, _exit); + signal(SIGFPE, _exit); signal(SIGSEGV, _exit); - signal(SIGBUS, _exit); + signal(SIGBUS, _exit); #endif coreFilesPrevented = true; @@ -197,7 +198,7 @@ int &FD; bool KeepOpen; }; -} +} // namespace std::error_code Process::FixupStandardFileDescriptors() { int NullFD = -1; @@ -239,7 +240,7 @@ if (sigfillset(&FullSet) < 0 || sigfillset(&SavedSet) < 0) return std::error_code(errno, std::generic_category()); - // Atomically swap our current signal mask with a full mask. + // Atomically swap our current signal mask with a full mask. #if LLVM_ENABLE_THREADS if (int EC = pthread_sigmask(SIG_SETMASK, &FullSet, &SavedSet)) return std::error_code(EC, std::generic_category()); @@ -329,15 +330,15 @@ bool checkTerminalEnvironmentForColors() { if (const char *TermStr = std::getenv("TERM")) { return StringSwitch(TermStr) - .Case("ansi", true) - .Case("cygwin", true) - .Case("linux", true) - .StartsWith("screen", true) - .StartsWith("xterm", true) - .StartsWith("vt100", true) - .StartsWith("rxvt", true) - .EndsWith("color", true) - .Default(false); + .Case("ansi", true) + .Case("cygwin", true) + .Case("linux", true) + .StartsWith("screen", true) + .StartsWith("xterm", true) + .StartsWith("vt100", true) + .StartsWith("rxvt", true) + .EndsWith("color", true) + .Default(false); } return false; @@ -370,7 +371,8 @@ // The 'tigetnum' routine returns -2 or -1 on errors, and might return 0 if // the terminfo says that no colors are supported. int colors_ti = tigetnum(const_cast("colors")); - bool HasColors = colors_ti >= 0 ? colors_ti : checkTerminalEnvironmentForColors(); + bool HasColors = + colors_ti >= 0 ? colors_ti : checkTerminalEnvironmentForColors(); // Now extract the structure allocated by setupterm and free its memory // through a really silly dance. @@ -410,20 +412,14 @@ } const char *Process::OutputColor(char code, bool bold, bool bg) { - return colorcodes[bg?1:0][bold?1:0][code&7]; + return colorcodes[bg ? 1 : 0][bold ? 1 : 0][code & 7]; } -const char *Process::OutputBold(bool bg) { - return "\033[1m"; -} +const char *Process::OutputBold(bool bg) { return "\033[1m"; } -const char *Process::OutputReverse() { - return "\033[7m"; -} +const char *Process::OutputReverse() { return "\033[7m"; } -const char *Process::ResetColor() { - return "\033[0m"; -} +const char *Process::ResetColor() { return "\033[0m"; } #if !HAVE_DECL_ARC4RANDOM static unsigned GetRandomNumberSeed() { diff --git a/llvm/lib/Support/Unix/Program.inc b/llvm/lib/Support/Unix/Program.inc --- a/llvm/lib/Support/Unix/Program.inc +++ b/llvm/lib/Support/Unix/Program.inc @@ -1,4 +1,5 @@ -//===- llvm/Support/Unix/Program.cpp -----------------------------*- C++ -*-===// +//===- llvm/Support/Unix/Program.cpp -----------------------------*- C++ +//-*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -55,7 +56,7 @@ #endif #if !USE_NSGETENVIRON - extern char **environ; +extern char **environ; #else #include // _NSGetEnviron #endif @@ -89,12 +90,12 @@ SmallString<128> FilePath(Path); sys::path::append(FilePath, Name); if (sys::fs::can_execute(FilePath.c_str())) - return std::string(FilePath.str()); // Found the executable! + return std::string(FilePath.str()); // Found the executable! } return errc::no_such_file_or_directory; } -static bool RedirectIO(Optional Path, int FD, std::string* ErrMsg) { +static bool RedirectIO(Optional Path, int FD, std::string *ErrMsg) { if (!Path) // Noop return false; std::string File; @@ -105,10 +106,10 @@ File = std::string(*Path); // Open the file - int InFD = open(File.c_str(), FD == 0 ? O_RDONLY : O_WRONLY|O_CREAT, 0666); + int InFD = open(File.c_str(), FD == 0 ? O_RDONLY : O_WRONLY | O_CREAT, 0666); if (InFD == -1) { - MakeErrMsg(ErrMsg, "Cannot open file '" + File + "' for " - + (FD == 0 ? "input" : "output")); + MakeErrMsg(ErrMsg, "Cannot open file '" + File + "' for " + + (FD == 0 ? "input" : "output")); return true; } @@ -118,7 +119,7 @@ close(InFD); return true; } - close(InFD); // Close the original FD + close(InFD); // Close the original FD return false; } @@ -135,30 +136,28 @@ File = Path->c_str(); if (int Err = posix_spawn_file_actions_addopen( - FileActions, FD, File, - FD == 0 ? O_RDONLY : O_WRONLY | O_CREAT, 0666)) + FileActions, FD, File, FD == 0 ? O_RDONLY : O_WRONLY | O_CREAT, 0666)) return MakeErrMsg(ErrMsg, "Cannot posix_spawn_file_actions_addopen", Err); return false; } #endif -static void TimeOutHandler(int Sig) { -} +static void TimeOutHandler(int Sig) {} static void SetMemoryLimits(unsigned size) { #if HAVE_SYS_RESOURCE_H && HAVE_GETRLIMIT && HAVE_SETRLIMIT struct rlimit r; - __typeof__ (r.rlim_cur) limit = (__typeof__ (r.rlim_cur)) (size) * 1048576; + __typeof__(r.rlim_cur) limit = (__typeof__(r.rlim_cur))(size)*1048576; // Heap size - getrlimit (RLIMIT_DATA, &r); + getrlimit(RLIMIT_DATA, &r); r.rlim_cur = limit; - setrlimit (RLIMIT_DATA, &r); + setrlimit(RLIMIT_DATA, &r); #ifdef RLIMIT_RSS // Resident set size. - getrlimit (RLIMIT_RSS, &r); + getrlimit(RLIMIT_RSS, &r); r.rlim_cur = limit; - setrlimit (RLIMIT_RSS, &r); + setrlimit(RLIMIT_RSS, &r); #endif #endif } @@ -263,7 +262,7 @@ posix_spawn_file_actions_destroy(FileActions); if (Err) - return !MakeErrMsg(ErrMsg, "posix_spawn failed", Err); + return !MakeErrMsg(ErrMsg, "posix_spawn failed", Err); PI.Pid = PID; PI.Process = PID; @@ -275,56 +274,62 @@ // Create a child process. int child = fork(); switch (child) { - // An error occurred: Return to the caller. - case -1: - MakeErrMsg(ErrMsg, "Couldn't fork"); - return false; + // An error occurred: Return to the caller. + case -1: + MakeErrMsg(ErrMsg, "Couldn't fork"); + return false; - // Child process: Execute the program. - case 0: { - // Redirect file descriptors... - if (!Redirects.empty()) { - // Redirect stdin - if (RedirectIO(Redirects[0], 0, ErrMsg)) { return false; } - // Redirect stdout - if (RedirectIO(Redirects[1], 1, ErrMsg)) { return false; } - if (Redirects[1] && Redirects[2] && *Redirects[1] == *Redirects[2]) { - // If stdout and stderr should go to the same place, redirect stderr - // to the FD already open for stdout. - if (-1 == dup2(1,2)) { - MakeErrMsg(ErrMsg, "Can't redirect stderr to stdout"); - return false; - } - } else { - // Just redirect stderr - if (RedirectIO(Redirects[2], 2, ErrMsg)) { return false; } - } + // Child process: Execute the program. + case 0: { + // Redirect file descriptors... + if (!Redirects.empty()) { + // Redirect stdin + if (RedirectIO(Redirects[0], 0, ErrMsg)) { + return false; } - - // Set memory limits - if (MemoryLimit!=0) { - SetMemoryLimits(MemoryLimit); + // Redirect stdout + if (RedirectIO(Redirects[1], 1, ErrMsg)) { + return false; + } + if (Redirects[1] && Redirects[2] && *Redirects[1] == *Redirects[2]) { + // If stdout and stderr should go to the same place, redirect stderr + // to the FD already open for stdout. + if (-1 == dup2(1, 2)) { + MakeErrMsg(ErrMsg, "Can't redirect stderr to stdout"); + return false; + } + } else { + // Just redirect stderr + if (RedirectIO(Redirects[2], 2, ErrMsg)) { + return false; + } } + } - // Execute! - std::string PathStr = std::string(Program); - if (Envp != nullptr) - execve(PathStr.c_str(), const_cast(Argv), - const_cast(Envp)); - else - execv(PathStr.c_str(), const_cast(Argv)); - // If the execve() failed, we should exit. Follow Unix protocol and - // return 127 if the executable was not found, and 126 otherwise. - // Use _exit rather than exit so that atexit functions and static - // object destructors cloned from the parent process aren't - // redundantly run, and so that any data buffered in stdio buffers - // cloned from the parent aren't redundantly written out. - _exit(errno == ENOENT ? 127 : 126); + // Set memory limits + if (MemoryLimit != 0) { + SetMemoryLimits(MemoryLimit); } - // Parent process: Break out of the switch to do our processing. - default: - break; + // Execute! + std::string PathStr = std::string(Program); + if (Envp != nullptr) + execve(PathStr.c_str(), const_cast(Argv), + const_cast(Envp)); + else + execv(PathStr.c_str(), const_cast(Argv)); + // If the execve() failed, we should exit. Follow Unix protocol and + // return 127 if the executable was not found, and 126 otherwise. + // Use _exit rather than exit so that atexit functions and static + // object destructors cloned from the parent process aren't + // redundantly run, and so that any data buffered in stdio buffers + // cloned from the parent aren't redundantly written out. + _exit(errno == ENOENT ? 127 : 126); + } + + // Parent process: Break out of the switch to do our processing. + default: + break; } PI.Pid = child; @@ -339,7 +344,7 @@ #ifndef _AIX using ::wait4; #else -static pid_t (wait4)(pid_t pid, int *status, int options, struct rusage *usage); +static pid_t(wait4)(pid_t pid, int *status, int options, struct rusage *usage); #endif } // namespace sys @@ -347,11 +352,11 @@ #ifdef _AIX #ifndef _ALL_SOURCE -extern "C" pid_t (wait4)(pid_t pid, int *status, int options, - struct rusage *usage); +extern "C" pid_t(wait4)(pid_t pid, int *status, int options, + struct rusage *usage); #endif -pid_t (llvm::sys::wait4)(pid_t pid, int *status, int options, - struct rusage *usage) { +pid_t(llvm::sys::wait4)(pid_t pid, int *status, int options, + struct rusage *usage) { assert(pid > 0 && "Only expecting to handle actual PID values!"); assert((options & ~WNOHANG) == 0 && "Expecting WNOHANG at most!"); assert(usage && "Expecting usage collection!"); @@ -494,13 +499,13 @@ return WaitResult; } -std::error_code llvm::sys::ChangeStdinMode(fs::OpenFlags Flags){ +std::error_code llvm::sys::ChangeStdinMode(fs::OpenFlags Flags) { if (!(Flags & fs::OF_Text)) return ChangeStdinToBinary(); return std::error_code(); } -std::error_code llvm::sys::ChangeStdoutMode(fs::OpenFlags Flags){ +std::error_code llvm::sys::ChangeStdoutMode(fs::OpenFlags Flags) { if (!(Flags & fs::OF_Text)) return ChangeStdoutToBinary(); return std::error_code(); @@ -520,7 +525,8 @@ llvm::sys::writeFileWithEncoding(StringRef FileName, StringRef Contents, WindowsEncodingMethod Encoding /*unused*/) { std::error_code EC; - llvm::raw_fd_ostream OS(FileName, EC, llvm::sys::fs::OpenFlags::OF_TextWithCRLF); + llvm::raw_fd_ostream OS(FileName, EC, + llvm::sys::fs::OpenFlags::OF_TextWithCRLF); if (EC) return EC; diff --git a/llvm/lib/Support/Unix/Signals.inc b/llvm/lib/Support/Unix/Signals.inc --- a/llvm/lib/Support/Unix/Signals.inc +++ b/llvm/lib/Support/Unix/Signals.inc @@ -48,7 +48,7 @@ #include #include #ifdef HAVE_BACKTRACE -# include BACKTRACE_HEADER // For backtrace(). +#include BACKTRACE_HEADER // For backtrace(). #endif #if HAVE_SIGNAL_H #include @@ -79,8 +79,8 @@ using namespace llvm; -static void SignalHandler(int Sig); // defined below. -static void InfoSignalHandler(int Sig); // defined below. +static void SignalHandler(int Sig); // defined below. +static void InfoSignalHandler(int Sig); // defined below. using SignalHandlerFunctionType = void (*)(); /// The function to call if ctrl-c is pressed. @@ -208,40 +208,45 @@ /// Signals that represent requested termination. There's no bug or failure, or /// if there is, it's not our direct responsibility. For whatever reason, our /// continued execution is no longer desirable. -static const int IntSigs[] = { - SIGHUP, SIGINT, SIGTERM, SIGUSR2 -}; +static const int IntSigs[] = {SIGHUP, SIGINT, SIGTERM, SIGUSR2}; /// Signals that represent that we have a bug, and our prompt termination has /// been ordered. -static const int KillSigs[] = { - SIGILL, SIGTRAP, SIGABRT, SIGFPE, SIGBUS, SIGSEGV, SIGQUIT +static const int KillSigs[] = {SIGILL, + SIGTRAP, + SIGABRT, + SIGFPE, + SIGBUS, + SIGSEGV, + SIGQUIT #ifdef SIGSYS - , SIGSYS + , + SIGSYS #endif #ifdef SIGXCPU - , SIGXCPU + , + SIGXCPU #endif #ifdef SIGXFSZ - , SIGXFSZ + , + SIGXFSZ #endif #ifdef SIGEMT - , SIGEMT + , + SIGEMT #endif }; /// Signals that represent requests for status. -static const int InfoSigs[] = { - SIGUSR1 +static const int InfoSigs[] = {SIGUSR1 #ifdef SIGINFO - , SIGINFO + , + SIGINFO #endif }; -static const size_t NumSigs = - std::size(IntSigs) + std::size(KillSigs) + - std::size(InfoSigs) + 1 /* SIGPIPE */; - +static const size_t NumSigs = std::size(IntSigs) + std::size(KillSigs) + + std::size(InfoSigs) + 1 /* SIGPIPE */; static std::atomic NumRegisteredSignals = ATOMIC_VAR_INIT(0); static struct { @@ -334,8 +339,8 @@ void sys::unregisterHandlers() { // Restore all of the signal handlers to how they were before we showed up. for (unsigned i = 0, e = NumRegisteredSignals.load(); i != e; ++i) { - sigaction(RegisteredSignalInfo[i].SigNo, - &RegisteredSignalInfo[i].SA, nullptr); + sigaction(RegisteredSignalInfo[i].SigNo, &RegisteredSignalInfo[i].SA, + nullptr); --NumRegisteredSignals; } } @@ -412,9 +417,7 @@ CurrentInfoFunction(); } -void llvm::sys::RunInterruptHandlers() { - RemoveFilesToRemove(); -} +void llvm::sys::RunInterruptHandlers() { RemoveFilesToRemove(); } void llvm::sys::SetInterruptFunction(void (*IF)()) { InterruptFunction.exchange(IF); @@ -437,8 +440,7 @@ } // The public API -bool llvm::sys::RemoveFileOnSignal(StringRef Filename, - std::string* ErrMsg) { +bool llvm::sys::RemoveFileOnSignal(StringRef Filename, std::string *ErrMsg) { // Ensure that cleanup will occur as soon as one file is added. static ManagedStatic FilesToRemoveCleanup; *FilesToRemoveCleanup; @@ -461,7 +463,7 @@ RegisterHandlers(); } -#if defined(HAVE_BACKTRACE) && ENABLE_BACKTRACES && HAVE_LINK_H && \ +#if defined(HAVE_BACKTRACE) && ENABLE_BACKTRACES && HAVE_LINK_H && \ (defined(__linux__) || defined(__FreeBSD__) || \ defined(__FreeBSD_kernel__) || defined(__NetBSD__)) struct DlIteratePhdrData { @@ -474,7 +476,7 @@ }; static int dl_iterate_phdr_cb(dl_phdr_info *info, size_t size, void *arg) { - DlIteratePhdrData *data = (DlIteratePhdrData*)arg; + DlIteratePhdrData *data = (DlIteratePhdrData *)arg; const char *name = data->first ? data->main_exec_name : info->dlpi_name; data->first = false; for (int i = 0; i < info->dlpi_phnum; i++) { @@ -567,8 +569,8 @@ #if defined(HAVE__UNWIND_BACKTRACE) // Try _Unwind_Backtrace() if backtrace() failed. if (!depth) - depth = unwindBacktrace(StackTrace, - static_cast(std::size(StackTrace))); + depth = + unwindBacktrace(StackTrace, static_cast(std::size(StackTrace))); #endif if (!depth) return; @@ -586,13 +588,16 @@ for (int i = 0; i < depth; ++i) { Dl_info dlinfo; dladdr(StackTrace[i], &dlinfo); - const char* name = strrchr(dlinfo.dli_fname, '/'); + const char *name = strrchr(dlinfo.dli_fname, '/'); int nwidth; - if (!name) nwidth = strlen(dlinfo.dli_fname); - else nwidth = strlen(name) - 1; + if (!name) + nwidth = strlen(dlinfo.dli_fname); + else + nwidth = strlen(name) - 1; - if (nwidth > width) width = nwidth; + if (nwidth > width) + width = nwidth; } for (int i = 0; i < depth; ++i) { @@ -601,23 +606,27 @@ OS << format("%-2d", i); - const char* name = strrchr(dlinfo.dli_fname, '/'); - if (!name) OS << format(" %-*s", width, dlinfo.dli_fname); - else OS << format(" %-*s", width, name+1); + const char *name = strrchr(dlinfo.dli_fname, '/'); + if (!name) + OS << format(" %-*s", width, dlinfo.dli_fname); + else + OS << format(" %-*s", width, name + 1); - OS << format(" %#0*lx", (int)(sizeof(void*) * 2) + 2, + OS << format(" %#0*lx", (int)(sizeof(void *) * 2) + 2, (unsigned long)StackTrace[i]); if (dlinfo.dli_sname != nullptr) { OS << ' '; int res; - char* d = itaniumDemangle(dlinfo.dli_sname, nullptr, nullptr, &res); - if (!d) OS << dlinfo.dli_sname; - else OS << d; + char *d = itaniumDemangle(dlinfo.dli_sname, nullptr, nullptr, &res); + if (!d) + OS << dlinfo.dli_sname; + else + OS << d; free(d); - OS << format(" + %tu", (static_cast(StackTrace[i])- - static_cast(dlinfo.dli_saddr))); + OS << format(" + %tu", (static_cast(StackTrace[i]) - + static_cast(dlinfo.dli_saddr))); } OS << '\n'; } @@ -648,11 +657,9 @@ exception_mask_t mask = EXC_MASK_CRASH; - kern_return_t ret = task_set_exception_ports(self, - mask, - MACH_PORT_NULL, - EXCEPTION_STATE_IDENTITY | MACH_EXCEPTION_CODES, - THREAD_STATE_NONE); + kern_return_t ret = task_set_exception_ports( + self, mask, MACH_PORT_NULL, + EXCEPTION_STATE_IDENTITY | MACH_EXCEPTION_CODES, THREAD_STATE_NONE); (void)ret; } #endif diff --git a/llvm/lib/Support/Unix/ThreadLocal.inc b/llvm/lib/Support/Unix/ThreadLocal.inc --- a/llvm/lib/Support/Unix/ThreadLocal.inc +++ b/llvm/lib/Support/Unix/ThreadLocal.inc @@ -1,4 +1,5 @@ -//=== llvm/Support/Unix/ThreadLocal.inc - Unix Thread Local Data -*- C++ -*-===// +//=== llvm/Support/Unix/ThreadLocal.inc - Unix Thread Local Data -*- C++ +//-*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -26,33 +27,31 @@ ThreadLocalImpl::ThreadLocalImpl() : data() { static_assert(sizeof(pthread_key_t) <= sizeof(data), "size too big"); - pthread_key_t* key = reinterpret_cast(&data); + pthread_key_t *key = reinterpret_cast(&data); int errorcode = pthread_key_create(key, nullptr); assert(errorcode == 0); - (void) errorcode; + (void)errorcode; } ThreadLocalImpl::~ThreadLocalImpl() { - pthread_key_t* key = reinterpret_cast(&data); + pthread_key_t *key = reinterpret_cast(&data); int errorcode = pthread_key_delete(*key); assert(errorcode == 0); - (void) errorcode; + (void)errorcode; } -void ThreadLocalImpl::setInstance(const void* d) { - pthread_key_t* key = reinterpret_cast(&data); +void ThreadLocalImpl::setInstance(const void *d) { + pthread_key_t *key = reinterpret_cast(&data); int errorcode = pthread_setspecific(*key, d); assert(errorcode == 0); - (void) errorcode; + (void)errorcode; } void *ThreadLocalImpl::getInstance() { - pthread_key_t* key = reinterpret_cast(&data); + pthread_key_t *key = reinterpret_cast(&data); return pthread_getspecific(*key); } -void ThreadLocalImpl::removeInstance() { - setInstance(nullptr); -} +void ThreadLocalImpl::removeInstance() { setInstance(nullptr); } -} +} // namespace llvm diff --git a/llvm/lib/Support/Unix/Threading.inc b/llvm/lib/Support/Unix/Threading.inc --- a/llvm/lib/Support/Unix/Threading.inc +++ b/llvm/lib/Support/Unix/Threading.inc @@ -98,13 +98,9 @@ } } -pthread_t llvm_thread_get_id_impl(pthread_t Thread) { - return Thread; -} +pthread_t llvm_thread_get_id_impl(pthread_t Thread) { return Thread; } -pthread_t llvm_thread_get_current_id_impl() { - return ::pthread_self(); -} +pthread_t llvm_thread_get_current_id_impl() { return ::pthread_self(); } } // namespace llvm @@ -131,7 +127,6 @@ #endif } - static constexpr uint32_t get_max_thread_name_length_impl() { #if defined(__NetBSD__) return PTHREAD_MAX_NAMELEN_NP; @@ -180,7 +175,7 @@ ::pthread_set_name_np(::pthread_self(), NameStr.data()); #elif defined(__NetBSD__) ::pthread_setname_np(::pthread_self(), "%s", - const_cast(NameStr.data())); + const_cast(NameStr.data())); #elif defined(__APPLE__) ::pthread_setname_np(NameStr.data()); #endif @@ -196,8 +191,8 @@ struct kinfo_proc *kp = nullptr, *nkp; size_t len = 0; int error; - int ctl[4] = { CTL_KERN, KERN_PROC, KERN_PROC_PID | KERN_PROC_INC_THREAD, - (int)pid }; + int ctl[4] = {CTL_KERN, KERN_PROC, KERN_PROC_PID | KERN_PROC_INC_THREAD, + (int)pid}; while (1) { error = sysctl(ctl, 4, kp, &len, nullptr, 0); @@ -240,7 +235,7 @@ #elif defined(__linux__) #if HAVE_PTHREAD_GETNAME_NP constexpr uint32_t len = get_max_thread_name_length_impl(); - char Buffer[len] = {'\0'}; // FIXME: working around MSan false positive. + char Buffer[len] = {'\0'}; // FIXME: working around MSan false positive. if (0 == ::pthread_getname_np(::pthread_self(), Buffer, len)) Name.append(Buffer, Buffer + strlen(Buffer)); #endif @@ -267,18 +262,22 @@ #elif defined(__APPLE__) // https://developer.apple.com/documentation/apple-silicon/tuning-your-code-s-performance-for-apple-silicon // - // Background - Applies to work that isn’t visible to the user and may take significant - // time to complete. Examples include indexing, backing up, or synchronizing data. This - // class emphasizes energy efficiency. + // Background - Applies to work that isn’t visible to the user and may take + // significant time to complete. Examples include indexing, backing up, or + // synchronizing data. This class emphasizes energy efficiency. // - // Utility - Applies to work that takes anywhere from a few seconds to a few minutes to - // complete. Examples include downloading a document or importing data. This class - // offers a balance between responsiveness, performance, and energy efficiency. - const auto qosClass = [&](){ + // Utility - Applies to work that takes anywhere from a few seconds to a few + // minutes to complete. Examples include downloading a document or importing + // data. This class offers a balance between responsiveness, performance, and + // energy efficiency. + const auto qosClass = [&]() { switch (Priority) { - case ThreadPriority::Background: return QOS_CLASS_BACKGROUND; - case ThreadPriority::Low: return QOS_CLASS_UTILITY; - case ThreadPriority::Default: return QOS_CLASS_DEFAULT; + case ThreadPriority::Background: + return QOS_CLASS_BACKGROUND; + case ThreadPriority::Low: + return QOS_CLASS_UTILITY; + case ThreadPriority::Default: + return QOS_CLASS_DEFAULT; } }(); return !pthread_set_qos_class_self_np(qosClass, 0) @@ -290,7 +289,7 @@ #include -int computeHostNumHardwareThreads() { +static int computeHostNumHardwareThreads() { #if defined(__FreeBSD__) cpuset_t mask; CPU_ZERO(&mask); diff --git a/llvm/lib/Support/Unix/Watchdog.inc b/llvm/lib/Support/Unix/Watchdog.inc --- a/llvm/lib/Support/Unix/Watchdog.inc +++ b/llvm/lib/Support/Unix/Watchdog.inc @@ -17,17 +17,17 @@ #endif namespace llvm { - namespace sys { - Watchdog::Watchdog(unsigned int seconds) { +namespace sys { +Watchdog::Watchdog(unsigned int seconds) { #ifdef HAVE_UNISTD_H - alarm(seconds); + alarm(seconds); #endif - } +} - Watchdog::~Watchdog() { +Watchdog::~Watchdog() { #ifdef HAVE_UNISTD_H - alarm(0); + alarm(0); #endif - } - } } +} // namespace sys +} // namespace llvm diff --git a/llvm/lib/Support/VirtualFileSystem.cpp b/llvm/lib/Support/VirtualFileSystem.cpp --- a/llvm/lib/Support/VirtualFileSystem.cpp +++ b/llvm/lib/Support/VirtualFileSystem.cpp @@ -46,6 +46,7 @@ #include #include #include +#include #include #include #include @@ -298,7 +299,7 @@ // The current working directory, with links resolved. (readlink .). SmallString<128> Resolved; }; - Optional WD; + std::optional WD; }; } // namespace @@ -1604,7 +1605,7 @@ return false; } - Optional + std::optional parseRedirectKind(yaml::Node *N) { SmallString<12> Storage; StringRef Value; diff --git a/llvm/lib/Support/Windows/COM.inc b/llvm/lib/Support/Windows/COM.inc --- a/llvm/lib/Support/Windows/COM.inc +++ b/llvm/lib/Support/Windows/COM.inc @@ -32,5 +32,5 @@ } InitializeCOMRAII::~InitializeCOMRAII() { ::CoUninitialize(); } -} -} +} // namespace sys +} // namespace llvm diff --git a/llvm/lib/Support/Windows/DynamicLibrary.inc b/llvm/lib/Support/Windows/DynamicLibrary.inc --- a/llvm/lib/Support/Windows/DynamicLibrary.inc +++ b/llvm/lib/Support/Windows/DynamicLibrary.inc @@ -10,8 +10,8 @@ // //===----------------------------------------------------------------------===// -#include "llvm/Support/Windows/WindowsSupport.h" #include "llvm/Support/ConvertUTF.h" +#include "llvm/Support/Windows/WindowsSupport.h" #include "llvm/Support/raw_ostream.h" #include @@ -21,13 +21,12 @@ //=== and must not be UNIX code. //===----------------------------------------------------------------------===// - DynamicLibrary::HandleSet::~HandleSet() { for (void *Handle : llvm::reverse(Handles)) FreeLibrary(HMODULE(Handle)); // 'Process' should not be released on Windows. - assert((!Process || Process==this) && "Bad Handle"); + assert((!Process || Process == this) && "Bad Handle"); // llvm_shutdown called, Return to default DynamicLibrary::SearchOrder = DynamicLibrary::SO_Linker; } @@ -51,7 +50,7 @@ return &DynamicLibrary::Invalid; } - return reinterpret_cast(Handle); + return reinterpret_cast(Handle); } static DynamicLibrary::HandleSet *IsOpenedHandlesInstance(void *Handle) { @@ -60,7 +59,7 @@ } void DynamicLibrary::HandleSet::DLClose(void *Handle) { - if (HandleSet* HS = IsOpenedHandlesInstance(Handle)) + if (HandleSet *HS = IsOpenedHandlesInstance(Handle)) HS->Process = nullptr; // Just drop the *Process* handle. else FreeLibrary((HMODULE)Handle); @@ -75,7 +74,7 @@ #else !EnumProcessModules(H, Data, Bytes, &Bytes) #endif - ) { + ) { std::string Err; if (MakeErrMsg(&Err, "EnumProcessModules failure")) llvm::errs() << Err << "\n"; @@ -85,7 +84,7 @@ } void *DynamicLibrary::HandleSet::DLSym(void *Handle, const char *Symbol) { - HandleSet* HS = IsOpenedHandlesInstance(Handle); + HandleSet *HS = IsOpenedHandlesInstance(Handle); if (!HS) return (void *)uintptr_t(GetProcAddress((HMODULE)Handle, Symbol)); @@ -128,7 +127,7 @@ // Try EXE first, mirroring what dlsym(dlopen(NULL)) does. if (FARPROC Ptr = GetProcAddress(HMODULE(Handles.front()), Symbol)) - return (void *) uintptr_t(Ptr); + return (void *)uintptr_t(Ptr); if (Handles.size() > 1) { // This is different behaviour than what Posix dlsym(dlopen(NULL)) does. @@ -137,19 +136,20 @@ // symbols from ucrt.dll first, but iterating NOT in reverse here would // mean that the msvc.dll versions would be returned. - for (auto I = Handles.rbegin(), E = Handles.rend()-1; I != E; ++I) { + for (auto I = Handles.rbegin(), E = Handles.rend() - 1; I != E; ++I) { if (FARPROC Ptr = GetProcAddress(HMODULE(*I), Symbol)) - return (void *) uintptr_t(Ptr); + return (void *)uintptr_t(Ptr); } } return nullptr; } - // Stack probing routines are in the support library (e.g. libgcc), but we don't // have dynamic linking on windows. Provide a hook. -#define EXPLICIT_SYMBOL(SYM) \ - extern "C" { extern void *SYM; } +#define EXPLICIT_SYMBOL(SYM) \ + extern "C" { \ + extern void *SYM; \ + } #define EXPLICIT_SYMBOL2(SYMFROM, SYMTO) EXPLICIT_SYMBOL(SYMTO) #ifdef _M_IX86 diff --git a/llvm/lib/Support/Windows/Host.inc b/llvm/lib/Support/Windows/Host.inc --- a/llvm/lib/Support/Windows/Host.inc +++ b/llvm/lib/Support/Windows/Host.inc @@ -19,14 +19,13 @@ using namespace llvm; -static std::string updateTripleOSVersion(std::string Triple) { - return Triple; -} +static std::string updateTripleOSVersion(std::string Triple) { return Triple; } std::string sys::getDefaultTargetTriple() { const char *Triple = LLVM_DEFAULT_TARGET_TRIPLE; - // Override the default target with an environment variable named by LLVM_TARGET_TRIPLE_ENV. + // Override the default target with an environment variable named by + // LLVM_TARGET_TRIPLE_ENV. #if defined(LLVM_TARGET_TRIPLE_ENV) if (const char *EnvTriple = std::getenv(LLVM_TARGET_TRIPLE_ENV)) Triple = EnvTriple; diff --git a/llvm/lib/Support/Windows/Memory.inc b/llvm/lib/Support/Windows/Memory.inc --- a/llvm/lib/Support/Windows/Memory.inc +++ b/llvm/lib/Support/Windows/Memory.inc @@ -28,13 +28,12 @@ case llvm::sys::Memory::MF_WRITE: // Note: PAGE_WRITE is not supported by VirtualProtect return PAGE_READWRITE; - case llvm::sys::Memory::MF_READ|llvm::sys::Memory::MF_WRITE: + case llvm::sys::Memory::MF_READ | llvm::sys::Memory::MF_WRITE: return PAGE_READWRITE; - case llvm::sys::Memory::MF_READ|llvm::sys::Memory::MF_EXEC: + case llvm::sys::Memory::MF_READ | llvm::sys::Memory::MF_EXEC: return PAGE_EXECUTE_READ; - case llvm::sys::Memory::MF_READ | - llvm::sys::Memory::MF_WRITE | - llvm::sys::Memory::MF_EXEC: + case llvm::sys::Memory::MF_READ | llvm::sys::Memory::MF_WRITE | + llvm::sys::Memory::MF_EXEC: return PAGE_EXECUTE_READWRITE; case llvm::sys::Memory::MF_EXEC: return PAGE_EXECUTE; @@ -49,7 +48,7 @@ // granularity may be larger than a single page (in practice, it is 64K) // so mapping less than that will create an unreachable fragment of memory. static size_t getAllocationGranularity() { - SYSTEM_INFO Info; + SYSTEM_INFO Info; ::GetSystemInfo(&Info); if (Info.dwPageSize > Info.dwAllocationGranularity) return Info.dwPageSize; @@ -99,8 +98,7 @@ MemoryBlock Memory::allocateMappedMemory(size_t NumBytes, const MemoryBlock *const NearBlock, - unsigned Flags, - std::error_code &EC) { + unsigned Flags, std::error_code &EC) { EC = std::error_code(); if (NumBytes == 0) return MemoryBlock(); @@ -121,8 +119,8 @@ size_t NumBlocks = (NumBytes + Granularity - 1) / Granularity; uintptr_t Start = NearBlock ? reinterpret_cast(NearBlock->base()) + - NearBlock->allocatedSize() - : 0; + NearBlock->allocatedSize() + : 0; // If the requested address is not aligned to the allocation granularity, // round up to get beyond NearBlock. VirtualAlloc would have rounded down. @@ -132,8 +130,8 @@ DWORD Protect = getWindowsProtectionFlags(Flags); size_t AllocSize = NumBlocks * Granularity; - void *PA = ::VirtualAlloc(reinterpret_cast(Start), - AllocSize, AllocType, Protect); + void *PA = ::VirtualAlloc(reinterpret_cast(Start), AllocSize, + AllocType, Protect); if (PA == NULL) { if (NearBlock || HugePages) { // Try again without the NearBlock hint and without large memory pages @@ -154,7 +152,7 @@ return Result; } - std::error_code Memory::releaseMappedMemory(MemoryBlock &M) { +std::error_code Memory::releaseMappedMemory(MemoryBlock &M) { if (M.Address == 0 || M.AllocatedSize == 0) return std::error_code(); @@ -167,8 +165,8 @@ return std::error_code(); } - std::error_code Memory::protectMappedMemory(const MemoryBlock &M, - unsigned Flags) { +std::error_code Memory::protectMappedMemory(const MemoryBlock &M, + unsigned Flags) { if (M.Address == 0 || M.AllocatedSize == 0) return std::error_code(); @@ -187,8 +185,7 @@ /// InvalidateInstructionCache - Before the JIT can run a block of code /// that has been emitted it must invalidate the instruction cache on some /// platforms. -void Memory::InvalidateInstructionCache( - const void *Addr, size_t Len) { +void Memory::InvalidateInstructionCache(const void *Addr, size_t Len) { FlushInstructionCache(GetCurrentProcess(), Addr, Len); } diff --git a/llvm/lib/Support/Windows/Path.inc b/llvm/lib/Support/Windows/Path.inc --- a/llvm/lib/Support/Windows/Path.inc +++ b/llvm/lib/Support/Windows/Path.inc @@ -37,15 +37,15 @@ #endif #ifdef _MSC_VER -# pragma comment(lib, "advapi32.lib") // This provides CryptAcquireContextW. -# pragma comment(lib, "ole32.lib") // This provides CoTaskMemFree +#pragma comment(lib, "advapi32.lib") // This provides CryptAcquireContextW. +#pragma comment(lib, "ole32.lib") // This provides CoTaskMemFree #endif using namespace llvm; -using llvm::sys::windows::UTF8ToUTF16; using llvm::sys::windows::CurCPToUTF16; using llvm::sys::windows::UTF16ToUTF8; +using llvm::sys::windows::UTF8ToUTF16; using llvm::sys::windows::widenPath; static bool is_separator(const wchar_t value) { @@ -59,7 +59,7 @@ } namespace llvm { -namespace sys { +namespace sys { namespace windows { // Convert a UTF-8 path to UTF-16. Also, if the absolute equivalent of the path @@ -193,9 +193,7 @@ return toTimePoint(Time); } -uint32_t file_status::getLinkCount() const { - return NumLinks; -} +uint32_t file_status::getLinkCount() const { return NumLinks; } std::error_code current_path(SmallVectorImpl &result) { SmallVector cur_path; @@ -372,8 +370,8 @@ // The buffer wasn't big enough, try again. In this case the return value // *does* indicate the size of the null terminator. Buffer.resize_for_overwrite(CountChars); - CountChars = ::GetFinalPathNameByHandleW( - H, Buffer.begin(), Buffer.size(), FILE_NAME_NORMALIZED); + CountChars = ::GetFinalPathNameByHandleW(H, Buffer.begin(), Buffer.size(), + FILE_NAME_NORMALIZED); } Buffer.truncate(CountChars); if (CountChars == 0) @@ -628,8 +626,7 @@ if (Attributes == INVALID_FILE_ATTRIBUTES) { // See if the file didn't actually exist. DWORD LastError = ::GetLastError(); - if (LastError != ERROR_FILE_NOT_FOUND && - LastError != ERROR_PATH_NOT_FOUND) + if (LastError != ERROR_FILE_NOT_FOUND && LastError != ERROR_PATH_NOT_FOUND) return mapWindowsError(LastError); return errc::no_such_file_or_directory; } @@ -650,15 +647,14 @@ bool equivalent(file_status A, file_status B) { assert(status_known(A) && status_known(B)); - return A.FileIndexHigh == B.FileIndexHigh && - A.FileIndexLow == B.FileIndexLow && - A.FileSizeHigh == B.FileSizeHigh && - A.FileSizeLow == B.FileSizeLow && - A.LastAccessedTimeHigh == B.LastAccessedTimeHigh && - A.LastAccessedTimeLow == B.LastAccessedTimeLow && - A.LastWriteTimeHigh == B.LastWriteTimeHigh && - A.LastWriteTimeLow == B.LastWriteTimeLow && - A.VolumeSerialNumber == B.VolumeSerialNumber; + return A.FileIndexHigh == B.FileIndexHigh && + A.FileIndexLow == B.FileIndexLow && A.FileSizeHigh == B.FileSizeHigh && + A.FileSizeLow == B.FileSizeLow && + A.LastAccessedTimeHigh == B.LastAccessedTimeHigh && + A.LastAccessedTimeLow == B.LastAccessedTimeLow && + A.LastWriteTimeHigh == B.LastWriteTimeHigh && + A.LastWriteTimeLow == B.LastWriteTimeLow && + A.VolumeSerialNumber == B.VolumeSerialNumber; } std::error_code equivalent(const Twine &A, const Twine &B, bool &result) { @@ -674,12 +670,10 @@ static bool isReservedName(StringRef path) { // This list of reserved names comes from MSDN, at: // http://msdn.microsoft.com/en-us/library/aa365247%28v=vs.85%29.aspx - static const char *const sReservedNames[] = { "nul", "con", "prn", "aux", - "com1", "com2", "com3", "com4", - "com5", "com6", "com7", "com8", - "com9", "lpt1", "lpt2", "lpt3", - "lpt4", "lpt5", "lpt6", "lpt7", - "lpt8", "lpt9" }; + static const char *const sReservedNames[] = { + "nul", "con", "prn", "aux", "com1", "com2", "com3", "com4", + "com5", "com6", "com7", "com8", "com9", "lpt1", "lpt2", "lpt3", + "lpt4", "lpt5", "lpt6", "lpt7", "lpt8", "lpt9"}; // First, check to see if this is a device namespace, which always // starts with \\.\, since device namespaces are not legal file paths. @@ -744,8 +738,7 @@ handle_status_error: DWORD LastError = ::GetLastError(); - if (LastError == ERROR_FILE_NOT_FOUND || - LastError == ERROR_PATH_NOT_FOUND) + if (LastError == ERROR_FILE_NOT_FOUND || LastError == ERROR_PATH_NOT_FOUND) Result = file_status(file_type::file_not_found); else if (LastError == ERROR_SHARING_VIOLATION) Result = file_status(file_type::type_unknown); @@ -795,9 +788,7 @@ return getStatus(FileHandle, Result); } -unsigned getUmask() { - return 0; -} +unsigned getUmask() { return 0; } std::error_code setPermissions(const Twine &Path, perms Permissions) { SmallVector PathUTF16; @@ -816,8 +807,7 @@ if (Attributes == 0) // FILE_ATTRIBUTE_NORMAL indicates no other attributes are set. Attributes |= FILE_ATTRIBUTE_NORMAL; - } - else { + } else { Attributes |= FILE_ATTRIBUTE_READONLY; // FILE_ATTRIBUTE_NORMAL is not compatible with any other attributes, so // remove it, if it is present. @@ -853,16 +843,19 @@ DWORD flprotect; switch (Mode) { - case readonly: flprotect = PAGE_READONLY; break; - case readwrite: flprotect = PAGE_READWRITE; break; - case priv: flprotect = PAGE_WRITECOPY; break; + case readonly: + flprotect = PAGE_READONLY; + break; + case readwrite: + flprotect = PAGE_READWRITE; + break; + case priv: + flprotect = PAGE_WRITECOPY; + break; } - HANDLE FileMappingHandle = - ::CreateFileMappingW(OrigFileHandle, 0, flprotect, - Hi_32(Size), - Lo_32(Size), - 0); + HANDLE FileMappingHandle = ::CreateFileMappingW(OrigFileHandle, 0, flprotect, + Hi_32(Size), Lo_32(Size), 0); if (FileMappingHandle == NULL) { std::error_code ec = mapWindowsError(GetLastError()); return ec; @@ -870,15 +863,18 @@ DWORD dwDesiredAccess; switch (Mode) { - case readonly: dwDesiredAccess = FILE_MAP_READ; break; - case readwrite: dwDesiredAccess = FILE_MAP_WRITE; break; - case priv: dwDesiredAccess = FILE_MAP_COPY; break; + case readonly: + dwDesiredAccess = FILE_MAP_READ; + break; + case readwrite: + dwDesiredAccess = FILE_MAP_WRITE; + break; + case priv: + dwDesiredAccess = FILE_MAP_COPY; + break; } - Mapping = ::MapViewOfFile(FileMappingHandle, - dwDesiredAccess, - Offset >> 32, - Offset & 0xffffffff, - Size); + Mapping = ::MapViewOfFile(FileMappingHandle, dwDesiredAccess, Offset >> 32, + Offset & 0xffffffff, Size); if (Mapping == NULL) { std::error_code ec = mapWindowsError(GetLastError()); ::CloseHandle(FileMappingHandle); @@ -1008,7 +1004,7 @@ size_t FilenameLen = ::wcslen(FirstFind.cFileName); while ((FilenameLen == 1 && FirstFind.cFileName[0] == L'.') || (FilenameLen == 2 && FirstFind.cFileName[0] == L'.' && - FirstFind.cFileName[1] == L'.')) + FirstFind.cFileName[1] == L'.')) if (!::FindNextFileW(FindHandle, &FirstFind)) { DWORD LastError = ::GetLastError(); // Check for end. @@ -1058,7 +1054,7 @@ size_t FilenameLen = ::wcslen(FindData.cFileName); if ((FilenameLen == 1 && FindData.cFileName[0] == L'.') || (FilenameLen == 2 && FindData.cFileName[0] == L'.' && - FindData.cFileName[1] == L'.')) + FindData.cFileName[1] == L'.')) return directory_iterator_increment(IT); SmallString<128> DirectoryEntryPathUTF8; @@ -1074,9 +1070,7 @@ return std::error_code(); } -ErrorOr directory_entry::status() const { - return Status; -} +ErrorOr directory_entry::status() const { return Status; } static std::error_code nativeFileToFd(Expected H, int &ResultFD, OpenFlags Flags) { @@ -1365,7 +1359,8 @@ StringRef PathStr(Path.begin(), Path.size()); PathStr = PathStr.drop_front(); - StringRef Expr = PathStr.take_until([](char c) { return path::is_separator(c); }); + StringRef Expr = + PathStr.take_until([](char c) { return path::is_separator(c); }); if (!Expr.empty()) { // This is probably a ~username/ expression. Don't support this on Windows. @@ -1496,12 +1491,12 @@ } // end namespace path namespace windows { -std::error_code CodePageToUTF16(unsigned codepage, - llvm::StringRef original, +std::error_code CodePageToUTF16(unsigned codepage, llvm::StringRef original, llvm::SmallVectorImpl &utf16) { if (!original.empty()) { - int len = ::MultiByteToWideChar(codepage, MB_ERR_INVALID_CHARS, original.begin(), - original.size(), utf16.begin(), 0); + int len = + ::MultiByteToWideChar(codepage, MB_ERR_INVALID_CHARS, original.begin(), + original.size(), utf16.begin(), 0); if (len == 0) { return mapWindowsError(::GetLastError()); @@ -1510,8 +1505,9 @@ utf16.reserve(len + 1); utf16.resize_for_overwrite(len); - len = ::MultiByteToWideChar(codepage, MB_ERR_INVALID_CHARS, original.begin(), - original.size(), utf16.begin(), utf16.size()); + len = + ::MultiByteToWideChar(codepage, MB_ERR_INVALID_CHARS, original.begin(), + original.size(), utf16.begin(), utf16.size()); if (len == 0) { return mapWindowsError(::GetLastError()); @@ -1531,18 +1527,17 @@ } std::error_code CurCPToUTF16(llvm::StringRef curcp, - llvm::SmallVectorImpl &utf16) { + llvm::SmallVectorImpl &utf16) { return CodePageToUTF16(CP_ACP, curcp, utf16); } -static -std::error_code UTF16ToCodePage(unsigned codepage, const wchar_t *utf16, - size_t utf16_len, - llvm::SmallVectorImpl &converted) { +static std::error_code UTF16ToCodePage(unsigned codepage, const wchar_t *utf16, + size_t utf16_len, + llvm::SmallVectorImpl &converted) { if (utf16_len) { // Get length. - int len = ::WideCharToMultiByte(codepage, 0, utf16, utf16_len, converted.begin(), - 0, NULL, NULL); + int len = ::WideCharToMultiByte(codepage, 0, utf16, utf16_len, + converted.begin(), 0, NULL, NULL); if (len == 0) { return mapWindowsError(::GetLastError()); diff --git a/llvm/lib/Support/Windows/Process.inc b/llvm/lib/Support/Windows/Process.inc --- a/llvm/lib/Support/Windows/Process.inc +++ b/llvm/lib/Support/Windows/Process.inc @@ -27,8 +27,8 @@ #include #if !defined(__MINGW32__) - #pragma comment(lib, "psapi.lib") - #pragma comment(lib, "shell32.lib") +#pragma comment(lib, "psapi.lib") +#pragma comment(lib, "shell32.lib") #endif //===----------------------------------------------------------------------===// @@ -38,7 +38,7 @@ #ifdef __MINGW32__ // This ban should be lifted when MinGW 1.0+ has defined this value. -# define _HEAPOK (-2) +#define _HEAPOK (-2) #endif using namespace llvm; @@ -67,9 +67,7 @@ return Ret; } -size_t -Process::GetMallocUsage() -{ +size_t Process::GetMallocUsage() { _HEAPINFO hinfo; hinfo._pentry = NULL; @@ -81,9 +79,11 @@ return size; } -void Process::GetTimeUsage(TimePoint<> &elapsed, std::chrono::nanoseconds &user_time, +void Process::GetTimeUsage(TimePoint<> &elapsed, + std::chrono::nanoseconds &user_time, std::chrono::nanoseconds &sys_time) { - elapsed = std::chrono::system_clock::now();; + elapsed = std::chrono::system_clock::now(); + ; FILETIME ProcCreate, ProcExit, KernelTime, UserTime; if (GetProcessTimes(GetCurrentProcess(), &ProcCreate, &ProcExit, &KernelTime, @@ -108,8 +108,7 @@ // // Windows also has modal pop-up message boxes. As this method is used by // bugpoint, preventing these pop-ups is additionally important. - SetErrorMode(SEM_FAILCRITICALERRORS | - SEM_NOGPFAULTERRORBOX | + SetErrorMode(SEM_FAILCRITICALERRORS | SEM_NOGPFAULTERRORBOX | SEM_NOOPENFILEERRORBOX); coreFilesPrevented = true; @@ -131,8 +130,7 @@ do { Buf.resize_for_overwrite(Size); SetLastError(NO_ERROR); - Size = - GetEnvironmentVariableW(NameUTF16.data(), Buf.data(), Buf.size()); + Size = GetEnvironmentVariableW(NameUTF16.data(), Buf.data(), Buf.size()); if (Size == 0 && GetLastError() == ERROR_ENVVAR_NOT_FOUND) return None; @@ -281,20 +279,14 @@ return std::error_code(); } -bool Process::StandardInIsUserInput() { - return FileDescriptorIsDisplayed(0); -} +bool Process::StandardInIsUserInput() { return FileDescriptorIsDisplayed(0); } -bool Process::StandardOutIsDisplayed() { - return FileDescriptorIsDisplayed(1); -} +bool Process::StandardOutIsDisplayed() { return FileDescriptorIsDisplayed(1); } -bool Process::StandardErrIsDisplayed() { - return FileDescriptorIsDisplayed(2); -} +bool Process::StandardErrIsDisplayed() { return FileDescriptorIsDisplayed(2); } bool Process::FileDescriptorIsDisplayed(int fd) { - DWORD Mode; // Unused + DWORD Mode; // Unused return (GetConsoleMode((HANDLE)_get_osfhandle(fd), &Mode) != 0); } @@ -319,13 +311,9 @@ return FileDescriptorIsDisplayed(fd); } -bool Process::StandardOutHasColors() { - return FileDescriptorHasColors(1); -} +bool Process::StandardOutHasColors() { return FileDescriptorHasColors(1); } -bool Process::StandardErrHasColors() { - return FileDescriptorHasColors(2); -} +bool Process::StandardErrHasColors() { return FileDescriptorHasColors(2); } static bool UseANSI = false; void Process::UseANSIEscapeCodes(bool enable) { @@ -342,41 +330,39 @@ } namespace { -class DefaultColors -{ - private: - WORD defaultColor; - public: - DefaultColors() - :defaultColor(GetCurrentColor()) {} - static unsigned GetCurrentColor() { - CONSOLE_SCREEN_BUFFER_INFO csbi; - if (GetConsoleScreenBufferInfo(GetStdHandle(STD_OUTPUT_HANDLE), &csbi)) - return csbi.wAttributes; - return 0; - } - WORD operator()() const { return defaultColor; } +class DefaultColors { +private: + WORD defaultColor; + +public: + DefaultColors() : defaultColor(GetCurrentColor()) {} + static unsigned GetCurrentColor() { + CONSOLE_SCREEN_BUFFER_INFO csbi; + if (GetConsoleScreenBufferInfo(GetStdHandle(STD_OUTPUT_HANDLE), &csbi)) + return csbi.wAttributes; + return 0; + } + WORD operator()() const { return defaultColor; } }; DefaultColors defaultColors; WORD fg_color(WORD color) { - return color & (FOREGROUND_BLUE | FOREGROUND_GREEN | - FOREGROUND_INTENSITY | FOREGROUND_RED); + return color & (FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_INTENSITY | + FOREGROUND_RED); } WORD bg_color(WORD color) { - return color & (BACKGROUND_BLUE | BACKGROUND_GREEN | - BACKGROUND_INTENSITY | BACKGROUND_RED); -} + return color & (BACKGROUND_BLUE | BACKGROUND_GREEN | BACKGROUND_INTENSITY | + BACKGROUND_RED); } +} // namespace -bool Process::ColorNeedsFlush() { - return !UseANSI; -} +bool Process::ColorNeedsFlush() { return !UseANSI; } const char *Process::OutputBold(bool bg) { - if (UseANSI) return "\033[1m"; + if (UseANSI) + return "\033[1m"; WORD colors = DefaultColors::GetCurrentColor(); if (bg) @@ -388,21 +374,22 @@ } const char *Process::OutputColor(char code, bool bold, bool bg) { - if (UseANSI) return colorcodes[bg?1:0][bold?1:0][code&7]; + if (UseANSI) + return colorcodes[bg ? 1 : 0][bold ? 1 : 0][code & 7]; WORD current = DefaultColors::GetCurrentColor(); WORD colors; if (bg) { - colors = ((code&1) ? BACKGROUND_RED : 0) | - ((code&2) ? BACKGROUND_GREEN : 0 ) | - ((code&4) ? BACKGROUND_BLUE : 0); + colors = ((code & 1) ? BACKGROUND_RED : 0) | + ((code & 2) ? BACKGROUND_GREEN : 0) | + ((code & 4) ? BACKGROUND_BLUE : 0); if (bold) colors |= BACKGROUND_INTENSITY; colors |= fg_color(current); } else { - colors = ((code&1) ? FOREGROUND_RED : 0) | - ((code&2) ? FOREGROUND_GREEN : 0 ) | - ((code&4) ? FOREGROUND_BLUE : 0); + colors = ((code & 1) ? FOREGROUND_RED : 0) | + ((code & 2) ? FOREGROUND_GREEN : 0) | + ((code & 4) ? FOREGROUND_BLUE : 0); if (bold) colors |= FOREGROUND_INTENSITY; colors |= bg_color(current); @@ -418,27 +405,27 @@ } const char *Process::OutputReverse() { - if (UseANSI) return "\033[7m"; + if (UseANSI) + return "\033[7m"; - const WORD attributes - = GetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE)); + const WORD attributes = + GetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE)); const WORD foreground_mask = FOREGROUND_BLUE | FOREGROUND_GREEN | - FOREGROUND_RED | FOREGROUND_INTENSITY; + FOREGROUND_RED | FOREGROUND_INTENSITY; const WORD background_mask = BACKGROUND_BLUE | BACKGROUND_GREEN | - BACKGROUND_RED | BACKGROUND_INTENSITY; + BACKGROUND_RED | BACKGROUND_INTENSITY; const WORD color_mask = foreground_mask | background_mask; WORD new_attributes = - ((attributes & FOREGROUND_BLUE )?BACKGROUND_BLUE :0) | - ((attributes & FOREGROUND_GREEN )?BACKGROUND_GREEN :0) | - ((attributes & FOREGROUND_RED )?BACKGROUND_RED :0) | - ((attributes & FOREGROUND_INTENSITY)?BACKGROUND_INTENSITY:0) | - ((attributes & BACKGROUND_BLUE )?FOREGROUND_BLUE :0) | - ((attributes & BACKGROUND_GREEN )?FOREGROUND_GREEN :0) | - ((attributes & BACKGROUND_RED )?FOREGROUND_RED :0) | - ((attributes & BACKGROUND_INTENSITY)?FOREGROUND_INTENSITY:0) | - 0; + ((attributes & FOREGROUND_BLUE) ? BACKGROUND_BLUE : 0) | + ((attributes & FOREGROUND_GREEN) ? BACKGROUND_GREEN : 0) | + ((attributes & FOREGROUND_RED) ? BACKGROUND_RED : 0) | + ((attributes & FOREGROUND_INTENSITY) ? BACKGROUND_INTENSITY : 0) | + ((attributes & BACKGROUND_BLUE) ? FOREGROUND_BLUE : 0) | + ((attributes & BACKGROUND_GREEN) ? FOREGROUND_GREEN : 0) | + ((attributes & BACKGROUND_RED) ? FOREGROUND_RED : 0) | + ((attributes & BACKGROUND_INTENSITY) ? FOREGROUND_INTENSITY : 0) | 0; new_attributes = (attributes & ~color_mask) | (new_attributes & color_mask); SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), new_attributes); @@ -446,7 +433,8 @@ } const char *Process::ResetColor() { - if (UseANSI) return "\033[0m"; + if (UseANSI) + return "\033[0m"; SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), defaultColors()); return 0; } @@ -485,7 +473,7 @@ return GetPseudoRandomNumber(); } -typedef NTSTATUS(WINAPI* RtlGetVersionPtr)(PRTL_OSVERSIONINFOW); +typedef NTSTATUS(WINAPI *RtlGetVersionPtr)(PRTL_OSVERSIONINFOW); #define STATUS_SUCCESS ((NTSTATUS)0x00000000L) llvm::VersionTuple llvm::GetWindowsOSVersion() { diff --git a/llvm/lib/Support/Windows/Program.inc b/llvm/lib/Support/Windows/Program.inc --- a/llvm/lib/Support/Windows/Program.inc +++ b/llvm/lib/Support/Windows/Program.inc @@ -82,8 +82,8 @@ windows::UTF8ToUTF16(Twine(Name + Ext).str(), U16NameExt)) return EC; - Len = ::SearchPathW(Path, c_str(U16NameExt), nullptr, - U16Result.size(), U16Result.data(), nullptr); + Len = ::SearchPathW(Path, c_str(U16NameExt), nullptr, U16Result.size(), + U16Result.data(), nullptr); } while (Len > U16Result.size()); if (Len == 0) @@ -92,7 +92,7 @@ U16Result.truncate(Len); if (std::error_code EC = - windows::UTF16ToUTF8(U16Result.data(), U16Result.size(), U8Result)) + windows::UTF16ToUTF8(U16Result.data(), U16Result.size(), U8Result)) return EC; if (sys::fs::can_execute(U8Result)) @@ -132,8 +132,8 @@ HANDLE h; if (!Path) { if (!DuplicateHandle(GetCurrentProcess(), (HANDLE)_get_osfhandle(fd), - GetCurrentProcess(), &h, - 0, TRUE, DUPLICATE_SAME_ACCESS)) + GetCurrentProcess(), &h, 0, TRUE, + DUPLICATE_SAME_ACCESS)) return INVALID_HANDLE_VALUE; return h; } @@ -162,14 +162,14 @@ FILE_SHARE_READ, &sa, fd == 0 ? OPEN_EXISTING : CREATE_ALWAYS, FILE_ATTRIBUTE_NORMAL, NULL); if (h == INVALID_HANDLE_VALUE) { - MakeErrMsg(ErrMsg, fname + ": Can't open file for " + - (fd ? "input" : "output")); + MakeErrMsg(ErrMsg, + fname + ": Can't open file for " + (fd ? "input" : "output")); } return h; } -} +} // namespace llvm static bool Execute(ProcessInfo &PI, StringRef Program, ArrayRef Args, Optional> Env, @@ -248,8 +248,8 @@ // If stdout and stderr should go to the same place, redirect stderr // to the handle already open for stdout. if (!DuplicateHandle(GetCurrentProcess(), si.hStdOutput, - GetCurrentProcess(), &si.hStdError, - 0, TRUE, DUPLICATE_SAME_ACCESS)) { + GetCurrentProcess(), &si.hStdError, 0, TRUE, + DUPLICATE_SAME_ACCESS)) { CloseHandle(si.hStdInput); CloseHandle(si.hStdOutput); MakeErrMsg(ErrMsg, "can't dup stderr to stdout"); @@ -301,8 +301,8 @@ // Now return an error if the process didn't get created. if (!rc) { SetLastError(err); - MakeErrMsg(ErrMsg, std::string("Couldn't execute program '") + - Program.str() + "'"); + MakeErrMsg(ErrMsg, + std::string("Couldn't execute program '") + Program.str() + "'"); return false; } @@ -490,13 +490,13 @@ return WaitResult; } -std::error_code llvm::sys::ChangeStdinMode(sys::fs::OpenFlags Flags){ +std::error_code llvm::sys::ChangeStdinMode(sys::fs::OpenFlags Flags) { if (!(Flags & fs::OF_CRLF)) return ChangeStdinToBinary(); return std::error_code(); } -std::error_code llvm::sys::ChangeStdoutMode(sys::fs::OpenFlags Flags){ +std::error_code llvm::sys::ChangeStdoutMode(sys::fs::OpenFlags Flags) { if (!(Flags & fs::OF_CRLF)) return ChangeStdoutToBinary(); return std::error_code(); @@ -533,8 +533,8 @@ if ((EC = windows::UTF8ToUTF16(Contents, ArgsUTF16))) return EC; - if ((EC = windows::UTF16ToCurCP( - ArgsUTF16.data(), ArgsUTF16.size(), ArgsCurCP))) + if ((EC = windows::UTF16ToCurCP(ArgsUTF16.data(), ArgsUTF16.size(), + ArgsCurCP))) return EC; OS.write(ArgsCurCP.data(), ArgsCurCP.size()); @@ -574,4 +574,4 @@ assert(!Result.getError()); return (Result->size() + 1) <= MaxCommandStringLength; } -} +} // namespace llvm diff --git a/llvm/lib/Support/Windows/Signals.inc b/llvm/lib/Support/Windows/Signals.inc --- a/llvm/lib/Support/Windows/Signals.inc +++ b/llvm/lib/Support/Windows/Signals.inc @@ -26,98 +26,99 @@ #include "llvm/Support/Windows/WindowsSupport.h" #ifdef __MINGW32__ - #include +#include #else - #include - #include +#include +#include #endif #include #ifdef _MSC_VER - #pragma comment(lib, "psapi.lib") +#pragma comment(lib, "psapi.lib") #elif __MINGW32__ - // The version of g++ that comes with MinGW does *not* properly understand - // the ll format specifier for printf. However, MinGW passes the format - // specifiers on to the MSVCRT entirely, and the CRT understands the ll - // specifier. So these warnings are spurious in this case. Since we compile - // with -Wall, this will generate these warnings which should be ignored. So - // we will turn off the warnings for this just file. However, MinGW also does - // not support push and pop for diagnostics, so we have to manually turn it - // back on at the end of the file. - #pragma GCC diagnostic ignored "-Wformat" - #pragma GCC diagnostic ignored "-Wformat-extra-args" - - #if !defined(__MINGW64_VERSION_MAJOR) - // MinGW.org does not have updated support for the 64-bit versions of the - // DebugHlp APIs. So we will have to load them manually. The structures and - // method signatures were pulled from DbgHelp.h in the Windows Platform SDK, - // and adjusted for brevity. - typedef struct _IMAGEHLP_LINE64 { - DWORD SizeOfStruct; - PVOID Key; - DWORD LineNumber; - PCHAR FileName; - DWORD64 Address; - } IMAGEHLP_LINE64, *PIMAGEHLP_LINE64; - - typedef struct _IMAGEHLP_SYMBOL64 { - DWORD SizeOfStruct; - DWORD64 Address; - DWORD Size; - DWORD Flags; - DWORD MaxNameLength; - CHAR Name[1]; - } IMAGEHLP_SYMBOL64, *PIMAGEHLP_SYMBOL64; - - typedef struct _tagADDRESS64 { - DWORD64 Offset; - WORD Segment; - ADDRESS_MODE Mode; - } ADDRESS64, *LPADDRESS64; - - typedef struct _KDHELP64 { - DWORD64 Thread; - DWORD ThCallbackStack; - DWORD ThCallbackBStore; - DWORD NextCallback; - DWORD FramePointer; - DWORD64 KiCallUserMode; - DWORD64 KeUserCallbackDispatcher; - DWORD64 SystemRangeStart; - DWORD64 KiUserExceptionDispatcher; - DWORD64 StackBase; - DWORD64 StackLimit; - DWORD64 Reserved[5]; - } KDHELP64, *PKDHELP64; - - typedef struct _tagSTACKFRAME64 { - ADDRESS64 AddrPC; - ADDRESS64 AddrReturn; - ADDRESS64 AddrFrame; - ADDRESS64 AddrStack; - ADDRESS64 AddrBStore; - PVOID FuncTableEntry; - DWORD64 Params[4]; - BOOL Far; - BOOL Virtual; - DWORD64 Reserved[3]; - KDHELP64 KdHelp; - } STACKFRAME64, *LPSTACKFRAME64; - #endif // !defined(__MINGW64_VERSION_MAJOR) +// The version of g++ that comes with MinGW does *not* properly understand +// the ll format specifier for printf. However, MinGW passes the format +// specifiers on to the MSVCRT entirely, and the CRT understands the ll +// specifier. So these warnings are spurious in this case. Since we compile +// with -Wall, this will generate these warnings which should be ignored. So +// we will turn off the warnings for this just file. However, MinGW also does +// not support push and pop for diagnostics, so we have to manually turn it +// back on at the end of the file. +#pragma GCC diagnostic ignored "-Wformat" +#pragma GCC diagnostic ignored "-Wformat-extra-args" + +#if !defined(__MINGW64_VERSION_MAJOR) +// MinGW.org does not have updated support for the 64-bit versions of the +// DebugHlp APIs. So we will have to load them manually. The structures and +// method signatures were pulled from DbgHelp.h in the Windows Platform SDK, +// and adjusted for brevity. +typedef struct _IMAGEHLP_LINE64 { + DWORD SizeOfStruct; + PVOID Key; + DWORD LineNumber; + PCHAR FileName; + DWORD64 Address; +} IMAGEHLP_LINE64, *PIMAGEHLP_LINE64; + +typedef struct _IMAGEHLP_SYMBOL64 { + DWORD SizeOfStruct; + DWORD64 Address; + DWORD Size; + DWORD Flags; + DWORD MaxNameLength; + CHAR Name[1]; +} IMAGEHLP_SYMBOL64, *PIMAGEHLP_SYMBOL64; + +typedef struct _tagADDRESS64 { + DWORD64 Offset; + WORD Segment; + ADDRESS_MODE Mode; +} ADDRESS64, *LPADDRESS64; + +typedef struct _KDHELP64 { + DWORD64 Thread; + DWORD ThCallbackStack; + DWORD ThCallbackBStore; + DWORD NextCallback; + DWORD FramePointer; + DWORD64 KiCallUserMode; + DWORD64 KeUserCallbackDispatcher; + DWORD64 SystemRangeStart; + DWORD64 KiUserExceptionDispatcher; + DWORD64 StackBase; + DWORD64 StackLimit; + DWORD64 Reserved[5]; +} KDHELP64, *PKDHELP64; + +typedef struct _tagSTACKFRAME64 { + ADDRESS64 AddrPC; + ADDRESS64 AddrReturn; + ADDRESS64 AddrFrame; + ADDRESS64 AddrStack; + ADDRESS64 AddrBStore; + PVOID FuncTableEntry; + DWORD64 Params[4]; + BOOL Far; + BOOL Virtual; + DWORD64 Reserved[3]; + KDHELP64 KdHelp; +} STACKFRAME64, *LPSTACKFRAME64; +#endif // !defined(__MINGW64_VERSION_MAJOR) #endif // __MINGW32__ -typedef BOOL (__stdcall *PREAD_PROCESS_MEMORY_ROUTINE64)(HANDLE hProcess, - DWORD64 qwBaseAddress, PVOID lpBuffer, DWORD nSize, - LPDWORD lpNumberOfBytesRead); +typedef BOOL(__stdcall *PREAD_PROCESS_MEMORY_ROUTINE64)( + HANDLE hProcess, DWORD64 qwBaseAddress, PVOID lpBuffer, DWORD nSize, + LPDWORD lpNumberOfBytesRead); -typedef PVOID (__stdcall *PFUNCTION_TABLE_ACCESS_ROUTINE64)( HANDLE ahProcess, - DWORD64 AddrBase); +typedef PVOID(__stdcall *PFUNCTION_TABLE_ACCESS_ROUTINE64)(HANDLE ahProcess, + DWORD64 AddrBase); -typedef DWORD64 (__stdcall *PGET_MODULE_BASE_ROUTINE64)(HANDLE hProcess, - DWORD64 Address); +typedef DWORD64(__stdcall *PGET_MODULE_BASE_ROUTINE64)(HANDLE hProcess, + DWORD64 Address); -typedef DWORD64 (__stdcall *PTRANSLATE_ADDRESS_ROUTINE64)(HANDLE hProcess, - HANDLE hThread, LPADDRESS64 lpaddr); +typedef DWORD64(__stdcall *PTRANSLATE_ADDRESS_ROUTINE64)(HANDLE hProcess, + HANDLE hThread, + LPADDRESS64 lpaddr); typedef BOOL(WINAPI *fpMiniDumpWriteDump)(HANDLE, DWORD, HANDLE, MINIDUMP_TYPE, PMINIDUMP_EXCEPTION_INFORMATION, @@ -125,38 +126,40 @@ PMINIDUMP_CALLBACK_INFORMATION); static fpMiniDumpWriteDump fMiniDumpWriteDump; -typedef BOOL (WINAPI *fpStackWalk64)(DWORD, HANDLE, HANDLE, LPSTACKFRAME64, - PVOID, PREAD_PROCESS_MEMORY_ROUTINE64, - PFUNCTION_TABLE_ACCESS_ROUTINE64, - PGET_MODULE_BASE_ROUTINE64, - PTRANSLATE_ADDRESS_ROUTINE64); +typedef BOOL(WINAPI *fpStackWalk64)(DWORD, HANDLE, HANDLE, LPSTACKFRAME64, + PVOID, PREAD_PROCESS_MEMORY_ROUTINE64, + PFUNCTION_TABLE_ACCESS_ROUTINE64, + PGET_MODULE_BASE_ROUTINE64, + PTRANSLATE_ADDRESS_ROUTINE64); static fpStackWalk64 fStackWalk64; -typedef DWORD64 (WINAPI *fpSymGetModuleBase64)(HANDLE, DWORD64); +typedef DWORD64(WINAPI *fpSymGetModuleBase64)(HANDLE, DWORD64); static fpSymGetModuleBase64 fSymGetModuleBase64; -typedef BOOL (WINAPI *fpSymGetSymFromAddr64)(HANDLE, DWORD64, - PDWORD64, PIMAGEHLP_SYMBOL64); +typedef BOOL(WINAPI *fpSymGetSymFromAddr64)(HANDLE, DWORD64, PDWORD64, + PIMAGEHLP_SYMBOL64); static fpSymGetSymFromAddr64 fSymGetSymFromAddr64; -typedef BOOL (WINAPI *fpSymGetLineFromAddr64)(HANDLE, DWORD64, - PDWORD, PIMAGEHLP_LINE64); +typedef BOOL(WINAPI *fpSymGetLineFromAddr64)(HANDLE, DWORD64, PDWORD, + PIMAGEHLP_LINE64); static fpSymGetLineFromAddr64 fSymGetLineFromAddr64; typedef BOOL(WINAPI *fpSymGetModuleInfo64)(HANDLE hProcess, DWORD64 dwAddr, PIMAGEHLP_MODULE64 ModuleInfo); static fpSymGetModuleInfo64 fSymGetModuleInfo64; -typedef PVOID (WINAPI *fpSymFunctionTableAccess64)(HANDLE, DWORD64); +typedef PVOID(WINAPI *fpSymFunctionTableAccess64)(HANDLE, DWORD64); static fpSymFunctionTableAccess64 fSymFunctionTableAccess64; -typedef DWORD (WINAPI *fpSymSetOptions)(DWORD); +typedef DWORD(WINAPI *fpSymSetOptions)(DWORD); static fpSymSetOptions fSymSetOptions; -typedef BOOL (WINAPI *fpSymInitialize)(HANDLE, PCSTR, BOOL); +typedef BOOL(WINAPI *fpSymInitialize)(HANDLE, PCSTR, BOOL); static fpSymInitialize fSymInitialize; -typedef BOOL (WINAPI *fpEnumerateLoadedModules)(HANDLE,PENUMLOADED_MODULES_CALLBACK64,PVOID); +typedef BOOL(WINAPI *fpEnumerateLoadedModules)(HANDLE, + PENUMLOADED_MODULES_CALLBACK64, + PVOID); static fpEnumerateLoadedModules fEnumerateLoadedModules; static bool isDebugHelpInitialized() { @@ -166,24 +169,23 @@ static bool load64BitDebugHelp(void) { HMODULE hLib = ::LoadLibraryW(L"Dbghelp.dll"); if (hLib) { - fMiniDumpWriteDump = (fpMiniDumpWriteDump) - ::GetProcAddress(hLib, "MiniDumpWriteDump"); - fStackWalk64 = (fpStackWalk64) - ::GetProcAddress(hLib, "StackWalk64"); - fSymGetModuleBase64 = (fpSymGetModuleBase64) - ::GetProcAddress(hLib, "SymGetModuleBase64"); - fSymGetSymFromAddr64 = (fpSymGetSymFromAddr64) - ::GetProcAddress(hLib, "SymGetSymFromAddr64"); - fSymGetLineFromAddr64 = (fpSymGetLineFromAddr64) - ::GetProcAddress(hLib, "SymGetLineFromAddr64"); - fSymGetModuleInfo64 = (fpSymGetModuleInfo64) - ::GetProcAddress(hLib, "SymGetModuleInfo64"); - fSymFunctionTableAccess64 = (fpSymFunctionTableAccess64) - ::GetProcAddress(hLib, "SymFunctionTableAccess64"); + fMiniDumpWriteDump = + (fpMiniDumpWriteDump)::GetProcAddress(hLib, "MiniDumpWriteDump"); + fStackWalk64 = (fpStackWalk64)::GetProcAddress(hLib, "StackWalk64"); + fSymGetModuleBase64 = + (fpSymGetModuleBase64)::GetProcAddress(hLib, "SymGetModuleBase64"); + fSymGetSymFromAddr64 = + (fpSymGetSymFromAddr64)::GetProcAddress(hLib, "SymGetSymFromAddr64"); + fSymGetLineFromAddr64 = + (fpSymGetLineFromAddr64)::GetProcAddress(hLib, "SymGetLineFromAddr64"); + fSymGetModuleInfo64 = + (fpSymGetModuleInfo64)::GetProcAddress(hLib, "SymGetModuleInfo64"); + fSymFunctionTableAccess64 = (fpSymFunctionTableAccess64)::GetProcAddress( + hLib, "SymFunctionTableAccess64"); fSymSetOptions = (fpSymSetOptions)::GetProcAddress(hLib, "SymSetOptions"); fSymInitialize = (fpSymInitialize)::GetProcAddress(hLib, "SymInitialize"); - fEnumerateLoadedModules = (fpEnumerateLoadedModules) - ::GetProcAddress(hLib, "EnumerateLoadedModules64"); + fEnumerateLoadedModules = (fpEnumerateLoadedModules)::GetProcAddress( + hLib, "EnumerateLoadedModules64"); } return isDebugHelpInitialized(); } @@ -261,12 +263,11 @@ intptr_t *Offsets; StringSaver *StrPool; }; -} +} // namespace -static BOOL CALLBACK findModuleCallback(PCSTR ModuleName, - DWORD64 ModuleBase, ULONG ModuleSize, - void *VoidData) { - FindModuleData *Data = (FindModuleData*)VoidData; +static BOOL CALLBACK findModuleCallback(PCSTR ModuleName, DWORD64 ModuleBase, + ULONG ModuleSize, void *VoidData) { + FindModuleData *Data = (FindModuleData *)VoidData; intptr_t Beg = ModuleBase; intptr_t End = Beg + ModuleSize; for (int I = 0; I < Data->Depth; I++) { @@ -454,7 +455,7 @@ } // The public API -bool sys::RemoveFileOnSignal(StringRef Filename, std::string* ErrMsg) { +bool sys::RemoveFileOnSignal(StringRef Filename, std::string *ErrMsg) { RegisterHandler(); if (CleanupExecuted) { @@ -482,7 +483,7 @@ std::vector::reverse_iterator I = find(reverse(*FilesToRemove), Filename); if (I != FilesToRemove->rend()) - FilesToRemove->erase(I.base()-1); + FilesToRemove->erase(I.base() - 1); LeaveCriticalSection(&CriticalSection); } @@ -519,7 +520,7 @@ RegisterHandler(); LeaveCriticalSection(&CriticalSection); } -} +} // namespace llvm #if defined(__MINGW32__) && !defined(__MINGW64_VERSION_MAJOR) // Provide a prototype for RtlCaptureContext, mingw32 from mingw.org is @@ -697,8 +698,7 @@ DWORD DumpType; DWORD TypeSize = sizeof(DumpType); if (ERROR_SUCCESS != ::RegGetValueW(Key, NULL, L"DumpType", RRF_RT_REG_DWORD, - NULL, &DumpType, - &TypeSize)) + NULL, &DumpType, &TypeSize)) return false; switch (DumpType) { @@ -865,14 +865,14 @@ // If an interrupt function has been set, go and run one it; otherwise, // the process dies. void (*IF)() = InterruptFunction; - InterruptFunction = 0; // Don't run it on another CTRL-C. + InterruptFunction = 0; // Don't run it on another CTRL-C. if (IF) { // Note: if the interrupt function throws an exception, there is nothing // to catch it in this thread so it will kill the process. - IF(); // Run it now. + IF(); // Run it now. LeaveCriticalSection(&CriticalSection); - return TRUE; // Don't kill the process. + return TRUE; // Don't kill the process. } // Allow normal processing to take place; i.e., the process dies. @@ -881,12 +881,12 @@ } #if __MINGW32__ - // We turned these warnings off for this file so that MinGW-g++ doesn't - // complain about the ll format specifiers used. Now we are turning the - // warnings back on. If MinGW starts to support diagnostic stacks, we can - // replace this with a pop. - #pragma GCC diagnostic warning "-Wformat" - #pragma GCC diagnostic warning "-Wformat-extra-args" +// We turned these warnings off for this file so that MinGW-g++ doesn't +// complain about the ll format specifiers used. Now we are turning the +// warnings back on. If MinGW starts to support diagnostic stacks, we can +// replace this with a pop. +#pragma GCC diagnostic warning "-Wformat" +#pragma GCC diagnostic warning "-Wformat-extra-args" #endif void sys::unregisterHandlers() {} diff --git a/llvm/lib/Support/Windows/ThreadLocal.inc b/llvm/lib/Support/Windows/ThreadLocal.inc --- a/llvm/lib/Support/Windows/ThreadLocal.inc +++ b/llvm/lib/Support/Windows/ThreadLocal.inc @@ -1,4 +1,5 @@ -//= llvm/Support/Win32/ThreadLocal.inc - Win32 Thread Local Data -*- C++ -*-===// +//= llvm/Support/Win32/ThreadLocal.inc - Win32 Thread Local Data -*- C++ +//-*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -15,37 +16,35 @@ //=== is guaranteed to work on *all* Win32 variants. //===----------------------------------------------------------------------===// -#include "llvm/Support/Windows/WindowsSupport.h" #include "llvm/Support/ThreadLocal.h" +#include "llvm/Support/Windows/WindowsSupport.h" namespace llvm { sys::ThreadLocalImpl::ThreadLocalImpl() : data() { static_assert(sizeof(DWORD) <= sizeof(data), "size too big"); - DWORD* tls = reinterpret_cast(&data); + DWORD *tls = reinterpret_cast(&data); *tls = TlsAlloc(); assert(*tls != TLS_OUT_OF_INDEXES); } sys::ThreadLocalImpl::~ThreadLocalImpl() { - DWORD* tls = reinterpret_cast(&data); + DWORD *tls = reinterpret_cast(&data); TlsFree(*tls); } void *sys::ThreadLocalImpl::getInstance() { - DWORD* tls = reinterpret_cast(&data); + DWORD *tls = reinterpret_cast(&data); return TlsGetValue(*tls); } -void sys::ThreadLocalImpl::setInstance(const void* d){ - DWORD* tls = reinterpret_cast(&data); - int errorcode = TlsSetValue(*tls, const_cast(d)); +void sys::ThreadLocalImpl::setInstance(const void *d) { + DWORD *tls = reinterpret_cast(&data); + int errorcode = TlsSetValue(*tls, const_cast(d)); assert(errorcode != 0); (void)errorcode; } -void sys::ThreadLocalImpl::removeInstance() { - setInstance(0); -} +void sys::ThreadLocalImpl::removeInstance() { setInstance(0); } -} +} // namespace llvm diff --git a/llvm/lib/Support/Windows/Threading.inc b/llvm/lib/Support/Windows/Threading.inc --- a/llvm/lib/Support/Windows/Threading.inc +++ b/llvm/lib/Support/Windows/Threading.inc @@ -49,19 +49,13 @@ } } -DWORD llvm_thread_get_id_impl(HANDLE hThread) { - return ::GetThreadId(hThread); -} +DWORD llvm_thread_get_id_impl(HANDLE hThread) { return ::GetThreadId(hThread); } -DWORD llvm_thread_get_current_id_impl() { - return ::GetCurrentThreadId(); -} +DWORD llvm_thread_get_current_id_impl() { return ::GetCurrentThreadId(); } } // namespace llvm -uint64_t llvm::get_threadid() { - return uint64_t(::GetCurrentThreadId()); -} +uint64_t llvm::get_threadid() { return uint64_t(::GetCurrentThreadId()); } uint32_t llvm::get_max_thread_name_length() { return 0; } @@ -86,9 +80,8 @@ __try { ::RaiseException(MS_VC_EXCEPTION, 0, sizeof(info) / sizeof(ULONG_PTR), - (ULONG_PTR *)&info); - } - __except (EXCEPTION_EXECUTE_HANDLER) { + (ULONG_PTR *)&info); + } __except (EXCEPTION_EXECUTE_HANDLER) { } } #endif @@ -247,7 +240,7 @@ return Cores; } -int computeHostNumHardwareThreads() { +static int computeHostNumHardwareThreads() { static unsigned Threads = aggregate(getProcessorGroups(), [](const ProcessorGroup &G) { return G.UsableThreads; }); diff --git a/llvm/lib/Support/Windows/Watchdog.inc b/llvm/lib/Support/Windows/Watchdog.inc --- a/llvm/lib/Support/Windows/Watchdog.inc +++ b/llvm/lib/Support/Windows/Watchdog.inc @@ -16,8 +16,8 @@ // and a second thread to run the TimerAPCProc. namespace llvm { - namespace sys { - Watchdog::Watchdog(unsigned int seconds) {} - Watchdog::~Watchdog() {} - } -} +namespace sys { +Watchdog::Watchdog(unsigned int seconds) {} +Watchdog::~Watchdog() {} +} // namespace sys +} // namespace llvm diff --git a/llvm/lib/Support/Windows/explicit_symbols.inc b/llvm/lib/Support/Windows/explicit_symbols.inc --- a/llvm/lib/Support/Windows/explicit_symbols.inc +++ b/llvm/lib/Support/Windows/explicit_symbols.inc @@ -1,94 +1,94 @@ /* in libgcc.a */ #ifdef HAVE__ALLOCA - EXPLICIT_SYMBOL(_alloca) - EXPLICIT_SYMBOL2(alloca, _alloca) +EXPLICIT_SYMBOL(_alloca) +EXPLICIT_SYMBOL2(alloca, _alloca) #endif #ifdef HAVE___ALLOCA - EXPLICIT_SYMBOL(__alloca) +EXPLICIT_SYMBOL(__alloca) #endif #ifdef HAVE___CHKSTK - EXPLICIT_SYMBOL(__chkstk) +EXPLICIT_SYMBOL(__chkstk) #endif #ifdef HAVE___CHKSTK_MS - EXPLICIT_SYMBOL(__chkstk_ms) +EXPLICIT_SYMBOL(__chkstk_ms) #endif #ifdef HAVE____CHKSTK - EXPLICIT_SYMBOL(___chkstk) +EXPLICIT_SYMBOL(___chkstk) #endif #ifdef HAVE____CHKSTK_MS - EXPLICIT_SYMBOL(___chkstk_ms) +EXPLICIT_SYMBOL(___chkstk_ms) #endif #ifdef HAVE___MAIN - EXPLICIT_SYMBOL(__main) // FIXME: Don't call it. +EXPLICIT_SYMBOL(__main) // FIXME: Don't call it. #endif #ifdef HAVE___ASHLDI3 - EXPLICIT_SYMBOL(__ashldi3) +EXPLICIT_SYMBOL(__ashldi3) #endif #ifdef HAVE___ASHRDI3 - EXPLICIT_SYMBOL(__ashrdi3) +EXPLICIT_SYMBOL(__ashrdi3) #endif #ifdef HAVE___CMPDI2 // FIXME: unused - EXPLICIT_SYMBOL(__cmpdi2) +EXPLICIT_SYMBOL(__cmpdi2) #endif #ifdef HAVE___DIVDI3 - EXPLICIT_SYMBOL(__divdi3) +EXPLICIT_SYMBOL(__divdi3) #endif #ifdef HAVE___FIXDFDI - EXPLICIT_SYMBOL(__fixdfdi) +EXPLICIT_SYMBOL(__fixdfdi) #endif #ifdef HAVE___FIXSFDI - EXPLICIT_SYMBOL(__fixsfdi) +EXPLICIT_SYMBOL(__fixsfdi) #endif #ifdef HAVE___FIXUNSDFDI - EXPLICIT_SYMBOL(__fixunsdfdi) +EXPLICIT_SYMBOL(__fixunsdfdi) #endif #ifdef HAVE___FIXUNSSFDI - EXPLICIT_SYMBOL(__fixunssfdi) +EXPLICIT_SYMBOL(__fixunssfdi) #endif #ifdef HAVE___FLOATDIDF - EXPLICIT_SYMBOL(__floatdidf) +EXPLICIT_SYMBOL(__floatdidf) #endif #ifdef HAVE___FLOATDISF - EXPLICIT_SYMBOL(__floatdisf) +EXPLICIT_SYMBOL(__floatdisf) #endif #ifdef HAVE___LSHRDI3 - EXPLICIT_SYMBOL(__lshrdi3) +EXPLICIT_SYMBOL(__lshrdi3) #endif #ifdef HAVE___MODDI3 - EXPLICIT_SYMBOL(__moddi3) +EXPLICIT_SYMBOL(__moddi3) #endif #ifdef HAVE___UDIVDI3 - EXPLICIT_SYMBOL(__udivdi3) +EXPLICIT_SYMBOL(__udivdi3) #endif #ifdef HAVE___UMODDI3 - EXPLICIT_SYMBOL(__umoddi3) +EXPLICIT_SYMBOL(__umoddi3) #endif /* msvcrt */ #if defined(_MSC_VER) - EXPLICIT_SYMBOL2(alloca, _alloca_probe) +EXPLICIT_SYMBOL2(alloca, _alloca_probe) #ifdef _M_IX86 #define INLINE_DEF_FLOAT_SYMBOL(SYM, ARGC) INLINE_DEF_SYMBOL##ARGC(float, SYM) - INLINE_DEF_FLOAT_SYMBOL(acosf, 1) - INLINE_DEF_FLOAT_SYMBOL(asinf, 1) - INLINE_DEF_FLOAT_SYMBOL(atanf, 1) - INLINE_DEF_FLOAT_SYMBOL(atan2f, 2) - INLINE_DEF_FLOAT_SYMBOL(ceilf, 1) - INLINE_DEF_FLOAT_SYMBOL(cosf, 1) - INLINE_DEF_FLOAT_SYMBOL(coshf, 1) - INLINE_DEF_FLOAT_SYMBOL(expf, 1) - INLINE_DEF_FLOAT_SYMBOL(floorf, 1) - INLINE_DEF_FLOAT_SYMBOL(fmodf, 2) - INLINE_DEF_FLOAT_SYMBOL(logf, 1) - INLINE_DEF_FLOAT_SYMBOL(powf, 2) - INLINE_DEF_FLOAT_SYMBOL(sinf, 1) - INLINE_DEF_FLOAT_SYMBOL(sinhf, 1) - INLINE_DEF_FLOAT_SYMBOL(sqrtf, 1) - INLINE_DEF_FLOAT_SYMBOL(tanf, 1) - INLINE_DEF_FLOAT_SYMBOL(tanhf, 1) +INLINE_DEF_FLOAT_SYMBOL(acosf, 1) +INLINE_DEF_FLOAT_SYMBOL(asinf, 1) +INLINE_DEF_FLOAT_SYMBOL(atanf, 1) +INLINE_DEF_FLOAT_SYMBOL(atan2f, 2) +INLINE_DEF_FLOAT_SYMBOL(ceilf, 1) +INLINE_DEF_FLOAT_SYMBOL(cosf, 1) +INLINE_DEF_FLOAT_SYMBOL(coshf, 1) +INLINE_DEF_FLOAT_SYMBOL(expf, 1) +INLINE_DEF_FLOAT_SYMBOL(floorf, 1) +INLINE_DEF_FLOAT_SYMBOL(fmodf, 2) +INLINE_DEF_FLOAT_SYMBOL(logf, 1) +INLINE_DEF_FLOAT_SYMBOL(powf, 2) +INLINE_DEF_FLOAT_SYMBOL(sinf, 1) +INLINE_DEF_FLOAT_SYMBOL(sinhf, 1) +INLINE_DEF_FLOAT_SYMBOL(sqrtf, 1) +INLINE_DEF_FLOAT_SYMBOL(tanf, 1) +INLINE_DEF_FLOAT_SYMBOL(tanhf, 1) #undef INLINE_DEF_FLOAT_SYMBOL #endif diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -507,6 +507,14 @@ def FeatureMEC : SubtargetFeature<"mec", "HasMEC", "true", "Enable Memory Encryption Contexts Extension", [FeatureRME]>; +def FeatureITE : SubtargetFeature<"ite", "HasITE", + "true", "Enable Armv9.4-A Instrumentation Extension FEAT_ITE", [FeatureETE, + FeatureTRBE]>; + +def FeatureRCPC3 : SubtargetFeature<"rcpc3", "HasRCPC3", + "true", "Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set (FEAT_LRCPC3)", + [FeatureRCPC_IMMO]>; + //===----------------------------------------------------------------------===// // Architectures. // diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp --- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp +++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp @@ -306,7 +306,7 @@ // ;DATA: higher 32 bits of the address of the trampoline // LDP X0, X30, [SP], #16 ; pop X0 and the link register from the stack // - OutStreamer->emitCodeAlignment(4, &getSubtargetInfo()); + OutStreamer->emitCodeAlignment(Align(4), &getSubtargetInfo()); auto CurSled = OutContext.createTempSymbol("xray_sled_", true); OutStreamer->emitLabel(CurSled); auto Target = OutContext.createTempSymbol(); diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -228,6 +228,7 @@ #include #include #include +#include #include using namespace llvm; @@ -3392,7 +3393,7 @@ StackOffset FrameRegOffset; int64_t Size; // If not None, move FrameReg to (FrameReg + FrameRegUpdate) at the end. - Optional FrameRegUpdate; + std::optional FrameRegUpdate; // MIFlags for any FrameReg updating instructions. unsigned FrameRegUpdateFlags; @@ -3734,7 +3735,7 @@ // Find contiguous runs of tagged memory and emit shorter instruction // sequencies for them when possible. TagStoreEdit TSE(MBB, FirstZeroData); - Optional EndOffset; + std::optional EndOffset; for (auto &Instr : Instrs) { if (EndOffset && *EndOffset != Instr.Offset) { // Found a gap. diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -92,6 +92,7 @@ #include #include #include +#include #include #include #include @@ -343,7 +344,7 @@ addQRTypeForNEON(MVT::v8bf16); } - if (Subtarget->hasSVE() || Subtarget->hasSME()) { + if (Subtarget->hasSVEorSME()) { // Add legal sve predicate types addRegisterClass(MVT::nxv1i1, &AArch64::PPRRegClass); addRegisterClass(MVT::nxv2i1, &AArch64::PPRRegClass); @@ -1155,7 +1156,7 @@ // FIXME: Move lowering for more nodes here if those are common between // SVE and SME. - if (Subtarget->hasSVE() || Subtarget->hasSME()) { + if (Subtarget->hasSVEorSME()) { for (auto VT : {MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1, MVT::nxv1i1}) { setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); @@ -1643,6 +1644,31 @@ setOperationAction(ISD::FMINNUM, VT, Custom); setOperationAction(ISD::FMAXIMUM, VT, Custom); setOperationAction(ISD::FMINIMUM, VT, Custom); + setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); + setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); + setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom); + setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom); + setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); + setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); + setOperationAction(ISD::FP_ROUND, VT, Custom); + setOperationAction(ISD::FCEIL, VT, Custom); + setOperationAction(ISD::FFLOOR, VT, Custom); + setOperationAction(ISD::FNEARBYINT, VT, Custom); + setOperationAction(ISD::FRINT, VT, Custom); + setOperationAction(ISD::FROUND, VT, Custom); + setOperationAction(ISD::FROUNDEVEN, VT, Custom); + setOperationAction(ISD::FTRUNC, VT, Custom); + if (VT.isFloatingPoint()) { + setCondCodeAction(ISD::SETO, VT, Expand); + setCondCodeAction(ISD::SETOLT, VT, Expand); + setCondCodeAction(ISD::SETOLE, VT, Expand); + setCondCodeAction(ISD::SETULT, VT, Expand); + setCondCodeAction(ISD::SETULE, VT, Expand); + setCondCodeAction(ISD::SETUGE, VT, Expand); + setCondCodeAction(ISD::SETUGT, VT, Expand); + setCondCodeAction(ISD::SETUEQ, VT, Expand); + setCondCodeAction(ISD::SETONE, VT, Expand); + } } void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) { @@ -1658,9 +1684,7 @@ if (VT.isFloatingPoint()) { setCondCodeAction(ISD::SETO, VT, Expand); setCondCodeAction(ISD::SETOLT, VT, Expand); - setCondCodeAction(ISD::SETLT, VT, Expand); setCondCodeAction(ISD::SETOLE, VT, Expand); - setCondCodeAction(ISD::SETLE, VT, Expand); setCondCodeAction(ISD::SETULT, VT, Expand); setCondCodeAction(ISD::SETULE, VT, Expand); setCondCodeAction(ISD::SETUGE, VT, Expand); @@ -8318,7 +8342,8 @@ IntVT = getPackedSVEVectorVT(VT.getVectorElementType().changeTypeToInteger()); - if (VT.isFixedLengthVector() && useSVEForFixedLengthVectorVT(VT)) { + if (VT.isFixedLengthVector() && + useSVEForFixedLengthVectorVT(VT, Subtarget->forceStreamingCompatibleSVE())) { EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT); In1 = convertToScalableVector(DAG, ContainerVT, In1); @@ -11945,6 +11970,11 @@ // Try to build a simple constant vector. Op = NormalizeBuildVector(Op, DAG); + // Thought this might return a non-BUILD_VECTOR (e.g. CONCAT_VECTORS), if so, + // abort. + if (Op.getOpcode() != ISD::BUILD_VECTOR) + return SDValue(); + if (VT.isInteger()) { // Certain vector constants, used to express things like logical NOT and // arithmetic NEG, are passed through unmodified. This allows special @@ -12886,7 +12916,8 @@ if (Op.getValueType().isScalableVector()) return LowerToPredicatedOp(Op, DAG, AArch64ISD::SETCC_MERGE_ZERO); - if (useSVEForFixedLengthVectorVT(Op.getOperand(0).getValueType())) + if (useSVEForFixedLengthVectorVT(Op.getOperand(0).getValueType(), + Subtarget->forceStreamingCompatibleSVE())) return LowerFixedLengthVectorSetccToSVE(Op, DAG); ISD::CondCode CC = cast(Op.getOperand(2))->get(); @@ -12964,7 +12995,8 @@ // Try to lower fixed length reductions to SVE. EVT SrcVT = Src.getValueType(); - bool OverrideNEON = Op.getOpcode() == ISD::VECREDUCE_AND || + bool OverrideNEON = Subtarget->forceStreamingCompatibleSVE() || + Op.getOpcode() == ISD::VECREDUCE_AND || Op.getOpcode() == ISD::VECREDUCE_OR || Op.getOpcode() == ISD::VECREDUCE_XOR || Op.getOpcode() == ISD::VECREDUCE_FADD || @@ -14989,17 +15021,20 @@ return CSNeg; } -static bool IsSVECntIntrinsic(SDValue S) { +static std::optional IsSVECntIntrinsic(SDValue S) { switch(getIntrinsicID(S.getNode())) { default: break; case Intrinsic::aarch64_sve_cntb: + return 8; case Intrinsic::aarch64_sve_cnth: + return 16; case Intrinsic::aarch64_sve_cntw: + return 32; case Intrinsic::aarch64_sve_cntd: - return true; + return 64; } - return false; + return {}; } /// Calculates what the pre-extend type is, based on the extension @@ -16912,7 +16947,7 @@ // (CSEL 1 0 CC Cond) => CC // (CSEL 0 1 CC Cond) => !CC -static Optional getCSETCondCode(SDValue Op) { +static std::optional getCSETCondCode(SDValue Op) { if (Op.getOpcode() != AArch64ISD::CSEL) return None; auto CC = static_cast(Op.getConstantOperandVal(2)); @@ -22851,7 +22886,7 @@ EVT InVT = Op.getOperand(0).getValueType(); EVT ContainerVT = getContainerForFixedLengthVector(DAG, InVT); - assert(useSVEForFixedLengthVectorVT(InVT) && + assert(InVT.isFixedLengthVector() && isTypeLegal(InVT) && "Only expected to lower fixed length vector operation!"); assert(Op.getValueType() == InVT.changeTypeToInteger() && "Expected integer result of the same bit length as the inputs!"); @@ -23279,6 +23314,24 @@ // used - simplify to just Val. return TLO.CombineTo(Op, ShiftR->getOperand(0)); } + case ISD::INTRINSIC_WO_CHAIN: { + if (auto ElementSize = IsSVECntIntrinsic(Op)) { + unsigned MaxSVEVectorSizeInBits = Subtarget->getMaxSVEVectorSizeInBits(); + if (!MaxSVEVectorSizeInBits) + MaxSVEVectorSizeInBits = AArch64::SVEMaxBitsPerVector; + unsigned MaxElements = MaxSVEVectorSizeInBits / *ElementSize; + // The SVE count intrinsics don't support the multiplier immediate so we + // don't have to account for that here. The value returned may be slightly + // over the true required bits, as this is based on the "ALL" pattern. The + // other patterns are also exposed by these intrinsics, but they all + // return a value that's strictly less than "ALL". + unsigned RequiredBits = Log2_32(MaxElements) + 1; + unsigned BitWidth = Known.Zero.getBitWidth(); + if (RequiredBits < BitWidth) + Known.Zero.setHighBits(BitWidth - RequiredBits); + return false; + } + } } return TargetLowering::SimplifyDemandedBitsForTargetNode( diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td --- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td +++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td @@ -4552,7 +4552,7 @@ class StoreRelease sz, bit o2, bit L, bit o1, bit o0, RegisterClass regtype, string asm> : LoadStoreExclusiveSimple, Sched<[WriteST]>; @@ -11758,6 +11758,90 @@ !not(isUnsigned) : simm8_64b), asm, OpNode>; } +//---------------------------------------------------------------------------- +// 2022 Armv8.9/Armv9.4 Extensions +//---------------------------------------------------------------------------- + +//--- +// RCPC instructions (FEAT_LRCPC3) +//--- + +class BaseLRCPC3 size, bit V, bits<2> opc, dag oops, dag iops, + string asm, string operands, string cstr = ""> + : I, + Sched<[WriteAtomic]> { + bits<5> Rt; + bits<5> Rn; + let Inst{31-30} = size; + let Inst{29-24} = {0,1,1,V,0,1}; + let Inst{23-22} = opc; + let Inst{21} = 0b0; + // Inst{20-12} + let Inst{11-10} = 0b10; + let Inst{9-5} = Rn; + let Inst{4-0} = Rt; + + let mayLoad = Inst{22}; + let mayStore = !not(Inst{22}); + let hasSideEffects = 0; +} + +class BaseLRCPC3IntegerLoadStorePair size, bits<2> opc, bits<4> opc2, + dag oops, dag iops, string asm, + string operands, string cstr> + : BaseLRCPC3 { + bits<5> Rt2; + let Inst{20-16} = Rt2; + let Inst{15-12} = opc2; +} + +class BaseLRCPC3IntegerLoadStore size, bits<2> opc, dag oops, dag iops, + string asm, string operands, string cstr> + : BaseLRCPC3 { + let Inst{20-12} = 0b000000000; // imm9 +} + +multiclass LRCPC3NEONLoadStoreUnscaledOffset size, bits<2> opc, RegisterClass regtype, + dag oops, dag iops, string asm> { + def i : BaseLRCPC3 { + bits<9> simm; // signed immediate encoded in imm9=Rt2:imm4 + let Inst{20-12} = simm; + } + + def a : InstAlias(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>; +} + +class LRCPC3NEONLdStSingle + : BaseSIMDLdStSingle, + Sched<[]> { + bit Q; + let Inst{31} = 0; + let Inst{30} = Q; + let Inst{23} = 0; + let Inst{20-16} = 0b00001; + let Inst{12} = 0; // S + let Inst{11-10} = 0b01; // size + + let mayLoad = L; + let mayStore = !not(L); + let hasSideEffects = 1; +} + +//--- +// Instrumentation Extension (FEAT_ITE) +//--- + +let Predicates = [HasITE] in +def TRCIT : RtSystemI<0b0, (outs), (ins GPR64:$Rt), "trcit", "\t$Rt"> { + let Inst{20-19} = 0b01; + let Inst{18-16} = 0b011; + let Inst{15-12} = 0b0111; + let Inst{11-8} = 0b0010; + let Inst{7-5} = 0b111; +} + //---------------------------------------------------------------------------- // Allow the size specifier tokens to be upper case, not just lower. def : TokenAlias<".4B", ".4b">; // Add dot product diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -3535,8 +3535,7 @@ // Copy a Predicate register by ORRing with itself. if (AArch64::PPRRegClass.contains(DestReg) && AArch64::PPRRegClass.contains(SrcReg)) { - assert((Subtarget.hasSVE() || Subtarget.hasSME()) && - "Unexpected SVE register."); + assert(Subtarget.hasSVEorSME() && "Unexpected SVE register."); BuildMI(MBB, I, DL, get(AArch64::ORR_PPzPP), DestReg) .addReg(SrcReg) // Pg .addReg(SrcReg) @@ -3547,8 +3546,7 @@ // Copy a Z register by ORRing with itself. if (AArch64::ZPRRegClass.contains(DestReg) && AArch64::ZPRRegClass.contains(SrcReg)) { - assert((Subtarget.hasSVE() || Subtarget.hasSME()) && - "Unexpected SVE register."); + assert(Subtarget.hasSVEorSME() && "Unexpected SVE register."); BuildMI(MBB, I, DL, get(AArch64::ORR_ZZZ), DestReg) .addReg(SrcReg) .addReg(SrcReg, getKillRegState(KillSrc)); @@ -3558,8 +3556,7 @@ // Copy a Z register pair by copying the individual sub-registers. if (AArch64::ZPR2RegClass.contains(DestReg) && AArch64::ZPR2RegClass.contains(SrcReg)) { - assert((Subtarget.hasSVE() || Subtarget.hasSME()) && - "Unexpected SVE register."); + assert(Subtarget.hasSVEorSME() && "Unexpected SVE register."); static const unsigned Indices[] = {AArch64::zsub0, AArch64::zsub1}; copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORR_ZZZ, Indices); @@ -3569,8 +3566,7 @@ // Copy a Z register triple by copying the individual sub-registers. if (AArch64::ZPR3RegClass.contains(DestReg) && AArch64::ZPR3RegClass.contains(SrcReg)) { - assert((Subtarget.hasSVE() || Subtarget.hasSME()) && - "Unexpected SVE register."); + assert(Subtarget.hasSVEorSME() && "Unexpected SVE register."); static const unsigned Indices[] = {AArch64::zsub0, AArch64::zsub1, AArch64::zsub2}; copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORR_ZZZ, @@ -3581,8 +3577,7 @@ // Copy a Z register quad by copying the individual sub-registers. if (AArch64::ZPR4RegClass.contains(DestReg) && AArch64::ZPR4RegClass.contains(SrcReg)) { - assert((Subtarget.hasSVE() || Subtarget.hasSME()) && - "Unexpected SVE register."); + assert(Subtarget.hasSVEorSME() && "Unexpected SVE register."); static const unsigned Indices[] = {AArch64::zsub0, AArch64::zsub1, AArch64::zsub2, AArch64::zsub3}; copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORR_ZZZ, @@ -4965,6 +4960,17 @@ return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath || (Inst.getFlag(MachineInstr::MIFlag::FmReassoc) && Inst.getFlag(MachineInstr::MIFlag::FmNsz)); + case AArch64::ADDXrr: + case AArch64::ANDXrr: + case AArch64::ORRXrr: + case AArch64::EORXrr: + case AArch64::EONXrr: + case AArch64::ADDWrr: + case AArch64::ANDWrr: + case AArch64::ORRWrr: + case AArch64::EORWrr: + case AArch64::EONWrr: + return true; default: return false; } diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -166,7 +166,7 @@ // A subset of SVE(2) instructions are legal in Streaming SVE execution mode, // they should be enabled if either has been specified. def HasSVEorSME - : Predicate<"Subtarget->hasSVE() || Subtarget->hasSME()">, + : Predicate<"Subtarget->hasSVEorSME()">, AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME), "sve or sme">; def HasSVE2orSME @@ -232,6 +232,10 @@ AssemblerPredicateWithAll<(all_of FeatureHBC), "hbc">; def HasMOPS : Predicate<"Subtarget->hasMOPS()">, AssemblerPredicateWithAll<(all_of FeatureMOPS), "mops">; +def HasITE : Predicate<"Subtarget->hasITE()">, + AssemblerPredicateWithAll<(all_of FeatureITE), "ite">; +def HasRCPC3 : Predicate<"Subtarget->hasRCPC3()">, + AssemblerPredicate<(all_of FeatureRCPC3), "rcpc3">; def IsLE : Predicate<"Subtarget->isLittleEndian()">; def IsBE : Predicate<"!Subtarget->isLittleEndian()">; def IsWindows : Predicate<"Subtarget->isTargetWindows()">; @@ -3901,6 +3905,21 @@ def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">; def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">; +/* +Aliases for when offset=0. Note that in contrast to LoadAcquire which has a $Rn +of type GPR64sp0, we deliberately choose to make $Rn of type GPR64sp and add an +alias for the case of immediate #0. This is because new STLR versions (from +LRCPC3 extension) do have a non-zero immediate value, so GPR64sp0 is not +appropriate anymore (it parses and discards the optional zero). This is not the +case for LoadAcquire because the new LRCPC3 LDAR instructions are post-indexed, +and the immediate values are not inside the [] brackets and thus not accepted +by GPR64sp0 parser. +*/ +def STLRW0 : InstAlias<"stlr\t$Rt, [$Rn, #0]" , (STLRW GPR32: $Rt, GPR64sp:$Rn)>; +def STLRX0 : InstAlias<"stlr\t$Rt, [$Rn, #0]" , (STLRX GPR64: $Rt, GPR64sp:$Rn)>; +def STLRB0 : InstAlias<"stlrb\t$Rt, [$Rn, #0]", (STLRB GPR32: $Rt, GPR64sp:$Rn)>; +def STLRH0 : InstAlias<"stlrh\t$Rt, [$Rn, #0]", (STLRH GPR32: $Rt, GPR64sp:$Rn)>; + def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">; def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">; def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">; @@ -3935,6 +3954,12 @@ def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">; def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">; def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">; + + // Aliases for when offset=0 + def STLLRW0 : InstAlias<"stllr\t$Rt, [$Rn, #0]", (STLLRW GPR32: $Rt, GPR64sp:$Rn)>; + def STLLRX0 : InstAlias<"stllr\t$Rt, [$Rn, #0]", (STLLRX GPR64: $Rt, GPR64sp:$Rn)>; + def STLLRB0 : InstAlias<"stllrb\t$Rt, [$Rn, #0]", (STLLRB GPR32: $Rt, GPR64sp:$Rn)>; + def STLLRH0 : InstAlias<"stllrh\t$Rt, [$Rn, #0]", (STLLRH GPR32: $Rt, GPR64sp:$Rn)>; } //===----------------------------------------------------------------------===// @@ -8526,6 +8551,53 @@ let DecoderNamespace = "Fallback"; } +//===----------------------------------------------------------------------===// +// RCPC Instructions (FEAT_LRCPC3) +//===----------------------------------------------------------------------===// + +let Predicates = [HasRCPC3] in { + // size opc opc2 + def STILPWpre: BaseLRCPC3IntegerLoadStorePair<0b10, 0b00, 0b0000, (outs GPR64sp:$wback), (ins GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn, #-8]!", "$Rn = $wback">; + def STILPXpre: BaseLRCPC3IntegerLoadStorePair<0b11, 0b00, 0b0000, (outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn, #-16]!", "$Rn = $wback">; + def STILPW: BaseLRCPC3IntegerLoadStorePair<0b10, 0b00, 0b0001, (outs), (ins GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn]", "">; + def STILPX: BaseLRCPC3IntegerLoadStorePair<0b11, 0b00, 0b0001, (outs), (ins GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, [$Rn]", "">; + def LDIAPPWpre: BaseLRCPC3IntegerLoadStorePair<0b10, 0b01, 0b0000, (outs GPR64sp:$wback, GPR32:$Rt, GPR32:$Rt2), (ins GPR64sp:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn], #8", "$Rn = $wback">; + def LDIAPPXpre: BaseLRCPC3IntegerLoadStorePair<0b11, 0b01, 0b0000, (outs GPR64sp:$wback, GPR64:$Rt, GPR64:$Rt2), (ins GPR64sp:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn], #16", "$Rn = $wback">; + def LDIAPPW: BaseLRCPC3IntegerLoadStorePair<0b10, 0b01, 0b0001, (outs GPR32:$Rt, GPR32:$Rt2), (ins GPR64sp0:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn]", "">; + def LDIAPPX: BaseLRCPC3IntegerLoadStorePair<0b11, 0b01, 0b0001, (outs GPR64:$Rt, GPR64:$Rt2), (ins GPR64sp0:$Rn), "ldiapp", "\t$Rt, $Rt2, [$Rn]", "">; + + // Aliases for when offset=0 + def : InstAlias<"stilp\t$Rt, $Rt2, [$Rn, #0]", (STILPW GPR32: $Rt, GPR32: $Rt2, GPR64sp:$Rn)>; + def : InstAlias<"stilp\t$Rt, $Rt2, [$Rn, #0]", (STILPX GPR64: $Rt, GPR64: $Rt2, GPR64sp:$Rn)>; + + // size opc + def STLRWpre: BaseLRCPC3IntegerLoadStore<0b10, 0b10, (outs GPR64sp:$wback), (ins GPR32:$Rt, GPR64sp:$Rn), "stlr", "\t$Rt, [$Rn, #-4]!", "$Rn = $wback">; + def STLRXpre: BaseLRCPC3IntegerLoadStore<0b11, 0b10, (outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64sp:$Rn), "stlr", "\t$Rt, [$Rn, #-8]!", "$Rn = $wback">; + def LDAPRWpre: BaseLRCPC3IntegerLoadStore<0b10, 0b11, (outs GPR64sp:$wback, GPR32:$Rt), (ins GPR64sp:$Rn), "ldapr", "\t$Rt, [$Rn], #4", "$Rn = $wback">; + def LDAPRXpre: BaseLRCPC3IntegerLoadStore<0b11, 0b11, (outs GPR64sp:$wback, GPR64:$Rt), (ins GPR64sp:$Rn), "ldapr", "\t$Rt, [$Rn], #8", "$Rn = $wback">; +} + +let Predicates = [HasRCPC3, HasNEON] in { + // size opc regtype + defm STLURb: LRCPC3NEONLoadStoreUnscaledOffset<0b00, 0b00, FPR8 , (outs), (ins FPR8 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">; + defm STLURh: LRCPC3NEONLoadStoreUnscaledOffset<0b01, 0b00, FPR16 , (outs), (ins FPR16 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">; + defm STLURs: LRCPC3NEONLoadStoreUnscaledOffset<0b10, 0b00, FPR32 , (outs), (ins FPR32 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">; + defm STLURd: LRCPC3NEONLoadStoreUnscaledOffset<0b11, 0b00, FPR64 , (outs), (ins FPR64 :$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">; + defm STLURq: LRCPC3NEONLoadStoreUnscaledOffset<0b00, 0b10, FPR128, (outs), (ins FPR128:$Rt, GPR64sp:$Rn, simm9:$simm), "stlur">; + defm LDAPURb: LRCPC3NEONLoadStoreUnscaledOffset<0b00, 0b01, FPR8 , (outs FPR8 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">; + defm LDAPURh: LRCPC3NEONLoadStoreUnscaledOffset<0b01, 0b01, FPR16 , (outs FPR16 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">; + defm LDAPURs: LRCPC3NEONLoadStoreUnscaledOffset<0b10, 0b01, FPR32 , (outs FPR32 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">; + defm LDAPURd: LRCPC3NEONLoadStoreUnscaledOffset<0b11, 0b01, FPR64 , (outs FPR64 :$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">; + defm LDAPURq: LRCPC3NEONLoadStoreUnscaledOffset<0b00, 0b11, FPR128, (outs FPR128:$Rt), (ins GPR64sp:$Rn, simm9:$simm), "ldapur">; + + // L + def STL1: LRCPC3NEONLdStSingle<0b0, (outs), (ins VecListOned:$Vt, VectorIndexD:$Q, GPR64sp:$Rn) , "stl1", "">; + def LDAP1: LRCPC3NEONLdStSingle<0b1, (outs VecListOned:$dst), (ins VecListOned:$Vt, VectorIndexD:$Q, GPR64sp0:$Rn), "ldap1", "$Vt = $dst">; + + // Aliases for when offset=0 + def : InstAlias<"stl1\t$Vt$Q, [$Rn, #0]", (STL1 VecListOned:$Vt, VectorIndexD:$Q, GPR64sp:$Rn)>; +} + include "AArch64InstrAtomics.td" include "AArch64SVEInstrInfo.td" include "AArch64SMEInstrInfo.td" diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp --- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -50,6 +50,7 @@ #include #include #include +#include using namespace llvm; @@ -1531,7 +1532,7 @@ int OffsetStride = IsUnscaled ? TII->getMemScale(FirstMI) : 1; bool IsPromotableZeroStore = isPromotableZeroStoreInst(FirstMI); - Optional MaybeCanRename; + std::optional MaybeCanRename; if (!EnableRenaming) MaybeCanRename = {false}; diff --git a/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp b/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp --- a/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp +++ b/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp @@ -26,6 +26,7 @@ #include "llvm/IR/IRBuilder.h" #include "llvm/Pass.h" #include "llvm/Support/raw_ostream.h" +#include #include using namespace llvm; @@ -507,7 +508,7 @@ DebugLoc DL = MI.getDebugLoc(); SmallVector Regs; int LRIdx = 0; - Optional FpOffset; + std::optional FpOffset; for (auto &MO : MI.operands()) { if (MO.isReg()) { if (MO.getReg() == AArch64::LR) diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -361,16 +361,20 @@ void mirFileLoaded(MachineFunction &MF) const override; + bool hasSVEorSME() const { return hasSVE() || hasSME(); } + // Return the known range for the bit length of SVE data registers. A value // of 0 means nothing is known about that particular limit beyong what's // implied by the architecture. unsigned getMaxSVEVectorSizeInBits() const { - assert(HasSVE && "Tried to get SVE vector length without SVE support!"); + assert(hasSVEorSME() && + "Tried to get SVE vector length without SVE support!"); return MaxSVEVectorSizeInBits; } unsigned getMinSVEVectorSizeInBits() const { - assert(HasSVE && "Tried to get SVE vector length without SVE support!"); + assert(hasSVEorSME() && + "Tried to get SVE vector length without SVE support!"); return MinSVEVectorSizeInBits; } diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -459,8 +459,8 @@ bool AArch64Subtarget::forceStreamingCompatibleSVE() const { if (ForceStreamingCompatibleSVE) { - assert((hasSVE() || hasSME()) && "Expected SVE to be available"); - return hasSVE() || hasSME(); + assert(hasSVEorSME() && "Expected SVE to be available"); + return hasSVEorSME(); } return false; } diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -692,6 +692,7 @@ let Requires = [{ {AArch64::FeatureSpecRestrict} }]; } def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>; +def : ROSysReg<"ID_DFR1_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b101>; def : ROSysReg<"ID_AFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b011>; def : ROSysReg<"ID_MMFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b100>; def : ROSysReg<"ID_MMFR1_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b101>; @@ -866,7 +867,7 @@ // Read-write regs //===---------------------- -// Op0 Op1 CRn CRm Op2 +// Op0 Op1 CRn CRm Op2 def : RWSysReg<"OSDTRRX_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b010>; def : RWSysReg<"OSDTRTX_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b010>; def : RWSysReg<"TEECR32_EL1", 0b10, 0b010, 0b0000, 0b0000, 0b000>; @@ -875,70 +876,15 @@ def : RWSysReg<"DBGDTR_EL0", 0b10, 0b011, 0b0000, 0b0100, 0b000>; def : RWSysReg<"OSECCR_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b010>; def : RWSysReg<"DBGVCR32_EL2", 0b10, 0b100, 0b0000, 0b0111, 0b000>; -def : RWSysReg<"DBGBVR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b100>; -def : RWSysReg<"DBGBVR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b100>; -def : RWSysReg<"DBGBVR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b100>; -def : RWSysReg<"DBGBVR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b100>; -def : RWSysReg<"DBGBVR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b100>; -def : RWSysReg<"DBGBVR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b100>; -def : RWSysReg<"DBGBVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b100>; -def : RWSysReg<"DBGBVR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b100>; -def : RWSysReg<"DBGBVR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b100>; -def : RWSysReg<"DBGBVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b100>; -def : RWSysReg<"DBGBVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b100>; -def : RWSysReg<"DBGBVR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b100>; -def : RWSysReg<"DBGBVR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b100>; -def : RWSysReg<"DBGBVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b100>; -def : RWSysReg<"DBGBVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b100>; -def : RWSysReg<"DBGBVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b100>; -def : RWSysReg<"DBGBCR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b101>; -def : RWSysReg<"DBGBCR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b101>; -def : RWSysReg<"DBGBCR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b101>; -def : RWSysReg<"DBGBCR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b101>; -def : RWSysReg<"DBGBCR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b101>; -def : RWSysReg<"DBGBCR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b101>; -def : RWSysReg<"DBGBCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b101>; -def : RWSysReg<"DBGBCR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b101>; -def : RWSysReg<"DBGBCR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b101>; -def : RWSysReg<"DBGBCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b101>; -def : RWSysReg<"DBGBCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b101>; -def : RWSysReg<"DBGBCR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b101>; -def : RWSysReg<"DBGBCR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b101>; -def : RWSysReg<"DBGBCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b101>; -def : RWSysReg<"DBGBCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b101>; -def : RWSysReg<"DBGBCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b101>; -def : RWSysReg<"DBGWVR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b110>; -def : RWSysReg<"DBGWVR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b110>; -def : RWSysReg<"DBGWVR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b110>; -def : RWSysReg<"DBGWVR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b110>; -def : RWSysReg<"DBGWVR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b110>; -def : RWSysReg<"DBGWVR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b110>; -def : RWSysReg<"DBGWVR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b110>; -def : RWSysReg<"DBGWVR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b110>; -def : RWSysReg<"DBGWVR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b110>; -def : RWSysReg<"DBGWVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b110>; -def : RWSysReg<"DBGWVR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b110>; -def : RWSysReg<"DBGWVR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b110>; -def : RWSysReg<"DBGWVR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b110>; -def : RWSysReg<"DBGWVR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b110>; -def : RWSysReg<"DBGWVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b110>; -def : RWSysReg<"DBGWVR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b110>; -def : RWSysReg<"DBGWCR0_EL1", 0b10, 0b000, 0b0000, 0b0000, 0b111>; -def : RWSysReg<"DBGWCR1_EL1", 0b10, 0b000, 0b0000, 0b0001, 0b111>; -def : RWSysReg<"DBGWCR2_EL1", 0b10, 0b000, 0b0000, 0b0010, 0b111>; -def : RWSysReg<"DBGWCR3_EL1", 0b10, 0b000, 0b0000, 0b0011, 0b111>; -def : RWSysReg<"DBGWCR4_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b111>; -def : RWSysReg<"DBGWCR5_EL1", 0b10, 0b000, 0b0000, 0b0101, 0b111>; -def : RWSysReg<"DBGWCR6_EL1", 0b10, 0b000, 0b0000, 0b0110, 0b111>; -def : RWSysReg<"DBGWCR7_EL1", 0b10, 0b000, 0b0000, 0b0111, 0b111>; -def : RWSysReg<"DBGWCR8_EL1", 0b10, 0b000, 0b0000, 0b1000, 0b111>; -def : RWSysReg<"DBGWCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b111>; -def : RWSysReg<"DBGWCR10_EL1", 0b10, 0b000, 0b0000, 0b1010, 0b111>; -def : RWSysReg<"DBGWCR11_EL1", 0b10, 0b000, 0b0000, 0b1011, 0b111>; -def : RWSysReg<"DBGWCR12_EL1", 0b10, 0b000, 0b0000, 0b1100, 0b111>; -def : RWSysReg<"DBGWCR13_EL1", 0b10, 0b000, 0b0000, 0b1101, 0b111>; -def : RWSysReg<"DBGWCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b111>; -def : RWSysReg<"DBGWCR15_EL1", 0b10, 0b000, 0b0000, 0b1111, 0b111>; +foreach n = 0-15 in { + defvar nb = !cast>(n); + // Op0 Op1 CRn CRm Op2 + def : RWSysReg<"DBGBVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b100>; + def : RWSysReg<"DBGBCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b101>; + def : RWSysReg<"DBGWVR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b110>; + def : RWSysReg<"DBGWCR"#n#"_EL1", 0b10, 0b000, 0b0000, nb, 0b111>; +} +// Op0 Op1 CRn CRm Op2 def : RWSysReg<"TEEHBR32_EL1", 0b10, 0b010, 0b0001, 0b0000, 0b000>; def : RWSysReg<"OSDLR_EL1", 0b10, 0b000, 0b0001, 0b0011, 0b100>; def : RWSysReg<"DBGPRCR_EL1", 0b10, 0b000, 0b0001, 0b0100, 0b100>; @@ -1687,6 +1633,8 @@ // v8.6a Activity Monitors Virtualization Support let Requires = [{ {AArch64::FeatureAMVS} }] in { +// Name Op0 Op1 CRn CRm Op2 +def : ROSysReg<"AMCG1IDR_EL0", 0b11, 0b011, 0b1101, 0b0010, 0b110>; foreach n = 0-15 in { foreach x = 0-1 in { def : RWSysReg<"AMEVCNTVOFF"#x#n#"_EL2", @@ -1706,6 +1654,14 @@ def : RWSysReg<"HFGITR_EL2", 0b11, 0b100, 0b0001, 0b0001, 0b110>; def : RWSysReg<"HDFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b100>; def : RWSysReg<"HDFGWTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b101>; +def : RWSysReg<"HAFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b110>; + +// v8.9a/v9.4a additions to Fine Grained Traps (FEAT_FGT2) +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"HDFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b000>; +def : RWSysReg<"HDFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b001>; +def : RWSysReg<"HFGRTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b010>; +def : RWSysReg<"HFGWTR2_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b011>; } // v8.6a Enhanced Counter Virtualization @@ -1770,3 +1726,80 @@ let Requires = [{ {AArch64::FeatureMPAM, AArch64::FeatureSME} }] in { def : RWSysReg<"MPAMSM_EL1", 0b11, 0b000, 0b1010, 0b0101, 0b011>; } // HasMPAM, HasSME + +// v8.9a/9.4a new Debug feature (FEAT_DEBUGv8p9) +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"MDSELR_EL1", 0b10, 0b000, 0b0000, 0b0100, 0b010>; + +// v8.9a/9.4a new Performance Monitors Extension (FEAT_PMUv3p9) +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"PMUACR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b100>; + +// v8.9a/9.4a PMU Snapshot Extension (FEAT_PMUv3_SS) +// Op0 Op1 CRn CRm Op2 +def : ROSysReg<"PMCCNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1011, 0b111>; +def : ROSysReg<"PMICNTSVR_EL1", 0b10, 0b000, 0b1110, 0b1100, 0b000>; +def : RWSysReg<"PMSSCR_EL1", 0b11, 0b000, 0b1001, 0b1101, 0b011>; +foreach n = 0-30 in { + defvar nb = !cast>(n); + def : ROSysReg<"PMEVCNTSVR"#n#"_EL1", 0b10, 0b000, 0b1110, {0b10,nb{4-3}}, nb{2-0}>; +} + +// v8.9a/v9.4a PMUv3 Fixed-function instruction counter (FEAT_PMUv3_ICNTR) +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"PMICNTR_EL0", 0b11, 0b011, 0b1001, 0b0100, 0b000>; +def : RWSysReg<"PMICFILTR_EL0", 0b11, 0b011, 0b1001, 0b0110, 0b000>; + +// v8.9a/v9.4a PMUv3 Performance Monitors Zero with Mask (FEAT_PMUv3p9/FEAT_PMUv3_ICNTR) +// Op0 Op1 CRn CRm Op2 +def : WOSysReg<"PMZR_EL0", 0b11, 0b011, 0b1001, 0b1101, 0b100>; + +// v8.9a/9.4a Synchronous-Exception-Based Event Profiling extension (FEAT_SEBEP) +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"PMECR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b101>; +def : RWSysReg<"PMIAR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b111>; + +// v8.9a/9.4a System Performance Monitors Extension (FEAT_SPMU) +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"SPMACCESSR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b011>; +def : RWSysReg<"SPMACCESSR_EL12", 0b10, 0b101, 0b1001, 0b1101, 0b011>; +def : RWSysReg<"SPMACCESSR_EL2", 0b10, 0b100, 0b1001, 0b1101, 0b011>; +def : RWSysReg<"SPMACCESSR_EL3", 0b10, 0b110, 0b1001, 0b1101, 0b011>; +def : RWSysReg<"SPMCNTENCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b010>; +def : RWSysReg<"SPMCNTENSET_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b001>; +def : RWSysReg<"SPMCR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b000>; +def : ROSysReg<"SPMDEVAFF_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b110>; +def : ROSysReg<"SPMDEVARCH_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b101>; +foreach n = 0-15 in { + defvar nb = !cast>(n); + // Op0 Op1 CRn CRm Op2 + def : RWSysReg<"SPMEVCNTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b000,nb{3}}, nb{2-0}>; + def : RWSysReg<"SPMEVFILT2R"#n#"_EL0", 0b10, 0b011, 0b1110, {0b011,nb{3}}, nb{2-0}>; + def : RWSysReg<"SPMEVFILTR"#n#"_EL0", 0b10, 0b011, 0b1110, {0b010,nb{3}}, nb{2-0}>; + def : RWSysReg<"SPMEVTYPER"#n#"_EL0", 0b10, 0b011, 0b1110, {0b001,nb{3}}, nb{2-0}>; +} +// Op0 Op1 CRn CRm Op2 +def : ROSysReg<"SPMIIDR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b100>; +def : RWSysReg<"SPMINTENCLR_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b010>; +def : RWSysReg<"SPMINTENSET_EL1", 0b10, 0b000, 0b1001, 0b1110, 0b001>; +def : RWSysReg<"SPMOVSCLR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b011>; +def : RWSysReg<"SPMOVSSET_EL0", 0b10, 0b011, 0b1001, 0b1110, 0b011>; +def : RWSysReg<"SPMSELR_EL0", 0b10, 0b011, 0b1001, 0b1100, 0b101>; +def : ROSysReg<"SPMCGCR0_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b000>; +def : ROSysReg<"SPMCGCR1_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b001>; +def : ROSysReg<"SPMCFGR_EL1", 0b10, 0b000, 0b1001, 0b1101, 0b111>; +def : RWSysReg<"SPMROOTCR_EL3", 0b10, 0b110, 0b1001, 0b1110, 0b111>; +def : RWSysReg<"SPMSCR_EL1", 0b10, 0b111, 0b1001, 0b1110, 0b111>; + +// v8.9a/9.4a Instrumentation Extension (FEAT_ITE) +// Op0 Op1 CRn CRm Op2 +let Requires = [{ {AArch64::FeatureITE} }] in { +def : RWSysReg<"TRCITEEDCR", 0b10, 0b001, 0b0000, 0b0010, 0b001>; +def : RWSysReg<"TRCITECR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b011>; +def : RWSysReg<"TRCITECR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b011>; +def : RWSysReg<"TRCITECR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b011>; +} + +// v8.9a/9.4a SPE Data Source Filtering (FEAT_SPE_FDS) +// Op0 Op1 CRn CRm Op2 +def : RWSysReg<"PMSDSFR_EL1", 0b11, 0b000, 0b1001, 0b1010, 0b100>; diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -2171,6 +2171,18 @@ Cost *= 4; return Cost; } else { + // If one of the operands is a uniform constant then the cost for each + // element is Cost for insertion, extraction and division. + // Insertion cost = 2, Extraction Cost = 2, Division = cost for the + // operation with scalar type + if ((Op1Info.isConstant() && Op1Info.isUniform()) || + (Op2Info.isConstant() && Op2Info.isUniform())) { + if (auto *VTy = dyn_cast(Ty)) { + InstructionCost DivCost = BaseT::getArithmeticInstrCost( + Opcode, Ty->getScalarType(), CostKind, Op1Info, Op2Info); + return (4 + DivCost) * VTy->getNumElements(); + } + } // On AArch64, without SVE, vector divisions are expanded // into scalar divisions of each pair of elements. Cost += getArithmeticInstrCost(Instruction::ExtractElement, Ty, diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -55,6 +55,7 @@ #include #include #include +#include #include #include #include @@ -938,7 +939,7 @@ /// a shifted immediate by value 'Shift' or '0', or if it is an unshifted /// immediate that can be shifted by 'Shift'. template - Optional > getShiftedVal() const { + std::optional> getShiftedVal() const { if (isShiftedImm() && Width == getShiftedImmShift()) if (auto *CE = dyn_cast(getShiftedImmVal())) return std::make_pair(CE->getValue(), Width); @@ -3465,7 +3466,7 @@ StringRef Tail = Name.drop_front(DotPosition); StringRef RowOrColumn = Head.take_back(); - MatrixKind Kind = StringSwitch(RowOrColumn) + MatrixKind Kind = StringSwitch(RowOrColumn.lower()) .Case("h", MatrixKind::Row) .Case("v", MatrixKind::Col) .Default(MatrixKind::Tile); @@ -7547,6 +7548,15 @@ case MCK__HASH_8: ExpectedVal = 8; break; + case MCK__HASH__MINUS_4: + ExpectedVal = -4; + break; + case MCK__HASH__MINUS_8: + ExpectedVal = -8; + break; + case MCK__HASH__MINUS_16: + ExpectedVal = -16; + break; case MCK_MPR: // If the Kind is a token for the MPR register class which has the "za" // register (SME accumulator array), check if the asm is a literal "za" diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -47,6 +47,7 @@ #include "llvm/Pass.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" +#include #define DEBUG_TYPE "aarch64-isel" @@ -1420,7 +1421,7 @@ } // Attempt to find a suitable operation with a constant on one side. - Optional C; + std::optional C; Register TestReg; switch (Opc) { default: diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp --- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp @@ -44,6 +44,7 @@ #include "llvm/InitializePasses.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include #define DEBUG_TYPE "aarch64-postlegalizer-lowering" @@ -111,8 +112,8 @@ /// Check if a G_EXT instruction can handle a shuffle mask \p M when the vector /// sources of the shuffle are different. -static Optional> getExtMask(ArrayRef M, - unsigned NumElts) { +static std::optional> getExtMask(ArrayRef M, + unsigned NumElts) { // Look for the first non-undef element. auto FirstRealElt = find_if(M, [](int Elt) { return Elt >= 0; }); if (FirstRealElt == M.end()) @@ -193,8 +194,8 @@ /// G_INSERT_VECTOR_ELT destination should be the LHS of the G_SHUFFLE_VECTOR. /// /// Second element is the destination lane for the G_INSERT_VECTOR_ELT. -static Optional> isINSMask(ArrayRef M, - int NumInputElements) { +static std::optional> isINSMask(ArrayRef M, + int NumInputElements) { if (M.size() != static_cast(NumInputElements)) return None; int NumLHSMatch = 0, NumRHSMatch = 0; @@ -557,9 +558,9 @@ /// be used to optimize the instruction. /// /// \note This assumes that the comparison has been legalized. -Optional> +std::optional> tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P, - const MachineRegisterInfo &MRI) { + const MachineRegisterInfo &MRI) { const auto &Ty = MRI.getType(RHS); if (Ty.isVector()) return None; diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp @@ -79,7 +79,7 @@ OutStreamer.switchSection(Nt); // Emit the note header. - OutStreamer.emitValueToAlignment(Align(8).value()); + OutStreamer.emitValueToAlignment(Align(8)); OutStreamer.emitIntValue(4, 4); // data size for "GNU\0" OutStreamer.emitIntValue(4 * 4, 4); // Elf_Prop size OutStreamer.emitIntValue(ELF::NT_GNU_PROPERTY_TYPE_0, 4); diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -8297,21 +8297,6 @@ // SVE BFloat16 Group //===----------------------------------------------------------------------===// -class sve_bfloat_dot_base opc, string asm, string ops, dag iops> -: I<(outs ZPR32:$Zda), iops, asm, ops, "", []>, Sched<[]> { - bits<5> Zda; - bits<5> Zn; - let Inst{31-21} = 0b01100100011; - let Inst{15-14} = opc; - let Inst{13-10} = 0b0000; - let Inst{9-5} = Zn; - let Inst{4-0} = Zda; - - let Constraints = "$Zda = $_Zda"; - let DestructiveInstType = DestructiveOther; - let ElementSize = ElementSizeH; -} - class sve_float_dot : I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm), asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> { @@ -8396,16 +8381,26 @@ } class sve_bfloat_matmul_longvecl_idx -: sve_bfloat_dot_base<0b01, asm, "\t$Zda, $Zn, $Zm$iop", - (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm, VectorIndexH:$iop)> { - bits<3> iop; +: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm, VectorIndexH:$iop), + asm, "\t$Zda, $Zn, $Zm$iop", "", []>, Sched<[]> { + bits<5> Zda; + bits<5> Zn; bits<3> Zm; - let Inst{23} = 0b1; + bits<3> iop; + let Inst{31-21} = 0b01100100111; let Inst{20-19} = iop{2-1}; let Inst{18-16} = Zm; + let Inst{15-14} = 0b01; let Inst{13} = sub; + let Inst{12} = 0b0; let Inst{11} = iop{0}; let Inst{10} = BT; + let Inst{9-5} = Zn; + let Inst{4-0} = Zda; + + let Constraints = "$Zda = $_Zda"; + let DestructiveInstType = DestructiveOther; + let ElementSize = ElementSizeH; } multiclass sve_bfloat_matmul_longvecl_idx { diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -1337,6 +1337,10 @@ // Some of the R600 registers have the same name, so this crashes. // For example T0_XYZW and T0_XY both have the asm name T0. let ShouldEmitMatchRegisterName = 0; + + // Call the custom operand parser for all operands. + let OperandParserMethod = "parseCustomOperand"; + let CallCustomParserForAllOperands = true; } def AMDGPUAsmWriter : AsmWriter { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp @@ -252,9 +252,8 @@ // CP microcode requires the kernel descriptor to be allocated on 64 byte // alignment. - Streamer.emitValueToAlignment(64, 0, 1, 0); - if (ReadOnlySection.getAlignment() < 64) - ReadOnlySection.setAlignment(Align(64)); + Streamer.emitValueToAlignment(Align(64), 0, 1, 0); + ReadOnlySection.ensureMinAlignment(Align(64)); const GCNSubtarget &STM = MF->getSubtarget(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td --- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td @@ -218,6 +218,7 @@ def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; +def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; def : GINodeEquiv; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -514,6 +514,7 @@ BUFFER_LOAD_BYTE, BUFFER_LOAD_SHORT, BUFFER_LOAD_FORMAT, + BUFFER_LOAD_FORMAT_TFE, BUFFER_LOAD_FORMAT_D16, SBUFFER_LOAD, BUFFER_STORE, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -1240,6 +1240,24 @@ if (G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS || G->getAddressSpace() == AMDGPUAS::REGION_ADDRESS) { + + if (G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) { + // special case handling for kernel block variable + // it's allocated in the kernel at a predictable address + // so that uses of it from functions and globals can be + // resolved here + // This only works if the current function is called from the kernel + // with the corresponding global + if (const GlobalVariable *GV2 = dyn_cast(GV)) { + if (MFI->isKnownAddressLDSGlobal(*GV2)) { + unsigned offset = MFI->calculateKnownAddressOfLDSGlobal(*GV2); + + return DAG.getConstant(offset + G->getOffset(), SDLoc(Op), + Op.getValueType()); + } + } + } + if (!MFI->isModuleEntryFunction() && !GV->getName().equals("llvm.amdgcn.module.lds")) { SDLoc DL(Op); @@ -4429,6 +4447,7 @@ NODE_NAME_CASE(BUFFER_LOAD_BYTE) NODE_NAME_CASE(BUFFER_LOAD_SHORT) NODE_NAME_CASE(BUFFER_LOAD_FORMAT) + NODE_NAME_CASE(BUFFER_LOAD_FORMAT_TFE) NODE_NAME_CASE(BUFFER_LOAD_FORMAT_D16) NODE_NAME_CASE(SBUFFER_LOAD) NODE_NAME_CASE(BUFFER_STORE) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -26,6 +26,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/IR/DiagnosticInfo.h" #include "llvm/IR/IntrinsicsAMDGPU.h" +#include #define DEBUG_TYPE "amdgpu-isel" @@ -4234,7 +4235,7 @@ // Try to fold a frame index directly into the MUBUF vaddr field, and any // offsets. - Optional FI; + std::optional FI; Register VAddr = Root.getReg(); if (const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg())) { Register PtrBase; diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -4466,6 +4466,27 @@ return true; } +static void buildBufferLoad(unsigned Opc, Register LoadDstReg, Register RSrc, + Register VIndex, Register VOffset, Register SOffset, + unsigned ImmOffset, unsigned Format, + unsigned AuxiliaryData, MachineMemOperand *MMO, + bool IsTyped, bool HasVIndex, MachineIRBuilder &B) { + auto MIB = B.buildInstr(Opc) + .addDef(LoadDstReg) // vdata + .addUse(RSrc) // rsrc + .addUse(VIndex) // vindex + .addUse(VOffset) // voffset + .addUse(SOffset) // soffset + .addImm(ImmOffset); // offset(imm) + + if (IsTyped) + MIB.addImm(Format); + + MIB.addImm(AuxiliaryData) // cachepolicy, swizzled buffer(imm) + .addImm(HasVIndex ? -1 : 0) // idxen(imm) + .addMemOperand(MMO); +} + bool AMDGPULegalizerInfo::legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B, @@ -4477,18 +4498,27 @@ const LLT S32 = LLT::scalar(32); Register Dst = MI.getOperand(0).getReg(); - Register RSrc = MI.getOperand(2).getReg(); + + Register StatusDst; + int OpOffset = 0; + assert(MI.getNumExplicitDefs() == 1 || MI.getNumExplicitDefs() == 2); + bool IsTFE = MI.getNumExplicitDefs() == 2; + if (IsTFE) { + StatusDst = MI.getOperand(1).getReg(); + ++OpOffset; + } + + Register RSrc = MI.getOperand(2 + OpOffset).getReg(); // The typed intrinsics add an immediate after the registers. const unsigned NumVIndexOps = IsTyped ? 8 : 7; // The struct intrinsic variants add one additional operand over raw. - const bool HasVIndex = MI.getNumOperands() == NumVIndexOps; + const bool HasVIndex = MI.getNumOperands() == NumVIndexOps + OpOffset; Register VIndex; - int OpOffset = 0; if (HasVIndex) { - VIndex = MI.getOperand(3).getReg(); - OpOffset = 1; + VIndex = MI.getOperand(3 + OpOffset).getReg(); + ++OpOffset; } else { VIndex = B.buildConstant(S32, 0).getReg(0); } @@ -4515,13 +4545,21 @@ unsigned Opc; + // TODO: Support TFE for typed and narrow loads. if (IsTyped) { + assert(!IsTFE); Opc = IsD16 ? AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT_D16 : AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT; } else if (IsFormat) { - Opc = IsD16 ? AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_D16 : - AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT; + if (IsD16) { + assert(!IsTFE); + Opc = AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_D16; + } else { + Opc = IsTFE ? AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_TFE + : AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT; + } } else { + assert(!IsTFE); switch (MemTy.getSizeInBits()) { case 8: Opc = AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE; @@ -4535,49 +4573,46 @@ } } - Register LoadDstReg; - - bool IsExtLoad = - (!IsD16 && MemTy.getSizeInBits() < 32) || (IsD16 && !Ty.isVector()); - LLT UnpackedTy = Ty.changeElementSize(32); - - if (IsExtLoad) - LoadDstReg = B.getMRI()->createGenericVirtualRegister(S32); - else if (Unpacked && IsD16 && Ty.isVector()) - LoadDstReg = B.getMRI()->createGenericVirtualRegister(UnpackedTy); - else - LoadDstReg = Dst; - - auto MIB = B.buildInstr(Opc) - .addDef(LoadDstReg) // vdata - .addUse(RSrc) // rsrc - .addUse(VIndex) // vindex - .addUse(VOffset) // voffset - .addUse(SOffset) // soffset - .addImm(ImmOffset); // offset(imm) - - if (IsTyped) - MIB.addImm(Format); - - MIB.addImm(AuxiliaryData) // cachepolicy, swizzled buffer(imm) - .addImm(HasVIndex ? -1 : 0) // idxen(imm) - .addMemOperand(MMO); - - if (LoadDstReg != Dst) { - B.setInsertPt(B.getMBB(), ++B.getInsertPt()); - - // Widen result for extending loads was widened. - if (IsExtLoad) - B.buildTrunc(Dst, LoadDstReg); - else { - // Repack to original 16-bit vector result - // FIXME: G_TRUNC should work, but legalization currently fails - auto Unmerge = B.buildUnmerge(S32, LoadDstReg); - SmallVector Repack; - for (unsigned I = 0, N = Unmerge->getNumOperands() - 1; I != N; ++I) - Repack.push_back(B.buildTrunc(EltTy, Unmerge.getReg(I)).getReg(0)); - B.buildMerge(Dst, Repack); + if (IsTFE) { + unsigned NumValueDWords = divideCeil(Ty.getSizeInBits(), 32); + unsigned NumLoadDWords = NumValueDWords + 1; + LLT LoadTy = LLT::fixed_vector(NumLoadDWords, S32); + Register LoadDstReg = B.getMRI()->createGenericVirtualRegister(LoadTy); + buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, + Format, AuxiliaryData, MMO, IsTyped, HasVIndex, B); + if (NumValueDWords == 1) { + B.buildUnmerge({Dst, StatusDst}, LoadDstReg); + } else { + SmallVector LoadElts; + for (unsigned I = 0; I != NumValueDWords; ++I) + LoadElts.push_back(B.getMRI()->createGenericVirtualRegister(S32)); + LoadElts.push_back(StatusDst); + B.buildUnmerge(LoadElts, LoadDstReg); + LoadElts.truncate(NumValueDWords); + B.buildMerge(Dst, LoadElts); } + } else if ((!IsD16 && MemTy.getSizeInBits() < 32) || + (IsD16 && !Ty.isVector())) { + Register LoadDstReg = B.getMRI()->createGenericVirtualRegister(S32); + buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, + Format, AuxiliaryData, MMO, IsTyped, HasVIndex, B); + B.setInsertPt(B.getMBB(), ++B.getInsertPt()); + B.buildTrunc(Dst, LoadDstReg); + } else if (Unpacked && IsD16 && Ty.isVector()) { + LLT UnpackedTy = Ty.changeElementSize(32); + Register LoadDstReg = B.getMRI()->createGenericVirtualRegister(UnpackedTy); + buildBufferLoad(Opc, LoadDstReg, RSrc, VIndex, VOffset, SOffset, ImmOffset, + Format, AuxiliaryData, MMO, IsTyped, HasVIndex, B); + B.setInsertPt(B.getMBB(), ++B.getInsertPt()); + // FIXME: G_TRUNC should work, but legalization currently fails + auto Unmerge = B.buildUnmerge(S32, LoadDstReg); + SmallVector Repack; + for (unsigned I = 0, N = Unmerge->getNumOperands() - 1; I != N; ++I) + Repack.push_back(B.buildTrunc(EltTy, Unmerge.getReg(I)).getReg(0)); + B.buildMerge(Dst, Repack); + } else { + buildBufferLoad(Opc, Dst, RSrc, VIndex, VOffset, SOffset, ImmOffset, Format, + AuxiliaryData, MMO, IsTyped, HasVIndex, B); } MI.eraseFromParent(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp @@ -6,23 +6,114 @@ // //===----------------------------------------------------------------------===// // -// This pass eliminates LDS uses from non-kernel functions. +// This pass eliminates local data store, LDS, uses from non-kernel functions. +// LDS is contiguous memory allocated per kernel execution. // -// The strategy is to create a new struct with a field for each LDS variable -// and allocate that struct at the same address for every kernel. Uses of the -// original LDS variables are then replaced with compile time offsets from that -// known address. AMDGPUMachineFunction allocates the LDS global. +// Background. // -// Local variables with constant annotation or non-undef initializer are passed +// The programming model is global variables, or equivalently function local +// static variables, accessible from kernels or other functions. For uses from +// kernels this is straightforward - assign an integer to the kernel for the +// memory required by all the variables combined, allocate them within that. +// For uses from functions there are performance tradeoffs to choose between. +// +// This model means the GPU runtime can specify the amount of memory allocated. +// If this is more than the kernel assumed, the excess can be made available +// using a language specific feature, which IR represents as a variable with +// no initializer. This feature is not yet implemented for non-kernel functions. +// This lowering could be extended to handle that use case, but would probably +// require closer integration with promoteAllocaToLDS. +// +// Consequences of this GPU feature: +// - memory is limited and exceeding it halts compilation +// - a global accessed by one kernel exists independent of other kernels +// - a global exists independent of simultaneous execution of the same kernel +// - the address of the global may be different from different kernels as they +// do not alias, which permits only allocating variables they use +// - if the address is allowed to differ, functions need help to find it +// +// Uses from kernels are implemented here by grouping them in a per-kernel +// struct instance. This duplicates the variables, accurately modelling their +// aliasing properties relative to a single global representation. It also +// permits control over alignment via padding. +// +// Uses from functions are more complicated and the primary purpose of this +// IR pass. Several different lowering are chosen between to meet requirements +// to avoid allocating any LDS where it is not necessary, as that impacts +// occupancy and may fail the compilation, while not imposing overhead on a +// feature whose primary advantage over global memory is performance. The basic +// design goal is to avoid one kernel imposing overhead on another. +// +// Implementation. +// +// LDS variables with constant annotation or non-undef initializer are passed // through unchanged for simplification or error diagnostics in later passes. +// Non-undef initializers are not yet implemented for LDS. +// +// LDS variables that are always allocated at the same address can be found +// by lookup at that address. Otherwise runtime information/cost is required. // -// To reduce the memory overhead variables that are only used by kernels are -// excluded from this transform. The analysis to determine whether a variable -// is only used by a kernel is cheap and conservative so this may allocate -// a variable in every kernel when it was not strictly necessary to do so. +// The simplest strategy possible is to group all LDS variables in a single +// struct and allocate that struct in every kernel such that the original +// variables are always at the same address. LDS is however a limited resource +// so this strategy is unusable in practice. It is not implemented here. // -// A possible future refinement is to specialise the structure per-kernel, so -// that fields can be elided based on more expensive analysis. +// Strategy | Precise allocation | Zero runtime cost | General purpose | +// --------+--------------------+-------------------+-----------------+ +// Module | No | Yes | Yes | +// Table | Yes | No | Yes | +// Kernel | Yes | Yes | No | +// Hybrid | Yes | Partial | Yes | +// +// Module spends LDS memory to save cycles. Table spends cycles and global +// memory to save LDS. Kernel is as fast as kernel allocation but only works +// for variables that are known reachable from a single kernel. Hybrid picks +// between all three. When forced to choose between LDS and cycles it minimises +// LDS use. + +// The "module" lowering implemented here finds LDS variables which are used by +// non-kernel functions and creates a new struct with a field for each of those +// LDS variables. Variables that are only used from kernels are excluded. +// Kernels that do not use this struct are annoteated with the attribute +// amdgpu-elide-module-lds which allows the back end to elide the allocation. +// +// The "table" lowering implemented here has three components. +// First kernels are assigned a unique integer identifier which is available in +// functions it calls through the intrinsic amdgcn_lds_kernel_id. The integer +// is passed through a specific SGPR, thus works with indirect calls. +// Second, each kernel allocates LDS variables independent of other kernels and +// writes the addresses it chose for each variable into an array in consistent +// order. If the kernel does not allocate a given variable, it writes undef to +// the corresponding array location. These arrays are written to a constant +// table in the order matching the kernel unique integer identifier. +// Third, uses from non-kernel functions are replaced with a table lookup using +// the intrinsic function to find the address of the variable. +// +// "Kernel" lowering is only applicable for variables that are unambiguously +// reachable from exactly one kernel. For those cases, accesses to the variable +// can be lowered to ConstantExpr address of a struct instance specific to that +// one kernel. This is zero cost in space and in compute. It will raise a fatal +// error on any variable that might be reachable from multiple kernels and is +// thus most easily used as part of the hybrid lowering strategy. +// +// Hybrid lowering is a mixture of the above. It uses the zero cost kernel +// lowering where it can. It lowers the variable accessed by the greatest +// number of kernels using the module strategy as that is free for the first +// variable. Any futher variables that can be lowered with the module strategy +// without incurring LDS memory overhead are. The remaining ones are lowered +// via table. +// +// Consequences +// - No heuristics or user controlled magic numbers, hybrid is the right choice +// - Kernels that don't use functions (or have had them all inlined) are not +// affected by any lowering for kernels that do. +// - Kernels that don't make indirect function calls are not affected by those +// that do. +// - Variables which are used by lots of kernels, e.g. those injected by a +// language runtime in most kernels, are expected to have no overhead +// - Implementations that instantiate templates per-kernel where those templates +// use LDS are expected to hit the "Kernel" lowering strategy +// - The runtime properties impose a cost in compiler implementation complexity // //===----------------------------------------------------------------------===// @@ -31,34 +122,68 @@ #include "Utils/AMDGPUMemoryUtils.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/DenseSet.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SetOperations.h" #include "llvm/ADT/SetVector.h" +#include "llvm/ADT/StringSwitch.h" #include "llvm/Analysis/CallGraph.h" #include "llvm/IR/Constants.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/IRBuilder.h" #include "llvm/IR/InlineAsm.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/IntrinsicsAMDGPU.h" #include "llvm/IR/MDBuilder.h" #include "llvm/InitializePasses.h" #include "llvm/Pass.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/OptimizedStructLayout.h" +#include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/ModuleUtils.h" + #include #include +#include + #define DEBUG_TYPE "amdgpu-lower-module-lds" using namespace llvm; -static cl::opt SuperAlignLDSGlobals( +namespace { + +cl::opt SuperAlignLDSGlobals( "amdgpu-super-align-lds-globals", cl::desc("Increase alignment of LDS if it is not on align boundary"), cl::init(true), cl::Hidden); -namespace { +enum class LoweringKind { module, table, kernel, hybrid }; +cl::opt LoweringKindLoc( + "amdgpu-lower-module-lds-strategy", + cl::desc("Specify lowering strategy for function LDS access:"), cl::Hidden, + cl::init(LoweringKind::module), + cl::values( + clEnumValN(LoweringKind::table, "table", "Lower via table lookup"), + clEnumValN(LoweringKind::module, "module", "Lower via module struct"), + clEnumValN( + LoweringKind::kernel, "kernel", + "Lower variables reachable from one kernel, otherwise abort"), + clEnumValN(LoweringKind::hybrid, "hybrid", + "Lower via mixture of above strategies"))); + +bool isKernelLDS(const Function *F) { + // Some weirdness here. AMDGPU::isKernelCC does not call into + // AMDGPU::isKernel with the calling conv, it instead calls into + // isModuleEntryFunction which returns true for more calling conventions + // than AMDGPU::isKernel does. There's a FIXME on AMDGPU::isKernel. + // There's also a test that checks that the LDS lowering does not hit on + // a graphics shader, denoted amdgpu_ps, so stay with the limited case. + // Putting LDS in the name of the function to draw attention to this. + return AMDGPU::isKernel(F->getCallingConv()); +} + class AMDGPULowerModuleLDS : public ModulePass { static void removeFromUsedList(Module &M, StringRef Name, @@ -92,15 +217,14 @@ ArrayType *ATy = ArrayType::get(Type::getInt8PtrTy(M.getContext()), Init.size()); GV = - new llvm::GlobalVariable(M, ATy, false, GlobalValue::AppendingLinkage, + new GlobalVariable(M, ATy, false, GlobalValue::AppendingLinkage, ConstantArray::get(ATy, Init), Name); GV->setSection("llvm.metadata"); } } - static void - removeFromUsedLists(Module &M, - const std::vector &LocalVars) { + static void removeFromUsedLists(Module &M, + const DenseSet &LocalVars) { // The verifier rejects used lists containing an inttoptr of a constant // so remove the variables from these lists before replaceAllUsesWith @@ -225,6 +349,350 @@ initializeAMDGPULowerModuleLDSPass(*PassRegistry::getPassRegistry()); } + using FunctionVariableMap = DenseMap>; + + using VariableFunctionMap = DenseMap>; + + static void getUsesOfLDSByFunction(CallGraph const &CG, Module &M, + FunctionVariableMap &kernels, + FunctionVariableMap &functions) { + + // Get uses from the current function, excluding uses by called functions + // Two output variables to avoid walking the globals list twice + for (auto &GV : M.globals()) { + if (!AMDGPU::isLDSVariableToLower(GV)) { + continue; + } + + SmallVector Stack(GV.users()); + for (User *V : GV.users()) { + if (auto *I = dyn_cast(V)) { + Function *F = I->getFunction(); + if (isKernelLDS(F)) { + kernels[F].insert(&GV); + } else { + functions[F].insert(&GV); + } + } + } + } + } + + struct LDSUsesInfoTy { + FunctionVariableMap direct_access; + FunctionVariableMap indirect_access; + }; + + static LDSUsesInfoTy getTransitiveUsesOfLDS(CallGraph const &CG, Module &M) { + + FunctionVariableMap direct_map_kernel; + FunctionVariableMap direct_map_function; + getUsesOfLDSByFunction(CG, M, direct_map_kernel, direct_map_function); + + // Collect variables that are used by functions whose address has escaped + DenseSet VariablesReachableThroughFunctionPointer; + for (Function &F : M.functions()) { + if (!isKernelLDS(&F)) + if (F.hasAddressTaken(nullptr, + /* IgnoreCallbackUses */ false, + /* IgnoreAssumeLikeCalls */ false, + /* IgnoreLLVMUsed */ true, + /* IgnoreArcAttachedCall */ false)) { + set_union(VariablesReachableThroughFunctionPointer, + direct_map_function[&F]); + } + } + + auto functionMakesUnknownCall = [&](const Function *F) -> bool { + assert(!F->isDeclaration()); + for (CallGraphNode::CallRecord R : *CG[F]) { + if (!R.second->getFunction()) { + return true; + } + } + return false; + }; + + // Work out which variables are reachable through function calls + FunctionVariableMap transitive_map_function = direct_map_function; + + // If the function makes any unknown call, assume the worst case that it can + // access all variables accessed by functions whose address escaped + for (Function &F : M.functions()) { + if (!F.isDeclaration() && functionMakesUnknownCall(&F)) { + if (!isKernelLDS(&F)) { + set_union(transitive_map_function[&F], + VariablesReachableThroughFunctionPointer); + } + } + } + + // Direct implementation of collecting all variables reachable from each + // function + for (Function &Func : M.functions()) { + if (Func.isDeclaration() || isKernelLDS(&Func)) + continue; + + DenseSet seen; // catches cycles + SmallVector wip{&Func}; + + while (!wip.empty()) { + Function *F = wip.pop_back_val(); + + // Can accelerate this by referring to transitive map for functions that + // have already been computed, with more care than this + set_union(transitive_map_function[&Func], direct_map_function[F]); + + for (CallGraphNode::CallRecord R : *CG[F]) { + Function *ith = R.second->getFunction(); + if (ith) { + if (!seen.contains(ith)) { + seen.insert(ith); + wip.push_back(ith); + } + } + } + } + } + + // direct_map_kernel lists which variables are used by the kernel + // find the variables which are used through a function call + FunctionVariableMap indirect_map_kernel; + + for (Function &Func : M.functions()) { + if (Func.isDeclaration() || !isKernelLDS(&Func)) + continue; + + for (CallGraphNode::CallRecord R : *CG[&Func]) { + Function *ith = R.second->getFunction(); + if (ith) { + set_union(indirect_map_kernel[&Func], transitive_map_function[ith]); + } else { + set_union(indirect_map_kernel[&Func], + VariablesReachableThroughFunctionPointer); + } + } + } + + return {std::move(direct_map_kernel), std::move(indirect_map_kernel)}; + } + + struct LDSVariableReplacement { + GlobalVariable *SGV = nullptr; + DenseMap LDSVarsToConstantGEP; + }; + + // remap from lds global to a constantexpr gep to where it has been moved to + // for each kernel + // an array with an element for each kernel containing where the corresponding + // variable was remapped to + + static Constant *getAddressesOfVariablesInKernel( + LLVMContext &Ctx, ArrayRef Variables, + DenseMap &LDSVarsToConstantGEP) { + // Create a ConstantArray containing the address of each Variable within the + // kernel corresponding to LDSVarsToConstantGEP, or poison if that kernel + // does not allocate it + // TODO: Drop the ptrtoint conversion + + Type *I32 = Type::getInt32Ty(Ctx); + + ArrayType *KernelOffsetsType = ArrayType::get(I32, Variables.size()); + + SmallVector Elements; + for (size_t i = 0; i < Variables.size(); i++) { + GlobalVariable *GV = Variables[i]; + if (LDSVarsToConstantGEP.count(GV) != 0) { + auto elt = ConstantExpr::getPtrToInt(LDSVarsToConstantGEP[GV], I32); + Elements.push_back(elt); + } else { + Elements.push_back(PoisonValue::get(I32)); + } + } + return ConstantArray::get(KernelOffsetsType, Elements); + } + + static GlobalVariable *buildLookupTable( + Module &M, ArrayRef Variables, + ArrayRef kernels, + DenseMap &KernelToReplacement) { + if (Variables.empty()) { + return nullptr; + } + LLVMContext &Ctx = M.getContext(); + + const size_t NumberVariables = Variables.size(); + const size_t NumberKernels = kernels.size(); + + ArrayType *KernelOffsetsType = + ArrayType::get(Type::getInt32Ty(Ctx), NumberVariables); + + ArrayType *AllKernelsOffsetsType = + ArrayType::get(KernelOffsetsType, NumberKernels); + + std::vector overallConstantExprElts(NumberKernels); + for (size_t i = 0; i < NumberKernels; i++) { + LDSVariableReplacement Replacement = KernelToReplacement[kernels[i]]; + overallConstantExprElts[i] = getAddressesOfVariablesInKernel( + Ctx, Variables, Replacement.LDSVarsToConstantGEP); + } + + Constant *init = + ConstantArray::get(AllKernelsOffsetsType, overallConstantExprElts); + + return new GlobalVariable( + M, AllKernelsOffsetsType, true, GlobalValue::InternalLinkage, init, + "llvm.amdgcn.lds.offset.table", nullptr, GlobalValue::NotThreadLocal, + AMDGPUAS::CONSTANT_ADDRESS); + } + + void replaceUsesInInstructionsWithTableLookup( + Module &M, ArrayRef ModuleScopeVariables, + GlobalVariable *LookupTable) { + + LLVMContext &Ctx = M.getContext(); + IRBuilder<> Builder(Ctx); + Type *I32 = Type::getInt32Ty(Ctx); + + // Accesses from a function use the amdgcn_lds_kernel_id intrinsic which + // lowers to a read from a live in register. Emit it once in the entry + // block to spare deduplicating it later. + + DenseMap tableKernelIndexCache; + auto getTableKernelIndex = [&](Function *F) -> Value * { + if (tableKernelIndexCache.count(F) == 0) { + LLVMContext &Ctx = M.getContext(); + FunctionType *FTy = FunctionType::get(Type::getInt32Ty(Ctx), {}); + Function *Decl = + Intrinsic::getDeclaration(&M, Intrinsic::amdgcn_lds_kernel_id, {}); + + BasicBlock::iterator it = + F->getEntryBlock().getFirstNonPHIOrDbgOrAlloca(); + Instruction &i = *it; + Builder.SetInsertPoint(&i); + + tableKernelIndexCache[F] = Builder.CreateCall(FTy, Decl, {}); + } + + return tableKernelIndexCache[F]; + }; + + for (size_t Index = 0; Index < ModuleScopeVariables.size(); Index++) { + auto *GV = ModuleScopeVariables[Index]; + + for (Use &U : make_early_inc_range(GV->uses())) { + auto *I = dyn_cast(U.getUser()); + if (!I) + continue; + + Value *tableKernelIndex = getTableKernelIndex(I->getFunction()); + + // So if the phi uses this value multiple times, what does this look + // like? + if (auto *Phi = dyn_cast(I)) { + BasicBlock *BB = Phi->getIncomingBlock(U); + Builder.SetInsertPoint(&(*(BB->getFirstInsertionPt()))); + } else { + Builder.SetInsertPoint(I); + } + + Value *GEPIdx[3] = { + ConstantInt::get(I32, 0), + tableKernelIndex, + ConstantInt::get(I32, Index), + }; + + Value *Address = Builder.CreateInBoundsGEP( + LookupTable->getValueType(), LookupTable, GEPIdx, GV->getName()); + + Value *loaded = Builder.CreateLoad(I32, Address); + + Value *replacement = + Builder.CreateIntToPtr(loaded, GV->getType(), GV->getName()); + + U.set(replacement); + } + } + } + + static DenseSet kernelsThatIndirectlyAccessAnyOfPassedVariables( + Module &M, LDSUsesInfoTy &LDSUsesInfo, + DenseSet const &VariableSet) { + + DenseSet KernelSet; + + if (VariableSet.empty()) return KernelSet; + + for (Function &Func : M.functions()) { + if (Func.isDeclaration() || !isKernelLDS(&Func)) + continue; + for (GlobalVariable *GV : LDSUsesInfo.indirect_access[&Func]) { + if (VariableSet.contains(GV)) { + KernelSet.insert(&Func); + break; + } + } + } + + return KernelSet; + } + + static GlobalVariable * + chooseBestVariableForModuleStrategy(const DataLayout &DL, + VariableFunctionMap &LDSVars) { + // Find the global variable with the most indirect uses from kernels + + struct CandidateTy { + GlobalVariable *GV = nullptr; + size_t UserCount = 0; + size_t Size = 0; + + CandidateTy() = default; + + CandidateTy(GlobalVariable *GV, uint64_t UserCount, uint64_t AllocSize) + : GV(GV), UserCount(UserCount), Size(AllocSize) {} + + bool operator<(const CandidateTy &Other) const { + // Fewer users makes module scope variable less attractive + if (UserCount < Other.UserCount) { + return true; + } + if (UserCount > Other.UserCount) { + return false; + } + + // Bigger makes module scope variable less attractive + if (Size < Other.Size) { + return false; + } + + if (Size > Other.Size) { + return true; + } + + // Arbitrary but consistent + return GV->getName() < Other.GV->getName(); + } + }; + + CandidateTy MostUsed; + + for (auto &K : LDSVars) { + GlobalVariable *GV = K.first; + if (K.second.size() <= 1) { + // A variable reachable by only one kernel is best lowered with kernel + // strategy + continue; + } + CandidateTy Candidate(GV, K.second.size(), + DL.getTypeAllocSize(GV->getValueType()).getFixedValue()); + if (MostUsed < Candidate) + MostUsed = Candidate; + } + + return MostUsed.GV; + } + bool runOnModule(Module &M) override { LLVMContext &Ctx = M.getContext(); CallGraph CG = CallGraph(M); @@ -232,96 +700,286 @@ Changed |= eliminateConstantExprUsesOfLDSFromAllInstructions(M); - // Move variables used by functions into amdgcn.module.lds - std::vector ModuleScopeVariables = - AMDGPU::findLDSVariablesToLower(M, nullptr); - if (!ModuleScopeVariables.empty()) { - std::string VarName = "llvm.amdgcn.module.lds"; - - GlobalVariable *SGV; - DenseMap LDSVarsToConstantGEP; - std::tie(SGV, LDSVarsToConstantGEP) = - createLDSVariableReplacement(M, VarName, ModuleScopeVariables); + Changed = true; // todo: narrow this down - appendToCompilerUsed( - M, {static_cast( - ConstantExpr::getPointerBitCastOrAddrSpaceCast( - cast(SGV), Type::getInt8PtrTy(Ctx)))}); + // For each kernel, what variables does it access directly or through + // callees + LDSUsesInfoTy LDSUsesInfo = getTransitiveUsesOfLDS(CG, M); - removeFromUsedLists(M, ModuleScopeVariables); - replaceLDSVariablesWithStruct(M, ModuleScopeVariables, SGV, - LDSVarsToConstantGEP, - [](Use &) { return true; }); + // For each variable accessed through callees, which kernels access it + VariableFunctionMap LDSToKernelsThatNeedToAccessItIndirectly; + for (auto &K : LDSUsesInfo.indirect_access) { + Function *F = K.first; + assert(isKernelLDS(F)); + for (GlobalVariable *GV : K.second) { + LDSToKernelsThatNeedToAccessItIndirectly[GV].insert(F); + } + } - // This ensures the variable is allocated when called functions access it. - // It also lets other passes, specifically PromoteAlloca, accurately - // calculate how much LDS will be used by the kernel after lowering. + // Partition variables into the different strategies + DenseSet ModuleScopeVariables; + DenseSet TableLookupVariables; + DenseSet KernelAccessVariables; - IRBuilder<> Builder(Ctx); - for (Function &Func : M.functions()) { - if (!Func.isDeclaration() && AMDGPU::isKernelCC(&Func)) { - const CallGraphNode *N = CG[&Func]; - const bool CalleesRequireModuleLDS = N->size() > 0; - - if (CalleesRequireModuleLDS) { - // If a function this kernel might call requires module LDS, - // annotate the kernel to let later passes know it will allocate - // this structure, even if not apparent from the IR. - markUsedByKernel(Builder, &Func, SGV); + { + GlobalVariable *HybridModuleRoot = + LoweringKindLoc != LoweringKind::hybrid + ? nullptr + : chooseBestVariableForModuleStrategy( + M.getDataLayout(), + LDSToKernelsThatNeedToAccessItIndirectly); + + DenseSet const EmptySet; + DenseSet const &HybridModuleRootKernels = + HybridModuleRoot + ? LDSToKernelsThatNeedToAccessItIndirectly[HybridModuleRoot] + : EmptySet; + + for (auto &K : LDSToKernelsThatNeedToAccessItIndirectly) { + // Each iteration of this loop assigns exactly one global variable to + // exactly one of the implementation strategies. + + GlobalVariable *GV = K.first; + assert(AMDGPU::isLDSVariableToLower(*GV)); + assert(K.second.size() != 0); + + switch (LoweringKindLoc) { + case LoweringKind::module: + ModuleScopeVariables.insert(GV); + break; + + case LoweringKind::table: + TableLookupVariables.insert(GV); + break; + + case LoweringKind::kernel: + if (K.second.size() == 1) { + KernelAccessVariables.insert(GV); } else { - // However if we are certain this kernel cannot call a function that - // requires module LDS, annotate the kernel so the backend can elide - // the allocation without repeating callgraph walks. - Func.addFnAttr("amdgpu-elide-module-lds"); + report_fatal_error("Cannot lower LDS to kernel access as it is " + "reachable from multiple kernels"); } + break; + + case LoweringKind::hybrid: { + if (GV == HybridModuleRoot) { + assert(K.second.size() != 1); + ModuleScopeVariables.insert(GV); + } else if (K.second.size() == 1) { + KernelAccessVariables.insert(GV); + } else if (set_is_subset(K.second, HybridModuleRootKernels)) { + ModuleScopeVariables.insert(GV); + } else { + TableLookupVariables.insert(GV); + } + break; + } } } - Changed = true; + assert(ModuleScopeVariables.size() + TableLookupVariables.size() + + KernelAccessVariables.size() == + LDSToKernelsThatNeedToAccessItIndirectly.size()); + } // Variables have now been partitioned into the three lowering strategies. + + // If the kernel accesses a variable that is going to be stored in the + // module instance through a call then that kernel needs to allocate the + // module instance + DenseSet KernelsThatAllocateModuleLDS = + kernelsThatIndirectlyAccessAnyOfPassedVariables(M, LDSUsesInfo, + ModuleScopeVariables); + DenseSet KernelsThatAllocateTableLDS = + kernelsThatIndirectlyAccessAnyOfPassedVariables(M, LDSUsesInfo, + TableLookupVariables); + + if (!ModuleScopeVariables.empty()) { + LDSVariableReplacement ModuleScopeReplacement = + createLDSVariableReplacement(M, "llvm.amdgcn.module.lds", + ModuleScopeVariables); + + appendToCompilerUsed(M, + {static_cast( + ConstantExpr::getPointerBitCastOrAddrSpaceCast( + cast(ModuleScopeReplacement.SGV), + Type::getInt8PtrTy(Ctx)))}); + + // historic + removeFromUsedLists(M, ModuleScopeVariables); + + // Replace all uses of module scope variable from non-kernel functions + replaceLDSVariablesWithStruct( + M, ModuleScopeVariables, ModuleScopeReplacement, [&](Use &U) { + Instruction *I = dyn_cast(U.getUser()); + if (!I) { + return false; + } + Function *F = I->getFunction(); + return !isKernelLDS(F); + }); + + // Replace uses of module scope variable from kernel functions that + // allocate the module scope variable, otherwise leave them unchanged + // Record on each kernel whether the module scope global is used by it + + LLVMContext &Ctx = M.getContext(); + IRBuilder<> Builder(Ctx); + + for (Function &Func : M.functions()) { + if (Func.isDeclaration() || !isKernelLDS(&Func)) + continue; + + if (KernelsThatAllocateModuleLDS.contains(&Func)) { + replaceLDSVariablesWithStruct( + M, ModuleScopeVariables, ModuleScopeReplacement, [&](Use &U) { + Instruction *I = dyn_cast(U.getUser()); + if (!I) { + return false; + } + Function *F = I->getFunction(); + return F == &Func; + }); + + markUsedByKernel(Builder, &Func, ModuleScopeReplacement.SGV); + + } else { + Func.addFnAttr("amdgpu-elide-module-lds"); + } + } } - // Move variables used by kernels into per-kernel instances - for (Function &F : M.functions()) { - if (F.isDeclaration()) + // Create a struct for each kernel for the non-module-scope variables + DenseMap KernelToReplacement; + for (Function &Func : M.functions()) { + if (Func.isDeclaration() || !isKernelLDS(&Func)) continue; - // Only lower compute kernels' LDS. - if (!AMDGPU::isKernel(F.getCallingConv())) + DenseSet KernelUsedVariables; + for (auto &v : LDSUsesInfo.direct_access[&Func]) { + KernelUsedVariables.insert(v); + } + for (auto &v : LDSUsesInfo.indirect_access[&Func]) { + KernelUsedVariables.insert(v); + } + + // Variables allocated in module lds must all resolve to that struct, + // not to the per-kernel instance. + if (KernelsThatAllocateModuleLDS.contains(&Func)) { + for (GlobalVariable *v : ModuleScopeVariables) { + KernelUsedVariables.erase(v); + } + } + + if (KernelUsedVariables.empty()) { + // Either used no LDS, or all the LDS it used was also in module continue; + } + + // The association between kernel function and LDS struct is done by + // symbol name, which only works if the function in question has a + // name This is not expected to be a problem in practice as kernels + // are called by name making anonymous ones (which are named by the + // backend) difficult to use. This does mean that llvm test cases need + // to name the kernels. + if (!Func.hasName()) { + report_fatal_error("Anonymous kernels cannot use LDS variables"); + } + + std::string VarName = + (Twine("llvm.amdgcn.kernel.") + Func.getName() + ".lds").str(); - std::vector KernelUsedVariables = - AMDGPU::findLDSVariablesToLower(M, &F); - - if (!KernelUsedVariables.empty()) { - // The association between kernel function and LDS struct is done by - // symbol name, which only works if the function in question has a name - // This is not expected to be a problem in practice as kernels are - // called by name making anonymous ones (which are named by the backend) - // difficult to use. This does mean that llvm test cases need - // to name the kernels. - if (!F.hasName()) { - report_fatal_error("Anonymous kernels cannot use LDS variables"); + auto Replacement = + createLDSVariableReplacement(M, VarName, KernelUsedVariables); + + // remove preserves existing codegen + removeFromUsedLists(M, KernelUsedVariables); + KernelToReplacement[&Func] = Replacement; + + // Rewrite uses within kernel to the new struct + replaceLDSVariablesWithStruct( + M, KernelUsedVariables, Replacement, [&Func](Use &U) { + Instruction *I = dyn_cast(U.getUser()); + return I && I->getFunction() == &Func; + }); + } + + // Lower zero cost accesses to the kernel instances just created + for (auto &GV : KernelAccessVariables) { + auto &funcs = LDSToKernelsThatNeedToAccessItIndirectly[GV]; + assert(funcs.size() == 1); // Only one kernel can access it + LDSVariableReplacement Replacement = + KernelToReplacement[*(funcs.begin())]; + + DenseSet Vec; + Vec.insert(GV); + + replaceLDSVariablesWithStruct(M, Vec, Replacement, [](Use &U) { + return isa(U.getUser()); + }); + } + + if (!KernelsThatAllocateTableLDS.empty()) { + // Collect the kernels that allocate table lookup LDS + std::vector OrderedKernels; + { + for (Function &Func : M.functions()) { + if (Func.isDeclaration()) + continue; + if (!isKernelLDS(&Func)) + continue; + + if (KernelsThatAllocateTableLDS.contains(&Func)) { + assert(Func.hasName()); // else fatal error earlier + OrderedKernels.push_back(&Func); + } } - std::string VarName = - (Twine("llvm.amdgcn.kernel.") + F.getName() + ".lds").str(); - GlobalVariable *SGV; - DenseMap LDSVarsToConstantGEP; - std::tie(SGV, LDSVarsToConstantGEP) = - createLDSVariableReplacement(M, VarName, KernelUsedVariables); - - removeFromUsedLists(M, KernelUsedVariables); - replaceLDSVariablesWithStruct( - M, KernelUsedVariables, SGV, LDSVarsToConstantGEP, [&F](Use &U) { - Instruction *I = dyn_cast(U.getUser()); - return I && I->getFunction() == &F; - }); - Changed = true; + // Put them in an arbitrary but reproducible order + llvm::sort(OrderedKernels.begin(), OrderedKernels.end(), + [](const Function *lhs, const Function *rhs) -> bool { + return lhs->getName() < rhs->getName(); + }); + + // Annotate the kernels with their order in this vector + LLVMContext &Ctx = M.getContext(); + IRBuilder<> Builder(Ctx); + + if (OrderedKernels.size() > UINT32_MAX) { + // 32 bit keeps it in one SGPR. > 2**32 kernels won't fit on the GPU + report_fatal_error("Unimplemented LDS lowering for > 2**32 kernels"); + } + + for (size_t i = 0; i < OrderedKernels.size(); i++) { + Metadata *AttrMDArgs[1] = { + ConstantAsMetadata::get(Builder.getInt32(i)), + }; + OrderedKernels[i]->setMetadata("llvm.amdgcn.lds.kernel.id", + MDNode::get(Ctx, AttrMDArgs)); + + markUsedByKernel(Builder, OrderedKernels[i], + KernelToReplacement[OrderedKernels[i]].SGV); + } } + + // The order must be consistent between lookup table and accesses to + // lookup table + std::vector TableLookupVariablesOrdered( + TableLookupVariables.begin(), TableLookupVariables.end()); + llvm::sort(TableLookupVariablesOrdered.begin(), + TableLookupVariablesOrdered.end(), + [](const GlobalVariable *lhs, const GlobalVariable *rhs) { + return lhs->getName() < rhs->getName(); + }); + + GlobalVariable *LookupTable = buildLookupTable( + M, TableLookupVariablesOrdered, OrderedKernels, KernelToReplacement); + replaceUsesInInstructionsWithTableLookup(M, TableLookupVariablesOrdered, + LookupTable); } for (auto &GV : make_early_inc_range(M.globals())) if (AMDGPU::isLDSVariableToLower(GV)) { + + // probably want to remove from used lists GV.removeDeadConstantUsers(); if (GV.use_empty()) GV.eraseFromParent(); @@ -375,10 +1033,9 @@ return Changed; } - std::tuple> - createLDSVariableReplacement( + static LDSVariableReplacement createLDSVariableReplacement( Module &M, std::string VarName, - std::vector const &LDSVarsToTransform) { + DenseSet const &LDSVarsToTransform) { // Create a struct instance containing LDSVarsToTransform and map from those // variables to ConstantExprGEP // Variables may be introduced to meet alignment requirements. No aliasing @@ -474,18 +1131,26 @@ } } assert(Map.size() == LDSVarsToTransform.size()); - return std::make_tuple(SGV, std::move(Map)); + return {SGV, std::move(Map)}; } template void replaceLDSVariablesWithStruct( - Module &M, std::vector const &LDSVarsToTransform, - GlobalVariable *SGV, - DenseMap &LDSVarsToConstantGEP, - PredicateTy Predicate) { + Module &M, DenseSet const &LDSVarsToTransformArg, + LDSVariableReplacement Replacement, PredicateTy Predicate) { LLVMContext &Ctx = M.getContext(); const DataLayout &DL = M.getDataLayout(); + // A hack... we need to insert the aliasing info in a predictable order for + // lit tests. Would like to have them in a stable order already, ideally the + // same order they get allocated, which might mean an ordered set container + std::vector LDSVarsToTransform( + LDSVarsToTransformArg.begin(), LDSVarsToTransformArg.end()); + llvm::sort(LDSVarsToTransform.begin(), LDSVarsToTransform.end(), + [](const GlobalVariable *lhs, const GlobalVariable *rhs) { + return lhs->getName() < rhs->getName(); + }); + // Create alias.scope and their lists. Each field in the new structure // does not alias with all other fields. SmallVector AliasScopes; @@ -506,18 +1171,16 @@ // field of the instance that will be allocated by AMDGPUMachineFunction for (size_t I = 0; I < NumberVars; I++) { GlobalVariable *GV = LDSVarsToTransform[I]; - Constant *GEP = LDSVarsToConstantGEP[GV]; + Constant *GEP = Replacement.LDSVarsToConstantGEP[GV]; GV->replaceUsesWithIf(GEP, Predicate); - if (GV->use_empty()) { - GV->eraseFromParent(); - } APInt APOff(DL.getIndexTypeSizeInBits(GEP->getType()), 0); GEP->stripAndAccumulateInBoundsConstantOffsets(DL, APOff); uint64_t Offset = APOff.getZExtValue(); - Align A = commonAlignment(SGV->getAlign().valueOrOne(), Offset); + Align A = + commonAlignment(Replacement.SGV->getAlign().valueOrOne(), Offset); if (I) NoAliasList[I - 1] = AliasScopes[I - 1]; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp @@ -14,6 +14,7 @@ #include "AMDGPUMCInstLower.h" #include "AMDGPUAsmPrinter.h" +#include "AMDGPUMachineFunction.h" #include "AMDGPUTargetMachine.h" #include "MCTargetDesc/AMDGPUInstPrinter.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h" @@ -165,6 +166,17 @@ } const MCExpr *AMDGPUAsmPrinter::lowerConstant(const Constant *CV) { + + // Intercept LDS variables with known addresses + if (const GlobalVariable *GV = dyn_cast(CV)) { + if (AMDGPUMachineFunction::isKnownAddressLDSGlobal(*GV)) { + unsigned offset = + AMDGPUMachineFunction::calculateKnownAddressOfLDSGlobal(*GV); + Constant *C = ConstantInt::get(CV->getContext(), APInt(32, offset)); + return AsmPrinter::lowerConstant(C); + } + } + if (const MCExpr *E = lowerAddrSpaceCast(TM, CV, OutContext)) return E; return AsmPrinter::lowerConstant(CV); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h --- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h @@ -98,6 +98,7 @@ unsigned allocateLDSGlobal(const DataLayout &DL, const GlobalVariable &GV) { return allocateLDSGlobal(DL, GV, DynLDSAlign); } + unsigned allocateLDSGlobal(const DataLayout &DL, const GlobalVariable &GV, Align Trailing); @@ -105,9 +106,17 @@ // A kernel function may have an associated LDS allocation, and a kernel-scope // LDS allocation must have an associated kernel function + + // LDS allocation should have an associated kernel function + static const Function * + getKernelLDSFunctionFromGlobal(const GlobalVariable &GV); static const GlobalVariable * getKernelLDSGlobalFromFunction(const Function &F); + // Module or kernel scope LDS variable + static bool isKnownAddressLDSGlobal(const GlobalVariable &GV); + static unsigned calculateKnownAddressOfLDSGlobal(const GlobalVariable &GV); + static Optional getLDSKernelIdMetadata(const Function &F); Align getDynLDSAlign() const { return DynLDSAlign; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp @@ -84,6 +84,24 @@ return Offset; } +static constexpr StringLiteral ModuleLDSName = "llvm.amdgcn.module.lds"; + +bool AMDGPUMachineFunction::isKnownAddressLDSGlobal(const GlobalVariable &GV) { + auto name = GV.getName(); + return (name == ModuleLDSName) || + (name.startswith("llvm.amdgcn.kernel.") && name.endswith(".lds")); +} + +const Function *AMDGPUMachineFunction::getKernelLDSFunctionFromGlobal( + const GlobalVariable &GV) { + const Module &M = *GV.getParent(); + StringRef N(GV.getName()); + if (N.consume_front("llvm.amdgcn.kernel.") && N.consume_back(".lds")) { + return M.getFunction(N); + } + return nullptr; +} + const GlobalVariable * AMDGPUMachineFunction::getKernelLDSGlobalFromFunction(const Function &F) { const Module *M = F.getParent(); @@ -98,6 +116,37 @@ return F.hasFnAttribute("amdgpu-elide-module-lds"); } +unsigned AMDGPUMachineFunction::calculateKnownAddressOfLDSGlobal( + const GlobalVariable &GV) { + // module.lds, then alignment padding, then kernel.lds, then other variables + // if any + + assert(isKnownAddressLDSGlobal(GV)); + unsigned Offset = 0; + + if (GV.getName() == ModuleLDSName) { + return 0; + } + + const Module *M = GV.getParent(); + const DataLayout &DL = M->getDataLayout(); + + const GlobalVariable *GVM = M->getNamedGlobal(ModuleLDSName); + const Function *f = getKernelLDSFunctionFromGlobal(GV); + + // Account for module.lds if allocated for this function + if (GVM && f && !canElideModuleLDS(*f)) { + // allocator aligns this to var align, but it's zero to begin with + Offset += DL.getTypeAllocSize(GVM->getValueType()); + } + + // No dynamic LDS alignment done by allocateModuleLDSGlobal + Offset = alignTo( + Offset, DL.getValueOrABITypeAlignment(GV.getAlign(), GV.getValueType())); + + return Offset; +} + void AMDGPUMachineFunction::allocateKnownAddressLDSGlobal(const Function &F) { const Module *M = F.getParent(); @@ -124,21 +173,25 @@ // } // other variables, e.g. dynamic lds, allocated after this call - const GlobalVariable *GV = M->getNamedGlobal("llvm.amdgcn.module.lds"); + const GlobalVariable *GV = M->getNamedGlobal(ModuleLDSName); const GlobalVariable *KV = getKernelLDSGlobalFromFunction(F); if (GV && !canElideModuleLDS(F)) { + assert(isKnownAddressLDSGlobal(*GV)); unsigned Offset = allocateLDSGlobal(M->getDataLayout(), *GV, Align()); (void)Offset; - assert(Offset == 0 && + assert(Offset == calculateKnownAddressOfLDSGlobal(*GV) && "Module LDS expected to be allocated before other LDS"); } if (KV) { // The per-kernel offset is deterministic because it is allocated // before any other non-module LDS variables. + assert(isKnownAddressLDSGlobal(*KV)); unsigned Offset = allocateLDSGlobal(M->getDataLayout(), *KV, Align()); (void)Offset; + assert(Offset == calculateKnownAddressOfLDSGlobal(*KV) && + "Kernel LDS expected to be immediately after module LDS"); } } } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp @@ -57,8 +57,7 @@ // TODO: Support conservative min/max merging instead of cloning. static constexpr const char *AttributeNames[] = {"amdgpu-waves-per-eu"}; -static constexpr unsigned NumAttr = - sizeof(AttributeNames) / sizeof(AttributeNames[0]); +static constexpr unsigned NumAttr = std::size(AttributeNames); class AMDGPUPropagateAttributes { diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -2877,6 +2877,7 @@ case AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE: case AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE: case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT: + case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_TFE: case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_D16: case AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT: case AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT_D16: @@ -4046,6 +4047,7 @@ case AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT: case AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT: case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT: + case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_TFE: case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_D16: case AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT: case AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT_D16: diff --git a/llvm/lib/Target/AMDGPU/AMDGPUReleaseVGPRs.cpp b/llvm/lib/Target/AMDGPU/AMDGPUReleaseVGPRs.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUReleaseVGPRs.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUReleaseVGPRs.cpp @@ -19,6 +19,7 @@ #include "llvm/ADT/DepthFirstIterator.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineOperand.h" +#include using namespace llvm; #define DEBUG_TYPE "release-vgprs" @@ -46,7 +47,8 @@ class LastVGPRUseIsVMEMStore { BitVector BlockVMEMStore; - static Optional lastVGPRUseIsStore(const MachineBasicBlock &MBB) { + static std::optional + lastVGPRUseIsStore(const MachineBasicBlock &MBB) { for (auto &MI : reverse(MBB.instrs())) { // If it's a VMEM store, a VGPR will be used, return true. if ((SIInstrInfo::isVMEM(MI) || SIInstrInfo::isFLAT(MI)) && diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -50,8 +50,6 @@ return TLOF.get(); } - void adjustPassManager(PassManagerBuilder &) override; - void registerPassBuilderCallbacks(PassBuilder &PB) override; void registerDefaultAliasAnalyses(AAManager &) override; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -51,7 +51,6 @@ #include "llvm/Transforms/IPO/AlwaysInliner.h" #include "llvm/Transforms/IPO/GlobalDCE.h" #include "llvm/Transforms/IPO/Internalize.h" -#include "llvm/Transforms/IPO/PassManagerBuilder.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Scalar/InferAddressSpaces.h" @@ -576,80 +575,6 @@ return !GV.use_empty(); } -void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) { - Builder.DivergentTarget = true; - - bool EnableOpt = getOptLevel() > CodeGenOpt::None; - bool Internalize = InternalizeSymbols; - bool EarlyInline = EarlyInlineAll && EnableOpt && !EnableFunctionCalls; - bool AMDGPUAA = EnableAMDGPUAliasAnalysis && EnableOpt; - bool LibCallSimplify = EnableLibCallSimplify && EnableOpt; - bool PromoteKernelArguments = - EnablePromoteKernelArguments && getOptLevel() > CodeGenOpt::Less; - - if (EnableFunctionCalls) { - delete Builder.Inliner; - Builder.Inliner = createFunctionInliningPass(); - } - - Builder.addExtension( - PassManagerBuilder::EP_ModuleOptimizerEarly, - [Internalize, EarlyInline, AMDGPUAA, this](const PassManagerBuilder &, - legacy::PassManagerBase &PM) { - if (AMDGPUAA) { - PM.add(createAMDGPUAAWrapperPass()); - PM.add(createAMDGPUExternalAAWrapperPass()); - } - PM.add(createAMDGPUUnifyMetadataPass()); - PM.add(createAMDGPUPrintfRuntimeBinding()); - if (Internalize) - PM.add(createInternalizePass(mustPreserveGV)); - PM.add(createAMDGPUPropagateAttributesLatePass(this)); - if (Internalize) - PM.add(createGlobalDCEPass()); - if (EarlyInline) - PM.add(createAMDGPUAlwaysInlinePass(false)); - }); - - Builder.addExtension( - PassManagerBuilder::EP_EarlyAsPossible, - [AMDGPUAA, LibCallSimplify, this](const PassManagerBuilder &, - legacy::PassManagerBase &PM) { - if (AMDGPUAA) { - PM.add(createAMDGPUAAWrapperPass()); - PM.add(createAMDGPUExternalAAWrapperPass()); - } - PM.add(llvm::createAMDGPUPropagateAttributesEarlyPass(this)); - PM.add(llvm::createAMDGPUUseNativeCallsPass()); - if (LibCallSimplify) - PM.add(llvm::createAMDGPUSimplifyLibCallsPass(this)); - }); - - Builder.addExtension( - PassManagerBuilder::EP_CGSCCOptimizerLate, - [EnableOpt, PromoteKernelArguments](const PassManagerBuilder &, - legacy::PassManagerBase &PM) { - // Add promote kernel arguments pass to the opt pipeline right before - // infer address spaces which is needed to do actual address space - // rewriting. - if (PromoteKernelArguments) - PM.add(createAMDGPUPromoteKernelArgumentsPass()); - - // Add infer address spaces pass to the opt pipeline after inlining - // but before SROA to increase SROA opportunities. - PM.add(createInferAddressSpacesPass()); - - // This should run after inlining to have any chance of doing anything, - // and before other cleanup optimizations. - PM.add(createAMDGPULowerKernelAttributesPass()); - - // Promote alloca to vector before SROA and loop unroll. If we manage - // to eliminate allocas before unroll we may choose to unroll less. - if (EnableOpt) - PM.add(createAMDGPUPromoteAllocaToVector()); - }); -} - void AMDGPUTargetMachine::registerDefaultAliasAnalyses(AAManager &AAM) { AAM.registerFunctionAnalysis(); } diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -38,6 +38,7 @@ #include "llvm/Support/MachineValueType.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/TargetParser.h" +#include using namespace llvm; using namespace llvm::AMDGPU; @@ -207,16 +208,7 @@ }; public: - bool isToken() const override { - if (Kind == Token) - return true; - - // When parsing operands, we can't always tell if something was meant to be - // a token, like 'gds', or an expression that references a global variable. - // In this case, we assume the string is an expression, and if we need to - // interpret is a token, then we treat the symbol name as the token. - return isSymbolRefExpr(); - } + bool isToken() const override { return Kind == Token; } bool isSymbolRefExpr() const { return isExpr() && Expr && isa(Expr); @@ -892,18 +884,8 @@ bool isWaitVDST() const; bool isWaitEXP() const; - StringRef getExpressionAsToken() const { - assert(isExpr()); - const MCSymbolRefExpr *S = cast(Expr); - return S->getSymbol().getName(); - } - StringRef getToken() const { assert(isToken()); - - if (Kind == Expression) - return getExpressionAsToken(); - return StringRef(Tok.Data, Tok.Length); } @@ -1271,10 +1253,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser { MCAsmParser &Parser; - // Number of extra operands parsed after the first optional operand. - // This may be necessary to skip hardcoded mandatory operands. - static const unsigned MAX_OPR_LOOKAHEAD = 8; - unsigned ForcedEncodingSize = 0; bool ForcedDPP = false; bool ForcedSDWA = false; @@ -1561,6 +1539,8 @@ SMLoc NameLoc, OperandVector &Operands) override; //bool ProcessInstruction(MCInst &Inst); + OperandMatchResultTy parseTokenOp(StringRef Name, OperandVector &Operands); + OperandMatchResultTy parseIntWithPrefix(const char *Prefix, int64_t &Int); OperandMatchResultTy @@ -1728,8 +1708,8 @@ public: void onBeginOfFile() override; - OperandMatchResultTy parseOptionalOperand(OperandVector &Operands); - OperandMatchResultTy parseOptionalOpr(OperandVector &Operands); + OperandMatchResultTy parseCustomOperand(OperandVector &Operands, + unsigned MCK); OperandMatchResultTy parseExpTgt(OperandVector &Operands); OperandMatchResultTy parseSendMsgOp(OperandVector &Operands); @@ -1839,13 +1819,6 @@ OperandMatchResultTy parseVOPD(OperandVector &Operands); }; -struct OptionalOperand { - const char *Name; - AMDGPUOperand::ImmTy Type; - bool IsBit; - bool (*ConvertResult)(int64_t&); -}; - } // end anonymous namespace // May be called with integer type with equivalent bitwidth. @@ -3086,8 +3059,6 @@ // -|...| // -abs(...) // name:... -// Note that simple opcode modifiers like 'gds' may be parsed as -// expressions; this is a special case. See getExpressionAsToken. // bool AMDGPUAsmParser::isModifier() { @@ -5013,7 +4984,7 @@ // Track if the asm explicitly contains the directive for the user SGPR // count. - Optional ExplicitUserSGPRCount; + std::optional ExplicitUserSGPRCount; bool ReserveVCC = true; bool ReserveFlatScr = true; Optional EnableWavefrontSize32; @@ -5927,6 +5898,16 @@ // Utility functions //===----------------------------------------------------------------------===// +OperandMatchResultTy AMDGPUAsmParser::parseTokenOp(StringRef Name, + OperandVector &Operands) { + SMLoc S = getLoc(); + if (!trySkipId(Name)) + return MatchOperand_NoMatch; + + Operands.push_back(AMDGPUOperand::CreateToken(this, Name, S)); + return MatchOperand_Success; +} + OperandMatchResultTy AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &IntVal) { @@ -6033,75 +6014,84 @@ OperandMatchResultTy AMDGPUAsmParser::parseCPol(OperandVector &Operands) { - unsigned CPolOn = 0; - unsigned CPolOff = 0; - SMLoc S = getLoc(); + OperandMatchResultTy Res = MatchOperand_NoMatch; - StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken(); - if (isGFX940() && !Mnemo.startswith("s_")) { - if (trySkipId("sc0")) - CPolOn = AMDGPU::CPol::SC0; - else if (trySkipId("nosc0")) - CPolOff = AMDGPU::CPol::SC0; - else if (trySkipId("nt")) - CPolOn = AMDGPU::CPol::NT; - else if (trySkipId("nont")) - CPolOff = AMDGPU::CPol::NT; - else if (trySkipId("sc1")) - CPolOn = AMDGPU::CPol::SC1; - else if (trySkipId("nosc1")) - CPolOff = AMDGPU::CPol::SC1; + for (;;) { + unsigned CPolOn = 0; + unsigned CPolOff = 0; + SMLoc S = getLoc(); + + StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken(); + if (isGFX940() && !Mnemo.startswith("s_")) { + if (trySkipId("sc0")) + CPolOn = AMDGPU::CPol::SC0; + else if (trySkipId("nosc0")) + CPolOff = AMDGPU::CPol::SC0; + else if (trySkipId("nt")) + CPolOn = AMDGPU::CPol::NT; + else if (trySkipId("nont")) + CPolOff = AMDGPU::CPol::NT; + else if (trySkipId("sc1")) + CPolOn = AMDGPU::CPol::SC1; + else if (trySkipId("nosc1")) + CPolOff = AMDGPU::CPol::SC1; + else + break; + } else if (trySkipId("glc")) + CPolOn = AMDGPU::CPol::GLC; + else if (trySkipId("noglc")) + CPolOff = AMDGPU::CPol::GLC; + else if (trySkipId("slc")) + CPolOn = AMDGPU::CPol::SLC; + else if (trySkipId("noslc")) + CPolOff = AMDGPU::CPol::SLC; + else if (trySkipId("dlc")) + CPolOn = AMDGPU::CPol::DLC; + else if (trySkipId("nodlc")) + CPolOff = AMDGPU::CPol::DLC; + else if (trySkipId("scc")) + CPolOn = AMDGPU::CPol::SCC; + else if (trySkipId("noscc")) + CPolOff = AMDGPU::CPol::SCC; else - return MatchOperand_NoMatch; - } - else if (trySkipId("glc")) - CPolOn = AMDGPU::CPol::GLC; - else if (trySkipId("noglc")) - CPolOff = AMDGPU::CPol::GLC; - else if (trySkipId("slc")) - CPolOn = AMDGPU::CPol::SLC; - else if (trySkipId("noslc")) - CPolOff = AMDGPU::CPol::SLC; - else if (trySkipId("dlc")) - CPolOn = AMDGPU::CPol::DLC; - else if (trySkipId("nodlc")) - CPolOff = AMDGPU::CPol::DLC; - else if (trySkipId("scc")) - CPolOn = AMDGPU::CPol::SCC; - else if (trySkipId("noscc")) - CPolOff = AMDGPU::CPol::SCC; - else - return MatchOperand_NoMatch; + break; - if (!isGFX10Plus() && ((CPolOn | CPolOff) & AMDGPU::CPol::DLC)) { - Error(S, "dlc modifier is not supported on this GPU"); - return MatchOperand_ParseFail; - } + if (!isGFX10Plus() && ((CPolOn | CPolOff) & AMDGPU::CPol::DLC)) { + Error(S, "dlc modifier is not supported on this GPU"); + return MatchOperand_ParseFail; + } - if (!isGFX90A() && ((CPolOn | CPolOff) & AMDGPU::CPol::SCC)) { - Error(S, "scc modifier is not supported on this GPU"); - return MatchOperand_ParseFail; - } + if (!isGFX90A() && ((CPolOn | CPolOff) & AMDGPU::CPol::SCC)) { + Error(S, "scc modifier is not supported on this GPU"); + return MatchOperand_ParseFail; + } - if (CPolSeen & (CPolOn | CPolOff)) { - Error(S, "duplicate cache policy modifier"); - return MatchOperand_ParseFail; - } + if (CPolSeen & (CPolOn | CPolOff)) { + Error(S, "duplicate cache policy modifier"); + return MatchOperand_ParseFail; + } - CPolSeen |= (CPolOn | CPolOff); + CPolSeen |= (CPolOn | CPolOff); + Res = MatchOperand_Success; - for (unsigned I = 1; I != Operands.size(); ++I) { - AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); - if (Op.isCPol()) { - Op.setImm((Op.getImm() | CPolOn) & ~CPolOff); - return MatchOperand_Success; + AMDGPUOperand *CPolOp = nullptr; + for (unsigned I = 1; I != Operands.size(); ++I) { + AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]); + if (Op.isCPol()) { + CPolOp = &Op; + break; + } } - } - Operands.push_back(AMDGPUOperand::CreateImm(this, CPolOn, S, - AMDGPUOperand::ImmTyCPol)); + if (CPolOp) { + CPolOp->setImm((CPolOp->getImm() | CPolOn) & ~CPolOff); + } else { + Operands.push_back( + AMDGPUOperand::CreateImm(this, CPolOn, S, AMDGPUOperand::ImmTyCPol)); + } + } - return MatchOperand_Success; + return Res; } static void addOptionalImmOperand( @@ -7588,12 +7578,9 @@ Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle)); - return Ok? MatchOperand_Success : MatchOperand_ParseFail; - } else { - // Swizzle "offset" operand is optional. - // If it is omitted, try parsing other optional operands. - return parseOptionalOpr(Operands); + return Ok ? MatchOperand_Success : MatchOperand_ParseFail; } + return MatchOperand_NoMatch; } bool @@ -8018,55 +8005,6 @@ return false; } -// Note: the order in this table matches the order of operands in AsmString. -static const OptionalOperand AMDGPUOptionalOperandTable[] = { - {"offen", AMDGPUOperand::ImmTyOffen, true, nullptr}, - {"idxen", AMDGPUOperand::ImmTyIdxen, true, nullptr}, - {"addr64", AMDGPUOperand::ImmTyAddr64, true, nullptr}, - {"offset0", AMDGPUOperand::ImmTyOffset0, false, nullptr}, - {"offset1", AMDGPUOperand::ImmTyOffset1, false, nullptr}, - {"gds", AMDGPUOperand::ImmTyGDS, true, nullptr}, - {"lds", AMDGPUOperand::ImmTyLDS, true, nullptr}, - {"offset", AMDGPUOperand::ImmTyOffset, false, nullptr}, - {"inst_offset", AMDGPUOperand::ImmTyInstOffset, false, nullptr}, - {"", AMDGPUOperand::ImmTyCPol, false, nullptr}, - {"swz", AMDGPUOperand::ImmTySWZ, true, nullptr}, - {"tfe", AMDGPUOperand::ImmTyTFE, true, nullptr}, - {"d16", AMDGPUOperand::ImmTyD16, true, nullptr}, - {"high", AMDGPUOperand::ImmTyHigh, true, nullptr}, - {"clamp", AMDGPUOperand::ImmTyClampSI, true, nullptr}, - {"omod", AMDGPUOperand::ImmTyOModSI, false, ConvertOmodMul}, - {"unorm", AMDGPUOperand::ImmTyUNorm, true, nullptr}, - {"da", AMDGPUOperand::ImmTyDA, true, nullptr}, - {"r128", AMDGPUOperand::ImmTyR128A16, true, nullptr}, - {"a16", AMDGPUOperand::ImmTyA16, true, nullptr}, - {"lwe", AMDGPUOperand::ImmTyLWE, true, nullptr}, - {"d16", AMDGPUOperand::ImmTyD16, true, nullptr}, - {"dmask", AMDGPUOperand::ImmTyDMask, false, nullptr}, - {"dim", AMDGPUOperand::ImmTyDim, false, nullptr}, - {"dst_sel", AMDGPUOperand::ImmTySdwaDstSel, false, nullptr}, - {"src0_sel", AMDGPUOperand::ImmTySdwaSrc0Sel, false, nullptr}, - {"src1_sel", AMDGPUOperand::ImmTySdwaSrc1Sel, false, nullptr}, - {"dst_unused", AMDGPUOperand::ImmTySdwaDstUnused, false, nullptr}, - {"compr", AMDGPUOperand::ImmTyExpCompr, true, nullptr }, - {"vm", AMDGPUOperand::ImmTyExpVM, true, nullptr}, - {"op_sel", AMDGPUOperand::ImmTyOpSel, false, nullptr}, - {"op_sel_hi", AMDGPUOperand::ImmTyOpSelHi, false, nullptr}, - {"neg_lo", AMDGPUOperand::ImmTyNegLo, false, nullptr}, - {"neg_hi", AMDGPUOperand::ImmTyNegHi, false, nullptr}, - {"dpp8", AMDGPUOperand::ImmTyDPP8, false, nullptr}, - {"dpp_ctrl", AMDGPUOperand::ImmTyDppCtrl, false, nullptr}, - {"row_mask", AMDGPUOperand::ImmTyDppRowMask, false, nullptr}, - {"bank_mask", AMDGPUOperand::ImmTyDppBankMask, false, nullptr}, - {"bound_ctrl", AMDGPUOperand::ImmTyDppBoundCtrl, false, ConvertBoundCtrl}, - {"fi", AMDGPUOperand::ImmTyDppFi, false, nullptr}, - {"blgp", AMDGPUOperand::ImmTyBLGP, false, nullptr}, - {"cbsz", AMDGPUOperand::ImmTyCBSZ, false, nullptr}, - {"abid", AMDGPUOperand::ImmTyABID, false, nullptr}, - {"wait_vdst", AMDGPUOperand::ImmTyWaitVDST, false, nullptr}, - {"wait_exp", AMDGPUOperand::ImmTyWaitEXP, false, nullptr} -}; - void AMDGPUAsmParser::onBeginOfFile() { if (!getParser().getStreamer().getTargetStreamer() || getSTI().getTargetTriple().getArch() == Triple::r600) @@ -8079,76 +8017,6 @@ getTargetStreamer().EmitDirectiveAMDGCNTarget(); } -OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) { - - OperandMatchResultTy res = parseOptionalOpr(Operands); - - // This is a hack to enable hardcoded mandatory operands which follow - // optional operands. - // - // Current design assumes that all operands after the first optional operand - // are also optional. However implementation of some instructions violates - // this rule (see e.g. flat/global atomic which have hardcoded 'glc' operands). - // - // To alleviate this problem, we have to (implicitly) parse extra operands - // to make sure autogenerated parser of custom operands never hit hardcoded - // mandatory operands. - - for (unsigned i = 0; i < MAX_OPR_LOOKAHEAD; ++i) { - if (res != MatchOperand_Success || - isToken(AsmToken::EndOfStatement)) - break; - - trySkipToken(AsmToken::Comma); - res = parseOptionalOpr(Operands); - } - - return res; -} - -OperandMatchResultTy AMDGPUAsmParser::parseOptionalOpr(OperandVector &Operands) { - OperandMatchResultTy res; - for (const OptionalOperand &Op : AMDGPUOptionalOperandTable) { - // try to parse any optional operand here - if (Op.IsBit) { - res = parseNamedBit(Op.Name, Operands, Op.Type); - } else if (Op.Type == AMDGPUOperand::ImmTyOModSI) { - res = parseOModOperand(Operands); - } else if (Op.Type == AMDGPUOperand::ImmTySdwaDstSel || - Op.Type == AMDGPUOperand::ImmTySdwaSrc0Sel || - Op.Type == AMDGPUOperand::ImmTySdwaSrc1Sel) { - res = parseSDWASel(Operands, Op.Name, Op.Type); - } else if (Op.Type == AMDGPUOperand::ImmTySdwaDstUnused) { - res = parseSDWADstUnused(Operands); - } else if (Op.Type == AMDGPUOperand::ImmTyOpSel || - Op.Type == AMDGPUOperand::ImmTyOpSelHi || - Op.Type == AMDGPUOperand::ImmTyNegLo || - Op.Type == AMDGPUOperand::ImmTyNegHi) { - res = parseOperandArrayWithPrefix(Op.Name, Operands, Op.Type, - Op.ConvertResult); - } else if (Op.Type == AMDGPUOperand::ImmTyDim) { - res = parseDim(Operands); - } else if (Op.Type == AMDGPUOperand::ImmTyCPol) { - res = parseCPol(Operands); - } else if (Op.Type == AMDGPUOperand::ImmTyDPP8) { - res = parseDPP8(Operands); - } else if (Op.Type == AMDGPUOperand::ImmTyDppCtrl) { - res = parseDPPCtrl(Operands); - } else { - res = parseIntWithPrefix(Op.Name, Operands, Op.Type, Op.ConvertResult); - if (Op.Type == AMDGPUOperand::ImmTyBLGP && res == MatchOperand_NoMatch) { - res = parseOperandArrayWithPrefix("neg", Operands, - AMDGPUOperand::ImmTyBLGP, - nullptr); - } - } - if (res != MatchOperand_NoMatch) { - return res; - } - } - return MatchOperand_NoMatch; -} - OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands) { StringRef Name = getTokenStr(); if (Name == "mul") { @@ -9242,6 +9110,133 @@ #define GET_MNEMONIC_CHECKER #include "AMDGPUGenAsmMatcher.inc" +OperandMatchResultTy +AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands, unsigned MCK) { + switch (MCK) { + case MCK_addr64: + return parseTokenOp("addr64", Operands); + case MCK_done: + return parseTokenOp("done", Operands); + case MCK_idxen: + return parseTokenOp("idxen", Operands); + case MCK_lds: + return parseTokenOp("lds", Operands); + case MCK_offen: + return parseTokenOp("offen", Operands); + case MCK_off: + return parseTokenOp("off", Operands); + case MCK_row_95_en: + return parseTokenOp("row_en", Operands); + case MCK_ImmABID: + return parseIntWithPrefix("abid", Operands, AMDGPUOperand::ImmTyABID); + case MCK_ImmBankMask: + return parseIntWithPrefix("bank_mask", Operands, + AMDGPUOperand::ImmTyDppBankMask); + case MCK_ImmBLGP: { + OperandMatchResultTy Res = + parseIntWithPrefix("blgp", Operands, AMDGPUOperand::ImmTyBLGP); + if (Res == MatchOperand_NoMatch) { + Res = parseOperandArrayWithPrefix("neg", Operands, + AMDGPUOperand::ImmTyBLGP); + } + return Res; + } + case MCK_ImmBoundCtrl: + return parseIntWithPrefix("bound_ctrl", Operands, + AMDGPUOperand::ImmTyDppBoundCtrl, + ConvertBoundCtrl); + case MCK_ImmCBSZ: + return parseIntWithPrefix("cbsz", Operands, AMDGPUOperand::ImmTyCBSZ); + case MCK_ImmClampSI: + return parseNamedBit("clamp", Operands, AMDGPUOperand::ImmTyClampSI); + case MCK_ImmCPol: + return parseCPol(Operands); + case MCK_ImmD16: + return parseNamedBit("d16", Operands, AMDGPUOperand::ImmTyD16); + case MCK_ImmDA: + return parseNamedBit("da", Operands, AMDGPUOperand::ImmTyDA); + case MCK_ImmDMask: + return parseIntWithPrefix("dmask", Operands, AMDGPUOperand::ImmTyDMask); + case MCK_ImmExpCompr: + return parseNamedBit("compr", Operands, AMDGPUOperand::ImmTyExpCompr); + case MCK_ImmExpVM: + return parseNamedBit("vm", Operands, AMDGPUOperand::ImmTyExpVM); + case MCK_ImmFI: + return parseIntWithPrefix("fi", Operands, AMDGPUOperand::ImmTyDppFi); + case MCK_gds: + case MCK_ImmGDS: + return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS); + case MCK_ImmGFX10A16: + return parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16); + case MCK_ImmHigh: + return parseNamedBit("high", Operands, AMDGPUOperand::ImmTyHigh); + case MCK_ImmLWE: + return parseNamedBit("lwe", Operands, AMDGPUOperand::ImmTyLWE); + case MCK_ImmNegHi: + return parseOperandArrayWithPrefix("neg_hi", Operands, + AMDGPUOperand::ImmTyNegHi); + case MCK_ImmNegLo: + return parseOperandArrayWithPrefix("neg_lo", Operands, + AMDGPUOperand::ImmTyNegLo); + case MCK_ImmOffset: + case MCK_ImmSMEMOffset: + return parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset); + case MCK_ImmFlatOffset: { + OperandMatchResultTy Res = + parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset); + if (Res == MatchOperand_NoMatch) { + Res = parseIntWithPrefix("inst_offset", Operands, + AMDGPUOperand::ImmTyInstOffset); + } + return Res; + } + case MCK_ImmOffset0: + return parseIntWithPrefix("offset0", Operands, AMDGPUOperand::ImmTyOffset0); + case MCK_ImmOffset1: + return parseIntWithPrefix("offset1", Operands, AMDGPUOperand::ImmTyOffset1); + case MCK_ImmOModSI: + return parseOModOperand(Operands); + case MCK_ImmOpSel: + return parseOperandArrayWithPrefix("op_sel", Operands, + AMDGPUOperand::ImmTyOpSel); + case MCK_ImmOpSelHi: + return parseOperandArrayWithPrefix("op_sel_hi", Operands, + AMDGPUOperand::ImmTyOpSelHi); + case MCK_ImmR128A16: { + OperandMatchResultTy Res = + parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128A16); + if (Res == MatchOperand_NoMatch) + Res = parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16); + return Res; + } + case MCK_ImmRowMask: + return parseIntWithPrefix("row_mask", Operands, + AMDGPUOperand::ImmTyDppRowMask); + case MCK_ImmSDWADstSel: + return parseSDWASel(Operands, "dst_sel", AMDGPUOperand::ImmTySdwaDstSel); + case MCK_ImmSDWADstUnused: + return parseSDWADstUnused(Operands); + case MCK_ImmSDWASrc0Sel: + return parseSDWASel(Operands, "src0_sel", AMDGPUOperand::ImmTySdwaSrc0Sel); + case MCK_ImmSDWASrc1Sel: + return parseSDWASel(Operands, "src1_sel", AMDGPUOperand::ImmTySdwaSrc1Sel); + case MCK_ImmSWZ: + return parseNamedBit("swz", Operands, AMDGPUOperand::ImmTySWZ); + case MCK_tfe: + case MCK_ImmTFE: + return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE); + case MCK_ImmUNorm: + return parseNamedBit("unorm", Operands, AMDGPUOperand::ImmTyUNorm); + case MCK_ImmWaitEXP: + return parseIntWithPrefix("wait_exp", Operands, + AMDGPUOperand::ImmTyWaitEXP); + case MCK_ImmWaitVDST: + return parseIntWithPrefix("wait_vdst", Operands, + AMDGPUOperand::ImmTyWaitVDST); + } + return tryCustomParseOperand(Operands, MCK); +} + // This function should be defined after auto-generated include so that we have // MatchClassKind enum defined unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op, @@ -9263,6 +9258,7 @@ case MCK_offen: return Operand.isOffen() ? Match_Success : Match_InvalidOperand; case MCK_tfe: + case MCK_ImmTFE: return Operand.isTFE() ? Match_Success : Match_InvalidOperand; case MCK_SSrcB32: // When operands have expression values, they will return true for isToken, diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td --- a/llvm/lib/Target/AMDGPU/BUFInstructions.td +++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td @@ -1299,6 +1299,11 @@ defm : MUBUF_LoadIntrinsicPat; defm : MUBUF_LoadIntrinsicPat; +defm : MUBUF_LoadIntrinsicPat; +defm : MUBUF_LoadIntrinsicPat; +defm : MUBUF_LoadIntrinsicPat; +defm : MUBUF_LoadIntrinsicPat; + let SubtargetPredicate = HasUnpackedD16VMem in { defm : MUBUF_LoadIntrinsicPat; defm : MUBUF_LoadIntrinsicPat; diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp @@ -543,9 +543,9 @@ S.emitValue(DescSZ, 4); // descz S.emitInt32(NoteType); // type S.emitBytes(Name); // name - S.emitValueToAlignment(4, 0, 1, 0); // padding 0 + S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0 EmitDesc(S); // desc - S.emitValueToAlignment(4, 0, 1, 0); // padding 0 + S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0 S.popSection(); } @@ -840,7 +840,7 @@ MCStreamer &OS = getStreamer(); OS.pushSection(); - OS.emitValueToAlignment(CacheLineSize, Encoded_pad, 4); + OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4); for (unsigned I = 0; I < FillSize; I += 4) OS.emitInt32(Encoded_pad); OS.popSection(); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp @@ -26,6 +26,7 @@ #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/Casting.h" +#include using namespace llvm; @@ -35,8 +36,9 @@ const MCRegisterInfo &MRI; /// Encode an fp or int literal - uint32_t getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo, - const MCSubtargetInfo &STI) const; + std::optional getLitEncoding(const MCOperand &MO, + const MCOperandInfo &OpInfo, + const MCSubtargetInfo &STI) const; public: SIMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) @@ -216,9 +218,10 @@ return 255; } -uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO, - const MCOperandInfo &OpInfo, - const MCSubtargetInfo &STI) const { +std::optional +SIMCCodeEmitter::getLitEncoding(const MCOperand &MO, + const MCOperandInfo &OpInfo, + const MCSubtargetInfo &STI) const { int64_t Imm; if (MO.isExpr()) { const auto *C = dyn_cast(MO.getExpr()); @@ -231,7 +234,7 @@ assert(!MO.isDFPImm()); if (!MO.isImm()) - return ~0; + return {}; Imm = MO.getImm(); } @@ -381,7 +384,8 @@ // Is this operand a literal immediate? const MCOperand &Op = MI.getOperand(i); - if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255) + auto Enc = getLitEncoding(Op, Desc.OpInfo[i], STI); + if (!Enc || *Enc != 255) continue; // Yes! Encode it @@ -452,9 +456,9 @@ return; } else { const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); - uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); - if (Enc != ~0U && Enc != 255) { - Op = Enc | SDWA9EncValues::SRC_SGPR_MASK; + auto Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); + if (Enc && *Enc != 255) { + Op = *Enc | SDWA9EncValues::SRC_SGPR_MASK; return; } } @@ -571,9 +575,8 @@ const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); if (AMDGPU::isSISrcOperand(Desc, OpNo)) { - uint32_t Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI); - if (Enc != ~0U) { - Op = Enc; + if (auto Enc = getLitEncoding(MO, Desc.OpInfo[OpNo], STI)) { + Op = *Enc; return; } } else if (MO.isImm()) { diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -919,11 +919,11 @@ Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); } -static EVT memVTFromImageData(Type *Ty, unsigned DMaskLanes) { - assert(DMaskLanes != 0); +static EVT memVTFromLoadIntrData(Type *Ty, unsigned MaxNumLanes) { + assert(MaxNumLanes != 0); if (auto *VT = dyn_cast(Ty)) { - unsigned NumElts = std::min(DMaskLanes, VT->getNumElements()); + unsigned NumElts = std::min(MaxNumLanes, VT->getNumElements()); return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(VT->getElementType()), NumElts); @@ -933,19 +933,15 @@ } // Peek through TFE struct returns to only use the data size. -static EVT memVTFromImageReturn(Type *Ty, unsigned DMaskLanes) { +static EVT memVTFromLoadIntrReturn(Type *Ty, unsigned MaxNumLanes) { auto *ST = dyn_cast(Ty); if (!ST) - return memVTFromImageData(Ty, DMaskLanes); + return memVTFromLoadIntrData(Ty, MaxNumLanes); - // Some intrinsics return an aggregate type - special case to work out the - // correct memVT. - // - // Only limited forms of aggregate type currently expected. - if (ST->getNumContainedTypes() != 2 || - !ST->getContainedType(1)->isIntegerTy(32)) - return EVT(); - return memVTFromImageData(ST->getContainedType(0), DMaskLanes); + // TFE intrinsics return an aggregate type. + assert(ST->getNumContainedTypes() == 2 && + ST->getContainedType(1)->isIntegerTy(32)); + return memVTFromLoadIntrData(ST->getContainedType(0), MaxNumLanes); } bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, @@ -978,7 +974,7 @@ Info.flags |= MachineMemOperand::MODereferenceable; if (ME.onlyReadsMemory()) { - unsigned DMaskLanes = 4; + unsigned MaxNumLanes = 4; if (RsrcIntr->IsImage) { const AMDGPU::ImageDimIntrinsicInfo *Intr @@ -991,12 +987,11 @@ // IR type. Check the dmask for the real number of elements loaded. unsigned DMask = cast(CI.getArgOperand(0))->getZExtValue(); - DMaskLanes = DMask == 0 ? 1 : countPopulation(DMask); + MaxNumLanes = DMask == 0 ? 1 : countPopulation(DMask); } + } - Info.memVT = memVTFromImageReturn(CI.getType(), DMaskLanes); - } else - Info.memVT = EVT::getEVT(CI.getType()); + Info.memVT = memVTFromLoadIntrReturn(CI.getType(), MaxNumLanes); // FIXME: What does alignment mean for an image? Info.opc = ISD::INTRINSIC_W_CHAIN; @@ -1008,7 +1003,7 @@ if (RsrcIntr->IsImage) { unsigned DMask = cast(CI.getArgOperand(1))->getZExtValue(); unsigned DMaskLanes = DMask == 0 ? 1 : countPopulation(DMask); - Info.memVT = memVTFromImageData(DataTy, DMaskLanes); + Info.memVT = memVTFromLoadIntrData(DataTy, DMaskLanes); } else Info.memVT = EVT::getEVT(DataTy); @@ -4854,8 +4849,18 @@ bool IsD16 = IsFormat && (EltType.getSizeInBits() == 16); - unsigned Opc = - IsFormat ? AMDGPUISD::BUFFER_LOAD_FORMAT : AMDGPUISD::BUFFER_LOAD; + assert(M->getNumValues() == 2 || M->getNumValues() == 3); + bool IsTFE = M->getNumValues() == 3; + + unsigned Opc; + if (IsFormat) { + Opc = IsTFE ? AMDGPUISD::BUFFER_LOAD_FORMAT_TFE + : AMDGPUISD::BUFFER_LOAD_FORMAT; + } else { + // TODO: Support non-format TFE loads. + assert(!IsTFE); + Opc = AMDGPUISD::BUFFER_LOAD; + } if (IsD16) { return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16, M, DAG, Ops); @@ -6003,10 +6008,23 @@ bool SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { // We can fold offsets for anything that doesn't require a GOT relocation. - return (GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS || - GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS || - GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS_32BIT) && - !shouldEmitGOTReloc(GA->getGlobal()); + auto const AS = GA->getAddressSpace(); + if (AS == AMDGPUAS::GLOBAL_ADDRESS) return true; + if (AS == AMDGPUAS::CONSTANT_ADDRESS) return true; + if ((AS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) && + !shouldEmitGOTReloc(GA->getGlobal())) return true; + + // Some LDS variables have compile time known addresses + if (AS == AMDGPUAS::LOCAL_ADDRESS) { + if (const GlobalVariable *GV = + dyn_cast(GA->getGlobal())) { + if (AMDGPUMachineFunction::isKnownAddressLDSGlobal(*GV)) { + return true; + } + } + } + + return false; } static SDValue @@ -7850,35 +7868,54 @@ } // Call DAG.getMemIntrinsicNode for a load, but first widen a dwordx3 type to -// dwordx4 if on SI. +// dwordx4 if on SI and handle TFE loads. SDValue SITargetLowering::getMemIntrinsicNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, ArrayRef Ops, EVT MemVT, MachineMemOperand *MMO, SelectionDAG &DAG) const { + LLVMContext &C = *DAG.getContext(); + MachineFunction &MF = DAG.getMachineFunction(); EVT VT = VTList.VTs[0]; - EVT WidenedVT = VT; - EVT WidenedMemVT = MemVT; - if (!Subtarget->hasDwordx3LoadStores() && - (WidenedVT == MVT::v3i32 || WidenedVT == MVT::v3f32)) { - WidenedVT = EVT::getVectorVT(*DAG.getContext(), - WidenedVT.getVectorElementType(), 4); - WidenedMemVT = EVT::getVectorVT(*DAG.getContext(), - WidenedMemVT.getVectorElementType(), 4); - MMO = DAG.getMachineFunction().getMachineMemOperand(MMO, 0, 16); - } - - assert(VTList.NumVTs == 2); - SDVTList WidenedVTList = DAG.getVTList(WidenedVT, VTList.VTs[1]); - auto NewOp = DAG.getMemIntrinsicNode(Opcode, DL, WidenedVTList, Ops, - WidenedMemVT, MMO); - if (WidenedVT != VT) { - auto Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, NewOp, - DAG.getVectorIdxConstant(0, DL)); - NewOp = DAG.getMergeValues({ Extract, SDValue(NewOp.getNode(), 1) }, DL); + assert(VTList.NumVTs == 2 || VTList.NumVTs == 3); + bool IsTFE = VTList.NumVTs == 3; + if (IsTFE) { + unsigned NumValueDWords = divideCeil(VT.getSizeInBits(), 32); + unsigned NumOpDWords = NumValueDWords + 1; + EVT OpDWordsVT = EVT::getVectorVT(C, MVT::i32, NumOpDWords); + SDVTList OpDWordsVTList = DAG.getVTList(OpDWordsVT, VTList.VTs[2]); + MachineMemOperand *OpDWordsMMO = + MF.getMachineMemOperand(MMO, 0, NumOpDWords * 4); + SDValue Op = getMemIntrinsicNode(Opcode, DL, OpDWordsVTList, Ops, + OpDWordsVT, OpDWordsMMO, DAG); + SDValue Status = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Op, + DAG.getVectorIdxConstant(NumValueDWords, DL)); + SDValue ZeroIdx = DAG.getVectorIdxConstant(0, DL); + SDValue ValueDWords = + NumValueDWords == 1 + ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Op, ZeroIdx) + : DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, + EVT::getVectorVT(C, MVT::i32, NumValueDWords), Op, + ZeroIdx); + SDValue Value = DAG.getNode(ISD::BITCAST, DL, VT, ValueDWords); + return DAG.getMergeValues({Value, Status, SDValue(Op.getNode(), 1)}, DL); } - return NewOp; + + if (!Subtarget->hasDwordx3LoadStores() && + (VT == MVT::v3i32 || VT == MVT::v3f32)) { + EVT WidenedVT = EVT::getVectorVT(C, VT.getVectorElementType(), 4); + EVT WidenedMemVT = EVT::getVectorVT(C, MemVT.getVectorElementType(), 4); + MachineMemOperand *WidenedMMO = MF.getMachineMemOperand(MMO, 0, 16); + SDVTList WidenedVTList = DAG.getVTList(WidenedVT, VTList.VTs[1]); + SDValue Op = DAG.getMemIntrinsicNode(Opcode, DL, WidenedVTList, Ops, + WidenedMemVT, WidenedMMO); + SDValue Value = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Op, + DAG.getVectorIdxConstant(0, DL)); + return DAG.getMergeValues({Value, SDValue(Op.getNode(), 1)}, DL); + } + + return DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops, MemVT, MMO); } SDValue SITargetLowering::handleD16VData(SDValue VData, SelectionDAG &DAG, diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -135,6 +135,8 @@ [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>; def SIbuffer_load_format : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT", SDTBufferLoad, [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>; +def SIbuffer_load_format_tfe : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT_TFE", SDTBufferLoad, + [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>; def SIbuffer_load_format_d16 : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT_D16", SDTBufferLoad, [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>; @@ -1149,7 +1151,7 @@ class NamedMatchClass : AsmOperandClass { let Name = "Imm"#CName; let PredicateMethod = "is"#CName; - let ParserMethod = !if(Optional, "parseOptionalOperand", "parse"#CName); + let ParserMethod = !if(Optional, "", "parse"#CName); let RenderMethod = "addImmOperands"; let IsOptional = Optional; let DefaultMethod = !if(Optional, "default"#CName, ?); @@ -1207,10 +1209,6 @@ let OperandType = "OPERAND_IMMEDIATE" in { -def offen : NamedOperandBit<"Offen", NamedMatchClass<"Offen">>; -def idxen : NamedOperandBit<"Idxen", NamedMatchClass<"Idxen">>; -def addr64 : NamedOperandBit<"Addr64", NamedMatchClass<"Addr64">>; - def flat_offset : NamedOperandU16<"FlatOffset", NamedMatchClass<"FlatOffset">>; def offset : NamedOperandU16<"Offset", NamedMatchClass<"Offset">>; def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>; diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -3233,6 +3233,7 @@ def G_AMDGPU_BUFFER_LOAD_SSHORT : BufferLoadGenericInstruction; def G_AMDGPU_BUFFER_LOAD : BufferLoadGenericInstruction; def G_AMDGPU_BUFFER_LOAD_FORMAT : BufferLoadGenericInstruction; +def G_AMDGPU_BUFFER_LOAD_FORMAT_TFE : BufferLoadGenericInstruction; def G_AMDGPU_BUFFER_LOAD_FORMAT_D16 : BufferLoadGenericInstruction; def G_AMDGPU_TBUFFER_LOAD_FORMAT : TBufferLoadGenericInstruction; def G_AMDGPU_TBUFFER_LOAD_FORMAT_D16 : TBufferLoadGenericInstruction; diff --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp --- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp +++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp @@ -25,6 +25,7 @@ #include "llvm/ADT/MapVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include using namespace llvm; @@ -691,7 +692,8 @@ // to SDWA preserve dst:v4 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE preserve:v3 // Check if one of operands of v_or_b32 is SDWA instruction - using CheckRetType = Optional>; + using CheckRetType = + std::optional>; auto CheckOROperandsForSDWA = [&](const MachineOperand *Op1, const MachineOperand *Op2) -> CheckRetType { if (!Op1 || !Op1->isReg() || !Op2 || !Op2->isReg()) diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -1388,7 +1388,9 @@ let SubtargetPredicate = isGFX11Plus in { def S_WAIT_EVENT : SOPP_Pseudo<"s_wait_event", (ins s16imm:$simm16), - "$simm16">; + "$simm16"> { + let hasSideEffects = 1; + } def S_DELAY_ALU : SOPP_Pseudo<"s_delay_alu", (ins DELAY_FLAG:$simm16), "$simm16">; } // End SubtargetPredicate = isGFX11Plus @@ -1430,6 +1432,10 @@ (S_SEXT_I32_I16 $src) >; +def : GCNPat < + (int_amdgcn_s_wait_event_export_ready), + (S_WAIT_EVENT (i16 0)) +>; //===----------------------------------------------------------------------===// // SOP2 Patterns diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -23,6 +23,7 @@ #include "llvm/Support/AMDHSAKernelDescriptor.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/TargetParser.h" +#include #define GET_INSTRINFO_NAMED_OPS #define GET_INSTRMAP_INFO @@ -583,8 +584,8 @@ // absence of the target features we assume we must generate code that can run // in any environment. SubtargetFeatures Features(FS); - Optional XnackRequested; - Optional SramEccRequested; + std::optional XnackRequested; + std::optional SramEccRequested; for (const std::string &Feature : Features.getFeatures()) { if (Feature == "+xnack") diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -1791,7 +1791,7 @@ // FIXME: Ideally we could vary the LDRB index based on the padding // between the sequence and jump table, however that relies on MCExprs // for load indexes which are currently not supported. - OutStreamer->emitCodeAlignment(4, &getSubtargetInfo()); + OutStreamer->emitCodeAlignment(Align(4), &getSubtargetInfo()); EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr) .addReg(Idx) .addReg(Idx) diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -35,6 +35,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetOptions.h" +#include using namespace llvm; @@ -3530,7 +3531,7 @@ CurDAG->RemoveDeadNode(N); } -static Optional> +static std::optional> getContiguousRangeOfSetBits(const APInt &A) { unsigned FirstOne = A.getBitWidth() - A.countLeadingZeros() - 1; unsigned LastOne = A.countTrailingZeros(); diff --git a/llvm/lib/Target/ARM/ARMMCInstLower.cpp b/llvm/lib/Target/ARM/ARMMCInstLower.cpp --- a/llvm/lib/Target/ARM/ARMMCInstLower.cpp +++ b/llvm/lib/Target/ARM/ARMMCInstLower.cpp @@ -194,7 +194,7 @@ // BLX ip // POP{ r0, lr } // - OutStreamer->emitCodeAlignment(4, &getSubtargetInfo()); + OutStreamer->emitCodeAlignment(Align(4), &getSubtargetInfo()); auto CurSled = OutContext.createTempSymbol("xray_sled_", true); OutStreamer->emitLabel(CurSled); auto Target = OutContext.createTempSymbol(); diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -11856,9 +11856,9 @@ assert(Section && "must have section to emit alignment"); if (Section->useCodeAlign()) - getStreamer().emitCodeAlignment(2, &getSTI()); + getStreamer().emitCodeAlignment(Align(2), &getSTI()); else - getStreamer().emitValueToAlignment(2); + getStreamer().emitValueToAlignment(Align(2)); return false; } @@ -12054,9 +12054,9 @@ const MCSection *Section = getStreamer().getCurrentSectionOnly(); assert(Section && "must have section to emit alignment"); if (Section->useCodeAlign()) - getStreamer().emitCodeAlignment(4, &getSTI(), 0); + getStreamer().emitCodeAlignment(Align(4), &getSTI(), 0); else - getStreamer().emitValueToAlignment(4, 0, 1, 0); + getStreamer().emitValueToAlignment(Align(4), 0, 1, 0); return false; } return true; diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -1169,7 +1169,7 @@ // Switch to .ARM.extab or .ARM.exidx section switchSection(EHSection); - emitValueToAlignment(4, 0, 1, 0); + emitValueToAlignment(Align(4), 0, 1, 0); } inline void ARMELFStreamer::SwitchToExTabSection(const MCSymbol &FnStart) { diff --git a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp --- a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp @@ -20,7 +20,6 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/CodeGen/TargetRegisterInfo.h" using namespace llvm; @@ -104,9 +103,6 @@ // Common implementation of LPMWRdZ and ELPMWRdZ. bool expandLPMWELPMW(Block &MBB, BlockIt MBBI, bool IsExt); - - /// Scavenges a free GPR8 register for use. - Register scavengeGPR8(MachineInstr &MI); }; char AVRExpandPseudo::ID = 0; @@ -131,9 +127,6 @@ TRI = STI.getRegisterInfo(); TII = STI.getInstrInfo(); - // We need to track liveness in order to use register scavenging. - MF.getProperties().set(MachineFunctionProperties::Property::TracksLiveness); - for (Block &MBB : MF) { bool ContinueExpanding = true; unsigned ExpandCount = 0; @@ -783,7 +776,6 @@ MachineInstr &MI = *MBBI; Register DstLoReg, DstHiReg; Register DstReg = MI.getOperand(0).getReg(); - Register TmpReg = 0; // 0 for no temporary register Register SrcReg = MI.getOperand(1).getReg(); bool SrcIsKill = MI.getOperand(1).isKill(); unsigned OpLo = IsExt ? AVR::ELPMRdZPi : AVR::LPMRdZPi; @@ -798,35 +790,19 @@ buildMI(MBB, MBBI, AVR::OUTARr).addImm(STI.getIORegRAMPZ()).addReg(Bank); } - // Use a temporary register if src and dst registers are the same. - if (DstReg == SrcReg) - TmpReg = scavengeGPR8(MI); - - Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg; - Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg; + // This is enforced by the @earlyclobber constraint. + assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same"); // Load low byte. auto MIBLO = buildMI(MBB, MBBI, OpLo) - .addReg(CurDstLoReg, RegState::Define) + .addReg(DstLoReg, RegState::Define) .addReg(SrcReg); - // Push low byte onto stack if necessary. - if (TmpReg) - buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg); - // Load high byte. auto MIBHI = buildMI(MBB, MBBI, OpHi) - .addReg(CurDstHiReg, RegState::Define) + .addReg(DstHiReg, RegState::Define) .addReg(SrcReg, getKillRegState(SrcIsKill)); - if (TmpReg) { - // Move the high byte into the final destination. - buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg); - - // Move the low byte from the scratch space into the final destination. - buildMI(MBB, MBBI, AVR::POPRd, DstLoReg); - } - MIBLO.setMemRefs(MI.memoperands()); MIBHI.setMemRefs(MI.memoperands()); @@ -924,31 +900,6 @@ return expandAtomicBinaryOp(Opcode, MBB, MBBI, [](MachineInstr &MI) {}); } -Register AVRExpandPseudo::scavengeGPR8(MachineInstr &MI) { - MachineBasicBlock &MBB = *MI.getParent(); - RegScavenger RS; - - RS.enterBasicBlock(MBB); - RS.forward(MI); - - BitVector Candidates = - TRI->getAllocatableSet(*MBB.getParent(), &AVR::GPR8RegClass); - - // Exclude all the registers being used by the instruction. - for (MachineOperand &MO : MI.operands()) { - if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() && - !Register::isVirtualRegister(MO.getReg())) - Candidates.reset(MO.getReg()); - } - - BitVector Available = RS.getRegsAvailable(&AVR::GPR8RegClass); - Available &= Candidates; - - signed Reg = Available.find_first(); - assert(Reg != -1 && "ran out of registers"); - return Reg; -} - template <> bool AVRExpandPseudo::expand(Block &MBB, BlockIt MBBI) { return expandAtomicBinaryOp(AVR::LDRdPtr, MBB, MBBI); diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp --- a/llvm/lib/Target/AVR/AVRISelLowering.cpp +++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp @@ -1582,7 +1582,7 @@ } unsigned TotalBytes = getTotalArgumentsSizeInBytes(Outs); - return TotalBytes <= (Subtarget.hasTinyEncoding() ? 4 : 8); + return TotalBytes <= (unsigned)(Subtarget.hasTinyEncoding() ? 4 : 8); } SDValue diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td --- a/llvm/lib/Target/AVR/AVRInstrInfo.td +++ b/llvm/lib/Target/AVR/AVRInstrInfo.td @@ -1673,6 +1673,7 @@ "lpm\t$rd, $z+", []>, Requires<[HasLPMX]>; + let Constraints = "@earlyclobber $dst" in def LPMWRdZ : Pseudo<(outs DREGS : $dst), (ins ZREG @@ -1712,6 +1713,7 @@ "elpmb\t$dst, $z, $p", []>, Requires<[HasELPMX]>; + let Constraints = "@earlyclobber $dst" in def ELPMWRdZ : Pseudo<(outs DREGS:$dst), (ins ZREG:$z, LD8:$p), "elpmw\t$dst, $z, $p", []>, Requires<[HasELPMX]>; diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp --- a/llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp +++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp @@ -20,6 +20,7 @@ CodePointerSize = 2; CalleeSaveStackSlotSize = 2; CommentString = ";"; + SeparatorString = "$"; PrivateGlobalPrefix = ".L"; PrivateLabelPrefix = ".L"; UsesELFSectionDirectiveForBSS = true; diff --git a/llvm/lib/Target/BPF/BPFIRPeephole.cpp b/llvm/lib/Target/BPF/BPFIRPeephole.cpp --- a/llvm/lib/Target/BPF/BPFIRPeephole.cpp +++ b/llvm/lib/Target/BPF/BPFIRPeephole.cpp @@ -14,6 +14,7 @@ #include "BPF.h" #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/Module.h" #include "llvm/IR/PassManager.h" #include "llvm/IR/Type.h" @@ -56,37 +57,32 @@ ToErase = nullptr; } - if (auto *Call = dyn_cast(&I)) { - if (auto *GV = dyn_cast(Call->getCalledOperand())) { - if (!GV->getName().equals("llvm.stacksave")) - continue; - if (!Call->hasOneUser()) - continue; - auto *Inst = cast(*Call->user_begin()); - LLVM_DEBUG(dbgs() << "Remove:"; I.dump()); - LLVM_DEBUG(dbgs() << "Remove:"; Inst->dump(); dbgs() << '\n'); - Changed = true; - Inst->eraseFromParent(); - ToErase = &I; - } + if (auto *II = dyn_cast(&I)) { + if (II->getIntrinsicID() != Intrinsic::stacksave) + continue; + if (!II->hasOneUser()) + continue; + auto *Inst = cast(*II->user_begin()); + LLVM_DEBUG(dbgs() << "Remove:"; I.dump()); + LLVM_DEBUG(dbgs() << "Remove:"; Inst->dump(); dbgs() << '\n'); + Changed = true; + Inst->eraseFromParent(); + ToErase = &I; continue; } if (auto *LD = dyn_cast(&I)) { if (!LD->hasOneUser()) continue; - auto *Call = dyn_cast(*LD->user_begin()); - if (!Call) - continue; - auto *GV = dyn_cast(Call->getCalledOperand()); - if (!GV) + auto *II = dyn_cast(*LD->user_begin()); + if (!II) continue; - if (!GV->getName().equals("llvm.stackrestore")) + if (II->getIntrinsicID() != Intrinsic::stackrestore) continue; LLVM_DEBUG(dbgs() << "Remove:"; I.dump()); - LLVM_DEBUG(dbgs() << "Remove:"; Call->dump(); dbgs() << '\n'); + LLVM_DEBUG(dbgs() << "Remove:"; II->dump(); dbgs() << '\n'); Changed = true; - Call->eraseFromParent(); + II->eraseFromParent(); ToErase = &I; } } diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.h b/llvm/lib/Target/BPF/BPFTargetMachine.h --- a/llvm/lib/Target/BPF/BPFTargetMachine.h +++ b/llvm/lib/Target/BPF/BPFTargetMachine.h @@ -40,7 +40,6 @@ return TLOF.get(); } - void adjustPassManager(PassManagerBuilder &) override; void registerPassBuilderCallbacks(PassBuilder &PB) override; }; } diff --git a/llvm/lib/Target/BPF/BPFTargetMachine.cpp b/llvm/lib/Target/BPF/BPFTargetMachine.cpp --- a/llvm/lib/Target/BPF/BPFTargetMachine.cpp +++ b/llvm/lib/Target/BPF/BPFTargetMachine.cpp @@ -24,7 +24,6 @@ #include "llvm/Passes/PassBuilder.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Transforms/IPO/PassManagerBuilder.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar/SimplifyCFG.h" #include "llvm/Transforms/Utils/SimplifyCFGOptions.h" @@ -102,28 +101,6 @@ return new BPFPassConfig(*this, PM); } -void BPFTargetMachine::adjustPassManager(PassManagerBuilder &Builder) { - Builder.addExtension( - PassManagerBuilder::EP_EarlyAsPossible, - [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) { - PM.add(createBPFAbstractMemberAccess(this)); - PM.add(createBPFPreserveDIType()); - PM.add(createBPFIRPeephole()); - }); - - Builder.addExtension( - PassManagerBuilder::EP_Peephole, - [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) { - PM.add(createCFGSimplificationPass( - SimplifyCFGOptions().hoistCommonInsts(true))); - }); - Builder.addExtension( - PassManagerBuilder::EP_ModuleOptimizerEarly, - [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) { - PM.add(createBPFAdjustOpt()); - }); -} - void BPFTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { PB.registerPipelineStartEPCallback( [=](ModulePassManager &MPM, OptimizationLevel) { diff --git a/llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp b/llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp --- a/llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp +++ b/llvm/lib/Target/CSKY/CSKYAsmPrinter.cpp @@ -105,7 +105,7 @@ // If this is the first entry of the pool, mark it. if (!InConstantPool) { - OutStreamer->emitValueToAlignment(4); + OutStreamer->emitValueToAlignment(Align(4)); InConstantPool = true; } diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.cpp --- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.cpp +++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYTargetStreamer.cpp @@ -30,7 +30,7 @@ Streamer.emitDataRegion(MCDR_DataRegion); for (const ConstantPoolEntry &Entry : Entries) { Streamer.emitCodeAlignment( - Entry.Size, + Align(Entry.Size), Streamer.getContext().getSubtargetInfo()); // align naturally Streamer.emitLabel(Entry.Label); Streamer.emitValue(Entry.Value, Entry.Size, Entry.Loc); diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp --- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp +++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp @@ -1495,7 +1495,7 @@ MES->switchSection(mySection); unsigned byteSize = is32bit ? 4 : 8; - getStreamer().emitCodeAlignment(byteSize, &getSTI(), byteSize); + getStreamer().emitCodeAlignment(Align(byteSize), &getSTI(), byteSize); MCSymbol *Sym; diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp --- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp +++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp @@ -807,7 +807,7 @@ static DecodeStatus DecodeSysRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const MCDisassembler *Decoder) { - if (RegNo >= sizeof(SysRegDecoderTable) / sizeof(SysRegDecoderTable[0])) + if (RegNo >= std::size(SysRegDecoderTable)) return MCDisassembler::Fail; if (SysRegDecoderTable[RegNo] == Hexagon::NoRegister) @@ -835,7 +835,7 @@ DecodeSysRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const MCDisassembler *Decoder) { RegNo = RegNo >> 1; - if (RegNo >= sizeof(SysReg64DecoderTable) / sizeof(SysReg64DecoderTable[0])) + if (RegNo >= std::size(SysReg64DecoderTable)) return MCDisassembler::Fail; if (SysReg64DecoderTable[RegNo] == Hexagon::NoRegister) diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp --- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -209,7 +209,7 @@ OutStreamer.emitLabel(Sym); OutStreamer.emitSymbolAttribute(Sym, MCSA_Global); OutStreamer.emitIntValue(Value, AlignSize); - OutStreamer.emitCodeAlignment(AlignSize, &STI); + OutStreamer.emitCodeAlignment(Align(AlignSize), &STI); } } else { assert(Imm.isExpr() && "Expected expression and found none"); @@ -237,7 +237,7 @@ OutStreamer.emitLabel(Sym); OutStreamer.emitSymbolAttribute(Sym, MCSA_Local); OutStreamer.emitValue(Imm.getExpr(), AlignSize); - OutStreamer.emitCodeAlignment(AlignSize, &STI); + OutStreamer.emitCodeAlignment(Align(AlignSize), &STI); } } return Sym; diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -60,6 +60,7 @@ #include #include #include +#include #include #include @@ -989,7 +990,7 @@ return ReachedExit; } -static Optional +static std::optional findCFILocation(MachineBasicBlock &B) { // The CFI instructions need to be inserted right after allocframe. // An exception to this is a situation where allocframe is bundled diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h @@ -97,6 +97,7 @@ void SelectSHL(SDNode *N); void SelectIntrinsicWChain(SDNode *N); void SelectIntrinsicWOChain(SDNode *N); + void SelectExtractSubvector(SDNode *N); void SelectConstant(SDNode *N); void SelectConstantFP(SDNode *N); void SelectV65Gather(SDNode *N); @@ -126,6 +127,7 @@ return SDValue(U, 0); } + void SelectHvxExtractSubvector(SDNode *N); void SelectHvxShuffle(SDNode *N); void SelectHvxRor(SDNode *N); void SelectHvxVAlign(SDNode *N); diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -692,6 +692,25 @@ SelectCode(N); } +void HexagonDAGToDAGISel::SelectExtractSubvector(SDNode *N) { + SDValue Inp = N->getOperand(0); + MVT ResTy = N->getValueType(0).getSimpleVT(); + auto IdxN = cast(N->getOperand(1)); + unsigned Idx = IdxN->getZExtValue(); +#ifndef NDEBUG + MVT InpTy = Inp.getValueType().getSimpleVT(); + assert(InpTy.getVectorElementType() == ResTy.getVectorElementType()); + unsigned ResLen = ResTy.getVectorNumElements(); + assert(2 * ResLen == InpTy.getVectorNumElements()); + assert(ResTy.getSizeInBits() == 32); + assert(Idx == 0 || Idx == ResLen); +#endif + unsigned SubReg = Idx == 0 ? Hexagon::isub_lo : Hexagon::isub_hi; + SDValue Ext = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(N), ResTy, Inp); + + ReplaceNode(N, Ext.getNode()); +} + // // Map floating point constant values. // @@ -884,6 +903,28 @@ if (N->isMachineOpcode()) return N->setNodeId(-1); // Already selected. + auto isHvxOp = [this](SDNode *N) { + auto &HST = MF->getSubtarget(); + for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { + if (HST.isHVXVectorType(N->getValueType(i), true)) + return true; + } + for (SDValue I : N->ops()) { + if (HST.isHVXVectorType(I.getValueType(), true)) + return true; + } + return false; + }; + + if (HST->useHVXOps() && isHvxOp(N)) { + switch (N->getOpcode()) { + case ISD::EXTRACT_SUBVECTOR: return SelectHvxExtractSubvector(N); + case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N); + + case HexagonISD::VROR: return SelectHvxRor(N); + } + } + switch (N->getOpcode()) { case ISD::Constant: return SelectConstant(N); case ISD::ConstantFP: return SelectConstantFP(N); @@ -893,6 +934,7 @@ case ISD::STORE: return SelectStore(N); case ISD::INTRINSIC_W_CHAIN: return SelectIntrinsicWChain(N); case ISD::INTRINSIC_WO_CHAIN: return SelectIntrinsicWOChain(N); + case ISD::EXTRACT_SUBVECTOR: return SelectExtractSubvector(N); case HexagonISD::ADDC: case HexagonISD::SUBC: return SelectAddSubCarry(N); @@ -905,13 +947,6 @@ case HexagonISD::V2Q: return SelectV2Q(N); } - if (HST->useHVXOps()) { - switch (N->getOpcode()) { - case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N); - case HexagonISD::VROR: return SelectHvxRor(N); - } - } - SelectCode(N); } diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp @@ -833,6 +833,7 @@ return MVT::getVectorVT(MVT::i1, HwLen); } + void selectExtractSubvector(SDNode *N); void selectShuffle(SDNode *N); void selectRor(SDNode *N); void selectVAlign(SDNode *N); @@ -2281,6 +2282,24 @@ return DAG.getNode(HexagonISD::ISEL, dl, VecTy, LV); } +void HvxSelector::selectExtractSubvector(SDNode *N) { + SDValue Inp = N->getOperand(0); + MVT ResTy = N->getValueType(0).getSimpleVT(); + auto IdxN = cast(N->getOperand(1)); + unsigned Idx = IdxN->getZExtValue(); +#ifndef NDEBUG + MVT InpTy = Inp.getValueType().getSimpleVT(); + assert(InpTy.getVectorElementType() == ResTy.getVectorElementType()); + unsigned ResLen = ResTy.getVectorNumElements(); + assert(2 * ResLen == InpTy.getVectorNumElements()); + assert(Idx == 0 || Idx == ResLen); +#endif + unsigned SubReg = Idx == 0 ? Hexagon::vsub_lo : Hexagon::vsub_hi; + SDValue Ext = DAG.getTargetExtractSubreg(SubReg, SDLoc(N), ResTy, Inp); + + ISel.ReplaceNode(N, Ext.getNode()); +} + void HvxSelector::selectShuffle(SDNode *N) { DEBUG_WITH_TYPE("isel", { dbgs() << "Starting " << __func__ << " on node:\n"; @@ -2390,6 +2409,10 @@ DAG.RemoveDeadNode(N); } +void HexagonDAGToDAGISel::SelectHvxExtractSubvector(SDNode *N) { + HvxSelector(*this, *CurDAG).selectExtractSubvector(N); +} + void HexagonDAGToDAGISel::SelectHvxShuffle(SDNode *N) { HvxSelector(*this, *CurDAG).selectShuffle(N); } diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.h b/llvm/lib/Target/Hexagon/HexagonISelLowering.h --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -447,6 +447,29 @@ VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const; SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const; + SDValue LoHalf(SDValue V, SelectionDAG &DAG) const { + MVT Ty = ty(V); + const SDLoc &dl(V); + if (!Ty.isVector()) { + assert(Ty.getSizeInBits() == 64); + return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, V); + } + MVT HalfTy = typeSplit(Ty).first; + SDValue Idx = getZero(dl, MVT::i32, DAG); + return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx); + } + SDValue HiHalf(SDValue V, SelectionDAG &DAG) const { + MVT Ty = ty(V); + const SDLoc &dl(V); + if (!Ty.isVector()) { + assert(Ty.getSizeInBits() == 64); + return DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, V); + } + MVT HalfTy = typeSplit(Ty).first; + SDValue Idx = DAG.getConstant(HalfTy.getVectorNumElements(), dl, MVT::i32); + return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfTy, V, Idx); + } + bool allowsHvxMemoryAccess(MVT VecTy, MachineMemOperand::Flags Flags, unsigned *Fast) const; bool allowsHvxMisalignedMemoryAccesses(MVT VecTy, @@ -478,8 +501,9 @@ const SDLoc &dl, SelectionDAG &DAG) const; SDValue insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV, const SDLoc &dl, SelectionDAG &DAG) const; - SDValue extractHvxSubvectorReg(SDValue VecV, SDValue IdxV, const SDLoc &dl, - MVT ResTy, SelectionDAG &DAG) const; + SDValue extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV, SDValue IdxV, + const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) + const; SDValue extractHvxSubvectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const; SDValue insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV, diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp --- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -2661,8 +2661,7 @@ unsigned Off = IdxN->getZExtValue() * ElemWidth; if (VecWidth == 64 && ValWidth == 32) { assert(Off == 0 || Off == 32); - unsigned SubIdx = Off == 0 ? Hexagon::isub_lo : Hexagon::isub_hi; - ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV); + ExtV = Off == 0 ? LoHalf(VecV, DAG) : HiHalf(VecV, DAG); } else if (Off == 0 && (ValWidth % 8) == 0) { ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy)); } else { @@ -2734,7 +2733,7 @@ while (Scale > 1) { // The longest possible subvector is at most 32 bits, so it is always // contained in the low subregister. - T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1); + T1 = LoHalf(T1, DAG); T1 = expandPredicate(T1, dl, DAG); Scale /= 2; } @@ -2994,7 +2993,7 @@ W = contractPredicate(W, dl, DAG); W = getCombine(DAG.getUNDEF(MVT::i32), W, dl, MVT::i64, DAG); } - W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W); + W = LoHalf(W, DAG); Words[IdxW].push_back(W); } diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp --- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp +++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp @@ -909,9 +909,7 @@ SDValue S = DAG.getVectorShuffle(ExtTy, dl, ExtVec, DAG.getUNDEF(ExtTy), Mask); - if (ExtLen == VecLen) - return S; - return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, VecTy, S); + return ExtLen == VecLen ? S : LoHalf(S, DAG); } } @@ -1033,18 +1031,11 @@ SmallVector Words[2]; unsigned IdxW = 0; - auto Lo32 = [&DAG, &dl] (SDValue P) { - return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, P); - }; - auto Hi32 = [&DAG, &dl] (SDValue P) { - return DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, P); - }; - SDValue W0 = isUndef(PredV) ? DAG.getUNDEF(MVT::i64) : DAG.getNode(HexagonISD::P2D, dl, MVT::i64, PredV); - Words[IdxW].push_back(Hi32(W0)); - Words[IdxW].push_back(Lo32(W0)); + Words[IdxW].push_back(HiHalf(W0, DAG)); + Words[IdxW].push_back(LoHalf(W0, DAG)); while (Bytes < BitBytes) { IdxW ^= 1; @@ -1053,8 +1044,8 @@ if (Bytes < 4) { for (const SDValue &W : Words[IdxW ^ 1]) { SDValue T = expandPredicate(W, dl, DAG); - Words[IdxW].push_back(Hi32(T)); - Words[IdxW].push_back(Lo32(T)); + Words[IdxW].push_back(HiHalf(T, DAG)); + Words[IdxW].push_back(LoHalf(T, DAG)); } } else { for (const SDValue &W : Words[IdxW ^ 1]) { @@ -1255,8 +1246,8 @@ } SDValue -HexagonTargetLowering::extractHvxSubvectorReg(SDValue VecV, SDValue IdxV, - const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const { +HexagonTargetLowering::extractHvxSubvectorReg(SDValue OrigOp, SDValue VecV, + SDValue IdxV, const SDLoc &dl, MVT ResTy, SelectionDAG &DAG) const { MVT VecTy = ty(VecV); unsigned HwLen = Subtarget.getVectorLength(); unsigned Idx = cast(IdxV.getNode())->getZExtValue(); @@ -1267,16 +1258,11 @@ // the subvector of interest. The subvector will never overlap two single // vectors. if (isHvxPairTy(VecTy)) { - unsigned SubIdx; - if (Idx * ElemWidth >= 8*HwLen) { - SubIdx = Hexagon::vsub_hi; + if (Idx * ElemWidth >= 8*HwLen) Idx -= VecTy.getVectorNumElements() / 2; - } else { - SubIdx = Hexagon::vsub_lo; - } - VecTy = typeSplit(VecTy).first; - VecV = DAG.getTargetExtractSubreg(SubIdx, dl, VecTy, VecV); - if (VecTy == ResTy) + + VecV = OrigOp; + if (typeSplit(VecTy).first == ResTy) return VecV; } @@ -1380,8 +1366,8 @@ SDValue PickHi; if (IsPair) { - V0 = DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, SingleTy, VecV); - V1 = DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, SingleTy, VecV); + V0 = LoHalf(VecV, DAG); + V1 = HiHalf(VecV, DAG); SDValue HalfV = DAG.getConstant(SingleTy.getVectorNumElements(), dl, MVT::i32); @@ -1427,8 +1413,8 @@ SingleV = DAG.getNode(HexagonISD::VINSERTW0, dl, SingleTy, V); } else { SDValue V = DAG.getBitcast(MVT::i64, SubV); - SDValue R0 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, V); - SDValue R1 = DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, V); + SDValue R0 = LoHalf(V, DAG); + SDValue R1 = HiHalf(V, DAG); SingleV = DAG.getNode(HexagonISD::VINSERTW0, dl, SingleTy, SingleV, R0); SingleV = DAG.getNode(HexagonISD::VROR, dl, SingleTy, SingleV, DAG.getConstant(4, dl, MVT::i32)); @@ -1818,7 +1804,7 @@ if (ElemTy == MVT::i1) return extractHvxSubvectorPred(SrcV, IdxV, dl, DstTy, DAG); - return extractHvxSubvectorReg(SrcV, IdxV, dl, DstTy, DAG); + return extractHvxSubvectorReg(Op, SrcV, IdxV, dl, DstTy, DAG); } SDValue @@ -2490,13 +2476,6 @@ SDValue S16 = DAG.getConstant(16, dl, MVT::i32); - auto LoVec = [&DAG, VecTy, dl](SDValue Pair) { - return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, VecTy, Pair); - }; - auto HiVec = [&DAG, VecTy, dl](SDValue Pair) { - return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, VecTy, Pair); - }; - // mulhs(A,B) = // = [(Hi(A)*2^16 + Lo(A)) *s (Hi(B)*2^16 + Lo(B))] >> 32 // = [Hi(A)*2^16 *s Hi(B)*2^16 + Hi(A) *su Lo(B)*2^16 @@ -2524,7 +2503,7 @@ // P0 = interleaved T1.h*B.uh (full precision product) SDValue P0 = getInstr(Hexagon::V6_vmpyhus, dl, PairTy, {T1, B}, DAG); // T2 = T1.even(h) * B.even(uh), i.e. Hi(A)*Lo(B) - SDValue T2 = LoVec(P0); + SDValue T2 = LoHalf(P0, DAG); // We need to add T0+T2, recording the carry-out, which will be 1<<16 // added to the final sum. // P1 = interleaved even/odd 32-bit (unsigned) sums of 16-bit halves @@ -2534,12 +2513,12 @@ // T3 = full-precision(T0+T2) >> 16 // The low halves are added-unsigned, the high ones are added-signed. SDValue T3 = getInstr(Hexagon::V6_vasrw_acc, dl, VecTy, - {HiVec(P2), LoVec(P1), S16}, DAG); + {HiHalf(P2, DAG), LoHalf(P1, DAG), S16}, DAG); SDValue T4 = getInstr(Hexagon::V6_vasrw, dl, VecTy, {B, S16}, DAG); // P3 = interleaved Hi(B)*Hi(A) (full precision), // which is now Lo(T1)*Lo(T4), so we want to keep the even product. SDValue P3 = getInstr(Hexagon::V6_vmpyhv, dl, PairTy, {T1, T4}, DAG); - SDValue T5 = LoVec(P3); + SDValue T5 = LoHalf(P3, DAG); // Add: SDValue T6 = DAG.getNode(ISD::ADD, dl, VecTy, {T3, T5}); return T6; @@ -2555,13 +2534,6 @@ SDValue S16 = DAG.getConstant(16, dl, MVT::i32); - auto LoVec = [&DAG, VecTy, dl](SDValue Pair) { - return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, VecTy, Pair); - }; - auto HiVec = [&DAG, VecTy, dl](SDValue Pair) { - return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, VecTy, Pair); - }; - if (SignedA && !SignedB) { // Make A:unsigned, B:signed. std::swap(A, B); @@ -2588,20 +2560,21 @@ // P2:lo = low halves of P1:lo + P1:hi, // P2:hi = high halves of P1:lo + P1:hi. - SDValue P2 = - getInstr(Hexagon::V6_vadduhw, dl, PairTy, {HiVec(P1), LoVec(P1)}, DAG); + SDValue P2 = getInstr(Hexagon::V6_vadduhw, dl, PairTy, + {HiHalf(P1, DAG), LoHalf(P1, DAG)}, DAG); // Still need to add the high halves of P0:lo to P2:lo - SDValue T2 = getInstr(Hexagon::V6_vlsrw, dl, VecTy, {LoVec(P0), S16}, DAG); - SDValue T3 = DAG.getNode(ISD::ADD, dl, VecTy, {LoVec(P2), T2}); + SDValue T2 = + getInstr(Hexagon::V6_vlsrw, dl, VecTy, {LoHalf(P0, DAG), S16}, DAG); + SDValue T3 = DAG.getNode(ISD::ADD, dl, VecTy, {LoHalf(P2, DAG), T2}); // The high halves of T3 will contribute to the HI part of LOHI. - SDValue T4 = - getInstr(Hexagon::V6_vasrw_acc, dl, VecTy, {HiVec(P2), T3, S16}, DAG); + SDValue T4 = getInstr(Hexagon::V6_vasrw_acc, dl, VecTy, + {HiHalf(P2, DAG), T3, S16}, DAG); // The low halves of P2 need to be added to high halves of the LO part. - Lo = getInstr(Hexagon::V6_vaslw_acc, dl, VecTy, {LoVec(P0), LoVec(P2), S16}, - DAG); - Hi = DAG.getNode(ISD::ADD, dl, VecTy, {HiVec(P0), T4}); + Lo = getInstr(Hexagon::V6_vaslw_acc, dl, VecTy, + {LoHalf(P0, DAG), LoHalf(P2, DAG), S16}, DAG); + Hi = DAG.getNode(ISD::ADD, dl, VecTy, {HiHalf(P0, DAG), T4}); if (SignedA) { assert(SignedB && "Signed A and unsigned B should have been inverted"); @@ -2628,20 +2601,14 @@ } SDValue -HexagonTargetLowering::emitHvxMulLoHiV62(SDValue A, bool SignedA, SDValue B, - bool SignedB, const SDLoc &dl, +HexagonTargetLowering::emitHvxMulLoHiV62(SDValue A, bool SignedA, + SDValue B, bool SignedB, + const SDLoc &dl, SelectionDAG &DAG) const { MVT VecTy = ty(A); MVT PairTy = typeJoin({VecTy, VecTy}); assert(VecTy.getVectorElementType() == MVT::i32); - auto LoVec = [&DAG, VecTy, dl](SDValue Pair) { - return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, VecTy, Pair); - }; - auto HiVec = [&DAG, VecTy, dl](SDValue Pair) { - return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, VecTy, Pair); - }; - if (SignedA && !SignedB) { // Make A:unsigned, B:signed. std::swap(A, B); @@ -2652,8 +2619,8 @@ SDValue P0 = getInstr(Hexagon::V6_vmpyewuh_64, dl, PairTy, {A, B}, DAG); SDValue P1 = getInstr(Hexagon::V6_vmpyowh_64_acc, dl, PairTy, {P0, A, B}, DAG); - SDValue Lo = LoVec(P1); - SDValue Hi = HiVec(P1); + SDValue Lo = LoHalf(P1, DAG); + SDValue Hi = HiHalf(P1, DAG); if (!SignedB) { assert(!SignedA && "Signed A and unsigned B should have been inverted"); @@ -2662,7 +2629,7 @@ // Mulhu(X, Y) = Mulhs(X, Y) + (X, if Y < 0) + (Y, if X < 0). // def: Pat<(VecI32 (mulhu HVI32:$A, HVI32:$B)), - // (V6_vaddw (HiVec (Muls64O $A, $B)), + // (V6_vaddw (HiHalf (Muls64O $A, $B)), // (V6_vaddwq (V6_vgtw (V6_vd0), $B), // (V6_vandvqv (V6_vgtw (V6_vd0), $A), $B), // $A))>; @@ -2678,7 +2645,7 @@ // Mulhus(unsigned X, signed Y) = Mulhs(X, Y) + (Y, if X < 0). // def: Pat<(VecI32 (HexagonMULHUS HVI32:$A, HVI32:$B)), // (V6_vaddwq (V6_vgtw (V6_vd0), $A), - // (HiVec (Muls64O $A, $B)), + // (HiHalf (Muls64O $A, $B)), // $B)>; SDValue Q0 = DAG.getSetCC(dl, PredTy, A, Zero, ISD::SETLT); Hi = getInstr(Hexagon::V6_vaddwq, dl, VecTy, {Q0, Hi, B}, DAG); diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h @@ -36,7 +36,6 @@ static unsigned getModuleMatchQuality(const Module &M); - void adjustPassManager(PassManagerBuilder &PMB) override; void registerPassBuilderCallbacks(PassBuilder &PB) override; TargetPassConfig *createPassConfig(PassManagerBase &PM) override; TargetTransformInfo getTargetTransformInfo(const Function &F) const override; diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -27,7 +27,6 @@ #include "llvm/MC/TargetRegistry.h" #include "llvm/Passes/PassBuilder.h" #include "llvm/Support/CommandLine.h" -#include "llvm/Transforms/IPO/PassManagerBuilder.h" #include "llvm/Transforms/Scalar.h" using namespace llvm; @@ -273,19 +272,6 @@ return I.get(); } -void HexagonTargetMachine::adjustPassManager(PassManagerBuilder &PMB) { - PMB.addExtension( - PassManagerBuilder::EP_LateLoopOptimizations, - [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) { - PM.add(createHexagonLoopIdiomPass()); - }); - PMB.addExtension( - PassManagerBuilder::EP_LoopOptimizerEnd, - [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) { - PM.add(createHexagonVectorLoopCarriedReuseLegacyPass()); - }); -} - void HexagonTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { PB.registerLateLoopOptimizationsEPCallback( [=](LoopPassManager &LPM, OptimizationLevel Level) { diff --git a/llvm/lib/Target/Hexagon/HexagonTargetStreamer.h b/llvm/lib/Target/Hexagon/HexagonTargetStreamer.h --- a/llvm/lib/Target/Hexagon/HexagonTargetStreamer.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetStreamer.h @@ -15,8 +15,7 @@ class HexagonTargetStreamer : public MCTargetStreamer { public: HexagonTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} - virtual void emitCodeAlignment(unsigned ByteAlignment, - const MCSubtargetInfo *STI, + virtual void emitCodeAlignment(Align Alignment, const MCSubtargetInfo *STI, unsigned MaxBytesToEmit = 0){}; virtual void emitFAlign(unsigned Size, unsigned MaxBytesToEmit){}; virtual void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size, diff --git a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp --- a/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp @@ -1576,6 +1576,7 @@ if (X.Sgn == Signed) { V6_vmpyh = HVC.HST.getIntrinsicId(Hexagon::V6_vmpyhv); } else if (Y.Sgn == Signed) { + // In vmpyhus the second operand is unsigned V6_vmpyh = HVC.HST.getIntrinsicId(Hexagon::V6_vmpyhus); } else { V6_vmpyh = HVC.HST.getIntrinsicId(Hexagon::V6_vmpyuhv); @@ -1583,9 +1584,9 @@ // i16*i16 -> i32 / interleaved Value *P = - HVC.createHvxIntrinsic(Builder, V6_vmpyh, HvxP32Ty, {X.Val, Y.Val}); + HVC.createHvxIntrinsic(Builder, V6_vmpyh, HvxP32Ty, {Y.Val, X.Val}); // Deinterleave - return HVC.vdeal(Builder, HVC.sublo(Builder, P), HVC.subhi(Builder, P)); + return HVC.vshuff(Builder, HVC.sublo(Builder, P), HVC.subhi(Builder, P)); } auto HvxIdioms::createMulH16(IRBuilderBase &Builder, SValue X, SValue Y) const diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp @@ -111,14 +111,13 @@ switchSection(&Section); if (ELFSymbol->isUndefined()) { - emitValueToAlignment(ByteAlignment, 0, 1, 0); + emitValueToAlignment(Align(ByteAlignment), 0, 1, 0); emitLabel(Symbol); emitZeros(Size); } // Update the maximum alignment of the section if necessary. - if (Align(ByteAlignment) > Section.getAlignment()) - Section.setAlignment(Align(ByteAlignment)); + Section.ensureMinAlignment(Align(ByteAlignment)); switchSection(P.first, P.second); } else { diff --git a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp --- a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp +++ b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp @@ -35,6 +35,7 @@ #include #include #include +#include using namespace llvm; @@ -693,7 +694,7 @@ LanaiAsmParser::parseRegister(bool RestoreOnFailure) { SMLoc Start = Parser.getTok().getLoc(); SMLoc End = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - Optional PercentTok; + std::optional PercentTok; unsigned RegNum; // Eat the '%'. diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp --- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp @@ -951,8 +951,7 @@ // Assemble multiplication from shift, add, sub using NAF form and running // sum. - for (unsigned int I = 0; I < sizeof(SignedDigit) / sizeof(SignedDigit[0]); - ++I) { + for (unsigned int I = 0; I < std::size(SignedDigit); ++I) { if (SignedDigit[I] == 0) continue; diff --git a/llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp --- a/llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp @@ -147,14 +147,18 @@ Register ScratchReg = MI.getOperand(1).getReg(); Register AddrReg = MI.getOperand(2).getReg(); Register IncrReg = MI.getOperand(3).getReg(); + AtomicOrdering Ordering = + static_cast(MI.getOperand(4).getImm()); // .loop: - // dbar 0 + // if(Ordering != AtomicOrdering::Monotonic) + // dbar 0 // ll.[w|d] dest, (addr) // binop scratch, dest, val // sc.[w|d] scratch, scratch, (addr) // beqz scratch, loop - BuildMI(LoopMBB, DL, TII->get(LoongArch::DBAR)).addImm(0); + if (Ordering != AtomicOrdering::Monotonic) + BuildMI(LoopMBB, DL, TII->get(LoongArch::DBAR)).addImm(0); BuildMI(LoopMBB, DL, TII->get(Width == 32 ? LoongArch::LL_W : LoongArch::LL_D), DestReg) .addReg(AddrReg) @@ -241,9 +245,12 @@ Register AddrReg = MI.getOperand(2).getReg(); Register IncrReg = MI.getOperand(3).getReg(); Register MaskReg = MI.getOperand(4).getReg(); + AtomicOrdering Ordering = + static_cast(MI.getOperand(5).getImm()); // .loop: - // dbar 0 + // if(Ordering != AtomicOrdering::Monotonic) + // dbar 0 // ll.w destreg, (alignedaddr) // binop scratch, destreg, incr // xor scratch, destreg, scratch @@ -251,7 +258,8 @@ // xor scratch, destreg, scratch // sc.w scratch, scratch, (alignedaddr) // beqz scratch, loop - BuildMI(LoopMBB, DL, TII->get(LoongArch::DBAR)).addImm(0); + if (Ordering != AtomicOrdering::Monotonic) + BuildMI(LoopMBB, DL, TII->get(LoongArch::DBAR)).addImm(0); BuildMI(LoopMBB, DL, TII->get(LoongArch::LL_W), DestReg) .addReg(AddrReg) .addImm(0); diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h @@ -192,6 +192,7 @@ SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) const; bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override; diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -93,6 +93,8 @@ setOperationAction(ISD::CTLZ, MVT::i32, Custom); setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom); setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i32, Custom); + setOperationAction(ISD::READ_REGISTER, MVT::i32, Custom); + setOperationAction(ISD::WRITE_REGISTER, MVT::i32, Custom); if (Subtarget.hasBasicF() && !Subtarget.hasBasicD()) setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); if (Subtarget.hasBasicF()) @@ -118,6 +120,8 @@ } else { setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); + setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom); + setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom); } static const ISD::CondCode FPCCToExpand[] = { @@ -244,10 +248,30 @@ return lowerFRAMEADDR(Op, DAG); case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); + case ISD::WRITE_REGISTER: + return lowerWRITE_REGISTER(Op, DAG); } return SDValue(); } +SDValue LoongArchTargetLowering::lowerWRITE_REGISTER(SDValue Op, + SelectionDAG &DAG) const { + + if (Subtarget.is64Bit() && Op.getOperand(2).getValueType() == MVT::i32) { + DAG.getContext()->emitError( + "On LA64, only 64-bit registers can be written."); + return Op.getOperand(0); + } + + if (!Subtarget.is64Bit() && Op.getOperand(2).getValueType() == MVT::i64) { + DAG.getContext()->emitError( + "On LA32, only 32-bit registers can be written."); + return Op.getOperand(0); + } + + return Op; +} + SDValue LoongArchTargetLowering::lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { if (!isa(Op.getOperand(0))) { @@ -927,6 +951,17 @@ } break; } + case ISD::READ_REGISTER: { + if (Subtarget.is64Bit()) + DAG.getContext()->emitError( + "On LA64, only 64-bit registers can be read."); + else + DAG.getContext()->emitError( + "On LA32, only 32-bit registers can be read."); + Results.push_back(DAG.getUNDEF(N->getValueType(0))); + Results.push_back(N->getOperand(0)); + break; + } } } diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td --- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td @@ -1296,7 +1296,7 @@ def PseudoMaskedAtomicLoadNand32 : PseudoMaskedAM; class PseudoAM : Pseudo<(outs GPR:$res, GPR:$scratch), - (ins GPR:$addr, GPR:$incr)> { + (ins GPR:$addr, GPR:$incr, grlenimm:$ordering)> { let Constraints = "@earlyclobber $res,@earlyclobber $scratch"; let mayLoad = 1; let mayStore = 1; @@ -1312,6 +1312,18 @@ def PseudoAtomicLoadOr32 : PseudoAM; def PseudoAtomicLoadXor32 : PseudoAM; +multiclass PseudoBinPat { + def : Pat<(!cast(Op#"_monotonic") GPR:$addr, GPR:$incr), + (BinInst GPR:$addr, GPR:$incr, 2)>; + def : Pat<(!cast(Op#"_acquire") GPR:$addr, GPR:$incr), + (BinInst GPR:$addr, GPR:$incr, 4)>; + def : Pat<(!cast(Op#"_release") GPR:$addr, GPR:$incr), + (BinInst GPR:$addr, GPR:$incr, 5)>; + def : Pat<(!cast(Op#"_acq_rel") GPR:$addr, GPR:$incr), + (BinInst GPR:$addr, GPR:$incr, 6)>; + def : Pat<(!cast(Op#"_seq_cst") GPR:$addr, GPR:$incr), + (BinInst GPR:$addr, GPR:$incr, 7)>; +} class PseudoMaskedAMUMinUMax : Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2), @@ -1371,8 +1383,7 @@ (AMADD_DB_D (SUB_D R0, GPR:$rk), GPR:$rj)>; def : AtomicPat; -def : Pat<(atomic_load_nand_64 GPR:$rj, GPR:$rk), - (PseudoAtomicLoadNand64 GPR:$rj, GPR:$rk)>; +defm : PseudoBinPat<"atomic_load_nand_64", PseudoAtomicLoadNand64>; def : AtomicPat; def : Pat<(atomic_load_add_32 GPR:$rj, GPR:$rk), @@ -1414,30 +1425,23 @@ (PseudoCmpXchg32 GPR:$addr, GPR:$cmp, GPR:$new)>; } // Predicates = [IsLA64] -def : Pat<(atomic_load_nand_32 GPR:$rj, GPR:$rk), - (PseudoAtomicLoadNand32 GPR:$rj, GPR:$rk)>; +defm : PseudoBinPat<"atomic_load_nand_32", PseudoAtomicLoadNand32>; let Predicates = [IsLA32] in { def : AtomicPat; -def : Pat<(atomic_swap_32 GPR:$addr, GPR:$incr), - (PseudoAtomicSwap32 GPR:$incr, GPR:$addr)>; +defm : PseudoBinPat<"atomic_swap_32", PseudoAtomicSwap32>; def : AtomicPat; def : AtomicPat; def : AtomicPat; -def : Pat<(atomic_load_add_32 GPR:$addr, GPR:$incr), - (PseudoAtomicLoadAdd32 GPR:$incr, GPR:$addr)>; -def : Pat<(atomic_load_sub_32 GPR:$addr, GPR:$incr), - (PseudoAtomicLoadSub32 GPR:$incr, GPR:$addr)>; -def : Pat<(atomic_load_and_32 GPR:$addr, GPR:$incr), - (PseudoAtomicLoadAnd32 GPR:$incr, GPR:$addr)>; -def : Pat<(atomic_load_or_32 GPR:$addr, GPR:$incr), - (PseudoAtomicLoadOr32 GPR:$incr, GPR:$addr)>; -def : Pat<(atomic_load_xor_32 GPR:$addr, GPR:$incr), - (PseudoAtomicLoadXor32 GPR:$incr, GPR:$addr)>; +defm : PseudoBinPat<"atomic_load_add_32", PseudoAtomicLoadAdd32>; +defm : PseudoBinPat<"atomic_load_sub_32", PseudoAtomicLoadSub32>; +defm : PseudoBinPat<"atomic_load_and_32", PseudoAtomicLoadAnd32>; +defm : PseudoBinPat<"atomic_load_or_32", PseudoAtomicLoadOr32>; +defm : PseudoBinPat<"atomic_load_xor_32", PseudoAtomicLoadXor32>; } // Predicates = [IsLA32] /// Intrinsics diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -3470,7 +3470,7 @@ getStreamer().switchSection(ReadOnlySection); getStreamer().emitLabel(Sym, IDLoc); - getStreamer().emitValueToAlignment(8); + getStreamer().emitValueToAlignment(Align(8)); getStreamer().emitIntValue(ImmOp64, 8); getStreamer().switchSection(CS); @@ -3553,7 +3553,7 @@ getStreamer().switchSection(ReadOnlySection); getStreamer().emitLabel(Sym, IDLoc); - getStreamer().emitValueToAlignment(8); + getStreamer().emitValueToAlignment(Align(8)); getStreamer().emitIntValue(ImmOp64, 8); getStreamer().switchSection(CS); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp @@ -270,7 +270,7 @@ S->getAssembler().setRelaxAll(true); // Set bundle-alignment as required by the NaCl ABI for the target. - S->emitBundleAlignMode(Log2(MIPS_NACL_BUNDLE_ALIGN)); + S->emitBundleAlignMode(MIPS_NACL_BUNDLE_ALIGN); return S; } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -899,9 +899,9 @@ MCSection &BSSSection = *OFI.getBSSSection(); MCA.registerSection(BSSSection); - TextSection.setAlignment(Align(std::max(16u, TextSection.getAlignment()))); - DataSection.setAlignment(Align(std::max(16u, DataSection.getAlignment()))); - BSSSection.setAlignment(Align(std::max(16u, BSSSection.getAlignment()))); + TextSection.ensureMinAlignment(Align(16)); + DataSection.ensureMinAlignment(Align(16)); + BSSSection.ensureMinAlignment(Align(16)); if (RoundSectionSizes) { // Make sections sizes a multiple of the alignment. This is useful for @@ -912,14 +912,12 @@ for (MCSection &S : MCA) { MCSectionELF &Section = static_cast(S); - unsigned Alignment = Section.getAlignment(); - if (Alignment) { - OS.switchSection(&Section); - if (Section.useCodeAlign()) - OS.emitCodeAlignment(Alignment, &STI, Alignment); - else - OS.emitValueToAlignment(Alignment, 0, 1, Alignment); - } + Align Alignment = Section.getAlign(); + OS.switchSection(&Section); + if (Section.useCodeAlign()) + OS.emitCodeAlignment(Alignment, &STI, Alignment.value()); + else + OS.emitValueToAlignment(Alignment, 0, 1, Alignment.value()); } } diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -1053,7 +1053,7 @@ // // .align 2 // - OutStreamer->emitValueToAlignment(4); + OutStreamer->emitValueToAlignment(Align(4)); MipsTargetStreamer &TS = getTargetStreamer(); // // .set nomips16 @@ -1202,7 +1202,7 @@ // LD RA, 8(SP) // DADDIU SP, SP, 16 // - OutStreamer->emitCodeAlignment(4, &getSubtargetInfo()); + OutStreamer->emitCodeAlignment(Align(4), &getSubtargetInfo()); auto CurSled = OutContext.createTempSymbol("xray_sled_", true); OutStreamer->emitLabel(CurSled); auto Target = OutContext.createTempSymbol(); diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.h @@ -62,7 +62,6 @@ return TLOF.get(); } - void adjustPassManager(PassManagerBuilder &) override; void registerPassBuilderCallbacks(PassBuilder &PB) override; TargetTransformInfo getTargetTransformInfo(const Function &F) const override; diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp --- a/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -31,7 +31,6 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Transforms/IPO/PassManagerBuilder.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Scalar/GVN.h" #include "llvm/Transforms/Vectorize.h" @@ -201,15 +200,6 @@ return new NVPTXPassConfig(*this, PM); } -void NVPTXTargetMachine::adjustPassManager(PassManagerBuilder &Builder) { - Builder.addExtension( - PassManagerBuilder::EP_EarlyAsPossible, - [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) { - PM.add(createNVVMReflectPass(Subtarget.getSmVersion())); - PM.add(createNVVMIntrRangePass(Subtarget.getSmVersion())); - }); -} - void NVPTXTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { PB.registerPipelineParsingCallback( [](StringRef PassName, FunctionPassManager &PM, diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp --- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp @@ -16,6 +16,7 @@ #include "llvm/CodeGen/TargetLowering.h" #include "llvm/IR/IntrinsicsNVPTX.h" #include "llvm/Support/Debug.h" +#include using namespace llvm; #define DEBUG_TYPE "NVPTXtti" @@ -139,10 +140,10 @@ // represents how to replace an NVVM intrinsic with target-generic LLVM IR. struct SimplifyAction { // Invariant: At most one of these Optionals has a value. - Optional IID; - Optional CastOp; - Optional BinaryOp; - Optional Special; + std::optional IID; + std::optional CastOp; + std::optional BinaryOp; + std::optional Special; FtzRequirementTy FtzRequirement = FTZ_Any; // Denormal handling is guarded by different attributes depending on the diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp @@ -1718,7 +1718,7 @@ return addErrorSuffix(" in '.tc' directive"); // Align to word size. - getParser().getStreamer().emitValueToAlignment(Size); + getParser().getStreamer().emitValueToAlignment(Align(Size)); // Emit expressions. return ParseDirectiveWord(Size, ID); diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.cpp @@ -55,7 +55,7 @@ // all of the nops required as part of the alignment operation. In the cases // when no nops are added then The fragment is still created but it remains // empty. - emitCodeAlignment(64, &STI, 4); + emitCodeAlignment(Align(64), &STI, 4); // Emit the instruction. // Since the previous emit created a new fragment then adding this instruction diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -196,7 +196,7 @@ void emitTCEntry(const MCSymbol &S, MCSymbolRefExpr::VariantKind Kind) override { // Creates a R_PPC64_TOC relocation - Streamer.emitValueToAlignment(8); + Streamer.emitValueToAlignment(Align(8)); Streamer.emitSymbolValue(&S, 8); } @@ -325,7 +325,7 @@ MCSymbolRefExpr::VariantKind Kind) override { const MCAsmInfo *MAI = Streamer.getContext().getAsmInfo(); const unsigned PointerSize = MAI->getCodePointerSize(); - Streamer.emitValueToAlignment(PointerSize); + Streamer.emitValueToAlignment(Align(PointerSize)); Streamer.emitValue(MCSymbolRefExpr::create(&S, Kind, Streamer.getContext()), PointerSize); } diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFStreamer.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFStreamer.cpp --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFStreamer.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCXCOFFStreamer.cpp @@ -46,7 +46,7 @@ // prefixed instruction. Align to 64 bytes if possible but add a maximum of 4 // bytes when trying to do that. If alignment requires adding more than 4 // bytes then the instruction won't be aligned. - emitCodeAlignment(64, &STI, 4); + emitCodeAlignment(Align(64), &STI, 4); // Emit the instruction. // Since the previous emit created a new fragment then adding this instruction diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -1537,7 +1537,7 @@ // // Update compiler-rt/lib/xray/xray_powerpc64.cc accordingly when number // of instructions change. - OutStreamer->emitCodeAlignment(8, &getSubtargetInfo()); + OutStreamer->emitCodeAlignment(Align(8), &getSubtargetInfo()); MCSymbol *BeginOfSled = OutContext.createTempSymbol(); OutStreamer->emitLabel(BeginOfSled); EmitToStreamer(*OutStreamer, RetInst); @@ -1661,7 +1661,7 @@ ".opd", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); OutStreamer->switchSection(Section); OutStreamer->emitLabel(CurrentFnSym); - OutStreamer->emitValueToAlignment(8); + OutStreamer->emitValueToAlignment(Align(8)); MCSymbol *Symbol1 = CurrentFnSymForSize; // Generates a R_PPC64_ADDR64 (from FK_DATA_8) relocation for the function // entry point. @@ -1693,7 +1693,7 @@ Name, ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); OutStreamer->switchSection(Section); if (!isPPC64) - OutStreamer->emitValueToAlignment(4); + OutStreamer->emitValueToAlignment(Align(4)); for (const auto &TOCMapPair : TOC) { const MCSymbol *const TOCEntryTarget = TOCMapPair.first.first; @@ -1974,7 +1974,7 @@ const DataLayout &DL = MMI->getModule()->getDataLayout(); const unsigned PointerSize = DL.getPointerSize(); // Add necessary paddings in 64 bit mode. - OutStreamer->emitValueToAlignment(PointerSize); + OutStreamer->emitValueToAlignment(Align(PointerSize)); OutStreamer->emitIntValue(0, PointerSize); OutStreamer->emitIntValue(0, PointerSize); @@ -2325,7 +2325,7 @@ MCSymbolRefExpr::create(TOCBaseSym, Ctx), Ctx); const DataLayout &DL = getDataLayout(); - OutStreamer->emitValueToAlignment(4); + OutStreamer->emitValueToAlignment(Align(4)); OutStreamer->AddComment("EHInfo Table"); OutStreamer->emitValue(Exp, DL.getPointerSize()); } @@ -2432,7 +2432,7 @@ if (GVKind.isBSSLocal() || GVKind.isThreadBSSLocal()) OutStreamer->emitXCOFFLocalCommonSymbol( OutContext.getOrCreateSymbol(GVSym->getSymbolTableName()), Size, - GVSym, Alignment.value()); + GVSym, Alignment); else OutStreamer->emitCommonSymbol(GVSym, Size, Alignment.value()); return; @@ -2589,8 +2589,7 @@ getObjFileLowering().SectionForGlobal(GO, GOKind, TM)); Align GOAlign = getGVAlignment(GO, GO->getParent()->getDataLayout()); - if (GOAlign > Csect->getAlignment()) - Csect->setAlignment(GOAlign); + Csect->ensureMinAlignment(GOAlign); }; // We need to know, up front, the alignment of csects for the assembly path, diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.cpp b/llvm/lib/Target/PowerPC/PPCCallingConv.cpp --- a/llvm/lib/Target/PowerPC/PPCCallingConv.cpp +++ b/llvm/lib/Target/PowerPC/PPCCallingConv.cpp @@ -120,7 +120,7 @@ return false; unsigned i; - for (i = 0; i < sizeof(HiRegList) / sizeof(HiRegList[0]); ++i) + for (i = 0; i < std::size(HiRegList); ++i) if (HiRegList[i] == Reg) break; @@ -149,7 +149,7 @@ return false; unsigned i; - for (i = 0; i < sizeof(HiRegList) / sizeof(HiRegList[0]); ++i) + for (i = 0; i < std::size(HiRegList); ++i) if (HiRegList[i] == Reg) break; diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -123,6 +123,7 @@ /// XXPERMDI - The PPC XXPERMDI instruction /// XXPERMDI, + XXPERM, /// The CMPB instruction (takes two operands of i32 or i64). CMPB, @@ -1290,6 +1291,8 @@ SDValue LowerFunnelShift(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerVPERM(SDValue Op, SelectionDAG &DAG, ArrayRef PermMask, + EVT VT, SDValue V1, SDValue V2) const; SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -138,7 +138,8 @@ STATISTIC(NumTailCalls, "Number of tail calls"); STATISTIC(NumSiblingCalls, "Number of sibling calls"); -STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM"); +STATISTIC(ShufflesHandledWithVPERM, + "Number of shuffles lowered to a VPERM or XXPERM"); STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed"); static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int); @@ -1640,6 +1641,8 @@ return "PPCISD::XXSPLTI32DX"; case PPCISD::VECINSERT: return "PPCISD::VECINSERT"; case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI"; + case PPCISD::XXPERM: + return "PPCISD::XXPERM"; case PPCISD::VECSHL: return "PPCISD::VECSHL"; case PPCISD::CMPB: return "PPCISD::CMPB"; case PPCISD::Hi: return "PPCISD::Hi"; @@ -10152,42 +10155,135 @@ // vector that will get spilled to the constant pool. if (V2.isUndef()) V2 = V1; + return LowerVPERM(Op, DAG, PermMask, VT, V1, V2); +} + +SDValue PPCTargetLowering::LowerVPERM(SDValue Op, SelectionDAG &DAG, + ArrayRef PermMask, EVT VT, + SDValue V1, SDValue V2) const { + unsigned Opcode = PPCISD::VPERM; + EVT ValType = V1.getValueType(); + SDLoc dl(Op); + bool NeedSwap = false; + bool isLittleEndian = Subtarget.isLittleEndian(); + bool isPPC64 = Subtarget.isPPC64(); + + // Only need to place items backwards in LE, + // the mask will be properly calculated. + if (isLittleEndian) + std::swap(V1, V2); + + if (Subtarget.isISA3_0() && (V1->hasOneUse() || V2->hasOneUse())) { + LLVM_DEBUG(dbgs() << "At least one of two input vectors are dead - using " + "XXPERM instead\n"); + Opcode = PPCISD::XXPERM; + + // if V2 is dead, then we swap V1 and V2 so we can + // use V2 as the destination instead. + if (!V1->hasOneUse() && V2->hasOneUse()) { + std::swap(V1, V2); + NeedSwap = !NeedSwap; + } + } + + bool V1HasXXSWAPD = V1->getOperand(0)->getOpcode() == PPCISD::XXSWAPD; + bool V2HasXXSWAPD = V2->getOperand(0)->getOpcode() == PPCISD::XXSWAPD; + // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except // that it is in input element units, not in bytes. Convert now. // For little endian, the order of the input vectors is reversed, and // the permutation mask is complemented with respect to 31. This is - // necessary to produce proper semantics with the big-endian-biased vperm + // necessary to produce proper semantics with the big-endian-based vperm // instruction. EVT EltVT = V1.getValueType().getVectorElementType(); - unsigned BytesPerElement = EltVT.getSizeInBits()/8; + unsigned BytesPerElement = EltVT.getSizeInBits() / 8; + + /* + Vectors will be appended like so: [ V1 | v2 ] + XXSWAPD on V1: + [ A | B | C | D ] -> [ C | D | A | B ] + 0-3 4-7 8-11 12-15 0-3 4-7 8-11 12-15 + i.e. index of A, B += 8, and index of C, D -= 8. + XXSWAPD on V2: + [ E | F | G | H ] -> [ G | H | E | F ] + 16-19 20-23 24-27 28-31 16-19 20-23 24-27 28-31 + i.e. index of E, F += 8, index of G, H -= 8 + Swap V1 and V2: + [ V1 | V2 ] -> [ V2 | V1 ] + 0-15 16-31 0-15 16-31 + i.e. index of V1 += 16, index of V2 -= 16 + */ SmallVector ResultMask; for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i]; + if (V1HasXXSWAPD) { + if (SrcElt < 8) + SrcElt += 8; + else if (SrcElt < 16) + SrcElt -= 8; + } + if (V2HasXXSWAPD) { + if (SrcElt > 23) + SrcElt -= 8; + else if (SrcElt > 15) + SrcElt += 8; + } + if (NeedSwap) { + if (SrcElt < 16) + SrcElt += 16; + else + SrcElt -= 16; + } for (unsigned j = 0; j != BytesPerElement; ++j) if (isLittleEndian) - ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j), - dl, MVT::i32)); + ResultMask.push_back( + DAG.getConstant(31 - (SrcElt * BytesPerElement + j), dl, MVT::i32)); else - ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl, - MVT::i32)); + ResultMask.push_back( + DAG.getConstant(SrcElt * BytesPerElement + j, dl, MVT::i32)); + } + + if (V1HasXXSWAPD) { + dl = SDLoc(V1->getOperand(0)); + V1 = V1->getOperand(0)->getOperand(1); + } + if (V2HasXXSWAPD) { + dl = SDLoc(V2->getOperand(0)); + V2 = V2->getOperand(0)->getOperand(1); + } + + if (V1HasXXSWAPD || V2HasXXSWAPD || Opcode == PPCISD::XXPERM) { + if (isPPC64 && ValType != MVT::v2f64) + V1 = DAG.getBitcast(MVT::v2f64, V1); + if (isPPC64 && V2.getValueType() != MVT::v2f64) + V2 = DAG.getBitcast(MVT::v2f64, V2); } ShufflesHandledWithVPERM++; SDValue VPermMask = DAG.getBuildVector(MVT::v16i8, dl, ResultMask); - LLVM_DEBUG(dbgs() << "Emitting a VPERM for the following shuffle:\n"); - LLVM_DEBUG(SVOp->dump()); - LLVM_DEBUG(dbgs() << "With the following permute control vector:\n"); - LLVM_DEBUG(VPermMask.dump()); + LLVM_DEBUG({ + ShuffleVectorSDNode *SVOp = cast(Op); + if (Opcode == PPCISD::XXPERM) { + dbgs() << "Emitting a XXPERM for the following shuffle:\n"; + } else { + dbgs() << "Emitting a VPERM for the following shuffle:\n"; + } + SVOp->dump(); + dbgs() << "With the following permute control vector:\n"; + VPermMask.dump(); + }); - if (isLittleEndian) - return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), - V2, V1, VPermMask); - else - return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), - V1, V2, VPermMask); + if (Opcode == PPCISD::XXPERM) + VPermMask = DAG.getBitcast(MVT::v4i32, VPermMask); + + SDValue VPERMNode = + DAG.getNode(Opcode, dl, V1.getValueType(), V1, V2, VPermMask); + + VPERMNode = DAG.getBitcast(ValType, VPERMNode); + return VPERMNode; } /// getVectorCompareInfo - Given an intrinsic, return false if it is not a diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -1057,6 +1057,8 @@ def : Pat<(PPCvperm v16i8:$vA, v16i8:$vB, v16i8:$vC), (VPERM $vA, $vB, $vC)>; +def : Pat<(PPCvperm v2f64:$vA, v2f64:$vB, v16i8:$vC), + (VPERM $vA, $vB, $vC)>; def : Pat<(PPCfre v4f32:$A), (VREFP $A)>; def : Pat<(PPCfrsqrte v4f32:$A), (VRSQRTEFP $A)>; diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -86,6 +86,9 @@ SDTCisVec<0>, SDTCisPtrTy<1> ]>; +def SDT_PPCxxperm : SDTypeProfile<1, 3, [ + SDTCisVT<0, v2f64>, SDTCisVT<1, v2f64>, + SDTCisVT<2, v2f64>, SDTCisVT<3, v4i32>]>; //--------------------------- Custom PPC nodes -------------------------------// def PPClxvd2x : SDNode<"PPCISD::LXVD2X", SDT_PPClxvd2x, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; @@ -116,6 +119,7 @@ def PPCSToV : SDNode<"PPCISD::SCALAR_TO_VECTOR_PERMUTED", SDTypeProfile<1, 1, []>, []>; +def PPCxxperm : SDNode<"PPCISD::XXPERM", SDT_PPCxxperm, []>; //-------------------------- Predicate definitions ---------------------------// def HasVSX : Predicate<"Subtarget->hasVSX()">; def IsLittleEndian : Predicate<"Subtarget->isLittleEndian()">; @@ -1643,13 +1647,14 @@ def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>; // Vector Permute - // FIXME: Setting the hasSideEffects flag here to match current behaviour. - let hasSideEffects = 1 in { - def XXPERM : XX3_XT5_XA5_XB5<60, 26, "xxperm" , vsrc, vsrc, vsrc, - IIC_VecPerm, []>; - def XXPERMR : XX3_XT5_XA5_XB5<60, 58, "xxpermr", vsrc, vsrc, vsrc, - IIC_VecPerm, []>; - } + def XXPERM : XX3Form<60, 26, (outs vsrc:$XT), + (ins vsrc:$XA, vsrc:$XTi, vsrc:$XB), + "xxperm $XT, $XA, $XB", IIC_VecPerm, []>, + RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; + def XXPERMR : XX3Form<60, 58, (outs vsrc:$XT), + (ins vsrc:$XA, vsrc:$XTi, vsrc:$XB), + "xxpermr $XT, $XA, $XB", IIC_VecPerm, []>, + RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; // Vector Splat Immediate Byte // FIXME: Setting the hasSideEffects flag here to match current behaviour. @@ -4143,6 +4148,8 @@ (v8i16 (VSPLTHs 3, (LXSIHZX ForceXForm:$A)))>; def : Pat<(v16i8 (PPCldsplat ForceXForm:$A)), (v16i8 (VSPLTBs 7, (LXSIBZX ForceXForm:$A)))>; +def : Pat<(v2f64 (PPCxxperm v2f64:$XT, v2f64:$XB, v4i32:$C)), + (XXPERM v2f64:$XT, v2f64:$XB, v4i32:$C)>; } // HasVSX, HasP9Vector // Any Power9 VSX subtarget with equivalent length but better Power10 VSX diff --git a/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp b/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp --- a/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp +++ b/llvm/lib/Target/PowerPC/PPCMacroFusion.cpp @@ -16,6 +16,7 @@ #include "llvm/ADT/DenseSet.h" #include "llvm/CodeGen/MacroFusion.h" #include "llvm/CodeGen/ScheduleDAGMutation.h" +#include using namespace llvm; namespace { @@ -55,7 +56,7 @@ bool hasOp1(unsigned Opc) const { return OpSet1.contains(Opc); } bool hasOp2(unsigned Opc) const { return OpSet2.contains(Opc); } bool isSupported() const { return Supported; } - Optional depOpIdx() const { + std::optional depOpIdx() const { if (DepOpIdx < 0) return None; return DepOpIdx; diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -292,6 +292,16 @@ "'Zca' (part of the C extension, excluding " "compressed floating point loads/stores)">; +def FeatureExtZcd + : SubtargetFeature<"experimental-zcd", "HasStdExtZcd", "true", + "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">; + +def HasStdExtCOrZcd + : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">, + AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZcd), + "'C' (Compressed Instructions) or " + "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">; + def FeatureExtZcf : SubtargetFeature<"experimental-zcf", "HasStdExtZcf", "true", "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">; diff --git a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp @@ -23,6 +23,7 @@ #include "llvm/IR/IntrinsicsRISCV.h" #include "llvm/IR/PatternMatch.h" #include "llvm/Transforms/Utils/Local.h" +#include using namespace llvm; using namespace PatternMatch; @@ -346,7 +347,7 @@ if (Ops[0]->getType()->isVectorTy()) return std::make_pair(nullptr, nullptr); - Optional VecOperand; + std::optional VecOperand; unsigned TypeScale = 0; // Look for a vector operand and scale. diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -22,6 +22,7 @@ #include "llvm/Support/KnownBits.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" +#include using namespace llvm; @@ -2636,7 +2637,7 @@ return false; // Retrieve the tail policy operand index, if any. - Optional TailPolicyOpIdx; + std::optional TailPolicyOpIdx; const RISCVInstrInfo &TII = *Subtarget->getInstrInfo(); const MCInstrDesc &MaskedMCID = TII.get(N->getMachineOpcode()); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -39,6 +39,7 @@ #include "llvm/Support/KnownBits.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" +#include using namespace llvm; @@ -2158,8 +2159,8 @@ int64_t Addend; }; -static Optional getExactInteger(const APFloat &APF, - uint32_t BitWidth) { +static std::optional getExactInteger(const APFloat &APF, + uint32_t BitWidth) { APSInt ValInt(BitWidth, !APF.isNegative()); // We use an arbitrary rounding mode here. If a floating-point is an exact // integer (e.g., 1.0), the rounding mode does not affect the output value. If @@ -2186,14 +2187,14 @@ // Note that this method will also match potentially unappealing index // sequences, like , however it is left to the caller to // determine whether this is worth generating code for. -static Optional isSimpleVIDSequence(SDValue Op) { +static std::optional isSimpleVIDSequence(SDValue Op) { unsigned NumElts = Op.getNumOperands(); assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unexpected BUILD_VECTOR"); bool IsInteger = Op.getValueType().isInteger(); - Optional SeqStepDenom; - Optional SeqStepNum, SeqAddend; - Optional> PrevElt; + std::optional SeqStepDenom; + std::optional SeqStepNum, SeqAddend; + std::optional> PrevElt; unsigned EltSizeInBits = Op.getValueType().getScalarSizeInBits(); for (unsigned Idx = 0; Idx < NumElts; Idx++) { // Assume undef elements match the sequence; we just have to be careful @@ -5496,8 +5497,7 @@ // TODO: We restrict this to unmasked loads currently in consideration of // the complexity of hanlding all falses masks. - if (IsUnmasked && isNullConstant(Stride) && - !Subtarget.hasOptimizedZeroStrideLoad()) { + if (IsUnmasked && isNullConstant(Stride)) { MVT ScalarVT = ContainerVT.getVectorElementType(); SDValue ScalarLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, XLenVT, Load->getChain(), Ptr, @@ -9700,6 +9700,33 @@ } } + // (select (x < 0), y, z) -> x >> (XLEN - 1) & (y - z) + z + // (select (x >= 0), y, z) -> x >> (XLEN - 1) & (z - y) + y + if (!Subtarget.hasShortForwardBranchOpt() && isa(TrueV) && + isa(FalseV) && isNullConstant(RHS) && + (CCVal == ISD::CondCode::SETLT || CCVal == ISD::CondCode::SETGE)) { + if (CCVal == ISD::CondCode::SETGE) + std::swap(TrueV, FalseV); + + int64_t TrueSImm = cast(TrueV)->getSExtValue(); + int64_t FalseSImm = cast(FalseV)->getSExtValue(); + // Only handle simm12, if it is not in this range, it can be considered as + // register. + if (isInt<12>(TrueSImm) && isInt<12>(FalseSImm) && + isInt<12>(TrueSImm - FalseSImm)) { + SDValue SRA = + DAG.getNode(ISD::SRA, DL, VT, LHS, + DAG.getConstant(Subtarget.getXLen() - 1, DL, VT)); + SDValue AND = + DAG.getNode(ISD::AND, DL, VT, SRA, + DAG.getConstant(TrueSImm - FalseSImm, DL, VT)); + return DAG.getNode(ISD::ADD, DL, VT, AND, FalseV); + } + + if (CCVal == ISD::CondCode::SETGE) + std::swap(TrueV, FalseV); + } + if (combine_CC(LHS, RHS, CC, DL, DAG, Subtarget)) return DAG.getNode(RISCVISD::SELECT_CC, DL, N->getValueType(0), {LHS, RHS, CC, TrueV, FalseV}); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -311,7 +311,7 @@ let Inst{5} = imm{3}; } -let Predicates = [HasStdExtC, HasStdExtD] in +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in def C_FLD : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000>, Sched<[WriteFLD64, ReadMemBase]> { bits<8> imm; @@ -345,7 +345,7 @@ let Inst{6-5} = imm{7-6}; } -let Predicates = [HasStdExtC, HasStdExtD] in +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in def C_FSD : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000>, Sched<[WriteFST64, ReadStoreData, ReadMemBase]> { bits<8> imm; @@ -501,7 +501,7 @@ let Inst{6-2} = imm{4-0}; } -let Predicates = [HasStdExtC, HasStdExtD] in +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>, Sched<[WriteFLD64, ReadMemBase]> { let Inst{6-5} = imm{4-3}; @@ -561,7 +561,7 @@ let Constraints = "$rs1 = $rs1_wb"; } -let Predicates = [HasStdExtC, HasStdExtD] in +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>, Sched<[WriteFST64, ReadStoreData, ReadMemBase]> { let Inst{12-10} = imm{5-3}; @@ -740,7 +740,7 @@ def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32C:$rs2, SPMem:$rs1, 0)>; } -let Predicates = [HasStdExtC, HasStdExtD] in { +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in { def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRCMem:$rs1, 0)>; def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRCMem:$rs1, 0)>; def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64C:$rd, SPMem:$rs1, 0)>; @@ -761,10 +761,10 @@ (C_ADDI4SPN GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm)>; } // Predicates = [HasStdExtCOrZca] -let Predicates = [HasStdExtC, HasStdExtD] in { +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in { def : CompressPat<(FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm), (C_FLD FPR64C:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>; -} // Predicates = [HasStdExtC, HasStdExtD] +} // Predicates = [HasStdExtCOrZcd, HasStdExtD] let Predicates = [HasStdExtCOrZca] in { def : CompressPat<(LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm), @@ -781,10 +781,10 @@ (C_LD GPRC:$rd, GPRCMem:$rs1, uimm8_lsb000:$imm)>; } // Predicates = [HasStdExtCOrZca, IsRV64] -let Predicates = [HasStdExtC, HasStdExtD] in { +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in { def : CompressPat<(FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm), (C_FSD FPR64C:$rs2, GPRCMem:$rs1, uimm8_lsb000:$imm)>; -} // Predicates = [HasStdExtC, HasStdExtD] +} // Predicates = [HasStdExtCOrZcd, HasStdExtD] let Predicates = [HasStdExtCOrZca] in { def : CompressPat<(SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm), @@ -878,10 +878,10 @@ (C_SLLI GPRNoX0:$rs1, uimmlog2xlennonzero:$imm)>; } // Predicates = [HasStdExtCOrZca] -let Predicates = [HasStdExtC, HasStdExtD] in { +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in { def : CompressPat<(FLD FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm), (C_FLDSP FPR64:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>; -} // Predicates = [HasStdExtC, HasStdExtD] +} // Predicates = [HasStdExtCOrZcd, HasStdExtD] let Predicates = [HasStdExtCOrZca] in { def : CompressPat<(LW GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm), @@ -920,10 +920,10 @@ (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } // Predicates = [HasStdExtCOrZca] -let Predicates = [HasStdExtC, HasStdExtD] in { +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in { def : CompressPat<(FSD FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm), (C_FSDSP FPR64:$rs2, SPMem:$rs1, uimm9_lsb000:$imm)>; -} // Predicates = [HasStdExtC, HasStdExtD] +} // Predicates = [HasStdExtCOrZcd, HasStdExtD] let Predicates = [HasStdExtCOrZca] in { def : CompressPat<(SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm), diff --git a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp --- a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp +++ b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp @@ -18,6 +18,7 @@ #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/Debug.h" #include "llvm/Target/TargetOptions.h" +#include #include using namespace llvm; @@ -341,7 +342,7 @@ // Lo: addi vreg2, vreg1, %pcrel_lo(1b) ---> lw vreg3, %pcrel_lo(1b)(vreg1) // Tail: lw vreg3, 8(vreg2) - Optional CommonOffset; + std::optional CommonOffset; for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) { switch (UseMI.getOpcode()) { default: diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h @@ -66,6 +66,11 @@ SmallVectorImpl &Ops) const override; unsigned getRegisterCostTableIndex(const MachineFunction &MF) const override; + + bool getRegAllocationHints(Register VirtReg, ArrayRef Order, + SmallVectorImpl &Hints, + const MachineFunction &MF, const VirtRegMap *VRM, + const LiveRegMatrix *Matrix) const override; }; } diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -29,6 +29,12 @@ using namespace llvm; +static cl::opt + DisableRegAllocHints("riscv-disable-regalloc-hints", cl::Hidden, + cl::init(false), + cl::desc("Disable two address hints for register " + "allocation")); + static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive"); static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive"); static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive"); @@ -376,3 +382,71 @@ RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const { return MF.getSubtarget().hasStdExtC() ? 1 : 0; } + +// Add two address hints to improve chances of being able to use a compressed +// instruction. +bool RISCVRegisterInfo::getRegAllocationHints( + Register VirtReg, ArrayRef Order, + SmallVectorImpl &Hints, const MachineFunction &MF, + const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const { + const MachineRegisterInfo *MRI = &MF.getRegInfo(); + + bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints( + VirtReg, Order, Hints, MF, VRM, Matrix); + + if (!VRM || DisableRegAllocHints) + return BaseImplRetVal; + + // Add any two address hints after any copy hints. + SmallSet TwoAddrHints; + + auto tryAddHint = [&](const MachineOperand &VRRegMO, + const MachineOperand &MO) -> void { + Register Reg = MO.getReg(); + Register PhysReg = + Register::isPhysicalRegister(Reg) ? Reg : Register(VRM->getPhys(Reg)); + if (PhysReg) { + assert(!MO.getSubReg() && !VRRegMO.getSubReg() && "Unexpected subreg!"); + if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg)) + TwoAddrHints.insert(PhysReg); + } + }; + + // For now we support the compressible instructions which can encode all + // registers and have a single register source. + // TODO: Add more compressed instructions. + auto isCompressible = [](const MachineInstr &MI) { + switch (MI.getOpcode()) { + default: + return false; + case RISCV::ADD: + case RISCV::SLLI: + return true; + case RISCV::ADDI: + case RISCV::ADDIW: + return MI.getOperand(2).isImm() && isInt<6>(MI.getOperand(2).getImm()); + } + }; + + for (auto &MO : MRI->reg_nodbg_operands(VirtReg)) { + const MachineInstr &MI = *MO.getParent(); + if (isCompressible(MI)) { + unsigned OpIdx = MI.getOperandNo(&MO); + if (OpIdx == 0 && MI.getOperand(1).isReg()) { + tryAddHint(MO, MI.getOperand(1)); + if (MI.isCommutable() && MI.getOperand(2).isReg()) + tryAddHint(MO, MI.getOperand(2)); + } else if (OpIdx == 1) { + tryAddHint(MO, MI.getOperand(0)); + } else if (MI.isCommutable() && OpIdx == 2) { + tryAddHint(MO, MI.getOperand(0)); + } + } + } + + for (MCPhysReg OrderReg : Order) + if (TwoAddrHints.count(OrderReg)) + Hints.push_back(OrderReg); + + return BaseImplRetVal; +} diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -56,6 +56,7 @@ bool HasStdExtZbc = false; bool HasStdExtZbs = false; bool HasStdExtZca = false; + bool HasStdExtZcd = false; bool HasStdExtZcf = false; bool HasStdExtV = false; bool HasStdExtZve32x = false; @@ -168,6 +169,7 @@ bool hasStdExtZbc() const { return HasStdExtZbc; } bool hasStdExtZbs() const { return HasStdExtZbs; } bool hasStdExtZca() const { return HasStdExtZca; } + bool hasStdExtZcd() const { return HasStdExtZcd; } bool hasStdExtZcf() const { return HasStdExtZcf; } bool hasStdExtZvl() const { return ZvlLen != 0; } bool hasStdExtZvfh() const { return HasStdExtZvfh; } diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp --- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp +++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp @@ -222,7 +222,7 @@ } bool First = true; - for (unsigned i = 0; i < sizeof(TagNames) / sizeof(char *); i++) { + for (unsigned i = 0; i < std::size(TagNames); i++) { if (Imm & (1 << i)) { O << (First ? "" : " | ") << TagNames[i]; First = false; diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -770,7 +770,10 @@ return false; // Do not tail call opt if the stack is used to pass parameters. - if (CCInfo.getNextStackOffset() != 0) + // 64-bit targets have a slightly higher limit since the ABI requires + // to allocate some space even when all the parameters fit inside registers. + unsigned StackOffsetLimit = Subtarget->is64Bit() ? 48 : 0; + if (CCInfo.getNextStackOffset() > StackOffsetLimit) return false; // Do not tail call opt if either the callee or caller returns @@ -1189,20 +1192,21 @@ SDValue Chain = CLI.Chain; auto PtrVT = getPointerTy(DAG.getDataLayout()); - // Sparc target does not yet support tail call optimization. - CLI.IsTailCall = false; - // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext()); CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64); + CLI.IsTailCall = CLI.IsTailCall && IsEligibleForTailCallOptimization( + CCInfo, CLI, DAG.getMachineFunction()); + // Get the size of the outgoing arguments stack space requirement. // The stack offset computed by CC_Sparc64 includes all arguments. // Called functions expect 6 argument words to exist in the stack frame, used // or not. - unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset()); + unsigned StackReserved = 6 * 8u; + unsigned ArgsSize = std::max(StackReserved, CCInfo.getNextStackOffset()); // Keep stack frames 16-byte aligned. ArgsSize = alignTo(ArgsSize, 16); @@ -1211,10 +1215,13 @@ if (CLI.IsVarArg) fixupVariableFloatArgs(ArgLocs, CLI.Outs); + assert(!CLI.IsTailCall || ArgsSize == StackReserved); + // Adjust the stack pointer to make room for the arguments. // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls // with more than 6 arguments. - Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, DL); + if (!CLI.IsTailCall) + Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, DL); // Collect the set of registers to pass to the function and their values. // This will be emitted as a sequence of CopyToReg nodes glued to the call @@ -1274,10 +1281,16 @@ DAG.getLoad(MVT::i64, DL, Store, HiPtrOff, MachinePointerInfo()); SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff, MachinePointerInfo()); - RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), - Hi64)); - RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1), - Lo64)); + + Register HiReg = VA.getLocReg(); + Register LoReg = VA.getLocReg() + 1; + if (!CLI.IsTailCall) { + HiReg = toCallerWindow(HiReg); + LoReg = toCallerWindow(LoReg); + } + + RegsToPass.push_back(std::make_pair(HiReg, Hi64)); + RegsToPass.push_back(std::make_pair(LoReg, Lo64)); continue; } @@ -1298,7 +1311,11 @@ ++i; } } - RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg)); + + Register Reg = VA.getLocReg(); + if (!CLI.IsTailCall) + Reg = toCallerWindow(Reg); + RegsToPass.push_back(std::make_pair(Reg, Arg)); continue; } @@ -1366,6 +1383,10 @@ Ops.push_back(InGlue); // Now the call itself. + if (CLI.IsTailCall) { + DAG.getMachineFunction().getFrameInfo().setHasTailCall(); + return DAG.getNode(SPISD::TAIL_CALL, DL, MVT::Other, Ops); + } SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops); InGlue = Chain.getValue(1); diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td --- a/llvm/lib/Target/VE/VEInstrInfo.td +++ b/llvm/lib/Target/VE/VEInstrInfo.td @@ -1194,8 +1194,6 @@ // Section 8.4 - Fixed-point Operation Instructions //----------------------------------------------------------------------------- -let isReMaterializable = 1, isAsCheapAsAMove = 1 in { - // Section 8.4.1 - ADD (Add) defm ADDUL : RRm<"addu.l", 0x48, I64, i64>; let cx = 1 in defm ADDUW : RRm<"addu.w", 0x48, I32, i32>; @@ -1218,8 +1216,6 @@ // Section 8.4.6 - SBX (Subtract) defm SUBSL : RRNCm<"subs.l", 0x5B, I64, i64, sub>; -} // isReMaterializable, isAsCheapAsAMove - // Section 8.4.7 - MPY (Multiply) defm MULUL : RRm<"mulu.l", 0x49, I64, i64>; let cx = 1 in defm MULUW : RRm<"mulu.w", 0x49, I32, i32>; @@ -1245,8 +1241,6 @@ // Section 8.4.13 - DVX (Divide) defm DIVSL : RRNCm<"divs.l", 0x7F, I64, i64, sdiv>; -let isReMaterializable = 1, isAsCheapAsAMove = 1 in { - // Section 8.4.14 - CMP (Compare) defm CMPUL : RRNCm<"cmpu.l", 0x55, I64, i64, cmpu>; let cx = 1 in defm CMPUW : RRNCm<"cmpu.w", 0x55, I32, i32, cmpu>; @@ -1269,18 +1263,15 @@ defm MAXSL : RRm<"maxs.l", 0x68, I64, i64, smax>; let cw = 1 in defm MINSL : RRm<"mins.l", 0x68, I64, i64, smin>; -} // isReMaterializable, isAsCheapAsAMove - //----------------------------------------------------------------------------- // Section 8.5 - Logical Operation Instructions //----------------------------------------------------------------------------- -let isReMaterializable = 1, isAsCheapAsAMove = 1 in { - // Section 8.5.1 - AND (AND) defm AND : RRm<"and", 0x44, I64, i64, and>; // Section 8.5.2 - OR (OR) +let isReMaterializable = 1, isAsCheapAsAMove = 1 in defm OR : RRm<"or", 0x45, I64, i64, or, simm7, mimm, /* MoveImm */ 1>; // Section 8.5.3 - XOR (Exclusive OR) @@ -1289,12 +1280,9 @@ // Section 8.5.4 - EQV (Equivalence) defm EQV : RRm<"eqv", 0x47, I64, i64>; -} // isReMaterializable, isAsCheapAsAMove - // Section 8.5.5 - NND (Negate AND) def and_not : PatFrags<(ops node:$x, node:$y), [(and (not node:$x), node:$y)]>; -let isReMaterializable = 1, isAsCheapAsAMove = 1 in defm NND : RRNCm<"nnd", 0x54, I64, i64, and_not>; // Section 8.5.6 - MRG (Merge) @@ -1304,18 +1292,15 @@ def ctlz_pat : PatFrags<(ops node:$src), [(ctlz node:$src), (ctlz_zero_undef node:$src)]>; -let isReMaterializable = 1, isAsCheapAsAMove = 1 in defm LDZ : RRI1m<"ldz", 0x67, I64, i64, ctlz_pat>; // Section 8.5.8 - PCNT (Population Count) defm PCNT : RRI1m<"pcnt", 0x38, I64, i64, ctpop>; // Section 8.5.9 - BRV (Bit Reverse) -let isReMaterializable = 1, isAsCheapAsAMove = 1 in defm BRV : RRI1m<"brv", 0x39, I64, i64, bitreverse>; // Section 8.5.10 - BSWP (Byte Swap) -let isReMaterializable = 1, isAsCheapAsAMove = 1 in defm BSWP : RRSWPm<"bswp", 0x2B, I64, i64>; def : Pat<(i64 (bswap i64:$src)), @@ -1330,7 +1315,6 @@ (EXTRACT_SUBREG (BSWPmi (MIMM $src), 1), sub_i32)>; // Section 8.5.11 - CMOV (Conditional Move) -let isReMaterializable = 1 in { let cw = 0, cw2 = 0 in defm CMOVL : RRCMOVm<"cmov.l.${cfw}", 0x3B, I64, i64, cmov>; let cw = 1, cw2 = 0 in @@ -1339,7 +1323,6 @@ defm CMOVD : RRCMOVm<"cmov.d.${cfw}", 0x3B, I64, f64, cmov, simm7fp>; let cw = 1, cw2 = 1 in defm CMOVS : RRCMOVm<"cmov.s.${cfw}", 0x3B, F32, f32, cmov, simm7fp>; -} def : MnemonicAlias<"cmov.l", "cmov.l.at">; def : MnemonicAlias<"cmov.w", "cmov.w.at">; def : MnemonicAlias<"cmov.d", "cmov.d.at">; @@ -1350,21 +1333,17 @@ //----------------------------------------------------------------------------- // Section 8.6.1 - SLL (Shift Left Logical) -let isReMaterializable = 1, isAsCheapAsAMove = 1 in defm SLL : RRIm<"sll", 0x65, I64, i64, shl>; // Section 8.6.2 - SLD (Shift Left Double) defm SLD : RRILDm<"sld", 0x64, I64>; // Section 8.6.3 - SRL (Shift Right Logical) -let isReMaterializable = 1, isAsCheapAsAMove = 1 in defm SRL : RRIm<"srl", 0x75, I64, i64, srl>; // Section 8.6.4 - SRD (Shift Right Double) defm SRD : RRIRDm<"srd", 0x74, I64>; -let isReMaterializable = 1, isAsCheapAsAMove = 1 in { - // Section 8.6.5 - SLA (Shift Left Arithmetic) defm SLAWSX : RRIm<"sla.w.sx", 0x66, I32, i32, shl>; let cx = 1 in defm SLAWZX : RRIm<"sla.w.zx", 0x66, I32, i32>; @@ -1379,8 +1358,6 @@ // Section 8.6.8 - SRAX (Shift Right Arithmetic) defm SRAL : RRIm<"sra.l", 0x77, I64, i64, sra>; -} // isReMaterializable, isAsCheapAsAMove - def : Pat<(i32 (srl i32:$src, (i32 simm7:$val))), (EXTRACT_SUBREG (SRLri (ANDrm (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $src, sub_i32), !add(32, 64)), imm:$val), sub_i32)>; diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -4727,9 +4727,9 @@ Section = getStreamer().getCurrentSectionOnly(); } if (Section->useCodeAlign()) - getStreamer().emitCodeAlignment(2, &getSTI(), 0); + getStreamer().emitCodeAlignment(Align(2), &getSTI(), 0); else - getStreamer().emitValueToAlignment(2, 0, 1, 0); + getStreamer().emitValueToAlignment(Align(2), 0, 1, 0); return false; } diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp --- a/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -584,8 +584,7 @@ // Update the maximum alignment on the current section if necessary. MCSection *Sec = OS.getCurrentSectionOnly(); - if (AlignBoundary.value() > Sec->getAlignment()) - Sec->setAlignment(AlignBoundary); + Sec->ensureMinAlignment(AlignBoundary); } Optional X86AsmBackend::getFixupKind(StringRef Name) const { diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp --- a/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86WinCOFFTargetStreamer.cpp @@ -438,7 +438,7 @@ FSM.emitFrameDataRecord(OS, Inst.Label); } - OS.emitValueToAlignment(4, 0); + OS.emitValueToAlignment(Align(4), 0); OS.emitLabel(FrameEnd); return false; } diff --git a/llvm/lib/Target/X86/X86CallingConv.cpp b/llvm/lib/Target/X86/X86CallingConv.cpp --- a/llvm/lib/Target/X86/X86CallingConv.cpp +++ b/llvm/lib/Target/X86/X86CallingConv.cpp @@ -240,7 +240,7 @@ // This is similar to CCAssignToReg<[EAX, EDX, ECX]>, but makes sure // not to split i64 and double between a register and stack static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; - static const unsigned NumRegs = sizeof(RegList) / sizeof(RegList[0]); + static const unsigned NumRegs = std::size(RegList); SmallVectorImpl &PendingMembers = State.getPendingLocs(); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -13167,6 +13167,124 @@ return DAG.getVectorShuffle(VT, DL, Unpck, DAG.getUNDEF(VT), PermuteMask); } +/// Try to lower a shuffle as a permute of the inputs followed by an +/// UNPCK instruction. +/// +/// This specifically targets cases where we end up with alternating between +/// the two inputs, and so can permute them into something that feeds a single +/// UNPCK instruction. Note that this routine only targets integer vectors +/// because for floating point vectors we have a generalized SHUFPS lowering +/// strategy that handles everything that doesn't *exactly* match an unpack, +/// making this clever lowering unnecessary. +static SDValue lowerShuffleAsPermuteAndUnpack(const SDLoc &DL, MVT VT, + SDValue V1, SDValue V2, + ArrayRef Mask, + const X86Subtarget &Subtarget, + SelectionDAG &DAG) { + int Size = Mask.size(); + assert(Mask.size() >= 2 && "Single element masks are invalid."); + + // This routine only supports 128-bit integer dual input vectors. + if (VT.isFloatingPoint() || !VT.is128BitVector() || V2.isUndef()) + return SDValue(); + + int NumLoInputs = + count_if(Mask, [Size](int M) { return M >= 0 && M % Size < Size / 2; }); + int NumHiInputs = + count_if(Mask, [Size](int M) { return M % Size >= Size / 2; }); + + bool UnpackLo = NumLoInputs >= NumHiInputs; + + auto TryUnpack = [&](int ScalarSize, int Scale) { + SmallVector V1Mask((unsigned)Size, -1); + SmallVector V2Mask((unsigned)Size, -1); + + for (int i = 0; i < Size; ++i) { + if (Mask[i] < 0) + continue; + + // Each element of the unpack contains Scale elements from this mask. + int UnpackIdx = i / Scale; + + // We only handle the case where V1 feeds the first slots of the unpack. + // We rely on canonicalization to ensure this is the case. + if ((UnpackIdx % 2 == 0) != (Mask[i] < Size)) + return SDValue(); + + // Setup the mask for this input. The indexing is tricky as we have to + // handle the unpack stride. + SmallVectorImpl &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask; + VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] = + Mask[i] % Size; + } + + // If we will have to shuffle both inputs to use the unpack, check whether + // we can just unpack first and shuffle the result. If so, skip this unpack. + if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) && + !isNoopShuffleMask(V2Mask)) + return SDValue(); + + // Shuffle the inputs into place. + V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask); + V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask); + + // Cast the inputs to the type we will use to unpack them. + MVT UnpackVT = + MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), Size / Scale); + V1 = DAG.getBitcast(UnpackVT, V1); + V2 = DAG.getBitcast(UnpackVT, V2); + + // Unpack the inputs and cast the result back to the desired type. + return DAG.getBitcast( + VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL, + UnpackVT, V1, V2)); + }; + + // We try each unpack from the largest to the smallest to try and find one + // that fits this mask. + int OrigScalarSize = VT.getScalarSizeInBits(); + for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) + if (SDValue Unpack = TryUnpack(ScalarSize, ScalarSize / OrigScalarSize)) + return Unpack; + + // If we're shuffling with a zero vector then we're better off not doing + // VECTOR_SHUFFLE(UNPCK()) as we lose track of those zero elements. + if (ISD::isBuildVectorAllZeros(V1.getNode()) || + ISD::isBuildVectorAllZeros(V2.getNode())) + return SDValue(); + + // If none of the unpack-rooted lowerings worked (or were profitable) try an + // initial unpack. + if (NumLoInputs == 0 || NumHiInputs == 0) { + assert((NumLoInputs > 0 || NumHiInputs > 0) && + "We have to have *some* inputs!"); + int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0; + + // FIXME: We could consider the total complexity of the permute of each + // possible unpacking. Or at the least we should consider how many + // half-crossings are created. + // FIXME: We could consider commuting the unpacks. + + SmallVector PermMask((unsigned)Size, -1); + for (int i = 0; i < Size; ++i) { + if (Mask[i] < 0) + continue; + + assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!"); + + PermMask[i] = + 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1); + } + return DAG.getVectorShuffle( + VT, DL, + DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL, DL, VT, + V1, V2), + DAG.getUNDEF(VT), PermMask); + } + + return SDValue(); +} + /// Helper to form a PALIGNR-based rotate+permute, merging 2 inputs and then /// permuting the elements of the result in place. static SDValue lowerShuffleAsByteRotateAndPermute( @@ -13346,6 +13464,10 @@ if (SDValue BlendPerm = lowerShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG)) return BlendPerm; + if (VT.getScalarSizeInBits() >= 32) + if (SDValue PermUnpack = lowerShuffleAsPermuteAndUnpack( + DL, VT, V1, V2, Mask, Subtarget, DAG)) + return PermUnpack; } // If the final mask is an alternating blend of vXi8/vXi16, convert to an @@ -14846,123 +14968,6 @@ DAG.getTargetConstant(InsertPSMask, DL, MVT::i8)); } -/// Try to lower a shuffle as a permute of the inputs followed by an -/// UNPCK instruction. -/// -/// This specifically targets cases where we end up with alternating between -/// the two inputs, and so can permute them into something that feeds a single -/// UNPCK instruction. Note that this routine only targets integer vectors -/// because for floating point vectors we have a generalized SHUFPS lowering -/// strategy that handles everything that doesn't *exactly* match an unpack, -/// making this clever lowering unnecessary. -static SDValue lowerShuffleAsPermuteAndUnpack( - const SDLoc &DL, MVT VT, SDValue V1, SDValue V2, ArrayRef Mask, - const X86Subtarget &Subtarget, SelectionDAG &DAG) { - assert(!VT.isFloatingPoint() && - "This routine only supports integer vectors."); - assert(VT.is128BitVector() && - "This routine only works on 128-bit vectors."); - assert(!V2.isUndef() && - "This routine should only be used when blending two inputs."); - assert(Mask.size() >= 2 && "Single element masks are invalid."); - - int Size = Mask.size(); - - int NumLoInputs = - count_if(Mask, [Size](int M) { return M >= 0 && M % Size < Size / 2; }); - int NumHiInputs = - count_if(Mask, [Size](int M) { return M % Size >= Size / 2; }); - - bool UnpackLo = NumLoInputs >= NumHiInputs; - - auto TryUnpack = [&](int ScalarSize, int Scale) { - SmallVector V1Mask((unsigned)Size, -1); - SmallVector V2Mask((unsigned)Size, -1); - - for (int i = 0; i < Size; ++i) { - if (Mask[i] < 0) - continue; - - // Each element of the unpack contains Scale elements from this mask. - int UnpackIdx = i / Scale; - - // We only handle the case where V1 feeds the first slots of the unpack. - // We rely on canonicalization to ensure this is the case. - if ((UnpackIdx % 2 == 0) != (Mask[i] < Size)) - return SDValue(); - - // Setup the mask for this input. The indexing is tricky as we have to - // handle the unpack stride. - SmallVectorImpl &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask; - VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] = - Mask[i] % Size; - } - - // If we will have to shuffle both inputs to use the unpack, check whether - // we can just unpack first and shuffle the result. If so, skip this unpack. - if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) && - !isNoopShuffleMask(V2Mask)) - return SDValue(); - - // Shuffle the inputs into place. - V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask); - V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask); - - // Cast the inputs to the type we will use to unpack them. - MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), Size / Scale); - V1 = DAG.getBitcast(UnpackVT, V1); - V2 = DAG.getBitcast(UnpackVT, V2); - - // Unpack the inputs and cast the result back to the desired type. - return DAG.getBitcast( - VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL, - UnpackVT, V1, V2)); - }; - - // We try each unpack from the largest to the smallest to try and find one - // that fits this mask. - int OrigScalarSize = VT.getScalarSizeInBits(); - for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) - if (SDValue Unpack = TryUnpack(ScalarSize, ScalarSize / OrigScalarSize)) - return Unpack; - - // If we're shuffling with a zero vector then we're better off not doing - // VECTOR_SHUFFLE(UNPCK()) as we lose track of those zero elements. - if (ISD::isBuildVectorAllZeros(V1.getNode()) || - ISD::isBuildVectorAllZeros(V2.getNode())) - return SDValue(); - - // If none of the unpack-rooted lowerings worked (or were profitable) try an - // initial unpack. - if (NumLoInputs == 0 || NumHiInputs == 0) { - assert((NumLoInputs > 0 || NumHiInputs > 0) && - "We have to have *some* inputs!"); - int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0; - - // FIXME: We could consider the total complexity of the permute of each - // possible unpacking. Or at the least we should consider how many - // half-crossings are created. - // FIXME: We could consider commuting the unpacks. - - SmallVector PermMask((unsigned)Size, -1); - for (int i = 0; i < Size; ++i) { - if (Mask[i] < 0) - continue; - - assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!"); - - PermMask[i] = - 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1); - } - return DAG.getVectorShuffle( - VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL, - DL, VT, V1, V2), - DAG.getUNDEF(VT), PermMask); - } - - return SDValue(); -} - /// Handle lowering of 2-lane 64-bit floating point shuffles. /// /// This is the basis function for the 2-lane 64-bit shuffles as we have full @@ -48610,20 +48615,31 @@ // Make sure this is an AND with constant. We will check the value of the // constant later. - if (!isa(N->getOperand(1))) + auto *C1 = dyn_cast(N->getOperand(1)); + if (!C1) return SDValue(); // This is implied by the ConstantSDNode. assert(!VT.isVector() && "Expected scalar VT!"); - if (N->getOperand(0).getOpcode() != ISD::BITCAST || - !N->getOperand(0).hasOneUse() || - !N->getOperand(0).getOperand(0).hasOneUse()) + SDValue Src = N->getOperand(0); + if (!Src.hasOneUse()) return SDValue(); - const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - SDValue Src = N->getOperand(0).getOperand(0); + // (Optionally) peek through any_extend(). + if (Src.getOpcode() == ISD::ANY_EXTEND) { + if (!Src.getOperand(0).hasOneUse()) + return SDValue(); + Src = Src.getOperand(0); + } + + if (Src.getOpcode() != ISD::BITCAST || !Src.getOperand(0).hasOneUse()) + return SDValue(); + + Src = Src.getOperand(0); EVT SrcVT = Src.getValueType(); + + const TargetLowering &TLI = DAG.getTargetLoweringInfo(); if (!SrcVT.isVector() || SrcVT.getVectorElementType() != MVT::i1 || !TLI.isTypeLegal(SrcVT)) return SDValue(); @@ -48636,18 +48652,27 @@ SDValue SubVec = Src.getOperand(0); EVT SubVecVT = SubVec.getValueType(); - // First subvector should be a setcc with a legal result type. The RHS of the - // AND should be a mask with this many bits. - if (SubVec.getOpcode() != ISD::SETCC || !TLI.isTypeLegal(SubVecVT) || - !N->getConstantOperandAPInt(1).isMask(SubVecVT.getVectorNumElements())) + // The RHS of the AND should be a mask with as many bits as SubVec. + if (!TLI.isTypeLegal(SubVecVT) || + !C1->getAPIntValue().isMask(SubVecVT.getVectorNumElements())) return SDValue(); - EVT SetccVT = SubVec.getOperand(0).getValueType(); - if (!TLI.isTypeLegal(SetccVT) || - !(Subtarget.hasVLX() || SetccVT.is512BitVector())) - return SDValue(); - - if (!(Subtarget.hasBWI() || SetccVT.getScalarSizeInBits() >= 32)) + // First subvector should be a setcc with a legal result type or a + // AND containing at least one setcc with a legal result type. + auto IsLegalSetCC = [&](SDValue V) { + if (V.getOpcode() != ISD::SETCC) + return false; + EVT SetccVT = V.getOperand(0).getValueType(); + if (!TLI.isTypeLegal(SetccVT) || + !(Subtarget.hasVLX() || SetccVT.is512BitVector())) + return false; + if (!(Subtarget.hasBWI() || SetccVT.getScalarSizeInBits() >= 32)) + return false; + return true; + }; + if (!(IsLegalSetCC(SubVec) || (SubVec.getOpcode() == ISD::AND && + (IsLegalSetCC(SubVec.getOperand(0)) || + IsLegalSetCC(SubVec.getOperand(1)))))) return SDValue(); // We passed all the checks. Rebuild the concat_vectors with zeroes @@ -48658,7 +48683,8 @@ Ops[0] = SubVec; SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, Ops); - return DAG.getBitcast(VT, Concat); + EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcVT.getSizeInBits()); + return DAG.getZExtOrTrunc(DAG.getBitcast(IntVT, Concat), dl, VT); } static SDValue combineAnd(SDNode *N, SelectionDAG &DAG, diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -1580,7 +1580,7 @@ // First we emit the label and the jump. auto CurSled = OutContext.createTempSymbol("xray_event_sled_", true); OutStreamer->AddComment("# XRay Custom Event Log"); - OutStreamer->emitCodeAlignment(2, &getSubtargetInfo()); + OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo()); OutStreamer->emitLabel(CurSled); // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as @@ -1676,7 +1676,7 @@ // First we emit the label and the jump. auto CurSled = OutContext.createTempSymbol("xray_typed_event_sled_", true); OutStreamer->AddComment("# XRay Typed Event Log"); - OutStreamer->emitCodeAlignment(2, &getSubtargetInfo()); + OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo()); OutStreamer->emitLabel(CurSled); // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as @@ -1778,7 +1778,7 @@ // call // 5 bytes // auto CurSled = OutContext.createTempSymbol("xray_sled_", true); - OutStreamer->emitCodeAlignment(2, &getSubtargetInfo()); + OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo()); OutStreamer->emitLabel(CurSled); // Use a two-byte `jmp`. This version of JMP takes an 8-bit relative offset as @@ -1808,7 +1808,7 @@ // // This just makes sure that the alignment for the next instruction is 2. auto CurSled = OutContext.createTempSymbol("xray_sled_", true); - OutStreamer->emitCodeAlignment(2, &getSubtargetInfo()); + OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo()); OutStreamer->emitLabel(CurSled); unsigned OpCode = MI.getOperand(0).getImm(); MCInst Ret; @@ -1832,7 +1832,7 @@ // the PATCHABLE_FUNCTION_ENTER case, followed by the lowering of the actual // tail call much like how we have it in PATCHABLE_RET. auto CurSled = OutContext.createTempSymbol("xray_sled_", true); - OutStreamer->emitCodeAlignment(2, &getSubtargetInfo()); + OutStreamer->emitCodeAlignment(Align(2), &getSubtargetInfo()); OutStreamer->emitLabel(CurSled); auto Target = OutContext.createTempSymbol(); diff --git a/llvm/lib/Target/X86/X86ScheduleSLM.td b/llvm/lib/Target/X86/X86ScheduleSLM.td --- a/llvm/lib/Target/X86/X86ScheduleSLM.td +++ b/llvm/lib/Target/X86/X86ScheduleSLM.td @@ -408,10 +408,12 @@ // Vector insert/extract operations. defm : SLMWriteResPair; -def : WriteRes; +def : WriteRes { + let NumMicroOps = 2; +} def : WriteRes { let Latency = 4; - let NumMicroOps = 2; + let NumMicroOps = 5; let ResourceCycles = [1, 2]; } diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -955,9 +955,6 @@ } // PBLENDW. -// ymm -def : InstRW<[ZnWriteFPU013Y], (instrs VPBLENDWYrri)>; - // x,m,i / v,v,m,i def : InstRW<[ZnWriteFPU013Ld], (instregex "(V?)PBLENDWrmi")>; // y,m,i diff --git a/llvm/lib/Target/X86/X86ScheduleZnver2.td b/llvm/lib/Target/X86/X86ScheduleZnver2.td --- a/llvm/lib/Target/X86/X86ScheduleZnver2.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver2.td @@ -520,7 +520,7 @@ //-- Move instructions --// // MOV. // r16,m. -def : InstRW<[WriteALULd, ReadAfterLd], (instregex "MOV16rm")>; +def : InstRW<[WriteALULd, ReadAfterLd], (instrs MOV16rm)>; // XCHG. // r,r. @@ -545,7 +545,7 @@ let Latency = 5; let NumMicroOps = 2; } -def : InstRW<[Zn2WritePop16r], (instregex "POP16rmm")>; +def : InstRW<[Zn2WritePop16r], (instrs POP16rmm)>; def : InstRW<[WriteMicrocoded], (instregex "POPF(16|32)")>; def : InstRW<[WriteMicrocoded], (instregex "POPA(16|32)")>; @@ -785,16 +785,16 @@ // LD_F. // r. -def : InstRW<[Zn2WriteFLDr], (instregex "LD_Frr")>; +def : InstRW<[Zn2WriteFLDr], (instrs LD_Frr)>; // m. def Zn2WriteLD_F80m : SchedWriteRes<[Zn2AGU, Zn2FPU13]> { let NumMicroOps = 2; } -def : InstRW<[Zn2WriteLD_F80m], (instregex "LD_F80m")>; +def : InstRW<[Zn2WriteLD_F80m], (instrs LD_F80m)>; // FBLD. -def : InstRW<[WriteMicrocoded], (instregex "FBLDm")>; +def : InstRW<[WriteMicrocoded], (instrs FBLDm)>; // FST(P). // r. @@ -804,11 +804,11 @@ def Zn2WriteST_FP80m : SchedWriteRes<[Zn2AGU, Zn2FPU23]> { let Latency = 5; } -def : InstRW<[Zn2WriteST_FP80m], (instregex "ST_FP80m")>; +def : InstRW<[Zn2WriteST_FP80m], (instrs ST_FP80m)>; // FBSTP. // m80. -def : InstRW<[WriteMicrocoded], (instregex "FBSTPm")>; +def : InstRW<[WriteMicrocoded], (instrs FBSTPm)>; def Zn2WriteFXCH : SchedWriteRes<[Zn2FPU]>; @@ -865,10 +865,10 @@ def : InstRW<[Zn2WriteFPU3], (instregex "FFREE")>; // FNSAVE. -def : InstRW<[WriteMicrocoded], (instregex "FSAVEm")>; +def : InstRW<[WriteMicrocoded], (instrs FSAVEm)>; // FRSTOR. -def : InstRW<[WriteMicrocoded], (instregex "FRSTORm")>; +def : InstRW<[WriteMicrocoded], (instrs FRSTORm)>; //-- Arithmetic instructions --// @@ -963,9 +963,6 @@ } // PBLENDW. -// ymm -def : InstRW<[Zn2WriteFPU013Y], (instrs VPBLENDWYrri)>; - // x,m,i / v,v,m,i def : InstRW<[Zn2WriteFPU013Ld], (instregex "(V?)PBLENDWrmi")>; // y,m,i @@ -1324,46 +1321,46 @@ // SHA1MSG2 // x,x. def Zn2WriteSHA1MSG2r : SchedWriteRes<[Zn2FPU12]> ; -def : InstRW<[Zn2WriteSHA1MSG2r], (instregex "SHA1MSG2rr")>; +def : InstRW<[Zn2WriteSHA1MSG2r], (instrs SHA1MSG2rr)>; // x,m. def Zn2WriteSHA1MSG2Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> { let Latency = 8; } -def : InstRW<[Zn2WriteSHA1MSG2Ld], (instregex "SHA1MSG2rm")>; +def : InstRW<[Zn2WriteSHA1MSG2Ld], (instrs SHA1MSG2rm)>; // SHA1NEXTE // x,x. def Zn2WriteSHA1NEXTEr : SchedWriteRes<[Zn2FPU1]> ; -def : InstRW<[Zn2WriteSHA1NEXTEr], (instregex "SHA1NEXTErr")>; +def : InstRW<[Zn2WriteSHA1NEXTEr], (instrs SHA1NEXTErr)>; // x,m. def Zn2WriteSHA1NEXTELd : SchedWriteRes<[Zn2AGU, Zn2FPU1]> { let Latency = 8; } -def : InstRW<[Zn2WriteSHA1NEXTELd], (instregex "SHA1NEXTErm")>; +def : InstRW<[Zn2WriteSHA1NEXTELd], (instrs SHA1NEXTErm)>; // SHA1RNDS4 // x,x. def Zn2WriteSHA1RNDS4r : SchedWriteRes<[Zn2FPU1]> { let Latency = 6; } -def : InstRW<[Zn2WriteSHA1RNDS4r], (instregex "SHA1RNDS4rr")>; +def : InstRW<[Zn2WriteSHA1RNDS4r], (instrs SHA1RNDS4rri)>; // x,m. def Zn2WriteSHA1RNDS4Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> { let Latency = 13; } -def : InstRW<[Zn2WriteSHA1RNDS4Ld], (instregex "SHA1RNDS4rm")>; +def : InstRW<[Zn2WriteSHA1RNDS4Ld], (instrs SHA1RNDS4rmi)>; // SHA256RNDS2 // x,x. def Zn2WriteSHA256RNDS2r : SchedWriteRes<[Zn2FPU1]> { let Latency = 4; } -def : InstRW<[Zn2WriteSHA256RNDS2r], (instregex "SHA256RNDS2rr")>; +def : InstRW<[Zn2WriteSHA256RNDS2r], (instrs SHA256RNDS2rr)>; // x,m. def Zn2WriteSHA256RNDS2Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> { let Latency = 11; } -def : InstRW<[Zn2WriteSHA256RNDS2Ld], (instregex "SHA256RNDS2rm")>; +def : InstRW<[Zn2WriteSHA256RNDS2Ld], (instrs SHA256RNDS2rm)>; //-- Arithmetic instructions --// diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp --- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp +++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp @@ -57,6 +57,7 @@ #include #include #include +#include #include using namespace llvm; @@ -164,7 +165,7 @@ const X86InstrInfo *TII = nullptr; const TargetRegisterInfo *TRI = nullptr; - Optional PS; + std::optional PS; void hardenEdgesWithLFENCE(MachineFunction &MF); diff --git a/llvm/lib/Testing/Support/CMakeLists.txt b/llvm/lib/Testing/Support/CMakeLists.txt --- a/llvm/lib/Testing/Support/CMakeLists.txt +++ b/llvm/lib/Testing/Support/CMakeLists.txt @@ -1,3 +1,7 @@ +# Do not build unittest libraries automatically, they will be pulled in +# by unittests if these are built. +set(EXCLUDE_FROM_ALL ON) + add_llvm_library(LLVMTestingSupport Annotations.cpp Error.cpp diff --git a/llvm/lib/Transforms/Coroutines/CoroElide.cpp b/llvm/lib/Transforms/Coroutines/CoroElide.cpp --- a/llvm/lib/Transforms/Coroutines/CoroElide.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroElide.cpp @@ -16,6 +16,7 @@ #include "llvm/IR/InstIterator.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FileSystem.h" +#include using namespace llvm; @@ -101,7 +102,8 @@ // Given a resume function @f.resume(%f.frame* %frame), returns the size // and expected alignment of %f.frame type. -static Optional> getFrameLayout(Function *Resume) { +static std::optional> +getFrameLayout(Function *Resume) { // Pull information from the function attributes. auto Size = Resume->getParamDereferenceableBytes(0); if (!Size) diff --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp --- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp @@ -37,6 +37,7 @@ #include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Utils/PromoteMemToReg.h" #include +#include using namespace llvm; @@ -1137,7 +1138,7 @@ FrameTypeBuilder B(C, DL, MaxFrameAlignment); AllocaInst *PromiseAlloca = Shape.getPromiseAlloca(); - Optional SwitchIndexFieldId; + std::optional SwitchIndexFieldId; if (Shape.ABI == coro::ABI::Switch) { auto *FramePtrTy = FrameTy->getPointerTo(); diff --git a/llvm/lib/Transforms/IPO/Attributor.cpp b/llvm/lib/Transforms/IPO/Attributor.cpp --- a/llvm/lib/Transforms/IPO/Attributor.cpp +++ b/llvm/lib/Transforms/IPO/Attributor.cpp @@ -54,6 +54,7 @@ #endif #include +#include #include using namespace llvm; @@ -737,7 +738,7 @@ // values and the ones in callbacks. If a callback was found that makes use // of the underlying call site operand, we want the corresponding callback // callee argument and not the direct callee argument. - Optional CBCandidateArg; + std::optional CBCandidateArg; SmallVector CallbackUses; const auto &CB = cast(getAnchorValue()); AbstractCallSite::getCallbackUses(CB, CallbackUses); diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp --- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp +++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp @@ -62,6 +62,7 @@ #include "llvm/Transforms/Utils/ValueMapper.h" #include #include +#include using namespace llvm; @@ -6153,7 +6154,7 @@ LoopInfo *LI = A.getInfoCache().getAnalysisResultForFunction(*F); - Optional MayContainIrreducibleControl; + std::optional MayContainIrreducibleControl; auto IsInLoop = [&](BasicBlock &BB) { if (&F->getEntryBlock() == &BB) return false; diff --git a/llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp b/llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp --- a/llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp +++ b/llvm/lib/Transforms/IPO/DeadArgumentElimination.cpp @@ -1056,7 +1056,7 @@ // value (possibly 0 if we became void). auto *NewRet = ReturnInst::Create(F->getContext(), RetVal, RI); NewRet->setDebugLoc(RI->getDebugLoc()); - BB.getInstList().erase(RI); + RI->eraseFromParent(); } // Clone metadata from the old function, including debug info descriptor. diff --git a/llvm/lib/Transforms/IPO/GlobalOpt.cpp b/llvm/lib/Transforms/IPO/GlobalOpt.cpp --- a/llvm/lib/Transforms/IPO/GlobalOpt.cpp +++ b/llvm/lib/Transforms/IPO/GlobalOpt.cpp @@ -68,6 +68,7 @@ #include "llvm/Transforms/Utils/Local.h" #include #include +#include #include #include @@ -2468,7 +2469,7 @@ SmallPtrSet NotDiscardableComdats; bool Changed = false; bool LocalChange = true; - Optional FirstNotFullyEvaluatedPriority; + std::optional FirstNotFullyEvaluatedPriority; while (LocalChange) { LocalChange = false; diff --git a/llvm/lib/Transforms/IPO/IROutliner.cpp b/llvm/lib/Transforms/IPO/IROutliner.cpp --- a/llvm/lib/Transforms/IPO/IROutliner.cpp +++ b/llvm/lib/Transforms/IPO/IROutliner.cpp @@ -26,6 +26,7 @@ #include "llvm/Pass.h" #include "llvm/Support/CommandLine.h" #include "llvm/Transforms/IPO.h" +#include #include #define DEBUG_TYPE "iroutliner" @@ -133,7 +134,7 @@ /// The argument that needs to be marked with the swifterr attribute. If not /// needed, there is no value. - Optional SwiftErrorArgument; + std::optional SwiftErrorArgument; /// For the \ref Regions, we look at every Value. If it is a constant, /// we check whether it is the same in Region. @@ -2671,7 +2672,7 @@ LoadInst *LI) { // For and load instructions following the call Value *Operand = LI->getPointerOperand(); - Optional OutputIdx; + std::optional OutputIdx; // Find if the operand it is an output register. for (unsigned ArgIdx = Region.NumExtractedInputs; ArgIdx < Region.Call->arg_size(); ArgIdx++) { diff --git a/llvm/lib/Transforms/IPO/Inliner.cpp b/llvm/lib/Transforms/IPO/Inliner.cpp --- a/llvm/lib/Transforms/IPO/Inliner.cpp +++ b/llvm/lib/Transforms/IPO/Inliner.cpp @@ -109,7 +109,9 @@ EnablePostSCCAdvisorPrinting("enable-scc-inline-advisor-printing", cl::init(false), cl::Hidden); +namespace llvm { extern cl::opt InlinerFunctionImportStats; +} static cl::opt CGSCCInlineReplayFile( "cgscc-inline-replay", cl::init(""), cl::value_desc("filename"), diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp @@ -167,6 +167,8 @@ New->setMetadata(LLVMContext::MD_DIAssignID, AI.getMetadata(LLVMContext::MD_DIAssignID)); + replaceAllDbgUsesWith(AI, *New, *New, DT); + // If the allocation has multiple real uses, insert a cast and change all // things that used it to use the new cast. This will also hack on CI, but it // will die soon. diff --git a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp @@ -169,7 +169,7 @@ } static Instruction *simplifyAllocaArraySize(InstCombinerImpl &IC, - AllocaInst &AI) { + AllocaInst &AI, DominatorTree &DT) { // Check for array size of 1 (scalar allocation). if (!AI.isArrayAllocation()) { // i32 1 is the canonical array size for scalar allocations. @@ -188,6 +188,8 @@ nullptr, AI.getName()); New->setAlignment(AI.getAlign()); + replaceAllDbgUsesWith(AI, *New, *New, DT); + // Scan to the end of the allocation instructions, to skip over a block of // allocas if possible...also skip interleaved debug info // @@ -356,7 +358,7 @@ } Instruction *InstCombinerImpl::visitAllocaInst(AllocaInst &AI) { - if (auto *I = simplifyAllocaArraySize(*this, AI)) + if (auto *I = simplifyAllocaArraySize(*this, AI, DT)) return I; if (AI.getAllocatedType()->isSized()) { diff --git a/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp b/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombinePHI.cpp @@ -20,6 +20,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Transforms/InstCombine/InstCombiner.h" #include "llvm/Transforms/Utils/Local.h" +#include using namespace llvm; using namespace llvm::PatternMatch; @@ -1328,7 +1329,7 @@ // Check that edges outgoing from the idom's terminators dominate respective // inputs of the Phi. - Optional Invert; + std::optional Invert; for (auto Pair : zip(PN.incoming_values(), PN.blocks())) { auto *Input = cast(std::get<0>(Pair)); BasicBlock *Pred = std::get<1>(Pair); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp @@ -187,12 +187,12 @@ ElementCount NumElts = cast(Ext.getVectorOperandType())->getElementCount(); Type *DestTy = Ext.getType(); + unsigned DestWidth = DestTy->getPrimitiveSizeInBits(); bool IsBigEndian = DL.isBigEndian(); // If we are casting an integer to vector and extracting a portion, that is // a shift-right and truncate. - if (X->getType()->isIntegerTy() && - isDesirableIntType(X->getType()->getPrimitiveSizeInBits())) { + if (X->getType()->isIntegerTy()) { assert(isa(Ext.getVectorOperand()->getType()) && "Expected fixed vector type for bitcast from scalar integer"); @@ -201,16 +201,18 @@ // BigEndian: extelt (bitcast i32 X to v4i8), 0 -> trunc i32 (X >> 24) to i8 if (IsBigEndian) ExtIndexC = NumElts.getKnownMinValue() - 1 - ExtIndexC; - unsigned ShiftAmountC = ExtIndexC * DestTy->getPrimitiveSizeInBits(); - if (!ShiftAmountC || Ext.getVectorOperand()->hasOneUse()) { - Value *Lshr = Builder.CreateLShr(X, ShiftAmountC, "extelt.offset"); + unsigned ShiftAmountC = ExtIndexC * DestWidth; + if (!ShiftAmountC || + (isDesirableIntType(X->getType()->getPrimitiveSizeInBits()) && + Ext.getVectorOperand()->hasOneUse())) { + if (ShiftAmountC) + X = Builder.CreateLShr(X, ShiftAmountC, "extelt.offset"); if (DestTy->isFloatingPointTy()) { - Type *DstIntTy = IntegerType::getIntNTy( - Lshr->getContext(), DestTy->getPrimitiveSizeInBits()); - Value *Trunc = Builder.CreateTrunc(Lshr, DstIntTy); + Type *DstIntTy = IntegerType::getIntNTy(X->getContext(), DestWidth); + Value *Trunc = Builder.CreateTrunc(X, DstIntTy); return new BitCastInst(Trunc, DestTy); } - return new TruncInst(Lshr, DestTy); + return new TruncInst(X, DestTy); } } @@ -283,7 +285,6 @@ return nullptr; unsigned SrcWidth = SrcTy->getScalarSizeInBits(); - unsigned DestWidth = DestTy->getPrimitiveSizeInBits(); unsigned ShAmt = Chunk * DestWidth; // TODO: This limitation is more strict than necessary. We could sum the diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -110,6 +110,7 @@ #define DEBUG_TYPE "instcombine" #include "llvm/Transforms/Utils/InstructionWorklist.h" +#include using namespace llvm; using namespace llvm::PatternMatch; @@ -4244,7 +4245,7 @@ // prove that the successor is not executed more frequently than our block. // Return the UserBlock if successful. auto getOptionalSinkBlockForInst = - [this](Instruction *I) -> Optional { + [this](Instruction *I) -> std::optional { if (!EnableCodeSinking) return None; diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp --- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp @@ -357,14 +357,14 @@ /// If WithFrameRecord is true, then __hwasan_tls will be used to access the /// ring buffer for storing stack allocations on targets that support it. struct ShadowMapping { - int Scale; + uint8_t Scale; uint64_t Offset; bool InGlobal; bool InTls; bool WithFrameRecord; void init(Triple &TargetTriple, bool InstrumentWithCalls); - uint64_t getObjectAlignment() const { return 1ULL << Scale; } + Align getObjectAlignment() const { return Align(1ULL << Scale); } }; ShadowMapping Mapping; @@ -959,7 +959,7 @@ IRBuilder<> IRB(O.getInsn()); if (isPowerOf2_64(O.TypeSize) && (O.TypeSize / 8 <= (1ULL << (kNumberOfAccessSizes - 1))) && - (!O.Alignment || *O.Alignment >= (1ULL << Mapping.Scale) || + (!O.Alignment || *O.Alignment >= Mapping.getObjectAlignment() || *O.Alignment >= O.TypeSize / 8)) { size_t AccessSizeIndex = TypeSizeToSizeIndex(O.TypeSize); if (InstrumentWithCalls) { @@ -1003,9 +1003,9 @@ if (ShadowSize) IRB.CreateMemSet(ShadowPtr, JustTag, ShadowSize, Align(1)); if (Size != AlignedSize) { - IRB.CreateStore( - ConstantInt::get(Int8Ty, Size % Mapping.getObjectAlignment()), - IRB.CreateConstGEP1_32(Int8Ty, ShadowPtr, ShadowSize)); + const uint8_t SizeRemainder = Size % Mapping.getObjectAlignment().value(); + IRB.CreateStore(ConstantInt::get(Int8Ty, SizeRemainder), + IRB.CreateConstGEP1_32(Int8Ty, ShadowPtr, ShadowSize)); IRB.CreateStore(JustTag, IRB.CreateConstGEP1_32( Int8Ty, IRB.CreateBitCast(AI, Int8PtrTy), AlignedSize - 1)); @@ -1031,7 +1031,7 @@ 48, 16, 120, 248, 56, 24, 8, 124, 252, 60, 28, 12, 4, 126, 254, 62, 30, 14, 6, 2, 127, 63, 31, 15, 7, 3, 1}; - return FastMasks[AllocaNo % (sizeof(FastMasks) / sizeof(FastMasks[0]))]; + return FastMasks[AllocaNo % std::size(FastMasks)]; } Value *HWAddressSanitizer::applyTagMask(IRBuilder<> &IRB, Value *OldTag) { @@ -1386,7 +1386,7 @@ for (auto &II : Info.LifetimeEnd) II->eraseFromParent(); } - memtag::alignAndPadAlloca(Info, Align(Mapping.getObjectAlignment())); + memtag::alignAndPadAlloca(Info, Mapping.getObjectAlignment()); } for (auto &I : SInfo.UnrecognizedLifetimes) I->eraseFromParent(); @@ -1512,7 +1512,7 @@ NewGV->setLinkage(GlobalValue::PrivateLinkage); NewGV->copyMetadata(GV, 0); NewGV->setAlignment( - MaybeAlign(std::max(GV->getAlignment(), Mapping.getObjectAlignment()))); + std::max(GV->getAlign().valueOrOne(), Mapping.getObjectAlignment())); // It is invalid to ICF two globals that have different tags. In the case // where the size of the global is a multiple of the tag granularity the diff --git a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp --- a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp +++ b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp @@ -44,6 +44,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils/Local.h" #include +#include #include using namespace llvm; @@ -729,7 +730,7 @@ // What is the smallest bit width that can accommodate the entire value ranges // of both of the operands? - std::array, 2> CRs; + std::array, 2> CRs; unsigned MinSignedBits = 0; for (auto I : zip(Instr->operands(), CRs)) { std::get<1>(I) = LVI->getConstantRange(std::get<0>(I), Instr); diff --git a/llvm/lib/Transforms/Scalar/GVN.cpp b/llvm/lib/Transforms/Scalar/GVN.cpp --- a/llvm/lib/Transforms/Scalar/GVN.cpp +++ b/llvm/lib/Transforms/Scalar/GVN.cpp @@ -76,6 +76,7 @@ #include #include #include +#include #include using namespace llvm; @@ -809,7 +810,7 @@ BasicBlock *BB, DenseMap &FullyAvailableBlocks) { SmallVector Worklist; - Optional UnavailableBB; + std::optional UnavailableBB; // The number of times we didn't find an entry for a block in a map and // optimistically inserted an entry marking block as speculatively available. @@ -1121,7 +1122,7 @@ /// basic block, before the pointer select. /// 3. There must be no instructions between the found loads and \p End that may /// clobber the loads. -static Optional +static std::optional tryToConvertLoadOfPtrSelect(BasicBlock *DepBB, BasicBlock::iterator End, Value *Address, Type *LoadTy, DominatorTree &DT, AAResults *AA) { diff --git a/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp b/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp --- a/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp +++ b/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp @@ -93,6 +93,7 @@ #include #include #include +#include #include #include @@ -547,8 +548,8 @@ // space of the main loop. struct SubRanges { - Optional LowLimit; - Optional HighLimit; + std::optional LowLimit; + std::optional HighLimit; }; // Compute a safe set of limits for the main loop to run in -- effectively the diff --git a/llvm/lib/Transforms/Scalar/LoopFlatten.cpp b/llvm/lib/Transforms/Scalar/LoopFlatten.cpp --- a/llvm/lib/Transforms/Scalar/LoopFlatten.cpp +++ b/llvm/lib/Transforms/Scalar/LoopFlatten.cpp @@ -75,6 +75,7 @@ #include "llvm/Transforms/Utils/LoopUtils.h" #include "llvm/Transforms/Utils/ScalarEvolutionExpander.h" #include "llvm/Transforms/Utils/SimplifyIndVar.h" +#include using namespace llvm; using namespace llvm::PatternMatch; @@ -913,7 +914,7 @@ bool Changed = false; - Optional MSSAU; + std::optional MSSAU; if (AR.MSSA) { MSSAU = MemorySSAUpdater(AR.MSSA); if (VerifyMemorySSA) @@ -983,7 +984,7 @@ auto *AC = &getAnalysis().getAssumptionCache(F); auto *MSSA = getAnalysisIfAvailable(); - Optional MSSAU; + std::optional MSSAU; if (MSSA) MSSAU = MemorySSAUpdater(&MSSA->getMSSA()); diff --git a/llvm/lib/Transforms/Scalar/LoopInstSimplify.cpp b/llvm/lib/Transforms/Scalar/LoopInstSimplify.cpp --- a/llvm/lib/Transforms/Scalar/LoopInstSimplify.cpp +++ b/llvm/lib/Transforms/Scalar/LoopInstSimplify.cpp @@ -35,6 +35,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Utils/LoopUtils.h" +#include #include using namespace llvm; @@ -214,7 +215,7 @@ PreservedAnalyses LoopInstSimplifyPass::run(Loop &L, LoopAnalysisManager &AM, LoopStandardAnalysisResults &AR, LPMUpdater &) { - Optional MSSAU; + std::optional MSSAU; if (AR.MSSA) { MSSAU = MemorySSAUpdater(AR.MSSA); if (VerifyMemorySSA) diff --git a/llvm/lib/Transforms/Scalar/LoopPredication.cpp b/llvm/lib/Transforms/Scalar/LoopPredication.cpp --- a/llvm/lib/Transforms/Scalar/LoopPredication.cpp +++ b/llvm/lib/Transforms/Scalar/LoopPredication.cpp @@ -200,6 +200,7 @@ #include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Utils/LoopUtils.h" #include "llvm/Transforms/Utils/ScalarEvolutionExpander.h" +#include #define DEBUG_TYPE "loop-predication" @@ -482,10 +483,10 @@ // Return an LoopICmp describing a latch check equivlent to LatchCheck but with // the requested type if safe to do so. May involve the use of a new IV. -static Optional generateLoopLatchCheck(const DataLayout &DL, - ScalarEvolution &SE, - const LoopICmp LatchCheck, - Type *RangeCheckType) { +static std::optional generateLoopLatchCheck(const DataLayout &DL, + ScalarEvolution &SE, + const LoopICmp LatchCheck, + Type *RangeCheckType) { auto *LatchType = LatchCheck.IV->getType(); if (RangeCheckType == LatchType) diff --git a/llvm/lib/Transforms/Scalar/LoopRotation.cpp b/llvm/lib/Transforms/Scalar/LoopRotation.cpp --- a/llvm/lib/Transforms/Scalar/LoopRotation.cpp +++ b/llvm/lib/Transforms/Scalar/LoopRotation.cpp @@ -25,6 +25,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils/LoopRotationUtils.h" #include "llvm/Transforms/Utils/LoopUtils.h" +#include using namespace llvm; #define DEBUG_TYPE "loop-rotate" @@ -55,7 +56,7 @@ const DataLayout &DL = L.getHeader()->getModule()->getDataLayout(); const SimplifyQuery SQ = getBestSimplifyQuery(AR, DL); - Optional MSSAU; + std::optional MSSAU; if (AR.MSSA) MSSAU = MemorySSAUpdater(AR.MSSA); bool Changed = LoopRotation(&L, &AR.LI, &AR.TTI, &AR.AC, &AR.DT, &AR.SE, @@ -116,7 +117,7 @@ auto &DT = getAnalysis().getDomTree(); auto &SE = getAnalysis().getSE(); const SimplifyQuery SQ = getBestSimplifyQuery(*this, F); - Optional MSSAU; + std::optional MSSAU; // Not requiring MemorySSA and getting it only if available will split // the loop pass pipeline when LoopRotate is being run first. auto *MSSAA = getAnalysisIfAvailable(); diff --git a/llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp b/llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp --- a/llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp +++ b/llvm/lib/Transforms/Scalar/LoopSimplifyCFG.cpp @@ -32,6 +32,7 @@ #include "llvm/Transforms/Scalar/LoopPassManager.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/LoopUtils.h" +#include using namespace llvm; #define DEBUG_TYPE "loop-simplifycfg" @@ -717,7 +718,7 @@ PreservedAnalyses LoopSimplifyCFGPass::run(Loop &L, LoopAnalysisManager &AM, LoopStandardAnalysisResults &AR, LPMUpdater &LPMU) { - Optional MSSAU; + std::optional MSSAU; if (AR.MSSA) MSSAU = MemorySSAUpdater(AR.MSSA); bool DeleteCurrentLoop = false; @@ -750,7 +751,7 @@ LoopInfo &LI = getAnalysis().getLoopInfo(); ScalarEvolution &SE = getAnalysis().getSE(); auto *MSSAA = getAnalysisIfAvailable(); - Optional MSSAU; + std::optional MSSAU; if (MSSAA) MSSAU = MemorySSAUpdater(&MSSAA->getMSSA()); if (MSSAA && VerifyMemorySSA) diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp --- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp +++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp @@ -124,6 +124,7 @@ #include #include #include +#include #include using namespace llvm; @@ -6614,7 +6615,7 @@ return nullptr; } -static Optional>> +static std::optional>> canFoldTermCondOfLoop(Loop *L, ScalarEvolution &SE, DominatorTree &DT, const LoopInfo &LI) { if (!L->isInnermost()) { diff --git a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp --- a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp +++ b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp @@ -64,6 +64,7 @@ #include #include #include +#include #include #include #include @@ -772,7 +773,7 @@ } }; -static Optional +static std::optional shouldPragmaUnroll(Loop *L, const PragmaInfo &PInfo, const unsigned TripMultiple, const unsigned TripCount, const UnrollCostEstimator UCE, @@ -800,7 +801,7 @@ return None; } -static Optional shouldFullUnroll( +static std::optional shouldFullUnroll( Loop *L, const TargetTransformInfo &TTI, DominatorTree &DT, ScalarEvolution &SE, const SmallPtrSetImpl &EphValues, const unsigned FullUnrollTripCount, const UnrollCostEstimator UCE, @@ -830,7 +831,7 @@ return None; } -static Optional +static std::optional shouldPartialUnroll(const unsigned LoopSize, const unsigned TripCount, const UnrollCostEstimator UCE, const TargetTransformInfo::UnrollingPreferences &UP) { diff --git a/llvm/lib/Transforms/Scalar/LowerConstantIntrinsics.cpp b/llvm/lib/Transforms/Scalar/LowerConstantIntrinsics.cpp --- a/llvm/lib/Transforms/Scalar/LowerConstantIntrinsics.cpp +++ b/llvm/lib/Transforms/Scalar/LowerConstantIntrinsics.cpp @@ -31,6 +31,7 @@ #include "llvm/Pass.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils/Local.h" +#include using namespace llvm; using namespace llvm::PatternMatch; @@ -96,7 +97,7 @@ static bool lowerConstantIntrinsics(Function &F, const TargetLibraryInfo &TLI, DominatorTree *DT) { - Optional DTU; + std::optional DTU; if (DT) DTU.emplace(DT, DomTreeUpdater::UpdateStrategy::Lazy); diff --git a/llvm/lib/Transforms/Scalar/PartiallyInlineLibCalls.cpp b/llvm/lib/Transforms/Scalar/PartiallyInlineLibCalls.cpp --- a/llvm/lib/Transforms/Scalar/PartiallyInlineLibCalls.cpp +++ b/llvm/lib/Transforms/Scalar/PartiallyInlineLibCalls.cpp @@ -22,6 +22,7 @@ #include "llvm/Support/DebugCounter.h" #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" +#include using namespace llvm; @@ -103,7 +104,7 @@ static bool runPartiallyInlineLibCalls(Function &F, TargetLibraryInfo *TLI, const TargetTransformInfo *TTI, DominatorTree *DT) { - Optional DTU; + std::optional DTU; if (DT) DTU.emplace(DT, DomTreeUpdater::UpdateStrategy::Lazy); diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp --- a/llvm/lib/Transforms/Scalar/SROA.cpp +++ b/llvm/lib/Transforms/Scalar/SROA.cpp @@ -113,6 +113,121 @@ cl::Hidden); namespace { +constexpr uint64_t ByteWidth = 8; +static uint64_t bitsToBytes(uint64_t Bits) { + assert(Bits % 8 == 0 && "unexpected bit count"); + return Bits / ByteWidth; +} +static uint64_t bytesToBits(uint64_t Bytes) { + assert(Bytes <= (UINT64_MAX / ByteWidth) && "too many bytes"); + return Bytes * ByteWidth; +} + +/// Find linked dbg.assign and generate a new one with the correct +/// FragmentInfo. Link Inst to the new dbg.assign. If Value is nullptr the +/// value component is copied from the old dbg.assign to the new. +/// \param OldAlloca Alloca for the variable before splitting. +/// \param RelativeOffsetInBytes Offset into \p OldAlloca relative to the +/// offset prior to splitting (change in offset). +/// \param SliceSizeInBytes New number of bytes being written to. +/// \param OldInst Instruction that is being split. +/// \param Inst New instruction performing this part of the +/// split store. +/// \param Dest Store destination. +/// \param Value Stored value. +/// \param DL Datalayout. +static void migrateDebugInfo(AllocaInst *OldAlloca, + uint64_t RelativeOffsetInBytes, + uint64_t SliceSizeInBytes, Instruction *OldInst, + Instruction *Inst, Value *Dest, Value *Value, + const DataLayout &DL) { + auto MarkerRange = at::getAssignmentMarkers(OldInst); + // Nothing to do if OldInst has no linked dbg.assign intrinsics. + if (MarkerRange.empty()) + return; + + uint64_t RelativeOffset = bytesToBits(RelativeOffsetInBytes); + uint64_t SliceSize = bytesToBits(SliceSizeInBytes); + + LLVM_DEBUG(dbgs() << " migrateDebugInfo\n"); + LLVM_DEBUG(dbgs() << " OldAlloca: " << *OldAlloca << "\n"); + LLVM_DEBUG(dbgs() << " RelativeOffset: " << RelativeOffset << "\n"); + LLVM_DEBUG(dbgs() << " SliceSize: " << SliceSize << "\n"); + LLVM_DEBUG(dbgs() << " OldInst: " << *OldInst << "\n"); + LLVM_DEBUG(dbgs() << " Inst: " << *Inst << "\n"); + LLVM_DEBUG(dbgs() << " Dest: " << *Dest << "\n"); + if (Value) + LLVM_DEBUG(dbgs() << " Value: " << *Value << "\n"); + + // The new inst needs a DIAssignID unique metadata tag (if OldInst has + // one). It shouldn't already have one: assert this assumption. + assert(!Inst->getMetadata(LLVMContext::MD_DIAssignID)); + DIAssignID *NewID = nullptr; + auto &Ctx = Inst->getContext(); + DIBuilder DIB(*OldInst->getModule(), /*AllowUnresolved*/ false); + uint64_t AllocaSize = *OldAlloca->getAllocationSizeInBits(DL); + assert(OldAlloca->isStaticAlloca()); + for (DbgAssignIntrinsic *DbgAssign : MarkerRange) { + LLVM_DEBUG(dbgs() << " existing dbg.assign is: " << *DbgAssign + << "\n"); + auto *Expr = DbgAssign->getExpression(); + + // Check if the dbg.assign already describes a fragment. + auto GetCurrentFragSize = [AllocaSize, DbgAssign, Expr]() -> uint64_t { + if (auto FI = Expr->getFragmentInfo()) + return FI->SizeInBits; + if (auto VarSize = DbgAssign->getVariable()->getSizeInBits()) + return *VarSize; + // The variable type has an unspecified size. This can happen in the + // case of DW_TAG_unspecified_type types, e.g. std::nullptr_t. Because + // there is no fragment and we do not know the size of the variable type, + // we'll guess by looking at the alloca. + return AllocaSize; + }; + uint64_t CurrentFragSize = GetCurrentFragSize(); + bool MakeNewFragment = CurrentFragSize != SliceSize; + assert(MakeNewFragment || RelativeOffset == 0); + + assert(SliceSize <= AllocaSize); + if (MakeNewFragment) { + assert(RelativeOffset + SliceSize <= CurrentFragSize); + auto E = DIExpression::createFragmentExpression(Expr, RelativeOffset, + SliceSize); + assert(E && "Failed to create fragment expr!"); + Expr = *E; + } + + // If we haven't created a DIAssignID ID do that now and attach it to Inst. + if (!NewID) { + NewID = DIAssignID::getDistinct(Ctx); + Inst->setMetadata(LLVMContext::MD_DIAssignID, NewID); + } + + Value = Value ? Value : DbgAssign->getValue(); + auto *NewAssign = DIB.insertDbgAssign( + Inst, Value, DbgAssign->getVariable(), Expr, Dest, + DIExpression::get(Ctx, None), DbgAssign->getDebugLoc()); + + // We could use more precision here at the cost of some additional (code) + // complexity - if the original dbg.assign was adjacent to its store, we + // could position this new dbg.assign adjacent to its store rather than the + // old dbg.assgn. That would result in interleaved dbg.assigns rather than + // what we get now: + // split store !1 + // split store !2 + // dbg.assign !1 + // dbg.assign !2 + // This (current behaviour) results results in debug assignments being + // noted as slightly offset (in code) from the store. In practice this + // should have little effect on the debugging experience due to the fact + // that all the split stores should get the same line number. + NewAssign->moveBefore(DbgAssign); + + NewAssign->setDebugLoc(DbgAssign->getDebugLoc()); + LLVM_DEBUG(dbgs() << "Created new assign intrinsic: " << *NewAssign + << "\n"); + } +} /// A custom IRBuilder inserter which prefixes all names, but only in /// Assert builds. @@ -2321,6 +2436,7 @@ // original alloca. uint64_t NewBeginOffset = 0, NewEndOffset = 0; + uint64_t RelativeOffset = 0; uint64_t SliceSize = 0; bool IsSplittable = false; bool IsSplit = false; @@ -2384,8 +2500,14 @@ NewBeginOffset = std::max(BeginOffset, NewAllocaBeginOffset); NewEndOffset = std::min(EndOffset, NewAllocaEndOffset); + RelativeOffset = NewBeginOffset - BeginOffset; SliceSize = NewEndOffset - NewBeginOffset; - + LLVM_DEBUG(dbgs() << " Begin:(" << BeginOffset << ", " << EndOffset + << ") NewBegin:(" << NewBeginOffset << ", " + << NewEndOffset << ") NewAllocaBegin:(" + << NewAllocaBeginOffset << ", " << NewAllocaEndOffset + << ")\n"); + assert(IsSplit || RelativeOffset == 0); OldUse = I->getUse(); OldPtr = cast(OldUse->get()); @@ -2623,6 +2745,9 @@ bool rewriteVectorizedStoreInst(Value *V, StoreInst &SI, Value *OldOp, AAMDNodes AATags) { + // Capture V for the purpose of debug-info accounting once it's converted + // to a vector store. + Value *OrigV = V; if (V->getType() != VecTy) { unsigned BeginIndex = getIndex(NewBeginOffset); unsigned EndIndex = getIndex(NewEndOffset); @@ -2648,6 +2773,9 @@ Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset)); Pass.DeadInsts.push_back(&SI); + // NOTE: Careful to use OrigV rather than V. + migrateDebugInfo(&OldAI, RelativeOffset, SliceSize, &SI, Store, + Store->getPointerOperand(), OrigV, DL); LLVM_DEBUG(dbgs() << " to: " << *Store << "\n"); return true; } @@ -2670,6 +2798,10 @@ LLVMContext::MD_access_group}); if (AATags) Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset)); + + migrateDebugInfo(&OldAI, RelativeOffset, SliceSize, &SI, Store, + Store->getPointerOperand(), Store->getValueOperand(), DL); + Pass.DeadInsts.push_back(&SI); LLVM_DEBUG(dbgs() << " to: " << *Store << "\n"); return true; @@ -2742,6 +2874,10 @@ NewSI->setAtomic(SI.getOrdering(), SI.getSyncScopeID()); if (NewSI->isAtomic()) NewSI->setAlignment(SI.getAlign()); + + migrateDebugInfo(&OldAI, RelativeOffset, SliceSize, &SI, NewSI, + NewSI->getPointerOperand(), NewSI->getValueOperand(), DL); + Pass.DeadInsts.push_back(&SI); deleteIfTriviallyDead(OldOp); @@ -2797,7 +2933,11 @@ assert(NewBeginOffset == BeginOffset); II.setDest(getNewAllocaSlicePtr(IRB, OldPtr->getType())); II.setDestAlignment(getSliceAlign()); - + // In theory we should call migrateDebugInfo here. However, we do not + // emit dbg.assign intrinsics for mem intrinsics storing through non- + // constant geps, or storing a variable number of bytes. + assert(at::getAssignmentMarkers(&II).empty() && + "AT: Unexpected link to non-const GEP"); deleteIfTriviallyDead(OldPtr); return false; } @@ -2830,11 +2970,15 @@ if (!CanContinue) { Type *SizeTy = II.getLength()->getType(); Constant *Size = ConstantInt::get(SizeTy, NewEndOffset - NewBeginOffset); - CallInst *New = IRB.CreateMemSet( + MemIntrinsic *New = cast(IRB.CreateMemSet( getNewAllocaSlicePtr(IRB, OldPtr->getType()), II.getValue(), Size, - MaybeAlign(getSliceAlign()), II.isVolatile()); + MaybeAlign(getSliceAlign()), II.isVolatile())); if (AATags) New->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset)); + + migrateDebugInfo(&OldAI, RelativeOffset, SliceSize, &II, New, + New->getRawDest(), nullptr, DL); + LLVM_DEBUG(dbgs() << " to: " << *New << "\n"); return false; } @@ -2906,6 +3050,10 @@ LLVMContext::MD_access_group}); if (AATags) New->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset)); + + migrateDebugInfo(&OldAI, RelativeOffset, SliceSize, &II, New, + New->getPointerOperand(), V, DL); + LLVM_DEBUG(dbgs() << " to: " << *New << "\n"); return !II.isVolatile(); } @@ -2923,7 +3071,6 @@ (!IsDest && II.getRawSource() == OldPtr)); Align SliceAlign = getSliceAlign(); - // For unsplit intrinsics, we simply modify the source and destination // pointers in place. This isn't just an optimization, it is a matter of // correctness. With unsplit intrinsics we may be dealing with transfers @@ -2934,10 +3081,16 @@ if (!IsSplittable) { Value *AdjustedPtr = getNewAllocaSlicePtr(IRB, OldPtr->getType()); if (IsDest) { + // Update the address component of linked dbg.assigns. + for (auto *DAI : at::getAssignmentMarkers(&II)) { + if (any_of(DAI->location_ops(), + [&](Value *V) { return V == II.getDest(); }) || + DAI->getAddress() == II.getDest()) + DAI->replaceVariableLocationOp(II.getDest(), AdjustedPtr); + } II.setDest(AdjustedPtr); II.setDestAlignment(SliceAlign); - } - else { + } else { II.setSource(AdjustedPtr); II.setSourceAlignment(SliceAlign); } @@ -3026,6 +3179,9 @@ Size, II.isVolatile()); if (AATags) New->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset)); + + migrateDebugInfo(&OldAI, RelativeOffset, SliceSize, &II, New, DestPtr, + nullptr, DL); LLVM_DEBUG(dbgs() << " to: " << *New << "\n"); return false; } @@ -3104,6 +3260,9 @@ LLVMContext::MD_access_group}); if (AATags) Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset)); + + migrateDebugInfo(&OldAI, RelativeOffset, SliceSize, &II, Store, DstPtr, Src, + DL); LLVM_DEBUG(dbgs() << " to: " << *Store << "\n"); return !II.isVolatile(); } @@ -3441,12 +3600,13 @@ struct StoreOpSplitter : public OpSplitter { StoreOpSplitter(Instruction *InsertionPoint, Value *Ptr, Type *BaseTy, - AAMDNodes AATags, Align BaseAlign, const DataLayout &DL, - IRBuilderTy &IRB) + AAMDNodes AATags, StoreInst *AggStore, Align BaseAlign, + const DataLayout &DL, IRBuilderTy &IRB) : OpSplitter(InsertionPoint, Ptr, BaseTy, BaseAlign, DL, IRB), - AATags(AATags) {} + AATags(AATags), AggStore(AggStore) {} AAMDNodes AATags; + StoreInst *AggStore; /// Emit a leaf store of a single value. This is called at the leaves of the /// recursive emission to actually produce stores. void emitFunc(Type *Ty, Value *&Agg, Align Alignment, const Twine &Name) { @@ -3468,6 +3628,25 @@ GEPOperator::accumulateConstantOffset(BaseTy, GEPIndices, DL, Offset)) Store->setAAMetadata(AATags.shift(Offset.getZExtValue())); + // migrateDebugInfo requires the base Alloca. Walk to it from this gep. + // If we cannot (because there's an intervening non-const or unbounded + // gep) then we wouldn't expect to see dbg.assign intrinsics linked to + // this instruction. + APInt OffsetInBytes(DL.getTypeSizeInBits(Ptr->getType()), false); + Value *Base = InBoundsGEP->stripAndAccumulateInBoundsConstantOffsets( + DL, OffsetInBytes); + if (auto *OldAI = dyn_cast(Base)) { + uint64_t SizeInBits = + DL.getTypeSizeInBits(Store->getValueOperand()->getType()); + migrateDebugInfo(OldAI, OffsetInBytes.getZExtValue(), + bitsToBytes(SizeInBits), AggStore, Store, + Store->getPointerOperand(), Store->getValueOperand(), + DL); + } else { + assert(at::getAssignmentMarkers(Store).empty() && + "AT: unexpected debug.assign linked to store through " + "unbounded GEP"); + } LLVM_DEBUG(dbgs() << " to: " << *Store << "\n"); } }; @@ -3481,7 +3660,7 @@ // We have an aggregate being stored, split it apart. LLVM_DEBUG(dbgs() << " original: " << SI << "\n"); - StoreOpSplitter Splitter(&SI, *U, V->getType(), SI.getAAMetadata(), + StoreOpSplitter Splitter(&SI, *U, V->getType(), SI.getAAMetadata(), &SI, getAdjustedAlignment(&SI, 0), DL, IRB); Splitter.emitSplitOps(V->getType(), V, V->getName() + ".fca"); Visited.erase(&SI); @@ -4082,7 +4261,8 @@ getAdjustedAlignment(SI, PartOffset), /*IsVolatile*/ false); PStore->copyMetadata(*SI, {LLVMContext::MD_mem_parallel_loop_access, - LLVMContext::MD_access_group}); + LLVMContext::MD_access_group, + LLVMContext::MD_DIAssignID}); LLVM_DEBUG(dbgs() << " +" << PartOffset << ":" << *PStore << "\n"); } @@ -4543,6 +4723,8 @@ // Migrate debug information from the old alloca to the new alloca(s) // and the individual partitions. TinyPtrVector DbgDeclares = FindDbgAddrUses(&AI); + for (auto *DbgAssign : at::getAssignmentMarkers(&AI)) + DbgDeclares.push_back(DbgAssign); for (DbgVariableIntrinsic *DbgDeclare : DbgDeclares) { auto *Expr = DbgDeclare->getExpression(); DIBuilder DIB(*AI.getModule(), /*AllowUnresolved*/ false); @@ -4562,9 +4744,10 @@ if (ExprFragment) { uint64_t AbsEnd = ExprFragment->OffsetInBits + ExprFragment->SizeInBits; - if (Start >= AbsEnd) + if (Start >= AbsEnd) { // No need to describe a SROAed padding. continue; + } Size = std::min(Size, AbsEnd - Start); } // The new, smaller fragment is stenciled out from the old fragment. @@ -4606,8 +4789,23 @@ OldDII->eraseFromParent(); } - DIB.insertDeclare(Fragment.Alloca, DbgDeclare->getVariable(), FragmentExpr, - DbgDeclare->getDebugLoc(), &AI); + if (auto *DbgAssign = dyn_cast(DbgDeclare)) { + if (!Fragment.Alloca->hasMetadata(LLVMContext::MD_DIAssignID)) { + Fragment.Alloca->setMetadata( + LLVMContext::MD_DIAssignID, + DIAssignID::getDistinct(AI.getContext())); + } + auto *NewAssign = DIB.insertDbgAssign( + Fragment.Alloca, DbgAssign->getValue(), DbgAssign->getVariable(), + FragmentExpr, Fragment.Alloca, DbgAssign->getAddressExpression(), + DbgAssign->getDebugLoc()); + NewAssign->setDebugLoc(DbgAssign->getDebugLoc()); + LLVM_DEBUG(dbgs() << "Created new assign intrinsic: " << *NewAssign + << "\n"); + } else { + DIB.insertDeclare(Fragment.Alloca, DbgDeclare->getVariable(), + FragmentExpr, DbgDeclare->getDebugLoc(), &AI); + } } } return Changed; @@ -4725,6 +4923,11 @@ OldDII->eraseFromParent(); } + for (DbgAssignIntrinsic *DAI : at::getAssignmentMarkers(I)) { + LLVM_DEBUG(dbgs() << " And deleting: " << *DAI << "\n"); + DAI->eraseFromParent(); + } + I->replaceAllUsesWith(UndefValue::get(I->getType())); for (Use &Operand : I->operands()) diff --git a/llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp b/llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp --- a/llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp +++ b/llvm/lib/Transforms/Scalar/ScalarizeMaskedMemIntrin.cpp @@ -35,6 +35,7 @@ #include "llvm/Transforms/Scalar.h" #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include +#include using namespace llvm; @@ -861,7 +862,7 @@ static bool runImpl(Function &F, const TargetTransformInfo &TTI, DominatorTree *DT) { - Optional DTU; + std::optional DTU; if (DT) DTU.emplace(DT, DomTreeUpdater::UpdateStrategy::Lazy); diff --git a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp --- a/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp +++ b/llvm/lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp @@ -1122,18 +1122,17 @@ // sizeof(int64). // // Emit an uglygep in this case. - Type *I8PtrTy = Type::getInt8PtrTy(GEP->getContext(), - GEP->getPointerAddressSpace()); - NewGEP = new BitCastInst(NewGEP, I8PtrTy, "", GEP); - NewGEP = GetElementPtrInst::Create( - Type::getInt8Ty(GEP->getContext()), NewGEP, - ConstantInt::get(IntPtrTy, AccumulativeByteOffset, true), "uglygep", - GEP); + IRBuilder<> Builder(GEP); + Type *I8PtrTy = + Builder.getInt8Ty()->getPointerTo(GEP->getPointerAddressSpace()); + + NewGEP = cast(Builder.CreateGEP( + Builder.getInt8Ty(), Builder.CreateBitCast(NewGEP, I8PtrTy), + {ConstantInt::get(IntPtrTy, AccumulativeByteOffset, true)}, "uglygep", + GEPWasInBounds)); + NewGEP->copyMetadata(*GEP); - // Inherit the inbounds attribute of the original GEP. - cast(NewGEP)->setIsInBounds(GEPWasInBounds); - if (GEP->getType() != I8PtrTy) - NewGEP = new BitCastInst(NewGEP, GEP->getType(), GEP->getName(), GEP); + NewGEP = cast(Builder.CreateBitCast(NewGEP, GEP->getType())); } GEP->replaceAllUsesWith(NewGEP); diff --git a/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp b/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp --- a/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp +++ b/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp @@ -63,6 +63,7 @@ #include #include #include +#include #include #define DEBUG_TYPE "simple-loop-unswitch" @@ -2988,7 +2989,7 @@ return (LoopCost - Cost) * (SuccessorsCount - 1); }; - Optional Best; + std::optional Best; for (auto &Candidate : UnswitchCandidates) { Instruction &TI = *Candidate.TI; ArrayRef Invariants = Candidate.Invariants; @@ -3210,7 +3211,7 @@ U.markLoopAsDeleted(L, Name); }; - Optional MSSAU; + std::optional MSSAU; if (AR.MSSA) { MSSAU = MemorySSAUpdater(AR.MSSA); if (VerifyMemorySSA) diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp --- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp +++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp @@ -82,10 +82,10 @@ // eventually be removed (they are themselves dead). if (!I.use_empty()) I.replaceAllUsesWith(PoisonValue::get(I.getType())); - BB->getInstList().pop_back(); + BB->back().eraseFromParent(); } new UnreachableInst(BB->getContext(), BB); - assert(BB->getInstList().size() == 1 && + assert(BB->size() == 1 && isa(BB->getTerminator()) && "The successor list of BB isn't empty before " "applying corresponding DTU updates."); @@ -279,13 +279,13 @@ if (PredecessorWithTwoSuccessors) { // Delete the unconditional branch from BB. - BB->getInstList().pop_back(); + BB->back().eraseFromParent(); // Update branch in the predecessor. PredBB_BI->setSuccessor(FallThruPath, NewSucc); } else { // Delete the unconditional branch from the predecessor. - PredBB->getInstList().pop_back(); + PredBB->back().eraseFromParent(); // Move terminator instruction. PredBB->getInstList().splice(PredBB->end(), BB->getInstList()); diff --git a/llvm/lib/Transforms/Utils/BypassSlowDivision.cpp b/llvm/lib/Transforms/Utils/BypassSlowDivision.cpp --- a/llvm/lib/Transforms/Utils/BypassSlowDivision.cpp +++ b/llvm/lib/Transforms/Utils/BypassSlowDivision.cpp @@ -417,7 +417,7 @@ // Split the basic block before the div/rem. BasicBlock *SuccessorBB = MainBB->splitBasicBlock(SlowDivOrRem); // Remove the unconditional branch from MainBB to SuccessorBB. - MainBB->getInstList().back().eraseFromParent(); + MainBB->back().eraseFromParent(); QuotRemWithBB Long; Long.BB = MainBB; Long.Quotient = ConstantInt::get(getSlowType(), 0); @@ -434,7 +434,7 @@ // Split the basic block before the div/rem. BasicBlock *SuccessorBB = MainBB->splitBasicBlock(SlowDivOrRem); // Remove the unconditional branch from MainBB to SuccessorBB. - MainBB->getInstList().back().eraseFromParent(); + MainBB->back().eraseFromParent(); QuotRemWithBB Fast = createFastBB(SuccessorBB); QuotRemWithBB Slow = createSlowBB(SuccessorBB); QuotRemPair Result = createDivRemPhiNodes(Fast, Slow, SuccessorBB); diff --git a/llvm/lib/Transforms/Utils/CallPromotionUtils.cpp b/llvm/lib/Transforms/Utils/CallPromotionUtils.cpp --- a/llvm/lib/Transforms/Utils/CallPromotionUtils.cpp +++ b/llvm/lib/Transforms/Utils/CallPromotionUtils.cpp @@ -415,18 +415,8 @@ // site. unsigned I = 0; for (; I < NumParams; ++I) { - Type *FormalTy = Callee->getFunctionType()->getFunctionParamType(I); - Type *ActualTy = CB.getArgOperand(I)->getType(); - if (FormalTy == ActualTy) - continue; - if (!CastInst::isBitOrNoopPointerCastable(ActualTy, FormalTy, DL)) { - if (FailureReason) - *FailureReason = "Argument type mismatch"; - return false; - } // Make sure that the callee and call agree on byval/inalloca. The types do // not have to match. - if (Callee->hasParamAttribute(I, Attribute::ByVal) != CB.getAttributes().hasParamAttr(I, Attribute::ByVal)) { if (FailureReason) @@ -439,6 +429,16 @@ *FailureReason = "inalloca mismatch"; return false; } + + Type *FormalTy = Callee->getFunctionType()->getFunctionParamType(I); + Type *ActualTy = CB.getArgOperand(I)->getType(); + if (FormalTy == ActualTy) + continue; + if (!CastInst::isBitOrNoopPointerCastable(ActualTy, FormalTy, DL)) { + if (FailureReason) + *FailureReason = "Argument type mismatch"; + return false; + } } for (; I < NumArgs; I++) { // Vararg functions can have more arguments than parameters. diff --git a/llvm/lib/Transforms/Utils/CloneFunction.cpp b/llvm/lib/Transforms/Utils/CloneFunction.cpp --- a/llvm/lib/Transforms/Utils/CloneFunction.cpp +++ b/llvm/lib/Transforms/Utils/CloneFunction.cpp @@ -33,6 +33,7 @@ #include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Utils/ValueMapper.h" #include +#include using namespace llvm; #define DEBUG_TYPE "clone-function" @@ -136,7 +137,7 @@ // duplicate instructions and then freeze them in the MD map. We also record // information about dbg.value and dbg.declare to avoid duplicating the // types. - Optional DIFinder; + std::optional DIFinder; // Track the subprogram attachment that needs to be cloned to fine-tune the // mapping within the same module. diff --git a/llvm/lib/Transforms/Utils/Debugify.cpp b/llvm/lib/Transforms/Utils/Debugify.cpp --- a/llvm/lib/Transforms/Utils/Debugify.cpp +++ b/llvm/lib/Transforms/Utils/Debugify.cpp @@ -243,13 +243,18 @@ bool llvm::stripDebugifyMetadata(Module &M) { bool Changed = false; - // Remove the llvm.debugify module-level named metadata. + // Remove the llvm.debugify and llvm.mir.debugify module-level named metadata. NamedMDNode *DebugifyMD = M.getNamedMetadata("llvm.debugify"); if (DebugifyMD) { M.eraseNamedMetadata(DebugifyMD); Changed = true; } + if (auto *MIRDebugifyMD = M.getNamedMetadata("llvm.mir.debugify")) { + M.eraseNamedMetadata(MIRDebugifyMD); + Changed = true; + } + // Strip out all debug intrinsics and supporting metadata (subprograms, types, // variables, etc). Changed |= StripDebugInfo(M); diff --git a/llvm/lib/Transforms/Utils/FlattenCFG.cpp b/llvm/lib/Transforms/Utils/FlattenCFG.cpp --- a/llvm/lib/Transforms/Utils/FlattenCFG.cpp +++ b/llvm/lib/Transforms/Utils/FlattenCFG.cpp @@ -284,7 +284,7 @@ do { CB = PBI->getSuccessor(1 - Idx); // Delete the conditional branch. - FirstCondBlock->getInstList().pop_back(); + FirstCondBlock->back().eraseFromParent(); FirstCondBlock->getInstList() .splice(FirstCondBlock->end(), CB->getInstList()); PBI = cast(FirstCondBlock->getTerminator()); @@ -480,7 +480,7 @@ } // Merge \param SecondEntryBlock into \param FirstEntryBlock. - FirstEntryBlock->getInstList().pop_back(); + FirstEntryBlock->back().eraseFromParent(); FirstEntryBlock->getInstList() .splice(FirstEntryBlock->end(), SecondEntryBlock->getInstList()); BranchInst *PBI = cast(FirstEntryBlock->getTerminator()); diff --git a/llvm/lib/Transforms/Utils/InlineFunction.cpp b/llvm/lib/Transforms/Utils/InlineFunction.cpp --- a/llvm/lib/Transforms/Utils/InlineFunction.cpp +++ b/llvm/lib/Transforms/Utils/InlineFunction.cpp @@ -2930,7 +2930,7 @@ OrigBB->getInstList().splice(Br->getIterator(), CalleeEntry->getInstList()); // Remove the unconditional branch. - OrigBB->getInstList().erase(Br); + Br->eraseFromParent(); // Now we can remove the CalleeEntry block, which is now empty. Caller->getBasicBlockList().erase(CalleeEntry); diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -80,6 +80,7 @@ #include #include #include +#include #include using namespace llvm; @@ -807,7 +808,7 @@ DestBB->moveAfter(PredBB); if (DTU) { - assert(PredBB->getInstList().size() == 1 && + assert(PredBB->size() == 1 && isa(PredBB->getTerminator()) && "The successor list of PredBB isn't empty before " "applying corresponding DTU updates."); @@ -1228,7 +1229,7 @@ // Clear the successor list of BB to match updates applying to DTU later. if (BB->getTerminator()) - BB->getInstList().pop_back(); + BB->back().eraseFromParent(); new UnreachableInst(BB->getContext(), BB); assert(succ_empty(BB) && "The successor list of BB isn't empty before " "applying corresponding DTU updates."); @@ -2048,7 +2049,7 @@ } /// A replacement for a dbg.value expression. -using DbgValReplacement = Optional; +using DbgValReplacement = std::optional; /// Point debug users of \p From to \p To using exprs given by \p RewriteExpr, /// possibly moving/undefing users to prevent use-before-def. Returns true if @@ -2238,7 +2239,7 @@ while (BBI != BBE) { if (!BBI->use_empty()) BBI->replaceAllUsesWith(PoisonValue::get(BBI->getType())); - BB->getInstList().erase(BBI++); + BBI++->eraseFromParent(); ++NumInstrsRemoved; } if (DTU) { @@ -2308,7 +2309,7 @@ CI->getName() + ".noexc"); // Delete the unconditional branch inserted by SplitBlock - BB->getInstList().pop_back(); + BB->back().eraseFromParent(); // Create the new invoke instruction. SmallVector InvokeArgs(CI->args()); @@ -2336,7 +2337,7 @@ CI->replaceAllUsesWith(II); // Delete the original call - Split->getInstList().pop_front(); + Split->front().eraseFromParent(); return Split; } diff --git a/llvm/lib/Transforms/Utils/LoopPeel.cpp b/llvm/lib/Transforms/Utils/LoopPeel.cpp --- a/llvm/lib/Transforms/Utils/LoopPeel.cpp +++ b/llvm/lib/Transforms/Utils/LoopPeel.cpp @@ -42,6 +42,7 @@ #include #include #include +#include using namespace llvm; using namespace llvm::PatternMatch; @@ -80,7 +81,7 @@ static const char *PeeledCountMetaData = "llvm.loop.peeled.count"; // Check whether we are capable of peeling this loop. -bool llvm::canPeel(Loop *L) { +bool llvm::canPeel(const Loop *L) { // Make sure the loop is in simplified form if (!L->isLoopSimplifyForm()) return false; @@ -100,57 +101,160 @@ return llvm::all_of(Exits, IsBlockFollowedByDeoptOrUnreachable); } -// This function calculates the number of iterations after which the given Phi -// becomes an invariant. The pre-calculated values are memorized in the map. The -// function (shortcut is I) is calculated according to the following definition: +namespace { + +// As a loop is peeled, it may be the case that Phi nodes become +// loop-invariant (ie, known because there is only one choice). +// For example, consider the following function: +// void g(int); +// void binary() { +// int x = 0; +// int y = 0; +// int a = 0; +// for(int i = 0; i <100000; ++i) { +// g(x); +// x = y; +// g(a); +// y = a + 1; +// a = 5; +// } +// } +// Peeling 3 iterations is beneficial because the values for x, y and a +// become known. The IR for this loop looks something like the following: +// +// %i = phi i32 [ 0, %entry ], [ %inc, %if.end ] +// %a = phi i32 [ 0, %entry ], [ 5, %if.end ] +// %y = phi i32 [ 0, %entry ], [ %add, %if.end ] +// %x = phi i32 [ 0, %entry ], [ %y, %if.end ] +// ... +// tail call void @_Z1gi(i32 signext %x) +// tail call void @_Z1gi(i32 signext %a) +// %add = add nuw nsw i32 %a, 1 +// %inc = add nuw nsw i32 %i, 1 +// %exitcond = icmp eq i32 %inc, 100000 +// br i1 %exitcond, label %for.cond.cleanup, label %for.body +// +// The arguments for the calls to g will become known after 3 iterations +// of the loop, because the phi nodes values become known after 3 iterations +// of the loop (ie, they are known on the 4th iteration, so peel 3 iterations). +// The first iteration has g(0), g(0); the second has g(0), g(5); the +// third has g(1), g(5) and the fourth (and all subsequent) have g(6), g(5). +// Now consider the phi nodes: +// %a is a phi with constants so it is determined after iteration 1. +// %y is a phi based on a constant and %a so it is determined on +// the iteration after %a is determined, so iteration 2. +// %x is a phi based on a constant and %y so it is determined on +// the iteration after %y, so iteration 3. +// %i is based on itself (and is an induction variable) so it is +// never determined. +// This means that peeling off 3 iterations will result in being able to +// remove the phi nodes for %a, %y, and %x. The arguments for the +// corresponding calls to g are determined and the code for computing +// x, y, and a can be removed. +// +// The PhiAnalyzer class calculates how many times a loop should be +// peeled based on the above analysis of the phi nodes in the loop while +// respecting the maximum specified. +class PhiAnalyzer { +public: + PhiAnalyzer(const Loop &L, unsigned MaxIterations); + + // Calculate the sufficient minimum number of iterations of the loop to peel + // such that phi instructions become determined (subject to allowable limits) + Optional calculateIterationsToPeel(); + +protected: + using PeelCounter = std::optional; + const PeelCounter Unknown = None; + + // Add 1 respecting Unknown and return Unknown if result over MaxIterations + PeelCounter addOne(PeelCounter PC) const { + if (PC == Unknown) + return Unknown; + return (*PC + 1 <= MaxIterations) ? PeelCounter{*PC + 1} : Unknown; + } + + // Calculate the number of iterations after which the given value + // becomes an invariant. + PeelCounter calculate(const Value &); + + const Loop &L; + const unsigned MaxIterations; + + // Map of Values to number of iterations to invariance + SmallDenseMap IterationsToInvariance; +}; + +PhiAnalyzer::PhiAnalyzer(const Loop &L, unsigned MaxIterations) + : L(L), MaxIterations(MaxIterations) { + assert(canPeel(&L) && "loop is not suitable for peeling"); + assert(MaxIterations > 0 && "no peeling is allowed?"); +} + +// This function calculates the number of iterations after which the value +// becomes an invariant. The pre-calculated values are memorized in a map. +// N.B. This number will be Unknown or <= MaxIterations. +// The function is calculated according to the following definition: // Given %x = phi , ..., [%y, %back.edge]. -// If %y is a loop invariant, then I(%x) = 1. -// If %y is a Phi from the loop header, I(%x) = I(%y) + 1. -// Otherwise, I(%x) is infinite. -// TODO: Actually if %y is an expression that depends only on Phi %z and some -// loop invariants, we can estimate I(%x) = I(%z) + 1. The example -// looks like: -// %x = phi(0, %a), <-- becomes invariant starting from 3rd iteration. -// %y = phi(0, 5), -// %a = %y + 1. -static Optional calculateIterationsToInvariance( - PHINode *Phi, Loop *L, BasicBlock *BackEdge, - SmallDenseMap > &IterationsToInvariance) { - assert(Phi->getParent() == L->getHeader() && - "Non-loop Phi should not be checked for turning into invariant."); - assert(BackEdge == L->getLoopLatch() && "Wrong latch?"); +// F(%x) = G(%y) + 1 (N.B. [MaxIterations | Unknown] + 1 => Unknown) +// G(%y) = 0 if %y is a loop invariant +// G(%y) = G(%BackEdgeValue) if %y is a phi in the header block +// G(%y) = TODO: if %y is an expression based on phis and loop invariants +// The example looks like: +// %x = phi(0, %a) <-- becomes invariant starting from 3rd iteration. +// %y = phi(0, 5) +// %a = %y + 1 +// G(%y) = Unknown otherwise (including phi not in header block) +PhiAnalyzer::PeelCounter PhiAnalyzer::calculate(const Value &V) { // If we already know the answer, take it from the map. - auto I = IterationsToInvariance.find(Phi); + auto I = IterationsToInvariance.find(&V); if (I != IterationsToInvariance.end()) return I->second; - // Otherwise we need to analyze the input from the back edge. - Value *Input = Phi->getIncomingValueForBlock(BackEdge); - // Place infinity to map to avoid infinite recursion for cycled Phis. Such + // Place Unknown to map to avoid infinite recursion. Such // cycles can never stop on an invariant. - IterationsToInvariance[Phi] = None; - Optional ToInvariance; - - if (L->isLoopInvariant(Input)) - ToInvariance = 1u; - else if (PHINode *IncPhi = dyn_cast(Input)) { - // Only consider Phis in header block. - if (IncPhi->getParent() != L->getHeader()) - return None; - // If the input becomes an invariant after X iterations, then our Phi - // becomes an invariant after X + 1 iterations. - auto InputToInvariance = calculateIterationsToInvariance( - IncPhi, L, BackEdge, IterationsToInvariance); - if (InputToInvariance) - ToInvariance = *InputToInvariance + 1u; + IterationsToInvariance[&V] = Unknown; + + if (L.isLoopInvariant(&V)) + // Loop invariant so known at start. + return (IterationsToInvariance[&V] = 0); + if (const PHINode *Phi = dyn_cast(&V)) { + if (Phi->getParent() != L.getHeader()) { + // Phi is not in header block so Unknown. + assert(IterationsToInvariance[&V] == Unknown && "unexpected value saved"); + return Unknown; + } + // We need to analyze the input from the back edge and add 1. + Value *Input = Phi->getIncomingValueForBlock(L.getLoopLatch()); + PeelCounter Iterations = calculate(*Input); + assert(IterationsToInvariance[Input] == Iterations && + "unexpected value saved"); + return (IterationsToInvariance[Phi] = addOne(Iterations)); } + // TODO: handle expressions - // If we found that this Phi lies in an invariant chain, update the map. - if (ToInvariance) - IterationsToInvariance[Phi] = ToInvariance; - return ToInvariance; + // Everything else is Unknown. + assert(IterationsToInvariance[&V] == Unknown && "unexpected value saved"); + return Unknown; +} + +Optional PhiAnalyzer::calculateIterationsToPeel() { + unsigned Iterations = 0; + for (auto &PHI : L.getHeader()->phis()) { + PeelCounter ToInvariance = calculate(PHI); + if (ToInvariance != Unknown) { + assert(*ToInvariance <= MaxIterations && "bad result in phi analysis"); + Iterations = std::max(Iterations, *ToInvariance); + if (Iterations == MaxIterations) + break; + } + } + assert((Iterations <= MaxIterations) && "bad result in phi analysis"); + return Iterations ? Optional(Iterations) : None; } +} // unnamed namespace + // Try to find any invariant memory reads that will become dereferenceable in // the remainder loop after peeling. The load must also be used (transitively) // by an exit condition. Returns the number of iterations to peel off (at the @@ -395,33 +499,26 @@ if (AlreadyPeeled >= UnrollPeelMaxCount) return; + // Pay respect to limitations implied by loop size and the max peel count. + unsigned MaxPeelCount = UnrollPeelMaxCount; + MaxPeelCount = std::min(MaxPeelCount, Threshold / LoopSize - 1); + + // Start the max computation with the PP.PeelCount value set by the target + // in TTI.getPeelingPreferences or by the flag -unroll-peel-count. + unsigned DesiredPeelCount = TargetPeelCount; + // Here we try to get rid of Phis which become invariants after 1, 2, ..., N // iterations of the loop. For this we compute the number for iterations after // which every Phi is guaranteed to become an invariant, and try to peel the // maximum number of iterations among these values, thus turning all those // Phis into invariants. - - // Store the pre-calculated values here. - SmallDenseMap> IterationsToInvariance; - // Now go through all Phis to calculate their the number of iterations they - // need to become invariants. - // Start the max computation with the PP.PeelCount value set by the target - // in TTI.getPeelingPreferences or by the flag -unroll-peel-count. - unsigned DesiredPeelCount = TargetPeelCount; - BasicBlock *BackEdge = L->getLoopLatch(); - assert(BackEdge && "Loop is not in simplified form?"); - for (auto BI = L->getHeader()->begin(); isa(&*BI); ++BI) { - PHINode *Phi = cast(&*BI); - auto ToInvariance = calculateIterationsToInvariance(Phi, L, BackEdge, - IterationsToInvariance); - if (ToInvariance) - DesiredPeelCount = std::max(DesiredPeelCount, *ToInvariance); + if (MaxPeelCount > DesiredPeelCount) { + // Check how many iterations are useful for resolving Phis + auto NumPeels = PhiAnalyzer(*L, MaxPeelCount).calculateIterationsToPeel(); + if (NumPeels) + DesiredPeelCount = std::max(DesiredPeelCount, *NumPeels); } - // Pay respect to limitations implied by loop size and the max peel count. - unsigned MaxPeelCount = UnrollPeelMaxCount; - MaxPeelCount = std::min(MaxPeelCount, Threshold / LoopSize - 1); - DesiredPeelCount = std::max(DesiredPeelCount, countToEliminateCompares(*L, MaxPeelCount, SE)); @@ -673,7 +770,7 @@ else VMap[&*I] = LatchVal; } - cast(VMap[Header])->getInstList().erase(NewPHI); + NewPHI->eraseFromParent(); } // Fix up the outgoing values - we need to add a value for the iteration diff --git a/llvm/lib/Transforms/Utils/LoopSimplify.cpp b/llvm/lib/Transforms/Utils/LoopSimplify.cpp --- a/llvm/lib/Transforms/Utils/LoopSimplify.cpp +++ b/llvm/lib/Transforms/Utils/LoopSimplify.cpp @@ -440,7 +440,7 @@ // eliminate the PHI Node. if (HasUniqueIncomingValue) { NewPN->replaceAllUsesWith(UniqueValue); - BEBlock->getInstList().erase(NewPN); + NewPN->eraseFromParent(); } } diff --git a/llvm/lib/Transforms/Utils/LoopUnroll.cpp b/llvm/lib/Transforms/Utils/LoopUnroll.cpp --- a/llvm/lib/Transforms/Utils/LoopUnroll.cpp +++ b/llvm/lib/Transforms/Utils/LoopUnroll.cpp @@ -559,7 +559,7 @@ if (It > 1 && L->contains(InValI)) InVal = LastValueMap[InValI]; VMap[OrigPHI] = InVal; - New->getInstList().erase(NewPHI); + NewPHI->eraseFromParent(); } // Update our running map of newest clones @@ -633,7 +633,7 @@ for (PHINode *PN : OrigPHINode) { if (CompletelyUnroll) { PN->replaceAllUsesWith(PN->getIncomingValueForBlock(Preheader)); - Header->getInstList().erase(PN); + PN->eraseFromParent(); } else if (ULO.Count > 1) { Value *InVal = PN->removeIncomingValue(LatchBlock, false); // If this value was defined in the loop, take the value defined by the diff --git a/llvm/lib/Transforms/Utils/LoopUnrollAndJam.cpp b/llvm/lib/Transforms/Utils/LoopUnrollAndJam.cpp --- a/llvm/lib/Transforms/Utils/LoopUnrollAndJam.cpp +++ b/llvm/lib/Transforms/Utils/LoopUnrollAndJam.cpp @@ -497,7 +497,7 @@ if (CompletelyUnroll) { while (PHINode *Phi = dyn_cast(ForeBlocksFirst[0]->begin())) { Phi->replaceAllUsesWith(Phi->getIncomingValueForBlock(Preheader)); - Phi->getParent()->getInstList().erase(Phi); + Phi->eraseFromParent(); } } else { // Update the PHI values to point to the last aft block diff --git a/llvm/lib/Transforms/Utils/LowerInvoke.cpp b/llvm/lib/Transforms/Utils/LowerInvoke.cpp --- a/llvm/lib/Transforms/Utils/LowerInvoke.cpp +++ b/llvm/lib/Transforms/Utils/LowerInvoke.cpp @@ -66,7 +66,7 @@ II->getUnwindDest()->removePredecessor(&BB); // Remove the invoke instruction now. - BB.getInstList().erase(II); + II->eraseFromParent(); ++NumInvokes; Changed = true; diff --git a/llvm/lib/Transforms/Utils/LowerSwitch.cpp b/llvm/lib/Transforms/Utils/LowerSwitch.cpp --- a/llvm/lib/Transforms/Utils/LowerSwitch.cpp +++ b/llvm/lib/Transforms/Utils/LowerSwitch.cpp @@ -520,7 +520,7 @@ // We are now done with the switch instruction, delete it. BasicBlock *OldDefault = SI->getDefaultDest(); - OrigBlock->getInstList().erase(SI); + SI->eraseFromParent(); // If the Default block has no more predecessors just add it to DeleteList. if (pred_empty(OldDefault)) diff --git a/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp b/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp --- a/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp +++ b/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp @@ -204,7 +204,12 @@ NewAI->setSwiftError(Info.AI->isSwiftError()); NewAI->copyMetadata(*Info.AI); - auto *NewPtr = new BitCastInst(NewAI, Info.AI->getType(), "", Info.AI); + Value *NewPtr = NewAI; + + // TODO: Remove when typed pointers dropped + if (Info.AI->getType() != NewAI->getType()) + NewPtr = new BitCastInst(NewAI, Info.AI->getType(), "", Info.AI); + Info.AI->replaceAllUsesWith(NewPtr); Info.AI->eraseFromParent(); Info.AI = NewAI; diff --git a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp --- a/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp +++ b/llvm/lib/Transforms/Utils/PromoteMemoryToRegister.cpp @@ -1057,7 +1057,7 @@ // Anything using the load now uses the current value. LI->replaceAllUsesWith(V); - BB->getInstList().erase(LI); + LI->eraseFromParent(); } else if (StoreInst *SI = dyn_cast(I)) { // Delete this instruction and mark the name as the current holder of the // value @@ -1079,7 +1079,7 @@ for (DbgVariableIntrinsic *DII : AllocaDbgUsers[ai->second]) if (DII->isAddressOfVariable()) ConvertDebugDeclareToDebugValue(DII, SI, DIB); - BB->getInstList().erase(SI); + SI->eraseFromParent(); } } diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -82,6 +82,7 @@ #include #include #include +#include #include #include #include @@ -3523,7 +3524,7 @@ /// Determine if the two branches share a common destination and deduce a glue /// that joins the branches' conditions to arrive at the common destination if /// that would be profitable. -static Optional> +static std::optional> shouldFoldCondBranchesToCommonDestination(BranchInst *BI, BranchInst *PBI, const TargetTransformInfo *TTI) { assert(BI && PBI && BI->isConditional() && PBI->isConditional() && diff --git a/llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp b/llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp --- a/llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp +++ b/llvm/lib/Transforms/Utils/UnifyFunctionExitNodes.cpp @@ -60,7 +60,7 @@ new UnreachableInst(F.getContext(), UnreachableBlock); for (BasicBlock *BB : UnreachableBlocks) { - BB->getInstList().pop_back(); // Remove the unreachable inst. + BB->back().eraseFromParent(); // Remove the unreachable inst. BranchInst::Create(UnreachableBlock, BB); } @@ -102,7 +102,7 @@ if (PN) PN->addIncoming(BB->getTerminator()->getOperand(0), BB); - BB->getInstList().pop_back(); // Remove the return insn + BB->back().eraseFromParent(); // Remove the return insn BranchInst::Create(NewRetBlock, BB); } diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -363,13 +363,14 @@ "vectorize-loops", cl::init(true), cl::Hidden, cl::desc("Run the Loop vectorization passes")); -cl::opt PrintVPlansInDotFormat( - "vplan-print-in-dot-format", cl::init(false), cl::Hidden, +static cl::opt PrintVPlansInDotFormat( + "vplan-print-in-dot-format", cl::Hidden, cl::desc("Use dot format instead of plain text when dumping VPlans")); -cl::opt ForceSafeDivisor( +static cl::opt ForceSafeDivisor( "force-widen-divrem-via-safe-divisor", cl::Hidden, - cl::desc("Override cost based safe divisor widening for div/rem instructions")); + cl::desc( + "Override cost based safe divisor widening for div/rem instructions")); /// A helper function that returns true if the given type is irregular. The /// type is irregular if its allocated size doesn't equal the store size of an @@ -2332,11 +2333,19 @@ /// variable on which to base the steps, \p Step is the size of the step. static void buildScalarSteps(Value *ScalarIV, Value *Step, const InductionDescriptor &ID, VPValue *Def, - VPTransformState &State) { + Type *TruncToTy, VPTransformState &State) { IRBuilderBase &Builder = State.Builder; + Type *ScalarIVTy = ScalarIV->getType()->getScalarType(); + if (TruncToTy) { + assert(Step->getType()->isIntegerTy() && + "Truncation requires an integer step"); + ScalarIV = State.Builder.CreateTrunc(ScalarIV, TruncToTy); + Step = State.Builder.CreateTrunc(Step, TruncToTy); + ScalarIVTy = ScalarIV->getType()->getScalarType(); + } + // We shouldn't have to build scalar steps if we aren't vectorizing. // Get the value type and ensure it and the step have the same integer type. - Type *ScalarIVTy = ScalarIV->getType()->getScalarType(); assert(ScalarIVTy == Step->getType() && "Val and Step should have the same type"); @@ -2427,8 +2436,14 @@ static Value *emitTransformedIndex(IRBuilderBase &B, Value *Index, Value *StartValue, Value *Step, const InductionDescriptor &ID) { - assert(Index->getType()->getScalarType() == Step->getType() && - "Index scalar type does not match StepValue type"); + Type *StepTy = Step->getType(); + Value *CastedIndex = StepTy->isIntegerTy() + ? B.CreateSExtOrTrunc(Index, StepTy) + : B.CreateCast(Instruction::SIToFP, Index, StepTy); + if (CastedIndex != Index) { + CastedIndex->setName(CastedIndex->getName() + ".cast"); + Index = CastedIndex; + } // Note: the IR at this point is broken. We cannot use SE to create any new // SCEV and then expand it, hoping that SCEV's simplification will give us @@ -2694,6 +2709,7 @@ for (unsigned Part = 0; Part < UF; Part++) { // Collect the stored vector from each member. SmallVector StoredVecs; + unsigned StoredIdx = 0; for (unsigned i = 0; i < InterleaveFactor; i++) { assert((Group->getMember(i) || MaskForGaps) && "Fail to get a member from an interleaved store group"); @@ -2706,7 +2722,8 @@ continue; } - Value *StoredVec = State.get(StoredValues[i], Part); + Value *StoredVec = State.get(StoredValues[StoredIdx], Part); + ++StoredIdx; if (Group->isReverse()) StoredVec = Builder.CreateVectorReverse(StoredVec, "reverse"); @@ -3132,25 +3149,19 @@ if (II.getInductionBinOp() && isa(II.getInductionBinOp())) B.setFastMathFlags(II.getInductionBinOp()->getFastMathFlags()); - Type *StepType = II.getStep()->getType(); - Instruction::CastOps CastOp = - CastInst::getCastOpcode(VectorTripCount, true, StepType, true); - Value *VTC = B.CreateCast(CastOp, VectorTripCount, StepType, "cast.vtc"); Value *Step = CreateStepValue(II.getStep(), *PSE.getSE(), &*B.GetInsertPoint()); - EndValue = emitTransformedIndex(B, VTC, II.getStartValue(), Step, II); + EndValue = + emitTransformedIndex(B, VectorTripCount, II.getStartValue(), Step, II); EndValue->setName("ind.end"); // Compute the end value for the additional bypass (if applicable). if (AdditionalBypass.first) { B.SetInsertPoint(&(*AdditionalBypass.first->getFirstInsertionPt())); - CastOp = CastInst::getCastOpcode(AdditionalBypass.second, true, StepType, - true); Value *Step = CreateStepValue(II.getStep(), *PSE.getSE(), &*B.GetInsertPoint()); - VTC = B.CreateCast(CastOp, AdditionalBypass.second, StepType, "cast.vtc"); - EndValueFromAdditionalBypass = - emitTransformedIndex(B, VTC, II.getStartValue(), Step, II); + EndValueFromAdditionalBypass = emitTransformedIndex( + B, AdditionalBypass.second, II.getStartValue(), Step, II); EndValueFromAdditionalBypass->setName("ind.end"); } } @@ -3347,17 +3358,11 @@ Value *CountMinusOne = B.CreateSub( VectorTripCount, ConstantInt::get(VectorTripCount->getType(), 1)); - Value *CMO = - !II.getStep()->getType()->isIntegerTy() - ? B.CreateCast(Instruction::SIToFP, CountMinusOne, - II.getStep()->getType()) - : B.CreateSExtOrTrunc(CountMinusOne, II.getStep()->getType()); - CMO->setName("cast.cmo"); - + CountMinusOne->setName("cmo"); Value *Step = CreateStepValue(II.getStep(), *PSE.getSE(), VectorHeader->getTerminator()); Value *Escape = - emitTransformedIndex(B, CMO, II.getStartValue(), Step, II); + emitTransformedIndex(B, CountMinusOne, II.getStartValue(), Step, II); Escape->setName("ind.escape"); MissingVals[UI] = Escape; } @@ -9542,27 +9547,17 @@ auto CreateScalarIV = [&](Value *&Step) -> Value * { Value *ScalarIV = State.get(getCanonicalIV(), VPIteration(0, 0)); auto *CanonicalIV = State.get(getParent()->getPlan()->getCanonicalIV(), 0); - if (!isCanonical() || CanonicalIV->getType() != Ty) { - ScalarIV = - Ty->isIntegerTy() - ? State.Builder.CreateSExtOrTrunc(ScalarIV, Ty) - : State.Builder.CreateCast(Instruction::SIToFP, ScalarIV, Ty); + if (!isCanonical() || CanonicalIV->getType() != Step->getType()) { ScalarIV = emitTransformedIndex(State.Builder, ScalarIV, getStartValue()->getLiveInIRValue(), Step, IndDesc); ScalarIV->setName("offset.idx"); } - if (TruncToTy) { - assert(Step->getType()->isIntegerTy() && - "Truncation requires an integer step"); - ScalarIV = State.Builder.CreateTrunc(ScalarIV, TruncToTy); - Step = State.Builder.CreateTrunc(Step, TruncToTy); - } return ScalarIV; }; Value *ScalarIV = CreateScalarIV(Step); - buildScalarSteps(ScalarIV, Step, IndDesc, this, State); + buildScalarSteps(ScalarIV, Step, IndDesc, this, TruncToTy, State); } void VPInterleaveRecipe::execute(VPTransformState &State) { diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -94,6 +94,7 @@ #include #include #include +#include #include #include #include @@ -12797,7 +12798,7 @@ return true; if (Opcodes1.size() > Opcodes2.size()) return false; - Optional ConstOrder; + std::optional ConstOrder; for (int I = 0, E = Opcodes1.size(); I < E; ++I) { // Undefs are compatible with any other value. if (isa(Opcodes1[I]) || isa(Opcodes2[I])) { diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -1952,19 +1952,16 @@ /// A recipe for handling phi nodes of integer and floating-point inductions, /// producing their scalar values. class VPScalarIVStepsRecipe : public VPRecipeBase, public VPValue { - /// Scalar type to use for the generated values. - Type *Ty; /// If not nullptr, truncate the generated values to TruncToTy. Type *TruncToTy; const InductionDescriptor &IndDesc; public: - VPScalarIVStepsRecipe(Type *Ty, const InductionDescriptor &IndDesc, + VPScalarIVStepsRecipe(const InductionDescriptor &IndDesc, VPValue *CanonicalIV, VPValue *Start, VPValue *Step, Type *TruncToTy) : VPRecipeBase(VPScalarIVStepsSC, {CanonicalIV, Start, Step}), - VPValue(nullptr, this), Ty(Ty), TruncToTy(TruncToTy), IndDesc(IndDesc) { - } + VPValue(nullptr, this), TruncToTy(TruncToTy), IndDesc(IndDesc) {} ~VPScalarIVStepsRecipe() override = default; diff --git a/llvm/lib/Transforms/Vectorize/VPlanSLP.cpp b/llvm/lib/Transforms/Vectorize/VPlanSLP.cpp --- a/llvm/lib/Transforms/Vectorize/VPlanSLP.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanSLP.cpp @@ -29,6 +29,7 @@ #include "llvm/Support/raw_ostream.h" #include #include +#include #include using namespace llvm; @@ -187,7 +188,7 @@ } /// Returns the opcode of Values or ~0 if they do not all agree. -static Optional getOpcode(ArrayRef Values) { +static std::optional getOpcode(ArrayRef Values) { unsigned Opcode = cast(Values[0])->getOpcode(); if (any_of(Values, [Opcode](VPValue *V) { return cast(V)->getOpcode() != Opcode; diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -394,8 +394,8 @@ vputils::getOrCreateVPValueForSCEVExpr(Plan, ID.getStep(), SE); Instruction *TruncI = IV->getTruncInst(); VPScalarIVStepsRecipe *Steps = new VPScalarIVStepsRecipe( - IV->getPHINode()->getType(), ID, Plan.getCanonicalIV(), - IV->getStartValue(), Step, TruncI ? TruncI->getType() : nullptr); + ID, Plan.getCanonicalIV(), IV->getStartValue(), Step, + TruncI ? TruncI->getType() : nullptr); HeaderVPBB->insert(Steps, HeaderVPBB->getFirstNonPhi()); // Update scalar users of IV to use Step instead. Use SetVector to ensure diff --git a/llvm/lib/XRay/InstrumentationMap.cpp b/llvm/lib/XRay/InstrumentationMap.cpp --- a/llvm/lib/XRay/InstrumentationMap.cpp +++ b/llvm/lib/XRay/InstrumentationMap.cpp @@ -188,7 +188,7 @@ SledEntry::FunctionKinds::TAIL, SledEntry::FunctionKinds::LOG_ARGS_ENTER, SledEntry::FunctionKinds::CUSTOM_EVENT}; - if (Kind >= sizeof(Kinds) / sizeof(Kinds[0])) + if (Kind >= std::size(Kinds)) return errorCodeToError( std::make_error_code(std::errc::executable_format_error)); Entry.Kind = Kinds[Kind]; diff --git a/llvm/test/Analysis/BasicAA/libfuncs.ll b/llvm/test/Analysis/BasicAA/libfuncs.ll --- a/llvm/test/Analysis/BasicAA/libfuncs.ll +++ b/llvm/test/Analysis/BasicAA/libfuncs.ll @@ -315,3 +315,53 @@ store i8 1, i8* %a.gep.5 ret i8* %res } + +declare i8* @__memcpy_chk(i8* writeonly, i8* readonly, i64, i64) + +define i8* @test_memcpy_chk_const_size(i8* noalias %a, i8* noalias %b, i64 %n) { +; CHECK-LABEL: Function: test_memcpy_chk_const_size +; CHECK: Just Mod: Ptr: i8* %a <-> %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 4, i64 %n) +; CHECK-NEXT: Just Mod: Ptr: i8* %res <-> %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 4, i64 %n) +; CHECK-NEXT: Just Mod: Ptr: i8* %a.gep.1 <-> %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 4, i64 %n) +; CHECK-NEXT: NoModRef: Ptr: i8* %a.gep.5 <-> %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 4, i64 %n) +; CHECK-NEXT: Just Ref: Ptr: i8* %b.gep.1 <-> %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 4, i64 %n) +; CHECK-NEXT: NoModRef: Ptr: i8* %b.gep.5 <-> %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 4, i64 %n) +; +entry: + load i8, i8* %a + %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 4, i64 %n) + load i8, i8* %res + %a.gep.1 = getelementptr i8, i8* %a, i32 1 + store i8 0, i8* %a.gep.1 + %a.gep.5 = getelementptr i8, i8* %a, i32 5 + store i8 1, i8* %a.gep.5 + %b.gep.1 = getelementptr i8, i8* %b, i32 1 + store i8 0, i8* %b.gep.1 + %b.gep.5 = getelementptr i8, i8* %b, i32 5 + store i8 1, i8* %b.gep.5 + ret i8* %res +} + +define i8* @test_memcpy_chk_variable_size(i8* noalias %a, i8* noalias %b, i64 %n.1, i64 %n.2) { +; CHECK-LABEL: Function: test_memcpy_chk_variable_size +; CHECK: Just Mod: Ptr: i8* %a <-> %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 %n.1, i64 %n.2) +; CHECK-NEXT: Just Mod: Ptr: i8* %res <-> %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 %n.1, i64 %n.2) +; CHECK-NEXT: Just Mod: Ptr: i8* %a.gep.1 <-> %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 %n.1, i64 %n.2) +; CHECK-NEXT: Just Mod: Ptr: i8* %a.gep.5 <-> %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 %n.1, i64 %n.2) +; CHECK-NEXT: Just Ref: Ptr: i8* %b.gep.1 <-> %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 %n.1, i64 %n.2) +; CHECK-NEXT: Just Ref: Ptr: i8* %b.gep.5 <-> %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 %n.1, i64 %n.2) +; +entry: + load i8, i8* %a + %res = tail call i8* @__memcpy_chk(i8* %a, i8* %b, i64 %n.1, i64 %n.2) + load i8, i8* %res + %a.gep.1 = getelementptr i8, i8* %a, i32 1 + store i8 0, i8* %a.gep.1 + %a.gep.5 = getelementptr i8, i8* %a, i32 5 + store i8 1, i8* %a.gep.5 + %b.gep.1 = getelementptr i8, i8* %b, i32 1 + store i8 0, i8* %b.gep.1 + %b.gep.5 = getelementptr i8, i8* %b, i32 5 + store i8 1, i8* %b.gep.5 + ret i8* %res +} diff --git a/llvm/test/Analysis/CostModel/AArch64/div.ll b/llvm/test/Analysis/CostModel/AArch64/div.ll --- a/llvm/test/Analysis/CostModel/AArch64/div.ll +++ b/llvm/test/Analysis/CostModel/AArch64/div.ll @@ -178,21 +178,21 @@ define i32 @sdiv_uniformconst() { ; CHECK-LABEL: 'sdiv_uniformconst' ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I64 = sdiv i64 undef, 7 -; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V2i64 = sdiv <2 x i64> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V4i64 = sdiv <4 x i64> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %V8i64 = sdiv <8 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2i64 = sdiv <2 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4i64 = sdiv <4 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i64 = sdiv <8 x i64> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = sdiv i32 undef, 7 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4i32 = sdiv <4 x i32> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 104 for instruction: %V8i32 = sdiv <8 x i32> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 208 for instruction: %V16i32 = sdiv <16 x i32> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i32 = sdiv <8 x i32> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i32 = sdiv <16 x i32> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = sdiv i16 undef, 7 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8i16 = sdiv <8 x i16> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 216 for instruction: %V16i16 = sdiv <16 x i16> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 432 for instruction: %V32i16 = sdiv <32 x i16> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i16 = sdiv <16 x i16> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i16 = sdiv <32 x i16> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = sdiv i8 undef, 7 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16i8 = sdiv <16 x i8> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 440 for instruction: %V32i8 = sdiv <32 x i8> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 880 for instruction: %V64i8 = sdiv <64 x i8> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i8 = sdiv <32 x i8> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V64i8 = sdiv <64 x i8> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; %I64 = sdiv i64 undef, 7 @@ -221,21 +221,21 @@ define i32 @udiv_uniformconst() { ; CHECK-LABEL: 'udiv_uniformconst' ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I64 = udiv i64 undef, 7 -; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V2i64 = udiv <2 x i64> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V4i64 = udiv <4 x i64> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %V8i64 = udiv <8 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2i64 = udiv <2 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4i64 = udiv <4 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i64 = udiv <8 x i64> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = udiv i32 undef, 7 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4i32 = udiv <4 x i32> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 104 for instruction: %V8i32 = udiv <8 x i32> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 208 for instruction: %V16i32 = udiv <16 x i32> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i32 = udiv <8 x i32> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i32 = udiv <16 x i32> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = udiv i16 undef, 7 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8i16 = udiv <8 x i16> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 216 for instruction: %V16i16 = udiv <16 x i16> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 432 for instruction: %V32i16 = udiv <32 x i16> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i16 = udiv <16 x i16> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i16 = udiv <32 x i16> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = udiv i8 undef, 7 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16i8 = udiv <16 x i8> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 440 for instruction: %V32i8 = udiv <32 x i8> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 880 for instruction: %V64i8 = udiv <64 x i8> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i8 = udiv <32 x i8> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V64i8 = udiv <64 x i8> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; %I64 = udiv i64 undef, 7 @@ -393,21 +393,21 @@ define i32 @udiv_uniformconstpow2() { ; CHECK-LABEL: 'udiv_uniformconstpow2' ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I64 = udiv i64 undef, 16 -; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V2i64 = udiv <2 x i64> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V4i64 = udiv <4 x i64> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %V8i64 = udiv <8 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2i64 = udiv <2 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4i64 = udiv <4 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i64 = udiv <8 x i64> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = udiv i32 undef, 16 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4i32 = udiv <4 x i32> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 104 for instruction: %V8i32 = udiv <8 x i32> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 208 for instruction: %V16i32 = udiv <16 x i32> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i32 = udiv <8 x i32> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i32 = udiv <16 x i32> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = udiv i16 undef, 16 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8i16 = udiv <8 x i16> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 216 for instruction: %V16i16 = udiv <16 x i16> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 432 for instruction: %V32i16 = udiv <32 x i16> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i16 = udiv <16 x i16> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i16 = udiv <32 x i16> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = udiv i8 undef, 16 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16i8 = udiv <16 x i8> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 440 for instruction: %V32i8 = udiv <32 x i8> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 880 for instruction: %V64i8 = udiv <64 x i8> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i8 = udiv <32 x i8> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V64i8 = udiv <64 x i8> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; %I64 = udiv i64 undef, 16 @@ -522,21 +522,21 @@ define i32 @sdiv_uniformconstnegpow2() { ; CHECK-LABEL: 'sdiv_uniformconstnegpow2' ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I64 = sdiv i64 undef, -16 -; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V2i64 = sdiv <2 x i64> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V4i64 = sdiv <4 x i64> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %V8i64 = sdiv <8 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2i64 = sdiv <2 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4i64 = sdiv <4 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i64 = sdiv <8 x i64> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = sdiv i32 undef, -16 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4i32 = sdiv <4 x i32> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 104 for instruction: %V8i32 = sdiv <8 x i32> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 208 for instruction: %V16i32 = sdiv <16 x i32> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i32 = sdiv <8 x i32> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i32 = sdiv <16 x i32> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = sdiv i16 undef, -16 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8i16 = sdiv <8 x i16> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 216 for instruction: %V16i16 = sdiv <16 x i16> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 432 for instruction: %V32i16 = sdiv <32 x i16> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i16 = sdiv <16 x i16> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i16 = sdiv <32 x i16> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = sdiv i8 undef, -16 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16i8 = sdiv <16 x i8> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 440 for instruction: %V32i8 = sdiv <32 x i8> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 880 for instruction: %V64i8 = sdiv <64 x i8> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i8 = sdiv <32 x i8> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V64i8 = sdiv <64 x i8> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; %I64 = sdiv i64 undef, -16 @@ -565,21 +565,21 @@ define i32 @udiv_uniformconstnegpow2() { ; CHECK-LABEL: 'udiv_uniformconstnegpow2' ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %I64 = udiv i64 undef, -16 -; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V2i64 = udiv <2 x i64> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V4i64 = udiv <4 x i64> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 192 for instruction: %V8i64 = udiv <8 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V2i64 = udiv <2 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %V4i64 = udiv <4 x i64> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i64 = udiv <8 x i64> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I32 = udiv i32 undef, -16 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V4i32 = udiv <4 x i32> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 104 for instruction: %V8i32 = udiv <8 x i32> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 208 for instruction: %V16i32 = udiv <16 x i32> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 40 for instruction: %V8i32 = udiv <8 x i32> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i32 = udiv <16 x i32> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I16 = udiv i16 undef, -16 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V8i16 = udiv <8 x i16> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 216 for instruction: %V16i16 = udiv <16 x i16> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 432 for instruction: %V32i16 = udiv <32 x i16> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 80 for instruction: %V16i16 = udiv <16 x i16> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i16 = udiv <32 x i16> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %I8 = udiv i8 undef, -16 ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V16i8 = udiv <16 x i8> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 440 for instruction: %V32i8 = udiv <32 x i8> undef, -; CHECK-NEXT: Cost Model: Found an estimated cost of 880 for instruction: %V64i8 = udiv <64 x i8> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 160 for instruction: %V32i8 = udiv <32 x i8> undef, +; CHECK-NEXT: Cost Model: Found an estimated cost of 320 for instruction: %V64i8 = udiv <64 x i8> undef, ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef ; %I64 = udiv i64 undef, -16 diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/always_uniform.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/always_uniform.ll --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/always_uniform.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/always_uniform.ll @@ -47,8 +47,8 @@ %asm = call { i32, i32 } asm "; def $0, $1, $2","=s,=v,v"(i32 %divergent) %sgpr = extractvalue { i32, i32 } %asm, 0 %vgpr = extractvalue { i32, i32 } %asm, 1 - store i32 %sgpr, i32 addrspace(1)* undef - store i32 %vgpr, i32 addrspace(1)* undef + store i32 %sgpr, ptr addrspace(1) undef + store i32 %vgpr, ptr addrspace(1) undef ret void } diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/atomics.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/atomics.ll --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/atomics.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/atomics.ll @@ -1,57 +1,57 @@ ; RUN: opt -mtriple amdgcn-- -passes='print' -disable-output %s 2>&1 | FileCheck %s -; CHECK: DIVERGENT: %orig = atomicrmw xchg i32* %ptr, i32 %val seq_cst -define amdgpu_kernel void @test1(i32* %ptr, i32 %val) #0 { - %orig = atomicrmw xchg i32* %ptr, i32 %val seq_cst - store i32 %orig, i32* %ptr +; CHECK: DIVERGENT: %orig = atomicrmw xchg ptr %ptr, i32 %val seq_cst +define amdgpu_kernel void @test1(ptr %ptr, i32 %val) #0 { + %orig = atomicrmw xchg ptr %ptr, i32 %val seq_cst + store i32 %orig, ptr %ptr ret void } -; CHECK: DIVERGENT: %orig = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst -define amdgpu_kernel void @test2(i32* %ptr, i32 %cmp, i32 %new) { - %orig = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst +; CHECK: DIVERGENT: %orig = cmpxchg ptr %ptr, i32 %cmp, i32 %new seq_cst seq_cst +define amdgpu_kernel void @test2(ptr %ptr, i32 %cmp, i32 %new) { + %orig = cmpxchg ptr %ptr, i32 %cmp, i32 %new seq_cst seq_cst %val = extractvalue { i32, i1 } %orig, 0 - store i32 %val, i32* %ptr + store i32 %val, ptr %ptr ret void } -; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, i1 false) -define i32 @test_atomic_inc_i32(i32 addrspace(1)* %ptr, i32 %val) #0 { - %ret = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, i1 false) +; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.atomic.inc.i32.p1(ptr addrspace(1) %ptr, i32 %val, i32 0, i32 0, i1 false) +define i32 @test_atomic_inc_i32(ptr addrspace(1) %ptr, i32 %val) #0 { + %ret = call i32 @llvm.amdgcn.atomic.inc.i32.p1(ptr addrspace(1) %ptr, i32 %val, i32 0, i32 0, i1 false) ret i32 %ret } -; CHECK: DIVERGENT: %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, i1 false) -define i64 @test_atomic_inc_i64(i64 addrspace(1)* %ptr, i64 %val) #0 { - %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, i1 false) +; CHECK: DIVERGENT: %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p1(ptr addrspace(1) %ptr, i64 %val, i32 0, i32 0, i1 false) +define i64 @test_atomic_inc_i64(ptr addrspace(1) %ptr, i64 %val) #0 { + %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p1(ptr addrspace(1) %ptr, i64 %val, i32 0, i32 0, i1 false) ret i64 %ret } -; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, i1 false) -define i32 @test_atomic_dec_i32(i32 addrspace(1)* %ptr, i32 %val) #0 { - %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, i1 false) +; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1(ptr addrspace(1) %ptr, i32 %val, i32 0, i32 0, i1 false) +define i32 @test_atomic_dec_i32(ptr addrspace(1) %ptr, i32 %val) #0 { + %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1(ptr addrspace(1) %ptr, i32 %val, i32 0, i32 0, i1 false) ret i32 %ret } -; CHECK: DIVERGENT: %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, i1 false) -define i64 @test_atomic_dec_i64(i64 addrspace(1)* %ptr, i64 %val) #0 { - %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, i1 false) +; CHECK: DIVERGENT: %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1(ptr addrspace(1) %ptr, i64 %val, i32 0, i32 0, i1 false) +define i64 @test_atomic_dec_i64(ptr addrspace(1) %ptr, i64 %val) #0 { + %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1(ptr addrspace(1) %ptr, i64 %val, i32 0, i32 0, i1 false) ret i64 %ret } -declare i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #1 -declare i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #1 -declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #1 -declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #1 +declare i32 @llvm.amdgcn.atomic.inc.i32.p1(ptr addrspace(1) nocapture, i32, i32, i32, i1) #1 +declare i64 @llvm.amdgcn.atomic.inc.i64.p1(ptr addrspace(1) nocapture, i64, i32, i32, i1) #1 +declare i32 @llvm.amdgcn.atomic.dec.i32.p1(ptr addrspace(1) nocapture, i32, i32, i32, i1) #1 +declare i64 @llvm.amdgcn.atomic.dec.i64.p1(ptr addrspace(1) nocapture, i64, i32, i32, i1) #1 -; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %val) -define amdgpu_kernel void @test_atomic_csub_i32(i32 addrspace(1)* %ptr, i32 %val) #0 { - %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %val) - store i32 %ret, i32 addrspace(1)* %ptr, align 4 +; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) %ptr, i32 %val) +define amdgpu_kernel void @test_atomic_csub_i32(ptr addrspace(1) %ptr, i32 %val) #0 { + %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) %ptr, i32 %val) + store i32 %ret, ptr addrspace(1) %ptr, align 4 ret void } -declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #1 +declare i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) nocapture, i32) #1 attributes #0 = { nounwind } attributes #1 = { argmemonly nounwind willreturn } diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/b42473-r1-crash.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/b42473-r1-crash.ll --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/b42473-r1-crash.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/b42473-r1-crash.ll @@ -3,10 +3,10 @@ declare i32 @gf2(i32) declare i32 @gf1(i32) -define void @tw1(i32 addrspace(4)* noalias nocapture readonly %A, i32 addrspace(4)* noalias nocapture %B) local_unnamed_addr #2 { +define void @tw1(ptr addrspace(4) noalias nocapture readonly %A, ptr addrspace(4) noalias nocapture %B) local_unnamed_addr #2 { ; CHECK: Divergence Analysis' for function 'tw1': -; CHECK: DIVERGENT: i32 addrspace(4)* %A -; CHECK: DIVERGENT: i32 addrspace(4)* %B +; CHECK: DIVERGENT: ptr addrspace(4) %A +; CHECK: DIVERGENT: ptr addrspace(4) %B entry: ; CHECK: DIVERGENT: %call = tail call i32 @gf2(i32 0) #0 ; CHECK: DIVERGENT: %cmp = icmp ult i32 %call, 16 @@ -17,66 +17,66 @@ if.then: ; CHECK: DIVERGENT: %call1 = tail call i32 @gf1(i32 0) #0 -; CHECK: DIVERGENT: %arrayidx = getelementptr inbounds i32, i32 addrspace(4)* %A, i32 %call1 -; CHECK: DIVERGENT: %0 = load i32, i32 addrspace(4)* %arrayidx, align 4 +; CHECK: DIVERGENT: %arrayidx = getelementptr inbounds i32, ptr addrspace(4) %A, i32 %call1 +; CHECK: DIVERGENT: %0 = load i32, ptr addrspace(4) %arrayidx, align 4 ; CHECK: DIVERGENT: %cmp225 = icmp sgt i32 %0, 0 -; CHECK: DIVERGENT: %arrayidx10 = getelementptr inbounds i32, i32 addrspace(4)* %B, i32 %call1 +; CHECK: DIVERGENT: %arrayidx10 = getelementptr inbounds i32, ptr addrspace(4) %B, i32 %call1 ; CHECK: DIVERGENT: br i1 %cmp225, label %while.body.preheader, label %if.then.while.end_crit_edge %call1 = tail call i32 @gf1(i32 0) #4 - %arrayidx = getelementptr inbounds i32, i32 addrspace(4)* %A, i32 %call1 - %0 = load i32, i32 addrspace(4)* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, ptr addrspace(4) %A, i32 %call1 + %0 = load i32, ptr addrspace(4) %arrayidx, align 4 %cmp225 = icmp sgt i32 %0, 0 - %arrayidx10 = getelementptr inbounds i32, i32 addrspace(4)* %B, i32 %call1 + %arrayidx10 = getelementptr inbounds i32, ptr addrspace(4) %B, i32 %call1 br i1 %cmp225, label %while.body.preheader, label %if.then.while.end_crit_edge while.body.preheader: br label %while.body if.then.while.end_crit_edge: -; CHECK: DIVERGENT: %.pre = load i32, i32 addrspace(4)* %arrayidx10, align 4 - %.pre = load i32, i32 addrspace(4)* %arrayidx10, align 4 +; CHECK: DIVERGENT: %.pre = load i32, ptr addrspace(4) %arrayidx10, align 4 + %.pre = load i32, ptr addrspace(4) %arrayidx10, align 4 br label %while.end while.body: ; CHECK-NOT: DIVERGENT: %i.026 = phi i32 [ %inc, %if.end.while.body_crit_edge ], [ 0, %while.body.preheader ] ; CHECK: DIVERGENT: %call3 = tail call i32 @gf1(i32 0) #0 ; CHECK: DIVERGENT: %cmp4 = icmp ult i32 %call3, 10 -; CHECK: DIVERGENT: %arrayidx6 = getelementptr inbounds i32, i32 addrspace(4)* %A, i32 %i.026 -; CHECK: DIVERGENT: %1 = load i32, i32 addrspace(4)* %arrayidx6, align 4 +; CHECK: DIVERGENT: %arrayidx6 = getelementptr inbounds i32, ptr addrspace(4) %A, i32 %i.026 +; CHECK: DIVERGENT: %1 = load i32, ptr addrspace(4) %arrayidx6, align 4 ; CHECK: DIVERGENT: br i1 %cmp4, label %if.then5, label %if.else %i.026 = phi i32 [ %inc, %if.end.while.body_crit_edge ], [ 0, %while.body.preheader ] %call3 = tail call i32 @gf1(i32 0) #4 %cmp4 = icmp ult i32 %call3, 10 - %arrayidx6 = getelementptr inbounds i32, i32 addrspace(4)* %A, i32 %i.026 - %1 = load i32, i32 addrspace(4)* %arrayidx6, align 4 + %arrayidx6 = getelementptr inbounds i32, ptr addrspace(4) %A, i32 %i.026 + %1 = load i32, ptr addrspace(4) %arrayidx6, align 4 br i1 %cmp4, label %if.then5, label %if.else if.then5: ; CHECK: DIVERGENT: %mul = shl i32 %1, 1 -; CHECK: DIVERGENT: %2 = load i32, i32 addrspace(4)* %arrayidx10, align 4 +; CHECK: DIVERGENT: %2 = load i32, ptr addrspace(4) %arrayidx10, align 4 ; CHECK: DIVERGENT: %add = add nsw i32 %2, %mul %mul = shl i32 %1, 1 - %2 = load i32, i32 addrspace(4)* %arrayidx10, align 4 + %2 = load i32, ptr addrspace(4) %arrayidx10, align 4 %add = add nsw i32 %2, %mul br label %if.end if.else: ; CHECK: DIVERGENT: %mul9 = shl i32 %1, 2 -; CHECK: DIVERGENT: %3 = load i32, i32 addrspace(4)* %arrayidx10, align 4 +; CHECK: DIVERGENT: %3 = load i32, ptr addrspace(4) %arrayidx10, align 4 ; CHECK: DIVERGENT: %add11 = add nsw i32 %3, %mul9 %mul9 = shl i32 %1, 2 - %3 = load i32, i32 addrspace(4)* %arrayidx10, align 4 + %3 = load i32, ptr addrspace(4) %arrayidx10, align 4 %add11 = add nsw i32 %3, %mul9 br label %if.end if.end: ; CHECK: DIVERGENT: %storemerge = phi i32 [ %add11, %if.else ], [ %add, %if.then5 ] -; CHECK: DIVERGENT: store i32 %storemerge, i32 addrspace(4)* %arrayidx10, align 4 +; CHECK: DIVERGENT: store i32 %storemerge, ptr addrspace(4) %arrayidx10, align 4 ; CHECK-NOT: DIVERGENT: %inc = add nuw nsw i32 %i.026, 1 ; CHECK: DIVERGENT: %exitcond = icmp ne i32 %inc, %0 ; CHECK: DIVERGENT: br i1 %exitcond, label %if.end.while.body_crit_edge, label %while.end.loopexit %storemerge = phi i32 [ %add11, %if.else ], [ %add, %if.then5 ] - store i32 %storemerge, i32 addrspace(4)* %arrayidx10, align 4 + store i32 %storemerge, ptr addrspace(4) %arrayidx10, align 4 %inc = add nuw nsw i32 %i.026, 1 %exitcond = icmp ne i32 %inc, %0 br i1 %exitcond, label %if.end.while.body_crit_edge, label %while.end.loopexit @@ -93,11 +93,11 @@ ; CHECK: DIVERGENT: %4 = phi i32 [ %.pre, %if.then.while.end_crit_edge ], [ %storemerge.lcssa, %while.end.loopexit ] ; CHECK: DIVERGENT: %i.0.lcssa = phi i32 [ 0, %if.then.while.end_crit_edge ], [ %0, %while.end.loopexit ] ; CHECK: DIVERGENT: %sub = sub nsw i32 %4, %i.0.lcssa -; CHECK: DIVERGENT: store i32 %sub, i32 addrspace(4)* %arrayidx10, align 4 +; CHECK: DIVERGENT: store i32 %sub, ptr addrspace(4) %arrayidx10, align 4 %4 = phi i32 [ %.pre, %if.then.while.end_crit_edge ], [ %storemerge.lcssa, %while.end.loopexit ] %i.0.lcssa = phi i32 [ 0, %if.then.while.end_crit_edge ], [ %0, %while.end.loopexit ] %sub = sub nsw i32 %4, %i.0.lcssa - store i32 %sub, i32 addrspace(4)* %arrayidx10, align 4 + store i32 %sub, ptr addrspace(4) %arrayidx10, align 4 br label %new_exit new_exit: diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/control-flow-intrinsics.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/control-flow-intrinsics.ll --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/control-flow-intrinsics.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/control-flow-intrinsics.ll @@ -10,7 +10,7 @@ entry: %cond = icmp eq i32 %arg0, 0 %break = call i64 @llvm.amdgcn.if.break.i64.i64(i1 %cond, i64 %saved) - store volatile i64 %break, i64 addrspace(1)* undef + store volatile i64 %break, ptr addrspace(1) undef ret void } @@ -27,8 +27,8 @@ %if.bool = extractvalue { i1, i64 } %if, 0 %if.mask = extractvalue { i1, i64 } %if, 1 %if.bool.ext = zext i1 %if.bool to i32 - store volatile i32 %if.bool.ext, i32 addrspace(1)* undef - store volatile i64 %if.mask, i64 addrspace(1)* undef + store volatile i32 %if.bool.ext, ptr addrspace(1) undef + store volatile i64 %if.mask, ptr addrspace(1) undef ret void } @@ -46,8 +46,8 @@ %if.bool = extractvalue { i1, i64 } %if, 0 %if.mask = extractvalue { i1, i64 } %if, 1 %if.bool.ext = zext i1 %if.bool to i32 - store volatile i32 %if.bool.ext, i32 addrspace(1)* undef - store volatile i64 %if.mask, i64 addrspace(1)* undef + store volatile i32 %if.bool.ext, ptr addrspace(1) undef + store volatile i64 %if.mask, ptr addrspace(1) undef ret void } @@ -57,7 +57,7 @@ entry: %loop = call i1 @llvm.amdgcn.loop.i64(i64 %mask) %loop.ext = zext i1 %loop to i32 - store volatile i32 %loop.ext, i32 addrspace(1)* undef + store volatile i32 %loop.ext, ptr addrspace(1) undef ret void } @@ -71,8 +71,8 @@ %else.bool = extractvalue { i1, i64 } %else, 0 %else.mask = extractvalue { i1, i64 } %else, 1 %else.bool.ext = zext i1 %else.bool to i32 - store volatile i32 %else.bool.ext, i32 addrspace(1)* undef - store volatile i64 %else.mask, i64 addrspace(1)* undef + store volatile i32 %else.bool.ext, ptr addrspace(1) undef + store volatile i64 %else.mask, ptr addrspace(1) undef ret void } @@ -88,8 +88,8 @@ %if.bool = extractvalue { i1, i64 } %if, 0 %if.mask = extractvalue { i1, i64 } %if, 1 %if.bool.ext = zext i1 %if.bool to i32 - store volatile i32 %if.bool.ext, i32 addrspace(1)* undef - store volatile i64 %if.mask, i64 addrspace(1)* undef + store volatile i32 %if.bool.ext, ptr addrspace(1) undef + store volatile i64 %if.mask, ptr addrspace(1) undef ret void } diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/inline-asm.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/inline-asm.ll --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/inline-asm.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/inline-asm.ll @@ -50,8 +50,8 @@ %asm = call { i32, i32 } asm "; def $0, $1", "=s,=s"() %sgpr0 = extractvalue { i32, i32 } %asm, 0 %sgpr1 = extractvalue { i32, i32 } %asm, 1 - store i32 %sgpr0, i32 addrspace(1)* undef - store i32 %sgpr1, i32 addrspace(1)* undef + store i32 %sgpr0, ptr addrspace(1) undef + store i32 %sgpr1, ptr addrspace(1) undef ret void } @@ -64,8 +64,8 @@ %asm = call { i32, i32 } asm "; def $0, $1", "=s,=v"() %sgpr = extractvalue { i32, i32 } %asm, 0 %vgpr = extractvalue { i32, i32 } %asm, 1 - store i32 %sgpr, i32 addrspace(1)* undef - store i32 %vgpr, i32 addrspace(1)* undef + store i32 %sgpr, ptr addrspace(1) undef + store i32 %vgpr, ptr addrspace(1) undef ret void } @@ -77,8 +77,8 @@ %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s"() %vgpr = extractvalue { i32, i32 } %asm, 0 %sgpr = extractvalue { i32, i32 } %asm, 1 - store i32 %vgpr, i32 addrspace(1)* undef - store i32 %sgpr, i32 addrspace(1)* undef + store i32 %vgpr, ptr addrspace(1) undef + store i32 %sgpr, ptr addrspace(1) undef ret void } @@ -89,8 +89,8 @@ %asm = call { i32, i32 } asm "; def $0, $1", "=s,=s,s"(i32 1234) %sgpr0 = extractvalue { i32, i32 } %asm, 0 %sgpr1 = extractvalue { i32, i32 } %asm, 1 - store i32 %sgpr0, i32 addrspace(1)* undef - store i32 %sgpr1, i32 addrspace(1)* undef + store i32 %sgpr0, ptr addrspace(1) undef + store i32 %sgpr1, ptr addrspace(1) undef ret void } @@ -102,7 +102,7 @@ %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s,v"(i32 1234) %vgpr = extractvalue { i32, i32 } %asm, 0 %sgpr = extractvalue { i32, i32 } %asm, 1 - store i32 %vgpr, i32 addrspace(1)* undef - store i32 %sgpr, i32 addrspace(1)* undef + store i32 %vgpr, ptr addrspace(1) undef + store i32 %sgpr, ptr addrspace(1) undef ret void } diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/intrinsics.ll @@ -1,51 +1,51 @@ ; RUN: opt -mtriple amdgcn-- -passes='print' -disable-output %s 2>&1 | FileCheck %s ; CHECK: DIVERGENT: %swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100) #0 -define amdgpu_kernel void @ds_swizzle(i32 addrspace(1)* %out, i32 %src) #0 { +define amdgpu_kernel void @ds_swizzle(ptr addrspace(1) %out, i32 %src) #0 { %swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100) #0 - store i32 %swizzle, i32 addrspace(1)* %out, align 4 + store i32 %swizzle, ptr addrspace(1) %out, align 4 ret void } ; CHECK: DIVERGENT: %v = call i32 @llvm.amdgcn.permlane16(i32 %src0, i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false) #0 -define amdgpu_kernel void @v_permlane16_b32(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) #0 { +define amdgpu_kernel void @v_permlane16_b32(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #0 { %v = call i32 @llvm.amdgcn.permlane16(i32 %src0, i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false) #0 - store i32 %v, i32 addrspace(1)* %out + store i32 %v, ptr addrspace(1) %out ret void } ; CHECK: DIVERGENT: %v = call i32 @llvm.amdgcn.permlanex16(i32 %src0, i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false) #0 -define amdgpu_kernel void @v_permlanex16_b32(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) #0 { +define amdgpu_kernel void @v_permlanex16_b32(ptr addrspace(1) %out, i32 %src0, i32 %src1, i32 %src2) #0 { %v = call i32 @llvm.amdgcn.permlanex16(i32 %src0, i32 %src0, i32 %src1, i32 %src2, i1 false, i1 false) #0 - store i32 %v, i32 addrspace(1)* %out + store i32 %v, ptr addrspace(1) %out ret void } ; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false) #0 -define amdgpu_kernel void @update_dpp(i32 addrspace(1)* %out, i32 %in1, i32 %in2) #0 { +define amdgpu_kernel void @update_dpp(ptr addrspace(1) %out, i32 %in1, i32 %in2) #0 { %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false) #0 - store i32 %tmp0, i32 addrspace(1)* %out + store i32 %tmp0, ptr addrspace(1) %out ret void } ; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 true) #0 -define amdgpu_kernel void @mov_dpp(i32 addrspace(1)* %out, i32 %in) #0 { +define amdgpu_kernel void @mov_dpp(ptr addrspace(1) %out, i32 %in) #0 { %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 true) #0 - store i32 %tmp0, i32 addrspace(1)* %out + store i32 %tmp0, ptr addrspace(1) %out ret void } ; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %in, i32 1) #0 -define amdgpu_kernel void @mov_dpp8(i32 addrspace(1)* %out, i32 %in) #0 { +define amdgpu_kernel void @mov_dpp8(ptr addrspace(1) %out, i32 %in) #0 { %tmp0 = call i32 @llvm.amdgcn.mov.dpp8.i32(i32 %in, i32 1) #0 - store i32 %tmp0, i32 addrspace(1)* %out + store i32 %tmp0, ptr addrspace(1) %out ret void } ; CHECK: DIVERGENT: %tmp0 = call i32 @llvm.amdgcn.writelane(i32 0, i32 1, i32 2) -define amdgpu_kernel void @writelane(i32 addrspace(1)* %out) #0 { +define amdgpu_kernel void @writelane(ptr addrspace(1) %out) #0 { %tmp0 = call i32 @llvm.amdgcn.writelane(i32 0, i32 1, i32 2) - store i32 %tmp0, i32 addrspace(1)* %out + store i32 %tmp0, ptr addrspace(1) %out ret void } diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll @@ -1,14 +1,14 @@ ; RUN: opt -mtriple amdgcn-- -passes='print' -disable-output %s 2>&1 | FileCheck %s ; CHECK-LABEL: Divergence Analysis' for function 'test_amdgpu_ps': -; CHECK: DIVERGENT: [4 x <16 x i8>] addrspace(4)* %arg0 +; CHECK: DIVERGENT: ptr addrspace(4) %arg0 ; CHECK-NOT: DIVERGENT ; CHECK: DIVERGENT: <2 x i32> %arg3 ; CHECK: DIVERGENT: <3 x i32> %arg4 ; CHECK: DIVERGENT: float %arg5 ; CHECK: DIVERGENT: i32 %arg6 -define amdgpu_ps void @test_amdgpu_ps([4 x <16 x i8>] addrspace(4)* byref([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { +define amdgpu_ps void @test_amdgpu_ps(ptr addrspace(4) byref([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { ret void } @@ -20,7 +20,7 @@ ; CHECK-NOT: %arg4 ; CHECK-NOT: %arg5 ; CHECK-NOT: %arg6 -define amdgpu_kernel void @test_amdgpu_kernel([4 x <16 x i8>] addrspace(4)* byref([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { +define amdgpu_kernel void @test_amdgpu_kernel(ptr addrspace(4) byref([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { ret void } @@ -32,7 +32,7 @@ ; CHECK: DIVERGENT: ; CHECK: DIVERGENT: ; CHECK: DIVERGENT: -define void @test_c([4 x <16 x i8>] addrspace(5)* byval([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { +define void @test_c(ptr addrspace(5) byval([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { ret void } diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/no-return-blocks.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/no-return-blocks.ll --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/no-return-blocks.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/no-return-blocks.ll @@ -1,25 +1,25 @@ ; RUN: opt -mtriple amdgcn-- -passes='print' -disable-output %s 2>&1 | FileCheck %s -; CHECK: DIVERGENT: %tmp5 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp2 -; CHECK: DIVERGENT: %tmp10 = load volatile float, float addrspace(1)* %tmp5, align 4 -; CHECK: DIVERGENT: %tmp11 = load volatile float, float addrspace(1)* %tmp5, align 4 +; CHECK: DIVERGENT: %tmp5 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %tmp2 +; CHECK: DIVERGENT: %tmp10 = load volatile float, ptr addrspace(1) %tmp5, align 4 +; CHECK: DIVERGENT: %tmp11 = load volatile float, ptr addrspace(1) %tmp5, align 4 ; The post dominator tree does not have a root node in this case -define amdgpu_kernel void @no_return_blocks(float addrspace(1)* noalias nocapture readonly %arg, float addrspace(1)* noalias nocapture readonly %arg1) #0 { +define amdgpu_kernel void @no_return_blocks(ptr addrspace(1) noalias nocapture readonly %arg, ptr addrspace(1) noalias nocapture readonly %arg1) #0 { bb0: %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tmp2 = sext i32 %tmp to i64 - %tmp5 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp2 - %tmp6 = load volatile float, float addrspace(1)* %tmp5, align 4 + %tmp5 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %tmp2 + %tmp6 = load volatile float, ptr addrspace(1) %tmp5, align 4 %tmp8 = fcmp olt float %tmp6, 0.000000e+00 br i1 %tmp8, label %bb1, label %bb2 bb1: - %tmp10 = load volatile float, float addrspace(1)* %tmp5, align 4 + %tmp10 = load volatile float, ptr addrspace(1) %tmp5, align 4 br label %bb2 bb2: - %tmp11 = load volatile float, float addrspace(1)* %tmp5, align 4 + %tmp11 = load volatile float, ptr addrspace(1) %tmp5, align 4 br label %bb1 } diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/unreachable-loop-block.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/unreachable-loop-block.ll --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/unreachable-loop-block.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/unreachable-loop-block.ll @@ -6,7 +6,7 @@ unreachable unreachable_loop: ; preds = %do.body.i, %if.then11 - %tmp = cmpxchg volatile i32 addrspace(1)* null, i32 0, i32 0 seq_cst seq_cst + %tmp = cmpxchg volatile ptr addrspace(1) null, i32 0, i32 0 seq_cst seq_cst %cmp.i = extractvalue { i32, i1 } %tmp, 1 br i1 %cmp.i, label %unreachable_loop, label %end diff --git a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/workitem-intrinsics.ll b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/workitem-intrinsics.ll --- a/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/workitem-intrinsics.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/workitem-intrinsics.ll @@ -9,35 +9,35 @@ ; CHECK: DIVERGENT: %id.x = call i32 @llvm.amdgcn.workitem.id.x() define amdgpu_kernel void @workitem_id_x() #1 { %id.x = call i32 @llvm.amdgcn.workitem.id.x() - store volatile i32 %id.x, i32 addrspace(1)* undef + store volatile i32 %id.x, ptr addrspace(1) undef ret void } ; CHECK: DIVERGENT: %id.y = call i32 @llvm.amdgcn.workitem.id.y() define amdgpu_kernel void @workitem_id_y() #1 { %id.y = call i32 @llvm.amdgcn.workitem.id.y() - store volatile i32 %id.y, i32 addrspace(1)* undef + store volatile i32 %id.y, ptr addrspace(1) undef ret void } ; CHECK: DIVERGENT: %id.z = call i32 @llvm.amdgcn.workitem.id.z() define amdgpu_kernel void @workitem_id_z() #1 { %id.z = call i32 @llvm.amdgcn.workitem.id.z() - store volatile i32 %id.z, i32 addrspace(1)* undef + store volatile i32 %id.z, ptr addrspace(1) undef ret void } ; CHECK: DIVERGENT: %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 0, i32 0) define amdgpu_kernel void @mbcnt_lo() #1 { %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 0, i32 0) - store volatile i32 %mbcnt.lo, i32 addrspace(1)* undef + store volatile i32 %mbcnt.lo, ptr addrspace(1) undef ret void } ; CHECK: DIVERGENT: %mbcnt.hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 0, i32 0) define amdgpu_kernel void @mbcnt_hi() #1 { %mbcnt.hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 0, i32 0) - store volatile i32 %mbcnt.hi, i32 addrspace(1)* undef + store volatile i32 %mbcnt.hi, ptr addrspace(1) undef ret void } diff --git a/llvm/test/Analysis/DivergenceAnalysis/NVPTX/daorder.ll b/llvm/test/Analysis/DivergenceAnalysis/NVPTX/daorder.ll --- a/llvm/test/Analysis/DivergenceAnalysis/NVPTX/daorder.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/NVPTX/daorder.ll @@ -44,4 +44,4 @@ declare i32 @llvm.nvvm.read.ptx.sreg.laneid() !nvvm.annotations = !{!0} -!0 = !{i32 (i32)* @daorder, !"kernel", i32 1} +!0 = !{ptr @daorder, !"kernel", i32 1} diff --git a/llvm/test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll b/llvm/test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll --- a/llvm/test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll @@ -168,8 +168,8 @@ declare i32 @llvm.nvvm.read.ptx.sreg.laneid() !nvvm.annotations = !{!0, !1, !2, !3, !4} -!0 = !{i32 (i32, i32, i32)* @no_diverge, !"kernel", i32 1} -!1 = !{i32 (i32, i32)* @sync, !"kernel", i32 1} -!2 = !{i32 (i32, i32, i32)* @mixed, !"kernel", i32 1} -!3 = !{i32 ()* @loop, !"kernel", i32 1} -!4 = !{i32 (i32)* @sync_no_loop, !"kernel", i32 1} +!0 = !{ptr @no_diverge, !"kernel", i32 1} +!1 = !{ptr @sync, !"kernel", i32 1} +!2 = !{ptr @mixed, !"kernel", i32 1} +!3 = !{ptr @loop, !"kernel", i32 1} +!4 = !{ptr @sync_no_loop, !"kernel", i32 1} diff --git a/llvm/test/Analysis/DivergenceAnalysis/NVPTX/hidden_diverge.ll b/llvm/test/Analysis/DivergenceAnalysis/NVPTX/hidden_diverge.ll --- a/llvm/test/Analysis/DivergenceAnalysis/NVPTX/hidden_diverge.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/NVPTX/hidden_diverge.ll @@ -27,4 +27,4 @@ declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() !nvvm.annotations = !{!0} -!0 = !{i32 (i32, i32, i32)* @hidden_diverge, !"kernel", i32 1} +!0 = !{ptr @hidden_diverge, !"kernel", i32 1} diff --git a/llvm/test/Analysis/DivergenceAnalysis/NVPTX/irreducible.ll b/llvm/test/Analysis/DivergenceAnalysis/NVPTX/irreducible.ll --- a/llvm/test/Analysis/DivergenceAnalysis/NVPTX/irreducible.ll +++ b/llvm/test/Analysis/DivergenceAnalysis/NVPTX/irreducible.ll @@ -59,4 +59,4 @@ declare i32 @llvm.nvvm.read.ptx.sreg.laneid() !nvvm.annotations = !{!0} -!0 = !{i32 (i1)* @unstructured_loop, !"kernel", i32 1} +!0 = !{ptr @unstructured_loop, !"kernel", i32 1} diff --git a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/atomics.ll b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/atomics.ll --- a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/atomics.ll +++ b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/atomics.ll @@ -1,57 +1,57 @@ ; RUN: opt -mtriple=amdgcn-- -amdgpu-use-legacy-divergence-analysis -passes='print' 2>&1 -disable-output %s | FileCheck %s -; CHECK: DIVERGENT: %orig = atomicrmw xchg i32* %ptr, i32 %val seq_cst -define amdgpu_kernel void @test1(i32* %ptr, i32 %val) #0 { - %orig = atomicrmw xchg i32* %ptr, i32 %val seq_cst - store i32 %orig, i32* %ptr +; CHECK: DIVERGENT: %orig = atomicrmw xchg ptr %ptr, i32 %val seq_cst +define amdgpu_kernel void @test1(ptr %ptr, i32 %val) #0 { + %orig = atomicrmw xchg ptr %ptr, i32 %val seq_cst + store i32 %orig, ptr %ptr ret void } -; CHECK: DIVERGENT: %orig = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst -define amdgpu_kernel void @test2(i32* %ptr, i32 %cmp, i32 %new) { - %orig = cmpxchg i32* %ptr, i32 %cmp, i32 %new seq_cst seq_cst +; CHECK: DIVERGENT: %orig = cmpxchg ptr %ptr, i32 %cmp, i32 %new seq_cst seq_cst +define amdgpu_kernel void @test2(ptr %ptr, i32 %cmp, i32 %new) { + %orig = cmpxchg ptr %ptr, i32 %cmp, i32 %new seq_cst seq_cst %val = extractvalue { i32, i1 } %orig, 0 - store i32 %val, i32* %ptr + store i32 %val, ptr %ptr ret void } -; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, i1 false) -define i32 @test_atomic_inc_i32(i32 addrspace(1)* %ptr, i32 %val) #0 { - %ret = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, i1 false) +; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.atomic.inc.i32.p1(ptr addrspace(1) %ptr, i32 %val, i32 0, i32 0, i1 false) +define i32 @test_atomic_inc_i32(ptr addrspace(1) %ptr, i32 %val) #0 { + %ret = call i32 @llvm.amdgcn.atomic.inc.i32.p1(ptr addrspace(1) %ptr, i32 %val, i32 0, i32 0, i1 false) ret i32 %ret } -; CHECK: DIVERGENT: %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, i1 false) -define i64 @test_atomic_inc_i64(i64 addrspace(1)* %ptr, i64 %val) #0 { - %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, i1 false) +; CHECK: DIVERGENT: %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p1(ptr addrspace(1) %ptr, i64 %val, i32 0, i32 0, i1 false) +define i64 @test_atomic_inc_i64(ptr addrspace(1) %ptr, i64 %val) #0 { + %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p1(ptr addrspace(1) %ptr, i64 %val, i32 0, i32 0, i1 false) ret i64 %ret } -; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, i1 false) -define i32 @test_atomic_dec_i32(i32 addrspace(1)* %ptr, i32 %val) #0 { - %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 %val, i32 0, i32 0, i1 false) +; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1(ptr addrspace(1) %ptr, i32 %val, i32 0, i32 0, i1 false) +define i32 @test_atomic_dec_i32(ptr addrspace(1) %ptr, i32 %val) #0 { + %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p1(ptr addrspace(1) %ptr, i32 %val, i32 0, i32 0, i1 false) ret i32 %ret } -; CHECK: DIVERGENT: %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, i1 false) -define i64 @test_atomic_dec_i64(i64 addrspace(1)* %ptr, i64 %val) #0 { - %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 %val, i32 0, i32 0, i1 false) +; CHECK: DIVERGENT: %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1(ptr addrspace(1) %ptr, i64 %val, i32 0, i32 0, i1 false) +define i64 @test_atomic_dec_i64(ptr addrspace(1) %ptr, i64 %val) #0 { + %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p1(ptr addrspace(1) %ptr, i64 %val, i32 0, i32 0, i1 false) ret i64 %ret } -declare i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #1 -declare i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #1 -declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #1 -declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #1 +declare i32 @llvm.amdgcn.atomic.inc.i32.p1(ptr addrspace(1) nocapture, i32, i32, i32, i1) #1 +declare i64 @llvm.amdgcn.atomic.inc.i64.p1(ptr addrspace(1) nocapture, i64, i32, i32, i1) #1 +declare i32 @llvm.amdgcn.atomic.dec.i32.p1(ptr addrspace(1) nocapture, i32, i32, i32, i1) #1 +declare i64 @llvm.amdgcn.atomic.dec.i64.p1(ptr addrspace(1) nocapture, i64, i32, i32, i1) #1 -; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %val) -define amdgpu_kernel void @test_atomic_csub_i32(i32 addrspace(1)* %ptr, i32 %val) #0 { - %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %val) - store i32 %ret, i32 addrspace(1)* %ptr, align 4 +; CHECK: DIVERGENT: %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) %ptr, i32 %val) +define amdgpu_kernel void @test_atomic_csub_i32(ptr addrspace(1) %ptr, i32 %val) #0 { + %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) %ptr, i32 %val) + store i32 %ret, ptr addrspace(1) %ptr, align 4 ret void } -declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #1 +declare i32 @llvm.amdgcn.global.atomic.csub.p1(ptr addrspace(1) nocapture, i32) #1 attributes #0 = { nounwind } attributes #1 = { argmemonly nounwind willreturn } diff --git a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/intrinsics.ll b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/intrinsics.ll --- a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/intrinsics.ll +++ b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/intrinsics.ll @@ -1,9 +1,9 @@ ; RUN: opt -mtriple=amdgcn-- -passes='print' 2>&1 -disable-output -amdgpu-use-legacy-divergence-analysis %s | FileCheck %s ; CHECK: DIVERGENT: %swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100) #0 -define amdgpu_kernel void @ds_swizzle(i32 addrspace(1)* %out, i32 %src) #0 { +define amdgpu_kernel void @ds_swizzle(ptr addrspace(1) %out, i32 %src) #0 { %swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100) #0 - store i32 %swizzle, i32 addrspace(1)* %out, align 4 + store i32 %swizzle, ptr addrspace(1) %out, align 4 ret void } diff --git a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll --- a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll +++ b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/kernel-args.ll @@ -1,14 +1,14 @@ ; RUN: opt %s -mtriple amdgcn-- -amdgpu-use-legacy-divergence-analysis -passes='print' 2>&1 -disable-output | FileCheck %s ; CHECK-LABEL: function 'test_amdgpu_ps': -; CHECK: DIVERGENT: [4 x <16 x i8>] addrspace(4)* %arg0 +; CHECK: DIVERGENT: ptr addrspace(4) %arg0 ; CHECK-NOT: DIVERGENT ; CHECK: DIVERGENT: <2 x i32> %arg3 ; CHECK: DIVERGENT: <3 x i32> %arg4 ; CHECK: DIVERGENT: float %arg5 ; CHECK: DIVERGENT: i32 %arg6 -define amdgpu_ps void @test_amdgpu_ps([4 x <16 x i8>] addrspace(4)* byref([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { +define amdgpu_ps void @test_amdgpu_ps(ptr addrspace(4) byref([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { ret void } @@ -20,7 +20,7 @@ ; CHECK-NOT: %arg4 ; CHECK-NOT: %arg5 ; CHECK-NOT: %arg6 -define amdgpu_kernel void @test_amdgpu_kernel([4 x <16 x i8>] addrspace(4)* byref([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { +define amdgpu_kernel void @test_amdgpu_kernel(ptr addrspace(4) byref([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { ret void } @@ -32,7 +32,7 @@ ; CHECK: DIVERGENT: ; CHECK: DIVERGENT: ; CHECK: DIVERGENT: -define void @test_c([4 x <16 x i8>] addrspace(4)* byval([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { +define void @test_c(ptr addrspace(4) byval([4 x <16 x i8>]) %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 { ret void } diff --git a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/loads.ll b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/loads.ll --- a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/loads.ll +++ b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/loads.ll @@ -2,14 +2,14 @@ ; Test that we consider loads from flat and private addrspaces to be divergent. -; CHECK: DIVERGENT: %val = load i32, i32* %flat, align 4 -define amdgpu_kernel void @flat_load(i32* %flat) { - %val = load i32, i32* %flat, align 4 +; CHECK: DIVERGENT: %val = load i32, ptr %flat, align 4 +define amdgpu_kernel void @flat_load(ptr %flat) { + %val = load i32, ptr %flat, align 4 ret void } -; CHECK: DIVERGENT: %val = load i32, i32 addrspace(5)* %priv, align 4 -define amdgpu_kernel void @private_load(i32 addrspace(5)* %priv) { - %val = load i32, i32 addrspace(5)* %priv, align 4 +; CHECK: DIVERGENT: %val = load i32, ptr addrspace(5) %priv, align 4 +define amdgpu_kernel void @private_load(ptr addrspace(5) %priv) { + %val = load i32, ptr addrspace(5) %priv, align 4 ret void } diff --git a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/no-return-blocks.ll b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/no-return-blocks.ll --- a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/no-return-blocks.ll +++ b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/no-return-blocks.ll @@ -1,25 +1,25 @@ ; RUN: opt %s -mtriple amdgcn-- -amdgpu-use-legacy-divergence-analysis -passes='print' 2>&1 -disable-output | FileCheck %s -; CHECK: DIVERGENT: %tmp5 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp2 -; CHECK: DIVERGENT: %tmp10 = load volatile float, float addrspace(1)* %tmp5, align 4 -; CHECK: DIVERGENT: %tmp11 = load volatile float, float addrspace(1)* %tmp5, align 4 +; CHECK: DIVERGENT: %tmp5 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %tmp2 +; CHECK: DIVERGENT: %tmp10 = load volatile float, ptr addrspace(1) %tmp5, align 4 +; CHECK: DIVERGENT: %tmp11 = load volatile float, ptr addrspace(1) %tmp5, align 4 ; The post dominator tree does not have a root node in this case -define amdgpu_kernel void @no_return_blocks(float addrspace(1)* noalias nocapture readonly %arg, float addrspace(1)* noalias nocapture readonly %arg1) #0 { +define amdgpu_kernel void @no_return_blocks(ptr addrspace(1) noalias nocapture readonly %arg, ptr addrspace(1) noalias nocapture readonly %arg1) #0 { bb0: %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tmp2 = sext i32 %tmp to i64 - %tmp5 = getelementptr inbounds float, float addrspace(1)* %arg, i64 %tmp2 - %tmp6 = load volatile float, float addrspace(1)* %tmp5, align 4 + %tmp5 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %tmp2 + %tmp6 = load volatile float, ptr addrspace(1) %tmp5, align 4 %tmp8 = fcmp olt float %tmp6, 0.000000e+00 br i1 %tmp8, label %bb1, label %bb2 bb1: - %tmp10 = load volatile float, float addrspace(1)* %tmp5, align 4 + %tmp10 = load volatile float, ptr addrspace(1) %tmp5, align 4 br label %bb2 bb2: - %tmp11 = load volatile float, float addrspace(1)* %tmp5, align 4 + %tmp11 = load volatile float, ptr addrspace(1) %tmp5, align 4 br label %bb1 } diff --git a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/unreachable-loop-block.ll b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/unreachable-loop-block.ll --- a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/unreachable-loop-block.ll +++ b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/unreachable-loop-block.ll @@ -6,7 +6,7 @@ unreachable unreachable_loop: ; preds = %do.body.i, %if.then11 - %tmp = cmpxchg volatile i32 addrspace(1)* null, i32 0, i32 0 seq_cst seq_cst + %tmp = cmpxchg volatile ptr addrspace(1) null, i32 0, i32 0 seq_cst seq_cst %cmp.i = extractvalue { i32, i1 } %tmp, 1 br i1 %cmp.i, label %unreachable_loop, label %end diff --git a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/workitem-intrinsics.ll b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/workitem-intrinsics.ll --- a/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/workitem-intrinsics.ll +++ b/llvm/test/Analysis/LegacyDivergenceAnalysis/AMDGPU/workitem-intrinsics.ll @@ -9,35 +9,35 @@ ; CHECK: DIVERGENT: %id.x = call i32 @llvm.amdgcn.workitem.id.x() define amdgpu_kernel void @workitem_id_x() #1 { %id.x = call i32 @llvm.amdgcn.workitem.id.x() - store volatile i32 %id.x, i32 addrspace(1)* undef + store volatile i32 %id.x, ptr addrspace(1) undef ret void } ; CHECK: DIVERGENT: %id.y = call i32 @llvm.amdgcn.workitem.id.y() define amdgpu_kernel void @workitem_id_y() #1 { %id.y = call i32 @llvm.amdgcn.workitem.id.y() - store volatile i32 %id.y, i32 addrspace(1)* undef + store volatile i32 %id.y, ptr addrspace(1) undef ret void } ; CHECK: DIVERGENT: %id.z = call i32 @llvm.amdgcn.workitem.id.z() define amdgpu_kernel void @workitem_id_z() #1 { %id.z = call i32 @llvm.amdgcn.workitem.id.z() - store volatile i32 %id.z, i32 addrspace(1)* undef + store volatile i32 %id.z, ptr addrspace(1) undef ret void } ; CHECK: DIVERGENT: %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 0, i32 0) define amdgpu_kernel void @mbcnt_lo() #1 { %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 0, i32 0) - store volatile i32 %mbcnt.lo, i32 addrspace(1)* undef + store volatile i32 %mbcnt.lo, ptr addrspace(1) undef ret void } ; CHECK: DIVERGENT: %mbcnt.hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 0, i32 0) define amdgpu_kernel void @mbcnt_hi() #1 { %mbcnt.hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 0, i32 0) - store volatile i32 %mbcnt.hi, i32 addrspace(1)* undef + store volatile i32 %mbcnt.hi, ptr addrspace(1) undef ret void } diff --git a/llvm/test/Analysis/LegacyDivergenceAnalysis/NVPTX/diverge.ll b/llvm/test/Analysis/LegacyDivergenceAnalysis/NVPTX/diverge.ll --- a/llvm/test/Analysis/LegacyDivergenceAnalysis/NVPTX/diverge.ll +++ b/llvm/test/Analysis/LegacyDivergenceAnalysis/NVPTX/diverge.ll @@ -211,9 +211,9 @@ declare i32 @llvm.nvvm.read.ptx.sreg.laneid() !nvvm.annotations = !{!0, !1, !2, !3, !4, !5} -!0 = !{i32 (i32, i32, i32)* @no_diverge, !"kernel", i32 1} -!1 = !{i32 (i32, i32)* @sync, !"kernel", i32 1} -!2 = !{i32 (i32, i32, i32)* @mixed, !"kernel", i32 1} -!3 = !{i32 ()* @loop, !"kernel", i32 1} -!4 = !{i32 (i1)* @unstructured_loop, !"kernel", i32 1} -!5 = !{i32 (i32)* @sync_no_loop, !"kernel", i32 1} +!0 = !{ptr @no_diverge, !"kernel", i32 1} +!1 = !{ptr @sync, !"kernel", i32 1} +!2 = !{ptr @mixed, !"kernel", i32 1} +!3 = !{ptr @loop, !"kernel", i32 1} +!4 = !{ptr @unstructured_loop, !"kernel", i32 1} +!5 = !{ptr @sync_no_loop, !"kernel", i32 1} diff --git a/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride1.ll b/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride1.ll --- a/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride1.ll +++ b/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride1.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -disable-output "-passes=print" 2>&1 | FileCheck %s ; CHECK: Loop %bb: backedge-taken count is ((-5 + %x) /u 3) -; CHECK: Loop %bb: max backedge-taken count is 1431655764 +; CHECK: Loop %bb: constant max backedge-taken count is 1431655764 ; ScalarEvolution can't compute a trip count because it doesn't know if diff --git a/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll b/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll --- a/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll +++ b/llvm/test/Analysis/ScalarEvolution/2008-11-18-Stride2.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -disable-output "-passes=print" 2>&1 2>&1 | FileCheck %s ; CHECK: Loop %bb: backedge-taken count is (((-3 + (-1 * (1 umin (-3 + (-1 * %x) + (1000 umax (3 + %x))))) + (-1 * %x) + (1000 umax (3 + %x))) /u 3) + (1 umin (-3 + (-1 * %x) + (1000 umax (3 + %x))))) -; CHECK: Loop %bb: max backedge-taken count is 334 +; CHECK: Loop %bb: constant max backedge-taken count is 334 ; This is a tricky testcase for unsigned wrap detection which ScalarEvolution diff --git a/llvm/test/Analysis/ScalarEvolution/add-expr-pointer-operand-sorting.ll b/llvm/test/Analysis/ScalarEvolution/add-expr-pointer-operand-sorting.ll --- a/llvm/test/Analysis/ScalarEvolution/add-expr-pointer-operand-sorting.ll +++ b/llvm/test/Analysis/ScalarEvolution/add-expr-pointer-operand-sorting.ll @@ -47,7 +47,8 @@ ; CHECK-NEXT: --> {(1 + %base),+,1}<%for.cond> U: full-set S: full-set Exits: <> LoopDispositions: { %for.cond: Computable } ; CHECK-NEXT: Determining loop execution counts for: @d ; CHECK-NEXT: Loop %for.cond: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.cond: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.cond: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.cond: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.cond: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/addrec-computed-during-addrec-calculation.ll b/llvm/test/Analysis/ScalarEvolution/addrec-computed-during-addrec-calculation.ll --- a/llvm/test/Analysis/ScalarEvolution/addrec-computed-during-addrec-calculation.ll +++ b/llvm/test/Analysis/ScalarEvolution/addrec-computed-during-addrec-calculation.ll @@ -27,15 +27,18 @@ ; CHECK-NEXT: --> {{\{}}{%iv,+,1}<%loop2>,+,1}<%loop3> U: full-set S: full-set --> {%iv,+,1}<%loop2> U: full-set S: full-set Exits: <> LoopDispositions: { %loop.header: Variant, %loop2: Variant, %loop3: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test ; CHECK-NEXT: Loop %loop2: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop2: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop2: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop2: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop2: Unpredictable predicated backedge-taken count. ; CHECK-NEXT: Loop %loop3: backedge-taken count is false -; CHECK-NEXT: Loop %loop3: max backedge-taken count is false +; CHECK-NEXT: Loop %loop3: constant max backedge-taken count is false +; CHECK-NEXT: Loop %loop3: symbolic max backedge-taken count is false ; CHECK-NEXT: Loop %loop3: Predicated backedge-taken count is false ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop3: Trip multiple is 1 ; CHECK-NEXT: Loop %loop.header: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop.header: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop.header: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop.header: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop.header: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/becount-invalidation.ll b/llvm/test/Analysis/ScalarEvolution/becount-invalidation.ll --- a/llvm/test/Analysis/ScalarEvolution/becount-invalidation.ll +++ b/llvm/test/Analysis/ScalarEvolution/becount-invalidation.ll @@ -30,10 +30,14 @@ ; CHECK-NEXT: Loop %loop2.header: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop2.header: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for loop2.latch: false -; CHECK-NEXT: Loop %loop2.header: max backedge-taken count is false +; CHECK-NEXT: Loop %loop2.header: constant max backedge-taken count is false +; CHECK-NEXT: Loop %loop2.header: symbolic max backedge-taken count is false +; CHECK-NEXT: symbolic max exit count for loop2.header: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for loop2.latch: false ; CHECK-NEXT: Loop %loop2.header: Unpredictable predicated backedge-taken count. ; CHECK-NEXT: Loop %loop.header: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop.header: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop.header: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop.header: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop.header: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/cycled_phis.ll b/llvm/test/Analysis/ScalarEvolution/cycled_phis.ll --- a/llvm/test/Analysis/ScalarEvolution/cycled_phis.ll +++ b/llvm/test/Analysis/ScalarEvolution/cycled_phis.ll @@ -15,7 +15,8 @@ ; CHECK-NEXT: --> %cond U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_01 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -51,10 +52,12 @@ ; CHECK-NEXT: --> %outer_cond U: full-set S: full-set Exits: <> LoopDispositions: { %outer_loop: Variant, %inner_loop: Invariant } ; CHECK-NEXT: Determining loop execution counts for: @test_02 ; CHECK-NEXT: Loop %inner_loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %inner_loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %inner_loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %inner_loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %inner_loop: Unpredictable predicated backedge-taken count. ; CHECK-NEXT: Loop %outer_loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %outer_loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %outer_loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %outer_loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %outer_loop: Unpredictable predicated backedge-taken count. ; entry: @@ -102,10 +105,12 @@ ; CHECK-NEXT: --> %outer_cond U: full-set S: full-set Exits: <> LoopDispositions: { %outer_loop: Variant, %inner_loop: Invariant } ; CHECK-NEXT: Determining loop execution counts for: @test_03 ; CHECK-NEXT: Loop %inner_loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %inner_loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %inner_loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %inner_loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %inner_loop: Unpredictable predicated backedge-taken count. ; CHECK-NEXT: Loop %outer_loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %outer_loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %outer_loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %outer_loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %outer_loop: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/exact-exit-count-more-precise.ll b/llvm/test/Analysis/ScalarEvolution/exact-exit-count-more-precise.ll --- a/llvm/test/Analysis/ScalarEvolution/exact-exit-count-more-precise.ll +++ b/llvm/test/Analysis/ScalarEvolution/exact-exit-count-more-precise.ll @@ -14,12 +14,14 @@ ; CHECK-NEXT: --> (%_tmp10.i umin %exitcond.i) U: full-set S: full-set Exits: true LoopDispositions: { %bb1.i: Variant, %bb2: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_and ; CHECK-NEXT: Loop %bb1.i: backedge-taken count is (1 + (-1 * %in)) -; CHECK-NEXT: Loop %bb1.i: max backedge-taken count is -1 +; CHECK-NEXT: Loop %bb1.i: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %bb1.i: symbolic max backedge-taken count is (1 + (-1 * %in)) ; CHECK-NEXT: Loop %bb1.i: Predicated backedge-taken count is (1 + (-1 * %in)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %bb1.i: Trip multiple is 1 ; CHECK-NEXT: Loop %bb2: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %bb2: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %bb2: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %bb2: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %bb2: Unpredictable predicated backedge-taken count. ; br label %bb2 @@ -54,7 +56,8 @@ ; CHECK-NEXT: --> (%C11 umax %C5) U: full-set S: full-set Exits: false LoopDispositions: { %BB: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_or ; CHECK-NEXT: Loop %BB: backedge-taken count is undef -; CHECK-NEXT: Loop %BB: max backedge-taken count is -1 +; CHECK-NEXT: Loop %BB: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %BB: symbolic max backedge-taken count is undef ; CHECK-NEXT: Loop %BB: Predicated backedge-taken count is undef ; CHECK-NEXT: Predicates: ; CHECK: Loop %BB: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/exhaustive-trip-counts.ll b/llvm/test/Analysis/ScalarEvolution/exhaustive-trip-counts.ll --- a/llvm/test/Analysis/ScalarEvolution/exhaustive-trip-counts.ll +++ b/llvm/test/Analysis/ScalarEvolution/exhaustive-trip-counts.ll @@ -6,7 +6,7 @@ define void @f_0() { ; CHECK-LABEL: Printing analysis 'Scalar Evolution Analysis' for function 'f_0': ; CHECK: Loop %for.body: backedge-taken count is 5 -; CHECK: Loop %for.body: max backedge-taken count is 5 +; CHECK: Loop %for.body: constant max backedge-taken count is 5 ; CHECK: Loop %for.body: Predicated backedge-taken count is 5 entry: diff --git a/llvm/test/Analysis/ScalarEvolution/exit-count-select-safe.ll b/llvm/test/Analysis/ScalarEvolution/exit-count-select-safe.ll --- a/llvm/test/Analysis/ScalarEvolution/exit-count-select-safe.ll +++ b/llvm/test/Analysis/ScalarEvolution/exit-count-select-safe.ll @@ -12,7 +12,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_2ops ; CHECK-NEXT: Loop %loop: backedge-taken count is (%n umin_seq %m) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%n umin_seq %m) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%n umin_seq %m) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -41,7 +42,8 @@ ; CHECK-NEXT: --> (true + ((true + %cond_p0) umin_seq (true + %cond_p1))) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_or_2ops ; CHECK-NEXT: Loop %loop: backedge-taken count is (%n umin_seq %m) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%n umin_seq %m) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%n umin_seq %m) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -72,7 +74,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1 umin_seq %cond_p2) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_3ops ; CHECK-NEXT: Loop %loop: backedge-taken count is (%n umin_seq %m umin_seq %k) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%n umin_seq %m umin_seq %k) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%n umin_seq %m umin_seq %k) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -105,7 +108,8 @@ ; CHECK-NEXT: --> (true + ((true + %cond_p0) umin_seq (true + %cond_p1) umin_seq (true + %cond_p2))) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_or_3ops ; CHECK-NEXT: Loop %loop: backedge-taken count is (%n umin_seq %m umin_seq %k) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%n umin_seq %m umin_seq %k) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%n umin_seq %m umin_seq %k) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -140,7 +144,8 @@ ; CHECK-NEXT: --> (true + ((true + %cond_p0) umin_seq (true + %cond_p1) umin_seq (true + %cond_p2) umin_seq (true + %cond_p3))) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_or_3ops_duplicate ; CHECK-NEXT: Loop %loop: backedge-taken count is (%n umin_seq %m umin_seq %k) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%n umin_seq %m umin_seq %k) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%n umin_seq %m umin_seq %k) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -177,7 +182,8 @@ ; CHECK-NEXT: --> (true + ((true + %cond_p0) umin_seq (true + %cond_p1) umin_seq (true + %cond_p2))) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_or_3ops_redundant_uminseq_operand ; CHECK-NEXT: Loop %loop: backedge-taken count is ((%n umin %m) umin_seq %k) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((%n umin %m) umin_seq %k) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((%n umin %m) umin_seq %k) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -213,7 +219,8 @@ ; CHECK-NEXT: --> (true + ((true + %cond_p0) umin_seq (true + %cond_p1) umin_seq (true + %cond_p2))) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_or_3ops_redundant_umin_operand ; CHECK-NEXT: Loop %loop: backedge-taken count is (%n umin_seq %k umin_seq %m) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%n umin_seq %k umin_seq %m) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%n umin_seq %k umin_seq %m) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -251,7 +258,8 @@ ; CHECK-NEXT: --> (true + ((true + %cond_p0) umin_seq (true + %cond_p1) umin_seq (true + %cond_p2))) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_or_4ops_redundant_operand_across_umins ; CHECK-NEXT: Loop %loop: backedge-taken count is ((%n umin %m) umin_seq %k umin_seq %q) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((%n umin %m) umin_seq %k umin_seq %q) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((%n umin %m) umin_seq %k umin_seq %q) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -290,7 +298,8 @@ ; CHECK-NEXT: --> (true + ((true + %cond_p0) umin_seq (true + %cond_p1) umin_seq (true + %cond_p2))) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_or_3ops_operand_wise_redundant_umin ; CHECK-NEXT: Loop %loop: backedge-taken count is ((%n umin %m) umin_seq %k) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((%n umin %m) umin_seq %k) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((%n umin %m) umin_seq %k) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -327,7 +336,8 @@ ; CHECK-NEXT: --> (true + ((true + %cond_p0) umin_seq (true + %cond_p1))) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_or_3ops_partially_redundant_umin ; CHECK-NEXT: Loop %loop: backedge-taken count is (%n umin_seq (%m umin %k)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%n umin_seq (%m umin %k)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%n umin_seq (%m umin %k)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -372,12 +382,14 @@ ; CHECK-NEXT: --> (true + ((true + %cond_p5) umin_seq (true + %cond_p6) umin_seq (true + %cond_p7))) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_or_5ops_redundant_opearand_of_inner_uminseq ; CHECK-NEXT: Loop %loop: backedge-taken count is (%a umin_seq %b umin_seq ((%e umin_seq %d) umin %c)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%a umin_seq %b umin_seq ((%e umin_seq %d) umin %c)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%a umin_seq %b umin_seq ((%e umin_seq %d) umin %c)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 ; CHECK-NEXT: Loop %first.loop: backedge-taken count is (%e umin_seq %d umin_seq %a) -; CHECK-NEXT: Loop %first.loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %first.loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %first.loop: symbolic max backedge-taken count is (%e umin_seq %d umin_seq %a) ; CHECK-NEXT: Loop %first.loop: Predicated backedge-taken count is (%e umin_seq %d umin_seq %a) ; CHECK-NEXT: Predicates: ; CHECK: Loop %first.loop: Trip multiple is 1 @@ -423,7 +435,8 @@ ; CHECK-NEXT: --> (true + ((true + %cond_p1) umin_seq (true + %cond_p0))) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_2ops_and_constant ; CHECK-NEXT: Loop %loop: backedge-taken count is (42 umin %n) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 42 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 42 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (42 umin %n) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (42 umin %n) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -461,17 +474,20 @@ ; CHECK-NEXT: --> {1,+,1}<%for.cond4> U: [1,2) S: [1,2) Exits: 1 LoopDispositions: { %for.cond4: Computable, %while.cond: Variant } ; CHECK-NEXT: Determining loop execution counts for: @computeSCEVAtScope ; CHECK-NEXT: Loop %for.cond: backedge-taken count is (-1 * %d.0) -; CHECK-NEXT: Loop %for.cond: max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.cond: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.cond: symbolic max backedge-taken count is (-1 * %d.0) ; CHECK-NEXT: Loop %for.cond: Predicated backedge-taken count is (-1 * %d.0) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.cond: Trip multiple is 1 ; CHECK-NEXT: Loop %for.cond4: backedge-taken count is 0 -; CHECK-NEXT: Loop %for.cond4: max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.cond4: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.cond4: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %for.cond4: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.cond4: Trip multiple is 1 ; CHECK-NEXT: Loop %while.cond: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %while.cond: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %while.cond: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %while.cond: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %while.cond: Unpredictable predicated backedge-taken count. ; entry: @@ -527,7 +543,8 @@ ; CHECK-NEXT: --> {(ptrtoint i64* %ptr to i64),+,1}<%loop> U: full-set S: full-set --> ((%n umin_seq %m) + (ptrtoint i64* %ptr to i64)) U: full-set S: full-set ; CHECK-NEXT: Determining loop execution counts for: @uminseq_vs_ptrtoint_complexity ; CHECK-NEXT: Loop %loop: backedge-taken count is (%n umin_seq %m) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%n umin_seq %m) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%n umin_seq %m) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -560,7 +577,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_implies_poison1 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((1 + %n) umin %n) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((1 + %n) umin %n) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((1 + %n) umin %n) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -592,7 +610,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_implies_poison2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((1 + %n) umin %n) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((1 + %n) umin %n) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((1 + %n) umin %n) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -624,7 +643,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_implies_poison3 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((%n + %m) umin %n) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((%n + %m) umin %n) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((%n + %m) umin %n) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -656,7 +676,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_implies_poison_wrong_direction ; CHECK-NEXT: Loop %loop: backedge-taken count is (%n umin_seq (%n + %m)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%n umin_seq (%n + %m)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%n umin_seq (%n + %m)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -686,7 +707,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_implies_poison_noundef ; CHECK-NEXT: Loop %loop: backedge-taken count is (%n umin %m) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%n umin %m) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%n umin %m) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -715,7 +737,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_implies_poison_noundef_wrong_direction ; CHECK-NEXT: Loop %loop: backedge-taken count is (%m umin_seq %n) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%m umin_seq %n) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%m umin_seq %n) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -748,7 +771,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_implies_poison_complex1 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((%n + %m) umin (1 + %n + %m)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((%n + %m) umin (1 + %n + %m)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((%n + %m) umin (1 + %n + %m)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -783,7 +807,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_implies_poison_complex2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((%n + %m) umin (%n + %m + %l)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((%n + %m) umin (%n + %m + %l)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((%n + %m) umin (%n + %m + %l)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -818,7 +843,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_implies_poison_complex_wrong_direction ; CHECK-NEXT: Loop %loop: backedge-taken count is ((%n + %m) umin_seq (%n + %m + %l)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((%n + %m) umin_seq (%n + %m + %l)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((%n + %m) umin_seq (%n + %m + %l)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -853,7 +879,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1 umin_seq %cond_p2) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_implies_multiple_ops ; CHECK-NEXT: Loop %loop: backedge-taken count is (((1 + %n) umin %n) umin_seq %m) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (((1 + %n) umin %n) umin_seq %m) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (((1 + %n) umin %n) umin_seq %m) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -889,7 +916,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1 umin_seq %cond_p2) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_implies_multiple_ops2 ; CHECK-NEXT: Loop %loop: backedge-taken count is (%n umin_seq %m umin_seq (1 + %n)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%n umin_seq %m umin_seq (1 + %n)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%n umin_seq %m umin_seq (1 + %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -925,7 +953,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1 umin_seq %cond_p2) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_implies_multiple_ops3 ; CHECK-NEXT: Loop %loop: backedge-taken count is (%m umin_seq ((1 + %n) umin %n)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%m umin_seq ((1 + %n) umin %n)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%m umin_seq ((1 + %n) umin %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -961,7 +990,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_not_zero ; CHECK-NEXT: Loop %loop: backedge-taken count is ((1 + (zext i16 %n to i32)) umin %m) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 65536 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 65536 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((1 + (zext i16 %n to i32)) umin %m) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((1 + (zext i16 %n to i32)) umin %m) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -996,7 +1026,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_not_zero_wrong_order ; CHECK-NEXT: Loop %loop: backedge-taken count is (%m umin_seq (1 + (zext i16 %n to i32))) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 65536 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 65536 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%m umin_seq (1 + (zext i16 %n to i32))) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%m umin_seq (1 + (zext i16 %n to i32))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1027,7 +1058,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_not_zero_needs_context ; CHECK-NEXT: Loop %loop: backedge-taken count is (%n umin_seq %m) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%n umin_seq %m) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%n umin_seq %m) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1065,7 +1097,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_known_smaller ; CHECK-NEXT: Loop %loop: backedge-taken count is (zext i16 %n to i32) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 65535 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 65535 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (zext i16 %n to i32) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (zext i16 %n to i32) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1103,7 +1136,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_known_smaller_equal ; CHECK-NEXT: Loop %loop: backedge-taken count is (zext i16 %n to i32) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 65535 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 65535 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (zext i16 %n to i32) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (zext i16 %n to i32) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1141,7 +1175,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_not_known_smaller_equal ; CHECK-NEXT: Loop %loop: backedge-taken count is ((zext i16 %n to i32) umin_seq (65534 + (zext i16 %m to i32))) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 65535 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 65535 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((zext i16 %n to i32) umin_seq (65534 + (zext i16 %m to i32))) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((zext i16 %n to i32) umin_seq (65534 + (zext i16 %m to i32))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1179,7 +1214,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_known_greater ; CHECK-NEXT: Loop %loop: backedge-taken count is (zext i16 %n to i32) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 65535 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 65535 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (zext i16 %n to i32) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (zext i16 %n to i32) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1217,7 +1253,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_known_greater_equal ; CHECK-NEXT: Loop %loop: backedge-taken count is (zext i16 %n to i32) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 65535 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 65535 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (zext i16 %n to i32) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (zext i16 %n to i32) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1255,7 +1292,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_not_known_greater_equal ; CHECK-NEXT: Loop %loop: backedge-taken count is ((zext i16 %n to i32) umin (65534 + (zext i16 %m to i32))) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 65535 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 65535 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((zext i16 %n to i32) umin (65534 + (zext i16 %m to i32))) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((zext i16 %n to i32) umin (65534 + (zext i16 %m to i32))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1287,7 +1325,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: false LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_zero_arg1 ; CHECK-NEXT: Loop %loop: backedge-taken count is 0 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 0 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1316,7 +1355,8 @@ ; CHECK-NEXT: --> (%cond_p0 umin_seq %cond_p1) U: full-set S: full-set Exits: false LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_zero_arg2 ; CHECK-NEXT: Loop %loop: backedge-taken count is 0 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 0 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/exit-count-select.ll b/llvm/test/Analysis/ScalarEvolution/exit-count-select.ll --- a/llvm/test/Analysis/ScalarEvolution/exit-count-select.ll +++ b/llvm/test/Analysis/ScalarEvolution/exit-count-select.ll @@ -14,7 +14,8 @@ ; CHECK-NEXT: --> (%cond_i umin_seq %cond_i2) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_m_const ; CHECK-NEXT: Loop %loop: backedge-taken count is (2 umin %n) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (2 umin %n) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (2 umin %n) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -45,7 +46,8 @@ ; CHECK-NEXT: --> (%cond_i umin_seq %cond_i2) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_nonzero ; CHECK-NEXT: Loop %loop: backedge-taken count is (2 umin %m) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (2 umin %m) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (2 umin %m) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -77,7 +79,8 @@ ; CHECK-NEXT: --> (%cond_i umin_seq %cond_i2) U: full-set S: full-set Exits: false LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_zero ; CHECK-NEXT: Loop %loop: backedge-taken count is 0 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 0 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -110,7 +113,8 @@ ; CHECK-NEXT: --> (%cond_i umin_seq %cond_i2) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_and_inversed ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -139,7 +143,8 @@ ; CHECK-NEXT: --> (true + ((true + %cond_i) umin_seq (true + %cond_i2))) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_or_m_const ; CHECK-NEXT: Loop %loop: backedge-taken count is (2 umin %n) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (2 umin %n) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (2 umin %n) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -170,7 +175,8 @@ ; CHECK-NEXT: --> (true + ((true + %cond_i) umin_seq (true + %cond_i2))) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_or_nonzero ; CHECK-NEXT: Loop %loop: backedge-taken count is (2 umin %m) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (2 umin %m) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (2 umin %m) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -202,7 +208,8 @@ ; CHECK-NEXT: --> (true + ((true + %cond_i) umin_seq (true + %cond_i2))) U: full-set S: full-set Exits: true LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_or_zero ; CHECK-NEXT: Loop %loop: backedge-taken count is 0 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 0 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -235,7 +242,8 @@ ; CHECK-NEXT: --> (true + ((true + %cond_i) umin_seq (true + %cond_i2))) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @logical_or_inversed ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/exponential-behavior.ll b/llvm/test/Analysis/ScalarEvolution/exponential-behavior.ll --- a/llvm/test/Analysis/ScalarEvolution/exponential-behavior.ll +++ b/llvm/test/Analysis/ScalarEvolution/exponential-behavior.ll @@ -3,7 +3,7 @@ ; CHECK: Printing analysis 'Scalar Evolution Analysis' for function 'f': ; CHECK: Loop %loop: Unpredictable backedge-taken count. -; CHECK: Loop %loop: max backedge-taken count is 0 +; CHECK: Loop %loop: constant max backedge-taken count is 0 ; CHECK: Loop %loop: Unpredictable predicated backedge-taken count. diff --git a/llvm/test/Analysis/ScalarEvolution/finite-trip-count.ll b/llvm/test/Analysis/ScalarEvolution/finite-trip-count.ll --- a/llvm/test/Analysis/ScalarEvolution/finite-trip-count.ll +++ b/llvm/test/Analysis/ScalarEvolution/finite-trip-count.ll @@ -10,9 +10,11 @@ ; CHECK-LABEL: 'SLE' ; CHECK-NEXT: Determining loop execution counts for: @SLE ; CHECK-NEXT: Loop %for.body: backedge-taken count is (0 smax (1 + %len)) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (0 smax (1 + %len)) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (0 smax (1 + %len)) ; CHECK-NEXT: Predicates: +; CHECK: Loop %for.body: Trip multiple is 1 ; entry: br label %for.body @@ -32,7 +34,9 @@ ; CHECK-LABEL: 'SLE_infinite' ; CHECK-NEXT: Determining loop execution counts for: @SLE_infinite ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: br label %for.body @@ -52,9 +56,11 @@ ; CHECK-LABEL: 'ULE' ; CHECK-NEXT: Determining loop execution counts for: @ULE ; CHECK-NEXT: Loop %for.body: backedge-taken count is (1 + %len) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (1 + %len) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (1 + %len) ; CHECK-NEXT: Predicates: +; CHECK: Loop %for.body: Trip multiple is 1 ; entry: br label %for.body @@ -74,7 +80,9 @@ ; CHECK-LABEL: 'ULE_infinite' ; CHECK-NEXT: Determining loop execution counts for: @ULE_infinite ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: br label %for.body @@ -93,10 +101,12 @@ define void @SGE(i32 %end) willreturn { ; CHECK-LABEL: 'SGE' ; CHECK-NEXT: Determining loop execution counts for: @SGE -; CHECK-NEXT: Loop %for.body: backedge-taken count is (100 + (-1 * (100 smin (-1 + %end)))) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -2147483548 -; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (100 + (-1 * (100 smin (-1 + %end)))) +; CHECK-NEXT: Loop %for.body: backedge-taken count is (100 + (-1 * (100 smin (-1 + %end)))) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -2147483548 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (100 + (-1 * (100 smin (-1 + %end)))) +; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (100 + (-1 * (100 smin (-1 + %end)))) ; CHECK-NEXT: Predicates: +; CHECK: Loop %for.body: Trip multiple is 1 ; entry: br label %for.body @@ -116,7 +126,9 @@ ; CHECK-LABEL: 'SGE_infinite' ; CHECK-NEXT: Determining loop execution counts for: @SGE_infinite ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: br label %for.body @@ -135,10 +147,12 @@ define void @UGE(i32 %end) willreturn { ; CHECK-LABEL: 'UGE' ; CHECK-NEXT: Determining loop execution counts for: @UGE -; CHECK-NEXT: Loop %for.body: backedge-taken count is (100 + (-1 * (100 umin (-1 + %end)))) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 100 -; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (100 + (-1 * (100 umin (-1 + %end)))) +; CHECK-NEXT: Loop %for.body: backedge-taken count is (100 + (-1 * (100 umin (-1 + %end)))) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 100 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (100 + (-1 * (100 umin (-1 + %end)))) +; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (100 + (-1 * (100 umin (-1 + %end)))) ; CHECK-NEXT: Predicates: +; CHECK: Loop %for.body: Trip multiple is 1 ; entry: br label %for.body @@ -158,7 +172,9 @@ ; CHECK-LABEL: 'UGE_infinite' ; CHECK-NEXT: Determining loop execution counts for: @UGE_infinite ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: br label %for.body diff --git a/llvm/test/Analysis/ScalarEvolution/flags-from-poison-noautogen.ll b/llvm/test/Analysis/ScalarEvolution/flags-from-poison-noautogen.ll --- a/llvm/test/Analysis/ScalarEvolution/flags-from-poison-noautogen.ll +++ b/llvm/test/Analysis/ScalarEvolution/flags-from-poison-noautogen.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; RUN: opt < %s -S -disable-output "-passes=print" 2>&1 | FileCheck %s ; This file is conceptually part of flags-from-poison.ll except that the @@ -18,19 +19,19 @@ ; CHECK-NEXT: %i_idx.inc = add nsw i32 %i_idx, 1 ; CHECK-NEXT: --> {1,+,1}<%inner> U: [1,0) S: [1,0) Exits: (1 + %inner_l) LoopDispositions: { %inner: Computable, %outer: Variant } ; CHECK-NEXT: %v = sub nsw i32 %i_idx, %o_idx.inc -; CHECK-NEXT: --> -; NOTE: Line deleted from autogen output due to format confusing regex matcher +; CHECK-NEXT: --> {{\{}}{-1,+,-1}<%outer>,+,1}<%inner> U: full-set S: full-set Exits: {(-1 + %inner_l),+,-1}<%outer> LoopDispositions: { %inner: Computable, %outer: Variant } ; CHECK-NEXT: %forub = udiv i32 1, %v -; CHECK-NEXT: --> -; NOTE: Line deleted from autogen output due to format confusing regex matcher +; CHECK-NEXT: --> (1 /u {{\{}}{-1,+,-1}<%outer>,+,1}<%inner>) U: [0,2) S: [0,2) Exits: (1 /u {(-1 + %inner_l),+,-1}<%outer>) LoopDispositions: { %inner: Computable, %outer: Variant } ; CHECK-NEXT: Determining loop execution counts for: @subrecurrences ; CHECK-NEXT: Loop %inner: backedge-taken count is %inner_l -; CHECK-NEXT: Loop %inner: max backedge-taken count is -1 +; CHECK-NEXT: Loop %inner: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %inner: symbolic max backedge-taken count is %inner_l ; CHECK-NEXT: Loop %inner: Predicated backedge-taken count is %inner_l ; CHECK-NEXT: Predicates: ; CHECK: Loop %inner: Trip multiple is 1 ; CHECK-NEXT: Loop %outer: backedge-taken count is %outer_l -; CHECK-NEXT: Loop %outer: max backedge-taken count is -1 +; CHECK-NEXT: Loop %outer: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %outer: symbolic max backedge-taken count is %outer_l ; CHECK-NEXT: Loop %outer: Predicated backedge-taken count is %outer_l ; CHECK-NEXT: Predicates: ; CHECK: Loop %outer: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll b/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll --- a/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll +++ b/llvm/test/Analysis/ScalarEvolution/flags-from-poison.ll @@ -30,7 +30,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-nsw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -68,7 +69,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-nuw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -107,7 +109,8 @@ ; CHECK-NEXT: --> ((4 * (sext i32 {(1 + %offset),+,1}<%loop> to i64)) + %input) U: full-set S: full-set Exits: ((4 * (sext i32 %needle to i64)) + %input) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-invariant ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %offset) + %needle) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %offset) + %needle) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %offset) + %needle) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -147,7 +150,8 @@ ; CHECK-NEXT: --> ((4 * ((sext i32 {1,+,1}<%loop> to i64) + (sext i32 %offset to i64))) + %input) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-bound ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -180,7 +184,8 @@ ; CHECK-NEXT: --> ((4 * (sext i32 {%offset,+,%offset}<%loop> to i64)) + %input) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-bound-unkn-preheader ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -211,7 +216,8 @@ ; CHECK-NEXT: --> ((4 * (sext i32 {%offset,+,%offset}<%loop> to i64)) + %input) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-bound-unkn-preheader-neg1 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -243,7 +249,8 @@ ; CHECK-NEXT: --> ((4 * (sext i32 {%offset,+,%offset}<%loop> to i64)) + %input) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-bound-unkn-preheader-neg2 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -278,7 +285,8 @@ ; CHECK-NEXT: --> ((4 * (sext i32 (%offset + %i) to i64)) + %input) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-bound-unkn-header ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -312,7 +320,8 @@ ; CHECK-NEXT: --> ((4 * (sext i32 (%offset + %i) to i64)) + %input) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-bound-unkn-header2 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -347,7 +356,8 @@ ; CHECK-NEXT: --> ((4 * (sext i32 (%offset + %i) to i64)) + %input) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test-add-scope-bound-unkn-header-neg ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -382,7 +392,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-nuw-from-icmp ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -421,7 +432,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-no-load ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -458,7 +470,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-not-header ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -496,7 +509,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-not-header2 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -538,7 +552,10 @@ ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for loop2: (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) +; CHECK-NEXT: symbolic max exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for loop2: (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; i1* %cond_buf) { @@ -576,7 +593,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-not-header4 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -617,7 +635,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: <> LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-not-header5 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -651,7 +670,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-call ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -688,7 +708,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-call2 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -724,7 +745,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-gep-propagates-poison ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -762,7 +784,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-mul-propagates ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -800,7 +823,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-mul-propagates-poison ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -837,7 +861,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-mul-propagates-poison-2 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -873,7 +898,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-div ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -907,7 +933,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-div2 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -941,7 +968,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-store ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -983,7 +1011,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-twice ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1026,7 +1055,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-mul-nsw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1063,7 +1093,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-mul-nuw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1102,7 +1133,8 @@ ; CHECK-NEXT: --> {(1 + %start),+,1}<%loop> U: full-set S: full-set Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-shl-nsw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %start) + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1141,7 +1173,8 @@ ; CHECK-NEXT: --> {(1 + %start),+,1}<%loop> U: full-set S: full-set Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-shl-nuw-edgecase ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %start) + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1180,7 +1213,8 @@ ; CHECK-NEXT: --> {(1 + %start),+,1}<%loop> U: full-set S: full-set Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-shl-nuw-nsw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %start) + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1219,7 +1253,8 @@ ; CHECK-NEXT: --> {(1 + %start),+,1}<%loop> U: full-set S: full-set Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-shl-no-nsw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %start) + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1258,7 +1293,8 @@ ; CHECK-NEXT: --> {(1 + %start),+,1}<%loop> U: full-set S: full-set Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-shl-nsw-edgecase ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %start) + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1295,7 +1331,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-shl-nuw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1335,7 +1372,8 @@ ; CHECK-NEXT: --> {(1 + %start),+,1}<%loop> U: full-set S: full-set Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-sub-no-nsw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %start) + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1376,7 +1414,8 @@ ; CHECK-NEXT: --> {(1 + %start),+,1}<%loop> U: full-set S: full-set Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-sub-nsw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %start) + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %start) + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1416,7 +1455,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-sub-nsw-lhs-non-negative ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1460,7 +1500,10 @@ ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for cont: (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) +; CHECK-NEXT: symbolic max exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for cont: (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -1510,7 +1553,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %numIterations LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-sub-with-add ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1577,7 +1621,10 @@ ; CHECK-NEXT: Loop %for.cond: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for if.then: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for if.else: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %for.cond: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.cond: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.cond: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: symbolic max exit count for if.then: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for if.else: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %for.cond: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/incorrect-exit-count.ll b/llvm/test/Analysis/ScalarEvolution/incorrect-exit-count.ll --- a/llvm/test/Analysis/ScalarEvolution/incorrect-exit-count.ll +++ b/llvm/test/Analysis/ScalarEvolution/incorrect-exit-count.ll @@ -60,18 +60,28 @@ ; CHECK-NEXT: Loop %for.cond6: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for for.cond6: 0 ; CHECK-NEXT: exit count for for.end: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %for.cond6: max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.cond6: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.cond6: symbolic max backedge-taken count is 0 +; CHECK-NEXT: symbolic max exit count for for.cond6: 0 +; CHECK-NEXT: symbolic max exit count for for.end: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %for.cond6: Unpredictable predicated backedge-taken count. ; CHECK-NEXT: Loop %inner.loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for inner.loop: 0 ; CHECK-NEXT: exit count for for.end.3: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %inner.loop: max backedge-taken count is 0 +; CHECK-NEXT: Loop %inner.loop: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %inner.loop: symbolic max backedge-taken count is 0 +; CHECK-NEXT: symbolic max exit count for inner.loop: 0 +; CHECK-NEXT: symbolic max exit count for for.end.3: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %inner.loop: Unpredictable predicated backedge-taken count. ; CHECK-NEXT: Loop %outer.loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for for.cond6: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for inner.loop: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for for.inc13.3: 2 -; CHECK-NEXT: Loop %outer.loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %outer.loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %outer.loop: symbolic max backedge-taken count is 2 +; CHECK-NEXT: symbolic max exit count for for.cond6: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for inner.loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for for.inc13.3: 2 ; CHECK-NEXT: Loop %outer.loop: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/increasing-or-decreasing-iv.ll b/llvm/test/Analysis/ScalarEvolution/increasing-or-decreasing-iv.ll --- a/llvm/test/Analysis/ScalarEvolution/increasing-or-decreasing-iv.ll +++ b/llvm/test/Analysis/ScalarEvolution/increasing-or-decreasing-iv.ll @@ -18,7 +18,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,129) S: [1,129) Exits: 128 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @f0 ; CHECK-NEXT: Loop %loop: backedge-taken count is 127 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 127 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 127 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 128 @@ -85,7 +86,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,17) S: [1,17) Exits: 16 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @f1 ; CHECK-NEXT: Loop %loop: backedge-taken count is 15 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 15 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 15 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 15 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 15 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 16 @@ -145,7 +147,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,129) S: [1,129) Exits: 128 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @f2 ; CHECK-NEXT: Loop %loop: backedge-taken count is 127 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 127 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 127 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 128 @@ -187,7 +190,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,129) S: [1,129) Exits: 128 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @f3 ; CHECK-NEXT: Loop %loop: backedge-taken count is 127 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 127 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 127 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 128 @@ -236,7 +240,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,129) S: [1,129) Exits: 128 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @f4 ; CHECK-NEXT: Loop %loop: backedge-taken count is 127 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 127 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 127 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 128 @@ -284,7 +289,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,129) S: [1,129) Exits: 128 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @f5 ; CHECK-NEXT: Loop %loop: backedge-taken count is 127 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 127 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 127 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 128 @@ -329,7 +335,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,129) S: [1,129) Exits: 128 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @f6 ; CHECK-NEXT: Loop %loop: backedge-taken count is 127 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 127 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 127 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 128 @@ -377,7 +384,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,129) S: [1,129) Exits: 128 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @f7 ; CHECK-NEXT: Loop %loop: backedge-taken count is 127 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 127 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 127 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 127 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 128 diff --git a/llvm/test/Analysis/ScalarEvolution/invalidation.ll b/llvm/test/Analysis/ScalarEvolution/invalidation.ll --- a/llvm/test/Analysis/ScalarEvolution/invalidation.ll +++ b/llvm/test/Analysis/ScalarEvolution/invalidation.ll @@ -40,7 +40,7 @@ define void @test(i32 %n) { ; CHECK-LABEL: Classifying expressions for: @test ; CHECK: Loop %loop: backedge-taken count is 14 -; CHECK: Loop %loop: max backedge-taken count is 14 +; CHECK: Loop %loop: constant max backedge-taken count is 14 ; CHECK: Loop %loop: Predicated backedge-taken count is 14 entry: diff --git a/llvm/test/Analysis/ScalarEvolution/load-with-range-metadata.ll b/llvm/test/Analysis/ScalarEvolution/load-with-range-metadata.ll --- a/llvm/test/Analysis/ScalarEvolution/load-with-range-metadata.ll +++ b/llvm/test/Analysis/ScalarEvolution/load-with-range-metadata.ll @@ -7,7 +7,7 @@ br label %loop loop: -; CHECK: Loop %loop: max backedge-taken count is 98 +; CHECK: Loop %loop: constant max backedge-taken count is 98 %index = phi i32 [ 0, %entry ], [ %index.inc, %loop ] %index.inc = add i32 %index, 1 %continue = icmp slt i32 %index.inc, %limit @@ -24,7 +24,7 @@ br label %loop loop: -; CHECK: Loop %loop: max backedge-taken count is 98 +; CHECK: Loop %loop: constant max backedge-taken count is 98 %index = phi i32 [ 0, %entry ], [ %index.inc, %loop ] %index.inc = add i32 %index, 1 %continue = icmp ult i32 %index.inc, %limit diff --git a/llvm/test/Analysis/ScalarEvolution/load.ll b/llvm/test/Analysis/ScalarEvolution/load.ll --- a/llvm/test/Analysis/ScalarEvolution/load.ll +++ b/llvm/test/Analysis/ScalarEvolution/load.ll @@ -31,7 +31,8 @@ ; CHECK-NEXT: --> {1,+,1}<%for.body> U: [1,51) S: [1,51) Exits: 50 LoopDispositions: { %for.body: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test1 ; CHECK-NEXT: Loop %for.body: backedge-taken count is 49 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 49 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 49 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 49 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 49 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 50 @@ -84,7 +85,8 @@ ; CHECK-NEXT: --> %1 U: full-set S: full-set Exits: null LoopDispositions: { %for.body: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test2 ; CHECK-NEXT: Loop %for.body: backedge-taken count is 4 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 4 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 5 diff --git a/llvm/test/Analysis/ScalarEvolution/logical-operations.ll b/llvm/test/Analysis/ScalarEvolution/logical-operations.ll --- a/llvm/test/Analysis/ScalarEvolution/logical-operations.ll +++ b/llvm/test/Analysis/ScalarEvolution/logical-operations.ll @@ -429,7 +429,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,102) S: [1,102) Exits: 101 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @tautological_select_like_phi ; CHECK-NEXT: Loop %loop: backedge-taken count is 100 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 100 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 100 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 100 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 100 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 101 diff --git a/llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info-rewrite-expressions.ll b/llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info-rewrite-expressions.ll --- a/llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info-rewrite-expressions.ll +++ b/llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info-rewrite-expressions.ll @@ -17,7 +17,8 @@ ; CHECK-NEXT: --> {8,+,8}<%loop> U: [8,25) S: [8,25) Exits: (8 + (8 * ((-8 + (8 * ((zext i32 %n to i64) /u 8))) /u 8))) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @rewrite_zext ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-8 + (8 * ((zext i32 %n to i64) /u 8))) /u 8) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-8 + (8 * ((zext i32 %n to i64) /u 8))) /u 8) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-8 + (8 * ((zext i32 %n to i64) /u 8))) /u 8) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -60,7 +61,8 @@ ; CHECK-NEXT: --> {4,+,4}<%loop> U: [4,17) S: [4,17) Exits: (4 + (4 * ((-4 + (4 * ((zext i32 (16 umin %N) to i64) /u 4))) /u 4))) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @rewrite_zext_min_max ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-4 + (4 * ((zext i32 (16 umin %N) to i64) /u 4))) /u 4) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-4 + (4 * ((zext i32 (16 umin %N) to i64) /u 4))) /u 4) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-4 + (4 * ((zext i32 (16 umin %N) to i64) /u 4))) /u 4) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -109,7 +111,8 @@ ; CHECK-NEXT: --> {4,+,4}<%loop> U: [4,5) S: [4,5) Exits: 4 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @rewrite_zext_with_info_from_icmp_ne ; CHECK-NEXT: Loop %loop: backedge-taken count is 0 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 0 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -158,7 +161,8 @@ ; CHECK-NEXT: --> {4,+,4}<%loop> U: [4,4294967297) S: [4,4294967297) Exits: (4 + (4 * ((-4 + (4 * ((4 + (zext i32 (-1 + (zext i2 (trunc i32 %N to i2) to i32)) to i64)) /u 4))) /u 4))) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @rewrite_zext_no_icmp_ne ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-4 + (4 * ((4 + (zext i32 (-1 + (zext i2 (trunc i32 %N to i2) to i32)) to i64)) /u 4))) /u 4) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 1073741823 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 1073741823 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-4 + (4 * ((4 + (zext i32 (-1 + (zext i2 (trunc i32 %N to i2) to i32)) to i64)) /u 4))) /u 4) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-4 + (4 * ((4 + (zext i32 (-1 + (zext i2 (trunc i32 %N to i2) to i32)) to i64)) /u 4))) /u 4) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -199,7 +203,8 @@ ; CHECK-NEXT: --> {8,+,8}<%loop> U: [8,33) S: [8,33) Exits: (8 + (8 * ((-8 + (8 * ((zext i32 %n to i64) /u 8))) /u 8))) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @rewrite_zext_and_base_1 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-8 + (8 * ((zext i32 %n to i64) /u 8))) /u 8) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-8 + (8 * ((zext i32 %n to i64) /u 8))) /u 8) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-8 + (8 * ((zext i32 %n to i64) /u 8))) /u 8) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -243,7 +248,8 @@ ; CHECK-NEXT: --> {8,+,8}<%loop> U: [8,33) S: [8,33) Exits: (8 + (8 * ((-8 + (8 * ((zext i32 %n to i64) /u 8))) /u 8))) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @rewrite_zext_and_base_2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-8 + (8 * ((zext i32 %n to i64) /u 8))) /u 8) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-8 + (8 * ((zext i32 %n to i64) /u 8))) /u 8) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-8 + (8 * ((zext i32 %n to i64) /u 8))) /u 8) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -285,7 +291,8 @@ ; CHECK-NEXT: --> {(2 + %init),+,2}<%loop> U: [4,19) S: [4,19) Exits: (2 + (2 * ((14 + (-1 * %init)) /u 2)) + %init) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @guard_pessimizes_analysis_step2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((14 + (-1 * %init)) /u 2) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((14 + (-1 * %init)) /u 2) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((14 + (-1 * %init)) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll b/llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll --- a/llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll +++ b/llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-guard-info.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; RUN: opt -passes='print' -disable-output %s 2>&1 | FileCheck %s -; Test case for PR40961. The loop guard limit the max backedge-taken count. +; Test case for PR40961. The loop guard limit the constant max backedge-taken count. define void @test_guard_less_than_16(i32* nocapture %a, i64 %i) { ; CHECK-LABEL: 'test_guard_less_than_16' @@ -14,7 +14,8 @@ ; CHECK-NEXT: --> {(1 + %i),+,1}<%loop> U: full-set S: full-set Exits: 16 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_less_than_16 ; CHECK-NEXT: Loop %loop: backedge-taken count is (15 + (-1 * %i)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 15 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 15 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (15 + (-1 * %i)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (15 + (-1 * %i)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -46,7 +47,8 @@ ; CHECK-NEXT: --> {(1 + %i),+,1}<%loop> U: full-set S: full-set Exits: 16 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_less_than_16_operands_swapped ; CHECK-NEXT: Loop %loop: backedge-taken count is (15 + (-1 * %i)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 15 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 15 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (15 + (-1 * %i)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (15 + (-1 * %i)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -78,7 +80,8 @@ ; CHECK-NEXT: --> {(1 + %i),+,1}<%loop> U: full-set S: full-set Exits: 16 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_less_than_16_branches_flipped ; CHECK-NEXT: Loop %loop: backedge-taken count is (15 + (-1 * %i)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (15 + (-1 * %i)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (15 + (-1 * %i)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -110,7 +113,8 @@ ; CHECK-NEXT: --> {(1 + %i),+,1}<%loop> U: full-set S: full-set Exits: 16 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_uge_16_branches_flipped ; CHECK-NEXT: Loop %loop: backedge-taken count is (15 + (-1 * %i)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 15 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 15 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (15 + (-1 * %i)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (15 + (-1 * %i)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -142,7 +146,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,14) S: [1,14) Exits: (1 + %N) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_eq_12 ; CHECK-NEXT: Loop %loop: backedge-taken count is %N -; CHECK-NEXT: Loop %loop: max backedge-taken count is 12 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 12 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %N ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %N ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -174,7 +179,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,14) S: [1,14) Exits: (1 + %N) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_ule_12 ; CHECK-NEXT: Loop %loop: backedge-taken count is %N -; CHECK-NEXT: Loop %loop: max backedge-taken count is 12 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 12 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %N ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %N ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -206,7 +212,8 @@ ; CHECK-NEXT: --> {2,+,2}<%loop> U: [2,15) S: [2,15) Exits: (2 + (2 * (%N /u 2))) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_ule_12_step2 ; CHECK-NEXT: Loop %loop: backedge-taken count is (%N /u 2) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%N /u 2) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%N /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -238,7 +245,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,11) S: [1,11) Exits: (1 + %i) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_multiple_const_guards_order1 ; CHECK-NEXT: Loop %loop: backedge-taken count is %i -; CHECK-NEXT: Loop %loop: max backedge-taken count is 9 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 9 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %i ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %i ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -274,7 +282,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,11) S: [1,11) Exits: (1 + %i) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_multiple_const_guards_order2 ; CHECK-NEXT: Loop %loop: backedge-taken count is %i -; CHECK-NEXT: Loop %loop: max backedge-taken count is 9 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 9 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %i ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %i ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -299,7 +308,7 @@ ret void } -; TODO: Currently we miss getting the tightest max backedge-taken count (11). +; TODO: Currently we miss getting the tightest constant max backedge-taken count (11). define void @test_multiple_var_guards_order1(i32* nocapture %a, i64 %i, i64 %N) { ; CHECK-LABEL: 'test_multiple_var_guards_order1' ; CHECK-NEXT: Classifying expressions for: @test_multiple_var_guards_order1 @@ -311,7 +320,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: (1 + %i) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_multiple_var_guards_order1 ; CHECK-NEXT: Loop %loop: backedge-taken count is %i -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %i ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %i ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -336,7 +346,7 @@ ret void } -; TODO: Currently we miss getting the tightest max backedge-taken count (11). +; TODO: Currently we miss getting the tightest constant max backedge-taken count (11). define void @test_multiple_var_guards_order2(i32* nocapture %a, i64 %i, i64 %N) { ; CHECK-LABEL: 'test_multiple_var_guards_order2' ; CHECK-NEXT: Classifying expressions for: @test_multiple_var_guards_order2 @@ -348,7 +358,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: (1 + %i) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_multiple_var_guards_order2 ; CHECK-NEXT: Loop %loop: backedge-taken count is %i -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %i ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %i ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -385,7 +396,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: (1 + %N) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_multiple_var_guards_cycle ; CHECK-NEXT: Loop %loop: backedge-taken count is %N -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %N ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %N ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -421,7 +433,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,5) S: [1,5) Exits: %count LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_ult_ne ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %count) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %count) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %count) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -457,7 +470,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,5) S: [1,5) Exits: %count LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_ne_ult ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %count) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %count) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %count) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -495,7 +509,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,5) S: [1,5) Exits: %count LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_if_and_enter ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %count) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %count) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %count) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -531,7 +546,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: %count LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_if_and_skip ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %count) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %count) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %count) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -569,7 +585,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,5) S: [1,5) Exits: %count LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_if_and_and ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %count) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %count) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %count) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -608,7 +625,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: %count LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_if_and_or ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %count) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %count) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %count) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -645,7 +663,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,5) S: [1,5) Exits: %count LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_if_or_skip ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %count) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %count) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %count) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -681,7 +700,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: %count LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_if_or_enter ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %count) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %count) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %count) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -719,7 +739,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,5) S: [1,5) Exits: %count LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_if_or_or ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %count) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %count) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %count) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -758,7 +779,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: %count LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_if_or_and ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %count) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %count) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %count) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -783,7 +805,7 @@ } ; Test case for PR47247. Both the guard condition and the assume limit the -; max backedge-taken count. +; constant max backedge-taken count. define void @test_guard_and_assume(i32* nocapture readonly %data, i64 %count) { ; CHECK-LABEL: 'test_guard_and_assume' @@ -796,7 +818,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,5) S: [1,5) Exits: %count LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_and_assume ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %count) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %count) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %count) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -832,7 +855,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,5) S: [1,5) Exits: %count LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_assume_and ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %count) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %count) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %count) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -870,7 +894,8 @@ ; CHECK-NEXT: --> {(1 + %init),+,1}<%loop> U: [3,12) S: [3,12) Exits: 10 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @guard_pessimizes_analysis_step1 ; CHECK-NEXT: Loop %loop: backedge-taken count is (9 + (-1 * %init)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 7 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 7 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (9 + (-1 * %init)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (9 + (-1 * %init)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -910,7 +935,8 @@ ; CHECK-NEXT: --> {(2 + %init),+,2}<%loop> U: [4,12) S: [4,12) Exits: (2 + (2 * ((8 + (-1 * %init)) /u 2)) + %init) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @guard_pessimizes_analysis_step2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((8 + (-1 * %init)) /u 2) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 3 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((8 + (-1 * %init)) /u 2) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((8 + (-1 * %init)) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -951,15 +977,18 @@ ; CHECK-NEXT: --> {(1 + %ptr),+,1}<%while.body125> U: full-set S: full-set Exits: {(-1 + (-1 * (ptrtoint i8* %ptr to i64)) + %ptr),+,-1}<%while.cond111> LoopDispositions: { %while.body125: Computable } ; CHECK-NEXT: Determining loop execution counts for: @crash ; CHECK-NEXT: Loop %while.body125: backedge-taken count is {(-2 + (-1 * (ptrtoint i8* %ptr to i64))),+,-1}<%while.cond111> -; CHECK-NEXT: Loop %while.body125: max backedge-taken count is -2 +; CHECK-NEXT: Loop %while.body125: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %while.body125: symbolic max backedge-taken count is {(-2 + (-1 * (ptrtoint i8* %ptr to i64))),+,-1}<%while.cond111> ; CHECK-NEXT: Loop %while.body125: Predicated backedge-taken count is {(-2 + (-1 * (ptrtoint i8* %ptr to i64))),+,-1}<%while.cond111> ; CHECK-NEXT: Predicates: ; CHECK: Loop %while.body125: Trip multiple is 1 ; CHECK-NEXT: Loop %while.cond111: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %while.cond111: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %while.cond111: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %while.cond111: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %while.cond111: Unpredictable predicated backedge-taken count. ; CHECK-NEXT: Loop %while.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %while.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %while.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %while.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %while.body: Unpredictable predicated backedge-taken count. ; entry: @@ -1002,7 +1031,8 @@ ; CHECK-NEXT: --> {(-1 + (%blockSize /u 4)),+,-1}<%while.body> U: [-1073741823,1073741823) S: [-1073741823,1073741823) Exits: 0 LoopDispositions: { %while.body: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_uge ; CHECK-NEXT: Loop %while.body: backedge-taken count is (-1 + (%blockSize /u 4)) -; CHECK-NEXT: Loop %while.body: max backedge-taken count is 1073741822 +; CHECK-NEXT: Loop %while.body: constant max backedge-taken count is 1073741822 +; CHECK-NEXT: Loop %while.body: symbolic max backedge-taken count is (-1 + (%blockSize /u 4)) ; CHECK-NEXT: Loop %while.body: Predicated backedge-taken count is (-1 + (%blockSize /u 4)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %while.body: Trip multiple is 1 @@ -1038,7 +1068,8 @@ ; CHECK-NEXT: --> {(-1 + (%blockSize /u 4)),+,-1}<%while.body> U: [-1073741823,1073741823) S: [-1073741823,1073741823) Exits: 0 LoopDispositions: { %while.body: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_ugt ; CHECK-NEXT: Loop %while.body: backedge-taken count is (-1 + (%blockSize /u 4)) -; CHECK-NEXT: Loop %while.body: max backedge-taken count is 1073741822 +; CHECK-NEXT: Loop %while.body: constant max backedge-taken count is 1073741822 +; CHECK-NEXT: Loop %while.body: symbolic max backedge-taken count is (-1 + (%blockSize /u 4)) ; CHECK-NEXT: Loop %while.body: Predicated backedge-taken count is (-1 + (%blockSize /u 4)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %while.body: Trip multiple is 1 @@ -1074,7 +1105,8 @@ ; CHECK-NEXT: --> {(-1 + (%blockSize /u 4)),+,-1}<%while.body> U: [-256,1073741823) S: [-256,1073741823) Exits: 0 LoopDispositions: { %while.body: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_uge_and_ule ; CHECK-NEXT: Loop %while.body: backedge-taken count is (-1 + (%blockSize /u 4)) -; CHECK-NEXT: Loop %while.body: max backedge-taken count is 255 +; CHECK-NEXT: Loop %while.body: constant max backedge-taken count is 255 +; CHECK-NEXT: Loop %while.body: symbolic max backedge-taken count is (-1 + (%blockSize /u 4)) ; CHECK-NEXT: Loop %while.body: Predicated backedge-taken count is (-1 + (%blockSize /u 4)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %while.body: Trip multiple is 1 @@ -1114,7 +1146,8 @@ ; CHECK-NEXT: --> {(-1 + (%blockSize /u 4)),+,-1}<%while.body> U: [-256,1073741823) S: [-256,1073741823) Exits: 0 LoopDispositions: { %while.body: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_ugt_and_ult ; CHECK-NEXT: Loop %while.body: backedge-taken count is (-1 + (%blockSize /u 4)) -; CHECK-NEXT: Loop %while.body: max backedge-taken count is 255 +; CHECK-NEXT: Loop %while.body: constant max backedge-taken count is 255 +; CHECK-NEXT: Loop %while.body: symbolic max backedge-taken count is (-1 + (%blockSize /u 4)) ; CHECK-NEXT: Loop %while.body: Predicated backedge-taken count is (-1 + (%blockSize /u 4)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %while.body: Trip multiple is 1 @@ -1156,7 +1189,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,12) S: [1,12) Exits: %N LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_slt_sgt_1 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %N) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 10 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 10 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %N) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %N) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1192,7 +1226,8 @@ ; CHECK-NEXT: --> {(1 + %i),+,1}<%loop> U: full-set S: full-set Exits: 18 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_slt_sgt_2 ; CHECK-NEXT: Loop %loop: backedge-taken count is (17 + (-1 * %i)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 12 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 12 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (17 + (-1 * %i)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (17 + (-1 * %i)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1228,7 +1263,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,13) S: [1,13) Exits: %N LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_sle_sge_1 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %N) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 11 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 11 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %N) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %N) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1264,7 +1300,8 @@ ; CHECK-NEXT: --> {(1 + %i),+,1}<%loop> U: full-set S: full-set Exits: 18 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_guard_sle_sge_2 ; CHECK-NEXT: Loop %loop: backedge-taken count is (17 + (-1 * %i)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 13 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 13 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (17 + (-1 * %i)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (17 + (-1 * %i)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1303,7 +1340,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,8) S: [1,8) Exits: %N LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @optimized_range_check_unsigned ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %N) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %N) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %N) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1339,7 +1377,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,8) S: [1,8) Exits: %N LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @optimized_range_check_unsigned_icmp_ops_swapped ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %N) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %N) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %N) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1377,7 +1416,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,22) S: [1,22) Exits: %N LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @optimized_range_check_unsigned2 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %N) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 20 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 20 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %N) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %N) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1416,7 +1456,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,4) S: [1,4) Exits: %N LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @optimized_range_check_unsigned3 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %N) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %N) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %N) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1454,7 +1495,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %N LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @not_optimized_range_check_unsigned1 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %N) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %N) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %N) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1491,7 +1533,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,-2147483648) S: [1,-2147483648) Exits: %N LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @not_optimized_range_check_unsigned2 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %N) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %N) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %N) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1522,7 +1565,8 @@ ; CHECK-NEXT: --> {4,+,4}<%loop> U: [4,29) S: [4,29) Exits: (4 + (4 * ((-4 + %num) /u 4))) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @sle_sgt_ult_umax_to_smax ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-4 + %num) /u 4) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-4 + %num) /u 4) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-4 + %num) /u 4) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -1559,7 +1603,8 @@ ; CHECK-NEXT: --> {4,+,4}<%loop> U: [4,-3) S: [-2147483648,2147483645) Exits: (4 + (4 * ((-4 + %num) /u 4))) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @ult_sle_sgt_umax_to_smax ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-4 + %num) /u 4) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 1073741823 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 1073741823 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-4 + %num) /u 4) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-4 + %num) /u 4) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-limit-by-wrapping.ll b/llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-limit-by-wrapping.ll --- a/llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-limit-by-wrapping.ll +++ b/llvm/test/Analysis/ScalarEvolution/max-backedge-taken-count-limit-by-wrapping.ll @@ -1,13 +1,18 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; RUN: opt < %s -disable-output "-passes=print" -scalar-evolution-max-iterations=0 -scalar-evolution-classify-expressions=0 2>&1 | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" define void @max_backedge_taken_count_by_wrapping1_nsw_nuw(i8 %N, i8* %ptr) { -; CHECK-LABEL: Determining loop execution counts for: @max_backedge_taken_count_by_wrapping1_nsw_nuw +; CHECK-LABEL: 'max_backedge_taken_count_by_wrapping1_nsw_nuw' +; CHECK-NEXT: Determining loop execution counts for: @max_backedge_taken_count_by_wrapping1_nsw_nuw ; CHECK-NEXT: Loop %loop: backedge-taken count is (%N /u 4) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 63 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 63 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%N /u 4) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%N /u 4) +; CHECK-NEXT: Predicates: +; CHECK: Loop %loop: Trip multiple is 1 ; entry: br label %loop @@ -25,10 +30,14 @@ } define void @max_backedge_taken_count_by_wrapping1_nuw(i8 %N, i8* %ptr) { -; CHECK-LABEL: Determining loop execution counts for: @max_backedge_taken_count_by_wrapping1_nuw +; CHECK-LABEL: 'max_backedge_taken_count_by_wrapping1_nuw' +; CHECK-NEXT: Determining loop execution counts for: @max_backedge_taken_count_by_wrapping1_nuw ; CHECK-NEXT: Loop %loop: backedge-taken count is (%N /u 4) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 63 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 63 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (%N /u 4) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (%N /u 4) +; CHECK-NEXT: Predicates: +; CHECK: Loop %loop: Trip multiple is 1 ; entry: br label %loop @@ -46,10 +55,14 @@ } define void @max_backedge_taken_count_by_wrapping2_nsw_nuw(i8 %N, i8* %ptr) { -; CHECK-LABEL: Determining loop execution counts for: @max_backedge_taken_count_by_wrapping2 +; CHECK-LABEL: 'max_backedge_taken_count_by_wrapping2_nsw_nuw' +; CHECK-NEXT: Determining loop execution counts for: @max_backedge_taken_count_by_wrapping2_nsw_nuw ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-64 + %N) /u 4) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 63 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 63 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-64 + %N) /u 4) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-64 + %N) /u 4) +; CHECK-NEXT: Predicates: +; CHECK: Loop %loop: Trip multiple is 1 ; entry: br label %loop @@ -67,10 +80,14 @@ } define void @max_backedge_taken_count_by_wrapping2_nuw(i8 %N, i8* %ptr) { -; CHECK-LABEL: Determining loop execution counts for: @max_backedge_taken_count_by_wrapping2 -; CHECK-NEXT: Loop %loop: backedge-taken count is ((-64 + %N) /u 4) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 63 +; CHECK-LABEL: 'max_backedge_taken_count_by_wrapping2_nuw' +; CHECK-NEXT: Determining loop execution counts for: @max_backedge_taken_count_by_wrapping2_nuw +; CHECK-NEXT: Loop %loop: backedge-taken count is ((-64 + %N) /u 4) +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 63 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-64 + %N) /u 4) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-64 + %N) /u 4) +; CHECK-NEXT: Predicates: +; CHECK: Loop %loop: Trip multiple is 1 ; entry: br label %loop diff --git a/llvm/test/Analysis/ScalarEvolution/max-be-count-not-constant.ll b/llvm/test/Analysis/ScalarEvolution/max-be-count-not-constant.ll --- a/llvm/test/Analysis/ScalarEvolution/max-be-count-not-constant.ll +++ b/llvm/test/Analysis/ScalarEvolution/max-be-count-not-constant.ll @@ -21,7 +21,8 @@ ; CHECK-NEXT: --> {(2 + %tmp),+,(2 + %tmp)}<%bb2> U: [1,5) S: [1,5) Exits: (2 + ((2 + %tmp) * (1 /u (2 + %tmp))) + %tmp) LoopDispositions: { %bb2: Computable } ; CHECK-NEXT: Determining loop execution counts for: @pluto ; CHECK-NEXT: Loop %bb2: backedge-taken count is (1 /u (2 + %tmp)) -; CHECK-NEXT: Loop %bb2: max backedge-taken count is 1 +; CHECK-NEXT: Loop %bb2: constant max backedge-taken count is 1 +; CHECK-NEXT: Loop %bb2: symbolic max backedge-taken count is (1 /u (2 + %tmp)) ; CHECK-NEXT: Loop %bb2: Predicated backedge-taken count is (1 /u (2 + %tmp)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %bb2: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/max-trip-count-address-space.ll b/llvm/test/Analysis/ScalarEvolution/max-trip-count-address-space.ll --- a/llvm/test/Analysis/ScalarEvolution/max-trip-count-address-space.ll +++ b/llvm/test/Analysis/ScalarEvolution/max-trip-count-address-space.ll @@ -65,4 +65,4 @@ ; CHECK: Determining loop execution counts for: @test ; CHECK-NEXT: backedge-taken count is -; CHECK-NEXT: max backedge-taken count is 2147483646 +; CHECK-NEXT: constant max backedge-taken count is 2147483646 diff --git a/llvm/test/Analysis/ScalarEvolution/max-trip-count.ll b/llvm/test/Analysis/ScalarEvolution/max-trip-count.ll --- a/llvm/test/Analysis/ScalarEvolution/max-trip-count.ll +++ b/llvm/test/Analysis/ScalarEvolution/max-trip-count.ll @@ -40,7 +40,7 @@ ; PR7845 ; CHECK: Loop %for.cond: Unpredictable backedge-taken count. -; CHECK: Loop %for.cond: max backedge-taken count is 5 +; CHECK: Loop %for.cond: constant max backedge-taken count is 5 @.str = private constant [4 x i8] c"%d\0A\00" ; <[4 x i8]*> [#uses=2] @@ -97,12 +97,12 @@ ; CHECK: Determining loop execution counts for: @test ; CHECK-NEXT: backedge-taken count is -; CHECK-NEXT: max backedge-taken count is 2147483646 +; CHECK-NEXT: constant max backedge-taken count is 2147483646 ; PR19799: Indvars miscompile due to an incorrect max backedge taken count from SCEV. ; CHECK-LABEL: @pr19799 ; CHECK: Loop %for.body.i: Unpredictable backedge-taken count. -; CHECK: Loop %for.body.i: max backedge-taken count is 1 +; CHECK: Loop %for.body.i: constant max backedge-taken count is 1 @a = common global i32 0, align 4 define i32 @pr19799() { @@ -128,7 +128,7 @@ ; PR18886: Indvars miscompile due to an incorrect max backedge taken count from SCEV. ; CHECK-LABEL: @pr18886 ; CHECK: Loop %for.body: Unpredictable backedge-taken count. -; CHECK: Loop %for.body: max backedge-taken count is 3 +; CHECK: Loop %for.body: constant max backedge-taken count is 3 @aa = global i64 0, align 8 define i32 @pr18886() { @@ -158,7 +158,7 @@ ; ; CHECK-LABEL: @cannot_compute_mustexit ; CHECK: Loop %for.body.i: Unpredictable backedge-taken count. -; CHECK: Loop %for.body.i: Unpredictable max backedge-taken count. +; CHECK: Loop %for.body.i: Unpredictable constant max backedge-taken count. @b = common global i32 0, align 4 define i32 @cannot_compute_mustexit() { @@ -187,7 +187,7 @@ ; ; CHECK-LABEL: @two_mustexit ; CHECK: Loop %for.body.i: backedge-taken count is 1 -; CHECK: Loop %for.body.i: max backedge-taken count is 1 +; CHECK: Loop %for.body.i: constant max backedge-taken count is 1 define i32 @two_mustexit() { entry: store i32 -1, i32* @a, align 4 @@ -209,7 +209,7 @@ } ; CHECK-LABEL: @ne_max_trip_count_1 -; CHECK: Loop %for.body: max backedge-taken count is 7 +; CHECK: Loop %for.body: constant max backedge-taken count is 7 define i32 @ne_max_trip_count_1(i32 %n) { entry: %masked = and i32 %n, 7 @@ -226,7 +226,7 @@ } ; CHECK-LABEL: @ne_max_trip_count_2 -; CHECK: Loop %for.body: max backedge-taken count is -1 +; CHECK: Loop %for.body: constant max backedge-taken count is -1 define i32 @ne_max_trip_count_2(i32 %n) { entry: %masked = and i32 %n, 7 @@ -243,7 +243,7 @@ } ; CHECK-LABEL: @ne_max_trip_count_3 -; CHECK: Loop %for.body: max backedge-taken count is 6 +; CHECK: Loop %for.body: constant max backedge-taken count is 6 define i32 @ne_max_trip_count_3(i32 %n) { entry: %masked = and i32 %n, 7 @@ -267,7 +267,7 @@ } ; CHECK-LABEL: @ne_max_trip_count_4 -; CHECK: Loop %for.body: max backedge-taken count is -2 +; CHECK: Loop %for.body: constant max backedge-taken count is -2 define i32 @ne_max_trip_count_4(i32 %n) { entry: %guard = icmp eq i32 %n, 0 @@ -294,7 +294,7 @@ define void @changing_end_bound(i32* %n_addr, i32* %addr) { ; CHECK-LABEL: Determining loop execution counts for: @changing_end_bound ; CHECK: Loop %loop: Unpredictable backedge-taken count. -; CHECK: Loop %loop: max backedge-taken count is 2147483646 +; CHECK: Loop %loop: constant max backedge-taken count is 2147483646 entry: br label %loop @@ -319,7 +319,7 @@ define void @changing_end_bound2(i32 %start, i32* %n_addr, i32* %addr) { ; CHECK-LABEL: Determining loop execution counts for: @changing_end_bound2 ; CHECK: Loop %loop: Unpredictable backedge-taken count. -; CHECK: Loop %loop: max backedge-taken count is -1 +; CHECK: Loop %loop: constant max backedge-taken count is -1 entry: br label %loop @@ -342,7 +342,7 @@ define void @changing_end_bound3(i32 %start, i32* %n_addr, i32* %addr) { ; CHECK-LABEL: Determining loop execution counts for: @changing_end_bound3 ; CHECK: Loop %loop: Unpredictable backedge-taken count. -; CHECK: Loop %loop: max backedge-taken count is 1073741823 +; CHECK: Loop %loop: constant max backedge-taken count is 1073741823 entry: br label %loop @@ -366,7 +366,7 @@ define void @changing_end_bound4(i32 %start, i32* %n_addr, i32* %addr) { ; CHECK-LABEL: Determining loop execution counts for: @changing_end_bound4 ; CHECK: Loop %loop: Unpredictable backedge-taken count. -; CHECK: Loop %loop: Unpredictable max backedge-taken count. +; CHECK: Loop %loop: Unpredictable constant max backedge-taken count. entry: br label %loop @@ -390,7 +390,7 @@ define void @changing_end_bound5(i32 %stride, i32 %start, i32* %n_addr, i32* %addr) { ; CHECK-LABEL: Determining loop execution counts for: @changing_end_bound5 ; CHECK: Loop %loop: Unpredictable backedge-taken count. -; CHECK: Loop %loop: Unpredictable max backedge-taken count. +; CHECK: Loop %loop: Unpredictable constant max backedge-taken count. entry: br label %loop @@ -413,7 +413,7 @@ define void @changing_end_bound6(i32 %start, i32* %n_addr, i32* %addr) { ; CHECK-LABEL: Determining loop execution counts for: @changing_end_bound6 ; CHECK: Loop %loop: Unpredictable backedge-taken count. -; CHECK: Loop %loop: Unpredictable max backedge-taken count. +; CHECK: Loop %loop: Unpredictable constant max backedge-taken count. entry: br label %loop @@ -436,7 +436,7 @@ define void @changing_end_bound7(i32 %start, i32* %n_addr, i32* %addr) { ; CHECK-LABEL: Determining loop execution counts for: @changing_end_bound7 ; CHECK: Loop %loop: Unpredictable backedge-taken count. -; CHECK: Loop %loop: Unpredictable max backedge-taken count. +; CHECK: Loop %loop: Unpredictable constant max backedge-taken count. entry: br label %loop @@ -458,7 +458,7 @@ define void @max_overflow_se(i8 %n) mustprogress { ; CHECK-LABEL: Determining loop execution counts for: @max_overflow_se ; CHECK: Loop %loop: backedge-taken count is 0 -; CHECK: Loop %loop: max backedge-taken count is 0 +; CHECK: Loop %loop: constant max backedge-taken count is 0 entry: br label %loop @@ -479,7 +479,7 @@ ; CHECK: Loop %loop: Unpredictable backedge-taken count. ; CHECK: exit count for loop: 1 ; CHECK: exit count for latch: ***COULDNOTCOMPUTE*** -; CHECK: Loop %loop: max backedge-taken count is 1 +; CHECK: Loop %loop: constant max backedge-taken count is 1 entry: br label %loop @@ -503,7 +503,7 @@ define void @bool_stride(i1 %s, i1 %n) mustprogress { ; CHECK-LABEL: Determining loop execution counts for: @bool_stride ; CHECK: Loop %loop: backedge-taken count is false -; CHECK: Loop %loop: max backedge-taken count is false +; CHECK: Loop %loop: constant max backedge-taken count is false entry: br label %loop @@ -523,7 +523,7 @@ define void @ne_zero_max_btc(i32 %a) { ; CHECK-LABEL: Determining loop execution counts for: @ne_zero_max_btc ; CHECK: Loop %for.body: backedge-taken count is 0 -; CHECK: Loop %for.body: max backedge-taken count is 0 +; CHECK: Loop %for.body: constant max backedge-taken count is 0 entry: %cmp = icmp slt i32 %a, 1 %spec.select = select i1 %cmp, i32 %a, i32 1 diff --git a/llvm/test/Analysis/ScalarEvolution/min-max-exprs.ll b/llvm/test/Analysis/ScalarEvolution/min-max-exprs.ll --- a/llvm/test/Analysis/ScalarEvolution/min-max-exprs.ll +++ b/llvm/test/Analysis/ScalarEvolution/min-max-exprs.ll @@ -47,7 +47,8 @@ ; CHECK-NEXT: --> {1,+,1}<%bb1> U: [1,-2147483647) S: [1,-2147483647) Exits: (1 + (0 smax %N)) LoopDispositions: { %bb1: Computable } ; CHECK-NEXT: Determining loop execution counts for: @f ; CHECK-NEXT: Loop %bb1: backedge-taken count is (0 smax %N) -; CHECK-NEXT: Loop %bb1: max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %bb1: constant max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %bb1: symbolic max backedge-taken count is (0 smax %N) ; CHECK-NEXT: Loop %bb1: Predicated backedge-taken count is (0 smax %N) ; CHECK-NEXT: Predicates: ; CHECK: Loop %bb1: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/ne-overflow.ll b/llvm/test/Analysis/ScalarEvolution/ne-overflow.ll --- a/llvm/test/Analysis/ScalarEvolution/ne-overflow.ll +++ b/llvm/test/Analysis/ScalarEvolution/ne-overflow.ll @@ -11,7 +11,8 @@ ; CHECK-LABEL: 'test' ; CHECK-NEXT: Determining loop execution counts for: @test ; CHECK-NEXT: Loop %for.body: backedge-taken count is ((-2 + %N) /u 2) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is ((-2 + %N) /u 2) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is ((-2 + %N) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -33,7 +34,8 @@ ; CHECK-LABEL: 'test_preinc' ; CHECK-NEXT: Determining loop execution counts for: @test_preinc ; CHECK-NEXT: Loop %for.body: backedge-taken count is (%N /u 2) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (%N /u 2) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (%N /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -58,7 +60,8 @@ ; CHECK-LABEL: 'test_well_defined_infinite_st' ; CHECK-NEXT: Determining loop execution counts for: @test_well_defined_infinite_st ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -79,7 +82,8 @@ ; CHECK-LABEL: 'test_well_defined_infinite_ld' ; CHECK-NEXT: Determining loop execution counts for: @test_well_defined_infinite_ld ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -100,7 +104,8 @@ ; CHECK-LABEL: 'test_no_mustprogress' ; CHECK-NEXT: Determining loop execution counts for: @test_no_mustprogress ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -122,7 +127,8 @@ ; CHECK-LABEL: 'test_1024' ; CHECK-NEXT: Determining loop execution counts for: @test_1024 ; CHECK-NEXT: Loop %for.body: backedge-taken count is ((-1024 + %N) /u 1024) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 4194303 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 4194303 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is ((-1024 + %N) /u 1024) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is ((-1024 + %N) /u 1024) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -144,7 +150,8 @@ ; CHECK-LABEL: 'test_uneven_divide' ; CHECK-NEXT: Determining loop execution counts for: @test_uneven_divide ; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + (-1431655765 * %N)) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + (-1431655765 * %N)) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + (-1431655765 * %N)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -166,7 +173,8 @@ ; CHECK-LABEL: 'test_non_invariant_rhs' ; CHECK-NEXT: Determining loop execution counts for: @test_non_invariant_rhs ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -189,7 +197,8 @@ ; CHECK-LABEL: 'test_abnormal_exit' ; CHECK-NEXT: Determining loop execution counts for: @test_abnormal_exit ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -213,7 +222,10 @@ ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for for.body: 9 ; CHECK-NEXT: exit count for for.latch: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 9 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 9 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 9 +; CHECK-NEXT: symbolic max exit count for for.body: 9 +; CHECK-NEXT: symbolic max exit count for for.latch: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -237,7 +249,8 @@ ; CHECK-LABEL: 'test_zext' ; CHECK-NEXT: Determining loop execution counts for: @test_zext ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (%N /u 2) ; CHECK-NEXT: Predicates: ; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: @@ -260,7 +273,8 @@ ; CHECK-LABEL: 'test_sext' ; CHECK-NEXT: Determining loop execution counts for: @test_sext ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -281,7 +295,8 @@ ; CHECK-LABEL: 'test_zext_of_sext' ; CHECK-NEXT: Determining loop execution counts for: @test_zext_of_sext ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -303,7 +318,8 @@ ; CHECK-LABEL: 'test_zext_offset' ; CHECK-NEXT: Determining loop execution counts for: @test_zext_offset ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -325,7 +341,8 @@ ; CHECK-LABEL: 'test_sext_offset' ; CHECK-NEXT: Determining loop execution counts for: @test_sext_offset ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/no-wrap-add-exprs.ll b/llvm/test/Analysis/ScalarEvolution/no-wrap-add-exprs.ll --- a/llvm/test/Analysis/ScalarEvolution/no-wrap-add-exprs.ll +++ b/llvm/test/Analysis/ScalarEvolution/no-wrap-add-exprs.ll @@ -304,7 +304,8 @@ ; CHECK-NEXT: --> (%a + %b) U: full-set S: full-set ; CHECK-NEXT: Determining loop execution counts for: @test2_a ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -340,7 +341,8 @@ ; CHECK-NEXT: --> (%a /u {(%a + %b),+,%b}<%loop>) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test2_b ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/no-wrap-symbolic-becount.ll b/llvm/test/Analysis/ScalarEvolution/no-wrap-symbolic-becount.ll --- a/llvm/test/Analysis/ScalarEvolution/no-wrap-symbolic-becount.ll +++ b/llvm/test/Analysis/ScalarEvolution/no-wrap-symbolic-becount.ll @@ -26,7 +26,10 @@ ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop: (zext i32 %start to i64) ; CHECK-NEXT: exit count for backedge: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (zext i32 %start to i64) +; CHECK-NEXT: symbolic max exit count for loop: (zext i32 %start to i64) +; CHECK-NEXT: symbolic max exit count for backedge: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -71,7 +74,8 @@ ; CHECK-NEXT: --> {(-1 + (2147483648 * (zext i32 %start to i64))),+,-1}<%loop> U: full-set S: full-set Exits: -9223372036854775807 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test_02 ; CHECK-NEXT: Loop %loop: backedge-taken count is (9223372036854775806 + (2147483648 * (zext i32 %start to i64))) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -2147483650 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -2147483650 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (9223372036854775806 + (2147483648 * (zext i32 %start to i64))) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (9223372036854775806 + (2147483648 * (zext i32 %start to i64))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -102,7 +106,8 @@ ; CHECK-NEXT: --> {(2001 + %startptr),+,1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @pointer_iv_nowrap ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -130,7 +135,8 @@ ; CHECK-NEXT: --> {(8004 + %startptr),+,4}<%loop> U: full-set S: full-set Exits: (8004 + (4 * ((-8001 + (-1 * (ptrtoint i32* %startptr to i64)) + ((8004 + (ptrtoint i32* %startptr to i64)) umax (ptrtoint i32* %endptr to i64))) /u 4)) + %startptr) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @pointer_iv_nowrap_guard ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-8001 + (-1 * (ptrtoint i32* %startptr to i64)) + ((8004 + (ptrtoint i32* %startptr to i64)) umax (ptrtoint i32* %endptr to i64))) /u 4) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4611686018427387903 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4611686018427387903 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-8001 + (-1 * (ptrtoint i32* %startptr to i64)) + ((8004 + (ptrtoint i32* %startptr to i64)) umax (ptrtoint i32* %endptr to i64))) /u 4) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-8001 + (-1 * (ptrtoint i32* %startptr to i64)) + ((8004 + (ptrtoint i32* %startptr to i64)) umax (ptrtoint i32* %endptr to i64))) /u 4) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/nsw-offset-assume.ll b/llvm/test/Analysis/ScalarEvolution/nsw-offset-assume.ll --- a/llvm/test/Analysis/ScalarEvolution/nsw-offset-assume.ll +++ b/llvm/test/Analysis/ScalarEvolution/nsw-offset-assume.ll @@ -45,7 +45,8 @@ ; CHECK-NEXT: --> {2,+,2}<%bb> U: [2,2147483647) S: [2,2147483647) Exits: (2 + (2 * ((-1 + (2 * (%no /u 2))) /u 2))) LoopDispositions: { %bb: Computable } ; CHECK-NEXT: Determining loop execution counts for: @foo ; CHECK-NEXT: Loop %bb: backedge-taken count is ((-1 + (2 * (%no /u 2))) /u 2) -; CHECK-NEXT: Loop %bb: max backedge-taken count is 1073741822 +; CHECK-NEXT: Loop %bb: constant max backedge-taken count is 1073741822 +; CHECK-NEXT: Loop %bb: symbolic max backedge-taken count is ((-1 + (2 * (%no /u 2))) /u 2) ; CHECK-NEXT: Loop %bb: Predicated backedge-taken count is ((-1 + (2 * (%no /u 2))) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %bb: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/nsw-offset.ll b/llvm/test/Analysis/ScalarEvolution/nsw-offset.ll --- a/llvm/test/Analysis/ScalarEvolution/nsw-offset.ll +++ b/llvm/test/Analysis/ScalarEvolution/nsw-offset.ll @@ -42,7 +42,8 @@ ; CHECK-NEXT: --> {2,+,2}<%bb> U: [2,2147483647) S: [2,2147483647) Exits: (2 + (2 * ((-1 + (2 * (%no /u 2))) /u 2))) LoopDispositions: { %bb: Computable } ; CHECK-NEXT: Determining loop execution counts for: @foo ; CHECK-NEXT: Loop %bb: backedge-taken count is ((-1 + (2 * (%no /u 2))) /u 2) -; CHECK-NEXT: Loop %bb: max backedge-taken count is 1073741822 +; CHECK-NEXT: Loop %bb: constant max backedge-taken count is 1073741822 +; CHECK-NEXT: Loop %bb: symbolic max backedge-taken count is ((-1 + (2 * (%no /u 2))) /u 2) ; CHECK-NEXT: Loop %bb: Predicated backedge-taken count is ((-1 + (2 * (%no /u 2))) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %bb: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/nsw.ll b/llvm/test/Analysis/ScalarEvolution/nsw.ll --- a/llvm/test/Analysis/ScalarEvolution/nsw.ll +++ b/llvm/test/Analysis/ScalarEvolution/nsw.ll @@ -28,7 +28,8 @@ ; CHECK-NEXT: --> {(8 + %p),+,8}<%bb> U: full-set S: full-set Exits: <> LoopDispositions: { %bb: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test1 ; CHECK-NEXT: Loop %bb: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %bb: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %bb: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %bb: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %bb: Unpredictable predicated backedge-taken count. ; entry: @@ -76,7 +77,8 @@ ; CHECK-NEXT: --> {(4 + %begin),+,4}<%for.body.i.i> U: full-set S: full-set Exits: (4 + (4 * ((-4 + (-1 * (ptrtoint i32* %begin to i64)) + (ptrtoint i32* %end to i64)) /u 4)) + %begin) LoopDispositions: { %for.body.i.i: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test2 ; CHECK-NEXT: Loop %for.body.i.i: backedge-taken count is ((-4 + (-1 * (ptrtoint i32* %begin to i64)) + (ptrtoint i32* %end to i64)) /u 4) -; CHECK-NEXT: Loop %for.body.i.i: max backedge-taken count is 4611686018427387903 +; CHECK-NEXT: Loop %for.body.i.i: constant max backedge-taken count is 4611686018427387903 +; CHECK-NEXT: Loop %for.body.i.i: symbolic max backedge-taken count is ((-4 + (-1 * (ptrtoint i32* %begin to i64)) + (ptrtoint i32* %end to i64)) /u 4) ; CHECK-NEXT: Loop %for.body.i.i: Predicated backedge-taken count is ((-4 + (-1 * (ptrtoint i32* %begin to i64)) + (ptrtoint i32* %end to i64)) /u 4) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body.i.i: Trip multiple is 1 @@ -116,7 +118,8 @@ ; CHECK-NEXT: --> {%begin,+,4}<%for.body.i.i> U: full-set S: full-set Exits: ((4 * ((-4 + (-1 * (ptrtoint i32* %begin to i64)) + (ptrtoint i32* %end to i64)) /u 4)) + %begin) LoopDispositions: { %for.body.i.i: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test3 ; CHECK-NEXT: Loop %for.body.i.i: backedge-taken count is ((-4 + (-1 * (ptrtoint i32* %begin to i64)) + (ptrtoint i32* %end to i64)) /u 4) -; CHECK-NEXT: Loop %for.body.i.i: max backedge-taken count is 4611686018427387903 +; CHECK-NEXT: Loop %for.body.i.i: constant max backedge-taken count is 4611686018427387903 +; CHECK-NEXT: Loop %for.body.i.i: symbolic max backedge-taken count is ((-4 + (-1 * (ptrtoint i32* %begin to i64)) + (ptrtoint i32* %end to i64)) /u 4) ; CHECK-NEXT: Loop %for.body.i.i: Predicated backedge-taken count is ((-4 + (-1 * (ptrtoint i32* %begin to i64)) + (ptrtoint i32* %end to i64)) /u 4) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body.i.i: Trip multiple is 1 @@ -178,7 +181,8 @@ ; CHECK-NEXT: --> {(4 + %arg),+,4}<%bb1> U: [4,0) S: [4,0) Exits: (8 + %arg) LoopDispositions: { %bb1: Computable } ; CHECK-NEXT: Determining loop execution counts for: @PR12375 ; CHECK-NEXT: Loop %bb1: backedge-taken count is 1 -; CHECK-NEXT: Loop %bb1: max backedge-taken count is 1 +; CHECK-NEXT: Loop %bb1: constant max backedge-taken count is 1 +; CHECK-NEXT: Loop %bb1: symbolic max backedge-taken count is 1 ; CHECK-NEXT: Loop %bb1: Predicated backedge-taken count is 1 ; CHECK-NEXT: Predicates: ; CHECK: Loop %bb1: Trip multiple is 2 @@ -208,7 +212,8 @@ ; CHECK-NEXT: --> {(4 + %arg),+,4}<%bb2> U: [4,0) S: [4,0) Exits: (4 + (4 * ((-1 + (-1 * (ptrtoint i32* %arg to i64)) + ((4 + (ptrtoint i32* %arg to i64)) umax (ptrtoint i32* %arg1 to i64))) /u 4)) + %arg) LoopDispositions: { %bb2: Computable } ; CHECK-NEXT: Determining loop execution counts for: @PR12376 ; CHECK-NEXT: Loop %bb2: backedge-taken count is ((-1 + (-1 * (ptrtoint i32* %arg to i64)) + ((4 + (ptrtoint i32* %arg to i64)) umax (ptrtoint i32* %arg1 to i64))) /u 4) -; CHECK-NEXT: Loop %bb2: max backedge-taken count is 4611686018427387902 +; CHECK-NEXT: Loop %bb2: constant max backedge-taken count is 4611686018427387902 +; CHECK-NEXT: Loop %bb2: symbolic max backedge-taken count is ((-1 + (-1 * (ptrtoint i32* %arg to i64)) + ((4 + (ptrtoint i32* %arg to i64)) umax (ptrtoint i32* %arg1 to i64))) /u 4) ; CHECK-NEXT: Loop %bb2: Predicated backedge-taken count is ((-1 + (-1 * (ptrtoint i32* %arg to i64)) + ((4 + (ptrtoint i32* %arg to i64)) umax (ptrtoint i32* %arg1 to i64))) /u 4) ; CHECK-NEXT: Predicates: ; CHECK: Loop %bb2: Trip multiple is 1 @@ -243,7 +248,8 @@ ; CHECK-NEXT: --> %buf.val U: full-set S: full-set Exits: <> LoopDispositions: { %for.body: Variant } ; CHECK-NEXT: Determining loop execution counts for: @nswnowrap ; CHECK-NEXT: Loop %for.body: backedge-taken count is ((-1 * %v) + ((1 + %v) smax %v)) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 1, actual taken count either this or zero. +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 1, actual taken count either this or zero. +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is ((-1 * %v) + ((1 + %v) smax %v)), actual taken count either this or zero. ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is ((-1 * %v) + ((1 + %v) smax %v)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -285,7 +291,8 @@ ; CHECK-NEXT: --> {(1 + %arg),+,1}<%for.body> U: full-set S: full-set Exits: (10 smax (1 + %arg)) LoopDispositions: { %for.body: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test4 ; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + (-1 * %arg) + (10 smax (1 + %arg))) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -2147483638 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -2147483638 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + (-1 * %arg) + (10 smax (1 + %arg))) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + (-1 * %arg) + (10 smax (1 + %arg))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -318,7 +325,8 @@ ; CHECK-NEXT: --> {7,+,7}<%loop> U: [7,0) S: [7,0) Exits: (7 + (7 * ((((-1 * (1 umin %n)) + %n) /u 7) + (1 umin %n)))) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @bad_postinc_nsw_a ; CHECK-NEXT: Loop %loop: backedge-taken count is ((((-1 * (1 umin %n)) + %n) /u 7) + (1 umin %n)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 613566756 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 613566756 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((((-1 * (1 umin %n)) + %n) /u 7) + (1 umin %n)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((((-1 * (1 umin %n)) + %n) /u 7) + (1 umin %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -349,7 +357,8 @@ ; CHECK-NEXT: --> 0 U: [0,1) S: [0,1) Exits: 0 LoopDispositions: { %loop: Invariant } ; CHECK-NEXT: Determining loop execution counts for: @postinc_poison_prop_through_and ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -377,7 +386,8 @@ ; CHECK-NEXT: --> {7,+,7}<%loop> U: [7,-3) S: [7,-3) Exits: (7 + (7 * ((-1 + (7 umax %n)) /u 7))) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @pr28012 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-1 + (7 umax %n)) /u 7) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 613566755 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 613566755 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-1 + (7 umax %n)) /u 7) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-1 + (7 umax %n)) /u 7) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -409,7 +419,8 @@ ; CHECK-NEXT: --> %cond U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @select_cond_poison_propagation ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/outer_phi.ll b/llvm/test/Analysis/ScalarEvolution/outer_phi.ll --- a/llvm/test/Analysis/ScalarEvolution/outer_phi.ll +++ b/llvm/test/Analysis/ScalarEvolution/outer_phi.ll @@ -20,12 +20,18 @@ ; CHECK-NEXT: Loop %inner: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for inner: %b ; CHECK-NEXT: exit count for inner.backedge: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %inner: max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %inner: constant max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %inner: symbolic max backedge-taken count is %b +; CHECK-NEXT: symbolic max exit count for inner: %b +; CHECK-NEXT: symbolic max exit count for inner.backedge: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %inner: Unpredictable predicated backedge-taken count. ; CHECK-NEXT: Loop %outer: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for inner: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for outer.backedge: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %outer: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %outer: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %outer: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: symbolic max exit count for inner: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for outer.backedge: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %outer: Unpredictable predicated backedge-taken count. ; entry: @@ -78,12 +84,18 @@ ; CHECK-NEXT: Loop %inner: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for inner: ((-1 * %outer.iv) + (%b smax %outer.iv)) ; CHECK-NEXT: exit count for inner.backedge: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %inner: max backedge-taken count is -1 +; CHECK-NEXT: Loop %inner: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %inner: symbolic max backedge-taken count is ((-1 * %outer.iv) + (%b smax %outer.iv)) +; CHECK-NEXT: symbolic max exit count for inner: ((-1 * %outer.iv) + (%b smax %outer.iv)) +; CHECK-NEXT: symbolic max exit count for inner.backedge: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %inner: Unpredictable predicated backedge-taken count. ; CHECK-NEXT: Loop %outer: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for inner: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for outer.backedge: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %outer: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %outer: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %outer: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: symbolic max exit count for inner: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for outer.backedge: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %outer: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/overflow-intrinsics-trip-count.ll b/llvm/test/Analysis/ScalarEvolution/overflow-intrinsics-trip-count.ll --- a/llvm/test/Analysis/ScalarEvolution/overflow-intrinsics-trip-count.ll +++ b/llvm/test/Analysis/ScalarEvolution/overflow-intrinsics-trip-count.ll @@ -12,7 +12,8 @@ ; CHECK-LABEL: 'uadd_exhaustive' ; CHECK-NEXT: Determining loop execution counts for: @uadd_exhaustive ; CHECK-NEXT: Loop %for.body: backedge-taken count is 35 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 35 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 35 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 35 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 35 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 36 @@ -38,7 +39,8 @@ ; CHECK-LABEL: 'sadd_exhaustive' ; CHECK-NEXT: Determining loop execution counts for: @sadd_exhaustive ; CHECK-NEXT: Loop %for.body: backedge-taken count is 67 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 67 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 67 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 67 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 67 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 68 @@ -64,7 +66,8 @@ ; CHECK-LABEL: 'usub_exhaustive' ; CHECK-NEXT: Determining loop execution counts for: @usub_exhaustive ; CHECK-NEXT: Loop %for.body: backedge-taken count is 50 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 50 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 50 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 50 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 50 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 51 @@ -90,7 +93,8 @@ ; CHECK-LABEL: 'ssub_exhaustive' ; CHECK-NEXT: Determining loop execution counts for: @ssub_exhaustive ; CHECK-NEXT: Loop %for.body: backedge-taken count is 68 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 68 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 68 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 68 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 68 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 69 @@ -116,7 +120,8 @@ ; CHECK-LABEL: 'smul_exhaustive' ; CHECK-NEXT: Determining loop execution counts for: @smul_exhaustive ; CHECK-NEXT: Loop %for.body: backedge-taken count is 14 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 14 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 14 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 14 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 14 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 15 @@ -142,7 +147,8 @@ ; CHECK-LABEL: 'umul_exhaustive' ; CHECK-NEXT: Determining loop execution counts for: @umul_exhaustive ; CHECK-NEXT: Loop %for.body: backedge-taken count is 15 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 15 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 15 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 15 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 15 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 16 @@ -168,7 +174,8 @@ ; CHECK-LABEL: 'uadd_symbolic_start' ; CHECK-NEXT: Determining loop execution counts for: @uadd_symbolic_start ; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + (-1 * %start)) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + (-1 * %start)) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + (-1 * %start)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -194,7 +201,8 @@ ; CHECK-LABEL: 'sadd_symbolic_start' ; CHECK-NEXT: Determining loop execution counts for: @sadd_symbolic_start ; CHECK-NEXT: Loop %for.body: backedge-taken count is (32767 + (-1 * %start)) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (32767 + (-1 * %start)) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (32767 + (-1 * %start)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -220,7 +228,8 @@ ; CHECK-LABEL: 'sadd_symbolic_start2' ; CHECK-NEXT: Determining loop execution counts for: @sadd_symbolic_start2 ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -245,7 +254,8 @@ ; CHECK-LABEL: 'sadd_symbolic_swapped' ; CHECK-NEXT: Determining loop execution counts for: @sadd_symbolic_swapped ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -269,7 +279,8 @@ ; CHECK-LABEL: 'usub_symbolic_start' ; CHECK-NEXT: Determining loop execution counts for: @usub_symbolic_start ; CHECK-NEXT: Loop %for.body: backedge-taken count is %start -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is %start ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is %start ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -295,7 +306,8 @@ ; CHECK-LABEL: 'ssub_symbolic_start' ; CHECK-NEXT: Determining loop execution counts for: @ssub_symbolic_start ; CHECK-NEXT: Loop %for.body: backedge-taken count is (-32768 + %start) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-32768 + %start) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-32768 + %start) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -321,7 +333,8 @@ ; CHECK-LABEL: 'smul_symbolic_start' ; CHECK-NEXT: Determining loop execution counts for: @smul_symbolic_start ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -345,7 +358,8 @@ ; CHECK-LABEL: 'umul_symbolic_start' ; CHECK-NEXT: Determining loop execution counts for: @umul_symbolic_start ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -371,7 +385,10 @@ ; CHECK-NEXT: Loop %for.body: backedge-taken count is ((230 + (-1 * %start)) umin (32767 + (-1 * %start))) ; CHECK-NEXT: exit count for for.body: (32767 + (-1 * %start)) ; CHECK-NEXT: exit count for for.latch: (230 + (-1 * %start)) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is ((230 + (-1 * %start)) umin (32767 + (-1 * %start))) +; CHECK-NEXT: symbolic max exit count for for.body: (32767 + (-1 * %start)) +; CHECK-NEXT: symbolic max exit count for for.latch: (230 + (-1 * %start)) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is ((230 + (-1 * %start)) umin (32767 + (-1 * %start))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/overflow-intrinsics.ll b/llvm/test/Analysis/ScalarEvolution/overflow-intrinsics.ll --- a/llvm/test/Analysis/ScalarEvolution/overflow-intrinsics.ll +++ b/llvm/test/Analysis/ScalarEvolution/overflow-intrinsics.ll @@ -31,7 +31,7 @@ %tmp2 = extractvalue { i32, i1 } %tmp0, 0 %cmp = icmp slt i32 %tmp2, 16 br i1 %cmp, label %for.body, label %for.cond.cleanup -; CHECK: Loop %for.body: max backedge-taken count is 15 +; CHECK: Loop %for.body: constant max backedge-taken count is 15 } define void @f_sadd_1(i8* %a) { @@ -66,7 +66,7 @@ %tmp2 = extractvalue { i32, i1 } %tmp0, 0 %cmp = icmp slt i32 %tmp2, 16 br i1 %cmp, label %for.body, label %for.cond.cleanup -; CHECK: Loop %for.body: max backedge-taken count is 15 +; CHECK: Loop %for.body: constant max backedge-taken count is 15 } define void @f_sadd_2(i8* %a, i1* %c) { @@ -216,7 +216,7 @@ %tmp2 = extractvalue { i32, i1 } %tmp0, 0 %cmp = icmp slt i32 %tmp2, 16 br i1 %cmp, label %for.body, label %for.cond.cleanup -; CHECK: Loop %for.body: max backedge-taken count is 15 +; CHECK: Loop %for.body: constant max backedge-taken count is 15 } define void @f_ssub(i8* nocapture %a) { @@ -247,7 +247,7 @@ %tmp2 = extractvalue { i32, i1 } %tmp0, 0 %cmp = icmp sgt i32 %tmp2, -1 br i1 %cmp, label %for.body, label %for.cond.cleanup -; CHECK: Loop %for.body: max backedge-taken count is 15 +; CHECK: Loop %for.body: constant max backedge-taken count is 15 } define void @f_usub(i8* nocapture %a) { @@ -278,7 +278,7 @@ %tmp2 = extractvalue { i32, i1 } %tmp0, 0 %cmp = icmp sgt i32 %tmp2, -1 br i1 %cmp, label %for.body, label %for.cond.cleanup -; CHECK: Loop %for.body: max backedge-taken count is 15 +; CHECK: Loop %for.body: constant max backedge-taken count is 15 } define i32 @f_smul(i32 %val_a, i32 %val_b) { diff --git a/llvm/test/Analysis/ScalarEvolution/pr25369.ll b/llvm/test/Analysis/ScalarEvolution/pr25369.ll --- a/llvm/test/Analysis/ScalarEvolution/pr25369.ll +++ b/llvm/test/Analysis/ScalarEvolution/pr25369.ll @@ -27,7 +27,7 @@ br i1 %tmp12, label %bb3, label %bb4 ; CHECK: Loop %bb4: backedge-taken count is 20 -; CHECK: Loop %bb4: max backedge-taken count is 20 +; CHECK: Loop %bb4: constant max backedge-taken count is 20 bb13: ; preds = %bb13, %bb3 %tmp14 = phi i64 [ 0, %bb3 ], [ %tmp15, %bb13 ] @@ -64,7 +64,7 @@ br i1 %tmp12, label %bb3, label %bb4 ; CHECK: Loop %bb4: Unpredictable backedge-taken count. -; CHECK: Loop %bb4: Unpredictable max backedge-taken count. +; CHECK: Loop %bb4: Unpredictable constant max backedge-taken count. bb13: ; preds = %bb13, %bb3 %tmp14 = phi i64 [ 0, %bb3 ], [ %tmp15, %bb13 ] diff --git a/llvm/test/Analysis/ScalarEvolution/pr34538.ll b/llvm/test/Analysis/ScalarEvolution/pr34538.ll --- a/llvm/test/Analysis/ScalarEvolution/pr34538.ll +++ b/llvm/test/Analysis/ScalarEvolution/pr34538.ll @@ -3,7 +3,7 @@ define i32 @pr34538() local_unnamed_addr #0 { ; CHECK-ANALYSIS-1: Loop %do.body: backedge-taken count is 10000 -; CHECK-ANALYSIS-1: Loop %do.body: max backedge-taken count is 10000 +; CHECK-ANALYSIS-1: Loop %do.body: constant max backedge-taken count is 10000 ; CHECK-ANALYSIS-1: Loop %do.body: Predicated backedge-taken count is 10000 entry: br label %do.body @@ -34,6 +34,6 @@ do.end: ; preds = %do.body ret i32 0 ; CHECK-ANALYSIS-2: Loop %do.body: backedge-taken count is 5000 -; CHECK-ANALYSIS-2: Loop %do.body: max backedge-taken count is 5000 +; CHECK-ANALYSIS-2: Loop %do.body: constant max backedge-taken count is 5000 ; CHECK-ANALYSIS-2: Loop %do.body: Predicated backedge-taken count is 5000 } diff --git a/llvm/test/Analysis/ScalarEvolution/pr48225.ll b/llvm/test/Analysis/ScalarEvolution/pr48225.ll --- a/llvm/test/Analysis/ScalarEvolution/pr48225.ll +++ b/llvm/test/Analysis/ScalarEvolution/pr48225.ll @@ -7,7 +7,7 @@ ; - %cond.false.on.first.iter is false on 1st iteration; ; - %cond.false.on.second.iter is false on 2nd iteration; ; - Therefore, their AND is false on first two iterations, and the backedge is taken twice. -; 'max backedge-taken count is 1' is a bug caused by wrong treatment of AND +; 'constant max backedge-taken count is 1' is a bug caused by wrong treatment of AND ; condition in the computation logic. It should be 2. define void @test_and(i1 %boolcond) { ; CHECK-LABEL: 'test_and' @@ -24,7 +24,10 @@ ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop: 2 ; CHECK-NEXT: exit count for backedge: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 2 +; CHECK-NEXT: symbolic max exit count for loop: 2 +; CHECK-NEXT: symbolic max exit count for backedge: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -54,7 +57,7 @@ ; - %cond.true.on.first.iter is true on 1st iteration; ; - %cond.true.on.second.iter is true on 2nd iteration; ; - Therefore, their OR is true on first two iterations, and the backedge is taken twice. -; 'max backedge-taken count is 1' is a bug caused by wrong treatment of OR +; 'constant max backedge-taken count is 1' is a bug caused by wrong treatment of OR ; condition in the computation logic. It should be 2. define void @test_or(i1 %boolcond) { ; CHECK-LABEL: 'test_or' @@ -71,7 +74,10 @@ ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop: 2 ; CHECK-NEXT: exit count for backedge: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 2 +; CHECK-NEXT: symbolic max exit count for loop: 2 +; CHECK-NEXT: symbolic max exit count for backedge: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/predicated-trip-count.ll b/llvm/test/Analysis/ScalarEvolution/predicated-trip-count.ll --- a/llvm/test/Analysis/ScalarEvolution/predicated-trip-count.ll +++ b/llvm/test/Analysis/ScalarEvolution/predicated-trip-count.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; RUN: opt < %s -disable-output "-passes=print" 2>&1 | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" @@ -17,35 +18,45 @@ ; throughout the execution of the loop. The resulting predicated ; backedge taken count is correct. -; CHECK: Classifying expressions for: @test1 -; CHECK: %i.0.ext = sext i16 %i.0 to i32 -; CHECK-NEXT: --> (sext i16 {0,+,1}<%bb3> to i32) -; CHECK: Loop %bb3: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %bb3: Unpredictable max backedge-taken count. -; CHECK-NEXT: Loop %bb3: Predicated backedge-taken count is (1 + (-1 smax %M)) -; CHECK-NEXT: Predicates: -; CHECK-NEXT: {0,+,1}<%bb3> Added Flags: define void @test1(i32 %N, i32 %M) { +; CHECK-LABEL: 'test1' +; CHECK-NEXT: Classifying expressions for: @test1 +; CHECK-NEXT: %tmp = getelementptr [1000 x i32], [1000 x i32]* @A, i32 0, i16 %i.0 +; CHECK-NEXT: --> ((4 * (sext i16 {0,+,1}<%bb3> to i64)) + @A) U: [0,-3) S: [-9223372036854775808,9223372036854775805) Exits: <> LoopDispositions: { %bb3: Computable } +; CHECK-NEXT: %tmp2 = add i16 %i.0, 1 +; CHECK-NEXT: --> {1,+,1}<%bb3> U: full-set S: full-set Exits: <> LoopDispositions: { %bb3: Computable } +; CHECK-NEXT: %i.0 = phi i16 [ 0, %entry ], [ %tmp2, %bb ] +; CHECK-NEXT: --> {0,+,1}<%bb3> U: full-set S: full-set Exits: <> LoopDispositions: { %bb3: Computable } +; CHECK-NEXT: %i.0.ext = sext i16 %i.0 to i32 +; CHECK-NEXT: --> (sext i16 {0,+,1}<%bb3> to i32) U: [-32768,32768) S: [-32768,32768) Exits: <> LoopDispositions: { %bb3: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test1 +; CHECK-NEXT: Loop %bb3: Unpredictable backedge-taken count. +; CHECK-NEXT: Loop %bb3: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %bb3: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: Loop %bb3: Predicated backedge-taken count is (1 + (-1 smax %M)) +; CHECK-NEXT: Predicates: +; CHECK-NEXT: {0,+,1}<%bb3> Added Flags: +; entry: - br label %bb3 + br label %bb3 bb: ; preds = %bb3 - %tmp = getelementptr [1000 x i32], [1000 x i32]* @A, i32 0, i16 %i.0 ; [#uses=1] - store i32 123, i32* %tmp - %tmp2 = add i16 %i.0, 1 ; [#uses=1] - br label %bb3 + %tmp = getelementptr [1000 x i32], [1000 x i32]* @A, i32 0, i16 %i.0 ; [#uses=1] + store i32 123, i32* %tmp + %tmp2 = add i16 %i.0, 1 ; [#uses=1] + br label %bb3 bb3: ; preds = %bb, %entry - %i.0 = phi i16 [ 0, %entry ], [ %tmp2, %bb ] ; [#uses=3] - %i.0.ext = sext i16 %i.0 to i32 - %tmp3 = icmp sle i32 %i.0.ext, %M ; [#uses=1] - br i1 %tmp3, label %bb, label %bb5 + %i.0 = phi i16 [ 0, %entry ], [ %tmp2, %bb ] ; [#uses=3] + %i.0.ext = sext i16 %i.0 to i32 + %tmp3 = icmp sle i32 %i.0.ext, %M ; [#uses=1] + br i1 %tmp3, label %bb, label %bb5 bb5: ; preds = %bb3 - br label %return + br label %return return: ; preds = %bb5 - ret void + ret void } ; The predicated backedge taken count is: @@ -74,36 +85,44 @@ ; we still have an infinite loop, since icmp sge %x, MIN_INT will always return ; true. -; CHECK: Classifying expressions for: @test2 - -; CHECK: %i.0.ext = sext i16 %i.0 to i32 -; CHECK-NEXT: --> (sext i16 {%Start,+,-1}<%bb3> to i32) -; CHECK: Loop %bb3: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %bb3: Unpredictable max backedge-taken count. +define void @test2(i32 %N, i32 %M, i16 %Start) { +; CHECK-LABEL: 'test2' +; CHECK-NEXT: Classifying expressions for: @test2 +; CHECK-NEXT: %tmp = getelementptr [1000 x i32], [1000 x i32]* @A, i32 0, i16 %i.0 +; CHECK-NEXT: --> ((4 * (sext i16 {%Start,+,-1}<%bb3> to i64)) + @A) U: [0,-3) S: [-9223372036854775808,9223372036854775805) Exits: <> LoopDispositions: { %bb3: Computable } +; CHECK-NEXT: %tmp2 = sub i16 %i.0, 1 +; CHECK-NEXT: --> {(-1 + %Start),+,-1}<%bb3> U: full-set S: full-set Exits: <> LoopDispositions: { %bb3: Computable } +; CHECK-NEXT: %i.0 = phi i16 [ %Start, %entry ], [ %tmp2, %bb ] +; CHECK-NEXT: --> {%Start,+,-1}<%bb3> U: full-set S: full-set Exits: <> LoopDispositions: { %bb3: Computable } +; CHECK-NEXT: %i.0.ext = sext i16 %i.0 to i32 +; CHECK-NEXT: --> (sext i16 {%Start,+,-1}<%bb3> to i32) U: [-32768,32768) S: [-32768,32768) Exits: <> LoopDispositions: { %bb3: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test2 +; CHECK-NEXT: Loop %bb3: Unpredictable backedge-taken count. +; CHECK-NEXT: Loop %bb3: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %bb3: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %bb3: Predicated backedge-taken count is (1 + (sext i16 %Start to i32) + (-1 * ((1 + (sext i16 %Start to i32)) smin %M))) -; CHECK-NEXT: Predicates: +; CHECK-NEXT: Predicates: ; CHECK-NEXT: {%Start,+,-1}<%bb3> Added Flags: - -define void @test2(i32 %N, i32 %M, i16 %Start) { +; entry: - br label %bb3 + br label %bb3 bb: ; preds = %bb3 - %tmp = getelementptr [1000 x i32], [1000 x i32]* @A, i32 0, i16 %i.0 ; [#uses=1] - store i32 123, i32* %tmp - %tmp2 = sub i16 %i.0, 1 ; [#uses=1] - br label %bb3 + %tmp = getelementptr [1000 x i32], [1000 x i32]* @A, i32 0, i16 %i.0 ; [#uses=1] + store i32 123, i32* %tmp + %tmp2 = sub i16 %i.0, 1 ; [#uses=1] + br label %bb3 bb3: ; preds = %bb, %entry - %i.0 = phi i16 [ %Start, %entry ], [ %tmp2, %bb ] ; [#uses=3] - %i.0.ext = sext i16 %i.0 to i32 - %tmp3 = icmp sge i32 %i.0.ext, %M ; [#uses=1] - br i1 %tmp3, label %bb, label %bb5 + %i.0 = phi i16 [ %Start, %entry ], [ %tmp2, %bb ] ; [#uses=3] + %i.0.ext = sext i16 %i.0 to i32 + %tmp3 = icmp sge i32 %i.0.ext, %M ; [#uses=1] + br i1 %tmp3, label %bb, label %bb5 bb5: ; preds = %bb3 - br label %return + br label %return return: ; preds = %bb5 - ret void + ret void } diff --git a/llvm/test/Analysis/ScalarEvolution/ptrtoint-constantexpr-loop.ll b/llvm/test/Analysis/ScalarEvolution/ptrtoint-constantexpr-loop.ll --- a/llvm/test/Analysis/ScalarEvolution/ptrtoint-constantexpr-loop.ll +++ b/llvm/test/Analysis/ScalarEvolution/ptrtoint-constantexpr-loop.ll @@ -23,7 +23,8 @@ ; PTR64_IDX64-NEXT: --> {2,+,2}<%bb11> U: [0,-1) S: [-2147483648,2147483647) Exits: <> LoopDispositions: { %bb11: Computable } ; PTR64_IDX64-NEXT: Determining loop execution counts for: @trunc_ptr_to_i64 ; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable backedge-taken count. -; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable max backedge-taken count. +; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable constant max backedge-taken count. +; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable symbolic max backedge-taken count. ; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable predicated backedge-taken count. ; ; PTR64_IDX32-LABEL: 'trunc_ptr_to_i64' @@ -40,7 +41,8 @@ ; PTR64_IDX32-NEXT: --> {2,+,2}<%bb11> U: [0,-1) S: [-2147483648,2147483647) Exits: <> LoopDispositions: { %bb11: Computable } ; PTR64_IDX32-NEXT: Determining loop execution counts for: @trunc_ptr_to_i64 ; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable backedge-taken count. -; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable max backedge-taken count. +; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable constant max backedge-taken count. +; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable symbolic max backedge-taken count. ; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable predicated backedge-taken count. ; ; PTR16_IDX16-LABEL: 'trunc_ptr_to_i64' @@ -57,7 +59,8 @@ ; PTR16_IDX16-NEXT: --> {2,+,2}<%bb11> U: [0,-1) S: [-2147483648,2147483647) Exits: <> LoopDispositions: { %bb11: Computable } ; PTR16_IDX16-NEXT: Determining loop execution counts for: @trunc_ptr_to_i64 ; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable backedge-taken count. -; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable max backedge-taken count. +; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable constant max backedge-taken count. +; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable symbolic max backedge-taken count. ; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable predicated backedge-taken count. ; ; PTR16_IDX32-LABEL: 'trunc_ptr_to_i64' @@ -74,7 +77,8 @@ ; PTR16_IDX32-NEXT: --> {2,+,2}<%bb11> U: [0,-1) S: [-2147483648,2147483647) Exits: <> LoopDispositions: { %bb11: Computable } ; PTR16_IDX32-NEXT: Determining loop execution counts for: @trunc_ptr_to_i64 ; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable backedge-taken count. -; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable max backedge-taken count. +; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable constant max backedge-taken count. +; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable symbolic max backedge-taken count. ; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable predicated backedge-taken count. ; bb: @@ -110,7 +114,8 @@ ; PTR64_IDX64-NEXT: --> {2,+,2}<%bb11> U: [0,-1) S: [-2147483648,2147483647) Exits: <> LoopDispositions: { %bb11: Computable } ; PTR64_IDX64-NEXT: Determining loop execution counts for: @trunc_ptr_to_i32 ; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable backedge-taken count. -; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable max backedge-taken count. +; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable constant max backedge-taken count. +; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable symbolic max backedge-taken count. ; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable predicated backedge-taken count. ; ; PTR64_IDX32-LABEL: 'trunc_ptr_to_i32' @@ -127,7 +132,8 @@ ; PTR64_IDX32-NEXT: --> {2,+,2}<%bb11> U: [0,-1) S: [-2147483648,2147483647) Exits: <> LoopDispositions: { %bb11: Computable } ; PTR64_IDX32-NEXT: Determining loop execution counts for: @trunc_ptr_to_i32 ; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable backedge-taken count. -; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable max backedge-taken count. +; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable constant max backedge-taken count. +; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable symbolic max backedge-taken count. ; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable predicated backedge-taken count. ; ; PTR16_IDX16-LABEL: 'trunc_ptr_to_i32' @@ -144,7 +150,8 @@ ; PTR16_IDX16-NEXT: --> {2,+,2}<%bb11> U: [0,-1) S: [-2147483648,2147483647) Exits: <> LoopDispositions: { %bb11: Computable } ; PTR16_IDX16-NEXT: Determining loop execution counts for: @trunc_ptr_to_i32 ; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable backedge-taken count. -; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable max backedge-taken count. +; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable constant max backedge-taken count. +; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable symbolic max backedge-taken count. ; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable predicated backedge-taken count. ; ; PTR16_IDX32-LABEL: 'trunc_ptr_to_i32' @@ -161,7 +168,8 @@ ; PTR16_IDX32-NEXT: --> {2,+,2}<%bb11> U: [0,-1) S: [-2147483648,2147483647) Exits: <> LoopDispositions: { %bb11: Computable } ; PTR16_IDX32-NEXT: Determining loop execution counts for: @trunc_ptr_to_i32 ; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable backedge-taken count. -; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable max backedge-taken count. +; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable constant max backedge-taken count. +; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable symbolic max backedge-taken count. ; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable predicated backedge-taken count. ; bb: @@ -197,7 +205,8 @@ ; PTR64_IDX64-NEXT: --> {2,+,2}<%bb11> U: [0,-1) S: [-2147483648,2147483647) Exits: <> LoopDispositions: { %bb11: Computable } ; PTR64_IDX64-NEXT: Determining loop execution counts for: @trunc_ptr_to_i128 ; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable backedge-taken count. -; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable max backedge-taken count. +; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable constant max backedge-taken count. +; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable symbolic max backedge-taken count. ; PTR64_IDX64-NEXT: Loop %bb11: Unpredictable predicated backedge-taken count. ; ; PTR64_IDX32-LABEL: 'trunc_ptr_to_i128' @@ -214,7 +223,8 @@ ; PTR64_IDX32-NEXT: --> {2,+,2}<%bb11> U: [0,-1) S: [-2147483648,2147483647) Exits: <> LoopDispositions: { %bb11: Computable } ; PTR64_IDX32-NEXT: Determining loop execution counts for: @trunc_ptr_to_i128 ; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable backedge-taken count. -; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable max backedge-taken count. +; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable constant max backedge-taken count. +; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable symbolic max backedge-taken count. ; PTR64_IDX32-NEXT: Loop %bb11: Unpredictable predicated backedge-taken count. ; ; PTR16_IDX16-LABEL: 'trunc_ptr_to_i128' @@ -231,7 +241,8 @@ ; PTR16_IDX16-NEXT: --> {2,+,2}<%bb11> U: [0,-1) S: [-2147483648,2147483647) Exits: <> LoopDispositions: { %bb11: Computable } ; PTR16_IDX16-NEXT: Determining loop execution counts for: @trunc_ptr_to_i128 ; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable backedge-taken count. -; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable max backedge-taken count. +; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable constant max backedge-taken count. +; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable symbolic max backedge-taken count. ; PTR16_IDX16-NEXT: Loop %bb11: Unpredictable predicated backedge-taken count. ; ; PTR16_IDX32-LABEL: 'trunc_ptr_to_i128' @@ -248,7 +259,8 @@ ; PTR16_IDX32-NEXT: --> {2,+,2}<%bb11> U: [0,-1) S: [-2147483648,2147483647) Exits: <> LoopDispositions: { %bb11: Computable } ; PTR16_IDX32-NEXT: Determining loop execution counts for: @trunc_ptr_to_i128 ; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable backedge-taken count. -; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable max backedge-taken count. +; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable constant max backedge-taken count. +; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable symbolic max backedge-taken count. ; PTR16_IDX32-NEXT: Loop %bb11: Unpredictable predicated backedge-taken count. ; bb: @@ -279,7 +291,8 @@ ; PTR64_IDX64-NEXT: --> %tmp9 U: [0,2) S: [0,2) Exits: <> LoopDispositions: { %bb7: Variant } ; PTR64_IDX64-NEXT: Determining loop execution counts for: @zext_ptr_to_i32 ; PTR64_IDX64-NEXT: Loop %bb7: Unpredictable backedge-taken count. -; PTR64_IDX64-NEXT: Loop %bb7: Unpredictable max backedge-taken count. +; PTR64_IDX64-NEXT: Loop %bb7: Unpredictable constant max backedge-taken count. +; PTR64_IDX64-NEXT: Loop %bb7: Unpredictable symbolic max backedge-taken count. ; PTR64_IDX64-NEXT: Loop %bb7: Unpredictable predicated backedge-taken count. ; ; PTR64_IDX32-LABEL: 'zext_ptr_to_i32' @@ -290,7 +303,8 @@ ; PTR64_IDX32-NEXT: --> %tmp9 U: [0,2) S: [0,2) Exits: <> LoopDispositions: { %bb7: Variant } ; PTR64_IDX32-NEXT: Determining loop execution counts for: @zext_ptr_to_i32 ; PTR64_IDX32-NEXT: Loop %bb7: Unpredictable backedge-taken count. -; PTR64_IDX32-NEXT: Loop %bb7: Unpredictable max backedge-taken count. +; PTR64_IDX32-NEXT: Loop %bb7: Unpredictable constant max backedge-taken count. +; PTR64_IDX32-NEXT: Loop %bb7: Unpredictable symbolic max backedge-taken count. ; PTR64_IDX32-NEXT: Loop %bb7: Unpredictable predicated backedge-taken count. ; ; PTR16_IDX16-LABEL: 'zext_ptr_to_i32' @@ -301,7 +315,8 @@ ; PTR16_IDX16-NEXT: --> %tmp9 U: [0,2) S: [0,2) Exits: <> LoopDispositions: { %bb7: Variant } ; PTR16_IDX16-NEXT: Determining loop execution counts for: @zext_ptr_to_i32 ; PTR16_IDX16-NEXT: Loop %bb7: Unpredictable backedge-taken count. -; PTR16_IDX16-NEXT: Loop %bb7: Unpredictable max backedge-taken count. +; PTR16_IDX16-NEXT: Loop %bb7: Unpredictable constant max backedge-taken count. +; PTR16_IDX16-NEXT: Loop %bb7: Unpredictable symbolic max backedge-taken count. ; PTR16_IDX16-NEXT: Loop %bb7: Unpredictable predicated backedge-taken count. ; ; PTR16_IDX32-LABEL: 'zext_ptr_to_i32' @@ -312,7 +327,8 @@ ; PTR16_IDX32-NEXT: --> %tmp9 U: [0,2) S: [0,2) Exits: <> LoopDispositions: { %bb7: Variant } ; PTR16_IDX32-NEXT: Determining loop execution counts for: @zext_ptr_to_i32 ; PTR16_IDX32-NEXT: Loop %bb7: Unpredictable backedge-taken count. -; PTR16_IDX32-NEXT: Loop %bb7: Unpredictable max backedge-taken count. +; PTR16_IDX32-NEXT: Loop %bb7: Unpredictable constant max backedge-taken count. +; PTR16_IDX32-NEXT: Loop %bb7: Unpredictable symbolic max backedge-taken count. ; PTR16_IDX32-NEXT: Loop %bb7: Unpredictable predicated backedge-taken count. ; bb: @@ -338,7 +354,8 @@ ; PTR64_IDX64-NEXT: --> %tmp9 U: [0,2) S: [0,2) Exits: <> LoopDispositions: { %bb7: Variant } ; PTR64_IDX64-NEXT: Determining loop execution counts for: @sext_to_i32 ; PTR64_IDX64-NEXT: Loop %bb7: Unpredictable backedge-taken count. -; PTR64_IDX64-NEXT: Loop %bb7: Unpredictable max backedge-taken count. +; PTR64_IDX64-NEXT: Loop %bb7: Unpredictable constant max backedge-taken count. +; PTR64_IDX64-NEXT: Loop %bb7: Unpredictable symbolic max backedge-taken count. ; PTR64_IDX64-NEXT: Loop %bb7: Unpredictable predicated backedge-taken count. ; ; PTR64_IDX32-LABEL: 'sext_to_i32' @@ -349,7 +366,8 @@ ; PTR64_IDX32-NEXT: --> %tmp9 U: [0,2) S: [0,2) Exits: <> LoopDispositions: { %bb7: Variant } ; PTR64_IDX32-NEXT: Determining loop execution counts for: @sext_to_i32 ; PTR64_IDX32-NEXT: Loop %bb7: Unpredictable backedge-taken count. -; PTR64_IDX32-NEXT: Loop %bb7: Unpredictable max backedge-taken count. +; PTR64_IDX32-NEXT: Loop %bb7: Unpredictable constant max backedge-taken count. +; PTR64_IDX32-NEXT: Loop %bb7: Unpredictable symbolic max backedge-taken count. ; PTR64_IDX32-NEXT: Loop %bb7: Unpredictable predicated backedge-taken count. ; ; PTR16_IDX16-LABEL: 'sext_to_i32' @@ -360,7 +378,8 @@ ; PTR16_IDX16-NEXT: --> %tmp9 U: [0,2) S: [0,2) Exits: <> LoopDispositions: { %bb7: Variant } ; PTR16_IDX16-NEXT: Determining loop execution counts for: @sext_to_i32 ; PTR16_IDX16-NEXT: Loop %bb7: Unpredictable backedge-taken count. -; PTR16_IDX16-NEXT: Loop %bb7: Unpredictable max backedge-taken count. +; PTR16_IDX16-NEXT: Loop %bb7: Unpredictable constant max backedge-taken count. +; PTR16_IDX16-NEXT: Loop %bb7: Unpredictable symbolic max backedge-taken count. ; PTR16_IDX16-NEXT: Loop %bb7: Unpredictable predicated backedge-taken count. ; ; PTR16_IDX32-LABEL: 'sext_to_i32' @@ -371,7 +390,8 @@ ; PTR16_IDX32-NEXT: --> %tmp9 U: [0,2) S: [0,2) Exits: <> LoopDispositions: { %bb7: Variant } ; PTR16_IDX32-NEXT: Determining loop execution counts for: @sext_to_i32 ; PTR16_IDX32-NEXT: Loop %bb7: Unpredictable backedge-taken count. -; PTR16_IDX32-NEXT: Loop %bb7: Unpredictable max backedge-taken count. +; PTR16_IDX32-NEXT: Loop %bb7: Unpredictable constant max backedge-taken count. +; PTR16_IDX32-NEXT: Loop %bb7: Unpredictable symbolic max backedge-taken count. ; PTR16_IDX32-NEXT: Loop %bb7: Unpredictable predicated backedge-taken count. ; bb: @@ -401,7 +421,8 @@ ; PTR64_IDX64-NEXT: --> {2,+,1}<%for.body> U: [2,0) S: [2,0) Exits: (trunc i64 (ptrtoint i64 (i32)* @sext_like_noop to i64) to i32) LoopDispositions: { %for.body: Computable } ; PTR64_IDX64-NEXT: Determining loop execution counts for: @sext_like_noop ; PTR64_IDX64-NEXT: Loop %for.body: backedge-taken count is (-2 + (trunc i64 (ptrtoint i64 (i32)* @sext_like_noop to i64) to i32)) -; PTR64_IDX64-NEXT: Loop %for.body: max backedge-taken count is -1 +; PTR64_IDX64-NEXT: Loop %for.body: constant max backedge-taken count is -1 +; PTR64_IDX64-NEXT: Loop %for.body: symbolic max backedge-taken count is (-2 + (trunc i64 (ptrtoint i64 (i32)* @sext_like_noop to i64) to i32)) ; PTR64_IDX64-NEXT: Loop %for.body: Predicated backedge-taken count is (-2 + (trunc i64 (ptrtoint i64 (i32)* @sext_like_noop to i64) to i32)) ; PTR64_IDX64-NEXT: Predicates: ; PTR64_IDX64: Loop %for.body: Trip multiple is 1 @@ -418,7 +439,8 @@ ; PTR64_IDX32-NEXT: --> {2,+,1}<%for.body> U: [2,0) S: [2,0) Exits: ptrtoint (i64 (i32)* @sext_like_noop to i32) LoopDispositions: { %for.body: Computable } ; PTR64_IDX32-NEXT: Determining loop execution counts for: @sext_like_noop ; PTR64_IDX32-NEXT: Loop %for.body: backedge-taken count is (-2 + ptrtoint (i64 (i32)* @sext_like_noop to i32)) -; PTR64_IDX32-NEXT: Loop %for.body: max backedge-taken count is -1 +; PTR64_IDX32-NEXT: Loop %for.body: constant max backedge-taken count is -1 +; PTR64_IDX32-NEXT: Loop %for.body: symbolic max backedge-taken count is (-2 + ptrtoint (i64 (i32)* @sext_like_noop to i32)) ; PTR64_IDX32-NEXT: Loop %for.body: Predicated backedge-taken count is (-2 + ptrtoint (i64 (i32)* @sext_like_noop to i32)) ; PTR64_IDX32-NEXT: Predicates: ; PTR64_IDX32: Loop %for.body: Trip multiple is 1 @@ -435,7 +457,8 @@ ; PTR16_IDX16-NEXT: --> {2,+,1}<%for.body> U: [2,0) S: [2,0) Exits: (zext i16 (ptrtoint i64 (i32)* @sext_like_noop to i16) to i32) LoopDispositions: { %for.body: Computable } ; PTR16_IDX16-NEXT: Determining loop execution counts for: @sext_like_noop ; PTR16_IDX16-NEXT: Loop %for.body: backedge-taken count is (-2 + (zext i16 (ptrtoint i64 (i32)* @sext_like_noop to i16) to i32)) -; PTR16_IDX16-NEXT: Loop %for.body: max backedge-taken count is -1 +; PTR16_IDX16-NEXT: Loop %for.body: constant max backedge-taken count is -1 +; PTR16_IDX16-NEXT: Loop %for.body: symbolic max backedge-taken count is (-2 + (zext i16 (ptrtoint i64 (i32)* @sext_like_noop to i16) to i32)) ; PTR16_IDX16-NEXT: Loop %for.body: Predicated backedge-taken count is (-2 + (zext i16 (ptrtoint i64 (i32)* @sext_like_noop to i16) to i32)) ; PTR16_IDX16-NEXT: Predicates: ; PTR16_IDX16: Loop %for.body: Trip multiple is 1 @@ -452,7 +475,8 @@ ; PTR16_IDX32-NEXT: --> {2,+,1}<%for.body> U: [2,0) S: [2,0) Exits: ptrtoint (i64 (i32)* @sext_like_noop to i32) LoopDispositions: { %for.body: Computable } ; PTR16_IDX32-NEXT: Determining loop execution counts for: @sext_like_noop ; PTR16_IDX32-NEXT: Loop %for.body: backedge-taken count is (-2 + ptrtoint (i64 (i32)* @sext_like_noop to i32)) -; PTR16_IDX32-NEXT: Loop %for.body: max backedge-taken count is -1 +; PTR16_IDX32-NEXT: Loop %for.body: constant max backedge-taken count is -1 +; PTR16_IDX32-NEXT: Loop %for.body: symbolic max backedge-taken count is (-2 + ptrtoint (i64 (i32)* @sext_like_noop to i32)) ; PTR16_IDX32-NEXT: Loop %for.body: Predicated backedge-taken count is (-2 + ptrtoint (i64 (i32)* @sext_like_noop to i32)) ; PTR16_IDX32-NEXT: Predicates: ; PTR16_IDX32: Loop %for.body: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/ptrtoint.ll b/llvm/test/Analysis/ScalarEvolution/ptrtoint.ll --- a/llvm/test/Analysis/ScalarEvolution/ptrtoint.ll +++ b/llvm/test/Analysis/ScalarEvolution/ptrtoint.ll @@ -229,7 +229,8 @@ ; X64-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: (zext i32 %count to i64) LoopDispositions: { %loop: Computable } ; X64-NEXT: Determining loop execution counts for: @ptrtoint_of_addrec ; X64-NEXT: Loop %loop: backedge-taken count is (-1 + (zext i32 %count to i64)) -; X64-NEXT: Loop %loop: max backedge-taken count is -1 +; X64-NEXT: Loop %loop: constant max backedge-taken count is -1 +; X64-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (zext i32 %count to i64)) ; X64-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (zext i32 %count to i64)) ; X64-NEXT: Predicates: ; X64: Loop %loop: Trip multiple is 1 @@ -248,7 +249,8 @@ ; X32-NEXT: --> {1,+,1}<%loop> U: [1,0) S: [1,0) Exits: (zext i32 %count to i64) LoopDispositions: { %loop: Computable } ; X32-NEXT: Determining loop execution counts for: @ptrtoint_of_addrec ; X32-NEXT: Loop %loop: backedge-taken count is (-1 + (zext i32 %count to i64)) -; X32-NEXT: Loop %loop: max backedge-taken count is -1 +; X32-NEXT: Loop %loop: constant max backedge-taken count is -1 +; X32-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (zext i32 %count to i64)) ; X32-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (zext i32 %count to i64)) ; X32-NEXT: Predicates: ; X32: Loop %loop: Trip multiple is 1 @@ -395,7 +397,8 @@ ; X64-NEXT: --> {(1 + %arg),+,1}<%bb6> U: full-set S: full-set Exits: ((-1 * (ptrtoint i8* %arg to i64)) + (ptrtoint i8* %arg1 to i64) + %arg) LoopDispositions: { %bb6: Computable } ; X64-NEXT: Determining loop execution counts for: @pr46786_c26_char ; X64-NEXT: Loop %bb6: backedge-taken count is (-1 + (-1 * (ptrtoint i8* %arg to i64)) + (ptrtoint i8* %arg1 to i64)) -; X64-NEXT: Loop %bb6: max backedge-taken count is -1 +; X64-NEXT: Loop %bb6: constant max backedge-taken count is -1 +; X64-NEXT: Loop %bb6: symbolic max backedge-taken count is (-1 + (-1 * (ptrtoint i8* %arg to i64)) + (ptrtoint i8* %arg1 to i64)) ; X64-NEXT: Loop %bb6: Predicated backedge-taken count is (-1 + (-1 * (ptrtoint i8* %arg to i64)) + (ptrtoint i8* %arg1 to i64)) ; X64-NEXT: Predicates: ; X64: Loop %bb6: Trip multiple is 1 @@ -422,7 +425,8 @@ ; X32-NEXT: --> {(1 + %arg),+,1}<%bb6> U: full-set S: full-set Exits: ((-1 * (ptrtoint i8* %arg to i32)) + (ptrtoint i8* %arg1 to i32) + %arg) LoopDispositions: { %bb6: Computable } ; X32-NEXT: Determining loop execution counts for: @pr46786_c26_char ; X32-NEXT: Loop %bb6: backedge-taken count is (-1 + (-1 * (ptrtoint i8* %arg to i32)) + (ptrtoint i8* %arg1 to i32)) -; X32-NEXT: Loop %bb6: max backedge-taken count is -1 +; X32-NEXT: Loop %bb6: constant max backedge-taken count is -1 +; X32-NEXT: Loop %bb6: symbolic max backedge-taken count is (-1 + (-1 * (ptrtoint i8* %arg to i32)) + (ptrtoint i8* %arg1 to i32)) ; X32-NEXT: Loop %bb6: Predicated backedge-taken count is (-1 + (-1 * (ptrtoint i8* %arg to i32)) + (ptrtoint i8* %arg1 to i32)) ; X32-NEXT: Predicates: ; X32: Loop %bb6: Trip multiple is 1 @@ -482,7 +486,8 @@ ; X64-NEXT: --> {(4 + %arg),+,4}<%bb6> U: full-set S: full-set Exits: (4 + (4 * ((-4 + (-1 * (ptrtoint i32* %arg to i64)) + (ptrtoint i32* %arg1 to i64)) /u 4)) + %arg) LoopDispositions: { %bb6: Computable } ; X64-NEXT: Determining loop execution counts for: @pr46786_c26_int ; X64-NEXT: Loop %bb6: backedge-taken count is ((-4 + (-1 * (ptrtoint i32* %arg to i64)) + (ptrtoint i32* %arg1 to i64)) /u 4) -; X64-NEXT: Loop %bb6: max backedge-taken count is 4611686018427387903 +; X64-NEXT: Loop %bb6: constant max backedge-taken count is 4611686018427387903 +; X64-NEXT: Loop %bb6: symbolic max backedge-taken count is ((-4 + (-1 * (ptrtoint i32* %arg to i64)) + (ptrtoint i32* %arg1 to i64)) /u 4) ; X64-NEXT: Loop %bb6: Predicated backedge-taken count is ((-4 + (-1 * (ptrtoint i32* %arg to i64)) + (ptrtoint i32* %arg1 to i64)) /u 4) ; X64-NEXT: Predicates: ; X64: Loop %bb6: Trip multiple is 1 @@ -511,7 +516,8 @@ ; X32-NEXT: --> {(4 + %arg),+,4}<%bb6> U: full-set S: full-set Exits: (4 + (4 * ((-4 + (-1 * (ptrtoint i32* %arg to i32)) + (ptrtoint i32* %arg1 to i32)) /u 4)) + %arg) LoopDispositions: { %bb6: Computable } ; X32-NEXT: Determining loop execution counts for: @pr46786_c26_int ; X32-NEXT: Loop %bb6: backedge-taken count is ((-4 + (-1 * (ptrtoint i32* %arg to i32)) + (ptrtoint i32* %arg1 to i32)) /u 4) -; X32-NEXT: Loop %bb6: max backedge-taken count is 1073741823 +; X32-NEXT: Loop %bb6: constant max backedge-taken count is 1073741823 +; X32-NEXT: Loop %bb6: symbolic max backedge-taken count is ((-4 + (-1 * (ptrtoint i32* %arg to i32)) + (ptrtoint i32* %arg1 to i32)) /u 4) ; X32-NEXT: Loop %bb6: Predicated backedge-taken count is ((-4 + (-1 * (ptrtoint i32* %arg to i32)) + (ptrtoint i32* %arg1 to i32)) /u 4) ; X32-NEXT: Predicates: ; X32: Loop %bb6: Trip multiple is 1 @@ -558,7 +564,10 @@ ; X64-NEXT: Loop %bb8: Unpredictable backedge-taken count. ; X64-NEXT: exit count for bb8: ***COULDNOTCOMPUTE*** ; X64-NEXT: exit count for bb10: (-2 + (-1 * %arg1) + (ptrtoint i8* %arg to i64)) -; X64-NEXT: Loop %bb8: max backedge-taken count is -1 +; X64-NEXT: Loop %bb8: constant max backedge-taken count is -1 +; X64-NEXT: Loop %bb8: symbolic max backedge-taken count is (-2 + (-1 * %arg1) + (ptrtoint i8* %arg to i64)) +; X64-NEXT: symbolic max exit count for bb8: ***COULDNOTCOMPUTE*** +; X64-NEXT: symbolic max exit count for bb10: (-2 + (-1 * %arg1) + (ptrtoint i8* %arg to i64)) ; X64-NEXT: Loop %bb8: Unpredictable predicated backedge-taken count. ; ; X32-LABEL: 'ptrtoint_of_integer' @@ -575,7 +584,10 @@ ; X32-NEXT: Loop %bb8: Unpredictable backedge-taken count. ; X32-NEXT: exit count for bb8: ***COULDNOTCOMPUTE*** ; X32-NEXT: exit count for bb10: (-2 + (zext i32 (ptrtoint i8* %arg to i32) to i64) + (-1 * %arg1)) -; X32-NEXT: Loop %bb8: max backedge-taken count is -1 +; X32-NEXT: Loop %bb8: constant max backedge-taken count is -1 +; X32-NEXT: Loop %bb8: symbolic max backedge-taken count is (-2 + (zext i32 (ptrtoint i8* %arg to i32) to i64) + (-1 * %arg1)) +; X32-NEXT: symbolic max exit count for bb8: ***COULDNOTCOMPUTE*** +; X32-NEXT: symbolic max exit count for bb10: (-2 + (zext i32 (ptrtoint i8* %arg to i32) to i64) + (-1 * %arg1)) ; X32-NEXT: Loop %bb8: Unpredictable predicated backedge-taken count. ; bb: diff --git a/llvm/test/Analysis/ScalarEvolution/range_nw_flag.ll b/llvm/test/Analysis/ScalarEvolution/range_nw_flag.ll --- a/llvm/test/Analysis/ScalarEvolution/range_nw_flag.ll +++ b/llvm/test/Analysis/ScalarEvolution/range_nw_flag.ll @@ -15,7 +15,8 @@ ; CHECK-NEXT: --> ((4 * (sext i32 {(1 + %offset),+,1}<%loop> to i64)) + %input) U: full-set S: full-set Exits: ((4 * (sext i32 (%offset + %numIterations) to i64)) + %input) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-add-nuw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -50,7 +51,8 @@ ; CHECK-NEXT: --> ((4 * (sext i32 {(1 + (10 smax %offset)),+,1}<%loop> to i64)) + %input) U: full-set S: full-set Exits: ((4 * (sext i32 ((10 smax %offset) + %numIterations) to i64)) + %input) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-addrec-nuw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -87,7 +89,8 @@ ; CHECK-NEXT: --> {(-4 + (4 * (sext i32 (-10 smin %offset) to i64)) + %input),+,-4}<%loop> U: full-set S: full-set Exits: (-4 + (4 * (sext i32 (-10 smin %offset) to i64)) + (-4 * (zext i32 (-1 + (-1 * %numIterations)) to i64)) + %input) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-addrec-nsw-start-neg-strip-neg ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %numIterations)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %numIterations)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %numIterations)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -124,7 +127,8 @@ ; CHECK-NEXT: --> {(-4 + (4 * (sext i32 (10 smin %offset) to i64)) + %input),+,-4}<%loop> U: full-set S: full-set Exits: (-4 + (4 * (sext i32 (10 smin %offset) to i64)) + (-4 * (zext i32 (-1 + (-1 * %numIterations)) to i64)) + %input) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-addrec-nsw-start-pos-strip-neg ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %numIterations)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %numIterations)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %numIterations)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -161,7 +165,8 @@ ; CHECK-NEXT: --> {(4 + (4 * (zext i32 (10 smax %offset) to i64)) + %input),+,4}<%loop> U: [44,0) S: [44,0) Exits: (4 + (4 * (zext i32 (-1 + %numIterations) to i64)) + (4 * (zext i32 (10 smax %offset) to i64)) + %input) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-addrec-nsw-start-pos-strip-pos ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -198,7 +203,8 @@ ; CHECK-NEXT: --> {(4 + (4 * (sext i32 (-10 smax %offset) to i64)) + %input),+,4}<%loop> U: full-set S: full-set Exits: (4 + (4 * (zext i32 (-1 + %numIterations) to i64)) + (4 * (sext i32 (-10 smax %offset) to i64)) + %input) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @test-addrec-nsw-start-neg-strip-pos ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %numIterations) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %numIterations) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/ranges.ll b/llvm/test/Analysis/ScalarEvolution/ranges.ll --- a/llvm/test/Analysis/ScalarEvolution/ranges.ll +++ b/llvm/test/Analysis/ScalarEvolution/ranges.ll @@ -114,7 +114,8 @@ ; CHECK-NEXT: --> (%range.1 /u 2) U: [0,1) S: [0,1) Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @phi_div ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/sdiv.ll b/llvm/test/Analysis/ScalarEvolution/sdiv.ll --- a/llvm/test/Analysis/ScalarEvolution/sdiv.ll +++ b/llvm/test/Analysis/ScalarEvolution/sdiv.ll @@ -31,7 +31,8 @@ ; CHECK-NEXT: --> {1,+,1}<%for.cond> U: [1,0) S: [1,0) Exits: (1 + %width) LoopDispositions: { %for.cond: Computable } ; CHECK-NEXT: Determining loop execution counts for: @_Z4loopi ; CHECK-NEXT: Loop %for.cond: backedge-taken count is %width -; CHECK-NEXT: Loop %for.cond: max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.cond: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.cond: symbolic max backedge-taken count is %width ; CHECK-NEXT: Loop %for.cond: Predicated backedge-taken count is %width ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.cond: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/sext-mul.ll b/llvm/test/Analysis/ScalarEvolution/sext-mul.ll --- a/llvm/test/Analysis/ScalarEvolution/sext-mul.ll +++ b/llvm/test/Analysis/ScalarEvolution/sext-mul.ll @@ -1,20 +1,41 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; RUN: opt < %s -disable-output "-passes=print" 2>&1 | FileCheck %s -; CHECK: %tmp9 = shl i64 %tmp8, 33 -; CHECK-NEXT: --> {{.*}} Exits: (-8589934592 + (8589934592 * (zext i32 %arg2 to i64))) -; CHECK: %tmp10 = ashr exact i64 %tmp9, 32 -; CHECK-NEXT: --> {{.*}} Exits: (sext i32 (-2 + (2 * %arg2)) to i64) -; CHECK: %tmp11 = getelementptr inbounds i32, i32* %arg, i64 %tmp10 -; CHECK-NEXT: --> {{.*}} Exits: ((4 * (sext i32 (-2 + (2 * %arg2)) to i64)) + %arg) -; CHECK: %tmp14 = or i64 %tmp10, 1 -; CHECK-NEXT: --> {{.*}} Exits: (1 + (sext i32 (-2 + (2 * %arg2)) to i64)) -; CHECK: %tmp15 = getelementptr inbounds i32, i32* %arg, i64 %tmp14 -; CHECK-NEXT: --> {{.*}} Exits: (4 + (4 * (sext i32 (-2 + (2 * %arg2)) to i64)) + %arg) -; CHECK:Loop %bb7: backedge-taken count is (-1 + (zext i32 %arg2 to i64)) -; CHECK-NEXT:Loop %bb7: max backedge-taken count is 2147483646 -; CHECK-NEXT:Loop %bb7: Predicated backedge-taken count is (-1 + (zext i32 %arg2 to i64)) - define void @foo(i32* nocapture %arg, i32 %arg1, i32 %arg2) { +; CHECK-LABEL: 'foo' +; CHECK-NEXT: Classifying expressions for: @foo +; CHECK-NEXT: %tmp4 = zext i32 %arg2 to i64 +; CHECK-NEXT: --> (zext i32 %arg2 to i64) U: [0,4294967296) S: [0,4294967296) +; CHECK-NEXT: %tmp8 = phi i64 [ %tmp18, %bb7 ], [ 0, %bb3 ] +; CHECK-NEXT: --> {0,+,1}<%bb7> U: [0,2147483647) S: [0,2147483647) Exits: (-1 + (zext i32 %arg2 to i64)) LoopDispositions: { %bb7: Computable } +; CHECK-NEXT: %tmp9 = shl i64 %tmp8, 33 +; CHECK-NEXT: --> {0,+,8589934592}<%bb7> U: [0,-17179869183) S: [-9223372036854775808,9223372028264841217) Exits: (-8589934592 + (8589934592 * (zext i32 %arg2 to i64))) LoopDispositions: { %bb7: Computable } +; CHECK-NEXT: %tmp10 = ashr exact i64 %tmp9, 32 +; CHECK-NEXT: --> (sext i32 {0,+,2}<%bb7> to i64) U: [0,-1) S: [-2147483648,2147483647) Exits: (sext i32 (-2 + (2 * %arg2)) to i64) LoopDispositions: { %bb7: Computable } +; CHECK-NEXT: %tmp11 = getelementptr inbounds i32, i32* %arg, i64 %tmp10 +; CHECK-NEXT: --> ((4 * (sext i32 {0,+,2}<%bb7> to i64)) + %arg) U: full-set S: full-set Exits: ((4 * (sext i32 (-2 + (2 * %arg2)) to i64)) + %arg) LoopDispositions: { %bb7: Computable } +; CHECK-NEXT: %tmp12 = load i32, i32* %tmp11, align 4 +; CHECK-NEXT: --> %tmp12 U: full-set S: full-set Exits: <> LoopDispositions: { %bb7: Variant } +; CHECK-NEXT: %tmp13 = sub nsw i32 %tmp12, %arg1 +; CHECK-NEXT: --> ((-1 * %arg1) + %tmp12) U: full-set S: full-set Exits: <> LoopDispositions: { %bb7: Variant } +; CHECK-NEXT: %tmp14 = or i64 %tmp10, 1 +; CHECK-NEXT: --> (1 + (sext i32 {0,+,2}<%bb7> to i64)) U: [1,0) S: [-2147483647,2147483648) Exits: (1 + (sext i32 (-2 + (2 * %arg2)) to i64)) LoopDispositions: { %bb7: Computable } +; CHECK-NEXT: %tmp15 = getelementptr inbounds i32, i32* %arg, i64 %tmp14 +; CHECK-NEXT: --> (4 + (4 * (sext i32 {0,+,2}<%bb7> to i64)) + %arg) U: full-set S: full-set Exits: (4 + (4 * (sext i32 (-2 + (2 * %arg2)) to i64)) + %arg) LoopDispositions: { %bb7: Computable } +; CHECK-NEXT: %tmp16 = load i32, i32* %tmp15, align 4 +; CHECK-NEXT: --> %tmp16 U: full-set S: full-set Exits: <> LoopDispositions: { %bb7: Variant } +; CHECK-NEXT: %tmp17 = mul nsw i32 %tmp16, %arg1 +; CHECK-NEXT: --> (%arg1 * %tmp16) U: full-set S: full-set Exits: <> LoopDispositions: { %bb7: Variant } +; CHECK-NEXT: %tmp18 = add nuw nsw i64 %tmp8, 1 +; CHECK-NEXT: --> {1,+,1}<%bb7> U: [1,2147483648) S: [1,2147483648) Exits: (zext i32 %arg2 to i64) LoopDispositions: { %bb7: Computable } +; CHECK-NEXT: Determining loop execution counts for: @foo +; CHECK-NEXT: Loop %bb7: backedge-taken count is (-1 + (zext i32 %arg2 to i64)) +; CHECK-NEXT: Loop %bb7: constant max backedge-taken count is 2147483646 +; CHECK-NEXT: Loop %bb7: symbolic max backedge-taken count is (-1 + (zext i32 %arg2 to i64)) +; CHECK-NEXT: Loop %bb7: Predicated backedge-taken count is (-1 + (zext i32 %arg2 to i64)) +; CHECK-NEXT: Predicates: +; CHECK: Loop %bb7: Trip multiple is 1 +; bb: %tmp = icmp sgt i32 %arg2, 0 br i1 %tmp, label %bb3, label %bb6 @@ -47,15 +68,41 @@ br i1 %tmp19, label %bb5, label %bb7 } -; CHECK: %t10 = ashr exact i128 %t9, 1 -; CHECK-NEXT: --> {{.*}} Exits: (sext i127 (-633825300114114700748351602688 + (633825300114114700748351602688 * (zext i32 %arg5 to i127))) to i128) -; CHECK: %t14 = or i128 %t10, 1 -; CHECK-NEXT: --> {{.*}} Exits: (1 + (sext i127 (-633825300114114700748351602688 + (633825300114114700748351602688 * (zext i32 %arg5 to i127))) to i128)) -; CHECK: Loop %bb7: backedge-taken count is (-1 + (zext i32 %arg5 to i128)) -; CHECK-NEXT: Loop %bb7: max backedge-taken count is 2147483646 -; CHECK-NEXT: Loop %bb7: Predicated backedge-taken count is (-1 + (zext i32 %arg5 to i128)) - define void @goo(i32* nocapture %arg3, i32 %arg4, i32 %arg5) { +; CHECK-LABEL: 'goo' +; CHECK-NEXT: Classifying expressions for: @goo +; CHECK-NEXT: %t4 = zext i32 %arg5 to i128 +; CHECK-NEXT: --> (zext i32 %arg5 to i128) U: [0,4294967296) S: [0,4294967296) +; CHECK-NEXT: %t8 = phi i128 [ %t18, %bb7 ], [ 0, %bb3 ] +; CHECK-NEXT: --> {0,+,1}<%bb7> U: [0,2147483647) S: [0,2147483647) Exits: (-1 + (zext i32 %arg5 to i128)) LoopDispositions: { %bb7: Computable } +; CHECK-NEXT: %t9 = shl i128 %t8, 100 +; CHECK-NEXT: --> {0,+,1267650600228229401496703205376}<%bb7> U: [0,-1267650600228229401496703205375) S: [-170141183460469231731687303715884105728,170141182192818631503457902219180900353) Exits: (-1267650600228229401496703205376 + (1267650600228229401496703205376 * (zext i32 %arg5 to i128))) LoopDispositions: { %bb7: Computable } +; CHECK-NEXT: %t10 = ashr exact i128 %t9, 1 +; CHECK-NEXT: --> (sext i127 {0,+,633825300114114700748351602688}<%bb7> to i128) U: [0,-633825300114114700748351602687) S: [-85070591730234615865843651857942052864,85070591096409315751728951109590450177) Exits: (sext i127 (-633825300114114700748351602688 + (633825300114114700748351602688 * (zext i32 %arg5 to i127))) to i128) LoopDispositions: { %bb7: Computable } +; CHECK-NEXT: %t11 = getelementptr inbounds i32, i32* %arg3, i128 %t10 +; CHECK-NEXT: --> %arg3 U: full-set S: full-set Exits: %arg3 LoopDispositions: { %bb7: Invariant } +; CHECK-NEXT: %t12 = load i32, i32* %t11, align 4 +; CHECK-NEXT: --> %t12 U: full-set S: full-set Exits: <> LoopDispositions: { %bb7: Variant } +; CHECK-NEXT: %t13 = sub nsw i32 %t12, %arg4 +; CHECK-NEXT: --> ((-1 * %arg4) + %t12) U: full-set S: full-set Exits: <> LoopDispositions: { %bb7: Variant } +; CHECK-NEXT: %t14 = or i128 %t10, 1 +; CHECK-NEXT: --> (1 + (sext i127 {0,+,633825300114114700748351602688}<%bb7> to i128)) U: [1,-633825300114114700748351602686) S: [-85070591730234615865843651857942052863,85070591096409315751728951109590450178) Exits: (1 + (sext i127 (-633825300114114700748351602688 + (633825300114114700748351602688 * (zext i32 %arg5 to i127))) to i128)) LoopDispositions: { %bb7: Computable } +; CHECK-NEXT: %t15 = getelementptr inbounds i32, i32* %arg3, i128 %t14 +; CHECK-NEXT: --> (4 + %arg3) U: [4,0) S: [4,0) Exits: (4 + %arg3) LoopDispositions: { %bb7: Invariant } +; CHECK-NEXT: %t16 = load i32, i32* %t15, align 4 +; CHECK-NEXT: --> %t16 U: full-set S: full-set Exits: <> LoopDispositions: { %bb7: Variant } +; CHECK-NEXT: %t17 = mul nsw i32 %t16, %arg4 +; CHECK-NEXT: --> (%arg4 * %t16) U: full-set S: full-set Exits: <> LoopDispositions: { %bb7: Variant } +; CHECK-NEXT: %t18 = add nuw nsw i128 %t8, 1 +; CHECK-NEXT: --> {1,+,1}<%bb7> U: [1,2147483648) S: [1,2147483648) Exits: (zext i32 %arg5 to i128) LoopDispositions: { %bb7: Computable } +; CHECK-NEXT: Determining loop execution counts for: @goo +; CHECK-NEXT: Loop %bb7: backedge-taken count is (-1 + (zext i32 %arg5 to i128)) +; CHECK-NEXT: Loop %bb7: constant max backedge-taken count is 2147483646 +; CHECK-NEXT: Loop %bb7: symbolic max backedge-taken count is (-1 + (zext i32 %arg5 to i128)) +; CHECK-NEXT: Loop %bb7: Predicated backedge-taken count is (-1 + (zext i32 %arg5 to i128)) +; CHECK-NEXT: Predicates: +; CHECK: Loop %bb7: Trip multiple is 1 +; bb: %t = icmp sgt i32 %arg5, 0 br i1 %t, label %bb3, label %bb6 diff --git a/llvm/test/Analysis/ScalarEvolution/sext-to-zext.ll b/llvm/test/Analysis/ScalarEvolution/sext-to-zext.ll --- a/llvm/test/Analysis/ScalarEvolution/sext-to-zext.ll +++ b/llvm/test/Analysis/ScalarEvolution/sext-to-zext.ll @@ -20,7 +20,8 @@ ; CHECK-NEXT: --> {(zext i32 %start to i64),+,(sext i32 %step to i64)}<%loop> U: [0,101) S: [0,101) Exits: ((zext i32 %start to i64) + (99 * (sext i32 %step to i64))) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @f ; CHECK-NEXT: Loop %loop: backedge-taken count is 99 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 99 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 99 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 99 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 99 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 100 diff --git a/llvm/test/Analysis/ScalarEvolution/shift-op.ll b/llvm/test/Analysis/ScalarEvolution/shift-op.ll --- a/llvm/test/Analysis/ScalarEvolution/shift-op.ll +++ b/llvm/test/Analysis/ScalarEvolution/shift-op.ll @@ -2,7 +2,7 @@ define void @test0(i32 %init) { ; CHECK-LABEL: Classifying expressions for: @test0 -; CHECK: Loop %loop: max backedge-taken count is 32 +; CHECK: Loop %loop: constant max backedge-taken count is 32 entry: br label %loop @@ -18,7 +18,7 @@ define void @test1(i32 %init) { ; CHECK-LABEL: Classifying expressions for: @test1 -; CHECK: Loop %loop: max backedge-taken count is 32 +; CHECK: Loop %loop: constant max backedge-taken count is 32 entry: br label %loop @@ -34,7 +34,7 @@ define void @test2(i32 %init) { ; CHECK-LABEL: Determining loop execution counts for: @test2 -; CHECK: Loop %loop: Unpredictable max backedge-taken count. +; CHECK: Loop %loop: Unpredictable constant max backedge-taken count. ; Unpredictable because %iv could "stabilize" to either -1 or 0, ; depending on %init. @@ -53,7 +53,7 @@ define void @test3(i32* %init.ptr) { ; CHECK-LABEL: Determining loop execution counts for: @test3 -; CHECK: Loop %loop: max backedge-taken count is 32 +; CHECK: Loop %loop: constant max backedge-taken count is 32 entry: %init = load i32, i32* %init.ptr, !range !0 br label %loop @@ -70,7 +70,7 @@ define void @test4(i32* %init.ptr) { ; CHECK-LABEL: Classifying expressions for: @test4 -; CHECK-LABEL: Loop %loop: max backedge-taken count is 32 +; CHECK-LABEL: Loop %loop: constant max backedge-taken count is 32 entry: %init = load i32, i32* %init.ptr, !range !1 br label %loop @@ -87,7 +87,7 @@ define void @test5(i32* %init.ptr) { ; CHECK-LABEL: Determining loop execution counts for: @test5 -; CHECK: Loop %loop: Unpredictable max backedge-taken count. +; CHECK: Loop %loop: Unpredictable constant max backedge-taken count. ; %iv will "stabilize" to -1, so this is an infinite loop entry: @@ -106,7 +106,7 @@ define void @test6(i32 %init, i32 %shift.amt) { ; CHECK-LABEL: Determining loop execution counts for: @test6 -; CHECK: Loop %loop: Unpredictable max backedge-taken count. +; CHECK: Loop %loop: Unpredictable constant max backedge-taken count. ; Potentially infinite loop, since %shift.amt could be 0 entry: @@ -124,7 +124,7 @@ define void @test7(i32 %init) { ; CHECK-LABEL: Classifying expressions for: @test7 -; CHECK: Loop %loop: max backedge-taken count is 32 +; CHECK: Loop %loop: constant max backedge-taken count is 32 entry: br label %loop @@ -141,7 +141,7 @@ define void @test8(i32 %init) { ; CHECK-LABEL: Classifying expressions for: @test8 -; CHECK: Loop %loop: Unpredictable max backedge-taken count. +; CHECK: Loop %loop: Unpredictable constant max backedge-taken count. ; In this test case, %iv.test stabilizes to 127, not -1, so the loop ; is infinite. @@ -162,7 +162,7 @@ define void @test9() { ; CHECK-LABEL: Determining loop execution counts for: @test9 -; CHECK: Loop %loop: Unpredictable max backedge-taken count. +; CHECK: Loop %loop: Unpredictable constant max backedge-taken count. ; This is an infinite loop, make sure that it recognized as such. diff --git a/llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll b/llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll --- a/llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll +++ b/llvm/test/Analysis/ScalarEvolution/shift-recurrences.ll @@ -10,7 +10,8 @@ ; CHECK-NEXT: --> (%iv.lshr /u 2) U: [0,512) S: [0,512) Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_lshr ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -33,7 +34,8 @@ ; CHECK-NEXT: --> (%iv.lshr /u 16) U: [0,64) S: [0,64) Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_lshr2 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -56,7 +58,8 @@ ; CHECK-NEXT: --> %iv.ashr.next U: [0,512) S: [0,512) Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_ashr_zeros ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -78,7 +81,8 @@ ; CHECK-NEXT: --> %iv.ashr.next U: [-512,0) S: [-512,0) Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_ashr_ones ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -101,7 +105,8 @@ ; CHECK-NEXT: --> %iv.ashr.next U: [-512,0) S: [-512,0) Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_ashr_ones2 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -125,7 +130,8 @@ ; CHECK-NEXT: --> %iv.ashr.next U: [-4611686018427387904,4611686018427387904) S: [-4611686018427387904,4611686018427387904) Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_ashr_unknown ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -149,7 +155,8 @@ ; CHECK-NEXT: --> %iv.ashr.next U: [-2,2) S: [-2,2) Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_ashr_wrong_op ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -172,7 +179,8 @@ ; CHECK-NEXT: --> (2 * %iv.shl) U: [0,-15) S: [-9223372036854775808,9223372036854775793) Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_shl ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -199,7 +207,8 @@ ; CHECK-NEXT: --> (2 * %iv.shl) U: [8,129) S: [8,129) Exits: 128 LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_shl2 ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 @@ -233,7 +242,8 @@ ; CHECK-NEXT: --> %iv.shl.next U: [0,-3) S: [-9223372036854775808,9223372036854775805) Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_shl3 ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 @@ -266,7 +276,8 @@ ; CHECK-NEXT: --> (2 * %iv.shl) U: [8,-9223372036854775807) S: [-9223372036854775808,9223372036854775801) Exits: -9223372036854775808 LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_shl4 ; CHECK-NEXT: Loop %loop: backedge-taken count is 60 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 60 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 60 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 60 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 60 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 61 @@ -298,7 +309,8 @@ ; CHECK-NEXT: --> (2 * %iv.shl) U: [0,-7) S: [-9223372036854775808,9223372036854775801) Exits: 0 LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_shl5 ; CHECK-NEXT: Loop %loop: backedge-taken count is 61 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 61 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 61 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 61 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 61 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 62 @@ -332,7 +344,8 @@ ; CHECK-NEXT: --> %iv.shl.next U: [0,-3) S: [-9223372036854775808,9223372036854775805) Exits: 16 LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_shl6 ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 @@ -365,7 +378,8 @@ ; CHECK-NEXT: --> %iv.shl.next U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_shl7 ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 @@ -418,7 +432,8 @@ ; CHECK-NEXT: --> poison U: full-set S: full-set ; CHECK-NEXT: Determining loop execution counts for: @unreachable_binop ; CHECK-NEXT: Loop %header: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %header: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %header: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %header: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %header: Unpredictable predicated backedge-taken count. ; entry: @@ -475,7 +490,8 @@ ; CHECK-NEXT: --> (1 + %tmp) U: [1,-2147483647) S: [1,-2147483647) Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @nonloop_recurrence_2 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; bb: @@ -509,7 +525,8 @@ ; CHECK-NEXT: --> %iv.ashr.next U: [0,512) S: [0,512) Exits: 31 LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_ashr_tc_positive ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 @@ -540,7 +557,8 @@ ; CHECK-NEXT: --> %iv.ashr.next U: [-64,0) S: [-64,0) Exits: -4 LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_ashr_tc_negative ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 @@ -573,7 +591,8 @@ ; CHECK-NEXT: --> %iv.ashr.next U: [-16,16) S: [-16,16) Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_ashr_tc_either ; CHECK-NEXT: Loop %loop: backedge-taken count is 60 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 60 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 60 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 60 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 60 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 61 @@ -605,7 +624,8 @@ ; CHECK-NEXT: --> %iv.ashr U: [1023,1024) S: [1023,1024) Exits: 1023 LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_ashr_zero_shift ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 @@ -636,7 +656,8 @@ ; CHECK-NEXT: --> (%iv.lshr /u 2) U: [31,512) S: [31,512) Exits: 31 LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_lshr_tc_positive ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 @@ -667,7 +688,8 @@ ; CHECK-NEXT: --> (%iv.lshr /u 2) U: [7,-128) S: [7,-128) Exits: 7 LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_lshr_tc_negative ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 @@ -700,7 +722,8 @@ ; CHECK-NEXT: --> (%iv.lshr /u 2) U: [0,-128) S: [0,-128) Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_lshr_tc_either ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 @@ -732,7 +755,8 @@ ; CHECK-NEXT: --> %iv.lshr U: [1023,1024) S: [1023,1024) Exits: 1023 LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_lshr_zero_shift ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 @@ -764,7 +788,8 @@ ; CHECK-NEXT: --> (%iv.lshr /u 4) U: [1,257) S: [1,257) Exits: 1 LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_lshr_power_of_2_start ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 @@ -796,7 +821,8 @@ ; CHECK-NEXT: --> (%iv.lshr /u 4) U: [0,240) S: [0,240) Exits: 0 LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_lshr_arbitrary_start ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 @@ -827,7 +853,8 @@ ; CHECK-NEXT: --> (%iv.lshr /u 4) U: [1,257) S: [1,257) Exits: 1 LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @test_lshr_start_power_of_2_plus_one ; CHECK-NEXT: Loop %loop: backedge-taken count is 4 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 5 diff --git a/llvm/test/Analysis/ScalarEvolution/sle.ll b/llvm/test/Analysis/ScalarEvolution/sle.ll --- a/llvm/test/Analysis/ScalarEvolution/sle.ll +++ b/llvm/test/Analysis/ScalarEvolution/sle.ll @@ -5,7 +5,7 @@ ; CHECK: @le ; CHECK: Loop %for.body: backedge-taken count is %n -; CHECK: Loop %for.body: max backedge-taken count is 9223372036854775807 +; CHECK: Loop %for.body: constant max backedge-taken count is 9223372036854775807 define void @le(i64 %n, double* nocapture %p) nounwind { entry: diff --git a/llvm/test/Analysis/ScalarEvolution/smin-smax-folds.ll b/llvm/test/Analysis/ScalarEvolution/smin-smax-folds.ll --- a/llvm/test/Analysis/ScalarEvolution/smin-smax-folds.ll +++ b/llvm/test/Analysis/ScalarEvolution/smin-smax-folds.ll @@ -6,9 +6,13 @@ ; Test case from PR1614. define i32 @test_PR1614(i32 %a, i32 %b, i32 %c) { ; CHECK-LABEL: 'test_PR1614' -; CHECK: --> (%a smax %b) -; CHECK: --> (%a smax %b smax %c) -; CHECK-NOT: smax +; CHECK-NEXT: Classifying expressions for: @test_PR1614 +; CHECK-NEXT: %B = select i1 %A, i32 %a, i32 %b +; CHECK-NEXT: --> (%a smax %b) U: full-set S: full-set +; CHECK-NEXT: %D = select i1 %C, i32 %B, i32 %c +; CHECK-NEXT: --> (%a smax %b smax %c) U: full-set S: full-set +; CHECK-NEXT: Determining loop execution counts for: @test_PR1614 +; %A = icmp sgt i32 %a, %b %B = select i1 %A, i32 %a, i32 %b @@ -30,7 +34,8 @@ ; CHECK-NEXT: --> {(-1 + %n),+,-1}<%for.body> U: full-set S: full-set Exits: -1 LoopDispositions: { %for.body: Computable } ; CHECK-NEXT: Determining loop execution counts for: @smin_simplify_with_guard ; CHECK-NEXT: Loop %for.body: backedge-taken count is %n -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -58,7 +63,6 @@ define void @smin_to_smax(i32 %n) { ; FIXME: ((-1 * (0 smin %n)) + %n) is actually just (0 smax %n) - ; CHECK-LABEL: 'smin_to_smax' ; CHECK-NEXT: Classifying expressions for: @smin_to_smax ; CHECK-NEXT: %i.011 = phi i32 [ %n, %for.body.lr.ph ], [ %dec, %for.body ] @@ -67,7 +71,8 @@ ; CHECK-NEXT: --> {(-1 + %n),+,-1}<%for.body> U: full-set S: full-set Exits: (-1 + (0 smin %n)) LoopDispositions: { %for.body: Computable } ; CHECK-NEXT: Determining loop execution counts for: @smin_to_smax ; CHECK-NEXT: Loop %for.body: backedge-taken count is ((-1 * (0 smin %n)) + %n) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 2147483647 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is ((-1 * (0 smin %n)) + %n) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is ((-1 * (0 smin %n)) + %n) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -94,18 +99,20 @@ ; The information from the loop guard can be used to simplify the trip count expression. define void @smax_simplify_with_guard(i32 %start, i32 %n) { -; CHECK-LABEL: 'smax_simplify_with_guard' +; CHECK-LABEL: 'smax_simplify_with_guard' ; CHECK-NEXT: Classifying expressions for: @smax_simplify_with_guard ; CHECK-NEXT: %k.0.i26 = phi i32 [ %start, %loop.ph ], [ %inc.i, %loop ] -; CHECK-NEXT: --> {%start,+,1}<%loop> U: full-set S: full-set Exits: %n LoopDispositions: { %loop: Computable } +; CHECK-NEXT: --> {%start,+,1}<%loop> U: full-set S: full-set Exits: %n LoopDispositions: { %loop: Computable } ; CHECK-NEXT: %inc.i = add nsw i32 %k.0.i26, 1 -; CHECK-NEXT: --> {(1 + %start),+,1}<%loop> U: full-set S: full-set Exits: (1 + %n) LoopDispositions: { %loop: Computable } +; CHECK-NEXT: --> {(1 + %start),+,1}<%loop> U: full-set S: full-set Exits: (1 + %n) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @smax_simplify_with_guard ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-1 * %start) + %n) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 -; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-1 * %start) + %n) +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-1 * %start) + %n) +; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-1 * %start) + %n) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 +; entry: %guard = icmp sge i32 %n, %start br i1 %guard, label %loop.ph, label %exit diff --git a/llvm/test/Analysis/ScalarEvolution/solve-quadratic-i1.ll b/llvm/test/Analysis/ScalarEvolution/solve-quadratic-i1.ll --- a/llvm/test/Analysis/ScalarEvolution/solve-quadratic-i1.ll +++ b/llvm/test/Analysis/ScalarEvolution/solve-quadratic-i1.ll @@ -18,7 +18,8 @@ ; CHECK-NEXT: --> (zext i1 {true,+,true,+,true}<%b1> to i16) U: [0,2) S: [0,2) Exits: 0 LoopDispositions: { %b1: Computable } ; CHECK-NEXT: Determining loop execution counts for: @f0 ; CHECK-NEXT: Loop %b1: backedge-taken count is 1 -; CHECK-NEXT: Loop %b1: max backedge-taken count is 1 +; CHECK-NEXT: Loop %b1: constant max backedge-taken count is 1 +; CHECK-NEXT: Loop %b1: symbolic max backedge-taken count is 1 ; CHECK-NEXT: Loop %b1: Predicated backedge-taken count is 1 ; CHECK-NEXT: Predicates: ; CHECK: Loop %b1: Trip multiple is 2 @@ -64,10 +65,12 @@ ; CHECK-NEXT: --> {3,+,4,+,1}<%b1> U: full-set S: full-set --> 12 U: [12,13) S: [12,13) ; CHECK-NEXT: Determining loop execution counts for: @f1 ; CHECK-NEXT: Loop %b3: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %b3: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %b3: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %b3: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %b3: Unpredictable predicated backedge-taken count. ; CHECK-NEXT: Loop %b1: backedge-taken count is 2 -; CHECK-NEXT: Loop %b1: max backedge-taken count is 2 +; CHECK-NEXT: Loop %b1: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %b1: symbolic max backedge-taken count is 2 ; CHECK-NEXT: Loop %b1: Predicated backedge-taken count is 2 ; CHECK-NEXT: Predicates: ; CHECK: Loop %b1: Trip multiple is 3 diff --git a/llvm/test/Analysis/ScalarEvolution/solve-quadratic-overflow.ll b/llvm/test/Analysis/ScalarEvolution/solve-quadratic-overflow.ll --- a/llvm/test/Analysis/ScalarEvolution/solve-quadratic-overflow.ll +++ b/llvm/test/Analysis/ScalarEvolution/solve-quadratic-overflow.ll @@ -1,35 +1,35 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; RUN: opt -disable-output "-passes=print" -S < %s 2>&1 | FileCheck %s ; The exit value from this loop was originally calculated as 0. ; The actual exit condition is 256*256 == 0 (in i16). -; CHECK: Printing analysis 'Scalar Evolution Analysis' for function 'f0': -; CHECK-NEXT: Classifying expressions for: @f0 -; CHECK-NEXT: %v1 = phi i16 [ 0, %b0 ], [ %v2, %b1 ] -; CHECK-NEXT: --> {0,+,-1}<%b1> U: [-255,1) S: [-255,1) Exits: -255 LoopDispositions: { %b1: Computable } -; CHECK-NEXT: %v2 = add i16 %v1, -1 -; CHECK-NEXT: --> {-1,+,-1}<%b1> U: [-256,0) S: [-256,0) Exits: -256 LoopDispositions: { %b1: Computable } -; CHECK-NEXT: %v3 = mul i16 %v2, %v2 -; CHECK-NEXT: --> {1,+,3,+,2}<%b1> U: full-set S: full-set Exits: 0 LoopDispositions: { %b1: Computable } -; CHECK-NEXT: %v5 = phi i16 [ %v2, %b1 ] -; CHECK-NEXT: --> {-1,+,-1}<%b1> U: [-256,0) S: [-256,0) --> -256 U: [-256,-255) S: [-256,-255) -; CHECK-NEXT: %v6 = phi i16 [ %v3, %b1 ] -; CHECK-NEXT: --> {1,+,3,+,2}<%b1> U: full-set S: full-set --> 0 U: [0,1) S: [0,1) -; CHECK-NEXT: %v7 = sext i16 %v5 to i32 -; CHECK-NEXT: --> {-1,+,-1}<%b1> U: [-256,0) S: [-256,0) --> -256 U: [-256,-255) S: [-256,-255) -; CHECK-NEXT: Determining loop execution counts for: @f0 -; CHECK-NEXT: Loop %b1: backedge-taken count is 255 -; CHECK-NEXT: Loop %b1: max backedge-taken count is 255 -; CHECK-NEXT: Loop %b1: Predicated backedge-taken count is 255 -; CHECK-NEXT: Predicates: -; CHECK-EMPTY: -; CHECK-NEXT: Loop %b1: Trip multiple is 256 - - @g0 = global i32 0, align 4 @g1 = global i16 0, align 2 define signext i32 @f0() { +; CHECK-LABEL: 'f0' +; CHECK-NEXT: Classifying expressions for: @f0 +; CHECK-NEXT: %v1 = phi i16 [ 0, %b0 ], [ %v2, %b1 ] +; CHECK-NEXT: --> {0,+,-1}<%b1> U: [-255,1) S: [-255,1) Exits: -255 LoopDispositions: { %b1: Computable } +; CHECK-NEXT: %v2 = add i16 %v1, -1 +; CHECK-NEXT: --> {-1,+,-1}<%b1> U: [-256,0) S: [-256,0) Exits: -256 LoopDispositions: { %b1: Computable } +; CHECK-NEXT: %v3 = mul i16 %v2, %v2 +; CHECK-NEXT: --> {1,+,3,+,2}<%b1> U: full-set S: full-set Exits: 0 LoopDispositions: { %b1: Computable } +; CHECK-NEXT: %v5 = phi i16 [ %v2, %b1 ] +; CHECK-NEXT: --> {-1,+,-1}<%b1> U: [-256,0) S: [-256,0) --> -256 U: [-256,-255) S: [-256,-255) +; CHECK-NEXT: %v6 = phi i16 [ %v3, %b1 ] +; CHECK-NEXT: --> {1,+,3,+,2}<%b1> U: full-set S: full-set --> 0 U: [0,1) S: [0,1) +; CHECK-NEXT: %v7 = sext i16 %v5 to i32 +; CHECK-NEXT: --> {-1,+,-1}<%b1> U: [-256,0) S: [-256,0) --> -256 U: [-256,-255) S: [-256,-255) +; CHECK-NEXT: Determining loop execution counts for: @f0 +; CHECK-NEXT: Loop %b1: backedge-taken count is 255 +; CHECK-NEXT: Loop %b1: constant max backedge-taken count is 255 +; CHECK-NEXT: Loop %b1: symbolic max backedge-taken count is 255 +; CHECK-NEXT: Loop %b1: Predicated backedge-taken count is 255 +; CHECK-NEXT: Predicates: +; CHECK: Loop %b1: Trip multiple is 256 +; b0: br label %b1 diff --git a/llvm/test/Analysis/ScalarEvolution/srem.ll b/llvm/test/Analysis/ScalarEvolution/srem.ll --- a/llvm/test/Analysis/ScalarEvolution/srem.ll +++ b/llvm/test/Analysis/ScalarEvolution/srem.ll @@ -31,7 +31,8 @@ ; CHECK-NEXT: --> {1,+,1}<%for.cond> U: [1,0) S: [1,0) Exits: (1 + %width) LoopDispositions: { %for.cond: Computable } ; CHECK-NEXT: Determining loop execution counts for: @_Z4loopi ; CHECK-NEXT: Loop %for.cond: backedge-taken count is %width -; CHECK-NEXT: Loop %for.cond: max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.cond: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.cond: symbolic max backedge-taken count is %width ; CHECK-NEXT: Loop %for.cond: Predicated backedge-taken count is %width ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.cond: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/symbolic_max_exit_count.ll b/llvm/test/Analysis/ScalarEvolution/symbolic_max_exit_count.ll new file mode 100644 --- /dev/null +++ b/llvm/test/Analysis/ScalarEvolution/symbolic_max_exit_count.ll @@ -0,0 +1,321 @@ +; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py +; RUN: opt -disable-output "-passes=print" < %s 2>&1 | FileCheck %s + +declare i1 @cond() + +define i32 @test_simple_case(i32 %start, i32 %len) { +; CHECK-LABEL: 'test_simple_case' +; CHECK-NEXT: Classifying expressions for: @test_simple_case +; CHECK-NEXT: %iv = phi i32 [ %start, %entry ], [ %iv.next, %backedge ] +; CHECK-NEXT: --> {%start,+,-1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %iv.minus.1 = add i32 %iv, -1 +; CHECK-NEXT: --> {(-1 + %start),+,-1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %iv.next = add i32 %iv, -1 +; CHECK-NEXT: --> {(-1 + %start),+,-1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %loop_cond = call i1 @cond() +; CHECK-NEXT: --> %loop_cond U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: Determining loop execution counts for: @test_simple_case +; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. +; CHECK-NEXT: exit count for loop: %start +; CHECK-NEXT: exit count for range_check_block: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: exit count for backedge: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %start +; CHECK-NEXT: symbolic max exit count for loop: %start +; CHECK-NEXT: symbolic max exit count for range_check_block: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for backedge: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. +; +entry: + br label %loop + +loop: + %iv = phi i32 [%start, %entry], [%iv.next, %backedge] + %zero_check = icmp ne i32 %iv, 0 + br i1 %zero_check, label %range_check_block, label %failed_1 + +range_check_block: + %iv.minus.1 = add i32 %iv, -1 + %range_check = icmp ult i32 %iv.minus.1, %len + br i1 %range_check, label %backedge, label %failed_2 + +backedge: + %iv.next = add i32 %iv, -1 + %loop_cond = call i1 @cond() + br i1 %loop_cond, label %done, label %loop + +done: + ret i32 %iv + +failed_1: + ret i32 -1 + +failed_2: + ret i32 -2 +} + +; TODO: Symbolic max can be %start +define i32 @test_litter_conditions(i32 %start, i32 %len) { +; CHECK-LABEL: 'test_litter_conditions' +; CHECK-NEXT: Classifying expressions for: @test_litter_conditions +; CHECK-NEXT: %iv = phi i32 [ %start, %entry ], [ %iv.next, %backedge ] +; CHECK-NEXT: --> {%start,+,-1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %fake_1 = call i1 @cond() +; CHECK-NEXT: --> %fake_1 U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: %and_1 = and i1 %zero_check, %fake_1 +; CHECK-NEXT: --> (%zero_check umin %fake_1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: %iv.minus.1 = add i32 %iv, -1 +; CHECK-NEXT: --> {(-1 + %start),+,-1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %fake_2 = call i1 @cond() +; CHECK-NEXT: --> %fake_2 U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: %and_2 = and i1 %range_check, %fake_2 +; CHECK-NEXT: --> (%range_check umin %fake_2) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: %iv.next = add i32 %iv, -1 +; CHECK-NEXT: --> {(-1 + %start),+,-1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %loop_cond = call i1 @cond() +; CHECK-NEXT: --> %loop_cond U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: Determining loop execution counts for: @test_litter_conditions +; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. +; CHECK-NEXT: exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: exit count for range_check_block: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: exit count for backedge: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: symbolic max exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for range_check_block: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for backedge: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. +; +entry: + br label %loop + +loop: + %iv = phi i32 [%start, %entry], [%iv.next, %backedge] + %zero_check = icmp ne i32 %iv, 0 + %fake_1 = call i1 @cond() + %and_1 = and i1 %zero_check, %fake_1 + br i1 %and_1, label %range_check_block, label %failed_1 + +range_check_block: + %iv.minus.1 = add i32 %iv, -1 + %range_check = icmp ult i32 %iv.minus.1, %len + %fake_2 = call i1 @cond() + %and_2 = and i1 %range_check, %fake_2 + br i1 %and_2, label %backedge, label %failed_2 + +backedge: + %iv.next = add i32 %iv, -1 + %loop_cond = call i1 @cond() + br i1 %loop_cond, label %done, label %loop + +done: + ret i32 %iv + +failed_1: + ret i32 -1 + +failed_2: + ret i32 -2 +} + +; TODO: Symbolic max can be %start +define i32 @test_litter_conditions_bad_context(i32 %start, i32 %len) { +; CHECK-LABEL: 'test_litter_conditions_bad_context' +; CHECK-NEXT: Classifying expressions for: @test_litter_conditions_bad_context +; CHECK-NEXT: %iv = phi i32 [ %start, %entry ], [ %iv.next, %backedge ] +; CHECK-NEXT: --> {%start,+,-1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %fake_1 = call i1 @cond() +; CHECK-NEXT: --> %fake_1 U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: %and_1 = and i1 %zero_check, %fake_1 +; CHECK-NEXT: --> (%zero_check umin %fake_1) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: %iv.minus.1 = add i32 %iv, -1 +; CHECK-NEXT: --> {(-1 + %start),+,-1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %fake_2 = call i1 @cond() +; CHECK-NEXT: --> %fake_2 U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: %and_2 = and i1 %range_check, %fake_2 +; CHECK-NEXT: --> (%range_check umin %fake_2) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: %iv.next = add i32 %iv, -1 +; CHECK-NEXT: --> {(-1 + %start),+,-1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %loop_cond = call i1 @cond() +; CHECK-NEXT: --> %loop_cond U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: Determining loop execution counts for: @test_litter_conditions_bad_context +; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. +; CHECK-NEXT: exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: exit count for range_check_block: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: exit count for backedge: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: symbolic max exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for range_check_block: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for backedge: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. +; +entry: + br label %loop + +loop: + %iv = phi i32 [%start, %entry], [%iv.next, %backedge] + %zero_check = icmp ne i32 %iv, 0 + %fake_1 = call i1 @cond() + %and_1 = and i1 %zero_check, %fake_1 + %iv.minus.1 = add i32 %iv, -1 + %range_check = icmp ult i32 %iv.minus.1, %len + %fake_2 = call i1 @cond() + %and_2 = and i1 %range_check, %fake_2 + br i1 %and_1, label %range_check_block, label %failed_1 + +range_check_block: + br i1 %and_2, label %backedge, label %failed_2 + +backedge: + %iv.next = add i32 %iv, -1 + %loop_cond = call i1 @cond() + br i1 %loop_cond, label %done, label %loop + +done: + ret i32 %iv + +failed_1: + ret i32 -1 + +failed_2: + ret i32 -2 +} + +; TODO: Symbolic max can be %start +define i32 @test_and_conditions(i32 %start, i32 %len) { +; CHECK-LABEL: 'test_and_conditions' +; CHECK-NEXT: Classifying expressions for: @test_and_conditions +; CHECK-NEXT: %iv = phi i32 [ %start, %entry ], [ %iv.next, %backedge ] +; CHECK-NEXT: --> {%start,+,-1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %iv.minus.1 = add i32 %iv, -1 +; CHECK-NEXT: --> {(-1 + %start),+,-1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %both_checks = and i1 %zero_check, %range_check +; CHECK-NEXT: --> (%range_check umin %zero_check) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: %iv.next = add i32 %iv, -1 +; CHECK-NEXT: --> {(-1 + %start),+,-1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %loop_cond = call i1 @cond() +; CHECK-NEXT: --> %loop_cond U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: Determining loop execution counts for: @test_and_conditions +; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. +; CHECK-NEXT: exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: exit count for backedge: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: symbolic max exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for backedge: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. +; +entry: + br label %loop + +loop: + %iv = phi i32 [%start, %entry], [%iv.next, %backedge] + %zero_check = icmp ne i32 %iv, 0 + %iv.minus.1 = add i32 %iv, -1 + %range_check = icmp ult i32 %iv.minus.1, %len + %both_checks = and i1 %zero_check, %range_check + br i1 %both_checks, label %backedge, label %failed + +backedge: + %iv.next = add i32 %iv, -1 + %loop_cond = call i1 @cond() + br i1 %loop_cond, label %done, label %loop + +done: + ret i32 %iv + +failed: + ret i32 -3 +} + +define i32 @test_mixup_constant_symbolic(i32 %end, i32 %len) { +; CHECK-LABEL: 'test_mixup_constant_symbolic' +; CHECK-NEXT: Classifying expressions for: @test_mixup_constant_symbolic +; CHECK-NEXT: %iv = phi i32 [ 0, %entry ], [ %iv.next, %backedge ] +; CHECK-NEXT: --> {0,+,1}<%loop> U: [0,1001) S: [0,1001) Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %iv.next = add i32 %iv, 1 +; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,1002) S: [1,1002) Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %loop_cond = call i1 @cond() +; CHECK-NEXT: --> %loop_cond U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: Determining loop execution counts for: @test_mixup_constant_symbolic +; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. +; CHECK-NEXT: exit count for loop: %end +; CHECK-NEXT: exit count for range_check_block: 1000 +; CHECK-NEXT: exit count for backedge: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 1000 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (1000 umin %end) +; CHECK-NEXT: symbolic max exit count for loop: %end +; CHECK-NEXT: symbolic max exit count for range_check_block: 1000 +; CHECK-NEXT: symbolic max exit count for backedge: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. +; +entry: + br label %loop + +loop: + %iv = phi i32 [0, %entry], [%iv.next, %backedge] + %zero_check = icmp ne i32 %iv, %end + br i1 %zero_check, label %range_check_block, label %failed_1 + +range_check_block: + %range_check = icmp ult i32 %iv, 1000 + br i1 %range_check, label %backedge, label %failed_2 + +backedge: + %iv.next = add i32 %iv, 1 + %loop_cond = call i1 @cond() + br i1 %loop_cond, label %done, label %loop + +done: + ret i32 %iv + +failed_1: + ret i32 -1 + +failed_2: + ret i32 -2 +} + +define i32 @test_mixup_constant_symbolic_merged(i32 %end, i32 %len) { +; CHECK-LABEL: 'test_mixup_constant_symbolic_merged' +; CHECK-NEXT: Classifying expressions for: @test_mixup_constant_symbolic_merged +; CHECK-NEXT: %iv = phi i32 [ 0, %entry ], [ %iv.next, %backedge ] +; CHECK-NEXT: --> {0,+,1}<%loop> U: [0,1001) S: [0,1001) Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %and = and i1 %zero_check, %range_check +; CHECK-NEXT: --> (%range_check umin %zero_check) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: %iv.next = add i32 %iv, 1 +; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,1002) S: [1,1002) Exits: <> LoopDispositions: { %loop: Computable } +; CHECK-NEXT: %loop_cond = call i1 @cond() +; CHECK-NEXT: --> %loop_cond U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } +; CHECK-NEXT: Determining loop execution counts for: @test_mixup_constant_symbolic_merged +; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. +; CHECK-NEXT: exit count for loop: (1000 umin %end) +; CHECK-NEXT: exit count for backedge: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 1000 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (1000 umin %end) +; CHECK-NEXT: symbolic max exit count for loop: (1000 umin %end) +; CHECK-NEXT: symbolic max exit count for backedge: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. +; +entry: + br label %loop + +loop: + %iv = phi i32 [0, %entry], [%iv.next, %backedge] + %zero_check = icmp ne i32 %iv, %end + %range_check = icmp ult i32 %iv, 1000 + %and = and i1 %zero_check, %range_check + br i1 %and, label %backedge, label %failed_1 + +backedge: + %iv.next = add i32 %iv, 1 + %loop_cond = call i1 @cond() + br i1 %loop_cond, label %done, label %loop + +done: + ret i32 %iv + +failed_1: + ret i32 -1 +} diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count-andor-selectform.ll b/llvm/test/Analysis/ScalarEvolution/trip-count-andor-selectform.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count-andor-selectform.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count-andor-selectform.ll @@ -8,7 +8,8 @@ ; CHECK-LABEL: 'unsimplified_and1' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_and1 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -31,7 +32,8 @@ ; CHECK-LABEL: 'unsimplified_and2' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_and2 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -54,7 +56,8 @@ ; CHECK-LABEL: 'unsimplified_and3' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_and3 ; CHECK-NEXT: Loop %loop: backedge-taken count is false -; CHECK-NEXT: Loop %loop: max backedge-taken count is false +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is false +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is false ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is false ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -77,7 +80,8 @@ ; CHECK-LABEL: 'unsimplified_and4' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_and4 ; CHECK-NEXT: Loop %loop: backedge-taken count is false -; CHECK-NEXT: Loop %loop: max backedge-taken count is false +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is false +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is false ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is false ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -100,7 +104,8 @@ ; CHECK-LABEL: 'unsimplified_or1' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_or1 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -121,7 +126,8 @@ ; CHECK-LABEL: 'unsimplified_or2' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_or2 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -142,7 +148,8 @@ ; CHECK-LABEL: 'unsimplified_or3' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_or3 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -165,7 +172,8 @@ ; CHECK-LABEL: 'unsimplified_or4' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_or4 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -188,7 +196,8 @@ ; CHECK-LABEL: 'reversed_and1' ; CHECK-NEXT: Determining loop execution counts for: @reversed_and1 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -211,7 +220,8 @@ ; CHECK-LABEL: 'reversed_and2' ; CHECK-NEXT: Determining loop execution counts for: @reversed_and2 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -234,7 +244,8 @@ ; CHECK-LABEL: 'reversed_and3' ; CHECK-NEXT: Determining loop execution counts for: @reversed_and3 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -255,7 +266,8 @@ ; CHECK-LABEL: 'reversed_and4' ; CHECK-NEXT: Determining loop execution counts for: @reversed_and4 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -276,7 +288,8 @@ ; CHECK-LABEL: 'reversed_or1' ; CHECK-NEXT: Determining loop execution counts for: @reversed_or1 ; CHECK-NEXT: Loop %loop: backedge-taken count is false -; CHECK-NEXT: Loop %loop: max backedge-taken count is false +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is false +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is false ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is false ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -299,7 +312,8 @@ ; CHECK-LABEL: 'reversed_or2' ; CHECK-NEXT: Determining loop execution counts for: @reversed_or2 ; CHECK-NEXT: Loop %loop: backedge-taken count is false -; CHECK-NEXT: Loop %loop: max backedge-taken count is false +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is false +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is false ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is false ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -322,7 +336,8 @@ ; CHECK-LABEL: 'reversed_or3' ; CHECK-NEXT: Determining loop execution counts for: @reversed_or3 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -345,7 +360,8 @@ ; CHECK-LABEL: 'reversed_or4' ; CHECK-NEXT: Determining loop execution counts for: @reversed_or4 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count-andor.ll b/llvm/test/Analysis/ScalarEvolution/trip-count-andor.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count-andor.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count-andor.ll @@ -8,7 +8,8 @@ ; CHECK-LABEL: 'unsimplified_and1' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_and1 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -31,7 +32,8 @@ ; CHECK-LABEL: 'unsimplified_and2' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_and2 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -54,7 +56,8 @@ ; CHECK-LABEL: 'unsimplified_and3' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_and3 ; CHECK-NEXT: Loop %loop: backedge-taken count is false -; CHECK-NEXT: Loop %loop: max backedge-taken count is false +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is false +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is false ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is false ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -77,7 +80,8 @@ ; CHECK-LABEL: 'unsimplified_and4' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_and4 ; CHECK-NEXT: Loop %loop: backedge-taken count is false -; CHECK-NEXT: Loop %loop: max backedge-taken count is false +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is false +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is false ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is false ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -100,7 +104,8 @@ ; CHECK-LABEL: 'unsimplified_or1' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_or1 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -121,7 +126,8 @@ ; CHECK-LABEL: 'unsimplified_or2' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_or2 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -142,7 +148,8 @@ ; CHECK-LABEL: 'unsimplified_or3' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_or3 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -165,7 +172,8 @@ ; CHECK-LABEL: 'unsimplified_or4' ; CHECK-NEXT: Determining loop execution counts for: @unsimplified_or4 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -188,7 +196,8 @@ ; CHECK-LABEL: 'reversed_and1' ; CHECK-NEXT: Determining loop execution counts for: @reversed_and1 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -211,7 +220,8 @@ ; CHECK-LABEL: 'reversed_and2' ; CHECK-NEXT: Determining loop execution counts for: @reversed_and2 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -234,7 +244,8 @@ ; CHECK-LABEL: 'reversed_and3' ; CHECK-NEXT: Determining loop execution counts for: @reversed_and3 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -255,7 +266,8 @@ ; CHECK-LABEL: 'reversed_and4' ; CHECK-NEXT: Determining loop execution counts for: @reversed_and4 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -276,7 +288,8 @@ ; CHECK-LABEL: 'reversed_or1' ; CHECK-NEXT: Determining loop execution counts for: @reversed_or1 ; CHECK-NEXT: Loop %loop: backedge-taken count is false -; CHECK-NEXT: Loop %loop: max backedge-taken count is false +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is false +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is false ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is false ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -299,7 +312,8 @@ ; CHECK-LABEL: 'reversed_or2' ; CHECK-NEXT: Determining loop execution counts for: @reversed_or2 ; CHECK-NEXT: Loop %loop: backedge-taken count is false -; CHECK-NEXT: Loop %loop: max backedge-taken count is false +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is false +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is false ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is false ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -322,7 +336,8 @@ ; CHECK-LABEL: 'reversed_or3' ; CHECK-NEXT: Determining loop execution counts for: @reversed_or3 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -345,7 +360,8 @@ ; CHECK-LABEL: 'reversed_or4' ; CHECK-NEXT: Determining loop execution counts for: @reversed_or4 ; CHECK-NEXT: Loop %loop: backedge-taken count is %n -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count-implied-addrec.ll b/llvm/test/Analysis/ScalarEvolution/trip-count-implied-addrec.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count-implied-addrec.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count-implied-addrec.ll @@ -13,7 +13,8 @@ ; CHECK-LABEL: 'nw_implies_nuw' ; CHECK-NEXT: Determining loop execution counts for: @nw_implies_nuw ; CHECK-NEXT: Loop %for.body: backedge-taken count is %n -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is %n ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is %n ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -36,7 +37,8 @@ ; CHECK-LABEL: 'neg_nw_nuw' ; CHECK-NEXT: Determining loop execution counts for: @neg_nw_nuw ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -57,7 +59,8 @@ ; CHECK-LABEL: 'nw_implies_nsw' ; CHECK-NEXT: Determining loop execution counts for: @nw_implies_nsw ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (128 + (-128 smax %n)) ; CHECK-NEXT: Predicates: ; CHECK-NEXT: {-128,+,1}<%for.body> Added Flags: @@ -80,7 +83,8 @@ ; CHECK-LABEL: 'neg_nw_nsw' ; CHECK-NEXT: Determining loop execution counts for: @neg_nw_nsw ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -102,7 +106,8 @@ ; CHECK-LABEL: 'actually_infinite' ; CHECK-NEXT: Determining loop execution counts for: @actually_infinite ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 257 ; CHECK-NEXT: Predicates: ; CHECK-NEXT: {0,+,1}<%for.body> Added Flags: @@ -126,7 +131,8 @@ ; CHECK-LABEL: 'rhs_mustexit_1' ; CHECK-NEXT: Determining loop execution counts for: @rhs_mustexit_1 ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + (1 umax (-1 + (zext i8 (trunc i16 %n.raw to i8) to i16)))) ; CHECK-NEXT: Predicates: ; CHECK-NEXT: {1,+,1}<%for.body> Added Flags: @@ -152,7 +158,8 @@ ; CHECK-LABEL: 'rhs_mustexit_3' ; CHECK-NEXT: Determining loop execution counts for: @rhs_mustexit_3 ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -177,7 +184,8 @@ ; CHECK-LABEL: 'rhs_mustexit_nonzero_step' ; CHECK-NEXT: Determining loop execution counts for: @rhs_mustexit_nonzero_step ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -202,7 +210,8 @@ ; CHECK-LABEL: 'neg_maybe_zero_step' ; CHECK-NEXT: Determining loop execution counts for: @neg_maybe_zero_step ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -226,7 +235,8 @@ ; CHECK-LABEL: 'neg_rhs_wrong_range' ; CHECK-NEXT: Determining loop execution counts for: @neg_rhs_wrong_range ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is ((-1 + (2 umax (-1 + (zext i8 (trunc i16 %n.raw to i8) to i16)))) /u 2) ; CHECK-NEXT: Predicates: ; CHECK-NEXT: {2,+,2}<%for.body> Added Flags: @@ -252,7 +262,8 @@ ; CHECK-LABEL: 'neg_rhs_maybe_infinite' ; CHECK-NEXT: Determining loop execution counts for: @neg_rhs_maybe_infinite ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + (1 umax (-1 + (zext i8 (trunc i16 %n.raw to i8) to i16)))) ; CHECK-NEXT: Predicates: ; CHECK-NEXT: {1,+,1}<%for.body> Added Flags: @@ -280,7 +291,8 @@ ; CHECK-LABEL: 'rhs_narrow_range' ; CHECK-NEXT: Determining loop execution counts for: @rhs_narrow_range ; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + (1 umax (2 * (zext i7 (trunc i16 (%n.raw /u 2) to i7) to i16)))) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 253 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 253 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + (1 umax (2 * (zext i7 (trunc i16 (%n.raw /u 2) to i7) to i16)))) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + (1 umax (2 * (zext i7 (trunc i16 (%n.raw /u 2) to i7) to i16)))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -306,7 +318,8 @@ ; CHECK-LABEL: 'ugt_constant_rhs' ; CHECK-NEXT: Determining loop execution counts for: @ugt_constant_rhs ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -328,7 +341,8 @@ ; CHECK-LABEL: 'ult_constant_rhs' ; CHECK-NEXT: Determining loop execution counts for: @ult_constant_rhs ; CHECK-NEXT: Loop %for.body: backedge-taken count is (255 + (-1 * (zext i8 (1 + %start) to i16))) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 255 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 255 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (255 + (-1 * (zext i8 (1 + %start) to i16))) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (255 + (-1 * (zext i8 (1 + %start) to i16))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -352,7 +366,8 @@ ; CHECK-LABEL: 'ult_constant_rhs_stride2' ; CHECK-NEXT: Determining loop execution counts for: @ult_constant_rhs_stride2 ; CHECK-NEXT: Loop %for.body: backedge-taken count is ((1 + (-1 * (zext i8 (2 + %start) to i16)) + (254 umax (zext i8 (2 + %start) to i16))) /u 2) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 127 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 127 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is ((1 + (-1 * (zext i8 (2 + %start) to i16)) + (254 umax (zext i8 (2 + %start) to i16))) /u 2) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is ((1 + (-1 * (zext i8 (2 + %start) to i16)) + (254 umax (zext i8 (2 + %start) to i16))) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -376,7 +391,8 @@ ; CHECK-LABEL: 'ult_constant_rhs_stride2_neg' ; CHECK-NEXT: Determining loop execution counts for: @ult_constant_rhs_stride2_neg ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is ((256 + (-1 * (zext i8 (2 + %start) to i16))) /u 2) ; CHECK-NEXT: Predicates: ; CHECK-NEXT: {(2 + %start),+,2}<%for.body> Added Flags: @@ -400,7 +416,8 @@ ; CHECK-LABEL: 'ult_restricted_rhs' ; CHECK-NEXT: Determining loop execution counts for: @ult_restricted_rhs ; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + (1 umax (zext i8 (trunc i16 %n.raw to i8) to i16))) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 254 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 254 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + (1 umax (zext i8 (trunc i16 %n.raw to i8) to i16))) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + (1 umax (zext i8 (trunc i16 %n.raw to i8) to i16))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -424,7 +441,8 @@ ; CHECK-LABEL: 'ult_guarded_rhs' ; CHECK-NEXT: Determining loop execution counts for: @ult_guarded_rhs ; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + (1 umax %n)) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -2 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + (1 umax %n)) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + (1 umax %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count-negative-stride.ll b/llvm/test/Analysis/ScalarEvolution/trip-count-negative-stride.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count-negative-stride.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count-negative-stride.ll @@ -13,7 +13,8 @@ ; CHECK-LABEL: 'ult_wrap' ; CHECK-NEXT: Determining loop execution counts for: @ult_wrap ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -35,7 +36,8 @@ ; CHECK-LABEL: 'ult_infinite' ; CHECK-NEXT: Determining loop execution counts for: @ult_infinite ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -57,7 +59,8 @@ ; CHECK-LABEL: 'ult_infinite_ub' ; CHECK-NEXT: Determining loop execution counts for: @ult_infinite_ub ; CHECK-NEXT: Loop %for.body: backedge-taken count is 1 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 1 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 1 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 1 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 2 @@ -81,7 +84,8 @@ ; CHECK-LABEL: 'ult_129_not_taken' ; CHECK-NEXT: Determining loop execution counts for: @ult_129_not_taken ; CHECK-NEXT: Loop %for.body: backedge-taken count is 0 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -103,7 +107,8 @@ ; CHECK-LABEL: 'ult_129_unknown_start' ; CHECK-NEXT: Determining loop execution counts for: @ult_129_unknown_start ; CHECK-NEXT: Loop %for.body: backedge-taken count is 0 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -127,7 +132,8 @@ ; CHECK-LABEL: 'ult_not_taken' ; CHECK-NEXT: Determining loop execution counts for: @ult_not_taken ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -153,7 +159,8 @@ ; CHECK-LABEL: 'ult_ub1' ; CHECK-NEXT: Determining loop execution counts for: @ult_ub1 ; CHECK-NEXT: Loop %for.body: backedge-taken count is 2 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 2 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 2 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 2 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 3 @@ -177,7 +184,8 @@ ; CHECK-LABEL: 'ult_ub2' ; CHECK-NEXT: Determining loop execution counts for: @ult_ub2 ; CHECK-NEXT: Loop %for.body: backedge-taken count is 0 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -201,7 +209,8 @@ ; CHECK-LABEL: 'ult_129_preinc' ; CHECK-NEXT: Determining loop execution counts for: @ult_129_preinc ; CHECK-NEXT: Loop %for.body: backedge-taken count is 1 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 1 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 1 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 1 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 2 @@ -223,7 +232,8 @@ ; CHECK-LABEL: 'ult_preinc' ; CHECK-NEXT: Determining loop execution counts for: @ult_preinc ; CHECK-NEXT: Loop %for.body: backedge-taken count is 1 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 1 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 1 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 1 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 2 @@ -247,7 +257,8 @@ ; CHECK-LABEL: 'ult_129_varying_rhs' ; CHECK-NEXT: Determining loop execution counts for: @ult_129_varying_rhs ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -268,7 +279,8 @@ ; CHECK-LABEL: 'ult_symbolic_varying_rhs' ; CHECK-NEXT: Determining loop execution counts for: @ult_symbolic_varying_rhs ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -297,7 +309,8 @@ ; CHECK-LABEL: 'slt_wrap' ; CHECK-NEXT: Determining loop execution counts for: @slt_wrap ; CHECK-NEXT: Loop %for.body: backedge-taken count is 63 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 63 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 63 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 63 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 63 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 64 @@ -321,7 +334,8 @@ ; CHECK-LABEL: 'slt_infinite' ; CHECK-NEXT: Determining loop execution counts for: @slt_infinite ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -343,7 +357,8 @@ ; CHECK-LABEL: 'slt_infinite_ub' ; CHECK-NEXT: Determining loop execution counts for: @slt_infinite_ub ; CHECK-NEXT: Loop %for.body: backedge-taken count is 0 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -367,7 +382,8 @@ ; CHECK-LABEL: 'slt_129_not_taken' ; CHECK-NEXT: Determining loop execution counts for: @slt_129_not_taken ; CHECK-NEXT: Loop %for.body: backedge-taken count is 0 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -390,7 +406,8 @@ ; CHECK-LABEL: 'slt_not_taken' ; CHECK-NEXT: Determining loop execution counts for: @slt_not_taken ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -412,7 +429,8 @@ ; CHECK-LABEL: 'slt_129_unknown_start' ; CHECK-NEXT: Determining loop execution counts for: @slt_129_unknown_start ; CHECK-NEXT: Loop %for.body: backedge-taken count is (((127 + (-1 * (1 umin (127 + (-1 * %start) + (0 smax (-127 + %start))))) + (-1 * %start) + (0 smax (-127 + %start))) /u -127) + (1 umin (127 + (-1 * %start) + (0 smax (-127 + %start))))) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 2 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (((127 + (-1 * (1 umin (127 + (-1 * %start) + (0 smax (-127 + %start))))) + (-1 * %start) + (0 smax (-127 + %start))) /u -127) + (1 umin (127 + (-1 * %start) + (0 smax (-127 + %start))))) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (((127 + (-1 * (1 umin (127 + (-1 * %start) + (0 smax (-127 + %start))))) + (-1 * %start) + (0 smax (-127 + %start))) /u -127) + (1 umin (127 + (-1 * %start) + (0 smax (-127 + %start))))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -437,7 +455,8 @@ ; CHECK-LABEL: 'slt_ub1' ; CHECK-NEXT: Determining loop execution counts for: @slt_ub1 ; CHECK-NEXT: Loop %for.body: backedge-taken count is false -; CHECK-NEXT: Loop %for.body: max backedge-taken count is false +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is false +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is false ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is false ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -461,7 +480,8 @@ ; CHECK-LABEL: 'slt_ub2' ; CHECK-NEXT: Determining loop execution counts for: @slt_ub2 ; CHECK-NEXT: Loop %for.body: backedge-taken count is false -; CHECK-NEXT: Loop %for.body: max backedge-taken count is false +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is false +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is false ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is false ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 @@ -485,7 +505,8 @@ ; CHECK-LABEL: 'slt_129_preinc' ; CHECK-NEXT: Determining loop execution counts for: @slt_129_preinc ; CHECK-NEXT: Loop %for.body: backedge-taken count is 1 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 1 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 1 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 1 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 2 @@ -507,7 +528,8 @@ ; CHECK-LABEL: 'slt_preinc' ; CHECK-NEXT: Determining loop execution counts for: @slt_preinc ; CHECK-NEXT: Loop %for.body: backedge-taken count is 1 -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 1 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is 1 ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is 1 ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 2 @@ -531,7 +553,8 @@ ; CHECK-LABEL: 'slt_129_varying_rhs' ; CHECK-NEXT: Determining loop execution counts for: @slt_129_varying_rhs ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -552,7 +575,8 @@ ; CHECK-LABEL: 'slt_symbolic_varying_rhs' ; CHECK-NEXT: Determining loop execution counts for: @slt_symbolic_varying_rhs ; CHECK-NEXT: Loop %for.body: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body: Unpredictable predicated backedge-taken count. ; entry: @@ -578,12 +602,14 @@ ; CHECK-LABEL: 'step_is_neg_addrec_slt_8' ; CHECK-NEXT: Determining loop execution counts for: @step_is_neg_addrec_slt_8 ; CHECK-NEXT: Loop %inner: backedge-taken count is (7 /u {0,+,-1}<%outer.header>) -; CHECK-NEXT: Loop %inner: max backedge-taken count is -2147483640 +; CHECK-NEXT: Loop %inner: constant max backedge-taken count is -2147483640 +; CHECK-NEXT: Loop %inner: symbolic max backedge-taken count is (7 /u {0,+,-1}<%outer.header>) ; CHECK-NEXT: Loop %inner: Predicated backedge-taken count is (7 /u {0,+,-1}<%outer.header>) ; CHECK-NEXT: Predicates: ; CHECK: Loop %inner: Trip multiple is 1 ; CHECK-NEXT: Loop %outer.header: backedge-taken count is 0 -; CHECK-NEXT: Loop %outer.header: max backedge-taken count is 0 +; CHECK-NEXT: Loop %outer.header: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %outer.header: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %outer.header: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %outer.header: Trip multiple is 1 @@ -618,12 +644,14 @@ ; CHECK-LABEL: 'step_is_neg_addrec_slt_var' ; CHECK-NEXT: Determining loop execution counts for: @step_is_neg_addrec_slt_var ; CHECK-NEXT: Loop %inner: backedge-taken count is ((((-1 * (1 umin ({0,+,1}<%outer.header> + ({0,+,-1}<%outer.header> smax %n)))) + {0,+,1}<%outer.header> + ({0,+,-1}<%outer.header> smax %n)) /u (1 umax {0,+,-1}<%outer.header>)) + (1 umin ({0,+,1}<%outer.header> + ({0,+,-1}<%outer.header> smax %n)))) -; CHECK-NEXT: Loop %inner: max backedge-taken count is -1 +; CHECK-NEXT: Loop %inner: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %inner: symbolic max backedge-taken count is ((((-1 * (1 umin ({0,+,1}<%outer.header> + ({0,+,-1}<%outer.header> smax %n)))) + {0,+,1}<%outer.header> + ({0,+,-1}<%outer.header> smax %n)) /u (1 umax {0,+,-1}<%outer.header>)) + (1 umin ({0,+,1}<%outer.header> + ({0,+,-1}<%outer.header> smax %n)))) ; CHECK-NEXT: Loop %inner: Predicated backedge-taken count is ((((-1 * (1 umin ({0,+,1}<%outer.header> + ({0,+,-1}<%outer.header> smax %n)))) + {0,+,1}<%outer.header> + ({0,+,-1}<%outer.header> smax %n)) /u (1 umax {0,+,-1}<%outer.header>)) + (1 umin ({0,+,1}<%outer.header> + ({0,+,-1}<%outer.header> smax %n)))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %inner: Trip multiple is 1 ; CHECK-NEXT: Loop %outer.header: backedge-taken count is 0 -; CHECK-NEXT: Loop %outer.header: max backedge-taken count is 0 +; CHECK-NEXT: Loop %outer.header: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %outer.header: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %outer.header: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %outer.header: Trip multiple is 1 @@ -658,12 +686,14 @@ ; CHECK-LABEL: 'step_is_neg_addrec_unknown_start' ; CHECK-NEXT: Determining loop execution counts for: @step_is_neg_addrec_unknown_start ; CHECK-NEXT: Loop %inner: backedge-taken count is ((((-1 * (1 umin ({(-1 * %n),+,1}<%outer.header> + (8 smax {%n,+,-1}<%outer.header>)))) + {(-1 * %n),+,1}<%outer.header> + (8 smax {%n,+,-1}<%outer.header>)) /u (1 umax {0,+,-1}<%outer.header>)) + (1 umin ({(-1 * %n),+,1}<%outer.header> + (8 smax {%n,+,-1}<%outer.header>)))) -; CHECK-NEXT: Loop %inner: max backedge-taken count is -2147483640 +; CHECK-NEXT: Loop %inner: constant max backedge-taken count is -2147483640 +; CHECK-NEXT: Loop %inner: symbolic max backedge-taken count is ((((-1 * (1 umin ({(-1 * %n),+,1}<%outer.header> + (8 smax {%n,+,-1}<%outer.header>)))) + {(-1 * %n),+,1}<%outer.header> + (8 smax {%n,+,-1}<%outer.header>)) /u (1 umax {0,+,-1}<%outer.header>)) + (1 umin ({(-1 * %n),+,1}<%outer.header> + (8 smax {%n,+,-1}<%outer.header>)))) ; CHECK-NEXT: Loop %inner: Predicated backedge-taken count is ((((-1 * (1 umin ({(-1 * %n),+,1}<%outer.header> + (8 smax {%n,+,-1}<%outer.header>)))) + {(-1 * %n),+,1}<%outer.header> + (8 smax {%n,+,-1}<%outer.header>)) /u (1 umax {0,+,-1}<%outer.header>)) + (1 umin ({(-1 * %n),+,1}<%outer.header> + (8 smax {%n,+,-1}<%outer.header>)))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %inner: Trip multiple is 1 ; CHECK-NEXT: Loop %outer.header: backedge-taken count is 0 -; CHECK-NEXT: Loop %outer.header: max backedge-taken count is 0 +; CHECK-NEXT: Loop %outer.header: constant max backedge-taken count is 0 +; CHECK-NEXT: Loop %outer.header: symbolic max backedge-taken count is 0 ; CHECK-NEXT: Loop %outer.header: Predicated backedge-taken count is 0 ; CHECK-NEXT: Predicates: ; CHECK: Loop %outer.header: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count-non-unit-stride.ll b/llvm/test/Analysis/ScalarEvolution/trip-count-non-unit-stride.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count-non-unit-stride.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count-non-unit-stride.ll @@ -15,7 +15,10 @@ ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for latch: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: symbolic max exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for latch: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; start: @@ -48,7 +51,10 @@ ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for latch: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: symbolic max exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for latch: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; start: @@ -80,7 +86,10 @@ ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for latch: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: symbolic max exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for latch: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; start: @@ -113,7 +122,10 @@ ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for latch: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: symbolic max exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for latch: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; start: @@ -145,7 +157,10 @@ ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for latch: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: symbolic max exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for latch: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; start: @@ -178,7 +193,10 @@ ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for loop: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for latch: ***COULDNOTCOMPUTE*** -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. +; CHECK-NEXT: symbolic max exit count for loop: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for latch: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; start: diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count-pow2.ll b/llvm/test/Analysis/ScalarEvolution/trip-count-pow2.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count-pow2.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count-pow2.ll @@ -14,7 +14,7 @@ ; CHECK-LABEL: @test1 ; CHECK: Loop %loop: backedge-taken count is ((-32 + (96 * %n)) /u 32) -; CHECK: Loop %loop: max backedge-taken count is 134217727 +; CHECK: Loop %loop: constant max backedge-taken count is 134217727 } ; PR19183 @@ -32,7 +32,7 @@ ; CHECK-LABEL: @test2 ; CHECK: Loop %loop: backedge-taken count is ((-32 + (32 * (%n /u 32))) /u 32) -; CHECK: Loop %loop: max backedge-taken count is 134217727 +; CHECK: Loop %loop: constant max backedge-taken count is 134217727 } define void @test3(i32 %n) { @@ -49,7 +49,7 @@ ; CHECK-LABEL: @test3 ; CHECK: Loop %loop: backedge-taken count is ((-32 + (32 * %n)) /u 32) -; CHECK: Loop %loop: max backedge-taken count is 134217727 +; CHECK: Loop %loop: constant max backedge-taken count is 134217727 } define void @test4(i32 %n) { @@ -66,7 +66,7 @@ ; CHECK-LABEL: @test4 ; CHECK: Loop %loop: backedge-taken count is ((-4 + (-1431655764 * %n)) /u 4) -; CHECK: Loop %loop: max backedge-taken count is 1073741823 +; CHECK: Loop %loop: constant max backedge-taken count is 1073741823 } define void @test5(i32 %n) { @@ -83,5 +83,5 @@ ; CHECK-LABEL: @test5 ; CHECK: Loop %loop: backedge-taken count is ((-4 + (4 * %n)) /u 4) -; CHECK: Loop %loop: max backedge-taken count is 1073741823 +; CHECK: Loop %loop: constant max backedge-taken count is 1073741823 } diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count-switch.ll b/llvm/test/Analysis/ScalarEvolution/trip-count-switch.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count-switch.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count-switch.ll @@ -26,5 +26,5 @@ ; CHECK-LABEL: @test1 ; CHECK: Loop %for.cond: backedge-taken count is 2 -; CHECK: Loop %for.cond: max backedge-taken count is 2 +; CHECK: Loop %for.cond: constant max backedge-taken count is 2 } diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll b/llvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count-unknown-stride.ll @@ -8,7 +8,7 @@ ; We should have a conservative estimate for the max backedge taken count for ; loops with unknown stride. -; CHECK: max backedge-taken count is -1 +; CHECK: constant max backedge-taken count is -1 target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" @@ -38,7 +38,7 @@ ; We should have a conservative estimate for the max backedge taken count for ; loops with unknown stride. -; CHECK: max backedge-taken count is -1 +; CHECK: constant max backedge-taken count is -1 define void @foo2(i32* nocapture %A, i32 %n, i32 %s) mustprogress { entry: @@ -62,7 +62,7 @@ ; loops being UB. ; CHECK-LABEL: Determining loop execution counts for: @foo3 ; CHECK: Loop %for.body: Unpredictable backedge-taken count. -; CHECK: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK: Loop %for.body: Unpredictable constant max backedge-taken count. define void @foo3(i32* nocapture %A, i32 %n, i32 %s) { entry: @@ -85,7 +85,7 @@ ; Same as foo2, but with mustprogress on loop, not function ; CHECK: Determining loop execution counts for: @foo4 ; CHECK: backedge-taken count is ((((-1 * (1 umin ((-1 * %s) + (%n smax %s)))) + (-1 * %s) + (%n smax %s)) /u (1 umax %s)) + (1 umin ((-1 * %s) + (%n smax %s)))) -; CHECK: max backedge-taken count is -1 +; CHECK: constant max backedge-taken count is -1 define void @foo4(i32* nocapture %A, i32 %n, i32 %s) { entry: @@ -111,7 +111,7 @@ ; We should have a conservative estimate for the max backedge taken count for ; loops with unknown stride. -; CHECK: max backedge-taken count is -1 +; CHECK: constant max backedge-taken count is -1 define void @foo5(i32* nocapture %A, i32 %n, i32 %s, i32 %start) mustprogress { entry: @@ -135,7 +135,7 @@ ; for unknown but potentially zero stride. ; CHECK-LABEL: Determining loop execution counts for: @zero_stride ; CHECK: Loop %for.body: Unpredictable backedge-taken count. -; CHECK: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK: Loop %for.body: Unpredictable constant max backedge-taken count. ; CHECK: Loop %for.body: Unpredictable predicated backedge-taken count. ; Note that this function is well defined only when %n <=s 0 define void @zero_stride(i32* nocapture %A, i32 %n) { @@ -158,7 +158,7 @@ ; CHECK-LABEL: Determining loop execution counts for: @zero_stride_ub ; CHECK: Loop %for.body: Unpredictable backedge-taken count. -; CHECK: Loop %for.body: Unpredictable max backedge-taken count. +; CHECK: Loop %for.body: Unpredictable constant max backedge-taken count. ; CHECK: Loop %for.body: Unpredictable predicated backedge-taken count. ; Note that this function will always execute undefined behavior and thus ; any value is valid for a backedge taken count. @@ -183,7 +183,7 @@ ; When %zero = 0, this loop is only well defined if %n < 0 and thus BTC = 0. ; CHECK-LABEL: Determining loop execution counts for: @zero_stride_symbolic ; CHECK: Loop %for.body: backedge-taken count is ((((-1 * (1 umin ((-1 * %zero) + (%n smax %zero)))) + (-1 * %zero) + (%n smax %zero)) /u (1 umax %zero)) + (1 umin ((-1 * %zero) + (%n smax %zero)))) -; CHECK: Loop %for.body: max backedge-taken count is -1 +; CHECK: Loop %for.body: constant max backedge-taken count is -1 define void @zero_stride_symbolic(i32* nocapture %A, i32 %n, i32 %zero) { entry: @@ -206,7 +206,7 @@ ; CHECK-LABEL: Determining loop execution counts for: @zero_stride_varying_rhs ; CHECK: Loop %for.body: Unpredictable backedge-taken count. -; CHECK: Loop %for.body: Unpredictable max backedge-taken count +; CHECK: Loop %for.body: Unpredictable constant max backedge-taken count define void @zero_stride_varying_rhs(i32* nocapture %A, i32* %n_p, i32 %zero) { entry: diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count.ll b/llvm/test/Analysis/ScalarEvolution/trip-count.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count.ll @@ -10,7 +10,8 @@ ; CHECK-LABEL: 'PR1101' ; CHECK-NEXT: Determining loop execution counts for: @PR1101 ; CHECK-NEXT: Loop %bb3: backedge-taken count is 10000 -; CHECK-NEXT: Loop %bb3: max backedge-taken count is 10000 +; CHECK-NEXT: Loop %bb3: constant max backedge-taken count is 10000 +; CHECK-NEXT: Loop %bb3: symbolic max backedge-taken count is 10000 ; CHECK-NEXT: Loop %bb3: Predicated backedge-taken count is 10000 ; CHECK-NEXT: Predicates: ; CHECK: Loop %bb3: Trip multiple is 10001 @@ -40,7 +41,8 @@ ; CHECK-LABEL: 'PR22795' ; CHECK-NEXT: Determining loop execution counts for: @PR22795 ; CHECK-NEXT: Loop %preheader: backedge-taken count is 7 -; CHECK-NEXT: Loop %preheader: max backedge-taken count is 7 +; CHECK-NEXT: Loop %preheader: constant max backedge-taken count is 7 +; CHECK-NEXT: Loop %preheader: symbolic max backedge-taken count is 7 ; CHECK-NEXT: Loop %preheader: Predicated backedge-taken count is 7 ; CHECK-NEXT: Predicates: ; CHECK: Loop %preheader: Trip multiple is 8 @@ -103,7 +105,8 @@ ; CHECK-LABEL: 'pr28012' ; CHECK-NEXT: Determining loop execution counts for: @pr28012 ; CHECK-NEXT: Loop %loop: backedge-taken count is -1431655751 -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1431655751 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1431655751 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is -1431655751 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is -1431655751 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 2863311546 diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count10.ll b/llvm/test/Analysis/ScalarEvolution/trip-count10.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count10.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count10.ll @@ -7,7 +7,8 @@ ; CHECK-LABEL: 'a' ; CHECK-NEXT: Determining loop execution counts for: @a ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -27,7 +28,8 @@ ; CHECK-LABEL: 'b' ; CHECK-NEXT: Determining loop execution counts for: @b ; CHECK-NEXT: Loop %loop: backedge-taken count is false -; CHECK-NEXT: Loop %loop: max backedge-taken count is false +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is false +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is false ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is false ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -49,7 +51,8 @@ ; CHECK-LABEL: 'c' ; CHECK-NEXT: Determining loop execution counts for: @c ; CHECK-NEXT: Loop %loop: backedge-taken count is false -; CHECK-NEXT: Loop %loop: max backedge-taken count is false +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is false +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is false ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is false ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -71,7 +74,8 @@ ; CHECK-LABEL: 'd' ; CHECK-NEXT: Determining loop execution counts for: @d ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -99,7 +103,8 @@ ; CHECK-LABEL: 'nonpolynomial' ; CHECK-NEXT: Determining loop execution counts for: @nonpolynomial ; CHECK-NEXT: Loop %loophead: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loophead: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loophead: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loophead: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loophead: Unpredictable predicated backedge-taken count. ; entry: @@ -127,7 +132,8 @@ ; CHECK-LABEL: 'constant_phi_operands' ; CHECK-NEXT: Determining loop execution counts for: @constant_phi_operands ; CHECK-NEXT: Loop %loop: backedge-taken count is 1 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 1 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 1 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 2 @@ -152,7 +158,8 @@ ; CHECK-LABEL: 'exit_orcond_nsw' ; CHECK-NEXT: Determining loop execution counts for: @exit_orcond_nsw ; CHECK-NEXT: Loop %for.body.i: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %for.body.i: max backedge-taken count is 1 +; CHECK-NEXT: Loop %for.body.i: constant max backedge-taken count is 1 +; CHECK-NEXT: Loop %for.body.i: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %for.body.i: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count12.ll b/llvm/test/Analysis/ScalarEvolution/trip-count12.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count12.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count12.ll @@ -2,7 +2,7 @@ ; CHECK: Determining loop execution counts for: @test ; CHECK: Loop %for.body: backedge-taken count is ((-2 + %len) /u 2) -; CHECK: Loop %for.body: max backedge-taken count is 1073741823 +; CHECK: Loop %for.body: constant max backedge-taken count is 1073741823 define zeroext i16 @test(i16* nocapture %p, i32 %len) nounwind readonly { entry: diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count13.ll b/llvm/test/Analysis/ScalarEvolution/trip-count13.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count13.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count13.ll @@ -14,7 +14,7 @@ ; CHECK-LABEL: Determining loop execution counts for: @u_0 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-100 + (-1 * %rhs) + ((100 + %rhs) umax %rhs)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -100, actual taken count either this or zero. +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -100, actual taken count either this or zero. leave: ret void @@ -34,7 +34,7 @@ ; CHECK-LABEL: Determining loop execution counts for: @u_1 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-1 * %start) + ((-100 + %start) umax %start)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -100, actual taken count either this or zero. +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -100, actual taken count either this or zero. leave: ret void @@ -54,7 +54,7 @@ ; CHECK-LABEL: Determining loop execution counts for: @s_0 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-100 + (-1 * %rhs) + ((100 + %rhs) smax %rhs)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -100, actual taken count either this or zero. +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -100, actual taken count either this or zero. leave: ret void @@ -74,7 +74,7 @@ ; CHECK-LABEL: Determining loop execution counts for: @s_1 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-1 * %start) + ((-100 + %start) smax %start)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -100, actual taken count either this or zero. +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -100, actual taken count either this or zero. leave: ret void @@ -93,7 +93,7 @@ ; CHECK-LABEL: Determining loop execution counts for: @s_2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-1 * ((-100 + %start) smin %start)) + %start) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 leave: ret void diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count14.ll b/llvm/test/Analysis/ScalarEvolution/trip-count14.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count14.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count14.ll @@ -5,7 +5,8 @@ ; CHECK-LABEL: 's32_max1' ; CHECK-NEXT: Determining loop execution counts for: @s32_max1 ; CHECK-NEXT: Loop %do.body: backedge-taken count is ((-1 * %n) + ((1 + %n) smax %n)) -; CHECK-NEXT: Loop %do.body: max backedge-taken count is 1, actual taken count either this or zero. +; CHECK-NEXT: Loop %do.body: constant max backedge-taken count is 1, actual taken count either this or zero. +; CHECK-NEXT: Loop %do.body: symbolic max backedge-taken count is ((-1 * %n) + ((1 + %n) smax %n)), actual taken count either this or zero. ; CHECK-NEXT: Loop %do.body: Predicated backedge-taken count is ((-1 * %n) + ((1 + %n) smax %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %do.body: Trip multiple is 1 @@ -30,7 +31,8 @@ ; CHECK-LABEL: 's32_max2' ; CHECK-NEXT: Determining loop execution counts for: @s32_max2 ; CHECK-NEXT: Loop %do.body: backedge-taken count is ((-1 * %n) + ((2 + %n) smax %n)) -; CHECK-NEXT: Loop %do.body: max backedge-taken count is 2, actual taken count either this or zero. +; CHECK-NEXT: Loop %do.body: constant max backedge-taken count is 2, actual taken count either this or zero. +; CHECK-NEXT: Loop %do.body: symbolic max backedge-taken count is ((-1 * %n) + ((2 + %n) smax %n)), actual taken count either this or zero. ; CHECK-NEXT: Loop %do.body: Predicated backedge-taken count is ((-1 * %n) + ((2 + %n) smax %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %do.body: Trip multiple is 1 @@ -55,7 +57,8 @@ ; CHECK-LABEL: 's32_maxx' ; CHECK-NEXT: Determining loop execution counts for: @s32_maxx ; CHECK-NEXT: Loop %do.body: backedge-taken count is ((-1 * %n) + ((%n + %x) smax %n)) -; CHECK-NEXT: Loop %do.body: max backedge-taken count is -1 +; CHECK-NEXT: Loop %do.body: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %do.body: symbolic max backedge-taken count is ((-1 * %n) + ((%n + %x) smax %n)) ; CHECK-NEXT: Loop %do.body: Predicated backedge-taken count is ((-1 * %n) + ((%n + %x) smax %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %do.body: Trip multiple is 1 @@ -82,7 +85,10 @@ ; CHECK-NEXT: Loop %do.body: backedge-taken count is (((-1 * %n) + ((2 + %n) smax %n)) umin ((-1 * %n) + %x)) ; CHECK-NEXT: exit count for do.body: ((-1 * %n) + %x) ; CHECK-NEXT: exit count for if.end: ((-1 * %n) + ((2 + %n) smax %n)) -; CHECK-NEXT: Loop %do.body: max backedge-taken count is 2 +; CHECK-NEXT: Loop %do.body: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %do.body: symbolic max backedge-taken count is (((-1 * %n) + ((2 + %n) smax %n)) umin ((-1 * %n) + %x)) +; CHECK-NEXT: symbolic max exit count for do.body: ((-1 * %n) + %x) +; CHECK-NEXT: symbolic max exit count for if.end: ((-1 * %n) + ((2 + %n) smax %n)) ; CHECK-NEXT: Loop %do.body: Predicated backedge-taken count is (((-1 * %n) + ((2 + %n) smax %n)) umin ((-1 * %n) + %x)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %do.body: Trip multiple is 1 @@ -111,7 +117,8 @@ ; CHECK-LABEL: 'u32_max1' ; CHECK-NEXT: Determining loop execution counts for: @u32_max1 ; CHECK-NEXT: Loop %do.body: backedge-taken count is ((-1 * %n) + ((1 + %n) umax %n)) -; CHECK-NEXT: Loop %do.body: max backedge-taken count is 1, actual taken count either this or zero. +; CHECK-NEXT: Loop %do.body: constant max backedge-taken count is 1, actual taken count either this or zero. +; CHECK-NEXT: Loop %do.body: symbolic max backedge-taken count is ((-1 * %n) + ((1 + %n) umax %n)), actual taken count either this or zero. ; CHECK-NEXT: Loop %do.body: Predicated backedge-taken count is ((-1 * %n) + ((1 + %n) umax %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %do.body: Trip multiple is 1 @@ -136,7 +143,8 @@ ; CHECK-LABEL: 'u32_max2' ; CHECK-NEXT: Determining loop execution counts for: @u32_max2 ; CHECK-NEXT: Loop %do.body: backedge-taken count is ((-1 * %n) + ((2 + %n) umax %n)) -; CHECK-NEXT: Loop %do.body: max backedge-taken count is 2, actual taken count either this or zero. +; CHECK-NEXT: Loop %do.body: constant max backedge-taken count is 2, actual taken count either this or zero. +; CHECK-NEXT: Loop %do.body: symbolic max backedge-taken count is ((-1 * %n) + ((2 + %n) umax %n)), actual taken count either this or zero. ; CHECK-NEXT: Loop %do.body: Predicated backedge-taken count is ((-1 * %n) + ((2 + %n) umax %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %do.body: Trip multiple is 1 @@ -161,7 +169,8 @@ ; CHECK-LABEL: 'u32_maxx' ; CHECK-NEXT: Determining loop execution counts for: @u32_maxx ; CHECK-NEXT: Loop %do.body: backedge-taken count is ((-1 * %n) + ((%n + %x) umax %n)) -; CHECK-NEXT: Loop %do.body: max backedge-taken count is -1 +; CHECK-NEXT: Loop %do.body: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %do.body: symbolic max backedge-taken count is ((-1 * %n) + ((%n + %x) umax %n)) ; CHECK-NEXT: Loop %do.body: Predicated backedge-taken count is ((-1 * %n) + ((%n + %x) umax %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %do.body: Trip multiple is 1 @@ -188,7 +197,10 @@ ; CHECK-NEXT: Loop %do.body: backedge-taken count is (((-1 * %n) + ((2 + %n) umax %n)) umin ((-1 * %n) + %x)) ; CHECK-NEXT: exit count for do.body: ((-1 * %n) + %x) ; CHECK-NEXT: exit count for if.end: ((-1 * %n) + ((2 + %n) umax %n)) -; CHECK-NEXT: Loop %do.body: max backedge-taken count is 2 +; CHECK-NEXT: Loop %do.body: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %do.body: symbolic max backedge-taken count is (((-1 * %n) + ((2 + %n) umax %n)) umin ((-1 * %n) + %x)) +; CHECK-NEXT: symbolic max exit count for do.body: ((-1 * %n) + %x) +; CHECK-NEXT: symbolic max exit count for if.end: ((-1 * %n) + ((2 + %n) umax %n)) ; CHECK-NEXT: Loop %do.body: Predicated backedge-taken count is (((-1 * %n) + ((2 + %n) umax %n)) umin ((-1 * %n) + %x)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %do.body: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count15.ll b/llvm/test/Analysis/ScalarEvolution/trip-count15.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count15.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count15.ll @@ -12,7 +12,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,4099) S: [1,4099) Exits: (2 + (4096 umin %n)) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @umin_unsigned_check ; CHECK-NEXT: Loop %loop: backedge-taken count is (1 + (4096 umin %n)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4097 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4097 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (1 + (4096 umin %n)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (1 + (4096 umin %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -42,7 +43,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,4099) S: [1,4099) Exits: (2 + (4096 umin %n)) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @umin_signed_check ; CHECK-NEXT: Loop %loop: backedge-taken count is (1 + (4096 umin %n)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4097 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4097 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (1 + (4096 umin %n)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (1 + (4096 umin %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -72,7 +74,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,4099) S: [1,4099) Exits: (1 + (0 smax (1 + (4096 smin %n)))) LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @smin_signed_check ; CHECK-NEXT: Loop %loop: backedge-taken count is (0 smax (1 + (4096 smin %n))) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4097 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4097 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (0 smax (1 + (4096 smin %n))) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (0 smax (1 + (4096 smin %n))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -102,7 +105,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @smin_unsigned_check ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count2.ll b/llvm/test/Analysis/ScalarEvolution/trip-count2.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count2.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count2.ll @@ -7,7 +7,8 @@ ; CHECK-LABEL: 'PR1101' ; CHECK-NEXT: Determining loop execution counts for: @PR1101 ; CHECK-NEXT: Loop %bb3: backedge-taken count is 4 -; CHECK-NEXT: Loop %bb3: max backedge-taken count is 4 +; CHECK-NEXT: Loop %bb3: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %bb3: symbolic max backedge-taken count is 4 ; CHECK-NEXT: Loop %bb3: Predicated backedge-taken count is 4 ; CHECK-NEXT: Predicates: ; CHECK: Loop %bb3: Trip multiple is 5 diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count3.ll b/llvm/test/Analysis/ScalarEvolution/trip-count3.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count3.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count3.ll @@ -40,7 +40,8 @@ ; CHECK-LABEL: 'sha_stream_bb3_2E_i' ; CHECK-NEXT: Determining loop execution counts for: @sha_stream_bb3_2E_i ; CHECK-NEXT: Loop %bb3.i: backedge-taken count is ((63 + (-1 * (63 smin %0)) + %0) /u 64) -; CHECK-NEXT: Loop %bb3.i: max backedge-taken count is 33554431 +; CHECK-NEXT: Loop %bb3.i: constant max backedge-taken count is 33554431 +; CHECK-NEXT: Loop %bb3.i: symbolic max backedge-taken count is ((63 + (-1 * (63 smin %0)) + %0) /u 64) ; CHECK-NEXT: Loop %bb3.i: Predicated backedge-taken count is ((63 + (-1 * (63 smin %0)) + %0) /u 64) ; CHECK-NEXT: Predicates: ; CHECK: Loop %bb3.i: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count4.ll b/llvm/test/Analysis/ScalarEvolution/trip-count4.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count4.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count4.ll @@ -7,7 +7,8 @@ ; CHECK-LABEL: 'another_count_down_signed' ; CHECK-NEXT: Determining loop execution counts for: @another_count_down_signed ; CHECK-NEXT: Loop %loop: backedge-taken count is (-11 + %n) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-11 + %n) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-11 + %n) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count6.ll b/llvm/test/Analysis/ScalarEvolution/trip-count6.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count6.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count6.ll @@ -9,7 +9,10 @@ ; CHECK-NEXT: Loop %bb: Unpredictable backedge-taken count. ; CHECK-NEXT: exit count for bb: ***COULDNOTCOMPUTE*** ; CHECK-NEXT: exit count for bb2: 1 -; CHECK-NEXT: Loop %bb: max backedge-taken count is 1 +; CHECK-NEXT: Loop %bb: constant max backedge-taken count is 1 +; CHECK-NEXT: Loop %bb: symbolic max backedge-taken count is 1 +; CHECK-NEXT: symbolic max exit count for bb: ***COULDNOTCOMPUTE*** +; CHECK-NEXT: symbolic max exit count for bb2: 1 ; CHECK-NEXT: Loop %bb: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count7.ll b/llvm/test/Analysis/ScalarEvolution/trip-count7.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count7.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count7.ll @@ -64,7 +64,8 @@ ; CHECK-LABEL: 'Doit_bb7_2E_i' ; CHECK-NEXT: Determining loop execution counts for: @Doit_bb7_2E_i ; CHECK-NEXT: Loop %bb7.i: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %bb7.i: max backedge-taken count is 8 +; CHECK-NEXT: Loop %bb7.i: constant max backedge-taken count is 8 +; CHECK-NEXT: Loop %bb7.i: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %bb7.i: Unpredictable predicated backedge-taken count. ; newFuncRoot: diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count8.ll b/llvm/test/Analysis/ScalarEvolution/trip-count8.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count8.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count8.ll @@ -8,7 +8,8 @@ ; CHECK-LABEL: 'foo' ; CHECK-NEXT: Determining loop execution counts for: @foo ; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + %ecx) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -2 +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + %ecx) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + %ecx) ; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count9.ll b/llvm/test/Analysis/ScalarEvolution/trip-count9.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-count9.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-count9.ll @@ -13,7 +13,8 @@ ; CHECK-LABEL: 'foo' ; CHECK-NEXT: Determining loop execution counts for: @foo ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %n) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %n) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %n) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -34,7 +35,8 @@ ; CHECK-LABEL: 'step2' ; CHECK-NEXT: Determining loop execution counts for: @step2 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -53,7 +55,8 @@ ; CHECK-LABEL: 'start1' ; CHECK-NEXT: Determining loop execution counts for: @start1 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-2 + (2 smax %n)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 5 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 5 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-2 + (2 smax %n)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-2 + (2 smax %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -74,7 +77,8 @@ ; CHECK-LABEL: 'start1_step2' ; CHECK-NEXT: Determining loop execution counts for: @start1_step2 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -93,7 +97,8 @@ ; CHECK-LABEL: 'startx' ; CHECK-NEXT: Determining loop execution counts for: @startx ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %x) + ((1 + %x) smax %n)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %x) + ((1 + %x) smax %n)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %x) + ((1 + %x) smax %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -114,7 +119,8 @@ ; CHECK-LABEL: 'startx_step2' ; CHECK-NEXT: Determining loop execution counts for: @startx_step2 ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: Unpredictable max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable constant max backedge-taken count. +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: @@ -133,7 +139,8 @@ ; CHECK-LABEL: 'nsw' ; CHECK-NEXT: Determining loop execution counts for: @nsw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + %n) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 6 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + %n) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + %n) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -162,7 +169,8 @@ ; CHECK-LABEL: 'nsw_step2' ; CHECK-NEXT: Determining loop execution counts for: @nsw_step2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-1 + %n) /u 2) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-1 + %n) /u 2) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-1 + %n) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -183,7 +191,8 @@ ; CHECK-LABEL: 'nsw_start1' ; CHECK-NEXT: Determining loop execution counts for: @nsw_start1 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-2 + (2 smax %n)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 5 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 5 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-2 + (2 smax %n)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-2 + (2 smax %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -204,7 +213,8 @@ ; CHECK-LABEL: 'nsw_start1_step2' ; CHECK-NEXT: Determining loop execution counts for: @nsw_start1_step2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-2 + (3 smax %n)) /u 2) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-2 + (3 smax %n)) /u 2) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-2 + (3 smax %n)) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -225,7 +235,8 @@ ; CHECK-LABEL: 'nsw_startx' ; CHECK-NEXT: Determining loop execution counts for: @nsw_startx ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %x) + ((1 + %x) smax %n)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %x) + ((1 + %x) smax %n)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %x) + ((1 + %x) smax %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -246,7 +257,8 @@ ; CHECK-LABEL: 'nsw_startx_step2' ; CHECK-NEXT: Determining loop execution counts for: @nsw_startx_step2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-1 + (-1 * %x) + ((2 + %x) smax %n)) /u 2) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 7 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 7 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-1 + (-1 * %x) + ((2 + %x) smax %n)) /u 2) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-1 + (-1 * %x) + ((2 + %x) smax %n)) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -267,7 +279,8 @@ ; CHECK-LABEL: 'even' ; CHECK-NEXT: Determining loop execution counts for: @even ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (2 * %n)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 5 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 5 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (2 * %n)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (2 * %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 2 @@ -289,7 +302,8 @@ ; CHECK-LABEL: 'even_step2' ; CHECK-NEXT: Determining loop execution counts for: @even_step2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-1 + (2 * %n)) /u 2) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-1 + (2 * %n)) /u 2) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-1 + (2 * %n)) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -311,7 +325,8 @@ ; CHECK-LABEL: 'even_start1' ; CHECK-NEXT: Determining loop execution counts for: @even_start1 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-2 + (2 * %n)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-2 + (2 * %n)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-2 + (2 * %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -333,7 +348,8 @@ ; CHECK-LABEL: 'even_start1_step2' ; CHECK-NEXT: Determining loop execution counts for: @even_start1_step2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-2 + (2 * %n)) /u 2) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-2 + (2 * %n)) /u 2) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-2 + (2 * %n)) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -355,7 +371,8 @@ ; CHECK-LABEL: 'even_startx' ; CHECK-NEXT: Determining loop execution counts for: @even_startx ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %x) + ((1 + %x) smax (2 * %n))) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %x) + ((1 + %x) smax (2 * %n))) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %x) + ((1 + %x) smax (2 * %n))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -377,7 +394,8 @@ ; CHECK-LABEL: 'even_startx_step2' ; CHECK-NEXT: Determining loop execution counts for: @even_startx_step2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-1 + (-1 * %x) + ((2 + %x) smax (2 * %n))) /u 2) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 7 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 7 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-1 + (-1 * %x) + ((2 + %x) smax (2 * %n))) /u 2) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-1 + (-1 * %x) + ((2 + %x) smax (2 * %n))) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -399,7 +417,8 @@ ; CHECK-LABEL: 'even_nsw' ; CHECK-NEXT: Determining loop execution counts for: @even_nsw ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (2 * %n)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 5 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 5 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (2 * %n)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (2 * %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 2 @@ -421,7 +440,8 @@ ; CHECK-LABEL: 'even_nsw_step2' ; CHECK-NEXT: Determining loop execution counts for: @even_nsw_step2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-1 + (2 * %n)) /u 2) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-1 + (2 * %n)) /u 2) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-1 + (2 * %n)) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -443,7 +463,8 @@ ; CHECK-LABEL: 'even_nsw_start1' ; CHECK-NEXT: Determining loop execution counts for: @even_nsw_start1 ; CHECK-NEXT: Loop %loop: backedge-taken count is (-2 + (2 * %n)) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-2 + (2 * %n)) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-2 + (2 * %n)) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -465,7 +486,8 @@ ; CHECK-LABEL: 'even_nsw_start1_step2' ; CHECK-NEXT: Determining loop execution counts for: @even_nsw_start1_step2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-2 + (2 * %n)) /u 2) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-2 + (2 * %n)) /u 2) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-2 + (2 * %n)) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -487,7 +509,8 @@ ; CHECK-LABEL: 'even_nsw_startx' ; CHECK-NEXT: Determining loop execution counts for: @even_nsw_startx ; CHECK-NEXT: Loop %loop: backedge-taken count is (-1 + (-1 * %x) + ((1 + %x) smax (2 * %n))) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -2 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-1 + (-1 * %x) + ((1 + %x) smax (2 * %n))) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (-1 + (-1 * %x) + ((1 + %x) smax (2 * %n))) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -509,7 +532,8 @@ ; CHECK-LABEL: 'even_nsw_startx_step2' ; CHECK-NEXT: Determining loop execution counts for: @even_nsw_startx_step2 ; CHECK-NEXT: Loop %loop: backedge-taken count is ((-1 + (-1 * %x) + ((2 + %x) smax (2 * %n))) /u 2) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 7 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 7 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is ((-1 + (-1 * %x) + ((2 + %x) smax (2 * %n))) /u 2) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-1 + (-1 * %x) + ((2 + %x) smax (2 * %n))) /u 2) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/trip-multiple-guard-info.ll b/llvm/test/Analysis/ScalarEvolution/trip-multiple-guard-info.ll --- a/llvm/test/Analysis/ScalarEvolution/trip-multiple-guard-info.ll +++ b/llvm/test/Analysis/ScalarEvolution/trip-multiple-guard-info.ll @@ -4,10 +4,20 @@ ; Tests for PR47904. define void @test_trip_multiple_4(i32 %num) { -; CHECK-LABEL: @test_trip_multiple_4 -; CHECK: Loop %for.body: backedge-taken count is (-1 + %num) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -2 +; CHECK-LABEL: 'test_trip_multiple_4' +; CHECK-NEXT: Classifying expressions for: @test_trip_multiple_4 +; CHECK-NEXT: %u = urem i32 %num, 4 +; CHECK-NEXT: --> (zext i2 (trunc i32 %num to i2) to i32) U: [0,4) S: [0,4) +; CHECK-NEXT: %i.010 = phi i32 [ 0, %entry ], [ %inc, %for.body ] +; CHECK-NEXT: --> {0,+,1}<%for.body> U: [0,-2147483648) S: [0,-2147483648) Exits: (-1 + %num) LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: %inc = add nuw nsw i32 %i.010, 1 +; CHECK-NEXT: --> {1,+,1}<%for.body> U: [1,-2147483648) S: [1,-2147483648) Exits: %num LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test_trip_multiple_4 +; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + %num) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + %num) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + %num) +; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 4 ; entry: @@ -30,10 +40,20 @@ define void @test_trip_multiple_4_ugt_5(i32 %num) { -; CHECK-LABEL: @test_trip_multiple_4_ugt_5 -; CHECK: Loop %for.body: backedge-taken count is (-1 + %num) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -2 +; CHECK-LABEL: 'test_trip_multiple_4_ugt_5' +; CHECK-NEXT: Classifying expressions for: @test_trip_multiple_4_ugt_5 +; CHECK-NEXT: %u = urem i32 %num, 4 +; CHECK-NEXT: --> (zext i2 (trunc i32 %num to i2) to i32) U: [0,4) S: [0,4) +; CHECK-NEXT: %i.010 = phi i32 [ 0, %entry ], [ %inc, %for.body ] +; CHECK-NEXT: --> {0,+,1}<%for.body> U: [0,-2147483648) S: [0,-2147483648) Exits: (-1 + %num) LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: %inc = add nuw nsw i32 %i.010, 1 +; CHECK-NEXT: --> {1,+,1}<%for.body> U: [1,-2147483648) S: [1,-2147483648) Exits: %num LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test_trip_multiple_4_ugt_5 +; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + %num) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + %num) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + %num) +; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 4 ; entry: @@ -56,10 +76,20 @@ define void @test_trip_multiple_4_ugt_5_order_swapped(i32 %num) { ; TODO: Trip multiple can be 4, it is missed due to the processing order of the assumes. -; CHECK-LABEL: @test_trip_multiple_4_ugt_5_order_swapped -; CHECK: Loop %for.body: backedge-taken count is (-1 + %num) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -2 +; CHECK-LABEL: 'test_trip_multiple_4_ugt_5_order_swapped' +; CHECK-NEXT: Classifying expressions for: @test_trip_multiple_4_ugt_5_order_swapped +; CHECK-NEXT: %u = urem i32 %num, 4 +; CHECK-NEXT: --> (zext i2 (trunc i32 %num to i2) to i32) U: [0,4) S: [0,4) +; CHECK-NEXT: %i.010 = phi i32 [ 0, %entry ], [ %inc, %for.body ] +; CHECK-NEXT: --> {0,+,1}<%for.body> U: [0,-2147483648) S: [0,-2147483648) Exits: (-1 + %num) LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: %inc = add nuw nsw i32 %i.010, 1 +; CHECK-NEXT: --> {1,+,1}<%for.body> U: [1,-2147483648) S: [1,-2147483648) Exits: %num LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test_trip_multiple_4_ugt_5_order_swapped +; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + %num) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + %num) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + %num) +; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 2 ; entry: @@ -81,10 +111,20 @@ } define void @test_trip_multiple_4_sgt_5(i32 %num) { -; CHECK-LABEL: @test_trip_multiple_4_sgt_5 -; CHECK: Loop %for.body: backedge-taken count is (-1 + %num) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 2147483646 +; CHECK-LABEL: 'test_trip_multiple_4_sgt_5' +; CHECK-NEXT: Classifying expressions for: @test_trip_multiple_4_sgt_5 +; CHECK-NEXT: %u = urem i32 %num, 4 +; CHECK-NEXT: --> (zext i2 (trunc i32 %num to i2) to i32) U: [0,4) S: [0,4) +; CHECK-NEXT: %i.010 = phi i32 [ 0, %entry ], [ %inc, %for.body ] +; CHECK-NEXT: --> {0,+,1}<%for.body> U: [0,2147483647) S: [0,2147483647) Exits: (-1 + %num) LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: %inc = add nuw nsw i32 %i.010, 1 +; CHECK-NEXT: --> {1,+,1}<%for.body> U: [1,-2147483648) S: [1,-2147483648) Exits: %num LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test_trip_multiple_4_sgt_5 +; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + %num) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 2147483646 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + %num) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + %num) +; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 4 ; entry: @@ -107,10 +147,20 @@ define void @test_trip_multiple_4_sgt_5_order_swapped(i32 %num) { ; TODO: Trip multiple can be 4, it is missed due to the processing order of the assumes. -; CHECK-LABEL: @test_trip_multiple_4_sgt_5_order_swapped -; CHECK: Loop %for.body: backedge-taken count is (-1 + %num) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 2147483646 +; CHECK-LABEL: 'test_trip_multiple_4_sgt_5_order_swapped' +; CHECK-NEXT: Classifying expressions for: @test_trip_multiple_4_sgt_5_order_swapped +; CHECK-NEXT: %u = urem i32 %num, 4 +; CHECK-NEXT: --> (zext i2 (trunc i32 %num to i2) to i32) U: [0,4) S: [0,4) +; CHECK-NEXT: %i.010 = phi i32 [ 0, %entry ], [ %inc, %for.body ] +; CHECK-NEXT: --> {0,+,1}<%for.body> U: [0,2147483647) S: [0,2147483647) Exits: (-1 + %num) LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: %inc = add nuw nsw i32 %i.010, 1 +; CHECK-NEXT: --> {1,+,1}<%for.body> U: [1,-2147483648) S: [1,-2147483648) Exits: %num LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test_trip_multiple_4_sgt_5_order_swapped +; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + %num) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 2147483646 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + %num) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + %num) +; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 2 ; entry: @@ -132,10 +182,20 @@ } define void @test_trip_multiple_4_uge_5(i32 %num) { -; CHECK-LABEL: @test_trip_multiple_4_uge_5 -; CHECK: Loop %for.body: backedge-taken count is (-1 + %num) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -2 +; CHECK-LABEL: 'test_trip_multiple_4_uge_5' +; CHECK-NEXT: Classifying expressions for: @test_trip_multiple_4_uge_5 +; CHECK-NEXT: %u = urem i32 %num, 4 +; CHECK-NEXT: --> (zext i2 (trunc i32 %num to i2) to i32) U: [0,4) S: [0,4) +; CHECK-NEXT: %i.010 = phi i32 [ 0, %entry ], [ %inc, %for.body ] +; CHECK-NEXT: --> {0,+,1}<%for.body> U: [0,-2147483648) S: [0,-2147483648) Exits: (-1 + %num) LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: %inc = add nuw nsw i32 %i.010, 1 +; CHECK-NEXT: --> {1,+,1}<%for.body> U: [1,-2147483648) S: [1,-2147483648) Exits: %num LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test_trip_multiple_4_uge_5 +; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + %num) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + %num) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + %num) +; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 4 ; entry: @@ -158,10 +218,20 @@ define void @test_trip_multiple_4_uge_5_order_swapped(i32 %num) { ; TODO: Trip multiple can be 4, it is missed due to the processing order of the assumes. -; CHECK-LABEL: @test_trip_multiple_4_uge_5_order_swapped -; CHECK: Loop %for.body: backedge-taken count is (-1 + %num) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -2 +; CHECK-LABEL: 'test_trip_multiple_4_uge_5_order_swapped' +; CHECK-NEXT: Classifying expressions for: @test_trip_multiple_4_uge_5_order_swapped +; CHECK-NEXT: %u = urem i32 %num, 4 +; CHECK-NEXT: --> (zext i2 (trunc i32 %num to i2) to i32) U: [0,4) S: [0,4) +; CHECK-NEXT: %i.010 = phi i32 [ 0, %entry ], [ %inc, %for.body ] +; CHECK-NEXT: --> {0,+,1}<%for.body> U: [0,-2147483648) S: [0,-2147483648) Exits: (-1 + %num) LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: %inc = add nuw nsw i32 %i.010, 1 +; CHECK-NEXT: --> {1,+,1}<%for.body> U: [1,-2147483648) S: [1,-2147483648) Exits: %num LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test_trip_multiple_4_uge_5_order_swapped +; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + %num) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + %num) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + %num) +; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 ; entry: @@ -184,10 +254,20 @@ define void @test_trip_multiple_4_sge_5(i32 %num) { ; TODO: Trip multiple can be 4, it is missed due to the processing order of the assumes. -; CHECK-LABEL: @test_trip_multiple_4_sge_5 -; CHECK: Loop %for.body: backedge-taken count is (-1 + %num) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 2147483646 +; CHECK-LABEL: 'test_trip_multiple_4_sge_5' +; CHECK-NEXT: Classifying expressions for: @test_trip_multiple_4_sge_5 +; CHECK-NEXT: %u = urem i32 %num, 4 +; CHECK-NEXT: --> (zext i2 (trunc i32 %num to i2) to i32) U: [0,4) S: [0,4) +; CHECK-NEXT: %i.010 = phi i32 [ 0, %entry ], [ %inc, %for.body ] +; CHECK-NEXT: --> {0,+,1}<%for.body> U: [0,2147483647) S: [0,2147483647) Exits: (-1 + %num) LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: %inc = add nuw nsw i32 %i.010, 1 +; CHECK-NEXT: --> {1,+,1}<%for.body> U: [1,-2147483648) S: [1,-2147483648) Exits: %num LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test_trip_multiple_4_sge_5 +; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + %num) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 2147483646 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + %num) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + %num) +; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 4 ; entry: @@ -209,10 +289,20 @@ } define void @test_trip_multiple_4_sge_5_order_swapped(i32 %num) { -; CHECK-LABEL: @test_trip_multiple_4_sge_5_order_swapped -; CHECK: Loop %for.body: backedge-taken count is (-1 + %num) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is 2147483646 +; CHECK-LABEL: 'test_trip_multiple_4_sge_5_order_swapped' +; CHECK-NEXT: Classifying expressions for: @test_trip_multiple_4_sge_5_order_swapped +; CHECK-NEXT: %u = urem i32 %num, 4 +; CHECK-NEXT: --> (zext i2 (trunc i32 %num to i2) to i32) U: [0,4) S: [0,4) +; CHECK-NEXT: %i.010 = phi i32 [ 0, %entry ], [ %inc, %for.body ] +; CHECK-NEXT: --> {0,+,1}<%for.body> U: [0,2147483647) S: [0,2147483647) Exits: (-1 + %num) LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: %inc = add nuw nsw i32 %i.010, 1 +; CHECK-NEXT: --> {1,+,1}<%for.body> U: [1,-2147483648) S: [1,-2147483648) Exits: %num LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test_trip_multiple_4_sge_5_order_swapped +; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + %num) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is 2147483646 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + %num) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + %num) +; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 ; entry: @@ -235,10 +325,20 @@ ; Same as @test_trip_multiple_4 but with the icmp operands swapped. define void @test_trip_multiple_4_icmp_ops_swapped(i32 %num) { -; CHECK-LABEL: @test_trip_multiple_4_icmp_ops_swapped -; CHECK: Loop %for.body: backedge-taken count is (-1 + %num) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -2 +; CHECK-LABEL: 'test_trip_multiple_4_icmp_ops_swapped' +; CHECK-NEXT: Classifying expressions for: @test_trip_multiple_4_icmp_ops_swapped +; CHECK-NEXT: %u = urem i32 %num, 4 +; CHECK-NEXT: --> (zext i2 (trunc i32 %num to i2) to i32) U: [0,4) S: [0,4) +; CHECK-NEXT: %i.010 = phi i32 [ 0, %entry ], [ %inc, %for.body ] +; CHECK-NEXT: --> {0,+,1}<%for.body> U: [0,-2147483648) S: [0,-2147483648) Exits: (-1 + %num) LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: %inc = add nuw nsw i32 %i.010, 1 +; CHECK-NEXT: --> {1,+,1}<%for.body> U: [1,-2147483648) S: [1,-2147483648) Exits: %num LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test_trip_multiple_4_icmp_ops_swapped +; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + %num) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + %num) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + %num) +; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 4 ; entry: @@ -260,10 +360,20 @@ } define void @test_trip_multiple_5(i32 %num) { -; CHECK-LABEL: @test_trip_multiple_5 -; CHECK: Loop %for.body: backedge-taken count is (-1 + %num) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -2 +; CHECK-LABEL: 'test_trip_multiple_5' +; CHECK-NEXT: Classifying expressions for: @test_trip_multiple_5 +; CHECK-NEXT: %u = urem i32 %num, 5 +; CHECK-NEXT: --> ((-5 * (%num /u 5)) + %num) U: full-set S: full-set +; CHECK-NEXT: %i.010 = phi i32 [ 0, %entry ], [ %inc, %for.body ] +; CHECK-NEXT: --> {0,+,1}<%for.body> U: [0,-2147483648) S: [0,-2147483648) Exits: (-1 + %num) LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: %inc = add nuw nsw i32 %i.010, 1 +; CHECK-NEXT: --> {1,+,1}<%for.body> U: [1,-2147483648) S: [1,-2147483648) Exits: %num LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test_trip_multiple_5 +; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + %num) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -2 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + %num) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + %num) +; CHECK-NEXT: Predicates: ; CHECK: Loop %for.body: Trip multiple is 1 ; entry: @@ -285,10 +395,23 @@ } define void @test_trunc_operand_larger_than_urem_expr(i64 %N) { -; CHECK-LABEL: @test_trunc_operand_larger_than_urem_expr -; CHECK: Loop %for.body: backedge-taken count is (-1 + %N) -; CHECK-NEXT: Loop %for.body: max backedge-taken count is -1 +; CHECK-LABEL: 'test_trunc_operand_larger_than_urem_expr' +; CHECK-NEXT: Classifying expressions for: @test_trunc_operand_larger_than_urem_expr +; CHECK-NEXT: %conv = trunc i64 %N to i32 +; CHECK-NEXT: --> (trunc i64 %N to i32) U: full-set S: full-set +; CHECK-NEXT: %and = and i32 %conv, 1 +; CHECK-NEXT: --> (zext i1 (trunc i64 %N to i1) to i32) U: [0,2) S: [0,2) +; CHECK-NEXT: %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] +; CHECK-NEXT: --> {0,+,1}<%for.body> U: [0,-9223372036854775808) S: [0,-9223372036854775808) Exits: (-1 + %N) LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: %iv.next = add nuw nsw i64 %iv, 1 +; CHECK-NEXT: --> {1,+,1}<%for.body> U: [1,-9223372036854775808) S: [1,-9223372036854775808) Exits: %N LoopDispositions: { %for.body: Computable } +; CHECK-NEXT: Determining loop execution counts for: @test_trunc_operand_larger_than_urem_expr +; CHECK-NEXT: Loop %for.body: backedge-taken count is (-1 + %N) +; CHECK-NEXT: Loop %for.body: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %for.body: symbolic max backedge-taken count is (-1 + %N) ; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (-1 + %N) +; CHECK-NEXT: Predicates: +; CHECK: Loop %for.body: Trip multiple is 1 ; entry: %conv = trunc i64 %N to i32 diff --git a/llvm/test/Analysis/ScalarEvolution/umin-umax-folds.ll b/llvm/test/Analysis/ScalarEvolution/umin-umax-folds.ll --- a/llvm/test/Analysis/ScalarEvolution/umin-umax-folds.ll +++ b/llvm/test/Analysis/ScalarEvolution/umin-umax-folds.ll @@ -16,7 +16,8 @@ ; CHECK-NEXT: --> (%cmp1 umin %cmp2) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @umin_sext_x_zext_x ; CHECK-NEXT: Loop %loop: backedge-taken count is (zext i32 %len to i64) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (zext i32 %len to i64) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (zext i32 %len to i64) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -51,7 +52,8 @@ ; CHECK-NEXT: --> (zext i32 %len to i64) U: [0,4294967296) S: [0,4294967296) Exits: (zext i32 %len to i64) LoopDispositions: { %loop: Invariant } ; CHECK-NEXT: Determining loop execution counts for: @ule_sext_x_zext_x ; CHECK-NEXT: Loop %loop: backedge-taken count is (zext i32 %len to i64) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (zext i32 %len to i64) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (zext i32 %len to i64) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -86,7 +88,8 @@ ; CHECK-NEXT: --> (sext i32 %len to i64) U: [-2147483648,2147483648) S: [-2147483648,2147483648) Exits: (sext i32 %len to i64) LoopDispositions: { %loop: Invariant } ; CHECK-NEXT: Determining loop execution counts for: @uge_sext_x_zext_x ; CHECK-NEXT: Loop %loop: backedge-taken count is (sext i32 %len to i64) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (sext i32 %len to i64) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (sext i32 %len to i64) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -121,7 +124,8 @@ ; CHECK-NEXT: --> (zext i32 %len to i64) U: [0,4294967296) S: [0,4294967296) Exits: (zext i32 %len to i64) LoopDispositions: { %loop: Invariant } ; CHECK-NEXT: Determining loop execution counts for: @ult_sext_x_zext_x ; CHECK-NEXT: Loop %loop: backedge-taken count is (zext i32 %len to i64) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (zext i32 %len to i64) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (zext i32 %len to i64) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -156,7 +160,8 @@ ; CHECK-NEXT: --> (sext i32 %len to i64) U: [-2147483648,2147483648) S: [-2147483648,2147483648) Exits: (sext i32 %len to i64) LoopDispositions: { %loop: Invariant } ; CHECK-NEXT: Determining loop execution counts for: @ugt_sext_x_zext_x ; CHECK-NEXT: Loop %loop: backedge-taken count is (sext i32 %len to i64) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (sext i32 %len to i64) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (sext i32 %len to i64) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -191,7 +196,8 @@ ; CHECK-NEXT: --> (zext i32 %len to i64) U: [0,4294967296) S: [0,4294967296) Exits: (zext i32 %len to i64) LoopDispositions: { %loop: Invariant } ; CHECK-NEXT: Determining loop execution counts for: @sle_sext_x_zext_x ; CHECK-NEXT: Loop %loop: backedge-taken count is (zext i32 %len to i64) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (zext i32 %len to i64) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (zext i32 %len to i64) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -226,7 +232,8 @@ ; CHECK-NEXT: --> (zext i32 %len to i64) U: [0,4294967296) S: [0,4294967296) Exits: (zext i32 %len to i64) LoopDispositions: { %loop: Invariant } ; CHECK-NEXT: Determining loop execution counts for: @sge_sext_x_zext_x ; CHECK-NEXT: Loop %loop: backedge-taken count is (zext i32 %len to i64) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (zext i32 %len to i64) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (zext i32 %len to i64) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -261,7 +268,8 @@ ; CHECK-NEXT: --> (sext i32 %len to i64) U: [-2147483648,2147483648) S: [-2147483648,2147483648) Exits: (sext i32 %len to i64) LoopDispositions: { %loop: Invariant } ; CHECK-NEXT: Determining loop execution counts for: @slt_sext_x_zext_x ; CHECK-NEXT: Loop %loop: backedge-taken count is (sext i32 %len to i64) -; CHECK-NEXT: Loop %loop: max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is -1 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (sext i32 %len to i64) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (sext i32 %len to i64) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 @@ -296,7 +304,8 @@ ; CHECK-NEXT: --> (zext i32 %len to i64) U: [0,4294967296) S: [0,4294967296) Exits: (zext i32 %len to i64) LoopDispositions: { %loop: Invariant } ; CHECK-NEXT: Determining loop execution counts for: @sgt_sext_x_zext_x ; CHECK-NEXT: Loop %loop: backedge-taken count is (zext i32 %len to i64) -; CHECK-NEXT: Loop %loop: max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 4294967295 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (zext i32 %len to i64) ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is (zext i32 %len to i64) ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 1 diff --git a/llvm/test/Analysis/ScalarEvolution/unknown_phis.ll b/llvm/test/Analysis/ScalarEvolution/unknown_phis.ll --- a/llvm/test/Analysis/ScalarEvolution/unknown_phis.ll +++ b/llvm/test/Analysis/ScalarEvolution/unknown_phis.ll @@ -48,7 +48,8 @@ ; CHECK-NEXT: --> {1,+,1}<%loop> U: [1,101) S: [1,101) Exits: 100 LoopDispositions: { %loop: Computable } ; CHECK-NEXT: Determining loop execution counts for: @merge_values_with_ranges_looped ; CHECK-NEXT: Loop %loop: backedge-taken count is 99 -; CHECK-NEXT: Loop %loop: max backedge-taken count is 99 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 99 +; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is 99 ; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is 99 ; CHECK-NEXT: Predicates: ; CHECK: Loop %loop: Trip multiple is 100 diff --git a/llvm/test/Analysis/ScalarEvolution/widenable-condition.ll b/llvm/test/Analysis/ScalarEvolution/widenable-condition.ll --- a/llvm/test/Analysis/ScalarEvolution/widenable-condition.ll +++ b/llvm/test/Analysis/ScalarEvolution/widenable-condition.ll @@ -23,7 +23,8 @@ ; CHECK-NEXT: --> (%cond_1 umin %widenable_cond3) U: full-set S: full-set Exits: <> LoopDispositions: { %loop: Variant } ; CHECK-NEXT: Determining loop execution counts for: @wc_max ; CHECK-NEXT: Loop %loop: Unpredictable backedge-taken count. -; CHECK-NEXT: Loop %loop: max backedge-taken count is 1999 +; CHECK-NEXT: Loop %loop: constant max backedge-taken count is 1999 +; CHECK-NEXT: Loop %loop: Unpredictable symbolic max backedge-taken count. ; CHECK-NEXT: Loop %loop: Unpredictable predicated backedge-taken count. ; entry: diff --git a/llvm/test/Assembler/opaque-ptr-struct-types.ll b/llvm/test/Assembler/opaque-ptr-struct-types.ll --- a/llvm/test/Assembler/opaque-ptr-struct-types.ll +++ b/llvm/test/Assembler/opaque-ptr-struct-types.ll @@ -20,7 +20,7 @@ @g = external global %T1 -@g.ifunc = ifunc %T8 (), ptr @f +@g.ifunc = ifunc %T8 (), ptr @f.resolver define %T2 @f(ptr %p) { alloca %T3 @@ -30,4 +30,12 @@ unreachable } +define %T2* @f.resolver(ptr %p) { + alloca %T3 + getelementptr %T4, ptr %p, i64 1 + call void @f(ptr sret(%T5) %p) + store ptr getelementptr (%T6, ptr @g, i64 1), ptr %p + unreachable +} + declare void @f2(ptr sret(%T7)) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll @@ -710,8 +710,8 @@ ; CHECK-NOLSE-O1-NEXT: ldrb w10, [x0, w1, sxtw] ; CHECK-NOLSE-O1-NEXT: ldurb w11, [x0, #-256] ; CHECK-NOLSE-O1-NEXT: ldrb w8, [x8] -; CHECK-NOLSE-O1-NEXT: add w9, w9, w10 ; CHECK-NOLSE-O1-NEXT: add w9, w9, w11 +; CHECK-NOLSE-O1-NEXT: add w9, w10, w9 ; CHECK-NOLSE-O1-NEXT: add w0, w9, w8 ; CHECK-NOLSE-O1-NEXT: ret ; @@ -733,9 +733,9 @@ ; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1-NEXT: ldrb w8, [x0, #4095] ; CHECK-LSE-O1-NEXT: ldrb w9, [x0, w1, sxtw] -; CHECK-LSE-O1-NEXT: add w8, w8, w9 -; CHECK-LSE-O1-NEXT: ldurb w9, [x0, #-256] -; CHECK-LSE-O1-NEXT: add w8, w8, w9 +; CHECK-LSE-O1-NEXT: ldurb w10, [x0, #-256] +; CHECK-LSE-O1-NEXT: add w8, w8, w10 +; CHECK-LSE-O1-NEXT: add w8, w9, w8 ; CHECK-LSE-O1-NEXT: add x9, x0, #291, lsl #12 ; =1191936 ; CHECK-LSE-O1-NEXT: ldrb w9, [x9] ; CHECK-LSE-O1-NEXT: add w0, w8, w9 @@ -780,8 +780,8 @@ ; CHECK-NOLSE-O1-NEXT: ldrh w10, [x0, w1, sxtw #1] ; CHECK-NOLSE-O1-NEXT: ldurh w11, [x0, #-256] ; CHECK-NOLSE-O1-NEXT: ldrh w8, [x8] -; CHECK-NOLSE-O1-NEXT: add w9, w9, w10 ; CHECK-NOLSE-O1-NEXT: add w9, w9, w11 +; CHECK-NOLSE-O1-NEXT: add w9, w10, w9 ; CHECK-NOLSE-O1-NEXT: add w0, w9, w8 ; CHECK-NOLSE-O1-NEXT: ret ; @@ -803,9 +803,9 @@ ; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1-NEXT: ldrh w8, [x0, #8190] ; CHECK-LSE-O1-NEXT: ldrh w9, [x0, w1, sxtw #1] -; CHECK-LSE-O1-NEXT: add w8, w8, w9 -; CHECK-LSE-O1-NEXT: ldurh w9, [x0, #-256] -; CHECK-LSE-O1-NEXT: add w8, w8, w9 +; CHECK-LSE-O1-NEXT: ldurh w10, [x0, #-256] +; CHECK-LSE-O1-NEXT: add w8, w8, w10 +; CHECK-LSE-O1-NEXT: add w8, w9, w8 ; CHECK-LSE-O1-NEXT: add x9, x0, #291, lsl #12 ; =1191936 ; CHECK-LSE-O1-NEXT: ldrh w9, [x9] ; CHECK-LSE-O1-NEXT: add w0, w8, w9 @@ -850,8 +850,8 @@ ; CHECK-NOLSE-O1-NEXT: ldr w10, [x0, w1, sxtw #2] ; CHECK-NOLSE-O1-NEXT: ldur w11, [x0, #-256] ; CHECK-NOLSE-O1-NEXT: ldr w8, [x8] -; CHECK-NOLSE-O1-NEXT: add w9, w9, w10 ; CHECK-NOLSE-O1-NEXT: add w9, w9, w11 +; CHECK-NOLSE-O1-NEXT: add w9, w10, w9 ; CHECK-NOLSE-O1-NEXT: add w0, w9, w8 ; CHECK-NOLSE-O1-NEXT: ret ; @@ -871,9 +871,9 @@ ; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1-NEXT: ldr w8, [x0, #16380] ; CHECK-LSE-O1-NEXT: ldr w9, [x0, w1, sxtw #2] -; CHECK-LSE-O1-NEXT: add w8, w8, w9 -; CHECK-LSE-O1-NEXT: ldur w9, [x0, #-256] -; CHECK-LSE-O1-NEXT: add w8, w8, w9 +; CHECK-LSE-O1-NEXT: ldur w10, [x0, #-256] +; CHECK-LSE-O1-NEXT: add w8, w8, w10 +; CHECK-LSE-O1-NEXT: add w8, w9, w8 ; CHECK-LSE-O1-NEXT: add x9, x0, #291, lsl #12 ; =1191936 ; CHECK-LSE-O1-NEXT: ldr w9, [x9] ; CHECK-LSE-O1-NEXT: add w0, w8, w9 @@ -916,8 +916,8 @@ ; CHECK-NOLSE-O1-NEXT: ldr x10, [x0, w1, sxtw #3] ; CHECK-NOLSE-O1-NEXT: ldur x11, [x0, #-256] ; CHECK-NOLSE-O1-NEXT: ldr x8, [x8] -; CHECK-NOLSE-O1-NEXT: add x9, x9, x10 ; CHECK-NOLSE-O1-NEXT: add x9, x9, x11 +; CHECK-NOLSE-O1-NEXT: add x9, x10, x9 ; CHECK-NOLSE-O1-NEXT: add x0, x9, x8 ; CHECK-NOLSE-O1-NEXT: ret ; @@ -937,9 +937,9 @@ ; CHECK-LSE-O1: ; %bb.0: ; CHECK-LSE-O1-NEXT: ldr x8, [x0, #32760] ; CHECK-LSE-O1-NEXT: ldr x9, [x0, w1, sxtw #3] -; CHECK-LSE-O1-NEXT: add x8, x8, x9 -; CHECK-LSE-O1-NEXT: ldur x9, [x0, #-256] -; CHECK-LSE-O1-NEXT: add x8, x8, x9 +; CHECK-LSE-O1-NEXT: ldur x10, [x0, #-256] +; CHECK-LSE-O1-NEXT: add x8, x8, x10 +; CHECK-LSE-O1-NEXT: add x8, x9, x8 ; CHECK-LSE-O1-NEXT: add x9, x0, #291, lsl #12 ; =1191936 ; CHECK-LSE-O1-NEXT: ldr x9, [x9] ; CHECK-LSE-O1-NEXT: add x0, x8, x9 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll @@ -389,8 +389,8 @@ ; CHECK-NEXT: renamable $w10 = LDRBBroW renamable $x0, killed renamable $w1, 1, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_regoff) ; CHECK-NEXT: renamable $w11 = LDURBBi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s8) from %ir.ptr_unscaled) ; CHECK-NEXT: renamable $w8 = LDRBBui killed renamable $x8, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_random) - ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w10, 0, pcsections !0 - ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0, pcsections !0 + ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0 + ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0 ; CHECK-NEXT: $w0 = ADDWrs killed renamable $w9, killed renamable $w8, 0, pcsections !0 ; CHECK-NEXT: RET undef $lr, implicit $w0 %ptr_unsigned = getelementptr i8, i8* %p, i32 4095 @@ -421,8 +421,8 @@ ; CHECK-NEXT: renamable $w10 = LDRHHroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s16) from %ir.ptr_regoff) ; CHECK-NEXT: renamable $w11 = LDURHHi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s16) from %ir.ptr_unscaled) ; CHECK-NEXT: renamable $w8 = LDRHHui killed renamable $x8, 0, pcsections !0 :: (load unordered (s16) from %ir.ptr_random) - ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w10, 0, pcsections !0 - ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0, pcsections !0 + ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0 + ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0 ; CHECK-NEXT: $w0 = ADDWrs killed renamable $w9, killed renamable $w8, 0, pcsections !0 ; CHECK-NEXT: RET undef $lr, implicit $w0 %ptr_unsigned = getelementptr i16, i16* %p, i32 4095 @@ -453,8 +453,8 @@ ; CHECK-NEXT: renamable $w10 = LDRWroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s32) from %ir.ptr_regoff) ; CHECK-NEXT: renamable $w11 = LDURWi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s32) from %ir.ptr_unscaled) ; CHECK-NEXT: renamable $w8 = LDRWui killed renamable $x8, 0, pcsections !0 :: (load unordered (s32) from %ir.ptr_random) - ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w10, 0, pcsections !0 - ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0, pcsections !0 + ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0 + ; CHECK-NEXT: $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0 ; CHECK-NEXT: $w0 = ADDWrs killed renamable $w9, killed renamable $w8, 0, pcsections !0 ; CHECK-NEXT: RET undef $lr, implicit $w0 %ptr_unsigned = getelementptr i32, i32* %p, i32 4095 @@ -485,8 +485,8 @@ ; CHECK-NEXT: renamable $x10 = LDRXroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s64) from %ir.ptr_regoff) ; CHECK-NEXT: renamable $x11 = LDURXi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s64) from %ir.ptr_unscaled) ; CHECK-NEXT: renamable $x8 = LDRXui killed renamable $x8, 0, pcsections !0 :: (load unordered (s64) from %ir.ptr_random) - ; CHECK-NEXT: $x9 = ADDXrs killed renamable $x9, killed renamable $x10, 0, pcsections !0 - ; CHECK-NEXT: $x9 = ADDXrs killed renamable $x9, killed renamable $x11, 0, pcsections !0 + ; CHECK-NEXT: $x9 = ADDXrs killed renamable $x9, killed renamable $x11, 0 + ; CHECK-NEXT: $x9 = ADDXrs killed renamable $x10, killed renamable $x9, 0 ; CHECK-NEXT: $x0 = ADDXrs killed renamable $x9, killed renamable $x8, 0, pcsections !0 ; CHECK-NEXT: RET undef $lr, implicit $x0 %ptr_unsigned = getelementptr i64, i64* %p, i32 4095 diff --git a/llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll b/llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll --- a/llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll +++ b/llvm/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll @@ -90,7 +90,7 @@ %conv = fptosi double %d10 to i32 %add = add nsw i32 %conv, %i10 %l1.0.l1.0. = load volatile i32, i32* %l1, align 4 - %add1 = add nsw i32 %add, %l1.0.l1.0. + %add1 = or i32 %add, %l1.0.l1.0. %call = tail call i32 @g() %add2 = add nsw i32 %add1, %call ret i32 %add2 @@ -172,7 +172,7 @@ %conv = fptosi double %d10 to i32 %add = add nsw i32 %conv, %i10 %l1.0.l1.0. = load volatile i32, i32* %l1, align 128 - %add1 = add nsw i32 %add, %l1.0.l1.0. + %add1 = or i32 %add, %l1.0.l1.0. %call = tail call i32 @g() %add2 = add nsw i32 %add1, %call ret i32 %add2 @@ -276,7 +276,7 @@ %conv = fptosi double %d10 to i32 %add = add nsw i32 %conv, %i10 %l1.0.l1.0. = load volatile i32, i32* %l1, align 4 - %add1 = add nsw i32 %add, %l1.0.l1.0. + %add1 = or i32 %add, %l1.0.l1.0. %call = tail call i32 @g() %add2 = add nsw i32 %add1, %call %1 = load volatile i32, i32* %vla, align 4, !tbaa !1 @@ -376,7 +376,7 @@ %conv = fptosi double %d10 to i32 %add = add nsw i32 %conv, %i10 %l1.0.l1.0. = load volatile i32, i32* %l1, align 128 - %add1 = add nsw i32 %add, %l1.0.l1.0. + %add1 = or i32 %add, %l1.0.l1.0. %call = tail call i32 @g() %add2 = add nsw i32 %add1, %call %1 = load volatile i32, i32* %vla, align 4, !tbaa !1 diff --git a/llvm/test/CodeGen/AArch64/arm64-rev.ll b/llvm/test/CodeGen/AArch64/arm64-rev.ll --- a/llvm/test/CodeGen/AArch64/arm64-rev.ll +++ b/llvm/test/CodeGen/AArch64/arm64-rev.ll @@ -183,11 +183,11 @@ ; GISEL-NEXT: lsl w9, w0, #8 ; GISEL-NEXT: and w10, w8, #0xff0000 ; GISEL-NEXT: and w11, w9, #0xff000000 +; GISEL-NEXT: and w8, w8, #0xff ; GISEL-NEXT: and w9, w9, #0xff00 ; GISEL-NEXT: orr w10, w11, w10 -; GISEL-NEXT: and w8, w8, #0xff -; GISEL-NEXT: orr w9, w10, w9 -; GISEL-NEXT: orr w0, w9, w8 +; GISEL-NEXT: orr w8, w9, w8 +; GISEL-NEXT: orr w0, w10, w8 ; GISEL-NEXT: ret entry: %tmp1 = lshr i32 %X, 8 @@ -729,16 +729,16 @@ ; GISEL-NEXT: lsl x9, x0, #8 ; GISEL-NEXT: and x10, x8, #0xff000000000000 ; GISEL-NEXT: and x11, x9, #0xff00000000000000 +; GISEL-NEXT: and x12, x8, #0xff00000000 +; GISEL-NEXT: and x13, x9, #0xff0000000000 ; GISEL-NEXT: orr x10, x10, x11 -; GISEL-NEXT: and x11, x8, #0xff00000000 -; GISEL-NEXT: orr x10, x10, x11 -; GISEL-NEXT: and x11, x9, #0xff0000000000 -; GISEL-NEXT: orr x10, x10, x11 -; GISEL-NEXT: and x11, x8, #0xff0000 -; GISEL-NEXT: orr x10, x10, x11 -; GISEL-NEXT: and x11, x9, #0xff000000 -; GISEL-NEXT: orr x10, x10, x11 +; GISEL-NEXT: orr x11, x12, x13 +; GISEL-NEXT: and x12, x8, #0xff0000 +; GISEL-NEXT: and x13, x9, #0xff000000 +; GISEL-NEXT: orr x12, x12, x13 ; GISEL-NEXT: and x8, x8, #0xff +; GISEL-NEXT: orr x10, x10, x11 +; GISEL-NEXT: orr x8, x12, x8 ; GISEL-NEXT: orr x8, x10, x8 ; GISEL-NEXT: and x9, x9, #0xff00 ; GISEL-NEXT: orr x0, x8, x9 @@ -782,21 +782,21 @@ ; GISEL-LABEL: test_rev16_x_hwbyteswaps_complex2: ; GISEL: // %bb.0: // %entry ; GISEL-NEXT: lsr x8, x0, #8 -; GISEL-NEXT: lsl x10, x0, #8 -; GISEL-NEXT: and x9, x8, #0xff000000000000 +; GISEL-NEXT: lsl x9, x0, #8 +; GISEL-NEXT: and x10, x8, #0xff000000000000 ; GISEL-NEXT: and x11, x8, #0xff00000000 -; GISEL-NEXT: orr x9, x9, x11 -; GISEL-NEXT: and x11, x8, #0xff0000 -; GISEL-NEXT: orr x9, x9, x11 +; GISEL-NEXT: and x12, x8, #0xff0000 ; GISEL-NEXT: and x8, x8, #0xff -; GISEL-NEXT: orr x8, x9, x8 -; GISEL-NEXT: and x9, x10, #0xff00000000000000 -; GISEL-NEXT: orr x8, x8, x9 -; GISEL-NEXT: and x9, x10, #0xff0000000000 -; GISEL-NEXT: orr x8, x8, x9 -; GISEL-NEXT: and x9, x10, #0xff000000 -; GISEL-NEXT: orr x8, x8, x9 -; GISEL-NEXT: and x9, x10, #0xff00 +; GISEL-NEXT: orr x10, x10, x11 +; GISEL-NEXT: orr x8, x12, x8 +; GISEL-NEXT: and x11, x9, #0xff00000000000000 +; GISEL-NEXT: and x12, x9, #0xff0000000000 +; GISEL-NEXT: orr x11, x11, x12 +; GISEL-NEXT: and x12, x9, #0xff000000 +; GISEL-NEXT: orr x8, x10, x8 +; GISEL-NEXT: orr x10, x11, x12 +; GISEL-NEXT: orr x8, x8, x10 +; GISEL-NEXT: and x9, x9, #0xff00 ; GISEL-NEXT: orr x0, x8, x9 ; GISEL-NEXT: ret entry: @@ -847,17 +847,17 @@ ; GISEL-NEXT: lsl x9, x0, #8 ; GISEL-NEXT: and x10, x8, #0xff000000000000 ; GISEL-NEXT: and x11, x9, #0xff00000000000000 +; GISEL-NEXT: and x12, x8, #0xff00000000 +; GISEL-NEXT: and x13, x9, #0xff0000000000 ; GISEL-NEXT: orr x10, x11, x10 -; GISEL-NEXT: and x11, x8, #0xff00000000 -; GISEL-NEXT: orr x10, x11, x10 -; GISEL-NEXT: and x11, x9, #0xff0000000000 -; GISEL-NEXT: orr x10, x11, x10 -; GISEL-NEXT: and x11, x8, #0xff0000 -; GISEL-NEXT: orr x10, x11, x10 -; GISEL-NEXT: and x11, x9, #0xff000000 -; GISEL-NEXT: orr x10, x11, x10 +; GISEL-NEXT: orr x11, x12, x13 +; GISEL-NEXT: and x12, x8, #0xff0000 +; GISEL-NEXT: and x13, x9, #0xff000000 +; GISEL-NEXT: orr x12, x12, x13 ; GISEL-NEXT: and x8, x8, #0xff -; GISEL-NEXT: orr x8, x8, x10 +; GISEL-NEXT: orr x10, x10, x11 +; GISEL-NEXT: orr x8, x12, x8 +; GISEL-NEXT: orr x8, x10, x8 ; GISEL-NEXT: and x9, x9, #0xff00 ; GISEL-NEXT: orr x0, x9, x8 ; GISEL-NEXT: ret @@ -918,24 +918,24 @@ ; CHECK-LABEL: test_or_and_combine2: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: lsr x8, x0, #8 -; CHECK-NEXT: lsl x10, x0, #8 -; CHECK-NEXT: and x9, x8, #0xff000000000000 +; CHECK-NEXT: lsl x9, x0, #8 +; CHECK-NEXT: and x10, x8, #0xff000000000000 +; CHECK-NEXT: and x11, x9, #0xff00000000 ; CHECK-NEXT: and x8, x8, #0xff0000 -; CHECK-NEXT: orr x9, x9, x10 -; CHECK-NEXT: and x10, x10, #0xff00000000 -; CHECK-NEXT: orr x9, x9, x10 +; CHECK-NEXT: orr x9, x10, x9 +; CHECK-NEXT: orr x8, x11, x8 ; CHECK-NEXT: orr x0, x9, x8 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_or_and_combine2: ; GISEL: // %bb.0: // %entry ; GISEL-NEXT: lsr x8, x0, #8 -; GISEL-NEXT: lsl x10, x0, #8 -; GISEL-NEXT: and x9, x8, #0xff000000000000 +; GISEL-NEXT: lsl x9, x0, #8 +; GISEL-NEXT: and x10, x8, #0xff000000000000 +; GISEL-NEXT: and x11, x9, #0xff00000000 ; GISEL-NEXT: and x8, x8, #0xff0000 -; GISEL-NEXT: orr x9, x9, x10 -; GISEL-NEXT: and x10, x10, #0xff00000000 -; GISEL-NEXT: orr x9, x9, x10 +; GISEL-NEXT: orr x9, x10, x9 +; GISEL-NEXT: orr x8, x11, x8 ; GISEL-NEXT: orr x0, x9, x8 ; GISEL-NEXT: ret entry: diff --git a/llvm/test/CodeGen/AArch64/cmp-chains.ll b/llvm/test/CodeGen/AArch64/cmp-chains.ll --- a/llvm/test/CodeGen/AArch64/cmp-chains.ll +++ b/llvm/test/CodeGen/AArch64/cmp-chains.ll @@ -76,11 +76,11 @@ ; GISEL-NEXT: cmp w0, w1 ; GISEL-NEXT: cset w9, lo ; GISEL-NEXT: cmp w4, w5 -; GISEL-NEXT: and w8, w8, w9 -; GISEL-NEXT: cset w9, ne +; GISEL-NEXT: cset w10, ne ; GISEL-NEXT: cmp w6, w7 +; GISEL-NEXT: cset w11, eq ; GISEL-NEXT: and w8, w8, w9 -; GISEL-NEXT: cset w9, eq +; GISEL-NEXT: and w9, w10, w11 ; GISEL-NEXT: and w0, w8, w9 ; GISEL-NEXT: ret %9 = icmp ugt i32 %2, %3 @@ -166,11 +166,11 @@ ; GISEL-NEXT: cmp w2, w3 ; GISEL-NEXT: cset w9, hi ; GISEL-NEXT: cmp w4, w5 -; GISEL-NEXT: orr w8, w8, w9 -; GISEL-NEXT: cset w9, ne +; GISEL-NEXT: cset w10, ne ; GISEL-NEXT: cmp w6, w7 +; GISEL-NEXT: cset w11, eq ; GISEL-NEXT: orr w8, w8, w9 -; GISEL-NEXT: cset w9, eq +; GISEL-NEXT: orr w9, w10, w11 ; GISEL-NEXT: orr w0, w8, w9 ; GISEL-NEXT: ret %9 = icmp ult i32 %0, %1 diff --git a/llvm/test/CodeGen/AArch64/pr-cf624b2.ll b/llvm/test/CodeGen/AArch64/pr-cf624b2.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/pr-cf624b2.ll @@ -0,0 +1,64 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s + +;; This used to crash mid-legalization because we'd no longer have BUILD_VECTOR, +;; but an CONCAT_VECTOR, and we didn't anticipate that. + +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" + +define linkonce_odr void @_ZN1y2beEPiRK1vPmPS1_(<8 x i8> %0, ptr %agg.tmp.i) { +; CHECK-LABEL: _ZN1y2beEPiRK1vPmPS1_: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: mov x8, sp +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: orr x9, x8, #0xf +; CHECK-NEXT: orr x11, x8, #0xc +; CHECK-NEXT: orr x10, x8, #0xe +; CHECK-NEXT: orr x12, x8, #0x8 +; CHECK-NEXT: st1 { v0.b }[0], [x8] +; CHECK-NEXT: st1 { v0.b }[15], [x9] +; CHECK-NEXT: orr x9, x8, #0x7 +; CHECK-NEXT: st1 { v0.b }[12], [x11] +; CHECK-NEXT: orr x11, x8, #0x4 +; CHECK-NEXT: st1 { v0.b }[14], [x10] +; CHECK-NEXT: orr x10, x8, #0x6 +; CHECK-NEXT: st1 { v0.b }[7], [x9] +; CHECK-NEXT: orr x9, x8, #0x3 +; CHECK-NEXT: st1 { v0.b }[8], [x12] +; CHECK-NEXT: mov w12, #11 +; CHECK-NEXT: st1 { v0.b }[4], [x11] +; CHECK-NEXT: mov w11, #13 +; CHECK-NEXT: st1 { v0.b }[3], [x9] +; CHECK-NEXT: orr x9, x8, #0x2 +; CHECK-NEXT: st1 { v0.b }[6], [x10] +; CHECK-NEXT: orr x10, x8, #0x1 +; CHECK-NEXT: orr x11, x8, x11 +; CHECK-NEXT: st1 { v0.b }[2], [x9] +; CHECK-NEXT: orr x9, x8, x12 +; CHECK-NEXT: st1 { v0.b }[1], [x10] +; CHECK-NEXT: mov w10, #9 +; CHECK-NEXT: st1 { v0.b }[13], [x11] +; CHECK-NEXT: mov w11, #5 +; CHECK-NEXT: st1 { v0.b }[11], [x9] +; CHECK-NEXT: mov w9, #10 +; CHECK-NEXT: orr x9, x8, x9 +; CHECK-NEXT: orr x10, x8, x10 +; CHECK-NEXT: orr x8, x8, x11 +; CHECK-NEXT: movi v1.2d, #0000000000000000 +; CHECK-NEXT: st1 { v0.b }[10], [x9] +; CHECK-NEXT: st1 { v0.b }[9], [x10] +; CHECK-NEXT: st1 { v0.b }[5], [x8] +; CHECK-NEXT: ldr q0, [sp] +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret +entry: + %ref.tmp6.sroa.0.0.vecblend.i = shufflevector <8 x i8> %0, <8 x i8> zeroinitializer, <24 x i32> + %ref.tmp6.sroa.0.20.vecblend.i = shufflevector <24 x i8> %ref.tmp6.sroa.0.0.vecblend.i, <24 x i8> zeroinitializer, <24 x i32> + %ref.tmp.sroa.0.0.vecblend.i = shufflevector <24 x i8> %ref.tmp6.sroa.0.20.vecblend.i, <24 x i8> zeroinitializer, <28 x i32> + %n.sroa.0.0.vecblend.i.i = shufflevector <28 x i8> %ref.tmp.sroa.0.0.vecblend.i, <28 x i8> zeroinitializer, <32 x i32> + store <32 x i8> %n.sroa.0.0.vecblend.i.i, ptr %agg.tmp.i, align 4 + ret void +} diff --git a/llvm/test/CodeGen/AArch64/reduce-and.ll b/llvm/test/CodeGen/AArch64/reduce-and.ll --- a/llvm/test/CodeGen/AArch64/reduce-and.ll +++ b/llvm/test/CodeGen/AArch64/reduce-and.ll @@ -264,13 +264,13 @@ ; CHECK-LABEL: test_redand_v4i8: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: umov w8, v0.h[1] -; CHECK-NEXT: umov w9, v0.h[0] -; CHECK-NEXT: umov w10, v0.h[2] -; CHECK-NEXT: umov w11, v0.h[3] +; CHECK-NEXT: umov w8, v0.h[3] +; CHECK-NEXT: umov w9, v0.h[2] +; CHECK-NEXT: umov w10, v0.h[1] +; CHECK-NEXT: umov w11, v0.h[0] ; CHECK-NEXT: and w8, w9, w8 -; CHECK-NEXT: and w8, w8, w10 -; CHECK-NEXT: and w0, w8, w11 +; CHECK-NEXT: and w10, w11, w10 +; CHECK-NEXT: and w0, w10, w8 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redand_v4i8: @@ -295,21 +295,21 @@ ; CHECK-LABEL: test_redand_v8i8: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: umov w8, v0.b[1] -; CHECK-NEXT: umov w9, v0.b[0] -; CHECK-NEXT: umov w10, v0.b[2] -; CHECK-NEXT: umov w11, v0.b[3] -; CHECK-NEXT: umov w12, v0.b[4] -; CHECK-NEXT: umov w13, v0.b[5] +; CHECK-NEXT: umov w8, v0.b[5] +; CHECK-NEXT: umov w9, v0.b[4] +; CHECK-NEXT: umov w10, v0.b[1] +; CHECK-NEXT: umov w11, v0.b[0] +; CHECK-NEXT: umov w12, v0.b[3] +; CHECK-NEXT: umov w13, v0.b[2] +; CHECK-NEXT: umov w14, v0.b[6] +; CHECK-NEXT: umov w15, v0.b[7] ; CHECK-NEXT: and w8, w9, w8 -; CHECK-NEXT: umov w9, v0.b[6] -; CHECK-NEXT: and w8, w8, w10 -; CHECK-NEXT: umov w10, v0.b[7] -; CHECK-NEXT: and w8, w8, w11 -; CHECK-NEXT: and w8, w8, w12 -; CHECK-NEXT: and w8, w8, w13 -; CHECK-NEXT: and w8, w8, w9 -; CHECK-NEXT: and w0, w8, w10 +; CHECK-NEXT: and w10, w11, w10 +; CHECK-NEXT: and w11, w13, w12 +; CHECK-NEXT: and w9, w10, w11 +; CHECK-NEXT: and w8, w8, w14 +; CHECK-NEXT: and w8, w9, w8 +; CHECK-NEXT: and w0, w8, w15 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redand_v8i8: @@ -352,16 +352,16 @@ ; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w11, v0.b[3] ; CHECK-NEXT: umov w12, v0.b[4] +; CHECK-NEXT: umov w13, v0.b[5] +; CHECK-NEXT: umov w14, v0.b[6] ; CHECK-NEXT: and w8, w9, w8 -; CHECK-NEXT: umov w9, v0.b[5] +; CHECK-NEXT: umov w9, v0.b[7] +; CHECK-NEXT: and w10, w10, w11 +; CHECK-NEXT: and w11, w12, w13 ; CHECK-NEXT: and w8, w8, w10 -; CHECK-NEXT: umov w10, v0.b[6] -; CHECK-NEXT: and w8, w8, w11 -; CHECK-NEXT: umov w11, v0.b[7] -; CHECK-NEXT: and w8, w8, w12 -; CHECK-NEXT: and w8, w8, w9 +; CHECK-NEXT: and w10, w11, w14 ; CHECK-NEXT: and w8, w8, w10 -; CHECK-NEXT: and w0, w8, w11 +; CHECK-NEXT: and w0, w8, w9 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redand_v16i8: @@ -406,16 +406,16 @@ ; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w11, v0.b[3] ; CHECK-NEXT: umov w12, v0.b[4] +; CHECK-NEXT: umov w13, v0.b[5] +; CHECK-NEXT: umov w14, v0.b[6] ; CHECK-NEXT: and w8, w9, w8 -; CHECK-NEXT: umov w9, v0.b[5] +; CHECK-NEXT: umov w9, v0.b[7] +; CHECK-NEXT: and w10, w10, w11 +; CHECK-NEXT: and w11, w12, w13 ; CHECK-NEXT: and w8, w8, w10 -; CHECK-NEXT: umov w10, v0.b[6] -; CHECK-NEXT: and w8, w8, w11 -; CHECK-NEXT: umov w11, v0.b[7] -; CHECK-NEXT: and w8, w8, w12 -; CHECK-NEXT: and w8, w8, w9 +; CHECK-NEXT: and w10, w11, w14 ; CHECK-NEXT: and w8, w8, w10 -; CHECK-NEXT: and w0, w8, w11 +; CHECK-NEXT: and w0, w8, w9 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redand_v32i8: @@ -454,13 +454,13 @@ ; CHECK-LABEL: test_redand_v4i16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: umov w8, v0.h[1] -; CHECK-NEXT: umov w9, v0.h[0] -; CHECK-NEXT: umov w10, v0.h[2] -; CHECK-NEXT: umov w11, v0.h[3] +; CHECK-NEXT: umov w8, v0.h[3] +; CHECK-NEXT: umov w9, v0.h[2] +; CHECK-NEXT: umov w10, v0.h[1] +; CHECK-NEXT: umov w11, v0.h[0] ; CHECK-NEXT: and w8, w9, w8 -; CHECK-NEXT: and w8, w8, w10 -; CHECK-NEXT: and w0, w8, w11 +; CHECK-NEXT: and w10, w11, w10 +; CHECK-NEXT: and w0, w10, w8 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redand_v4i16: @@ -491,8 +491,8 @@ ; CHECK-NEXT: umov w10, v0.h[2] ; CHECK-NEXT: umov w11, v0.h[3] ; CHECK-NEXT: and w8, w9, w8 -; CHECK-NEXT: and w8, w8, w10 -; CHECK-NEXT: and w0, w8, w11 +; CHECK-NEXT: and w9, w10, w11 +; CHECK-NEXT: and w0, w8, w9 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redand_v8i16: @@ -525,8 +525,8 @@ ; CHECK-NEXT: umov w10, v0.h[2] ; CHECK-NEXT: umov w11, v0.h[3] ; CHECK-NEXT: and w8, w9, w8 -; CHECK-NEXT: and w8, w8, w10 -; CHECK-NEXT: and w0, w8, w11 +; CHECK-NEXT: and w9, w10, w11 +; CHECK-NEXT: and w0, w8, w9 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redand_v16i16: diff --git a/llvm/test/CodeGen/AArch64/reduce-or.ll b/llvm/test/CodeGen/AArch64/reduce-or.ll --- a/llvm/test/CodeGen/AArch64/reduce-or.ll +++ b/llvm/test/CodeGen/AArch64/reduce-or.ll @@ -263,13 +263,13 @@ ; CHECK-LABEL: test_redor_v4i8: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: umov w8, v0.h[1] -; CHECK-NEXT: umov w9, v0.h[0] -; CHECK-NEXT: umov w10, v0.h[2] -; CHECK-NEXT: umov w11, v0.h[3] +; CHECK-NEXT: umov w8, v0.h[3] +; CHECK-NEXT: umov w9, v0.h[2] +; CHECK-NEXT: umov w10, v0.h[1] +; CHECK-NEXT: umov w11, v0.h[0] ; CHECK-NEXT: orr w8, w9, w8 -; CHECK-NEXT: orr w8, w8, w10 -; CHECK-NEXT: orr w0, w8, w11 +; CHECK-NEXT: orr w10, w11, w10 +; CHECK-NEXT: orr w0, w10, w8 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redor_v4i8: @@ -294,21 +294,21 @@ ; CHECK-LABEL: test_redor_v8i8: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: umov w8, v0.b[1] -; CHECK-NEXT: umov w9, v0.b[0] -; CHECK-NEXT: umov w10, v0.b[2] -; CHECK-NEXT: umov w11, v0.b[3] -; CHECK-NEXT: umov w12, v0.b[4] -; CHECK-NEXT: umov w13, v0.b[5] +; CHECK-NEXT: umov w8, v0.b[5] +; CHECK-NEXT: umov w9, v0.b[4] +; CHECK-NEXT: umov w10, v0.b[1] +; CHECK-NEXT: umov w11, v0.b[0] +; CHECK-NEXT: umov w12, v0.b[3] +; CHECK-NEXT: umov w13, v0.b[2] +; CHECK-NEXT: umov w14, v0.b[6] +; CHECK-NEXT: umov w15, v0.b[7] ; CHECK-NEXT: orr w8, w9, w8 -; CHECK-NEXT: umov w9, v0.b[6] -; CHECK-NEXT: orr w8, w8, w10 -; CHECK-NEXT: umov w10, v0.b[7] -; CHECK-NEXT: orr w8, w8, w11 -; CHECK-NEXT: orr w8, w8, w12 -; CHECK-NEXT: orr w8, w8, w13 -; CHECK-NEXT: orr w8, w8, w9 -; CHECK-NEXT: orr w0, w8, w10 +; CHECK-NEXT: orr w10, w11, w10 +; CHECK-NEXT: orr w11, w13, w12 +; CHECK-NEXT: orr w9, w10, w11 +; CHECK-NEXT: orr w8, w8, w14 +; CHECK-NEXT: orr w8, w9, w8 +; CHECK-NEXT: orr w0, w8, w15 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redor_v8i8: @@ -351,16 +351,16 @@ ; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w11, v0.b[3] ; CHECK-NEXT: umov w12, v0.b[4] +; CHECK-NEXT: umov w13, v0.b[5] +; CHECK-NEXT: umov w14, v0.b[6] ; CHECK-NEXT: orr w8, w9, w8 -; CHECK-NEXT: umov w9, v0.b[5] +; CHECK-NEXT: umov w9, v0.b[7] +; CHECK-NEXT: orr w10, w10, w11 +; CHECK-NEXT: orr w11, w12, w13 ; CHECK-NEXT: orr w8, w8, w10 -; CHECK-NEXT: umov w10, v0.b[6] -; CHECK-NEXT: orr w8, w8, w11 -; CHECK-NEXT: umov w11, v0.b[7] -; CHECK-NEXT: orr w8, w8, w12 -; CHECK-NEXT: orr w8, w8, w9 +; CHECK-NEXT: orr w10, w11, w14 ; CHECK-NEXT: orr w8, w8, w10 -; CHECK-NEXT: orr w0, w8, w11 +; CHECK-NEXT: orr w0, w8, w9 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redor_v16i8: @@ -405,16 +405,16 @@ ; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w11, v0.b[3] ; CHECK-NEXT: umov w12, v0.b[4] +; CHECK-NEXT: umov w13, v0.b[5] +; CHECK-NEXT: umov w14, v0.b[6] ; CHECK-NEXT: orr w8, w9, w8 -; CHECK-NEXT: umov w9, v0.b[5] +; CHECK-NEXT: umov w9, v0.b[7] +; CHECK-NEXT: orr w10, w10, w11 +; CHECK-NEXT: orr w11, w12, w13 ; CHECK-NEXT: orr w8, w8, w10 -; CHECK-NEXT: umov w10, v0.b[6] -; CHECK-NEXT: orr w8, w8, w11 -; CHECK-NEXT: umov w11, v0.b[7] -; CHECK-NEXT: orr w8, w8, w12 -; CHECK-NEXT: orr w8, w8, w9 +; CHECK-NEXT: orr w10, w11, w14 ; CHECK-NEXT: orr w8, w8, w10 -; CHECK-NEXT: orr w0, w8, w11 +; CHECK-NEXT: orr w0, w8, w9 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redor_v32i8: @@ -453,13 +453,13 @@ ; CHECK-LABEL: test_redor_v4i16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: umov w8, v0.h[1] -; CHECK-NEXT: umov w9, v0.h[0] -; CHECK-NEXT: umov w10, v0.h[2] -; CHECK-NEXT: umov w11, v0.h[3] +; CHECK-NEXT: umov w8, v0.h[3] +; CHECK-NEXT: umov w9, v0.h[2] +; CHECK-NEXT: umov w10, v0.h[1] +; CHECK-NEXT: umov w11, v0.h[0] ; CHECK-NEXT: orr w8, w9, w8 -; CHECK-NEXT: orr w8, w8, w10 -; CHECK-NEXT: orr w0, w8, w11 +; CHECK-NEXT: orr w10, w11, w10 +; CHECK-NEXT: orr w0, w10, w8 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redor_v4i16: @@ -490,8 +490,8 @@ ; CHECK-NEXT: umov w10, v0.h[2] ; CHECK-NEXT: umov w11, v0.h[3] ; CHECK-NEXT: orr w8, w9, w8 -; CHECK-NEXT: orr w8, w8, w10 -; CHECK-NEXT: orr w0, w8, w11 +; CHECK-NEXT: orr w9, w10, w11 +; CHECK-NEXT: orr w0, w8, w9 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redor_v8i16: @@ -524,8 +524,8 @@ ; CHECK-NEXT: umov w10, v0.h[2] ; CHECK-NEXT: umov w11, v0.h[3] ; CHECK-NEXT: orr w8, w9, w8 -; CHECK-NEXT: orr w8, w8, w10 -; CHECK-NEXT: orr w0, w8, w11 +; CHECK-NEXT: orr w9, w10, w11 +; CHECK-NEXT: orr w0, w8, w9 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redor_v16i16: diff --git a/llvm/test/CodeGen/AArch64/reduce-xor.ll b/llvm/test/CodeGen/AArch64/reduce-xor.ll --- a/llvm/test/CodeGen/AArch64/reduce-xor.ll +++ b/llvm/test/CodeGen/AArch64/reduce-xor.ll @@ -262,13 +262,13 @@ ; CHECK-LABEL: test_redxor_v4i8: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: umov w8, v0.h[1] -; CHECK-NEXT: umov w9, v0.h[0] -; CHECK-NEXT: umov w10, v0.h[2] -; CHECK-NEXT: umov w11, v0.h[3] +; CHECK-NEXT: umov w8, v0.h[3] +; CHECK-NEXT: umov w9, v0.h[2] +; CHECK-NEXT: umov w10, v0.h[1] +; CHECK-NEXT: umov w11, v0.h[0] ; CHECK-NEXT: eor w8, w9, w8 -; CHECK-NEXT: eor w8, w8, w10 -; CHECK-NEXT: eor w0, w8, w11 +; CHECK-NEXT: eor w10, w11, w10 +; CHECK-NEXT: eor w0, w10, w8 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redxor_v4i8: @@ -293,21 +293,21 @@ ; CHECK-LABEL: test_redxor_v8i8: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: umov w8, v0.b[1] -; CHECK-NEXT: umov w9, v0.b[0] -; CHECK-NEXT: umov w10, v0.b[2] -; CHECK-NEXT: umov w11, v0.b[3] -; CHECK-NEXT: umov w12, v0.b[4] -; CHECK-NEXT: umov w13, v0.b[5] +; CHECK-NEXT: umov w8, v0.b[5] +; CHECK-NEXT: umov w9, v0.b[4] +; CHECK-NEXT: umov w10, v0.b[1] +; CHECK-NEXT: umov w11, v0.b[0] +; CHECK-NEXT: umov w12, v0.b[3] +; CHECK-NEXT: umov w13, v0.b[2] +; CHECK-NEXT: umov w14, v0.b[6] +; CHECK-NEXT: umov w15, v0.b[7] ; CHECK-NEXT: eor w8, w9, w8 -; CHECK-NEXT: umov w9, v0.b[6] -; CHECK-NEXT: eor w8, w8, w10 -; CHECK-NEXT: umov w10, v0.b[7] -; CHECK-NEXT: eor w8, w8, w11 -; CHECK-NEXT: eor w8, w8, w12 -; CHECK-NEXT: eor w8, w8, w13 -; CHECK-NEXT: eor w8, w8, w9 -; CHECK-NEXT: eor w0, w8, w10 +; CHECK-NEXT: eor w10, w11, w10 +; CHECK-NEXT: eor w11, w13, w12 +; CHECK-NEXT: eor w9, w10, w11 +; CHECK-NEXT: eor w8, w8, w14 +; CHECK-NEXT: eor w8, w9, w8 +; CHECK-NEXT: eor w0, w8, w15 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redxor_v8i8: @@ -350,16 +350,16 @@ ; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w11, v0.b[3] ; CHECK-NEXT: umov w12, v0.b[4] +; CHECK-NEXT: umov w13, v0.b[5] +; CHECK-NEXT: umov w14, v0.b[6] ; CHECK-NEXT: eor w8, w9, w8 -; CHECK-NEXT: umov w9, v0.b[5] +; CHECK-NEXT: umov w9, v0.b[7] +; CHECK-NEXT: eor w10, w10, w11 +; CHECK-NEXT: eor w11, w12, w13 ; CHECK-NEXT: eor w8, w8, w10 -; CHECK-NEXT: umov w10, v0.b[6] -; CHECK-NEXT: eor w8, w8, w11 -; CHECK-NEXT: umov w11, v0.b[7] -; CHECK-NEXT: eor w8, w8, w12 -; CHECK-NEXT: eor w8, w8, w9 +; CHECK-NEXT: eor w10, w11, w14 ; CHECK-NEXT: eor w8, w8, w10 -; CHECK-NEXT: eor w0, w8, w11 +; CHECK-NEXT: eor w0, w8, w9 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redxor_v16i8: @@ -404,16 +404,16 @@ ; CHECK-NEXT: umov w10, v0.b[2] ; CHECK-NEXT: umov w11, v0.b[3] ; CHECK-NEXT: umov w12, v0.b[4] +; CHECK-NEXT: umov w13, v0.b[5] +; CHECK-NEXT: umov w14, v0.b[6] ; CHECK-NEXT: eor w8, w9, w8 -; CHECK-NEXT: umov w9, v0.b[5] +; CHECK-NEXT: umov w9, v0.b[7] +; CHECK-NEXT: eor w10, w10, w11 +; CHECK-NEXT: eor w11, w12, w13 ; CHECK-NEXT: eor w8, w8, w10 -; CHECK-NEXT: umov w10, v0.b[6] -; CHECK-NEXT: eor w8, w8, w11 -; CHECK-NEXT: umov w11, v0.b[7] -; CHECK-NEXT: eor w8, w8, w12 -; CHECK-NEXT: eor w8, w8, w9 +; CHECK-NEXT: eor w10, w11, w14 ; CHECK-NEXT: eor w8, w8, w10 -; CHECK-NEXT: eor w0, w8, w11 +; CHECK-NEXT: eor w0, w8, w9 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redxor_v32i8: @@ -452,13 +452,13 @@ ; CHECK-LABEL: test_redxor_v4i16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: umov w8, v0.h[1] -; CHECK-NEXT: umov w9, v0.h[0] -; CHECK-NEXT: umov w10, v0.h[2] -; CHECK-NEXT: umov w11, v0.h[3] +; CHECK-NEXT: umov w8, v0.h[3] +; CHECK-NEXT: umov w9, v0.h[2] +; CHECK-NEXT: umov w10, v0.h[1] +; CHECK-NEXT: umov w11, v0.h[0] ; CHECK-NEXT: eor w8, w9, w8 -; CHECK-NEXT: eor w8, w8, w10 -; CHECK-NEXT: eor w0, w8, w11 +; CHECK-NEXT: eor w10, w11, w10 +; CHECK-NEXT: eor w0, w10, w8 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redxor_v4i16: @@ -489,8 +489,8 @@ ; CHECK-NEXT: umov w10, v0.h[2] ; CHECK-NEXT: umov w11, v0.h[3] ; CHECK-NEXT: eor w8, w9, w8 -; CHECK-NEXT: eor w8, w8, w10 -; CHECK-NEXT: eor w0, w8, w11 +; CHECK-NEXT: eor w9, w10, w11 +; CHECK-NEXT: eor w0, w8, w9 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redxor_v8i16: @@ -523,8 +523,8 @@ ; CHECK-NEXT: umov w10, v0.h[2] ; CHECK-NEXT: umov w11, v0.h[3] ; CHECK-NEXT: eor w8, w9, w8 -; CHECK-NEXT: eor w8, w8, w10 -; CHECK-NEXT: eor w0, w8, w11 +; CHECK-NEXT: eor w9, w10, w11 +; CHECK-NEXT: eor w0, w8, w9 ; CHECK-NEXT: ret ; ; GISEL-LABEL: test_redxor_v16i16: diff --git a/llvm/test/CodeGen/AArch64/selectopt-logical.ll b/llvm/test/CodeGen/AArch64/selectopt-logical.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/selectopt-logical.ll @@ -0,0 +1,117 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -select-optimize -mtriple=aarch64-linux-gnu -mcpu=neoverse-v2 -S < %s | FileCheck %s + +define i32 @test(ptr nocapture noundef readnone %x, i32 noundef %iters) { +; CHECK-LABEL: @test( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[ITERS:%.*]], 0 +; CHECK-NEXT: br i1 [[CMP3]], label [[FOR_BODY_I_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]] +; CHECK: for.body.i.preheader: +; CHECK-NEXT: [[I_05:%.*]] = phi i32 [ [[INC:%.*]], [[INNER_LOOP_010_EXIT:%.*]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[RES_04:%.*]] = phi i32 [ [[OR:%.*]], [[INNER_LOOP_010_EXIT]] ], [ 0, [[ENTRY]] ] +; CHECK-NEXT: br label [[FOR_BODY_I:%.*]] +; CHECK: for.cond.cleanup: +; CHECK-NEXT: [[RES_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[OR]], [[INNER_LOOP_010_EXIT]] ] +; CHECK-NEXT: ret i32 [[RES_0_LCSSA]] +; CHECK: for.body.i: +; CHECK-NEXT: [[INDVARS_IV_I:%.*]] = phi i64 [ 0, [[FOR_BODY_I_PREHEADER]] ], [ [[INDVARS_IV_NEXT_I_4:%.*]], [[FOR_BODY_I]] ] +; CHECK-NEXT: [[ALL_0_OFF010_I:%.*]] = phi i1 [ true, [[FOR_BODY_I_PREHEADER]] ], [ [[ALL_0_OFF0__I_4:%.*]], [[FOR_BODY_I]] ] +; CHECK-NEXT: [[ANY_0_OFF09_I:%.*]] = phi i1 [ false, [[FOR_BODY_I_PREHEADER]] ], [ [[DOTANY_0_OFF0_I_4:%.*]], [[FOR_BODY_I]] ] +; CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds float, ptr [[X:%.*]], i64 [[INDVARS_IV_I]] +; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDX_I]], align 4 +; CHECK-NEXT: [[CMP1_I:%.*]] = fcmp fast olt float [[TMP0]], 0.000000e+00 +; CHECK-NEXT: [[INDVARS_IV_NEXT_I:%.*]] = add nuw nsw i64 [[INDVARS_IV_I]], 1 +; CHECK-NEXT: [[ARRAYIDX_I_1:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_I]] +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[ARRAYIDX_I_1]], align 4 +; CHECK-NEXT: [[CMP1_I_1:%.*]] = fcmp fast olt float [[TMP1]], 0.000000e+00 +; CHECK-NEXT: [[INDVARS_IV_NEXT_I_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_I]], 2 +; CHECK-NEXT: [[ARRAYIDX_I_2:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_I_1]] +; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[ARRAYIDX_I_2]], align 4 +; CHECK-NEXT: [[CMP1_I_2:%.*]] = fcmp fast olt float [[TMP2]], 0.000000e+00 +; CHECK-NEXT: [[INDVARS_IV_NEXT_I_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_I]], 3 +; CHECK-NEXT: [[ARRAYIDX_I_3:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_I_2]] +; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[ARRAYIDX_I_3]], align 4 +; CHECK-NEXT: [[CMP1_I_3:%.*]] = fcmp fast olt float [[TMP3]], 0.000000e+00 +; CHECK-NEXT: [[INDVARS_IV_NEXT_I_3:%.*]] = add nuw nsw i64 [[INDVARS_IV_I]], 4 +; CHECK-NEXT: [[ARRAYIDX_I_4:%.*]] = getelementptr inbounds float, ptr [[X]], i64 [[INDVARS_IV_NEXT_I_3]] +; CHECK-NEXT: [[TMP4:%.*]] = load float, ptr [[ARRAYIDX_I_4]], align 4 +; CHECK-NEXT: [[CMP1_I_4:%.*]] = fcmp fast olt float [[TMP4]], 0.000000e+00 +; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[CMP1_I_4]], i1 true, i1 [[CMP1_I_3]] +; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], i1 true, i1 [[CMP1_I_2]] +; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i1 true, i1 [[CMP1_I_1]] +; CHECK-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], i1 true, i1 [[CMP1_I]] +; CHECK-NEXT: [[DOTANY_0_OFF0_I_4]] = select i1 [[TMP8]], i1 true, i1 [[ANY_0_OFF09_I]] +; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[CMP1_I_4]], i1 [[CMP1_I_3]], i1 false +; CHECK-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i1 [[CMP1_I_2]], i1 false +; CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i1 [[CMP1_I_1]], i1 false +; CHECK-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i1 [[CMP1_I]], i1 false +; CHECK-NEXT: [[ALL_0_OFF0__I_4]] = select i1 [[TMP12]], i1 [[ALL_0_OFF010_I]], i1 false +; CHECK-NEXT: [[INDVARS_IV_NEXT_I_4]] = add nuw nsw i64 [[INDVARS_IV_I]], 5 +; CHECK-NEXT: [[EXITCOND_NOT_I_4:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_I_4]], 10000 +; CHECK-NEXT: br i1 [[EXITCOND_NOT_I_4]], label [[INNER_LOOP_010_EXIT]], label [[FOR_BODY_I]] +; CHECK: inner_loop_010.exit: +; CHECK-NEXT: [[TMP13:%.*]] = select i1 [[DOTANY_0_OFF0_I_4]], i32 2, i32 3 +; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[ALL_0_OFF0__I_4]], i32 1, i32 [[TMP13]] +; CHECK-NEXT: [[OR]] = or i32 [[TMP14]], [[RES_04]] +; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_05]], 1 +; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[ITERS]] +; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_I_PREHEADER]] +; +entry: + %cmp3 = icmp sgt i32 %iters, 0 + br i1 %cmp3, label %for.body.i.preheader, label %for.cond.cleanup + +for.body.i.preheader: ; preds = %entry, %inner_loop_010.exit + %i.05 = phi i32 [ %inc, %inner_loop_010.exit ], [ 0, %entry ] + %res.04 = phi i32 [ %or, %inner_loop_010.exit ], [ 0, %entry ] + br label %for.body.i + +for.cond.cleanup: ; preds = %inner_loop_010.exit, %entry + %res.0.lcssa = phi i32 [ 0, %entry ], [ %or, %inner_loop_010.exit ] + ret i32 %res.0.lcssa + +for.body.i: ; preds = %for.body.i, %for.body.i.preheader + %indvars.iv.i = phi i64 [ 0, %for.body.i.preheader ], [ %indvars.iv.next.i.4, %for.body.i ] + %all.0.off010.i = phi i1 [ true, %for.body.i.preheader ], [ %all.0.off0..i.4, %for.body.i ] + %any.0.off09.i = phi i1 [ false, %for.body.i.preheader ], [ %.any.0.off0.i.4, %for.body.i ] + %arrayidx.i = getelementptr inbounds float, ptr %x, i64 %indvars.iv.i + %0 = load float, ptr %arrayidx.i, align 4 + %cmp1.i = fcmp fast olt float %0, 0.000000e+00 + %indvars.iv.next.i = add nuw nsw i64 %indvars.iv.i, 1 + %arrayidx.i.1 = getelementptr inbounds float, ptr %x, i64 %indvars.iv.next.i + %1 = load float, ptr %arrayidx.i.1, align 4 + %cmp1.i.1 = fcmp fast olt float %1, 0.000000e+00 + %indvars.iv.next.i.1 = add nuw nsw i64 %indvars.iv.i, 2 + %arrayidx.i.2 = getelementptr inbounds float, ptr %x, i64 %indvars.iv.next.i.1 + %2 = load float, ptr %arrayidx.i.2, align 4 + %cmp1.i.2 = fcmp fast olt float %2, 0.000000e+00 + %indvars.iv.next.i.2 = add nuw nsw i64 %indvars.iv.i, 3 + %arrayidx.i.3 = getelementptr inbounds float, ptr %x, i64 %indvars.iv.next.i.2 + %3 = load float, ptr %arrayidx.i.3, align 4 + %cmp1.i.3 = fcmp fast olt float %3, 0.000000e+00 + %indvars.iv.next.i.3 = add nuw nsw i64 %indvars.iv.i, 4 + %arrayidx.i.4 = getelementptr inbounds float, ptr %x, i64 %indvars.iv.next.i.3 + %4 = load float, ptr %arrayidx.i.4, align 4 + %cmp1.i.4 = fcmp fast olt float %4, 0.000000e+00 + %5 = select i1 %cmp1.i.4, i1 true, i1 %cmp1.i.3 + %6 = select i1 %5, i1 true, i1 %cmp1.i.2 + %7 = select i1 %6, i1 true, i1 %cmp1.i.1 + %8 = select i1 %7, i1 true, i1 %cmp1.i + %.any.0.off0.i.4 = select i1 %8, i1 true, i1 %any.0.off09.i + %9 = select i1 %cmp1.i.4, i1 %cmp1.i.3, i1 false + %10 = select i1 %9, i1 %cmp1.i.2, i1 false + %11 = select i1 %10, i1 %cmp1.i.1, i1 false + %12 = select i1 %11, i1 %cmp1.i, i1 false + %all.0.off0..i.4 = select i1 %12, i1 %all.0.off010.i, i1 false + %indvars.iv.next.i.4 = add nuw nsw i64 %indvars.iv.i, 5 + %exitcond.not.i.4 = icmp eq i64 %indvars.iv.next.i.4, 10000 + br i1 %exitcond.not.i.4, label %inner_loop_010.exit, label %for.body.i + +inner_loop_010.exit: ; preds = %for.body.i + %13 = select i1 %.any.0.off0.i.4, i32 2, i32 3 + %14 = select i1 %all.0.off0..i.4, i32 1, i32 %13 + %or = or i32 %14, %res.04 + %inc = add nuw nsw i32 %i.05, 1 + %exitcond.not = icmp eq i32 %inc, %iters + br i1 %exitcond.not, label %for.cond.cleanup, label %for.body.i.preheader +} diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll @@ -0,0 +1,422 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +target triple = "aarch64-unknown-linux-gnu" + +;============ f16 + +define void @test_copysign_v4f16_v4f16(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v4f16_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: ldr d1, [x1] +; CHECK-NEXT: and z0.h, z0.h, #0x7fff +; CHECK-NEXT: and z1.h, z1.h, #0x8000 +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: str d0, [x0] +; CHECK-NEXT: ret + %a = load <4 x half>, ptr %ap + %b = load <4 x half>, ptr %bp + %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b) + store <4 x half> %r, ptr %ap + ret void +} + +define void @test_copysign_v8f16_v8f16(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v8f16_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x1] +; CHECK-NEXT: and z0.h, z0.h, #0x7fff +; CHECK-NEXT: and z1.h, z1.h, #0x8000 +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ret + %a = load <8 x half>, ptr %ap + %b = load <8 x half>, ptr %bp + %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b) + store <8 x half> %r, ptr %ap + ret void +} + +define void @test_copysign_v16f16_v16f16(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v16f16_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x1] +; CHECK-NEXT: and z0.h, z0.h, #0x8000 +; CHECK-NEXT: ldp q2, q3, [x0] +; CHECK-NEXT: and z1.h, z1.h, #0x8000 +; CHECK-NEXT: and z2.h, z2.h, #0x7fff +; CHECK-NEXT: orr z0.d, z2.d, z0.d +; CHECK-NEXT: and z3.h, z3.h, #0x7fff +; CHECK-NEXT: orr z1.d, z3.d, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %a = load <16 x half>, ptr %ap + %b = load <16 x half>, ptr %bp + %r = call <16 x half> @llvm.copysign.v16f16(<16 x half> %a, <16 x half> %b) + store <16 x half> %r, ptr %ap + ret void +} + +;============ f32 + +define void @test_copysign_v2f32_v2f32(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v2f32_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: ldr d1, [x1] +; CHECK-NEXT: and z0.s, z0.s, #0x7fffffff +; CHECK-NEXT: and z1.s, z1.s, #0x80000000 +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: str d0, [x0] +; CHECK-NEXT: ret + %a = load <2 x float>, ptr %ap + %b = load <2 x float>, ptr %bp + %r = call <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b) + store <2 x float> %r, ptr %ap + ret void +} + +define void @test_copysign_v4f32_v4f32(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v4f32_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x1] +; CHECK-NEXT: and z0.s, z0.s, #0x7fffffff +; CHECK-NEXT: and z1.s, z1.s, #0x80000000 +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ret + %a = load <4 x float>, ptr %ap + %b = load <4 x float>, ptr %bp + %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b) + store <4 x float> %r, ptr %ap + ret void +} + +define void @test_copysign_v8f32_v8f32(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v8f32_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x1] +; CHECK-NEXT: and z0.s, z0.s, #0x80000000 +; CHECK-NEXT: ldp q2, q3, [x0] +; CHECK-NEXT: and z1.s, z1.s, #0x80000000 +; CHECK-NEXT: and z2.s, z2.s, #0x7fffffff +; CHECK-NEXT: orr z0.d, z2.d, z0.d +; CHECK-NEXT: and z3.s, z3.s, #0x7fffffff +; CHECK-NEXT: orr z1.d, z3.d, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %a = load <8 x float>, ptr %ap + %b = load <8 x float>, ptr %bp + %r = call <8 x float> @llvm.copysign.v8f32(<8 x float> %a, <8 x float> %b) + store <8 x float> %r, ptr %ap + ret void +} + +;============ f64 + +define void @test_copysign_v2f64_v2f64(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v2f64_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x1] +; CHECK-NEXT: and z0.d, z0.d, #0x7fffffffffffffff +; CHECK-NEXT: and z1.d, z1.d, #0x8000000000000000 +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ret + %a = load <2 x double>, ptr %ap + %b = load <2 x double>, ptr %bp + %r = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b) + store <2 x double> %r, ptr %ap + ret void +} + +define void @test_copysign_v4f64_v4f64(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v4f64_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x1] +; CHECK-NEXT: and z0.d, z0.d, #0x8000000000000000 +; CHECK-NEXT: ldp q2, q3, [x0] +; CHECK-NEXT: and z1.d, z1.d, #0x8000000000000000 +; CHECK-NEXT: and z2.d, z2.d, #0x7fffffffffffffff +; CHECK-NEXT: orr z0.d, z2.d, z0.d +; CHECK-NEXT: and z3.d, z3.d, #0x7fffffffffffffff +; CHECK-NEXT: orr z1.d, z3.d, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %a = load <4 x double>, ptr %ap + %b = load <4 x double>, ptr %bp + %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b) + store <4 x double> %r, ptr %ap + ret void +} + +;============ v2f32 + +define void @test_copysign_v2f32_v2f64(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v2f32_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr q0, [x1] +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fcvt z0.s, p0/m, z0.d +; CHECK-NEXT: mov z1.d, z0.d[1] +; CHECK-NEXT: fmov x8, d0 +; CHECK-NEXT: fmov x9, d1 +; CHECK-NEXT: ldr d0, [x0] +; CHECK-NEXT: stp w8, w9, [sp, #8] +; CHECK-NEXT: and z0.s, z0.s, #0x7fffffff +; CHECK-NEXT: ldr d1, [sp, #8] +; CHECK-NEXT: and z1.s, z1.s, #0x80000000 +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: str d0, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %a = load <2 x float>, ptr %ap + %b = load <2 x double>, ptr %bp + %tmp0 = fptrunc <2 x double> %b to <2 x float> + %r = call <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %tmp0) + store <2 x float> %r, ptr %ap + ret void +} + +;============ v4f32 + +; SplitVecOp #1 +define void @test_copysign_v4f32_v4f64(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v4f32_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldp q1, q0, [x1] +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: fcvt z1.s, p0/m, z1.d +; CHECK-NEXT: fmov x10, d1 +; CHECK-NEXT: fcvt z0.s, p0/m, z0.d +; CHECK-NEXT: mov z2.d, z0.d[1] +; CHECK-NEXT: fmov x8, d0 +; CHECK-NEXT: fmov x9, d2 +; CHECK-NEXT: mov z2.d, z1.d[1] +; CHECK-NEXT: fmov x11, d2 +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: stp w8, w9, [sp, #8] +; CHECK-NEXT: stp w10, w11, [sp] +; CHECK-NEXT: and z0.s, z0.s, #0x7fffffff +; CHECK-NEXT: ldr q1, [sp] +; CHECK-NEXT: and z1.s, z1.s, #0x80000000 +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %a = load <4 x float>, ptr %ap + %b = load <4 x double>, ptr %bp + %tmp0 = fptrunc <4 x double> %b to <4 x float> + %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %tmp0) + store <4 x float> %r, ptr %ap + ret void +} + +;============ v2f64 + +define void @test_copysign_v2f64_v2f32(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v2f64_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr s0, [x1, #4] +; CHECK-NEXT: ldr q1, [x0] +; CHECK-NEXT: fcvt d0, s0 +; CHECK-NEXT: and z1.d, z1.d, #0x7fffffffffffffff +; CHECK-NEXT: str d0, [sp, #8] +; CHECK-NEXT: ldr s0, [x1] +; CHECK-NEXT: fcvt d0, s0 +; CHECK-NEXT: str d0, [sp] +; CHECK-NEXT: ldr q0, [sp] +; CHECK-NEXT: and z0.d, z0.d, #0x8000000000000000 +; CHECK-NEXT: orr z0.d, z1.d, z0.d +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %a = load <2 x double>, ptr %ap + %b = load < 2 x float>, ptr %bp + %tmp0 = fpext <2 x float> %b to <2 x double> + %r = call <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %tmp0) + store <2 x double> %r, ptr %ap + ret void +} + +;============ v4f64 + +; SplitVecRes mismatched +define void @test_copysign_v4f64_v4f32(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v4f64_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: ldr s0, [x1, #12] +; CHECK-NEXT: ldp q2, q1, [x0] +; CHECK-NEXT: fcvt d0, s0 +; CHECK-NEXT: and z2.d, z2.d, #0x7fffffffffffffff +; CHECK-NEXT: str d0, [sp, #24] +; CHECK-NEXT: and z1.d, z1.d, #0x7fffffffffffffff +; CHECK-NEXT: ldr s0, [x1, #8] +; CHECK-NEXT: fcvt d0, s0 +; CHECK-NEXT: str d0, [sp, #16] +; CHECK-NEXT: ldr s0, [x1, #4] +; CHECK-NEXT: fcvt d0, s0 +; CHECK-NEXT: str d0, [sp, #8] +; CHECK-NEXT: ldr s0, [x1] +; CHECK-NEXT: fcvt d0, s0 +; CHECK-NEXT: str d0, [sp] +; CHECK-NEXT: ldp q3, q0, [sp] +; CHECK-NEXT: and z3.d, z3.d, #0x8000000000000000 +; CHECK-NEXT: and z0.d, z0.d, #0x8000000000000000 +; CHECK-NEXT: orr z0.d, z1.d, z0.d +; CHECK-NEXT: orr z1.d, z2.d, z3.d +; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: ret + %a = load <4 x double>, ptr %ap + %b = load <4 x float>, ptr %bp + %tmp0 = fpext <4 x float> %b to <4 x double> + %r = call <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %tmp0) + store <4 x double> %r, ptr %ap + ret void +} + +;============ v4f16 + +define void @test_copysign_v4f16_v4f32(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v4f16_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr q0, [x1] +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fcvt z0.h, p0/m, z0.s +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: mov z1.s, z0.s[3] +; CHECK-NEXT: mov z2.s, z0.s[2] +; CHECK-NEXT: mov z0.s, z0.s[1] +; CHECK-NEXT: fmov w9, s1 +; CHECK-NEXT: ldr d1, [x0] +; CHECK-NEXT: fmov w10, s2 +; CHECK-NEXT: strh w8, [sp, #8] +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: strh w9, [sp, #14] +; CHECK-NEXT: and z1.h, z1.h, #0x7fff +; CHECK-NEXT: strh w10, [sp, #12] +; CHECK-NEXT: strh w8, [sp, #10] +; CHECK-NEXT: ldr d0, [sp, #8] +; CHECK-NEXT: and z0.h, z0.h, #0x8000 +; CHECK-NEXT: orr z0.d, z1.d, z0.d +; CHECK-NEXT: str d0, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %a = load <4 x half>, ptr %ap + %b = load <4 x float>, ptr %bp + %tmp0 = fptrunc <4 x float> %b to <4 x half> + %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %tmp0) + store <4 x half> %r, ptr %ap + ret void +} + +define void @test_copysign_v4f16_v4f64(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v4f16_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldp q1, q0, [x1] +; CHECK-NEXT: fcvt h3, d1 +; CHECK-NEXT: mov z1.d, z1.d[1] +; CHECK-NEXT: fcvt h1, d1 +; CHECK-NEXT: fcvt h2, d0 +; CHECK-NEXT: mov z0.d, z0.d[1] +; CHECK-NEXT: fcvt h0, d0 +; CHECK-NEXT: ldr d4, [x0] +; CHECK-NEXT: str h3, [sp, #8] +; CHECK-NEXT: str h1, [sp, #10] +; CHECK-NEXT: str h2, [sp, #12] +; CHECK-NEXT: and z4.h, z4.h, #0x7fff +; CHECK-NEXT: str h0, [sp, #14] +; CHECK-NEXT: ldr d0, [sp, #8] +; CHECK-NEXT: and z0.h, z0.h, #0x8000 +; CHECK-NEXT: orr z0.d, z4.d, z0.d +; CHECK-NEXT: str d0, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %a = load <4 x half>, ptr %ap + %b = load <4 x double>, ptr %bp + %tmp0 = fptrunc <4 x double> %b to <4 x half> + %r = call <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %tmp0) + store <4 x half> %r, ptr %ap + ret void +} + +;============ v8f16 + +define void @test_copysign_v8f16_v8f32(ptr %ap, ptr %bp) #0 { +; CHECK-LABEL: test_copysign_v8f16_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldp q0, q1, [x1] +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: fcvt z0.h, p0/m, z0.s +; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: mov z5.s, z0.s[2] +; CHECK-NEXT: fcvt z1.h, p0/m, z1.s +; CHECK-NEXT: mov z6.s, z0.s[1] +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: mov z2.s, z1.s[3] +; CHECK-NEXT: mov z3.s, z1.s[2] +; CHECK-NEXT: mov z4.s, z1.s[1] +; CHECK-NEXT: mov z1.s, z0.s[3] +; CHECK-NEXT: fmov w10, s2 +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: strh w8, [sp, #8] +; CHECK-NEXT: fmov w8, s3 +; CHECK-NEXT: strh w9, [sp] +; CHECK-NEXT: fmov w9, s4 +; CHECK-NEXT: strh w10, [sp, #14] +; CHECK-NEXT: fmov w10, s1 +; CHECK-NEXT: and z0.h, z0.h, #0x7fff +; CHECK-NEXT: strh w8, [sp, #12] +; CHECK-NEXT: fmov w8, s5 +; CHECK-NEXT: strh w9, [sp, #10] +; CHECK-NEXT: fmov w9, s6 +; CHECK-NEXT: strh w10, [sp, #6] +; CHECK-NEXT: strh w8, [sp, #4] +; CHECK-NEXT: strh w9, [sp, #2] +; CHECK-NEXT: ldr q1, [sp] +; CHECK-NEXT: and z1.h, z1.h, #0x8000 +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %a = load <8 x half>, ptr %ap + %b = load <8 x float>, ptr %bp + %tmp0 = fptrunc <8 x float> %b to <8 x half> + %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %tmp0) + store <8 x half> %r, ptr %ap + ret void +} + +declare <4 x half> @llvm.copysign.v4f16(<4 x half> %a, <4 x half> %b) #0 +declare <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b) #0 +declare <16 x half> @llvm.copysign.v16f16(<16 x half> %a, <16 x half> %b) #0 + +declare <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b) #0 +declare <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b) #0 +declare <8 x float> @llvm.copysign.v8f32(<8 x float> %a, <8 x float> %b) #0 + +declare <2 x double> @llvm.copysign.v2f64(<2 x double> %a, <2 x double> %b) #0 +declare <4 x double> @llvm.copysign.v4f64(<4 x double> %a, <4 x double> %b) #0 + +attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll @@ -0,0 +1,660 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +; +; FCMP OEQ +; + +define <2 x i16> @fcmp_oeq_v2f16(<2 x half> %op1, <2 x half> %op2) #0 { +; CHECK-LABEL: fcmp_oeq_v2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, z1.h +; CHECK-NEXT: punpklo p0.h, p0.b +; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %cmp = fcmp oeq <2 x half> %op1, %op2 + %sext = sext <2 x i1> %cmp to <2 x i16> + ret <2 x i16> %sext +} + +define <4 x i16> @fcmp_oeq_v4f16(<4 x half> %op1, <4 x half> %op2) #0 { +; CHECK-LABEL: fcmp_oeq_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, z1.h +; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %cmp = fcmp oeq <4 x half> %op1, %op2 + %sext = sext <4 x i1> %cmp to <4 x i16> + ret <4 x i16> %sext +} + +define <8 x i16> @fcmp_oeq_v8f16(<8 x half> %op1, <8 x half> %op2) #0 { +; CHECK-LABEL: fcmp_oeq_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: fcmeq p0.h, p0/z, z0.h, z1.h +; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %cmp = fcmp oeq <8 x half> %op1, %op2 + %sext = sext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %sext +} + +define void @fcmp_oeq_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_oeq_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmeq p1.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmeq p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp oeq <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +define <2 x i32> @fcmp_oeq_v2f32(<2 x float> %op1, <2 x float> %op2) #0 { +; CHECK-LABEL: fcmp_oeq_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, z1.s +; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %cmp = fcmp oeq <2 x float> %op1, %op2 + %sext = sext <2 x i1> %cmp to <2 x i32> + ret <2 x i32> %sext +} + +define <4 x i32> @fcmp_oeq_v4f32(<4 x float> %op1, <4 x float> %op2) #0 { +; CHECK-LABEL: fcmp_oeq_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, z1.s +; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %cmp = fcmp oeq <4 x float> %op1, %op2 + %sext = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %sext +} + +define void @fcmp_oeq_v8f32(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_oeq_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmeq p1.s, p0/z, z1.s, z0.s +; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmeq p0.s, p0/z, z2.s, z3.s +; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b + %cmp = fcmp oeq <8 x float> %op1, %op2 + %sext = sext <8 x i1> %cmp to <8 x i32> + store <8 x i32> %sext, ptr %c + ret void +} + +define <1 x i64> @fcmp_oeq_v1f64(<1 x double> %op1, <1 x double> %op2) #0 { +; CHECK-LABEL: fcmp_oeq_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d, vl1 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, z1.d +; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %cmp = fcmp oeq <1 x double> %op1, %op2 + %sext = sext <1 x i1> %cmp to <1 x i64> + ret <1 x i64> %sext +} + +define <2 x i64> @fcmp_oeq_v2f64(<2 x double> %op1, <2 x double> %op2) #0 { +; CHECK-LABEL: fcmp_oeq_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, z1.d +; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %cmp = fcmp oeq <2 x double> %op1, %op2 + %sext = sext <2 x i1> %cmp to <2 x i64> + ret <2 x i64> %sext +} + +define void @fcmp_oeq_v4f64(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_oeq_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmeq p1.d, p0/z, z1.d, z0.d +; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmeq p0.d, p0/z, z2.d, z3.d +; CHECK-NEXT: mov z1.d, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b + %cmp = fcmp oeq <4 x double> %op1, %op2 + %sext = sext <4 x i1> %cmp to <4 x i64> + store <4 x i64> %sext, ptr %c + ret void +} + +; +; FCMP UEQ +; + +define void @fcmp_ueq_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_ueq_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmuo p1.h, p0/z, z1.h, z0.h +; CHECK-NEXT: fcmeq p2.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov p1.b, p2/m, p2.b +; CHECK-NEXT: fcmuo p2.h, p0/z, z2.h, z3.h +; CHECK-NEXT: fcmeq p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: sel p0.b, p0, p0.b, p2.b +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp ueq <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP ONE +; + +define void @fcmp_one_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_one_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h +; CHECK-NEXT: fcmgt p2.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov p1.b, p2/m, p2.b +; CHECK-NEXT: fcmgt p2.h, p0/z, z3.h, z2.h +; CHECK-NEXT: fcmgt p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: sel p0.b, p0, p0.b, p2.b +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp one <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP UNE +; + +define void @fcmp_une_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_une_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmne p1.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp une <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP OGT +; + +define void @fcmp_ogt_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_ogt_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmgt p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp ogt <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP UGT +; + +define void @fcmp_ugt_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_ugt_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: adrp x8, .LCPI14_0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI14_0] +; CHECK-NEXT: fcmge p0.h, p0/z, z3.h, z2.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: eor z0.d, z0.d, z4.d +; CHECK-NEXT: eor z1.d, z1.d, z4.d +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp ugt <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP OLT +; + +define void @fcmp_olt_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_olt_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmgt p0.h, p0/z, z3.h, z2.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp olt <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP ULT +; + +define void @fcmp_ult_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_ult_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: adrp x8, .LCPI16_0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI16_0] +; CHECK-NEXT: fcmge p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: eor z0.d, z0.d, z4.d +; CHECK-NEXT: eor z1.d, z1.d, z4.d +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp ult <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP OGE +; + +define void @fcmp_oge_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_oge_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmge p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp oge <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP UGE +; + +define void @fcmp_uge_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_uge_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: adrp x8, .LCPI18_0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI18_0] +; CHECK-NEXT: fcmgt p0.h, p0/z, z3.h, z2.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: eor z0.d, z0.d, z4.d +; CHECK-NEXT: eor z1.d, z1.d, z4.d +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp uge <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP OLE +; + +define void @fcmp_ole_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_ole_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmge p0.h, p0/z, z3.h, z2.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp ole <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP ULE +; + +define void @fcmp_ule_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_ule_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: adrp x8, .LCPI20_0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI20_0] +; CHECK-NEXT: fcmgt p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: eor z0.d, z0.d, z4.d +; CHECK-NEXT: eor z1.d, z1.d, z4.d +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp ule <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP UNO +; + +define void @fcmp_uno_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_uno_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmuo p1.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmuo p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp uno <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP ORD +; + +define void @fcmp_ord_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_ord_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: adrp x8, .LCPI22_0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmuo p1.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI22_0] +; CHECK-NEXT: fcmuo p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: eor z0.d, z0.d, z4.d +; CHECK-NEXT: eor z1.d, z1.d, z4.d +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp ord <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP EQ +; + +define void @fcmp_eq_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_eq_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmeq p1.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmeq p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp fast oeq <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP NE +; + +define void @fcmp_ne_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_ne_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmne p1.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp fast one <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP GT +; + +define void @fcmp_gt_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_gt_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmgt p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp fast ogt <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP LT +; + +define void @fcmp_lt_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_lt_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmgt p0.h, p0/z, z3.h, z2.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp fast olt <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP GE +; + +define void @fcmp_ge_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_ge_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z0.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmge p0.h, p0/z, z2.h, z3.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp fast oge <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +; +; FCMP LE +; + +define void @fcmp_le_v16f16(ptr %a, ptr %b, ptr %c) #0 { +; CHECK-LABEL: fcmp_le_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q3, [x1] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmge p0.h, p0/z, z3.h, z2.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x2] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %cmp = fcmp fast ole <16 x half> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, ptr %c + ret void +} + +attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll @@ -0,0 +1,514 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +; +; FADDA +; + +define half @fadda_v4f16(half %start, <4 x half> %a) #0 { +; CHECK-LABEL: fadda_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: fadda h0, p0, h0, z1.h +; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ret + %res = call half @llvm.vector.reduce.fadd.v4f16(half %start, <4 x half> %a) + ret half %res +} + +define half @fadda_v8f16(half %start, <8 x half> %a) #0 { +; CHECK-LABEL: fadda_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: fadda h0, p0, h0, z1.h +; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ret + %res = call half @llvm.vector.reduce.fadd.v8f16(half %start, <8 x half> %a) + ret half %res +} + +define half @fadda_v16f16(half %start, <16 x half>* %a) #0 { +; CHECK-LABEL: fadda_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: // kill: def $h0 killed $h0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: fadda h0, p0, h0, z1.h +; CHECK-NEXT: fadda h0, p0, h0, z2.h +; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ret + %op = load <16 x half>, <16 x half>* %a + %res = call half @llvm.vector.reduce.fadd.v16f16(half %start, <16 x half> %op) + ret half %res +} + +define float @fadda_v2f32(float %start, <2 x float> %a) #0 { +; CHECK-LABEL: fadda_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: fadda s0, p0, s0, z1.s +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ret + %res = call float @llvm.vector.reduce.fadd.v2f32(float %start, <2 x float> %a) + ret float %res +} + +define float @fadda_v4f32(float %start, <4 x float> %a) #0 { +; CHECK-LABEL: fadda_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: fadda s0, p0, s0, z1.s +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ret + %res = call float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %a) + ret float %res +} + +define float @fadda_v8f32(float %start, <8 x float>* %a) #0 { +; CHECK-LABEL: fadda_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: // kill: def $s0 killed $s0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: fadda s0, p0, s0, z1.s +; CHECK-NEXT: fadda s0, p0, s0, z2.s +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ret + %op = load <8 x float>, <8 x float>* %a + %res = call float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %op) + ret float %res +} + +define double @fadda_v1f64(double %start, <1 x double> %a) #0 { +; CHECK-LABEL: fadda_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: fadd d0, d0, d1 +; CHECK-NEXT: ret + %res = call double @llvm.vector.reduce.fadd.v1f64(double %start, <1 x double> %a) + ret double %res +} + +define double @fadda_v2f64(double %start, <2 x double> %a) #0 { +; CHECK-LABEL: fadda_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: fadda d0, p0, d0, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call double @llvm.vector.reduce.fadd.v2f64(double %start, <2 x double> %a) + ret double %res +} + +define double @fadda_v4f64(double %start, <4 x double>* %a) #0 { +; CHECK-LABEL: fadda_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: fadda d0, p0, d0, z1.d +; CHECK-NEXT: fadda d0, p0, d0, z2.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %op = load <4 x double>, <4 x double>* %a + %res = call double @llvm.vector.reduce.fadd.v4f64(double %start, <4 x double> %op) + ret double %res +} + +; +; FADDV +; + +define half @faddv_v4f16(half %start, <4 x half> %a) #0 { +; CHECK-LABEL: faddv_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: faddv h1, p0, z1.h +; CHECK-NEXT: fadd h0, h0, h1 +; CHECK-NEXT: ret + %res = call fast half @llvm.vector.reduce.fadd.v4f16(half %start, <4 x half> %a) + ret half %res +} + +define half @faddv_v8f16(half %start, <8 x half> %a) #0 { +; CHECK-LABEL: faddv_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: faddv h1, p0, z1.h +; CHECK-NEXT: fadd h0, h0, h1 +; CHECK-NEXT: ret + %res = call fast half @llvm.vector.reduce.fadd.v8f16(half %start, <8 x half> %a) + ret half %res +} + +define half @faddv_v16f16(half %start, <16 x half>* %a) #0 { +; CHECK-LABEL: faddv_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q2, q1, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: fadd z1.h, p0/m, z1.h, z2.h +; CHECK-NEXT: faddv h1, p0, z1.h +; CHECK-NEXT: fadd h0, h0, h1 +; CHECK-NEXT: ret + %op = load <16 x half>, <16 x half>* %a + %res = call fast half @llvm.vector.reduce.fadd.v16f16(half %start, <16 x half> %op) + ret half %res +} + +define float @faddv_v2f32(float %start, <2 x float> %a) #0 { +; CHECK-LABEL: faddv_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: faddv s1, p0, z1.s +; CHECK-NEXT: fadd s0, s0, s1 +; CHECK-NEXT: ret + %res = call fast float @llvm.vector.reduce.fadd.v2f32(float %start, <2 x float> %a) + ret float %res +} + +define float @faddv_v4f32(float %start, <4 x float> %a) #0 { +; CHECK-LABEL: faddv_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: faddv s1, p0, z1.s +; CHECK-NEXT: fadd s0, s0, s1 +; CHECK-NEXT: ret + %res = call fast float @llvm.vector.reduce.fadd.v4f32(float %start, <4 x float> %a) + ret float %res +} + +define float @faddv_v8f32(float %start, <8 x float>* %a) #0 { +; CHECK-LABEL: faddv_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q2, q1, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: fadd z1.s, p0/m, z1.s, z2.s +; CHECK-NEXT: faddv s1, p0, z1.s +; CHECK-NEXT: fadd s0, s0, s1 +; CHECK-NEXT: ret + %op = load <8 x float>, <8 x float>* %a + %res = call fast float @llvm.vector.reduce.fadd.v8f32(float %start, <8 x float> %op) + ret float %res +} + +define double @faddv_v1f64(double %start, <1 x double> %a) #0 { +; CHECK-LABEL: faddv_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: fadd d0, d0, d1 +; CHECK-NEXT: ret + %res = call fast double @llvm.vector.reduce.fadd.v1f64(double %start, <1 x double> %a) + ret double %res +} + +define double @faddv_v2f64(double %start, <2 x double> %a) #0 { +; CHECK-LABEL: faddv_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: faddv d1, p0, z1.d +; CHECK-NEXT: fadd d0, d0, d1 +; CHECK-NEXT: ret + %res = call fast double @llvm.vector.reduce.fadd.v2f64(double %start, <2 x double> %a) + ret double %res +} + +define double @faddv_v4f64(double %start, <4 x double>* %a) #0 { +; CHECK-LABEL: faddv_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q2, q1, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: fadd z1.d, p0/m, z1.d, z2.d +; CHECK-NEXT: faddv d1, p0, z1.d +; CHECK-NEXT: fadd d0, d0, d1 +; CHECK-NEXT: ret + %op = load <4 x double>, <4 x double>* %a + %res = call fast double @llvm.vector.reduce.fadd.v4f64(double %start, <4 x double> %op) + ret double %res +} + +; +; FMAXV +; + +define half @fmaxv_v4f16(<4 x half> %a) #0 { +; CHECK-LABEL: fmaxv_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: fmaxnmv h0, p0, z0.h +; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ret + %res = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %a) + ret half %res +} + +define half @fmaxv_v8f16(<8 x half> %a) #0 { +; CHECK-LABEL: fmaxv_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: fmaxnmv h0, p0, z0.h +; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ret + %res = call half @llvm.vector.reduce.fmax.v8f16(<8 x half> %a) + ret half %res +} + +define half @fmaxv_v16f16(<16 x half>* %a) #0 { +; CHECK-LABEL: fmaxv_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: fmaxnm z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: fmaxnmv h0, p0, z0.h +; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ret + %op = load <16 x half>, <16 x half>* %a + %res = call half @llvm.vector.reduce.fmax.v16f16(<16 x half> %op) + ret half %res +} + +define float @fmaxv_v2f32(<2 x float> %a) #0 { +; CHECK-LABEL: fmaxv_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: fmaxnmv s0, p0, z0.s +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ret + %res = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %a) + ret float %res +} + +define float @fmaxv_v4f32(<4 x float> %a) #0 { +; CHECK-LABEL: fmaxv_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: fmaxnmv s0, p0, z0.s +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ret + %res = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a) + ret float %res +} + +define float @fmaxv_v8f32(<8 x float>* %a) #0 { +; CHECK-LABEL: fmaxv_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: fmaxnm z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: fmaxnmv s0, p0, z0.s +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ret + %op = load <8 x float>, <8 x float>* %a + %res = call float @llvm.vector.reduce.fmax.v8f32(<8 x float> %op) + ret float %res +} + +define double @fmaxv_v1f64(<1 x double> %a) #0 { +; CHECK-LABEL: fmaxv_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a) + ret double %res +} + +define double @fmaxv_v2f64(<2 x double> %a) #0 { +; CHECK-LABEL: fmaxv_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: fmaxnmv d0, p0, z0.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a) + ret double %res +} + +define double @fmaxv_v4f64(<4 x double>* %a) #0 { +; CHECK-LABEL: fmaxv_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: fmaxnm z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: fmaxnmv d0, p0, z0.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %op = load <4 x double>, <4 x double>* %a + %res = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %op) + ret double %res +} + +; +; FMINV +; + +define half @fminv_v4f16(<4 x half> %a) #0 { +; CHECK-LABEL: fminv_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: fminnmv h0, p0, z0.h +; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ret + %res = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %a) + ret half %res +} + +define half @fminv_v8f16(<8 x half> %a) #0 { +; CHECK-LABEL: fminv_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: fminnmv h0, p0, z0.h +; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ret + %res = call half @llvm.vector.reduce.fmin.v8f16(<8 x half> %a) + ret half %res +} + +define half @fminv_v16f16(<16 x half>* %a) #0 { +; CHECK-LABEL: fminv_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: fminnm z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: fminnmv h0, p0, z0.h +; CHECK-NEXT: // kill: def $h0 killed $h0 killed $z0 +; CHECK-NEXT: ret + %op = load <16 x half>, <16 x half>* %a + %res = call half @llvm.vector.reduce.fmin.v16f16(<16 x half> %op) + ret half %res +} + +define float @fminv_v2f32(<2 x float> %a) #0 { +; CHECK-LABEL: fminv_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: fminnmv s0, p0, z0.s +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ret + %res = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a) + ret float %res +} + +define float @fminv_v4f32(<4 x float> %a) #0 { +; CHECK-LABEL: fminv_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: fminnmv s0, p0, z0.s +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ret + %res = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a) + ret float %res +} + +define float @fminv_v8f32(<8 x float>* %a) #0 { +; CHECK-LABEL: fminv_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: fminnm z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: fminnmv s0, p0, z0.s +; CHECK-NEXT: // kill: def $s0 killed $s0 killed $z0 +; CHECK-NEXT: ret + %op = load <8 x float>, <8 x float>* %a + %res = call float @llvm.vector.reduce.fmin.v8f32(<8 x float> %op) + ret float %res +} + +define double @fminv_v1f64(<1 x double> %a) #0 { +; CHECK-LABEL: fminv_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a) + ret double %res +} + +define double @fminv_v2f64(<2 x double> %a) #0 { +; CHECK-LABEL: fminv_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: fminnmv d0, p0, z0.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a) + ret double %res +} + +define double @fminv_v4f64(<4 x double>* %a) #0 { +; CHECK-LABEL: fminv_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: fminnm z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: fminnmv d0, p0, z0.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %op = load <4 x double>, <4 x double>* %a + %res = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %op) + ret double %res +} + +attributes #0 = { "target-features"="+sve" } + +declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>) +declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>) +declare half @llvm.vector.reduce.fadd.v16f16(half, <16 x half>) + +declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>) +declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>) +declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>) + +declare double @llvm.vector.reduce.fadd.v1f64(double, <1 x double>) +declare double @llvm.vector.reduce.fadd.v2f64(double, <2 x double>) +declare double @llvm.vector.reduce.fadd.v4f64(double, <4 x double>) + +declare half @llvm.vector.reduce.fmax.v4f16(<4 x half>) +declare half @llvm.vector.reduce.fmax.v8f16(<8 x half>) +declare half @llvm.vector.reduce.fmax.v16f16(<16 x half>) + +declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>) +declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>) +declare float @llvm.vector.reduce.fmax.v8f32(<8 x float>) + +declare double @llvm.vector.reduce.fmax.v1f64(<1 x double>) +declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>) +declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>) + +declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>) +declare half @llvm.vector.reduce.fmin.v8f16(<8 x half>) +declare half @llvm.vector.reduce.fmin.v16f16(<16 x half>) + +declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>) +declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>) +declare float @llvm.vector.reduce.fmin.v8f32(<8 x float>) + +declare double @llvm.vector.reduce.fmin.v1f64(<1 x double>) +declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>) +declare double @llvm.vector.reduce.fmin.v4f64(<4 x double>) diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll @@ -0,0 +1,1063 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +; +; CEIL -> FRINTP +; + +define <2 x half> @frintp_v2f16(<2 x half> %op) #0 { +; CHECK-LABEL: frintp_v2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frintp z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x half> @llvm.ceil.v2f16(<2 x half> %op) + ret <2 x half> %res +} + +define <4 x half> @frintp_v4f16(<4 x half> %op) #0 { +; CHECK-LABEL: frintp_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frintp z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x half> @llvm.ceil.v4f16(<4 x half> %op) + ret <4 x half> %res +} + +define <8 x half> @frintp_v8f16(<8 x half> %op) #0 { +; CHECK-LABEL: frintp_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frintp z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.ceil.v8f16(<8 x half> %op) + ret <8 x half> %res +} + +define void @frintp_v16f16(<16 x half>* %a) #0 { +; CHECK-LABEL: frintp_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frintp z0.h, p0/m, z0.h +; CHECK-NEXT: frintp z1.h, p0/m, z1.h +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <16 x half>, <16 x half>* %a + %res = call <16 x half> @llvm.ceil.v16f16(<16 x half> %op) + store <16 x half> %res, <16 x half>* %a + ret void +} + +define <2 x float> @frintp_v2f32(<2 x float> %op) #0 { +; CHECK-LABEL: frintp_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: frintp z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x float> @llvm.ceil.v2f32(<2 x float> %op) + ret <2 x float> %res +} + +define <4 x float> @frintp_v4f32(<4 x float> %op) #0 { +; CHECK-LABEL: frintp_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frintp z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.ceil.v4f32(<4 x float> %op) + ret <4 x float> %res +} + +define void @frintp_v8f32(<8 x float>* %a) #0 { +; CHECK-LABEL: frintp_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frintp z0.s, p0/m, z0.s +; CHECK-NEXT: frintp z1.s, p0/m, z1.s +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <8 x float>, <8 x float>* %a + %res = call <8 x float> @llvm.ceil.v8f32(<8 x float> %op) + store <8 x float> %res, <8 x float>* %a + ret void +} + +define <1 x double> @frintp_v1f64(<1 x double> %op) #0 { +; CHECK-LABEL: frintp_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: frintp d0, d0 +; CHECK-NEXT: ret + %res = call <1 x double> @llvm.ceil.v1f64(<1 x double> %op) + ret <1 x double> %res +} + +define <2 x double> @frintp_v2f64(<2 x double> %op) #0 { +; CHECK-LABEL: frintp_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frintp z0.d, p0/m, z0.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.ceil.v2f64(<2 x double> %op) + ret <2 x double> %res +} + +define void @frintp_v4f64(<4 x double>* %a) #0 { +; CHECK-LABEL: frintp_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frintp z0.d, p0/m, z0.d +; CHECK-NEXT: frintp z1.d, p0/m, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <4 x double>, <4 x double>* %a + %res = call <4 x double> @llvm.ceil.v4f64(<4 x double> %op) + store <4 x double> %res, <4 x double>* %a + ret void +} + +; +; FLOOR -> FRINTM +; + +define <2 x half> @frintm_v2f16(<2 x half> %op) #0 { +; CHECK-LABEL: frintm_v2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frintm z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x half> @llvm.floor.v2f16(<2 x half> %op) + ret <2 x half> %res +} + +define <4 x half> @frintm_v4f16(<4 x half> %op) #0 { +; CHECK-LABEL: frintm_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frintm z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x half> @llvm.floor.v4f16(<4 x half> %op) + ret <4 x half> %res +} + +define <8 x half> @frintm_v8f16(<8 x half> %op) #0 { +; CHECK-LABEL: frintm_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frintm z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.floor.v8f16(<8 x half> %op) + ret <8 x half> %res +} + +define void @frintm_v16f16(<16 x half>* %a) #0 { +; CHECK-LABEL: frintm_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frintm z0.h, p0/m, z0.h +; CHECK-NEXT: frintm z1.h, p0/m, z1.h +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <16 x half>, <16 x half>* %a + %res = call <16 x half> @llvm.floor.v16f16(<16 x half> %op) + store <16 x half> %res, <16 x half>* %a + ret void +} + +define <2 x float> @frintm_v2f32(<2 x float> %op) #0 { +; CHECK-LABEL: frintm_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: frintm z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x float> @llvm.floor.v2f32(<2 x float> %op) + ret <2 x float> %res +} + +define <4 x float> @frintm_v4f32(<4 x float> %op) #0 { +; CHECK-LABEL: frintm_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frintm z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.floor.v4f32(<4 x float> %op) + ret <4 x float> %res +} + +define void @frintm_v8f32(<8 x float>* %a) #0 { +; CHECK-LABEL: frintm_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frintm z0.s, p0/m, z0.s +; CHECK-NEXT: frintm z1.s, p0/m, z1.s +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <8 x float>, <8 x float>* %a + %res = call <8 x float> @llvm.floor.v8f32(<8 x float> %op) + store <8 x float> %res, <8 x float>* %a + ret void +} + +define <1 x double> @frintm_v1f64(<1 x double> %op) #0 { +; CHECK-LABEL: frintm_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: frintm d0, d0 +; CHECK-NEXT: ret + %res = call <1 x double> @llvm.floor.v1f64(<1 x double> %op) + ret <1 x double> %res +} + +define <2 x double> @frintm_v2f64(<2 x double> %op) #0 { +; CHECK-LABEL: frintm_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frintm z0.d, p0/m, z0.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.floor.v2f64(<2 x double> %op) + ret <2 x double> %res +} + +define void @frintm_v4f64(<4 x double>* %a) #0 { +; CHECK-LABEL: frintm_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frintm z0.d, p0/m, z0.d +; CHECK-NEXT: frintm z1.d, p0/m, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <4 x double>, <4 x double>* %a + %res = call <4 x double> @llvm.floor.v4f64(<4 x double> %op) + store <4 x double> %res, <4 x double>* %a + ret void +} + +; +; FNEARBYINT -> FRINTI +; + +define <2 x half> @frinti_v2f16(<2 x half> %op) #0 { +; CHECK-LABEL: frinti_v2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frinti z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x half> @llvm.nearbyint.v2f16(<2 x half> %op) + ret <2 x half> %res +} + +define <4 x half> @frinti_v4f16(<4 x half> %op) #0 { +; CHECK-LABEL: frinti_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frinti z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x half> @llvm.nearbyint.v4f16(<4 x half> %op) + ret <4 x half> %res +} + +define <8 x half> @frinti_v8f16(<8 x half> %op) #0 { +; CHECK-LABEL: frinti_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frinti z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.nearbyint.v8f16(<8 x half> %op) + ret <8 x half> %res +} + +define void @frinti_v16f16(<16 x half>* %a) #0 { +; CHECK-LABEL: frinti_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frinti z0.h, p0/m, z0.h +; CHECK-NEXT: frinti z1.h, p0/m, z1.h +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <16 x half>, <16 x half>* %a + %res = call <16 x half> @llvm.nearbyint.v16f16(<16 x half> %op) + store <16 x half> %res, <16 x half>* %a + ret void +} + +define <2 x float> @frinti_v2f32(<2 x float> %op) #0 { +; CHECK-LABEL: frinti_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: frinti z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %op) + ret <2 x float> %res +} + +define <4 x float> @frinti_v4f32(<4 x float> %op) #0 { +; CHECK-LABEL: frinti_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frinti z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %op) + ret <4 x float> %res +} + +define void @frinti_v8f32(<8 x float>* %a) #0 { +; CHECK-LABEL: frinti_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frinti z0.s, p0/m, z0.s +; CHECK-NEXT: frinti z1.s, p0/m, z1.s +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <8 x float>, <8 x float>* %a + %res = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %op) + store <8 x float> %res, <8 x float>* %a + ret void +} + +define <1 x double> @frinti_v1f64(<1 x double> %op) #0 { +; CHECK-LABEL: frinti_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: frinti d0, d0 +; CHECK-NEXT: ret + %res = call <1 x double> @llvm.nearbyint.v1f64(<1 x double> %op) + ret <1 x double> %res +} + +define <2 x double> @frinti_v2f64(<2 x double> %op) #0 { +; CHECK-LABEL: frinti_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frinti z0.d, p0/m, z0.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %op) + ret <2 x double> %res +} + +define void @frinti_v4f64(<4 x double>* %a) #0 { +; CHECK-LABEL: frinti_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frinti z0.d, p0/m, z0.d +; CHECK-NEXT: frinti z1.d, p0/m, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <4 x double>, <4 x double>* %a + %res = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %op) + store <4 x double> %res, <4 x double>* %a + ret void +} + +; +; RINT -> FRINTX +; + +define <2 x half> @frintx_v2f16(<2 x half> %op) #0 { +; CHECK-LABEL: frintx_v2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frintx z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x half> @llvm.rint.v2f16(<2 x half> %op) + ret <2 x half> %res +} + +define <4 x half> @frintx_v4f16(<4 x half> %op) #0 { +; CHECK-LABEL: frintx_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frintx z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x half> @llvm.rint.v4f16(<4 x half> %op) + ret <4 x half> %res +} + +define <8 x half> @frintx_v8f16(<8 x half> %op) #0 { +; CHECK-LABEL: frintx_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frintx z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.rint.v8f16(<8 x half> %op) + ret <8 x half> %res +} + +define void @frintx_v16f16(<16 x half>* %a) #0 { +; CHECK-LABEL: frintx_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frintx z0.h, p0/m, z0.h +; CHECK-NEXT: frintx z1.h, p0/m, z1.h +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <16 x half>, <16 x half>* %a + %res = call <16 x half> @llvm.rint.v16f16(<16 x half> %op) + store <16 x half> %res, <16 x half>* %a + ret void +} + +define <2 x float> @frintx_v2f32(<2 x float> %op) #0 { +; CHECK-LABEL: frintx_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: frintx z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x float> @llvm.rint.v2f32(<2 x float> %op) + ret <2 x float> %res +} + +define <4 x float> @frintx_v4f32(<4 x float> %op) #0 { +; CHECK-LABEL: frintx_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frintx z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.rint.v4f32(<4 x float> %op) + ret <4 x float> %res +} + +define void @frintx_v8f32(<8 x float>* %a) #0 { +; CHECK-LABEL: frintx_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frintx z0.s, p0/m, z0.s +; CHECK-NEXT: frintx z1.s, p0/m, z1.s +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <8 x float>, <8 x float>* %a + %res = call <8 x float> @llvm.rint.v8f32(<8 x float> %op) + store <8 x float> %res, <8 x float>* %a + ret void +} + +define <1 x double> @frintx_v1f64(<1 x double> %op) #0 { +; CHECK-LABEL: frintx_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: frintx d0, d0 +; CHECK-NEXT: ret + %res = call <1 x double> @llvm.rint.v1f64(<1 x double> %op) + ret <1 x double> %res +} + +define <2 x double> @frintx_v2f64(<2 x double> %op) #0 { +; CHECK-LABEL: frintx_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frintx z0.d, p0/m, z0.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.rint.v2f64(<2 x double> %op) + ret <2 x double> %res +} + +define void @frintx_v4f64(<4 x double>* %a) #0 { +; CHECK-LABEL: frintx_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frintx z0.d, p0/m, z0.d +; CHECK-NEXT: frintx z1.d, p0/m, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <4 x double>, <4 x double>* %a + %res = call <4 x double> @llvm.rint.v4f64(<4 x double> %op) + store <4 x double> %res, <4 x double>* %a + ret void +} + +; +; ROUND -> FRINTA +; + +define <2 x half> @frinta_v2f16(<2 x half> %op) #0 { +; CHECK-LABEL: frinta_v2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frinta z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x half> @llvm.round.v2f16(<2 x half> %op) + ret <2 x half> %res +} + +define <4 x half> @frinta_v4f16(<4 x half> %op) #0 { +; CHECK-LABEL: frinta_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frinta z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x half> @llvm.round.v4f16(<4 x half> %op) + ret <4 x half> %res +} + +define <8 x half> @frinta_v8f16(<8 x half> %op) #0 { +; CHECK-LABEL: frinta_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frinta z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.round.v8f16(<8 x half> %op) + ret <8 x half> %res +} + +define void @frinta_v16f16(<16 x half>* %a) #0 { +; CHECK-LABEL: frinta_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frinta z0.h, p0/m, z0.h +; CHECK-NEXT: frinta z1.h, p0/m, z1.h +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <16 x half>, <16 x half>* %a + %res = call <16 x half> @llvm.round.v16f16(<16 x half> %op) + store <16 x half> %res, <16 x half>* %a + ret void +} + +define <2 x float> @frinta_v2f32(<2 x float> %op) #0 { +; CHECK-LABEL: frinta_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: frinta z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x float> @llvm.round.v2f32(<2 x float> %op) + ret <2 x float> %res +} + +define <4 x float> @frinta_v4f32(<4 x float> %op) #0 { +; CHECK-LABEL: frinta_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frinta z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.round.v4f32(<4 x float> %op) + ret <4 x float> %res +} + +define void @frinta_v8f32(<8 x float>* %a) #0 { +; CHECK-LABEL: frinta_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frinta z0.s, p0/m, z0.s +; CHECK-NEXT: frinta z1.s, p0/m, z1.s +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <8 x float>, <8 x float>* %a + %res = call <8 x float> @llvm.round.v8f32(<8 x float> %op) + store <8 x float> %res, <8 x float>* %a + ret void +} + +define <1 x double> @frinta_v1f64(<1 x double> %op) #0 { +; CHECK-LABEL: frinta_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: frinta d0, d0 +; CHECK-NEXT: ret + %res = call <1 x double> @llvm.round.v1f64(<1 x double> %op) + ret <1 x double> %res +} + +define <2 x double> @frinta_v2f64(<2 x double> %op) #0 { +; CHECK-LABEL: frinta_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frinta z0.d, p0/m, z0.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.round.v2f64(<2 x double> %op) + ret <2 x double> %res +} + +define void @frinta_v4f64(<4 x double>* %a) #0 { +; CHECK-LABEL: frinta_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frinta z0.d, p0/m, z0.d +; CHECK-NEXT: frinta z1.d, p0/m, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <4 x double>, <4 x double>* %a + %res = call <4 x double> @llvm.round.v4f64(<4 x double> %op) + store <4 x double> %res, <4 x double>* %a + ret void +} + +; +; ROUNDEVEN -> FRINTN +; + +define <2 x half> @frintn_v2f16(<2 x half> %op) #0 { +; CHECK-LABEL: frintn_v2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frintn z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x half> @llvm.roundeven.v2f16(<2 x half> %op) + ret <2 x half> %res +} + +define <4 x half> @frintn_v4f16(<4 x half> %op) #0 { +; CHECK-LABEL: frintn_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frintn z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x half> @llvm.roundeven.v4f16(<4 x half> %op) + ret <4 x half> %res +} + +define <8 x half> @frintn_v8f16(<8 x half> %op) #0 { +; CHECK-LABEL: frintn_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frintn z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.roundeven.v8f16(<8 x half> %op) + ret <8 x half> %res +} + +define void @frintn_v16f16(<16 x half>* %a) #0 { +; CHECK-LABEL: frintn_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frintn z0.h, p0/m, z0.h +; CHECK-NEXT: frintn z1.h, p0/m, z1.h +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <16 x half>, <16 x half>* %a + %res = call <16 x half> @llvm.roundeven.v16f16(<16 x half> %op) + store <16 x half> %res, <16 x half>* %a + ret void +} + +define <2 x float> @frintn_v2f32(<2 x float> %op) #0 { +; CHECK-LABEL: frintn_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: frintn z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %op) + ret <2 x float> %res +} + +define <4 x float> @frintn_v4f32(<4 x float> %op) #0 { +; CHECK-LABEL: frintn_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frintn z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %op) + ret <4 x float> %res +} + +define void @frintn_v8f32(<8 x float>* %a) #0 { +; CHECK-LABEL: frintn_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frintn z0.s, p0/m, z0.s +; CHECK-NEXT: frintn z1.s, p0/m, z1.s +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <8 x float>, <8 x float>* %a + %res = call <8 x float> @llvm.roundeven.v8f32(<8 x float> %op) + store <8 x float> %res, <8 x float>* %a + ret void +} + +define <1 x double> @frintn_v1f64(<1 x double> %op) #0 { +; CHECK-LABEL: frintn_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: frintn d0, d0 +; CHECK-NEXT: ret + %res = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %op) + ret <1 x double> %res +} + +define <2 x double> @frintn_v2f64(<2 x double> %op) #0 { +; CHECK-LABEL: frintn_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frintn z0.d, p0/m, z0.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %op) + ret <2 x double> %res +} + +define void @frintn_v4f64(<4 x double>* %a) #0 { +; CHECK-LABEL: frintn_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frintn z0.d, p0/m, z0.d +; CHECK-NEXT: frintn z1.d, p0/m, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <4 x double>, <4 x double>* %a + %res = call <4 x double> @llvm.roundeven.v4f64(<4 x double> %op) + store <4 x double> %res, <4 x double>* %a + ret void +} + +; +; TRUNC -> FRINTZ +; + +define <2 x half> @frintz_v2f16(<2 x half> %op) #0 { +; CHECK-LABEL: frintz_v2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frintz z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x half> @llvm.trunc.v2f16(<2 x half> %op) + ret <2 x half> %res +} + +define <4 x half> @frintz_v4f16(<4 x half> %op) #0 { +; CHECK-LABEL: frintz_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: frintz z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x half> @llvm.trunc.v4f16(<4 x half> %op) + ret <4 x half> %res +} + +define <8 x half> @frintz_v8f16(<8 x half> %op) #0 { +; CHECK-LABEL: frintz_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frintz z0.h, p0/m, z0.h +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <8 x half> @llvm.trunc.v8f16(<8 x half> %op) + ret <8 x half> %res +} + +define void @frintz_v16f16(<16 x half>* %a) #0 { +; CHECK-LABEL: frintz_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: frintz z0.h, p0/m, z0.h +; CHECK-NEXT: frintz z1.h, p0/m, z1.h +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <16 x half>, <16 x half>* %a + %res = call <16 x half> @llvm.trunc.v16f16(<16 x half> %op) + store <16 x half> %res, <16 x half>* %a + ret void +} + +define <2 x float> @frintz_v2f32(<2 x float> %op) #0 { +; CHECK-LABEL: frintz_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: frintz z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x float> @llvm.trunc.v2f32(<2 x float> %op) + ret <2 x float> %res +} + +define <4 x float> @frintz_v4f32(<4 x float> %op) #0 { +; CHECK-LABEL: frintz_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frintz z0.s, p0/m, z0.s +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <4 x float> @llvm.trunc.v4f32(<4 x float> %op) + ret <4 x float> %res +} + +define void @frintz_v8f32(<8 x float>* %a) #0 { +; CHECK-LABEL: frintz_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: frintz z0.s, p0/m, z0.s +; CHECK-NEXT: frintz z1.s, p0/m, z1.s +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <8 x float>, <8 x float>* %a + %res = call <8 x float> @llvm.trunc.v8f32(<8 x float> %op) + store <8 x float> %res, <8 x float>* %a + ret void +} + +define <1 x double> @frintz_v1f64(<1 x double> %op) #0 { +; CHECK-LABEL: frintz_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: frintz d0, d0 +; CHECK-NEXT: ret + %res = call <1 x double> @llvm.trunc.v1f64(<1 x double> %op) + ret <1 x double> %res +} + +define <2 x double> @frintz_v2f64(<2 x double> %op) #0 { +; CHECK-LABEL: frintz_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frintz z0.d, p0/m, z0.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %res = call <2 x double> @llvm.trunc.v2f64(<2 x double> %op) + ret <2 x double> %res +} + +define void @frintz_v4f64(<4 x double>* %a) #0 { +; CHECK-LABEL: frintz_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: frintz z0.d, p0/m, z0.d +; CHECK-NEXT: frintz z1.d, p0/m, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op = load <4 x double>, <4 x double>* %a + %res = call <4 x double> @llvm.trunc.v4f64(<4 x double> %op) + store <4 x double> %res, <4 x double>* %a + ret void +} + +attributes #0 = { "target-features"="+sve" } + +declare <2 x half> @llvm.ceil.v2f16(<2 x half>) +declare <4 x half> @llvm.ceil.v4f16(<4 x half>) +declare <8 x half> @llvm.ceil.v8f16(<8 x half>) +declare <16 x half> @llvm.ceil.v16f16(<16 x half>) +declare <32 x half> @llvm.ceil.v32f16(<32 x half>) +declare <64 x half> @llvm.ceil.v64f16(<64 x half>) +declare <128 x half> @llvm.ceil.v128f16(<128 x half>) +declare <2 x float> @llvm.ceil.v2f32(<2 x float>) +declare <4 x float> @llvm.ceil.v4f32(<4 x float>) +declare <8 x float> @llvm.ceil.v8f32(<8 x float>) +declare <16 x float> @llvm.ceil.v16f32(<16 x float>) +declare <32 x float> @llvm.ceil.v32f32(<32 x float>) +declare <64 x float> @llvm.ceil.v64f32(<64 x float>) +declare <1 x double> @llvm.ceil.v1f64(<1 x double>) +declare <2 x double> @llvm.ceil.v2f64(<2 x double>) +declare <4 x double> @llvm.ceil.v4f64(<4 x double>) +declare <8 x double> @llvm.ceil.v8f64(<8 x double>) +declare <16 x double> @llvm.ceil.v16f64(<16 x double>) +declare <32 x double> @llvm.ceil.v32f64(<32 x double>) + +declare <2 x half> @llvm.floor.v2f16(<2 x half>) +declare <4 x half> @llvm.floor.v4f16(<4 x half>) +declare <8 x half> @llvm.floor.v8f16(<8 x half>) +declare <16 x half> @llvm.floor.v16f16(<16 x half>) +declare <32 x half> @llvm.floor.v32f16(<32 x half>) +declare <64 x half> @llvm.floor.v64f16(<64 x half>) +declare <128 x half> @llvm.floor.v128f16(<128 x half>) +declare <2 x float> @llvm.floor.v2f32(<2 x float>) +declare <4 x float> @llvm.floor.v4f32(<4 x float>) +declare <8 x float> @llvm.floor.v8f32(<8 x float>) +declare <16 x float> @llvm.floor.v16f32(<16 x float>) +declare <32 x float> @llvm.floor.v32f32(<32 x float>) +declare <64 x float> @llvm.floor.v64f32(<64 x float>) +declare <1 x double> @llvm.floor.v1f64(<1 x double>) +declare <2 x double> @llvm.floor.v2f64(<2 x double>) +declare <4 x double> @llvm.floor.v4f64(<4 x double>) +declare <8 x double> @llvm.floor.v8f64(<8 x double>) +declare <16 x double> @llvm.floor.v16f64(<16 x double>) +declare <32 x double> @llvm.floor.v32f64(<32 x double>) + +declare <2 x half> @llvm.nearbyint.v2f16(<2 x half>) +declare <4 x half> @llvm.nearbyint.v4f16(<4 x half>) +declare <8 x half> @llvm.nearbyint.v8f16(<8 x half>) +declare <16 x half> @llvm.nearbyint.v16f16(<16 x half>) +declare <32 x half> @llvm.nearbyint.v32f16(<32 x half>) +declare <64 x half> @llvm.nearbyint.v64f16(<64 x half>) +declare <128 x half> @llvm.nearbyint.v128f16(<128 x half>) +declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) +declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) +declare <8 x float> @llvm.nearbyint.v8f32(<8 x float>) +declare <16 x float> @llvm.nearbyint.v16f32(<16 x float>) +declare <32 x float> @llvm.nearbyint.v32f32(<32 x float>) +declare <64 x float> @llvm.nearbyint.v64f32(<64 x float>) +declare <1 x double> @llvm.nearbyint.v1f64(<1 x double>) +declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) +declare <4 x double> @llvm.nearbyint.v4f64(<4 x double>) +declare <8 x double> @llvm.nearbyint.v8f64(<8 x double>) +declare <16 x double> @llvm.nearbyint.v16f64(<16 x double>) +declare <32 x double> @llvm.nearbyint.v32f64(<32 x double>) + +declare <2 x half> @llvm.rint.v2f16(<2 x half>) +declare <4 x half> @llvm.rint.v4f16(<4 x half>) +declare <8 x half> @llvm.rint.v8f16(<8 x half>) +declare <16 x half> @llvm.rint.v16f16(<16 x half>) +declare <32 x half> @llvm.rint.v32f16(<32 x half>) +declare <64 x half> @llvm.rint.v64f16(<64 x half>) +declare <128 x half> @llvm.rint.v128f16(<128 x half>) +declare <2 x float> @llvm.rint.v2f32(<2 x float>) +declare <4 x float> @llvm.rint.v4f32(<4 x float>) +declare <8 x float> @llvm.rint.v8f32(<8 x float>) +declare <16 x float> @llvm.rint.v16f32(<16 x float>) +declare <32 x float> @llvm.rint.v32f32(<32 x float>) +declare <64 x float> @llvm.rint.v64f32(<64 x float>) +declare <1 x double> @llvm.rint.v1f64(<1 x double>) +declare <2 x double> @llvm.rint.v2f64(<2 x double>) +declare <4 x double> @llvm.rint.v4f64(<4 x double>) +declare <8 x double> @llvm.rint.v8f64(<8 x double>) +declare <16 x double> @llvm.rint.v16f64(<16 x double>) +declare <32 x double> @llvm.rint.v32f64(<32 x double>) + +declare <2 x half> @llvm.round.v2f16(<2 x half>) +declare <4 x half> @llvm.round.v4f16(<4 x half>) +declare <8 x half> @llvm.round.v8f16(<8 x half>) +declare <16 x half> @llvm.round.v16f16(<16 x half>) +declare <32 x half> @llvm.round.v32f16(<32 x half>) +declare <64 x half> @llvm.round.v64f16(<64 x half>) +declare <128 x half> @llvm.round.v128f16(<128 x half>) +declare <2 x float> @llvm.round.v2f32(<2 x float>) +declare <4 x float> @llvm.round.v4f32(<4 x float>) +declare <8 x float> @llvm.round.v8f32(<8 x float>) +declare <16 x float> @llvm.round.v16f32(<16 x float>) +declare <32 x float> @llvm.round.v32f32(<32 x float>) +declare <64 x float> @llvm.round.v64f32(<64 x float>) +declare <1 x double> @llvm.round.v1f64(<1 x double>) +declare <2 x double> @llvm.round.v2f64(<2 x double>) +declare <4 x double> @llvm.round.v4f64(<4 x double>) +declare <8 x double> @llvm.round.v8f64(<8 x double>) +declare <16 x double> @llvm.round.v16f64(<16 x double>) +declare <32 x double> @llvm.round.v32f64(<32 x double>) + +declare <2 x half> @llvm.roundeven.v2f16(<2 x half>) +declare <4 x half> @llvm.roundeven.v4f16(<4 x half>) +declare <8 x half> @llvm.roundeven.v8f16(<8 x half>) +declare <16 x half> @llvm.roundeven.v16f16(<16 x half>) +declare <32 x half> @llvm.roundeven.v32f16(<32 x half>) +declare <64 x half> @llvm.roundeven.v64f16(<64 x half>) +declare <128 x half> @llvm.roundeven.v128f16(<128 x half>) +declare <2 x float> @llvm.roundeven.v2f32(<2 x float>) +declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) +declare <8 x float> @llvm.roundeven.v8f32(<8 x float>) +declare <16 x float> @llvm.roundeven.v16f32(<16 x float>) +declare <32 x float> @llvm.roundeven.v32f32(<32 x float>) +declare <64 x float> @llvm.roundeven.v64f32(<64 x float>) +declare <1 x double> @llvm.roundeven.v1f64(<1 x double>) +declare <2 x double> @llvm.roundeven.v2f64(<2 x double>) +declare <4 x double> @llvm.roundeven.v4f64(<4 x double>) +declare <8 x double> @llvm.roundeven.v8f64(<8 x double>) +declare <16 x double> @llvm.roundeven.v16f64(<16 x double>) +declare <32 x double> @llvm.roundeven.v32f64(<32 x double>) + +declare <2 x half> @llvm.trunc.v2f16(<2 x half>) +declare <4 x half> @llvm.trunc.v4f16(<4 x half>) +declare <8 x half> @llvm.trunc.v8f16(<8 x half>) +declare <16 x half> @llvm.trunc.v16f16(<16 x half>) +declare <32 x half> @llvm.trunc.v32f16(<32 x half>) +declare <64 x half> @llvm.trunc.v64f16(<64 x half>) +declare <128 x half> @llvm.trunc.v128f16(<128 x half>) +declare <2 x float> @llvm.trunc.v2f32(<2 x float>) +declare <4 x float> @llvm.trunc.v4f32(<4 x float>) +declare <8 x float> @llvm.trunc.v8f32(<8 x float>) +declare <16 x float> @llvm.trunc.v16f32(<16 x float>) +declare <32 x float> @llvm.trunc.v32f32(<32 x float>) +declare <64 x float> @llvm.trunc.v64f32(<64 x float>) +declare <1 x double> @llvm.trunc.v1f64(<1 x double>) +declare <2 x double> @llvm.trunc.v2f64(<2 x double>) +declare <4 x double> @llvm.trunc.v4f64(<4 x double>) +declare <8 x double> @llvm.trunc.v8f64(<8 x double>) +declare <16 x double> @llvm.trunc.v16f64(<16 x double>) +declare <32 x double> @llvm.trunc.v32f64(<32 x double>) diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll @@ -0,0 +1,286 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: adrp x9, .LCPI0_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI0_0] +; CHECK-NEXT: strh w8, [sp, #14] +; CHECK-NEXT: strh w8, [sp, #12] +; CHECK-NEXT: strh w8, [sp, #10] +; CHECK-NEXT: strh w8, [sp, #8] +; CHECK-NEXT: ldr d2, [sp, #8] +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <2 x half> %op1, <2 x half> %op2 + ret <2 x half> %sel +} + +define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: adrp x9, .LCPI1_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI1_0] +; CHECK-NEXT: strh w8, [sp, #14] +; CHECK-NEXT: strh w8, [sp, #12] +; CHECK-NEXT: strh w8, [sp, #10] +; CHECK-NEXT: strh w8, [sp, #8] +; CHECK-NEXT: ldr d2, [sp, #8] +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <4 x half> %op1, <4 x half> %op2 + ret <4 x half> %sel +} + +define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: adrp x9, .LCPI2_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI2_0] +; CHECK-NEXT: strh w8, [sp, #14] +; CHECK-NEXT: strh w8, [sp, #12] +; CHECK-NEXT: strh w8, [sp, #10] +; CHECK-NEXT: strh w8, [sp, #8] +; CHECK-NEXT: strh w8, [sp, #6] +; CHECK-NEXT: strh w8, [sp, #4] +; CHECK-NEXT: strh w8, [sp, #2] +; CHECK-NEXT: strh w8, [sp] +; CHECK-NEXT: ldr q2, [sp] +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <8 x half> %op1, <8 x half> %op2 + ret <8 x half> %sel +} + +define void @select_v16f16(ptr %a, ptr %b, i1 %mask) #0 { +; CHECK-LABEL: select_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w2, #0x1 +; CHECK-NEXT: adrp x9, .LCPI3_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x0, #16] +; CHECK-NEXT: ldr q2, [x1] +; CHECK-NEXT: ldr q3, [x1, #16] +; CHECK-NEXT: strh w8, [sp, #14] +; CHECK-NEXT: strh w8, [sp, #12] +; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI3_0] +; CHECK-NEXT: strh w8, [sp, #10] +; CHECK-NEXT: strh w8, [sp, #8] +; CHECK-NEXT: strh w8, [sp, #6] +; CHECK-NEXT: strh w8, [sp, #4] +; CHECK-NEXT: strh w8, [sp, #2] +; CHECK-NEXT: strh w8, [sp] +; CHECK-NEXT: ldr q4, [sp] +; CHECK-NEXT: eor z5.d, z4.d, z5.d +; CHECK-NEXT: and z1.d, z1.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z4.d +; CHECK-NEXT: and z2.d, z2.d, z5.d +; CHECK-NEXT: and z3.d, z3.d, z5.d +; CHECK-NEXT: orr z0.d, z0.d, z2.d +; CHECK-NEXT: orr z1.d, z1.d, z3.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %op1 = load volatile <16 x half>, ptr %a + %op2 = load volatile <16 x half>, ptr %b + %sel = select i1 %mask, <16 x half> %op1, <16 x half> %op2 + store <16 x half> %sel, ptr %a + ret void +} + +define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: adrp x9, .LCPI4_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI4_0] +; CHECK-NEXT: stp w8, w8, [sp, #8] +; CHECK-NEXT: ldr d2, [sp, #8] +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <2 x float> %op1, <2 x float> %op2 + ret <2 x float> %sel +} + +define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: adrp x9, .LCPI5_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI5_0] +; CHECK-NEXT: stp w8, w8, [sp, #8] +; CHECK-NEXT: stp w8, w8, [sp] +; CHECK-NEXT: ldr q2, [sp] +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <4 x float> %op1, <4 x float> %op2 + ret <4 x float> %sel +} + +define void @select_v8f32(ptr %a, ptr %b, i1 %mask) #0 { +; CHECK-LABEL: select_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w2, #0x1 +; CHECK-NEXT: adrp x9, .LCPI6_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x0, #16] +; CHECK-NEXT: ldr q2, [x1] +; CHECK-NEXT: ldr q3, [x1, #16] +; CHECK-NEXT: stp w8, w8, [sp, #8] +; CHECK-NEXT: stp w8, w8, [sp] +; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI6_0] +; CHECK-NEXT: ldr q4, [sp] +; CHECK-NEXT: eor z5.d, z4.d, z5.d +; CHECK-NEXT: and z1.d, z1.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z4.d +; CHECK-NEXT: and z2.d, z2.d, z5.d +; CHECK-NEXT: and z3.d, z3.d, z5.d +; CHECK-NEXT: orr z0.d, z0.d, z2.d +; CHECK-NEXT: orr z1.d, z1.d, z3.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %op1 = load volatile <8 x float>, ptr %a + %op2 = load volatile <8 x float>, ptr %b + %sel = select i1 %mask, <8 x float> %op1, <8 x float> %op2 + store <8 x float> %sel, ptr %a + ret void +} + +define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: mov x9, #-1 +; CHECK-NEXT: csetm x8, ne +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: fmov d3, x9 +; CHECK-NEXT: fmov d2, x8 +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %sel = select i1 %mask, <1 x double> %op1, <1 x double> %op2 + ret <1 x double> %sel +} + +define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: adrp x9, .LCPI8_0 +; CHECK-NEXT: csetm x8, ne +; CHECK-NEXT: stp x8, x8, [sp, #-16]! +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr q2, [sp] +; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI8_0] +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <2 x double> %op1, <2 x double> %op2 + ret <2 x double> %sel +} + +define void @select_v4f64(ptr %a, ptr %b, i1 %mask) #0 { +; CHECK-LABEL: select_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: tst w2, #0x1 +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: csetm x8, ne +; CHECK-NEXT: ldr q1, [x0, #16] +; CHECK-NEXT: ldr q2, [x1] +; CHECK-NEXT: adrp x9, .LCPI9_0 +; CHECK-NEXT: ldr q3, [x1, #16] +; CHECK-NEXT: stp x8, x8, [sp, #-16]! +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI9_0] +; CHECK-NEXT: ldr q5, [sp] +; CHECK-NEXT: eor z4.d, z5.d, z4.d +; CHECK-NEXT: and z1.d, z1.d, z5.d +; CHECK-NEXT: and z0.d, z0.d, z5.d +; CHECK-NEXT: and z2.d, z2.d, z4.d +; CHECK-NEXT: and z3.d, z3.d, z4.d +; CHECK-NEXT: orr z0.d, z0.d, z2.d +; CHECK-NEXT: orr z1.d, z1.d, z3.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %op1 = load volatile <4 x double>, ptr %a + %op2 = load volatile <4 x double>, ptr %b + %sel = select i1 %mask, <4 x double> %op1, <4 x double> %op2 + store <4 x double> %sel, ptr %a + ret void +} + +attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll @@ -0,0 +1,266 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, <2 x i1> %mask) #0 { +; CHECK-LABEL: select_v2f16: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: mov z3.s, z2.s[1] +; CHECK-NEXT: adrp x8, .LCPI0_0 +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: fmov w10, s3 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_0] +; CHECK-NEXT: adrp x8, .LCPI0_1 +; CHECK-NEXT: strh w9, [sp, #8] +; CHECK-NEXT: strh w10, [sp, #10] +; CHECK-NEXT: ldr d3, [sp, #8] +; CHECK-NEXT: ldr d4, [x8, :lo12:.LCPI0_1] +; CHECK-NEXT: lsl z3.h, p0/m, z3.h, z2.h +; CHECK-NEXT: asrr z2.h, p0/m, z2.h, z3.h +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select <2 x i1> %mask, <2 x half> %op1, <2 x half> %op2 + ret <2 x half> %sel +} + +define <4 x half> @select_v4f16(<4 x half> %op1, <4 x half> %op2, <4 x i1> %mask) #0 { +; CHECK-LABEL: select_v4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI1_0 +; CHECK-NEXT: adrp x9, .LCPI1_1 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI1_0] +; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI1_1] +; CHECK-NEXT: lsl z2.h, p0/m, z2.h, z3.h +; CHECK-NEXT: asr z2.h, p0/m, z2.h, z3.h +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %sel = select <4 x i1> %mask, <4 x half> %op1, <4 x half> %op2 + ret <4 x half> %sel +} + +define <8 x half> @select_v8f16(<8 x half> %op1, <8 x half> %op2, <8 x i1> %mask) #0 { +; CHECK-LABEL: select_v8f16: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI2_0 +; CHECK-NEXT: adrp x9, .LCPI2_1 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: uunpklo z2.h, z2.b +; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI2_0] +; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI2_1] +; CHECK-NEXT: lsl z2.h, p0/m, z2.h, z3.h +; CHECK-NEXT: asr z2.h, p0/m, z2.h, z3.h +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %sel = select <8 x i1> %mask, <8 x half> %op1, <8 x half> %op2 + ret <8 x half> %sel +} + +define void @select_v16f16(ptr %a, ptr %b) #0 { +; CHECK-LABEL: select_v16f16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x1] +; CHECK-NEXT: adrp x8, .LCPI3_0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI3_0] +; CHECK-NEXT: fcmeq p1.h, p0/z, z2.h, z1.h +; CHECK-NEXT: fcmeq p0.h, p0/z, z3.h, z0.h +; CHECK-NEXT: mov z5.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z6.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: and z2.d, z2.d, z5.d +; CHECK-NEXT: eor z5.d, z5.d, z4.d +; CHECK-NEXT: eor z4.d, z6.d, z4.d +; CHECK-NEXT: and z3.d, z3.d, z6.d +; CHECK-NEXT: and z0.d, z0.d, z4.d +; CHECK-NEXT: and z1.d, z1.d, z5.d +; CHECK-NEXT: orr z0.d, z3.d, z0.d +; CHECK-NEXT: orr z1.d, z2.d, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op1 = load <16 x half>, ptr %a + %op2 = load <16 x half>, ptr %b + %mask = fcmp oeq <16 x half> %op1, %op2 + %sel = select <16 x i1> %mask, <16 x half> %op1, <16 x half> %op2 + store <16 x half> %sel, ptr %a + ret void +} + +define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, <2 x i1> %mask) #0 { +; CHECK-LABEL: select_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI4_0 +; CHECK-NEXT: adrp x9, .LCPI4_1 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI4_0] +; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI4_1] +; CHECK-NEXT: lsl z2.s, p0/m, z2.s, z3.s +; CHECK-NEXT: asr z2.s, p0/m, z2.s, z3.s +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %sel = select <2 x i1> %mask, <2 x float> %op1, <2 x float> %op2 + ret <2 x float> %sel +} + +define <4 x float> @select_v4f32(<4 x float> %op1, <4 x float> %op2, <4 x i1> %mask) #0 { +; CHECK-LABEL: select_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI5_0 +; CHECK-NEXT: adrp x9, .LCPI5_1 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: uunpklo z2.s, z2.h +; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI5_0] +; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI5_1] +; CHECK-NEXT: lsl z2.s, p0/m, z2.s, z3.s +; CHECK-NEXT: asr z2.s, p0/m, z2.s, z3.s +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %sel = select <4 x i1> %mask, <4 x float> %op1, <4 x float> %op2 + ret <4 x float> %sel +} + +define void @select_v8f32(ptr %a, ptr %b) #0 { +; CHECK-LABEL: select_v8f32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x1] +; CHECK-NEXT: adrp x8, .LCPI6_0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI6_0] +; CHECK-NEXT: fcmeq p1.s, p0/z, z2.s, z1.s +; CHECK-NEXT: fcmeq p0.s, p0/z, z3.s, z0.s +; CHECK-NEXT: mov z5.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z6.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: and z2.d, z2.d, z5.d +; CHECK-NEXT: eor z5.d, z5.d, z4.d +; CHECK-NEXT: eor z4.d, z6.d, z4.d +; CHECK-NEXT: and z3.d, z3.d, z6.d +; CHECK-NEXT: and z0.d, z0.d, z4.d +; CHECK-NEXT: and z1.d, z1.d, z5.d +; CHECK-NEXT: orr z0.d, z3.d, z0.d +; CHECK-NEXT: orr z1.d, z2.d, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op1 = load <8 x float>, ptr %a + %op2 = load <8 x float>, ptr %b + %mask = fcmp oeq <8 x float> %op1, %op2 + %sel = select <8 x i1> %mask, <8 x float> %op1, <8 x float> %op2 + store <8 x float> %sel, ptr %a + ret void +} + +define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x i1> %mask) #0 { +; CHECK-LABEL: select_v1f64: +; CHECK: // %bb.0: +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: mov x9, #-1 +; CHECK-NEXT: csetm x8, ne +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: fmov d3, x9 +; CHECK-NEXT: fmov d2, x8 +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %sel = select <1 x i1> %mask, <1 x double> %op1, <1 x double> %op2 + ret <1 x double> %sel +} + +define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x i1> %mask) #0 { +; CHECK-LABEL: select_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI8_0 +; CHECK-NEXT: adrp x9, .LCPI8_1 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: uunpklo z2.d, z2.s +; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI8_0] +; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI8_1] +; CHECK-NEXT: lsl z2.d, p0/m, z2.d, z3.d +; CHECK-NEXT: asr z2.d, p0/m, z2.d, z3.d +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %sel = select <2 x i1> %mask, <2 x double> %op1, <2 x double> %op2 + ret <2 x double> %sel +} + +define void @select_v4f64(ptr %a, ptr %b) #0 { +; CHECK-LABEL: select_v4f64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q0, q1, [x1] +; CHECK-NEXT: adrp x8, .LCPI9_0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI9_0] +; CHECK-NEXT: fcmeq p1.d, p0/z, z2.d, z1.d +; CHECK-NEXT: fcmeq p0.d, p0/z, z3.d, z0.d +; CHECK-NEXT: mov z5.d, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z6.d, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: and z2.d, z2.d, z5.d +; CHECK-NEXT: eor z5.d, z5.d, z4.d +; CHECK-NEXT: eor z4.d, z6.d, z4.d +; CHECK-NEXT: and z3.d, z3.d, z6.d +; CHECK-NEXT: and z0.d, z0.d, z4.d +; CHECK-NEXT: and z1.d, z1.d, z5.d +; CHECK-NEXT: orr z0.d, z3.d, z0.d +; CHECK-NEXT: orr z1.d, z2.d, z1.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ret + %op1 = load <4 x double>, ptr %a + %op2 = load <4 x double>, ptr %b + %mask = fcmp oeq <4 x double> %op1, %op2 + %sel = select <4 x i1> %mask, <4 x double> %op1, <4 x double> %op2 + store <4 x double> %sel, ptr %a + ret void +} + +attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll @@ -0,0 +1,814 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +; +; UADDV +; + +define i8 @uaddv_v8i8(<8 x i8> %a) #0 { +; CHECK-LABEL: uaddv_v8i8: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.b, vl8 +; CHECK-NEXT: uaddv d0, p0, z0.b +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 +; CHECK-NEXT: ret + %res = call i8 @llvm.vector.reduce.add.v8i8(<8 x i8> %a) + ret i8 %res +} + +define i8 @uaddv_v16i8(<16 x i8> %a) #0 { +; CHECK-LABEL: uaddv_v16i8: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: uaddv d0, p0, z0.b +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 +; CHECK-NEXT: ret + %res = call i8 @llvm.vector.reduce.add.v16i8(<16 x i8> %a) + ret i8 %res +} + +define i8 @uaddv_v32i8(<32 x i8>* %a) #0 { +; CHECK-LABEL: uaddv_v32i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: add z0.b, z1.b, z0.b +; CHECK-NEXT: uaddv d0, p0, z0.b +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 +; CHECK-NEXT: ret + %op = load <32 x i8>, <32 x i8>* %a + %res = call i8 @llvm.vector.reduce.add.v32i8(<32 x i8> %op) + ret i8 %res +} + +define i16 @uaddv_v4i16(<4 x i16> %a) #0 { +; CHECK-LABEL: uaddv_v4i16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: uaddv d0, p0, z0.h +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 +; CHECK-NEXT: ret + %res = call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %a) + ret i16 %res +} + +define i16 @uaddv_v8i16(<8 x i16> %a) #0 { +; CHECK-LABEL: uaddv_v8i16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: uaddv d0, p0, z0.h +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 +; CHECK-NEXT: ret + %res = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %a) + ret i16 %res +} + +define i16 @uaddv_v16i16(<16 x i16>* %a) #0 { +; CHECK-LABEL: uaddv_v16i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: add z0.h, z1.h, z0.h +; CHECK-NEXT: uaddv d0, p0, z0.h +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 +; CHECK-NEXT: ret + %op = load <16 x i16>, <16 x i16>* %a + %res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %op) + ret i16 %res +} + +define i32 @uaddv_v2i32(<2 x i32> %a) #0 { +; CHECK-LABEL: uaddv_v2i32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: uaddv d0, p0, z0.s +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 +; CHECK-NEXT: ret + %res = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> %a) + ret i32 %res +} + +define i32 @uaddv_v4i32(<4 x i32> %a) #0 { +; CHECK-LABEL: uaddv_v4i32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: uaddv d0, p0, z0.s +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 +; CHECK-NEXT: ret + %res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a) + ret i32 %res +} + +define i32 @uaddv_v8i32(<8 x i32>* %a) #0 { +; CHECK-LABEL: uaddv_v8i32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: add z0.s, z1.s, z0.s +; CHECK-NEXT: uaddv d0, p0, z0.s +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 +; CHECK-NEXT: ret + %op = load <8 x i32>, <8 x i32>* %a + %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %op) + ret i32 %res +} + +define i64 @uaddv_v2i64(<2 x i64> %a) #0 { +; CHECK-LABEL: uaddv_v2i64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: uaddv d0, p0, z0.d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret + %res = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %a) + ret i64 %res +} + +define i64 @uaddv_v4i64(<4 x i64>* %a) #0 { +; CHECK-LABEL: uaddv_v4i64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: add z0.d, z1.d, z0.d +; CHECK-NEXT: uaddv d0, p0, z0.d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret + %op = load <4 x i64>, <4 x i64>* %a + %res = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %op) + ret i64 %res +} + +; +; SMAXV +; + +define i8 @smaxv_v8i8(<8 x i8> %a) #0 { +; CHECK-LABEL: smaxv_v8i8: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.b, vl8 +; CHECK-NEXT: smaxv b0, p0, z0.b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i8 @llvm.vector.reduce.smax.v8i8(<8 x i8> %a) + ret i8 %res +} + +define i8 @smaxv_v16i8(<16 x i8> %a) #0 { +; CHECK-LABEL: smaxv_v16i8: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: smaxv b0, p0, z0.b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %a) + ret i8 %res +} + +define i8 @smaxv_v32i8(<32 x i8>* %a) #0 { +; CHECK-LABEL: smaxv_v32i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: smaxv b0, p0, z0.b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %op = load <32 x i8>, <32 x i8>* %a + %res = call i8 @llvm.vector.reduce.smax.v32i8(<32 x i8> %op) + ret i8 %res +} + +define i16 @smaxv_v4i16(<4 x i16> %a) #0 { +; CHECK-LABEL: smaxv_v4i16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: smaxv h0, p0, z0.h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i16 @llvm.vector.reduce.smax.v4i16(<4 x i16> %a) + ret i16 %res +} + +define i16 @smaxv_v8i16(<8 x i16> %a) #0 { +; CHECK-LABEL: smaxv_v8i16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: smaxv h0, p0, z0.h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %a) + ret i16 %res +} + +define i16 @smaxv_v16i16(<16 x i16>* %a) #0 { +; CHECK-LABEL: smaxv_v16i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: smaxv h0, p0, z0.h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %op = load <16 x i16>, <16 x i16>* %a + %res = call i16 @llvm.vector.reduce.smax.v16i16(<16 x i16> %op) + ret i16 %res +} + +define i32 @smaxv_v2i32(<2 x i32> %a) #0 { +; CHECK-LABEL: smaxv_v2i32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: smaxv s0, p0, z0.s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i32 @llvm.vector.reduce.smax.v2i32(<2 x i32> %a) + ret i32 %res +} + +define i32 @smaxv_v4i32(<4 x i32> %a) #0 { +; CHECK-LABEL: smaxv_v4i32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: smaxv s0, p0, z0.s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %a) + ret i32 %res +} + +define i32 @smaxv_v8i32(<8 x i32>* %a) #0 { +; CHECK-LABEL: smaxv_v8i32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: smaxv s0, p0, z0.s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %op = load <8 x i32>, <8 x i32>* %a + %res = call i32 @llvm.vector.reduce.smax.v8i32(<8 x i32> %op) + ret i32 %res +} + +; No NEON 64-bit vector SMAXV support. Use SVE. +define i64 @smaxv_v2i64(<2 x i64> %a) #0 { +; CHECK-LABEL: smaxv_v2i64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: smaxv d0, p0, z0.d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret + %res = call i64 @llvm.vector.reduce.smax.v2i64(<2 x i64> %a) + ret i64 %res +} + +define i64 @smaxv_v4i64(<4 x i64>* %a) #0 { +; CHECK-LABEL: smaxv_v4i64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: smaxv d0, p0, z0.d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret + %op = load <4 x i64>, <4 x i64>* %a + %res = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> %op) + ret i64 %res +} + +; +; SMINV +; + +define i8 @sminv_v8i8(<8 x i8> %a) #0 { +; CHECK-LABEL: sminv_v8i8: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.b, vl8 +; CHECK-NEXT: sminv b0, p0, z0.b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i8 @llvm.vector.reduce.smin.v8i8(<8 x i8> %a) + ret i8 %res +} + +define i8 @sminv_v16i8(<16 x i8> %a) #0 { +; CHECK-LABEL: sminv_v16i8: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: sminv b0, p0, z0.b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %a) + ret i8 %res +} + +define i8 @sminv_v32i8(<32 x i8>* %a) #0 { +; CHECK-LABEL: sminv_v32i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: sminv b0, p0, z0.b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %op = load <32 x i8>, <32 x i8>* %a + %res = call i8 @llvm.vector.reduce.smin.v32i8(<32 x i8> %op) + ret i8 %res +} + +define i16 @sminv_v4i16(<4 x i16> %a) #0 { +; CHECK-LABEL: sminv_v4i16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: sminv h0, p0, z0.h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i16 @llvm.vector.reduce.smin.v4i16(<4 x i16> %a) + ret i16 %res +} + +define i16 @sminv_v8i16(<8 x i16> %a) #0 { +; CHECK-LABEL: sminv_v8i16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: sminv h0, p0, z0.h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %a) + ret i16 %res +} + +define i16 @sminv_v16i16(<16 x i16>* %a) #0 { +; CHECK-LABEL: sminv_v16i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: sminv h0, p0, z0.h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %op = load <16 x i16>, <16 x i16>* %a + %res = call i16 @llvm.vector.reduce.smin.v16i16(<16 x i16> %op) + ret i16 %res +} + +define i32 @sminv_v2i32(<2 x i32> %a) #0 { +; CHECK-LABEL: sminv_v2i32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: sminv s0, p0, z0.s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i32 @llvm.vector.reduce.smin.v2i32(<2 x i32> %a) + ret i32 %res +} + +define i32 @sminv_v4i32(<4 x i32> %a) #0 { +; CHECK-LABEL: sminv_v4i32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: sminv s0, p0, z0.s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %a) + ret i32 %res +} + +define i32 @sminv_v8i32(<8 x i32>* %a) #0 { +; CHECK-LABEL: sminv_v8i32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: sminv s0, p0, z0.s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %op = load <8 x i32>, <8 x i32>* %a + %res = call i32 @llvm.vector.reduce.smin.v8i32(<8 x i32> %op) + ret i32 %res +} + +; No NEON 64-bit vector SMINV support. Use SVE. +define i64 @sminv_v2i64(<2 x i64> %a) #0 { +; CHECK-LABEL: sminv_v2i64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: sminv d0, p0, z0.d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret + %res = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %a) + ret i64 %res +} + +define i64 @sminv_v4i64(<4 x i64>* %a) #0 { +; CHECK-LABEL: sminv_v4i64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: sminv d0, p0, z0.d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret + %op = load <4 x i64>, <4 x i64>* %a + %res = call i64 @llvm.vector.reduce.smin.v4i64(<4 x i64> %op) + ret i64 %res +} + +; +; UMAXV +; + +define i8 @umaxv_v8i8(<8 x i8> %a) #0 { +; CHECK-LABEL: umaxv_v8i8: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.b, vl8 +; CHECK-NEXT: umaxv b0, p0, z0.b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i8 @llvm.vector.reduce.umax.v8i8(<8 x i8> %a) + ret i8 %res +} + +define i8 @umaxv_v16i8(<16 x i8> %a) #0 { +; CHECK-LABEL: umaxv_v16i8: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: umaxv b0, p0, z0.b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %a) + ret i8 %res +} + +define i8 @umaxv_v32i8(<32 x i8>* %a) #0 { +; CHECK-LABEL: umaxv_v32i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: umaxv b0, p0, z0.b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %op = load <32 x i8>, <32 x i8>* %a + %res = call i8 @llvm.vector.reduce.umax.v32i8(<32 x i8> %op) + ret i8 %res +} + +define i16 @umaxv_v4i16(<4 x i16> %a) #0 { +; CHECK-LABEL: umaxv_v4i16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: umaxv h0, p0, z0.h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> %a) + ret i16 %res +} + +define i16 @umaxv_v8i16(<8 x i16> %a) #0 { +; CHECK-LABEL: umaxv_v8i16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: umaxv h0, p0, z0.h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %a) + ret i16 %res +} + +define i16 @umaxv_v16i16(<16 x i16>* %a) #0 { +; CHECK-LABEL: umaxv_v16i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: umaxv h0, p0, z0.h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %op = load <16 x i16>, <16 x i16>* %a + %res = call i16 @llvm.vector.reduce.umax.v16i16(<16 x i16> %op) + ret i16 %res +} + +define i32 @umaxv_v2i32(<2 x i32> %a) #0 { +; CHECK-LABEL: umaxv_v2i32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: umaxv s0, p0, z0.s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i32 @llvm.vector.reduce.umax.v2i32(<2 x i32> %a) + ret i32 %res +} + +define i32 @umaxv_v4i32(<4 x i32> %a) #0 { +; CHECK-LABEL: umaxv_v4i32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: umaxv s0, p0, z0.s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %a) + ret i32 %res +} + +define i32 @umaxv_v8i32(<8 x i32>* %a) #0 { +; CHECK-LABEL: umaxv_v8i32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: umaxv s0, p0, z0.s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %op = load <8 x i32>, <8 x i32>* %a + %res = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %op) + ret i32 %res +} + +; No NEON 64-bit vector UMAXV support. Use SVE. +define i64 @umaxv_v2i64(<2 x i64> %a) #0 { +; CHECK-LABEL: umaxv_v2i64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: umaxv d0, p0, z0.d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret + %res = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %a) + ret i64 %res +} + +define i64 @umaxv_v4i64(<4 x i64>* %a) #0 { +; CHECK-LABEL: umaxv_v4i64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: umaxv d0, p0, z0.d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret + %op = load <4 x i64>, <4 x i64>* %a + %res = call i64 @llvm.vector.reduce.umax.v4i64(<4 x i64> %op) + ret i64 %res +} + +; +; UMINV +; + +define i8 @uminv_v8i8(<8 x i8> %a) #0 { +; CHECK-LABEL: uminv_v8i8: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.b, vl8 +; CHECK-NEXT: uminv b0, p0, z0.b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i8 @llvm.vector.reduce.umin.v8i8(<8 x i8> %a) + ret i8 %res +} + +define i8 @uminv_v16i8(<16 x i8> %a) #0 { +; CHECK-LABEL: uminv_v16i8: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: uminv b0, p0, z0.b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %a) + ret i8 %res +} + +define i8 @uminv_v32i8(<32 x i8>* %a) #0 { +; CHECK-LABEL: uminv_v32i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: uminv b0, p0, z0.b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %op = load <32 x i8>, <32 x i8>* %a + %res = call i8 @llvm.vector.reduce.umin.v32i8(<32 x i8> %op) + ret i8 %res +} + +define i16 @uminv_v4i16(<4 x i16> %a) #0 { +; CHECK-LABEL: uminv_v4i16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: uminv h0, p0, z0.h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i16 @llvm.vector.reduce.umin.v4i16(<4 x i16> %a) + ret i16 %res +} + +define i16 @uminv_v8i16(<8 x i16> %a) #0 { +; CHECK-LABEL: uminv_v8i16: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: uminv h0, p0, z0.h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %a) + ret i16 %res +} + +define i16 @uminv_v16i16(<16 x i16>* %a) #0 { +; CHECK-LABEL: uminv_v16i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: uminv h0, p0, z0.h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %op = load <16 x i16>, <16 x i16>* %a + %res = call i16 @llvm.vector.reduce.umin.v16i16(<16 x i16> %op) + ret i16 %res +} + +define i32 @uminv_v2i32(<2 x i32> %a) #0 { +; CHECK-LABEL: uminv_v2i32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: uminv s0, p0, z0.s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i32 @llvm.vector.reduce.umin.v2i32(<2 x i32> %a) + ret i32 %res +} + +define i32 @uminv_v4i32(<4 x i32> %a) #0 { +; CHECK-LABEL: uminv_v4i32: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: uminv s0, p0, z0.s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %res = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %a) + ret i32 %res +} + +define i32 @uminv_v8i32(<8 x i32>* %a) #0 { +; CHECK-LABEL: uminv_v8i32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: uminv s0, p0, z0.s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %op = load <8 x i32>, <8 x i32>* %a + %res = call i32 @llvm.vector.reduce.umin.v8i32(<8 x i32> %op) + ret i32 %res +} + +; No NEON 64-bit vector UMINV support. Use SVE. +define i64 @uminv_v2i64(<2 x i64> %a) #0 { +; CHECK-LABEL: uminv_v2i64: +; CHECK: // %bb.0: +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: uminv d0, p0, z0.d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret + %res = call i64 @llvm.vector.reduce.umin.v2i64(<2 x i64> %a) + ret i64 %res +} + +define i64 @uminv_v4i64(<4 x i64>* %a) #0 { +; CHECK-LABEL: uminv_v4i64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: uminv d0, p0, z0.d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret + %op = load <4 x i64>, <4 x i64>* %a + %res = call i64 @llvm.vector.reduce.umin.v4i64(<4 x i64> %op) + ret i64 %res +} + +attributes #0 = { "target-features"="+sve" } + +declare i8 @llvm.vector.reduce.add.v8i8(<8 x i8>) +declare i8 @llvm.vector.reduce.add.v16i8(<16 x i8>) +declare i8 @llvm.vector.reduce.add.v32i8(<32 x i8>) + +declare i16 @llvm.vector.reduce.add.v4i16(<4 x i16>) +declare i16 @llvm.vector.reduce.add.v8i16(<8 x i16>) +declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>) + +declare i32 @llvm.vector.reduce.add.v2i32(<2 x i32>) +declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) +declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>) + +declare i64 @llvm.vector.reduce.add.v2i64(<2 x i64>) +declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>) + +declare i8 @llvm.vector.reduce.smax.v8i8(<8 x i8>) +declare i8 @llvm.vector.reduce.smax.v16i8(<16 x i8>) +declare i8 @llvm.vector.reduce.smax.v32i8(<32 x i8>) + +declare i16 @llvm.vector.reduce.smax.v4i16(<4 x i16>) +declare i16 @llvm.vector.reduce.smax.v8i16(<8 x i16>) +declare i16 @llvm.vector.reduce.smax.v16i16(<16 x i16>) + +declare i32 @llvm.vector.reduce.smax.v2i32(<2 x i32>) +declare i32 @llvm.vector.reduce.smax.v4i32(<4 x i32>) +declare i32 @llvm.vector.reduce.smax.v8i32(<8 x i32>) + +declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>) +declare i64 @llvm.vector.reduce.smax.v4i64(<4 x i64>) + +declare i8 @llvm.vector.reduce.smin.v8i8(<8 x i8>) +declare i8 @llvm.vector.reduce.smin.v16i8(<16 x i8>) +declare i8 @llvm.vector.reduce.smin.v32i8(<32 x i8>) + +declare i16 @llvm.vector.reduce.smin.v4i16(<4 x i16>) +declare i16 @llvm.vector.reduce.smin.v8i16(<8 x i16>) +declare i16 @llvm.vector.reduce.smin.v16i16(<16 x i16>) + +declare i32 @llvm.vector.reduce.smin.v2i32(<2 x i32>) +declare i32 @llvm.vector.reduce.smin.v4i32(<4 x i32>) +declare i32 @llvm.vector.reduce.smin.v8i32(<8 x i32>) + +declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>) +declare i64 @llvm.vector.reduce.smin.v4i64(<4 x i64>) + +declare i8 @llvm.vector.reduce.umax.v8i8(<8 x i8>) +declare i8 @llvm.vector.reduce.umax.v16i8(<16 x i8>) +declare i8 @llvm.vector.reduce.umax.v32i8(<32 x i8>) + +declare i16 @llvm.vector.reduce.umax.v4i16(<4 x i16>) +declare i16 @llvm.vector.reduce.umax.v8i16(<8 x i16>) +declare i16 @llvm.vector.reduce.umax.v16i16(<16 x i16>) + +declare i32 @llvm.vector.reduce.umax.v2i32(<2 x i32>) +declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>) +declare i32 @llvm.vector.reduce.umax.v8i32(<8 x i32>) + +declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>) +declare i64 @llvm.vector.reduce.umax.v4i64(<4 x i64>) + +declare i8 @llvm.vector.reduce.umin.v8i8(<8 x i8>) +declare i8 @llvm.vector.reduce.umin.v16i8(<16 x i8>) +declare i8 @llvm.vector.reduce.umin.v32i8(<32 x i8>) + +declare i16 @llvm.vector.reduce.umin.v4i16(<4 x i16>) +declare i16 @llvm.vector.reduce.umin.v8i16(<8 x i16>) +declare i16 @llvm.vector.reduce.umin.v16i16(<16 x i16>) + +declare i32 @llvm.vector.reduce.umin.v2i32(<2 x i32>) +declare i32 @llvm.vector.reduce.umin.v4i32(<4 x i32>) +declare i32 @llvm.vector.reduce.umin.v8i32(<8 x i32>) + +declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>) +declare i64 @llvm.vector.reduce.umin.v4i64(<4 x i64>) diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll @@ -0,0 +1,427 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v4i8: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: adrp x9, .LCPI0_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI0_0] +; CHECK-NEXT: strh w8, [sp, #14] +; CHECK-NEXT: strh w8, [sp, #12] +; CHECK-NEXT: strh w8, [sp, #10] +; CHECK-NEXT: strh w8, [sp, #8] +; CHECK-NEXT: ldr d2, [sp, #8] +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <4 x i8> %op1, <4 x i8> %op2 + ret <4 x i8> %sel +} + +define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v8i8: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: adrp x9, .LCPI1_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI1_0] +; CHECK-NEXT: strb w8, [sp, #15] +; CHECK-NEXT: strb w8, [sp, #14] +; CHECK-NEXT: strb w8, [sp, #13] +; CHECK-NEXT: strb w8, [sp, #12] +; CHECK-NEXT: strb w8, [sp, #11] +; CHECK-NEXT: strb w8, [sp, #10] +; CHECK-NEXT: strb w8, [sp, #9] +; CHECK-NEXT: strb w8, [sp, #8] +; CHECK-NEXT: ldr d2, [sp, #8] +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <8 x i8> %op1, <8 x i8> %op2 + ret <8 x i8> %sel +} + +define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v16i8: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: adrp x9, .LCPI2_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI2_0] +; CHECK-NEXT: strb w8, [sp, #15] +; CHECK-NEXT: strb w8, [sp, #14] +; CHECK-NEXT: strb w8, [sp, #13] +; CHECK-NEXT: strb w8, [sp, #12] +; CHECK-NEXT: strb w8, [sp, #11] +; CHECK-NEXT: strb w8, [sp, #10] +; CHECK-NEXT: strb w8, [sp, #9] +; CHECK-NEXT: strb w8, [sp, #8] +; CHECK-NEXT: strb w8, [sp, #7] +; CHECK-NEXT: strb w8, [sp, #6] +; CHECK-NEXT: strb w8, [sp, #5] +; CHECK-NEXT: strb w8, [sp, #4] +; CHECK-NEXT: strb w8, [sp, #3] +; CHECK-NEXT: strb w8, [sp, #2] +; CHECK-NEXT: strb w8, [sp, #1] +; CHECK-NEXT: strb w8, [sp] +; CHECK-NEXT: ldr q2, [sp] +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <16 x i8> %op1, <16 x i8> %op2 + ret <16 x i8> %sel +} + +define void @select_v32i8(ptr %a, ptr %b, i1 %mask) #0 { +; CHECK-LABEL: select_v32i8: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w2, #0x1 +; CHECK-NEXT: adrp x9, .LCPI3_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x0, #16] +; CHECK-NEXT: ldr q2, [x1] +; CHECK-NEXT: ldr q3, [x1, #16] +; CHECK-NEXT: strb w8, [sp, #15] +; CHECK-NEXT: strb w8, [sp, #14] +; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI3_0] +; CHECK-NEXT: strb w8, [sp, #13] +; CHECK-NEXT: strb w8, [sp, #12] +; CHECK-NEXT: strb w8, [sp, #11] +; CHECK-NEXT: strb w8, [sp, #10] +; CHECK-NEXT: strb w8, [sp, #9] +; CHECK-NEXT: strb w8, [sp, #8] +; CHECK-NEXT: strb w8, [sp, #7] +; CHECK-NEXT: strb w8, [sp, #6] +; CHECK-NEXT: strb w8, [sp, #5] +; CHECK-NEXT: strb w8, [sp, #4] +; CHECK-NEXT: strb w8, [sp, #3] +; CHECK-NEXT: strb w8, [sp, #2] +; CHECK-NEXT: strb w8, [sp, #1] +; CHECK-NEXT: strb w8, [sp] +; CHECK-NEXT: ldr q4, [sp] +; CHECK-NEXT: eor z5.d, z4.d, z5.d +; CHECK-NEXT: and z1.d, z1.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z4.d +; CHECK-NEXT: and z2.d, z2.d, z5.d +; CHECK-NEXT: and z3.d, z3.d, z5.d +; CHECK-NEXT: orr z0.d, z0.d, z2.d +; CHECK-NEXT: orr z1.d, z1.d, z3.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %op1 = load volatile <32 x i8>, ptr %a + %op2 = load volatile <32 x i8>, ptr %b + %sel = select i1 %mask, <32 x i8> %op1, <32 x i8> %op2 + store <32 x i8> %sel, ptr %a + ret void +} + +define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v2i16: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: adrp x9, .LCPI4_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI4_0] +; CHECK-NEXT: stp w8, w8, [sp, #8] +; CHECK-NEXT: ldr d2, [sp, #8] +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <2 x i16> %op1, <2 x i16> %op2 + ret <2 x i16> %sel +} + +define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v4i16: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: adrp x9, .LCPI5_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI5_0] +; CHECK-NEXT: strh w8, [sp, #14] +; CHECK-NEXT: strh w8, [sp, #12] +; CHECK-NEXT: strh w8, [sp, #10] +; CHECK-NEXT: strh w8, [sp, #8] +; CHECK-NEXT: ldr d2, [sp, #8] +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <4 x i16> %op1, <4 x i16> %op2 + ret <4 x i16> %sel +} + +define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v8i16: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: adrp x9, .LCPI6_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI6_0] +; CHECK-NEXT: strh w8, [sp, #14] +; CHECK-NEXT: strh w8, [sp, #12] +; CHECK-NEXT: strh w8, [sp, #10] +; CHECK-NEXT: strh w8, [sp, #8] +; CHECK-NEXT: strh w8, [sp, #6] +; CHECK-NEXT: strh w8, [sp, #4] +; CHECK-NEXT: strh w8, [sp, #2] +; CHECK-NEXT: strh w8, [sp] +; CHECK-NEXT: ldr q2, [sp] +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <8 x i16> %op1, <8 x i16> %op2 + ret <8 x i16> %sel +} + +define void @select_v16i16(ptr %a, ptr %b, i1 %mask) #0 { +; CHECK-LABEL: select_v16i16: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w2, #0x1 +; CHECK-NEXT: adrp x9, .LCPI7_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x0, #16] +; CHECK-NEXT: ldr q2, [x1] +; CHECK-NEXT: ldr q3, [x1, #16] +; CHECK-NEXT: strh w8, [sp, #14] +; CHECK-NEXT: strh w8, [sp, #12] +; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI7_0] +; CHECK-NEXT: strh w8, [sp, #10] +; CHECK-NEXT: strh w8, [sp, #8] +; CHECK-NEXT: strh w8, [sp, #6] +; CHECK-NEXT: strh w8, [sp, #4] +; CHECK-NEXT: strh w8, [sp, #2] +; CHECK-NEXT: strh w8, [sp] +; CHECK-NEXT: ldr q4, [sp] +; CHECK-NEXT: eor z5.d, z4.d, z5.d +; CHECK-NEXT: and z1.d, z1.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z4.d +; CHECK-NEXT: and z2.d, z2.d, z5.d +; CHECK-NEXT: and z3.d, z3.d, z5.d +; CHECK-NEXT: orr z0.d, z0.d, z2.d +; CHECK-NEXT: orr z1.d, z1.d, z3.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %op1 = load volatile <16 x i16>, ptr %a + %op2 = load volatile <16 x i16>, ptr %b + %sel = select i1 %mask, <16 x i16> %op1, <16 x i16> %op2 + store <16 x i16> %sel, ptr %a + ret void +} + +define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v2i32: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: adrp x9, .LCPI8_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x9, :lo12:.LCPI8_0] +; CHECK-NEXT: stp w8, w8, [sp, #8] +; CHECK-NEXT: ldr d2, [sp, #8] +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <2 x i32> %op1, <2 x i32> %op2 + ret <2 x i32> %sel +} + +define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v4i32: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: adrp x9, .LCPI9_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI9_0] +; CHECK-NEXT: stp w8, w8, [sp, #8] +; CHECK-NEXT: stp w8, w8, [sp] +; CHECK-NEXT: ldr q2, [sp] +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <4 x i32> %op1, <4 x i32> %op2 + ret <4 x i32> %sel +} + +define void @select_v8i32(ptr %a, ptr %b, i1 %mask) #0 { +; CHECK-LABEL: select_v8i32: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #16 +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: tst w2, #0x1 +; CHECK-NEXT: adrp x9, .LCPI10_0 +; CHECK-NEXT: csetm w8, ne +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldr q1, [x0, #16] +; CHECK-NEXT: ldr q2, [x1] +; CHECK-NEXT: ldr q3, [x1, #16] +; CHECK-NEXT: stp w8, w8, [sp, #8] +; CHECK-NEXT: stp w8, w8, [sp] +; CHECK-NEXT: ldr q5, [x9, :lo12:.LCPI10_0] +; CHECK-NEXT: ldr q4, [sp] +; CHECK-NEXT: eor z5.d, z4.d, z5.d +; CHECK-NEXT: and z1.d, z1.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z4.d +; CHECK-NEXT: and z2.d, z2.d, z5.d +; CHECK-NEXT: and z3.d, z3.d, z5.d +; CHECK-NEXT: orr z0.d, z0.d, z2.d +; CHECK-NEXT: orr z1.d, z1.d, z3.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %op1 = load volatile <8 x i32>, ptr %a + %op2 = load volatile <8 x i32>, ptr %b + %sel = select i1 %mask, <8 x i32> %op1, <8 x i32> %op2 + store <8 x i32> %sel, ptr %a + ret void +} + +define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v1i64: +; CHECK: // %bb.0: +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: mov x9, #-1 +; CHECK-NEXT: csetm x8, ne +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: fmov d3, x9 +; CHECK-NEXT: fmov d2, x8 +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %sel = select i1 %mask, <1 x i64> %op1, <1 x i64> %op2 + ret <1 x i64> %sel +} + +define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) #0 { +; CHECK-LABEL: select_v2i64: +; CHECK: // %bb.0: +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: adrp x9, .LCPI12_0 +; CHECK-NEXT: csetm x8, ne +; CHECK-NEXT: stp x8, x8, [sp, #-16]! +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr q2, [sp] +; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI12_0] +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %sel = select i1 %mask, <2 x i64> %op1, <2 x i64> %op2 + ret <2 x i64> %sel +} + +define void @select_v4i64(ptr %a, ptr %b, i1 %mask) #0 { +; CHECK-LABEL: select_v4i64: +; CHECK: // %bb.0: +; CHECK-NEXT: tst w2, #0x1 +; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: csetm x8, ne +; CHECK-NEXT: ldr q1, [x0, #16] +; CHECK-NEXT: ldr q2, [x1] +; CHECK-NEXT: adrp x9, .LCPI13_0 +; CHECK-NEXT: ldr q3, [x1, #16] +; CHECK-NEXT: stp x8, x8, [sp, #-16]! +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI13_0] +; CHECK-NEXT: ldr q5, [sp] +; CHECK-NEXT: eor z4.d, z5.d, z4.d +; CHECK-NEXT: and z1.d, z1.d, z5.d +; CHECK-NEXT: and z0.d, z0.d, z5.d +; CHECK-NEXT: and z2.d, z2.d, z4.d +; CHECK-NEXT: and z3.d, z3.d, z4.d +; CHECK-NEXT: orr z0.d, z0.d, z2.d +; CHECK-NEXT: orr z1.d, z1.d, z3.d +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ret + %op1 = load volatile <4 x i64>, ptr %a + %op2 = load volatile <4 x i64>, ptr %b + %sel = select i1 %mask, <4 x i64> %op1, <4 x i64> %op2 + store <4 x i64> %sel, ptr %a + ret void +} + +attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll @@ -0,0 +1,356 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s + +target triple = "aarch64-unknown-linux-gnu" + +define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, <4 x i1> %mask) #0 { +; CHECK-LABEL: select_v4i8: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI0_0 +; CHECK-NEXT: adrp x9, .LCPI0_1 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI0_0] +; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI0_1] +; CHECK-NEXT: lsl z2.h, p0/m, z2.h, z3.h +; CHECK-NEXT: asr z2.h, p0/m, z2.h, z3.h +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %sel = select <4 x i1> %mask, <4 x i8> %op1, <4 x i8> %op2 + ret <4 x i8> %sel +} + +define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) #0 { +; CHECK-LABEL: select_v8i8: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI1_0 +; CHECK-NEXT: adrp x9, .LCPI1_1 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: ptrue p0.b, vl8 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI1_0] +; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI1_1] +; CHECK-NEXT: lsl z2.b, p0/m, z2.b, z3.b +; CHECK-NEXT: asr z2.b, p0/m, z2.b, z3.b +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %sel = select <8 x i1> %mask, <8 x i8> %op1, <8 x i8> %op2 + ret <8 x i8> %sel +} + +define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask) #0 { +; CHECK-LABEL: select_v16i8: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI2_0 +; CHECK-NEXT: adrp x9, .LCPI2_1 +; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI2_0] +; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI2_1] +; CHECK-NEXT: lsl z2.b, p0/m, z2.b, z3.b +; CHECK-NEXT: asr z2.b, p0/m, z2.b, z3.b +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %sel = select <16 x i1> %mask, <16 x i8> %op1, <16 x i8> %op2 + ret <16 x i8> %sel +} + +define void @select_v32i8(ptr %a, ptr %b) #0 { +; CHECK-LABEL: select_v32i8: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x1] +; CHECK-NEXT: adrp x8, .LCPI3_0 +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI3_0] +; CHECK-NEXT: cmpeq p1.b, p0/z, z2.b, z0.b +; CHECK-NEXT: cmpeq p0.b, p0/z, z3.b, z1.b +; CHECK-NEXT: mov z5.b, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z6.b, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: and z2.d, z2.d, z5.d +; CHECK-NEXT: eor z5.d, z5.d, z4.d +; CHECK-NEXT: eor z4.d, z6.d, z4.d +; CHECK-NEXT: and z3.d, z3.d, z6.d +; CHECK-NEXT: and z1.d, z1.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z5.d +; CHECK-NEXT: orr z1.d, z3.d, z1.d +; CHECK-NEXT: orr z0.d, z2.d, z0.d +; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: ret + %op1 = load <32 x i8>, ptr %a + %op2 = load <32 x i8>, ptr %b + %mask = icmp eq <32 x i8> %op1, %op2 + %sel = select <32 x i1> %mask, <32 x i8> %op1, <32 x i8> %op2 + store <32 x i8> %sel, ptr %a + ret void +} + +define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, <2 x i1> %mask) #0 { +; CHECK-LABEL: select_v2i16: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI4_0 +; CHECK-NEXT: adrp x9, .LCPI4_1 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI4_0] +; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI4_1] +; CHECK-NEXT: lsl z2.s, p0/m, z2.s, z3.s +; CHECK-NEXT: asr z2.s, p0/m, z2.s, z3.s +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %sel = select <2 x i1> %mask, <2 x i16> %op1, <2 x i16> %op2 + ret <2 x i16> %sel +} + +define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, <4 x i1> %mask) #0 { +; CHECK-LABEL: select_v4i16: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI5_0 +; CHECK-NEXT: adrp x9, .LCPI5_1 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI5_0] +; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI5_1] +; CHECK-NEXT: lsl z2.h, p0/m, z2.h, z3.h +; CHECK-NEXT: asr z2.h, p0/m, z2.h, z3.h +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %sel = select <4 x i1> %mask, <4 x i16> %op1, <4 x i16> %op2 + ret <4 x i16> %sel +} + +define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) #0 { +; CHECK-LABEL: select_v8i16: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI6_0 +; CHECK-NEXT: adrp x9, .LCPI6_1 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: uunpklo z2.h, z2.b +; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI6_0] +; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI6_1] +; CHECK-NEXT: lsl z2.h, p0/m, z2.h, z3.h +; CHECK-NEXT: asr z2.h, p0/m, z2.h, z3.h +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %sel = select <8 x i1> %mask, <8 x i16> %op1, <8 x i16> %op2 + ret <8 x i16> %sel +} + +define void @select_v16i16(ptr %a, ptr %b) #0 { +; CHECK-LABEL: select_v16i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x1] +; CHECK-NEXT: adrp x8, .LCPI7_0 +; CHECK-NEXT: ptrue p0.h, vl8 +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI7_0] +; CHECK-NEXT: cmpeq p1.h, p0/z, z2.h, z0.h +; CHECK-NEXT: cmpeq p0.h, p0/z, z3.h, z1.h +; CHECK-NEXT: mov z5.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z6.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: and z2.d, z2.d, z5.d +; CHECK-NEXT: eor z5.d, z5.d, z4.d +; CHECK-NEXT: eor z4.d, z6.d, z4.d +; CHECK-NEXT: and z3.d, z3.d, z6.d +; CHECK-NEXT: and z1.d, z1.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z5.d +; CHECK-NEXT: orr z1.d, z3.d, z1.d +; CHECK-NEXT: orr z0.d, z2.d, z0.d +; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: ret + %op1 = load <16 x i16>, ptr %a + %op2 = load <16 x i16>, ptr %b + %mask = icmp eq <16 x i16> %op1, %op2 + %sel = select <16 x i1> %mask, <16 x i16> %op1, <16 x i16> %op2 + store <16 x i16> %sel, ptr %a + ret void +} + +define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) #0 { +; CHECK-LABEL: select_v2i32: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI8_0 +; CHECK-NEXT: adrp x9, .LCPI8_1 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI8_0] +; CHECK-NEXT: ldr d4, [x9, :lo12:.LCPI8_1] +; CHECK-NEXT: lsl z2.s, p0/m, z2.s, z3.s +; CHECK-NEXT: asr z2.s, p0/m, z2.s, z3.s +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %sel = select <2 x i1> %mask, <2 x i32> %op1, <2 x i32> %op2 + ret <2 x i32> %sel +} + +define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) #0 { +; CHECK-LABEL: select_v4i32: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI9_0 +; CHECK-NEXT: adrp x9, .LCPI9_1 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: uunpklo z2.s, z2.h +; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI9_0] +; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI9_1] +; CHECK-NEXT: lsl z2.s, p0/m, z2.s, z3.s +; CHECK-NEXT: asr z2.s, p0/m, z2.s, z3.s +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %sel = select <4 x i1> %mask, <4 x i32> %op1, <4 x i32> %op2 + ret <4 x i32> %sel +} + +define void @select_v8i32(ptr %a, ptr %b) #0 { +; CHECK-LABEL: select_v8i32: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x1] +; CHECK-NEXT: adrp x8, .LCPI10_0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI10_0] +; CHECK-NEXT: cmpeq p1.s, p0/z, z2.s, z0.s +; CHECK-NEXT: cmpeq p0.s, p0/z, z3.s, z1.s +; CHECK-NEXT: mov z5.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z6.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: and z2.d, z2.d, z5.d +; CHECK-NEXT: eor z5.d, z5.d, z4.d +; CHECK-NEXT: eor z4.d, z6.d, z4.d +; CHECK-NEXT: and z3.d, z3.d, z6.d +; CHECK-NEXT: and z1.d, z1.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z5.d +; CHECK-NEXT: orr z1.d, z3.d, z1.d +; CHECK-NEXT: orr z0.d, z2.d, z0.d +; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: ret + %op1 = load <8 x i32>, ptr %a + %op2 = load <8 x i32>, ptr %b + %mask = icmp eq <8 x i32> %op1, %op2 + %sel = select <8 x i1> %mask, <8 x i32> %op1, <8 x i32> %op2 + store <8 x i32> %sel, ptr %a + ret void +} + +define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) #0 { +; CHECK-LABEL: select_v1i64: +; CHECK: // %bb.0: +; CHECK-NEXT: tst w0, #0x1 +; CHECK-NEXT: mov x9, #-1 +; CHECK-NEXT: csetm x8, ne +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: fmov d3, x9 +; CHECK-NEXT: fmov d2, x8 +; CHECK-NEXT: eor z3.d, z2.d, z3.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %sel = select <1 x i1> %mask, <1 x i64> %op1, <1 x i64> %op2 + ret <1 x i64> %sel +} + +define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) #0 { +; CHECK-LABEL: select_v2i64: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI12_0 +; CHECK-NEXT: adrp x9, .LCPI12_1 +; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 +; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 +; CHECK-NEXT: uunpklo z2.d, z2.s +; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI12_0] +; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI12_1] +; CHECK-NEXT: lsl z2.d, p0/m, z2.d, z3.d +; CHECK-NEXT: asr z2.d, p0/m, z2.d, z3.d +; CHECK-NEXT: eor z3.d, z2.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: and z1.d, z1.d, z3.d +; CHECK-NEXT: orr z0.d, z0.d, z1.d +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 +; CHECK-NEXT: ret + %sel = select <2 x i1> %mask, <2 x i64> %op1, <2 x i64> %op2 + ret <2 x i64> %sel +} + +define void @select_v4i64(ptr %a, ptr %b) #0 { +; CHECK-LABEL: select_v4i64: +; CHECK: // %bb.0: +; CHECK-NEXT: ldp q1, q0, [x1] +; CHECK-NEXT: adrp x8, .LCPI13_0 +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ldp q3, q2, [x0] +; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI13_0] +; CHECK-NEXT: cmpeq p1.d, p0/z, z2.d, z0.d +; CHECK-NEXT: cmpeq p0.d, p0/z, z3.d, z1.d +; CHECK-NEXT: mov z5.d, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z6.d, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: and z2.d, z2.d, z5.d +; CHECK-NEXT: eor z5.d, z5.d, z4.d +; CHECK-NEXT: eor z4.d, z6.d, z4.d +; CHECK-NEXT: and z3.d, z3.d, z6.d +; CHECK-NEXT: and z1.d, z1.d, z4.d +; CHECK-NEXT: and z0.d, z0.d, z5.d +; CHECK-NEXT: orr z1.d, z3.d, z1.d +; CHECK-NEXT: orr z0.d, z2.d, z0.d +; CHECK-NEXT: stp q1, q0, [x0] +; CHECK-NEXT: ret + %op1 = load <4 x i64>, ptr %a + %op2 = load <4 x i64>, ptr %b + %mask = icmp eq <4 x i64> %op1, %op2 + %sel = select <4 x i1> %mask, <4 x i64> %op1, <4 x i64> %op2 + store <4 x i64> %sel, ptr %a + ret void +} + +attributes #0 = { "target-features"="+sve" uwtable } diff --git a/llvm/test/CodeGen/AArch64/swift-return.ll b/llvm/test/CodeGen/AArch64/swift-return.ll --- a/llvm/test/CodeGen/AArch64/swift-return.ll +++ b/llvm/test/CodeGen/AArch64/swift-return.ll @@ -28,8 +28,8 @@ ; CHECK-LABEL: test2 ; CHECK: bl _gen2 ; CHECK: add [[TMP:x.*]], x0, x1 -; CHECK: add [[TMP]], [[TMP]], x2 -; CHECK: add [[TMP]], [[TMP]], x3 +; CHECK: add [[TMP2:x.*]], x2, x3 +; CHECK: add [[TMP]], [[TMP]], [[TMP2]] ; CHECK: add x0, [[TMP]], x4 ; CHECK-O0-LABEL: test2 ; CHECK-O0: bl _gen2 @@ -75,8 +75,8 @@ ; CHECK-LABEL: test3 ; CHECK: bl _gen3 ; CHECK: add [[TMP:w.*]], w0, w1 -; CHECK: add [[TMP]], [[TMP]], w2 -; CHECK: add w0, [[TMP]], w3 +; CHECK: add [[TMP2:w.*]], w2, w3 +; CHECK: add w0, [[TMP]], [[TMP2]] ; CHECK-O0-LABEL: test3 ; CHECK-O0: bl _gen3 ; CHECK-O0: add [[TMP:w.*]], w0, w1 @@ -159,8 +159,8 @@ ; CHECK-DAG: fadd d0, d0, d2 ; CHECK-DAG: fadd d0, d0, d3 ; CHECK-DAG: add [[TMP:w.*]], w0, w1 -; CHECK-DAG: add [[TMP]], [[TMP]], w2 -; CHECK-DAG: add w0, [[TMP]], w3 +; CHECK-DAG: add [[TMP2:w.*]], w2, w3 +; CHECK-DAG: add w0, [[TMP]], [[TMP2]] ; CHECK-O0-LABEL: test6 ; CHECK-O0: bl _gen6 ; CHECK-O0-DAG: fadd d0, d0, d1 diff --git a/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll b/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll --- a/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll +++ b/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll @@ -97,28 +97,28 @@ ; CHECK-LABEL: test_v9i8: ; CHECK: // %bb.0: ; CHECK-NEXT: mov w8, #-1 -; CHECK-NEXT: umov w12, v0.b[4] +; CHECK-NEXT: umov w9, v0.b[5] ; CHECK-NEXT: mov v1.16b, v0.16b +; CHECK-NEXT: umov w10, v0.b[6] +; CHECK-NEXT: umov w15, v0.b[7] ; CHECK-NEXT: mov v1.b[9], w8 ; CHECK-NEXT: mov v1.b[10], w8 ; CHECK-NEXT: mov v1.b[11], w8 ; CHECK-NEXT: mov v1.b[13], w8 +; CHECK-NEXT: umov w8, v0.b[4] ; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8 -; CHECK-NEXT: and v1.8b, v0.8b, v1.8b -; CHECK-NEXT: umov w8, v1.b[1] -; CHECK-NEXT: umov w9, v1.b[0] -; CHECK-NEXT: umov w10, v1.b[2] -; CHECK-NEXT: umov w11, v1.b[3] -; CHECK-NEXT: and w8, w9, w8 -; CHECK-NEXT: umov w9, v0.b[5] -; CHECK-NEXT: and w8, w8, w10 -; CHECK-NEXT: umov w10, v0.b[6] -; CHECK-NEXT: and w8, w8, w11 -; CHECK-NEXT: umov w11, v0.b[7] -; CHECK-NEXT: and w8, w8, w12 ; CHECK-NEXT: and w8, w8, w9 ; CHECK-NEXT: and w8, w8, w10 -; CHECK-NEXT: and w0, w8, w11 +; CHECK-NEXT: and w8, w8, w15 +; CHECK-NEXT: and v1.8b, v0.8b, v1.8b +; CHECK-NEXT: umov w11, v1.b[1] +; CHECK-NEXT: umov w12, v1.b[0] +; CHECK-NEXT: umov w13, v1.b[2] +; CHECK-NEXT: umov w14, v1.b[3] +; CHECK-NEXT: and w9, w12, w11 +; CHECK-NEXT: and w11, w13, w14 +; CHECK-NEXT: and w9, w9, w11 +; CHECK-NEXT: and w0, w9, w8 ; CHECK-NEXT: ret %b = call i8 @llvm.vector.reduce.and.v9i8(<9 x i8> %a) ret i8 %b diff --git a/llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll b/llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll --- a/llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll +++ b/llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll @@ -29,9 +29,8 @@ ; CHECK-LABEL: cntb_and_elimination: ; CHECK: // %bb.0: ; CHECK-NEXT: cntb x8 -; CHECK-NEXT: and x9, x8, #0x1ff -; CHECK-NEXT: and x8, x8, #0x3fffffffc -; CHECK-NEXT: add x0, x9, x8 +; CHECK-NEXT: and x9, x8, #0x1fc +; CHECK-NEXT: add x0, x8, x9 ; CHECK-NEXT: ret %cntb = call i64 @llvm.aarch64.sve.cntb(i32 31) %and_redundant = and i64 %cntb, 511 @@ -44,9 +43,8 @@ ; CHECK-LABEL: cnth_and_elimination: ; CHECK: // %bb.0: ; CHECK-NEXT: cnth x8 -; CHECK-NEXT: and x9, x8, #0x3ff -; CHECK-NEXT: and x8, x8, #0x3fffffffc -; CHECK-NEXT: add x0, x9, x8 +; CHECK-NEXT: and x9, x8, #0xfc +; CHECK-NEXT: add x0, x8, x9 ; CHECK-NEXT: ret %cnth = call i64 @llvm.aarch64.sve.cnth(i32 31) %and_redundant = and i64 %cnth, 1023 @@ -59,9 +57,8 @@ ; CHECK-LABEL: cntw_and_elimination: ; CHECK: // %bb.0: ; CHECK-NEXT: cntw x8 -; CHECK-NEXT: and x9, x8, #0x7f -; CHECK-NEXT: and x8, x8, #0x3fffffffc -; CHECK-NEXT: add x0, x9, x8 +; CHECK-NEXT: and x9, x8, #0x7c +; CHECK-NEXT: add x0, x8, x9 ; CHECK-NEXT: ret %cntw = call i64 @llvm.aarch64.sve.cntw(i32 31) %and_redundant = and i64 %cntw, 127 @@ -74,9 +71,8 @@ ; CHECK-LABEL: cntd_and_elimination: ; CHECK: // %bb.0: ; CHECK-NEXT: cntd x8 -; CHECK-NEXT: and x9, x8, #0x3f -; CHECK-NEXT: and x8, x8, #0x3fffffffc -; CHECK-NEXT: add x0, x9, x8 +; CHECK-NEXT: and x9, x8, #0x3c +; CHECK-NEXT: add x0, x8, x9 ; CHECK-NEXT: ret %cntd = call i64 @llvm.aarch64.sve.cntd(i32 31) %and_redundant = and i64 %cntd, 63 @@ -112,8 +108,7 @@ define i64 @count_bytes_trunc_zext() { ; CHECK-LABEL: count_bytes_trunc_zext: ; CHECK: // %bb.0: -; CHECK-NEXT: cntb x8 -; CHECK-NEXT: and x0, x8, #0xffffffff +; CHECK-NEXT: cntb x0 ; CHECK-NEXT: ret %cnt = call i64 @llvm.aarch64.sve.cntb(i32 31) %trunc = trunc i64 %cnt to i32 @@ -124,8 +119,7 @@ define i64 @count_halfs_trunc_zext() { ; CHECK-LABEL: count_halfs_trunc_zext: ; CHECK: // %bb.0: -; CHECK-NEXT: cnth x8 -; CHECK-NEXT: and x0, x8, #0xffffffff +; CHECK-NEXT: cnth x0 ; CHECK-NEXT: ret %cnt = call i64 @llvm.aarch64.sve.cnth(i32 31) %trunc = trunc i64 %cnt to i32 @@ -136,8 +130,7 @@ define i64 @count_words_trunc_zext() { ; CHECK-LABEL: count_words_trunc_zext: ; CHECK: // %bb.0: -; CHECK-NEXT: cntw x8 -; CHECK-NEXT: and x0, x8, #0xffffffff +; CHECK-NEXT: cntw x0 ; CHECK-NEXT: ret %cnt = call i64 @llvm.aarch64.sve.cntw(i32 31) %trunc = trunc i64 %cnt to i32 @@ -148,8 +141,7 @@ define i64 @count_doubles_trunc_zext() { ; CHECK-LABEL: count_doubles_trunc_zext: ; CHECK: // %bb.0: -; CHECK-NEXT: cntd x8 -; CHECK-NEXT: and x0, x8, #0xffffffff +; CHECK-NEXT: cntd x0 ; CHECK-NEXT: ret %cnt = call i64 @llvm.aarch64.sve.cntd(i32 31) %trunc = trunc i64 %cnt to i32 @@ -160,8 +152,7 @@ define i64 @count_bytes_trunc_sext() { ; CHECK-LABEL: count_bytes_trunc_sext: ; CHECK: // %bb.0: -; CHECK-NEXT: cntb x8 -; CHECK-NEXT: sxtw x0, w8 +; CHECK-NEXT: cntb x0 ; CHECK-NEXT: ret %cnt = call i64 @llvm.aarch64.sve.cntb(i32 31) %trunc = trunc i64 %cnt to i32 @@ -172,8 +163,7 @@ define i64 @count_halfs_trunc_sext() { ; CHECK-LABEL: count_halfs_trunc_sext: ; CHECK: // %bb.0: -; CHECK-NEXT: cnth x8 -; CHECK-NEXT: sxtw x0, w8 +; CHECK-NEXT: cnth x0 ; CHECK-NEXT: ret %cnt = call i64 @llvm.aarch64.sve.cnth(i32 31) %trunc = trunc i64 %cnt to i32 @@ -184,8 +174,7 @@ define i64 @count_words_trunc_sext() { ; CHECK-LABEL: count_words_trunc_sext: ; CHECK: // %bb.0: -; CHECK-NEXT: cntw x8 -; CHECK-NEXT: sxtw x0, w8 +; CHECK-NEXT: cntw x0 ; CHECK-NEXT: ret %cnt = call i64 @llvm.aarch64.sve.cntw(i32 31) %trunc = trunc i64 %cnt to i32 @@ -196,8 +185,7 @@ define i64 @count_doubles_trunc_sext() { ; CHECK-LABEL: count_doubles_trunc_sext: ; CHECK: // %bb.0: -; CHECK-NEXT: cntd x8 -; CHECK-NEXT: sxtw x0, w8 +; CHECK-NEXT: cntd x0 ; CHECK-NEXT: ret %cnt = call i64 @llvm.aarch64.sve.cntd(i32 31) %trunc = trunc i64 %cnt to i32 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/dropped_debug_info_assert.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=instruction-select -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=instruction-select --amdgpu-lower-module-lds-strategy=module -o - %s | FileCheck %s ; Make sure there are no assertions on dropped debug info declare void @callee() diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs --amdgpu-lower-module-lds-strategy=module -o - %s | FileCheck %s define amdgpu_kernel void @asm_convergent() convergent{ ; CHECK-LABEL: name: asm_convergent diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll @@ -4,7 +4,7 @@ declare float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i32 immarg) declare <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i32 immarg) -; GFX908: LLVM ERROR: cannot select: %24:vgpr_32(s32) = G_AMDGPU_BUFFER_ATOMIC_FADD %28:vgpr, %14:sgpr(<4 x s32>), %29:vgpr(s32), %30:vgpr, %27:sgpr, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 4) (in function: buffer_atomic_add_f32_rtn) +; GFX908: LLVM ERROR: cannot select: %{{[0-9]+}}:vgpr_32(s32) = G_AMDGPU_BUFFER_ATOMIC_FADD %{{[0-9]+}}:vgpr, %{{[0-9]+}}:sgpr(<4 x s32>), %{{[0-9]+}}:vgpr(s32), %{{[0-9]+}}:vgpr, %{{[0-9]+}}:sgpr, 0, 0, 0 :: (volatile dereferenceable load store (s32), align 1, addrspace 4) (in function: buffer_atomic_add_f32_rtn) ; GFX90A-LABEL: {{^}}buffer_atomic_add_f32_rtn: ; GFX90A: buffer_atomic_add_f32 v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9:]+}}], s{{[0-9]+}} offen glc diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll @@ -1,7 +1,7 @@ ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX90A %s ; RUN: not --crash llc -global-isel < %s -march=amdgcn -mcpu=gfx908 -verify-machineinstrs 2>&1 | FileCheck %s -check-prefix=GFX908 -; GFX908: LLVM ERROR: cannot select: %29:vgpr_32(s32) = G_AMDGPU_BUFFER_ATOMIC_FADD %40:vgpr, %15:sgpr(<4 x s32>), %41:vgpr(s32), %42:vgpr, %33:sgpr, 0, 0, -1 :: (volatile dereferenceable load store (s32), align 1, addrspace 4) (in function: buffer_atomic_add_f32_rtn) +; GFX908: LLVM ERROR: cannot select: %{{[0-9]+}}:vgpr_32(s32) = G_AMDGPU_BUFFER_ATOMIC_FADD %{{[0-9]+}}:vgpr, %{{[0-9]+}}:sgpr(<4 x s32>), %{{[0-9]+}}:vgpr(s32), %{{[0-9]+}}:vgpr, %{{[0-9]+}}:sgpr, 0, 0, -1 :: (volatile dereferenceable load store (s32), align 1, addrspace 4) (in function: buffer_atomic_add_f32_rtn) declare float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i32, i32 immarg) declare <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i32, i32 immarg) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll @@ -214,10 +214,125 @@ ret float %fval } +define amdgpu_cs void @struct_buffer_load_format_v4i32_tfe(<4 x i32> inreg %rsrc, <4 x i32> addrspace(1)* %value, i32 addrspace(1)* %status) { + ; CHECK-LABEL: name: struct_buffer_load_format_v4i32_tfe + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN:%[0-9]+]]:vreg_160 = BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN [[COPY8]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x s32>) from custom "BufferResource", align 1, addrspace 4) + ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN]].sub0 + ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN]].sub1 + ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN]].sub2 + ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN]].sub3 + ; CHECK-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN]].sub4 + ; CHECK-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2, [[COPY12]], %subreg.sub3 + ; CHECK-NEXT: FLAT_STORE_DWORDX4 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<4 x s32>) into %ir.value, addrspace 1) + ; CHECK-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY13]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.status, addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + %load = call { <4 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v4i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) + + %v = extractvalue { <4 x i32>, i32 } %load, 0 + store <4 x i32> %v, <4 x i32> addrspace(1)* %value + + %s = extractvalue { <4 x i32>, i32 } %load, 1 + store i32 %s, i32 addrspace(1)* %status + + ret void +} + +define amdgpu_cs void @struct_buffer_load_format_v3i32_tfe(<4 x i32> inreg %rsrc, <3 x i32> addrspace(1)* %value, i32 addrspace(1)* %status) { + ; CHECK-LABEL: name: struct_buffer_load_format_v3i32_tfe + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN [[COPY8]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x s32>) from custom "BufferResource", align 1, addrspace 4) + ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN]].sub0 + ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN]].sub1 + ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN]].sub2 + ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN]].sub3 + ; CHECK-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY9]], %subreg.sub0, [[COPY10]], %subreg.sub1, [[COPY11]], %subreg.sub2 + ; CHECK-NEXT: FLAT_STORE_DWORDX3 [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], 0, 0, implicit $exec, implicit $flat_scr :: (store (<3 x s32>) into %ir.value, align 16, addrspace 1) + ; CHECK-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY12]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.status, addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + %load = call { <3 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v3i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) + + %v = extractvalue { <3 x i32>, i32 } %load, 0 + store <3 x i32> %v, <3 x i32> addrspace(1)* %value + + %s = extractvalue { <3 x i32>, i32 } %load, 1 + store i32 %s, i32 addrspace(1)* %status + + ret void +} + +define amdgpu_cs void @struct_buffer_load_format_i32_tfe(<4 x i32> inreg %rsrc, i32 addrspace(1)* %value, i32 addrspace(1)* %status) { + ; CHECK-LABEL: name: struct_buffer_load_format_i32_tfe + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; CHECK-NEXT: [[BUFFER_LOAD_FORMAT_X_TFE_IDXEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_X_TFE_IDXEN [[COPY8]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (s32) from custom "BufferResource", align 1, addrspace 4) + ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_X_TFE_IDXEN]].sub0 + ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_X_TFE_IDXEN]].sub1 + ; CHECK-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE1]], [[COPY9]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.value, addrspace 1) + ; CHECK-NEXT: FLAT_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec, implicit $flat_scr :: (store (s32) into %ir.status, addrspace 1) + ; CHECK-NEXT: S_ENDPGM 0 + %load = call { i32, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) + + %v = extractvalue { i32, i32 } %load, 0 + store i32 %v, i32 addrspace(1)* %value + + %s = extractvalue { i32, i32 } %load, 1 + store i32 %s, i32 addrspace(1)* %status + + ret void +} + declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32 immarg) #0 declare <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32>, i32, i32, i32, i32 immarg) #0 declare <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32, i32 immarg) #0 declare <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32, i32 immarg) #0 declare i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32>, i32, i32, i32, i32 immarg) #0 +declare { <4 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v4i32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0 +declare { <3 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v3i32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0 +declare { i32, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_i32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0 attributes #0 = { nounwind readonly } diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll --- a/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll +++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck %s -; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgpu-lower-module-lds-strategy=module -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdgpu-lower-module-lds-strategy=module -o - %s | FileCheck %s ; Test that a null check is not emitted for lowered addrspacecast @@ -28,7 +28,6 @@ ; CHECK-LABEL: {{^}}cast_lds_gv: ; CHECK: s_getreg_b32 [[GETREG:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) ; CHECK: s_lshl_b32 [[APERTURE:s[0-9]+]], [[GETREG]], 16 -; CHECK: v_mov_b32_e32 v0, 0 ; CHECK: v_mov_b32_e32 v1, [[APERTURE]] ; CHECK-NOT: v0 ; CHECK-NOT: v1 diff --git a/llvm/test/CodeGen/AMDGPU/ds_write2.ll b/llvm/test/CodeGen/AMDGPU/ds_write2.ll --- a/llvm/test/CodeGen/AMDGPU/ds_write2.ll +++ b/llvm/test/CodeGen/AMDGPU/ds_write2.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope --check-prefix=CI %s -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt,-unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-ALIGNED %s -; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt,+unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-UNALIGNED %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt --amdgpu-lower-module-lds-strategy=module < %s | FileCheck -enable-var-scope --check-prefix=CI %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt,-unaligned-access-mode --amdgpu-lower-module-lds-strategy=module < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-ALIGNED %s +; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt,+unaligned-access-mode --amdgpu-lower-module-lds-strategy=module < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-UNALIGNED %s @lds = addrspace(3) global [512 x float] undef, align 4 @lds.f64 = addrspace(3) global [512 x double] undef, align 8 diff --git a/llvm/test/CodeGen/AMDGPU/hsa.ll b/llvm/test/CodeGen/AMDGPU/hsa.ll --- a/llvm/test/CodeGen/AMDGPU/hsa.ll +++ b/llvm/test/CodeGen/AMDGPU/hsa.ll @@ -1,13 +1,13 @@ -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA-CI %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA-VI %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj --amdhsa-code-object-version=2 | llvm-readobj -S --sd --syms - | FileCheck --check-prefix=ELF %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-readobj -S --sd --syms - | FileCheck %s --check-prefix=ELF -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W32 %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W64 %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W32 %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W64 %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=HSA %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=-flat-for-global --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=HSA-CI %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=HSA %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=-flat-for-global --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=HSA-VI %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj --amdhsa-code-object-version=2 --amdgpu-lower-module-lds-strategy=module | llvm-readobj -S --sd --syms - | FileCheck --check-prefix=ELF %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 --amdgpu-lower-module-lds-strategy=module | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-readobj -S --sd --syms - | FileCheck %s --check-prefix=ELF +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W32 %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W64 %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W32 %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 --amdgpu-lower-module-lds-strategy=module | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W64 %s ; The SHT_NOTE section contains the output from the .hsa_code_object_* ; directives. diff --git a/llvm/test/CodeGen/AMDGPU/lds-size.ll b/llvm/test/CodeGen/AMDGPU/lds-size.ll --- a/llvm/test/CodeGen/AMDGPU/lds-size.ll +++ b/llvm/test/CodeGen/AMDGPU/lds-size.ll @@ -9,7 +9,7 @@ ; GCN-NEXT: .long 32900 ; EG: .long 166120 -; EG-NEXT: .long 1 +; EG-NEXT: .long 0 ; ALL: {{^}}test: ; HSA: granulated_lds_size = 0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll @@ -0,0 +1,15 @@ +; RUN: llc -global-isel=0 -march=amdgcn -verify-machineinstrs -mcpu=gfx1100 < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs -mcpu=gfx1100 < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}test_wait_event: +; GCN: s_wait_event 0x0 + +define amdgpu_ps void @test_wait_event() #0 { +entry: + call void @llvm.amdgcn.s.wait.event.export.ready() #0 + ret void +} + +declare void @llvm.amdgcn.s.wait.event.export.ready() #0 + +attributes #0 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll @@ -1,5 +1,6 @@ -;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s +;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefixes=CHECK,GFX6 %s +;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefixes=CHECK,GFX8PLUS %s +;RUN: llc < %s -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs | FileCheck --check-prefixes=CHECK,GFX8PLUS %s ;CHECK-LABEL: {{^}}buffer_load: ;CHECK: buffer_load_format_xyzw v[0:3], {{v[0-9]+}}, s[0:3], 0 idxen @@ -118,9 +119,115 @@ ret <2 x float> %data } +;CHECK-LABEL: {{^}}buffer_load_v4i32_tfe: +;CHECK: buffer_load_format_xyzw v[2:6], {{v[0-9]+}}, s[0:3], 0 idxen tfe +;CHECK: s_waitcnt +define amdgpu_cs float @buffer_load_v4i32_tfe(<4 x i32> inreg %rsrc, <4 x i32> addrspace(1)* %out) { + %load = call { <4 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v4i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) + %data = extractvalue { <4 x i32>, i32 } %load, 0 + store <4 x i32> %data, <4 x i32> addrspace(1)* %out + %status = extractvalue { <4 x i32>, i32 } %load, 1 + %fstatus = bitcast i32 %status to float + ret float %fstatus +} + +;CHECK-LABEL: {{^}}buffer_load_v4f32_tfe: +;CHECK: buffer_load_format_xyzw v[2:6], {{v[0-9]+}}, s[0:3], 0 idxen tfe +;CHECK: s_waitcnt +define amdgpu_cs float @buffer_load_v4f32_tfe(<4 x i32> inreg %rsrc, <4 x float> addrspace(1)* %out) { + %load = call { <4 x float>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v4f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) + %data = extractvalue { <4 x float>, i32 } %load, 0 + store <4 x float> %data, <4 x float> addrspace(1)* %out + %status = extractvalue { <4 x float>, i32 } %load, 1 + %fstatus = bitcast i32 %status to float + ret float %fstatus +} + +;CHECK-LABEL: {{^}}buffer_load_v3i32_tfe: +;CHECK: buffer_load_format_xyz v[2:5], {{v[0-9]+}}, s[0:3], 0 idxen tfe +;CHECK: s_waitcnt +define amdgpu_cs float @buffer_load_v3i32_tfe(<4 x i32> inreg %rsrc, <3 x i32> addrspace(1)* %out) { + %load = call { <3 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v3i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) + %data = extractvalue { <3 x i32>, i32 } %load, 0 + store <3 x i32> %data, <3 x i32> addrspace(1)* %out + %status = extractvalue { <3 x i32>, i32 } %load, 1 + %fstatus = bitcast i32 %status to float + ret float %fstatus +} + +;CHECK-LABEL: {{^}}buffer_load_v3f32_tfe: +;CHECK: buffer_load_format_xyz v[2:5], {{v[0-9]+}}, s[0:3], 0 idxen tfe +;CHECK: s_waitcnt +define amdgpu_cs float @buffer_load_v3f32_tfe(<4 x i32> inreg %rsrc, <3 x float> addrspace(1)* %out) { + %load = call { <3 x float>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v3f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) + %data = extractvalue { <3 x float>, i32 } %load, 0 + store <3 x float> %data, <3 x float> addrspace(1)* %out + %status = extractvalue { <3 x float>, i32 } %load, 1 + %fstatus = bitcast i32 %status to float + ret float %fstatus +} + +;CHECK-LABEL: {{^}}buffer_load_v2i32_tfe: +;GFX6: buffer_load_format_xyz v[2:5], {{v[0-9]+}}, s[0:3], 0 idxen tfe +;GFX8PLUS: buffer_load_format_xy v[2:4], {{v[0-9]+}}, s[0:3], 0 idxen tfe +;CHECK: s_waitcnt +define amdgpu_cs float @buffer_load_v2i32_tfe(<4 x i32> inreg %rsrc, <2 x i32> addrspace(1)* %out) { + %load = call { <2 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v2i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) + %data = extractvalue { <2 x i32>, i32 } %load, 0 + store <2 x i32> %data, <2 x i32> addrspace(1)* %out + %status = extractvalue { <2 x i32>, i32 } %load, 1 + %fstatus = bitcast i32 %status to float + ret float %fstatus +} + +;CHECK-LABEL: {{^}}buffer_load_v2f32_tfe: +;GFX6: buffer_load_format_xyz v[2:5], {{v[0-9]+}}, s[0:3], 0 idxen tfe +;GFX8PLUS: buffer_load_format_xy v[2:4], {{v[0-9]+}}, s[0:3], 0 idxen tfe +;CHECK: s_waitcnt +define amdgpu_cs float @buffer_load_v2f32_tfe(<4 x i32> inreg %rsrc, <2 x float> addrspace(1)* %out) { + %load = call { <2 x float>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v2f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) + %data = extractvalue { <2 x float>, i32 } %load, 0 + store <2 x float> %data, <2 x float> addrspace(1)* %out + %status = extractvalue { <2 x float>, i32 } %load, 1 + %fstatus = bitcast i32 %status to float + ret float %fstatus +} + +;CHECK-LABEL: {{^}}buffer_load_i32_tfe: +;CHECK: buffer_load_format_x v[2:3], {{v[0-9]+}}, s[0:3], 0 idxen tfe +;CHECK: s_waitcnt +define amdgpu_cs float @buffer_load_i32_tfe(<4 x i32> inreg %rsrc, i32 addrspace(1)* %out) { + %load = call { i32, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_i32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) + %data = extractvalue { i32, i32 } %load, 0 + store i32 %data, i32 addrspace(1)* %out + %status = extractvalue { i32, i32 } %load, 1 + %fstatus = bitcast i32 %status to float + ret float %fstatus +} + +;CHECK-LABEL: {{^}}buffer_load_f32_tfe: +;CHECK: buffer_load_format_x v[2:3], {{v[0-9]+}}, s[0:3], 0 idxen tfe +;CHECK: s_waitcnt +define amdgpu_cs float @buffer_load_f32_tfe(<4 x i32> inreg %rsrc, float addrspace(1)* %out) { + %load = call { float, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_f32i32s(<4 x i32> %rsrc, i32 0, i32 0, i32 0, i32 0) + %data = extractvalue { float, i32 } %load, 0 + store float %data, float addrspace(1)* %out + %status = extractvalue { float, i32 } %load, 1 + %fstatus = bitcast i32 %status to float + ret float %fstatus +} + declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32) #0 declare <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32>, i32, i32, i32, i32) #0 declare <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32, i32) #0 declare i32 @llvm.amdgcn.struct.buffer.load.format.i32(<4 x i32>, i32, i32, i32, i32) #0 +declare { <4 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v4i32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0 +declare { <4 x float>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v4f32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0 +declare { <3 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v3i32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0 +declare { <3 x float>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v3f32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0 +declare { <2 x i32>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v2i32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0 +declare { <2 x float>, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_v2f32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0 +declare { i32, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_i32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0 +declare { float, i32 } @llvm.amdgcn.struct.buffer.load.format.sl_f32i32s(<4 x i32>, i32, i32, i32, i32 immarg) #0 attributes #0 = { nounwind readonly } diff --git a/llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll b/llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll --- a/llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll +++ b/llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,SI -; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GCN,CI +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s -check-prefixes=GCN,SI +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s -check-prefixes=GCN,CI @local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/local-memory.r600.ll b/llvm/test/CodeGen/AMDGPU/local-memory.r600.ll --- a/llvm/test/CodeGen/AMDGPU/local-memory.r600.ll +++ b/llvm/test/CodeGen/AMDGPU/local-memory.r600.ll @@ -4,7 +4,7 @@ ; Check that the LDS size emitted correctly ; EG: .long 166120 -; EG-NEXT: .long 128 +; EG-NEXT: .long 0 ; FUNC-LABEL: {{^}}local_memory: @@ -36,7 +36,7 @@ ; Check that the LDS size emitted correctly ; EG: .long 166120 -; EG-NEXT: .long 8 +; EG-NEXT: .long 0 ; GCN: .long 47180 ; GCN-NEXT: .long 32900 diff --git a/llvm/test/CodeGen/AMDGPU/lower-kernel-and-module-lds.ll b/llvm/test/CodeGen/AMDGPU/lower-kernel-and-module-lds.ll --- a/llvm/test/CodeGen/AMDGPU/lower-kernel-and-module-lds.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-kernel-and-module-lds.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck %s -; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s @lds.size.1.align.1 = internal unnamed_addr addrspace(3) global [1 x i8] undef, align 1 @lds.size.2.align.2 = internal unnamed_addr addrspace(3) global [2 x i8] undef, align 2 @@ -8,7 +8,7 @@ @lds.size.16.align.16 = internal unnamed_addr addrspace(3) global [16 x i8] undef, align 16 ; CHECK: %llvm.amdgcn.module.lds.t = type { [8 x i8], [1 x i8] } -; CHECK: %llvm.amdgcn.kernel.k0.lds.t = type { [16 x i8], [4 x i8], [2 x i8] } +; CHECK: %llvm.amdgcn.kernel.k0.lds.t = type { [16 x i8], [4 x i8], [2 x i8], [1 x i8] } ; CHECK: %llvm.amdgcn.kernel.k1.lds.t = type { [16 x i8], [4 x i8], [2 x i8] } ; CHECK: %llvm.amdgcn.kernel.k2.lds.t = type { [2 x i8] } ; CHECK: %llvm.amdgcn.kernel.k3.lds.t = type { [4 x i8] } @@ -23,8 +23,8 @@ ;. define amdgpu_kernel void @k0() #0 { ; CHECK-LABEL: @k0( -; CHECK-NEXT: %lds.size.1.align.1.bc = bitcast [1 x i8] addrspace(3)* getelementptr inbounds (%llvm.amdgcn.module.lds.t, %llvm.amdgcn.module.lds.t addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 1) to i8 addrspace(3)* -; CHECK-NEXT: store i8 1, i8 addrspace(3)* %lds.size.1.align.1.bc, align 8 +; CHECK-NEXT: %lds.size.1.align.1.bc = bitcast [1 x i8] addrspace(3)* getelementptr inbounds (%llvm.amdgcn.kernel.k0.lds.t, %llvm.amdgcn.kernel.k0.lds.t addrspace(3)* @llvm.amdgcn.kernel.k0.lds, i32 0, i32 3) to i8 addrspace(3)* +; CHECK-NEXT: store i8 1, i8 addrspace(3)* %lds.size.1.align.1.bc, align 2, !alias.scope !0, !noalias !3 ; CHECK-NEXT: %lds.size.2.align.2.bc = bitcast [2 x i8] addrspace(3)* getelementptr inbounds (%llvm.amdgcn.kernel.k0.lds.t, %llvm.amdgcn.kernel.k0.lds.t addrspace(3)* @llvm.amdgcn.kernel.k0.lds, i32 0, i32 2) to i8 addrspace(3)* ; CHECK-NEXT: store i8 2, i8 addrspace(3)* %lds.size.2.align.2.bc, align 4 ; CHECK-NEXT: %lds.size.4.align.4.bc = bitcast [4 x i8] addrspace(3)* getelementptr inbounds (%llvm.amdgcn.kernel.k0.lds.t, %llvm.amdgcn.kernel.k0.lds.t addrspace(3)* @llvm.amdgcn.kernel.k0.lds, i32 0, i32 1) to i8 addrspace(3)* @@ -94,9 +94,15 @@ ret void } + +define amdgpu_kernel void @calls_f0() { + call void @f0() + ret void +} + define void @f0() { ; CHECK-LABEL: @f0( -; CHECK-NEXT: %lds.size.1.align.1.bc = bitcast [1 x i8] addrspace(3)* getelementptr inbounds (%llvm.amdgcn.module.lds.t, %llvm.amdgcn.module.lds.t addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 1) to i8 addrspace(3)* +; CHECK: %lds.size.1.align.1.bc = bitcast [1 x i8] addrspace(3)* getelementptr inbounds (%llvm.amdgcn.module.lds.t, %llvm.amdgcn.module.lds.t addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 1) to i8 addrspace(3)* ; CHECK-NEXT: store i8 1, i8 addrspace(3)* %lds.size.1.align.1.bc, align 8 ; CHECK-NEXT: %lds.size.8.align.8.bc = bitcast [8 x i8] addrspace(3)* getelementptr inbounds (%llvm.amdgcn.module.lds.t, %llvm.amdgcn.module.lds.t addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 0) to i8 addrspace(3)* ; CHECK-NEXT: store i8 8, i8 addrspace(3)* %lds.size.8.align.8.bc, align 8 diff --git a/llvm/test/CodeGen/AMDGPU/lower-kernel-lds-constexpr.ll b/llvm/test/CodeGen/AMDGPU/lower-kernel-lds-constexpr.ll --- a/llvm/test/CodeGen/AMDGPU/lower-kernel-lds-constexpr.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-kernel-lds-constexpr.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: -p --check-globals -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck %s -; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s @lds.1 = internal unnamed_addr addrspace(3) global [2 x i8] undef, align 1 diff --git a/llvm/test/CodeGen/AMDGPU/lower-kernel-lds-super-align.ll b/llvm/test/CodeGen/AMDGPU/lower-kernel-lds-super-align.ll --- a/llvm/test/CodeGen/AMDGPU/lower-kernel-lds-super-align.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-kernel-lds-super-align.ll @@ -1,7 +1,7 @@ -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-super-align-lds-globals=true < %s | FileCheck --check-prefixes=CHECK,SUPER-ALIGN_ON %s -; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-super-align-lds-globals=true < %s | FileCheck --check-prefixes=CHECK,SUPER-ALIGN_ON %s -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-super-align-lds-globals=false < %s | FileCheck --check-prefixes=CHECK,SUPER-ALIGN_OFF %s -; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-super-align-lds-globals=false < %s | FileCheck --check-prefixes=CHECK,SUPER-ALIGN_OFF %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-super-align-lds-globals=true --amdgpu-lower-module-lds-strategy=module < %s | FileCheck --check-prefixes=CHECK,SUPER-ALIGN_ON %s +; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-super-align-lds-globals=true --amdgpu-lower-module-lds-strategy=module < %s | FileCheck --check-prefixes=CHECK,SUPER-ALIGN_ON %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-super-align-lds-globals=false --amdgpu-lower-module-lds-strategy=module < %s | FileCheck --check-prefixes=CHECK,SUPER-ALIGN_OFF %s +; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-super-align-lds-globals=false --amdgpu-lower-module-lds-strategy=module < %s | FileCheck --check-prefixes=CHECK,SUPER-ALIGN_OFF %s ; CHECK: %llvm.amdgcn.kernel.k1.lds.t = type { [32 x i8] } ; CHECK: %llvm.amdgcn.kernel.k2.lds.t = type { i16, [2 x i8], i16 } diff --git a/llvm/test/CodeGen/AMDGPU/lower-kernel-lds.ll b/llvm/test/CodeGen/AMDGPU/lower-kernel-lds.ll --- a/llvm/test/CodeGen/AMDGPU/lower-kernel-lds.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-kernel-lds.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck %s -; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s @lds.size.1.align.1 = internal unnamed_addr addrspace(3) global [1 x i8] undef, align 1 @lds.size.2.align.2 = internal unnamed_addr addrspace(3) global [2 x i8] undef, align 2 diff --git a/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll b/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll --- a/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-memcpy.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=gfx900 -O3 < %s | FileCheck -check-prefix=GCN %s -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck %s -; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -O3 --amdgpu-lower-module-lds-strategy=module < %s | FileCheck -check-prefix=GCN %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s %vec_type = type { %vec_base } %vec_base = type { %union.anon } diff --git a/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll b/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll --- a/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck %s -; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s @a = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4 @b = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr-phi.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr-phi.ll --- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr-phi.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr-phi.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck %s -; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s @var = addrspace(3) global i32 undef, align 4 diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr.ll --- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr.ll @@ -1,12 +1,11 @@ -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck %s -; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s ; CHECK: %llvm.amdgcn.module.lds.t = type { float, float } +; CHECK: %llvm.amdgcn.kernel.timestwo.lds.t = type { float, float } @a_func = addrspace(3) global float undef, align 4 -; CHECK: %llvm.amdgcn.kernel.timestwo.lds.t = type { float } - @kern = addrspace(3) global float undef, align 4 ; @a_func is only used from a non-kernel function so is rewritten @@ -56,21 +55,20 @@ ; CHECK-LABEL: @timestwo() #0 ; CHECK-NOT: call void @llvm.donothing() - -; CHECK: %1 = bitcast float addrspace(3)* getelementptr inbounds (%llvm.amdgcn.module.lds.t, %llvm.amdgcn.module.lds.t addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 1) to i32 addrspace(3)* +; CHECK: %1 = bitcast float addrspace(3)* getelementptr inbounds (%llvm.amdgcn.kernel.timestwo.lds.t, %llvm.amdgcn.kernel.timestwo.lds.t addrspace(3)* @llvm.amdgcn.kernel.timestwo.lds, i32 0, i32 0) to i32 addrspace(3)* ; CHECK: %2 = addrspacecast i32 addrspace(3)* %1 to i32* ; CHECK: %3 = ptrtoint i32* %2 to i64 -; CHECK: %4 = bitcast float addrspace(3)* getelementptr inbounds (%llvm.amdgcn.kernel.timestwo.lds.t, %llvm.amdgcn.kernel.timestwo.lds.t addrspace(3)* @llvm.amdgcn.kernel.timestwo.lds, i32 0, i32 0) to i32 addrspace(3)* +; CHECK: %4 = bitcast float addrspace(3)* getelementptr inbounds (%llvm.amdgcn.kernel.timestwo.lds.t, %llvm.amdgcn.kernel.timestwo.lds.t addrspace(3)* @llvm.amdgcn.kernel.timestwo.lds, i32 0, i32 1) to i32 addrspace(3)* ; CHECK: %5 = addrspacecast i32 addrspace(3)* %4 to i32* ; CHECK: %6 = ptrtoint i32* %5 to i64 ; CHECK: %7 = add i64 %3, %6 ; CHECK: %8 = inttoptr i64 %7 to i32* ; CHECK: %ld = load i32, i32* %8, align 4 ; CHECK: %mul = mul i32 %ld, 2 -; CHECK: %9 = bitcast float addrspace(3)* getelementptr inbounds (%llvm.amdgcn.kernel.timestwo.lds.t, %llvm.amdgcn.kernel.timestwo.lds.t addrspace(3)* @llvm.amdgcn.kernel.timestwo.lds, i32 0, i32 0) to i32 addrspace(3)* +; CHECK: %9 = bitcast float addrspace(3)* getelementptr inbounds (%llvm.amdgcn.kernel.timestwo.lds.t, %llvm.amdgcn.kernel.timestwo.lds.t addrspace(3)* @llvm.amdgcn.kernel.timestwo.lds, i32 0, i32 1) to i32 addrspace(3)* ; CHECK: %10 = addrspacecast i32 addrspace(3)* %9 to i32* ; CHECK: %11 = ptrtoint i32* %10 to i64 -; CHECK: %12 = bitcast float addrspace(3)* getelementptr inbounds (%llvm.amdgcn.module.lds.t, %llvm.amdgcn.module.lds.t addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 1) to i32 addrspace(3)* +; CHECK: %12 = bitcast float addrspace(3)* getelementptr inbounds (%llvm.amdgcn.kernel.timestwo.lds.t, %llvm.amdgcn.kernel.timestwo.lds.t addrspace(3)* @llvm.amdgcn.kernel.timestwo.lds, i32 0, i32 0) to i32 addrspace(3)* ; CHECK: %13 = addrspacecast i32 addrspace(3)* %12 to i32* ; CHECK: %14 = ptrtoint i32* %13 to i64 ; CHECK: %15 = add i64 %11, %14 @@ -84,5 +82,13 @@ ret void } +; CHECK-LABEL: @through_functions() +define amdgpu_kernel void @through_functions() { + %ld = call i32 @get_func() + %mul = mul i32 %ld, 4 + call void @set_func(i32 %mul) + ret void +} + attributes #0 = { "amdgpu-elide-module-lds" } ; CHECK: attributes #0 = { "amdgpu-elide-module-lds" } diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-inactive.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-inactive.ll --- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-inactive.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-inactive.ll @@ -6,8 +6,8 @@ ; CHECK-NOT: llvm.amdgcn.module.lds ; CHECK-NOT: llvm.amdgcn.module.lds.t -; var1, var2 would be transformed were they used from a non-kernel function -; CHECK-NOT: @var1 = +; var1 is removed, var2 stays because it's in compiler.used +; CHECK-NOT: @var1 ; CHECK: @var2 = addrspace(3) global float undef @var1 = addrspace(3) global i32 undef @var2 = addrspace(3) global float undef diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll --- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck -check-prefix=OPT %s -; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck -check-prefix=OPT %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -check-prefix=OPT %s +; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -check-prefix=OPT %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -check-prefix=GCN %s ; Check that module LDS is allocated at address 0 and kernel starts its ; allocation past module LDS when a call is present. diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-ambiguous.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-ambiguous.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-ambiguous.ll @@ -0,0 +1,97 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -check-prefixes=CHECK,M_OR_HY %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=table | FileCheck -check-prefixes=CHECK,TABLE %s +; RUN: not --crash opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=kernel 2>&1 | FileCheck -check-prefixes=KERNEL %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=hybrid | FileCheck -check-prefixes=CHECK,M_OR_HY %s + +;; Two kernels access the same variable, specialisation gives them each their own copy of it + +@kernel.lds = addrspace(3) global i8 undef +define amdgpu_kernel void @k0() { +; CHECK-LABEL: @k0( +; CHECK-NEXT: [[LD:%.*]] = load i8, i8 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K0_LDS_T:%.*]], [[LLVM_AMDGCN_KERNEL_K0_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k0.lds, i32 0, i32 0), align 1 +; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[LD]], 2 +; CHECK-NEXT: store i8 [[MUL]], i8 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K0_LDS_T]], [[LLVM_AMDGCN_KERNEL_K0_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k0.lds, i32 0, i32 0), align 1 +; CHECK-NEXT: ret void +; + %ld = load i8, i8 addrspace(3)* @kernel.lds + %mul = mul i8 %ld, 2 + store i8 %mul, i8 addrspace(3)* @kernel.lds + ret void +} + +define amdgpu_kernel void @k1() { +; CHECK-LABEL: @k1( +; CHECK-NEXT: [[LD:%.*]] = load i8, i8 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K1_LDS_T:%.*]], [[LLVM_AMDGCN_KERNEL_K1_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k1.lds, i32 0, i32 0), align 1 +; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[LD]], 3 +; CHECK-NEXT: store i8 [[MUL]], i8 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K1_LDS_T]], [[LLVM_AMDGCN_KERNEL_K1_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k1.lds, i32 0, i32 0), align 1 +; CHECK-NEXT: ret void +; + %ld = load i8, i8 addrspace(3)* @kernel.lds + %mul = mul i8 %ld, 3 + store i8 %mul, i8 addrspace(3)* @kernel.lds + ret void +} + +;; Function accesses variable, reachable from two kernels, can't use kernel lowering for either +;; Hybrid can put it in module lds without cost as the first variable is free + +; KERNEL: LLVM ERROR: Cannot lower LDS to kernel access as it is reachable from multiple kernels + +@function.lds = addrspace(3) global i16 undef +define void @f0() { +; M_OR_HY-LABEL: @f0( +; M_OR_HY-NEXT: [[LD:%.*]] = load i16, i16 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_MODULE_LDS_T:%.*]], [[LLVM_AMDGCN_MODULE_LDS_T]] addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 0), align 2 +; M_OR_HY-NEXT: [[MUL:%.*]] = mul i16 [[LD]], 4 +; M_OR_HY-NEXT: store i16 [[MUL]], i16 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_MODULE_LDS_T]], [[LLVM_AMDGCN_MODULE_LDS_T]] addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 0), align 2 +; M_OR_HY-NEXT: ret void +; +; TABLE-LABEL: @f0( +; TABLE-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id() +; TABLE-NEXT: [[FUNCTION_LDS2:%.*]] = getelementptr inbounds [2 x [1 x i32]], [2 x [1 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 0 +; TABLE-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(4)* [[FUNCTION_LDS2]], align 4 +; TABLE-NEXT: [[FUNCTION_LDS3:%.*]] = inttoptr i32 [[TMP2]] to i16 addrspace(3)* +; TABLE-NEXT: [[LD:%.*]] = load i16, i16 addrspace(3)* [[FUNCTION_LDS3]], align 2 +; TABLE-NEXT: [[MUL:%.*]] = mul i16 [[LD]], 4 +; TABLE-NEXT: [[FUNCTION_LDS:%.*]] = getelementptr inbounds [2 x [1 x i32]], [2 x [1 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 0 +; TABLE-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(4)* [[FUNCTION_LDS]], align 4 +; TABLE-NEXT: [[FUNCTION_LDS1:%.*]] = inttoptr i32 [[TMP3]] to i16 addrspace(3)* +; TABLE-NEXT: store i16 [[MUL]], i16 addrspace(3)* [[FUNCTION_LDS1]], align 2 +; TABLE-NEXT: ret void +; + %ld = load i16, i16 addrspace(3)* @function.lds + %mul = mul i16 %ld, 4 + store i16 %mul, i16 addrspace(3)* @function.lds + ret void +} + + +define amdgpu_kernel void @k0_f0() { +; M_OR_HY-LABEL: @k0_f0( +; M_OR_HY-NEXT: call void @llvm.donothing() [ "ExplicitUse"([[LLVM_AMDGCN_MODULE_LDS_T:%.*]] addrspace(3)* @llvm.amdgcn.module.lds) ] +; M_OR_HY-NEXT: call void @f0() +; M_OR_HY-NEXT: ret void +; +; TABLE-LABEL: @k0_f0( +; TABLE-NEXT: call void @llvm.donothing() [ "ExplicitUse"([[LLVM_AMDGCN_KERNEL_K0_F0_LDS_T:%.*]] addrspace(3)* @llvm.amdgcn.kernel.k0_f0.lds) ] +; TABLE-NEXT: call void @f0() +; TABLE-NEXT: ret void +; + call void @f0() + ret void +} + +define amdgpu_kernel void @k1_f0() { +; M_OR_HY-LABEL: @k1_f0( +; M_OR_HY-NEXT: call void @llvm.donothing() [ "ExplicitUse"([[LLVM_AMDGCN_MODULE_LDS_T:%.*]] addrspace(3)* @llvm.amdgcn.module.lds) ] +; M_OR_HY-NEXT: call void @f0() +; M_OR_HY-NEXT: ret void +; +; TABLE-LABEL: @k1_f0( +; TABLE-NEXT: call void @llvm.donothing() [ "ExplicitUse"([[LLVM_AMDGCN_KERNEL_K1_F0_LDS_T:%.*]] addrspace(3)* @llvm.amdgcn.kernel.k1_f0.lds) ] +; TABLE-NEXT: call void @f0() +; TABLE-NEXT: ret void +; + call void @f0() + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-unambiguous.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-unambiguous.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-unambiguous.ll @@ -0,0 +1,144 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -check-prefixes=CHECK,MODULE %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=table | FileCheck -check-prefixes=CHECK,TABLE %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=kernel | FileCheck -check-prefixes=CHECK,K_OR_HY %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=hybrid | FileCheck -check-prefixes=CHECK,K_OR_HY %s + +;; Same checks for kernel and for hybrid as an unambiguous reference to a variable - one where exactly one kernel +;; can reach it - is the case where hybrid lowering can always prefer the direct access. + +;; Single kernel is sole user of single variable, all options codegen as direct access to kernel struct + +@k0.lds = addrspace(3) global i8 undef +define amdgpu_kernel void @k0() { +; CHECK-LABEL: @k0( +; CHECK-NEXT: [[LD:%.*]] = load i8, i8 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K0_LDS_T:%.*]], [[LLVM_AMDGCN_KERNEL_K0_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k0.lds, i32 0, i32 0), align 1 +; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[LD]], 2 +; CHECK-NEXT: store i8 [[MUL]], i8 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K0_LDS_T]], [[LLVM_AMDGCN_KERNEL_K0_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k0.lds, i32 0, i32 0), align 1 +; CHECK-NEXT: ret void +; + %ld = load i8, i8 addrspace(3)* @k0.lds + %mul = mul i8 %ld, 2 + store i8 %mul, i8 addrspace(3)* @k0.lds + ret void +} + +;; Function is reachable from one kernel. Variable goes in module lds or the kernel struct, but never both. + +@f0.lds = addrspace(3) global i16 undef +define void @f0() { +; MODULE-LABEL: @f0( +; MODULE-NEXT: [[LD:%.*]] = load i16, i16 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_MODULE_LDS_T:%.*]], [[LLVM_AMDGCN_MODULE_LDS_T]] addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 1), align 4, !alias.scope !0, !noalias !3 +; MODULE-NEXT: [[MUL:%.*]] = mul i16 [[LD]], 3 +; MODULE-NEXT: store i16 [[MUL]], i16 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_MODULE_LDS_T]], [[LLVM_AMDGCN_MODULE_LDS_T]] addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 1), align 4, !alias.scope !0, !noalias !3 +; MODULE-NEXT: ret void +; +; TABLE-LABEL: @f0( +; TABLE-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id() +; TABLE-NEXT: [[F0_LDS2:%.*]] = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 1 +; TABLE-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(4)* [[F0_LDS2]], align 4 +; TABLE-NEXT: [[F0_LDS3:%.*]] = inttoptr i32 [[TMP2]] to i16 addrspace(3)* +; TABLE-NEXT: [[LD:%.*]] = load i16, i16 addrspace(3)* [[F0_LDS3]], align 2 +; TABLE-NEXT: [[MUL:%.*]] = mul i16 [[LD]], 3 +; TABLE-NEXT: [[F0_LDS:%.*]] = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 1 +; TABLE-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(4)* [[F0_LDS]], align 4 +; TABLE-NEXT: [[F0_LDS1:%.*]] = inttoptr i32 [[TMP3]] to i16 addrspace(3)* +; TABLE-NEXT: store i16 [[MUL]], i16 addrspace(3)* [[F0_LDS1]], align 2 +; TABLE-NEXT: ret void +; +; K_OR_HY-LABEL: @f0( +; K_OR_HY-NEXT: [[LD:%.*]] = load i16, i16 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K_F0_LDS_T:%.*]], [[LLVM_AMDGCN_KERNEL_K_F0_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k_f0.lds, i32 0, i32 0), align 2 +; K_OR_HY-NEXT: [[MUL:%.*]] = mul i16 [[LD]], 3 +; K_OR_HY-NEXT: store i16 [[MUL]], i16 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K_F0_LDS_T]], [[LLVM_AMDGCN_KERNEL_K_F0_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k_f0.lds, i32 0, i32 0), align 2 +; K_OR_HY-NEXT: ret void +; + %ld = load i16, i16 addrspace(3)* @f0.lds + %mul = mul i16 %ld, 3 + store i16 %mul, i16 addrspace(3)* @f0.lds + ret void +} + +define amdgpu_kernel void @k_f0() { +; MODULE-LABEL: @k_f0( +; MODULE-NEXT: call void @llvm.donothing() [ "ExplicitUse"([[LLVM_AMDGCN_MODULE_LDS_T:%.*]] addrspace(3)* @llvm.amdgcn.module.lds) ] +; MODULE-NEXT: call void @f0() +; MODULE-NEXT: ret void +; +; TABLE-LABEL: @k_f0( +; TABLE-NEXT: call void @llvm.donothing() [ "ExplicitUse"([[LLVM_AMDGCN_KERNEL_K_F0_LDS_T:%.*]] addrspace(3)* @llvm.amdgcn.kernel.k_f0.lds) ] +; TABLE-NEXT: call void @f0() +; TABLE-NEXT: ret void +; +; K_OR_HY-LABEL: @k_f0( +; K_OR_HY-NEXT: call void @f0() +; K_OR_HY-NEXT: ret void +; + call void @f0() + ret void +} + +;; As above, but with the kernel also uing the variable. + +@both.lds = addrspace(3) global i32 undef +define void @f_both() { +; MODULE-LABEL: @f_both( +; MODULE-NEXT: [[LD:%.*]] = load i32, i32 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_MODULE_LDS_T:%.*]], [[LLVM_AMDGCN_MODULE_LDS_T]] addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 0), align 4, !alias.scope !4, !noalias !3 +; MODULE-NEXT: [[MUL:%.*]] = mul i32 [[LD]], 4 +; MODULE-NEXT: store i32 [[MUL]], i32 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_MODULE_LDS_T]], [[LLVM_AMDGCN_MODULE_LDS_T]] addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 0), align 4, !alias.scope !4, !noalias !3 +; MODULE-NEXT: ret void +; +; TABLE-LABEL: @f_both( +; TABLE-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id() +; TABLE-NEXT: [[BOTH_LDS2:%.*]] = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 0 +; TABLE-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(4)* [[BOTH_LDS2]], align 4 +; TABLE-NEXT: [[BOTH_LDS3:%.*]] = inttoptr i32 [[TMP2]] to i32 addrspace(3)* +; TABLE-NEXT: [[LD:%.*]] = load i32, i32 addrspace(3)* [[BOTH_LDS3]], align 4 +; TABLE-NEXT: [[MUL:%.*]] = mul i32 [[LD]], 4 +; TABLE-NEXT: [[BOTH_LDS:%.*]] = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 0 +; TABLE-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(4)* [[BOTH_LDS]], align 4 +; TABLE-NEXT: [[BOTH_LDS1:%.*]] = inttoptr i32 [[TMP3]] to i32 addrspace(3)* +; TABLE-NEXT: store i32 [[MUL]], i32 addrspace(3)* [[BOTH_LDS1]], align 4 +; TABLE-NEXT: ret void +; +; K_OR_HY-LABEL: @f_both( +; K_OR_HY-NEXT: [[LD:%.*]] = load i32, i32 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K0_BOTH_LDS_T:%.*]], [[LLVM_AMDGCN_KERNEL_K0_BOTH_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k0_both.lds, i32 0, i32 0), align 4 +; K_OR_HY-NEXT: [[MUL:%.*]] = mul i32 [[LD]], 4 +; K_OR_HY-NEXT: store i32 [[MUL]], i32 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K0_BOTH_LDS_T]], [[LLVM_AMDGCN_KERNEL_K0_BOTH_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k0_both.lds, i32 0, i32 0), align 4 +; K_OR_HY-NEXT: ret void +; + %ld = load i32, i32 addrspace(3)* @both.lds + %mul = mul i32 %ld, 4 + store i32 %mul, i32 addrspace(3)* @both.lds + ret void +} + +define amdgpu_kernel void @k0_both() { +; MODULE-LABEL: @k0_both( +; MODULE-NEXT: call void @llvm.donothing() [ "ExplicitUse"([[LLVM_AMDGCN_MODULE_LDS_T:%.*]] addrspace(3)* @llvm.amdgcn.module.lds) ] +; MODULE-NEXT: [[LD:%.*]] = load i32, i32 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_MODULE_LDS_T]], [[LLVM_AMDGCN_MODULE_LDS_T]] addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 0), align 4, !alias.scope !4, !noalias !0 +; MODULE-NEXT: [[MUL:%.*]] = mul i32 [[LD]], 5 +; MODULE-NEXT: store i32 [[MUL]], i32 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_MODULE_LDS_T]], [[LLVM_AMDGCN_MODULE_LDS_T]] addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 0), align 4, !alias.scope !4, !noalias !0 +; MODULE-NEXT: call void @f_both() +; MODULE-NEXT: ret void +; +; TABLE-LABEL: @k0_both( +; TABLE-NEXT: call void @llvm.donothing() [ "ExplicitUse"([[LLVM_AMDGCN_KERNEL_K0_BOTH_LDS_T:%.*]] addrspace(3)* @llvm.amdgcn.kernel.k0_both.lds) ] +; TABLE-NEXT: [[LD:%.*]] = load i32, i32 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K0_BOTH_LDS_T]], [[LLVM_AMDGCN_KERNEL_K0_BOTH_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k0_both.lds, i32 0, i32 0), align 4 +; TABLE-NEXT: [[MUL:%.*]] = mul i32 [[LD]], 5 +; TABLE-NEXT: store i32 [[MUL]], i32 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K0_BOTH_LDS_T]], [[LLVM_AMDGCN_KERNEL_K0_BOTH_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k0_both.lds, i32 0, i32 0), align 4 +; TABLE-NEXT: call void @f_both() +; TABLE-NEXT: ret void +; +; K_OR_HY-LABEL: @k0_both( +; K_OR_HY-NEXT: [[LD:%.*]] = load i32, i32 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K0_BOTH_LDS_T:%.*]], [[LLVM_AMDGCN_KERNEL_K0_BOTH_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k0_both.lds, i32 0, i32 0), align 4 +; K_OR_HY-NEXT: [[MUL:%.*]] = mul i32 [[LD]], 5 +; K_OR_HY-NEXT: store i32 [[MUL]], i32 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K0_BOTH_LDS_T]], [[LLVM_AMDGCN_KERNEL_K0_BOTH_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k0_both.lds, i32 0, i32 0), align 4 +; K_OR_HY-NEXT: call void @f_both() +; K_OR_HY-NEXT: ret void +; + %ld = load i32, i32 addrspace(3)* @both.lds + %mul = mul i32 %ld, 5 + store i32 %mul, i32 addrspace(3)* @both.lds + call void @f_both() + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-used-list.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-used-list.ll --- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-used-list.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-used-list.ll @@ -1,5 +1,5 @@ -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck %s -; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s ; Check new struct is added to compiler.used and that the replaced variable is removed @@ -28,6 +28,13 @@ @llvm.compiler.used = appending global [2 x i8*] [i8* addrspacecast (i8 addrspace(3)* bitcast (float addrspace(3)* @tolower to i8 addrspace(3)*) to i8*), i8* addrspacecast (i8 addrspace(1)* bitcast (i64 addrspace(1)* @ignored to i8 addrspace(1)*) to i8*)], section "llvm.metadata" + +; Functions that are not called are ignored by the lowering +define amdgpu_kernel void @call_func() { + call void @func() + ret void +} + ; CHECK-LABEL: @func() ; CHECK: %dec = atomicrmw fsub float addrspace(3)* getelementptr inbounds (%llvm.amdgcn.module.lds.t, %llvm.amdgcn.module.lds.t addrspace(3)* @llvm.amdgcn.module.lds, i32 0, i32 0), float 1.000000e+00 monotonic, align 8 define void @func() { diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll @@ -0,0 +1,373 @@ +; RUN: opt -S -mtriple=amdgcn--amdhsa -amdgpu-lower-module-lds < %s --amdgpu-lower-module-lds-strategy=table | FileCheck -check-prefix=OPT %s +; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=table | FileCheck -check-prefix=GCN %s + +; Opt checks from utils/update_test_checks.py, llc checks from utils/update_llc_test_checks.py, both modified. + +; Define four variables and four non-kernel functions which access exactly one variable each +@v0 = addrspace(3) global float undef +@v1 = addrspace(3) global i16 undef, align 16 +@v2 = addrspace(3) global i64 undef +@v3 = addrspace(3) global i8 undef +@unused = addrspace(3) global i16 undef + +; OPT: %llvm.amdgcn.kernel.kernel_no_table.lds.t = type { i64 } +; OPT: %llvm.amdgcn.kernel.k01.lds.t = type { i16, [2 x i8], float } +; OPT: %llvm.amdgcn.kernel.k23.lds.t = type { i64, i8 } +; OPT: %llvm.amdgcn.kernel.k123.lds.t = type { i16, i8, [5 x i8], i64 } + +; OPT: @llvm.amdgcn.kernel.kernel_no_table.lds = internal addrspace(3) global %llvm.amdgcn.kernel.kernel_no_table.lds.t undef, align 8 +; OPT: @llvm.amdgcn.kernel.k01.lds = internal addrspace(3) global %llvm.amdgcn.kernel.k01.lds.t undef, align 16 +; OPT: @llvm.amdgcn.kernel.k23.lds = internal addrspace(3) global %llvm.amdgcn.kernel.k23.lds.t undef, align 8 +; OPT: @llvm.amdgcn.kernel.k123.lds = internal addrspace(3) global %llvm.amdgcn.kernel.k123.lds.t undef, align 16 + +; Salient parts of the IR lookup table check: +; It has (top level) size 3 as there are 3 kernels that call functions which use lds +; The next level down has type [4 x i16] as there are 4 variables accessed by functions which use lds +; The kernel naming pattern and the structs being named after the functions helps verify placement of undef +; The remainder are constant expressions into the variable instances checked above + +; OPT{LITERAL}: @llvm.amdgcn.lds.offset.table = internal addrspace(4) constant [3 x [4 x i32]] [[4 x i32] [i32 ptrtoint (float addrspace(3)* getelementptr inbounds (%llvm.amdgcn.kernel.k01.lds.t, %llvm.amdgcn.kernel.k01.lds.t addrspace(3)* @llvm.amdgcn.kernel.k01.lds, i32 0, i32 2) to i32), i32 ptrtoint (%llvm.amdgcn.kernel.k01.lds.t addrspace(3)* @llvm.amdgcn.kernel.k01.lds to i32), i32 poison, i32 poison], [4 x i32] [i32 poison, i32 ptrtoint (%llvm.amdgcn.kernel.k123.lds.t addrspace(3)* @llvm.amdgcn.kernel.k123.lds to i32), i32 ptrtoint (i64 addrspace(3)* getelementptr inbounds (%llvm.amdgcn.kernel.k123.lds.t, %llvm.amdgcn.kernel.k123.lds.t addrspace(3)* @llvm.amdgcn.kernel.k123.lds, i32 0, i32 3) to i32), i32 ptrtoint (i8 addrspace(3)* getelementptr inbounds (%llvm.amdgcn.kernel.k123.lds.t, %llvm.amdgcn.kernel.k123.lds.t addrspace(3)* @llvm.amdgcn.kernel.k123.lds, i32 0, i32 1) to i32)], [4 x i32] [i32 poison, i32 poison, i32 ptrtoint (%llvm.amdgcn.kernel.k23.lds.t addrspace(3)* @llvm.amdgcn.kernel.k23.lds to i32), i32 ptrtoint (i8 addrspace(3)* getelementptr inbounds (%llvm.amdgcn.kernel.k23.lds.t, %llvm.amdgcn.kernel.k23.lds.t addrspace(3)* @llvm.amdgcn.kernel.k23.lds, i32 0, i32 1) to i32)]] + +define void @f0() { +; OPT-LABEL: @f0( +; OPT-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id() +; OPT-NEXT: [[V02:%.*]] = getelementptr inbounds [3 x [4 x i32]], [3 x [4 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 0 +; OPT-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(4)* [[V02]], align 4 +; OPT-NEXT: [[V03:%.*]] = inttoptr i32 [[TMP2]] to float addrspace(3)* +; OPT-NEXT: [[LD:%.*]] = load float, float addrspace(3)* [[V03]], align 4 +; OPT-NEXT: [[MUL:%.*]] = fmul float [[LD]], 2.000000e+00 +; OPT-NEXT: [[V0:%.*]] = getelementptr inbounds [3 x [4 x i32]], [3 x [4 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 0 +; OPT-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(4)* [[V0]], align 4 +; OPT-NEXT: [[V01:%.*]] = inttoptr i32 [[TMP3]] to float addrspace(3)* +; OPT-NEXT: store float [[MUL]], float addrspace(3)* [[V01]], align 4 +; OPT-NEXT: ret void +; +; GCN-LABEL: f0: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s4, s15 +; GCN-NEXT: s_ashr_i32 s5, s15, 31 +; GCN-NEXT: s_getpc_b64 s[6:7] +; GCN-NEXT: s_add_u32 s6, s6, llvm.amdgcn.lds.offset.table@rel32@lo+4 +; GCN-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.lds.offset.table@rel32@hi+12 +; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4 +; GCN-NEXT: s_add_u32 s4, s4, s6 +; GCN-NEXT: s_addc_u32 s5, s5, s7 +; GCN-NEXT: s_load_dword s4, s[4:5], 0x0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: s_mov_b32 m0, -1 +; GCN-NEXT: ds_read_b32 v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_add_f32_e32 v1, v1, v1 +; GCN-NEXT: ds_write_b32 v0, v1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] + %ld = load float, float addrspace(3)* @v0 + %mul = fmul float %ld, 2. + store float %mul, float addrspace(3)* @v0 + ret void +} + +define void @f1() { +; OPT-LABEL: @f1( +; OPT-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id() +; OPT-NEXT: [[V12:%.*]] = getelementptr inbounds [3 x [4 x i32]], [3 x [4 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 1 +; OPT-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(4)* [[V12]], align 4 +; OPT-NEXT: [[V13:%.*]] = inttoptr i32 [[TMP2]] to i16 addrspace(3)* +; OPT-NEXT: [[LD:%.*]] = load i16, i16 addrspace(3)* [[V13]], align 2 +; OPT-NEXT: [[MUL:%.*]] = mul i16 [[LD]], 3 +; OPT-NEXT: [[V1:%.*]] = getelementptr inbounds [3 x [4 x i32]], [3 x [4 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 1 +; OPT-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(4)* [[V1]], align 4 +; OPT-NEXT: [[V11:%.*]] = inttoptr i32 [[TMP3]] to i16 addrspace(3)* +; OPT-NEXT: store i16 [[MUL]], i16 addrspace(3)* [[V11]], align 2 +; OPT-NEXT: ret void +; +; GCN-LABEL: f1: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s4, s15 +; GCN-NEXT: s_ashr_i32 s5, s15, 31 +; GCN-NEXT: s_getpc_b64 s[6:7] +; GCN-NEXT: s_add_u32 s6, s6, llvm.amdgcn.lds.offset.table@rel32@lo+8 +; GCN-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.lds.offset.table@rel32@hi+16 +; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4 +; GCN-NEXT: s_add_u32 s4, s4, s6 +; GCN-NEXT: s_addc_u32 s5, s5, s7 +; GCN-NEXT: s_load_dword s4, s[4:5], 0x0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: s_mov_b32 m0, -1 +; GCN-NEXT: ds_read_u16 v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mul_lo_u32 v1, v1, 3 +; GCN-NEXT: ds_write_b16 v0, v1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] + %ld = load i16, i16 addrspace(3)* @v1 + %mul = mul i16 %ld, 3 + store i16 %mul, i16 addrspace(3)* @v1 + ret void +} + +define void @f2() { +; OPT-LABEL: @f2( +; OPT-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id() +; OPT-NEXT: [[V22:%.*]] = getelementptr inbounds [3 x [4 x i32]], [3 x [4 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 2 +; OPT-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(4)* [[V22]], align 4 +; OPT-NEXT: [[V23:%.*]] = inttoptr i32 [[TMP2]] to i64 addrspace(3)* +; OPT-NEXT: [[LD:%.*]] = load i64, i64 addrspace(3)* [[V23]], align 4 +; OPT-NEXT: [[MUL:%.*]] = mul i64 [[LD]], 4 +; OPT-NEXT: [[V2:%.*]] = getelementptr inbounds [3 x [4 x i32]], [3 x [4 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 2 +; OPT-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(4)* [[V2]], align 4 +; OPT-NEXT: [[V21:%.*]] = inttoptr i32 [[TMP3]] to i64 addrspace(3)* +; OPT-NEXT: store i64 [[MUL]], i64 addrspace(3)* [[V21]], align 4 +; OPT-NEXT: ret void +; +; GCN-LABEL: f2: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s4, s15 +; GCN-NEXT: s_ashr_i32 s5, s15, 31 +; GCN-NEXT: s_getpc_b64 s[6:7] +; GCN-NEXT: s_add_u32 s6, s6, llvm.amdgcn.lds.offset.table@rel32@lo+12 +; GCN-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.lds.offset.table@rel32@hi+20 +; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4 +; GCN-NEXT: s_add_u32 s4, s4, s6 +; GCN-NEXT: s_addc_u32 s5, s5, s7 +; GCN-NEXT: s_load_dword s4, s[4:5], 0x0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v2, s4 +; GCN-NEXT: s_mov_b32 m0, -1 +; GCN-NEXT: ds_read_b64 v[0:1], v2 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], 2 +; GCN-NEXT: ds_write_b64 v2, v[0:1] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] + %ld = load i64, i64 addrspace(3)* @v2 + %mul = mul i64 %ld, 4 + store i64 %mul, i64 addrspace(3)* @v2 + ret void +} + +define void @f3() { +; OPT-LABEL: @f3( +; OPT-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id() +; OPT-NEXT: [[V32:%.*]] = getelementptr inbounds [3 x [4 x i32]], [3 x [4 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 3 +; OPT-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(4)* [[V32]], align 4 +; OPT-NEXT: [[V33:%.*]] = inttoptr i32 [[TMP2]] to i8 addrspace(3)* +; OPT-NEXT: [[LD:%.*]] = load i8, i8 addrspace(3)* [[V33]], align 1 +; OPT-NEXT: [[MUL:%.*]] = mul i8 [[LD]], 5 +; OPT-NEXT: [[V3:%.*]] = getelementptr inbounds [3 x [4 x i32]], [3 x [4 x i32]] addrspace(4)* @llvm.amdgcn.lds.offset.table, i32 0, i32 [[TMP1]], i32 3 +; OPT-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(4)* [[V3]], align 4 +; OPT-NEXT: [[V31:%.*]] = inttoptr i32 [[TMP3]] to i8 addrspace(3)* +; OPT-NEXT: store i8 [[MUL]], i8 addrspace(3)* [[V31]], align 1 +; OPT-NEXT: ret void +; +; GCN-LABEL: f3: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s4, s15 +; GCN-NEXT: s_ashr_i32 s5, s15, 31 +; GCN-NEXT: s_getpc_b64 s[6:7] +; GCN-NEXT: s_add_u32 s6, s6, llvm.amdgcn.lds.offset.table@rel32@lo+16 +; GCN-NEXT: s_addc_u32 s7, s7, llvm.amdgcn.lds.offset.table@rel32@hi+24 +; GCN-NEXT: s_lshl_b64 s[4:5], s[4:5], 4 +; GCN-NEXT: s_add_u32 s4, s4, s6 +; GCN-NEXT: s_addc_u32 s5, s5, s7 +; GCN-NEXT: s_load_dword s4, s[4:5], 0x0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: s_mov_b32 m0, -1 +; GCN-NEXT: ds_read_u8 v1, v0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_mul_lo_u32 v1, v1, 5 +; GCN-NEXT: ds_write_b8 v0, v1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_setpc_b64 s[30:31] + %ld = load i8, i8 addrspace(3)* @v3 + %mul = mul i8 %ld, 5 + store i8 %mul, i8 addrspace(3)* @v3 + ret void +} + +; Doesn't access any via a function, won't be in the lookup table +define amdgpu_kernel void @kernel_no_table() { +; OPT-LABEL: @kernel_no_table() { +; OPT-NEXT: [[LD:%.*]] = load i64, i64 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_KERNEL_NO_TABLE_LDS_T:%.*]], [[LLVM_AMDGCN_KERNEL_KERNEL_NO_TABLE_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.kernel_no_table.lds, i32 0, i32 0), align 8 +; OPT-NEXT: [[MUL:%.*]] = mul i64 [[LD]], 8 +; OPT-NEXT: store i64 [[MUL]], i64 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_KERNEL_NO_TABLE_LDS_T]], [[LLVM_AMDGCN_KERNEL_KERNEL_NO_TABLE_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.kernel_no_table.lds, i32 0, i32 0), align 8 +; OPT-NEXT: ret void +; +; GCN-LABEL: kernel_no_table: +; GCN: ; %bb.0: +; GCN-NEXT: v_mov_b32_e32 v2, 0 +; GCN-NEXT: s_mov_b32 m0, -1 +; GCN-NEXT: ds_read_b64 v[0:1], v2 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_lshl_b64 v[0:1], v[0:1], 3 +; GCN-NEXT: ds_write_b64 v2, v[0:1] +; GCN-NEXT: s_endpgm + %ld = load i64, i64 addrspace(3)* @v2 + %mul = mul i64 %ld, 8 + store i64 %mul, i64 addrspace(3)* @v2 + ret void +} + +; Access two variables, will allocate those two +define amdgpu_kernel void @k01() { +; OPT-LABEL: @k01() !llvm.amdgcn.lds.kernel.id !0 { +; OPT-NEXT: call void @llvm.donothing() [ "ExplicitUse"([[LLVM_AMDGCN_KERNEL_K01_LDS_T:%.*]] addrspace(3)* @llvm.amdgcn.kernel.k01.lds) ] +; OPT-NEXT: call void @f0() +; OPT-NEXT: call void @f1() +; OPT-NEXT: ret void +; +; GCN-LABEL: k01: +; GCN: ; %bb.0: +; GCN-NEXT: s_mov_b32 s32, 0 +; GCN-NEXT: s_mov_b32 flat_scratch_lo, s7 +; GCN-NEXT: s_add_i32 s6, s6, s9 +; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s6, 8 +; GCN-NEXT: s_add_u32 s0, s0, s9 +; GCN-NEXT: s_addc_u32 s1, s1, 0 +; GCN-NEXT: s_mov_b64 s[8:9], s[4:5] +; GCN-NEXT: s_getpc_b64 s[4:5] +; GCN-NEXT: s_add_u32 s4, s4, f0@gotpcrel32@lo+4 +; GCN-NEXT: s_addc_u32 s5, s5, f0@gotpcrel32@hi+12 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 +; GCN-NEXT: s_mov_b32 s15, 0 +; GCN-NEXT: s_mov_b64 s[6:7], s[8:9] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] +; GCN-NEXT: s_getpc_b64 s[4:5] +; GCN-NEXT: s_add_u32 s4, s4, f1@gotpcrel32@lo+4 +; GCN-NEXT: s_addc_u32 s5, s5, f1@gotpcrel32@hi+12 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 +; GCN-NEXT: s_mov_b32 s15, 0 +; GCN-NEXT: s_mov_b64 s[6:7], s[8:9] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] +; GCN-NEXT: s_endpgm +; GCN: .amdhsa_group_segment_fixed_size 8 + call void @f0() + call void @f1() + ret void +} + +define amdgpu_kernel void @k23() { +; OPT-LABEL: @k23() !llvm.amdgcn.lds.kernel.id !1 { +; OPT-NEXT: call void @llvm.donothing() [ "ExplicitUse"([[LLVM_AMDGCN_KERNEL_K23_LDS_T:%.*]] addrspace(3)* @llvm.amdgcn.kernel.k23.lds) ] +; OPT-NEXT: call void @f2() +; OPT-NEXT: call void @f3() +; OPT-NEXT: ret void +; +; GCN-LABEL: k23: +; GCN: ; %bb.0: +; GCN-NEXT: s_mov_b32 s32, 0 +; GCN-NEXT: s_mov_b32 flat_scratch_lo, s7 +; GCN-NEXT: s_add_i32 s6, s6, s9 +; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s6, 8 +; GCN-NEXT: s_add_u32 s0, s0, s9 +; GCN-NEXT: s_addc_u32 s1, s1, 0 +; GCN-NEXT: s_mov_b64 s[8:9], s[4:5] +; GCN-NEXT: s_getpc_b64 s[4:5] +; GCN-NEXT: s_add_u32 s4, s4, f2@gotpcrel32@lo+4 +; GCN-NEXT: s_addc_u32 s5, s5, f2@gotpcrel32@hi+12 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 +; GCN-NEXT: s_mov_b32 s15, 2 +; GCN-NEXT: s_mov_b64 s[6:7], s[8:9] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] +; GCN-NEXT: s_getpc_b64 s[4:5] +; GCN-NEXT: s_add_u32 s4, s4, f3@gotpcrel32@lo+4 +; GCN-NEXT: s_addc_u32 s5, s5, f3@gotpcrel32@hi+12 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 +; GCN-NEXT: s_mov_b32 s15, 2 +; GCN-NEXT: s_mov_b64 s[6:7], s[8:9] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] +; GCN-NEXT: s_endpgm +; GCN: .amdhsa_group_segment_fixed_size 16 + call void @f2() + call void @f3() + ret void +} + +; Access and allocate three variables +define amdgpu_kernel void @k123() { +; OPT-LABEL: @k123() !llvm.amdgcn.lds.kernel.id !2 { +; OPT-NEXT: call void @llvm.donothing() [ "ExplicitUse"([[LLVM_AMDGCN_KERNEL_K123_LDS_T:%.*]] addrspace(3)* @llvm.amdgcn.kernel.k123.lds) ] +; OPT-NEXT: call void @f1() +; OPT-NEXT: [[LD:%.*]] = load i8, i8 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K123_LDS_T]], [[LLVM_AMDGCN_KERNEL_K123_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k123.lds, i32 0, i32 1), align 2, !alias.scope !3, !noalias !6 +; OPT-NEXT: [[MUL:%.*]] = mul i8 [[LD]], 8 +; OPT-NEXT: store i8 [[MUL]], i8 addrspace(3)* getelementptr inbounds ([[LLVM_AMDGCN_KERNEL_K123_LDS_T]], [[LLVM_AMDGCN_KERNEL_K123_LDS_T]] addrspace(3)* @llvm.amdgcn.kernel.k123.lds, i32 0, i32 1), align 2, !alias.scope !3, !noalias !6 +; OPT-NEXT: call void @f2() +; OPT-NEXT: ret void +; +; GCN-LABEL: k123: +; GCN: ; %bb.0: +; GCN-NEXT: s_mov_b32 s32, 0 +; GCN-NEXT: s_mov_b32 flat_scratch_lo, s7 +; GCN-NEXT: s_add_i32 s6, s6, s9 +; GCN-NEXT: s_lshr_b32 flat_scratch_hi, s6, 8 +; GCN-NEXT: s_add_u32 s0, s0, s9 +; GCN-NEXT: s_addc_u32 s1, s1, 0 +; GCN-NEXT: s_mov_b64 s[8:9], s[4:5] +; GCN-NEXT: s_getpc_b64 s[4:5] +; GCN-NEXT: s_add_u32 s4, s4, f1@gotpcrel32@lo+4 +; GCN-NEXT: s_addc_u32 s5, s5, f1@gotpcrel32@hi+12 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 +; GCN-NEXT: s_mov_b32 s15, 1 +; GCN-NEXT: s_mov_b64 s[6:7], s[8:9] +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] +; GCN-NEXT: v_mov_b32_e32 v0, 0 +; GCN-NEXT: s_mov_b32 m0, -1 +; GCN-NEXT: ds_read_u8 v1, v0 offset:2 +; GCN-NEXT: s_getpc_b64 s[4:5] +; GCN-NEXT: s_add_u32 s4, s4, f2@gotpcrel32@lo+4 +; GCN-NEXT: s_addc_u32 s5, s5, f2@gotpcrel32@hi+12 +; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v1 +; GCN-NEXT: ds_write_b8 v0, v1 offset:2 +; GCN-NEXT: s_mov_b32 s15, 1 +; GCN-NEXT: s_mov_b64 s[6:7], s[8:9] +; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] +; GCN-NEXT: s_endpgm +; GCN: .amdhsa_group_segment_fixed_size 16 + call void @f1() + %ld = load i8, i8 addrspace(3)* @v3 + %mul = mul i8 %ld, 8 + store i8 %mul, i8 addrspace(3)* @v3 + call void @f2() + ret void +} + + +; OPT: declare i32 @llvm.amdgcn.lds.kernel.id() + +!0 = !{i32 0} +!1 = !{i32 2} +!2 = !{i32 1} + + +; Table size length number-kernels * number-variables * sizeof(uint16_t) +; GCN: .type llvm.amdgcn.lds.offset.table,@object +; GCN-NEXT: .section .data.rel.ro,#alloc,#write +; GCN-NEXT: .p2align 4, 0x0 +; GCN-NEXT: llvm.amdgcn.lds.offset.table: +; GCN-NEXT: .long 0+4 +; GCN-NEXT: .long 0 +; GCN-NEXT: .zero 4 +; GCN-NEXT: .zero 4 +; GCN-NEXT: .zero 4 +; GCN-NEXT: .long 0 +; GCN-NEXT: .long 0+8 +; GCN-NEXT: .long 0+2 +; GCN-NEXT: .zero 4 +; GCN-NEXT: .zero 4 +; GCN-NEXT: .long 0 +; GCN-NEXT: .long 0+8 +; GCN-NEXT: .size llvm.amdgcn.lds.offset.table, 48 diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds.ll --- a/llvm/test/CodeGen/AMDGPU/lower-module-lds.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds.ll @@ -1,18 +1,20 @@ -; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck %s -; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s +; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s ; Padding to meet alignment, so references to @var1 replaced with gep ptr, 0, 2 ; No i64 as addrspace(3) types with initializers are ignored. Likewise no addrspace(4). ; CHECK: %llvm.amdgcn.module.lds.t = type { float, [4 x i8], i32 } -; Variables removed by pass +; Variable removed by pass ; CHECK-NOT: @var0 -; CHECK-NOT: @var1 @var0 = addrspace(3) global float undef, align 8 @var1 = addrspace(3) global i32 undef, align 8 -@ptr = addrspace(1) global i32 addrspace(3)* @var1, align 4 +; The invalid use by the global is left unchanged +; CHECK: @var1 = addrspace(3) global i32 undef, align 8 +; CHECK: @ptr = addrspace(1) global i32 addrspace(3)* @var1, align 4 +@ptr = addrspace(1) global i32 addrspace(3)* @var1, align 4 ; A variable that is unchanged by pass ; CHECK: @with_init = addrspace(3) global i64 0 diff --git a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll --- a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll +++ b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX9 %s -; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX10 %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX9 %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX10 %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX9 %s +; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,GFX10 %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX9 %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s --amdgpu-lower-module-lds-strategy=module | FileCheck -enable-var-scope -check-prefixes=CHECK,G_GFX10 %s ; Test case looks at the allocated offset of @used_by_both. It's at zero when ; allocated by itself, but at 8 when allocated in combination with the double. @@ -121,41 +121,19 @@ } ; CHECK: ; LDSByteSize: 16 bytes -; Kernel only needs to allocate the i32 it uses, but because that i32 was -; also used by a non-kernel function it was block allocated along with -; the double used by the non-kernel function, this kernel allocates 16 bytes -; and the accesses to the integer are at offset 8 +; Previous lowering was less efficient here than necessary as the i32 used +; by the kernel is also used by an unrelated non-kernel function. Codegen +; is now the same as nocall_ideal. define amdgpu_kernel void @nocall_false_sharing() { -; GFX9-LABEL: nocall_false_sharing: -; GFX9: ; %bb.0: -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: ds_write_b32 v0, v0 offset:8 -; GFX9-NEXT: s_endpgm -; -; GFX10-LABEL: nocall_false_sharing: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_mov_b32_e32 v0, 0 -; GFX10-NEXT: ds_write_b32 v0, v0 offset:8 -; GFX10-NEXT: s_endpgm -; -; G_GFX9-LABEL: nocall_false_sharing: -; G_GFX9: ; %bb.0: -; G_GFX9-NEXT: v_mov_b32_e32 v0, 0 -; G_GFX9-NEXT: v_mov_b32_e32 v1, 8 -; G_GFX9-NEXT: ds_write_b32 v1, v0 -; G_GFX9-NEXT: s_endpgm -; -; G_GFX10-LABEL: nocall_false_sharing: -; G_GFX10: ; %bb.0: -; G_GFX10-NEXT: v_mov_b32_e32 v0, 0 -; G_GFX10-NEXT: v_mov_b32_e32 v1, 8 -; G_GFX10-NEXT: ds_write_b32 v1, v0 -; G_GFX10-NEXT: s_endpgm +; CHECK-LABEL: nocall_false_sharing: +; CHECK: ; %bb.0: +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: ds_write_b32 v0, v0 +; CHECK-NEXT: s_endpgm store i32 0, i32 addrspace(3)* @used_by_both ret void } -; CHECK: ; LDSByteSize: 16 bytes - +; CHECK: ; LDSByteSize: 4 bytes define void @nonkernel() { diff --git a/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll b/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll --- a/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll +++ b/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -march=amdgcn -mcpu=gfx900 -amdgpu-aa -amdgpu-aa-wrapper -amdgpu-annotate-uniform -S < %s | FileCheck %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: opt -march=amdgcn -mcpu=gfx900 -amdgpu-aa -amdgpu-aa-wrapper -amdgpu-annotate-uniform -S --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs --amdgpu-lower-module-lds-strategy=module < %s | FileCheck -check-prefix=GCN %s ; Check that barrier or fence in between of loads is not considered a clobber ; for the purpose of converting vector loads into scalar. diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll --- a/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll +++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mattr=+promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -; RUN: llc -march=amdgcn -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mattr=+promote-alloca,+max-private-element-size-4 -verify-machineinstrs --amdgpu-lower-module-lds-strategy=module < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs --amdgpu-lower-module-lds-strategy=module < %s | FileCheck -check-prefix=GCN %s ; Pointer value is stored in a candidate for LDS usage. diff --git a/llvm/test/CodeGen/AVR/elpm.ll b/llvm/test/CodeGen/AVR/elpm.ll --- a/llvm/test/CodeGen/AVR/elpm.ll +++ b/llvm/test/CodeGen/AVR/elpm.ll @@ -44,8 +44,8 @@ ; CHECK-NEXT: movw r30, r22 ; CHECK-NEXT: ldi r18, 1 ; CHECK-NEXT: out 59, r18 -; CHECK-NEXT: elpm r18, Z+ -; CHECK-NEXT: elpm r19, Z +; CHECK-NEXT: elpm r20, Z+ +; CHECK-NEXT: elpm r21, Z ; CHECK-NEXT: lsl r24 ; CHECK-NEXT: rol r25 ; CHECK-NEXT: subi r24, -lo8(arr0) @@ -53,8 +53,8 @@ ; CHECK-NEXT: movw r30, r24 ; CHECK-NEXT: lpm r24, Z+ ; CHECK-NEXT: lpm r25, Z -; CHECK-NEXT: sub r24, r18 -; CHECK-NEXT: sbc r25, r19 +; CHECK-NEXT: sub r24, r20 +; CHECK-NEXT: sbc r25, r21 ; CHECK-NEXT: ret entry: %arrayidx = getelementptr inbounds [4 x i16], [4 x i16] addrspace(1)* @arr0, i16 0, i16 %a @@ -73,8 +73,8 @@ ; CHECK-NEXT: subi r24, -lo8(arr2) ; CHECK-NEXT: sbci r25, -hi8(arr2) ; CHECK-NEXT: movw r30, r24 -; CHECK-NEXT: ldi r24, 2 -; CHECK-NEXT: out 59, r24 +; CHECK-NEXT: ldi r18, 2 +; CHECK-NEXT: out 59, r18 ; CHECK-NEXT: elpm r24, Z+ ; CHECK-NEXT: elpm r25, Z ; CHECK-NEXT: lsl r22 @@ -106,19 +106,19 @@ ; CHECK-NEXT: movw r30, r22 ; CHECK-NEXT: ldi r18, 1 ; CHECK-NEXT: out 59, r18 -; CHECK-NEXT: elpm r18, Z+ -; CHECK-NEXT: elpm r19, Z +; CHECK-NEXT: elpm r20, Z+ +; CHECK-NEXT: elpm r21, Z ; CHECK-NEXT: lsl r24 ; CHECK-NEXT: rol r25 ; CHECK-NEXT: subi r24, -lo8(arr2) ; CHECK-NEXT: sbci r25, -hi8(arr2) ; CHECK-NEXT: movw r30, r24 -; CHECK-NEXT: ldi r24, 2 -; CHECK-NEXT: out 59, r24 +; CHECK-NEXT: ldi r18, 2 +; CHECK-NEXT: out 59, r18 ; CHECK-NEXT: elpm r24, Z+ ; CHECK-NEXT: elpm r25, Z -; CHECK-NEXT: sub r24, r18 -; CHECK-NEXT: sbc r25, r19 +; CHECK-NEXT: sub r24, r20 +; CHECK-NEXT: sbc r25, r21 ; CHECK-NEXT: ret entry: %arrayidx = getelementptr inbounds [4 x i16], [4 x i16] addrspace(3)* @arr2, i16 0, i16 %a diff --git a/llvm/test/CodeGen/AVR/pseudo/ELPMWRdZ.mir b/llvm/test/CodeGen/AVR/pseudo/ELPMWRdZ.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AVR/pseudo/ELPMWRdZ.mir @@ -0,0 +1,32 @@ +# RUN: llc -mcpu=atmega1284p -start-before=greedy %s -o - | FileCheck %s + +# This test checks the expansion of the 16-bit ELPM pseudo instruction and that +# the register allocator won't use R31R30 as an output register (which would +# lead to undefined behavior). + +--- | + target triple = "avr--" + define void @test_elpmwrdz() { + entry: + ret void + } +... + +--- +name: test_elpmwrdz +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $r31r30 + + ; CHECK-LABEL: test_elpmwrdz + ; CHECK: elpm r24, Z+ + ; CHECK-NEXT: elpm r25, Z + ; CHECK-NEXT: movw r30, r24 + + %1:zreg = COPY killed $r31r30 + %2:ld8 = LDIRdK 1 + %3:dregs = ELPMWRdZ %1, %2, implicit-def dead $r31r30 + $r31r30 = COPY %3 + RET implicit $r31r30 +... diff --git a/llvm/test/CodeGen/BPF/vla.ll b/llvm/test/CodeGen/BPF/vla.ll --- a/llvm/test/CodeGen/BPF/vla.ll +++ b/llvm/test/CodeGen/BPF/vla.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt --bpf-ir-peephole -mtriple=bpf-pc-linux -S %s | FileCheck %s ; Source: ; #define AA 40 @@ -27,13 +28,26 @@ target triple = "bpf" ; Function Attrs: nounwind -define dso_local i32 @test1() #0 { +define dso_local i32 @test1() { +; CHECK-LABEL: @test1( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[A]] to i8* +; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) +; CHECK-NEXT: store i32 8, i32* [[A]], align 4 +; CHECK-NEXT: [[VLA:%.*]] = alloca i8, i64 68, align 1 +; CHECK-NEXT: call void @foo(i8* [[VLA]]) +; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[A]] to i8* +; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP1]]) +; CHECK-NEXT: ret i32 0 +; entry: %a = alloca i32, align 4 %saved_stack = alloca i8*, align 8 %0 = bitcast i32* %a to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #4 - store i32 8, i32* %a, align 4, !tbaa !3 + call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) + store i32 8, i32* %a, align 4 %1 = call i8* @llvm.stacksave() store i8* %1, i8** %saved_stack, align 8 %vla = alloca i8, i64 68, align 1 @@ -41,42 +55,51 @@ %2 = load i8*, i8** %saved_stack, align 8 call void @llvm.stackrestore(i8* %2) %3 = bitcast i32* %a to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %3) #4 + call void @llvm.lifetime.end.p0i8(i64 4, i8* %3) ret i32 0 } -; CHECK: define dso_local i32 @test1 -; CHECK-NOT: %[[#]] = call i8* @llvm.stacksave() -; CHECK-NOT: store i8* %[[#]], i8** %saved_stack, align 8 -; CHECK-NOT: %[[#]] = load i8*, i8** %saved_stack, align 8 -; CHECK-NOT: call void @llvm.stackrestore(i8* %[[#]]) - -; Function Attrs: argmemonly nofree nosync nounwind willreturn -declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1 +declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) -; Function Attrs: nofree nosync nounwind willreturn -declare i8* @llvm.stacksave() #2 +declare i8* @llvm.stacksave() -declare dso_local void @foo(i8*) #3 +declare dso_local void @foo(i8*) -; Function Attrs: nofree nosync nounwind willreturn -declare void @llvm.stackrestore(i8*) #2 +declare void @llvm.stackrestore(i8*) -; Function Attrs: argmemonly nofree nosync nounwind willreturn -declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1 +declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) -; Function Attrs: nounwind -define dso_local i32 @test2(i32 %b) #0 { +define dso_local i32 @test2(i32 %b) { +; CHECK-LABEL: @test2( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 +; CHECK-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 +; CHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 +; CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4 +; CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[A]] to i8* +; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP0]]) +; CHECK-NEXT: store i32 8, i32* [[A]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 8, [[TMP1]] +; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[ADD]] to i64 +; CHECK-NEXT: [[VLA:%.*]] = alloca i8, i64 [[TMP2]], align 1 +; CHECK-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 +; CHECK-NEXT: call void @foo(i8* [[VLA]]) +; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32* [[A]] to i8* +; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP3]]) +; CHECK-NEXT: ret i32 0 +; entry: %b.addr = alloca i32, align 4 %a = alloca i32, align 4 %saved_stack = alloca i8*, align 8 %__vla_expr0 = alloca i64, align 8 - store i32 %b, i32* %b.addr, align 4, !tbaa !3 + store i32 %b, i32* %b.addr, align 4 %0 = bitcast i32* %a to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #4 - store i32 8, i32* %a, align 4, !tbaa !3 - %1 = load i32, i32* %b.addr, align 4, !tbaa !3 + call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) + store i32 8, i32* %a, align 4 + %1 = load i32, i32* %b.addr, align 4 %add = add nsw i32 8, %1 %2 = zext i32 %add to i64 %3 = call i8* @llvm.stacksave() @@ -87,29 +110,6 @@ %4 = load i8*, i8** %saved_stack, align 8 call void @llvm.stackrestore(i8* %4) %5 = bitcast i32* %a to i8* - call void @llvm.lifetime.end.p0i8(i64 4, i8* %5) #4 + call void @llvm.lifetime.end.p0i8(i64 4, i8* %5) ret i32 0 } - -; CHECK: define dso_local i32 @test2 -; CHECK-NOT: %[[#]] = call i8* @llvm.stacksave() -; CHECK-NOT: store i8* %[[#]], i8** %saved_stack, align 8 -; CHECK-NOT: %[[#]] = load i8*, i8** %saved_stack, align 8 -; CHECK-NOT: call void @llvm.stackrestore(i8* %[[#]]) - -attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #1 = { argmemonly nofree nosync nounwind willreturn } -attributes #2 = { nofree nosync nounwind willreturn } -attributes #3 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" } -attributes #4 = { nounwind } - -!llvm.module.flags = !{!0, !1} -!llvm.ident = !{!2} - -!0 = !{i32 1, !"wchar_size", i32 4} -!1 = !{i32 7, !"frame-pointer", i32 2} -!2 = !{!"clang version 14.0.0 (https://github.com/llvm/llvm-project.git 64c5d5c671fb5b5f25c464652a4eec2cf743af0d)"} -!3 = !{!4, !4, i64 0} -!4 = !{!"int", !5, i64 0} -!5 = !{!"omnipotent char", !6, i64 0} -!6 = !{!"Simple C/C++ TBAA"} diff --git a/llvm/test/CodeGen/Generic/MIRDebugify/locations-and-values.mir b/llvm/test/CodeGen/Generic/MIRDebugify/locations-and-values.mir --- a/llvm/test/CodeGen/Generic/MIRDebugify/locations-and-values.mir +++ b/llvm/test/CodeGen/Generic/MIRDebugify/locations-and-values.mir @@ -1,6 +1,8 @@ # RUN: llc -run-pass=mir-debugify -o - %s | FileCheck --check-prefixes=ALL,VALUE %s # RUN: llc -run-pass=mir-debugify -debugify-level=locations -o - %s | FileCheck --check-prefixes=ALL --implicit-check-not=dbg.value %s # RUN: llc -run-pass=mir-debugify,mir-strip-debug,mir-debugify -o - %s | FileCheck --check-prefixes=ALL,VALUE %s +# RUN: llc -run-pass=mir-debugify,mir-strip-debug -o - %s | FileCheck --check-prefix=STRIP %s + --- | ; ModuleID = 'loc-only.ll' source_filename = "loc-only.ll" @@ -24,6 +26,8 @@ ; ALL: ![[VERSION]] = !{i32 2, !"Debug Info Version", i32 3} ; VALUE: [[VAR1:![0-9]+]] = !DILocalVariable(name: "1" ; VALUE: [[VAR2:![0-9]+]] = !DILocalVariable(name: "2" + ; STRIP-NOT: !llvm.debugify + ; STRIP-NOT: !llvm.mir.debugify ... --- diff --git a/llvm/test/CodeGen/Generic/MIRDebugify/multifunction-module.mir b/llvm/test/CodeGen/Generic/MIRDebugify/multifunction-module.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/Generic/MIRDebugify/multifunction-module.mir @@ -0,0 +1,47 @@ +# RUN: llc -run-pass=mir-debugify,mir-check-debugify -o - %s 2>&1 | FileCheck %s + +# CHECK: Machine IR debug info check: PASS +# CHECK-NOT: Assertion `Var <= NumVars && "Unexpected name for DILocalVariable"' + +--- | + define i32 @foo(i32 %a0, i32 %a1, i32 %a2, i32 %a3) { + %t0 = add i32 %a0, %a1 + %t1 = add i32 %t0, %a2 + %t2 = add i32 %t1, %a3 + ret i32 %t2 + } + + define i32 @bar(i32 %a0, i32 %a1, i32 %a2, i32 %a3) { + %t0 = add i32 %a0, %a1 + %t1 = add i32 %a2, %t0 + %t2 = add i32 %t1, %a3 + ret i32 %t2 + } + +... +--- +name: foo +body: | + bb.1 (%ir-block.0): + %0:_(s32) = IMPLICIT_DEF + %1:_(s32) = IMPLICIT_DEF + %2:_(s32) = IMPLICIT_DEF + %3:_(s32) = IMPLICIT_DEF + %4:_(s32) = G_ADD %0, %1 + %5:_(s32) = G_ADD %4, %2 + %6:_(s32) = G_ADD %5, %3 + +... +--- +name: bar +body: | + bb.1 (%ir-block.0): + %0:_(s32) = IMPLICIT_DEF + %1:_(s32) = IMPLICIT_DEF + %2:_(s32) = IMPLICIT_DEF + %3:_(s32) = IMPLICIT_DEF + %4:_(s32) = G_ADD %0, %1 + %5:_(s32) = G_ADD %2, %4 + %6:_(s32) = G_ADD %5, %3 + +... diff --git a/llvm/test/CodeGen/Hexagon/autohvx/fp-to-int.ll b/llvm/test/CodeGen/Hexagon/autohvx/fp-to-int.ll --- a/llvm/test/CodeGen/Hexagon/autohvx/fp-to-int.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/fp-to-int.ll @@ -13,13 +13,13 @@ ; CHECK-NEXT: { ; CHECK-NEXT: r3:2 = combine(##32768,#1) ; CHECK-NEXT: r4 = #14 -; CHECK-NEXT: v0 = vmem(r0+#0) +; CHECK-NEXT: v1 = vmem(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v2.h = vsplat(r3) ; CHECK-NEXT: r6 = #5 ; CHECK-NEXT: v3.h = vasl(v0.h,r2) -; CHECK-NEXT: v1 = vmem(r0+#1) +; CHECK-NEXT: v0.cur = vmem(r0+#1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v4.h = vsplat(r4) @@ -33,55 +33,55 @@ ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r3 = #16 -; CHECK-NEXT: v5.h = vasl(v0.h,r6) -; CHECK-NEXT: q1 = vcmp.gt(v7.h,v1.h) +; CHECK-NEXT: v5.h = vasl(v1.h,r6) +; CHECK-NEXT: q1 = vcmp.gt(v7.h,v0.h) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v6.h = vsplat(r3) -; CHECK-NEXT: v28.h = vasr(v3.h,r5) +; CHECK-NEXT: v27.h = vasr(v3.h,r5) ; CHECK-NEXT: v5 = vor(v5,v2) -; CHECK-NEXT: q0 = vcmp.gt(v7.h,v0.h) +; CHECK-NEXT: q0 = vcmp.gt(v7.h,v1.h) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v9.h = vsplat(r4) ; CHECK-NEXT: v8.h = vasr(v8.h,r5) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v27.h = vasl(v1.h,r6) -; CHECK-NEXT: v1.h = vsub(v4.h,v28.h) +; CHECK-NEXT: v26.h = vasl(v0.h,r6) +; CHECK-NEXT: v0.h = vsub(v4.h,v27.h) ; CHECK-NEXT: v4.h = vsub(v4.h,v8.h) -; CHECK-NEXT: v29 = vmux(q0,v2,v9) +; CHECK-NEXT: v28 = vmux(q0,v2,v9) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v1.h = vmin(v1.h,v6.h) -; CHECK-NEXT: v0 = vor(v27,v2) ; CHECK-NEXT: v4.h = vmin(v4.h,v6.h) +; CHECK-NEXT: v1 = vor(v26,v2) +; CHECK-NEXT: v0.h = vmin(v0.h,v6.h) ; CHECK-NEXT: v2 = vmux(q1,v2,v9) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: q2 = vcmp.gt(v1.h,v7.h) -; CHECK-NEXT: q3 = vcmp.gt(v4.h,v7.h) +; CHECK-NEXT: q2 = vcmp.gt(v4.h,v7.h) +; CHECK-NEXT: q3 = vcmp.gt(v0.h,v7.h) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v5.h = vlsr(v5.h,v1.h) +; CHECK-NEXT: v5.h = vlsr(v5.h,v4.h) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0.h = vlsr(v0.h,v4.h) -; CHECK-NEXT: v30.h = vsub(v7.h,v5.h) +; CHECK-NEXT: v1.h = vlsr(v1.h,v0.h) +; CHECK-NEXT: v29.h = vsub(v7.h,v5.h) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v31.h = vsub(v7.h,v0.h) -; CHECK-NEXT: v5 = vmux(q0,v30,v5) +; CHECK-NEXT: v30.h = vsub(v7.h,v1.h) +; CHECK-NEXT: v5 = vmux(q0,v29,v5) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0 = vmux(q1,v31,v0) -; CHECK-NEXT: v1 = vmux(q2,v5,v29) +; CHECK-NEXT: v1 = vmux(q1,v30,v1) +; CHECK-NEXT: v31 = vmux(q2,v5,v28) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0 = vmux(q3,v0,v2) +; CHECK-NEXT: v1 = vmux(q3,v1,v2) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0.b = vpack(v0.h,v1.h):sat +; CHECK-NEXT: v0.b = vpack(v1.h,v31.h):sat ; CHECK-NEXT: jumpr r31 ; CHECK-NEXT: vmem(r1+#0) = v0.new ; CHECK-NEXT: } @@ -491,127 +491,127 @@ ; CHECK: .cfi_startproc ; CHECK-NEXT: // %bb.0: ; CHECK-NEXT: { -; CHECK-NEXT: r3:2 = combine(#1,#8) ; CHECK-NEXT: r4 = ##-2147483648 -; CHECK-NEXT: v6 = vmem(r0+#1) +; CHECK-NEXT: r3:2 = combine(#1,#8) +; CHECK-NEXT: v4 = vmem(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0 = vsplat(r4) +; CHECK-NEXT: v1 = vsplat(r4) ; CHECK-NEXT: r7 = #30 ; CHECK-NEXT: r6 = #24 -; CHECK-NEXT: v4 = vmem(r0+#0) +; CHECK-NEXT: v2 = vmem(r0+#2) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v10 = vsplat(r7) ; CHECK-NEXT: r5 = #32 -; CHECK-NEXT: v9.w = vasl(v6.w,r3) -; CHECK-NEXT: v1 = vmem(r0+#3) +; CHECK-NEXT: v8.w = vasl(v6.w,r3) +; CHECK-NEXT: v6.cur = vmem(r0+#1) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v8.w = vasl(v4.w,r3) -; CHECK-NEXT: v14 = vxor(v14,v14) -; CHECK-NEXT: v9.w = vsub(v9.w,v0.w) -; CHECK-NEXT: v2 = vmem(r0+#2) +; CHECK-NEXT: v7.w = vasl(v4.w,r3) +; CHECK-NEXT: v12 = vxor(v12,v12) +; CHECK-NEXT: v8.w = vsub(v8.w,v1.w) +; CHECK-NEXT: v0 = vmem(r0+#3) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v13 = vsplat(r5) -; CHECK-NEXT: v11.w = vasl(v2.w,r3) -; CHECK-NEXT: v8.w = vsub(v8.w,v0.w) -; CHECK-NEXT: q1 = vcmp.gt(v14.w,v6.w) +; CHECK-NEXT: v11.w = vasl(v0.w,r3) +; CHECK-NEXT: v7.w = vsub(v7.w,v1.w) +; CHECK-NEXT: q0 = vcmp.gt(v12.w,v4.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v12.w = vasl(v1.w,r3) -; CHECK-NEXT: q0 = vcmp.gt(v14.w,v4.w) -; CHECK-NEXT: v11.w = vsub(v11.w,v0.w) +; CHECK-NEXT: v9.w = vasl(v2.w,r3) +; CHECK-NEXT: q1 = vcmp.gt(v12.w,v6.w) +; CHECK-NEXT: v11.w = vsub(v11.w,v1.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r3 = ##2147483647 ; CHECK-NEXT: r7 = #64 -; CHECK-NEXT: v9.w = vasr(v9.w,r6) +; CHECK-NEXT: v8.w = vasr(v8.w,r6) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v20 = vsplat(r3) -; CHECK-NEXT: v7.w = vasl(v6.w,r2) -; CHECK-NEXT: v21.w = vsub(v12.w,v0.w) -; CHECK-NEXT: v9.w = vsub(v10.w,v9.w) +; CHECK-NEXT: v23 = vsplat(r3) +; CHECK-NEXT: v7.w = vasr(v7.w,r6) +; CHECK-NEXT: v20.w = vsub(v9.w,v1.w) +; CHECK-NEXT: v8.w = vsub(v10.w,v8.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v8.w = vasr(v8.w,r6) -; CHECK-NEXT: v27 = vmux(q1,v0,v20) -; CHECK-NEXT: v25 = vmux(q0,v0,v20) -; CHECK-NEXT: v9.w = vmin(v9.w,v13.w) +; CHECK-NEXT: v21.w = vasl(v6.w,r2) +; CHECK-NEXT: v28 = vmux(q1,v1,v23) +; CHECK-NEXT: v26 = vmux(q0,v1,v23) +; CHECK-NEXT: v7.w = vsub(v10.w,v7.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v5.w = vasl(v4.w,r2) -; CHECK-NEXT: v7 = vor(v7,v0) -; CHECK-NEXT: v8.w = vsub(v10.w,v8.w) -; CHECK-NEXT: q3 = vcmp.gt(v9.w,v14.w) +; CHECK-NEXT: v8.w = vmin(v8.w,v13.w) +; CHECK-NEXT: v9 = vor(v21,v1) +; CHECK-NEXT: v22.w = vmin(v7.w,v13.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v11.w = vasr(v11.w,r6) -; CHECK-NEXT: v8.w = vmin(v8.w,v13.w) -; CHECK-NEXT: v5 = vor(v5,v0) +; CHECK-NEXT: v4.w = vasr(v20.w,r6) +; CHECK-NEXT: q3 = vcmp.gt(v8.w,v12.w) +; CHECK-NEXT: v5 = vor(v5,v1) +; CHECK-NEXT: q2 = vcmp.gt(v22.w,v12.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v6.w = vasr(v21.w,r6) -; CHECK-NEXT: v11.w = vsub(v10.w,v11.w) -; CHECK-NEXT: q2 = vcmp.gt(v8.w,v14.w) +; CHECK-NEXT: v11.w = vasr(v11.w,r6) +; CHECK-NEXT: v4.w = vsub(v10.w,v4.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v3.w = vasl(v1.w,r2) -; CHECK-NEXT: v6.w = vsub(v10.w,v6.w) -; CHECK-NEXT: v23.w = vmin(v11.w,v13.w) +; CHECK-NEXT: v3.w = vasl(v2.w,r2) +; CHECK-NEXT: v10.w = vsub(v10.w,v11.w) +; CHECK-NEXT: v4.w = vmin(v4.w,v13.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v22.w = vasl(v2.w,r2) -; CHECK-NEXT: v3 = vor(v3,v0) -; CHECK-NEXT: v6.w = vmin(v6.w,v13.w) +; CHECK-NEXT: v24.w = vasl(v0.w,r2) +; CHECK-NEXT: v3 = vor(v3,v1) +; CHECK-NEXT: v10.w = vmin(v10.w,v13.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v7.w = vlsr(v7.w,v9.w) -; CHECK-NEXT: v12 = vor(v22,v0) +; CHECK-NEXT: v8.w = vlsr(v9.w,v8.w) +; CHECK-NEXT: v6 = vor(v24,v1) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v5.w = vlsr(v5.w,v8.w) -; CHECK-NEXT: v26.w = vsub(v14.w,v7.w) +; CHECK-NEXT: v5.w = vlsr(v5.w,v22.w) +; CHECK-NEXT: v27.w = vsub(v12.w,v8.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v28.w = vlsr(v12.w,v23.w) -; CHECK-NEXT: v24.w = vsub(v14.w,v5.w) -; CHECK-NEXT: v7 = vmux(q1,v26,v7) +; CHECK-NEXT: v3.w = vlsr(v3.w,v4.w) +; CHECK-NEXT: v25.w = vsub(v12.w,v5.w) +; CHECK-NEXT: v8 = vmux(q1,v27,v8) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v3.w = vlsr(v3.w,v6.w) -; CHECK-NEXT: v5 = vmux(q0,v24,v5) -; CHECK-NEXT: q0 = vcmp.gt(v14.w,v2.w) -; CHECK-NEXT: v29.w = vsub(v14.w,v28.w) +; CHECK-NEXT: v6.w = vlsr(v6.w,v10.w) +; CHECK-NEXT: v5 = vmux(q0,v25,v5) +; CHECK-NEXT: q0 = vcmp.gt(v12.w,v2.w) +; CHECK-NEXT: v29.w = vsub(v12.w,v3.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v2 = vmux(q3,v7,v27) -; CHECK-NEXT: q3 = vcmp.gt(v14.w,v1.w) -; CHECK-NEXT: v31.w = vsub(v14.w,v3.w) -; CHECK-NEXT: v5 = vmux(q2,v5,v25) +; CHECK-NEXT: v2 = vmux(q3,v8,v28) +; CHECK-NEXT: q3 = vcmp.gt(v12.w,v0.w) +; CHECK-NEXT: v30.w = vsub(v12.w,v6.w) +; CHECK-NEXT: v5 = vmux(q2,v5,v26) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v1 = vmux(q0,v0,v20) -; CHECK-NEXT: v30 = vmux(q0,v29,v28) -; CHECK-NEXT: q2 = vcmp.gt(v23.w,v14.w) -; CHECK-NEXT: v3 = vmux(q3,v31,v3) +; CHECK-NEXT: v0 = vmux(q0,v1,v23) +; CHECK-NEXT: v3 = vmux(q0,v29,v3) +; CHECK-NEXT: q2 = vcmp.gt(v4.w,v12.w) +; CHECK-NEXT: v31 = vmux(q3,v30,v6) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v2.h = vpack(v2.w,v5.w):sat -; CHECK-NEXT: v0 = vmux(q3,v0,v20) -; CHECK-NEXT: q3 = vcmp.gt(v6.w,v14.w) -; CHECK-NEXT: v1 = vmux(q2,v30,v1) +; CHECK-NEXT: v1 = vmux(q3,v1,v23) +; CHECK-NEXT: q3 = vcmp.gt(v10.w,v12.w) +; CHECK-NEXT: v0 = vmux(q2,v3,v0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0 = vmux(q3,v3,v0) +; CHECK-NEXT: v1 = vmux(q3,v31,v1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v3.h = vpack(v1.w,v0.w):sat ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0.h = vpack(v0.w,v1.w):sat +; CHECK-NEXT: v0.h = vpack(v1.w,v0.w):sat ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v1.b = vpack(v3.h,v2.h):sat @@ -638,13 +638,13 @@ ; CHECK-NEXT: { ; CHECK-NEXT: r3:2 = combine(##-2147483648,#8) ; CHECK-NEXT: r4 = #1 -; CHECK-NEXT: v1 = vmem(r0+#1) +; CHECK-NEXT: v1 = vmem(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v3 = vsplat(r3) ; CHECK-NEXT: r5 = #30 ; CHECK-NEXT: v4.w = vasl(v0.w,r4) -; CHECK-NEXT: v0.cur = vmem(r0+#0) +; CHECK-NEXT: v0.cur = vmem(r0+#1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v5.w = vasl(v1.w,r4) @@ -653,64 +653,64 @@ ; CHECK-NEXT: r4 = #32 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v7 = vsplat(r5) -; CHECK-NEXT: v8 = vsplat(r4) +; CHECK-NEXT: v6 = vsplat(r5) +; CHECK-NEXT: v7 = vsplat(r4) ; CHECK-NEXT: v2.w = vasl(v1.w,r2) ; CHECK-NEXT: v5.w = vsub(v5.w,v3.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v4.w = vasr(v4.w,r6) -; CHECK-NEXT: v27 = vxor(v27,v27) +; CHECK-NEXT: v26 = vxor(v26,v26) ; CHECK-NEXT: v2 = vor(v2,v3) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r3 = ##2147483647 ; CHECK-NEXT: v5.w = vasr(v5.w,r6) -; CHECK-NEXT: q0 = vcmp.gt(v27.w,v0.w) +; CHECK-NEXT: q0 = vcmp.gt(v26.w,v1.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v28 = vsplat(r3) -; CHECK-NEXT: v6.w = vasl(v0.w,r2) -; CHECK-NEXT: v4.w = vsub(v7.w,v4.w) -; CHECK-NEXT: q2 = vcmp.gt(v27.w,v1.w) +; CHECK-NEXT: v27 = vsplat(r3) +; CHECK-NEXT: v4.w = vsub(v6.w,v4.w) +; CHECK-NEXT: q2 = vcmp.gt(v26.w,v0.w) +; CHECK-NEXT: v5.w = vsub(v6.w,v5.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v5.w = vsub(v7.w,v5.w) -; CHECK-NEXT: v4.w = vmin(v4.w,v8.w) -; CHECK-NEXT: v31 = vmux(q0,v3,v28) -; CHECK-NEXT: v6 = vor(v6,v3) +; CHECK-NEXT: v8.w = vasl(v0.w,r2) +; CHECK-NEXT: v4.w = vmin(v4.w,v7.w) +; CHECK-NEXT: v30 = vmux(q0,v3,v27) +; CHECK-NEXT: v5.w = vmin(v5.w,v7.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v5.w = vmin(v5.w,v8.w) -; CHECK-NEXT: q1 = vcmp.gt(v4.w,v27.w) -; CHECK-NEXT: v0 = vmux(q2,v3,v28) +; CHECK-NEXT: v25 = vor(v8,v3) +; CHECK-NEXT: v1 = vmux(q2,v3,v27) +; CHECK-NEXT: q3 = vcmp.gt(v4.w,v26.w) +; CHECK-NEXT: q1 = vcmp.gt(v5.w,v26.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r2 = #64 -; CHECK-NEXT: v6.w = vlsr(v6.w,v4.w) -; CHECK-NEXT: q3 = vcmp.gt(v5.w,v27.w) +; CHECK-NEXT: v2.w = vlsr(v2.w,v5.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v2.w = vlsr(v2.w,v5.w) -; CHECK-NEXT: v29.w = vsub(v27.w,v6.w) +; CHECK-NEXT: v28.w = vlsr(v25.w,v4.w) +; CHECK-NEXT: v29.w = vsub(v26.w,v2.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v30.w = vsub(v27.w,v2.w) -; CHECK-NEXT: v1 = vmux(q0,v29,v6) +; CHECK-NEXT: v6.w = vsub(v26.w,v28.w) +; CHECK-NEXT: v0 = vmux(q0,v29,v2) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v2 = vmux(q2,v30,v2) -; CHECK-NEXT: v1 = vmux(q1,v1,v31) +; CHECK-NEXT: v31 = vmux(q2,v6,v28) +; CHECK-NEXT: v0 = vmux(q1,v0,v30) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: q3 = vsetq(r2) -; CHECK-NEXT: v0 = vmux(q3,v2,v0) +; CHECK-NEXT: v1 = vmux(q3,v31,v1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v2.h = vpack(v1.w,v0.w):sat ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0.h = vpack(v0.w,v1.w):sat +; CHECK-NEXT: v0.h = vpack(v1.w,v0.w):sat ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v0.b = vpack(v2.h,v0.h):sat @@ -808,13 +808,13 @@ ; CHECK-NEXT: { ; CHECK-NEXT: r3:2 = combine(##-2147483648,#1) ; CHECK-NEXT: r4 = #30 -; CHECK-NEXT: v0 = vmem(r0+#0) +; CHECK-NEXT: v1 = vmem(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v2 = vsplat(r3) ; CHECK-NEXT: r6 = #8 ; CHECK-NEXT: v3.w = vasl(v0.w,r2) -; CHECK-NEXT: v1 = vmem(r0+#1) +; CHECK-NEXT: v0.cur = vmem(r0+#1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v4 = vsplat(r4) @@ -828,55 +828,55 @@ ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r3 = #32 -; CHECK-NEXT: v5.w = vasl(v0.w,r6) -; CHECK-NEXT: q1 = vcmp.gt(v7.w,v1.w) +; CHECK-NEXT: v5.w = vasl(v1.w,r6) +; CHECK-NEXT: q1 = vcmp.gt(v7.w,v0.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v6 = vsplat(r3) -; CHECK-NEXT: v28.w = vasr(v3.w,r5) +; CHECK-NEXT: v27.w = vasr(v3.w,r5) ; CHECK-NEXT: v5 = vor(v5,v2) -; CHECK-NEXT: q0 = vcmp.gt(v7.w,v0.w) +; CHECK-NEXT: q0 = vcmp.gt(v7.w,v1.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v9 = vsplat(r4) ; CHECK-NEXT: v8.w = vasr(v8.w,r5) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v27.w = vasl(v1.w,r6) -; CHECK-NEXT: v1.w = vsub(v4.w,v28.w) +; CHECK-NEXT: v26.w = vasl(v0.w,r6) +; CHECK-NEXT: v0.w = vsub(v4.w,v27.w) ; CHECK-NEXT: v4.w = vsub(v4.w,v8.w) -; CHECK-NEXT: v29 = vmux(q0,v2,v9) +; CHECK-NEXT: v28 = vmux(q0,v2,v9) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v1.w = vmin(v1.w,v6.w) -; CHECK-NEXT: v0 = vor(v27,v2) ; CHECK-NEXT: v4.w = vmin(v4.w,v6.w) +; CHECK-NEXT: v1 = vor(v26,v2) +; CHECK-NEXT: v0.w = vmin(v0.w,v6.w) ; CHECK-NEXT: v2 = vmux(q1,v2,v9) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: q2 = vcmp.gt(v1.w,v7.w) -; CHECK-NEXT: q3 = vcmp.gt(v4.w,v7.w) +; CHECK-NEXT: q2 = vcmp.gt(v4.w,v7.w) +; CHECK-NEXT: q3 = vcmp.gt(v0.w,v7.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v5.w = vlsr(v5.w,v1.w) +; CHECK-NEXT: v5.w = vlsr(v5.w,v4.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0.w = vlsr(v0.w,v4.w) -; CHECK-NEXT: v30.w = vsub(v7.w,v5.w) +; CHECK-NEXT: v1.w = vlsr(v1.w,v0.w) +; CHECK-NEXT: v29.w = vsub(v7.w,v5.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v31.w = vsub(v7.w,v0.w) -; CHECK-NEXT: v5 = vmux(q0,v30,v5) +; CHECK-NEXT: v30.w = vsub(v7.w,v1.w) +; CHECK-NEXT: v5 = vmux(q0,v29,v5) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0 = vmux(q1,v31,v0) -; CHECK-NEXT: v1 = vmux(q2,v5,v29) +; CHECK-NEXT: v1 = vmux(q1,v30,v1) +; CHECK-NEXT: v31 = vmux(q2,v5,v28) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0 = vmux(q3,v0,v2) +; CHECK-NEXT: v1 = vmux(q3,v1,v2) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0.h = vpack(v0.w,v1.w):sat +; CHECK-NEXT: v0.h = vpack(v1.w,v31.w):sat ; CHECK-NEXT: jumpr r31 ; CHECK-NEXT: vmem(r1+#0) = v0.new ; CHECK-NEXT: } @@ -1097,13 +1097,13 @@ ; CHECK-NEXT: { ; CHECK-NEXT: r3:2 = combine(##32768,#1) ; CHECK-NEXT: r4 = #14 -; CHECK-NEXT: v0 = vmem(r0+#0) +; CHECK-NEXT: v0 = vmem(r0+#1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v2.h = vsplat(r3) ; CHECK-NEXT: r7:6 = combine(#11,#16) ; CHECK-NEXT: v3.h = vasl(v0.h,r2) -; CHECK-NEXT: v1 = vmem(r0+#1) +; CHECK-NEXT: v1 = vmem(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v6.h = vsplat(r4) @@ -1113,7 +1113,7 @@ ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v7.h = vsplat(r6) -; CHECK-NEXT: v5.h = vasl(v0.h,r5) +; CHECK-NEXT: v5.h = vasl(v1.h,r5) ; CHECK-NEXT: v4.h = vsub(v4.h,v2.h) ; CHECK-NEXT: v28 = vxor(v28,v28) ; CHECK-NEXT: } @@ -1125,26 +1125,28 @@ ; CHECK-NEXT: { ; CHECK-NEXT: v29.h = vsplat(r2) ; CHECK-NEXT: v4.h = vasr(v4.h,r7) -; CHECK-NEXT: q2 = vcmp.gt(v28.h,v0.h) +; CHECK-NEXT: q2 = vcmp.gt(v28.h,v1.h) ; CHECK-NEXT: v3.h = vsub(v6.h,v3.h) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v8.h = vasl(v1.h,r5) -; CHECK-NEXT: q3 = vcmp.gt(v28.h,v1.h) +; CHECK-NEXT: v8.h = vasl(v0.h,r5) +; CHECK-NEXT: q3 = vcmp.gt(v28.h,v0.h) ; CHECK-NEXT: v4.h = vsub(v6.h,v4.h) ; CHECK-NEXT: v3.h = vmin(v3.h,v7.h) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v4.h = vmin(v4.h,v7.h) ; CHECK-NEXT: v2 = vor(v8,v2) -; CHECK-NEXT: q0 = vcmp.gt(v28.h,v3.h) +; CHECK-NEXT: q1 = vcmp.gt(v28.h,v3.h) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: q0 = vcmp.gt(v28.h,v4.h) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v5.h = vlsr(v5.h,v3.h) -; CHECK-NEXT: q1 = vcmp.gt(v28.h,v4.h) +; CHECK-NEXT: v5.h = vlsr(v5.h,v4.h) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v2.h = vlsr(v2.h,v4.h) +; CHECK-NEXT: v2.h = vlsr(v2.h,v3.h) ; CHECK-NEXT: v30 = vmux(q0,v29,v5) ; CHECK-NEXT: } ; CHECK-NEXT: { @@ -1550,7 +1552,7 @@ ; CHECK-NEXT: v5 = vmem(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v4 = vsplat(r3) +; CHECK-NEXT: v3 = vsplat(r3) ; CHECK-NEXT: r5 = #30 ; CHECK-NEXT: r6 = #24 ; CHECK-NEXT: v2 = vmem(r0+#1) @@ -1559,29 +1561,29 @@ ; CHECK-NEXT: v14 = vsplat(r5) ; CHECK-NEXT: v8.w = vasl(v5.w,r4) ; CHECK-NEXT: v13 = vxor(v13,v13) -; CHECK-NEXT: v0 = vmem(r0+#2) +; CHECK-NEXT: v0 = vmem(r0+#3) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r7 = #64 ; CHECK-NEXT: v9.w = vasl(v2.w,r4) -; CHECK-NEXT: v8.w = vsub(v8.w,v4.w) -; CHECK-NEXT: v1 = vmem(r0+#3) +; CHECK-NEXT: v8.w = vsub(v8.w,v3.w) +; CHECK-NEXT: v1 = vmem(r0+#2) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v11.w = vasl(v0.w,r4) +; CHECK-NEXT: v12.w = vasl(v0.w,r4) ; CHECK-NEXT: q0 = vcmp.gt(v13.w,v5.w) -; CHECK-NEXT: v9.w = vsub(v9.w,v4.w) +; CHECK-NEXT: v9.w = vsub(v9.w,v3.w) ; CHECK-NEXT: q3 = vcmp.gt(v13.w,v2.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r4 = #32 -; CHECK-NEXT: v12.w = vasl(v1.w,r4) -; CHECK-NEXT: v11.w = vsub(v11.w,v4.w) +; CHECK-NEXT: v11.w = vasl(v1.w,r4) +; CHECK-NEXT: v12.w = vsub(v12.w,v3.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v24 = vsplat(r4) +; CHECK-NEXT: v23 = vsplat(r4) ; CHECK-NEXT: v8.w = vasr(v8.w,r6) -; CHECK-NEXT: v12.w = vsub(v12.w,v4.w) +; CHECK-NEXT: v11.w = vsub(v11.w,v3.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v9.w = vasr(v9.w,r6) @@ -1590,70 +1592,70 @@ ; CHECK-NEXT: { ; CHECK-NEXT: v6.w = vasl(v5.w,r2) ; CHECK-NEXT: v9.w = vsub(v14.w,v9.w) -; CHECK-NEXT: v8.w = vmin(v8.w,v24.w) +; CHECK-NEXT: v8.w = vmin(v8.w,v23.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v7.w = vasl(v2.w,r2) -; CHECK-NEXT: v6 = vor(v6,v4) -; CHECK-NEXT: v9.w = vmin(v9.w,v24.w) +; CHECK-NEXT: v6 = vor(v6,v3) +; CHECK-NEXT: v9.w = vmin(v9.w,v23.w) ; CHECK-NEXT: q1 = vcmp.gt(v13.w,v8.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v23.w = vasr(v11.w,r6) -; CHECK-NEXT: v7 = vor(v7,v4) +; CHECK-NEXT: v22.w = vasr(v11.w,r6) +; CHECK-NEXT: v7 = vor(v7,v3) ; CHECK-NEXT: q2 = vcmp.gt(v13.w,v9.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v12.w = vasr(v12.w,r6) -; CHECK-NEXT: v5.w = vsub(v14.w,v23.w) +; CHECK-NEXT: v5.w = vsub(v14.w,v22.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v3.w = vasl(v1.w,r2) -; CHECK-NEXT: v25.w = vsub(v14.w,v12.w) -; CHECK-NEXT: v5.w = vmin(v5.w,v24.w) +; CHECK-NEXT: v4.w = vasl(v1.w,r2) +; CHECK-NEXT: v24.w = vsub(v14.w,v12.w) +; CHECK-NEXT: v5.w = vmin(v5.w,v23.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r2 = ##2147483647 ; CHECK-NEXT: v10.w = vasl(v0.w,r2) -; CHECK-NEXT: v3 = vor(v3,v4) +; CHECK-NEXT: v4 = vor(v4,v3) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v26 = vsplat(r2) +; CHECK-NEXT: v25 = vsplat(r2) ; CHECK-NEXT: v6.w = vlsr(v6.w,v8.w) -; CHECK-NEXT: v10 = vor(v10,v4) -; CHECK-NEXT: v4.w = vmin(v25.w,v24.w) +; CHECK-NEXT: v3 = vor(v10,v3) +; CHECK-NEXT: v10.w = vmin(v24.w,v23.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v7.w = vlsr(v7.w,v9.w) -; CHECK-NEXT: v6 = vmux(q1,v26,v6) +; CHECK-NEXT: v27 = vmux(q1,v25,v6) ; CHECK-NEXT: q1 = vcmp.gt(v13.w,v5.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v27.w = vlsr(v10.w,v5.w) -; CHECK-NEXT: v7 = vmux(q2,v26,v7) -; CHECK-NEXT: q2 = vcmp.gt(v13.w,v4.w) -; CHECK-NEXT: v28 = vmux(q0,v13,v6) +; CHECK-NEXT: v26.w = vlsr(v4.w,v5.w) +; CHECK-NEXT: v28 = vmux(q2,v25,v7) +; CHECK-NEXT: q2 = vcmp.gt(v13.w,v10.w) +; CHECK-NEXT: v4 = vmux(q0,v13,v27) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v3.w = vlsr(v3.w,v4.w) -; CHECK-NEXT: v29 = vmux(q3,v13,v7) -; CHECK-NEXT: v2 = vmux(q1,v26,v27) -; CHECK-NEXT: q1 = vcmp.gt(v13.w,v0.w) +; CHECK-NEXT: v3.w = vlsr(v3.w,v10.w) +; CHECK-NEXT: v29 = vmux(q3,v13,v28) +; CHECK-NEXT: v2 = vmux(q1,v25,v26) +; CHECK-NEXT: q1 = vcmp.gt(v13.w,v1.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: q3 = vcmp.gt(v13.w,v1.w) -; CHECK-NEXT: v0 = vmux(q2,v26,v3) -; CHECK-NEXT: v1 = vmux(q1,v13,v2) +; CHECK-NEXT: q3 = vcmp.gt(v13.w,v0.w) +; CHECK-NEXT: v1 = vmux(q2,v25,v3) +; CHECK-NEXT: v0 = vmux(q1,v13,v2) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v30.uh = vpack(v29.w,v28.w):sat -; CHECK-NEXT: v0 = vmux(q3,v13,v0) +; CHECK-NEXT: v30.uh = vpack(v29.w,v4.w):sat +; CHECK-NEXT: v1 = vmux(q3,v13,v1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v31.uh = vpack(v1.w,v0.w):sat ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0.uh = vpack(v0.w,v1.w):sat +; CHECK-NEXT: v0.uh = vpack(v1.w,v0.w):sat ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v1.ub = vpack(v31.h,v30.h):sat @@ -1680,13 +1682,13 @@ ; CHECK-NEXT: { ; CHECK-NEXT: r3:2 = combine(##-2147483648,#1) ; CHECK-NEXT: r4 = #30 -; CHECK-NEXT: v0 = vmem(r0+#0) +; CHECK-NEXT: v0 = vmem(r0+#1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v2 = vsplat(r3) ; CHECK-NEXT: r7:6 = combine(#24,#32) ; CHECK-NEXT: v3.w = vasl(v0.w,r2) -; CHECK-NEXT: v1 = vmem(r0+#1) +; CHECK-NEXT: v1 = vmem(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v6 = vsplat(r4) @@ -1696,7 +1698,7 @@ ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v7 = vsplat(r6) -; CHECK-NEXT: v5.w = vasl(v0.w,r5) +; CHECK-NEXT: v5.w = vasl(v1.w,r5) ; CHECK-NEXT: v4.w = vsub(v4.w,v2.w) ; CHECK-NEXT: v27 = vxor(v27,v27) ; CHECK-NEXT: } @@ -1708,13 +1710,13 @@ ; CHECK-NEXT: { ; CHECK-NEXT: v28 = vsplat(r3) ; CHECK-NEXT: v4.w = vasr(v4.w,r7) -; CHECK-NEXT: q2 = vcmp.gt(v27.w,v0.w) +; CHECK-NEXT: q2 = vcmp.gt(v27.w,v1.w) ; CHECK-NEXT: v3.w = vsub(v6.w,v3.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r2 = #64 -; CHECK-NEXT: v8.w = vasl(v1.w,r5) -; CHECK-NEXT: q3 = vcmp.gt(v27.w,v1.w) +; CHECK-NEXT: v8.w = vasl(v0.w,r5) +; CHECK-NEXT: q3 = vcmp.gt(v27.w,v0.w) ; CHECK-NEXT: v4.w = vsub(v6.w,v4.w) ; CHECK-NEXT: } ; CHECK-NEXT: { @@ -1723,14 +1725,14 @@ ; CHECK-NEXT: v2 = vor(v8,v2) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: q0 = vcmp.gt(v27.w,v3.w) +; CHECK-NEXT: q1 = vcmp.gt(v27.w,v3.w) +; CHECK-NEXT: q0 = vcmp.gt(v27.w,v4.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v5.w = vlsr(v5.w,v3.w) -; CHECK-NEXT: q1 = vcmp.gt(v27.w,v4.w) +; CHECK-NEXT: v5.w = vlsr(v5.w,v4.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v2.w = vlsr(v2.w,v4.w) +; CHECK-NEXT: v2.w = vlsr(v2.w,v3.w) ; CHECK-NEXT: v29 = vmux(q0,v28,v5) ; CHECK-NEXT: } ; CHECK-NEXT: { @@ -1839,13 +1841,13 @@ ; CHECK-NEXT: { ; CHECK-NEXT: r3:2 = combine(##-2147483648,#1) ; CHECK-NEXT: r4 = #30 -; CHECK-NEXT: v0 = vmem(r0+#0) +; CHECK-NEXT: v0 = vmem(r0+#1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v2 = vsplat(r3) ; CHECK-NEXT: r7:6 = combine(#24,#32) ; CHECK-NEXT: v3.w = vasl(v0.w,r2) -; CHECK-NEXT: v1 = vmem(r0+#1) +; CHECK-NEXT: v1 = vmem(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v6 = vsplat(r4) @@ -1855,7 +1857,7 @@ ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v7 = vsplat(r6) -; CHECK-NEXT: v5.w = vasl(v0.w,r5) +; CHECK-NEXT: v5.w = vasl(v1.w,r5) ; CHECK-NEXT: v4.w = vsub(v4.w,v2.w) ; CHECK-NEXT: v28 = vxor(v28,v28) ; CHECK-NEXT: } @@ -1867,26 +1869,28 @@ ; CHECK-NEXT: { ; CHECK-NEXT: v29 = vsplat(r2) ; CHECK-NEXT: v4.w = vasr(v4.w,r7) -; CHECK-NEXT: q2 = vcmp.gt(v28.w,v0.w) +; CHECK-NEXT: q2 = vcmp.gt(v28.w,v1.w) ; CHECK-NEXT: v3.w = vsub(v6.w,v3.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v8.w = vasl(v1.w,r5) -; CHECK-NEXT: q3 = vcmp.gt(v28.w,v1.w) +; CHECK-NEXT: v8.w = vasl(v0.w,r5) +; CHECK-NEXT: q3 = vcmp.gt(v28.w,v0.w) ; CHECK-NEXT: v4.w = vsub(v6.w,v4.w) ; CHECK-NEXT: v3.w = vmin(v3.w,v7.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v4.w = vmin(v4.w,v7.w) ; CHECK-NEXT: v2 = vor(v8,v2) -; CHECK-NEXT: q0 = vcmp.gt(v28.w,v3.w) +; CHECK-NEXT: q1 = vcmp.gt(v28.w,v3.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v5.w = vlsr(v5.w,v3.w) -; CHECK-NEXT: q1 = vcmp.gt(v28.w,v4.w) +; CHECK-NEXT: q0 = vcmp.gt(v28.w,v4.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v2.w = vlsr(v2.w,v4.w) +; CHECK-NEXT: v5.w = vlsr(v5.w,v4.w) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: v2.w = vlsr(v2.w,v3.w) ; CHECK-NEXT: v30 = vmux(q0,v29,v5) ; CHECK-NEXT: } ; CHECK-NEXT: { diff --git a/llvm/test/CodeGen/Hexagon/autohvx/int-to-fp.ll b/llvm/test/CodeGen/Hexagon/autohvx/int-to-fp.ll --- a/llvm/test/CodeGen/Hexagon/autohvx/int-to-fp.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/int-to-fp.ll @@ -1041,111 +1041,111 @@ ; CHECK-NEXT: { ; CHECK-NEXT: r3:2 = combine(#8,#1) ; CHECK-NEXT: r6 = #255 -; CHECK-NEXT: v2.w = vabs(v1.w) +; CHECK-NEXT: v3.w = vabs(v1.w) ; CHECK-NEXT: v1.cur = vmem(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v4 = vsplat(r2) ; CHECK-NEXT: r4 = #512 -; CHECK-NEXT: v3.w = vabs(v0.w) +; CHECK-NEXT: v2.w = vabs(v0.w) ; CHECK-NEXT: v0.cur = vmem(r0+#1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v9 = vsplat(r4) ; CHECK-NEXT: v8 = vsplat(r6) -; CHECK-NEXT: v5.uw = vcl0(v2.uw) +; CHECK-NEXT: v6.uw = vcl0(v3.uw) ; CHECK-NEXT: v7 = vxor(v7,v7) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r4 = #159 -; CHECK-NEXT: v6.uw = vcl0(v3.uw) -; CHECK-NEXT: v5.w = vadd(v5.w,v4.w) +; CHECK-NEXT: v5.uw = vcl0(v2.uw) +; CHECK-NEXT: v6.w = vadd(v6.w,v4.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v28 = vsplat(r4) +; CHECK-NEXT: v27 = vsplat(r4) ; CHECK-NEXT: r5 = ##-2147483648 -; CHECK-NEXT: v6.w = vadd(v6.w,v4.w) +; CHECK-NEXT: v5.w = vadd(v5.w,v4.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v13 = vsplat(r5) -; CHECK-NEXT: v2.w = vasl(v2.w,v5.w) +; CHECK-NEXT: v3.w = vasl(v3.w,v6.w) ; CHECK-NEXT: q0 = vcmp.gt(v7.w,v1.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v3.w = vasl(v3.w,v6.w) -; CHECK-NEXT: v27 = vmux(q0,v13,v7) -; CHECK-NEXT: v10.w = vadd(v2.w,v8.w) -; CHECK-NEXT: v11 = vand(v2,v9) +; CHECK-NEXT: v2.w = vasl(v2.w,v5.w) +; CHECK-NEXT: v26 = vmux(q0,v13,v7) +; CHECK-NEXT: v10.w = vadd(v3.w,v8.w) +; CHECK-NEXT: v11 = vand(v3,v9) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v9 = vand(v3,v9) +; CHECK-NEXT: v9 = vand(v2,v9) ; CHECK-NEXT: q1 = vcmp.eq(v11.w,v7.w) -; CHECK-NEXT: v8.w = vadd(v3.w,v8.w) -; CHECK-NEXT: q2 = vcmp.gt(v2.uw,v10.uw) +; CHECK-NEXT: v8.w = vadd(v2.w,v8.w) +; CHECK-NEXT: q2 = vcmp.gt(v3.uw,v10.uw) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v12.uw = vlsr(v2.uw,r3) +; CHECK-NEXT: v12.uw = vlsr(v3.uw,r3) ; CHECK-NEXT: q3 = vcmp.eq(v9.w,v7.w) -; CHECK-NEXT: v23 = vmux(q1,v7,v4) -; CHECK-NEXT: q1 = vcmp.gt(v3.uw,v8.uw) +; CHECK-NEXT: v22 = vmux(q1,v7,v4) +; CHECK-NEXT: q1 = vcmp.gt(v2.uw,v8.uw) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v2.uw = vlsr(v10.uw,r3) -; CHECK-NEXT: v25 = vmux(q3,v7,v4) -; CHECK-NEXT: v24 = vmux(q2,v4,v7) +; CHECK-NEXT: v3.uw = vlsr(v10.uw,r3) +; CHECK-NEXT: v24 = vmux(q3,v7,v4) +; CHECK-NEXT: v23 = vmux(q2,v4,v7) ; CHECK-NEXT: v4 = vmux(q1,v4,v7) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v8.uw = vlsr(v8.uw,r3) -; CHECK-NEXT: v9.w = vadd(v2.w,v23.w) -; CHECK-NEXT: v5.w = vsub(v24.w,v5.w) -; CHECK-NEXT: v4.w = vsub(v4.w,v6.w) +; CHECK-NEXT: v9.w = vadd(v3.w,v22.w) +; CHECK-NEXT: v6.w = vsub(v23.w,v6.w) +; CHECK-NEXT: v4.w = vsub(v4.w,v5.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v3.uw = vlsr(v3.uw,r3) -; CHECK-NEXT: v26.w = vadd(v8.w,v25.w) -; CHECK-NEXT: q3 = vcmp.eq(v12.w,v2.w) -; CHECK-NEXT: v5.w = vadd(v5.w,v28.w) +; CHECK-NEXT: v2.uw = vlsr(v2.uw,r3) +; CHECK-NEXT: v25.w = vadd(v8.w,v24.w) +; CHECK-NEXT: q3 = vcmp.eq(v12.w,v3.w) +; CHECK-NEXT: v6.w = vadd(v6.w,v27.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r3 = #23 -; CHECK-NEXT: v2.uw = vlsr(v2.uw,r2) -; CHECK-NEXT: q2 = vcmp.eq(v3.w,v8.w) -; CHECK-NEXT: v4.w = vadd(v4.w,v28.w) +; CHECK-NEXT: v3.uw = vlsr(v3.uw,r2) +; CHECK-NEXT: q2 = vcmp.eq(v2.w,v8.w) +; CHECK-NEXT: v4.w = vadd(v4.w,v27.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v9.uw = vlsr(v9.uw,r2) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v29.uw = vlsr(v26.uw,r2) -; CHECK-NEXT: v2 = vmux(q3,v9,v2) +; CHECK-NEXT: v28.uw = vlsr(v25.uw,r2) +; CHECK-NEXT: v3 = vmux(q3,v9,v3) ; CHECK-NEXT: q3 = vcmp.gt(v7.w,v0.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v3.uw = vlsr(v8.uw,r2) +; CHECK-NEXT: v2.uw = vlsr(v8.uw,r2) ; CHECK-NEXT: v30 = vmux(q3,v13,v7) -; CHECK-NEXT: v2 = vor(v27,v2) +; CHECK-NEXT: v3 = vor(v26,v3) ; CHECK-NEXT: q3 = vcmp.eq(v0.w,v7.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v5.w = vasl(v5.w,r3) -; CHECK-NEXT: v3 = vmux(q2,v29,v3) +; CHECK-NEXT: v29.w = vasl(v6.w,r3) +; CHECK-NEXT: v2 = vmux(q2,v28,v2) ; CHECK-NEXT: q2 = vcmp.eq(v1.w,v7.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v3.w = vasl(v4.w,r3) -; CHECK-NEXT: v31 = vor(v30,v3) -; CHECK-NEXT: v2 = vor(v2,v5) +; CHECK-NEXT: v2.w = vasl(v4.w,r3) +; CHECK-NEXT: v31 = vor(v30,v2) +; CHECK-NEXT: v3 = vor(v3,v29) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v1 = vor(v31,v3) -; CHECK-NEXT: v2 = vmux(q2,v7,v2) +; CHECK-NEXT: v1 = vor(v31,v2) +; CHECK-NEXT: v3 = vmux(q2,v7,v3) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v0 = vmux(q3,v7,v1) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v2.qf32 = vadd(v2.sf,v7.sf) +; CHECK-NEXT: v2.qf32 = vadd(v3.sf,v7.sf) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v3.qf32 = vadd(v0.sf,v7.sf) @@ -2372,19 +2372,19 @@ ; CHECK-NEXT: r3:2 = combine(#8,#1) ; CHECK-NEXT: r6 = #255 ; CHECK-NEXT: v1.uw = vcl0(v0.uw) -; CHECK-NEXT: v0.cur = vmem(r0+#0) +; CHECK-NEXT: v0.cur = vmem(r0+#1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v4 = vsplat(r2) ; CHECK-NEXT: r4 = #512 ; CHECK-NEXT: v3.uw = vcl0(v2.uw) -; CHECK-NEXT: v2.cur = vmem(r0+#1) +; CHECK-NEXT: v2.cur = vmem(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v7 = vsplat(r4) ; CHECK-NEXT: v6 = vsplat(r6) -; CHECK-NEXT: v1.w = vadd(v1.w,v4.w) ; CHECK-NEXT: v3.w = vadd(v3.w,v4.w) +; CHECK-NEXT: v1.w = vadd(v1.w,v4.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r4 = #159 @@ -2392,10 +2392,10 @@ ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v10 = vsplat(r4) -; CHECK-NEXT: v5.w = vasl(v0.w,v1.w) +; CHECK-NEXT: v5.w = vasl(v2.w,v3.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v8.w = vasl(v2.w,v3.w) +; CHECK-NEXT: v8.w = vasl(v0.w,v1.w) ; CHECK-NEXT: v11.w = vadd(v5.w,v6.w) ; CHECK-NEXT: v13 = vand(v5,v7) ; CHECK-NEXT: } @@ -2406,36 +2406,36 @@ ; CHECK-NEXT: q1 = vcmp.eq(v13.w,v9.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v27.uw = vlsr(v11.uw,r3) +; CHECK-NEXT: v28.uw = vlsr(v11.uw,r3) ; CHECK-NEXT: q3 = vcmp.gt(v8.uw,v6.uw) ; CHECK-NEXT: q2 = vcmp.eq(v7.w,v9.w) -; CHECK-NEXT: v29 = vmux(q0,v4,v9) +; CHECK-NEXT: v30 = vmux(q0,v4,v9) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v6.uw = vlsr(v6.uw,r3) -; CHECK-NEXT: v28 = vmux(q1,v9,v4) -; CHECK-NEXT: v30 = vmux(q3,v4,v9) +; CHECK-NEXT: v29 = vmux(q1,v9,v4) +; CHECK-NEXT: v31 = vmux(q3,v4,v9) ; CHECK-NEXT: v4 = vmux(q2,v9,v4) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v1.w = vsub(v29.w,v1.w) -; CHECK-NEXT: v7.w = vadd(v27.w,v28.w) ; CHECK-NEXT: v3.w = vsub(v30.w,v3.w) +; CHECK-NEXT: v7.w = vadd(v28.w,v29.w) +; CHECK-NEXT: v1.w = vsub(v31.w,v1.w) ; CHECK-NEXT: v4.w = vadd(v6.w,v4.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v12.uw = vlsr(v5.uw,r3) -; CHECK-NEXT: v1.w = vadd(v1.w,v10.w) ; CHECK-NEXT: v3.w = vadd(v3.w,v10.w) -; CHECK-NEXT: q2 = vcmp.eq(v0.w,v9.w) +; CHECK-NEXT: v1.w = vadd(v1.w,v10.w) +; CHECK-NEXT: q2 = vcmp.eq(v2.w,v9.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r3 = #23 ; CHECK-NEXT: v14.uw = vlsr(v8.uw,r3) -; CHECK-NEXT: q3 = vcmp.eq(v12.w,v27.w) +; CHECK-NEXT: q3 = vcmp.eq(v12.w,v28.w) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v5.uw = vlsr(v27.uw,r2) +; CHECK-NEXT: v5.uw = vlsr(v28.uw,r2) ; CHECK-NEXT: q1 = vcmp.eq(v14.w,v6.w) ; CHECK-NEXT: } ; CHECK-NEXT: { @@ -2444,28 +2444,28 @@ ; CHECK-NEXT: { ; CHECK-NEXT: v4.uw = vlsr(v4.uw,r2) ; CHECK-NEXT: v5 = vmux(q3,v7,v5) -; CHECK-NEXT: q3 = vcmp.eq(v2.w,v9.w) +; CHECK-NEXT: q3 = vcmp.eq(v0.w,v9.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v6.uw = vlsr(v6.uw,r2) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v1.w = vasl(v1.w,r3) -; CHECK-NEXT: v31 = vmux(q1,v4,v6) +; CHECK-NEXT: v3.w = vasl(v3.w,r3) +; CHECK-NEXT: v2 = vmux(q1,v4,v6) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v3.w = vasl(v3.w,r3) -; CHECK-NEXT: v1 = vor(v5,v1) +; CHECK-NEXT: v1.w = vasl(v1.w,r3) +; CHECK-NEXT: v3 = vor(v5,v3) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0 = vor(v31,v3) -; CHECK-NEXT: v1 = vmux(q2,v9,v1) +; CHECK-NEXT: v1 = vor(v2,v1) +; CHECK-NEXT: v3 = vmux(q2,v9,v3) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0 = vmux(q3,v9,v0) +; CHECK-NEXT: v0 = vmux(q3,v9,v1) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v2.qf32 = vadd(v1.sf,v9.sf) +; CHECK-NEXT: v2.qf32 = vadd(v3.sf,v9.sf) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v3.qf32 = vadd(v0.sf,v9.sf) diff --git a/llvm/test/CodeGen/Hexagon/autohvx/mulh.ll b/llvm/test/CodeGen/Hexagon/autohvx/mulh.ll --- a/llvm/test/CodeGen/Hexagon/autohvx/mulh.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/mulh.ll @@ -7,16 +7,31 @@ ; V60-LABEL: mulhs16: ; V60: // %bb.0: ; V60-NEXT: { -; V60-NEXT: v1:0.w = vmpy(v0.h,v1.h) +; V60-NEXT: v1:0.w = vmpy(v1.h,v0.h) ; V60-NEXT: } ; V60-NEXT: { -; V60-NEXT: r7 = #-4 +; V60-NEXT: r7:6 = combine(#64,#68) ; V60-NEXT: } ; V60-NEXT: { -; V60-NEXT: v1:0 = vdeal(v1,v0,r7) +; V60-NEXT: r5 = #120 ; V60-NEXT: } ; V60-NEXT: { -; V60-NEXT: v0.h = vpacko(v1.w,v0.w) +; V60-NEXT: v1:0 = vshuff(v1,v0,r7) +; V60-NEXT: } +; V60-NEXT: { +; V60-NEXT: v3:2 = vdeal(v0,v0,r6) +; V60-NEXT: } +; V60-NEXT: { +; V60-NEXT: v31:30 = vdeal(v0,v1,r6) +; V60-NEXT: } +; V60-NEXT: { +; V60-NEXT: v3:2 = vshuff(v3,v2,r5) +; V60-NEXT: } +; V60-NEXT: { +; V60-NEXT: v1:0 = vshuff(v31,v30,r5) +; V60-NEXT: } +; V60-NEXT: { +; V60-NEXT: v0.h = vpacko(v0.w,v2.w) ; V60-NEXT: } ; V60-NEXT: { ; V60-NEXT: jumpr r31 @@ -25,16 +40,31 @@ ; V65-LABEL: mulhs16: ; V65: // %bb.0: ; V65-NEXT: { -; V65-NEXT: v1:0.w = vmpy(v0.h,v1.h) +; V65-NEXT: v1:0.w = vmpy(v1.h,v0.h) +; V65-NEXT: } +; V65-NEXT: { +; V65-NEXT: r7:6 = combine(#64,#68) +; V65-NEXT: } +; V65-NEXT: { +; V65-NEXT: r5 = #120 +; V65-NEXT: } +; V65-NEXT: { +; V65-NEXT: v1:0 = vshuff(v1,v0,r7) +; V65-NEXT: } +; V65-NEXT: { +; V65-NEXT: v3:2 = vdeal(v0,v0,r6) +; V65-NEXT: } +; V65-NEXT: { +; V65-NEXT: v31:30 = vdeal(v0,v1,r6) ; V65-NEXT: } ; V65-NEXT: { -; V65-NEXT: r7 = #-4 +; V65-NEXT: v3:2 = vshuff(v3,v2,r5) ; V65-NEXT: } ; V65-NEXT: { -; V65-NEXT: v1:0 = vdeal(v1,v0,r7) +; V65-NEXT: v1:0 = vshuff(v31,v30,r5) ; V65-NEXT: } ; V65-NEXT: { -; V65-NEXT: v0.h = vpacko(v1.w,v0.w) +; V65-NEXT: v0.h = vpacko(v0.w,v2.w) ; V65-NEXT: } ; V65-NEXT: { ; V65-NEXT: jumpr r31 @@ -43,16 +73,31 @@ ; V69-LABEL: mulhs16: ; V69: // %bb.0: ; V69-NEXT: { -; V69-NEXT: v1:0.w = vmpy(v0.h,v1.h) +; V69-NEXT: v1:0.w = vmpy(v1.h,v0.h) +; V69-NEXT: } +; V69-NEXT: { +; V69-NEXT: r7:6 = combine(#64,#68) +; V69-NEXT: } +; V69-NEXT: { +; V69-NEXT: r5 = #120 +; V69-NEXT: } +; V69-NEXT: { +; V69-NEXT: v1:0 = vshuff(v1,v0,r7) ; V69-NEXT: } ; V69-NEXT: { -; V69-NEXT: r7 = #-4 +; V69-NEXT: v3:2 = vdeal(v0,v0,r6) ; V69-NEXT: } ; V69-NEXT: { -; V69-NEXT: v1:0 = vdeal(v1,v0,r7) +; V69-NEXT: v31:30 = vdeal(v0,v1,r6) ; V69-NEXT: } ; V69-NEXT: { -; V69-NEXT: v0.h = vpacko(v1.w,v0.w) +; V69-NEXT: v3:2 = vshuff(v3,v2,r5) +; V69-NEXT: } +; V69-NEXT: { +; V69-NEXT: v1:0 = vshuff(v31,v30,r5) +; V69-NEXT: } +; V69-NEXT: { +; V69-NEXT: v0.h = vpacko(v0.w,v2.w) ; V69-NEXT: } ; V69-NEXT: { ; V69-NEXT: jumpr r31 @@ -69,16 +114,31 @@ ; V60-LABEL: mulhu16: ; V60: // %bb.0: ; V60-NEXT: { -; V60-NEXT: v1:0.uw = vmpy(v0.uh,v1.uh) +; V60-NEXT: v1:0.uw = vmpy(v1.uh,v0.uh) +; V60-NEXT: } +; V60-NEXT: { +; V60-NEXT: r7:6 = combine(#64,#68) +; V60-NEXT: } +; V60-NEXT: { +; V60-NEXT: r5 = #120 +; V60-NEXT: } +; V60-NEXT: { +; V60-NEXT: v1:0 = vshuff(v1,v0,r7) +; V60-NEXT: } +; V60-NEXT: { +; V60-NEXT: v3:2 = vdeal(v0,v0,r6) ; V60-NEXT: } ; V60-NEXT: { -; V60-NEXT: r7 = #-4 +; V60-NEXT: v31:30 = vdeal(v0,v1,r6) ; V60-NEXT: } ; V60-NEXT: { -; V60-NEXT: v1:0 = vdeal(v1,v0,r7) +; V60-NEXT: v3:2 = vshuff(v3,v2,r5) ; V60-NEXT: } ; V60-NEXT: { -; V60-NEXT: v0.h = vpacko(v1.w,v0.w) +; V60-NEXT: v1:0 = vshuff(v31,v30,r5) +; V60-NEXT: } +; V60-NEXT: { +; V60-NEXT: v0.h = vpacko(v0.w,v2.w) ; V60-NEXT: } ; V60-NEXT: { ; V60-NEXT: jumpr r31 @@ -87,16 +147,31 @@ ; V65-LABEL: mulhu16: ; V65: // %bb.0: ; V65-NEXT: { -; V65-NEXT: v1:0.uw = vmpy(v0.uh,v1.uh) +; V65-NEXT: v1:0.uw = vmpy(v1.uh,v0.uh) +; V65-NEXT: } +; V65-NEXT: { +; V65-NEXT: r7:6 = combine(#64,#68) +; V65-NEXT: } +; V65-NEXT: { +; V65-NEXT: r5 = #120 +; V65-NEXT: } +; V65-NEXT: { +; V65-NEXT: v1:0 = vshuff(v1,v0,r7) +; V65-NEXT: } +; V65-NEXT: { +; V65-NEXT: v3:2 = vdeal(v0,v0,r6) +; V65-NEXT: } +; V65-NEXT: { +; V65-NEXT: v31:30 = vdeal(v0,v1,r6) ; V65-NEXT: } ; V65-NEXT: { -; V65-NEXT: r7 = #-4 +; V65-NEXT: v3:2 = vshuff(v3,v2,r5) ; V65-NEXT: } ; V65-NEXT: { -; V65-NEXT: v1:0 = vdeal(v1,v0,r7) +; V65-NEXT: v1:0 = vshuff(v31,v30,r5) ; V65-NEXT: } ; V65-NEXT: { -; V65-NEXT: v0.h = vpacko(v1.w,v0.w) +; V65-NEXT: v0.h = vpacko(v0.w,v2.w) ; V65-NEXT: } ; V65-NEXT: { ; V65-NEXT: jumpr r31 diff --git a/llvm/test/CodeGen/Hexagon/autohvx/qmul.ll b/llvm/test/CodeGen/Hexagon/autohvx/qmul.ll --- a/llvm/test/CodeGen/Hexagon/autohvx/qmul.ll +++ b/llvm/test/CodeGen/Hexagon/autohvx/qmul.ll @@ -72,31 +72,46 @@ ; CHECK-LABEL: f2: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: v0 = vmem(r0+#0) +; CHECK-NEXT: v0 = vmem(r1+#0) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r7 = #64 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7 = #-4 +; CHECK-NEXT: r5:4 = combine(#68,#120) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r3 = #15 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v1 = vmem(r1+#0) +; CHECK-NEXT: v1 = vmem(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: v1:0.w = vmpy(v0.h,v1.h) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v1:0 = vdeal(v1,v0,r7) +; CHECK-NEXT: v1:0 = vshuff(v1,v0,r7) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0.uw = vlsr(v0.uw,r3) +; CHECK-NEXT: v3:2 = vdeal(v0,v0,r5) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: v31:30 = vdeal(v0,v1,r5) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v1.uw = vlsr(v1.uw,r3) +; CHECK-NEXT: v3:2 = vshuff(v3,v2,r4) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: v1:0 = vshuff(v31,v30,r4) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: v1.uw = vlsr(v2.uw,r3) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: v0.uw = vlsr(v0.uw,r3) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: v0.h = vpacke(v1.w,v0.w) +; CHECK-NEXT: v0.h = vpacke(v0.w,v1.w) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: vmem(r2+#0) = v0 diff --git a/llvm/test/CodeGen/LoongArch/get-reg-error-la32.ll b/llvm/test/CodeGen/LoongArch/get-reg-error-la32.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/get-reg-error-la32.ll @@ -0,0 +1,21 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: not llc < %s --mtriple=loongarch32 2>&1 | FileCheck %s + +define i64 @read_sp() nounwind { +entry: +; CHECK: On LA32, only 32-bit registers can be read. + %a1 = call i64 @llvm.read_register.i64(metadata !0) + ret i64 %a1 +} + +define void @write_sp(i64 %val) nounwind { +entry: +; CHECK: On LA32, only 32-bit registers can be written. + call void @llvm.write_register.i64(metadata !0, i64 %val) + ret void +} + +declare i64 @llvm.read_register.i64(metadata) nounwind +declare void @llvm.write_register.i64(metadata, i64) nounwind + +!0 = !{!"$sp\00"} diff --git a/llvm/test/CodeGen/LoongArch/get-reg-error-la64.ll b/llvm/test/CodeGen/LoongArch/get-reg-error-la64.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/get-reg-error-la64.ll @@ -0,0 +1,21 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: not llc < %s --mtriple=loongarch64 2>&1 | FileCheck %s + +define i32 @read_sp() nounwind { +entry: +; CHECK: On LA64, only 64-bit registers can be read. + %a1 = call i32 @llvm.read_register.i32(metadata !0) + ret i32 %a1 +} + +define void @write_sp(i32 %val) nounwind { +entry: +; CHECK: On LA64, only 64-bit registers can be written. + call void @llvm.write_register.i32(metadata !0, i32 %val) + ret void +} + +declare i32 @llvm.read_register.i32(metadata) nounwind +declare void @llvm.write_register.i32(metadata, i32) nounwind + +!0 = !{!"$sp\00"} diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll --- a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll +++ b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw.ll @@ -109,9 +109,9 @@ ; LA32: # %bb.0: ; LA32-NEXT: .LBB2_1: # =>This Inner Loop Header: Depth=1 ; LA32-NEXT: dbar 0 -; LA32-NEXT: ll.w $a2, $a1, 0 -; LA32-NEXT: move $a3, $a0 -; LA32-NEXT: sc.w $a3, $a1, 0 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: move $a3, $a1 +; LA32-NEXT: sc.w $a3, $a0, 0 ; LA32-NEXT: beqz $a3, .LBB2_1 ; LA32-NEXT: # %bb.2: ; LA32-NEXT: move $a0, $a2 @@ -253,9 +253,9 @@ ; LA32: # %bb.0: ; LA32-NEXT: .LBB6_1: # =>This Inner Loop Header: Depth=1 ; LA32-NEXT: dbar 0 -; LA32-NEXT: ll.w $a2, $a1, 0 -; LA32-NEXT: add.w $a3, $a2, $a0 -; LA32-NEXT: sc.w $a3, $a1, 0 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: add.w $a3, $a2, $a1 +; LA32-NEXT: sc.w $a3, $a0, 0 ; LA32-NEXT: beqz $a3, .LBB6_1 ; LA32-NEXT: # %bb.2: ; LA32-NEXT: move $a0, $a2 @@ -397,9 +397,9 @@ ; LA32: # %bb.0: ; LA32-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 ; LA32-NEXT: dbar 0 -; LA32-NEXT: ll.w $a2, $a1, 0 -; LA32-NEXT: sub.w $a3, $a2, $a0 -; LA32-NEXT: sc.w $a3, $a1, 0 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: sub.w $a3, $a2, $a1 +; LA32-NEXT: sc.w $a3, $a0, 0 ; LA32-NEXT: beqz $a3, .LBB10_1 ; LA32-NEXT: # %bb.2: ; LA32-NEXT: move $a0, $a2 @@ -612,9 +612,9 @@ ; LA32-NEXT: and $a0, $a0, $a3 ; LA32-NEXT: .LBB16_1: # =>This Inner Loop Header: Depth=1 ; LA32-NEXT: dbar 0 -; LA32-NEXT: ll.w $a3, $a1, 0 -; LA32-NEXT: and $a4, $a3, $a0 -; LA32-NEXT: sc.w $a4, $a1, 0 +; LA32-NEXT: ll.w $a3, $a0, 0 +; LA32-NEXT: and $a4, $a3, $a1 +; LA32-NEXT: sc.w $a4, $a0, 0 ; LA32-NEXT: beqz $a4, .LBB16_1 ; LA32-NEXT: # %bb.2: ; LA32-NEXT: srl.w $a0, $a3, $a2 @@ -651,9 +651,9 @@ ; LA32-NEXT: and $a0, $a0, $a2 ; LA32-NEXT: .LBB17_1: # =>This Inner Loop Header: Depth=1 ; LA32-NEXT: dbar 0 -; LA32-NEXT: ll.w $a2, $a1, 0 -; LA32-NEXT: and $a4, $a2, $a0 -; LA32-NEXT: sc.w $a4, $a1, 0 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: and $a4, $a2, $a1 +; LA32-NEXT: sc.w $a4, $a0, 0 ; LA32-NEXT: beqz $a4, .LBB17_1 ; LA32-NEXT: # %bb.2: ; LA32-NEXT: srl.w $a0, $a2, $a3 @@ -682,9 +682,9 @@ ; LA32: # %bb.0: ; LA32-NEXT: .LBB18_1: # =>This Inner Loop Header: Depth=1 ; LA32-NEXT: dbar 0 -; LA32-NEXT: ll.w $a2, $a1, 0 -; LA32-NEXT: and $a3, $a2, $a0 -; LA32-NEXT: sc.w $a3, $a1, 0 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: and $a3, $a2, $a1 +; LA32-NEXT: sc.w $a3, $a0, 0 ; LA32-NEXT: beqz $a3, .LBB18_1 ; LA32-NEXT: # %bb.2: ; LA32-NEXT: move $a0, $a2 @@ -729,9 +729,9 @@ ; LA32-NEXT: sll.w $a1, $a1, $a0 ; LA32-NEXT: .LBB20_1: # =>This Inner Loop Header: Depth=1 ; LA32-NEXT: dbar 0 -; LA32-NEXT: ll.w $a3, $a1, 0 -; LA32-NEXT: or $a4, $a3, $a2 -; LA32-NEXT: sc.w $a4, $a1, 0 +; LA32-NEXT: ll.w $a3, $a2, 0 +; LA32-NEXT: or $a4, $a3, $a1 +; LA32-NEXT: sc.w $a4, $a2, 0 ; LA32-NEXT: beqz $a4, .LBB20_1 ; LA32-NEXT: # %bb.2: ; LA32-NEXT: srl.w $a0, $a3, $a0 @@ -761,9 +761,9 @@ ; LA32-NEXT: sll.w $a1, $a1, $a0 ; LA32-NEXT: .LBB21_1: # =>This Inner Loop Header: Depth=1 ; LA32-NEXT: dbar 0 -; LA32-NEXT: ll.w $a3, $a1, 0 -; LA32-NEXT: or $a4, $a3, $a2 -; LA32-NEXT: sc.w $a4, $a1, 0 +; LA32-NEXT: ll.w $a3, $a2, 0 +; LA32-NEXT: or $a4, $a3, $a1 +; LA32-NEXT: sc.w $a4, $a2, 0 ; LA32-NEXT: beqz $a4, .LBB21_1 ; LA32-NEXT: # %bb.2: ; LA32-NEXT: srl.w $a0, $a3, $a0 @@ -788,9 +788,9 @@ ; LA32: # %bb.0: ; LA32-NEXT: .LBB22_1: # =>This Inner Loop Header: Depth=1 ; LA32-NEXT: dbar 0 -; LA32-NEXT: ll.w $a2, $a1, 0 -; LA32-NEXT: or $a3, $a2, $a0 -; LA32-NEXT: sc.w $a3, $a1, 0 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: or $a3, $a2, $a1 +; LA32-NEXT: sc.w $a3, $a0, 0 ; LA32-NEXT: beqz $a3, .LBB22_1 ; LA32-NEXT: # %bb.2: ; LA32-NEXT: move $a0, $a2 @@ -835,9 +835,9 @@ ; LA32-NEXT: sll.w $a1, $a1, $a0 ; LA32-NEXT: .LBB24_1: # =>This Inner Loop Header: Depth=1 ; LA32-NEXT: dbar 0 -; LA32-NEXT: ll.w $a3, $a1, 0 -; LA32-NEXT: xor $a4, $a3, $a2 -; LA32-NEXT: sc.w $a4, $a1, 0 +; LA32-NEXT: ll.w $a3, $a2, 0 +; LA32-NEXT: xor $a4, $a3, $a1 +; LA32-NEXT: sc.w $a4, $a2, 0 ; LA32-NEXT: beqz $a4, .LBB24_1 ; LA32-NEXT: # %bb.2: ; LA32-NEXT: srl.w $a0, $a3, $a0 @@ -867,9 +867,9 @@ ; LA32-NEXT: sll.w $a1, $a1, $a0 ; LA32-NEXT: .LBB25_1: # =>This Inner Loop Header: Depth=1 ; LA32-NEXT: dbar 0 -; LA32-NEXT: ll.w $a3, $a1, 0 -; LA32-NEXT: xor $a4, $a3, $a2 -; LA32-NEXT: sc.w $a4, $a1, 0 +; LA32-NEXT: ll.w $a3, $a2, 0 +; LA32-NEXT: xor $a4, $a3, $a1 +; LA32-NEXT: sc.w $a4, $a2, 0 ; LA32-NEXT: beqz $a4, .LBB25_1 ; LA32-NEXT: # %bb.2: ; LA32-NEXT: srl.w $a0, $a3, $a0 @@ -894,9 +894,9 @@ ; LA32: # %bb.0: ; LA32-NEXT: .LBB26_1: # =>This Inner Loop Header: Depth=1 ; LA32-NEXT: dbar 0 -; LA32-NEXT: ll.w $a2, $a1, 0 -; LA32-NEXT: xor $a3, $a2, $a0 -; LA32-NEXT: sc.w $a3, $a1, 0 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: xor $a3, $a2, $a1 +; LA32-NEXT: sc.w $a3, $a0, 0 ; LA32-NEXT: beqz $a3, .LBB26_1 ; LA32-NEXT: # %bb.2: ; LA32-NEXT: move $a0, $a2 @@ -930,3 +930,901 @@ %1 = atomicrmw xor ptr %a, i64 %b acquire ret i64 %1 } + +define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { +; LA32-LABEL: atomicrmw_xchg_i8_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $a2, $zero, -4 +; LA32-NEXT: and $a2, $a0, $a2 +; LA32-NEXT: slli.w $a0, $a0, 3 +; LA32-NEXT: ori $a3, $zero, 255 +; LA32-NEXT: sll.w $a3, $a3, $a0 +; LA32-NEXT: andi $a1, $a1, 255 +; LA32-NEXT: sll.w $a1, $a1, $a0 +; LA32-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a4, $a2, 0 +; LA32-NEXT: addi.w $a5, $a1, 0 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: and $a5, $a5, $a3 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: sc.w $a5, $a2, 0 +; LA32-NEXT: beqz $a5, .LBB28_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a4, $a0 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_xchg_i8_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: addi.w $a2, $zero, -4 +; LA64-NEXT: and $a2, $a0, $a2 +; LA64-NEXT: slli.d $a0, $a0, 3 +; LA64-NEXT: ori $a3, $zero, 255 +; LA64-NEXT: sll.w $a3, $a3, $a0 +; LA64-NEXT: addi.w $a3, $a3, 0 +; LA64-NEXT: andi $a1, $a1, 255 +; LA64-NEXT: sll.w $a1, $a1, $a0 +; LA64-NEXT: addi.w $a1, $a1, 0 +; LA64-NEXT: .LBB28_1: # =>This Inner Loop Header: Depth=1 +; LA64-NEXT: ll.w $a4, $a2, 0 +; LA64-NEXT: addi.w $a5, $a1, 0 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: and $a5, $a5, $a3 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: sc.w $a5, $a2, 0 +; LA64-NEXT: beqz $a5, .LBB28_1 +; LA64-NEXT: # %bb.2: +; LA64-NEXT: srl.w $a0, $a4, $a0 +; LA64-NEXT: ret + %1 = atomicrmw xchg ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { +; LA32-LABEL: atomicrmw_xchg_i16_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $a2, $zero, -4 +; LA32-NEXT: and $a2, $a0, $a2 +; LA32-NEXT: slli.w $a0, $a0, 3 +; LA32-NEXT: lu12i.w $a3, 15 +; LA32-NEXT: ori $a3, $a3, 4095 +; LA32-NEXT: sll.w $a3, $a3, $a0 +; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0 +; LA32-NEXT: sll.w $a1, $a1, $a0 +; LA32-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a4, $a2, 0 +; LA32-NEXT: addi.w $a5, $a1, 0 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: and $a5, $a5, $a3 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: sc.w $a5, $a2, 0 +; LA32-NEXT: beqz $a5, .LBB29_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a4, $a0 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_xchg_i16_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: addi.w $a2, $zero, -4 +; LA64-NEXT: and $a2, $a0, $a2 +; LA64-NEXT: slli.d $a0, $a0, 3 +; LA64-NEXT: lu12i.w $a3, 15 +; LA64-NEXT: ori $a3, $a3, 4095 +; LA64-NEXT: sll.w $a3, $a3, $a0 +; LA64-NEXT: addi.w $a3, $a3, 0 +; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0 +; LA64-NEXT: sll.w $a1, $a1, $a0 +; LA64-NEXT: addi.w $a1, $a1, 0 +; LA64-NEXT: .LBB29_1: # =>This Inner Loop Header: Depth=1 +; LA64-NEXT: ll.w $a4, $a2, 0 +; LA64-NEXT: addi.w $a5, $a1, 0 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: and $a5, $a5, $a3 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: sc.w $a5, $a2, 0 +; LA64-NEXT: beqz $a5, .LBB29_1 +; LA64-NEXT: # %bb.2: +; LA64-NEXT: srl.w $a0, $a4, $a0 +; LA64-NEXT: ret + %1 = atomicrmw xchg ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { +; LA32-LABEL: atomicrmw_xchg_i32_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: .LBB30_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: move $a3, $a1 +; LA32-NEXT: sc.w $a3, $a0, 0 +; LA32-NEXT: beqz $a3, .LBB30_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: move $a0, $a2 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_xchg_i32_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: amswap_db.w $a2, $a1, $a0 +; LA64-NEXT: move $a0, $a2 +; LA64-NEXT: ret + %1 = atomicrmw xchg ptr %a, i32 %b monotonic + ret i32 %1 +} + +define i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind { +; LA32-LABEL: atomicrmw_xchg_i64_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $sp, $sp, -16 +; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill +; LA32-NEXT: move $a3, $zero +; LA32-NEXT: bl %plt(__atomic_exchange_8) +; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 16 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_xchg_i64_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: amswap_db.d $a2, $a1, $a0 +; LA64-NEXT: move $a0, $a2 +; LA64-NEXT: ret + %1 = atomicrmw xchg ptr %a, i64 %b monotonic + ret i64 %1 +} + +define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { +; LA32-LABEL: atomicrmw_add_i8_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $a2, $zero, -4 +; LA32-NEXT: and $a2, $a0, $a2 +; LA32-NEXT: slli.w $a0, $a0, 3 +; LA32-NEXT: ori $a3, $zero, 255 +; LA32-NEXT: sll.w $a3, $a3, $a0 +; LA32-NEXT: andi $a1, $a1, 255 +; LA32-NEXT: sll.w $a1, $a1, $a0 +; LA32-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a4, $a2, 0 +; LA32-NEXT: add.w $a5, $a4, $a1 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: and $a5, $a5, $a3 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: sc.w $a5, $a2, 0 +; LA32-NEXT: beqz $a5, .LBB32_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a4, $a0 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_add_i8_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: addi.w $a2, $zero, -4 +; LA64-NEXT: and $a2, $a0, $a2 +; LA64-NEXT: slli.d $a0, $a0, 3 +; LA64-NEXT: ori $a3, $zero, 255 +; LA64-NEXT: sll.w $a3, $a3, $a0 +; LA64-NEXT: addi.w $a3, $a3, 0 +; LA64-NEXT: andi $a1, $a1, 255 +; LA64-NEXT: sll.w $a1, $a1, $a0 +; LA64-NEXT: addi.w $a1, $a1, 0 +; LA64-NEXT: .LBB32_1: # =>This Inner Loop Header: Depth=1 +; LA64-NEXT: ll.w $a4, $a2, 0 +; LA64-NEXT: add.w $a5, $a4, $a1 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: and $a5, $a5, $a3 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: sc.w $a5, $a2, 0 +; LA64-NEXT: beqz $a5, .LBB32_1 +; LA64-NEXT: # %bb.2: +; LA64-NEXT: srl.w $a0, $a4, $a0 +; LA64-NEXT: ret + %1 = atomicrmw add ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { +; LA32-LABEL: atomicrmw_add_i16_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $a2, $zero, -4 +; LA32-NEXT: and $a2, $a0, $a2 +; LA32-NEXT: slli.w $a0, $a0, 3 +; LA32-NEXT: lu12i.w $a3, 15 +; LA32-NEXT: ori $a3, $a3, 4095 +; LA32-NEXT: sll.w $a3, $a3, $a0 +; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0 +; LA32-NEXT: sll.w $a1, $a1, $a0 +; LA32-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a4, $a2, 0 +; LA32-NEXT: add.w $a5, $a4, $a1 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: and $a5, $a5, $a3 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: sc.w $a5, $a2, 0 +; LA32-NEXT: beqz $a5, .LBB33_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a4, $a0 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_add_i16_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: addi.w $a2, $zero, -4 +; LA64-NEXT: and $a2, $a0, $a2 +; LA64-NEXT: slli.d $a0, $a0, 3 +; LA64-NEXT: lu12i.w $a3, 15 +; LA64-NEXT: ori $a3, $a3, 4095 +; LA64-NEXT: sll.w $a3, $a3, $a0 +; LA64-NEXT: addi.w $a3, $a3, 0 +; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0 +; LA64-NEXT: sll.w $a1, $a1, $a0 +; LA64-NEXT: addi.w $a1, $a1, 0 +; LA64-NEXT: .LBB33_1: # =>This Inner Loop Header: Depth=1 +; LA64-NEXT: ll.w $a4, $a2, 0 +; LA64-NEXT: add.w $a5, $a4, $a1 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: and $a5, $a5, $a3 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: sc.w $a5, $a2, 0 +; LA64-NEXT: beqz $a5, .LBB33_1 +; LA64-NEXT: # %bb.2: +; LA64-NEXT: srl.w $a0, $a4, $a0 +; LA64-NEXT: ret + %1 = atomicrmw add ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { +; LA32-LABEL: atomicrmw_add_i32_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: .LBB34_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: add.w $a3, $a2, $a1 +; LA32-NEXT: sc.w $a3, $a0, 0 +; LA32-NEXT: beqz $a3, .LBB34_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: move $a0, $a2 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_add_i32_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: amadd_db.w $a2, $a1, $a0 +; LA64-NEXT: move $a0, $a2 +; LA64-NEXT: ret + %1 = atomicrmw add ptr %a, i32 %b monotonic + ret i32 %1 +} + +define i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind { +; LA32-LABEL: atomicrmw_add_i64_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $sp, $sp, -16 +; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill +; LA32-NEXT: move $a3, $zero +; LA32-NEXT: bl %plt(__atomic_fetch_add_8) +; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 16 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_add_i64_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: amadd_db.d $a2, $a1, $a0 +; LA64-NEXT: move $a0, $a2 +; LA64-NEXT: ret + %1 = atomicrmw add ptr %a, i64 %b monotonic + ret i64 %1 +} + +define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { +; LA32-LABEL: atomicrmw_sub_i8_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $a2, $zero, -4 +; LA32-NEXT: and $a2, $a0, $a2 +; LA32-NEXT: slli.w $a0, $a0, 3 +; LA32-NEXT: ori $a3, $zero, 255 +; LA32-NEXT: sll.w $a3, $a3, $a0 +; LA32-NEXT: andi $a1, $a1, 255 +; LA32-NEXT: sll.w $a1, $a1, $a0 +; LA32-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a4, $a2, 0 +; LA32-NEXT: sub.w $a5, $a4, $a1 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: and $a5, $a5, $a3 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: sc.w $a5, $a2, 0 +; LA32-NEXT: beqz $a5, .LBB36_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a4, $a0 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_sub_i8_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: addi.w $a2, $zero, -4 +; LA64-NEXT: and $a2, $a0, $a2 +; LA64-NEXT: slli.d $a0, $a0, 3 +; LA64-NEXT: ori $a3, $zero, 255 +; LA64-NEXT: sll.w $a3, $a3, $a0 +; LA64-NEXT: addi.w $a3, $a3, 0 +; LA64-NEXT: andi $a1, $a1, 255 +; LA64-NEXT: sll.w $a1, $a1, $a0 +; LA64-NEXT: addi.w $a1, $a1, 0 +; LA64-NEXT: .LBB36_1: # =>This Inner Loop Header: Depth=1 +; LA64-NEXT: ll.w $a4, $a2, 0 +; LA64-NEXT: sub.w $a5, $a4, $a1 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: and $a5, $a5, $a3 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: sc.w $a5, $a2, 0 +; LA64-NEXT: beqz $a5, .LBB36_1 +; LA64-NEXT: # %bb.2: +; LA64-NEXT: srl.w $a0, $a4, $a0 +; LA64-NEXT: ret + %1 = atomicrmw sub ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { +; LA32-LABEL: atomicrmw_sub_i16_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $a2, $zero, -4 +; LA32-NEXT: and $a2, $a0, $a2 +; LA32-NEXT: slli.w $a0, $a0, 3 +; LA32-NEXT: lu12i.w $a3, 15 +; LA32-NEXT: ori $a3, $a3, 4095 +; LA32-NEXT: sll.w $a3, $a3, $a0 +; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0 +; LA32-NEXT: sll.w $a1, $a1, $a0 +; LA32-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a4, $a2, 0 +; LA32-NEXT: sub.w $a5, $a4, $a1 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: and $a5, $a5, $a3 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: sc.w $a5, $a2, 0 +; LA32-NEXT: beqz $a5, .LBB37_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a4, $a0 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_sub_i16_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: addi.w $a2, $zero, -4 +; LA64-NEXT: and $a2, $a0, $a2 +; LA64-NEXT: slli.d $a0, $a0, 3 +; LA64-NEXT: lu12i.w $a3, 15 +; LA64-NEXT: ori $a3, $a3, 4095 +; LA64-NEXT: sll.w $a3, $a3, $a0 +; LA64-NEXT: addi.w $a3, $a3, 0 +; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0 +; LA64-NEXT: sll.w $a1, $a1, $a0 +; LA64-NEXT: addi.w $a1, $a1, 0 +; LA64-NEXT: .LBB37_1: # =>This Inner Loop Header: Depth=1 +; LA64-NEXT: ll.w $a4, $a2, 0 +; LA64-NEXT: sub.w $a5, $a4, $a1 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: and $a5, $a5, $a3 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: sc.w $a5, $a2, 0 +; LA64-NEXT: beqz $a5, .LBB37_1 +; LA64-NEXT: # %bb.2: +; LA64-NEXT: srl.w $a0, $a4, $a0 +; LA64-NEXT: ret + %1 = atomicrmw sub ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { +; LA32-LABEL: atomicrmw_sub_i32_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: .LBB38_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: sub.w $a3, $a2, $a1 +; LA32-NEXT: sc.w $a3, $a0, 0 +; LA32-NEXT: beqz $a3, .LBB38_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: move $a0, $a2 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_sub_i32_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: sub.w $a2, $zero, $a1 +; LA64-NEXT: amadd_db.w $a1, $a2, $a0 +; LA64-NEXT: move $a0, $a1 +; LA64-NEXT: ret + %1 = atomicrmw sub ptr %a, i32 %b monotonic + ret i32 %1 +} + +define i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind { +; LA32-LABEL: atomicrmw_sub_i64_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $sp, $sp, -16 +; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill +; LA32-NEXT: move $a3, $zero +; LA32-NEXT: bl %plt(__atomic_fetch_sub_8) +; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 16 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_sub_i64_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: sub.d $a2, $zero, $a1 +; LA64-NEXT: amadd_db.d $a1, $a2, $a0 +; LA64-NEXT: move $a0, $a1 +; LA64-NEXT: ret + %1 = atomicrmw sub ptr %a, i64 %b monotonic + ret i64 %1 +} + +define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { +; LA32-LABEL: atomicrmw_nand_i8_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $a2, $zero, -4 +; LA32-NEXT: and $a2, $a0, $a2 +; LA32-NEXT: slli.w $a0, $a0, 3 +; LA32-NEXT: ori $a3, $zero, 255 +; LA32-NEXT: sll.w $a3, $a3, $a0 +; LA32-NEXT: andi $a1, $a1, 255 +; LA32-NEXT: sll.w $a1, $a1, $a0 +; LA32-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a4, $a2, 0 +; LA32-NEXT: and $a5, $a4, $a1 +; LA32-NEXT: nor $a5, $a5, $zero +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: and $a5, $a5, $a3 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: sc.w $a5, $a2, 0 +; LA32-NEXT: beqz $a5, .LBB40_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a4, $a0 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_nand_i8_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: addi.w $a2, $zero, -4 +; LA64-NEXT: and $a2, $a0, $a2 +; LA64-NEXT: slli.d $a0, $a0, 3 +; LA64-NEXT: ori $a3, $zero, 255 +; LA64-NEXT: sll.w $a3, $a3, $a0 +; LA64-NEXT: addi.w $a3, $a3, 0 +; LA64-NEXT: andi $a1, $a1, 255 +; LA64-NEXT: sll.w $a1, $a1, $a0 +; LA64-NEXT: addi.w $a1, $a1, 0 +; LA64-NEXT: .LBB40_1: # =>This Inner Loop Header: Depth=1 +; LA64-NEXT: ll.w $a4, $a2, 0 +; LA64-NEXT: and $a5, $a4, $a1 +; LA64-NEXT: nor $a5, $a5, $zero +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: and $a5, $a5, $a3 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: sc.w $a5, $a2, 0 +; LA64-NEXT: beqz $a5, .LBB40_1 +; LA64-NEXT: # %bb.2: +; LA64-NEXT: srl.w $a0, $a4, $a0 +; LA64-NEXT: ret + %1 = atomicrmw nand ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { +; LA32-LABEL: atomicrmw_nand_i16_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $a2, $zero, -4 +; LA32-NEXT: and $a2, $a0, $a2 +; LA32-NEXT: slli.w $a0, $a0, 3 +; LA32-NEXT: lu12i.w $a3, 15 +; LA32-NEXT: ori $a3, $a3, 4095 +; LA32-NEXT: sll.w $a3, $a3, $a0 +; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0 +; LA32-NEXT: sll.w $a1, $a1, $a0 +; LA32-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a4, $a2, 0 +; LA32-NEXT: and $a5, $a4, $a1 +; LA32-NEXT: nor $a5, $a5, $zero +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: and $a5, $a5, $a3 +; LA32-NEXT: xor $a5, $a4, $a5 +; LA32-NEXT: sc.w $a5, $a2, 0 +; LA32-NEXT: beqz $a5, .LBB41_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a4, $a0 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_nand_i16_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: addi.w $a2, $zero, -4 +; LA64-NEXT: and $a2, $a0, $a2 +; LA64-NEXT: slli.d $a0, $a0, 3 +; LA64-NEXT: lu12i.w $a3, 15 +; LA64-NEXT: ori $a3, $a3, 4095 +; LA64-NEXT: sll.w $a3, $a3, $a0 +; LA64-NEXT: addi.w $a3, $a3, 0 +; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0 +; LA64-NEXT: sll.w $a1, $a1, $a0 +; LA64-NEXT: addi.w $a1, $a1, 0 +; LA64-NEXT: .LBB41_1: # =>This Inner Loop Header: Depth=1 +; LA64-NEXT: ll.w $a4, $a2, 0 +; LA64-NEXT: and $a5, $a4, $a1 +; LA64-NEXT: nor $a5, $a5, $zero +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: and $a5, $a5, $a3 +; LA64-NEXT: xor $a5, $a4, $a5 +; LA64-NEXT: sc.w $a5, $a2, 0 +; LA64-NEXT: beqz $a5, .LBB41_1 +; LA64-NEXT: # %bb.2: +; LA64-NEXT: srl.w $a0, $a4, $a0 +; LA64-NEXT: ret + %1 = atomicrmw nand ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { +; LA32-LABEL: atomicrmw_nand_i32_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: and $a3, $a2, $a1 +; LA32-NEXT: nor $a3, $a3, $zero +; LA32-NEXT: sc.w $a3, $a0, 0 +; LA32-NEXT: beqz $a3, .LBB42_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: move $a0, $a2 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_nand_i32_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: .LBB42_1: # =>This Inner Loop Header: Depth=1 +; LA64-NEXT: ll.w $a2, $a0, 0 +; LA64-NEXT: and $a3, $a2, $a1 +; LA64-NEXT: nor $a3, $a3, $zero +; LA64-NEXT: sc.w $a3, $a0, 0 +; LA64-NEXT: beqz $a3, .LBB42_1 +; LA64-NEXT: # %bb.2: +; LA64-NEXT: move $a0, $a2 +; LA64-NEXT: ret + %1 = atomicrmw nand ptr %a, i32 %b monotonic + ret i32 %1 +} + +define i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind { +; LA32-LABEL: atomicrmw_nand_i64_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $sp, $sp, -16 +; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill +; LA32-NEXT: move $a3, $zero +; LA32-NEXT: bl %plt(__atomic_fetch_nand_8) +; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 16 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_nand_i64_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: .LBB43_1: # =>This Inner Loop Header: Depth=1 +; LA64-NEXT: ll.d $a2, $a0, 0 +; LA64-NEXT: and $a3, $a2, $a1 +; LA64-NEXT: nor $a3, $a3, $zero +; LA64-NEXT: sc.d $a3, $a0, 0 +; LA64-NEXT: beqz $a3, .LBB43_1 +; LA64-NEXT: # %bb.2: +; LA64-NEXT: move $a0, $a2 +; LA64-NEXT: ret + %1 = atomicrmw nand ptr %a, i64 %b monotonic + ret i64 %1 +} + +define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { +; LA32-LABEL: atomicrmw_and_i8_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: slli.w $a2, $a0, 3 +; LA32-NEXT: ori $a3, $zero, 255 +; LA32-NEXT: sll.w $a3, $a3, $a2 +; LA32-NEXT: andi $a1, $a1, 255 +; LA32-NEXT: sll.w $a1, $a1, $a2 +; LA32-NEXT: orn $a1, $a1, $a3 +; LA32-NEXT: addi.w $a3, $zero, -4 +; LA32-NEXT: and $a0, $a0, $a3 +; LA32-NEXT: .LBB44_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a3, $a0, 0 +; LA32-NEXT: and $a4, $a3, $a1 +; LA32-NEXT: sc.w $a4, $a0, 0 +; LA32-NEXT: beqz $a4, .LBB44_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a3, $a2 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_and_i8_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: slli.d $a2, $a0, 3 +; LA64-NEXT: ori $a3, $zero, 255 +; LA64-NEXT: sll.w $a3, $a3, $a2 +; LA64-NEXT: andi $a1, $a1, 255 +; LA64-NEXT: sll.w $a1, $a1, $a2 +; LA64-NEXT: orn $a1, $a1, $a3 +; LA64-NEXT: addi.w $a3, $zero, -4 +; LA64-NEXT: and $a0, $a0, $a3 +; LA64-NEXT: amand_db.w $a3, $a1, $a0 +; LA64-NEXT: srl.w $a0, $a3, $a2 +; LA64-NEXT: ret + %1 = atomicrmw and ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { +; LA32-LABEL: atomicrmw_and_i16_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: lu12i.w $a2, 15 +; LA32-NEXT: ori $a2, $a2, 4095 +; LA32-NEXT: slli.w $a3, $a0, 3 +; LA32-NEXT: sll.w $a2, $a2, $a3 +; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0 +; LA32-NEXT: sll.w $a1, $a1, $a3 +; LA32-NEXT: orn $a1, $a1, $a2 +; LA32-NEXT: addi.w $a2, $zero, -4 +; LA32-NEXT: and $a0, $a0, $a2 +; LA32-NEXT: .LBB45_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: and $a4, $a2, $a1 +; LA32-NEXT: sc.w $a4, $a0, 0 +; LA32-NEXT: beqz $a4, .LBB45_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a2, $a3 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_and_i16_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: lu12i.w $a2, 15 +; LA64-NEXT: ori $a2, $a2, 4095 +; LA64-NEXT: slli.d $a3, $a0, 3 +; LA64-NEXT: sll.w $a2, $a2, $a3 +; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0 +; LA64-NEXT: sll.w $a1, $a1, $a3 +; LA64-NEXT: orn $a1, $a1, $a2 +; LA64-NEXT: addi.w $a2, $zero, -4 +; LA64-NEXT: and $a0, $a0, $a2 +; LA64-NEXT: amand_db.w $a2, $a1, $a0 +; LA64-NEXT: srl.w $a0, $a2, $a3 +; LA64-NEXT: ret + %1 = atomicrmw and ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { +; LA32-LABEL: atomicrmw_and_i32_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: .LBB46_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: and $a3, $a2, $a1 +; LA32-NEXT: sc.w $a3, $a0, 0 +; LA32-NEXT: beqz $a3, .LBB46_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: move $a0, $a2 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_and_i32_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: amand_db.w $a2, $a1, $a0 +; LA64-NEXT: move $a0, $a2 +; LA64-NEXT: ret + %1 = atomicrmw and ptr %a, i32 %b monotonic + ret i32 %1 +} + +define i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind { +; LA32-LABEL: atomicrmw_and_i64_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $sp, $sp, -16 +; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill +; LA32-NEXT: move $a3, $zero +; LA32-NEXT: bl %plt(__atomic_fetch_and_8) +; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 16 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_and_i64_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: amand_db.d $a2, $a1, $a0 +; LA64-NEXT: move $a0, $a2 +; LA64-NEXT: ret + %1 = atomicrmw and ptr %a, i64 %b monotonic + ret i64 %1 +} + +define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { +; LA32-LABEL: atomicrmw_or_i8_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $a2, $zero, -4 +; LA32-NEXT: and $a2, $a0, $a2 +; LA32-NEXT: slli.w $a0, $a0, 3 +; LA32-NEXT: andi $a1, $a1, 255 +; LA32-NEXT: sll.w $a1, $a1, $a0 +; LA32-NEXT: .LBB48_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a3, $a2, 0 +; LA32-NEXT: or $a4, $a3, $a1 +; LA32-NEXT: sc.w $a4, $a2, 0 +; LA32-NEXT: beqz $a4, .LBB48_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a3, $a0 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_or_i8_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: addi.w $a2, $zero, -4 +; LA64-NEXT: and $a2, $a0, $a2 +; LA64-NEXT: slli.d $a0, $a0, 3 +; LA64-NEXT: andi $a1, $a1, 255 +; LA64-NEXT: sll.w $a1, $a1, $a0 +; LA64-NEXT: amor_db.w $a3, $a1, $a2 +; LA64-NEXT: srl.w $a0, $a3, $a0 +; LA64-NEXT: ret + %1 = atomicrmw or ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { +; LA32-LABEL: atomicrmw_or_i16_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $a2, $zero, -4 +; LA32-NEXT: and $a2, $a0, $a2 +; LA32-NEXT: slli.w $a0, $a0, 3 +; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0 +; LA32-NEXT: sll.w $a1, $a1, $a0 +; LA32-NEXT: .LBB49_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a3, $a2, 0 +; LA32-NEXT: or $a4, $a3, $a1 +; LA32-NEXT: sc.w $a4, $a2, 0 +; LA32-NEXT: beqz $a4, .LBB49_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a3, $a0 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_or_i16_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: addi.w $a2, $zero, -4 +; LA64-NEXT: and $a2, $a0, $a2 +; LA64-NEXT: slli.d $a0, $a0, 3 +; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0 +; LA64-NEXT: sll.w $a1, $a1, $a0 +; LA64-NEXT: amor_db.w $a3, $a1, $a2 +; LA64-NEXT: srl.w $a0, $a3, $a0 +; LA64-NEXT: ret + %1 = atomicrmw or ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { +; LA32-LABEL: atomicrmw_or_i32_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: .LBB50_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: or $a3, $a2, $a1 +; LA32-NEXT: sc.w $a3, $a0, 0 +; LA32-NEXT: beqz $a3, .LBB50_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: move $a0, $a2 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_or_i32_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: amor_db.w $a2, $a1, $a0 +; LA64-NEXT: move $a0, $a2 +; LA64-NEXT: ret + %1 = atomicrmw or ptr %a, i32 %b monotonic + ret i32 %1 +} + +define i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind { +; LA32-LABEL: atomicrmw_or_i64_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $sp, $sp, -16 +; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill +; LA32-NEXT: move $a3, $zero +; LA32-NEXT: bl %plt(__atomic_fetch_or_8) +; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 16 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_or_i64_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: amor_db.d $a2, $a1, $a0 +; LA64-NEXT: move $a0, $a2 +; LA64-NEXT: ret + %1 = atomicrmw or ptr %a, i64 %b monotonic + ret i64 %1 +} + +define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { +; LA32-LABEL: atomicrmw_xor_i8_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $a2, $zero, -4 +; LA32-NEXT: and $a2, $a0, $a2 +; LA32-NEXT: slli.w $a0, $a0, 3 +; LA32-NEXT: andi $a1, $a1, 255 +; LA32-NEXT: sll.w $a1, $a1, $a0 +; LA32-NEXT: .LBB52_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a3, $a2, 0 +; LA32-NEXT: xor $a4, $a3, $a1 +; LA32-NEXT: sc.w $a4, $a2, 0 +; LA32-NEXT: beqz $a4, .LBB52_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a3, $a0 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_xor_i8_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: addi.w $a2, $zero, -4 +; LA64-NEXT: and $a2, $a0, $a2 +; LA64-NEXT: slli.d $a0, $a0, 3 +; LA64-NEXT: andi $a1, $a1, 255 +; LA64-NEXT: sll.w $a1, $a1, $a0 +; LA64-NEXT: amxor_db.w $a3, $a1, $a2 +; LA64-NEXT: srl.w $a0, $a3, $a0 +; LA64-NEXT: ret + %1 = atomicrmw xor ptr %a, i8 %b monotonic + ret i8 %1 +} + +define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { +; LA32-LABEL: atomicrmw_xor_i16_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $a2, $zero, -4 +; LA32-NEXT: and $a2, $a0, $a2 +; LA32-NEXT: slli.w $a0, $a0, 3 +; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0 +; LA32-NEXT: sll.w $a1, $a1, $a0 +; LA32-NEXT: .LBB53_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a3, $a2, 0 +; LA32-NEXT: xor $a4, $a3, $a1 +; LA32-NEXT: sc.w $a4, $a2, 0 +; LA32-NEXT: beqz $a4, .LBB53_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: srl.w $a0, $a3, $a0 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_xor_i16_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: addi.w $a2, $zero, -4 +; LA64-NEXT: and $a2, $a0, $a2 +; LA64-NEXT: slli.d $a0, $a0, 3 +; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0 +; LA64-NEXT: sll.w $a1, $a1, $a0 +; LA64-NEXT: amxor_db.w $a3, $a1, $a2 +; LA64-NEXT: srl.w $a0, $a3, $a0 +; LA64-NEXT: ret + %1 = atomicrmw xor ptr %a, i16 %b monotonic + ret i16 %1 +} + +define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { +; LA32-LABEL: atomicrmw_xor_i32_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: .LBB54_1: # =>This Inner Loop Header: Depth=1 +; LA32-NEXT: ll.w $a2, $a0, 0 +; LA32-NEXT: xor $a3, $a2, $a1 +; LA32-NEXT: sc.w $a3, $a0, 0 +; LA32-NEXT: beqz $a3, .LBB54_1 +; LA32-NEXT: # %bb.2: +; LA32-NEXT: move $a0, $a2 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_xor_i32_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: amxor_db.w $a2, $a1, $a0 +; LA64-NEXT: move $a0, $a2 +; LA64-NEXT: ret + %1 = atomicrmw xor ptr %a, i32 %b monotonic + ret i32 %1 +} + +define i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind { +; LA32-LABEL: atomicrmw_xor_i64_monotonic: +; LA32: # %bb.0: +; LA32-NEXT: addi.w $sp, $sp, -16 +; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill +; LA32-NEXT: move $a3, $zero +; LA32-NEXT: bl %plt(__atomic_fetch_xor_8) +; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload +; LA32-NEXT: addi.w $sp, $sp, 16 +; LA32-NEXT: ret +; +; LA64-LABEL: atomicrmw_xor_i64_monotonic: +; LA64: # %bb.0: +; LA64-NEXT: amxor_db.d $a2, $a1, $a0 +; LA64-NEXT: move $a0, $a2 +; LA64-NEXT: ret + %1 = atomicrmw xor ptr %a, i64 %b monotonic + ret i64 %1 +} diff --git a/llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll b/llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll --- a/llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll +++ b/llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll @@ -444,16 +444,16 @@ define <8 x i16> @shuffle_vector_halfword_0_4(<8 x i16> %a) { ; CHECK-64-LABEL: shuffle_vector_halfword_0_4: ; CHECK-64: # %bb.0: # %entry -; CHECK-64-NEXT: ld 3, L..C0(2) -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: ld 3, L..C0(2) # %const.0 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: shuffle_vector_halfword_0_4: ; CHECK-32: # %bb.0: # %entry -; CHECK-32-NEXT: lwz 3, L..C0(2) -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lwz 3, L..C0(2) # %const.0 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> @@ -493,16 +493,16 @@ define <8 x i16> @shuffle_vector_halfword_3_4(<8 x i16> %a) { ; CHECK-64-LABEL: shuffle_vector_halfword_3_4: ; CHECK-64: # %bb.0: # %entry -; CHECK-64-NEXT: ld 3, L..C1(2) -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: ld 3, L..C1(2) # %const.0 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: shuffle_vector_halfword_3_4: ; CHECK-32: # %bb.0: # %entry -; CHECK-32-NEXT: lwz 3, L..C1(2) -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lwz 3, L..C1(2) # %const.0 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> @@ -542,16 +542,16 @@ define <8 x i16> @shuffle_vector_halfword_6_4(<8 x i16> %a) { ; CHECK-64-LABEL: shuffle_vector_halfword_6_4: ; CHECK-64: # %bb.0: # %entry -; CHECK-64-NEXT: ld 3, L..C2(2) -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: ld 3, L..C2(2) # %const.0 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: shuffle_vector_halfword_6_4: ; CHECK-32: # %bb.0: # %entry -; CHECK-32-NEXT: lwz 3, L..C2(2) -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lwz 3, L..C2(2) # %const.0 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> @@ -561,16 +561,16 @@ define <8 x i16> @shuffle_vector_halfword_7_4(<8 x i16> %a) { ; CHECK-64-LABEL: shuffle_vector_halfword_7_4: ; CHECK-64: # %bb.0: # %entry -; CHECK-64-NEXT: ld 3, L..C3(2) -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: ld 3, L..C3(2) # %const.0 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: shuffle_vector_halfword_7_4: ; CHECK-32: # %bb.0: # %entry -; CHECK-32-NEXT: lwz 3, L..C3(2) -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lwz 3, L..C3(2) # %const.0 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> @@ -1460,16 +1460,16 @@ define <16 x i8> @shuffle_vector_byte_1_8(<16 x i8> %a) { ; CHECK-64-LABEL: shuffle_vector_byte_1_8: ; CHECK-64: # %bb.0: # %entry -; CHECK-64-NEXT: ld 3, L..C4(2) -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: ld 3, L..C4(2) # %const.0 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: shuffle_vector_byte_1_8: ; CHECK-32: # %bb.0: # %entry -; CHECK-32-NEXT: lwz 3, L..C4(2) -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lwz 3, L..C4(2) # %const.0 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1479,16 +1479,16 @@ define <16 x i8> @shuffle_vector_byte_2_8(<16 x i8> %a) { ; CHECK-64-LABEL: shuffle_vector_byte_2_8: ; CHECK-64: # %bb.0: # %entry -; CHECK-64-NEXT: ld 3, L..C5(2) -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: ld 3, L..C5(2) # %const.0 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: shuffle_vector_byte_2_8: ; CHECK-32: # %bb.0: # %entry -; CHECK-32-NEXT: lwz 3, L..C5(2) -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lwz 3, L..C5(2) # %const.0 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1528,16 +1528,16 @@ define <16 x i8> @shuffle_vector_byte_5_8(<16 x i8> %a) { ; CHECK-64-LABEL: shuffle_vector_byte_5_8: ; CHECK-64: # %bb.0: # %entry -; CHECK-64-NEXT: ld 3, L..C6(2) -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: ld 3, L..C6(2) # %const.0 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: shuffle_vector_byte_5_8: ; CHECK-32: # %bb.0: # %entry -; CHECK-32-NEXT: lwz 3, L..C6(2) -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lwz 3, L..C6(2) # %const.0 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1547,16 +1547,16 @@ define <16 x i8> @shuffle_vector_byte_6_8(<16 x i8> %a) { ; CHECK-64-LABEL: shuffle_vector_byte_6_8: ; CHECK-64: # %bb.0: # %entry -; CHECK-64-NEXT: ld 3, L..C7(2) -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: ld 3, L..C7(2) # %const.0 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: shuffle_vector_byte_6_8: ; CHECK-32: # %bb.0: # %entry -; CHECK-32-NEXT: lwz 3, L..C7(2) -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lwz 3, L..C7(2) # %const.0 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1566,16 +1566,16 @@ define <16 x i8> @shuffle_vector_byte_7_8(<16 x i8> %a) { ; CHECK-64-LABEL: shuffle_vector_byte_7_8: ; CHECK-64: # %bb.0: # %entry -; CHECK-64-NEXT: ld 3, L..C8(2) -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: ld 3, L..C8(2) # %const.0 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: shuffle_vector_byte_7_8: ; CHECK-32: # %bb.0: # %entry -; CHECK-32-NEXT: lwz 3, L..C8(2) -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lwz 3, L..C8(2) # %const.0 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1630,16 +1630,16 @@ define <16 x i8> @shuffle_vector_byte_11_8(<16 x i8> %a) { ; CHECK-64-LABEL: shuffle_vector_byte_11_8: ; CHECK-64: # %bb.0: # %entry -; CHECK-64-NEXT: ld 3, L..C9(2) -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: ld 3, L..C9(2) # %const.0 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: shuffle_vector_byte_11_8: ; CHECK-32: # %bb.0: # %entry -; CHECK-32-NEXT: lwz 3, L..C9(2) -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lwz 3, L..C9(2) # %const.0 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1649,16 +1649,16 @@ define <16 x i8> @shuffle_vector_byte_12_8(<16 x i8> %a) { ; CHECK-64-LABEL: shuffle_vector_byte_12_8: ; CHECK-64: # %bb.0: # %entry -; CHECK-64-NEXT: ld 3, L..C10(2) -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: ld 3, L..C10(2) # %const.0 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: shuffle_vector_byte_12_8: ; CHECK-32: # %bb.0: # %entry -; CHECK-32-NEXT: lwz 3, L..C10(2) -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lwz 3, L..C10(2) # %const.0 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1698,16 +1698,16 @@ define <16 x i8> @shuffle_vector_byte_15_8(<16 x i8> %a) { ; CHECK-64-LABEL: shuffle_vector_byte_15_8: ; CHECK-64: # %bb.0: # %entry -; CHECK-64-NEXT: ld 3, L..C11(2) -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: ld 3, L..C11(2) # %const.0 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: shuffle_vector_byte_15_8: ; CHECK-32: # %bb.0: # %entry -; CHECK-32-NEXT: lwz 3, L..C11(2) -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lwz 3, L..C11(2) # %const.0 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> diff --git a/llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll b/llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll --- a/llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll +++ b/llvm/test/CodeGen/PowerPC/aix-p9-xxinsertw-xxextractuw.ll @@ -1447,15 +1447,15 @@ ; CHECK-64-LABEL: testSameVecEl0LE: ; CHECK-64: # %bb.0: # %entry ; CHECK-64-NEXT: ld 3, L..C0(2) # %const.0 -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: testSameVecEl0LE: ; CHECK-32: # %bb.0: # %entry ; CHECK-32-NEXT: lwz 3, L..C0(2) # %const.0 -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> @@ -1465,15 +1465,15 @@ ; CHECK-64-LABEL: testSameVecEl1LE: ; CHECK-64: # %bb.0: # %entry ; CHECK-64-NEXT: ld 3, L..C1(2) # %const.0 -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: testSameVecEl1LE: ; CHECK-32: # %bb.0: # %entry ; CHECK-32-NEXT: lwz 3, L..C1(2) # %const.0 -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> @@ -1483,15 +1483,15 @@ ; CHECK-64-LABEL: testSameVecEl3LE: ; CHECK-64: # %bb.0: # %entry ; CHECK-64-NEXT: ld 3, L..C2(2) # %const.0 -; CHECK-64-NEXT: lxv 35, 0(3) -; CHECK-64-NEXT: vperm 2, 2, 2, 3 +; CHECK-64-NEXT: lxv 0, 0(3) +; CHECK-64-NEXT: xxperm 34, 34, 0 ; CHECK-64-NEXT: blr ; ; CHECK-32-LABEL: testSameVecEl3LE: ; CHECK-32: # %bb.0: # %entry ; CHECK-32-NEXT: lwz 3, L..C2(2) # %const.0 -; CHECK-32-NEXT: lxv 35, 0(3) -; CHECK-32-NEXT: vperm 2, 2, 2, 3 +; CHECK-32-NEXT: lxv 0, 0(3) +; CHECK-32-NEXT: xxperm 34, 34, 0 ; CHECK-32-NEXT: blr entry: %vecins = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll --- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll +++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll @@ -928,8 +928,8 @@ ; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l -; P9BE-NEXT: lxv v3, 0(r3) -; P9BE-NEXT: vperm v2, v2, v2, v3 +; P9BE-NEXT: lxv vs0, 0(r3) +; P9BE-NEXT: xxperm v2, v2, vs0 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffMemConsDi: @@ -1028,8 +1028,8 @@ ; P9BE-NEXT: lxvx v2, r3, r4 ; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l -; P9BE-NEXT: lxv v3, 0(r3) -; P9BE-NEXT: vperm v2, v2, v2, v3 +; P9BE-NEXT: lxv vs0, 0(r3) +; P9BE-NEXT: xxperm v2, v2, vs0 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffMemVarDi: @@ -1040,8 +1040,8 @@ ; P9LE-NEXT: lxvx v2, r3, r4 ; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l -; P9LE-NEXT: lxv v3, 0(r3) -; P9LE-NEXT: vperm v2, v2, v2, v3 +; P9LE-NEXT: lxv vs0, 0(r3) +; P9LE-NEXT: xxperm v2, v2, vs0 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffMemVarDi: @@ -1058,15 +1058,14 @@ ; ; P8LE-LABEL: fromDiffMemVarDi: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: sldi r4, r4, 2 ; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha +; P8LE-NEXT: sldi r4, r4, 2 +; P8LE-NEXT: addi r5, r5, .LCPI9_0@toc@l ; P8LE-NEXT: add r3, r3, r4 -; P8LE-NEXT: addi r4, r5, .LCPI9_0@toc@l +; P8LE-NEXT: lxvd2x vs0, 0, r5 ; P8LE-NEXT: addi r3, r3, -12 -; P8LE-NEXT: lxvd2x vs1, 0, r4 -; P8LE-NEXT: lxvd2x vs0, 0, r3 -; P8LE-NEXT: xxswapd v3, vs1 -; P8LE-NEXT: xxswapd v2, vs0 +; P8LE-NEXT: lxvd2x v2, 0, r3 +; P8LE-NEXT: xxswapd v3, vs0 ; P8LE-NEXT: vperm v2, v2, v2, v3 ; P8LE-NEXT: blr entry: @@ -1448,22 +1447,22 @@ define <4 x i32> @fromDiffMemConsDConvftoi(ptr nocapture readonly %ptr) { ; P9BE-LABEL: fromDiffMemConsDConvftoi: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: lxv v2, 0(r3) +; P9BE-NEXT: lxv vs0, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l -; P9BE-NEXT: lxv v3, 0(r3) -; P9BE-NEXT: vperm v2, v2, v2, v3 -; P9BE-NEXT: xvcvspsxws v2, v2 +; P9BE-NEXT: lxv vs1, 0(r3) +; P9BE-NEXT: xxperm vs0, vs0, vs1 +; P9BE-NEXT: xvcvspsxws v2, vs0 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffMemConsDConvftoi: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: lxv v2, 0(r3) +; P9LE-NEXT: lxv vs0, 0(r3) ; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l -; P9LE-NEXT: lxv v3, 0(r3) -; P9LE-NEXT: vperm v2, v2, v2, v3 -; P9LE-NEXT: xvcvspsxws v2, v2 +; P9LE-NEXT: lxv vs1, 0(r3) +; P9LE-NEXT: xxperm vs0, vs0, vs1 +; P9LE-NEXT: xvcvspsxws v2, vs0 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffMemConsDConvftoi: @@ -1479,11 +1478,10 @@ ; P8LE-LABEL: fromDiffMemConsDConvftoi: ; P8LE: # %bb.0: # %entry ; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha -; P8LE-NEXT: lxvd2x vs0, 0, r3 +; P8LE-NEXT: lxvd2x v2, 0, r3 ; P8LE-NEXT: addi r4, r4, .LCPI18_0@toc@l -; P8LE-NEXT: lxvd2x vs1, 0, r4 -; P8LE-NEXT: xxswapd v2, vs0 -; P8LE-NEXT: xxswapd v3, vs1 +; P8LE-NEXT: lxvd2x vs0, 0, r4 +; P8LE-NEXT: xxswapd v3, vs0 ; P8LE-NEXT: vperm v2, v2, v2, v3 ; P8LE-NEXT: xvcvspsxws v2, v2 ; P8LE-NEXT: blr @@ -2450,8 +2448,8 @@ ; P9BE-NEXT: lxv v2, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l -; P9BE-NEXT: lxv v3, 0(r3) -; P9BE-NEXT: vperm v2, v2, v2, v3 +; P9BE-NEXT: lxv vs0, 0(r3) +; P9BE-NEXT: xxperm v2, v2, vs0 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffMemConsDui: @@ -2550,8 +2548,8 @@ ; P9BE-NEXT: lxvx v2, r3, r4 ; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l -; P9BE-NEXT: lxv v3, 0(r3) -; P9BE-NEXT: vperm v2, v2, v2, v3 +; P9BE-NEXT: lxv vs0, 0(r3) +; P9BE-NEXT: xxperm v2, v2, vs0 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffMemVarDui: @@ -2562,8 +2560,8 @@ ; P9LE-NEXT: lxvx v2, r3, r4 ; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l -; P9LE-NEXT: lxv v3, 0(r3) -; P9LE-NEXT: vperm v2, v2, v2, v3 +; P9LE-NEXT: lxv vs0, 0(r3) +; P9LE-NEXT: xxperm v2, v2, vs0 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffMemVarDui: @@ -2580,15 +2578,14 @@ ; ; P8LE-LABEL: fromDiffMemVarDui: ; P8LE: # %bb.0: # %entry -; P8LE-NEXT: sldi r4, r4, 2 ; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha +; P8LE-NEXT: sldi r4, r4, 2 +; P8LE-NEXT: addi r5, r5, .LCPI41_0@toc@l ; P8LE-NEXT: add r3, r3, r4 -; P8LE-NEXT: addi r4, r5, .LCPI41_0@toc@l +; P8LE-NEXT: lxvd2x vs0, 0, r5 ; P8LE-NEXT: addi r3, r3, -12 -; P8LE-NEXT: lxvd2x vs1, 0, r4 -; P8LE-NEXT: lxvd2x vs0, 0, r3 -; P8LE-NEXT: xxswapd v3, vs1 -; P8LE-NEXT: xxswapd v2, vs0 +; P8LE-NEXT: lxvd2x v2, 0, r3 +; P8LE-NEXT: xxswapd v3, vs0 ; P8LE-NEXT: vperm v2, v2, v2, v3 ; P8LE-NEXT: blr entry: @@ -2970,22 +2967,22 @@ define <4 x i32> @fromDiffMemConsDConvftoui(ptr nocapture readonly %ptr) { ; P9BE-LABEL: fromDiffMemConsDConvftoui: ; P9BE: # %bb.0: # %entry -; P9BE-NEXT: lxv v2, 0(r3) +; P9BE-NEXT: lxv vs0, 0(r3) ; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l -; P9BE-NEXT: lxv v3, 0(r3) -; P9BE-NEXT: vperm v2, v2, v2, v3 -; P9BE-NEXT: xvcvspuxws v2, v2 +; P9BE-NEXT: lxv vs1, 0(r3) +; P9BE-NEXT: xxperm vs0, vs0, vs1 +; P9BE-NEXT: xvcvspuxws v2, vs0 ; P9BE-NEXT: blr ; ; P9LE-LABEL: fromDiffMemConsDConvftoui: ; P9LE: # %bb.0: # %entry -; P9LE-NEXT: lxv v2, 0(r3) +; P9LE-NEXT: lxv vs0, 0(r3) ; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha ; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l -; P9LE-NEXT: lxv v3, 0(r3) -; P9LE-NEXT: vperm v2, v2, v2, v3 -; P9LE-NEXT: xvcvspuxws v2, v2 +; P9LE-NEXT: lxv vs1, 0(r3) +; P9LE-NEXT: xxperm vs0, vs0, vs1 +; P9LE-NEXT: xvcvspuxws v2, vs0 ; P9LE-NEXT: blr ; ; P8BE-LABEL: fromDiffMemConsDConvftoui: @@ -3001,11 +2998,10 @@ ; P8LE-LABEL: fromDiffMemConsDConvftoui: ; P8LE: # %bb.0: # %entry ; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha -; P8LE-NEXT: lxvd2x vs0, 0, r3 +; P8LE-NEXT: lxvd2x v2, 0, r3 ; P8LE-NEXT: addi r4, r4, .LCPI50_0@toc@l -; P8LE-NEXT: lxvd2x vs1, 0, r4 -; P8LE-NEXT: xxswapd v2, vs0 -; P8LE-NEXT: xxswapd v3, vs1 +; P8LE-NEXT: lxvd2x vs0, 0, r4 +; P8LE-NEXT: xxswapd v3, vs0 ; P8LE-NEXT: vperm v2, v2, v2, v3 ; P8LE-NEXT: xvcvspuxws v2, v2 ; P8LE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll --- a/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll +++ b/llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll @@ -491,10 +491,10 @@ ; CHECK-P9-BE: # %bb.0: # %entry ; CHECK-P9-BE-NEXT: lxsd v2, 0(r3) ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI12_0@toc@ha -; CHECK-P9-BE-NEXT: xxlxor v4, v4, v4 +; CHECK-P9-BE-NEXT: xxlxor vs0, vs0, vs0 ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI12_0@toc@l -; CHECK-P9-BE-NEXT: lxv v3, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v4, v2, v3 +; CHECK-P9-BE-NEXT: lxv vs1, 0(r3) +; CHECK-P9-BE-NEXT: xxperm v2, vs0, vs1 ; CHECK-P9-BE-NEXT: blr ; ; CHECK-NOVSX-LABEL: testmrglb3: @@ -748,11 +748,12 @@ ; CHECK-P9-BE: # %bb.0: # %entry ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI15_0@toc@l -; CHECK-P9-BE-NEXT: lxv v3, 0(r3) +; CHECK-P9-BE-NEXT: lxv vs1, 0(r3) ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI15_1@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI15_1@toc@l -; CHECK-P9-BE-NEXT: lxv v4, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v2, v4, v3 +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) +; CHECK-P9-BE-NEXT: xxperm vs0, v2, vs1 +; CHECK-P9-BE-NEXT: xxlor v2, vs0, vs0 ; CHECK-P9-BE-NEXT: blr ; ; CHECK-NOVSX-LABEL: replace_undefs_in_splat: diff --git a/llvm/test/CodeGen/PowerPC/extract-and-store.ll b/llvm/test/CodeGen/PowerPC/extract-and-store.ll --- a/llvm/test/CodeGen/PowerPC/extract-and-store.ll +++ b/llvm/test/CodeGen/PowerPC/extract-and-store.ll @@ -600,29 +600,29 @@ ; CHECK-P9-LABEL: test_stores_exceed_vec_size: ; CHECK-P9: # %bb.0: # %entry ; CHECK-P9-NEXT: addis r3, r2, .LCPI16_0@toc@ha -; CHECK-P9-NEXT: xxsldwi vs0, vs34, vs34, 1 +; CHECK-P9-NEXT: xxsldwi vs1, vs34, vs34, 1 ; CHECK-P9-NEXT: addi r3, r3, .LCPI16_0@toc@l -; CHECK-P9-NEXT: lxv vs35, 0(r3) -; CHECK-P9-NEXT: li r3, 16 -; CHECK-P9-NEXT: stfiwx f0, r5, r3 +; CHECK-P9-NEXT: lxv vs0, 0(r3) ; CHECK-P9-NEXT: li r3, 20 ; CHECK-P9-NEXT: stxsiwx vs34, r5, r3 -; CHECK-P9-NEXT: vperm v3, v2, v2, v3 -; CHECK-P9-NEXT: stxv vs35, 0(r5) +; CHECK-P9-NEXT: li r3, 16 +; CHECK-P9-NEXT: stfiwx f1, r5, r3 +; CHECK-P9-NEXT: xxperm vs34, vs34, vs0 +; CHECK-P9-NEXT: stxv vs34, 0(r5) ; CHECK-P9-NEXT: blr ; ; CHECK-P9-BE-LABEL: test_stores_exceed_vec_size: ; CHECK-P9-BE: # %bb.0: # %entry ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha -; CHECK-P9-BE-NEXT: xxsldwi vs0, vs34, vs34, 1 +; CHECK-P9-BE-NEXT: xxsldwi vs1, vs34, vs34, 1 ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI16_0@toc@l -; CHECK-P9-BE-NEXT: lxv vs35, 0(r3) +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) ; CHECK-P9-BE-NEXT: li r3, 16 ; CHECK-P9-BE-NEXT: stxsiwx vs34, r5, r3 ; CHECK-P9-BE-NEXT: li r3, 20 -; CHECK-P9-BE-NEXT: stfiwx f0, r5, r3 -; CHECK-P9-BE-NEXT: vperm v3, v2, v2, v3 -; CHECK-P9-BE-NEXT: stxv vs35, 0(r5) +; CHECK-P9-BE-NEXT: stfiwx f1, r5, r3 +; CHECK-P9-BE-NEXT: xxperm vs34, vs34, vs0 +; CHECK-P9-BE-NEXT: stxv vs34, 0(r5) ; CHECK-P9-BE-NEXT: blr entry: %vecext = extractelement <4 x i32> %a, i32 2 diff --git a/llvm/test/CodeGen/PowerPC/fp-classify.ll b/llvm/test/CodeGen/PowerPC/fp-classify.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fp-classify.ll @@ -0,0 +1,279 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=P8 +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s \ +; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=P9 + +define zeroext i1 @abs_isinff(float %x) { +; P8-LABEL: abs_isinff: +; P8: # %bb.0: # %entry +; P8-NEXT: xsabsdp 0, 1 +; P8-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; P8-NEXT: li 4, 1 +; P8-NEXT: lfs 1, .LCPI0_0@toc@l(3) +; P8-NEXT: li 3, 0 +; P8-NEXT: fcmpu 0, 0, 1 +; P8-NEXT: iseleq 3, 4, 3 +; P8-NEXT: blr +; +; P9-LABEL: abs_isinff: +; P9: # %bb.0: # %entry +; P9-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; P9-NEXT: xsabsdp 0, 1 +; P9-NEXT: li 4, 1 +; P9-NEXT: lfs 1, .LCPI0_0@toc@l(3) +; P9-NEXT: li 3, 0 +; P9-NEXT: fcmpu 0, 0, 1 +; P9-NEXT: iseleq 3, 4, 3 +; P9-NEXT: blr +entry: + %0 = tail call float @llvm.fabs.f32(float %x) + %cmpinf = fcmp oeq float %0, 0x7FF0000000000000 + ret i1 %cmpinf +} + +define zeroext i1 @abs_isinf(double %x) { +; P8-LABEL: abs_isinf: +; P8: # %bb.0: # %entry +; P8-NEXT: xsabsdp 0, 1 +; P8-NEXT: addis 3, 2, .LCPI1_0@toc@ha +; P8-NEXT: li 4, 1 +; P8-NEXT: lfs 1, .LCPI1_0@toc@l(3) +; P8-NEXT: li 3, 0 +; P8-NEXT: fcmpu 0, 0, 1 +; P8-NEXT: iseleq 3, 4, 3 +; P8-NEXT: blr +; +; P9-LABEL: abs_isinf: +; P9: # %bb.0: # %entry +; P9-NEXT: addis 3, 2, .LCPI1_0@toc@ha +; P9-NEXT: xsabsdp 0, 1 +; P9-NEXT: li 4, 1 +; P9-NEXT: lfs 1, .LCPI1_0@toc@l(3) +; P9-NEXT: li 3, 0 +; P9-NEXT: fcmpu 0, 0, 1 +; P9-NEXT: iseleq 3, 4, 3 +; P9-NEXT: blr +entry: + %0 = tail call double @llvm.fabs.f64(double %x) + %cmpinf = fcmp oeq double %0, 0x7FF0000000000000 + ret i1 %cmpinf +} + +define zeroext i1 @abs_isinfq(fp128 %x) { +; P8-LABEL: abs_isinfq: +; P8: # %bb.0: # %entry +; P8-NEXT: mflr 0 +; P8-NEXT: stdu 1, -48(1) +; P8-NEXT: std 0, 64(1) +; P8-NEXT: .cfi_def_cfa_offset 48 +; P8-NEXT: .cfi_offset lr, 16 +; P8-NEXT: xxswapd 0, 34 +; P8-NEXT: addi 3, 1, 32 +; P8-NEXT: stxvd2x 0, 0, 3 +; P8-NEXT: lbz 4, 47(1) +; P8-NEXT: clrlwi 4, 4, 25 +; P8-NEXT: stb 4, 47(1) +; P8-NEXT: lxvd2x 0, 0, 3 +; P8-NEXT: addis 3, 2, .LCPI2_0@toc@ha +; P8-NEXT: addi 3, 3, .LCPI2_0@toc@l +; P8-NEXT: xxswapd 34, 0 +; P8-NEXT: lxvd2x 0, 0, 3 +; P8-NEXT: xxswapd 35, 0 +; P8-NEXT: bl __eqkf2 +; P8-NEXT: nop +; P8-NEXT: cntlzw 3, 3 +; P8-NEXT: srwi 3, 3, 5 +; P8-NEXT: addi 1, 1, 48 +; P8-NEXT: ld 0, 16(1) +; P8-NEXT: mtlr 0 +; P8-NEXT: blr +; +; P9-LABEL: abs_isinfq: +; P9: # %bb.0: # %entry +; P9-NEXT: addis 3, 2, .LCPI2_0@toc@ha +; P9-NEXT: xsabsqp 2, 2 +; P9-NEXT: li 4, 1 +; P9-NEXT: addi 3, 3, .LCPI2_0@toc@l +; P9-NEXT: lxv 35, 0(3) +; P9-NEXT: li 3, 0 +; P9-NEXT: xscmpuqp 0, 2, 3 +; P9-NEXT: iseleq 3, 4, 3 +; P9-NEXT: blr +entry: + %0 = tail call fp128 @llvm.fabs.f128(fp128 %x) + %cmpinf = fcmp oeq fp128 %0, 0xL00000000000000007FFF000000000000 + ret i1 %cmpinf +} + +define <4 x i1> @abs_isinfv4f32(<4 x float> %x) { +; P8-LABEL: abs_isinfv4f32: +; P8: # %bb.0: # %entry +; P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha +; P8-NEXT: xvabssp 0, 34 +; P8-NEXT: addi 3, 3, .LCPI3_0@toc@l +; P8-NEXT: lxvd2x 1, 0, 3 +; P8-NEXT: xxswapd 1, 1 +; P8-NEXT: xvcmpeqsp 34, 0, 1 +; P8-NEXT: blr +; +; P9-LABEL: abs_isinfv4f32: +; P9: # %bb.0: # %entry +; P9-NEXT: addis 3, 2, .LCPI3_0@toc@ha +; P9-NEXT: xvabssp 0, 34 +; P9-NEXT: addi 3, 3, .LCPI3_0@toc@l +; P9-NEXT: lxv 1, 0(3) +; P9-NEXT: xvcmpeqsp 34, 0, 1 +; P9-NEXT: blr +entry: + %0 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %x) + %cmpinf = fcmp oeq <4 x float> %0, + ret <4 x i1> %cmpinf +} + +define <2 x i1> @abs_isinfv2f64(<2 x double> %x) { +; P8-LABEL: abs_isinfv2f64: +; P8: # %bb.0: # %entry +; P8-NEXT: addis 3, 2, .LCPI4_0@toc@ha +; P8-NEXT: xvabsdp 0, 34 +; P8-NEXT: addi 3, 3, .LCPI4_0@toc@l +; P8-NEXT: lxvd2x 1, 0, 3 +; P8-NEXT: xxswapd 1, 1 +; P8-NEXT: xvcmpeqdp 34, 0, 1 +; P8-NEXT: blr +; +; P9-LABEL: abs_isinfv2f64: +; P9: # %bb.0: # %entry +; P9-NEXT: addis 3, 2, .LCPI4_0@toc@ha +; P9-NEXT: xvabsdp 0, 34 +; P9-NEXT: addi 3, 3, .LCPI4_0@toc@l +; P9-NEXT: lxv 1, 0(3) +; P9-NEXT: xvcmpeqdp 34, 0, 1 +; P9-NEXT: blr +entry: + %0 = tail call <2 x double> @llvm.fabs.v2f64(<2 x double> %x) + %cmpinf = fcmp oeq <2 x double> %0, + ret <2 x i1> %cmpinf +} + +define zeroext i1 @iszerof(float %x) { +; P8-LABEL: iszerof: +; P8: # %bb.0: # %entry +; P8-NEXT: xxlxor 0, 0, 0 +; P8-NEXT: li 3, 0 +; P8-NEXT: li 4, 1 +; P8-NEXT: fcmpu 0, 1, 0 +; P8-NEXT: iseleq 3, 4, 3 +; P8-NEXT: blr +; +; P9-LABEL: iszerof: +; P9: # %bb.0: # %entry +; P9-NEXT: xxlxor 0, 0, 0 +; P9-NEXT: li 3, 0 +; P9-NEXT: li 4, 1 +; P9-NEXT: fcmpu 0, 1, 0 +; P9-NEXT: iseleq 3, 4, 3 +; P9-NEXT: blr +entry: + %cmp = fcmp oeq float %x, 0.000000e+00 + ret i1 %cmp +} + +define zeroext i1 @iszero(double %x) { +; P8-LABEL: iszero: +; P8: # %bb.0: # %entry +; P8-NEXT: xxlxor 0, 0, 0 +; P8-NEXT: li 3, 0 +; P8-NEXT: li 4, 1 +; P8-NEXT: fcmpu 0, 1, 0 +; P8-NEXT: iseleq 3, 4, 3 +; P8-NEXT: blr +; +; P9-LABEL: iszero: +; P9: # %bb.0: # %entry +; P9-NEXT: xxlxor 0, 0, 0 +; P9-NEXT: li 3, 0 +; P9-NEXT: li 4, 1 +; P9-NEXT: fcmpu 0, 1, 0 +; P9-NEXT: iseleq 3, 4, 3 +; P9-NEXT: blr +entry: + %cmp = fcmp oeq double %x, 0.000000e+00 + ret i1 %cmp +} + +define zeroext i1 @iszeroq(fp128 %x) { +; P8-LABEL: iszeroq: +; P8: # %bb.0: # %entry +; P8-NEXT: mflr 0 +; P8-NEXT: stdu 1, -32(1) +; P8-NEXT: std 0, 48(1) +; P8-NEXT: .cfi_def_cfa_offset 32 +; P8-NEXT: .cfi_offset lr, 16 +; P8-NEXT: addis 3, 2, .LCPI7_0@toc@ha +; P8-NEXT: addi 3, 3, .LCPI7_0@toc@l +; P8-NEXT: lxvd2x 0, 0, 3 +; P8-NEXT: xxswapd 35, 0 +; P8-NEXT: bl __eqkf2 +; P8-NEXT: nop +; P8-NEXT: cntlzw 3, 3 +; P8-NEXT: srwi 3, 3, 5 +; P8-NEXT: addi 1, 1, 32 +; P8-NEXT: ld 0, 16(1) +; P8-NEXT: mtlr 0 +; P8-NEXT: blr +; +; P9-LABEL: iszeroq: +; P9: # %bb.0: # %entry +; P9-NEXT: addis 3, 2, .LCPI7_0@toc@ha +; P9-NEXT: li 4, 1 +; P9-NEXT: addi 3, 3, .LCPI7_0@toc@l +; P9-NEXT: lxv 35, 0(3) +; P9-NEXT: li 3, 0 +; P9-NEXT: xscmpuqp 0, 2, 3 +; P9-NEXT: iseleq 3, 4, 3 +; P9-NEXT: blr +entry: + %cmp = fcmp oeq fp128 %x, 0xL00000000000000000000000000000000 + ret i1 %cmp +} + +define <4 x i1> @iszerov4f32(<4 x float> %x) { +; P8-LABEL: iszerov4f32: +; P8: # %bb.0: # %entry +; P8-NEXT: xxlxor 0, 0, 0 +; P8-NEXT: xvcmpeqsp 34, 34, 0 +; P8-NEXT: blr +; +; P9-LABEL: iszerov4f32: +; P9: # %bb.0: # %entry +; P9-NEXT: xxlxor 0, 0, 0 +; P9-NEXT: xvcmpeqsp 34, 34, 0 +; P9-NEXT: blr +entry: + %cmp = fcmp oeq <4 x float> %x, + ret <4 x i1> %cmp +} + +define <2 x i1> @iszerov2f64(<2 x double> %x) { +; P8-LABEL: iszerov2f64: +; P8: # %bb.0: # %entry +; P8-NEXT: xxlxor 0, 0, 0 +; P8-NEXT: xvcmpeqdp 34, 34, 0 +; P8-NEXT: blr +; +; P9-LABEL: iszerov2f64: +; P9: # %bb.0: # %entry +; P9-NEXT: xxlxor 0, 0, 0 +; P9-NEXT: xvcmpeqdp 34, 34, 0 +; P9-NEXT: blr +entry: + %cmp = fcmp oeq <2 x double> %x, + ret <2 x i1> %cmp +} + +declare float @llvm.fabs.f32(float) +declare double @llvm.fabs.f64(double) +declare fp128 @llvm.fabs.f128(fp128) +declare <4 x float> @llvm.fabs.v4f32(<4 x float>) +declare <2 x double> @llvm.fabs.v2f64(<2 x double>) diff --git a/llvm/test/CodeGen/PowerPC/load-and-splat.ll b/llvm/test/CodeGen/PowerPC/load-and-splat.ll --- a/llvm/test/CodeGen/PowerPC/load-and-splat.ll +++ b/llvm/test/CodeGen/PowerPC/load-and-splat.ll @@ -215,11 +215,11 @@ ; P9-AIX32-NEXT: stw r4, -16(r1) ; P9-AIX32-NEXT: lwz r4, L..C0(r2) # %const.0 ; P9-AIX32-NEXT: stw r5, -32(r1) -; P9-AIX32-NEXT: lxv v3, -16(r1) -; P9-AIX32-NEXT: lxv v4, -32(r1) -; P9-AIX32-NEXT: lxv v2, 0(r4) -; P9-AIX32-NEXT: vperm v2, v4, v3, v2 -; P9-AIX32-NEXT: stxv v2, 0(r3) +; P9-AIX32-NEXT: lxv vs1, -16(r1) +; P9-AIX32-NEXT: lxv vs2, -32(r1) +; P9-AIX32-NEXT: lxv vs0, 0(r4) +; P9-AIX32-NEXT: xxperm vs1, vs2, vs0 +; P9-AIX32-NEXT: stxv vs1, 0(r3) ; P9-AIX32-NEXT: blr ; ; P8-AIX32-LABEL: test4: @@ -291,12 +291,12 @@ ; P9-AIX32-NEXT: srawi r5, r4, 31 ; P9-AIX32-NEXT: stw r4, -16(r1) ; P9-AIX32-NEXT: lwz r4, L..C1(r2) # %const.0 -; P9-AIX32-NEXT: lxv v3, -16(r1) +; P9-AIX32-NEXT: lxv vs1, -16(r1) ; P9-AIX32-NEXT: stw r5, -32(r1) -; P9-AIX32-NEXT: lxv v4, -32(r1) -; P9-AIX32-NEXT: lxv v2, 0(r4) -; P9-AIX32-NEXT: vperm v2, v4, v3, v2 -; P9-AIX32-NEXT: stxv v2, 0(r3) +; P9-AIX32-NEXT: lxv vs2, -32(r1) +; P9-AIX32-NEXT: lxv vs0, 0(r4) +; P9-AIX32-NEXT: xxperm vs1, vs2, vs0 +; P9-AIX32-NEXT: stxv vs1, 0(r3) ; P9-AIX32-NEXT: blr ; ; P8-AIX32-LABEL: test5: @@ -367,13 +367,13 @@ ; P9-AIX32-NEXT: lwz r4, 0(r4) ; P9-AIX32-NEXT: li r5, 0 ; P9-AIX32-NEXT: stw r5, -32(r1) -; P9-AIX32-NEXT: lxv v3, -32(r1) +; P9-AIX32-NEXT: lxv vs1, -32(r1) ; P9-AIX32-NEXT: stw r4, -16(r1) ; P9-AIX32-NEXT: lwz r4, L..C2(r2) # %const.0 -; P9-AIX32-NEXT: lxv v4, -16(r1) -; P9-AIX32-NEXT: lxv v2, 0(r4) -; P9-AIX32-NEXT: vperm v2, v3, v4, v2 -; P9-AIX32-NEXT: stxv v2, 0(r3) +; P9-AIX32-NEXT: lxv vs2, -16(r1) +; P9-AIX32-NEXT: lxv vs0, 0(r4) +; P9-AIX32-NEXT: xxperm vs2, vs1, vs0 +; P9-AIX32-NEXT: stxv vs2, 0(r3) ; P9-AIX32-NEXT: blr ; ; P8-AIX32-LABEL: test6: diff --git a/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll b/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll --- a/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll +++ b/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll @@ -98,8 +98,8 @@ ; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-P9-BE-NEXT: lxv v3, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) +; CHECK-P9-BE-NEXT: xxperm v2, v2, vs0 ; CHECK-P9-BE-NEXT: blr %v1 = load <4 x i32>, ptr %vp1 %v2 = load <4 x i32>, ptr %vp2 @@ -138,8 +138,8 @@ ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l -; CHECK-P9-BE-NEXT: lxv v3, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) +; CHECK-P9-BE-NEXT: xxperm v2, v2, vs0 ; CHECK-P9-BE-NEXT: blr %v1 = load <4 x i32>, ptr %vp1 %v2 = load <4 x i32>, ptr %vp2 @@ -178,8 +178,8 @@ ; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-P9-BE-NEXT: lxv v3, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) +; CHECK-P9-BE-NEXT: xxperm v2, v2, vs0 ; CHECK-P9-BE-NEXT: blr %v1 = load <8 x i16>, ptr %vp1 %v2 = load <8 x i16>, ptr %vp2 @@ -218,8 +218,8 @@ ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-P9-BE-NEXT: lxv v3, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) +; CHECK-P9-BE-NEXT: xxperm v2, v2, vs0 ; CHECK-P9-BE-NEXT: blr %v1 = load <8 x i16>, ptr %vp1 %v2 = load <8 x i16>, ptr %vp2 @@ -360,8 +360,8 @@ ; CHECK-P9-BE-NEXT: lxv v2, 0(r3) ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI9_0@toc@l -; CHECK-P9-BE-NEXT: lxv v3, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) +; CHECK-P9-BE-NEXT: xxperm v2, v2, vs0 ; CHECK-P9-BE-NEXT: blr %v1 = load <4 x float>, ptr %vp1 %v2 = load <4 x float>, ptr %vp2 @@ -400,8 +400,8 @@ ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI10_0@toc@ha ; CHECK-P9-BE-NEXT: lxv v2, 0(r4) ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI10_0@toc@l -; CHECK-P9-BE-NEXT: lxv v3, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) +; CHECK-P9-BE-NEXT: xxperm v2, v2, vs0 ; CHECK-P9-BE-NEXT: blr %v1 = load <4 x float>, ptr %vp1 %v2 = load <4 x float>, ptr %vp2 @@ -493,8 +493,8 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI13_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI13_0@toc@l -; CHECK-P9-BE-NEXT: lxv v3, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) +; CHECK-P9-BE-NEXT: xxperm v2, v2, vs0 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> @@ -532,9 +532,9 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI14_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI14_0@toc@l -; CHECK-P9-BE-NEXT: lxv v2, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 -; CHECK-P9-BE-NEXT: stxv v2, 0(r7) +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) +; CHECK-P9-BE-NEXT: xxperm v3, v3, vs0 +; CHECK-P9-BE-NEXT: stxv v3, 0(r7) ; CHECK-P9-BE-NEXT: blr %v3 = shufflevector <4 x i32> %v1, <4 x i32> %v2, <4 x i32> store <4 x i32> %v3, ptr %vp @@ -571,8 +571,8 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI15_0@toc@l -; CHECK-P9-BE-NEXT: lxv v3, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) +; CHECK-P9-BE-NEXT: xxperm v2, v2, vs0 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> @@ -610,9 +610,9 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI16_0@toc@l -; CHECK-P9-BE-NEXT: lxv v2, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 -; CHECK-P9-BE-NEXT: stxv v2, 0(r7) +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) +; CHECK-P9-BE-NEXT: xxperm v3, v3, vs0 +; CHECK-P9-BE-NEXT: stxv v3, 0(r7) ; CHECK-P9-BE-NEXT: blr %v3 = shufflevector <8 x i16> %v1, <8 x i16> %v2, <8 x i32> store <8 x i16> %v3, ptr %vp @@ -775,8 +775,8 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI21_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI21_0@toc@l -; CHECK-P9-BE-NEXT: lxv v3, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v2, v2, v3 +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) +; CHECK-P9-BE-NEXT: xxperm v2, v2, vs0 ; CHECK-P9-BE-NEXT: stxv v2, 0(r7) ; CHECK-P9-BE-NEXT: blr %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> @@ -814,9 +814,9 @@ ; CHECK-P9-BE: # %bb.0: ; CHECK-P9-BE-NEXT: addis r3, r2, .LCPI22_0@toc@ha ; CHECK-P9-BE-NEXT: addi r3, r3, .LCPI22_0@toc@l -; CHECK-P9-BE-NEXT: lxv v2, 0(r3) -; CHECK-P9-BE-NEXT: vperm v2, v3, v3, v2 -; CHECK-P9-BE-NEXT: stxv v2, 0(r7) +; CHECK-P9-BE-NEXT: lxv vs0, 0(r3) +; CHECK-P9-BE-NEXT: xxperm v3, v3, vs0 +; CHECK-P9-BE-NEXT: stxv v3, 0(r7) ; CHECK-P9-BE-NEXT: blr %v3 = shufflevector <4 x float> %v1, <4 x float> %v2, <4 x i32> store <4 x float> %v3, ptr %vp diff --git a/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll b/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll --- a/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll +++ b/llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll @@ -81,8 +81,8 @@ define <1 x i128> @test_vrlqnm(<1 x i128> %a, <1 x i128> %b, <1 x i128> %c) { ; CHECK-LE-LABEL: test_vrlqnm: ; CHECK-LE: # %bb.0: # %entry -; CHECK-LE-NEXT: plxv v5, .LCPI4_0@PCREL(0), 1 -; CHECK-LE-NEXT: vperm v3, v4, v3, v5 +; CHECK-LE-NEXT: plxv vs0, .LCPI4_0@PCREL(0), 1 +; CHECK-LE-NEXT: xxperm v3, v4, vs0 ; CHECK-LE-NEXT: vrlqnm v2, v2, v3 ; CHECK-LE-NEXT: blr ; @@ -90,9 +90,9 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxv v5, 0(r3) -; CHECK-BE-NEXT: vperm v3, v3, v4, v5 -; CHECK-BE-NEXT: vrlqnm v2, v2, v3 +; CHECK-BE-NEXT: lxv vs0, 0(r3) +; CHECK-BE-NEXT: xxperm v4, v3, vs0 +; CHECK-BE-NEXT: vrlqnm v2, v2, v4 ; CHECK-BE-NEXT: blr entry: %0 = bitcast <1 x i128> %b to <16 x i8> diff --git a/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll b/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll --- a/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll +++ b/llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll @@ -451,8 +451,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI16_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI16_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: blr entry: %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> @@ -464,8 +464,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI17_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI17_0@toc@l -; CHECK-NEXT: lxv 35, 0(3) -; CHECK-NEXT: vperm 2, 2, 2, 3 +; CHECK-NEXT: lxv 0, 0(3) +; CHECK-NEXT: xxperm 34, 34, 0 ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shuffle_vector_halfword_1_3: @@ -482,8 +482,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI18_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI18_0@toc@l -; CHECK-NEXT: lxv 35, 0(3) -; CHECK-NEXT: vperm 2, 2, 2, 3 +; CHECK-NEXT: lxv 0, 0(3) +; CHECK-NEXT: xxperm 34, 34, 0 ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shuffle_vector_halfword_2_3: @@ -505,8 +505,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI19_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI19_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: blr entry: %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> @@ -518,8 +518,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI20_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI20_0@toc@l -; CHECK-NEXT: lxv 35, 0(3) -; CHECK-NEXT: vperm 2, 2, 2, 3 +; CHECK-NEXT: lxv 0, 0(3) +; CHECK-NEXT: xxperm 34, 34, 0 ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shuffle_vector_halfword_4_3: @@ -536,8 +536,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI21_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI21_0@toc@l -; CHECK-NEXT: lxv 35, 0(3) -; CHECK-NEXT: vperm 2, 2, 2, 3 +; CHECK-NEXT: lxv 0, 0(3) +; CHECK-NEXT: xxperm 34, 34, 0 ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shuffle_vector_halfword_5_3: @@ -559,8 +559,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI22_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI22_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: blr entry: %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> @@ -577,8 +577,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI23_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI23_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: blr entry: %vecins = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> @@ -1455,8 +1455,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI56_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI56_0@toc@l -; CHECK-NEXT: lxv 35, 0(3) -; CHECK-NEXT: vperm 2, 2, 2, 3 +; CHECK-NEXT: lxv 0, 0(3) +; CHECK-NEXT: xxperm 34, 34, 0 ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shuffle_vector_byte_0_7: @@ -1478,8 +1478,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI57_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI57_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1496,8 +1496,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI58_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI58_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1509,8 +1509,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI59_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI59_0@toc@l -; CHECK-NEXT: lxv 35, 0(3) -; CHECK-NEXT: vperm 2, 2, 2, 3 +; CHECK-NEXT: lxv 0, 0(3) +; CHECK-NEXT: xxperm 34, 34, 0 ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shuffle_vector_byte_3_7: @@ -1527,8 +1527,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI60_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI60_0@toc@l -; CHECK-NEXT: lxv 35, 0(3) -; CHECK-NEXT: vperm 2, 2, 2, 3 +; CHECK-NEXT: lxv 0, 0(3) +; CHECK-NEXT: xxperm 34, 34, 0 ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shuffle_vector_byte_4_7: @@ -1550,8 +1550,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI61_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI61_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1568,8 +1568,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI62_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI62_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1586,8 +1586,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI63_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI63_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1599,8 +1599,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI64_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI64_0@toc@l -; CHECK-NEXT: lxv 35, 0(3) -; CHECK-NEXT: vperm 2, 2, 2, 3 +; CHECK-NEXT: lxv 0, 0(3) +; CHECK-NEXT: xxperm 34, 34, 0 ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shuffle_vector_byte_8_7: @@ -1617,8 +1617,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI65_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI65_0@toc@l -; CHECK-NEXT: lxv 35, 0(3) -; CHECK-NEXT: vperm 2, 2, 2, 3 +; CHECK-NEXT: lxv 0, 0(3) +; CHECK-NEXT: xxperm 34, 34, 0 ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shuffle_vector_byte_9_7: @@ -1635,8 +1635,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI66_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI66_0@toc@l -; CHECK-NEXT: lxv 35, 0(3) -; CHECK-NEXT: vperm 2, 2, 2, 3 +; CHECK-NEXT: lxv 0, 0(3) +; CHECK-NEXT: xxperm 34, 34, 0 ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shuffle_vector_byte_10_7: @@ -1658,8 +1658,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI67_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI67_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1676,8 +1676,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI68_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI68_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> @@ -1689,8 +1689,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI69_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI69_0@toc@l -; CHECK-NEXT: lxv 35, 0(3) -; CHECK-NEXT: vperm 2, 2, 2, 3 +; CHECK-NEXT: lxv 0, 0(3) +; CHECK-NEXT: xxperm 34, 34, 0 ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shuffle_vector_byte_13_7: @@ -1707,8 +1707,8 @@ ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: addis 3, 2, .LCPI70_0@toc@ha ; CHECK-NEXT: addi 3, 3, .LCPI70_0@toc@l -; CHECK-NEXT: lxv 35, 0(3) -; CHECK-NEXT: vperm 2, 2, 2, 3 +; CHECK-NEXT: lxv 0, 0(3) +; CHECK-NEXT: xxperm 34, 34, 0 ; CHECK-NEXT: blr ; ; CHECK-BE-LABEL: shuffle_vector_byte_14_7: @@ -1730,8 +1730,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI71_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI71_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: blr entry: %vecins = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> diff --git a/llvm/test/CodeGen/PowerPC/ppc-shufflevector-combine.ll b/llvm/test/CodeGen/PowerPC/ppc-shufflevector-combine.ll --- a/llvm/test/CodeGen/PowerPC/ppc-shufflevector-combine.ll +++ b/llvm/test/CodeGen/PowerPC/ppc-shufflevector-combine.ll @@ -22,10 +22,10 @@ ; AIX-LABEL: shufflevector_combine: ; AIX: # %bb.0: # %newFuncRoot ; AIX-NEXT: ld 3, L..C0(2) # %const.0 -; AIX-NEXT: xxlxor 36, 36, 36 -; AIX-NEXT: lxv 35, 0(3) +; AIX-NEXT: xxlxor 1, 1, 1 +; AIX-NEXT: lxv 0, 0(3) ; AIX-NEXT: li 3, 0 -; AIX-NEXT: vperm 2, 4, 2, 3 +; AIX-NEXT: xxperm 34, 1, 0 ; AIX-NEXT: vinsw 2, 3, 8 ; AIX-NEXT: vpkuwum 2, 2, 2 ; AIX-NEXT: blr @@ -33,44 +33,44 @@ ; AIX-32-LABEL: shufflevector_combine: ; AIX-32: # %bb.0: # %newFuncRoot ; AIX-32-NEXT: lwz 3, L..C0(2) # %const.0 -; AIX-32-NEXT: xxlxor 36, 36, 36 -; AIX-32-NEXT: lxv 35, 0(3) +; AIX-32-NEXT: xxlxor 1, 1, 1 +; AIX-32-NEXT: lxv 0, 0(3) ; AIX-32-NEXT: li 3, 0 -; AIX-32-NEXT: vperm 2, 4, 2, 3 +; AIX-32-NEXT: xxperm 34, 1, 0 ; AIX-32-NEXT: vinsw 2, 3, 8 ; AIX-32-NEXT: vpkuwum 2, 2, 2 ; AIX-32-NEXT: blr ; ; LE-LABEL: shufflevector_combine: ; LE: # %bb.0: # %newFuncRoot -; LE-NEXT: plxv v3, .LCPI0_0@PCREL(0), 1 -; LE-NEXT: xxlxor v4, v4, v4 +; LE-NEXT: plxv vs0, .LCPI0_0@PCREL(0), 1 +; LE-NEXT: xxlxor v3, v3, v3 ; LE-NEXT: li r3, 0 -; LE-NEXT: vperm v2, v2, v4, v3 -; LE-NEXT: vinsw v2, r3, 4 -; LE-NEXT: vpkuwum v2, v2, v2 +; LE-NEXT: xxperm v3, v2, vs0 +; LE-NEXT: vinsw v3, r3, 4 +; LE-NEXT: vpkuwum v2, v3, v3 ; LE-NEXT: blr ; ; LE-32-LABEL: shufflevector_combine: ; LE-32: # %bb.0: # %newFuncRoot ; LE-32-NEXT: li r3, .LCPI0_0@l ; LE-32-NEXT: lis r4, .LCPI0_0@ha -; LE-32-NEXT: xxlxor v4, v4, v4 -; LE-32-NEXT: lxvx v3, r4, r3 +; LE-32-NEXT: xxlxor v3, v3, v3 +; LE-32-NEXT: lxvx vs0, r4, r3 ; LE-32-NEXT: li r3, 0 -; LE-32-NEXT: vperm v2, v2, v4, v3 -; LE-32-NEXT: vinsw v2, r3, 4 -; LE-32-NEXT: vpkuwum v2, v2, v2 +; LE-32-NEXT: xxperm v3, v2, vs0 +; LE-32-NEXT: vinsw v3, r3, 4 +; LE-32-NEXT: vpkuwum v2, v3, v3 ; LE-32-NEXT: blr ; ; BE-LABEL: shufflevector_combine: ; BE: # %bb.0: # %newFuncRoot ; BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; BE-NEXT: xxlxor v4, v4, v4 +; BE-NEXT: xxlxor vs0, vs0, vs0 ; BE-NEXT: addi r3, r3, .LCPI0_0@toc@l -; BE-NEXT: lxv v3, 0(r3) +; BE-NEXT: lxv vs1, 0(r3) ; BE-NEXT: li r3, 0 -; BE-NEXT: vperm v2, v4, v2, v3 +; BE-NEXT: xxperm v2, vs0, vs1 ; BE-NEXT: vinsw v2, r3, 8 ; BE-NEXT: vpkuwum v2, v2, v2 ; BE-NEXT: blr @@ -79,10 +79,10 @@ ; BE-32: # %bb.0: # %newFuncRoot ; BE-32-NEXT: li r3, .LCPI0_0@l ; BE-32-NEXT: lis r4, .LCPI0_0@ha -; BE-32-NEXT: xxlxor v4, v4, v4 -; BE-32-NEXT: lxvx v3, r4, r3 +; BE-32-NEXT: xxlxor vs1, vs1, vs1 +; BE-32-NEXT: lxvx vs0, r4, r3 ; BE-32-NEXT: li r3, 0 -; BE-32-NEXT: vperm v2, v4, v2, v3 +; BE-32-NEXT: xxperm v2, vs1, vs0 ; BE-32-NEXT: vinsw v2, r3, 8 ; BE-32-NEXT: vpkuwum v2, v2, v2 ; BE-32-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll b/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll --- a/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll @@ -544,6 +544,7 @@ ; CHECK-PWR9-BE-NEXT: li r10, 7 ; CHECK-PWR9-BE-NEXT: vextublx r11, r10, v2 ; CHECK-PWR9-BE-NEXT: vextublx r10, r10, v3 +; CHECK-PWR9-BE-NEXT: mtfprwz f2, r9 ; CHECK-PWR9-BE-NEXT: clrlwi r11, r11, 24 ; CHECK-PWR9-BE-NEXT: clrlwi r10, r10, 24 ; CHECK-PWR9-BE-NEXT: sub r10, r11, r10 @@ -562,7 +563,6 @@ ; CHECK-PWR9-BE-NEXT: li r12, 9 ; CHECK-PWR9-BE-NEXT: vextublx r0, r12, v2 ; CHECK-PWR9-BE-NEXT: vextublx r12, r12, v3 -; CHECK-PWR9-BE-NEXT: mtvsrwz v0, r11 ; CHECK-PWR9-BE-NEXT: clrlwi r0, r0, 24 ; CHECK-PWR9-BE-NEXT: clrlwi r12, r12, 24 ; CHECK-PWR9-BE-NEXT: sub r12, r0, r12 @@ -572,6 +572,7 @@ ; CHECK-PWR9-BE-NEXT: li r0, 10 ; CHECK-PWR9-BE-NEXT: vextublx r30, r0, v2 ; CHECK-PWR9-BE-NEXT: vextublx r0, r0, v3 +; CHECK-PWR9-BE-NEXT: mtvsrwz v4, r12 ; CHECK-PWR9-BE-NEXT: clrlwi r30, r30, 24 ; CHECK-PWR9-BE-NEXT: clrlwi r0, r0, 24 ; CHECK-PWR9-BE-NEXT: sub r0, r30, r0 @@ -599,8 +600,6 @@ ; CHECK-PWR9-BE-NEXT: li r28, 13 ; CHECK-PWR9-BE-NEXT: vextublx r27, r28, v2 ; CHECK-PWR9-BE-NEXT: vextublx r28, r28, v3 -; CHECK-PWR9-BE-NEXT: mtvsrwz v5, r29 -; CHECK-PWR9-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-PWR9-BE-NEXT: clrlwi r27, r27, 24 ; CHECK-PWR9-BE-NEXT: clrlwi r28, r28, 24 ; CHECK-PWR9-BE-NEXT: sub r28, r27, r28 @@ -619,12 +618,14 @@ ; CHECK-PWR9-BE-NEXT: li r26, 15 ; CHECK-PWR9-BE-NEXT: vextublx r25, r26, v2 ; CHECK-PWR9-BE-NEXT: vextublx r26, r26, v3 -; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r27 +; CHECK-PWR9-BE-NEXT: mtfprwz f0, r27 ; CHECK-PWR9-BE-NEXT: addis r27, r2, .LCPI9_0@toc@ha +; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r28 +; CHECK-PWR9-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-PWR9-BE-NEXT: addi r27, r27, .LCPI9_0@toc@l ; CHECK-PWR9-BE-NEXT: clrlwi r25, r25, 24 ; CHECK-PWR9-BE-NEXT: clrlwi r26, r26, 24 -; CHECK-PWR9-BE-NEXT: lxv v4, 0(r27) +; CHECK-PWR9-BE-NEXT: lxv vs1, 0(r27) ; CHECK-PWR9-BE-NEXT: ld r27, -40(r1) # 8-byte Folded Reload ; CHECK-PWR9-BE-NEXT: sub r26, r25, r26 ; CHECK-PWR9-BE-NEXT: srawi r25, r26, 31 @@ -633,32 +634,31 @@ ; CHECK-PWR9-BE-NEXT: ld r25, -56(r1) # 8-byte Folded Reload ; CHECK-PWR9-BE-NEXT: mtvsrwz v2, r26 ; CHECK-PWR9-BE-NEXT: ld r26, -48(r1) # 8-byte Folded Reload -; CHECK-PWR9-BE-NEXT: vperm v2, v3, v2, v4 -; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r28 -; CHECK-PWR9-BE-NEXT: ld r28, -32(r1) # 8-byte Folded Reload -; CHECK-PWR9-BE-NEXT: vperm v3, v5, v3, v4 -; CHECK-PWR9-BE-NEXT: mtvsrwz v5, r0 +; CHECK-PWR9-BE-NEXT: xxperm v2, vs0, vs1 +; CHECK-PWR9-BE-NEXT: mtfprwz f0, r29 +; CHECK-PWR9-BE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload +; CHECK-PWR9-BE-NEXT: xxperm v3, vs0, vs1 +; CHECK-PWR9-BE-NEXT: mtfprwz f0, r0 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r30 ; CHECK-PWR9-BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload -; CHECK-PWR9-BE-NEXT: vperm v3, v5, v3, v4 -; CHECK-PWR9-BE-NEXT: mtvsrwz v5, r12 -; CHECK-PWR9-BE-NEXT: vperm v5, v0, v5, v4 -; CHECK-PWR9-BE-NEXT: mtvsrwz v0, r3 -; CHECK-PWR9-BE-NEXT: vmrghh v3, v5, v3 -; CHECK-PWR9-BE-NEXT: mtvsrwz v5, r7 +; CHECK-PWR9-BE-NEXT: xxperm v3, vs0, vs1 +; CHECK-PWR9-BE-NEXT: mtfprwz f0, r11 +; CHECK-PWR9-BE-NEXT: xxperm v4, vs0, vs1 +; CHECK-PWR9-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-PWR9-BE-NEXT: mtvsrwz v4, r4 ; CHECK-PWR9-BE-NEXT: xxmrghw vs0, v3, v2 ; CHECK-PWR9-BE-NEXT: mtvsrwz v2, r10 -; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r9 -; CHECK-PWR9-BE-NEXT: vperm v2, v3, v2, v4 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r8 -; CHECK-PWR9-BE-NEXT: vperm v3, v5, v3, v4 -; CHECK-PWR9-BE-NEXT: mtvsrwz v5, r5 +; CHECK-PWR9-BE-NEXT: xxperm v2, vs2, vs1 +; CHECK-PWR9-BE-NEXT: mtfprwz f2, r7 +; CHECK-PWR9-BE-NEXT: xxperm v3, vs2, vs1 +; CHECK-PWR9-BE-NEXT: mtfprwz f2, r5 ; CHECK-PWR9-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-PWR9-BE-NEXT: mtvsrwz v3, r6 -; CHECK-PWR9-BE-NEXT: vperm v3, v5, v3, v4 -; CHECK-PWR9-BE-NEXT: mtvsrwz v5, r4 -; CHECK-PWR9-BE-NEXT: vperm v4, v0, v5, v4 +; CHECK-PWR9-BE-NEXT: xxperm v3, vs2, vs1 +; CHECK-PWR9-BE-NEXT: mtfprwz f2, r3 +; CHECK-PWR9-BE-NEXT: xxperm v4, vs2, vs1 ; CHECK-PWR9-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-PWR9-BE-NEXT: xxmrghw vs1, v3, v2 ; CHECK-PWR9-BE-NEXT: xxmrghd v2, vs1, vs0 diff --git a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll --- a/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll +++ b/llvm/test/CodeGen/PowerPC/pre-inc-disable.ll @@ -19,20 +19,20 @@ ; P9LE-LABEL: test64: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: add 5, 3, 4 -; P9LE-NEXT: lxsdx 2, 3, 4 +; P9LE-NEXT: lfdx 0, 3, 4 ; P9LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; P9LE-NEXT: xxlxor 4, 4, 4 +; P9LE-NEXT: xxlxor 2, 2, 2 +; P9LE-NEXT: vspltisw 4, 8 +; P9LE-NEXT: lxsd 3, 4(5) ; P9LE-NEXT: addi 3, 3, .LCPI0_0@toc@l -; P9LE-NEXT: lxv 3, 0(3) +; P9LE-NEXT: vadduwm 4, 4, 4 +; P9LE-NEXT: lxv 1, 0(3) ; P9LE-NEXT: addis 3, 2, .LCPI0_1@toc@ha ; P9LE-NEXT: addi 3, 3, .LCPI0_1@toc@l -; P9LE-NEXT: vperm 2, 2, 4, 3 -; P9LE-NEXT: lxsd 3, 4(5) -; P9LE-NEXT: lxv 4, 0(3) -; P9LE-NEXT: vperm 3, 3, 3, 4 -; P9LE-NEXT: vspltisw 4, 8 +; P9LE-NEXT: xxperm 2, 0, 1 +; P9LE-NEXT: lxv 0, 0(3) +; P9LE-NEXT: xxperm 3, 3, 0 ; P9LE-NEXT: vnegw 3, 3 -; P9LE-NEXT: vadduwm 4, 4, 4 ; P9LE-NEXT: vslw 3, 3, 4 ; P9LE-NEXT: vsubuwm 2, 3, 2 ; P9LE-NEXT: xxswapd 0, 2 @@ -44,18 +44,18 @@ ; P9BE-NEXT: add 5, 3, 4 ; P9BE-NEXT: lxsdx 2, 3, 4 ; P9BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha -; P9BE-NEXT: xxlxor 4, 4, 4 +; P9BE-NEXT: xxlxor 0, 0, 0 +; P9BE-NEXT: vspltisw 4, 8 +; P9BE-NEXT: lxsd 3, 4(5) ; P9BE-NEXT: addi 3, 3, .LCPI0_0@toc@l -; P9BE-NEXT: lxv 3, 0(3) +; P9BE-NEXT: vadduwm 4, 4, 4 +; P9BE-NEXT: lxv 1, 0(3) ; P9BE-NEXT: addis 3, 2, .LCPI0_1@toc@ha ; P9BE-NEXT: addi 3, 3, .LCPI0_1@toc@l -; P9BE-NEXT: vperm 2, 4, 2, 3 -; P9BE-NEXT: lxsd 3, 4(5) -; P9BE-NEXT: lxv 4, 0(3) -; P9BE-NEXT: vperm 3, 3, 3, 4 -; P9BE-NEXT: vspltisw 4, 8 +; P9BE-NEXT: xxperm 2, 0, 1 +; P9BE-NEXT: lxv 0, 0(3) +; P9BE-NEXT: xxperm 3, 3, 0 ; P9BE-NEXT: vnegw 3, 3 -; P9BE-NEXT: vadduwm 4, 4, 4 ; P9BE-NEXT: vslw 3, 3, 4 ; P9BE-NEXT: vsubuwm 2, 3, 2 ; P9BE-NEXT: xxswapd 0, 2 @@ -67,16 +67,16 @@ ; P9BE-AIX-NEXT: add 5, 3, 4 ; P9BE-AIX-NEXT: lxsdx 2, 3, 4 ; P9BE-AIX-NEXT: ld 3, L..C0(2) # %const.0 -; P9BE-AIX-NEXT: xxlxor 4, 4, 4 -; P9BE-AIX-NEXT: lxv 3, 0(3) -; P9BE-AIX-NEXT: ld 3, L..C1(2) # %const.1 -; P9BE-AIX-NEXT: vperm 2, 4, 2, 3 -; P9BE-AIX-NEXT: lxsd 3, 4(5) -; P9BE-AIX-NEXT: lxv 4, 0(3) -; P9BE-AIX-NEXT: vperm 3, 3, 3, 4 +; P9BE-AIX-NEXT: xxlxor 1, 1, 1 ; P9BE-AIX-NEXT: vspltisw 4, 8 -; P9BE-AIX-NEXT: vnegw 3, 3 +; P9BE-AIX-NEXT: lxsd 3, 4(5) +; P9BE-AIX-NEXT: lxv 0, 0(3) +; P9BE-AIX-NEXT: ld 3, L..C1(2) # %const.1 ; P9BE-AIX-NEXT: vadduwm 4, 4, 4 +; P9BE-AIX-NEXT: xxperm 2, 1, 0 +; P9BE-AIX-NEXT: lxv 0, 0(3) +; P9BE-AIX-NEXT: xxperm 3, 3, 0 +; P9BE-AIX-NEXT: vnegw 3, 3 ; P9BE-AIX-NEXT: vslw 3, 3, 4 ; P9BE-AIX-NEXT: vsubuwm 2, 3, 2 ; P9BE-AIX-NEXT: xxswapd 0, 2 @@ -86,26 +86,26 @@ ; P9BE-AIX32-LABEL: test64: ; P9BE-AIX32: # %bb.0: # %entry ; P9BE-AIX32-NEXT: lwzux 4, 3, 4 -; P9BE-AIX32-NEXT: xxlxor 4, 4, 4 +; P9BE-AIX32-NEXT: xxlxor 2, 2, 2 +; P9BE-AIX32-NEXT: vspltisw 4, 8 ; P9BE-AIX32-NEXT: stw 4, -48(1) +; P9BE-AIX32-NEXT: vadduwm 4, 4, 4 ; P9BE-AIX32-NEXT: lwz 4, 4(3) ; P9BE-AIX32-NEXT: lxv 0, -48(1) ; P9BE-AIX32-NEXT: stw 4, -32(1) ; P9BE-AIX32-NEXT: lwz 4, L..C0(2) # %const.0 -; P9BE-AIX32-NEXT: lwz 3, 8(3) ; P9BE-AIX32-NEXT: lxv 1, -32(1) -; P9BE-AIX32-NEXT: lxv 3, 0(4) +; P9BE-AIX32-NEXT: lwz 3, 8(3) ; P9BE-AIX32-NEXT: stw 3, -16(1) ; P9BE-AIX32-NEXT: lwz 3, L..C1(2) # %const.1 ; P9BE-AIX32-NEXT: xxmrghw 2, 0, 1 +; P9BE-AIX32-NEXT: lxv 0, 0(4) +; P9BE-AIX32-NEXT: xxperm 2, 2, 0 ; P9BE-AIX32-NEXT: lxv 0, -16(1) -; P9BE-AIX32-NEXT: vperm 2, 4, 2, 3 -; P9BE-AIX32-NEXT: lxv 4, 0(3) ; P9BE-AIX32-NEXT: xxmrghw 3, 1, 0 -; P9BE-AIX32-NEXT: vperm 3, 3, 3, 4 -; P9BE-AIX32-NEXT: vspltisw 4, 8 +; P9BE-AIX32-NEXT: lxv 0, 0(3) +; P9BE-AIX32-NEXT: xxperm 3, 3, 0 ; P9BE-AIX32-NEXT: vnegw 3, 3 -; P9BE-AIX32-NEXT: vadduwm 4, 4, 4 ; P9BE-AIX32-NEXT: vslw 3, 3, 4 ; P9BE-AIX32-NEXT: vsubuwm 2, 3, 2 ; P9BE-AIX32-NEXT: xxswapd 0, 2 @@ -137,20 +137,21 @@ ; P9LE-LABEL: test32: ; P9LE: # %bb.0: # %entry ; P9LE-NEXT: add 5, 3, 4 -; P9LE-NEXT: lxsiwzx 2, 3, 4 +; P9LE-NEXT: lfiwzx 0, 3, 4 ; P9LE-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; P9LE-NEXT: xxlxor 3, 3, 3 +; P9LE-NEXT: vspltisw 4, 8 ; P9LE-NEXT: addi 3, 3, .LCPI1_0@toc@l -; P9LE-NEXT: lxv 4, 0(3) +; P9LE-NEXT: lxv 1, 0(3) ; P9LE-NEXT: li 3, 4 -; P9LE-NEXT: lxsiwzx 5, 5, 3 -; P9LE-NEXT: vperm 2, 2, 3, 4 -; P9LE-NEXT: vperm 3, 5, 3, 4 -; P9LE-NEXT: vspltisw 4, 8 -; P9LE-NEXT: vnegw 3, 3 +; P9LE-NEXT: xxlxor 2, 2, 2 ; P9LE-NEXT: vadduwm 4, 4, 4 -; P9LE-NEXT: vslw 3, 3, 4 -; P9LE-NEXT: vsubuwm 2, 3, 2 +; P9LE-NEXT: xxperm 3, 0, 1 +; P9LE-NEXT: lfiwzx 0, 5, 3 +; P9LE-NEXT: xxperm 2, 0, 1 +; P9LE-NEXT: vnegw 2, 2 +; P9LE-NEXT: vslw 2, 2, 4 +; P9LE-NEXT: vsubuwm 2, 2, 3 ; P9LE-NEXT: xxswapd 0, 2 ; P9LE-NEXT: stxv 0, 0(3) ; P9LE-NEXT: blr @@ -158,20 +159,21 @@ ; P9BE-LABEL: test32: ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: add 5, 3, 4 -; P9BE-NEXT: lxsiwzx 2, 3, 4 +; P9BE-NEXT: lfiwzx 0, 3, 4 ; P9BE-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; P9BE-NEXT: xxlxor 3, 3, 3 +; P9BE-NEXT: vspltisw 4, 8 ; P9BE-NEXT: addi 3, 3, .LCPI1_0@toc@l -; P9BE-NEXT: lxv 4, 0(3) +; P9BE-NEXT: lxv 1, 0(3) ; P9BE-NEXT: li 3, 4 -; P9BE-NEXT: lxsiwzx 5, 5, 3 -; P9BE-NEXT: vperm 2, 3, 2, 4 -; P9BE-NEXT: vperm 3, 3, 5, 4 -; P9BE-NEXT: vspltisw 4, 8 -; P9BE-NEXT: vnegw 3, 3 +; P9BE-NEXT: xxlxor 2, 2, 2 ; P9BE-NEXT: vadduwm 4, 4, 4 -; P9BE-NEXT: vslw 3, 3, 4 -; P9BE-NEXT: vsubuwm 2, 3, 2 +; P9BE-NEXT: xxperm 3, 0, 1 +; P9BE-NEXT: lfiwzx 0, 5, 3 +; P9BE-NEXT: xxperm 2, 0, 1 +; P9BE-NEXT: vnegw 2, 2 +; P9BE-NEXT: vslw 2, 2, 4 +; P9BE-NEXT: vsubuwm 2, 2, 3 ; P9BE-NEXT: xxswapd 0, 2 ; P9BE-NEXT: stxv 0, 0(3) ; P9BE-NEXT: blr @@ -179,19 +181,20 @@ ; P9BE-AIX-LABEL: test32: ; P9BE-AIX: # %bb.0: # %entry ; P9BE-AIX-NEXT: add 5, 3, 4 -; P9BE-AIX-NEXT: lxsiwzx 2, 3, 4 +; P9BE-AIX-NEXT: lfiwzx 0, 3, 4 ; P9BE-AIX-NEXT: ld 3, L..C2(2) # %const.0 ; P9BE-AIX-NEXT: xxlxor 3, 3, 3 -; P9BE-AIX-NEXT: lxv 4, 0(3) -; P9BE-AIX-NEXT: li 3, 4 -; P9BE-AIX-NEXT: lxsiwzx 5, 5, 3 -; P9BE-AIX-NEXT: vperm 2, 3, 2, 4 -; P9BE-AIX-NEXT: vperm 3, 3, 5, 4 +; P9BE-AIX-NEXT: xxlxor 2, 2, 2 ; P9BE-AIX-NEXT: vspltisw 4, 8 -; P9BE-AIX-NEXT: vnegw 3, 3 ; P9BE-AIX-NEXT: vadduwm 4, 4, 4 -; P9BE-AIX-NEXT: vslw 3, 3, 4 -; P9BE-AIX-NEXT: vsubuwm 2, 3, 2 +; P9BE-AIX-NEXT: lxv 1, 0(3) +; P9BE-AIX-NEXT: li 3, 4 +; P9BE-AIX-NEXT: xxperm 3, 0, 1 +; P9BE-AIX-NEXT: lfiwzx 0, 5, 3 +; P9BE-AIX-NEXT: xxperm 2, 0, 1 +; P9BE-AIX-NEXT: vnegw 2, 2 +; P9BE-AIX-NEXT: vslw 2, 2, 4 +; P9BE-AIX-NEXT: vsubuwm 2, 2, 3 ; P9BE-AIX-NEXT: xxswapd 0, 2 ; P9BE-AIX-NEXT: stxv 0, 0(3) ; P9BE-AIX-NEXT: blr @@ -199,19 +202,20 @@ ; P9BE-AIX32-LABEL: test32: ; P9BE-AIX32: # %bb.0: # %entry ; P9BE-AIX32-NEXT: add 5, 3, 4 -; P9BE-AIX32-NEXT: lxsiwzx 2, 3, 4 +; P9BE-AIX32-NEXT: lfiwzx 0, 3, 4 ; P9BE-AIX32-NEXT: lwz 3, L..C2(2) # %const.0 ; P9BE-AIX32-NEXT: xxlxor 3, 3, 3 -; P9BE-AIX32-NEXT: lxv 4, 0(3) -; P9BE-AIX32-NEXT: li 3, 4 -; P9BE-AIX32-NEXT: lxsiwzx 5, 5, 3 -; P9BE-AIX32-NEXT: vperm 2, 3, 2, 4 -; P9BE-AIX32-NEXT: vperm 3, 3, 5, 4 +; P9BE-AIX32-NEXT: xxlxor 2, 2, 2 ; P9BE-AIX32-NEXT: vspltisw 4, 8 -; P9BE-AIX32-NEXT: vnegw 3, 3 ; P9BE-AIX32-NEXT: vadduwm 4, 4, 4 -; P9BE-AIX32-NEXT: vslw 3, 3, 4 -; P9BE-AIX32-NEXT: vsubuwm 2, 3, 2 +; P9BE-AIX32-NEXT: lxv 1, 0(3) +; P9BE-AIX32-NEXT: li 3, 4 +; P9BE-AIX32-NEXT: xxperm 3, 0, 1 +; P9BE-AIX32-NEXT: lfiwzx 0, 5, 3 +; P9BE-AIX32-NEXT: xxperm 2, 0, 1 +; P9BE-AIX32-NEXT: vnegw 2, 2 +; P9BE-AIX32-NEXT: vslw 2, 2, 4 +; P9BE-AIX32-NEXT: vsubuwm 2, 2, 3 ; P9BE-AIX32-NEXT: xxswapd 0, 2 ; P9BE-AIX32-NEXT: stxv 0, 0(3) ; P9BE-AIX32-NEXT: blr @@ -249,15 +253,15 @@ ; P9LE-NEXT: li 6, 0 ; P9LE-NEXT: addi 3, 3, .LCPI2_0@toc@l ; P9LE-NEXT: mtvsrd 3, 6 +; P9LE-NEXT: lxv 0, 0(3) +; P9LE-NEXT: li 3, 0 ; P9LE-NEXT: vmrghh 4, 3, 4 ; P9LE-NEXT: vmrghh 2, 3, 2 ; P9LE-NEXT: vsplth 3, 3, 3 ; P9LE-NEXT: xxmrglw 3, 4, 3 -; P9LE-NEXT: lxv 4, 0(3) -; P9LE-NEXT: li 3, 0 -; P9LE-NEXT: vperm 2, 2, 3, 4 -; P9LE-NEXT: xxspltw 3, 2, 2 -; P9LE-NEXT: vadduwm 2, 2, 3 +; P9LE-NEXT: xxperm 3, 2, 0 +; P9LE-NEXT: xxspltw 2, 3, 2 +; P9LE-NEXT: vadduwm 2, 3, 2 ; P9LE-NEXT: vextuwrx 3, 3, 2 ; P9LE-NEXT: cmpw 3, 5 ; P9LE-NEXT: bgelr+ 0 @@ -268,24 +272,25 @@ ; P9BE-NEXT: sldi 4, 4, 1 ; P9BE-NEXT: li 7, 16 ; P9BE-NEXT: add 6, 3, 4 -; P9BE-NEXT: lxsihzx 5, 3, 4 -; P9BE-NEXT: addis 3, 2, .LCPI2_1@toc@ha -; P9BE-NEXT: lxsihzx 2, 6, 7 +; P9BE-NEXT: lxsihzx 0, 6, 7 ; P9BE-NEXT: addis 6, 2, .LCPI2_0@toc@ha -; P9BE-NEXT: addi 3, 3, .LCPI2_1@toc@l ; P9BE-NEXT: addi 6, 6, .LCPI2_0@toc@l -; P9BE-NEXT: lxv 3, 0(6) +; P9BE-NEXT: lxv 1, 0(6) ; P9BE-NEXT: li 6, 0 -; P9BE-NEXT: mtvsrwz 4, 6 -; P9BE-NEXT: vperm 2, 4, 2, 3 -; P9BE-NEXT: vperm 3, 4, 5, 3 -; P9BE-NEXT: vsplth 4, 4, 3 -; P9BE-NEXT: xxmrghw 3, 4, 3 -; P9BE-NEXT: lxv 4, 0(3) +; P9BE-NEXT: mtvsrwz 2, 6 +; P9BE-NEXT: vmr 3, 2 +; P9BE-NEXT: vsplth 4, 2, 3 +; P9BE-NEXT: xxperm 3, 0, 1 +; P9BE-NEXT: lxsihzx 0, 3, 4 +; P9BE-NEXT: addis 3, 2, .LCPI2_1@toc@ha +; P9BE-NEXT: addi 3, 3, .LCPI2_1@toc@l +; P9BE-NEXT: xxperm 2, 0, 1 +; P9BE-NEXT: lxv 1, 0(3) ; P9BE-NEXT: li 3, 0 -; P9BE-NEXT: vperm 2, 3, 2, 4 -; P9BE-NEXT: xxspltw 3, 2, 1 -; P9BE-NEXT: vadduwm 2, 2, 3 +; P9BE-NEXT: xxmrghw 0, 4, 2 +; P9BE-NEXT: xxperm 3, 0, 1 +; P9BE-NEXT: xxspltw 2, 3, 1 +; P9BE-NEXT: vadduwm 2, 3, 2 ; P9BE-NEXT: vextuwlx 3, 3, 2 ; P9BE-NEXT: cmpw 3, 5 ; P9BE-NEXT: bgelr+ 0 @@ -296,22 +301,23 @@ ; P9BE-AIX-NEXT: sldi 4, 4, 1 ; P9BE-AIX-NEXT: li 7, 16 ; P9BE-AIX-NEXT: add 6, 3, 4 -; P9BE-AIX-NEXT: lxsihzx 5, 3, 4 -; P9BE-AIX-NEXT: ld 3, L..C3(2) # %const.1 -; P9BE-AIX-NEXT: lxsihzx 2, 6, 7 -; P9BE-AIX-NEXT: ld 6, L..C4(2) # %const.0 -; P9BE-AIX-NEXT: lxv 3, 0(6) +; P9BE-AIX-NEXT: lxsihzx 0, 6, 7 +; P9BE-AIX-NEXT: ld 6, L..C3(2) # %const.0 +; P9BE-AIX-NEXT: lxv 1, 0(6) ; P9BE-AIX-NEXT: li 6, 0 -; P9BE-AIX-NEXT: mtvsrwz 4, 6 -; P9BE-AIX-NEXT: vperm 2, 4, 2, 3 -; P9BE-AIX-NEXT: vperm 3, 4, 5, 3 -; P9BE-AIX-NEXT: vsplth 4, 4, 3 -; P9BE-AIX-NEXT: xxmrghw 3, 4, 3 -; P9BE-AIX-NEXT: lxv 4, 0(3) +; P9BE-AIX-NEXT: mtvsrwz 2, 6 +; P9BE-AIX-NEXT: vmr 3, 2 +; P9BE-AIX-NEXT: vsplth 4, 2, 3 +; P9BE-AIX-NEXT: xxperm 3, 0, 1 +; P9BE-AIX-NEXT: lxsihzx 0, 3, 4 +; P9BE-AIX-NEXT: ld 3, L..C4(2) # %const.1 +; P9BE-AIX-NEXT: xxperm 2, 0, 1 +; P9BE-AIX-NEXT: lxv 1, 0(3) ; P9BE-AIX-NEXT: li 3, 0 -; P9BE-AIX-NEXT: vperm 2, 3, 2, 4 -; P9BE-AIX-NEXT: xxspltw 3, 2, 1 -; P9BE-AIX-NEXT: vadduwm 2, 2, 3 +; P9BE-AIX-NEXT: xxmrghw 0, 4, 2 +; P9BE-AIX-NEXT: xxperm 3, 0, 1 +; P9BE-AIX-NEXT: xxspltw 2, 3, 1 +; P9BE-AIX-NEXT: vadduwm 2, 3, 2 ; P9BE-AIX-NEXT: vextuwlx 3, 3, 2 ; P9BE-AIX-NEXT: cmpw 3, 5 ; P9BE-AIX-NEXT: bgelr+ 0 @@ -331,13 +337,13 @@ ; P9BE-AIX32-NEXT: lwz 3, L..C3(2) # %const.0 ; P9BE-AIX32-NEXT: lxv 3, -32(1) ; P9BE-AIX32-NEXT: vmrghh 4, 2, 4 +; P9BE-AIX32-NEXT: lxv 0, 0(3) ; P9BE-AIX32-NEXT: vmrghh 3, 2, 3 ; P9BE-AIX32-NEXT: vsplth 2, 2, 0 ; P9BE-AIX32-NEXT: xxmrghw 2, 2, 4 -; P9BE-AIX32-NEXT: lxv 4, 0(3) -; P9BE-AIX32-NEXT: vperm 2, 2, 3, 4 -; P9BE-AIX32-NEXT: xxspltw 3, 2, 1 -; P9BE-AIX32-NEXT: vadduwm 2, 2, 3 +; P9BE-AIX32-NEXT: xxperm 3, 2, 0 +; P9BE-AIX32-NEXT: xxspltw 2, 3, 1 +; P9BE-AIX32-NEXT: vadduwm 2, 3, 2 ; P9BE-AIX32-NEXT: stxv 2, -16(1) ; P9BE-AIX32-NEXT: lwz 3, -16(1) ; P9BE-AIX32-NEXT: cmpw 3, 5 @@ -389,13 +395,13 @@ ; P9LE-NEXT: vmrghb 2, 3, 2 ; P9LE-NEXT: addi 3, 3, .LCPI3_0@toc@l ; P9LE-NEXT: vmrglh 2, 2, 4 +; P9LE-NEXT: lxv 1, 0(3) +; P9LE-NEXT: li 3, 0 ; P9LE-NEXT: vmrghb 3, 3, 5 ; P9LE-NEXT: xxmrglw 2, 2, 4 ; P9LE-NEXT: vmrglh 3, 3, 4 -; P9LE-NEXT: xxmrglw 3, 4, 3 -; P9LE-NEXT: lxv 4, 0(3) -; P9LE-NEXT: li 3, 0 -; P9LE-NEXT: vperm 2, 3, 2, 4 +; P9LE-NEXT: xxmrglw 0, 4, 3 +; P9LE-NEXT: xxperm 2, 0, 1 ; P9LE-NEXT: xxspltw 3, 2, 2 ; P9LE-NEXT: vadduwm 2, 2, 3 ; P9LE-NEXT: vextuwrx 3, 3, 2 @@ -407,24 +413,27 @@ ; P9BE: # %bb.0: # %entry ; P9BE-NEXT: add 6, 3, 4 ; P9BE-NEXT: li 7, 8 -; P9BE-NEXT: lxsibzx 5, 3, 4 -; P9BE-NEXT: addis 3, 2, .LCPI3_1@toc@ha -; P9BE-NEXT: lxsibzx 2, 6, 7 +; P9BE-NEXT: lxsibzx 0, 6, 7 ; P9BE-NEXT: addis 6, 2, .LCPI3_0@toc@ha -; P9BE-NEXT: addi 3, 3, .LCPI3_1@toc@l ; P9BE-NEXT: addi 6, 6, .LCPI3_0@toc@l -; P9BE-NEXT: lxv 3, 0(6) +; P9BE-NEXT: lxv 1, 0(6) ; P9BE-NEXT: li 6, 0 -; P9BE-NEXT: mtvsrwz 4, 6 -; P9BE-NEXT: vperm 2, 4, 2, 3 -; P9BE-NEXT: vperm 3, 4, 5, 3 -; P9BE-NEXT: vspltb 4, 4, 7 -; P9BE-NEXT: vmrghh 3, 3, 4 -; P9BE-NEXT: xxspltw 4, 4, 0 -; P9BE-NEXT: xxmrghw 2, 3, 2 -; P9BE-NEXT: lxv 3, 0(3) +; P9BE-NEXT: mtvsrwz 2, 6 +; P9BE-NEXT: vspltb 3, 2, 7 +; P9BE-NEXT: xxperm 0, 2, 1 +; P9BE-NEXT: lxsibzx 1, 3, 4 +; P9BE-NEXT: addis 3, 2, .LCPI3_1@toc@ha +; P9BE-NEXT: addi 3, 3, .LCPI3_1@toc@l +; P9BE-NEXT: lxv 2, 0(3) +; P9BE-NEXT: addis 3, 2, .LCPI3_2@toc@ha +; P9BE-NEXT: addi 3, 3, .LCPI3_2@toc@l +; P9BE-NEXT: xxperm 2, 1, 2 +; P9BE-NEXT: xxspltw 1, 3, 0 +; P9BE-NEXT: vmrghh 2, 2, 3 +; P9BE-NEXT: xxmrghw 2, 2, 0 +; P9BE-NEXT: lxv 0, 0(3) ; P9BE-NEXT: li 3, 0 -; P9BE-NEXT: vperm 2, 4, 2, 3 +; P9BE-NEXT: xxperm 2, 1, 0 ; P9BE-NEXT: xxspltw 3, 2, 1 ; P9BE-NEXT: vadduwm 2, 2, 3 ; P9BE-NEXT: vextuwlx 3, 3, 2 @@ -436,22 +445,24 @@ ; P9BE-AIX: # %bb.0: # %entry ; P9BE-AIX-NEXT: add 6, 3, 4 ; P9BE-AIX-NEXT: li 7, 8 -; P9BE-AIX-NEXT: lxsibzx 5, 3, 4 -; P9BE-AIX-NEXT: ld 3, L..C5(2) # %const.1 -; P9BE-AIX-NEXT: lxsibzx 2, 6, 7 -; P9BE-AIX-NEXT: ld 6, L..C6(2) # %const.0 -; P9BE-AIX-NEXT: lxv 3, 0(6) +; P9BE-AIX-NEXT: lxsibzx 0, 6, 7 +; P9BE-AIX-NEXT: ld 6, L..C5(2) # %const.0 +; P9BE-AIX-NEXT: lxv 1, 0(6) ; P9BE-AIX-NEXT: li 6, 0 -; P9BE-AIX-NEXT: mtvsrwz 4, 6 -; P9BE-AIX-NEXT: vperm 2, 4, 2, 3 -; P9BE-AIX-NEXT: vperm 3, 4, 5, 3 -; P9BE-AIX-NEXT: vspltb 4, 4, 7 -; P9BE-AIX-NEXT: vmrghh 3, 3, 4 -; P9BE-AIX-NEXT: xxspltw 4, 4, 0 -; P9BE-AIX-NEXT: xxmrghw 2, 3, 2 -; P9BE-AIX-NEXT: lxv 3, 0(3) +; P9BE-AIX-NEXT: mtvsrwz 2, 6 +; P9BE-AIX-NEXT: vspltb 3, 2, 7 +; P9BE-AIX-NEXT: xxperm 0, 2, 1 +; P9BE-AIX-NEXT: lxsibzx 1, 3, 4 +; P9BE-AIX-NEXT: ld 3, L..C6(2) # %const.1 +; P9BE-AIX-NEXT: lxv 2, 0(3) +; P9BE-AIX-NEXT: ld 3, L..C7(2) # %const.2 +; P9BE-AIX-NEXT: xxperm 2, 1, 2 +; P9BE-AIX-NEXT: xxspltw 1, 3, 0 +; P9BE-AIX-NEXT: vmrghh 2, 2, 3 +; P9BE-AIX-NEXT: xxmrghw 2, 2, 0 +; P9BE-AIX-NEXT: lxv 0, 0(3) ; P9BE-AIX-NEXT: li 3, 0 -; P9BE-AIX-NEXT: vperm 2, 4, 2, 3 +; P9BE-AIX-NEXT: xxperm 2, 1, 0 ; P9BE-AIX-NEXT: xxspltw 3, 2, 1 ; P9BE-AIX-NEXT: vadduwm 2, 2, 3 ; P9BE-AIX-NEXT: vextuwlx 3, 3, 2 @@ -463,21 +474,23 @@ ; P9BE-AIX32: # %bb.0: # %entry ; P9BE-AIX32-NEXT: add 6, 3, 4 ; P9BE-AIX32-NEXT: li 7, 8 -; P9BE-AIX32-NEXT: lxsibzx 5, 3, 4 -; P9BE-AIX32-NEXT: lwz 3, L..C4(2) # %const.1 -; P9BE-AIX32-NEXT: lxsibzx 2, 6, 7 -; P9BE-AIX32-NEXT: lwz 6, L..C5(2) # %const.0 -; P9BE-AIX32-NEXT: lxv 3, 0(6) +; P9BE-AIX32-NEXT: lxsibzx 0, 6, 7 +; P9BE-AIX32-NEXT: lwz 6, L..C4(2) # %const.0 +; P9BE-AIX32-NEXT: lxv 1, 0(6) ; P9BE-AIX32-NEXT: li 6, 0 -; P9BE-AIX32-NEXT: mtvsrwz 4, 6 -; P9BE-AIX32-NEXT: vperm 2, 4, 2, 3 -; P9BE-AIX32-NEXT: vperm 3, 4, 5, 3 -; P9BE-AIX32-NEXT: vspltb 4, 4, 7 -; P9BE-AIX32-NEXT: vmrghh 3, 3, 4 -; P9BE-AIX32-NEXT: xxspltw 4, 4, 0 -; P9BE-AIX32-NEXT: xxmrghw 2, 3, 2 -; P9BE-AIX32-NEXT: lxv 3, 0(3) -; P9BE-AIX32-NEXT: vperm 2, 4, 2, 3 +; P9BE-AIX32-NEXT: mtvsrwz 2, 6 +; P9BE-AIX32-NEXT: vspltb 3, 2, 7 +; P9BE-AIX32-NEXT: xxperm 0, 2, 1 +; P9BE-AIX32-NEXT: lxsibzx 1, 3, 4 +; P9BE-AIX32-NEXT: lwz 3, L..C5(2) # %const.1 +; P9BE-AIX32-NEXT: lxv 2, 0(3) +; P9BE-AIX32-NEXT: lwz 3, L..C6(2) # %const.2 +; P9BE-AIX32-NEXT: xxperm 2, 1, 2 +; P9BE-AIX32-NEXT: xxspltw 1, 3, 0 +; P9BE-AIX32-NEXT: vmrghh 2, 2, 3 +; P9BE-AIX32-NEXT: xxmrghw 2, 2, 0 +; P9BE-AIX32-NEXT: lxv 0, 0(3) +; P9BE-AIX32-NEXT: xxperm 2, 1, 0 ; P9BE-AIX32-NEXT: xxspltw 3, 2, 1 ; P9BE-AIX32-NEXT: vadduwm 2, 2, 3 ; P9BE-AIX32-NEXT: stxv 2, -16(1) diff --git a/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll b/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll --- a/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll +++ b/llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll @@ -81,7 +81,7 @@ ; P9BE-NEXT: mulli r4, r4, -124 ; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: lis r4, -21386 -; P9BE-NEXT: mtvsrwz v3, r3 +; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: ori r4, r4, 37253 ; P9BE-NEXT: vextuhlx r3, r3, v2 @@ -94,15 +94,15 @@ ; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: lis r4, -16728 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; P9BE-NEXT: ori r4, r4, 63249 ; P9BE-NEXT: addi r3, r3, .LCPI0_0@toc@l -; P9BE-NEXT: lxv v5, 0(r3) +; P9BE-NEXT: lxv vs2, 0(r3) ; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: extsh r3, r3 -; P9BE-NEXT: vperm v3, v4, v3, v5 +; P9BE-NEXT: xxperm vs0, vs1, vs2 ; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: srwi r5, r4, 31 ; P9BE-NEXT: srawi r4, r4, 8 @@ -110,7 +110,7 @@ ; P9BE-NEXT: mulli r4, r4, -1003 ; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: lis r4, 21399 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: ori r4, r4, 33437 ; P9BE-NEXT: vextuhlx r3, r3, v2 @@ -121,9 +121,9 @@ ; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: mulli r4, r4, 98 ; P9BE-NEXT: sub r3, r3, r4 -; P9BE-NEXT: mtvsrwz v2, r3 -; P9BE-NEXT: vperm v2, v2, v4, v5 -; P9BE-NEXT: xxmrghw v2, v3, v2 +; P9BE-NEXT: mtfprwz f3, r3 +; P9BE-NEXT: xxperm vs1, vs3, vs2 +; P9BE-NEXT: xxmrghw v2, vs0, vs1 ; P9BE-NEXT: blr ; ; P8LE-LABEL: fold_srem_vec_1: @@ -309,7 +309,7 @@ ; P9BE-NEXT: add r5, r5, r6 ; P9BE-NEXT: mulli r5, r5, 95 ; P9BE-NEXT: sub r3, r3, r5 -; P9BE-NEXT: mtvsrwz v3, r3 +; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: extsh r3, r3 @@ -320,14 +320,14 @@ ; P9BE-NEXT: add r5, r5, r6 ; P9BE-NEXT: mulli r5, r5, 95 ; P9BE-NEXT: sub r3, r3, r5 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; P9BE-NEXT: lxv v5, 0(r3) +; P9BE-NEXT: lxv vs2, 0(r3) ; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: extsh r3, r3 -; P9BE-NEXT: vperm v3, v4, v3, v5 +; P9BE-NEXT: xxperm vs0, vs1, vs2 ; P9BE-NEXT: mulhw r5, r3, r4 ; P9BE-NEXT: add r5, r5, r3 ; P9BE-NEXT: srwi r6, r5, 31 @@ -335,7 +335,7 @@ ; P9BE-NEXT: add r5, r5, r6 ; P9BE-NEXT: mulli r5, r5, 95 ; P9BE-NEXT: sub r3, r3, r5 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: extsh r3, r3 @@ -346,9 +346,9 @@ ; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: sub r3, r3, r4 -; P9BE-NEXT: mtvsrwz v2, r3 -; P9BE-NEXT: vperm v2, v2, v4, v5 -; P9BE-NEXT: xxmrghw v2, v2, v3 +; P9BE-NEXT: mtfprwz f3, r3 +; P9BE-NEXT: xxperm vs1, vs3, vs2 +; P9BE-NEXT: xxmrghw v2, vs1, vs0 ; P9BE-NEXT: blr ; ; P8LE-LABEL: fold_srem_vec_2: @@ -536,7 +536,7 @@ ; P9BE-NEXT: add r4, r4, r6 ; P9BE-NEXT: mulli r6, r4, 95 ; P9BE-NEXT: sub r3, r3, r6 -; P9BE-NEXT: mtvsrwz v3, r3 +; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: extsh r6, r3 @@ -547,14 +547,14 @@ ; P9BE-NEXT: add r6, r6, r7 ; P9BE-NEXT: mulli r7, r6, 95 ; P9BE-NEXT: sub r3, r3, r7 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI2_0@toc@l -; P9BE-NEXT: lxv v5, 0(r3) +; P9BE-NEXT: lxv vs2, 0(r3) ; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: extsh r7, r3 -; P9BE-NEXT: vperm v3, v4, v3, v5 +; P9BE-NEXT: xxperm vs0, vs1, vs2 ; P9BE-NEXT: mulhw r8, r7, r5 ; P9BE-NEXT: add r7, r8, r7 ; P9BE-NEXT: srwi r8, r7, 31 @@ -562,7 +562,7 @@ ; P9BE-NEXT: add r7, r7, r8 ; P9BE-NEXT: mulli r8, r7, 95 ; P9BE-NEXT: sub r3, r3, r8 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: extsh r3, r3 @@ -572,17 +572,17 @@ ; P9BE-NEXT: srawi r5, r5, 6 ; P9BE-NEXT: add r5, r5, r8 ; P9BE-NEXT: mulli r8, r5, 95 -; P9BE-NEXT: mtvsrwz v0, r5 ; P9BE-NEXT: sub r3, r3, r8 -; P9BE-NEXT: mtvsrwz v2, r3 -; P9BE-NEXT: vperm v2, v2, v4, v5 -; P9BE-NEXT: mtvsrwz v4, r6 -; P9BE-NEXT: xxmrghw v2, v2, v3 -; P9BE-NEXT: mtvsrwz v3, r4 -; P9BE-NEXT: vperm v3, v4, v3, v5 -; P9BE-NEXT: mtvsrwz v4, r7 -; P9BE-NEXT: vperm v4, v0, v4, v5 -; P9BE-NEXT: xxmrghw v3, v4, v3 +; P9BE-NEXT: mtfprwz f3, r3 +; P9BE-NEXT: xxperm vs1, vs3, vs2 +; P9BE-NEXT: mtfprwz f3, r5 +; P9BE-NEXT: xxmrghw v2, vs1, vs0 +; P9BE-NEXT: mtfprwz f0, r4 +; P9BE-NEXT: mtfprwz f1, r6 +; P9BE-NEXT: xxperm vs0, vs1, vs2 +; P9BE-NEXT: mtfprwz f1, r7 +; P9BE-NEXT: xxperm vs1, vs3, vs2 +; P9BE-NEXT: xxmrghw v3, vs1, vs0 ; P9BE-NEXT: vadduhm v2, v2, v3 ; P9BE-NEXT: blr ; @@ -768,7 +768,7 @@ ; P9BE-NEXT: addze r4, r4 ; P9BE-NEXT: slwi r4, r4, 5 ; P9BE-NEXT: sub r3, r3, r4 -; P9BE-NEXT: mtvsrwz v3, r3 +; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: extsh r3, r3 @@ -777,15 +777,15 @@ ; P9BE-NEXT: slwi r4, r4, 6 ; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: lis r4, -21386 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; P9BE-NEXT: ori r4, r4, 37253 ; P9BE-NEXT: addi r3, r3, .LCPI3_0@toc@l -; P9BE-NEXT: lxv v5, 0(r3) +; P9BE-NEXT: lxv vs2, 0(r3) ; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: extsh r3, r3 -; P9BE-NEXT: vperm v3, v4, v3, v5 +; P9BE-NEXT: xxperm vs0, vs1, vs2 ; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: add r4, r4, r3 ; P9BE-NEXT: srwi r5, r4, 31 @@ -793,7 +793,7 @@ ; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: sub r3, r3, r4 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: extsh r3, r3 @@ -801,9 +801,9 @@ ; P9BE-NEXT: addze r4, r4 ; P9BE-NEXT: slwi r4, r4, 3 ; P9BE-NEXT: sub r3, r3, r4 -; P9BE-NEXT: mtvsrwz v2, r3 -; P9BE-NEXT: vperm v2, v2, v4, v5 -; P9BE-NEXT: xxmrghw v2, v3, v2 +; P9BE-NEXT: mtfprwz f3, r3 +; P9BE-NEXT: xxperm vs1, vs3, vs2 +; P9BE-NEXT: xxmrghw v2, vs0, vs1 ; P9BE-NEXT: blr ; ; P8LE-LABEL: dont_fold_srem_power_of_two: @@ -959,7 +959,7 @@ ; P9BE-NEXT: mulli r4, r4, 23 ; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: lis r4, 24749 -; P9BE-NEXT: mtvsrwz v3, r3 +; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: ori r4, r4, 47143 ; P9BE-NEXT: vextuhlx r3, r3, v2 @@ -971,15 +971,15 @@ ; P9BE-NEXT: mulli r4, r4, 5423 ; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: lis r4, -14230 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; P9BE-NEXT: ori r4, r4, 30865 ; P9BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; P9BE-NEXT: lxv v5, 0(r3) +; P9BE-NEXT: lxv vs2, 0(r3) ; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: extsh r3, r3 -; P9BE-NEXT: vperm v3, v3, v4, v5 +; P9BE-NEXT: xxperm vs1, vs0, vs2 ; P9BE-NEXT: mulhw r4, r3, r4 ; P9BE-NEXT: add r4, r4, r3 ; P9BE-NEXT: srwi r5, r4, 31 @@ -987,11 +987,11 @@ ; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: mulli r4, r4, 654 ; P9BE-NEXT: sub r3, r3, r4 -; P9BE-NEXT: mtvsrwz v2, r3 +; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: li r3, 0 -; P9BE-NEXT: mtvsrwz v4, r3 -; P9BE-NEXT: vperm v2, v4, v2, v5 -; P9BE-NEXT: xxmrghw v2, v2, v3 +; P9BE-NEXT: mtfprwz f3, r3 +; P9BE-NEXT: xxperm vs0, vs3, vs2 +; P9BE-NEXT: xxmrghw v2, vs0, vs1 ; P9BE-NEXT: blr ; ; P8LE-LABEL: dont_fold_srem_one: @@ -1150,7 +1150,7 @@ ; P9BE-NEXT: mulli r4, r4, 23 ; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: lis r4, 24749 -; P9BE-NEXT: mtvsrwz v3, r3 +; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: ori r4, r4, 47143 ; P9BE-NEXT: vextuhlx r3, r3, v2 @@ -1161,23 +1161,23 @@ ; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: mulli r4, r4, 5423 ; P9BE-NEXT: sub r3, r3, r4 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; P9BE-NEXT: lxv v5, 0(r3) +; P9BE-NEXT: lxv vs2, 0(r3) ; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: extsh r3, r3 -; P9BE-NEXT: vperm v3, v3, v4, v5 +; P9BE-NEXT: xxperm vs1, vs0, vs2 ; P9BE-NEXT: srawi r4, r3, 15 ; P9BE-NEXT: addze r4, r4 ; P9BE-NEXT: slwi r4, r4, 15 ; P9BE-NEXT: sub r3, r3, r4 -; P9BE-NEXT: mtvsrwz v2, r3 +; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: li r3, 0 -; P9BE-NEXT: mtvsrwz v4, r3 -; P9BE-NEXT: vperm v2, v4, v2, v5 -; P9BE-NEXT: xxmrghw v2, v2, v3 +; P9BE-NEXT: mtfprwz f3, r3 +; P9BE-NEXT: xxperm vs0, vs3, vs2 +; P9BE-NEXT: xxmrghw v2, vs0, vs1 ; P9BE-NEXT: blr ; ; P8LE-LABEL: dont_fold_urem_i16_smax: diff --git a/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll b/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll --- a/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll +++ b/llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll @@ -74,7 +74,7 @@ ; P9BE-NEXT: mulli r4, r4, 1003 ; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: lis r4, 21399 -; P9BE-NEXT: mtvsrwz v3, r3 +; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: ori r4, r4, 33437 ; P9BE-NEXT: vextuhlx r3, r3, v2 @@ -83,21 +83,21 @@ ; P9BE-NEXT: srwi r4, r4, 5 ; P9BE-NEXT: mulli r4, r4, 98 ; P9BE-NEXT: sub r3, r3, r4 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI0_0@toc@l -; P9BE-NEXT: lxv v5, 0(r3) +; P9BE-NEXT: lxv vs2, 0(r3) ; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: clrlwi r4, r3, 16 ; P9BE-NEXT: rlwinm r3, r3, 30, 18, 31 -; P9BE-NEXT: vperm v3, v4, v3, v5 +; P9BE-NEXT: xxperm vs0, vs1, vs2 ; P9BE-NEXT: mulhwu r3, r3, r5 ; P9BE-NEXT: srwi r3, r3, 2 ; P9BE-NEXT: mulli r3, r3, 124 ; P9BE-NEXT: sub r3, r4, r3 ; P9BE-NEXT: lis r4, 22765 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: ori r4, r4, 8969 ; P9BE-NEXT: vextuhlx r3, r3, v2 @@ -109,9 +109,9 @@ ; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: sub r3, r3, r4 -; P9BE-NEXT: mtvsrwz v2, r3 -; P9BE-NEXT: vperm v2, v2, v4, v5 -; P9BE-NEXT: xxmrghw v2, v2, v3 +; P9BE-NEXT: mtfprwz f3, r3 +; P9BE-NEXT: xxperm vs1, vs3, vs2 +; P9BE-NEXT: xxmrghw v2, vs1, vs0 ; P9BE-NEXT: blr ; ; P8LE-LABEL: fold_urem_vec_1: @@ -285,7 +285,7 @@ ; P9BE-NEXT: srwi r5, r5, 6 ; P9BE-NEXT: mulli r5, r5, 95 ; P9BE-NEXT: sub r3, r3, r5 -; P9BE-NEXT: mtvsrwz v3, r3 +; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: clrlwi r3, r3, 16 @@ -296,14 +296,14 @@ ; P9BE-NEXT: srwi r5, r5, 6 ; P9BE-NEXT: mulli r5, r5, 95 ; P9BE-NEXT: sub r3, r3, r5 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; P9BE-NEXT: lxv v5, 0(r3) +; P9BE-NEXT: lxv vs2, 0(r3) ; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: clrlwi r3, r3, 16 -; P9BE-NEXT: vperm v3, v4, v3, v5 +; P9BE-NEXT: xxperm vs0, vs1, vs2 ; P9BE-NEXT: mulhwu r5, r3, r4 ; P9BE-NEXT: sub r6, r3, r5 ; P9BE-NEXT: srwi r6, r6, 1 @@ -311,7 +311,7 @@ ; P9BE-NEXT: srwi r5, r5, 6 ; P9BE-NEXT: mulli r5, r5, 95 ; P9BE-NEXT: sub r3, r3, r5 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: clrlwi r3, r3, 16 @@ -322,9 +322,9 @@ ; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: sub r3, r3, r4 -; P9BE-NEXT: mtvsrwz v2, r3 -; P9BE-NEXT: vperm v2, v2, v4, v5 -; P9BE-NEXT: xxmrghw v2, v2, v3 +; P9BE-NEXT: mtfprwz f3, r3 +; P9BE-NEXT: xxperm vs1, vs3, vs2 +; P9BE-NEXT: xxmrghw v2, vs1, vs0 ; P9BE-NEXT: blr ; ; P8LE-LABEL: fold_urem_vec_2: @@ -512,7 +512,7 @@ ; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: mulli r6, r4, 95 ; P9BE-NEXT: sub r3, r3, r6 -; P9BE-NEXT: mtvsrwz v3, r3 +; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: clrlwi r6, r3, 16 @@ -523,14 +523,14 @@ ; P9BE-NEXT: srwi r6, r6, 6 ; P9BE-NEXT: mulli r7, r6, 95 ; P9BE-NEXT: sub r3, r3, r7 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI2_0@toc@l -; P9BE-NEXT: lxv v5, 0(r3) +; P9BE-NEXT: lxv vs2, 0(r3) ; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: clrlwi r7, r3, 16 -; P9BE-NEXT: vperm v3, v4, v3, v5 +; P9BE-NEXT: xxperm vs0, vs1, vs2 ; P9BE-NEXT: mulhwu r8, r7, r5 ; P9BE-NEXT: sub r7, r7, r8 ; P9BE-NEXT: srwi r7, r7, 1 @@ -538,7 +538,7 @@ ; P9BE-NEXT: srwi r7, r7, 6 ; P9BE-NEXT: mulli r8, r7, 95 ; P9BE-NEXT: sub r3, r3, r8 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: clrlwi r3, r3, 16 @@ -548,17 +548,17 @@ ; P9BE-NEXT: add r5, r8, r5 ; P9BE-NEXT: srwi r5, r5, 6 ; P9BE-NEXT: mulli r8, r5, 95 -; P9BE-NEXT: mtvsrwz v0, r5 ; P9BE-NEXT: sub r3, r3, r8 -; P9BE-NEXT: mtvsrwz v2, r3 -; P9BE-NEXT: vperm v2, v2, v4, v5 -; P9BE-NEXT: mtvsrwz v4, r6 -; P9BE-NEXT: xxmrghw v2, v2, v3 -; P9BE-NEXT: mtvsrwz v3, r4 -; P9BE-NEXT: vperm v3, v4, v3, v5 -; P9BE-NEXT: mtvsrwz v4, r7 -; P9BE-NEXT: vperm v4, v0, v4, v5 -; P9BE-NEXT: xxmrghw v3, v4, v3 +; P9BE-NEXT: mtfprwz f3, r3 +; P9BE-NEXT: xxperm vs1, vs3, vs2 +; P9BE-NEXT: mtfprwz f3, r5 +; P9BE-NEXT: xxmrghw v2, vs1, vs0 +; P9BE-NEXT: mtfprwz f0, r4 +; P9BE-NEXT: mtfprwz f1, r6 +; P9BE-NEXT: xxperm vs0, vs1, vs2 +; P9BE-NEXT: mtfprwz f1, r7 +; P9BE-NEXT: xxperm vs1, vs3, vs2 +; P9BE-NEXT: xxmrghw v3, vs1, vs0 ; P9BE-NEXT: vadduhm v2, v2, v3 ; P9BE-NEXT: blr ; @@ -730,18 +730,18 @@ ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: ori r4, r4, 8969 ; P9BE-NEXT: clrlwi r3, r3, 27 -; P9BE-NEXT: mtvsrwz v3, r3 +; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: clrlwi r3, r3, 26 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI3_0@toc@l -; P9BE-NEXT: lxv v5, 0(r3) +; P9BE-NEXT: lxv vs2, 0(r3) ; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: clrlwi r3, r3, 16 -; P9BE-NEXT: vperm v3, v4, v3, v5 +; P9BE-NEXT: xxperm vs0, vs1, vs2 ; P9BE-NEXT: mulhwu r4, r3, r4 ; P9BE-NEXT: sub r5, r3, r4 ; P9BE-NEXT: srwi r5, r5, 1 @@ -749,13 +749,13 @@ ; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: sub r3, r3, r4 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: clrlwi r3, r3, 29 -; P9BE-NEXT: mtvsrwz v2, r3 -; P9BE-NEXT: vperm v2, v2, v4, v5 -; P9BE-NEXT: xxmrghw v2, v3, v2 +; P9BE-NEXT: mtfprwz f3, r3 +; P9BE-NEXT: xxperm vs1, vs3, vs2 +; P9BE-NEXT: xxmrghw v2, vs0, vs1 ; P9BE-NEXT: blr ; ; P8LE-LABEL: dont_fold_urem_power_of_two: @@ -879,7 +879,7 @@ ; P9BE-NEXT: mulli r4, r4, 5423 ; P9BE-NEXT: sub r3, r3, r4 ; P9BE-NEXT: lis r4, -19946 -; P9BE-NEXT: mtvsrwz v3, r3 +; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: ori r4, r4, 17097 ; P9BE-NEXT: vextuhlx r3, r3, v2 @@ -888,24 +888,24 @@ ; P9BE-NEXT: srwi r4, r4, 4 ; P9BE-NEXT: mulli r4, r4, 23 ; P9BE-NEXT: sub r3, r3, r4 -; P9BE-NEXT: mtvsrwz v4, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; P9BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; P9BE-NEXT: lxv v5, 0(r3) +; P9BE-NEXT: lxv vs2, 0(r3) ; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: clrlwi r4, r3, 16 ; P9BE-NEXT: rlwinm r3, r3, 31, 17, 31 -; P9BE-NEXT: vperm v3, v4, v3, v5 +; P9BE-NEXT: xxperm vs0, vs1, vs2 ; P9BE-NEXT: mulhwu r3, r3, r5 ; P9BE-NEXT: srwi r3, r3, 8 ; P9BE-NEXT: mulli r3, r3, 654 ; P9BE-NEXT: sub r3, r4, r3 -; P9BE-NEXT: mtvsrwz v2, r3 +; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: li r3, 0 -; P9BE-NEXT: mtvsrwz v4, r3 -; P9BE-NEXT: vperm v2, v4, v2, v5 -; P9BE-NEXT: xxmrghw v2, v2, v3 +; P9BE-NEXT: mtfprwz f3, r3 +; P9BE-NEXT: xxperm vs1, vs3, vs2 +; P9BE-NEXT: xxmrghw v2, vs1, vs0 ; P9BE-NEXT: blr ; ; P8LE-LABEL: dont_fold_urem_one: diff --git a/llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll b/llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll --- a/llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll +++ b/llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll @@ -57,11 +57,11 @@ ; CHECK-BE-P9-LABEL: test_v16i8_v16i8: ; CHECK-BE-P9: # %bb.0: # %entry ; CHECK-BE-P9-NEXT: addis r5, r2, .LCPI0_0@toc@ha -; CHECK-BE-P9-NEXT: lxsibzx v3, 0, r4 -; CHECK-BE-P9-NEXT: lxsibzx v4, 0, r3 +; CHECK-BE-P9-NEXT: lxsibzx v2, 0, r4 +; CHECK-BE-P9-NEXT: lxsibzx f1, 0, r3 ; CHECK-BE-P9-NEXT: addi r5, r5, .LCPI0_0@toc@l -; CHECK-BE-P9-NEXT: lxv v2, 0(r5) -; CHECK-BE-P9-NEXT: vperm v2, v4, v3, v2 +; CHECK-BE-P9-NEXT: lxv vs0, 0(r5) +; CHECK-BE-P9-NEXT: xxperm v2, vs1, vs0 ; CHECK-BE-P9-NEXT: blr ; ; CHECK-AIX-64-P8-LABEL: test_v16i8_v16i8: @@ -78,10 +78,10 @@ ; CHECK-AIX-64-P9-LABEL: test_v16i8_v16i8: ; CHECK-AIX-64-P9: # %bb.0: # %entry ; CHECK-AIX-64-P9-NEXT: ld r5, L..C0(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: lxsibzx v3, 0, r4 -; CHECK-AIX-64-P9-NEXT: lxsibzx v4, 0, r3 -; CHECK-AIX-64-P9-NEXT: lxv v2, 0(r5) -; CHECK-AIX-64-P9-NEXT: vperm v2, v4, v3, v2 +; CHECK-AIX-64-P9-NEXT: lxsibzx v2, 0, r4 +; CHECK-AIX-64-P9-NEXT: lxsibzx f1, 0, r3 +; CHECK-AIX-64-P9-NEXT: lxv vs0, 0(r5) +; CHECK-AIX-64-P9-NEXT: xxperm v2, vs1, vs0 ; CHECK-AIX-64-P9-NEXT: blr ; ; CHECK-AIX-32-P8-LABEL: test_v16i8_v16i8: @@ -98,10 +98,10 @@ ; CHECK-AIX-32-P9-LABEL: test_v16i8_v16i8: ; CHECK-AIX-32-P9: # %bb.0: # %entry ; CHECK-AIX-32-P9-NEXT: lwz r5, L..C0(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxsibzx v3, 0, r4 -; CHECK-AIX-32-P9-NEXT: lxsibzx v4, 0, r3 -; CHECK-AIX-32-P9-NEXT: lxv v2, 0(r5) -; CHECK-AIX-32-P9-NEXT: vperm v2, v4, v3, v2 +; CHECK-AIX-32-P9-NEXT: lxsibzx v2, 0, r4 +; CHECK-AIX-32-P9-NEXT: lxsibzx f1, 0, r3 +; CHECK-AIX-32-P9-NEXT: lxv vs0, 0(r5) +; CHECK-AIX-32-P9-NEXT: xxperm v2, vs1, vs0 ; CHECK-AIX-32-P9-NEXT: blr entry: %0 = load <1 x i8>, ptr %a, align 4 @@ -184,23 +184,22 @@ ; CHECK-LE-P8-LABEL: test_none_v16i8: ; CHECK-LE-P8: # %bb.0: # %entry ; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha -; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r4 +; CHECK-LE-P8-NEXT: lxvd2x v2, 0, r4 ; CHECK-LE-P8-NEXT: mtvsrd v4, r3 ; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l -; CHECK-LE-P8-NEXT: lxvd2x vs1, 0, r5 -; CHECK-LE-P8-NEXT: xxswapd v2, vs0 -; CHECK-LE-P8-NEXT: xxswapd v3, vs1 +; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r5 +; CHECK-LE-P8-NEXT: xxswapd v3, vs0 ; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-LE-P8-NEXT: blr ; ; CHECK-LE-P9-LABEL: test_none_v16i8: ; CHECK-LE-P9: # %bb.0: # %entry -; CHECK-LE-P9-NEXT: mtvsrd v3, r3 +; CHECK-LE-P9-NEXT: mtfprd f0, r3 ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-LE-P9-NEXT: lxv v2, 0(r4) ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) -; CHECK-LE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-LE-P9-NEXT: blr ; ; CHECK-BE-P8-LABEL: test_none_v16i8: @@ -215,12 +214,12 @@ ; ; CHECK-BE-P9-LABEL: test_none_v16i8: ; CHECK-BE-P9: # %bb.0: # %entry -; CHECK-BE-P9-NEXT: mtvsrwz v3, r3 +; CHECK-BE-P9-NEXT: mtfprwz f0, r3 ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-BE-P9-NEXT: lxv v2, 0(r4) ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-BE-P9-NEXT: blr ; ; CHECK-AIX-64-P8-LABEL: test_none_v16i8: @@ -234,11 +233,11 @@ ; ; CHECK-AIX-64-P9-LABEL: test_none_v16i8: ; CHECK-AIX-64-P9: # %bb.0: # %entry -; CHECK-AIX-64-P9-NEXT: mtvsrwz v3, r3 +; CHECK-AIX-64-P9-NEXT: mtfprwz f0, r3 ; CHECK-AIX-64-P9-NEXT: ld r3, L..C1(r2) # %const.0 ; CHECK-AIX-64-P9-NEXT: lxv v2, 0(r4) -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-64-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-64-P9-NEXT: blr ; ; CHECK-AIX-32-P8-LABEL: test_none_v16i8: @@ -432,23 +431,22 @@ ; CHECK-LE-P8-LABEL: test_none_v8i16: ; CHECK-LE-P8: # %bb.0: # %entry ; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha -; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r4 +; CHECK-LE-P8-NEXT: lxvd2x v2, 0, r4 ; CHECK-LE-P8-NEXT: mtvsrd v4, r3 ; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l -; CHECK-LE-P8-NEXT: lxvd2x vs1, 0, r5 -; CHECK-LE-P8-NEXT: xxswapd v2, vs0 -; CHECK-LE-P8-NEXT: xxswapd v3, vs1 +; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r5 +; CHECK-LE-P8-NEXT: xxswapd v3, vs0 ; CHECK-LE-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-LE-P8-NEXT: blr ; ; CHECK-LE-P9-LABEL: test_none_v8i16: ; CHECK-LE-P9: # %bb.0: # %entry -; CHECK-LE-P9-NEXT: mtvsrd v3, r3 +; CHECK-LE-P9-NEXT: mtfprd f0, r3 ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-LE-P9-NEXT: lxv v2, 0(r4) ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) -; CHECK-LE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-LE-P9-NEXT: blr ; ; CHECK-BE-P8-LABEL: test_none_v8i16: @@ -463,12 +461,12 @@ ; ; CHECK-BE-P9-LABEL: test_none_v8i16: ; CHECK-BE-P9: # %bb.0: # %entry -; CHECK-BE-P9-NEXT: mtvsrwz v3, r3 +; CHECK-BE-P9-NEXT: mtfprwz f0, r3 ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-BE-P9-NEXT: lxv v2, 0(r4) ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-BE-P9-NEXT: blr ; ; CHECK-AIX-64-P8-LABEL: test_none_v8i16: @@ -482,11 +480,11 @@ ; ; CHECK-AIX-64-P9-LABEL: test_none_v8i16: ; CHECK-AIX-64-P9: # %bb.0: # %entry -; CHECK-AIX-64-P9-NEXT: mtvsrwz v3, r3 +; CHECK-AIX-64-P9-NEXT: mtfprwz f0, r3 ; CHECK-AIX-64-P9-NEXT: ld r3, L..C2(r2) # %const.0 ; CHECK-AIX-64-P9-NEXT: lxv v2, 0(r4) -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-64-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-64-P9-NEXT: blr ; ; CHECK-AIX-32-P8-LABEL: test_none_v8i16: @@ -845,9 +843,9 @@ ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI10_0@toc@ha ; CHECK-LE-P9-NEXT: lxsibzx v3, 0, r4 ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI10_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) +; CHECK-LE-P9-NEXT: lxv vs0, 0(r3) ; CHECK-LE-P9-NEXT: vspltb v3, v3, 7 -; CHECK-LE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-LE-P9-NEXT: xxperm v2, v3, vs0 ; CHECK-LE-P9-NEXT: blr ; ; CHECK-BE-P8-LABEL: test_v4i32_none: @@ -864,13 +862,13 @@ ; ; CHECK-BE-P9-LABEL: test_v4i32_none: ; CHECK-BE-P9: # %bb.0: # %entry -; CHECK-BE-P9-NEXT: lxsiwzx v2, 0, r3 +; CHECK-BE-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI10_0@toc@ha -; CHECK-BE-P9-NEXT: lxsibzx v3, 0, r4 +; CHECK-BE-P9-NEXT: lxsibzx v2, 0, r4 ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI10_0@toc@l -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: vspltb v3, v3, 7 -; CHECK-BE-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: vspltb v2, v2, 7 +; CHECK-BE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-BE-P9-NEXT: blr ; ; CHECK-AIX-64-P8-LABEL: test_v4i32_none: @@ -886,12 +884,12 @@ ; ; CHECK-AIX-64-P9-LABEL: test_v4i32_none: ; CHECK-AIX-64-P9: # %bb.0: # %entry -; CHECK-AIX-64-P9-NEXT: lxsiwzx v2, 0, r3 +; CHECK-AIX-64-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-AIX-64-P9-NEXT: ld r3, L..C3(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: lxsibzx v3, 0, r4 -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-64-P9-NEXT: vspltb v3, v3, 7 -; CHECK-AIX-64-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-64-P9-NEXT: lxsibzx v2, 0, r4 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-64-P9-NEXT: vspltb v2, v2, 7 +; CHECK-AIX-64-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-64-P9-NEXT: blr ; ; CHECK-AIX-32-P8-LABEL: test_v4i32_none: @@ -907,12 +905,12 @@ ; ; CHECK-AIX-32-P9-LABEL: test_v4i32_none: ; CHECK-AIX-32-P9: # %bb.0: # %entry -; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r3 +; CHECK-AIX-32-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C1(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxsibzx v3, 0, r4 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vspltb v3, v3, 7 -; CHECK-AIX-32-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-32-P9-NEXT: lxsibzx v2, 0, r4 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: vspltb v2, v2, 7 +; CHECK-AIX-32-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-32-P9-NEXT: blr entry: %0 = load <4 x i8>, ptr %a, align 4 @@ -1102,11 +1100,11 @@ ; CHECK-LE-P9: # %bb.0: # %entry ; CHECK-LE-P9-NEXT: lxsibzx v2, 0, r3 ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI13_0@toc@ha -; CHECK-LE-P9-NEXT: lxsd v3, 0(r4) +; CHECK-LE-P9-NEXT: lfd f0, 0(r4) ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI13_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) ; CHECK-LE-P9-NEXT: vspltb v2, v2, 7 -; CHECK-LE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-LE-P9-NEXT: blr ; ; CHECK-BE-P8-LABEL: test_1_2: @@ -1158,10 +1156,10 @@ ; CHECK-AIX-32-P9: # %bb.0: # %entry ; CHECK-AIX-32-P9-NEXT: lxsibzx v2, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C2(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxsiwzx v3, 0, r4 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vspltb v2, v2, 7 -; CHECK-AIX-32-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-32-P9-NEXT: vspltb v3, v2, 7 +; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r4 +; CHECK-AIX-32-P9-NEXT: lxv vs0, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm v2, v3, vs0 ; CHECK-AIX-32-P9-NEXT: blr entry: %0 = load <1 x i8>, ptr %a, align 4 @@ -1194,11 +1192,11 @@ ; CHECK-LE-P9: # %bb.0: # %entry ; CHECK-LE-P9-NEXT: lxsibzx v2, 0, r3 ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI14_0@toc@ha -; CHECK-LE-P9-NEXT: lxsd v3, 0(r4) +; CHECK-LE-P9-NEXT: lfd f0, 0(r4) ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI14_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) ; CHECK-LE-P9-NEXT: vspltb v2, v2, 7 -; CHECK-LE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-LE-P9-NEXT: blr ; ; CHECK-BE-P8-LABEL: test_none_v2i64: @@ -1250,10 +1248,10 @@ ; CHECK-AIX-32-P9: # %bb.0: # %entry ; CHECK-AIX-32-P9-NEXT: lxsibzx v2, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C3(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxsiwzx v3, 0, r4 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vspltb v2, v2, 7 -; CHECK-AIX-32-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-32-P9-NEXT: vspltb v3, v2, 7 +; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r4 +; CHECK-AIX-32-P9-NEXT: lxv vs0, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm v2, v3, vs0 ; CHECK-AIX-32-P9-NEXT: blr entry: %0 = load <1 x i8>, ptr %a, align 4 @@ -1288,9 +1286,9 @@ ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI15_0@toc@ha ; CHECK-LE-P9-NEXT: lxsibzx v3, 0, r4 ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI15_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) +; CHECK-LE-P9-NEXT: lxv vs0, 0(r3) ; CHECK-LE-P9-NEXT: vspltb v3, v3, 7 -; CHECK-LE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-LE-P9-NEXT: xxperm v2, v3, vs0 ; CHECK-LE-P9-NEXT: blr ; ; CHECK-BE-P8-LABEL: test_v2i64_none: @@ -1385,11 +1383,11 @@ ; CHECK-BE-P9-LABEL: test_v8i16_v8i16rhs: ; CHECK-BE-P9: # %bb.0: # %entry ; CHECK-BE-P9-NEXT: addis r5, r2, .LCPI16_0@toc@ha -; CHECK-BE-P9-NEXT: mtvsrwz v3, r4 -; CHECK-BE-P9-NEXT: mtvsrwz v4, r3 +; CHECK-BE-P9-NEXT: mtvsrwz v2, r4 +; CHECK-BE-P9-NEXT: mtfprwz f1, r3 ; CHECK-BE-P9-NEXT: addi r5, r5, .LCPI16_0@toc@l -; CHECK-BE-P9-NEXT: lxv v2, 0(r5) -; CHECK-BE-P9-NEXT: vperm v2, v4, v3, v2 +; CHECK-BE-P9-NEXT: lxv vs0, 0(r5) +; CHECK-BE-P9-NEXT: xxperm v2, vs1, vs0 ; CHECK-BE-P9-NEXT: blr ; ; CHECK-AIX-64-P8-LABEL: test_v8i16_v8i16rhs: @@ -1404,10 +1402,10 @@ ; CHECK-AIX-64-P9-LABEL: test_v8i16_v8i16rhs: ; CHECK-AIX-64-P9: # %bb.0: # %entry ; CHECK-AIX-64-P9-NEXT: ld r5, L..C4(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: mtvsrwz v3, r4 -; CHECK-AIX-64-P9-NEXT: mtvsrwz v4, r3 -; CHECK-AIX-64-P9-NEXT: lxv v2, 0(r5) -; CHECK-AIX-64-P9-NEXT: vperm v2, v4, v3, v2 +; CHECK-AIX-64-P9-NEXT: mtvsrwz v2, r4 +; CHECK-AIX-64-P9-NEXT: mtfprwz f1, r3 +; CHECK-AIX-64-P9-NEXT: lxv vs0, 0(r5) +; CHECK-AIX-64-P9-NEXT: xxperm v2, vs1, vs0 ; CHECK-AIX-64-P9-NEXT: blr ; ; CHECK-AIX-32-P8-LABEL: test_v8i16_v8i16rhs: @@ -1803,11 +1801,11 @@ ; ; CHECK-AIX-32-P9-LABEL: test_v2i64_v2i64: ; CHECK-AIX-32-P9: # %bb.0: # %entry -; CHECK-AIX-32-P9-NEXT: lxvwsx v2, 0, r3 +; CHECK-AIX-32-P9-NEXT: lxvwsx vs0, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C4(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxsiwzx v3, 0, r4 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r4 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-32-P9-NEXT: blr entry: %0 = load <8 x i8>, ptr %a, align 4 @@ -1998,9 +1996,9 @@ ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI24_0@toc@l ; CHECK-LE-P9-NEXT: xxswapd v2, f0 ; CHECK-LE-P9-NEXT: lfd f0, 0(r4) -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) ; CHECK-LE-P9-NEXT: xxswapd v3, f0 -; CHECK-LE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-LE-P9-NEXT: lxv vs0, 0(r3) +; CHECK-LE-P9-NEXT: xxperm v2, v3, vs0 ; CHECK-LE-P9-NEXT: blr ; ; CHECK-BE-P8-LABEL: test_v4i32_v2i64: @@ -2018,11 +2016,11 @@ ; CHECK-BE-P9: # %bb.0: # %entry ; CHECK-BE-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI24_0@toc@ha -; CHECK-BE-P9-NEXT: lxsd v3, 0(r4) +; CHECK-BE-P9-NEXT: lxsd v2, 0(r4) ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI24_0@toc@l -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: xxsldwi v2, f0, f0, 1 -; CHECK-BE-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: xxsldwi vs0, f0, f0, 1 +; CHECK-BE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-BE-P9-NEXT: blr ; ; CHECK-AIX-64-P8-LABEL: test_v4i32_v2i64: @@ -2039,10 +2037,10 @@ ; CHECK-AIX-64-P9: # %bb.0: # %entry ; CHECK-AIX-64-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-AIX-64-P9-NEXT: ld r3, L..C5(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: lxsd v3, 0(r4) -; CHECK-AIX-64-P9-NEXT: xxsldwi v2, f0, f0, 1 -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-64-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-64-P9-NEXT: lxsd v2, 0(r4) +; CHECK-AIX-64-P9-NEXT: xxsldwi vs0, f0, f0, 1 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-64-P9-NEXT: blr ; ; CHECK-AIX-32-P8-LABEL: test_v4i32_v2i64: @@ -2064,17 +2062,17 @@ ; ; CHECK-AIX-32-P9-LABEL: test_v4i32_v2i64: ; CHECK-AIX-32-P9: # %bb.0: # %entry -; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r3 +; CHECK-AIX-32-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, 4(r4) ; CHECK-AIX-32-P9-NEXT: stw r3, -16(r1) ; CHECK-AIX-32-P9-NEXT: lwz r3, 0(r4) -; CHECK-AIX-32-P9-NEXT: lxv vs0, -16(r1) +; CHECK-AIX-32-P9-NEXT: lxv vs1, -16(r1) ; CHECK-AIX-32-P9-NEXT: stw r3, -32(r1) ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C5(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxv vs1, -32(r1) -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: xxmrghw v3, vs1, vs0 -; CHECK-AIX-32-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-32-P9-NEXT: lxv vs2, -32(r1) +; CHECK-AIX-32-P9-NEXT: xxmrghw v2, vs2, vs1 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-32-P9-NEXT: blr entry: %0 = load <4 x i8>, ptr %a, align 4 diff --git a/llvm/test/CodeGen/PowerPC/v2i64_scalar_to_vector_shuffle.ll b/llvm/test/CodeGen/PowerPC/v2i64_scalar_to_vector_shuffle.ll --- a/llvm/test/CodeGen/PowerPC/v2i64_scalar_to_vector_shuffle.ll +++ b/llvm/test/CodeGen/PowerPC/v2i64_scalar_to_vector_shuffle.ll @@ -1611,16 +1611,16 @@ ; ; CHECK-AIX-32-P9-LABEL: test_v4i32_v2i64: ; CHECK-AIX-32-P9: # %bb.0: # %entry +; CHECK-AIX-32-P9-NEXT: stw r4, -32(r1) ; CHECK-AIX-32-P9-NEXT: stw r3, -48(r1) ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C0(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: stw r4, -32(r1) ; CHECK-AIX-32-P9-NEXT: lxv vs0, -32(r1) ; CHECK-AIX-32-P9-NEXT: lxv vs1, -48(r1) ; CHECK-AIX-32-P9-NEXT: stw r5, -16(r1) -; CHECK-AIX-32-P9-NEXT: lxv v4, -16(r1) -; CHECK-AIX-32-P9-NEXT: lxv v3, 0(r3) -; CHECK-AIX-32-P9-NEXT: xxmrghw v2, vs1, vs0 -; CHECK-AIX-32-P9-NEXT: vperm v2, v2, v4, v3 +; CHECK-AIX-32-P9-NEXT: lxv v2, -16(r1) +; CHECK-AIX-32-P9-NEXT: xxmrghw v3, vs1, vs0 +; CHECK-AIX-32-P9-NEXT: lxv vs0, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm v2, v3, vs0 ; CHECK-AIX-32-P9-NEXT: blr entry: %lhs.tmp = insertelement <4 x i32> undef, i32 %arg1, i32 0 diff --git a/llvm/test/CodeGen/PowerPC/v4i32_scalar_to_vector_shuffle.ll b/llvm/test/CodeGen/PowerPC/v4i32_scalar_to_vector_shuffle.ll --- a/llvm/test/CodeGen/PowerPC/v4i32_scalar_to_vector_shuffle.ll +++ b/llvm/test/CodeGen/PowerPC/v4i32_scalar_to_vector_shuffle.ll @@ -42,13 +42,13 @@ ; ; CHECK-LE-P9-LABEL: test_none_v8i16: ; CHECK-LE-P9: # %bb.0: # %entry -; CHECK-LE-P9-NEXT: lxsihzx v2, 0, r3 -; CHECK-LE-P9-NEXT: lxsd v3, 0(r3) +; CHECK-LE-P9-NEXT: lxsihzx f0, 0, r3 +; CHECK-LE-P9-NEXT: lfd f1, 0(r3) ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) -; CHECK-LE-P9-NEXT: vperm v2, v2, v3, v4 -; CHECK-LE-P9-NEXT: xxswapd vs0, v2 +; CHECK-LE-P9-NEXT: lxv vs2, 0(r3) +; CHECK-LE-P9-NEXT: xxperm vs1, vs0, vs2 +; CHECK-LE-P9-NEXT: xxswapd vs0, vs1 ; CHECK-LE-P9-NEXT: stfd f0, 0(r3) ; CHECK-LE-P9-NEXT: blr ; @@ -227,11 +227,11 @@ ; CHECK-LE-P9: # %bb.0: # %entry ; CHECK-LE-P9-NEXT: li r3, 0 ; CHECK-LE-P9-NEXT: vextuwrx r3, r3, v2 -; CHECK-LE-P9-NEXT: mtvsrwz v3, r3 +; CHECK-LE-P9-NEXT: mtfprwz f0, r3 ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) -; CHECK-LE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-LE-P9-NEXT: stxv v2, 0(r5) ; CHECK-LE-P9-NEXT: blr ; @@ -251,12 +251,12 @@ ; CHECK-BE-P9: # %bb.0: # %entry ; CHECK-BE-P9-NEXT: li r3, 0 ; CHECK-BE-P9-NEXT: vextuwlx r3, r3, v2 -; CHECK-BE-P9-NEXT: mtvsrwz v3, r3 +; CHECK-BE-P9-NEXT: mtfprwz f0, r3 ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v2, v3, v4 -; CHECK-BE-P9-NEXT: stxv v2, 0(r5) +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: xxperm vs0, v2, vs1 +; CHECK-BE-P9-NEXT: stxv vs0, 0(r5) ; CHECK-BE-P9-NEXT: blr ; ; CHECK-AIX-64-P8-LABEL: test_none_v4i32: @@ -274,11 +274,11 @@ ; CHECK-AIX-64-P9: # %bb.0: # %entry ; CHECK-AIX-64-P9-NEXT: li r4, 0 ; CHECK-AIX-64-P9-NEXT: vextuwlx r4, r4, v2 -; CHECK-AIX-64-P9-NEXT: mtvsrwz v3, r4 +; CHECK-AIX-64-P9-NEXT: mtfprwz f0, r4 ; CHECK-AIX-64-P9-NEXT: ld r4, L..C0(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r4) -; CHECK-AIX-64-P9-NEXT: vperm v2, v2, v3, v4 -; CHECK-AIX-64-P9-NEXT: stxv v2, 0(r3) +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r4) +; CHECK-AIX-64-P9-NEXT: xxperm vs0, v2, vs1 +; CHECK-AIX-64-P9-NEXT: stxv vs0, 0(r3) ; CHECK-AIX-64-P9-NEXT: blr ; ; CHECK-AIX-32-P8-LABEL: test_none_v4i32: @@ -296,11 +296,11 @@ ; CHECK-AIX-32-P9: # %bb.0: # %entry ; CHECK-AIX-32-P9-NEXT: addi r4, r1, -16 ; CHECK-AIX-32-P9-NEXT: stxv v2, -16(r1) -; CHECK-AIX-32-P9-NEXT: lxsiwzx v3, 0, r4 +; CHECK-AIX-32-P9-NEXT: lfiwzx f0, 0, r4 ; CHECK-AIX-32-P9-NEXT: lwz r4, L..C0(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r4) -; CHECK-AIX-32-P9-NEXT: vperm v2, v2, v3, v4 -; CHECK-AIX-32-P9-NEXT: stxv v2, 0(r3) +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r4) +; CHECK-AIX-32-P9-NEXT: xxperm vs0, v2, vs1 +; CHECK-AIX-32-P9-NEXT: stxv vs0, 0(r3) ; CHECK-AIX-32-P9-NEXT: blr entry: %0 = extractelement <2 x i32> %vec, i64 0 @@ -332,12 +332,12 @@ ; CHECK-LE-P9: # %bb.0: # %entry ; CHECK-LE-P9-NEXT: li r3, 0 ; CHECK-LE-P9-NEXT: vextuwrx r3, r3, v2 -; CHECK-LE-P9-NEXT: mtvsrwz v3, r3 +; CHECK-LE-P9-NEXT: mtfprwz f0, r3 ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) -; CHECK-LE-P9-NEXT: vperm v2, v2, v3, v4 -; CHECK-LE-P9-NEXT: stxv v2, 0(r5) +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-LE-P9-NEXT: xxperm vs0, v2, vs1 +; CHECK-LE-P9-NEXT: stxv vs0, 0(r5) ; CHECK-LE-P9-NEXT: blr ; ; CHECK-BE-P8-LABEL: test_v4i32_none: @@ -356,11 +356,11 @@ ; CHECK-BE-P9: # %bb.0: # %entry ; CHECK-BE-P9-NEXT: li r3, 0 ; CHECK-BE-P9-NEXT: vextuwlx r3, r3, v2 -; CHECK-BE-P9-NEXT: mtvsrwz v3, r3 +; CHECK-BE-P9-NEXT: mtfprwz f0, r3 ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-BE-P9-NEXT: stxv v2, 0(r5) ; CHECK-BE-P9-NEXT: blr ; @@ -379,10 +379,10 @@ ; CHECK-AIX-64-P9: # %bb.0: # %entry ; CHECK-AIX-64-P9-NEXT: li r4, 0 ; CHECK-AIX-64-P9-NEXT: vextuwlx r4, r4, v2 -; CHECK-AIX-64-P9-NEXT: mtvsrwz v3, r4 +; CHECK-AIX-64-P9-NEXT: mtfprwz f0, r4 ; CHECK-AIX-64-P9-NEXT: ld r4, L..C1(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r4) -; CHECK-AIX-64-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r4) +; CHECK-AIX-64-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-64-P9-NEXT: stxv v2, 0(r3) ; CHECK-AIX-64-P9-NEXT: blr ; @@ -401,10 +401,10 @@ ; CHECK-AIX-32-P9: # %bb.0: # %entry ; CHECK-AIX-32-P9-NEXT: addi r4, r1, -16 ; CHECK-AIX-32-P9-NEXT: stxv v2, -16(r1) -; CHECK-AIX-32-P9-NEXT: lxsiwzx v3, 0, r4 +; CHECK-AIX-32-P9-NEXT: lfiwzx f0, 0, r4 ; CHECK-AIX-32-P9-NEXT: lwz r4, L..C1(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r4) -; CHECK-AIX-32-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r4) +; CHECK-AIX-32-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-32-P9-NEXT: stxv v2, 0(r3) ; CHECK-AIX-32-P9-NEXT: blr entry: @@ -438,13 +438,13 @@ ; ; CHECK-LE-P9-LABEL: test_none_v2i64: ; CHECK-LE-P9: # %bb.0: # %entry -; CHECK-LE-P9-NEXT: lxsd v3, 0(r3) +; CHECK-LE-P9-NEXT: lfd f0, 0(r3) ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-LE-P9-NEXT: mtfprwz f0, r4 +; CHECK-LE-P9-NEXT: mtfprwz f1, r4 ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-LE-P9-NEXT: xxinsertw v2, vs0, 12 -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) -; CHECK-LE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-LE-P9-NEXT: xxinsertw v2, vs1, 12 +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-LE-P9-NEXT: stxv v2, 0(r3) ; ; CHECK-BE-P8-LABEL: test_none_v2i64: @@ -463,14 +463,14 @@ ; ; CHECK-BE-P9-LABEL: test_none_v2i64: ; CHECK-BE-P9: # %bb.0: # %entry -; CHECK-BE-P9-NEXT: lxsd v3, 0(r3) +; CHECK-BE-P9-NEXT: lfd f0, 0(r3) ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-BE-P9-NEXT: mtfprwz f0, r4 +; CHECK-BE-P9-NEXT: mtfprwz f1, r4 ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-P9-NEXT: xxinsertw v2, vs0, 0 -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v2, v3, v4 -; CHECK-BE-P9-NEXT: stxv v2, 0(r3) +; CHECK-BE-P9-NEXT: xxinsertw v2, vs1, 0 +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: xxperm vs0, v2, vs1 +; CHECK-BE-P9-NEXT: stxv vs0, 0(r3) ; ; CHECK-AIX-64-P8-LABEL: test_none_v2i64: ; CHECK-AIX-64-P8: # %bb.0: # %entry @@ -486,13 +486,13 @@ ; ; CHECK-AIX-64-P9-LABEL: test_none_v2i64: ; CHECK-AIX-64-P9: # %bb.0: # %entry -; CHECK-AIX-64-P9-NEXT: lxsd v3, 0(r3) +; CHECK-AIX-64-P9-NEXT: lfd f0, 0(r3) ; CHECK-AIX-64-P9-NEXT: ld r3, L..C2(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: mtfprwz f0, r4 -; CHECK-AIX-64-P9-NEXT: xxinsertw v2, vs0, 0 -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-64-P9-NEXT: vperm v2, v2, v3, v4 -; CHECK-AIX-64-P9-NEXT: stxv v2, 0(r3) +; CHECK-AIX-64-P9-NEXT: mtfprwz f1, r4 +; CHECK-AIX-64-P9-NEXT: xxinsertw v2, vs1, 0 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm vs0, v2, vs1 +; CHECK-AIX-64-P9-NEXT: stxv vs0, 0(r3) ; ; CHECK-AIX-32-P8-LABEL: test_none_v2i64: ; CHECK-AIX-32-P8: # %bb.0: # %entry @@ -510,13 +510,13 @@ ; ; CHECK-AIX-32-P9-LABEL: test_none_v2i64: ; CHECK-AIX-32-P9: # %bb.0: # %entry -; CHECK-AIX-32-P9-NEXT: lxsiwzx v3, 0, r3 +; CHECK-AIX-32-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C2(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: mtfprwz f0, r4 -; CHECK-AIX-32-P9-NEXT: xxinsertw v2, vs0, 0 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vperm v2, v2, v3, v4 -; CHECK-AIX-32-P9-NEXT: stxv v2, 0(r3) +; CHECK-AIX-32-P9-NEXT: mtfprwz f1, r4 +; CHECK-AIX-32-P9-NEXT: xxinsertw v2, vs1, 0 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm vs0, v2, vs1 +; CHECK-AIX-32-P9-NEXT: stxv vs0, 0(r3) entry: %0 = load <2 x i32>, ptr %ptr, align 4 %tmp = insertelement <2 x i32> %vec, i32 %v1, i32 0 @@ -895,10 +895,10 @@ ; CHECK-LE-P9: # %bb.0: # %entry ; CHECK-LE-P9-NEXT: lxsiwzx v2, 0, r3 ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI9_0@toc@ha -; CHECK-LE-P9-NEXT: lxsiwzx v3, 0, r4 +; CHECK-LE-P9-NEXT: lfiwzx f0, 0, r4 ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI9_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) -; CHECK-LE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-LE-P9-NEXT: blr ; ; CHECK-BE-P8-LABEL: test_v4i32_v4i32: @@ -913,12 +913,12 @@ ; ; CHECK-BE-P9-LABEL: test_v4i32_v4i32: ; CHECK-BE-P9: # %bb.0: # %entry -; CHECK-BE-P9-NEXT: lxsiwzx v2, 0, r3 +; CHECK-BE-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI9_0@toc@ha -; CHECK-BE-P9-NEXT: lxsiwzx v3, 0, r4 +; CHECK-BE-P9-NEXT: lxsiwzx v2, 0, r4 ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI9_0@toc@l -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-BE-P9-NEXT: blr ; ; CHECK-AIX-64-P8-LABEL: test_v4i32_v4i32: @@ -932,11 +932,11 @@ ; ; CHECK-AIX-64-P9-LABEL: test_v4i32_v4i32: ; CHECK-AIX-64-P9: # %bb.0: # %entry -; CHECK-AIX-64-P9-NEXT: lxsiwzx v2, 0, r3 +; CHECK-AIX-64-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-AIX-64-P9-NEXT: ld r3, L..C3(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: lxsiwzx v3, 0, r4 -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-64-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-64-P9-NEXT: lxsiwzx v2, 0, r4 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-64-P9-NEXT: blr ; ; CHECK-AIX-32-P8-LABEL: test_v4i32_v4i32: @@ -950,11 +950,11 @@ ; ; CHECK-AIX-32-P9-LABEL: test_v4i32_v4i32: ; CHECK-AIX-32-P9: # %bb.0: # %entry -; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r3 +; CHECK-AIX-32-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C3(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxsiwzx v3, 0, r4 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r4 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-32-P9-NEXT: blr entry: %load1 = load <4 x i8>, ptr %a diff --git a/llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll b/llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll --- a/llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll +++ b/llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll @@ -41,11 +41,11 @@ ; ; CHECK-LE-P9-LABEL: test_none_v8i16: ; CHECK-LE-P9: # %bb.0: # %entry -; CHECK-LE-P9-NEXT: lxsihzx v3, 0, r3 +; CHECK-LE-P9-NEXT: lxsihzx f0, 0, r3 ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) -; CHECK-LE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-LE-P9-NEXT: stxv v2, 0(r3) ; CHECK-LE-P9-NEXT: blr ; @@ -62,12 +62,12 @@ ; ; CHECK-BE-P9-LABEL: test_none_v8i16: ; CHECK-BE-P9: # %bb.0: # %entry -; CHECK-BE-P9-NEXT: lxsihzx v3, 0, r3 +; CHECK-BE-P9-NEXT: lxsihzx f0, 0, r3 ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v2, v3, v4 -; CHECK-BE-P9-NEXT: stxv v2, 0(r3) +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: xxperm vs0, v2, vs1 +; CHECK-BE-P9-NEXT: stxv vs0, 0(r3) ; CHECK-BE-P9-NEXT: blr ; ; CHECK-AIX-64-P8-LABEL: test_none_v8i16: @@ -82,11 +82,11 @@ ; ; CHECK-AIX-64-P9-LABEL: test_none_v8i16: ; CHECK-AIX-64-P9: # %bb.0: # %entry -; CHECK-AIX-64-P9-NEXT: lxsihzx v3, 0, r3 +; CHECK-AIX-64-P9-NEXT: lxsihzx f0, 0, r3 ; CHECK-AIX-64-P9-NEXT: ld r3, L..C0(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-64-P9-NEXT: vperm v2, v2, v3, v4 -; CHECK-AIX-64-P9-NEXT: stxv v2, 0(r3) +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm vs0, v2, vs1 +; CHECK-AIX-64-P9-NEXT: stxv vs0, 0(r3) ; CHECK-AIX-64-P9-NEXT: blr ; ; CHECK-AIX-32-P8-LABEL: test_none_v8i16: @@ -101,11 +101,11 @@ ; ; CHECK-AIX-32-P9-LABEL: test_none_v8i16: ; CHECK-AIX-32-P9: # %bb.0: # %entry -; CHECK-AIX-32-P9-NEXT: lxsihzx v3, 0, r3 +; CHECK-AIX-32-P9-NEXT: lxsihzx f0, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C0(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vperm v2, v2, v3, v4 -; CHECK-AIX-32-P9-NEXT: stxv v2, 0(r3) +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm vs0, v2, vs1 +; CHECK-AIX-32-P9-NEXT: stxv vs0, 0(r3) ; CHECK-AIX-32-P9-NEXT: blr entry: %load0.tmp = load <2 x i8>, ptr %a0 @@ -140,14 +140,14 @@ ; ; CHECK-LE-P9-LABEL: test_v8i16_none: ; CHECK-LE-P9: # %bb.0: # %entry -; CHECK-LE-P9-NEXT: lxsihzx v3, 0, r3 +; CHECK-LE-P9-NEXT: lxsihzx f0, 0, r3 ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha -; CHECK-LE-P9-NEXT: mtvsrwz v4, r9 +; CHECK-LE-P9-NEXT: mtvsrwz v3, r9 ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-LE-P9-NEXT: vinsertb v2, v4, 15 -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) -; CHECK-LE-P9-NEXT: vperm v2, v2, v3, v4 -; CHECK-LE-P9-NEXT: stxv v2, 0(r3) +; CHECK-LE-P9-NEXT: vinsertb v2, v3, 15 +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-LE-P9-NEXT: xxperm vs0, v2, vs1 +; CHECK-LE-P9-NEXT: stxv vs0, 0(r3) ; CHECK-LE-P9-NEXT: blr ; ; CHECK-BE-P8-LABEL: test_v8i16_none: @@ -168,13 +168,13 @@ ; ; CHECK-BE-P9-LABEL: test_v8i16_none: ; CHECK-BE-P9: # %bb.0: # %entry -; CHECK-BE-P9-NEXT: lxsihzx v3, 0, r3 +; CHECK-BE-P9-NEXT: lxsihzx f0, 0, r3 ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha -; CHECK-BE-P9-NEXT: mtvsrwz v4, r9 +; CHECK-BE-P9-NEXT: mtvsrwz v3, r9 ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-BE-P9-NEXT: vinsertb v2, v4, 0 -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-BE-P9-NEXT: vinsertb v2, v3, 0 +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-BE-P9-NEXT: stxv v2, 0(r3) ; CHECK-BE-P9-NEXT: blr ; @@ -194,12 +194,12 @@ ; ; CHECK-AIX-64-P9-LABEL: test_v8i16_none: ; CHECK-AIX-64-P9: # %bb.0: # %entry -; CHECK-AIX-64-P9-NEXT: lxsihzx v3, 0, r3 +; CHECK-AIX-64-P9-NEXT: lxsihzx f0, 0, r3 ; CHECK-AIX-64-P9-NEXT: ld r3, L..C1(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: mtvsrwz v4, r5 -; CHECK-AIX-64-P9-NEXT: vinsertb v2, v4, 0 -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-64-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-AIX-64-P9-NEXT: mtvsrwz v3, r5 +; CHECK-AIX-64-P9-NEXT: vinsertb v2, v3, 0 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-64-P9-NEXT: stxv v2, 0(r3) ; CHECK-AIX-64-P9-NEXT: blr ; @@ -219,12 +219,12 @@ ; ; CHECK-AIX-32-P9-LABEL: test_v8i16_none: ; CHECK-AIX-32-P9: # %bb.0: # %entry -; CHECK-AIX-32-P9-NEXT: lxsihzx v3, 0, r3 +; CHECK-AIX-32-P9-NEXT: lxsihzx f0, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C1(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: mtvsrwz v4, r5 -; CHECK-AIX-32-P9-NEXT: vinsertb v2, v4, 0 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-AIX-32-P9-NEXT: mtvsrwz v3, r5 +; CHECK-AIX-32-P9-NEXT: vinsertb v2, v3, 0 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-32-P9-NEXT: stxv v2, 0(r3) ; CHECK-AIX-32-P9-NEXT: blr entry: @@ -263,11 +263,11 @@ ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-LE-P9-NEXT: mtvsrd v3, r5 ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) +; CHECK-LE-P9-NEXT: lxv vs0, 0(r3) ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI2_1@toc@ha ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI2_1@toc@l -; CHECK-LE-P9-NEXT: vperm v3, v3, v3, v4 ; CHECK-LE-P9-NEXT: lxv v4, 0(r3) +; CHECK-LE-P9-NEXT: xxperm v3, v3, vs0 ; CHECK-LE-P9-NEXT: vperm v2, v3, v2, v4 ; CHECK-LE-P9-NEXT: xxswapd vs0, v2 ; CHECK-LE-P9-NEXT: stfd f0, 0(r3) @@ -294,11 +294,11 @@ ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-BE-P9-NEXT: mtvsrwz v3, r5 ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) +; CHECK-BE-P9-NEXT: lxv vs0, 0(r3) ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI2_1@toc@ha ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI2_1@toc@l -; CHECK-BE-P9-NEXT: vperm v3, v3, v3, v4 ; CHECK-BE-P9-NEXT: lxv v4, 0(r3) +; CHECK-BE-P9-NEXT: xxperm v3, v3, vs0 ; CHECK-BE-P9-NEXT: vperm v2, v2, v3, v4 ; CHECK-BE-P9-NEXT: stxsd v2, 0(r3) ; CHECK-BE-P9-NEXT: blr @@ -321,10 +321,10 @@ ; CHECK-AIX-64-P9-NEXT: lxsiwzx v2, 0, r3 ; CHECK-AIX-64-P9-NEXT: ld r3, L..C2(r2) # %const.0 ; CHECK-AIX-64-P9-NEXT: mtvsrwz v3, r5 -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) +; CHECK-AIX-64-P9-NEXT: lxv vs0, 0(r3) ; CHECK-AIX-64-P9-NEXT: ld r3, L..C3(r2) # %const.1 -; CHECK-AIX-64-P9-NEXT: vperm v3, v3, v3, v4 ; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm v3, v3, vs0 ; CHECK-AIX-64-P9-NEXT: vperm v2, v2, v3, v4 ; CHECK-AIX-64-P9-NEXT: stxsd v2, 0(r3) ; CHECK-AIX-64-P9-NEXT: blr @@ -387,13 +387,13 @@ ; ; CHECK-LE-P9-LABEL: test_v4i32_none: ; CHECK-LE-P9: # %bb.0: # %entry -; CHECK-LE-P9-NEXT: lxsiwzx v2, 0, r3 +; CHECK-LE-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha -; CHECK-LE-P9-NEXT: xxlxor v4, v4, v4 +; CHECK-LE-P9-NEXT: xxlxor vs1, vs1, vs1 ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l -; CHECK-LE-P9-NEXT: lxv v3, 0(r3) -; CHECK-LE-P9-NEXT: vperm v2, v4, v2, v3 -; CHECK-LE-P9-NEXT: stxv v2, 0(r3) +; CHECK-LE-P9-NEXT: lxv vs2, 0(r3) +; CHECK-LE-P9-NEXT: xxperm vs0, vs1, vs2 +; CHECK-LE-P9-NEXT: stxv vs0, 0(r3) ; CHECK-LE-P9-NEXT: blr ; ; CHECK-BE-P8-LABEL: test_v4i32_none: @@ -409,13 +409,13 @@ ; ; CHECK-BE-P9-LABEL: test_v4i32_none: ; CHECK-BE-P9: # %bb.0: # %entry -; CHECK-BE-P9-NEXT: lxsiwzx v2, 0, r3 +; CHECK-BE-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI3_0@toc@ha -; CHECK-BE-P9-NEXT: xxlxor v4, v4, v4 +; CHECK-BE-P9-NEXT: xxlxor vs1, vs1, vs1 ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI3_0@toc@l -; CHECK-BE-P9-NEXT: lxv v3, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v4, v2, v3 -; CHECK-BE-P9-NEXT: stxv v2, 0(r3) +; CHECK-BE-P9-NEXT: lxv vs2, 0(r3) +; CHECK-BE-P9-NEXT: xxperm vs0, vs1, vs2 +; CHECK-BE-P9-NEXT: stxv vs0, 0(r3) ; CHECK-BE-P9-NEXT: blr ; ; CHECK-AIX-64-P8-LABEL: test_v4i32_none: @@ -430,12 +430,12 @@ ; ; CHECK-AIX-64-P9-LABEL: test_v4i32_none: ; CHECK-AIX-64-P9: # %bb.0: # %entry -; CHECK-AIX-64-P9-NEXT: lxsiwzx v2, 0, r3 +; CHECK-AIX-64-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-AIX-64-P9-NEXT: ld r3, L..C4(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-AIX-64-P9-NEXT: lxv v3, 0(r3) -; CHECK-AIX-64-P9-NEXT: vperm v2, v4, v2, v3 -; CHECK-AIX-64-P9-NEXT: stxv v2, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxlxor vs2, vs2, vs2 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm vs0, vs2, vs1 +; CHECK-AIX-64-P9-NEXT: stxv vs0, 0(r3) ; CHECK-AIX-64-P9-NEXT: blr ; ; CHECK-AIX-32-P8-LABEL: test_v4i32_none: @@ -450,12 +450,12 @@ ; ; CHECK-AIX-32-P9-LABEL: test_v4i32_none: ; CHECK-AIX-32-P9: # %bb.0: # %entry -; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r3 +; CHECK-AIX-32-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C3(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-AIX-32-P9-NEXT: lxv v3, 0(r3) -; CHECK-AIX-32-P9-NEXT: vperm v2, v4, v2, v3 -; CHECK-AIX-32-P9-NEXT: stxv v2, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxlxor vs2, vs2, vs2 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm vs0, vs2, vs1 +; CHECK-AIX-32-P9-NEXT: stxv vs0, 0(r3) ; CHECK-AIX-32-P9-NEXT: blr entry: %0 = load <2 x i16>, ptr %ptr1, align 1 @@ -470,15 +470,14 @@ ; CHECK-LE-P8-LABEL: test_none_v2i64: ; CHECK-LE-P8: # %bb.0: # %entry ; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI4_0@toc@ha -; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r4 ; CHECK-LE-P8-NEXT: lxsdx v2, 0, r3 +; CHECK-LE-P8-NEXT: lxvd2x v3, 0, r4 ; CHECK-LE-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha ; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI4_0@toc@l ; CHECK-LE-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l -; CHECK-LE-P8-NEXT: lxvd2x vs1, 0, r5 -; CHECK-LE-P8-NEXT: xxswapd v3, vs0 +; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r5 +; CHECK-LE-P8-NEXT: xxswapd v4, vs0 ; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r3 -; CHECK-LE-P8-NEXT: xxswapd v4, vs1 ; CHECK-LE-P8-NEXT: vperm v2, v2, v3, v4 ; CHECK-LE-P8-NEXT: xxswapd v3, vs0 ; CHECK-LE-P8-NEXT: xxlxor v4, v4, v4 @@ -489,16 +488,16 @@ ; ; CHECK-LE-P9-LABEL: test_none_v2i64: ; CHECK-LE-P9: # %bb.0: # %entry -; CHECK-LE-P9-NEXT: lxsd v2, 0(r3) +; CHECK-LE-P9-NEXT: lfd f0, 0(r3) ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-LE-P9-NEXT: lxv v3, 0(r4) +; CHECK-LE-P9-NEXT: lxv v2, 0(r4) +; CHECK-LE-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI4_1@toc@ha ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI4_1@toc@l -; CHECK-LE-P9-NEXT: vperm v2, v2, v3, v4 ; CHECK-LE-P9-NEXT: lxv v3, 0(r3) -; CHECK-LE-P9-NEXT: xxlxor v4, v4, v4 +; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-LE-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-LE-P9-NEXT: stxv v2, 0(r3) ; CHECK-LE-P9-NEXT: blr @@ -520,11 +519,11 @@ ; CHECK-BE-P9: # %bb.0: # %entry ; CHECK-BE-P9-NEXT: lxsd v2, 0(r3) ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-BE-P9-NEXT: lxv v3, 0(r4) -; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-BE-P9-NEXT: lxv vs0, 0(r4) ; CHECK-BE-P9-NEXT: xxlxor v3, v3, v3 +; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-BE-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-P9-NEXT: stxv v2, 0(r3) ; CHECK-BE-P9-NEXT: blr @@ -545,10 +544,10 @@ ; CHECK-AIX-64-P9: # %bb.0: # %entry ; CHECK-AIX-64-P9-NEXT: lxsd v2, 0(r3) ; CHECK-AIX-64-P9-NEXT: ld r3, L..C5(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: lxv v3, 0(r4) -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-64-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r4) ; CHECK-AIX-64-P9-NEXT: xxlxor v3, v3, v3 +; CHECK-AIX-64-P9-NEXT: lxv vs0, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm v2, vs1, vs0 ; CHECK-AIX-64-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-AIX-64-P9-NEXT: stxv v2, 0(r3) ; CHECK-AIX-64-P9-NEXT: blr @@ -569,10 +568,10 @@ ; CHECK-AIX-32-P9: # %bb.0: # %entry ; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C4(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxv v3, 0(r4) -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-AIX-32-P9-NEXT: lxv vs0, 0(r4) ; CHECK-AIX-32-P9-NEXT: xxlxor v3, v3, v3 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-32-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-AIX-32-P9-NEXT: stxv v2, 0(r3) ; CHECK-AIX-32-P9-NEXT: blr @@ -602,13 +601,13 @@ ; ; CHECK-LE-P9-LABEL: test_v2i64_none: ; CHECK-LE-P9: # %bb.0: # %entry -; CHECK-LE-P9-NEXT: lxsd v2, 0(r3) +; CHECK-LE-P9-NEXT: lfd f0, 0(r3) ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha -; CHECK-LE-P9-NEXT: xxlxor v4, v4, v4 +; CHECK-LE-P9-NEXT: xxlxor vs1, vs1, vs1 ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-LE-P9-NEXT: lxv v3, 0(r3) -; CHECK-LE-P9-NEXT: vperm v2, v4, v2, v3 -; CHECK-LE-P9-NEXT: stxv v2, 0(r3) +; CHECK-LE-P9-NEXT: lxv vs2, 0(r3) +; CHECK-LE-P9-NEXT: xxperm vs0, vs1, vs2 +; CHECK-LE-P9-NEXT: stxv vs0, 0(r3) ; CHECK-LE-P9-NEXT: blr ; ; CHECK-BE-P8-LABEL: test_v2i64_none: @@ -624,13 +623,13 @@ ; ; CHECK-BE-P9-LABEL: test_v2i64_none: ; CHECK-BE-P9: # %bb.0: # %entry -; CHECK-BE-P9-NEXT: lxsd v2, 0(r3) +; CHECK-BE-P9-NEXT: lfd f0, 0(r3) ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha -; CHECK-BE-P9-NEXT: xxlxor v4, v4, v4 +; CHECK-BE-P9-NEXT: xxlxor vs1, vs1, vs1 ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-BE-P9-NEXT: lxv v3, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v4, v2, v3 -; CHECK-BE-P9-NEXT: stxv v2, 0(r3) +; CHECK-BE-P9-NEXT: lxv vs2, 0(r3) +; CHECK-BE-P9-NEXT: xxperm vs0, vs1, vs2 +; CHECK-BE-P9-NEXT: stxv vs0, 0(r3) ; CHECK-BE-P9-NEXT: blr ; ; CHECK-AIX-64-P8-LABEL: test_v2i64_none: @@ -645,12 +644,12 @@ ; ; CHECK-AIX-64-P9-LABEL: test_v2i64_none: ; CHECK-AIX-64-P9: # %bb.0: # %entry -; CHECK-AIX-64-P9-NEXT: lxsd v2, 0(r3) +; CHECK-AIX-64-P9-NEXT: lfd f0, 0(r3) ; CHECK-AIX-64-P9-NEXT: ld r3, L..C6(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: xxlxor v4, v4, v4 -; CHECK-AIX-64-P9-NEXT: lxv v3, 0(r3) -; CHECK-AIX-64-P9-NEXT: vperm v2, v4, v2, v3 -; CHECK-AIX-64-P9-NEXT: stxv v2, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxlxor vs2, vs2, vs2 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm vs0, vs2, vs1 +; CHECK-AIX-64-P9-NEXT: stxv vs0, 0(r3) ; CHECK-AIX-64-P9-NEXT: blr ; ; CHECK-AIX-32-P8-LABEL: test_v2i64_none: @@ -674,17 +673,17 @@ ; CHECK-AIX-32-P9-LABEL: test_v2i64_none: ; CHECK-AIX-32-P9: # %bb.0: # %entry ; CHECK-AIX-32-P9-NEXT: lwz r4, 4(r3) -; CHECK-AIX-32-P9-NEXT: xxlxor v4, v4, v4 +; CHECK-AIX-32-P9-NEXT: xxlxor vs2, vs2, vs2 ; CHECK-AIX-32-P9-NEXT: stw r4, -16(r1) ; CHECK-AIX-32-P9-NEXT: lwz r3, 0(r3) ; CHECK-AIX-32-P9-NEXT: lxv vs0, -16(r1) ; CHECK-AIX-32-P9-NEXT: stw r3, -32(r1) ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C5(r2) # %const.0 ; CHECK-AIX-32-P9-NEXT: lxv vs1, -32(r1) -; CHECK-AIX-32-P9-NEXT: lxv v3, 0(r3) -; CHECK-AIX-32-P9-NEXT: xxmrghw v2, vs1, vs0 -; CHECK-AIX-32-P9-NEXT: vperm v2, v4, v2, v3 -; CHECK-AIX-32-P9-NEXT: stxv v2, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxmrghw vs0, vs1, vs0 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm vs0, vs2, vs1 +; CHECK-AIX-32-P9-NEXT: stxv vs0, 0(r3) ; CHECK-AIX-32-P9-NEXT: blr entry: %0 = load <4 x i16>, ptr %ptr1, align 1 @@ -712,10 +711,10 @@ ; CHECK-LE-P9: # %bb.0: # %entry ; CHECK-LE-P9-NEXT: lxsihzx v2, 0, r3 ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI6_0@toc@ha -; CHECK-LE-P9-NEXT: lxsihzx v3, 0, r4 +; CHECK-LE-P9-NEXT: lxsihzx f0, 0, r4 ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI6_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) -; CHECK-LE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-LE-P9-NEXT: blr ; ; CHECK-BE-P8-LABEL: test_v8i16_v8i16: @@ -732,12 +731,12 @@ ; ; CHECK-BE-P9-LABEL: test_v8i16_v8i16: ; CHECK-BE-P9: # %bb.0: # %entry -; CHECK-BE-P9-NEXT: lxsihzx v2, 0, r3 +; CHECK-BE-P9-NEXT: lxsihzx f0, 0, r3 ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI6_0@toc@ha -; CHECK-BE-P9-NEXT: lxsihzx v3, 0, r4 +; CHECK-BE-P9-NEXT: lxsihzx v2, 0, r4 ; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI6_0@toc@l -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-BE-P9-NEXT: blr ; ; CHECK-AIX-64-P8-LABEL: test_v8i16_v8i16: @@ -753,11 +752,11 @@ ; ; CHECK-AIX-64-P9-LABEL: test_v8i16_v8i16: ; CHECK-AIX-64-P9: # %bb.0: # %entry -; CHECK-AIX-64-P9-NEXT: lxsihzx v2, 0, r3 +; CHECK-AIX-64-P9-NEXT: lxsihzx f0, 0, r3 ; CHECK-AIX-64-P9-NEXT: ld r3, L..C7(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: lxsihzx v3, 0, r4 -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-64-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-64-P9-NEXT: lxsihzx v2, 0, r4 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-64-P9-NEXT: blr ; ; CHECK-AIX-32-P8-LABEL: test_v8i16_v8i16: @@ -773,11 +772,11 @@ ; ; CHECK-AIX-32-P9-LABEL: test_v8i16_v8i16: ; CHECK-AIX-32-P9: # %bb.0: # %entry -; CHECK-AIX-32-P9-NEXT: lxsihzx v2, 0, r3 +; CHECK-AIX-32-P9-NEXT: lxsihzx f0, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C6(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxsihzx v3, 0, r4 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-32-P9-NEXT: lxsihzx v2, 0, r4 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-32-P9-NEXT: blr entry: %load1 = load <2 x i8>, ptr %a @@ -993,16 +992,16 @@ ; ; CHECK-LE-P9-LABEL: test_v4i32_v4i32: ; CHECK-LE-P9: # %bb.0: # %entry -; CHECK-LE-P9-NEXT: lxsiwzx v2, 0, r3 +; CHECK-LE-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI9_0@toc@ha -; CHECK-LE-P9-NEXT: lxsiwzx v3, 0, r4 +; CHECK-LE-P9-NEXT: lxsiwzx v2, 0, r4 +; CHECK-LE-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI9_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI9_1@toc@ha ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI9_1@toc@l -; CHECK-LE-P9-NEXT: vperm v2, v2, v3, v4 ; CHECK-LE-P9-NEXT: lxv v3, 0(r3) -; CHECK-LE-P9-NEXT: xxlxor v4, v4, v4 +; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-LE-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-LE-P9-NEXT: stxv v2, 0(r3) ; CHECK-LE-P9-NEXT: blr @@ -1024,11 +1023,11 @@ ; CHECK-BE-P9: # %bb.0: # %entry ; CHECK-BE-P9-NEXT: lxsiwzx v2, 0, r3 ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI9_0@toc@ha -; CHECK-BE-P9-NEXT: lxsiwzx v3, 0, r4 -; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI9_0@toc@l -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-BE-P9-NEXT: lfiwzx f0, 0, r4 ; CHECK-BE-P9-NEXT: xxlxor v3, v3, v3 +; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI9_0@toc@l +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-BE-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-P9-NEXT: stxv v2, 0(r3) ; CHECK-BE-P9-NEXT: blr @@ -1049,10 +1048,10 @@ ; CHECK-AIX-64-P9: # %bb.0: # %entry ; CHECK-AIX-64-P9-NEXT: lxsiwzx v2, 0, r3 ; CHECK-AIX-64-P9-NEXT: ld r3, L..C8(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: lxsiwzx v3, 0, r4 -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-64-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-AIX-64-P9-NEXT: lfiwzx f0, 0, r4 ; CHECK-AIX-64-P9-NEXT: xxlxor v3, v3, v3 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-64-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-AIX-64-P9-NEXT: stxv v2, 0(r3) ; CHECK-AIX-64-P9-NEXT: blr @@ -1073,10 +1072,10 @@ ; CHECK-AIX-32-P9: # %bb.0: # %entry ; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C7(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxsiwzx v3, 0, r4 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-AIX-32-P9-NEXT: lfiwzx f0, 0, r4 ; CHECK-AIX-32-P9-NEXT: xxlxor v3, v3, v3 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-32-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-AIX-32-P9-NEXT: stxv v2, 0(r3) ; CHECK-AIX-32-P9-NEXT: blr @@ -1245,11 +1244,11 @@ ; ; CHECK-AIX-32-P9-LABEL: test_v4i32_v2i64: ; CHECK-AIX-32-P9: # %bb.0: # %entry -; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r3 +; CHECK-AIX-32-P9-NEXT: lfiwzx f0, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C8(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxsiwzx v3, 0, r4 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vperm v2, v2, v3, v4 +; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r4 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-32-P9-NEXT: blr entry: %0 = load <2 x i8>, ptr %a, align 4 @@ -1286,16 +1285,16 @@ ; ; CHECK-LE-P9-LABEL: test_v2i64_v2i64: ; CHECK-LE-P9: # %bb.0: # %entry -; CHECK-LE-P9-NEXT: lxsd v2, 0(r3) +; CHECK-LE-P9-NEXT: lfd f0, 0(r3) ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI12_0@toc@ha -; CHECK-LE-P9-NEXT: lxsd v3, 0(r4) +; CHECK-LE-P9-NEXT: lxsd v2, 0(r4) +; CHECK-LE-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI12_0@toc@l -; CHECK-LE-P9-NEXT: lxv v4, 0(r3) +; CHECK-LE-P9-NEXT: lxv vs1, 0(r3) ; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI12_1@toc@ha ; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI12_1@toc@l -; CHECK-LE-P9-NEXT: vperm v2, v2, v3, v4 ; CHECK-LE-P9-NEXT: lxv v3, 0(r3) -; CHECK-LE-P9-NEXT: xxlxor v4, v4, v4 +; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-LE-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-LE-P9-NEXT: stxv v2, 0(r3) ; CHECK-LE-P9-NEXT: blr @@ -1317,11 +1316,11 @@ ; CHECK-BE-P9: # %bb.0: # %entry ; CHECK-BE-P9-NEXT: lxsd v2, 0(r3) ; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI12_0@toc@ha -; CHECK-BE-P9-NEXT: lxsd v3, 0(r4) -; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI12_0@toc@l -; CHECK-BE-P9-NEXT: lxv v4, 0(r3) -; CHECK-BE-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-BE-P9-NEXT: lfd f0, 0(r4) ; CHECK-BE-P9-NEXT: xxlxor v3, v3, v3 +; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI12_0@toc@l +; CHECK-BE-P9-NEXT: lxv vs1, 0(r3) +; CHECK-BE-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-BE-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-P9-NEXT: stxv v2, 0(r3) ; CHECK-BE-P9-NEXT: blr @@ -1342,10 +1341,10 @@ ; CHECK-AIX-64-P9: # %bb.0: # %entry ; CHECK-AIX-64-P9-NEXT: lxsd v2, 0(r3) ; CHECK-AIX-64-P9-NEXT: ld r3, L..C9(r2) # %const.0 -; CHECK-AIX-64-P9-NEXT: lxsd v3, 0(r4) -; CHECK-AIX-64-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-64-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-AIX-64-P9-NEXT: lfd f0, 0(r4) ; CHECK-AIX-64-P9-NEXT: xxlxor v3, v3, v3 +; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-64-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-64-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-AIX-64-P9-NEXT: stxv v2, 0(r3) ; CHECK-AIX-64-P9-NEXT: blr @@ -1366,10 +1365,10 @@ ; CHECK-AIX-32-P9: # %bb.0: # %entry ; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C9(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxsiwzx v3, 0, r4 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-AIX-32-P9-NEXT: lfiwzx f0, 0, r4 ; CHECK-AIX-32-P9-NEXT: xxlxor v3, v3, v3 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-32-P9-NEXT: vmrghh v2, v3, v2 ; CHECK-AIX-32-P9-NEXT: stxv v2, 0(r3) ; CHECK-AIX-32-P9-NEXT: blr @@ -1446,9 +1445,9 @@ ; CHECK-AIX-32-P9: # %bb.0: # %entry ; CHECK-AIX-32-P9-NEXT: lxsiwzx v2, 0, r3 ; CHECK-AIX-32-P9-NEXT: lwz r3, L..C10(r2) # %const.0 -; CHECK-AIX-32-P9-NEXT: lxsiwzx v3, 0, r4 -; CHECK-AIX-32-P9-NEXT: lxv v4, 0(r3) -; CHECK-AIX-32-P9-NEXT: vperm v2, v3, v2, v4 +; CHECK-AIX-32-P9-NEXT: lfiwzx f0, 0, r4 +; CHECK-AIX-32-P9-NEXT: lxv vs1, 0(r3) +; CHECK-AIX-32-P9-NEXT: xxperm v2, vs0, vs1 ; CHECK-AIX-32-P9-NEXT: blr entry: %0 = load <2 x i8>, ptr %a, align 4 diff --git a/llvm/test/CodeGen/PowerPC/vec-itofp.ll b/llvm/test/CodeGen/PowerPC/vec-itofp.ll --- a/llvm/test/CodeGen/PowerPC/vec-itofp.ll +++ b/llvm/test/CodeGen/PowerPC/vec-itofp.ll @@ -203,13 +203,13 @@ ; ; CHECK-P9-LABEL: test2: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: lxv v2, 0(r4) +; CHECK-P9-NEXT: lxv vs1, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha -; CHECK-P9-NEXT: xxlxor v4, v4, v4 +; CHECK-P9-NEXT: xxlxor vs0, vs0, vs0 ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l -; CHECK-P9-NEXT: lxv v3, 0(r4) -; CHECK-P9-NEXT: vperm v2, v4, v2, v3 -; CHECK-P9-NEXT: xvcvuxddp vs0, v2 +; CHECK-P9-NEXT: lxv vs2, 0(r4) +; CHECK-P9-NEXT: xxperm vs1, vs0, vs2 +; CHECK-P9-NEXT: xvcvuxddp vs0, vs1 ; CHECK-P9-NEXT: stxv vs0, 0(r3) ; CHECK-P9-NEXT: blr ; @@ -459,8 +459,8 @@ ; CHECK-P9-NEXT: lxv v2, 0(r4) ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxv v3, 0(r4) -; CHECK-P9-NEXT: vperm v2, v2, v2, v3 +; CHECK-P9-NEXT: lxv vs0, 0(r4) +; CHECK-P9-NEXT: xxperm v2, v2, vs0 ; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: xvcvsxddp vs0, v2 ; CHECK-P9-NEXT: stxv vs0, 0(r3) @@ -471,8 +471,8 @@ ; CHECK-BE-NEXT: lxv v2, 0(r4) ; CHECK-BE-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addi r4, r4, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxv v3, 0(r4) -; CHECK-BE-NEXT: vperm v2, v2, v2, v3 +; CHECK-BE-NEXT: lxv vs0, 0(r4) +; CHECK-BE-NEXT: xxperm v2, v2, vs0 ; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: xvcvsxddp vs0, v2 ; CHECK-BE-NEXT: stxv vs0, 0(r3) diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll @@ -50,19 +50,19 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtfprd f0, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; CHECK-BE-NEXT: xscvspdpn f1, vs0 +; CHECK-BE-NEXT: xscvspdpn f2, vs0 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) +; CHECK-BE-NEXT: lxv vs1, 0(r3) ; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 +; CHECK-BE-NEXT: mtfprwz f2, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: li r3, 0 -; CHECK-BE-NEXT: vperm v2, v3, v4, v2 +; CHECK-BE-NEXT: xxperm v2, vs2, vs1 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: blr entry: @@ -130,31 +130,31 @@ ; ; CHECK-BE-LABEL: test4elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 +; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 3 +; CHECK-BE-NEXT: xxswapd vs2, v2 ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xxswapd vs0, v2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xscvspdpn f0, v2 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v4, v5, v4, v3 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v2, r3 -; CHECK-BE-NEXT: vperm v2, v5, v2, v3 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v4 +; CHECK-BE-NEXT: xxsldwi vs3, v2, v2, 1 +; CHECK-BE-NEXT: xscvspdpn f1, vs1 +; CHECK-BE-NEXT: xscvspdpn f2, vs2 +; CHECK-BE-NEXT: xscvspdpn f3, vs3 +; CHECK-BE-NEXT: lxv vs0, 0(r3) +; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 +; CHECK-BE-NEXT: mtfprwz f2, r3 +; CHECK-BE-NEXT: xxperm vs1, vs2, vs0 +; CHECK-BE-NEXT: xscvspdpn f2, v2 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 +; CHECK-BE-NEXT: mffprwz r3, f2 +; CHECK-BE-NEXT: mtfprwz f2, r3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: xxperm vs3, vs2, vs0 +; CHECK-BE-NEXT: xxmrghw vs0, vs3, vs1 ; CHECK-BE-NEXT: mffprd r3, f0 ; CHECK-BE-NEXT: blr entry: @@ -273,51 +273,51 @@ ; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xxswapd vs2, vs1 -; CHECK-BE-NEXT: mtvsrwz v3, r3 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xscvspdpn f2, vs1 +; CHECK-BE-NEXT: lxv vs2, 0(r3) +; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3 +; CHECK-BE-NEXT: xxswapd vs4, vs1 +; CHECK-BE-NEXT: xscvspdpn f3, vs3 +; CHECK-BE-NEXT: xscvspdpn f4, vs4 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: xscvdpsxws f4, f4 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: mffprwz r3, f4 +; CHECK-BE-NEXT: mtfprwz f4, r3 +; CHECK-BE-NEXT: xxperm vs3, vs4, vs2 +; CHECK-BE-NEXT: xscvspdpn f4, vs1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 +; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 +; CHECK-BE-NEXT: mffprwz r3, f4 +; CHECK-BE-NEXT: mtfprwz f4, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 -; CHECK-BE-NEXT: xxmrghw vs1, v4, v3 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xxswapd vs2, vs0 -; CHECK-BE-NEXT: mtvsrwz v3, r3 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xscvspdpn f2, vs0 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: xxperm vs1, vs4, vs2 +; CHECK-BE-NEXT: xxswapd vs4, vs0 +; CHECK-BE-NEXT: xxmrghw vs1, vs1, vs3 +; CHECK-BE-NEXT: xxsldwi vs3, vs0, vs0, 3 +; CHECK-BE-NEXT: xscvspdpn f4, vs4 +; CHECK-BE-NEXT: xscvspdpn f3, vs3 +; CHECK-BE-NEXT: xscvdpsxws f4, f4 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: mffprwz r3, f4 +; CHECK-BE-NEXT: mtfprwz f4, r3 +; CHECK-BE-NEXT: xxperm vs3, vs4, vs2 +; CHECK-BE-NEXT: xscvspdpn f4, vs0 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 +; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mffprwz r3, f4 +; CHECK-BE-NEXT: mtfprwz f4, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: vperm v2, v4, v5, v2 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtfprwz f0, r3 +; CHECK-BE-NEXT: xxperm vs0, vs4, vs2 +; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs3 ; CHECK-BE-NEXT: xxmrghd v2, vs0, vs1 ; CHECK-BE-NEXT: blr entry: @@ -534,104 +534,104 @@ ; ; CHECK-BE-LABEL: test16elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: lxv vs1, 16(r4) +; CHECK-BE-NEXT: lxv vs2, 16(r4) +; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: addis r5, r2, .LCPI3_0@toc@ha -; CHECK-BE-NEXT: lxv vs0, 0(r4) +; CHECK-BE-NEXT: lxv vs0, 48(r4) ; CHECK-BE-NEXT: addi r5, r5, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r5) -; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 -; CHECK-BE-NEXT: xxswapd vs3, vs1 -; CHECK-BE-NEXT: xscvspdpn f4, vs1 +; CHECK-BE-NEXT: lxv vs3, 0(r5) +; CHECK-BE-NEXT: xscvspdpn f6, vs2 +; CHECK-BE-NEXT: xxsldwi vs4, vs2, vs2, 3 +; CHECK-BE-NEXT: xscvspdpn f9, vs1 +; CHECK-BE-NEXT: xxswapd vs5, vs2 +; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1 +; CHECK-BE-NEXT: xxsldwi vs7, vs1, vs1, 3 +; CHECK-BE-NEXT: xxswapd vs8, vs1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 -; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 3 +; CHECK-BE-NEXT: xxsldwi vs10, vs0, vs0, 3 +; CHECK-BE-NEXT: xxswapd vs11, vs0 +; CHECK-BE-NEXT: xscvdpsxws f6, f6 +; CHECK-BE-NEXT: xscvspdpn f4, vs4 +; CHECK-BE-NEXT: xscvdpsxws f9, f9 +; CHECK-BE-NEXT: xscvspdpn f5, vs5 ; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: xscvspdpn f3, vs3 +; CHECK-BE-NEXT: xscvspdpn f7, vs7 +; CHECK-BE-NEXT: xscvspdpn f8, vs8 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 +; CHECK-BE-NEXT: xscvspdpn f10, vs10 +; CHECK-BE-NEXT: xscvspdpn f11, vs11 +; CHECK-BE-NEXT: xscvdpsxws f4, f4 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: xscvdpsxws f7, f7 +; CHECK-BE-NEXT: xscvdpsxws f8, f8 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: xscvdpsxws f10, f10 +; CHECK-BE-NEXT: xscvdpsxws f11, f11 +; CHECK-BE-NEXT: mffprwz r5, f6 +; CHECK-BE-NEXT: mtfprwz f6, r5 +; CHECK-BE-NEXT: mffprwz r5, f9 +; CHECK-BE-NEXT: mtfprwz f9, r5 +; CHECK-BE-NEXT: mffprwz r5, f4 +; CHECK-BE-NEXT: mtfprwz f4, r5 +; CHECK-BE-NEXT: mffprwz r5, f5 +; CHECK-BE-NEXT: mtfprwz f5, r5 ; CHECK-BE-NEXT: mffprwz r5, f2 -; CHECK-BE-NEXT: xxswapd vs2, vs0 -; CHECK-BE-NEXT: mtvsrwz v3, r5 -; CHECK-BE-NEXT: mffprwz r5, f3 -; CHECK-BE-NEXT: xscvdpsxws f3, f4 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: mtvsrwz v4, r5 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: mffprwz r5, f3 -; CHECK-BE-NEXT: xscvspdpn f3, vs5 -; CHECK-BE-NEXT: mtvsrwz v4, r5 -; CHECK-BE-NEXT: mffprwz r5, f1 -; CHECK-BE-NEXT: xscvspdpn f1, vs0 +; CHECK-BE-NEXT: xxperm vs4, vs5, vs3 +; CHECK-BE-NEXT: xscvspdpn f5, vs0 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: mtvsrwz v5, r5 -; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: mtfprwz f2, r5 +; CHECK-BE-NEXT: mffprwz r5, f7 +; CHECK-BE-NEXT: mtfprwz f7, r5 +; CHECK-BE-NEXT: mffprwz r5, f8 +; CHECK-BE-NEXT: xxperm vs2, vs6, vs3 ; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 +; CHECK-BE-NEXT: mtfprwz f8, r5 ; CHECK-BE-NEXT: mffprwz r5, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r5 -; CHECK-BE-NEXT: mffprwz r5, f3 -; CHECK-BE-NEXT: mtvsrwz v0, r5 -; CHECK-BE-NEXT: mffprwz r5, f2 -; CHECK-BE-NEXT: xxmrghw vs2, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v1, r5 -; CHECK-BE-NEXT: mffprwz r5, f0 -; CHECK-BE-NEXT: lxv vs0, 48(r4) -; CHECK-BE-NEXT: vperm v0, v1, v0, v2 -; CHECK-BE-NEXT: mtvsrwz v1, r5 -; CHECK-BE-NEXT: vperm v5, v5, v1, v2 -; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 -; CHECK-BE-NEXT: xxswapd vs3, vs0 -; CHECK-BE-NEXT: xscvspdpn f4, vs0 -; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 -; CHECK-BE-NEXT: xscvspdpn f1, vs1 -; CHECK-BE-NEXT: xscvspdpn f3, vs3 -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f4, f4 -; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: xxmrghw vs2, vs2, vs4 +; CHECK-BE-NEXT: lxv vs4, 32(r4) ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r5, f1 -; CHECK-BE-NEXT: lxv vs1, 32(r4) -; CHECK-BE-NEXT: mffprwz r4, f4 -; CHECK-BE-NEXT: mtvsrwz v3, r5 -; CHECK-BE-NEXT: mffprwz r5, f3 -; CHECK-BE-NEXT: xxmrghw vs3, v5, v0 -; CHECK-BE-NEXT: mtvsrwz v4, r5 -; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2 -; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 -; CHECK-BE-NEXT: mtvsrwz v4, r4 +; CHECK-BE-NEXT: mtfprwz f1, r5 +; CHECK-BE-NEXT: xxperm vs7, vs8, vs3 +; CHECK-BE-NEXT: mffprwz r5, f10 +; CHECK-BE-NEXT: xxperm vs1, vs9, vs3 +; CHECK-BE-NEXT: mtfprwz f10, r5 +; CHECK-BE-NEXT: mffprwz r5, f11 +; CHECK-BE-NEXT: mffprwz r4, f5 +; CHECK-BE-NEXT: mtfprwz f11, r5 +; CHECK-BE-NEXT: xxmrghw vs1, vs1, vs7 +; CHECK-BE-NEXT: mtfprwz f5, r4 +; CHECK-BE-NEXT: xxperm vs10, vs11, vs3 ; CHECK-BE-NEXT: mffprwz r4, f0 -; CHECK-BE-NEXT: xscvspdpn f3, vs3 -; CHECK-BE-NEXT: mtvsrwz v5, r4 -; CHECK-BE-NEXT: stxv vs2, 0(r3) -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: xxmrghw vs0, v4, v3 -; CHECK-BE-NEXT: mffprwz r4, f3 -; CHECK-BE-NEXT: xxswapd vs3, vs1 -; CHECK-BE-NEXT: mtvsrwz v3, r4 -; CHECK-BE-NEXT: xscvspdpn f3, vs3 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: mffprwz r4, f3 -; CHECK-BE-NEXT: xscvspdpn f3, vs1 -; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 -; CHECK-BE-NEXT: mtvsrwz v4, r4 -; CHECK-BE-NEXT: xscvspdpn f1, vs1 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 -; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mffprwz r4, f3 -; CHECK-BE-NEXT: mtvsrwz v4, r4 -; CHECK-BE-NEXT: mffprwz r4, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r4 -; CHECK-BE-NEXT: vperm v2, v4, v5, v2 -; CHECK-BE-NEXT: xxmrghw vs1, v2, v3 -; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0 +; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs2 +; CHECK-BE-NEXT: xxsldwi vs2, vs4, vs4, 3 +; CHECK-BE-NEXT: mtfprwz f0, r4 +; CHECK-BE-NEXT: xxperm vs0, vs5, vs3 +; CHECK-BE-NEXT: xxswapd vs5, vs4 +; CHECK-BE-NEXT: xscvspdpn f2, vs2 +; CHECK-BE-NEXT: stxv vs1, 0(r3) +; CHECK-BE-NEXT: xscvspdpn f5, vs5 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 +; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs10 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 +; CHECK-BE-NEXT: mffprwz r4, f2 +; CHECK-BE-NEXT: mtfprwz f2, r4 +; CHECK-BE-NEXT: mffprwz r4, f5 +; CHECK-BE-NEXT: mtfprwz f5, r4 +; CHECK-BE-NEXT: xxperm vs2, vs5, vs3 +; CHECK-BE-NEXT: xscvspdpn f5, vs4 +; CHECK-BE-NEXT: xxsldwi vs4, vs4, vs4, 1 +; CHECK-BE-NEXT: xscvspdpn f4, vs4 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 +; CHECK-BE-NEXT: xscvdpsxws f4, f4 +; CHECK-BE-NEXT: mffprwz r4, f5 +; CHECK-BE-NEXT: mtfprwz f5, r4 +; CHECK-BE-NEXT: mffprwz r4, f4 +; CHECK-BE-NEXT: mtfprwz f4, r4 +; CHECK-BE-NEXT: xxperm vs4, vs5, vs3 +; CHECK-BE-NEXT: xxmrghw vs2, vs4, vs2 +; CHECK-BE-NEXT: xxmrghd vs0, vs2, vs0 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: blr entry: @@ -682,19 +682,19 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtfprd f0, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-BE-NEXT: xscvspdpn f1, vs0 +; CHECK-BE-NEXT: xscvspdpn f2, vs0 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) +; CHECK-BE-NEXT: lxv vs1, 0(r3) ; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 +; CHECK-BE-NEXT: mtfprwz f2, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: li r3, 0 -; CHECK-BE-NEXT: vperm v2, v3, v4, v2 +; CHECK-BE-NEXT: xxperm v2, vs2, vs1 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: blr entry: @@ -762,31 +762,31 @@ ; ; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 +; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 3 +; CHECK-BE-NEXT: xxswapd vs2, v2 ; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xxswapd vs0, v2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xscvspdpn f0, v2 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v4, v5, v4, v3 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v2, r3 -; CHECK-BE-NEXT: vperm v2, v5, v2, v3 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v4 +; CHECK-BE-NEXT: xxsldwi vs3, v2, v2, 1 +; CHECK-BE-NEXT: xscvspdpn f1, vs1 +; CHECK-BE-NEXT: xscvspdpn f2, vs2 +; CHECK-BE-NEXT: xscvspdpn f3, vs3 +; CHECK-BE-NEXT: lxv vs0, 0(r3) +; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 +; CHECK-BE-NEXT: mtfprwz f2, r3 +; CHECK-BE-NEXT: xxperm vs1, vs2, vs0 +; CHECK-BE-NEXT: xscvspdpn f2, v2 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 +; CHECK-BE-NEXT: mffprwz r3, f2 +; CHECK-BE-NEXT: mtfprwz f2, r3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: xxperm vs3, vs2, vs0 +; CHECK-BE-NEXT: xxmrghw vs0, vs3, vs1 ; CHECK-BE-NEXT: mffprd r3, f0 ; CHECK-BE-NEXT: blr entry: @@ -905,51 +905,51 @@ ; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xxswapd vs2, vs1 -; CHECK-BE-NEXT: mtvsrwz v3, r3 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xscvspdpn f2, vs1 +; CHECK-BE-NEXT: lxv vs2, 0(r3) +; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3 +; CHECK-BE-NEXT: xxswapd vs4, vs1 +; CHECK-BE-NEXT: xscvspdpn f3, vs3 +; CHECK-BE-NEXT: xscvspdpn f4, vs4 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: xscvdpsxws f4, f4 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: mffprwz r3, f4 +; CHECK-BE-NEXT: mtfprwz f4, r3 +; CHECK-BE-NEXT: xxperm vs3, vs4, vs2 +; CHECK-BE-NEXT: xscvspdpn f4, vs1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 +; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 +; CHECK-BE-NEXT: mffprwz r3, f4 +; CHECK-BE-NEXT: mtfprwz f4, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 -; CHECK-BE-NEXT: xxmrghw vs1, v4, v3 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xxswapd vs2, vs0 -; CHECK-BE-NEXT: mtvsrwz v3, r3 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xscvspdpn f2, vs0 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: xxperm vs1, vs4, vs2 +; CHECK-BE-NEXT: xxswapd vs4, vs0 +; CHECK-BE-NEXT: xxmrghw vs1, vs1, vs3 +; CHECK-BE-NEXT: xxsldwi vs3, vs0, vs0, 3 +; CHECK-BE-NEXT: xscvspdpn f4, vs4 +; CHECK-BE-NEXT: xscvspdpn f3, vs3 +; CHECK-BE-NEXT: xscvdpsxws f4, f4 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: mffprwz r3, f4 +; CHECK-BE-NEXT: mtfprwz f4, r3 +; CHECK-BE-NEXT: xxperm vs3, vs4, vs2 +; CHECK-BE-NEXT: xscvspdpn f4, vs0 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 +; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mffprwz r3, f4 +; CHECK-BE-NEXT: mtfprwz f4, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: vperm v2, v4, v5, v2 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtfprwz f0, r3 +; CHECK-BE-NEXT: xxperm vs0, vs4, vs2 +; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs3 ; CHECK-BE-NEXT: xxmrghd v2, vs0, vs1 ; CHECK-BE-NEXT: blr entry: @@ -1166,104 +1166,104 @@ ; ; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: lxv vs1, 16(r4) +; CHECK-BE-NEXT: lxv vs2, 16(r4) +; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha -; CHECK-BE-NEXT: lxv vs0, 0(r4) +; CHECK-BE-NEXT: lxv vs0, 48(r4) ; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r5) -; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 -; CHECK-BE-NEXT: xxswapd vs3, vs1 -; CHECK-BE-NEXT: xscvspdpn f4, vs1 +; CHECK-BE-NEXT: lxv vs3, 0(r5) +; CHECK-BE-NEXT: xscvspdpn f6, vs2 +; CHECK-BE-NEXT: xxsldwi vs4, vs2, vs2, 3 +; CHECK-BE-NEXT: xscvspdpn f9, vs1 +; CHECK-BE-NEXT: xxswapd vs5, vs2 +; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1 +; CHECK-BE-NEXT: xxsldwi vs7, vs1, vs1, 3 +; CHECK-BE-NEXT: xxswapd vs8, vs1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 -; CHECK-BE-NEXT: xxsldwi vs5, vs0, vs0, 3 +; CHECK-BE-NEXT: xxsldwi vs10, vs0, vs0, 3 +; CHECK-BE-NEXT: xxswapd vs11, vs0 +; CHECK-BE-NEXT: xscvdpsxws f6, f6 +; CHECK-BE-NEXT: xscvspdpn f4, vs4 +; CHECK-BE-NEXT: xscvdpsxws f9, f9 +; CHECK-BE-NEXT: xscvspdpn f5, vs5 ; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: xscvspdpn f3, vs3 +; CHECK-BE-NEXT: xscvspdpn f7, vs7 +; CHECK-BE-NEXT: xscvspdpn f8, vs8 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 +; CHECK-BE-NEXT: xscvspdpn f10, vs10 +; CHECK-BE-NEXT: xscvspdpn f11, vs11 +; CHECK-BE-NEXT: xscvdpsxws f4, f4 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: xscvdpsxws f7, f7 +; CHECK-BE-NEXT: xscvdpsxws f8, f8 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: xscvdpsxws f10, f10 +; CHECK-BE-NEXT: xscvdpsxws f11, f11 +; CHECK-BE-NEXT: mffprwz r5, f6 +; CHECK-BE-NEXT: mtfprwz f6, r5 +; CHECK-BE-NEXT: mffprwz r5, f9 +; CHECK-BE-NEXT: mtfprwz f9, r5 +; CHECK-BE-NEXT: mffprwz r5, f4 +; CHECK-BE-NEXT: mtfprwz f4, r5 +; CHECK-BE-NEXT: mffprwz r5, f5 +; CHECK-BE-NEXT: mtfprwz f5, r5 ; CHECK-BE-NEXT: mffprwz r5, f2 -; CHECK-BE-NEXT: xxswapd vs2, vs0 -; CHECK-BE-NEXT: mtvsrwz v3, r5 -; CHECK-BE-NEXT: mffprwz r5, f3 -; CHECK-BE-NEXT: xscvdpsxws f3, f4 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: mtvsrwz v4, r5 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: mffprwz r5, f3 -; CHECK-BE-NEXT: xscvspdpn f3, vs5 -; CHECK-BE-NEXT: mtvsrwz v4, r5 -; CHECK-BE-NEXT: mffprwz r5, f1 -; CHECK-BE-NEXT: xscvspdpn f1, vs0 +; CHECK-BE-NEXT: xxperm vs4, vs5, vs3 +; CHECK-BE-NEXT: xscvspdpn f5, vs0 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: mtvsrwz v5, r5 -; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: mtfprwz f2, r5 +; CHECK-BE-NEXT: mffprwz r5, f7 +; CHECK-BE-NEXT: mtfprwz f7, r5 +; CHECK-BE-NEXT: mffprwz r5, f8 +; CHECK-BE-NEXT: xxperm vs2, vs6, vs3 ; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 +; CHECK-BE-NEXT: mtfprwz f8, r5 ; CHECK-BE-NEXT: mffprwz r5, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r5 -; CHECK-BE-NEXT: mffprwz r5, f3 -; CHECK-BE-NEXT: mtvsrwz v0, r5 -; CHECK-BE-NEXT: mffprwz r5, f2 -; CHECK-BE-NEXT: xxmrghw vs2, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v1, r5 -; CHECK-BE-NEXT: mffprwz r5, f0 -; CHECK-BE-NEXT: lxv vs0, 48(r4) -; CHECK-BE-NEXT: vperm v0, v1, v0, v2 -; CHECK-BE-NEXT: mtvsrwz v1, r5 -; CHECK-BE-NEXT: vperm v5, v5, v1, v2 -; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 -; CHECK-BE-NEXT: xxswapd vs3, vs0 -; CHECK-BE-NEXT: xscvspdpn f4, vs0 -; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 -; CHECK-BE-NEXT: xscvspdpn f1, vs1 -; CHECK-BE-NEXT: xscvspdpn f3, vs3 -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f4, f4 -; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: xxmrghw vs2, vs2, vs4 +; CHECK-BE-NEXT: lxv vs4, 32(r4) ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r5, f1 -; CHECK-BE-NEXT: lxv vs1, 32(r4) -; CHECK-BE-NEXT: mffprwz r4, f4 -; CHECK-BE-NEXT: mtvsrwz v3, r5 -; CHECK-BE-NEXT: mffprwz r5, f3 -; CHECK-BE-NEXT: xxmrghw vs3, v5, v0 -; CHECK-BE-NEXT: mtvsrwz v4, r5 -; CHECK-BE-NEXT: xxmrghd vs2, vs3, vs2 -; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 -; CHECK-BE-NEXT: mtvsrwz v4, r4 +; CHECK-BE-NEXT: mtfprwz f1, r5 +; CHECK-BE-NEXT: xxperm vs7, vs8, vs3 +; CHECK-BE-NEXT: mffprwz r5, f10 +; CHECK-BE-NEXT: xxperm vs1, vs9, vs3 +; CHECK-BE-NEXT: mtfprwz f10, r5 +; CHECK-BE-NEXT: mffprwz r5, f11 +; CHECK-BE-NEXT: mffprwz r4, f5 +; CHECK-BE-NEXT: mtfprwz f11, r5 +; CHECK-BE-NEXT: xxmrghw vs1, vs1, vs7 +; CHECK-BE-NEXT: mtfprwz f5, r4 +; CHECK-BE-NEXT: xxperm vs10, vs11, vs3 ; CHECK-BE-NEXT: mffprwz r4, f0 -; CHECK-BE-NEXT: xscvspdpn f3, vs3 -; CHECK-BE-NEXT: mtvsrwz v5, r4 -; CHECK-BE-NEXT: stxv vs2, 0(r3) -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: xxmrghw vs0, v4, v3 -; CHECK-BE-NEXT: mffprwz r4, f3 -; CHECK-BE-NEXT: xxswapd vs3, vs1 -; CHECK-BE-NEXT: mtvsrwz v3, r4 -; CHECK-BE-NEXT: xscvspdpn f3, vs3 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: mffprwz r4, f3 -; CHECK-BE-NEXT: xscvspdpn f3, vs1 -; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 -; CHECK-BE-NEXT: mtvsrwz v4, r4 -; CHECK-BE-NEXT: xscvspdpn f1, vs1 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 -; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mffprwz r4, f3 -; CHECK-BE-NEXT: mtvsrwz v4, r4 -; CHECK-BE-NEXT: mffprwz r4, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r4 -; CHECK-BE-NEXT: vperm v2, v4, v5, v2 -; CHECK-BE-NEXT: xxmrghw vs1, v2, v3 -; CHECK-BE-NEXT: xxmrghd vs0, vs1, vs0 +; CHECK-BE-NEXT: xxmrghd vs1, vs1, vs2 +; CHECK-BE-NEXT: xxsldwi vs2, vs4, vs4, 3 +; CHECK-BE-NEXT: mtfprwz f0, r4 +; CHECK-BE-NEXT: xxperm vs0, vs5, vs3 +; CHECK-BE-NEXT: xxswapd vs5, vs4 +; CHECK-BE-NEXT: xscvspdpn f2, vs2 +; CHECK-BE-NEXT: stxv vs1, 0(r3) +; CHECK-BE-NEXT: xscvspdpn f5, vs5 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 +; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs10 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 +; CHECK-BE-NEXT: mffprwz r4, f2 +; CHECK-BE-NEXT: mtfprwz f2, r4 +; CHECK-BE-NEXT: mffprwz r4, f5 +; CHECK-BE-NEXT: mtfprwz f5, r4 +; CHECK-BE-NEXT: xxperm vs2, vs5, vs3 +; CHECK-BE-NEXT: xscvspdpn f5, vs4 +; CHECK-BE-NEXT: xxsldwi vs4, vs4, vs4, 1 +; CHECK-BE-NEXT: xscvspdpn f4, vs4 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 +; CHECK-BE-NEXT: xscvdpsxws f4, f4 +; CHECK-BE-NEXT: mffprwz r4, f5 +; CHECK-BE-NEXT: mtfprwz f5, r4 +; CHECK-BE-NEXT: mffprwz r4, f4 +; CHECK-BE-NEXT: mtfprwz f4, r4 +; CHECK-BE-NEXT: xxperm vs4, vs5, vs3 +; CHECK-BE-NEXT: xxmrghw vs2, vs4, vs2 +; CHECK-BE-NEXT: xxmrghd vs0, vs2, vs0 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll @@ -55,19 +55,19 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtfprd f0, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; CHECK-BE-NEXT: xscvspdpn f1, vs0 +; CHECK-BE-NEXT: xscvspdpn f2, vs0 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) +; CHECK-BE-NEXT: lxv vs1, 0(r3) ; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 +; CHECK-BE-NEXT: mtfprwz f2, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: addi r3, r1, -2 -; CHECK-BE-NEXT: vperm v2, v3, v4, v2 +; CHECK-BE-NEXT: xxperm v2, vs2, vs1 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10 ; CHECK-BE-NEXT: stxsihx v2, 0, r3 ; CHECK-BE-NEXT: lhz r3, -2(r1) @@ -138,32 +138,32 @@ ; ; CHECK-BE-LABEL: test4elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 +; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha +; CHECK-BE-NEXT: xxsldwi vs2, v2, v2, 1 ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xxswapd vs0, v2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xscvspdpn f0, v2 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v4, v5, v4, v3 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 +; CHECK-BE-NEXT: xscvspdpn f1, vs1 +; CHECK-BE-NEXT: xscvspdpn f2, vs2 +; CHECK-BE-NEXT: lxv vs0, 0(r3) +; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 +; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: xxswapd vs1, v2 +; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: xscvspdpn f1, vs1 +; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: xxperm v3, vs1, vs0 +; CHECK-BE-NEXT: xscvspdpn f1, v2 +; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: li r3, 0 -; CHECK-BE-NEXT: vperm v2, v5, v2, v3 -; CHECK-BE-NEXT: vmrghh v2, v2, v4 +; CHECK-BE-NEXT: xxperm v2, vs1, vs0 +; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: blr entry: @@ -285,52 +285,52 @@ ; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xxswapd vs2, vs1 -; CHECK-BE-NEXT: mtvsrwz v3, r3 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xscvspdpn f2, vs1 +; CHECK-BE-NEXT: lxv vs2, 0(r3) +; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3 +; CHECK-BE-NEXT: xscvspdpn f3, vs3 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: xxswapd vs3, vs1 +; CHECK-BE-NEXT: mtvsrwz v2, r3 +; CHECK-BE-NEXT: xscvspdpn f3, vs3 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: xxperm v2, vs3, vs2 +; CHECK-BE-NEXT: xscvspdpn f3, vs1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs3, vs2 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: xxperm v3, vs1, vs2 ; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 ; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: vperm v4, v5, v4, v2 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtfprwz f1, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v0, r3 -; CHECK-BE-NEXT: vperm v2, v5, v0, v2 -; CHECK-BE-NEXT: vmrghh v2, v2, v4 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: xxperm v4, vs1, vs2 +; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: xxmrghw vs0, v3, v2 ; CHECK-BE-NEXT: mffprd r3, f0 ; CHECK-BE-NEXT: blr entry: @@ -550,97 +550,97 @@ ; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3 -; CHECK-BE-NEXT: xscvspdpn f4, vs4 -; CHECK-BE-NEXT: xscvdpsxws f4, f4 -; CHECK-BE-NEXT: mffprwz r3, f4 -; CHECK-BE-NEXT: xxswapd vs4, vs3 -; CHECK-BE-NEXT: mtvsrwz v3, r3 -; CHECK-BE-NEXT: xscvspdpn f4, vs4 -; CHECK-BE-NEXT: xscvdpsxws f4, f4 -; CHECK-BE-NEXT: mffprwz r3, f4 -; CHECK-BE-NEXT: xscvspdpn f4, vs3 +; CHECK-BE-NEXT: lxv vs4, 0(r3) +; CHECK-BE-NEXT: xxsldwi vs5, vs3, vs3, 3 +; CHECK-BE-NEXT: xscvspdpn f5, vs5 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 +; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: xxswapd vs5, vs3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 +; CHECK-BE-NEXT: xscvspdpn f5, vs5 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 +; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: mtfprwz f5, r3 +; CHECK-BE-NEXT: xxperm v2, vs5, vs4 +; CHECK-BE-NEXT: xscvspdpn f5, vs3 ; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3 -; CHECK-BE-NEXT: xscvdpsxws f4, f4 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: mffprwz r3, f4 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: mtfprwz f5, r3 ; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs5, vs4 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: xxswapd vs3, vs2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: xxperm v3, vs3, vs4 ; CHECK-BE-NEXT: xscvspdpn f3, vs2 ; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: vperm v4, v5, v4, v2 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 +; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: xxperm v4, vs3, vs4 ; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3 -; CHECK-BE-NEXT: mtvsrwz v5, r3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: mtvsrwz v0, r3 +; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: vperm v5, v5, v0, v2 -; CHECK-BE-NEXT: vmrghh v4, v5, v4 +; CHECK-BE-NEXT: xxmrghw vs2, v3, v2 ; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: xxswapd vs3, vs1 -; CHECK-BE-NEXT: xxmrghw vs2, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: xxperm v2, vs3, vs4 ; CHECK-BE-NEXT: xscvspdpn f3, vs1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: mffprwz r3, f3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs3, vs4 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: xxperm v3, vs1, vs4 ; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 ; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: vperm v4, v5, v4, v2 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtfprwz f1, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v0, r3 -; CHECK-BE-NEXT: vperm v2, v5, v0, v2 -; CHECK-BE-NEXT: vmrghh v2, v2, v4 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: xxperm v4, vs1, vs4 +; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: xxmrghw vs0, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, vs0, vs2 ; CHECK-BE-NEXT: blr entry: @@ -695,19 +695,19 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: mtfprd f0, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha -; CHECK-BE-NEXT: xscvspdpn f1, vs0 +; CHECK-BE-NEXT: xscvspdpn f2, vs0 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) +; CHECK-BE-NEXT: lxv vs1, 0(r3) ; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 +; CHECK-BE-NEXT: mtfprwz f2, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: addi r3, r1, -2 -; CHECK-BE-NEXT: vperm v2, v3, v4, v2 +; CHECK-BE-NEXT: xxperm v2, vs2, vs1 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10 ; CHECK-BE-NEXT: stxsihx v2, 0, r3 ; CHECK-BE-NEXT: lhz r3, -2(r1) @@ -778,32 +778,32 @@ ; ; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 +; CHECK-BE-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha +; CHECK-BE-NEXT: xxsldwi vs2, v2, v2, 1 ; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xxswapd vs0, v2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xscvspdpn f0, v2 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v4, v5, v4, v3 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: xscvspdpn f0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 +; CHECK-BE-NEXT: xscvspdpn f1, vs1 +; CHECK-BE-NEXT: xscvspdpn f2, vs2 +; CHECK-BE-NEXT: lxv vs0, 0(r3) +; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 +; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: xxswapd vs1, v2 +; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: xscvspdpn f1, vs1 +; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: xxperm v3, vs1, vs0 +; CHECK-BE-NEXT: xscvspdpn f1, v2 +; CHECK-BE-NEXT: xscvdpsxws f1, f1 +; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: li r3, 0 -; CHECK-BE-NEXT: vperm v2, v5, v2, v3 -; CHECK-BE-NEXT: vmrghh v2, v2, v4 +; CHECK-BE-NEXT: xxperm v2, vs1, vs0 +; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: blr entry: @@ -925,52 +925,52 @@ ; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xxswapd vs2, vs1 -; CHECK-BE-NEXT: mtvsrwz v3, r3 -; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: xscvspdpn f2, vs1 +; CHECK-BE-NEXT: lxv vs2, 0(r3) +; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3 +; CHECK-BE-NEXT: xscvspdpn f3, vs3 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: xxswapd vs3, vs1 +; CHECK-BE-NEXT: mtvsrwz v2, r3 +; CHECK-BE-NEXT: xscvspdpn f3, vs3 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: xxperm v2, vs3, vs2 +; CHECK-BE-NEXT: xscvspdpn f3, vs1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs3, vs2 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: xxperm v3, vs1, vs2 ; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 ; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: vperm v4, v5, v4, v2 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtfprwz f1, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v0, r3 -; CHECK-BE-NEXT: vperm v2, v5, v0, v2 -; CHECK-BE-NEXT: vmrghh v2, v2, v4 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: xxperm v4, vs1, vs2 +; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: xxmrghw vs0, v3, v2 ; CHECK-BE-NEXT: mffprd r3, f0 ; CHECK-BE-NEXT: blr entry: @@ -1190,97 +1190,97 @@ ; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI7_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3 -; CHECK-BE-NEXT: xscvspdpn f4, vs4 -; CHECK-BE-NEXT: xscvdpsxws f4, f4 -; CHECK-BE-NEXT: mffprwz r3, f4 -; CHECK-BE-NEXT: xxswapd vs4, vs3 -; CHECK-BE-NEXT: mtvsrwz v3, r3 -; CHECK-BE-NEXT: xscvspdpn f4, vs4 -; CHECK-BE-NEXT: xscvdpsxws f4, f4 -; CHECK-BE-NEXT: mffprwz r3, f4 -; CHECK-BE-NEXT: xscvspdpn f4, vs3 +; CHECK-BE-NEXT: lxv vs4, 0(r3) +; CHECK-BE-NEXT: xxsldwi vs5, vs3, vs3, 3 +; CHECK-BE-NEXT: xscvspdpn f5, vs5 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 +; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: xxswapd vs5, vs3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 +; CHECK-BE-NEXT: xscvspdpn f5, vs5 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 +; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: mtfprwz f5, r3 +; CHECK-BE-NEXT: xxperm v2, vs5, vs4 +; CHECK-BE-NEXT: xscvspdpn f5, vs3 ; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3 -; CHECK-BE-NEXT: xscvdpsxws f4, f4 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: mffprwz r3, f4 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: mtfprwz f5, r3 ; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs5, vs4 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: xxswapd vs3, vs2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: xxperm v3, vs3, vs4 ; CHECK-BE-NEXT: xscvspdpn f3, vs2 ; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvspdpn f2, vs2 -; CHECK-BE-NEXT: vperm v4, v5, v4, v2 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 +; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: xxperm v4, vs3, vs4 ; CHECK-BE-NEXT: xxsldwi vs3, vs1, vs1, 3 -; CHECK-BE-NEXT: mtvsrwz v5, r3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: mtvsrwz v0, r3 +; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: vperm v5, v5, v0, v2 -; CHECK-BE-NEXT: vmrghh v4, v5, v4 +; CHECK-BE-NEXT: xxmrghw vs2, v3, v2 ; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: xxswapd vs3, vs1 -; CHECK-BE-NEXT: xxmrghw vs2, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: xxperm v2, vs3, vs4 ; CHECK-BE-NEXT: xscvspdpn f3, vs1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: mffprwz r3, f3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs3, vs4 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: xxperm v3, vs1, vs4 ; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 ; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: vperm v4, v5, v4, v2 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtfprwz f1, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v0, r3 -; CHECK-BE-NEXT: vperm v2, v5, v0, v2 -; CHECK-BE-NEXT: vmrghh v2, v2, v4 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: xxperm v4, vs1, vs4 +; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: xxmrghw vs0, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, vs0, vs2 ; CHECK-BE-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll @@ -40,18 +40,18 @@ ; ; CHECK-BE-LABEL: test2elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: xscvdpsxws f0, v2 +; CHECK-BE-NEXT: xxswapd vs2, v2 +; CHECK-BE-NEXT: xscvdpsxws f1, v2 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xxswapd vs0, v2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 +; CHECK-BE-NEXT: lxv vs0, 0(r3) +; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: li r3, 0 -; CHECK-BE-NEXT: vperm v2, v4, v2, v3 +; CHECK-BE-NEXT: xxperm v2, vs1, vs0 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: blr entry: @@ -117,24 +117,24 @@ ; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xscvdpsxws f2, f1 +; CHECK-BE-NEXT: lxv vs2, 0(r3) +; CHECK-BE-NEXT: xscvdpsxws f3, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: xscvdpsxws f1, f0 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: xxperm vs1, vs3, vs2 +; CHECK-BE-NEXT: xscvdpsxws f3, f0 ; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 -; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: vperm v2, v4, v5, v2 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtfprwz f0, r3 +; CHECK-BE-NEXT: xxperm vs0, vs3, vs2 +; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs1 ; CHECK-BE-NEXT: mffprd r3, f0 ; CHECK-BE-NEXT: blr entry: @@ -242,41 +242,41 @@ ; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xscvdpsxws f4, f3 +; CHECK-BE-NEXT: lxv vs4, 0(r3) +; CHECK-BE-NEXT: xscvdpsxws f5, f3 ; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: mffprwz r3, f4 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: mtfprwz f5, r3 ; CHECK-BE-NEXT: mffprwz r3, f3 -; CHECK-BE-NEXT: xscvdpsxws f3, f2 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: xxperm vs3, vs5, vs4 +; CHECK-BE-NEXT: xscvdpsxws f5, f2 ; CHECK-BE-NEXT: xxswapd vs2, vs2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 -; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: mtfprwz f5, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 +; CHECK-BE-NEXT: mtfprwz f2, r3 +; CHECK-BE-NEXT: xxperm vs2, vs5, vs4 +; CHECK-BE-NEXT: xxmrghw vs2, vs2, vs3 ; CHECK-BE-NEXT: xscvdpsxws f3, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 ; CHECK-BE-NEXT: mffprwz r3, f3 -; CHECK-BE-NEXT: xxmrghw vs2, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: xscvdpsxws f1, f0 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: xxperm vs1, vs3, vs4 +; CHECK-BE-NEXT: xscvdpsxws f3, f0 ; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 -; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: vperm v2, v4, v5, v2 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtfprwz f0, r3 +; CHECK-BE-NEXT: xxperm vs0, vs3, vs4 +; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs1 ; CHECK-BE-NEXT: xxmrghd v2, vs0, vs2 ; CHECK-BE-NEXT: blr entry: @@ -465,87 +465,87 @@ ; ; CHECK-BE-LABEL: test16elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: lxv vs2, 48(r4) -; CHECK-BE-NEXT: lxv vs1, 32(r4) -; CHECK-BE-NEXT: lxv vs0, 16(r4) -; CHECK-BE-NEXT: addis r5, r2, .LCPI3_0@toc@ha -; CHECK-BE-NEXT: addi r5, r5, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r5) -; CHECK-BE-NEXT: xscvdpsxws f3, f2 -; CHECK-BE-NEXT: xscvdpsxws f4, f1 -; CHECK-BE-NEXT: xxswapd vs2, vs2 -; CHECK-BE-NEXT: xscvdpsxws f5, f0 -; CHECK-BE-NEXT: xxswapd vs1, vs1 -; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r5, f3 +; CHECK-BE-NEXT: lxv vs7, 48(r4) +; CHECK-BE-NEXT: lxv vs0, 64(r4) +; CHECK-BE-NEXT: lxv vs1, 80(r4) +; CHECK-BE-NEXT: lxv vs2, 96(r4) +; CHECK-BE-NEXT: xscvdpsxws f9, f7 +; CHECK-BE-NEXT: xxswapd vs7, vs7 ; CHECK-BE-NEXT: lxv vs3, 112(r4) -; CHECK-BE-NEXT: mtvsrwz v3, r5 -; CHECK-BE-NEXT: mffprwz r5, f4 ; CHECK-BE-NEXT: lxv vs4, 0(r4) -; CHECK-BE-NEXT: mtvsrwz v4, r5 -; CHECK-BE-NEXT: mffprwz r5, f5 -; CHECK-BE-NEXT: xscvdpsxws f7, f3 -; CHECK-BE-NEXT: xxswapd vs3, vs3 -; CHECK-BE-NEXT: mtvsrwz v5, r5 -; CHECK-BE-NEXT: mffprwz r5, f2 -; CHECK-BE-NEXT: lxv vs2, 96(r4) -; CHECK-BE-NEXT: xscvdpsxws f5, f4 +; CHECK-BE-NEXT: lxv vs5, 16(r4) +; CHECK-BE-NEXT: lxv vs6, 32(r4) +; CHECK-BE-NEXT: addis r4, r2, .LCPI3_0@toc@ha +; CHECK-BE-NEXT: addi r4, r4, .LCPI3_0@toc@l +; CHECK-BE-NEXT: lxv vs8, 0(r4) +; CHECK-BE-NEXT: xscvdpsxws f7, f7 +; CHECK-BE-NEXT: mffprwz r4, f9 +; CHECK-BE-NEXT: mtfprwz f9, r4 +; CHECK-BE-NEXT: mffprwz r4, f7 +; CHECK-BE-NEXT: mtfprwz f7, r4 +; CHECK-BE-NEXT: xxperm vs7, vs9, vs8 +; CHECK-BE-NEXT: xscvdpsxws f9, f6 +; CHECK-BE-NEXT: xxswapd vs6, vs6 +; CHECK-BE-NEXT: xscvdpsxws f6, f6 +; CHECK-BE-NEXT: mffprwz r4, f9 +; CHECK-BE-NEXT: mtfprwz f9, r4 +; CHECK-BE-NEXT: mffprwz r4, f6 +; CHECK-BE-NEXT: mtfprwz f6, r4 +; CHECK-BE-NEXT: xxperm vs6, vs9, vs8 +; CHECK-BE-NEXT: xscvdpsxws f9, f5 +; CHECK-BE-NEXT: xxswapd vs5, vs5 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 +; CHECK-BE-NEXT: xxmrghw vs6, vs6, vs7 +; CHECK-BE-NEXT: mffprwz r4, f9 +; CHECK-BE-NEXT: mtfprwz f9, r4 +; CHECK-BE-NEXT: mffprwz r4, f5 +; CHECK-BE-NEXT: mtfprwz f5, r4 +; CHECK-BE-NEXT: xxperm vs5, vs9, vs8 +; CHECK-BE-NEXT: xscvdpsxws f9, f4 ; CHECK-BE-NEXT: xxswapd vs4, vs4 -; CHECK-BE-NEXT: mtvsrwz v0, r5 -; CHECK-BE-NEXT: mffprwz r5, f1 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: lxv vs1, 80(r4) ; CHECK-BE-NEXT: xscvdpsxws f4, f4 -; CHECK-BE-NEXT: vperm v3, v3, v0, v2 -; CHECK-BE-NEXT: mtvsrwz v0, r5 -; CHECK-BE-NEXT: mffprwz r5, f0 -; CHECK-BE-NEXT: lxv vs0, 64(r4) -; CHECK-BE-NEXT: vperm v4, v4, v0, v2 -; CHECK-BE-NEXT: mtvsrwz v0, r5 -; CHECK-BE-NEXT: mffprwz r4, f5 -; CHECK-BE-NEXT: vperm v5, v5, v0, v2 -; CHECK-BE-NEXT: xxmrghw vs6, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v3, r4 +; CHECK-BE-NEXT: mffprwz r4, f9 +; CHECK-BE-NEXT: mtfprwz f9, r4 ; CHECK-BE-NEXT: mffprwz r4, f4 -; CHECK-BE-NEXT: mtvsrwz v4, r4 -; CHECK-BE-NEXT: mffprwz r4, f7 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 -; CHECK-BE-NEXT: mtvsrwz v4, r4 -; CHECK-BE-NEXT: mffprwz r4, f3 -; CHECK-BE-NEXT: xscvdpsxws f3, f2 +; CHECK-BE-NEXT: mtfprwz f4, r4 +; CHECK-BE-NEXT: xxperm vs4, vs9, vs8 +; CHECK-BE-NEXT: xscvdpsxws f9, f3 +; CHECK-BE-NEXT: xxswapd vs3, vs3 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: xxmrghw vs4, vs4, vs5 +; CHECK-BE-NEXT: xscvdpsxws f5, f2 ; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: xxmrghw vs4, v3, v5 -; CHECK-BE-NEXT: mtvsrwz v3, r4 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs4, vs4, vs6 +; CHECK-BE-NEXT: mffprwz r4, f9 +; CHECK-BE-NEXT: mtfprwz f9, r4 +; CHECK-BE-NEXT: stxv vs4, 0(r3) ; CHECK-BE-NEXT: mffprwz r4, f3 +; CHECK-BE-NEXT: mtfprwz f3, r4 +; CHECK-BE-NEXT: mffprwz r4, f5 +; CHECK-BE-NEXT: mtfprwz f5, r4 +; CHECK-BE-NEXT: mffprwz r4, f2 +; CHECK-BE-NEXT: xxperm vs3, vs9, vs8 +; CHECK-BE-NEXT: mtfprwz f2, r4 +; CHECK-BE-NEXT: xxperm vs2, vs5, vs8 +; CHECK-BE-NEXT: xxmrghw vs2, vs2, vs3 ; CHECK-BE-NEXT: xscvdpsxws f3, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs1 -; CHECK-BE-NEXT: mtvsrwz v4, r4 -; CHECK-BE-NEXT: stxv vs4, 0(r3) -; CHECK-BE-NEXT: mffprwz r4, f2 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r4 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 ; CHECK-BE-NEXT: mffprwz r4, f3 -; CHECK-BE-NEXT: xxmrghw vs2, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v3, r4 +; CHECK-BE-NEXT: mtfprwz f3, r4 ; CHECK-BE-NEXT: mffprwz r4, f1 -; CHECK-BE-NEXT: xscvdpsxws f1, f0 +; CHECK-BE-NEXT: mtfprwz f1, r4 +; CHECK-BE-NEXT: xxperm vs1, vs3, vs8 +; CHECK-BE-NEXT: xscvdpsxws f3, f0 ; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: mtvsrwz v4, r4 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 -; CHECK-BE-NEXT: mffprwz r4, f1 -; CHECK-BE-NEXT: mtvsrwz v4, r4 +; CHECK-BE-NEXT: mffprwz r4, f3 +; CHECK-BE-NEXT: mtfprwz f3, r4 ; CHECK-BE-NEXT: mffprwz r4, f0 -; CHECK-BE-NEXT: mtvsrwz v5, r4 -; CHECK-BE-NEXT: vperm v2, v4, v5, v2 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtfprwz f0, r4 +; CHECK-BE-NEXT: xxperm vs0, vs3, vs8 +; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs1 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs2 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: blr @@ -587,18 +587,18 @@ ; ; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: xscvdpsxws f0, v2 +; CHECK-BE-NEXT: xxswapd vs2, v2 +; CHECK-BE-NEXT: xscvdpsxws f1, v2 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xxswapd vs0, v2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 +; CHECK-BE-NEXT: lxv vs0, 0(r3) +; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: li r3, 0 -; CHECK-BE-NEXT: vperm v2, v4, v2, v3 +; CHECK-BE-NEXT: xxperm v2, vs1, vs0 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: blr entry: @@ -664,24 +664,24 @@ ; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xscvdpsxws f2, f1 +; CHECK-BE-NEXT: lxv vs2, 0(r3) +; CHECK-BE-NEXT: xscvdpsxws f3, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: xscvdpsxws f1, f0 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: xxperm vs1, vs3, vs2 +; CHECK-BE-NEXT: xscvdpsxws f3, f0 ; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 -; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: vperm v2, v4, v5, v2 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtfprwz f0, r3 +; CHECK-BE-NEXT: xxperm vs0, vs3, vs2 +; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs1 ; CHECK-BE-NEXT: mffprd r3, f0 ; CHECK-BE-NEXT: blr entry: @@ -789,41 +789,41 @@ ; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xscvdpsxws f4, f3 +; CHECK-BE-NEXT: lxv vs4, 0(r3) +; CHECK-BE-NEXT: xscvdpsxws f5, f3 ; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: mffprwz r3, f4 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: mtfprwz f5, r3 ; CHECK-BE-NEXT: mffprwz r3, f3 -; CHECK-BE-NEXT: xscvdpsxws f3, f2 +; CHECK-BE-NEXT: mtfprwz f3, r3 +; CHECK-BE-NEXT: xxperm vs3, vs5, vs4 +; CHECK-BE-NEXT: xscvdpsxws f5, f2 ; CHECK-BE-NEXT: xxswapd vs2, vs2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 -; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: mtfprwz f5, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 +; CHECK-BE-NEXT: mtfprwz f2, r3 +; CHECK-BE-NEXT: xxperm vs2, vs5, vs4 +; CHECK-BE-NEXT: xxmrghw vs2, vs2, vs3 ; CHECK-BE-NEXT: xscvdpsxws f3, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 ; CHECK-BE-NEXT: mffprwz r3, f3 -; CHECK-BE-NEXT: xxmrghw vs2, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: xscvdpsxws f1, f0 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: xxperm vs1, vs3, vs4 +; CHECK-BE-NEXT: xscvdpsxws f3, f0 ; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 -; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: vperm v2, v4, v5, v2 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtfprwz f0, r3 +; CHECK-BE-NEXT: xxperm vs0, vs3, vs4 +; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs1 ; CHECK-BE-NEXT: xxmrghd v2, vs0, vs2 ; CHECK-BE-NEXT: blr entry: @@ -1012,87 +1012,87 @@ ; ; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: lxv vs2, 48(r4) -; CHECK-BE-NEXT: lxv vs1, 32(r4) -; CHECK-BE-NEXT: lxv vs0, 16(r4) -; CHECK-BE-NEXT: addis r5, r2, .LCPI7_0@toc@ha -; CHECK-BE-NEXT: addi r5, r5, .LCPI7_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r5) -; CHECK-BE-NEXT: xscvdpsxws f3, f2 -; CHECK-BE-NEXT: xscvdpsxws f4, f1 -; CHECK-BE-NEXT: xxswapd vs2, vs2 -; CHECK-BE-NEXT: xscvdpsxws f5, f0 -; CHECK-BE-NEXT: xxswapd vs1, vs1 -; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r5, f3 +; CHECK-BE-NEXT: lxv vs7, 48(r4) +; CHECK-BE-NEXT: lxv vs0, 64(r4) +; CHECK-BE-NEXT: lxv vs1, 80(r4) +; CHECK-BE-NEXT: lxv vs2, 96(r4) +; CHECK-BE-NEXT: xscvdpsxws f9, f7 +; CHECK-BE-NEXT: xxswapd vs7, vs7 ; CHECK-BE-NEXT: lxv vs3, 112(r4) -; CHECK-BE-NEXT: mtvsrwz v3, r5 -; CHECK-BE-NEXT: mffprwz r5, f4 ; CHECK-BE-NEXT: lxv vs4, 0(r4) -; CHECK-BE-NEXT: mtvsrwz v4, r5 -; CHECK-BE-NEXT: mffprwz r5, f5 -; CHECK-BE-NEXT: xscvdpsxws f7, f3 -; CHECK-BE-NEXT: xxswapd vs3, vs3 -; CHECK-BE-NEXT: mtvsrwz v5, r5 -; CHECK-BE-NEXT: mffprwz r5, f2 -; CHECK-BE-NEXT: lxv vs2, 96(r4) -; CHECK-BE-NEXT: xscvdpsxws f5, f4 +; CHECK-BE-NEXT: lxv vs5, 16(r4) +; CHECK-BE-NEXT: lxv vs6, 32(r4) +; CHECK-BE-NEXT: addis r4, r2, .LCPI7_0@toc@ha +; CHECK-BE-NEXT: addi r4, r4, .LCPI7_0@toc@l +; CHECK-BE-NEXT: lxv vs8, 0(r4) +; CHECK-BE-NEXT: xscvdpsxws f7, f7 +; CHECK-BE-NEXT: mffprwz r4, f9 +; CHECK-BE-NEXT: mtfprwz f9, r4 +; CHECK-BE-NEXT: mffprwz r4, f7 +; CHECK-BE-NEXT: mtfprwz f7, r4 +; CHECK-BE-NEXT: xxperm vs7, vs9, vs8 +; CHECK-BE-NEXT: xscvdpsxws f9, f6 +; CHECK-BE-NEXT: xxswapd vs6, vs6 +; CHECK-BE-NEXT: xscvdpsxws f6, f6 +; CHECK-BE-NEXT: mffprwz r4, f9 +; CHECK-BE-NEXT: mtfprwz f9, r4 +; CHECK-BE-NEXT: mffprwz r4, f6 +; CHECK-BE-NEXT: mtfprwz f6, r4 +; CHECK-BE-NEXT: xxperm vs6, vs9, vs8 +; CHECK-BE-NEXT: xscvdpsxws f9, f5 +; CHECK-BE-NEXT: xxswapd vs5, vs5 +; CHECK-BE-NEXT: xscvdpsxws f5, f5 +; CHECK-BE-NEXT: xxmrghw vs6, vs6, vs7 +; CHECK-BE-NEXT: mffprwz r4, f9 +; CHECK-BE-NEXT: mtfprwz f9, r4 +; CHECK-BE-NEXT: mffprwz r4, f5 +; CHECK-BE-NEXT: mtfprwz f5, r4 +; CHECK-BE-NEXT: xxperm vs5, vs9, vs8 +; CHECK-BE-NEXT: xscvdpsxws f9, f4 ; CHECK-BE-NEXT: xxswapd vs4, vs4 -; CHECK-BE-NEXT: mtvsrwz v0, r5 -; CHECK-BE-NEXT: mffprwz r5, f1 -; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: lxv vs1, 80(r4) ; CHECK-BE-NEXT: xscvdpsxws f4, f4 -; CHECK-BE-NEXT: vperm v3, v3, v0, v2 -; CHECK-BE-NEXT: mtvsrwz v0, r5 -; CHECK-BE-NEXT: mffprwz r5, f0 -; CHECK-BE-NEXT: lxv vs0, 64(r4) -; CHECK-BE-NEXT: vperm v4, v4, v0, v2 -; CHECK-BE-NEXT: mtvsrwz v0, r5 -; CHECK-BE-NEXT: mffprwz r4, f5 -; CHECK-BE-NEXT: vperm v5, v5, v0, v2 -; CHECK-BE-NEXT: xxmrghw vs6, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v3, r4 +; CHECK-BE-NEXT: mffprwz r4, f9 +; CHECK-BE-NEXT: mtfprwz f9, r4 ; CHECK-BE-NEXT: mffprwz r4, f4 -; CHECK-BE-NEXT: mtvsrwz v4, r4 -; CHECK-BE-NEXT: mffprwz r4, f7 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 -; CHECK-BE-NEXT: mtvsrwz v4, r4 -; CHECK-BE-NEXT: mffprwz r4, f3 -; CHECK-BE-NEXT: xscvdpsxws f3, f2 +; CHECK-BE-NEXT: mtfprwz f4, r4 +; CHECK-BE-NEXT: xxperm vs4, vs9, vs8 +; CHECK-BE-NEXT: xscvdpsxws f9, f3 +; CHECK-BE-NEXT: xxswapd vs3, vs3 +; CHECK-BE-NEXT: xscvdpsxws f3, f3 +; CHECK-BE-NEXT: xxmrghw vs4, vs4, vs5 +; CHECK-BE-NEXT: xscvdpsxws f5, f2 ; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: xxmrghw vs4, v3, v5 -; CHECK-BE-NEXT: mtvsrwz v3, r4 -; CHECK-BE-NEXT: vperm v3, v4, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs4, vs4, vs6 +; CHECK-BE-NEXT: mffprwz r4, f9 +; CHECK-BE-NEXT: mtfprwz f9, r4 +; CHECK-BE-NEXT: stxv vs4, 0(r3) ; CHECK-BE-NEXT: mffprwz r4, f3 +; CHECK-BE-NEXT: mtfprwz f3, r4 +; CHECK-BE-NEXT: mffprwz r4, f5 +; CHECK-BE-NEXT: mtfprwz f5, r4 +; CHECK-BE-NEXT: mffprwz r4, f2 +; CHECK-BE-NEXT: xxperm vs3, vs9, vs8 +; CHECK-BE-NEXT: mtfprwz f2, r4 +; CHECK-BE-NEXT: xxperm vs2, vs5, vs8 +; CHECK-BE-NEXT: xxmrghw vs2, vs2, vs3 ; CHECK-BE-NEXT: xscvdpsxws f3, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs1 -; CHECK-BE-NEXT: mtvsrwz v4, r4 -; CHECK-BE-NEXT: stxv vs4, 0(r3) -; CHECK-BE-NEXT: mffprwz r4, f2 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r4 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 ; CHECK-BE-NEXT: mffprwz r4, f3 -; CHECK-BE-NEXT: xxmrghw vs2, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v3, r4 +; CHECK-BE-NEXT: mtfprwz f3, r4 ; CHECK-BE-NEXT: mffprwz r4, f1 -; CHECK-BE-NEXT: xscvdpsxws f1, f0 +; CHECK-BE-NEXT: mtfprwz f1, r4 +; CHECK-BE-NEXT: xxperm vs1, vs3, vs8 +; CHECK-BE-NEXT: xscvdpsxws f3, f0 ; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: mtvsrwz v4, r4 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 -; CHECK-BE-NEXT: mffprwz r4, f1 -; CHECK-BE-NEXT: mtvsrwz v4, r4 +; CHECK-BE-NEXT: mffprwz r4, f3 +; CHECK-BE-NEXT: mtfprwz f3, r4 ; CHECK-BE-NEXT: mffprwz r4, f0 -; CHECK-BE-NEXT: mtvsrwz v5, r4 -; CHECK-BE-NEXT: vperm v2, v4, v5, v2 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtfprwz f0, r4 +; CHECK-BE-NEXT: xxperm vs0, vs3, vs8 +; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs1 ; CHECK-BE-NEXT: xxmrghd vs0, vs0, vs2 ; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll @@ -45,18 +45,18 @@ ; ; CHECK-BE-LABEL: test2elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: xscvdpsxws f0, v2 +; CHECK-BE-NEXT: xxswapd vs2, v2 +; CHECK-BE-NEXT: xscvdpsxws f1, v2 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xxswapd vs0, v2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 +; CHECK-BE-NEXT: lxv vs0, 0(r3) +; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: addi r3, r1, -2 -; CHECK-BE-NEXT: vperm v2, v4, v2, v3 +; CHECK-BE-NEXT: xxperm v2, vs1, vs0 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10 ; CHECK-BE-NEXT: stxsihx v2, 0, r3 ; CHECK-BE-NEXT: lhz r3, -2(r1) @@ -125,25 +125,25 @@ ; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xscvdpsxws f2, f1 +; CHECK-BE-NEXT: lxv vs2, 0(r3) +; CHECK-BE-NEXT: xscvdpsxws f3, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 +; CHECK-BE-NEXT: xxperm v2, vs3, vs2 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtfprwz f1, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: li r3, 0 -; CHECK-BE-NEXT: vperm v2, v4, v5, v2 -; CHECK-BE-NEXT: vmrghh v2, v2, v3 +; CHECK-BE-NEXT: xxperm v3, vs1, vs2 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: blr entry: @@ -254,42 +254,42 @@ ; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xscvdpsxws f4, f3 +; CHECK-BE-NEXT: lxv vs4, 0(r3) +; CHECK-BE-NEXT: xscvdpsxws f5, f3 ; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: mffprwz r3, f4 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: mtfprwz f5, r3 ; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xxswapd vs2, vs2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 +; CHECK-BE-NEXT: xxperm v2, vs5, vs4 ; CHECK-BE-NEXT: mffprwz r3, f3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs3, vs4 ; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: vmrghh v3, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 +; CHECK-BE-NEXT: mtfprwz f2, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs2, vs4 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtfprwz f1, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v0, r3 -; CHECK-BE-NEXT: vperm v2, v5, v0, v2 -; CHECK-BE-NEXT: vmrghh v2, v2, v4 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: xxperm v4, vs1, vs4 +; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: xxmrghw vs0, v3, v2 ; CHECK-BE-NEXT: mffprd r3, f0 ; CHECK-BE-NEXT: blr entry: @@ -479,7 +479,7 @@ ; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3) -; CHECK-BE-NEXT: xscvdpsxws f8, f7 +; CHECK-BE-NEXT: xscvdpsxws f9, f7 ; CHECK-BE-NEXT: xxswapd vs7, vs7 ; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs4, 64(r3) @@ -487,75 +487,75 @@ ; CHECK-BE-NEXT: lxv vs6, 96(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) +; CHECK-BE-NEXT: lxv vs8, 0(r3) ; CHECK-BE-NEXT: xscvdpsxws f7, f7 -; CHECK-BE-NEXT: mffprwz r3, f8 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f9 +; CHECK-BE-NEXT: mtfprwz f9, r3 ; CHECK-BE-NEXT: mffprwz r3, f7 ; CHECK-BE-NEXT: xscvdpsxws f7, f6 ; CHECK-BE-NEXT: xxswapd vs6, vs6 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: xscvdpsxws f6, f6 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 +; CHECK-BE-NEXT: xxperm v2, vs9, vs8 ; CHECK-BE-NEXT: mffprwz r3, f7 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtfprwz f7, r3 ; CHECK-BE-NEXT: mffprwz r3, f6 ; CHECK-BE-NEXT: xscvdpsxws f6, f5 ; CHECK-BE-NEXT: xxswapd vs5, vs5 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvdpsxws f5, f5 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs7, vs8 ; CHECK-BE-NEXT: mffprwz r3, f6 -; CHECK-BE-NEXT: vmrghh v3, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 +; CHECK-BE-NEXT: mtfprwz f6, r3 ; CHECK-BE-NEXT: mffprwz r3, f5 ; CHECK-BE-NEXT: xscvdpsxws f5, f4 ; CHECK-BE-NEXT: xxswapd vs4, vs4 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvdpsxws f4, f4 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs6, vs8 ; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: mtfprwz f5, r3 +; CHECK-BE-NEXT: mffprwz r3, f4 +; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: xxperm v4, vs5, vs8 ; CHECK-BE-NEXT: xscvdpsxws f5, f3 ; CHECK-BE-NEXT: xxswapd vs3, vs3 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: mffprwz r3, f4 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: mtvsrwz v0, r3 -; CHECK-BE-NEXT: vperm v5, v5, v0, v2 +; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: xxmrghw vs4, v3, v2 ; CHECK-BE-NEXT: mffprwz r3, f5 -; CHECK-BE-NEXT: vmrghh v4, v5, v4 -; CHECK-BE-NEXT: xxmrghw vs4, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mtfprwz f5, r3 ; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xxswapd vs2, vs2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 +; CHECK-BE-NEXT: xxperm v2, vs5, vs8 ; CHECK-BE-NEXT: mffprwz r3, f3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs3, vs8 ; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: vmrghh v3, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 +; CHECK-BE-NEXT: mtfprwz f2, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs2, vs8 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtfprwz f1, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v0, r3 -; CHECK-BE-NEXT: vperm v2, v5, v0, v2 -; CHECK-BE-NEXT: vmrghh v2, v2, v4 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: xxperm v4, vs1, vs8 +; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: xxmrghw vs0, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, vs0, vs4 ; CHECK-BE-NEXT: blr entry: @@ -600,18 +600,18 @@ ; ; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: xscvdpsxws f0, v2 +; CHECK-BE-NEXT: xxswapd vs2, v2 +; CHECK-BE-NEXT: xscvdpsxws f1, v2 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: xxswapd vs0, v2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 +; CHECK-BE-NEXT: xscvdpsxws f2, f2 +; CHECK-BE-NEXT: lxv vs0, 0(r3) +; CHECK-BE-NEXT: mffprwz r3, f1 +; CHECK-BE-NEXT: mtfprwz f1, r3 +; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: addi r3, r1, -2 -; CHECK-BE-NEXT: vperm v2, v4, v2, v3 +; CHECK-BE-NEXT: xxperm v2, vs1, vs0 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10 ; CHECK-BE-NEXT: stxsihx v2, 0, r3 ; CHECK-BE-NEXT: lhz r3, -2(r1) @@ -680,25 +680,25 @@ ; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xscvdpsxws f2, f1 +; CHECK-BE-NEXT: lxv vs2, 0(r3) +; CHECK-BE-NEXT: xscvdpsxws f3, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 +; CHECK-BE-NEXT: xxperm v2, vs3, vs2 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtfprwz f1, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: li r3, 0 -; CHECK-BE-NEXT: vperm v2, v4, v5, v2 -; CHECK-BE-NEXT: vmrghh v2, v2, v3 +; CHECK-BE-NEXT: xxperm v3, vs1, vs2 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: blr entry: @@ -809,42 +809,42 @@ ; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI6_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI6_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) -; CHECK-BE-NEXT: xscvdpsxws f4, f3 +; CHECK-BE-NEXT: lxv vs4, 0(r3) +; CHECK-BE-NEXT: xscvdpsxws f5, f3 ; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: mffprwz r3, f4 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: mtfprwz f5, r3 ; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xxswapd vs2, vs2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 +; CHECK-BE-NEXT: xxperm v2, vs5, vs4 ; CHECK-BE-NEXT: mffprwz r3, f3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs3, vs4 ; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: vmrghh v3, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 +; CHECK-BE-NEXT: mtfprwz f2, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs2, vs4 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtfprwz f1, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v0, r3 -; CHECK-BE-NEXT: vperm v2, v5, v0, v2 -; CHECK-BE-NEXT: vmrghh v2, v2, v4 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: xxperm v4, vs1, vs4 +; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: xxmrghw vs0, v3, v2 ; CHECK-BE-NEXT: mffprd r3, f0 ; CHECK-BE-NEXT: blr entry: @@ -1034,7 +1034,7 @@ ; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3) -; CHECK-BE-NEXT: xscvdpsxws f8, f7 +; CHECK-BE-NEXT: xscvdpsxws f9, f7 ; CHECK-BE-NEXT: xxswapd vs7, vs7 ; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs4, 64(r3) @@ -1042,75 +1042,75 @@ ; CHECK-BE-NEXT: lxv vs6, 96(r3) ; CHECK-BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI7_0@toc@l -; CHECK-BE-NEXT: lxv v2, 0(r3) +; CHECK-BE-NEXT: lxv vs8, 0(r3) ; CHECK-BE-NEXT: xscvdpsxws f7, f7 -; CHECK-BE-NEXT: mffprwz r3, f8 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mffprwz r3, f9 +; CHECK-BE-NEXT: mtfprwz f9, r3 ; CHECK-BE-NEXT: mffprwz r3, f7 ; CHECK-BE-NEXT: xscvdpsxws f7, f6 ; CHECK-BE-NEXT: xxswapd vs6, vs6 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: xscvdpsxws f6, f6 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 +; CHECK-BE-NEXT: xxperm v2, vs9, vs8 ; CHECK-BE-NEXT: mffprwz r3, f7 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtfprwz f7, r3 ; CHECK-BE-NEXT: mffprwz r3, f6 ; CHECK-BE-NEXT: xscvdpsxws f6, f5 ; CHECK-BE-NEXT: xxswapd vs5, vs5 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvdpsxws f5, f5 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs7, vs8 ; CHECK-BE-NEXT: mffprwz r3, f6 -; CHECK-BE-NEXT: vmrghh v3, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 +; CHECK-BE-NEXT: mtfprwz f6, r3 ; CHECK-BE-NEXT: mffprwz r3, f5 ; CHECK-BE-NEXT: xscvdpsxws f5, f4 ; CHECK-BE-NEXT: xxswapd vs4, vs4 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvdpsxws f4, f4 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs6, vs8 ; CHECK-BE-NEXT: mffprwz r3, f5 +; CHECK-BE-NEXT: mtfprwz f5, r3 +; CHECK-BE-NEXT: mffprwz r3, f4 +; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: xxperm v4, vs5, vs8 ; CHECK-BE-NEXT: xscvdpsxws f5, f3 ; CHECK-BE-NEXT: xxswapd vs3, vs3 -; CHECK-BE-NEXT: mtvsrwz v5, r3 -; CHECK-BE-NEXT: mffprwz r3, f4 ; CHECK-BE-NEXT: xscvdpsxws f3, f3 -; CHECK-BE-NEXT: mtvsrwz v0, r3 -; CHECK-BE-NEXT: vperm v5, v5, v0, v2 +; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: xxmrghw vs4, v3, v2 ; CHECK-BE-NEXT: mffprwz r3, f5 -; CHECK-BE-NEXT: vmrghh v4, v5, v4 -; CHECK-BE-NEXT: xxmrghw vs4, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v3, r3 +; CHECK-BE-NEXT: mtfprwz f5, r3 ; CHECK-BE-NEXT: mffprwz r3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xxswapd vs2, vs2 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: xscvdpsxws f2, f2 -; CHECK-BE-NEXT: vperm v3, v3, v4, v2 +; CHECK-BE-NEXT: xxperm v2, vs5, vs8 ; CHECK-BE-NEXT: mffprwz r3, f3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: mtfprwz f3, r3 ; CHECK-BE-NEXT: mffprwz r3, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xxswapd vs1, vs1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvdpsxws f1, f1 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs3, vs8 ; CHECK-BE-NEXT: mffprwz r3, f2 -; CHECK-BE-NEXT: vmrghh v3, v4, v3 -; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: vmrghh v2, v3, v2 +; CHECK-BE-NEXT: mtfprwz f2, r3 ; CHECK-BE-NEXT: mffprwz r3, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xxswapd vs0, vs0 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtvsrwz v3, r3 ; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: vperm v4, v4, v5, v2 +; CHECK-BE-NEXT: xxperm v3, vs2, vs8 ; CHECK-BE-NEXT: mffprwz r3, f1 -; CHECK-BE-NEXT: mtvsrwz v5, r3 +; CHECK-BE-NEXT: mtfprwz f1, r3 ; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v0, r3 -; CHECK-BE-NEXT: vperm v2, v5, v0, v2 -; CHECK-BE-NEXT: vmrghh v2, v2, v4 -; CHECK-BE-NEXT: xxmrghw vs0, v2, v3 +; CHECK-BE-NEXT: mtvsrwz v4, r3 +; CHECK-BE-NEXT: xxperm v4, vs1, vs8 +; CHECK-BE-NEXT: vmrghh v3, v4, v3 +; CHECK-BE-NEXT: xxmrghw vs0, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, vs0, vs4 ; CHECK-BE-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll @@ -80,13 +80,13 @@ ; ; CHECK-BE-LABEL: test4elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: mtvsrd v2, r3 +; CHECK-BE-NEXT: mtfprd f1, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha -; CHECK-BE-NEXT: xxlxor v4, v4, v4 +; CHECK-BE-NEXT: xxlxor vs0, vs0, vs0 ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: vperm v2, v4, v2, v3 -; CHECK-BE-NEXT: xvcvuxwsp v2, v2 +; CHECK-BE-NEXT: lxv vs2, 0(r3) +; CHECK-BE-NEXT: xxperm vs1, vs0, vs2 +; CHECK-BE-NEXT: xvcvuxwsp v2, vs1 ; CHECK-BE-NEXT: blr entry: %0 = bitcast i64 %a.coerce to <4 x i16> diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll @@ -24,24 +24,24 @@ ; ; CHECK-P9-LABEL: test2elt: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: mtvsrwz v2, r3 +; CHECK-P9-NEXT: mtfprwz f1, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; CHECK-P9-NEXT: xxlxor v4, v4, v4 +; CHECK-P9-NEXT: xxlxor vs0, vs0, vs0 ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-P9-NEXT: lxv v3, 0(r3) -; CHECK-P9-NEXT: vperm v2, v4, v2, v3 -; CHECK-P9-NEXT: xvcvuxddp v2, v2 +; CHECK-P9-NEXT: lxv vs2, 0(r3) +; CHECK-P9-NEXT: xxperm vs1, vs0, vs2 +; CHECK-P9-NEXT: xvcvuxddp v2, vs1 ; CHECK-P9-NEXT: blr ; ; CHECK-BE-LABEL: test2elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: mtvsrwz v2, r3 +; CHECK-BE-NEXT: mtfprwz f1, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; CHECK-BE-NEXT: xxlxor v4, v4, v4 +; CHECK-BE-NEXT: xxlxor vs0, vs0, vs0 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: vperm v2, v4, v2, v3 -; CHECK-BE-NEXT: xvcvuxddp v2, v2 +; CHECK-BE-NEXT: lxv vs2, 0(r3) +; CHECK-BE-NEXT: xxperm vs1, vs0, vs2 +; CHECK-BE-NEXT: xvcvuxddp v2, vs1 ; CHECK-BE-NEXT: blr entry: %0 = bitcast i32 %a.coerce to <2 x i16> @@ -399,8 +399,8 @@ ; CHECK-P9-NEXT: mtvsrwz v2, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-P9-NEXT: lxv v3, 0(r3) -; CHECK-P9-NEXT: vperm v2, v2, v2, v3 +; CHECK-P9-NEXT: lxv vs0, 0(r3) +; CHECK-P9-NEXT: xxperm v2, v2, vs0 ; CHECK-P9-NEXT: vextsh2d v2, v2 ; CHECK-P9-NEXT: xvcvsxddp v2, v2 ; CHECK-P9-NEXT: blr @@ -410,8 +410,8 @@ ; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: vperm v2, v2, v2, v3 +; CHECK-BE-NEXT: lxv vs0, 0(r3) +; CHECK-BE-NEXT: xxperm v2, v2, vs0 ; CHECK-BE-NEXT: vextsh2d v2, v2 ; CHECK-BE-NEXT: xvcvsxddp v2, v2 ; CHECK-BE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll @@ -76,24 +76,24 @@ ; ; CHECK-P9-LABEL: test4elt: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: mtvsrwz v2, r3 +; CHECK-P9-NEXT: mtfprwz f1, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha -; CHECK-P9-NEXT: xxlxor v4, v4, v4 +; CHECK-P9-NEXT: xxlxor vs0, vs0, vs0 ; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-P9-NEXT: lxv v3, 0(r3) -; CHECK-P9-NEXT: vperm v2, v4, v2, v3 -; CHECK-P9-NEXT: xvcvuxwsp v2, v2 +; CHECK-P9-NEXT: lxv vs2, 0(r3) +; CHECK-P9-NEXT: xxperm vs1, vs0, vs2 +; CHECK-P9-NEXT: xvcvuxwsp v2, vs1 ; CHECK-P9-NEXT: blr ; ; CHECK-BE-LABEL: test4elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: mtvsrwz v2, r3 +; CHECK-BE-NEXT: mtfprwz f1, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI1_0@toc@ha -; CHECK-BE-NEXT: xxlxor v4, v4, v4 +; CHECK-BE-NEXT: xxlxor vs0, vs0, vs0 ; CHECK-BE-NEXT: addi r3, r3, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: vperm v2, v4, v2, v3 -; CHECK-BE-NEXT: xvcvuxwsp v2, v2 +; CHECK-BE-NEXT: lxv vs2, 0(r3) +; CHECK-BE-NEXT: xxperm vs1, vs0, vs2 +; CHECK-BE-NEXT: xvcvuxwsp v2, vs1 ; CHECK-BE-NEXT: blr entry: %0 = bitcast i32 %a.coerce to <4 x i8> @@ -348,8 +348,8 @@ ; CHECK-P9-NEXT: mtvsrwz v2, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-P9-NEXT: lxv v3, 0(r3) -; CHECK-P9-NEXT: vperm v2, v2, v2, v3 +; CHECK-P9-NEXT: lxv vs0, 0(r3) +; CHECK-P9-NEXT: xxperm v2, v2, vs0 ; CHECK-P9-NEXT: vextsb2w v2, v2 ; CHECK-P9-NEXT: xvcvsxwsp v2, v2 ; CHECK-P9-NEXT: blr @@ -359,8 +359,8 @@ ; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI5_0@toc@l -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: vperm v2, v2, v2, v3 +; CHECK-BE-NEXT: lxv vs0, 0(r3) +; CHECK-BE-NEXT: xxperm v2, v2, vs0 ; CHECK-BE-NEXT: vextsb2w v2, v2 ; CHECK-BE-NEXT: xvcvsxwsp v2, v2 ; CHECK-BE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll --- a/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll +++ b/llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll @@ -24,24 +24,24 @@ ; ; CHECK-P9-LABEL: test2elt: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: mtvsrwz v2, r3 +; CHECK-P9-NEXT: mtfprwz f1, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; CHECK-P9-NEXT: xxlxor v4, v4, v4 +; CHECK-P9-NEXT: xxlxor vs0, vs0, vs0 ; CHECK-P9-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-P9-NEXT: lxv v3, 0(r3) -; CHECK-P9-NEXT: vperm v2, v4, v2, v3 -; CHECK-P9-NEXT: xvcvuxddp v2, v2 +; CHECK-P9-NEXT: lxv vs2, 0(r3) +; CHECK-P9-NEXT: xxperm vs1, vs0, vs2 +; CHECK-P9-NEXT: xvcvuxddp v2, vs1 ; CHECK-P9-NEXT: blr ; ; CHECK-BE-LABEL: test2elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: mtvsrwz v2, r3 +; CHECK-BE-NEXT: mtfprwz f1, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha -; CHECK-BE-NEXT: xxlxor v4, v4, v4 +; CHECK-BE-NEXT: xxlxor vs0, vs0, vs0 ; CHECK-BE-NEXT: addi r3, r3, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: vperm v2, v4, v2, v3 -; CHECK-BE-NEXT: xvcvuxddp v2, v2 +; CHECK-BE-NEXT: lxv vs2, 0(r3) +; CHECK-BE-NEXT: xxperm vs1, vs0, vs2 +; CHECK-BE-NEXT: xvcvuxddp v2, vs1 ; CHECK-BE-NEXT: blr entry: %0 = bitcast i16 %a.coerce to <2 x i8> @@ -434,8 +434,8 @@ ; CHECK-P9-NEXT: mtvsrwz v2, r3 ; CHECK-P9-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-P9-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-P9-NEXT: lxv v3, 0(r3) -; CHECK-P9-NEXT: vperm v2, v2, v2, v3 +; CHECK-P9-NEXT: lxv vs0, 0(r3) +; CHECK-P9-NEXT: xxperm v2, v2, vs0 ; CHECK-P9-NEXT: vextsb2d v2, v2 ; CHECK-P9-NEXT: xvcvsxddp v2, v2 ; CHECK-P9-NEXT: blr @@ -445,8 +445,8 @@ ; CHECK-BE-NEXT: mtvsrwz v2, r3 ; CHECK-BE-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-BE-NEXT: addi r3, r3, .LCPI4_0@toc@l -; CHECK-BE-NEXT: lxv v3, 0(r3) -; CHECK-BE-NEXT: vperm v2, v2, v2, v3 +; CHECK-BE-NEXT: lxv vs0, 0(r3) +; CHECK-BE-NEXT: xxperm v2, v2, vs0 ; CHECK-BE-NEXT: vextsb2d v2, v2 ; CHECK-BE-NEXT: xvcvsxddp v2, v2 ; CHECK-BE-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll b/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll --- a/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll +++ b/llvm/test/CodeGen/PowerPC/vec_extract_p9.ll @@ -192,11 +192,11 @@ ; CHECK-LE: # %bb.0: # %entry ; CHECK-LE-NEXT: addis 3, 2, .LCPI9_0@toc@ha ; CHECK-LE-NEXT: addi 3, 3, .LCPI9_0@toc@l -; CHECK-LE-NEXT: lxv 36, 0(3) +; CHECK-LE-NEXT: lxv 0, 0(3) ; CHECK-LE-NEXT: addis 3, 2, .LCPI9_1@toc@ha ; CHECK-LE-NEXT: lfs 1, .LCPI9_1@toc@l(3) -; CHECK-LE-NEXT: vperm 2, 2, 3, 4 -; CHECK-LE-NEXT: xxswapd 0, 34 +; CHECK-LE-NEXT: xxperm 35, 34, 0 +; CHECK-LE-NEXT: xxswapd 0, 35 ; CHECK-LE-NEXT: xsadddp 1, 0, 1 ; CHECK-LE-NEXT: blr ; @@ -204,10 +204,10 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI9_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI9_0@toc@l -; CHECK-BE-NEXT: lxv 36, 0(3) +; CHECK-BE-NEXT: lxv 0, 0(3) ; CHECK-BE-NEXT: addis 3, 2, .LCPI9_1@toc@ha +; CHECK-BE-NEXT: xxperm 34, 35, 0 ; CHECK-BE-NEXT: lfs 0, .LCPI9_1@toc@l(3) -; CHECK-BE-NEXT: vperm 2, 3, 2, 4 ; CHECK-BE-NEXT: xsadddp 1, 34, 0 ; CHECK-BE-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/vec_int_ext.ll b/llvm/test/CodeGen/PowerPC/vec_int_ext.ll --- a/llvm/test/CodeGen/PowerPC/vec_int_ext.ll +++ b/llvm/test/CodeGen/PowerPC/vec_int_ext.ll @@ -12,8 +12,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI0_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI0_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: vextsb2w 2, 2 ; CHECK-BE-NEXT: blr @@ -43,8 +43,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI1_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI1_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: vextsb2d 2, 2 ; CHECK-BE-NEXT: blr @@ -68,8 +68,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI2_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI2_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: vextsh2w 2, 2 ; CHECK-BE-NEXT: blr @@ -99,8 +99,8 @@ ; CHECK-BE: # %bb.0: # %entry ; CHECK-BE-NEXT: addis 3, 2, .LCPI3_0@toc@ha ; CHECK-BE-NEXT: addi 3, 3, .LCPI3_0@toc@l -; CHECK-BE-NEXT: lxv 35, 0(3) -; CHECK-BE-NEXT: vperm 2, 2, 2, 3 +; CHECK-BE-NEXT: lxv 0, 0(3) +; CHECK-BE-NEXT: xxperm 34, 34, 0 ; CHECK-BE-NEXT: vextsh2d 2, 2 ; CHECK-BE-NEXT: blr @@ -339,39 +339,39 @@ ; CHECK-BE-NEXT: vextublx 10, 10, 2 ; CHECK-BE-NEXT: vextublx 7, 7, 2 ; CHECK-BE-NEXT: vextublx 8, 8, 2 -; CHECK-BE-NEXT: li 3, 0 -; CHECK-BE-NEXT: li 4, 2 ; CHECK-BE-NEXT: li 5, 4 ; CHECK-BE-NEXT: li 6, 6 +; CHECK-BE-NEXT: li 3, 0 +; CHECK-BE-NEXT: li 4, 2 ; CHECK-BE-NEXT: extsb 9, 9 ; CHECK-BE-NEXT: extsb 10, 10 -; CHECK-BE-NEXT: vextublx 3, 3, 2 -; CHECK-BE-NEXT: vextublx 4, 4, 2 -; CHECK-BE-NEXT: vextublx 5, 5, 2 ; CHECK-BE-NEXT: extsb 7, 7 ; CHECK-BE-NEXT: extsb 8, 8 -; CHECK-BE-NEXT: extsb 5, 5 -; CHECK-BE-NEXT: extsb 3, 3 -; CHECK-BE-NEXT: extsb 4, 4 -; CHECK-BE-NEXT: mtvsrwz 35, 9 -; CHECK-BE-NEXT: addis 9, 2, .LCPI11_0@toc@ha +; CHECK-BE-NEXT: vextublx 5, 5, 2 ; CHECK-BE-NEXT: vextublx 6, 6, 2 -; CHECK-BE-NEXT: mtvsrwz 34, 10 -; CHECK-BE-NEXT: mtvsrwz 37, 7 +; CHECK-BE-NEXT: extsb 5, 5 ; CHECK-BE-NEXT: extsb 6, 6 +; CHECK-BE-NEXT: mtfprwz 1, 9 +; CHECK-BE-NEXT: addis 9, 2, .LCPI11_0@toc@ha +; CHECK-BE-NEXT: mtfprwz 0, 10 +; CHECK-BE-NEXT: mtfprwz 3, 7 +; CHECK-BE-NEXT: vextublx 3, 3, 2 +; CHECK-BE-NEXT: extsb 3, 3 +; CHECK-BE-NEXT: mtfprwz 4, 3 ; CHECK-BE-NEXT: addi 9, 9, .LCPI11_0@toc@l -; CHECK-BE-NEXT: lxv 36, 0(9) -; CHECK-BE-NEXT: vperm 2, 3, 2, 4 -; CHECK-BE-NEXT: mtvsrwz 35, 8 -; CHECK-BE-NEXT: vperm 3, 5, 3, 4 -; CHECK-BE-NEXT: mtvsrwz 37, 3 -; CHECK-BE-NEXT: xxmrghw 0, 35, 34 -; CHECK-BE-NEXT: mtvsrwz 34, 6 -; CHECK-BE-NEXT: mtvsrwz 35, 5 -; CHECK-BE-NEXT: vperm 2, 3, 2, 4 -; CHECK-BE-NEXT: mtvsrwz 35, 4 -; CHECK-BE-NEXT: vperm 3, 5, 3, 4 -; CHECK-BE-NEXT: xxmrghw 1, 35, 34 +; CHECK-BE-NEXT: vextublx 4, 4, 2 +; CHECK-BE-NEXT: extsb 4, 4 +; CHECK-BE-NEXT: lxv 2, 0(9) +; CHECK-BE-NEXT: xxperm 0, 1, 2 +; CHECK-BE-NEXT: mtfprwz 1, 8 +; CHECK-BE-NEXT: xxperm 1, 3, 2 +; CHECK-BE-NEXT: mtfprwz 3, 5 +; CHECK-BE-NEXT: xxmrghw 0, 1, 0 +; CHECK-BE-NEXT: mtfprwz 1, 6 +; CHECK-BE-NEXT: xxperm 1, 3, 2 +; CHECK-BE-NEXT: mtfprwz 3, 4 +; CHECK-BE-NEXT: xxperm 3, 4, 2 +; CHECK-BE-NEXT: xxmrghw 1, 3, 1 ; CHECK-BE-NEXT: xxmrghd 34, 1, 0 ; CHECK-BE-NEXT: blr entry: diff --git a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll --- a/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll +++ b/llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll @@ -81,7 +81,6 @@ ; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xscvspdpn 3, 3 -; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xsdivsp 0, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 35 ; PC64LE9-NEXT: xscvspdpn 1, 1 @@ -89,11 +88,12 @@ ; PC64LE9-NEXT: xxsldwi 2, 35, 35, 3 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xsdivsp 2, 3, 2 -; PC64LE9-NEXT: xscvdpspn 35, 0 +; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 1, 1 ; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xxmrghw 34, 1, 2 -; PC64LE9-NEXT: vperm 2, 3, 2, 4 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: blr entry: %div = call <3 x float> @llvm.experimental.constrained.fdiv.v3f32( @@ -362,15 +362,15 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 1, 30 ; PC64LE9-NEXT: addis 3, 2, .LCPI7_0@toc@ha -; PC64LE9-NEXT: xscvdpspn 35, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 62, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload -; PC64LE9-NEXT: addi 3, 3, .LCPI7_0@toc@l ; PC64LE9-NEXT: lfd 30, 64(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lxv 36, 0(3) +; PC64LE9-NEXT: addi 3, 3, .LCPI7_0@toc@l ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: vperm 2, 3, 2, 4 +; PC64LE9-NEXT: xscvdpspn 0, 31 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 @@ -678,19 +678,19 @@ ; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xscvspdpn 3, 3 -; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xsmulsp 0, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 35 ; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xsmulsp 1, 2, 1 ; PC64LE9-NEXT: xxsldwi 2, 35, 35, 3 -; PC64LE9-NEXT: xscvdpspn 35, 0 +; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xsmulsp 2, 3, 2 ; PC64LE9-NEXT: xscvdpspn 1, 1 ; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xxmrghw 34, 1, 2 -; PC64LE9-NEXT: vperm 2, 3, 2, 4 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: blr entry: %mul = call <3 x float> @llvm.experimental.constrained.fmul.v3f32( @@ -840,19 +840,19 @@ ; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xscvspdpn 3, 3 -; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xsaddsp 0, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 35 ; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xsaddsp 1, 2, 1 ; PC64LE9-NEXT: xxsldwi 2, 35, 35, 3 -; PC64LE9-NEXT: xscvdpspn 35, 0 +; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xsaddsp 2, 3, 2 ; PC64LE9-NEXT: xscvdpspn 1, 1 ; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xxmrghw 34, 1, 2 -; PC64LE9-NEXT: vperm 2, 3, 2, 4 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: blr entry: %add = call <3 x float> @llvm.experimental.constrained.fadd.v3f32( @@ -1002,19 +1002,19 @@ ; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xscvspdpn 3, 3 -; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xssubsp 0, 1, 0 ; PC64LE9-NEXT: xxswapd 1, 35 ; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xssubsp 1, 2, 1 ; PC64LE9-NEXT: xxsldwi 2, 35, 35, 3 -; PC64LE9-NEXT: xscvdpspn 35, 0 +; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xssubsp 2, 3, 2 ; PC64LE9-NEXT: xscvdpspn 1, 1 ; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xxmrghw 34, 1, 2 -; PC64LE9-NEXT: vperm 2, 3, 2, 4 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: blr entry: %sub = call <3 x float> @llvm.experimental.constrained.fsub.v3f32( @@ -1154,15 +1154,15 @@ ; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xscvspdpn 0, 0 -; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xssqrtsp 1, 1 ; PC64LE9-NEXT: xssqrtsp 2, 2 ; PC64LE9-NEXT: xssqrtsp 0, 0 ; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xscvdpspn 1, 1 -; PC64LE9-NEXT: xscvdpspn 36, 0 +; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxmrghw 34, 1, 2 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: blr entry: %sqrt = call <3 x float> @llvm.experimental.constrained.sqrt.v3f32( @@ -1422,15 +1422,15 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 1, 30 ; PC64LE9-NEXT: addis 3, 2, .LCPI32_0@toc@ha -; PC64LE9-NEXT: xscvdpspn 35, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 62, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload -; PC64LE9-NEXT: addi 3, 3, .LCPI32_0@toc@l ; PC64LE9-NEXT: lfd 30, 64(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lxv 36, 0(3) +; PC64LE9-NEXT: addi 3, 3, .LCPI32_0@toc@l ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: vperm 2, 3, 2, 4 +; PC64LE9-NEXT: xscvdpspn 0, 31 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 @@ -1850,15 +1850,15 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 1, 30 ; PC64LE9-NEXT: addis 3, 2, .LCPI37_0@toc@ha -; PC64LE9-NEXT: xscvdpspn 35, 31 ; PC64LE9-NEXT: lxv 63, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload +; PC64LE9-NEXT: lfd 30, 64(1) # 8-byte Folded Reload ; PC64LE9-NEXT: ld 30, 48(1) # 8-byte Folded Reload ; PC64LE9-NEXT: addi 3, 3, .LCPI37_0@toc@l -; PC64LE9-NEXT: lfd 30, 64(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lxv 36, 0(3) ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: vperm 2, 3, 2, 4 +; PC64LE9-NEXT: xscvdpspn 0, 31 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 @@ -2231,14 +2231,14 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 1, 30 ; PC64LE9-NEXT: addis 3, 2, .LCPI42_0@toc@ha -; PC64LE9-NEXT: xscvdpspn 36, 31 ; PC64LE9-NEXT: lxv 63, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload -; PC64LE9-NEXT: addi 3, 3, .LCPI42_0@toc@l ; PC64LE9-NEXT: lfd 30, 48(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lxv 35, 0(3) +; PC64LE9-NEXT: addi 3, 3, .LCPI42_0@toc@l ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: xscvdpspn 1, 31 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload +; PC64LE9-NEXT: xxperm 34, 1, 0 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 @@ -2582,14 +2582,14 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 1, 30 ; PC64LE9-NEXT: addis 3, 2, .LCPI47_0@toc@ha -; PC64LE9-NEXT: xscvdpspn 36, 31 ; PC64LE9-NEXT: lxv 63, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload -; PC64LE9-NEXT: addi 3, 3, .LCPI47_0@toc@l ; PC64LE9-NEXT: lfd 30, 48(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lxv 35, 0(3) +; PC64LE9-NEXT: addi 3, 3, .LCPI47_0@toc@l ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: xscvdpspn 1, 31 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload +; PC64LE9-NEXT: xxperm 34, 1, 0 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 @@ -2933,14 +2933,14 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 1, 30 ; PC64LE9-NEXT: addis 3, 2, .LCPI52_0@toc@ha -; PC64LE9-NEXT: xscvdpspn 36, 31 ; PC64LE9-NEXT: lxv 63, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload -; PC64LE9-NEXT: addi 3, 3, .LCPI52_0@toc@l ; PC64LE9-NEXT: lfd 30, 48(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lxv 35, 0(3) +; PC64LE9-NEXT: addi 3, 3, .LCPI52_0@toc@l ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: xscvdpspn 1, 31 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload +; PC64LE9-NEXT: xxperm 34, 1, 0 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 @@ -3284,14 +3284,14 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 1, 30 ; PC64LE9-NEXT: addis 3, 2, .LCPI57_0@toc@ha -; PC64LE9-NEXT: xscvdpspn 36, 31 ; PC64LE9-NEXT: lxv 63, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload -; PC64LE9-NEXT: addi 3, 3, .LCPI57_0@toc@l ; PC64LE9-NEXT: lfd 30, 48(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lxv 35, 0(3) +; PC64LE9-NEXT: addi 3, 3, .LCPI57_0@toc@l ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: xscvdpspn 1, 31 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload +; PC64LE9-NEXT: xxperm 34, 1, 0 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 @@ -3635,14 +3635,14 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 1, 30 ; PC64LE9-NEXT: addis 3, 2, .LCPI62_0@toc@ha -; PC64LE9-NEXT: xscvdpspn 36, 31 ; PC64LE9-NEXT: lxv 63, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload -; PC64LE9-NEXT: addi 3, 3, .LCPI62_0@toc@l ; PC64LE9-NEXT: lfd 30, 48(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lxv 35, 0(3) +; PC64LE9-NEXT: addi 3, 3, .LCPI62_0@toc@l ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: xscvdpspn 1, 31 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload +; PC64LE9-NEXT: xxperm 34, 1, 0 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 @@ -3986,14 +3986,14 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 1, 30 ; PC64LE9-NEXT: addis 3, 2, .LCPI67_0@toc@ha -; PC64LE9-NEXT: xscvdpspn 36, 31 ; PC64LE9-NEXT: lxv 63, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload -; PC64LE9-NEXT: addi 3, 3, .LCPI67_0@toc@l ; PC64LE9-NEXT: lfd 30, 48(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lxv 35, 0(3) +; PC64LE9-NEXT: addi 3, 3, .LCPI67_0@toc@l ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: xscvdpspn 1, 31 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload +; PC64LE9-NEXT: xxperm 34, 1, 0 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 @@ -4337,14 +4337,14 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 1, 30 ; PC64LE9-NEXT: addis 3, 2, .LCPI72_0@toc@ha -; PC64LE9-NEXT: xscvdpspn 36, 31 ; PC64LE9-NEXT: lxv 63, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload -; PC64LE9-NEXT: addi 3, 3, .LCPI72_0@toc@l ; PC64LE9-NEXT: lfd 30, 48(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lxv 35, 0(3) +; PC64LE9-NEXT: addi 3, 3, .LCPI72_0@toc@l ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: xscvdpspn 1, 31 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload +; PC64LE9-NEXT: xxperm 34, 1, 0 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 @@ -4594,15 +4594,15 @@ ; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xscvspdpn 0, 0 -; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xsrdpic 1, 1 ; PC64LE9-NEXT: xsrdpic 2, 2 ; PC64LE9-NEXT: xsrdpic 0, 0 ; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xscvdpspn 1, 1 -; PC64LE9-NEXT: xscvdpspn 36, 0 +; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxmrghw 34, 1, 2 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: blr entry: %rint = call <3 x float> @llvm.experimental.constrained.rint.v3f32( @@ -4827,14 +4827,14 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 1, 30 ; PC64LE9-NEXT: addis 3, 2, .LCPI82_0@toc@ha -; PC64LE9-NEXT: xscvdpspn 36, 31 ; PC64LE9-NEXT: lxv 63, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload -; PC64LE9-NEXT: addi 3, 3, .LCPI82_0@toc@l ; PC64LE9-NEXT: lfd 30, 48(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lxv 35, 0(3) +; PC64LE9-NEXT: addi 3, 3, .LCPI82_0@toc@l ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: xscvdpspn 1, 31 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: lfd 31, 56(1) # 8-byte Folded Reload +; PC64LE9-NEXT: xxperm 34, 1, 0 ; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 @@ -5152,15 +5152,15 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 1, 30 ; PC64LE9-NEXT: addis 3, 2, .LCPI87_0@toc@ha -; PC64LE9-NEXT: xscvdpspn 35, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 62, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload -; PC64LE9-NEXT: addi 3, 3, .LCPI87_0@toc@l ; PC64LE9-NEXT: lfd 30, 64(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lxv 36, 0(3) +; PC64LE9-NEXT: addi 3, 3, .LCPI87_0@toc@l ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: vperm 2, 3, 2, 4 +; PC64LE9-NEXT: xscvdpspn 0, 31 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 @@ -5394,15 +5394,15 @@ ; PC64LE9-NEXT: xscvdpspn 0, 1 ; PC64LE9-NEXT: xscvdpspn 1, 30 ; PC64LE9-NEXT: addis 3, 2, .LCPI92_0@toc@ha -; PC64LE9-NEXT: xscvdpspn 35, 31 ; PC64LE9-NEXT: lxv 63, 48(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 62, 32(1) # 16-byte Folded Reload -; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload -; PC64LE9-NEXT: addi 3, 3, .LCPI92_0@toc@l ; PC64LE9-NEXT: lfd 30, 64(1) # 8-byte Folded Reload -; PC64LE9-NEXT: lxv 36, 0(3) +; PC64LE9-NEXT: addi 3, 3, .LCPI92_0@toc@l ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: vperm 2, 3, 2, 4 +; PC64LE9-NEXT: xscvdpspn 0, 31 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: lfd 31, 72(1) # 8-byte Folded Reload +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: mtlr 0 @@ -5587,22 +5587,23 @@ ; PC64LE9-NEXT: xxswapd 1, 34 ; PC64LE9-NEXT: xscvspdpn 0, 0 ; PC64LE9-NEXT: xscvspdpn 1, 1 +; PC64LE9-NEXT: xxsldwi 2, 34, 34, 1 +; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xscvdpsxws 0, 0 ; PC64LE9-NEXT: xscvdpsxws 1, 1 +; PC64LE9-NEXT: xscvdpsxws 2, 2 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mtfprwz 0, 3 ; PC64LE9-NEXT: mffprwz 3, 1 ; PC64LE9-NEXT: mtfprwz 1, 3 ; PC64LE9-NEXT: addis 3, 2, .LCPI97_0@toc@ha -; PC64LE9-NEXT: xxmrghw 35, 1, 0 -; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: addi 3, 3, .LCPI97_0@toc@l -; PC64LE9-NEXT: lxv 36, 0(3) -; PC64LE9-NEXT: xscvspdpn 0, 0 -; PC64LE9-NEXT: xscvdpsxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrwz 34, 3 -; PC64LE9-NEXT: vperm 2, 2, 3, 4 +; PC64LE9-NEXT: xxmrghw 0, 1, 0 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: mffprwz 3, 2 +; PC64LE9-NEXT: mtfprwz 2, 3 +; PC64LE9-NEXT: xxperm 0, 2, 1 +; PC64LE9-NEXT: xxlor 34, 0, 0 ; PC64LE9-NEXT: blr entry: %result = call <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f32( @@ -5856,12 +5857,12 @@ ; PC64LE9-NEXT: mtfprwz 1, 3 ; PC64LE9-NEXT: addis 3, 2, .LCPI105_0@toc@ha ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: xscvdpsxws 0, 3 +; PC64LE9-NEXT: xscvdpsxws 1, 3 ; PC64LE9-NEXT: addi 3, 3, .LCPI105_0@toc@l -; PC64LE9-NEXT: lxv 35, 0(3) -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrwz 36, 3 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: mffprwz 3, 1 +; PC64LE9-NEXT: mtfprwz 1, 3 +; PC64LE9-NEXT: xxperm 34, 1, 0 ; PC64LE9-NEXT: blr entry: %result = call <3 x i32> @llvm.experimental.constrained.fptosi.v3i32.v3f64( @@ -6083,22 +6084,23 @@ ; PC64LE9-NEXT: xxswapd 1, 34 ; PC64LE9-NEXT: xscvspdpn 0, 0 ; PC64LE9-NEXT: xscvspdpn 1, 1 +; PC64LE9-NEXT: xxsldwi 2, 34, 34, 1 +; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xscvdpuxws 0, 0 ; PC64LE9-NEXT: xscvdpuxws 1, 1 +; PC64LE9-NEXT: xscvdpuxws 2, 2 ; PC64LE9-NEXT: mffprwz 3, 0 ; PC64LE9-NEXT: mtfprwz 0, 3 ; PC64LE9-NEXT: mffprwz 3, 1 ; PC64LE9-NEXT: mtfprwz 1, 3 ; PC64LE9-NEXT: addis 3, 2, .LCPI113_0@toc@ha -; PC64LE9-NEXT: xxmrghw 35, 1, 0 -; PC64LE9-NEXT: xxsldwi 0, 34, 34, 1 ; PC64LE9-NEXT: addi 3, 3, .LCPI113_0@toc@l -; PC64LE9-NEXT: lxv 36, 0(3) -; PC64LE9-NEXT: xscvspdpn 0, 0 -; PC64LE9-NEXT: xscvdpuxws 0, 0 -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrwz 34, 3 -; PC64LE9-NEXT: vperm 2, 2, 3, 4 +; PC64LE9-NEXT: xxmrghw 0, 1, 0 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: mffprwz 3, 2 +; PC64LE9-NEXT: mtfprwz 2, 3 +; PC64LE9-NEXT: xxperm 0, 2, 1 +; PC64LE9-NEXT: xxlor 34, 0, 0 ; PC64LE9-NEXT: blr entry: %result = call <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f32( @@ -6351,12 +6353,12 @@ ; PC64LE9-NEXT: mtfprwz 1, 3 ; PC64LE9-NEXT: addis 3, 2, .LCPI121_0@toc@ha ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: xscvdpuxws 0, 3 +; PC64LE9-NEXT: xscvdpuxws 1, 3 ; PC64LE9-NEXT: addi 3, 3, .LCPI121_0@toc@l -; PC64LE9-NEXT: lxv 35, 0(3) -; PC64LE9-NEXT: mffprwz 3, 0 -; PC64LE9-NEXT: mtvsrwz 36, 3 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: mffprwz 3, 1 +; PC64LE9-NEXT: mtfprwz 1, 3 +; PC64LE9-NEXT: xxperm 34, 1, 0 ; PC64LE9-NEXT: blr entry: %result = call <3 x i32> @llvm.experimental.constrained.fptoui.v3i32.v3f64( @@ -6559,13 +6561,13 @@ ; PC64LE9-NEXT: xsrsp 1, 2 ; PC64LE9-NEXT: addis 3, 2, .LCPI129_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI129_0@toc@l -; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 1, 1 ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: xsrsp 0, 3 -; PC64LE9-NEXT: xscvdpspn 36, 0 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: xsrsp 1, 3 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: xscvdpspn 1, 1 +; PC64LE9-NEXT: xxperm 34, 1, 0 ; PC64LE9-NEXT: blr entry: %result = call <3 x float> @llvm.experimental.constrained.fptrunc.v3f32.v3f64( @@ -6769,15 +6771,15 @@ ; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xscvspdpn 0, 0 -; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xsrdpip 1, 1 ; PC64LE9-NEXT: xsrdpip 2, 2 ; PC64LE9-NEXT: xsrdpip 0, 0 ; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xscvdpspn 1, 1 -; PC64LE9-NEXT: xscvdpspn 36, 0 +; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxmrghw 34, 1, 2 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: blr entry: %ceil = call <3 x float> @llvm.experimental.constrained.ceil.v3f32( @@ -6885,15 +6887,15 @@ ; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xscvspdpn 0, 0 -; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xsrdpim 1, 1 ; PC64LE9-NEXT: xsrdpim 2, 2 ; PC64LE9-NEXT: xsrdpim 0, 0 ; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xscvdpspn 1, 1 -; PC64LE9-NEXT: xscvdpspn 36, 0 +; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxmrghw 34, 1, 2 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: blr entry: %floor = call <3 x float> @llvm.experimental.constrained.floor.v3f32( @@ -7000,15 +7002,15 @@ ; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xscvspdpn 0, 0 -; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xsrdpi 1, 1 ; PC64LE9-NEXT: xsrdpi 2, 2 ; PC64LE9-NEXT: xsrdpi 0, 0 ; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xscvdpspn 1, 1 -; PC64LE9-NEXT: xscvdpspn 36, 0 +; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxmrghw 34, 1, 2 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: blr entry: %round = call <3 x float> @llvm.experimental.constrained.round.v3f32( @@ -7116,15 +7118,15 @@ ; PC64LE9-NEXT: xscvspdpn 1, 1 ; PC64LE9-NEXT: xscvspdpn 2, 2 ; PC64LE9-NEXT: xscvspdpn 0, 0 -; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xsrdpiz 1, 1 ; PC64LE9-NEXT: xsrdpiz 2, 2 ; PC64LE9-NEXT: xsrdpiz 0, 0 ; PC64LE9-NEXT: xscvdpspn 2, 2 ; PC64LE9-NEXT: xscvdpspn 1, 1 -; PC64LE9-NEXT: xscvdpspn 36, 0 +; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xxmrghw 34, 1, 2 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: blr entry: %trunc = call <3 x float> @llvm.experimental.constrained.trunc.v3f32( @@ -7265,8 +7267,8 @@ ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI155_0@toc@ha ; PC64LE9-NEXT: addi 3, 3, .LCPI155_0@toc@l -; PC64LE9-NEXT: lxv 35, 0(3) -; PC64LE9-NEXT: vperm 2, 2, 2, 3 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: xxperm 34, 34, 0 ; PC64LE9-NEXT: vextsh2d 2, 2 ; PC64LE9-NEXT: xvcvsxddp 34, 34 ; PC64LE9-NEXT: blr @@ -7479,14 +7481,15 @@ ; PC64LE9-NEXT: xscvsxdsp 1, 1 ; PC64LE9-NEXT: addi 3, 3, .LCPI161_0@toc@l ; PC64LE9-NEXT: xscvdpspn 0, 0 -; PC64LE9-NEXT: lxv 36, 0(3) -; PC64LE9-NEXT: mfvsrwz 3, 34 ; PC64LE9-NEXT: xscvdpspn 1, 1 -; PC64LE9-NEXT: xxmrghw 35, 1, 0 -; PC64LE9-NEXT: mtfprwa 0, 3 -; PC64LE9-NEXT: xscvsxdsp 0, 0 -; PC64LE9-NEXT: xscvdpspn 34, 0 -; PC64LE9-NEXT: vperm 2, 2, 3, 4 +; PC64LE9-NEXT: xxmrghw 0, 1, 0 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: mfvsrwz 3, 34 +; PC64LE9-NEXT: mtfprwa 2, 3 +; PC64LE9-NEXT: xscvsxdsp 2, 2 +; PC64LE9-NEXT: xscvdpspn 2, 2 +; PC64LE9-NEXT: xxperm 0, 2, 1 +; PC64LE9-NEXT: xxlor 34, 0, 0 ; PC64LE9-NEXT: blr entry: %result = call <3 x float> @@ -7552,14 +7555,14 @@ ; PC64LE9-NEXT: xscvsxdsp 0, 0 ; PC64LE9-NEXT: xscvsxdsp 1, 1 ; PC64LE9-NEXT: addi 3, 3, .LCPI163_0@toc@l -; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 1, 1 ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: mtfprd 0, 5 -; PC64LE9-NEXT: xscvsxdsp 0, 0 -; PC64LE9-NEXT: xscvdpspn 36, 0 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: mtfprd 1, 5 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: xscvsxdsp 1, 1 +; PC64LE9-NEXT: xscvdpspn 1, 1 +; PC64LE9-NEXT: xxperm 34, 1, 0 ; PC64LE9-NEXT: blr entry: %result = call <3 x float> @@ -7830,10 +7833,10 @@ ; PC64LE9-LABEL: constrained_vector_uitofp_v2f64_v2i16: ; PC64LE9: # %bb.0: # %entry ; PC64LE9-NEXT: addis 3, 2, .LCPI173_0@toc@ha -; PC64LE9-NEXT: xxlxor 36, 36, 36 +; PC64LE9-NEXT: xxlxor 0, 0, 0 ; PC64LE9-NEXT: addi 3, 3, .LCPI173_0@toc@l -; PC64LE9-NEXT: lxv 35, 0(3) -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: xxperm 34, 0, 1 ; PC64LE9-NEXT: xvcvuxddp 34, 34 ; PC64LE9-NEXT: blr entry: @@ -8045,14 +8048,15 @@ ; PC64LE9-NEXT: xscvuxdsp 1, 1 ; PC64LE9-NEXT: addi 3, 3, .LCPI179_0@toc@l ; PC64LE9-NEXT: xscvdpspn 0, 0 -; PC64LE9-NEXT: lxv 36, 0(3) -; PC64LE9-NEXT: mfvsrwz 3, 34 ; PC64LE9-NEXT: xscvdpspn 1, 1 -; PC64LE9-NEXT: xxmrghw 35, 1, 0 -; PC64LE9-NEXT: mtfprwz 0, 3 -; PC64LE9-NEXT: xscvuxdsp 0, 0 -; PC64LE9-NEXT: xscvdpspn 34, 0 -; PC64LE9-NEXT: vperm 2, 2, 3, 4 +; PC64LE9-NEXT: xxmrghw 0, 1, 0 +; PC64LE9-NEXT: lxv 1, 0(3) +; PC64LE9-NEXT: mfvsrwz 3, 34 +; PC64LE9-NEXT: mtfprwz 2, 3 +; PC64LE9-NEXT: xscvuxdsp 2, 2 +; PC64LE9-NEXT: xscvdpspn 2, 2 +; PC64LE9-NEXT: xxperm 0, 2, 1 +; PC64LE9-NEXT: xxlor 34, 0, 0 ; PC64LE9-NEXT: blr entry: %result = call <3 x float> @@ -8118,14 +8122,14 @@ ; PC64LE9-NEXT: xscvuxdsp 0, 0 ; PC64LE9-NEXT: xscvuxdsp 1, 1 ; PC64LE9-NEXT: addi 3, 3, .LCPI181_0@toc@l -; PC64LE9-NEXT: lxv 35, 0(3) ; PC64LE9-NEXT: xscvdpspn 0, 0 ; PC64LE9-NEXT: xscvdpspn 1, 1 ; PC64LE9-NEXT: xxmrghw 34, 1, 0 -; PC64LE9-NEXT: mtfprd 0, 5 -; PC64LE9-NEXT: xscvuxdsp 0, 0 -; PC64LE9-NEXT: xscvdpspn 36, 0 -; PC64LE9-NEXT: vperm 2, 4, 2, 3 +; PC64LE9-NEXT: mtfprd 1, 5 +; PC64LE9-NEXT: lxv 0, 0(3) +; PC64LE9-NEXT: xscvuxdsp 1, 1 +; PC64LE9-NEXT: xscvdpspn 1, 1 +; PC64LE9-NEXT: xxperm 34, 1, 0 ; PC64LE9-NEXT: blr entry: %result = call <3 x float> diff --git a/llvm/test/CodeGen/RISCV/add-before-shl.ll b/llvm/test/CodeGen/RISCV/add-before-shl.ll --- a/llvm/test/CodeGen/RISCV/add-before-shl.ll +++ b/llvm/test/CodeGen/RISCV/add-before-shl.ll @@ -196,7 +196,7 @@ ; ; RV32C-LABEL: add_wide_operand: ; RV32C: # %bb.0: -; RV32C-NEXT: c.lw a2, 4(a1) +; RV32C-NEXT: lw a6, 4(a1) ; RV32C-NEXT: c.lw a3, 12(a1) ; RV32C-NEXT: c.lw a4, 0(a1) ; RV32C-NEXT: c.lw a1, 8(a1) @@ -204,18 +204,18 @@ ; RV32C-NEXT: c.add a3, a5 ; RV32C-NEXT: c.slli a3, 3 ; RV32C-NEXT: srli a5, a1, 29 -; RV32C-NEXT: or a6, a3, a5 -; RV32C-NEXT: srli a5, a4, 29 -; RV32C-NEXT: slli a3, a2, 3 ; RV32C-NEXT: c.or a3, a5 -; RV32C-NEXT: c.srli a2, 29 +; RV32C-NEXT: srli a5, a4, 29 +; RV32C-NEXT: slli a2, a6, 3 +; RV32C-NEXT: c.or a2, a5 +; RV32C-NEXT: srli a5, a6, 29 ; RV32C-NEXT: c.slli a1, 3 -; RV32C-NEXT: c.or a1, a2 -; RV32C-NEXT: slli a2, a4, 3 -; RV32C-NEXT: c.sw a2, 0(a0) +; RV32C-NEXT: c.or a1, a5 +; RV32C-NEXT: c.slli a4, 3 +; RV32C-NEXT: c.sw a4, 0(a0) ; RV32C-NEXT: c.sw a1, 8(a0) -; RV32C-NEXT: c.sw a3, 4(a0) -; RV32C-NEXT: sw a6, 12(a0) +; RV32C-NEXT: c.sw a2, 4(a0) +; RV32C-NEXT: c.sw a3, 12(a0) ; RV32C-NEXT: c.jr ra ; ; RV64C-LABEL: add_wide_operand: diff --git a/llvm/test/CodeGen/RISCV/addcarry.ll b/llvm/test/CodeGen/RISCV/addcarry.ll --- a/llvm/test/CodeGen/RISCV/addcarry.ll +++ b/llvm/test/CodeGen/RISCV/addcarry.ll @@ -32,13 +32,13 @@ ; RISCV32-NEXT: # %bb.3: ; RISCV32-NEXT: sub a5, a5, a0 ; RISCV32-NEXT: .LBB0_4: -; RISCV32-NEXT: slli a1, a5, 30 -; RISCV32-NEXT: srli a3, a4, 2 -; RISCV32-NEXT: or a1, a1, a3 -; RISCV32-NEXT: slli a3, a4, 30 +; RISCV32-NEXT: slli a5, a5, 30 +; RISCV32-NEXT: srli a1, a4, 2 +; RISCV32-NEXT: or a1, a5, a1 +; RISCV32-NEXT: slli a4, a4, 30 ; RISCV32-NEXT: mul a0, a0, a2 ; RISCV32-NEXT: srli a0, a0, 2 -; RISCV32-NEXT: or a0, a3, a0 +; RISCV32-NEXT: or a0, a4, a0 ; RISCV32-NEXT: ret %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2); ret i64 %tmp; diff --git a/llvm/test/CodeGen/RISCV/aext-to-sext.ll b/llvm/test/CodeGen/RISCV/aext-to-sext.ll --- a/llvm/test/CodeGen/RISCV/aext-to-sext.ll +++ b/llvm/test/CodeGen/RISCV/aext-to-sext.ll @@ -82,8 +82,8 @@ ; RV64I-NEXT: # %bb.1: # %iffalse ; RV64I-NEXT: li a1, -2 ; RV64I-NEXT: .LBB2_2: # %merge -; RV64I-NEXT: slli a0, a1, 32 -; RV64I-NEXT: srli a0, a0, 32 +; RV64I-NEXT: slli a1, a1, 32 +; RV64I-NEXT: srli a0, a1, 32 ; RV64I-NEXT: ret %a = icmp ne i32 %c, 0 br i1 %a, label %iftrue, label %iffalse diff --git a/llvm/test/CodeGen/RISCV/and.ll b/llvm/test/CodeGen/RISCV/and.ll --- a/llvm/test/CodeGen/RISCV/and.ll +++ b/llvm/test/CodeGen/RISCV/and.ll @@ -187,8 +187,8 @@ define i64 @and64_0x7fffffff00000000(i64 %x) { ; RV32I-LABEL: and64_0x7fffffff00000000: ; RV32I: # %bb.0: -; RV32I-NEXT: slli a0, a1, 1 -; RV32I-NEXT: srli a1, a0, 1 +; RV32I-NEXT: slli a1, a1, 1 +; RV32I-NEXT: srli a1, a1, 1 ; RV32I-NEXT: li a0, 0 ; RV32I-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll --- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll +++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll @@ -8350,8 +8350,8 @@ ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 16 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: and s3, s0, s2 ; RV32I-NEXT: j .LBB100_2 ; RV32I-NEXT: .LBB100_1: # %atomicrmw.start @@ -8419,8 +8419,8 @@ ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s2, a0, -1 +; RV64I-NEXT: lui s2, 16 +; RV64I-NEXT: addiw s2, s2, -1 ; RV64I-NEXT: and s3, s0, s2 ; RV64I-NEXT: j .LBB100_2 ; RV64I-NEXT: .LBB100_1: # %atomicrmw.start @@ -8492,8 +8492,8 @@ ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 16 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: and s3, s0, s2 ; RV32I-NEXT: j .LBB101_2 ; RV32I-NEXT: .LBB101_1: # %atomicrmw.start @@ -8561,8 +8561,8 @@ ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s2, a0, -1 +; RV64I-NEXT: lui s2, 16 +; RV64I-NEXT: addiw s2, s2, -1 ; RV64I-NEXT: and s3, s0, s2 ; RV64I-NEXT: j .LBB101_2 ; RV64I-NEXT: .LBB101_1: # %atomicrmw.start @@ -8634,8 +8634,8 @@ ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 16 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: and s3, s0, s2 ; RV32I-NEXT: j .LBB102_2 ; RV32I-NEXT: .LBB102_1: # %atomicrmw.start @@ -8703,8 +8703,8 @@ ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s2, a0, -1 +; RV64I-NEXT: lui s2, 16 +; RV64I-NEXT: addiw s2, s2, -1 ; RV64I-NEXT: and s3, s0, s2 ; RV64I-NEXT: j .LBB102_2 ; RV64I-NEXT: .LBB102_1: # %atomicrmw.start @@ -8776,8 +8776,8 @@ ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 16 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: and s3, s0, s2 ; RV32I-NEXT: j .LBB103_2 ; RV32I-NEXT: .LBB103_1: # %atomicrmw.start @@ -8845,8 +8845,8 @@ ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s2, a0, -1 +; RV64I-NEXT: lui s2, 16 +; RV64I-NEXT: addiw s2, s2, -1 ; RV64I-NEXT: and s3, s0, s2 ; RV64I-NEXT: j .LBB103_2 ; RV64I-NEXT: .LBB103_1: # %atomicrmw.start @@ -8918,8 +8918,8 @@ ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 16 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: and s3, s0, s2 ; RV32I-NEXT: j .LBB104_2 ; RV32I-NEXT: .LBB104_1: # %atomicrmw.start @@ -8987,8 +8987,8 @@ ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s2, a0, -1 +; RV64I-NEXT: lui s2, 16 +; RV64I-NEXT: addiw s2, s2, -1 ; RV64I-NEXT: and s3, s0, s2 ; RV64I-NEXT: j .LBB104_2 ; RV64I-NEXT: .LBB104_1: # %atomicrmw.start @@ -9060,8 +9060,8 @@ ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 16 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: and s3, s0, s2 ; RV32I-NEXT: j .LBB105_2 ; RV32I-NEXT: .LBB105_1: # %atomicrmw.start @@ -9129,8 +9129,8 @@ ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s2, a0, -1 +; RV64I-NEXT: lui s2, 16 +; RV64I-NEXT: addiw s2, s2, -1 ; RV64I-NEXT: and s3, s0, s2 ; RV64I-NEXT: j .LBB105_2 ; RV64I-NEXT: .LBB105_1: # %atomicrmw.start @@ -9202,8 +9202,8 @@ ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 16 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: and s3, s0, s2 ; RV32I-NEXT: j .LBB106_2 ; RV32I-NEXT: .LBB106_1: # %atomicrmw.start @@ -9271,8 +9271,8 @@ ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s2, a0, -1 +; RV64I-NEXT: lui s2, 16 +; RV64I-NEXT: addiw s2, s2, -1 ; RV64I-NEXT: and s3, s0, s2 ; RV64I-NEXT: j .LBB106_2 ; RV64I-NEXT: .LBB106_1: # %atomicrmw.start @@ -9344,8 +9344,8 @@ ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 16 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: and s3, s0, s2 ; RV32I-NEXT: j .LBB107_2 ; RV32I-NEXT: .LBB107_1: # %atomicrmw.start @@ -9413,8 +9413,8 @@ ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s2, a0, -1 +; RV64I-NEXT: lui s2, 16 +; RV64I-NEXT: addiw s2, s2, -1 ; RV64I-NEXT: and s3, s0, s2 ; RV64I-NEXT: j .LBB107_2 ; RV64I-NEXT: .LBB107_1: # %atomicrmw.start @@ -9486,8 +9486,8 @@ ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 16 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: and s3, s0, s2 ; RV32I-NEXT: j .LBB108_2 ; RV32I-NEXT: .LBB108_1: # %atomicrmw.start @@ -9555,8 +9555,8 @@ ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s2, a0, -1 +; RV64I-NEXT: lui s2, 16 +; RV64I-NEXT: addiw s2, s2, -1 ; RV64I-NEXT: and s3, s0, s2 ; RV64I-NEXT: j .LBB108_2 ; RV64I-NEXT: .LBB108_1: # %atomicrmw.start @@ -9628,8 +9628,8 @@ ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 16 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: and s3, s0, s2 ; RV32I-NEXT: j .LBB109_2 ; RV32I-NEXT: .LBB109_1: # %atomicrmw.start @@ -9697,8 +9697,8 @@ ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s2, a0, -1 +; RV64I-NEXT: lui s2, 16 +; RV64I-NEXT: addiw s2, s2, -1 ; RV64I-NEXT: and s3, s0, s2 ; RV64I-NEXT: j .LBB109_2 ; RV64I-NEXT: .LBB109_1: # %atomicrmw.start diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll --- a/llvm/test/CodeGen/RISCV/atomic-signext.ll +++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll @@ -609,8 +609,8 @@ ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: j .LBB10_1 ; RV32I-NEXT: .LBB10_4: # %atomicrmw.end -; RV32I-NEXT: slli a0, a3, 24 -; RV32I-NEXT: srai a0, a0, 24 +; RV32I-NEXT: slli a3, a3, 24 +; RV32I-NEXT: srai a0, a3, 24 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -683,8 +683,8 @@ ; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: j .LBB10_1 ; RV64I-NEXT: .LBB10_4: # %atomicrmw.end -; RV64I-NEXT: slli a0, a3, 56 -; RV64I-NEXT: srai a0, a0, 56 +; RV64I-NEXT: slli a3, a3, 56 +; RV64I-NEXT: srai a0, a3, 56 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -761,8 +761,8 @@ ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: j .LBB11_1 ; RV32I-NEXT: .LBB11_4: # %atomicrmw.end -; RV32I-NEXT: slli a0, a3, 24 -; RV32I-NEXT: srai a0, a0, 24 +; RV32I-NEXT: slli a3, a3, 24 +; RV32I-NEXT: srai a0, a3, 24 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -835,8 +835,8 @@ ; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: j .LBB11_1 ; RV64I-NEXT: .LBB11_4: # %atomicrmw.end -; RV64I-NEXT: slli a0, a3, 56 -; RV64I-NEXT: srai a0, a0, 56 +; RV64I-NEXT: slli a3, a3, 56 +; RV64I-NEXT: srai a0, a3, 56 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -911,8 +911,8 @@ ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: j .LBB12_1 ; RV32I-NEXT: .LBB12_4: # %atomicrmw.end -; RV32I-NEXT: slli a0, a3, 24 -; RV32I-NEXT: srai a0, a0, 24 +; RV32I-NEXT: slli a3, a3, 24 +; RV32I-NEXT: srai a0, a3, 24 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -978,8 +978,8 @@ ; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: j .LBB12_1 ; RV64I-NEXT: .LBB12_4: # %atomicrmw.end -; RV64I-NEXT: slli a0, a3, 56 -; RV64I-NEXT: srai a0, a0, 56 +; RV64I-NEXT: slli a3, a3, 56 +; RV64I-NEXT: srai a0, a3, 56 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -1049,8 +1049,8 @@ ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: j .LBB13_1 ; RV32I-NEXT: .LBB13_4: # %atomicrmw.end -; RV32I-NEXT: slli a0, a3, 24 -; RV32I-NEXT: srai a0, a0, 24 +; RV32I-NEXT: slli a3, a3, 24 +; RV32I-NEXT: srai a0, a3, 24 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1116,8 +1116,8 @@ ; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: j .LBB13_1 ; RV64I-NEXT: .LBB13_4: # %atomicrmw.end -; RV64I-NEXT: slli a0, a3, 56 -; RV64I-NEXT: srai a0, a0, 56 +; RV64I-NEXT: slli a3, a3, 56 +; RV64I-NEXT: srai a0, a3, 56 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -1657,8 +1657,8 @@ ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: j .LBB21_1 ; RV32I-NEXT: .LBB21_4: # %atomicrmw.end -; RV32I-NEXT: slli a0, a3, 16 -; RV32I-NEXT: srai a0, a0, 16 +; RV32I-NEXT: slli a3, a3, 16 +; RV32I-NEXT: srai a0, a3, 16 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1733,8 +1733,8 @@ ; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: j .LBB21_1 ; RV64I-NEXT: .LBB21_4: # %atomicrmw.end -; RV64I-NEXT: slli a0, a3, 48 -; RV64I-NEXT: srai a0, a0, 48 +; RV64I-NEXT: slli a3, a3, 48 +; RV64I-NEXT: srai a0, a3, 48 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -1813,8 +1813,8 @@ ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: j .LBB22_1 ; RV32I-NEXT: .LBB22_4: # %atomicrmw.end -; RV32I-NEXT: slli a0, a3, 16 -; RV32I-NEXT: srai a0, a0, 16 +; RV32I-NEXT: slli a3, a3, 16 +; RV32I-NEXT: srai a0, a3, 16 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -1889,8 +1889,8 @@ ; RV64I-NEXT: mv a2, s1 ; RV64I-NEXT: j .LBB22_1 ; RV64I-NEXT: .LBB22_4: # %atomicrmw.end -; RV64I-NEXT: slli a0, a3, 48 -; RV64I-NEXT: srai a0, a0, 48 +; RV64I-NEXT: slli a3, a3, 48 +; RV64I-NEXT: srai a0, a3, 48 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -1946,8 +1946,8 @@ ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 16 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: and s3, s0, s2 ; RV32I-NEXT: j .LBB23_2 ; RV32I-NEXT: .LBB23_1: # %atomicrmw.start @@ -1970,8 +1970,8 @@ ; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB23_1 ; RV32I-NEXT: .LBB23_4: # %atomicrmw.end -; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: srai a0, a0, 16 +; RV32I-NEXT: slli a1, a1, 16 +; RV32I-NEXT: srai a0, a1, 16 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -2018,8 +2018,8 @@ ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s2, a0, -1 +; RV64I-NEXT: lui s2, 16 +; RV64I-NEXT: addiw s2, s2, -1 ; RV64I-NEXT: and s3, s0, s2 ; RV64I-NEXT: j .LBB23_2 ; RV64I-NEXT: .LBB23_1: # %atomicrmw.start @@ -2042,8 +2042,8 @@ ; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB23_1 ; RV64I-NEXT: .LBB23_4: # %atomicrmw.end -; RV64I-NEXT: slli a0, a1, 48 -; RV64I-NEXT: srai a0, a0, 48 +; RV64I-NEXT: slli a1, a1, 48 +; RV64I-NEXT: srai a0, a1, 48 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload @@ -2094,8 +2094,8 @@ ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: lhu a1, 0(a0) -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 16 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: and s3, s0, s2 ; RV32I-NEXT: j .LBB24_2 ; RV32I-NEXT: .LBB24_1: # %atomicrmw.start @@ -2118,8 +2118,8 @@ ; RV32I-NEXT: mv a2, s0 ; RV32I-NEXT: j .LBB24_1 ; RV32I-NEXT: .LBB24_4: # %atomicrmw.end -; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: srai a0, a0, 16 +; RV32I-NEXT: slli a1, a1, 16 +; RV32I-NEXT: srai a0, a1, 16 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload @@ -2166,8 +2166,8 @@ ; RV64I-NEXT: mv s0, a1 ; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: lhu a1, 0(a0) -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s2, a0, -1 +; RV64I-NEXT: lui s2, 16 +; RV64I-NEXT: addiw s2, s2, -1 ; RV64I-NEXT: and s3, s0, s2 ; RV64I-NEXT: j .LBB24_2 ; RV64I-NEXT: .LBB24_1: # %atomicrmw.start @@ -2190,8 +2190,8 @@ ; RV64I-NEXT: mv a2, s0 ; RV64I-NEXT: j .LBB24_1 ; RV64I-NEXT: .LBB24_4: # %atomicrmw.end -; RV64I-NEXT: slli a0, a1, 48 -; RV64I-NEXT: srai a0, a0, 48 +; RV64I-NEXT: slli a1, a1, 48 +; RV64I-NEXT: srai a0, a1, 48 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/bittest.ll b/llvm/test/CodeGen/RISCV/bittest.ll --- a/llvm/test/CodeGen/RISCV/bittest.ll +++ b/llvm/test/CodeGen/RISCV/bittest.ll @@ -987,8 +987,8 @@ define i64 @bit_55_nz_select_i64(i64 %a, i64 %b, i64 %c) { ; RV32I-LABEL: bit_55_nz_select_i64: ; RV32I: # %bb.0: -; RV32I-NEXT: slli a0, a1, 8 -; RV32I-NEXT: srli a6, a0, 31 +; RV32I-NEXT: slli a1, a1, 8 +; RV32I-NEXT: srli a6, a1, 31 ; RV32I-NEXT: mv a1, a3 ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: bnez a6, .LBB34_2 @@ -1584,8 +1584,8 @@ define void @bit_62_z_branch_i64(i64 %0) { ; RV32-LABEL: bit_62_z_branch_i64: ; RV32: # %bb.0: -; RV32-NEXT: slli a0, a1, 1 -; RV32-NEXT: bltz a0, .LBB55_2 +; RV32-NEXT: slli a1, a1, 1 +; RV32-NEXT: bltz a1, .LBB55_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: tail bar@plt ; RV32-NEXT: .LBB55_2: @@ -1614,8 +1614,8 @@ define void @bit_62_nz_branch_i64(i64 %0) { ; RV32-LABEL: bit_62_nz_branch_i64: ; RV32: # %bb.0: -; RV32-NEXT: slli a0, a1, 1 -; RV32-NEXT: bgez a0, .LBB56_2 +; RV32-NEXT: slli a1, a1, 1 +; RV32-NEXT: bgez a1, .LBB56_2 ; RV32-NEXT: # %bb.1: ; RV32-NEXT: tail bar@plt ; RV32-NEXT: .LBB56_2: diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation.ll b/llvm/test/CodeGen/RISCV/branch-relaxation.ll --- a/llvm/test/CodeGen/RISCV/branch-relaxation.ll +++ b/llvm/test/CodeGen/RISCV/branch-relaxation.ll @@ -342,11 +342,9 @@ ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: li ra, 1 ; CHECK-RV64-NEXT: #NO_APP -; CHECK-RV64-NEXT: sd ra, 16(sp) # 8-byte Folded Spill ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: li t0, 5 ; CHECK-RV64-NEXT: #NO_APP -; CHECK-RV64-NEXT: sd t0, 8(sp) # 8-byte Folded Spill ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: li t1, 6 ; CHECK-RV64-NEXT: #NO_APP @@ -422,24 +420,24 @@ ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: li t5, 30 ; CHECK-RV64-NEXT: #NO_APP -; CHECK-RV64-NEXT: sext.w t0, t5 +; CHECK-RV64-NEXT: sd t5, 16(sp) # 8-byte Folded Spill +; CHECK-RV64-NEXT: sext.w t5, t5 ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: li t6, 31 ; CHECK-RV64-NEXT: #NO_APP -; CHECK-RV64-NEXT: sext.w ra, t6 -; CHECK-RV64-NEXT: beq t0, ra, .LBB2_1 +; CHECK-RV64-NEXT: sd t6, 8(sp) # 8-byte Folded Spill +; CHECK-RV64-NEXT: sext.w t6, t6 +; CHECK-RV64-NEXT: beq t5, t6, .LBB2_1 ; CHECK-RV64-NEXT: # %bb.3: -; CHECK-RV64-NEXT: jump .LBB2_2, t0 +; CHECK-RV64-NEXT: jump .LBB2_2, t5 ; CHECK-RV64-NEXT: .LBB2_1: # %branch_1 ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: .zero 1048576 ; CHECK-RV64-NEXT: #NO_APP ; CHECK-RV64-NEXT: .LBB2_2: # %branch_2 -; CHECK-RV64-NEXT: ld ra, 16(sp) # 8-byte Folded Reload ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: # reg use ra ; CHECK-RV64-NEXT: #NO_APP -; CHECK-RV64-NEXT: ld t0, 8(sp) # 8-byte Folded Reload ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: # reg use t0 ; CHECK-RV64-NEXT: #NO_APP @@ -515,9 +513,11 @@ ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: # reg use t4 ; CHECK-RV64-NEXT: #NO_APP +; CHECK-RV64-NEXT: ld t5, 16(sp) # 8-byte Folded Reload ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: # reg use t5 ; CHECK-RV64-NEXT: #NO_APP +; CHECK-RV64-NEXT: ld t6, 8(sp) # 8-byte Folded Reload ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: # reg use t6 ; CHECK-RV64-NEXT: #NO_APP @@ -885,17 +885,9 @@ ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: li ra, 1 ; CHECK-RV64-NEXT: #NO_APP -; CHECK-RV64-NEXT: lui a0, 1 -; CHECK-RV64-NEXT: addiw a0, a0, -8 -; CHECK-RV64-NEXT: add a0, sp, a0 -; CHECK-RV64-NEXT: sd ra, 0(a0) # 8-byte Folded Spill ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: li t0, 5 ; CHECK-RV64-NEXT: #NO_APP -; CHECK-RV64-NEXT: lui a0, 1 -; CHECK-RV64-NEXT: addiw a0, a0, -16 -; CHECK-RV64-NEXT: add a0, sp, a0 -; CHECK-RV64-NEXT: sd t0, 0(a0) # 8-byte Folded Spill ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: li t1, 6 ; CHECK-RV64-NEXT: #NO_APP @@ -971,30 +963,32 @@ ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: li t5, 30 ; CHECK-RV64-NEXT: #NO_APP -; CHECK-RV64-NEXT: sext.w t0, t5 +; CHECK-RV64-NEXT: sd t0, 0(sp) +; CHECK-RV64-NEXT: lui t0, 1 +; CHECK-RV64-NEXT: addiw t0, t0, -8 +; CHECK-RV64-NEXT: add t0, sp, t0 +; CHECK-RV64-NEXT: sd t5, 0(t0) # 8-byte Folded Spill +; CHECK-RV64-NEXT: sext.w t5, t5 ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: li t6, 31 ; CHECK-RV64-NEXT: #NO_APP -; CHECK-RV64-NEXT: sext.w ra, t6 -; CHECK-RV64-NEXT: beq t0, ra, .LBB3_1 +; CHECK-RV64-NEXT: lui t0, 1 +; CHECK-RV64-NEXT: addiw t0, t0, -16 +; CHECK-RV64-NEXT: add t0, sp, t0 +; CHECK-RV64-NEXT: sd t6, 0(t0) # 8-byte Folded Spill +; CHECK-RV64-NEXT: ld t0, 0(sp) +; CHECK-RV64-NEXT: sext.w t6, t6 +; CHECK-RV64-NEXT: beq t5, t6, .LBB3_1 ; CHECK-RV64-NEXT: # %bb.3: -; CHECK-RV64-NEXT: jump .LBB3_2, t0 +; CHECK-RV64-NEXT: jump .LBB3_2, t5 ; CHECK-RV64-NEXT: .LBB3_1: # %branch_1 ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: .zero 1048576 ; CHECK-RV64-NEXT: #NO_APP ; CHECK-RV64-NEXT: .LBB3_2: # %branch_2 -; CHECK-RV64-NEXT: lui t0, 1 -; CHECK-RV64-NEXT: addiw t0, t0, -8 -; CHECK-RV64-NEXT: add t0, sp, t0 -; CHECK-RV64-NEXT: ld ra, 0(t0) # 8-byte Folded Reload ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: # reg use ra ; CHECK-RV64-NEXT: #NO_APP -; CHECK-RV64-NEXT: lui t0, 1 -; CHECK-RV64-NEXT: addiw t0, t0, -16 -; CHECK-RV64-NEXT: add t0, sp, t0 -; CHECK-RV64-NEXT: ld t0, 0(t0) # 8-byte Folded Reload ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: # reg use t0 ; CHECK-RV64-NEXT: #NO_APP @@ -1070,9 +1064,17 @@ ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: # reg use t4 ; CHECK-RV64-NEXT: #NO_APP +; CHECK-RV64-NEXT: lui a0, 1 +; CHECK-RV64-NEXT: addiw a0, a0, -8 +; CHECK-RV64-NEXT: add a0, sp, a0 +; CHECK-RV64-NEXT: ld t5, 0(a0) # 8-byte Folded Reload ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: # reg use t5 ; CHECK-RV64-NEXT: #NO_APP +; CHECK-RV64-NEXT: lui a0, 1 +; CHECK-RV64-NEXT: addiw a0, a0, -16 +; CHECK-RV64-NEXT: add a0, sp, a0 +; CHECK-RV64-NEXT: ld t6, 0(a0) # 8-byte Folded Reload ; CHECK-RV64-NEXT: #APP ; CHECK-RV64-NEXT: # reg use t6 ; CHECK-RV64-NEXT: #NO_APP diff --git a/llvm/test/CodeGen/RISCV/calling-conv-half.ll b/llvm/test/CodeGen/RISCV/calling-conv-half.ll --- a/llvm/test/CodeGen/RISCV/calling-conv-half.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-half.ll @@ -19,8 +19,8 @@ ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: slli a0, a1, 16 -; RV32I-NEXT: srli a0, a0, 16 +; RV32I-NEXT: slli a1, a1, 16 +; RV32I-NEXT: srli a0, a1, 16 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: call __fixsfsi@plt ; RV32I-NEXT: add a0, s0, a0 @@ -35,8 +35,8 @@ ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: slli a0, a1, 48 -; RV64I-NEXT: srli a0, a0, 48 +; RV64I-NEXT: slli a1, a1, 48 +; RV64I-NEXT: srli a0, a1, 48 ; RV64I-NEXT: call __extendhfsf2@plt ; RV64I-NEXT: call __fixsfdi@plt ; RV64I-NEXT: addw a0, s0, a0 diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll --- a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll @@ -33,8 +33,8 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -16 ; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: li a0, 1 -; RV64I-NEXT: slli a1, a0, 62 +; RV64I-NEXT: li a1, 1 +; RV64I-NEXT: slli a1, a1, 62 ; RV64I-NEXT: li a0, 1 ; RV64I-NEXT: call callee_double_in_regs@plt ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll --- a/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll @@ -335,8 +335,8 @@ ; RV64I-NEXT: ld a1, 0(sp) ; RV64I-NEXT: ld a2, 16(sp) ; RV64I-NEXT: ld a3, 32(sp) -; RV64I-NEXT: add a4, a5, a7 -; RV64I-NEXT: add a1, a4, a1 +; RV64I-NEXT: add a5, a5, a7 +; RV64I-NEXT: add a1, a5, a1 ; RV64I-NEXT: add a1, a1, a2 ; RV64I-NEXT: add a1, a1, a3 ; RV64I-NEXT: add a0, a1, a0 diff --git a/llvm/test/CodeGen/RISCV/div-by-constant.ll b/llvm/test/CodeGen/RISCV/div-by-constant.ll --- a/llvm/test/CodeGen/RISCV/div-by-constant.ll +++ b/llvm/test/CodeGen/RISCV/div-by-constant.ll @@ -83,8 +83,8 @@ ; RV32-NEXT: add a3, a6, a3 ; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sub a0, a1, a0 -; RV32-NEXT: mul a0, a0, a4 -; RV32-NEXT: add a1, a3, a0 +; RV32-NEXT: mul a1, a0, a4 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: mul a0, a5, a4 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/div-pow2.ll b/llvm/test/CodeGen/RISCV/div-pow2.ll --- a/llvm/test/CodeGen/RISCV/div-pow2.ll +++ b/llvm/test/CodeGen/RISCV/div-pow2.ll @@ -408,9 +408,9 @@ ; RV32I-NEXT: srai a1, a1, 31 ; RV32I-NEXT: add a1, a0, a1 ; RV32I-NEXT: sltu a0, a1, a0 -; RV32I-NEXT: add a1, a2, a0 -; RV32I-NEXT: srai a0, a1, 1 -; RV32I-NEXT: srai a1, a1, 31 +; RV32I-NEXT: add a2, a2, a0 +; RV32I-NEXT: srai a0, a2, 1 +; RV32I-NEXT: srai a1, a2, 31 ; RV32I-NEXT: ret ; ; RV64I-LABEL: sdiv64_pow2_8589934592: diff --git a/llvm/test/CodeGen/RISCV/div.ll b/llvm/test/CodeGen/RISCV/div.ll --- a/llvm/test/CodeGen/RISCV/div.ll +++ b/llvm/test/CodeGen/RISCV/div.ll @@ -198,8 +198,8 @@ ; RV32IM-NEXT: add a3, a6, a3 ; RV32IM-NEXT: sltu a0, a0, a2 ; RV32IM-NEXT: sub a0, a1, a0 -; RV32IM-NEXT: mul a0, a0, a4 -; RV32IM-NEXT: add a1, a3, a0 +; RV32IM-NEXT: mul a1, a0, a4 +; RV32IM-NEXT: add a1, a3, a1 ; RV32IM-NEXT: mul a0, a5, a4 ; RV32IM-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll --- a/llvm/test/CodeGen/RISCV/double-convert.ll +++ b/llvm/test/CodeGen/RISCV/double-convert.ll @@ -110,10 +110,9 @@ ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lui a0, 269824 -; RV32I-NEXT: addi a3, a0, -1 +; RV32I-NEXT: lui a3, 269824 +; RV32I-NEXT: addi a3, a3, -1 ; RV32I-NEXT: lui a2, 1047552 -; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: lui a3, 794112 @@ -161,9 +160,8 @@ ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: li a0, -497 -; RV64I-NEXT: slli a1, a0, 53 -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: li a1, -497 +; RV64I-NEXT: slli a1, a1, 53 ; RV64I-NEXT: call __gedf2@plt ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 @@ -306,10 +304,9 @@ ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lui a0, 270080 -; RV32I-NEXT: addi a3, a0, -1 +; RV32I-NEXT: lui a3, 270080 +; RV32I-NEXT: addi a3, a3, -1 ; RV32I-NEXT: lui a2, 1048064 -; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: neg s2, a0 @@ -596,10 +593,9 @@ ; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lui a0, 278016 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 278016 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: li a2, -1 -; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: mv s4, a0 @@ -676,9 +672,8 @@ ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: li a0, -481 -; RV64I-NEXT: slli a1, a0, 53 -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: li a1, -481 +; RV64I-NEXT: slli a1, a1, 53 ; RV64I-NEXT: call __gedf2@plt ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 @@ -800,10 +795,9 @@ ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lui a0, 278272 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 278272 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: li a2, -1 -; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a3, s2 ; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: sgtz a0, a0 @@ -1357,8 +1351,8 @@ ; RV32I-NEXT: .LBB26_2: # %start ; RV32I-NEXT: blez s2, .LBB26_4 ; RV32I-NEXT: # %bb.3: # %start -; RV32I-NEXT: lui a0, 8 -; RV32I-NEXT: addi s3, a0, -1 +; RV32I-NEXT: lui s3, 8 +; RV32I-NEXT: addi s3, s3, -1 ; RV32I-NEXT: .LBB26_4: # %start ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 @@ -1387,9 +1381,8 @@ ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: li a0, -505 -; RV64I-NEXT: slli a1, a0, 53 -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: li a1, -505 +; RV64I-NEXT: slli a1, a1, 53 ; RV64I-NEXT: call __gedf2@plt ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 @@ -1406,8 +1399,8 @@ ; RV64I-NEXT: call __gtdf2@plt ; RV64I-NEXT: blez a0, .LBB26_4 ; RV64I-NEXT: # %bb.3: # %start -; RV64I-NEXT: lui a0, 8 -; RV64I-NEXT: addiw s1, a0, -1 +; RV64I-NEXT: lui s1, 8 +; RV64I-NEXT: addiw s1, s1, -1 ; RV64I-NEXT: .LBB26_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 @@ -1492,9 +1485,8 @@ ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: mv s2, a0 -; RV32I-NEXT: lui a0, 265984 -; RV32I-NEXT: addi a3, a0, -32 -; RV32I-NEXT: mv a0, s2 +; RV32I-NEXT: lui a3, 265984 +; RV32I-NEXT: addi a3, a3, -32 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: mv s3, a0 @@ -1693,9 +1685,8 @@ ; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: li a0, -509 -; RV64I-NEXT: slli a1, a0, 53 -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: li a1, -509 +; RV64I-NEXT: slli a1, a1, 53 ; RV64I-NEXT: call __gedf2@plt ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 @@ -1705,8 +1696,8 @@ ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: li s1, -128 ; RV64I-NEXT: .LBB30_2: # %start -; RV64I-NEXT: lui a0, 65919 -; RV64I-NEXT: slli a1, a0, 34 +; RV64I-NEXT: lui a1, 65919 +; RV64I-NEXT: slli a1, a1, 34 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __gtdf2@plt ; RV64I-NEXT: blez a0, .LBB30_4 @@ -1845,8 +1836,8 @@ ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __fixunsdfdi@plt ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lui a0, 131967 -; RV64I-NEXT: slli a1, a0, 33 +; RV64I-NEXT: lui a1, 131967 +; RV64I-NEXT: slli a1, a1, 33 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __gtdf2@plt ; RV64I-NEXT: blez a0, .LBB32_2 @@ -1902,10 +1893,9 @@ ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lui a0, 270080 -; RV32I-NEXT: addi a3, a0, -1 +; RV32I-NEXT: lui a3, 270080 +; RV32I-NEXT: addi a3, a3, -1 ; RV32I-NEXT: lui a2, 1048064 -; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: neg s2, a0 @@ -1993,10 +1983,9 @@ ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lui a0, 269824 -; RV32I-NEXT: addi a3, a0, -1 +; RV32I-NEXT: lui a3, 269824 +; RV32I-NEXT: addi a3, a3, -1 ; RV32I-NEXT: lui a2, 1047552 -; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: call __gtdf2@plt ; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: lui a3, 794112 @@ -2044,9 +2033,8 @@ ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: li a0, -497 -; RV64I-NEXT: slli a1, a0, 53 -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: li a1, -497 +; RV64I-NEXT: slli a1, a1, 53 ; RV64I-NEXT: call __gedf2@plt ; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv a0, s0 diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll --- a/llvm/test/CodeGen/RISCV/float-arith.ll +++ b/llvm/test/CodeGen/RISCV/float-arith.ll @@ -238,8 +238,8 @@ ; RV32I-NEXT: not a0, a0 ; RV32I-NEXT: lui a1, 524288 ; RV32I-NEXT: and a0, a0, a1 -; RV32I-NEXT: slli a1, s0, 1 -; RV32I-NEXT: srli a1, a1, 1 +; RV32I-NEXT: slli s0, s0, 1 +; RV32I-NEXT: srli a1, s0, 1 ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload @@ -256,8 +256,8 @@ ; RV64I-NEXT: not a0, a0 ; RV64I-NEXT: lui a1, 524288 ; RV64I-NEXT: and a0, a0, a1 -; RV64I-NEXT: slli a1, s0, 33 -; RV64I-NEXT: srli a1, a1, 33 +; RV64I-NEXT: slli s0, s0, 33 +; RV64I-NEXT: srli a1, s0, 33 ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll b/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll --- a/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll +++ b/llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll @@ -73,8 +73,8 @@ ; RV32F-NEXT: mv s1, a0 ; RV32F-NEXT: call __adddf3@plt ; RV32F-NEXT: mv a2, a0 -; RV32F-NEXT: slli a0, a1, 1 -; RV32F-NEXT: srli a3, a0, 1 +; RV32F-NEXT: slli a1, a1, 1 +; RV32F-NEXT: srli a3, a1, 1 ; RV32F-NEXT: mv a0, s1 ; RV32F-NEXT: mv a1, s0 ; RV32F-NEXT: call __adddf3@plt diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll --- a/llvm/test/CodeGen/RISCV/float-convert.ll +++ b/llvm/test/CodeGen/RISCV/float-convert.ll @@ -65,8 +65,8 @@ ; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: lui s1, 524288 ; RV32I-NEXT: .LBB1_2: # %start -; RV32I-NEXT: lui a0, 323584 -; RV32I-NEXT: addi a1, a0, -1 +; RV32I-NEXT: lui a1, 323584 +; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: blez a0, .LBB1_4 @@ -107,8 +107,8 @@ ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: lui s1, 524288 ; RV64I-NEXT: .LBB1_2: # %start -; RV64I-NEXT: lui a0, 323584 -; RV64I-NEXT: addiw a1, a0, -1 +; RV64I-NEXT: lui a1, 323584 +; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: blez a0, .LBB1_4 @@ -239,8 +239,8 @@ ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfsi@plt ; RV32I-NEXT: and s1, s1, a0 -; RV32I-NEXT: lui a0, 325632 -; RV32I-NEXT: addi a1, a0, -1 +; RV32I-NEXT: lui a1, 325632 +; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: sgtz a0, a0 @@ -266,8 +266,8 @@ ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __fixunssfdi@plt ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lui a0, 325632 -; RV64I-NEXT: addiw a1, a0, -1 +; RV64I-NEXT: lui a1, 325632 +; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: blez a0, .LBB4_2 @@ -584,8 +584,8 @@ ; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: lui s3, 524288 ; RV32I-NEXT: .LBB12_2: # %start -; RV32I-NEXT: lui a0, 389120 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 389120 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __gtsf2@plt @@ -647,8 +647,8 @@ ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: slli s1, s3, 63 ; RV64I-NEXT: .LBB12_2: # %start -; RV64I-NEXT: lui a0, 389120 -; RV64I-NEXT: addiw a1, a0, -1 +; RV64I-NEXT: lui a1, 389120 +; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: blez a0, .LBB12_4 @@ -762,8 +762,8 @@ ; RV32I-NEXT: call __fixunssfdi@plt ; RV32I-NEXT: mv s1, a1 ; RV32I-NEXT: and s3, s2, a0 -; RV32I-NEXT: lui a0, 391168 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: lui s2, 391168 +; RV32I-NEXT: addi s2, s2, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s2 ; RV32I-NEXT: call __gtsf2@plt @@ -805,8 +805,8 @@ ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __fixunssfdi@plt ; RV64I-NEXT: and s1, s1, a0 -; RV64I-NEXT: lui a0, 391168 -; RV64I-NEXT: addiw a1, a0, -1 +; RV64I-NEXT: lui a1, 391168 +; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: sgtz a0, a0 @@ -1204,8 +1204,8 @@ ; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: blez a0, .LBB24_4 ; RV32I-NEXT: # %bb.3: # %start -; RV32I-NEXT: lui a0, 8 -; RV32I-NEXT: addi s1, a0, -1 +; RV32I-NEXT: lui s1, 8 +; RV32I-NEXT: addi s1, s1, -1 ; RV32I-NEXT: .LBB24_4: # %start ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s0 @@ -1246,8 +1246,8 @@ ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: blez a0, .LBB24_4 ; RV64I-NEXT: # %bb.3: # %start -; RV64I-NEXT: lui a0, 8 -; RV64I-NEXT: addiw s1, a0, -1 +; RV64I-NEXT: lui s1, 8 +; RV64I-NEXT: addiw s1, s1, -1 ; RV64I-NEXT: .LBB24_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 @@ -1710,8 +1710,8 @@ ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfsi@plt ; RV32I-NEXT: and s1, s1, a0 -; RV32I-NEXT: lui a0, 325632 -; RV32I-NEXT: addi a1, a0, -1 +; RV32I-NEXT: lui a1, 325632 +; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: sgtz a0, a0 @@ -1737,8 +1737,8 @@ ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __fixunssfdi@plt ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lui a0, 325632 -; RV64I-NEXT: addiw a1, a0, -1 +; RV64I-NEXT: lui a1, 325632 +; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: blez a0, .LBB31_2 @@ -1794,8 +1794,8 @@ ; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: lui s1, 524288 ; RV32I-NEXT: .LBB32_2: # %start -; RV32I-NEXT: lui a0, 323584 -; RV32I-NEXT: addi a1, a0, -1 +; RV32I-NEXT: lui a1, 323584 +; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: blez a0, .LBB32_4 @@ -1836,8 +1836,8 @@ ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: lui s1, 524288 ; RV64I-NEXT: .LBB32_2: # %start -; RV64I-NEXT: lui a0, 323584 -; RV64I-NEXT: addiw a1, a0, -1 +; RV64I-NEXT: lui a1, 323584 +; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: blez a0, .LBB32_4 diff --git a/llvm/test/CodeGen/RISCV/fold-vector-cmp.ll b/llvm/test/CodeGen/RISCV/fold-vector-cmp.ll --- a/llvm/test/CodeGen/RISCV/fold-vector-cmp.ll +++ b/llvm/test/CodeGen/RISCV/fold-vector-cmp.ll @@ -17,9 +17,9 @@ ; CHECK-V-NEXT: vmv.v.x v8, a1 ; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, tu, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 -; CHECK-V-NEXT: addiw a0, a1, 2 +; CHECK-V-NEXT: addiw a1, a1, 2 ; CHECK-V-NEXT: vsetvli zero, zero, e32, mf2, ta, ma -; CHECK-V-NEXT: vmslt.vx v0, v8, a0 +; CHECK-V-NEXT: vmslt.vx v0, v8, a1 ; CHECK-V-NEXT: vmv.v.i v8, 0 ; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll --- a/llvm/test/CodeGen/RISCV/forced-atomics.ll +++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll @@ -2957,8 +2957,8 @@ ; RV64-NO-ATOMIC-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: ld s2, 0(a0) -; RV64-NO-ATOMIC-NEXT: li a0, 1023 -; RV64-NO-ATOMIC-NEXT: slli s1, a0, 52 +; RV64-NO-ATOMIC-NEXT: li s1, 1023 +; RV64-NO-ATOMIC-NEXT: slli s1, s1, 52 ; RV64-NO-ATOMIC-NEXT: .LBB54_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: mv a0, s2 @@ -2991,8 +2991,8 @@ ; RV64-ATOMIC-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: mv s0, a0 ; RV64-ATOMIC-NEXT: ld a0, 0(a0) -; RV64-ATOMIC-NEXT: li a1, 1023 -; RV64-ATOMIC-NEXT: slli s1, a1, 52 +; RV64-ATOMIC-NEXT: li s1, 1023 +; RV64-ATOMIC-NEXT: slli s1, s1, 52 ; RV64-ATOMIC-NEXT: .LBB54_1: # %atomicrmw.start ; RV64-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-NEXT: mv s2, a0 @@ -3063,8 +3063,8 @@ ; RV64-NO-ATOMIC-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: ld s2, 0(a0) -; RV64-NO-ATOMIC-NEXT: li a0, -1025 -; RV64-NO-ATOMIC-NEXT: slli s1, a0, 52 +; RV64-NO-ATOMIC-NEXT: li s1, -1025 +; RV64-NO-ATOMIC-NEXT: slli s1, s1, 52 ; RV64-NO-ATOMIC-NEXT: .LBB55_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: mv a0, s2 @@ -3097,8 +3097,8 @@ ; RV64-ATOMIC-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: mv s0, a0 ; RV64-ATOMIC-NEXT: ld a0, 0(a0) -; RV64-ATOMIC-NEXT: li a1, -1025 -; RV64-ATOMIC-NEXT: slli s1, a1, 52 +; RV64-ATOMIC-NEXT: li s1, -1025 +; RV64-ATOMIC-NEXT: slli s1, s1, 52 ; RV64-ATOMIC-NEXT: .LBB55_1: # %atomicrmw.start ; RV64-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-NEXT: mv s2, a0 @@ -3169,8 +3169,8 @@ ; RV64-NO-ATOMIC-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: ld s2, 0(a0) -; RV64-NO-ATOMIC-NEXT: li a0, 1023 -; RV64-NO-ATOMIC-NEXT: slli s1, a0, 52 +; RV64-NO-ATOMIC-NEXT: li s1, 1023 +; RV64-NO-ATOMIC-NEXT: slli s1, s1, 52 ; RV64-NO-ATOMIC-NEXT: .LBB56_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: mv a0, s2 @@ -3203,8 +3203,8 @@ ; RV64-ATOMIC-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: mv s0, a0 ; RV64-ATOMIC-NEXT: ld a0, 0(a0) -; RV64-ATOMIC-NEXT: li a1, 1023 -; RV64-ATOMIC-NEXT: slli s1, a1, 52 +; RV64-ATOMIC-NEXT: li s1, 1023 +; RV64-ATOMIC-NEXT: slli s1, s1, 52 ; RV64-ATOMIC-NEXT: .LBB56_1: # %atomicrmw.start ; RV64-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-NEXT: mv s2, a0 @@ -3275,8 +3275,8 @@ ; RV64-NO-ATOMIC-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64-NO-ATOMIC-NEXT: mv s0, a0 ; RV64-NO-ATOMIC-NEXT: ld s2, 0(a0) -; RV64-NO-ATOMIC-NEXT: li a0, 1023 -; RV64-NO-ATOMIC-NEXT: slli s1, a0, 52 +; RV64-NO-ATOMIC-NEXT: li s1, 1023 +; RV64-NO-ATOMIC-NEXT: slli s1, s1, 52 ; RV64-NO-ATOMIC-NEXT: .LBB57_1: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: mv a0, s2 @@ -3309,8 +3309,8 @@ ; RV64-ATOMIC-NEXT: sd s2, 0(sp) # 8-byte Folded Spill ; RV64-ATOMIC-NEXT: mv s0, a0 ; RV64-ATOMIC-NEXT: ld a0, 0(a0) -; RV64-ATOMIC-NEXT: li a1, 1023 -; RV64-ATOMIC-NEXT: slli s1, a1, 52 +; RV64-ATOMIC-NEXT: li s1, 1023 +; RV64-ATOMIC-NEXT: slli s1, s1, 52 ; RV64-ATOMIC-NEXT: .LBB57_1: # %atomicrmw.start ; RV64-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-ATOMIC-NEXT: mv s2, a0 diff --git a/llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll b/llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll --- a/llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll +++ b/llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll @@ -831,8 +831,8 @@ ; CHECK-NOV-LABEL: stest_f64i16: ; CHECK-NOV: # %bb.0: # %entry ; CHECK-NOV-NEXT: fcvt.w.d a1, fa1, rtz -; CHECK-NOV-NEXT: lui a0, 8 -; CHECK-NOV-NEXT: addiw a2, a0, -1 +; CHECK-NOV-NEXT: lui a2, 8 +; CHECK-NOV-NEXT: addiw a2, a2, -1 ; CHECK-NOV-NEXT: fcvt.w.d a0, fa0, rtz ; CHECK-NOV-NEXT: bge a1, a2, .LBB9_5 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -884,8 +884,8 @@ ; CHECK-NOV-LABEL: utest_f64i16: ; CHECK-NOV: # %bb.0: # %entry ; CHECK-NOV-NEXT: fcvt.wu.d a0, fa0, rtz -; CHECK-NOV-NEXT: lui a1, 16 -; CHECK-NOV-NEXT: addiw a2, a1, -1 +; CHECK-NOV-NEXT: lui a2, 16 +; CHECK-NOV-NEXT: addiw a2, a2, -1 ; CHECK-NOV-NEXT: fcvt.wu.d a1, fa1, rtz ; CHECK-NOV-NEXT: bgeu a0, a2, .LBB10_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -921,8 +921,8 @@ ; CHECK-NOV-LABEL: ustest_f64i16: ; CHECK-NOV: # %bb.0: # %entry ; CHECK-NOV-NEXT: fcvt.w.d a0, fa0, rtz -; CHECK-NOV-NEXT: lui a1, 16 -; CHECK-NOV-NEXT: addiw a2, a1, -1 +; CHECK-NOV-NEXT: lui a2, 16 +; CHECK-NOV-NEXT: addiw a2, a2, -1 ; CHECK-NOV-NEXT: fcvt.w.d a1, fa1, rtz ; CHECK-NOV-NEXT: blt a0, a2, .LBB11_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -965,8 +965,8 @@ ; CHECK-NOV-LABEL: stest_f32i16: ; CHECK-NOV: # %bb.0: # %entry ; CHECK-NOV-NEXT: fcvt.w.s a1, fa3, rtz -; CHECK-NOV-NEXT: lui a2, 8 -; CHECK-NOV-NEXT: addiw a5, a2, -1 +; CHECK-NOV-NEXT: lui a5, 8 +; CHECK-NOV-NEXT: addiw a5, a5, -1 ; CHECK-NOV-NEXT: fcvt.w.s a2, fa2, rtz ; CHECK-NOV-NEXT: bge a1, a5, .LBB12_10 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -1046,8 +1046,8 @@ ; CHECK-NOV-LABEL: utest_f32i16: ; CHECK-NOV: # %bb.0: # %entry ; CHECK-NOV-NEXT: fcvt.wu.s a1, fa0, rtz -; CHECK-NOV-NEXT: lui a2, 16 -; CHECK-NOV-NEXT: addiw a3, a2, -1 +; CHECK-NOV-NEXT: lui a3, 16 +; CHECK-NOV-NEXT: addiw a3, a3, -1 ; CHECK-NOV-NEXT: fcvt.wu.s a2, fa1, rtz ; CHECK-NOV-NEXT: bgeu a1, a3, .LBB13_6 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -1101,8 +1101,8 @@ ; CHECK-NOV-LABEL: ustest_f32i16: ; CHECK-NOV: # %bb.0: # %entry ; CHECK-NOV-NEXT: fcvt.w.s a1, fa0, rtz -; CHECK-NOV-NEXT: lui a2, 16 -; CHECK-NOV-NEXT: addiw a4, a2, -1 +; CHECK-NOV-NEXT: lui a4, 16 +; CHECK-NOV-NEXT: addiw a4, a4, -1 ; CHECK-NOV-NEXT: fcvt.w.s a2, fa1, rtz ; CHECK-NOV-NEXT: bge a1, a4, .LBB14_6 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -1238,8 +1238,8 @@ ; CHECK-NOV-NEXT: mv a0, s1 ; CHECK-NOV-NEXT: call __extendhfsf2@plt ; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz -; CHECK-NOV-NEXT: lui a1, 8 -; CHECK-NOV-NEXT: addiw a7, a1, -1 +; CHECK-NOV-NEXT: lui a7, 8 +; CHECK-NOV-NEXT: addiw a7, a7, -1 ; CHECK-NOV-NEXT: bge a0, a7, .LBB15_18 ; CHECK-NOV-NEXT: # %bb.1: # %entry ; CHECK-NOV-NEXT: fcvt.l.s a1, fs5, rtz @@ -1828,8 +1828,8 @@ ; CHECK-NOV-NEXT: mv a0, s1 ; CHECK-NOV-NEXT: call __extendhfsf2@plt ; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz -; CHECK-NOV-NEXT: lui a1, 16 -; CHECK-NOV-NEXT: addiw a3, a1, -1 +; CHECK-NOV-NEXT: lui a3, 16 +; CHECK-NOV-NEXT: addiw a3, a3, -1 ; CHECK-NOV-NEXT: bge a0, a3, .LBB17_10 ; CHECK-NOV-NEXT: # %bb.1: # %entry ; CHECK-NOV-NEXT: fcvt.l.s a1, fs5, rtz @@ -4113,8 +4113,8 @@ ; CHECK-NOV-LABEL: stest_f64i16_mm: ; CHECK-NOV: # %bb.0: # %entry ; CHECK-NOV-NEXT: fcvt.w.d a1, fa1, rtz -; CHECK-NOV-NEXT: lui a0, 8 -; CHECK-NOV-NEXT: addiw a2, a0, -1 +; CHECK-NOV-NEXT: lui a2, 8 +; CHECK-NOV-NEXT: addiw a2, a2, -1 ; CHECK-NOV-NEXT: fcvt.w.d a0, fa0, rtz ; CHECK-NOV-NEXT: bge a1, a2, .LBB36_5 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -4164,8 +4164,8 @@ ; CHECK-NOV-LABEL: utest_f64i16_mm: ; CHECK-NOV: # %bb.0: # %entry ; CHECK-NOV-NEXT: fcvt.wu.d a0, fa0, rtz -; CHECK-NOV-NEXT: lui a1, 16 -; CHECK-NOV-NEXT: addiw a2, a1, -1 +; CHECK-NOV-NEXT: lui a2, 16 +; CHECK-NOV-NEXT: addiw a2, a2, -1 ; CHECK-NOV-NEXT: fcvt.wu.d a1, fa1, rtz ; CHECK-NOV-NEXT: bgeu a0, a2, .LBB37_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -4200,8 +4200,8 @@ ; CHECK-NOV-LABEL: ustest_f64i16_mm: ; CHECK-NOV: # %bb.0: # %entry ; CHECK-NOV-NEXT: fcvt.w.d a1, fa1, rtz -; CHECK-NOV-NEXT: lui a0, 16 -; CHECK-NOV-NEXT: addiw a2, a0, -1 +; CHECK-NOV-NEXT: lui a2, 16 +; CHECK-NOV-NEXT: addiw a2, a2, -1 ; CHECK-NOV-NEXT: fcvt.w.d a0, fa0, rtz ; CHECK-NOV-NEXT: blt a1, a2, .LBB38_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -4242,8 +4242,8 @@ ; CHECK-NOV-LABEL: stest_f32i16_mm: ; CHECK-NOV: # %bb.0: # %entry ; CHECK-NOV-NEXT: fcvt.w.s a1, fa3, rtz -; CHECK-NOV-NEXT: lui a2, 8 -; CHECK-NOV-NEXT: addiw a5, a2, -1 +; CHECK-NOV-NEXT: lui a5, 8 +; CHECK-NOV-NEXT: addiw a5, a5, -1 ; CHECK-NOV-NEXT: fcvt.w.s a2, fa2, rtz ; CHECK-NOV-NEXT: bge a1, a5, .LBB39_10 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -4321,8 +4321,8 @@ ; CHECK-NOV-LABEL: utest_f32i16_mm: ; CHECK-NOV: # %bb.0: # %entry ; CHECK-NOV-NEXT: fcvt.wu.s a1, fa0, rtz -; CHECK-NOV-NEXT: lui a2, 16 -; CHECK-NOV-NEXT: addiw a3, a2, -1 +; CHECK-NOV-NEXT: lui a3, 16 +; CHECK-NOV-NEXT: addiw a3, a3, -1 ; CHECK-NOV-NEXT: fcvt.wu.s a2, fa1, rtz ; CHECK-NOV-NEXT: bgeu a1, a3, .LBB40_6 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -4375,8 +4375,8 @@ ; CHECK-NOV-LABEL: ustest_f32i16_mm: ; CHECK-NOV: # %bb.0: # %entry ; CHECK-NOV-NEXT: fcvt.w.s a1, fa3, rtz -; CHECK-NOV-NEXT: lui a2, 16 -; CHECK-NOV-NEXT: addiw a4, a2, -1 +; CHECK-NOV-NEXT: lui a4, 16 +; CHECK-NOV-NEXT: addiw a4, a4, -1 ; CHECK-NOV-NEXT: fcvt.w.s a2, fa2, rtz ; CHECK-NOV-NEXT: bge a1, a4, .LBB41_6 ; CHECK-NOV-NEXT: # %bb.1: # %entry @@ -4510,8 +4510,8 @@ ; CHECK-NOV-NEXT: mv a0, s1 ; CHECK-NOV-NEXT: call __extendhfsf2@plt ; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz -; CHECK-NOV-NEXT: lui a1, 8 -; CHECK-NOV-NEXT: addiw a7, a1, -1 +; CHECK-NOV-NEXT: lui a7, 8 +; CHECK-NOV-NEXT: addiw a7, a7, -1 ; CHECK-NOV-NEXT: bge a0, a7, .LBB42_18 ; CHECK-NOV-NEXT: # %bb.1: # %entry ; CHECK-NOV-NEXT: fcvt.l.s a1, fs5, rtz @@ -4823,8 +4823,8 @@ ; CHECK-NOV-NEXT: call __extendhfsf2@plt ; CHECK-NOV-NEXT: fmv.s fs0, fa0 ; CHECK-NOV-NEXT: fcvt.lu.s s3, fs6, rtz -; CHECK-NOV-NEXT: fcvt.lu.s a0, fs5, rtz -; CHECK-NOV-NEXT: sext.w s2, a0 +; CHECK-NOV-NEXT: fcvt.lu.s s2, fs5, rtz +; CHECK-NOV-NEXT: sext.w s2, s2 ; CHECK-NOV-NEXT: mv a0, s1 ; CHECK-NOV-NEXT: call __extendhfsf2@plt ; CHECK-NOV-NEXT: fcvt.lu.s a0, fa0, rtz @@ -5095,8 +5095,8 @@ ; CHECK-NOV-NEXT: mv a0, s1 ; CHECK-NOV-NEXT: call __extendhfsf2@plt ; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz -; CHECK-NOV-NEXT: lui a1, 16 -; CHECK-NOV-NEXT: addiw a3, a1, -1 +; CHECK-NOV-NEXT: lui a3, 16 +; CHECK-NOV-NEXT: addiw a3, a3, -1 ; CHECK-NOV-NEXT: bge a0, a3, .LBB44_10 ; CHECK-NOV-NEXT: # %bb.1: # %entry ; CHECK-NOV-NEXT: fcvt.l.s a1, fs5, rtz @@ -5587,8 +5587,8 @@ ; CHECK-NOV-NEXT: snez a1, s1 ; CHECK-NOV-NEXT: addi a1, a1, -1 ; CHECK-NOV-NEXT: and a1, a1, s0 -; CHECK-NOV-NEXT: addi a2, s1, -1 -; CHECK-NOV-NEXT: seqz a2, a2 +; CHECK-NOV-NEXT: addi s1, s1, -1 +; CHECK-NOV-NEXT: seqz a2, s1 ; CHECK-NOV-NEXT: addi a2, a2, -1 ; CHECK-NOV-NEXT: and a1, a2, a1 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -5627,8 +5627,8 @@ ; CHECK-V-NEXT: snez a2, s1 ; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a2, a2, s0 -; CHECK-V-NEXT: addi a3, s1, -1 -; CHECK-V-NEXT: seqz a3, a3 +; CHECK-V-NEXT: addi s1, s1, -1 +; CHECK-V-NEXT: seqz a3, s1 ; CHECK-V-NEXT: addi a3, a3, -1 ; CHECK-V-NEXT: and a2, a3, a2 ; CHECK-V-NEXT: snez a3, a1 @@ -5694,14 +5694,14 @@ ; CHECK-NOV-NEXT: slti a3, a1, 1 ; CHECK-NOV-NEXT: neg a3, a3 ; CHECK-NOV-NEXT: and a3, a3, a0 -; CHECK-NOV-NEXT: addi a0, a1, -1 -; CHECK-NOV-NEXT: seqz a0, a0 -; CHECK-NOV-NEXT: addi a1, a0, -1 +; CHECK-NOV-NEXT: addi a1, a1, -1 +; CHECK-NOV-NEXT: seqz a1, a1 +; CHECK-NOV-NEXT: addi a1, a1, -1 ; CHECK-NOV-NEXT: slti a0, s1, 1 ; CHECK-NOV-NEXT: neg a0, a0 ; CHECK-NOV-NEXT: and a0, a0, s0 -; CHECK-NOV-NEXT: addi a5, s1, -1 -; CHECK-NOV-NEXT: seqz a5, a5 +; CHECK-NOV-NEXT: addi s1, s1, -1 +; CHECK-NOV-NEXT: seqz a5, s1 ; CHECK-NOV-NEXT: addi a5, a5, -1 ; CHECK-NOV-NEXT: and a0, a5, a0 ; CHECK-NOV-NEXT: beqz a4, .LBB47_6 @@ -6074,8 +6074,8 @@ ; CHECK-NOV-NEXT: snez a1, s1 ; CHECK-NOV-NEXT: addi a1, a1, -1 ; CHECK-NOV-NEXT: and a1, a1, s0 -; CHECK-NOV-NEXT: addi a2, s1, -1 -; CHECK-NOV-NEXT: seqz a2, a2 +; CHECK-NOV-NEXT: addi s1, s1, -1 +; CHECK-NOV-NEXT: seqz a2, s1 ; CHECK-NOV-NEXT: addi a2, a2, -1 ; CHECK-NOV-NEXT: and a1, a2, a1 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -6114,8 +6114,8 @@ ; CHECK-V-NEXT: snez a2, s1 ; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a2, a2, s0 -; CHECK-V-NEXT: addi a3, s1, -1 -; CHECK-V-NEXT: seqz a3, a3 +; CHECK-V-NEXT: addi s1, s1, -1 +; CHECK-V-NEXT: seqz a3, s1 ; CHECK-V-NEXT: addi a3, a3, -1 ; CHECK-V-NEXT: and a2, a3, a2 ; CHECK-V-NEXT: snez a3, a1 @@ -6181,14 +6181,14 @@ ; CHECK-NOV-NEXT: slti a3, a1, 1 ; CHECK-NOV-NEXT: neg a3, a3 ; CHECK-NOV-NEXT: and a3, a3, a0 -; CHECK-NOV-NEXT: addi a0, a1, -1 -; CHECK-NOV-NEXT: seqz a0, a0 -; CHECK-NOV-NEXT: addi a1, a0, -1 +; CHECK-NOV-NEXT: addi a1, a1, -1 +; CHECK-NOV-NEXT: seqz a1, a1 +; CHECK-NOV-NEXT: addi a1, a1, -1 ; CHECK-NOV-NEXT: slti a0, s1, 1 ; CHECK-NOV-NEXT: neg a0, a0 ; CHECK-NOV-NEXT: and a0, a0, s0 -; CHECK-NOV-NEXT: addi a5, s1, -1 -; CHECK-NOV-NEXT: seqz a5, a5 +; CHECK-NOV-NEXT: addi s1, s1, -1 +; CHECK-NOV-NEXT: seqz a5, s1 ; CHECK-NOV-NEXT: addi a5, a5, -1 ; CHECK-NOV-NEXT: and a0, a5, a0 ; CHECK-NOV-NEXT: beqz a4, .LBB50_6 @@ -6557,8 +6557,8 @@ ; CHECK-NOV-NEXT: snez a1, s2 ; CHECK-NOV-NEXT: addi a1, a1, -1 ; CHECK-NOV-NEXT: and a1, a1, s1 -; CHECK-NOV-NEXT: addi a2, s2, -1 -; CHECK-NOV-NEXT: seqz a2, a2 +; CHECK-NOV-NEXT: addi s2, s2, -1 +; CHECK-NOV-NEXT: seqz a2, s2 ; CHECK-NOV-NEXT: addi a2, a2, -1 ; CHECK-NOV-NEXT: and a1, a2, a1 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -6599,8 +6599,8 @@ ; CHECK-V-NEXT: snez a1, s2 ; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: and a1, a1, s1 -; CHECK-V-NEXT: addi a2, s2, -1 -; CHECK-V-NEXT: seqz a2, a2 +; CHECK-V-NEXT: addi s2, s2, -1 +; CHECK-V-NEXT: seqz a2, s2 ; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a1, a2, a1 ; CHECK-V-NEXT: sd a1, 8(sp) @@ -6659,14 +6659,14 @@ ; CHECK-NOV-NEXT: slti a3, a1, 1 ; CHECK-NOV-NEXT: neg a3, a3 ; CHECK-NOV-NEXT: and a3, a3, a0 -; CHECK-NOV-NEXT: addi a0, a1, -1 -; CHECK-NOV-NEXT: seqz a0, a0 -; CHECK-NOV-NEXT: addi a1, a0, -1 +; CHECK-NOV-NEXT: addi a1, a1, -1 +; CHECK-NOV-NEXT: seqz a1, a1 +; CHECK-NOV-NEXT: addi a1, a1, -1 ; CHECK-NOV-NEXT: slti a0, s1, 1 ; CHECK-NOV-NEXT: neg a0, a0 ; CHECK-NOV-NEXT: and a0, a0, s0 -; CHECK-NOV-NEXT: addi a5, s1, -1 -; CHECK-NOV-NEXT: seqz a5, a5 +; CHECK-NOV-NEXT: addi s1, s1, -1 +; CHECK-NOV-NEXT: seqz a5, s1 ; CHECK-NOV-NEXT: addi a5, a5, -1 ; CHECK-NOV-NEXT: and a0, a5, a0 ; CHECK-NOV-NEXT: beqz a4, .LBB53_6 @@ -6722,14 +6722,14 @@ ; CHECK-V-NEXT: slti a3, a1, 1 ; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: and a3, a3, a0 -; CHECK-V-NEXT: addi a0, a1, -1 -; CHECK-V-NEXT: seqz a0, a0 -; CHECK-V-NEXT: addi a1, a0, -1 +; CHECK-V-NEXT: addi a1, a1, -1 +; CHECK-V-NEXT: seqz a1, a1 +; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: slti a0, s1, 1 ; CHECK-V-NEXT: neg a0, a0 ; CHECK-V-NEXT: and a0, a0, s0 -; CHECK-V-NEXT: addi a5, s1, -1 -; CHECK-V-NEXT: seqz a5, a5 +; CHECK-V-NEXT: addi s1, s1, -1 +; CHECK-V-NEXT: seqz a5, s1 ; CHECK-V-NEXT: addi a5, a5, -1 ; CHECK-V-NEXT: and a0, a5, a0 ; CHECK-V-NEXT: beqz a4, .LBB53_6 diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll --- a/llvm/test/CodeGen/RISCV/half-arith.ll +++ b/llvm/test/CodeGen/RISCV/half-arith.ll @@ -438,8 +438,8 @@ ; RV32I-NEXT: call __truncsfhf2@plt ; RV32I-NEXT: lui a1, 1048568 ; RV32I-NEXT: and a0, a0, a1 -; RV32I-NEXT: slli a1, s1, 17 -; RV32I-NEXT: srli a1, a1, 17 +; RV32I-NEXT: slli s1, s1, 17 +; RV32I-NEXT: srli a1, s1, 17 ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload @@ -477,8 +477,8 @@ ; RV64I-NEXT: call __truncsfhf2@plt ; RV64I-NEXT: lui a1, 1048568 ; RV64I-NEXT: and a0, a0, a1 -; RV64I-NEXT: slli a1, s1, 49 -; RV64I-NEXT: srli a1, a1, 49 +; RV64I-NEXT: slli s1, s1, 49 +; RV64I-NEXT: srli a1, s1, 49 ; RV64I-NEXT: or a0, a1, a0 ; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload @@ -908,8 +908,8 @@ ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s0, a1 -; RV32I-NEXT: lui a1, 16 -; RV32I-NEXT: addi s3, a1, -1 +; RV32I-NEXT: lui s3, 16 +; RV32I-NEXT: addi s3, s3, -1 ; RV32I-NEXT: and a0, a0, s3 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: li a1, 0 @@ -966,8 +966,8 @@ ; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s1, a2 ; RV64I-NEXT: mv s0, a1 -; RV64I-NEXT: lui a1, 16 -; RV64I-NEXT: addiw s3, a1, -1 +; RV64I-NEXT: lui s3, 16 +; RV64I-NEXT: addiw s3, s3, -1 ; RV64I-NEXT: and a0, a0, s3 ; RV64I-NEXT: call __extendhfsf2@plt ; RV64I-NEXT: li a1, 0 @@ -1040,8 +1040,8 @@ ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s1, a2 ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: addi s3, a0, -1 +; RV32I-NEXT: lui s3, 16 +; RV32I-NEXT: addi s3, s3, -1 ; RV32I-NEXT: and a0, a1, s3 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: li a1, 0 @@ -1098,8 +1098,8 @@ ; RV64I-NEXT: sd s4, 0(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s1, a2 ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lui a0, 16 -; RV64I-NEXT: addiw s3, a0, -1 +; RV64I-NEXT: lui s3, 16 +; RV64I-NEXT: addiw s3, s3, -1 ; RV64I-NEXT: and a0, a1, s3 ; RV64I-NEXT: call __extendhfsf2@plt ; RV64I-NEXT: li a1, 0 @@ -1743,8 +1743,8 @@ ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s1, a1 -; RV32I-NEXT: lui a1, 16 -; RV32I-NEXT: addi s3, a1, -1 +; RV32I-NEXT: lui s3, 16 +; RV32I-NEXT: addi s3, s3, -1 ; RV32I-NEXT: and a0, a0, s3 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: li a1, 0 @@ -1804,8 +1804,8 @@ ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 -; RV64I-NEXT: lui a1, 16 -; RV64I-NEXT: addiw s3, a1, -1 +; RV64I-NEXT: lui s3, 16 +; RV64I-NEXT: addiw s3, s3, -1 ; RV64I-NEXT: and a0, a0, s3 ; RV64I-NEXT: call __extendhfsf2@plt ; RV64I-NEXT: li a1, 0 @@ -1882,8 +1882,8 @@ ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a2 ; RV32I-NEXT: mv s1, a1 -; RV32I-NEXT: lui a1, 16 -; RV32I-NEXT: addi s3, a1, -1 +; RV32I-NEXT: lui s3, 16 +; RV32I-NEXT: addi s3, s3, -1 ; RV32I-NEXT: and a0, a0, s3 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: li a1, 0 @@ -1933,8 +1933,8 @@ ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill ; RV64I-NEXT: mv s0, a2 ; RV64I-NEXT: mv s1, a1 -; RV64I-NEXT: lui a1, 16 -; RV64I-NEXT: addiw s3, a1, -1 +; RV64I-NEXT: lui s3, 16 +; RV64I-NEXT: addiw s3, s3, -1 ; RV64I-NEXT: and a0, a0, s3 ; RV64I-NEXT: call __extendhfsf2@plt ; RV64I-NEXT: li a1, 0 diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll --- a/llvm/test/CodeGen/RISCV/half-convert.ll +++ b/llvm/test/CodeGen/RISCV/half-convert.ll @@ -152,8 +152,8 @@ ; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: blez a0, .LBB1_4 ; RV32I-NEXT: # %bb.3: # %start -; RV32I-NEXT: lui a0, 8 -; RV32I-NEXT: addi s1, a0, -1 +; RV32I-NEXT: lui s1, 8 +; RV32I-NEXT: addi s1, s1, -1 ; RV32I-NEXT: .LBB1_4: # %start ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s0 @@ -195,8 +195,8 @@ ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: blez a0, .LBB1_4 ; RV64I-NEXT: # %bb.3: # %start -; RV64I-NEXT: lui a0, 8 -; RV64I-NEXT: addiw s1, a0, -1 +; RV64I-NEXT: lui s1, 8 +; RV64I-NEXT: addiw s1, s1, -1 ; RV64I-NEXT: .LBB1_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 @@ -317,8 +317,8 @@ ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: lui a1, 16 -; RV32I-NEXT: addi s0, a1, -1 +; RV32I-NEXT: lui s0, 16 +; RV32I-NEXT: addi s0, s0, -1 ; RV32I-NEXT: and a0, a0, s0 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: mv s3, a0 @@ -355,8 +355,8 @@ ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: lui a1, 16 -; RV64I-NEXT: addiw s0, a1, -1 +; RV64I-NEXT: lui s0, 16 +; RV64I-NEXT: addiw s0, s0, -1 ; RV64I-NEXT: and a0, a0, s0 ; RV64I-NEXT: call __extendhfsf2@plt ; RV64I-NEXT: mv s3, a0 @@ -484,8 +484,8 @@ ; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: lui s1, 524288 ; RV32I-NEXT: .LBB5_2: # %start -; RV32I-NEXT: lui a0, 323584 -; RV32I-NEXT: addi a1, a0, -1 +; RV32I-NEXT: lui a1, 323584 +; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: blez a0, .LBB5_4 @@ -529,8 +529,8 @@ ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: lui s1, 524288 ; RV64I-NEXT: .LBB5_2: # %start -; RV64I-NEXT: lui a0, 323584 -; RV64I-NEXT: addiw a1, a0, -1 +; RV64I-NEXT: lui a1, 323584 +; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: blez a0, .LBB5_4 @@ -718,9 +718,8 @@ ; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lui a0, 325632 -; RV32I-NEXT: addi a1, a0, -1 -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: lui a1, 325632 +; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: neg s1, a0 @@ -757,8 +756,8 @@ ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __fixunssfdi@plt ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lui a0, 325632 -; RV64I-NEXT: addiw a1, a0, -1 +; RV64I-NEXT: lui a1, 325632 +; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: blez a0, .LBB8_2 @@ -961,8 +960,8 @@ ; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: lui s2, 524288 ; RV32I-NEXT: .LBB10_2: # %start -; RV32I-NEXT: lui a0, 389120 -; RV32I-NEXT: addi s3, a0, -1 +; RV32I-NEXT: lui s3, 389120 +; RV32I-NEXT: addi s3, s3, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s3 ; RV32I-NEXT: call __gtsf2@plt @@ -1027,8 +1026,8 @@ ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: slli s1, s3, 63 ; RV64I-NEXT: .LBB10_2: # %start -; RV64I-NEXT: lui a0, 389120 -; RV64I-NEXT: addiw a1, a0, -1 +; RV64I-NEXT: lui a1, 389120 +; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: blez a0, .LBB10_4 @@ -1192,9 +1191,8 @@ ; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lui a0, 391168 -; RV32I-NEXT: addi s1, a0, -1 -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: lui s1, 391168 +; RV32I-NEXT: addi s1, s1, -1 ; RV32I-NEXT: mv a1, s1 ; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: sgtz a0, a0 @@ -1242,9 +1240,8 @@ ; RV64I-NEXT: srli a0, a0, 48 ; RV64I-NEXT: call __extendhfsf2@plt ; RV64I-NEXT: mv s0, a0 -; RV64I-NEXT: lui a0, 391168 -; RV64I-NEXT: addiw a1, a0, -1 -; RV64I-NEXT: mv a0, s0 +; RV64I-NEXT: lui a1, 391168 +; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: sgtz a0, a0 ; RV64I-NEXT: neg s1, a0 @@ -2267,8 +2264,8 @@ ; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: blez a0, .LBB32_4 ; RV32I-NEXT: # %bb.3: # %start -; RV32I-NEXT: lui a0, 8 -; RV32I-NEXT: addi s1, a0, -1 +; RV32I-NEXT: lui s1, 8 +; RV32I-NEXT: addi s1, s1, -1 ; RV32I-NEXT: .LBB32_4: # %start ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: mv a1, s0 @@ -2312,8 +2309,8 @@ ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: blez a0, .LBB32_4 ; RV64I-NEXT: # %bb.3: # %start -; RV64I-NEXT: lui a0, 8 -; RV64I-NEXT: addiw s1, a0, -1 +; RV64I-NEXT: lui s1, 8 +; RV64I-NEXT: addiw s1, s1, -1 ; RV64I-NEXT: .LBB32_4: # %start ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: mv a1, s0 @@ -2435,8 +2432,8 @@ ; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: lui a1, 16 -; RV32I-NEXT: addi s3, a1, -1 +; RV32I-NEXT: lui s3, 16 +; RV32I-NEXT: addi s3, s3, -1 ; RV32I-NEXT: and a0, a0, s3 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: mv s2, a0 @@ -2476,8 +2473,8 @@ ; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: lui a1, 16 -; RV64I-NEXT: addiw s3, a1, -1 +; RV64I-NEXT: lui s3, 16 +; RV64I-NEXT: addiw s3, s3, -1 ; RV64I-NEXT: and a0, a0, s3 ; RV64I-NEXT: call __extendhfsf2@plt ; RV64I-NEXT: mv s2, a0 @@ -2941,9 +2938,8 @@ ; RV32I-NEXT: srli a0, a0, 16 ; RV32I-NEXT: call __extendhfsf2@plt ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lui a0, 325632 -; RV32I-NEXT: addi a1, a0, -1 -; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: lui a1, 325632 +; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: sgtz a0, a0 ; RV32I-NEXT: neg s1, a0 @@ -2980,8 +2976,8 @@ ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __fixunssfdi@plt ; RV64I-NEXT: mv s1, a0 -; RV64I-NEXT: lui a0, 325632 -; RV64I-NEXT: addiw a1, a0, -1 +; RV64I-NEXT: lui a1, 325632 +; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s2 ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: blez a0, .LBB39_2 @@ -3058,8 +3054,8 @@ ; RV32I-NEXT: # %bb.1: # %start ; RV32I-NEXT: lui s1, 524288 ; RV32I-NEXT: .LBB40_2: # %start -; RV32I-NEXT: lui a0, 323584 -; RV32I-NEXT: addi a1, a0, -1 +; RV32I-NEXT: lui a1, 323584 +; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __gtsf2@plt ; RV32I-NEXT: blez a0, .LBB40_4 @@ -3103,8 +3099,8 @@ ; RV64I-NEXT: # %bb.1: # %start ; RV64I-NEXT: lui s1, 524288 ; RV64I-NEXT: .LBB40_2: # %start -; RV64I-NEXT: lui a0, 323584 -; RV64I-NEXT: addiw a1, a0, -1 +; RV64I-NEXT: lui a1, 323584 +; RV64I-NEXT: addiw a1, a1, -1 ; RV64I-NEXT: mv a0, s0 ; RV64I-NEXT: call __gtsf2@plt ; RV64I-NEXT: blez a0, .LBB40_4 diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll --- a/llvm/test/CodeGen/RISCV/imm.ll +++ b/llvm/test/CodeGen/RISCV/imm.ll @@ -733,8 +733,8 @@ define i64 @imm_left_shifted_lui_3() nounwind { ; RV32I-LABEL: imm_left_shifted_lui_3: ; RV32I: # %bb.0: -; RV32I-NEXT: lui a0, 1 -; RV32I-NEXT: addi a1, a0, 1 +; RV32I-NEXT: lui a1, 1 +; RV32I-NEXT: addi a1, a1, 1 ; RV32I-NEXT: li a0, 0 ; RV32I-NEXT: ret ; @@ -2316,8 +2316,8 @@ define i64 @li_rori_2() { ; RV32I-LABEL: li_rori_2: ; RV32I: # %bb.0: -; RV32I-NEXT: lui a0, 720896 -; RV32I-NEXT: addi a1, a0, -1 +; RV32I-NEXT: lui a1, 720896 +; RV32I-NEXT: addi a1, a1, -1 ; RV32I-NEXT: li a0, -6 ; RV32I-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll --- a/llvm/test/CodeGen/RISCV/mul.ll +++ b/llvm/test/CodeGen/RISCV/mul.ll @@ -1412,8 +1412,8 @@ ; RV32I-NEXT: mv a2, s2 ; RV32I-NEXT: li a3, 0 ; RV32I-NEXT: call __muldi3@plt -; RV32I-NEXT: add a2, a0, s5 -; RV32I-NEXT: sltu a0, a2, a0 +; RV32I-NEXT: add s5, a0, s5 +; RV32I-NEXT: sltu a0, s5, a0 ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: add s8, s7, a0 ; RV32I-NEXT: mv a0, s0 @@ -1436,18 +1436,18 @@ ; RV32I-NEXT: mv a2, s1 ; RV32I-NEXT: mv a3, s0 ; RV32I-NEXT: call __muldi3@plt -; RV32I-NEXT: add a3, a0, s2 -; RV32I-NEXT: add a2, s9, a3 -; RV32I-NEXT: sltu a4, a2, s9 -; RV32I-NEXT: sltu a5, s9, s5 -; RV32I-NEXT: sltu a6, s8, s7 -; RV32I-NEXT: add a6, s6, a6 -; RV32I-NEXT: add a5, a6, a5 +; RV32I-NEXT: add s2, a0, s2 +; RV32I-NEXT: add a2, s9, s2 +; RV32I-NEXT: sltu a3, a2, s9 +; RV32I-NEXT: sltu a4, s9, s5 +; RV32I-NEXT: sltu a5, s8, s7 +; RV32I-NEXT: add a5, s6, a5 +; RV32I-NEXT: add a4, a5, a4 ; RV32I-NEXT: add a1, a1, s3 -; RV32I-NEXT: sltu a0, a3, a0 +; RV32I-NEXT: sltu a0, s2, a0 ; RV32I-NEXT: add a0, a1, a0 -; RV32I-NEXT: add a0, a5, a0 -; RV32I-NEXT: add a1, a0, a4 +; RV32I-NEXT: add a0, a4, a0 +; RV32I-NEXT: add a1, a0, a3 ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/narrow-shl-cst.ll b/llvm/test/CodeGen/RISCV/narrow-shl-cst.ll --- a/llvm/test/CodeGen/RISCV/narrow-shl-cst.ll +++ b/llvm/test/CodeGen/RISCV/narrow-shl-cst.ll @@ -39,8 +39,8 @@ define i64 @test3(i64 %x) nounwind { ; RV32-LABEL: test3: ; RV32: # %bb.0: -; RV32-NEXT: andi a0, a0, 241 -; RV32-NEXT: slli a1, a0, 8 +; RV32-NEXT: andi a1, a0, 241 +; RV32-NEXT: slli a1, a1, 8 ; RV32-NEXT: li a0, 0 ; RV32-NEXT: ret ; @@ -57,8 +57,8 @@ define i64 @test4(i64 %x) nounwind { ; RV32-LABEL: test4: ; RV32: # %bb.0: -; RV32-NEXT: ori a0, a0, 241 -; RV32-NEXT: slli a1, a0, 8 +; RV32-NEXT: ori a1, a0, 241 +; RV32-NEXT: slli a1, a1, 8 ; RV32-NEXT: li a0, 0 ; RV32-NEXT: ret ; @@ -75,8 +75,8 @@ define i64 @test5(i64 %x) nounwind { ; RV32-LABEL: test5: ; RV32: # %bb.0: -; RV32-NEXT: ori a0, a0, 31 -; RV32-NEXT: slli a1, a0, 8 +; RV32-NEXT: ori a1, a0, 31 +; RV32-NEXT: slli a1, a1, 8 ; RV32-NEXT: li a0, 0 ; RV32-NEXT: ret ; @@ -93,8 +93,8 @@ define i64 @test6(i64 %x) nounwind { ; RV32-LABEL: test6: ; RV32: # %bb.0: -; RV32-NEXT: xori a0, a0, 241 -; RV32-NEXT: slli a1, a0, 8 +; RV32-NEXT: xori a1, a0, 241 +; RV32-NEXT: slli a1, a1, 8 ; RV32-NEXT: li a0, 0 ; RV32-NEXT: ret ; @@ -111,8 +111,8 @@ define i64 @test7(i64 %x) nounwind { ; RV32-LABEL: test7: ; RV32: # %bb.0: -; RV32-NEXT: xori a0, a0, 31 -; RV32-NEXT: slli a1, a0, 8 +; RV32-NEXT: xori a1, a0, 31 +; RV32-NEXT: slli a1, a1, 8 ; RV32-NEXT: li a0, 0 ; RV32-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll b/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll --- a/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll +++ b/llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll @@ -64,16 +64,16 @@ ; CHECK-NEXT: lw a6, 0(a4) ; CHECK-NEXT: addiw a5, a5, 4 ; CHECK-NEXT: sw a5, -4(a4) -; CHECK-NEXT: addiw a5, a6, 4 -; CHECK-NEXT: sw a5, 0(a4) +; CHECK-NEXT: addiw a6, a6, 4 +; CHECK-NEXT: sw a6, 0(a4) ; CHECK-NEXT: addi a3, a3, 2 ; CHECK-NEXT: addi a4, a4, 8 ; CHECK-NEXT: bne a1, a3, .LBB1_4 ; CHECK-NEXT: .LBB1_5: # %for.cond.cleanup.loopexit.unr-lcssa ; CHECK-NEXT: beqz a2, .LBB1_7 ; CHECK-NEXT: # %bb.6: # %for.body.epil -; CHECK-NEXT: slli a1, a3, 2 -; CHECK-NEXT: add a0, a0, a1 +; CHECK-NEXT: slli a3, a3, 2 +; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: lw a1, 0(a0) ; CHECK-NEXT: addiw a1, a1, 4 ; CHECK-NEXT: sw a1, 0(a0) diff --git a/llvm/test/CodeGen/RISCV/rotl-rotr.ll b/llvm/test/CodeGen/RISCV/rotl-rotr.ll --- a/llvm/test/CodeGen/RISCV/rotl-rotr.ll +++ b/llvm/test/CodeGen/RISCV/rotl-rotr.ll @@ -1076,8 +1076,8 @@ ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: sltu a1, a0, a1 -; RV32I-NEXT: add a2, a5, a3 -; RV32I-NEXT: add a1, a2, a1 +; RV32I-NEXT: add a3, a5, a3 +; RV32I-NEXT: add a1, a3, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: rotl_64_mask_shared: @@ -1131,8 +1131,8 @@ ; RV32ZBB-NEXT: and a0, a0, a2 ; RV32ZBB-NEXT: add a0, a1, a0 ; RV32ZBB-NEXT: sltu a1, a0, a1 -; RV32ZBB-NEXT: add a2, a5, a3 -; RV32ZBB-NEXT: add a1, a2, a1 +; RV32ZBB-NEXT: add a3, a5, a3 +; RV32ZBB-NEXT: add a1, a3, a1 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: rotl_64_mask_shared: @@ -1211,8 +1211,8 @@ ; RV32I-NEXT: sll a1, a1, a7 ; RV32I-NEXT: or a1, a1, t0 ; RV32I-NEXT: srl t0, a0, a4 -; RV32I-NEXT: slli a0, a6, 1 -; RV32I-NEXT: sll a6, a0, a7 +; RV32I-NEXT: slli a6, a6, 1 +; RV32I-NEXT: sll a6, a6, a7 ; RV32I-NEXT: addi a0, a5, -32 ; RV32I-NEXT: or a6, a6, t0 ; RV32I-NEXT: bltz a0, .LBB19_6 @@ -1265,8 +1265,8 @@ ; RV32ZBB-NEXT: sll a1, a1, a7 ; RV32ZBB-NEXT: or a1, a1, t0 ; RV32ZBB-NEXT: srl t0, a0, a4 -; RV32ZBB-NEXT: slli a0, a6, 1 -; RV32ZBB-NEXT: sll a6, a0, a7 +; RV32ZBB-NEXT: slli a6, a6, 1 +; RV32ZBB-NEXT: sll a6, a6, a7 ; RV32ZBB-NEXT: addi a0, a5, -32 ; RV32ZBB-NEXT: or a6, a6, t0 ; RV32ZBB-NEXT: bltz a0, .LBB19_6 @@ -1528,8 +1528,8 @@ ; RV32I-NEXT: not a0, a4 ; RV32I-NEXT: sll t0, t0, a0 ; RV32I-NEXT: srl t1, a1, a4 -; RV32I-NEXT: slli a1, a6, 1 -; RV32I-NEXT: sll t2, a1, a0 +; RV32I-NEXT: slli a6, a6, 1 +; RV32I-NEXT: sll t2, a6, a0 ; RV32I-NEXT: mv a6, a2 ; RV32I-NEXT: beqz a5, .LBB23_6 ; RV32I-NEXT: # %bb.5: @@ -1546,13 +1546,13 @@ ; RV32I-NEXT: sll a2, a2, a0 ; RV32I-NEXT: or a2, a2, t0 ; RV32I-NEXT: srl a3, a3, a4 -; RV32I-NEXT: slli a4, a6, 1 -; RV32I-NEXT: sll a0, a4, a0 +; RV32I-NEXT: slli a6, a6, 1 +; RV32I-NEXT: sll a0, a6, a0 ; RV32I-NEXT: or a0, a0, a3 -; RV32I-NEXT: add a3, a7, a0 +; RV32I-NEXT: add a7, a7, a0 ; RV32I-NEXT: add a0, a1, a2 ; RV32I-NEXT: sltu a1, a0, a1 -; RV32I-NEXT: add a1, a3, a1 +; RV32I-NEXT: add a1, a7, a1 ; RV32I-NEXT: ret ; ; RV64I-LABEL: rotr_64_mask_multiple: @@ -1584,8 +1584,8 @@ ; RV32ZBB-NEXT: not a0, a4 ; RV32ZBB-NEXT: sll t0, t0, a0 ; RV32ZBB-NEXT: srl t1, a1, a4 -; RV32ZBB-NEXT: slli a1, a6, 1 -; RV32ZBB-NEXT: sll t2, a1, a0 +; RV32ZBB-NEXT: slli a6, a6, 1 +; RV32ZBB-NEXT: sll t2, a6, a0 ; RV32ZBB-NEXT: mv a6, a2 ; RV32ZBB-NEXT: beqz a5, .LBB23_6 ; RV32ZBB-NEXT: # %bb.5: @@ -1602,13 +1602,13 @@ ; RV32ZBB-NEXT: sll a2, a2, a0 ; RV32ZBB-NEXT: or a2, a2, t0 ; RV32ZBB-NEXT: srl a3, a3, a4 -; RV32ZBB-NEXT: slli a4, a6, 1 -; RV32ZBB-NEXT: sll a0, a4, a0 +; RV32ZBB-NEXT: slli a6, a6, 1 +; RV32ZBB-NEXT: sll a0, a6, a0 ; RV32ZBB-NEXT: or a0, a0, a3 -; RV32ZBB-NEXT: add a3, a7, a0 +; RV32ZBB-NEXT: add a7, a7, a0 ; RV32ZBB-NEXT: add a0, a1, a2 ; RV32ZBB-NEXT: sltu a1, a0, a1 -; RV32ZBB-NEXT: add a1, a3, a1 +; RV32ZBB-NEXT: add a1, a7, a1 ; RV32ZBB-NEXT: ret ; ; RV64ZBB-LABEL: rotr_64_mask_multiple: diff --git a/llvm/test/CodeGen/RISCV/rv32zba.ll b/llvm/test/CodeGen/RISCV/rv32zba.ll --- a/llvm/test/CodeGen/RISCV/rv32zba.ll +++ b/llvm/test/CodeGen/RISCV/rv32zba.ll @@ -44,9 +44,9 @@ ; RV32I-LABEL: sh3add: ; RV32I: # %bb.0: ; RV32I-NEXT: slli a0, a0, 3 -; RV32I-NEXT: add a1, a2, a0 -; RV32I-NEXT: lw a0, 0(a1) -; RV32I-NEXT: lw a1, 4(a1) +; RV32I-NEXT: add a2, a2, a0 +; RV32I-NEXT: lw a0, 0(a2) +; RV32I-NEXT: lw a1, 4(a2) ; RV32I-NEXT: ret ; ; RV32ZBA-LABEL: sh3add: diff --git a/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll --- a/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbb-zbkb.ll @@ -207,8 +207,8 @@ ; CHECK-NEXT: sll a0, a0, a5 ; CHECK-NEXT: or a0, a0, a4 ; CHECK-NEXT: srl a1, a1, a2 -; CHECK-NEXT: slli a2, a3, 1 -; CHECK-NEXT: sll a2, a2, a5 +; CHECK-NEXT: slli a3, a3, 1 +; CHECK-NEXT: sll a2, a3, a5 ; CHECK-NEXT: or a1, a2, a1 ; CHECK-NEXT: ret %or = tail call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b) @@ -305,8 +305,8 @@ ; CHECK-NEXT: neg a4, a3 ; CHECK-NEXT: and a2, a4, a2 ; CHECK-NEXT: sll a0, a1, a0 -; CHECK-NEXT: addi a1, a3, -1 -; CHECK-NEXT: and a1, a1, a0 +; CHECK-NEXT: addi a3, a3, -1 +; CHECK-NEXT: and a1, a3, a0 ; CHECK-NEXT: not a0, a2 ; CHECK-NEXT: not a1, a1 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rv32zbkb.ll b/llvm/test/CodeGen/RISCV/rv32zbkb.ll --- a/llvm/test/CodeGen/RISCV/rv32zbkb.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbkb.ll @@ -149,8 +149,8 @@ ; RV32I-LABEL: packh_i64: ; RV32I: # %bb.0: ; RV32I-NEXT: andi a0, a0, 255 -; RV32I-NEXT: slli a1, a2, 24 -; RV32I-NEXT: srli a1, a1, 16 +; RV32I-NEXT: slli a2, a2, 24 +; RV32I-NEXT: srli a1, a2, 16 ; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rv32zbs.ll b/llvm/test/CodeGen/RISCV/rv32zbs.ll --- a/llvm/test/CodeGen/RISCV/rv32zbs.ll +++ b/llvm/test/CodeGen/RISCV/rv32zbs.ll @@ -54,8 +54,8 @@ ; RV32I-NEXT: neg a6, a5 ; RV32I-NEXT: and a4, a6, a4 ; RV32I-NEXT: sll a2, a3, a2 -; RV32I-NEXT: addi a3, a5, -1 -; RV32I-NEXT: and a2, a3, a2 +; RV32I-NEXT: addi a5, a5, -1 +; RV32I-NEXT: and a2, a5, a2 ; RV32I-NEXT: not a3, a4 ; RV32I-NEXT: not a2, a2 ; RV32I-NEXT: and a0, a3, a0 @@ -176,8 +176,8 @@ ; RV32I-NEXT: neg a0, a4 ; RV32I-NEXT: and a0, a0, a2 ; RV32I-NEXT: sll a1, a1, a3 -; RV32I-NEXT: addi a2, a4, -1 -; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: addi a4, a4, -1 +; RV32I-NEXT: and a1, a4, a1 ; RV32I-NEXT: ret ; ; RV32ZBS-LABEL: bset_i64_zero: diff --git a/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll b/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll --- a/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll +++ b/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll @@ -21,8 +21,8 @@ ; CHECK-NEXT: mv a1, s1 ; CHECK-NEXT: call __addsf3@plt ; CHECK-NEXT: slli a0, a0, 32 -; CHECK-NEXT: slli a1, s2, 32 -; CHECK-NEXT: srli a1, a1, 32 +; CHECK-NEXT: slli s2, s2, 32 +; CHECK-NEXT: srli a1, s2, 32 ; CHECK-NEXT: or a0, a0, a1 ; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rv64zbkb.ll b/llvm/test/CodeGen/RISCV/rv64zbkb.ll --- a/llvm/test/CodeGen/RISCV/rv64zbkb.ll +++ b/llvm/test/CodeGen/RISCV/rv64zbkb.ll @@ -252,8 +252,8 @@ ; RV64I: # %bb.0: ; RV64I-NEXT: addw a0, a1, a0 ; RV64I-NEXT: slli a0, a0, 32 -; RV64I-NEXT: slli a1, a2, 32 -; RV64I-NEXT: srli a1, a1, 32 +; RV64I-NEXT: slli a2, a2, 32 +; RV64I-NEXT: srli a1, a2, 32 ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll b/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll --- a/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll @@ -82,10 +82,10 @@ ; CHECK-NEXT: vl8re32.v v24, (a1) ; CHECK-NEXT: vl8re32.v v0, (a5) ; CHECK-NEXT: vs8r.v v16, (a0) -; CHECK-NEXT: add a1, a0, a2 -; CHECK-NEXT: vs8r.v v24, (a1) -; CHECK-NEXT: add a1, a0, a4 -; CHECK-NEXT: vs8r.v v0, (a1) +; CHECK-NEXT: add a2, a0, a2 +; CHECK-NEXT: vs8r.v v24, (a2) +; CHECK-NEXT: add a4, a0, a4 +; CHECK-NEXT: vs8r.v v0, (a4) ; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: ret @@ -148,30 +148,30 @@ ; CHECK-NEXT: vl8re32.v v16, (t3) ; CHECK-NEXT: vl8re32.v v24, (t2) ; CHECK-NEXT: vs8r.v v8, (a0) -; CHECK-NEXT: add a1, a0, a2 -; CHECK-NEXT: vs8r.v v16, (a1) -; CHECK-NEXT: add a1, a0, t1 -; CHECK-NEXT: vs8r.v v24, (a1) -; CHECK-NEXT: add a1, a0, a7 -; CHECK-NEXT: vs8r.v v0, (a1) -; CHECK-NEXT: add a1, a0, a6 -; CHECK-NEXT: addi a2, sp, 16 -; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload -; CHECK-NEXT: vs8r.v v8, (a1) -; CHECK-NEXT: add a1, a0, a5 -; CHECK-NEXT: csrr a2, vlenb -; CHECK-NEXT: slli a2, a2, 3 -; CHECK-NEXT: add a2, sp, a2 -; CHECK-NEXT: addi a2, a2, 16 -; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload -; CHECK-NEXT: vs8r.v v8, (a1) -; CHECK-NEXT: add a1, a0, a4 -; CHECK-NEXT: csrr a2, vlenb -; CHECK-NEXT: slli a2, a2, 4 -; CHECK-NEXT: add a2, sp, a2 -; CHECK-NEXT: addi a2, a2, 16 -; CHECK-NEXT: vl8re8.v v8, (a2) # Unknown-size Folded Reload -; CHECK-NEXT: vs8r.v v8, (a1) +; CHECK-NEXT: add a2, a0, a2 +; CHECK-NEXT: vs8r.v v16, (a2) +; CHECK-NEXT: add t1, a0, t1 +; CHECK-NEXT: vs8r.v v24, (t1) +; CHECK-NEXT: add a7, a0, a7 +; CHECK-NEXT: vs8r.v v0, (a7) +; CHECK-NEXT: add a6, a0, a6 +; CHECK-NEXT: addi a1, sp, 16 +; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload +; CHECK-NEXT: vs8r.v v8, (a6) +; CHECK-NEXT: add a5, a0, a5 +; CHECK-NEXT: csrr a1, vlenb +; CHECK-NEXT: slli a1, a1, 3 +; CHECK-NEXT: add a1, sp, a1 +; CHECK-NEXT: addi a1, a1, 16 +; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload +; CHECK-NEXT: vs8r.v v8, (a5) +; CHECK-NEXT: add a4, a0, a4 +; CHECK-NEXT: csrr a1, vlenb +; CHECK-NEXT: slli a1, a1, 4 +; CHECK-NEXT: add a1, sp, a1 +; CHECK-NEXT: addi a1, a1, 16 +; CHECK-NEXT: vl8re8.v v8, (a1) # Unknown-size Folded Reload +; CHECK-NEXT: vs8r.v v8, (a4) ; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: li a2, 24 diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll @@ -648,8 +648,8 @@ ; RV64-NEXT: # %bb.1: ; RV64-NEXT: mv a2, a1 ; RV64-NEXT: .LBB52_2: -; RV64-NEXT: slli a1, a2, 3 -; RV64-NEXT: add a0, a0, a1 +; RV64-NEXT: slli a2, a2, 3 +; RV64-NEXT: add a0, a0, a2 ; RV64-NEXT: fld fa0, 0(a0) ; RV64-NEXT: addi sp, s0, -80 ; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll @@ -151,18 +151,18 @@ ; RV32-NEXT: add a4, a0, a2 ; RV32-NEXT: vl8r.v v16, (a4) ; RV32-NEXT: vl8r.v v24, (a0) -; RV32-NEXT: add a0, a3, a1 -; RV32-NEXT: vsetvli a1, zero, e8, m8, ta, ma +; RV32-NEXT: add a1, a3, a1 +; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV32-NEXT: vmseq.vi v8, v16, 0 ; RV32-NEXT: vmseq.vi v0, v24, 0 ; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmerge.vim v24, v16, 1, v0 ; RV32-NEXT: vs8r.v v24, (a3) -; RV32-NEXT: add a1, a3, a2 +; RV32-NEXT: add a2, a3, a2 ; RV32-NEXT: vmv1r.v v0, v8 ; RV32-NEXT: vmerge.vim v8, v16, 1, v0 -; RV32-NEXT: vs8r.v v8, (a1) -; RV32-NEXT: lb a0, 0(a0) +; RV32-NEXT: vs8r.v v8, (a2) +; RV32-NEXT: lb a0, 0(a1) ; RV32-NEXT: addi sp, s0, -80 ; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload @@ -191,18 +191,18 @@ ; RV64-NEXT: add a4, a0, a2 ; RV64-NEXT: vl8r.v v16, (a4) ; RV64-NEXT: vl8r.v v24, (a0) -; RV64-NEXT: add a0, a3, a1 -; RV64-NEXT: vsetvli a1, zero, e8, m8, ta, ma +; RV64-NEXT: add a1, a3, a1 +; RV64-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV64-NEXT: vmseq.vi v8, v16, 0 ; RV64-NEXT: vmseq.vi v0, v24, 0 ; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vmerge.vim v24, v16, 1, v0 ; RV64-NEXT: vs8r.v v24, (a3) -; RV64-NEXT: add a1, a3, a2 +; RV64-NEXT: add a2, a3, a2 ; RV64-NEXT: vmv1r.v v0, v8 ; RV64-NEXT: vmerge.vim v8, v16, 1, v0 -; RV64-NEXT: vs8r.v v8, (a1) -; RV64-NEXT: lb a0, 0(a0) +; RV64-NEXT: vs8r.v v8, (a2) +; RV64-NEXT: lb a0, 0(a1) ; RV64-NEXT: addi sp, s0, -80 ; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll @@ -830,8 +830,8 @@ ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: .LBB72_2: -; CHECK-NEXT: slli a1, a2, 3 -; CHECK-NEXT: add a0, a0, a1 +; CHECK-NEXT: slli a2, a2, 3 +; CHECK-NEXT: add a0, a0, a2 ; CHECK-NEXT: ld a0, 0(a0) ; CHECK-NEXT: addi sp, s0, -80 ; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll @@ -178,60 +178,104 @@ define void @gather_zero_stride(i8* noalias nocapture %A, i8* noalias nocapture readonly %B) { ; -; V-LABEL: gather_zero_stride: +; CHECK-LABEL: gather_zero_stride: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: li a2, 0 +; CHECK-NEXT: li a3, 32 +; CHECK-NEXT: li a4, 1024 +; CHECK-NEXT: .LBB3_1: # %vector.body +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: lbu a5, 0(a1) +; CHECK-NEXT: add a6, a0, a2 +; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, ma +; CHECK-NEXT: vle8.v v8, (a6) +; CHECK-NEXT: vadd.vx v8, v8, a5 +; CHECK-NEXT: vse8.v v8, (a6) +; CHECK-NEXT: addi a2, a2, 32 +; CHECK-NEXT: addi a1, a1, 160 +; CHECK-NEXT: bne a2, a4, .LBB3_1 +; CHECK-NEXT: # %bb.2: # %for.cond.cleanup +; CHECK-NEXT: ret +entry: + br label %vector.body + +vector.body: ; preds = %vector.body, %entry + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %vec.ind = phi <32 x i64> [ zeroinitializer, %entry ], [ %vec.ind.next, %vector.body ] + %0 = mul nuw nsw <32 x i64> %vec.ind, + %1 = getelementptr inbounds i8, i8* %B, <32 x i64> %0 + %wide.masked.gather = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> %1, i32 1, <32 x i1> , <32 x i8> undef) + %2 = getelementptr inbounds i8, i8* %A, i64 %index + %3 = bitcast i8* %2 to <32 x i8>* + %wide.load = load <32 x i8>, <32 x i8>* %3, align 1 + %4 = add <32 x i8> %wide.load, %wide.masked.gather + %5 = bitcast i8* %2 to <32 x i8>* + store <32 x i8> %4, <32 x i8>* %5, align 1 + %index.next = add nuw i64 %index, 32 + %vec.ind.next = add <32 x i64> %vec.ind, + %6 = icmp eq i64 %index.next, 1024 + br i1 %6, label %for.cond.cleanup, label %vector.body + +for.cond.cleanup: ; preds = %vector.body + ret void +} + +define void @gather_zero_stride_unfold(i8* noalias nocapture %A, i8* noalias nocapture readonly %B) { +; V-LABEL: gather_zero_stride_unfold: ; V: # %bb.0: # %entry ; V-NEXT: li a2, 0 ; V-NEXT: li a3, 32 ; V-NEXT: li a4, 1024 -; V-NEXT: .LBB3_1: # %vector.body +; V-NEXT: .LBB4_1: # %vector.body ; V-NEXT: # =>This Inner Loop Header: Depth=1 ; V-NEXT: vsetvli zero, a3, e8, m1, ta, ma ; V-NEXT: vlse8.v v8, (a1), zero ; V-NEXT: add a5, a0, a2 ; V-NEXT: vle8.v v9, (a5) -; V-NEXT: vadd.vv v8, v9, v8 +; V-NEXT: vdivu.vv v8, v8, v9 ; V-NEXT: vse8.v v8, (a5) ; V-NEXT: addi a2, a2, 32 ; V-NEXT: addi a1, a1, 160 -; V-NEXT: bne a2, a4, .LBB3_1 +; V-NEXT: bne a2, a4, .LBB4_1 ; V-NEXT: # %bb.2: # %for.cond.cleanup ; V-NEXT: ret ; -; ZVE32F-LABEL: gather_zero_stride: +; ZVE32F-LABEL: gather_zero_stride_unfold: ; ZVE32F: # %bb.0: # %entry ; ZVE32F-NEXT: li a2, 0 ; ZVE32F-NEXT: li a3, 32 ; ZVE32F-NEXT: li a4, 1024 -; ZVE32F-NEXT: .LBB3_1: # %vector.body +; ZVE32F-NEXT: .LBB4_1: # %vector.body ; ZVE32F-NEXT: # =>This Inner Loop Header: Depth=1 ; ZVE32F-NEXT: vsetvli zero, a3, e8, m1, ta, ma ; ZVE32F-NEXT: vlse8.v v8, (a1), zero ; ZVE32F-NEXT: add a5, a0, a2 ; ZVE32F-NEXT: vle8.v v9, (a5) -; ZVE32F-NEXT: vadd.vv v8, v9, v8 +; ZVE32F-NEXT: vdivu.vv v8, v8, v9 ; ZVE32F-NEXT: vse8.v v8, (a5) ; ZVE32F-NEXT: addi a2, a2, 32 ; ZVE32F-NEXT: addi a1, a1, 160 -; ZVE32F-NEXT: bne a2, a4, .LBB3_1 +; ZVE32F-NEXT: bne a2, a4, .LBB4_1 ; ZVE32F-NEXT: # %bb.2: # %for.cond.cleanup ; ZVE32F-NEXT: ret ; -; NOT-OPTIMIZED-LABEL: gather_zero_stride: +; NOT-OPTIMIZED-LABEL: gather_zero_stride_unfold: ; NOT-OPTIMIZED: # %bb.0: # %entry ; NOT-OPTIMIZED-NEXT: li a2, 0 ; NOT-OPTIMIZED-NEXT: li a3, 32 ; NOT-OPTIMIZED-NEXT: li a4, 1024 -; NOT-OPTIMIZED-NEXT: .LBB3_1: # %vector.body +; NOT-OPTIMIZED-NEXT: .LBB4_1: # %vector.body ; NOT-OPTIMIZED-NEXT: # =>This Inner Loop Header: Depth=1 ; NOT-OPTIMIZED-NEXT: lbu a5, 0(a1) -; NOT-OPTIMIZED-NEXT: add a6, a0, a2 ; NOT-OPTIMIZED-NEXT: vsetvli zero, a3, e8, m1, ta, ma +; NOT-OPTIMIZED-NEXT: add a6, a0, a2 ; NOT-OPTIMIZED-NEXT: vle8.v v8, (a6) -; NOT-OPTIMIZED-NEXT: vadd.vx v8, v8, a5 +; NOT-OPTIMIZED-NEXT: vmv.v.x v9, a5 +; NOT-OPTIMIZED-NEXT: vdivu.vv v8, v9, v8 ; NOT-OPTIMIZED-NEXT: vse8.v v8, (a6) ; NOT-OPTIMIZED-NEXT: addi a2, a2, 32 ; NOT-OPTIMIZED-NEXT: addi a1, a1, 160 -; NOT-OPTIMIZED-NEXT: bne a2, a4, .LBB3_1 +; NOT-OPTIMIZED-NEXT: bne a2, a4, .LBB4_1 ; NOT-OPTIMIZED-NEXT: # %bb.2: # %for.cond.cleanup ; NOT-OPTIMIZED-NEXT: ret entry: @@ -246,7 +290,7 @@ %2 = getelementptr inbounds i8, i8* %A, i64 %index %3 = bitcast i8* %2 to <32 x i8>* %wide.load = load <32 x i8>, <32 x i8>* %3, align 1 - %4 = add <32 x i8> %wide.load, %wide.masked.gather + %4 = udiv <32 x i8> %wide.masked.gather, %wide.load %5 = bitcast i8* %2 to <32 x i8>* store <32 x i8> %4, <32 x i8>* %5, align 1 %index.next = add nuw i64 %index, 32 @@ -270,7 +314,7 @@ ; CHECK-NEXT: li a3, 32 ; CHECK-NEXT: li a4, 5 ; CHECK-NEXT: li a5, 1024 -; CHECK-NEXT: .LBB4_1: # %vector.body +; CHECK-NEXT: .LBB5_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: add a6, a1, a2 ; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, ma @@ -280,7 +324,7 @@ ; CHECK-NEXT: vsse8.v v8, (a0), a4 ; CHECK-NEXT: addi a2, a2, 32 ; CHECK-NEXT: addi a0, a0, 160 -; CHECK-NEXT: bne a2, a5, .LBB4_1 +; CHECK-NEXT: bne a2, a5, .LBB5_1 ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: ret entry: @@ -318,7 +362,7 @@ ; V-NEXT: vmv.s.x v0, a4 ; V-NEXT: li a4, 5 ; V-NEXT: li a5, 1024 -; V-NEXT: .LBB5_1: # %vector.body +; V-NEXT: .LBB6_1: # %vector.body ; V-NEXT: # =>This Inner Loop Header: Depth=1 ; V-NEXT: add a6, a1, a2 ; V-NEXT: vsetvli zero, a3, e8, m1, ta, mu @@ -329,7 +373,7 @@ ; V-NEXT: vsse8.v v9, (a0), a4, v0.t ; V-NEXT: addi a2, a2, 32 ; V-NEXT: addi a0, a0, 160 -; V-NEXT: bne a2, a5, .LBB5_1 +; V-NEXT: bne a2, a5, .LBB6_1 ; V-NEXT: # %bb.2: # %for.cond.cleanup ; V-NEXT: ret ; @@ -343,7 +387,7 @@ ; ZVE32F-NEXT: vmv.s.x v0, a4 ; ZVE32F-NEXT: li a4, 5 ; ZVE32F-NEXT: li a5, 1024 -; ZVE32F-NEXT: .LBB5_1: # %vector.body +; ZVE32F-NEXT: .LBB6_1: # %vector.body ; ZVE32F-NEXT: # =>This Inner Loop Header: Depth=1 ; ZVE32F-NEXT: add a6, a1, a2 ; ZVE32F-NEXT: vsetvli zero, a3, e8, m1, ta, mu @@ -354,7 +398,7 @@ ; ZVE32F-NEXT: vsse8.v v9, (a0), a4, v0.t ; ZVE32F-NEXT: addi a2, a2, 32 ; ZVE32F-NEXT: addi a0, a0, 160 -; ZVE32F-NEXT: bne a2, a5, .LBB5_1 +; ZVE32F-NEXT: bne a2, a5, .LBB6_1 ; ZVE32F-NEXT: # %bb.2: # %for.cond.cleanup ; ZVE32F-NEXT: ret entry: @@ -391,7 +435,7 @@ ; CHECK-NEXT: li a2, 1024 ; CHECK-NEXT: li a3, 16 ; CHECK-NEXT: li a4, 32 -; CHECK-NEXT: .LBB6_1: # %vector.body +; CHECK-NEXT: .LBB7_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetivli zero, 8, e32, m1, ta, ma ; CHECK-NEXT: vlse32.v v8, (a1), a3 @@ -404,7 +448,7 @@ ; CHECK-NEXT: addi a2, a2, -8 ; CHECK-NEXT: addi a0, a0, 32 ; CHECK-NEXT: addi a1, a1, 128 -; CHECK-NEXT: bnez a2, .LBB6_1 +; CHECK-NEXT: bnez a2, .LBB7_1 ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: ret entry: @@ -442,7 +486,7 @@ ; CHECK-NEXT: li a2, 1024 ; CHECK-NEXT: li a3, 32 ; CHECK-NEXT: li a4, 16 -; CHECK-NEXT: .LBB7_1: # %vector.body +; CHECK-NEXT: .LBB8_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, ma ; CHECK-NEXT: vle8.v v8, (a1) @@ -453,7 +497,7 @@ ; CHECK-NEXT: addi a2, a2, -8 ; CHECK-NEXT: addi a1, a1, 32 ; CHECK-NEXT: addi a0, a0, 128 -; CHECK-NEXT: bnez a2, .LBB7_1 +; CHECK-NEXT: bnez a2, .LBB8_1 ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: ret entry: @@ -495,7 +539,7 @@ ; CHECK-NEXT: li a2, 1024 ; CHECK-NEXT: li a3, 16 ; CHECK-NEXT: vsetivli zero, 8, e32, m1, ta, ma -; CHECK-NEXT: .LBB8_1: # %vector.body +; CHECK-NEXT: .LBB9_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: addi a4, a1, -128 ; CHECK-NEXT: vlse32.v v8, (a4), a3 @@ -510,7 +554,7 @@ ; CHECK-NEXT: addi a2, a2, -16 ; CHECK-NEXT: addi a0, a0, 64 ; CHECK-NEXT: addi a1, a1, 256 -; CHECK-NEXT: bnez a2, .LBB8_1 +; CHECK-NEXT: bnez a2, .LBB9_1 ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: ret entry: @@ -561,7 +605,7 @@ ; CHECK-NEXT: li a3, 64 ; CHECK-NEXT: li a4, 16 ; CHECK-NEXT: vsetivli zero, 8, e32, m1, ta, ma -; CHECK-NEXT: .LBB9_1: # %vector.body +; CHECK-NEXT: .LBB10_1: # %vector.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vlse32.v v8, (a1), a3 ; CHECK-NEXT: vlse32.v v9, (a0), a4 @@ -588,7 +632,7 @@ ; CHECK-NEXT: addi a2, a2, -8 ; CHECK-NEXT: addi a1, a1, 512 ; CHECK-NEXT: addi a0, a0, 128 -; CHECK-NEXT: bnez a2, .LBB9_1 +; CHECK-NEXT: bnez a2, .LBB10_1 ; CHECK-NEXT: # %bb.2: # %for.cond.cleanup ; CHECK-NEXT: ret entry: @@ -650,7 +694,7 @@ ; V-NEXT: li a2, 1024 ; V-NEXT: li a3, 40 ; V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; V-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 +; V-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 ; V-NEXT: vlse64.v v8, (a1), a3 ; V-NEXT: addi a4, a1, 80 ; V-NEXT: vlse64.v v9, (a4), a3 @@ -660,7 +704,7 @@ ; V-NEXT: addi a2, a2, -4 ; V-NEXT: addi a0, a0, 32 ; V-NEXT: addi a1, a1, 160 -; V-NEXT: bnez a2, .LBB10_1 +; V-NEXT: bnez a2, .LBB11_1 ; V-NEXT: # %bb.2: ; V-NEXT: ret ; @@ -670,7 +714,7 @@ ; ZVE32F-NEXT: li a3, 1 ; ZVE32F-NEXT: li a4, 1024 ; ZVE32F-NEXT: li a5, 40 -; ZVE32F-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1 +; ZVE32F-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 ; ZVE32F-NEXT: mul a6, a3, a5 ; ZVE32F-NEXT: add a6, a1, a6 ; ZVE32F-NEXT: mul a7, a2, a5 @@ -687,7 +731,7 @@ ; ZVE32F-NEXT: addi a3, a3, 4 ; ZVE32F-NEXT: addi a4, a4, -4 ; ZVE32F-NEXT: addi a0, a0, 32 -; ZVE32F-NEXT: bnez a4, .LBB10_1 +; ZVE32F-NEXT: bnez a4, .LBB11_1 ; ZVE32F-NEXT: # %bb.2: ; ZVE32F-NEXT: ret br label %3 @@ -727,7 +771,7 @@ ; V-NEXT: li a2, 1024 ; V-NEXT: li a3, 40 ; V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; V-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 +; V-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 ; V-NEXT: vle64.v v8, (a1) ; V-NEXT: addi a4, a1, 16 ; V-NEXT: vle64.v v9, (a4) @@ -737,7 +781,7 @@ ; V-NEXT: addi a2, a2, -4 ; V-NEXT: addi a1, a1, 32 ; V-NEXT: addi a0, a0, 160 -; V-NEXT: bnez a2, .LBB11_1 +; V-NEXT: bnez a2, .LBB12_1 ; V-NEXT: # %bb.2: ; V-NEXT: ret ; @@ -747,7 +791,7 @@ ; ZVE32F-NEXT: li a3, 1 ; ZVE32F-NEXT: li a4, 1024 ; ZVE32F-NEXT: li a5, 40 -; ZVE32F-NEXT: .LBB11_1: # =>This Inner Loop Header: Depth=1 +; ZVE32F-NEXT: .LBB12_1: # =>This Inner Loop Header: Depth=1 ; ZVE32F-NEXT: ld a6, 8(a1) ; ZVE32F-NEXT: ld a7, 0(a1) ; ZVE32F-NEXT: ld t0, 24(a1) @@ -764,7 +808,7 @@ ; ZVE32F-NEXT: addi a3, a3, 4 ; ZVE32F-NEXT: addi a4, a4, -4 ; ZVE32F-NEXT: addi a1, a1, 32 -; ZVE32F-NEXT: bnez a4, .LBB11_1 +; ZVE32F-NEXT: bnez a4, .LBB12_1 ; ZVE32F-NEXT: # %bb.2: ; ZVE32F-NEXT: ret br label %3 @@ -801,17 +845,17 @@ ; CHECK-LABEL: strided_load_startval_add_with_splat: ; CHECK: # %bb.0: ; CHECK-NEXT: li a3, 1024 -; CHECK-NEXT: beq a2, a3, .LBB12_7 +; CHECK-NEXT: beq a2, a3, .LBB13_7 ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: li a3, 1023 ; CHECK-NEXT: subw a4, a3, a2 ; CHECK-NEXT: li a5, 31 ; CHECK-NEXT: mv a3, a2 -; CHECK-NEXT: bltu a4, a5, .LBB12_5 +; CHECK-NEXT: bltu a4, a5, .LBB13_5 ; CHECK-NEXT: # %bb.2: -; CHECK-NEXT: slli a3, a4, 32 -; CHECK-NEXT: srli a3, a3, 32 -; CHECK-NEXT: addi a4, a3, 1 +; CHECK-NEXT: slli a4, a4, 32 +; CHECK-NEXT: srli a4, a4, 32 +; CHECK-NEXT: addi a4, a4, 1 ; CHECK-NEXT: andi a5, a4, -32 ; CHECK-NEXT: add a3, a5, a2 ; CHECK-NEXT: slli a6, a2, 2 @@ -821,7 +865,7 @@ ; CHECK-NEXT: li a7, 32 ; CHECK-NEXT: li t0, 5 ; CHECK-NEXT: mv t1, a5 -; CHECK-NEXT: .LBB12_3: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB13_3: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vsetvli zero, a7, e8, m1, ta, ma ; CHECK-NEXT: vlse8.v v8, (a6), t0 ; CHECK-NEXT: vle8.v v9, (a2) @@ -830,16 +874,16 @@ ; CHECK-NEXT: addi t1, t1, -32 ; CHECK-NEXT: addi a2, a2, 32 ; CHECK-NEXT: addi a6, a6, 160 -; CHECK-NEXT: bnez t1, .LBB12_3 +; CHECK-NEXT: bnez t1, .LBB13_3 ; CHECK-NEXT: # %bb.4: -; CHECK-NEXT: beq a4, a5, .LBB12_7 -; CHECK-NEXT: .LBB12_5: +; CHECK-NEXT: beq a4, a5, .LBB13_7 +; CHECK-NEXT: .LBB13_5: ; CHECK-NEXT: addiw a2, a3, -1024 ; CHECK-NEXT: add a0, a0, a3 ; CHECK-NEXT: slli a4, a3, 2 ; CHECK-NEXT: add a3, a4, a3 ; CHECK-NEXT: add a1, a1, a3 -; CHECK-NEXT: .LBB12_6: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: .LBB13_6: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: lb a3, 0(a1) ; CHECK-NEXT: lb a4, 0(a0) ; CHECK-NEXT: addw a3, a4, a3 @@ -847,8 +891,8 @@ ; CHECK-NEXT: addiw a2, a2, 1 ; CHECK-NEXT: addi a0, a0, 1 ; CHECK-NEXT: addi a1, a1, 5 -; CHECK-NEXT: bnez a2, .LBB12_6 -; CHECK-NEXT: .LBB12_7: +; CHECK-NEXT: bnez a2, .LBB13_6 +; CHECK-NEXT: .LBB13_7: ; CHECK-NEXT: ret %4 = icmp eq i32 %2, 1024 br i1 %4, label %36, label %5 @@ -920,11 +964,11 @@ ; CHECK-LABEL: gather_no_scalar_remainder: ; CHECK: # %bb.0: # %bb ; CHECK-NEXT: slli a2, a2, 4 -; CHECK-NEXT: beqz a2, .LBB13_3 +; CHECK-NEXT: beqz a2, .LBB14_3 ; CHECK-NEXT: # %bb.1: # %bb2 ; CHECK-NEXT: li a3, 5 ; CHECK-NEXT: vsetivli zero, 16, e8, mf2, ta, ma -; CHECK-NEXT: .LBB13_2: # %bb4 +; CHECK-NEXT: .LBB14_2: # %bb4 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: vlse8.v v8, (a1), a3 ; CHECK-NEXT: vle8.v v9, (a0) @@ -933,8 +977,8 @@ ; CHECK-NEXT: addi a2, a2, -16 ; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a1, a1, 80 -; CHECK-NEXT: bnez a2, .LBB13_2 -; CHECK-NEXT: .LBB13_3: # %bb16 +; CHECK-NEXT: bnez a2, .LBB14_2 +; CHECK-NEXT: .LBB14_3: # %bb16 ; CHECK-NEXT: ret bb: %i = shl i64 %arg2, 4 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll @@ -35,15 +35,15 @@ ; RV32-NEXT: lw t0, 8(a1) ; RV32-NEXT: lw a1, 12(a1) ; RV32-NEXT: add a5, a5, a6 -; RV32-NEXT: add a6, a4, a7 -; RV32-NEXT: sltu a4, a6, a4 +; RV32-NEXT: add a7, a4, a7 +; RV32-NEXT: sltu a4, a7, a4 ; RV32-NEXT: add a4, a5, a4 ; RV32-NEXT: add a1, a3, a1 -; RV32-NEXT: add a3, a2, t0 -; RV32-NEXT: sltu a2, a3, a2 +; RV32-NEXT: add t0, a2, t0 +; RV32-NEXT: sltu a2, t0, a2 ; RV32-NEXT: add a1, a1, a2 -; RV32-NEXT: sw a3, 8(a0) -; RV32-NEXT: sw a6, 0(a0) +; RV32-NEXT: sw t0, 8(a0) +; RV32-NEXT: sw a7, 0(a0) ; RV32-NEXT: sw a1, 12(a0) ; RV32-NEXT: sw a4, 4(a0) ; RV32-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll @@ -104,8 +104,8 @@ ; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a1, 48 ; LMULMAX1-NEXT: vse64.v v11, (a0) -; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse64.v v9, (a0) +; LMULMAX1-NEXT: addi a1, a1, 16 +; LMULMAX1-NEXT: vse64.v v9, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x half>, <8 x half>* %x %d = fpext <8 x half> %a to <8 x double> diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll @@ -96,8 +96,8 @@ ; LMULMAX1-NEXT: vfcvt.rtz.x.f.v v8, v8 ; LMULMAX1-NEXT: vfcvt.rtz.x.f.v v9, v9 ; LMULMAX1-NEXT: vse32.v v9, (a1) -; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse32.v v8, (a0) +; LMULMAX1-NEXT: addi a1, a1, 16 +; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %d = fptosi <8 x float> %a to <8 x i32> @@ -123,8 +123,8 @@ ; LMULMAX1-NEXT: vfcvt.rtz.xu.f.v v8, v8 ; LMULMAX1-NEXT: vfcvt.rtz.xu.f.v v9, v9 ; LMULMAX1-NEXT: vse32.v v9, (a1) -; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse32.v v8, (a0) +; LMULMAX1-NEXT: addi a1, a1, 16 +; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x float>, <8 x float>* %x %d = fptoui <8 x float> %a to <8 x i32> diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll @@ -102,8 +102,8 @@ ; LMULMAX1-NEXT: vfcvt.f.x.v v8, v8 ; LMULMAX1-NEXT: vfcvt.f.x.v v9, v9 ; LMULMAX1-NEXT: vse32.v v9, (a1) -; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse32.v v8, (a0) +; LMULMAX1-NEXT: addi a1, a1, 16 +; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %d = sitofp <8 x i32> %a to <8 x float> @@ -129,8 +129,8 @@ ; LMULMAX1-NEXT: vfcvt.f.xu.v v8, v8 ; LMULMAX1-NEXT: vfcvt.f.xu.v v9, v9 ; LMULMAX1-NEXT: vse32.v v9, (a1) -; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse32.v v8, (a0) +; LMULMAX1-NEXT: addi a1, a1, 16 +; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x i32>, <8 x i32>* %x %d = uitofp <8 x i32> %a to <8 x float> @@ -263,8 +263,8 @@ ; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a1, 48 ; LMULMAX1-NEXT: vse64.v v11, (a0) -; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse64.v v9, (a0) +; LMULMAX1-NEXT: addi a1, a1, 16 +; LMULMAX1-NEXT: vse64.v v9, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %d = sitofp <8 x i16> %a to <8 x double> @@ -307,8 +307,8 @@ ; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a1, 48 ; LMULMAX1-NEXT: vse64.v v11, (a0) -; LMULMAX1-NEXT: addi a0, a1, 16 -; LMULMAX1-NEXT: vse64.v v9, (a0) +; LMULMAX1-NEXT: addi a1, a1, 16 +; LMULMAX1-NEXT: vse64.v v9, (a1) ; LMULMAX1-NEXT: ret %a = load <8 x i16>, <8 x i16>* %x %d = uitofp <8 x i16> %a to <8 x double> diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll @@ -108,8 +108,8 @@ ; RV64-NEXT: vsetvli zero, a3, e16, m4, ta, ma ; RV64-NEXT: vle16.v v8, (a0) ; RV64-NEXT: vmv.s.x v12, a1 -; RV64-NEXT: slli a1, a2, 32 -; RV64-NEXT: srli a1, a1, 32 +; RV64-NEXT: slli a2, a2, 32 +; RV64-NEXT: srli a1, a2, 32 ; RV64-NEXT: addi a2, a1, 1 ; RV64-NEXT: vsetvli zero, a2, e16, m4, tu, ma ; RV64-NEXT: vslideup.vx v8, v12, a1 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll @@ -773,8 +773,8 @@ ; LMULMAX1-RV32-NEXT: addi a0, a3, 48 ; LMULMAX1-RV32-NEXT: vse64.v v13, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v14, (a3) -; LMULMAX1-RV32-NEXT: addi a0, a3, 16 -; LMULMAX1-RV32-NEXT: vse64.v v15, (a0) +; LMULMAX1-RV32-NEXT: addi a3, a3, 16 +; LMULMAX1-RV32-NEXT: vse64.v v15, (a3) ; LMULMAX1-RV32-NEXT: ret ; ; LMULMAX8-RV64-LABEL: vadd_vx_v16i64: @@ -847,8 +847,8 @@ ; LMULMAX1-RV64-NEXT: vse64.v v14, (a0) ; LMULMAX1-RV64-NEXT: addi a0, a2, 48 ; LMULMAX1-RV64-NEXT: vse64.v v12, (a0) -; LMULMAX1-RV64-NEXT: addi a0, a2, 16 -; LMULMAX1-RV64-NEXT: vse64.v v13, (a0) +; LMULMAX1-RV64-NEXT: addi a2, a2, 16 +; LMULMAX1-RV64-NEXT: vse64.v v13, (a2) ; LMULMAX1-RV64-NEXT: ret %va = load <16 x i64>, <16 x i64>* %a %head = insertelement <16 x i64> poison, i64 %b, i32 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll @@ -208,9 +208,9 @@ define void @splat_concat_high(<4 x i16>* %x, <4 x i16>* %y, <8 x i16>* %z) { ; CHECK-LABEL: splat_concat_high: ; CHECK: # %bb.0: -; CHECK-NEXT: addi a0, a1, 2 +; CHECK-NEXT: addi a1, a1, 2 ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma -; CHECK-NEXT: vlse16.v v8, (a0), zero +; CHECK-NEXT: vlse16.v v8, (a1), zero ; CHECK-NEXT: vse16.v v8, (a2) ; CHECK-NEXT: ret %a = load <4 x i16>, <4 x i16>* %x diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll @@ -5877,12 +5877,12 @@ ; ; RV64ZVE32F-LABEL: mgather_baseidx_zext_v8i16_v8i64: ; RV64ZVE32F: # %bb.0: -; RV64ZVE32F-NEXT: lui a3, 16 +; RV64ZVE32F-NEXT: lui a5, 16 ; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a6, v0 -; RV64ZVE32F-NEXT: andi a4, a6, 1 -; RV64ZVE32F-NEXT: addiw a5, a3, -1 -; RV64ZVE32F-NEXT: beqz a4, .LBB53_3 +; RV64ZVE32F-NEXT: andi a3, a6, 1 +; RV64ZVE32F-NEXT: addiw a5, a5, -1 +; RV64ZVE32F-NEXT: beqz a3, .LBB53_3 ; RV64ZVE32F-NEXT: # %bb.1: # %cond.load ; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll @@ -6005,9 +6005,9 @@ ; RV64ZVE32F-NEXT: andi a0, a7, -128 ; RV64ZVE32F-NEXT: beqz a0, .LBB51_9 ; RV64ZVE32F-NEXT: .LBB51_8: # %cond.store13 -; RV64ZVE32F-NEXT: slli a0, a5, 3 -; RV64ZVE32F-NEXT: add a0, a1, a0 -; RV64ZVE32F-NEXT: sd a3, 0(a0) +; RV64ZVE32F-NEXT: slli a5, a5, 3 +; RV64ZVE32F-NEXT: add a1, a1, a5 +; RV64ZVE32F-NEXT: sd a3, 0(a1) ; RV64ZVE32F-NEXT: .LBB51_9: # %else14 ; RV64ZVE32F-NEXT: ld s0, 24(sp) # 8-byte Folded Reload ; RV64ZVE32F-NEXT: ld s1, 16(sp) # 8-byte Folded Reload @@ -6024,39 +6024,39 @@ ; RV64ZVE32F-NEXT: andi a0, a7, 2 ; RV64ZVE32F-NEXT: beqz a0, .LBB51_2 ; RV64ZVE32F-NEXT: .LBB51_11: # %cond.store1 -; RV64ZVE32F-NEXT: slli a0, s2, 3 -; RV64ZVE32F-NEXT: add a0, a1, a0 -; RV64ZVE32F-NEXT: sd s1, 0(a0) +; RV64ZVE32F-NEXT: slli s2, s2, 3 +; RV64ZVE32F-NEXT: add s2, a1, s2 +; RV64ZVE32F-NEXT: sd s1, 0(s2) ; RV64ZVE32F-NEXT: andi a0, a7, 4 ; RV64ZVE32F-NEXT: beqz a0, .LBB51_3 ; RV64ZVE32F-NEXT: .LBB51_12: # %cond.store3 -; RV64ZVE32F-NEXT: slli a0, s0, 3 -; RV64ZVE32F-NEXT: add a0, a1, a0 -; RV64ZVE32F-NEXT: sd t6, 0(a0) +; RV64ZVE32F-NEXT: slli s0, s0, 3 +; RV64ZVE32F-NEXT: add s0, a1, s0 +; RV64ZVE32F-NEXT: sd t6, 0(s0) ; RV64ZVE32F-NEXT: andi a0, a7, 8 ; RV64ZVE32F-NEXT: beqz a0, .LBB51_4 ; RV64ZVE32F-NEXT: .LBB51_13: # %cond.store5 -; RV64ZVE32F-NEXT: slli a0, t5, 3 -; RV64ZVE32F-NEXT: add a0, a1, a0 -; RV64ZVE32F-NEXT: sd t3, 0(a0) +; RV64ZVE32F-NEXT: slli t5, t5, 3 +; RV64ZVE32F-NEXT: add t5, a1, t5 +; RV64ZVE32F-NEXT: sd t3, 0(t5) ; RV64ZVE32F-NEXT: andi a0, a7, 16 ; RV64ZVE32F-NEXT: beqz a0, .LBB51_5 ; RV64ZVE32F-NEXT: .LBB51_14: # %cond.store7 -; RV64ZVE32F-NEXT: slli a0, t4, 3 -; RV64ZVE32F-NEXT: add a0, a1, a0 -; RV64ZVE32F-NEXT: sd t1, 0(a0) +; RV64ZVE32F-NEXT: slli t4, t4, 3 +; RV64ZVE32F-NEXT: add t4, a1, t4 +; RV64ZVE32F-NEXT: sd t1, 0(t4) ; RV64ZVE32F-NEXT: andi a0, a7, 32 ; RV64ZVE32F-NEXT: beqz a0, .LBB51_6 ; RV64ZVE32F-NEXT: .LBB51_15: # %cond.store9 -; RV64ZVE32F-NEXT: slli a0, t2, 3 -; RV64ZVE32F-NEXT: add a0, a1, a0 -; RV64ZVE32F-NEXT: sd a6, 0(a0) +; RV64ZVE32F-NEXT: slli t2, t2, 3 +; RV64ZVE32F-NEXT: add t2, a1, t2 +; RV64ZVE32F-NEXT: sd a6, 0(t2) ; RV64ZVE32F-NEXT: andi a0, a7, 64 ; RV64ZVE32F-NEXT: beqz a0, .LBB51_7 ; RV64ZVE32F-NEXT: .LBB51_16: # %cond.store11 -; RV64ZVE32F-NEXT: slli a0, t0, 3 -; RV64ZVE32F-NEXT: add a0, a1, a0 -; RV64ZVE32F-NEXT: sd a4, 0(a0) +; RV64ZVE32F-NEXT: slli t0, t0, 3 +; RV64ZVE32F-NEXT: add t0, a1, t0 +; RV64ZVE32F-NEXT: sd a4, 0(t0) ; RV64ZVE32F-NEXT: andi a0, a7, -128 ; RV64ZVE32F-NEXT: bnez a0, .LBB51_8 ; RV64ZVE32F-NEXT: j .LBB51_9 @@ -10701,44 +10701,44 @@ ; RV64ZVE32F-NEXT: andi a1, a3, 2 ; RV64ZVE32F-NEXT: beqz a1, .LBB90_2 ; RV64ZVE32F-NEXT: .LBB90_10: # %cond.store1 -; RV64ZVE32F-NEXT: slli a1, t1, 3 -; RV64ZVE32F-NEXT: add a1, a0, a1 -; RV64ZVE32F-NEXT: fsd fa1, 0(a1) +; RV64ZVE32F-NEXT: slli t1, t1, 3 +; RV64ZVE32F-NEXT: add t1, a0, t1 +; RV64ZVE32F-NEXT: fsd fa1, 0(t1) ; RV64ZVE32F-NEXT: andi a1, a3, 4 ; RV64ZVE32F-NEXT: beqz a1, .LBB90_3 ; RV64ZVE32F-NEXT: .LBB90_11: # %cond.store3 -; RV64ZVE32F-NEXT: slli a1, t0, 3 -; RV64ZVE32F-NEXT: add a1, a0, a1 -; RV64ZVE32F-NEXT: fsd fa2, 0(a1) +; RV64ZVE32F-NEXT: slli t0, t0, 3 +; RV64ZVE32F-NEXT: add t0, a0, t0 +; RV64ZVE32F-NEXT: fsd fa2, 0(t0) ; RV64ZVE32F-NEXT: andi a1, a3, 8 ; RV64ZVE32F-NEXT: beqz a1, .LBB90_4 ; RV64ZVE32F-NEXT: .LBB90_12: # %cond.store5 -; RV64ZVE32F-NEXT: slli a1, a7, 3 -; RV64ZVE32F-NEXT: add a1, a0, a1 -; RV64ZVE32F-NEXT: fsd fa3, 0(a1) +; RV64ZVE32F-NEXT: slli a7, a7, 3 +; RV64ZVE32F-NEXT: add a7, a0, a7 +; RV64ZVE32F-NEXT: fsd fa3, 0(a7) ; RV64ZVE32F-NEXT: andi a1, a3, 16 ; RV64ZVE32F-NEXT: beqz a1, .LBB90_5 ; RV64ZVE32F-NEXT: .LBB90_13: # %cond.store7 -; RV64ZVE32F-NEXT: slli a1, a6, 3 -; RV64ZVE32F-NEXT: add a1, a0, a1 -; RV64ZVE32F-NEXT: fsd fa4, 0(a1) +; RV64ZVE32F-NEXT: slli a6, a6, 3 +; RV64ZVE32F-NEXT: add a6, a0, a6 +; RV64ZVE32F-NEXT: fsd fa4, 0(a6) ; RV64ZVE32F-NEXT: andi a1, a3, 32 ; RV64ZVE32F-NEXT: beqz a1, .LBB90_6 ; RV64ZVE32F-NEXT: .LBB90_14: # %cond.store9 -; RV64ZVE32F-NEXT: slli a1, a5, 3 -; RV64ZVE32F-NEXT: add a1, a0, a1 -; RV64ZVE32F-NEXT: fsd fa5, 0(a1) +; RV64ZVE32F-NEXT: slli a5, a5, 3 +; RV64ZVE32F-NEXT: add a5, a0, a5 +; RV64ZVE32F-NEXT: fsd fa5, 0(a5) ; RV64ZVE32F-NEXT: andi a1, a3, 64 ; RV64ZVE32F-NEXT: beqz a1, .LBB90_7 ; RV64ZVE32F-NEXT: .LBB90_15: # %cond.store11 -; RV64ZVE32F-NEXT: slli a1, a4, 3 -; RV64ZVE32F-NEXT: add a1, a0, a1 -; RV64ZVE32F-NEXT: fsd fa6, 0(a1) +; RV64ZVE32F-NEXT: slli a4, a4, 3 +; RV64ZVE32F-NEXT: add a4, a0, a4 +; RV64ZVE32F-NEXT: fsd fa6, 0(a4) ; RV64ZVE32F-NEXT: andi a1, a3, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB90_8 ; RV64ZVE32F-NEXT: .LBB90_16: # %cond.store13 -; RV64ZVE32F-NEXT: slli a1, a2, 3 -; RV64ZVE32F-NEXT: add a0, a0, a1 +; RV64ZVE32F-NEXT: slli a2, a2, 3 +; RV64ZVE32F-NEXT: add a0, a0, a2 ; RV64ZVE32F-NEXT: fsd fa7, 0(a0) ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds double, double* %base, <8 x i64> %idxs diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll @@ -423,9 +423,9 @@ ; RV32-NEXT: lbu a6, 3(a0) ; RV32-NEXT: slli a3, a3, 8 ; RV32-NEXT: or a3, a3, a4 -; RV32-NEXT: slli a4, a5, 16 -; RV32-NEXT: slli a5, a6, 24 -; RV32-NEXT: or a4, a5, a4 +; RV32-NEXT: slli a5, a5, 16 +; RV32-NEXT: slli a6, a6, 24 +; RV32-NEXT: or a4, a6, a5 ; RV32-NEXT: or a3, a4, a3 ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; RV32-NEXT: vmv.v.x v8, a3 @@ -444,9 +444,9 @@ ; RV32-NEXT: lbu a0, 7(a0) ; RV32-NEXT: slli a2, a2, 8 ; RV32-NEXT: or a2, a2, a3 -; RV32-NEXT: slli a3, a4, 16 +; RV32-NEXT: slli a4, a4, 16 ; RV32-NEXT: slli a0, a0, 24 -; RV32-NEXT: or a0, a0, a3 +; RV32-NEXT: or a0, a0, a4 ; RV32-NEXT: or a0, a0, a2 ; RV32-NEXT: vmv.s.x v9, a0 ; RV32-NEXT: vsetvli zero, zero, e32, mf2, tu, ma @@ -471,9 +471,9 @@ ; RV64-NEXT: lb a6, 3(a0) ; RV64-NEXT: slli a3, a3, 8 ; RV64-NEXT: or a3, a3, a4 -; RV64-NEXT: slli a4, a5, 16 -; RV64-NEXT: slli a5, a6, 24 -; RV64-NEXT: or a4, a5, a4 +; RV64-NEXT: slli a5, a5, 16 +; RV64-NEXT: slli a6, a6, 24 +; RV64-NEXT: or a4, a6, a5 ; RV64-NEXT: or a3, a4, a3 ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; RV64-NEXT: vmv.v.x v8, a3 @@ -492,9 +492,9 @@ ; RV64-NEXT: lb a0, 7(a0) ; RV64-NEXT: slli a2, a2, 8 ; RV64-NEXT: or a2, a2, a3 -; RV64-NEXT: slli a3, a4, 16 +; RV64-NEXT: slli a4, a4, 16 ; RV64-NEXT: slli a0, a0, 24 -; RV64-NEXT: or a0, a0, a3 +; RV64-NEXT: or a0, a0, a4 ; RV64-NEXT: or a0, a0, a2 ; RV64-NEXT: vmv.s.x v9, a0 ; RV64-NEXT: vsetvli zero, zero, e32, mf2, tu, ma diff --git a/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll --- a/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll @@ -659,8 +659,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma ; CHECK-NEXT: vmv.s.x v9, a0 -; CHECK-NEXT: slli a0, a1, 32 -; CHECK-NEXT: srli a0, a0, 32 +; CHECK-NEXT: slli a1, a1, 32 +; CHECK-NEXT: srli a0, a1, 32 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 @@ -696,8 +696,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv.s.x v10, a0 -; CHECK-NEXT: slli a0, a1, 32 -; CHECK-NEXT: srli a0, a0, 32 +; CHECK-NEXT: slli a1, a1, 32 +; CHECK-NEXT: srli a0, a1, 32 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, tu, ma ; CHECK-NEXT: vslideup.vx v8, v10, a0 @@ -733,8 +733,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64, m4, ta, ma ; CHECK-NEXT: vmv.s.x v12, a0 -; CHECK-NEXT: slli a0, a1, 32 -; CHECK-NEXT: srli a0, a0, 32 +; CHECK-NEXT: slli a1, a1, 32 +; CHECK-NEXT: srli a0, a1, 32 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m4, tu, ma ; CHECK-NEXT: vslideup.vx v8, v12, a0 @@ -770,8 +770,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv.s.x v16, a0 -; CHECK-NEXT: slli a0, a1, 32 -; CHECK-NEXT: srli a0, a0, 32 +; CHECK-NEXT: slli a1, a1, 32 +; CHECK-NEXT: srli a0, a1, 32 ; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma ; CHECK-NEXT: vslideup.vx v8, v16, a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll --- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll @@ -2174,9 +2174,9 @@ ; CHECK-NEXT: beqz a5, .LBB34_7 ; CHECK-NEXT: .LBB34_5: # %for.body.preheader ; CHECK-NEXT: addi a2, a4, -1024 -; CHECK-NEXT: slli a3, a4, 2 -; CHECK-NEXT: add a1, a1, a3 -; CHECK-NEXT: add a0, a0, a3 +; CHECK-NEXT: slli a4, a4, 2 +; CHECK-NEXT: add a1, a1, a4 +; CHECK-NEXT: add a0, a0, a4 ; CHECK-NEXT: .LBB34_6: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: flw ft0, 0(a0) @@ -2277,9 +2277,9 @@ ; CHECK-NEXT: beqz a5, .LBB35_7 ; CHECK-NEXT: .LBB35_5: # %for.body.preheader ; CHECK-NEXT: addi a2, a4, -1024 -; CHECK-NEXT: slli a3, a4, 2 -; CHECK-NEXT: add a1, a1, a3 -; CHECK-NEXT: add a0, a0, a3 +; CHECK-NEXT: slli a4, a4, 2 +; CHECK-NEXT: add a1, a1, a4 +; CHECK-NEXT: add a0, a0, a4 ; CHECK-NEXT: .LBB35_6: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: flw ft0, 0(a0) diff --git a/llvm/test/CodeGen/RISCV/rvv/vpstore.ll b/llvm/test/CodeGen/RISCV/rvv/vpstore.ll --- a/llvm/test/CodeGen/RISCV/rvv/vpstore.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vpstore.ll @@ -446,8 +446,8 @@ ; CHECK-NEXT: srli a2, a3, 2 ; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v0, v24, a2 -; CHECK-NEXT: slli a2, a3, 4 -; CHECK-NEXT: add a1, a1, a2 +; CHECK-NEXT: slli a3, a3, 4 +; CHECK-NEXT: add a1, a1, a3 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: vl8re8.v v8, (a0) # Unknown-size Folded Reload diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll @@ -93,11 +93,11 @@ define half @vpreduce_fadd_nxv64f16(half %s, %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_fadd_nxv64f16: ; CHECK: # %bb.0: -; CHECK-NEXT: csrr a1, vlenb -; CHECK-NEXT: srli a2, a1, 1 +; CHECK-NEXT: csrr a2, vlenb +; CHECK-NEXT: srli a1, a2, 1 ; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma -; CHECK-NEXT: vslidedown.vx v24, v0, a2 -; CHECK-NEXT: slli a2, a1, 2 +; CHECK-NEXT: vslidedown.vx v24, v0, a1 +; CHECK-NEXT: slli a2, a2, 2 ; CHECK-NEXT: sub a1, a0, a2 ; CHECK-NEXT: sltu a3, a0, a1 ; CHECK-NEXT: addi a3, a3, -1 @@ -125,11 +125,11 @@ define half @vpreduce_ord_fadd_nxv64f16(half %s, %v, %m, i32 zeroext %evl) { ; CHECK-LABEL: vpreduce_ord_fadd_nxv64f16: ; CHECK: # %bb.0: -; CHECK-NEXT: csrr a1, vlenb -; CHECK-NEXT: srli a2, a1, 1 +; CHECK-NEXT: csrr a2, vlenb +; CHECK-NEXT: srli a1, a2, 1 ; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma -; CHECK-NEXT: vslidedown.vx v24, v0, a2 -; CHECK-NEXT: slli a2, a1, 2 +; CHECK-NEXT: vslidedown.vx v24, v0, a1 +; CHECK-NEXT: slli a2, a2, 2 ; CHECK-NEXT: sub a1, a0, a2 ; CHECK-NEXT: sltu a3, a0, a1 ; CHECK-NEXT: addi a3, a3, -1 diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll --- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll @@ -1153,11 +1153,11 @@ define signext i32 @vpreduce_umax_nxv32i32(i32 signext %s, %v, %m, i32 zeroext %evl) { ; RV32-LABEL: vpreduce_umax_nxv32i32: ; RV32: # %bb.0: -; RV32-NEXT: csrr a2, vlenb -; RV32-NEXT: srli a3, a2, 2 +; RV32-NEXT: csrr a3, vlenb +; RV32-NEXT: srli a2, a3, 2 ; RV32-NEXT: vsetvli a4, zero, e8, mf2, ta, ma -; RV32-NEXT: vslidedown.vx v24, v0, a3 -; RV32-NEXT: slli a3, a2, 1 +; RV32-NEXT: vslidedown.vx v24, v0, a2 +; RV32-NEXT: slli a3, a3, 1 ; RV32-NEXT: sub a2, a1, a3 ; RV32-NEXT: sltu a4, a1, a2 ; RV32-NEXT: addi a4, a4, -1 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll @@ -592,21 +592,21 @@ ; CHECK-NEXT: vsetvli a6, zero, e64, m1, ta, mu ; CHECK-NEXT: blez a0, .LBB11_3 ; CHECK-NEXT: # %bb.1: # %for.body.preheader -; CHECK-NEXT: li a5, 0 +; CHECK-NEXT: li a4, 0 ; CHECK-NEXT: li t1, 0 ; CHECK-NEXT: slli a7, a6, 3 ; CHECK-NEXT: .LBB11_2: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 -; CHECK-NEXT: add t0, a2, a5 +; CHECK-NEXT: add t0, a2, a4 ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vle64.v v8, (t0) -; CHECK-NEXT: add a4, a3, a5 -; CHECK-NEXT: vle64.v v9, (a4) +; CHECK-NEXT: add a5, a3, a4 +; CHECK-NEXT: vle64.v v9, (a5) ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: add a4, a1, a5 -; CHECK-NEXT: vse64.v v8, (a4) +; CHECK-NEXT: add a5, a1, a4 +; CHECK-NEXT: vse64.v v8, (a5) ; CHECK-NEXT: add t1, t1, a6 -; CHECK-NEXT: add a5, a5, a7 +; CHECK-NEXT: add a4, a4, a7 ; CHECK-NEXT: blt t1, a0, .LBB11_2 ; CHECK-NEXT: .LBB11_3: # %for.end ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/select-binop-identity.ll b/llvm/test/CodeGen/RISCV/select-binop-identity.ll --- a/llvm/test/CodeGen/RISCV/select-binop-identity.ll +++ b/llvm/test/CodeGen/RISCV/select-binop-identity.ll @@ -174,10 +174,10 @@ ; RV32I: # %bb.0: ; RV32I-NEXT: beqz a0, .LBB7_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: add a0, a4, a2 +; RV32I-NEXT: add a2, a4, a2 ; RV32I-NEXT: add a1, a3, a1 -; RV32I-NEXT: sltu a2, a1, a3 -; RV32I-NEXT: add a4, a0, a2 +; RV32I-NEXT: sltu a4, a1, a3 +; RV32I-NEXT: add a4, a2, a4 ; RV32I-NEXT: mv a3, a1 ; RV32I-NEXT: .LBB7_2: ; RV32I-NEXT: mv a0, a3 diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll --- a/llvm/test/CodeGen/RISCV/select-const.ll +++ b/llvm/test/CodeGen/RISCV/select-const.ll @@ -391,3 +391,41 @@ %2 = select i1 %1, i32 10001, i32 10002 ret i32 %2 } + +define i32 @select_slt_zero_constant1_constant2(i32 signext %x) { +; RV32-LABEL: select_slt_zero_constant1_constant2: +; RV32: # %bb.0: +; RV32-NEXT: srai a0, a0, 31 +; RV32-NEXT: andi a0, a0, 10 +; RV32-NEXT: addi a0, a0, -3 +; RV32-NEXT: ret +; +; RV64-LABEL: select_slt_zero_constant1_constant2: +; RV64: # %bb.0: +; RV64-NEXT: srai a0, a0, 63 +; RV64-NEXT: andi a0, a0, 10 +; RV64-NEXT: addi a0, a0, -3 +; RV64-NEXT: ret + %cmp = icmp slt i32 %x, 0 + %cond = select i1 %cmp, i32 7, i32 -3 + ret i32 %cond +} + +define i32 @select_sgt_negative_one_constant1_constant2(i32 signext %x) { +; RV32-LABEL: select_sgt_negative_one_constant1_constant2: +; RV32: # %bb.0: +; RV32-NEXT: srai a0, a0, 31 +; RV32-NEXT: andi a0, a0, -10 +; RV32-NEXT: addi a0, a0, 7 +; RV32-NEXT: ret +; +; RV64-LABEL: select_sgt_negative_one_constant1_constant2: +; RV64: # %bb.0: +; RV64-NEXT: srai a0, a0, 63 +; RV64-NEXT: andi a0, a0, -10 +; RV64-NEXT: addi a0, a0, 7 +; RV64-NEXT: ret + %cmp = icmp sgt i32 %x, -1 + %cond = select i1 %cmp, i32 7, i32 -3 + ret i32 %cond +} diff --git a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll --- a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll +++ b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll @@ -64,12 +64,12 @@ ; RV32I-NEXT: lw a6, 0(a6) ; RV32I-NEXT: beqz a1, .LBB1_9 ; RV32I-NEXT: # %bb.8: # %entry -; RV32I-NEXT: addi a1, a4, 12 +; RV32I-NEXT: addi a3, a4, 12 ; RV32I-NEXT: j .LBB1_10 ; RV32I-NEXT: .LBB1_9: -; RV32I-NEXT: addi a1, a3, 12 +; RV32I-NEXT: addi a3, a3, 12 ; RV32I-NEXT: .LBB1_10: # %entry -; RV32I-NEXT: lw a1, 0(a1) +; RV32I-NEXT: lw a1, 0(a3) ; RV32I-NEXT: sw a1, 12(a0) ; RV32I-NEXT: sw a6, 8(a0) ; RV32I-NEXT: sw a5, 4(a0) @@ -147,12 +147,12 @@ ; RV32I-NEXT: lw a6, 0(a6) ; RV32I-NEXT: bnez a1, .LBB3_9 ; RV32I-NEXT: # %bb.8: # %entry -; RV32I-NEXT: addi a1, a3, 12 +; RV32I-NEXT: addi a2, a3, 12 ; RV32I-NEXT: j .LBB3_10 ; RV32I-NEXT: .LBB3_9: -; RV32I-NEXT: addi a1, a2, 12 +; RV32I-NEXT: addi a2, a2, 12 ; RV32I-NEXT: .LBB3_10: # %entry -; RV32I-NEXT: lw a1, 0(a1) +; RV32I-NEXT: lw a1, 0(a2) ; RV32I-NEXT: sw a1, 12(a0) ; RV32I-NEXT: sw a6, 8(a0) ; RV32I-NEXT: sw a5, 4(a0) diff --git a/llvm/test/CodeGen/RISCV/shadowcallstack.ll b/llvm/test/CodeGen/RISCV/shadowcallstack.ll --- a/llvm/test/CodeGen/RISCV/shadowcallstack.ll +++ b/llvm/test/CodeGen/RISCV/shadowcallstack.ll @@ -88,9 +88,9 @@ ; RV32-NEXT: call bar@plt ; RV32-NEXT: mv s3, a0 ; RV32-NEXT: call bar@plt -; RV32-NEXT: add a1, s0, s1 +; RV32-NEXT: add s0, s0, s1 ; RV32-NEXT: add a0, s3, a0 -; RV32-NEXT: add a0, a1, a0 +; RV32-NEXT: add a0, s0, a0 ; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s1, 4(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/shifts.ll b/llvm/test/CodeGen/RISCV/shifts.ll --- a/llvm/test/CodeGen/RISCV/shifts.ll +++ b/llvm/test/CodeGen/RISCV/shifts.ll @@ -563,8 +563,8 @@ ; RV32I-NEXT: sll a0, a0, a5 ; RV32I-NEXT: or a0, a0, a4 ; RV32I-NEXT: srl a1, a1, a2 -; RV32I-NEXT: slli a2, a3, 1 -; RV32I-NEXT: sll a2, a2, a5 +; RV32I-NEXT: slli a3, a3, 1 +; RV32I-NEXT: sll a2, a3, a5 ; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: ret ; @@ -631,8 +631,8 @@ ; RV32I-NEXT: sll a4, a4, t1 ; RV32I-NEXT: or a3, a4, a3 ; RV32I-NEXT: srl a1, a1, a2 -; RV32I-NEXT: slli a2, a5, 1 -; RV32I-NEXT: sll a2, a2, t1 +; RV32I-NEXT: slli a5, a5, 1 +; RV32I-NEXT: sll a2, a5, t1 ; RV32I-NEXT: or a1, a2, a1 ; RV32I-NEXT: sw a1, 12(a0) ; RV32I-NEXT: sw a3, 8(a0) @@ -665,8 +665,8 @@ ; RV64I-NEXT: sll a0, a0, a5 ; RV64I-NEXT: or a0, a0, a4 ; RV64I-NEXT: srl a1, a1, a2 -; RV64I-NEXT: slli a2, a3, 1 -; RV64I-NEXT: sll a2, a2, a5 +; RV64I-NEXT: slli a3, a3, 1 +; RV64I-NEXT: sll a2, a3, a5 ; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: ret %res = tail call i128 @llvm.fshr.i128(i128 %a, i128 %a, i128 %b) diff --git a/llvm/test/CodeGen/RISCV/split-offsets.ll b/llvm/test/CodeGen/RISCV/split-offsets.ll --- a/llvm/test/CodeGen/RISCV/split-offsets.ll +++ b/llvm/test/CodeGen/RISCV/split-offsets.ll @@ -56,19 +56,19 @@ ; RV32I-LABEL: test2: ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: li a3, 0 -; RV32I-NEXT: lw a4, 0(a0) -; RV32I-NEXT: lui a0, 20 -; RV32I-NEXT: addi a5, a0, -1920 -; RV32I-NEXT: add a0, a1, a5 -; RV32I-NEXT: add a1, a4, a5 +; RV32I-NEXT: lw a0, 0(a0) +; RV32I-NEXT: lui a4, 20 +; RV32I-NEXT: addi a4, a4, -1920 +; RV32I-NEXT: add a1, a1, a4 +; RV32I-NEXT: add a0, a0, a4 ; RV32I-NEXT: bge a3, a2, .LBB1_2 ; RV32I-NEXT: .LBB1_1: # %while_body ; RV32I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32I-NEXT: addi a4, a3, 1 -; RV32I-NEXT: sw a4, 0(a1) -; RV32I-NEXT: sw a3, 4(a1) ; RV32I-NEXT: sw a4, 0(a0) ; RV32I-NEXT: sw a3, 4(a0) +; RV32I-NEXT: sw a4, 0(a1) +; RV32I-NEXT: sw a3, 4(a1) ; RV32I-NEXT: mv a3, a4 ; RV32I-NEXT: blt a3, a2, .LBB1_1 ; RV32I-NEXT: .LBB1_2: # %while_end @@ -77,20 +77,20 @@ ; RV64I-LABEL: test2: ; RV64I: # %bb.0: # %entry ; RV64I-NEXT: li a3, 0 -; RV64I-NEXT: ld a4, 0(a0) -; RV64I-NEXT: lui a0, 20 -; RV64I-NEXT: addiw a5, a0, -1920 -; RV64I-NEXT: add a0, a1, a5 -; RV64I-NEXT: add a1, a4, a5 +; RV64I-NEXT: ld a0, 0(a0) +; RV64I-NEXT: lui a4, 20 +; RV64I-NEXT: addiw a4, a4, -1920 +; RV64I-NEXT: add a1, a1, a4 +; RV64I-NEXT: add a0, a0, a4 ; RV64I-NEXT: sext.w a2, a2 ; RV64I-NEXT: bge a3, a2, .LBB1_2 ; RV64I-NEXT: .LBB1_1: # %while_body ; RV64I-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64I-NEXT: addiw a4, a3, 1 -; RV64I-NEXT: sw a4, 0(a1) -; RV64I-NEXT: sw a3, 4(a1) ; RV64I-NEXT: sw a4, 0(a0) ; RV64I-NEXT: sw a3, 4(a0) +; RV64I-NEXT: sw a4, 0(a1) +; RV64I-NEXT: sw a3, 4(a1) ; RV64I-NEXT: mv a3, a4 ; RV64I-NEXT: blt a3, a2, .LBB1_1 ; RV64I-NEXT: .LBB1_2: # %while_end diff --git a/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll b/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll --- a/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll +++ b/llvm/test/CodeGen/RISCV/split-udiv-by-constant.ll @@ -24,8 +24,8 @@ ; RV32-NEXT: add a3, a6, a3 ; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sub a0, a1, a0 -; RV32-NEXT: mul a0, a0, a4 -; RV32-NEXT: add a1, a3, a0 +; RV32-NEXT: mul a1, a0, a4 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: mul a0, a5, a4 ; RV32-NEXT: ret ; @@ -49,8 +49,8 @@ ; RV64-NEXT: add a5, a6, a5 ; RV64-NEXT: sltu a0, a0, a3 ; RV64-NEXT: sub a0, a1, a0 -; RV64-NEXT: mul a0, a0, a2 -; RV64-NEXT: add a1, a5, a0 +; RV64-NEXT: mul a1, a0, a2 +; RV64-NEXT: add a1, a5, a1 ; RV64-NEXT: mul a0, a4, a2 ; RV64-NEXT: ret %a = udiv iXLen2 %x, 3 @@ -77,8 +77,8 @@ ; RV32-NEXT: add a3, a6, a3 ; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sub a0, a1, a0 -; RV32-NEXT: mul a0, a0, a4 -; RV32-NEXT: add a1, a3, a0 +; RV32-NEXT: mul a1, a0, a4 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: mul a0, a5, a4 ; RV32-NEXT: ret ; @@ -102,8 +102,8 @@ ; RV64-NEXT: add a5, a6, a5 ; RV64-NEXT: sltu a0, a0, a3 ; RV64-NEXT: sub a0, a1, a0 -; RV64-NEXT: mul a0, a0, a2 -; RV64-NEXT: add a1, a5, a0 +; RV64-NEXT: mul a1, a0, a2 +; RV64-NEXT: add a1, a5, a1 ; RV64-NEXT: mul a0, a4, a2 ; RV64-NEXT: ret %a = udiv iXLen2 %x, 5 @@ -184,8 +184,8 @@ ; RV32-NEXT: add a5, a6, a5 ; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sub a0, a1, a0 -; RV32-NEXT: mul a0, a0, a4 -; RV32-NEXT: add a1, a5, a0 +; RV32-NEXT: mul a1, a0, a4 +; RV32-NEXT: add a1, a5, a1 ; RV32-NEXT: mul a0, a3, a4 ; RV32-NEXT: ret ; @@ -211,8 +211,8 @@ ; RV64-NEXT: add a4, a6, a4 ; RV64-NEXT: sltu a0, a0, a2 ; RV64-NEXT: sub a0, a1, a0 -; RV64-NEXT: mul a0, a0, a5 -; RV64-NEXT: add a1, a4, a0 +; RV64-NEXT: mul a1, a0, a5 +; RV64-NEXT: add a1, a4, a1 ; RV64-NEXT: mul a0, a3, a5 ; RV64-NEXT: ret %a = udiv iXLen2 %x, 15 @@ -239,8 +239,8 @@ ; RV32-NEXT: add a3, a6, a3 ; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sub a0, a1, a0 -; RV32-NEXT: mul a0, a0, a4 -; RV32-NEXT: add a1, a3, a0 +; RV32-NEXT: mul a1, a0, a4 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: mul a0, a5, a4 ; RV32-NEXT: ret ; @@ -264,8 +264,8 @@ ; RV64-NEXT: add a5, a6, a5 ; RV64-NEXT: sltu a0, a0, a3 ; RV64-NEXT: sub a0, a1, a0 -; RV64-NEXT: mul a0, a0, a2 -; RV64-NEXT: add a1, a5, a0 +; RV64-NEXT: mul a1, a0, a2 +; RV64-NEXT: add a1, a5, a1 ; RV64-NEXT: mul a0, a4, a2 ; RV64-NEXT: ret %a = udiv iXLen2 %x, 17 @@ -294,8 +294,8 @@ ; RV32-NEXT: add a5, a6, a5 ; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sub a0, a1, a0 -; RV32-NEXT: mul a0, a0, a4 -; RV32-NEXT: add a1, a5, a0 +; RV32-NEXT: mul a1, a0, a4 +; RV32-NEXT: add a1, a5, a1 ; RV32-NEXT: mul a0, a3, a4 ; RV32-NEXT: ret ; @@ -321,8 +321,8 @@ ; RV64-NEXT: add a4, a6, a4 ; RV64-NEXT: sltu a0, a0, a2 ; RV64-NEXT: sub a0, a1, a0 -; RV64-NEXT: mul a0, a0, a5 -; RV64-NEXT: add a1, a4, a0 +; RV64-NEXT: mul a1, a0, a5 +; RV64-NEXT: add a1, a4, a1 ; RV64-NEXT: mul a0, a3, a5 ; RV64-NEXT: ret %a = udiv iXLen2 %x, 255 @@ -349,8 +349,8 @@ ; RV32-NEXT: add a3, a6, a3 ; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sub a0, a1, a0 -; RV32-NEXT: mul a0, a0, a4 -; RV32-NEXT: add a1, a3, a0 +; RV32-NEXT: mul a1, a0, a4 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: mul a0, a5, a4 ; RV32-NEXT: ret ; @@ -374,8 +374,8 @@ ; RV64-NEXT: add a5, a6, a5 ; RV64-NEXT: sltu a0, a0, a3 ; RV64-NEXT: sub a0, a1, a0 -; RV64-NEXT: mul a0, a0, a2 -; RV64-NEXT: add a1, a5, a0 +; RV64-NEXT: mul a1, a0, a2 +; RV64-NEXT: add a1, a5, a1 ; RV64-NEXT: mul a0, a4, a2 ; RV64-NEXT: ret %a = udiv iXLen2 %x, 257 @@ -436,8 +436,8 @@ ; RV64-NEXT: add a5, a6, a5 ; RV64-NEXT: sltu a0, a0, a2 ; RV64-NEXT: sub a0, a1, a0 -; RV64-NEXT: mul a0, a0, a4 -; RV64-NEXT: add a1, a5, a0 +; RV64-NEXT: mul a1, a0, a4 +; RV64-NEXT: add a1, a5, a1 ; RV64-NEXT: mul a0, a3, a4 ; RV64-NEXT: ret %a = udiv iXLen2 %x, 65535 @@ -464,8 +464,8 @@ ; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sub a0, a1, a0 ; RV32-NEXT: slli a1, a0, 16 -; RV32-NEXT: sub a0, a0, a1 -; RV32-NEXT: add a1, a4, a0 +; RV32-NEXT: sub a1, a0, a1 +; RV32-NEXT: add a1, a4, a1 ; RV32-NEXT: sub a0, a3, a5 ; RV32-NEXT: ret ; @@ -491,8 +491,8 @@ ; RV64-NEXT: add a3, a6, a3 ; RV64-NEXT: sltu a0, a0, a2 ; RV64-NEXT: sub a0, a1, a0 -; RV64-NEXT: mul a0, a0, a4 -; RV64-NEXT: add a1, a3, a0 +; RV64-NEXT: mul a1, a0, a4 +; RV64-NEXT: add a1, a3, a1 ; RV64-NEXT: mul a0, a5, a4 ; RV64-NEXT: ret %a = udiv iXLen2 %x, 65537 @@ -523,8 +523,8 @@ ; RV32-NEXT: add a3, a6, a3 ; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sub a0, a1, a0 -; RV32-NEXT: mul a0, a0, a4 -; RV32-NEXT: add a1, a3, a0 +; RV32-NEXT: mul a1, a0, a4 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: mul a0, a5, a4 ; RV32-NEXT: ret ; @@ -552,8 +552,8 @@ ; RV64-NEXT: add a5, a6, a5 ; RV64-NEXT: sltu a0, a0, a3 ; RV64-NEXT: sub a0, a1, a0 -; RV64-NEXT: mul a0, a0, a2 -; RV64-NEXT: add a1, a5, a0 +; RV64-NEXT: mul a1, a0, a2 +; RV64-NEXT: add a1, a5, a1 ; RV64-NEXT: mul a0, a4, a2 ; RV64-NEXT: ret %a = udiv iXLen2 %x, 12 diff --git a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll --- a/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll @@ -325,8 +325,8 @@ ; RV32-NEXT: srli a0, a0, 1 ; RV32-NEXT: or a0, a0, a1 ; RV32-NEXT: lw s4, 0(s0) -; RV32-NEXT: slli a1, a2, 30 -; RV32-NEXT: srli a1, a1, 31 +; RV32-NEXT: slli a2, a2, 30 +; RV32-NEXT: srli a1, a2, 31 ; RV32-NEXT: neg a1, a1 ; RV32-NEXT: li a2, 7 ; RV32-NEXT: li a3, 0 @@ -353,21 +353,21 @@ ; RV32-NEXT: seqz a3, a3 ; RV32-NEXT: or a0, a0, a1 ; RV32-NEXT: snez a0, a0 -; RV32-NEXT: addi a1, a3, -1 +; RV32-NEXT: addi a3, a3, -1 ; RV32-NEXT: addi a2, a2, -1 -; RV32-NEXT: neg a3, a0 -; RV32-NEXT: sw a3, 0(s0) -; RV32-NEXT: andi a3, a2, 7 -; RV32-NEXT: sb a3, 12(s0) -; RV32-NEXT: slli a3, a1, 1 -; RV32-NEXT: or a0, a3, a0 +; RV32-NEXT: neg a1, a0 +; RV32-NEXT: sw a1, 0(s0) +; RV32-NEXT: andi a1, a2, 7 +; RV32-NEXT: sb a1, 12(s0) +; RV32-NEXT: slli a1, a3, 1 +; RV32-NEXT: or a0, a1, a0 ; RV32-NEXT: sw a0, 4(s0) -; RV32-NEXT: srli a0, a1, 31 -; RV32-NEXT: andi a1, a1, 1 +; RV32-NEXT: srli a0, a3, 31 +; RV32-NEXT: andi a1, a3, 1 ; RV32-NEXT: slli a1, a1, 1 ; RV32-NEXT: or a0, a0, a1 -; RV32-NEXT: slli a1, a2, 2 -; RV32-NEXT: or a0, a0, a1 +; RV32-NEXT: slli a2, a2, 2 +; RV32-NEXT: or a0, a0, a2 ; RV32-NEXT: sw a0, 8(s0) ; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload @@ -400,8 +400,8 @@ ; RV64-NEXT: slli a1, a1, 62 ; RV64-NEXT: or a0, a1, a0 ; RV64-NEXT: srai a0, a0, 31 -; RV64-NEXT: slli a1, a2, 31 -; RV64-NEXT: srai s2, a1, 31 +; RV64-NEXT: slli a2, a2, 31 +; RV64-NEXT: srai s2, a2, 31 ; RV64-NEXT: li a1, 7 ; RV64-NEXT: call __moddi3@plt ; RV64-NEXT: mv s3, a0 @@ -420,10 +420,10 @@ ; RV64-NEXT: srli a0, a0, 1 ; RV64-NEXT: or a0, a0, a2 ; RV64-NEXT: sltu a0, a1, a0 -; RV64-NEXT: addi a1, s1, -2 -; RV64-NEXT: seqz a1, a1 -; RV64-NEXT: addi a2, s3, -1 -; RV64-NEXT: seqz a2, a2 +; RV64-NEXT: addi s1, s1, -2 +; RV64-NEXT: seqz a1, s1 +; RV64-NEXT: addi s3, s3, -1 +; RV64-NEXT: seqz a2, s3 ; RV64-NEXT: neg a0, a0 ; RV64-NEXT: addi a2, a2, -1 ; RV64-NEXT: addi a1, a1, -1 @@ -437,8 +437,8 @@ ; RV64-NEXT: sb a1, 12(s0) ; RV64-NEXT: slli a0, a0, 31 ; RV64-NEXT: srli a0, a0, 31 -; RV64-NEXT: slli a1, a2, 33 -; RV64-NEXT: or a0, a0, a1 +; RV64-NEXT: slli a2, a2, 33 +; RV64-NEXT: or a0, a0, a2 ; RV64-NEXT: sd a0, 0(s0) ; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload @@ -475,8 +475,8 @@ ; RV32M-NEXT: srli a0, a0, 1 ; RV32M-NEXT: or a0, a0, a1 ; RV32M-NEXT: lw s4, 0(s0) -; RV32M-NEXT: slli a1, a2, 30 -; RV32M-NEXT: srli a1, a1, 31 +; RV32M-NEXT: slli a2, a2, 30 +; RV32M-NEXT: srli a1, a2, 31 ; RV32M-NEXT: neg a1, a1 ; RV32M-NEXT: li a2, 7 ; RV32M-NEXT: li a3, 0 @@ -503,21 +503,21 @@ ; RV32M-NEXT: seqz a3, a3 ; RV32M-NEXT: or a0, a0, a1 ; RV32M-NEXT: snez a0, a0 -; RV32M-NEXT: addi a1, a3, -1 +; RV32M-NEXT: addi a3, a3, -1 ; RV32M-NEXT: addi a2, a2, -1 -; RV32M-NEXT: neg a3, a0 -; RV32M-NEXT: sw a3, 0(s0) -; RV32M-NEXT: andi a3, a2, 7 -; RV32M-NEXT: sb a3, 12(s0) -; RV32M-NEXT: slli a3, a1, 1 -; RV32M-NEXT: or a0, a3, a0 +; RV32M-NEXT: neg a1, a0 +; RV32M-NEXT: sw a1, 0(s0) +; RV32M-NEXT: andi a1, a2, 7 +; RV32M-NEXT: sb a1, 12(s0) +; RV32M-NEXT: slli a1, a3, 1 +; RV32M-NEXT: or a0, a1, a0 ; RV32M-NEXT: sw a0, 4(s0) -; RV32M-NEXT: srli a0, a1, 31 -; RV32M-NEXT: andi a1, a1, 1 +; RV32M-NEXT: srli a0, a3, 31 +; RV32M-NEXT: andi a1, a3, 1 ; RV32M-NEXT: slli a1, a1, 1 ; RV32M-NEXT: or a0, a0, a1 -; RV32M-NEXT: slli a1, a2, 2 -; RV32M-NEXT: or a0, a0, a1 +; RV32M-NEXT: slli a2, a2, 2 +; RV32M-NEXT: or a0, a0, a2 ; RV32M-NEXT: sw a0, 8(s0) ; RV32M-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32M-NEXT: lw s0, 24(sp) # 4-byte Folded Reload @@ -590,8 +590,8 @@ ; RV64M-NEXT: srli a3, a3, 62 ; RV64M-NEXT: or a1, a3, a1 ; RV64M-NEXT: sw a1, 8(a0) -; RV64M-NEXT: slli a1, a2, 29 -; RV64M-NEXT: srli a1, a1, 61 +; RV64M-NEXT: slli a2, a2, 29 +; RV64M-NEXT: srli a1, a2, 61 ; RV64M-NEXT: sb a1, 12(a0) ; RV64M-NEXT: ret ; @@ -620,8 +620,8 @@ ; RV32MV-NEXT: slli a3, a2, 30 ; RV32MV-NEXT: srli a0, a0, 2 ; RV32MV-NEXT: or s5, a0, a3 -; RV32MV-NEXT: slli a0, a2, 29 -; RV32MV-NEXT: srli a2, a0, 31 +; RV32MV-NEXT: slli a2, a2, 29 +; RV32MV-NEXT: srli a2, a2, 31 ; RV32MV-NEXT: lw a0, 0(s2) ; RV32MV-NEXT: neg s6, a2 ; RV32MV-NEXT: andi a1, a1, 1 @@ -779,10 +779,10 @@ ; RV64MV-NEXT: slli a4, a3, 33 ; RV64MV-NEXT: or a1, a1, a4 ; RV64MV-NEXT: sd a1, 0(a0) -; RV64MV-NEXT: slli a1, a2, 2 -; RV64MV-NEXT: slli a2, a3, 31 -; RV64MV-NEXT: srli a2, a2, 62 -; RV64MV-NEXT: or a1, a2, a1 +; RV64MV-NEXT: slli a2, a2, 2 +; RV64MV-NEXT: slli a3, a3, 31 +; RV64MV-NEXT: srli a1, a3, 62 +; RV64MV-NEXT: or a1, a1, a2 ; RV64MV-NEXT: sw a1, 8(a0) ; RV64MV-NEXT: addi sp, s0, -64 ; RV64MV-NEXT: ld ra, 56(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll b/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll --- a/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll +++ b/llvm/test/CodeGen/RISCV/srem-vector-lkk.ll @@ -423,12 +423,12 @@ ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: call __divsi3@plt ; RV32I-NEXT: add a0, s8, a0 -; RV32I-NEXT: add a1, s7, s2 -; RV32I-NEXT: add a2, s6, s3 -; RV32I-NEXT: add a3, s5, s4 -; RV32I-NEXT: sh a3, 6(s0) -; RV32I-NEXT: sh a2, 4(s0) -; RV32I-NEXT: sh a1, 2(s0) +; RV32I-NEXT: add s2, s7, s2 +; RV32I-NEXT: add s3, s6, s3 +; RV32I-NEXT: add s4, s5, s4 +; RV32I-NEXT: sh s4, 6(s0) +; RV32I-NEXT: sh s3, 4(s0) +; RV32I-NEXT: sh s2, 2(s0) ; RV32I-NEXT: sh a0, 0(s0) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll b/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll --- a/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll +++ b/llvm/test/CodeGen/RISCV/uadd_sat_plus.ll @@ -54,40 +54,40 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind { ; RV32I-LABEL: func64: ; RV32I: # %bb.0: -; RV32I-NEXT: add a3, a1, a5 -; RV32I-NEXT: add a2, a0, a4 -; RV32I-NEXT: sltu a0, a2, a0 -; RV32I-NEXT: add a3, a3, a0 -; RV32I-NEXT: beq a3, a1, .LBB1_2 +; RV32I-NEXT: add a2, a1, a5 +; RV32I-NEXT: add a4, a0, a4 +; RV32I-NEXT: sltu a0, a4, a0 +; RV32I-NEXT: add a2, a2, a0 +; RV32I-NEXT: beq a2, a1, .LBB1_2 ; RV32I-NEXT: # %bb.1: -; RV32I-NEXT: sltu a0, a3, a1 +; RV32I-NEXT: sltu a0, a2, a1 ; RV32I-NEXT: .LBB1_2: ; RV32I-NEXT: neg a1, a0 -; RV32I-NEXT: or a0, a1, a2 -; RV32I-NEXT: or a1, a1, a3 +; RV32I-NEXT: or a0, a1, a4 +; RV32I-NEXT: or a1, a1, a2 ; RV32I-NEXT: ret ; ; RV64I-LABEL: func64: ; RV64I: # %bb.0: -; RV64I-NEXT: add a1, a0, a2 -; RV64I-NEXT: sltu a0, a1, a0 +; RV64I-NEXT: add a2, a0, a2 +; RV64I-NEXT: sltu a0, a2, a0 ; RV64I-NEXT: neg a0, a0 -; RV64I-NEXT: or a0, a0, a1 +; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: ret ; ; RV32IZbb-LABEL: func64: ; RV32IZbb: # %bb.0: -; RV32IZbb-NEXT: add a3, a1, a5 -; RV32IZbb-NEXT: add a2, a0, a4 -; RV32IZbb-NEXT: sltu a0, a2, a0 -; RV32IZbb-NEXT: add a3, a3, a0 -; RV32IZbb-NEXT: beq a3, a1, .LBB1_2 +; RV32IZbb-NEXT: add a2, a1, a5 +; RV32IZbb-NEXT: add a4, a0, a4 +; RV32IZbb-NEXT: sltu a0, a4, a0 +; RV32IZbb-NEXT: add a2, a2, a0 +; RV32IZbb-NEXT: beq a2, a1, .LBB1_2 ; RV32IZbb-NEXT: # %bb.1: -; RV32IZbb-NEXT: sltu a0, a3, a1 +; RV32IZbb-NEXT: sltu a0, a2, a1 ; RV32IZbb-NEXT: .LBB1_2: ; RV32IZbb-NEXT: neg a1, a0 -; RV32IZbb-NEXT: or a0, a1, a2 -; RV32IZbb-NEXT: or a1, a1, a3 +; RV32IZbb-NEXT: or a0, a1, a4 +; RV32IZbb-NEXT: or a1, a1, a2 ; RV32IZbb-NEXT: ret ; ; RV64IZbb-LABEL: func64: diff --git a/llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll --- a/llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll +++ b/llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll @@ -37,11 +37,11 @@ ; RISCV32-NEXT: add s4, s3, t1 ; RISCV32-NEXT: add t1, s0, s4 ; RISCV32-NEXT: sltu t2, t1, s0 -; RISCV32-NEXT: sltu t6, s0, t6 +; RISCV32-NEXT: sltu s0, s0, t6 ; RISCV32-NEXT: sltu t4, t5, t4 ; RISCV32-NEXT: mulhu t5, t3, a2 ; RISCV32-NEXT: add t4, t5, t4 -; RISCV32-NEXT: add s0, t4, t6 +; RISCV32-NEXT: add s0, t4, s0 ; RISCV32-NEXT: mul t4, t3, t0 ; RISCV32-NEXT: mul t5, a7, a5 ; RISCV32-NEXT: add t4, t5, t4 diff --git a/llvm/test/CodeGen/RISCV/unaligned-load-store.ll b/llvm/test/CodeGen/RISCV/unaligned-load-store.ll --- a/llvm/test/CodeGen/RISCV/unaligned-load-store.ll +++ b/llvm/test/CodeGen/RISCV/unaligned-load-store.ll @@ -68,9 +68,9 @@ ; RV32I-NEXT: lbu a0, 3(a0) ; RV32I-NEXT: slli a1, a1, 8 ; RV32I-NEXT: or a1, a1, a2 -; RV32I-NEXT: slli a2, a3, 16 +; RV32I-NEXT: slli a3, a3, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a0, a0, a2 +; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: ret ; @@ -82,9 +82,9 @@ ; RV64I-NEXT: lb a0, 3(a0) ; RV64I-NEXT: slli a1, a1, 8 ; RV64I-NEXT: or a1, a1, a2 -; RV64I-NEXT: slli a2, a3, 16 +; RV64I-NEXT: slli a3, a3, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, a2 +; RV64I-NEXT: or a0, a0, a3 ; RV64I-NEXT: or a0, a0, a1 ; RV64I-NEXT: ret ; @@ -105,9 +105,9 @@ ; RV32I-NEXT: lbu a4, 3(a0) ; RV32I-NEXT: slli a1, a1, 8 ; RV32I-NEXT: or a1, a1, a2 -; RV32I-NEXT: slli a2, a3, 16 -; RV32I-NEXT: slli a3, a4, 24 -; RV32I-NEXT: or a2, a3, a2 +; RV32I-NEXT: slli a3, a3, 16 +; RV32I-NEXT: slli a4, a4, 24 +; RV32I-NEXT: or a2, a4, a3 ; RV32I-NEXT: or a2, a2, a1 ; RV32I-NEXT: lbu a1, 5(a0) ; RV32I-NEXT: lbu a3, 4(a0) @@ -115,9 +115,9 @@ ; RV32I-NEXT: lbu a0, 7(a0) ; RV32I-NEXT: slli a1, a1, 8 ; RV32I-NEXT: or a1, a1, a3 -; RV32I-NEXT: slli a3, a4, 16 +; RV32I-NEXT: slli a4, a4, 16 ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: or a0, a0, a3 +; RV32I-NEXT: or a0, a0, a4 ; RV32I-NEXT: or a1, a0, a1 ; RV32I-NEXT: mv a0, a2 ; RV32I-NEXT: ret @@ -130,9 +130,9 @@ ; RV64I-NEXT: lbu a4, 3(a0) ; RV64I-NEXT: slli a1, a1, 8 ; RV64I-NEXT: or a1, a1, a2 -; RV64I-NEXT: slli a2, a3, 16 -; RV64I-NEXT: slli a3, a4, 24 -; RV64I-NEXT: or a2, a3, a2 +; RV64I-NEXT: slli a3, a3, 16 +; RV64I-NEXT: slli a4, a4, 24 +; RV64I-NEXT: or a2, a4, a3 ; RV64I-NEXT: or a1, a2, a1 ; RV64I-NEXT: lbu a2, 5(a0) ; RV64I-NEXT: lbu a3, 4(a0) @@ -140,9 +140,9 @@ ; RV64I-NEXT: lbu a0, 7(a0) ; RV64I-NEXT: slli a2, a2, 8 ; RV64I-NEXT: or a2, a2, a3 -; RV64I-NEXT: slli a3, a4, 16 +; RV64I-NEXT: slli a4, a4, 16 ; RV64I-NEXT: slli a0, a0, 24 -; RV64I-NEXT: or a0, a0, a3 +; RV64I-NEXT: or a0, a0, a4 ; RV64I-NEXT: or a0, a0, a2 ; RV64I-NEXT: slli a0, a0, 32 ; RV64I-NEXT: or a0, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll --- a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll @@ -357,18 +357,18 @@ ; RV32-NEXT: addi a0, a0, -1463 ; RV32-NEXT: andi a0, a0, 2047 ; RV32-NEXT: sltiu a0, a0, 293 -; RV32-NEXT: addi a1, s3, -1 +; RV32-NEXT: addi s3, s3, -1 ; RV32-NEXT: addi a0, a0, -1 -; RV32-NEXT: addi a2, s1, -1 -; RV32-NEXT: slli a3, a2, 21 -; RV32-NEXT: srli a3, a3, 31 -; RV32-NEXT: sb a3, 4(s0) -; RV32-NEXT: andi a1, a1, 2047 +; RV32-NEXT: addi s1, s1, -1 +; RV32-NEXT: slli a1, s1, 21 +; RV32-NEXT: srli a1, a1, 31 +; RV32-NEXT: sb a1, 4(s0) +; RV32-NEXT: andi a1, s3, 2047 ; RV32-NEXT: andi a0, a0, 2047 ; RV32-NEXT: slli a0, a0, 11 ; RV32-NEXT: or a0, a1, a0 -; RV32-NEXT: slli a1, a2, 22 -; RV32-NEXT: or a0, a0, a1 +; RV32-NEXT: slli s1, s1, 22 +; RV32-NEXT: or a0, a0, s1 ; RV32-NEXT: sw a0, 0(s0) ; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload @@ -414,11 +414,11 @@ ; RV64-NEXT: addiw a0, a0, -1638 ; RV64-NEXT: andi a0, a0, 2047 ; RV64-NEXT: sltiu a0, a0, 2 -; RV64-NEXT: addiw a1, s3, -1 +; RV64-NEXT: addiw s3, s3, -1 ; RV64-NEXT: addi a0, a0, -1 -; RV64-NEXT: addiw a2, s2, -1 -; RV64-NEXT: andi a1, a1, 2047 -; RV64-NEXT: andi a2, a2, 2047 +; RV64-NEXT: addiw s2, s2, -1 +; RV64-NEXT: andi a1, s3, 2047 +; RV64-NEXT: andi a2, s2, 2047 ; RV64-NEXT: slli a2, a2, 11 ; RV64-NEXT: or a1, a1, a2 ; RV64-NEXT: slli a0, a0, 22 diff --git a/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll b/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll --- a/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll +++ b/llvm/test/CodeGen/RISCV/urem-vector-lkk.ll @@ -413,12 +413,12 @@ ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: call __udivsi3@plt ; RV32I-NEXT: add a0, s8, a0 -; RV32I-NEXT: add a1, s7, s2 -; RV32I-NEXT: add a2, s6, s3 -; RV32I-NEXT: add a3, s5, s4 -; RV32I-NEXT: sh a3, 6(s0) -; RV32I-NEXT: sh a2, 4(s0) -; RV32I-NEXT: sh a1, 2(s0) +; RV32I-NEXT: add s2, s7, s2 +; RV32I-NEXT: add s3, s6, s3 +; RV32I-NEXT: add s4, s5, s4 +; RV32I-NEXT: sh s4, 6(s0) +; RV32I-NEXT: sh s3, 4(s0) +; RV32I-NEXT: sh s2, 2(s0) ; RV32I-NEXT: sh a0, 0(s0) ; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll --- a/llvm/test/CodeGen/RISCV/vararg.ll +++ b/llvm/test/CodeGen/RISCV/vararg.ll @@ -459,8 +459,8 @@ ; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16 ; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; LP64-LP64F-LP64D-FPELIM-NEXT: li a0, 1023 -; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 52 +; LP64-LP64F-LP64D-FPELIM-NEXT: li a1, 1023 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 52 ; LP64-LP64F-LP64D-FPELIM-NEXT: li a2, 2 ; LP64-LP64F-LP64D-FPELIM-NEXT: call va1@plt ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -473,8 +473,8 @@ ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16 -; LP64-LP64F-LP64D-WITHFP-NEXT: li a0, 1023 -; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 52 +; LP64-LP64F-LP64D-WITHFP-NEXT: li a1, 1023 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 52 ; LP64-LP64F-LP64D-WITHFP-NEXT: li a2, 2 ; LP64-LP64F-LP64D-WITHFP-NEXT: call va1@plt ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload @@ -775,8 +775,8 @@ ; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16 ; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; LP64-LP64F-LP64D-FPELIM-NEXT: li a0, 1023 -; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a0, 52 +; LP64-LP64F-LP64D-FPELIM-NEXT: li a1, 1023 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a1, a1, 52 ; LP64-LP64F-LP64D-FPELIM-NEXT: call va2@plt ; LP64-LP64F-LP64D-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, 16 @@ -788,8 +788,8 @@ ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16 -; LP64-LP64F-LP64D-WITHFP-NEXT: li a0, 1023 -; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a0, 52 +; LP64-LP64F-LP64D-WITHFP-NEXT: li a1, 1023 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a1, a1, 52 ; LP64-LP64F-LP64D-WITHFP-NEXT: call va2@plt ; LP64-LP64F-LP64D-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; LP64-LP64F-LP64D-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload @@ -1110,8 +1110,8 @@ ; LP64-LP64F-LP64D-FPELIM: # %bb.0: ; LP64-LP64F-LP64D-FPELIM-NEXT: addi sp, sp, -16 ; LP64-LP64F-LP64D-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill -; LP64-LP64F-LP64D-FPELIM-NEXT: li a0, 1 -; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a0, 62 +; LP64-LP64F-LP64D-FPELIM-NEXT: li a2, 1 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a2, a2, 62 ; LP64-LP64F-LP64D-FPELIM-NEXT: li a0, 2 ; LP64-LP64F-LP64D-FPELIM-NEXT: li a1, 1111 ; LP64-LP64F-LP64D-FPELIM-NEXT: call va3@plt @@ -1125,8 +1125,8 @@ ; LP64-LP64F-LP64D-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; LP64-LP64F-LP64D-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill ; LP64-LP64F-LP64D-WITHFP-NEXT: addi s0, sp, 16 -; LP64-LP64F-LP64D-WITHFP-NEXT: li a0, 1 -; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a0, 62 +; LP64-LP64F-LP64D-WITHFP-NEXT: li a2, 1 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a2, a2, 62 ; LP64-LP64F-LP64D-WITHFP-NEXT: li a0, 2 ; LP64-LP64F-LP64D-WITHFP-NEXT: li a1, 1111 ; LP64-LP64F-LP64D-WITHFP-NEXT: call va3@plt @@ -1527,8 +1527,8 @@ ; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, %hi(.LCPI11_2) ; LP64-LP64F-LP64D-FPELIM-NEXT: ld a3, %lo(.LCPI11_2)(a0) ; LP64-LP64F-LP64D-FPELIM-NEXT: lui a0, 2384 -; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a0, a0, 761 -; LP64-LP64F-LP64D-FPELIM-NEXT: slli a6, a0, 11 +; LP64-LP64F-LP64D-FPELIM-NEXT: addiw a6, a0, 761 +; LP64-LP64F-LP64D-FPELIM-NEXT: slli a6, a6, 11 ; LP64-LP64F-LP64D-FPELIM-NEXT: li a0, 1 ; LP64-LP64F-LP64D-FPELIM-NEXT: li a1, 11 ; LP64-LP64F-LP64D-FPELIM-NEXT: li a4, 12 @@ -1559,8 +1559,8 @@ ; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, %hi(.LCPI11_2) ; LP64-LP64F-LP64D-WITHFP-NEXT: ld a3, %lo(.LCPI11_2)(a0) ; LP64-LP64F-LP64D-WITHFP-NEXT: lui a0, 2384 -; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a0, a0, 761 -; LP64-LP64F-LP64D-WITHFP-NEXT: slli a6, a0, 11 +; LP64-LP64F-LP64D-WITHFP-NEXT: addiw a6, a0, 761 +; LP64-LP64F-LP64D-WITHFP-NEXT: slli a6, a6, 11 ; LP64-LP64F-LP64D-WITHFP-NEXT: li a0, 1 ; LP64-LP64F-LP64D-WITHFP-NEXT: li a1, 11 ; LP64-LP64F-LP64D-WITHFP-NEXT: li a4, 12 diff --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll --- a/llvm/test/CodeGen/RISCV/xaluo.ll +++ b/llvm/test/CodeGen/RISCV/xaluo.ll @@ -4018,9 +4018,9 @@ ; RV32-LABEL: uaddo.i64.constant_2048: ; RV32: # %bb.0: # %entry ; RV32-NEXT: mv a3, a0 -; RV32-NEXT: addi a0, a0, 2047 -; RV32-NEXT: addi a4, a0, 1 -; RV32-NEXT: sltu a0, a4, a3 +; RV32-NEXT: addi a4, a0, 2047 +; RV32-NEXT: addi a4, a4, 1 +; RV32-NEXT: sltu a0, a4, a0 ; RV32-NEXT: add a5, a1, a0 ; RV32-NEXT: bgeu a4, a3, .LBB67_2 ; RV32-NEXT: # %bb.1: # %entry @@ -4041,9 +4041,9 @@ ; RV32ZBA-LABEL: uaddo.i64.constant_2048: ; RV32ZBA: # %bb.0: # %entry ; RV32ZBA-NEXT: mv a3, a0 -; RV32ZBA-NEXT: addi a0, a0, 2047 -; RV32ZBA-NEXT: addi a4, a0, 1 -; RV32ZBA-NEXT: sltu a0, a4, a3 +; RV32ZBA-NEXT: addi a4, a0, 2047 +; RV32ZBA-NEXT: addi a4, a4, 1 +; RV32ZBA-NEXT: sltu a0, a4, a0 ; RV32ZBA-NEXT: add a5, a1, a0 ; RV32ZBA-NEXT: bgeu a4, a3, .LBB67_2 ; RV32ZBA-NEXT: # %bb.1: # %entry @@ -4072,9 +4072,9 @@ ; RV32-LABEL: uaddo.i64.constant_2049: ; RV32: # %bb.0: # %entry ; RV32-NEXT: mv a3, a0 -; RV32-NEXT: addi a0, a0, 2047 -; RV32-NEXT: addi a4, a0, 2 -; RV32-NEXT: sltu a0, a4, a3 +; RV32-NEXT: addi a4, a0, 2047 +; RV32-NEXT: addi a4, a4, 2 +; RV32-NEXT: sltu a0, a4, a0 ; RV32-NEXT: add a5, a1, a0 ; RV32-NEXT: bgeu a4, a3, .LBB68_2 ; RV32-NEXT: # %bb.1: # %entry @@ -4095,9 +4095,9 @@ ; RV32ZBA-LABEL: uaddo.i64.constant_2049: ; RV32ZBA: # %bb.0: # %entry ; RV32ZBA-NEXT: mv a3, a0 -; RV32ZBA-NEXT: addi a0, a0, 2047 -; RV32ZBA-NEXT: addi a4, a0, 2 -; RV32ZBA-NEXT: sltu a0, a4, a3 +; RV32ZBA-NEXT: addi a4, a0, 2047 +; RV32ZBA-NEXT: addi a4, a4, 2 +; RV32ZBA-NEXT: sltu a0, a4, a0 ; RV32ZBA-NEXT: add a5, a1, a0 ; RV32ZBA-NEXT: bgeu a4, a3, .LBB68_2 ; RV32ZBA-NEXT: # %bb.1: # %entry diff --git a/llvm/test/CodeGen/SPARC/2011-01-11-Call.ll b/llvm/test/CodeGen/SPARC/2011-01-11-Call.ll --- a/llvm/test/CodeGen/SPARC/2011-01-11-Call.ll +++ b/llvm/test/CodeGen/SPARC/2011-01-11-Call.ll @@ -37,11 +37,9 @@ ; V8-NEXT: mov %g1, %o7 ; V9-LABEL: test_tail_call_with_return -; V9: save %sp -; V9: call foo -; V9-NEXT: nop -; V9: ret -; V9-NEXT: restore %g0, %o0, %o0 +; V9: mov %o7, %g1 +; V9-NEXT: call foo +; V9-NEXT: mov %g1, %o7 define i32 @test_tail_call_with_return() nounwind { entry: diff --git a/llvm/test/CodeGen/SPARC/tailcall.ll b/llvm/test/CodeGen/SPARC/tailcall.ll --- a/llvm/test/CodeGen/SPARC/tailcall.ll +++ b/llvm/test/CodeGen/SPARC/tailcall.ll @@ -1,46 +1,72 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=sparc -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=sparc -verify-machineinstrs | FileCheck %s --check-prefix=V8 +; RUN: llc < %s -mtriple=sparcv9 -verify-machineinstrs | FileCheck %s --check-prefix=V9 define i32 @simple_leaf(i32 %i) #0 { -; CHECK-LABEL: simple_leaf: -; CHECK: ! %bb.0: ! %entry -; CHECK-NEXT: mov %o7, %g1 -; CHECK-NEXT: call foo -; CHECK-NEXT: mov %g1, %o7 +; V8-LABEL: simple_leaf: +; V8: ! %bb.0: ! %entry +; V8-NEXT: mov %o7, %g1 +; V8-NEXT: call foo +; V8-NEXT: mov %g1, %o7 +; +; V9-LABEL: simple_leaf: +; V9: ! %bb.0: ! %entry +; V9-NEXT: mov %o7, %g1 +; V9-NEXT: call foo +; V9-NEXT: mov %g1, %o7 entry: %call = tail call i32 @foo(i32 %i) ret i32 %call } define i32 @simple_standard(i32 %i) #1 { -; CHECK-LABEL: simple_standard: -; CHECK: ! %bb.0: ! %entry -; CHECK-NEXT: save %sp, -96, %sp -; CHECK-NEXT: call foo -; CHECK-NEXT: restore +; V8-LABEL: simple_standard: +; V8: ! %bb.0: ! %entry +; V8-NEXT: save %sp, -96, %sp +; V8-NEXT: call foo +; V8-NEXT: restore +; +; V9-LABEL: simple_standard: +; V9: ! %bb.0: ! %entry +; V9-NEXT: save %sp, -128, %sp +; V9-NEXT: call foo +; V9-NEXT: restore entry: %call = tail call i32 @foo(i32 %i) ret i32 %call } define i32 @extra_arg_leaf(i32 %i) #0 { -; CHECK-LABEL: extra_arg_leaf: -; CHECK: ! %bb.0: ! %entry -; CHECK-NEXT: mov 12, %o1 -; CHECK-NEXT: mov %o7, %g1 -; CHECK-NEXT: call foo2 -; CHECK-NEXT: mov %g1, %o7 +; V8-LABEL: extra_arg_leaf: +; V8: ! %bb.0: ! %entry +; V8-NEXT: mov 12, %o1 +; V8-NEXT: mov %o7, %g1 +; V8-NEXT: call foo2 +; V8-NEXT: mov %g1, %o7 +; +; V9-LABEL: extra_arg_leaf: +; V9: ! %bb.0: ! %entry +; V9-NEXT: mov 12, %o1 +; V9-NEXT: mov %o7, %g1 +; V9-NEXT: call foo2 +; V9-NEXT: mov %g1, %o7 entry: %call = tail call i32 @foo2(i32 %i, i32 12) ret i32 %call } define i32 @extra_arg_standard(i32 %i) #1 { -; CHECK-LABEL: extra_arg_standard: -; CHECK: ! %bb.0: ! %entry -; CHECK-NEXT: save %sp, -96, %sp -; CHECK-NEXT: call foo2 -; CHECK-NEXT: restore %g0, 12, %o1 +; V8-LABEL: extra_arg_standard: +; V8: ! %bb.0: ! %entry +; V8-NEXT: save %sp, -96, %sp +; V8-NEXT: call foo2 +; V8-NEXT: restore %g0, 12, %o1 +; +; V9-LABEL: extra_arg_standard: +; V9: ! %bb.0: ! %entry +; V9-NEXT: save %sp, -128, %sp +; V9-NEXT: call foo2 +; V9-NEXT: restore %g0, 12, %o1 entry: %call = tail call i32 @foo2(i32 %i, i32 12) ret i32 %call @@ -49,17 +75,31 @@ ; Perform tail call optimization for external symbol. define void @caller_extern(i8* %src) optsize #0 { -; CHECK-LABEL: caller_extern: -; CHECK: ! %bb.0: ! %entry -; CHECK-NEXT: sethi %hi(dest), %o1 -; CHECK-NEXT: add %o1, %lo(dest), %o1 -; CHECK-NEXT: mov 7, %o2 -; CHECK-NEXT: mov %o0, %o3 -; CHECK-NEXT: mov %o1, %o0 -; CHECK-NEXT: mov %o3, %o1 -; CHECK-NEXT: mov %o7, %g1 -; CHECK-NEXT: call memcpy -; CHECK-NEXT: mov %g1, %o7 +; V8-LABEL: caller_extern: +; V8: ! %bb.0: ! %entry +; V8-NEXT: sethi %hi(dest), %o1 +; V8-NEXT: add %o1, %lo(dest), %o1 +; V8-NEXT: mov 7, %o2 +; V8-NEXT: mov %o0, %o3 +; V8-NEXT: mov %o1, %o0 +; V8-NEXT: mov %o3, %o1 +; V8-NEXT: mov %o7, %g1 +; V8-NEXT: call memcpy +; V8-NEXT: mov %g1, %o7 +; +; V9-LABEL: caller_extern: +; V9: ! %bb.0: ! %entry +; V9-NEXT: sethi %h44(dest), %o1 +; V9-NEXT: add %o1, %m44(dest), %o1 +; V9-NEXT: sllx %o1, 12, %o1 +; V9-NEXT: add %o1, %l44(dest), %o1 +; V9-NEXT: mov 7, %o2 +; V9-NEXT: mov %o0, %o3 +; V9-NEXT: mov %o1, %o0 +; V9-NEXT: mov %o3, %o1 +; V9-NEXT: mov %o7, %g1 +; V9-NEXT: call memcpy +; V9-NEXT: mov %g1, %o7 entry: tail call void @llvm.memcpy.p0i8.p0i8.i32( i8* getelementptr inbounds ([2 x i8], @@ -71,24 +111,38 @@ ; Perform tail call optimization for function pointer. define i32 @func_ptr_test(i32 ()* nocapture %func_ptr) #0 { -; CHECK-LABEL: func_ptr_test: -; CHECK: ! %bb.0: ! %entry -; CHECK-NEXT: jmp %o0 -; CHECK-NEXT: nop +; V8-LABEL: func_ptr_test: +; V8: ! %bb.0: ! %entry +; V8-NEXT: jmp %o0 +; V8-NEXT: nop +; +; V9-LABEL: func_ptr_test: +; V9: ! %bb.0: ! %entry +; V9-NEXT: jmp %o0 +; V9-NEXT: nop entry: %call = tail call i32 %func_ptr() #1 ret i32 %call } define i32 @func_ptr_test2(i32 (i32, i32, i32)* nocapture %func_ptr, -; CHECK-LABEL: func_ptr_test2: -; CHECK: ! %bb.0: ! %entry -; CHECK-NEXT: save %sp, -96, %sp -; CHECK-NEXT: mov 10, %i3 -; CHECK-NEXT: mov %i0, %i4 -; CHECK-NEXT: mov %i1, %i0 -; CHECK-NEXT: jmp %i4 -; CHECK-NEXT: restore %g0, %i3, %o1 +; V8-LABEL: func_ptr_test2: +; V8: ! %bb.0: ! %entry +; V8-NEXT: save %sp, -96, %sp +; V8-NEXT: mov 10, %i3 +; V8-NEXT: mov %i0, %i4 +; V8-NEXT: mov %i1, %i0 +; V8-NEXT: jmp %i4 +; V8-NEXT: restore %g0, %i3, %o1 +; +; V9-LABEL: func_ptr_test2: +; V9: ! %bb.0: ! %entry +; V9-NEXT: save %sp, -128, %sp +; V9-NEXT: mov 10, %i3 +; V9-NEXT: mov %i0, %i4 +; V9-NEXT: mov %i1, %i0 +; V9-NEXT: jmp %i4 +; V9-NEXT: restore %g0, %i3, %o1 i32 %r, i32 %q) #1 { entry: %call = tail call i32 %func_ptr(i32 %r, i32 10, i32 %q) #1 @@ -99,20 +153,35 @@ ; Do not tail call optimize if stack is used to pass parameters. define i32 @caller_args() #0 { -; CHECK-LABEL: caller_args: -; CHECK: ! %bb.0: ! %entry -; CHECK-NEXT: save %sp, -104, %sp -; CHECK-NEXT: mov 6, %i0 -; CHECK-NEXT: mov %g0, %o0 -; CHECK-NEXT: mov 1, %o1 -; CHECK-NEXT: mov 2, %o2 -; CHECK-NEXT: mov 3, %o3 -; CHECK-NEXT: mov 4, %o4 -; CHECK-NEXT: mov 5, %o5 -; CHECK-NEXT: call foo7 -; CHECK-NEXT: st %i0, [%sp+92] -; CHECK-NEXT: ret -; CHECK-NEXT: restore %g0, %o0, %o0 +; V8-LABEL: caller_args: +; V8: ! %bb.0: ! %entry +; V8-NEXT: save %sp, -104, %sp +; V8-NEXT: mov 6, %i0 +; V8-NEXT: mov %g0, %o0 +; V8-NEXT: mov 1, %o1 +; V8-NEXT: mov 2, %o2 +; V8-NEXT: mov 3, %o3 +; V8-NEXT: mov 4, %o4 +; V8-NEXT: mov 5, %o5 +; V8-NEXT: call foo7 +; V8-NEXT: st %i0, [%sp+92] +; V8-NEXT: ret +; V8-NEXT: restore %g0, %o0, %o0 +; +; V9-LABEL: caller_args: +; V9: ! %bb.0: ! %entry +; V9-NEXT: save %sp, -192, %sp +; V9-NEXT: mov 6, %i0 +; V9-NEXT: mov 0, %o0 +; V9-NEXT: mov 1, %o1 +; V9-NEXT: mov 2, %o2 +; V9-NEXT: mov 3, %o3 +; V9-NEXT: mov 4, %o4 +; V9-NEXT: mov 5, %o5 +; V9-NEXT: call foo7 +; V9-NEXT: stx %i0, [%sp+2223] +; V9-NEXT: ret +; V9-NEXT: restore %g0, %o0, %o0 entry: %r = tail call i32 @foo7(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6) ret i32 %r @@ -123,15 +192,23 @@ ; byval parameters. define i32 @caller_byval() #0 { -; CHECK-LABEL: caller_byval: -; CHECK: ! %bb.0: ! %entry -; CHECK-NEXT: save %sp, -104, %sp -; CHECK-NEXT: ld [%fp+-4], %i0 -; CHECK-NEXT: st %i0, [%fp+-8] -; CHECK-NEXT: call callee_byval -; CHECK-NEXT: add %fp, -8, %o0 -; CHECK-NEXT: ret -; CHECK-NEXT: restore %g0, %o0, %o0 +; V8-LABEL: caller_byval: +; V8: ! %bb.0: ! %entry +; V8-NEXT: save %sp, -104, %sp +; V8-NEXT: ld [%fp+-4], %i0 +; V8-NEXT: st %i0, [%fp+-8] +; V8-NEXT: call callee_byval +; V8-NEXT: add %fp, -8, %o0 +; V8-NEXT: ret +; V8-NEXT: restore %g0, %o0, %o0 +; +; V9-LABEL: caller_byval: +; V9: ! %bb.0: ! %entry +; V9-NEXT: save %sp, -192, %sp +; V9-NEXT: call callee_byval +; V9-NEXT: add %fp, 2039, %o0 +; V9-NEXT: ret +; V9-NEXT: restore %g0, %o0, %o0 entry: %a = alloca i32* %r = tail call i32 @callee_byval(i32** byval(i32*) %a) @@ -141,11 +218,17 @@ ; Perform tail call optimization for sret function. define void @sret_test(%struct.a* noalias sret(%struct.a) %agg.result) #0 { -; CHECK-LABEL: sret_test: -; CHECK: ! %bb.0: ! %entry -; CHECK-NEXT: mov %o7, %g1 -; CHECK-NEXT: call sret_func -; CHECK-NEXT: mov %g1, %o7 +; V8-LABEL: sret_test: +; V8: ! %bb.0: ! %entry +; V8-NEXT: mov %o7, %g1 +; V8-NEXT: call sret_func +; V8-NEXT: mov %g1, %o7 +; +; V9-LABEL: sret_test: +; V9: ! %bb.0: ! %entry +; V9-NEXT: mov %o7, %g1 +; V9-NEXT: call sret_func +; V9-NEXT: mov %g1, %o7 entry: tail call void bitcast (void (%struct.a*)* @sret_func to void (%struct.a*)*)(%struct.a* sret(%struct.a) %agg.result) @@ -157,17 +240,30 @@ ; struct will generate a memcpy as the tail function. define void @ret_large_struct(%struct.big* noalias sret(%struct.big) %agg.result) #0 { -; CHECK-LABEL: ret_large_struct: -; CHECK: ! %bb.0: ! %entry -; CHECK-NEXT: save %sp, -96, %sp -; CHECK-NEXT: ld [%fp+64], %i0 -; CHECK-NEXT: sethi %hi(bigstruct), %i1 -; CHECK-NEXT: add %i1, %lo(bigstruct), %o1 -; CHECK-NEXT: mov 400, %o2 -; CHECK-NEXT: call memcpy -; CHECK-NEXT: mov %i0, %o0 -; CHECK-NEXT: jmp %i7+12 -; CHECK-NEXT: restore +; V8-LABEL: ret_large_struct: +; V8: ! %bb.0: ! %entry +; V8-NEXT: save %sp, -96, %sp +; V8-NEXT: ld [%fp+64], %i0 +; V8-NEXT: sethi %hi(bigstruct), %i1 +; V8-NEXT: add %i1, %lo(bigstruct), %o1 +; V8-NEXT: mov 400, %o2 +; V8-NEXT: call memcpy +; V8-NEXT: mov %i0, %o0 +; V8-NEXT: jmp %i7+12 +; V8-NEXT: restore +; +; V9-LABEL: ret_large_struct: +; V9: ! %bb.0: ! %entry +; V9-NEXT: save %sp, -176, %sp +; V9-NEXT: sethi %h44(bigstruct), %i1 +; V9-NEXT: add %i1, %m44(bigstruct), %i1 +; V9-NEXT: sllx %i1, 12, %i1 +; V9-NEXT: add %i1, %l44(bigstruct), %o1 +; V9-NEXT: mov 400, %o2 +; V9-NEXT: call memcpy +; V9-NEXT: mov %i0, %o0 +; V9-NEXT: ret +; V9-NEXT: restore entry: %0 = bitcast %struct.big* %agg.result to i8* tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %0, i8* align 4 bitcast (%struct.big* @bigstruct to i8*), i32 400, i1 false) @@ -177,10 +273,17 @@ ; Test register + immediate pattern. define void @addri_test(i32 %ptr) #0 { -; CHECK-LABEL: addri_test: -; CHECK: ! %bb.0: ! %entry -; CHECK-NEXT: jmp %o0+4 -; CHECK-NEXT: nop +; V8-LABEL: addri_test: +; V8: ! %bb.0: ! %entry +; V8-NEXT: jmp %o0+4 +; V8-NEXT: nop +; +; V9-LABEL: addri_test: +; V9: ! %bb.0: ! %entry +; V9-NEXT: add %o0, 4, %o0 +; V9-NEXT: srl %o0, 0, %o0 +; V9-NEXT: jmp %o0 +; V9-NEXT: nop entry: %add = add nsw i32 %ptr, 4 %0 = inttoptr i32 %add to void ()* diff --git a/llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll b/llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll --- a/llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll +++ b/llvm/test/CodeGen/X86/avx512vl-vec-masked-cmp.ll @@ -1610,6 +1610,37 @@ } +define i32 @test_masked_vpcmpeqd_v4i1_v32i1_mask_i32(i32 %__u, <2 x i64> %__a, <2 x i64> %__b) local_unnamed_addr { +; VLX-LABEL: test_masked_vpcmpeqd_v4i1_v32i1_mask_i32: +; VLX: # %bb.0: # %entry +; VLX-NEXT: kmovd %edi, %k1 +; VLX-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 {%k1} +; VLX-NEXT: kmovb %k0, %eax +; VLX-NEXT: retq +; +; NoVLX-LABEL: test_masked_vpcmpeqd_v4i1_v32i1_mask_i32: +; NoVLX: # %bb.0: # %entry +; NoVLX-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1 +; NoVLX-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0 +; NoVLX-NEXT: kmovw %edi, %k1 +; NoVLX-NEXT: vpcmpeqd %zmm1, %zmm0, %k0 {%k1} +; NoVLX-NEXT: kmovw %k0, %eax +; NoVLX-NEXT: andl $15, %eax +; NoVLX-NEXT: vzeroupper +; NoVLX-NEXT: retq +entry: + %0 = bitcast <2 x i64> %__a to <4 x i32> + %1 = bitcast <2 x i64> %__b to <4 x i32> + %2 = icmp eq <4 x i32> %0, %1 + %3 = bitcast i32 %__u to <32 x i1> + %extract.i = shufflevector <32 x i1> %3, <32 x i1> undef, <4 x i32> + %4 = and <4 x i1> %2, %extract.i + %5 = bitcast <4 x i1> %4 to i4 + %6 = zext i4 %5 to i32 + ret i32 %6 +} + + define zeroext i64 @test_vpcmpeqd_v4i1_v64i1_mask(<2 x i64> %__a, <2 x i64> %__b) local_unnamed_addr { ; VLX-LABEL: test_vpcmpeqd_v4i1_v64i1_mask: ; VLX: # %bb.0: # %entry diff --git a/llvm/test/CodeGen/X86/combine-and.ll b/llvm/test/CodeGen/X86/combine-and.ll --- a/llvm/test/CodeGen/X86/combine-and.ll +++ b/llvm/test/CodeGen/X86/combine-and.ll @@ -1,5 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 < %s | FileCheck %s --check-prefixes=CHECK,SSE +; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx2 < %s | FileCheck %s --check-prefixes=CHECK,AVX,AVX2 +; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512dq,+avx512bw < %s | FileCheck %s --check-prefixes=CHECK,AVX,AVX512 define i32 @and_self(i32 %x) { ; CHECK-LABEL: and_self: @@ -25,140 +27,223 @@ ; define <4 x i32> @test1(<4 x i32> %A) { -; CHECK-LABEL: test1: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] -; CHECK-NEXT: retq +; SSE-LABEL: test1: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] +; SSE-NEXT: retq +; +; AVX-LABEL: test1: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } define <4 x i32> @test2(<4 x i32> %A) { -; CHECK-LABEL: test2: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3] -; CHECK-NEXT: retq +; SSE-LABEL: test2: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3] +; SSE-NEXT: retq +; +; AVX-LABEL: test2: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } define <4 x i32> @test3(<4 x i32> %A) { -; CHECK-LABEL: test3: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2],xmm1[3] -; CHECK-NEXT: retq +; SSE-LABEL: test3: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2],xmm1[3] +; SSE-NEXT: retq +; +; AVX-LABEL: test3: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2],xmm1[3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } define <4 x i32> @test4(<4 x i32> %A) { -; CHECK-LABEL: test4: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3] -; CHECK-NEXT: retq +; SSE-LABEL: test4: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3] +; SSE-NEXT: retq +; +; AVX-LABEL: test4: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } define <4 x i32> @test5(<4 x i32> %A) { -; CHECK-LABEL: test5: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] -; CHECK-NEXT: retq +; SSE-LABEL: test5: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] +; SSE-NEXT: retq +; +; AVX-LABEL: test5: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } define <4 x i32> @test6(<4 x i32> %A) { -; CHECK-LABEL: test6: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3] -; CHECK-NEXT: retq +; SSE-LABEL: test6: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3] +; SSE-NEXT: retq +; +; AVX-LABEL: test6: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } define <4 x i32> @test7(<4 x i32> %A) { -; CHECK-LABEL: test7: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] -; CHECK-NEXT: retq +; SSE-LABEL: test7: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; SSE-NEXT: retq +; +; AVX-LABEL: test7: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } define <4 x i32> @test8(<4 x i32> %A) { -; CHECK-LABEL: test8: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3] -; CHECK-NEXT: retq +; SSE-LABEL: test8: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3] +; SSE-NEXT: retq +; +; AVX-LABEL: test8: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } define <4 x i32> @test9(<4 x i32> %A) { -; CHECK-LABEL: test9: -; CHECK: # %bb.0: -; CHECK-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero -; CHECK-NEXT: retq +; SSE-LABEL: test9: +; SSE: # %bb.0: +; SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero +; SSE-NEXT: retq +; +; AVX-LABEL: test9: +; AVX: # %bb.0: +; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } define <4 x i32> @test10(<4 x i32> %A) { -; CHECK-LABEL: test10: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3] -; CHECK-NEXT: retq +; SSE-LABEL: test10: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3] +; SSE-NEXT: retq +; +; AVX-LABEL: test10: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } define <4 x i32> @test11(<4 x i32> %A) { -; CHECK-LABEL: test11: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] -; CHECK-NEXT: retq +; SSE-LABEL: test11: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; SSE-NEXT: retq +; +; AVX-LABEL: test11: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } define <4 x i32> @test12(<4 x i32> %A) { -; CHECK-LABEL: test12: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3] -; CHECK-NEXT: retq +; SSE-LABEL: test12: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3] +; SSE-NEXT: retq +; +; AVX-LABEL: test12: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } define <4 x i32> @test13(<4 x i32> %A) { -; CHECK-LABEL: test13: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3] -; CHECK-NEXT: retq +; SSE-LABEL: test13: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3] +; SSE-NEXT: retq +; +; AVX-LABEL: test13: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2],xmm0[3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } define <4 x i32> @test14(<4 x i32> %A) { -; CHECK-LABEL: test14: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] -; CHECK-NEXT: retq +; SSE-LABEL: test14: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] +; SSE-NEXT: retq +; +; AVX-LABEL: test14: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, ret <4 x i32> %1 } @@ -166,20 +251,31 @@ ; X & undef must fold to 0. So lane 0 must choose from the zero vector. define <4 x i32> @undef_lane(<4 x i32> %x) { -; CHECK-LABEL: undef_lane: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm1, %xmm1 -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3] -; CHECK-NEXT: retq +; SSE-LABEL: undef_lane: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3] +; SSE-NEXT: retq +; +; AVX-LABEL: undef_lane: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3] +; AVX-NEXT: retq %r = and <4 x i32> %x, ret <4 x i32> %r } define <4 x i32> @test15(<4 x i32> %A, <4 x i32> %B) { -; CHECK-LABEL: test15: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] -; CHECK-NEXT: retq +; SSE-LABEL: test15: +; SSE: # %bb.0: +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] +; SSE-NEXT: retq +; +; AVX-LABEL: test15: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, %2 = and <4 x i32> %B, %3 = or <4 x i32> %1, %2 @@ -187,10 +283,15 @@ } define <4 x i32> @test16(<4 x i32> %A, <4 x i32> %B) { -; CHECK-LABEL: test16: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] -; CHECK-NEXT: retq +; SSE-LABEL: test16: +; SSE: # %bb.0: +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] +; SSE-NEXT: retq +; +; AVX-LABEL: test16: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, %2 = and <4 x i32> %B, %3 = or <4 x i32> %1, %2 @@ -198,10 +299,15 @@ } define <4 x i32> @test17(<4 x i32> %A, <4 x i32> %B) { -; CHECK-LABEL: test17: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3] -; CHECK-NEXT: retq +; SSE-LABEL: test17: +; SSE: # %bb.0: +; SSE-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3] +; SSE-NEXT: retq +; +; AVX-LABEL: test17: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3] +; AVX-NEXT: retq %1 = and <4 x i32> %A, %2 = and <4 x i32> %B, %3 = or <4 x i32> %1, %2 @@ -213,30 +319,51 @@ ; define <2 x i64> @and_or_v2i64(<2 x i64> %a0) { -; CHECK-LABEL: and_or_v2i64: -; CHECK: # %bb.0: -; CHECK-NEXT: movaps {{.*#+}} xmm0 = [8,8] -; CHECK-NEXT: retq +; SSE-LABEL: and_or_v2i64: +; SSE: # %bb.0: +; SSE-NEXT: movaps {{.*#+}} xmm0 = [8,8] +; SSE-NEXT: retq +; +; AVX2-LABEL: and_or_v2i64: +; AVX2: # %bb.0: +; AVX2-NEXT: vmovaps {{.*#+}} xmm0 = [8,8] +; AVX2-NEXT: retq +; +; AVX512-LABEL: and_or_v2i64: +; AVX512: # %bb.0: +; AVX512-NEXT: vmovddup {{.*#+}} xmm0 = [8,8] +; AVX512-NEXT: # xmm0 = mem[0,0] +; AVX512-NEXT: retq %1 = or <2 x i64> %a0, %2 = and <2 x i64> %1, ret <2 x i64> %2 } define <4 x i32> @and_or_v4i32(<4 x i32> %a0) { -; CHECK-LABEL: and_or_v4i32: -; CHECK: # %bb.0: -; CHECK-NEXT: movaps {{.*#+}} xmm0 = [3,3,3,3] -; CHECK-NEXT: retq +; SSE-LABEL: and_or_v4i32: +; SSE: # %bb.0: +; SSE-NEXT: movaps {{.*#+}} xmm0 = [3,3,3,3] +; SSE-NEXT: retq +; +; AVX-LABEL: and_or_v4i32: +; AVX: # %bb.0: +; AVX-NEXT: vbroadcastss {{.*#+}} xmm0 = [3,3,3,3] +; AVX-NEXT: retq %1 = or <4 x i32> %a0, %2 = and <4 x i32> %1, ret <4 x i32> %2 } define <8 x i16> @and_or_v8i16(<8 x i16> %a0) { -; CHECK-LABEL: and_or_v8i16: -; CHECK: # %bb.0: -; CHECK-NEXT: movaps {{.*#+}} xmm0 = [15,7,3,1,14,10,2,32767] -; CHECK-NEXT: retq +; SSE-LABEL: and_or_v8i16: +; SSE: # %bb.0: +; SSE-NEXT: movaps {{.*#+}} xmm0 = [15,7,3,1,14,10,2,32767] +; SSE-NEXT: retq +; +; AVX-LABEL: and_or_v8i16: +; AVX: # %bb.0: +; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [15,7,3,1,14,10,2,32767] +; AVX-NEXT: retq %1 = or <8 x i16> %a0, %2 = and <8 x i16> %1, ret <8 x i16> %2 @@ -247,10 +374,15 @@ ; define <2 x i64> @and_or_zext_v2i32(<2 x i32> %a0) { -; CHECK-LABEL: and_or_zext_v2i32: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm0, %xmm0 -; CHECK-NEXT: retq +; SSE-LABEL: and_or_zext_v2i32: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm0, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: and_or_zext_v2i32: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; AVX-NEXT: retq %1 = zext <2 x i32> %a0 to <2 x i64> %2 = or <2 x i64> %1, %3 = and <2 x i64> %2, @@ -258,10 +390,15 @@ } define <4 x i32> @and_or_zext_v4i16(<4 x i16> %a0) { -; CHECK-LABEL: and_or_zext_v4i16: -; CHECK: # %bb.0: -; CHECK-NEXT: xorps %xmm0, %xmm0 -; CHECK-NEXT: retq +; SSE-LABEL: and_or_zext_v4i16: +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm0, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: and_or_zext_v4i16: +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; AVX-NEXT: retq %1 = zext <4 x i16> %a0 to <4 x i32> %2 = or <4 x i32> %1, %3 = and <4 x i32> %2, @@ -273,21 +410,32 @@ ; define <8 x i16> @ashr_mask1_v8i16(<8 x i16> %a0) { -; CHECK-LABEL: ashr_mask1_v8i16: -; CHECK: # %bb.0: -; CHECK-NEXT: psrlw $15, %xmm0 -; CHECK-NEXT: retq +; SSE-LABEL: ashr_mask1_v8i16: +; SSE: # %bb.0: +; SSE-NEXT: psrlw $15, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: ashr_mask1_v8i16: +; AVX: # %bb.0: +; AVX-NEXT: vpsrlw $15, %xmm0, %xmm0 +; AVX-NEXT: retq %1 = ashr <8 x i16> %a0, %2 = and <8 x i16> %1, ret <8 x i16> %2 } define <4 x i32> @ashr_mask7_v4i32(<4 x i32> %a0) { -; CHECK-LABEL: ashr_mask7_v4i32: -; CHECK: # %bb.0: -; CHECK-NEXT: psrad $31, %xmm0 -; CHECK-NEXT: psrld $29, %xmm0 -; CHECK-NEXT: retq +; SSE-LABEL: ashr_mask7_v4i32: +; SSE: # %bb.0: +; SSE-NEXT: psrad $31, %xmm0 +; SSE-NEXT: psrld $29, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: ashr_mask7_v4i32: +; AVX: # %bb.0: +; AVX-NEXT: vpsrad $31, %xmm0, %xmm0 +; AVX-NEXT: vpsrld $29, %xmm0, %xmm0 +; AVX-NEXT: retq %1 = ashr <4 x i32> %a0, %2 = and <4 x i32> %1, ret <4 x i32> %2 @@ -299,12 +447,19 @@ ; PR34620 - redundant PAND after vector shift of a byte vector (PSRLW) define <16 x i8> @PR34620(<16 x i8> %a0, <16 x i8> %a1) { -; CHECK-LABEL: PR34620: -; CHECK: # %bb.0: -; CHECK-NEXT: psrlw $1, %xmm0 -; CHECK-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; CHECK-NEXT: paddb %xmm1, %xmm0 -; CHECK-NEXT: retq +; SSE-LABEL: PR34620: +; SSE: # %bb.0: +; SSE-NEXT: psrlw $1, %xmm0 +; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE-NEXT: paddb %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: PR34620: +; AVX: # %bb.0: +; AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 +; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: vpaddb %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq %1 = lshr <16 x i8> %a0, %2 = and <16 x i8> %1, %3 = add <16 x i8> %2, %a1 diff --git a/llvm/test/CodeGen/X86/combine-mul.ll b/llvm/test/CodeGen/X86/combine-mul.ll --- a/llvm/test/CodeGen/X86/combine-mul.ll +++ b/llvm/test/CodeGen/X86/combine-mul.ll @@ -430,6 +430,130 @@ ret <4 x i32> %3 } +; PR59217 - Reuse umul_lohi/smul_lohi node + +define i64 @combine_mul_umul_lohi_i64(i64 %a, i64 %b) { +; SSE-LABEL: combine_mul_umul_lohi_i64: +; SSE: # %bb.0: +; SSE-NEXT: movq %rdi, %rax +; SSE-NEXT: mulq %rsi +; SSE-NEXT: imulq %rsi, %rdi +; SSE-NEXT: xorq %rdx, %rdi +; SSE-NEXT: movq %rdi, %rax +; SSE-NEXT: retq +; +; AVX-LABEL: combine_mul_umul_lohi_i64: +; AVX: # %bb.0: +; AVX-NEXT: movq %rdi, %rax +; AVX-NEXT: mulq %rsi +; AVX-NEXT: imulq %rsi, %rdi +; AVX-NEXT: xorq %rdx, %rdi +; AVX-NEXT: movq %rdi, %rax +; AVX-NEXT: retq + %a128 = zext i64 %a to i128 + %b128 = zext i64 %b to i128 + %m128 = mul nuw i128 %a128, %b128 + %hi128 = lshr i128 %m128, 64 + %hi = trunc i128 %hi128 to i64 + %lo = mul i64 %a, %b + %r = xor i64 %lo, %hi + ret i64 %r +} + +define i64 @combine_mul_smul_lohi_commute_i64(i64 %a, i64 %b) { +; SSE-LABEL: combine_mul_smul_lohi_commute_i64: +; SSE: # %bb.0: +; SSE-NEXT: movq %rdi, %rax +; SSE-NEXT: imulq %rsi +; SSE-NEXT: imulq %rdi, %rsi +; SSE-NEXT: xorq %rdx, %rsi +; SSE-NEXT: movq %rsi, %rax +; SSE-NEXT: retq +; +; AVX-LABEL: combine_mul_smul_lohi_commute_i64: +; AVX: # %bb.0: +; AVX-NEXT: movq %rdi, %rax +; AVX-NEXT: imulq %rsi +; AVX-NEXT: imulq %rdi, %rsi +; AVX-NEXT: xorq %rdx, %rsi +; AVX-NEXT: movq %rsi, %rax +; AVX-NEXT: retq + %a128 = sext i64 %a to i128 + %b128 = sext i64 %b to i128 + %m128 = mul nsw i128 %a128, %b128 + %hi128 = lshr i128 %m128, 64 + %hi = trunc i128 %hi128 to i64 + %lo = mul i64 %b, %a + %r = xor i64 %lo, %hi + ret i64 %r +} + +define i64 @combine_mul_umul_lohi_const_i64(i64 %h) { +; SSE-LABEL: combine_mul_umul_lohi_const_i64: +; SSE: # %bb.0: +; SSE-NEXT: movabsq $-4265267296055464877, %rcx # imm = 0xC4CEB9FE1A85EC53 +; SSE-NEXT: movq %rdi, %rax +; SSE-NEXT: mulq %rcx +; SSE-NEXT: imulq %rdi, %rcx +; SSE-NEXT: xorq %rdx, %rcx +; SSE-NEXT: movq %rcx, %rax +; SSE-NEXT: retq +; +; AVX-LABEL: combine_mul_umul_lohi_const_i64: +; AVX: # %bb.0: +; AVX-NEXT: movabsq $-4265267296055464877, %rcx # imm = 0xC4CEB9FE1A85EC53 +; AVX-NEXT: movq %rdi, %rax +; AVX-NEXT: mulq %rcx +; AVX-NEXT: imulq %rdi, %rcx +; AVX-NEXT: xorq %rdx, %rcx +; AVX-NEXT: movq %rcx, %rax +; AVX-NEXT: retq + %h128 = zext i64 %h to i128 + %m128 = mul nuw i128 %h128, 14181476777654086739 + %hi128 = lshr i128 %m128, 64 + %hi = trunc i128 %hi128 to i64 + %lo = mul i64 %h, 14181476777654086739 + %r = xor i64 %lo, %hi + ret i64 %r +} + +define i64 @combine_mul_smul_lohi_const_i64(i64 %h) { +; SSE-LABEL: combine_mul_smul_lohi_const_i64: +; SSE: # %bb.0: +; SSE-NEXT: movq %rdi, %rsi +; SSE-NEXT: sarq $63, %rsi +; SSE-NEXT: movabsq $-4265267296055464877, %rcx # imm = 0xC4CEB9FE1A85EC53 +; SSE-NEXT: movq %rdi, %rax +; SSE-NEXT: mulq %rcx +; SSE-NEXT: imulq %rcx, %rsi +; SSE-NEXT: addq %rdx, %rsi +; SSE-NEXT: imulq %rdi, %rcx +; SSE-NEXT: xorq %rsi, %rcx +; SSE-NEXT: movq %rcx, %rax +; SSE-NEXT: retq +; +; AVX-LABEL: combine_mul_smul_lohi_const_i64: +; AVX: # %bb.0: +; AVX-NEXT: movq %rdi, %rsi +; AVX-NEXT: sarq $63, %rsi +; AVX-NEXT: movabsq $-4265267296055464877, %rcx # imm = 0xC4CEB9FE1A85EC53 +; AVX-NEXT: movq %rdi, %rax +; AVX-NEXT: mulq %rcx +; AVX-NEXT: imulq %rcx, %rsi +; AVX-NEXT: addq %rdx, %rsi +; AVX-NEXT: imulq %rdi, %rcx +; AVX-NEXT: xorq %rsi, %rcx +; AVX-NEXT: movq %rcx, %rax +; AVX-NEXT: retq + %h128 = sext i64 %h to i128 + %m128 = mul nsw i128 %h128, 14181476777654086739 + %hi128 = lshr i128 %m128, 64 + %hi = trunc i128 %hi128 to i64 + %lo = mul i64 %h, 14181476777654086739 + %r = xor i64 %lo, %hi + ret i64 %r +} + ; This would infinite loop because DAGCombiner wants to turn this into a shift, ; but x86 lowering wants to avoid non-uniform vector shift amounts. diff --git a/llvm/test/CodeGen/X86/oddshuffles.ll b/llvm/test/CodeGen/X86/oddshuffles.ll --- a/llvm/test/CodeGen/X86/oddshuffles.ll +++ b/llvm/test/CodeGen/X86/oddshuffles.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2 -; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42 -; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1 +; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2 +; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE42 +; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1 ; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2,AVX2-SLOW ; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx2,+fast-variable-crosslane-shuffle,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2,AVX2-FAST,AVX2-FAST-ALL ; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+avx2,+fast-variable-perlane-shuffle | FileCheck %s --check-prefixes=AVX,AVX2,AVX2-FAST,AVX2-FAST-PERLANE -; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+xop | FileCheck %s --check-prefix=XOP +; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+xop | FileCheck %s --check-prefixes=AVX,XOP define void @v3i64(<2 x i64> %a, <2 x i64> %b, ptr %p) nounwind { ; SSE2-LABEL: v3i64: @@ -29,13 +29,6 @@ ; AVX-NEXT: vpextrq $1, %xmm0, 16(%rdi) ; AVX-NEXT: vmovdqa %xmm1, (%rdi) ; AVX-NEXT: retq -; -; XOP-LABEL: v3i64: -; XOP: # %bb.0: -; XOP-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm0[0],xmm1[0] -; XOP-NEXT: vpextrq $1, %xmm0, 16(%rdi) -; XOP-NEXT: vmovdqa %xmm1, (%rdi) -; XOP-NEXT: retq %r = shufflevector <2 x i64> %a, <2 x i64> %b, <3 x i32> store <3 x i64> %r, ptr %p ret void @@ -54,13 +47,6 @@ ; AVX-NEXT: vmovhps %xmm0, 16(%rdi) ; AVX-NEXT: vmovaps %xmm1, (%rdi) ; AVX-NEXT: retq -; -; XOP-LABEL: v3f64: -; XOP: # %bb.0: -; XOP-NEXT: vmovlhps {{.*#+}} xmm1 = xmm0[0],xmm1[0] -; XOP-NEXT: vmovhps %xmm0, 16(%rdi) -; XOP-NEXT: vmovaps %xmm1, (%rdi) -; XOP-NEXT: retq %r = shufflevector <2 x double> %a, <2 x double> %b, <3 x i32> store <3 x double> %r, ptr %p ret void @@ -88,13 +74,6 @@ ; AVX-NEXT: vextractps $1, %xmm0, 8(%rdi) ; AVX-NEXT: vmovlps %xmm1, (%rdi) ; AVX-NEXT: retq -; -; XOP-LABEL: v3i32: -; XOP: # %bb.0: -; XOP-NEXT: vunpcklps {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; XOP-NEXT: vextractps $1, %xmm0, 8(%rdi) -; XOP-NEXT: vmovlps %xmm1, (%rdi) -; XOP-NEXT: retq %r = shufflevector <2 x i32> %a, <2 x i32> %b, <3 x i32> store <3 x i32> %r, ptr %p ret void @@ -125,14 +104,6 @@ ; AVX-NEXT: vpextrw $3, %xmm0, 8(%rdi) ; AVX-NEXT: vmovq %xmm1, (%rdi) ; AVX-NEXT: retq -; -; XOP-LABEL: v5i16: -; XOP: # %bb.0: -; XOP-NEXT: vpsrlq $16, %xmm1, %xmm1 -; XOP-NEXT: vpunpcklwd {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] -; XOP-NEXT: vpextrw $3, %xmm0, 8(%rdi) -; XOP-NEXT: vmovq %xmm1, (%rdi) -; XOP-NEXT: retq %r = shufflevector <4 x i16> %a, <4 x i16> %b, <5 x i32> store <5 x i16> %r, ptr %p ret void @@ -150,37 +121,19 @@ ; ; SSE42-LABEL: v5i32: ; SSE42: # %bb.0: -; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,2,2] -; SSE42-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero -; SSE42-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] +; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,2,2,3] ; SSE42-NEXT: pextrd $3, %xmm0, 16(%rdi) -; SSE42-NEXT: movdqa %xmm2, (%rdi) +; SSE42-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE42-NEXT: movdqa %xmm0, (%rdi) ; SSE42-NEXT: retq ; -; AVX1-LABEL: v5i32: -; AVX1: # %bb.0: -; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,2,2] -; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero -; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7] -; AVX1-NEXT: vpextrd $3, %xmm0, 16(%rdi) -; AVX1-NEXT: vmovdqa %xmm1, (%rdi) -; AVX1-NEXT: retq -; -; AVX2-LABEL: v5i32: -; AVX2: # %bb.0: -; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,2,2] -; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero -; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3] -; AVX2-NEXT: vpextrd $3, %xmm0, 16(%rdi) -; AVX2-NEXT: vmovdqa %xmm1, (%rdi) -; AVX2-NEXT: retq -; -; XOP-LABEL: v5i32: -; XOP: # %bb.0: -; XOP-NEXT: vpperm {{.*#+}} xmm1 = xmm0[0,1,2,3],xmm1[4,5,6,7],xmm0[4,5,6,7],xmm1[8,9,10,11] -; XOP-NEXT: vpextrd $3, %xmm0, 16(%rdi) -; XOP-NEXT: vmovdqa %xmm1, (%rdi) -; XOP-NEXT: retq +; AVX-LABEL: v5i32: +; AVX: # %bb.0: +; AVX-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[1,2,2,3] +; AVX-NEXT: vunpcklps {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; AVX-NEXT: vextractps $3, %xmm0, 16(%rdi) +; AVX-NEXT: vmovaps %xmm1, (%rdi) +; AVX-NEXT: retq %r = shufflevector <4 x i32> %a, <4 x i32> %b, <5 x i32> store <5 x i32> %r, ptr %p ret void @@ -212,14 +165,6 @@ ; AVX-NEXT: vextractps $3, %xmm0, 16(%rdi) ; AVX-NEXT: vmovaps %xmm1, (%rdi) ; AVX-NEXT: retq -; -; XOP-LABEL: v5f32: -; XOP: # %bb.0: -; XOP-NEXT: vshufps {{.*#+}} xmm1 = xmm0[0,1],xmm1[1,2] -; XOP-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,2,1,3] -; XOP-NEXT: vextractps $3, %xmm0, 16(%rdi) -; XOP-NEXT: vmovaps %xmm1, (%rdi) -; XOP-NEXT: retq %r = shufflevector <4 x float> %a, <4 x float> %b, <5 x i32> store <5 x float> %r, ptr %p ret void @@ -253,14 +198,23 @@ ; SSE42-NEXT: movd %xmm1, (%rdi) ; SSE42-NEXT: retq ; -; AVX-LABEL: v7i8: -; AVX: # %bb.0: -; AVX-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] -; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1,4,7,4,3,6,0,u,u,u,u,u,u,u,u,u] -; AVX-NEXT: vpextrb $0, %xmm1, 6(%rdi) -; AVX-NEXT: vpextrw $2, %xmm0, 4(%rdi) -; AVX-NEXT: vmovd %xmm0, (%rdi) -; AVX-NEXT: retq +; AVX1-LABEL: v7i8: +; AVX1: # %bb.0: +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1,4,7,4,3,6,0,u,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpextrb $0, %xmm1, 6(%rdi) +; AVX1-NEXT: vpextrw $2, %xmm0, 4(%rdi) +; AVX1-NEXT: vmovd %xmm0, (%rdi) +; AVX1-NEXT: retq +; +; AVX2-LABEL: v7i8: +; AVX2: # %bb.0: +; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7] +; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[1,4,7,4,3,6,0,u,u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpextrb $0, %xmm1, 6(%rdi) +; AVX2-NEXT: vpextrw $2, %xmm0, 4(%rdi) +; AVX2-NEXT: vmovd %xmm0, (%rdi) +; AVX2-NEXT: retq ; ; XOP-LABEL: v7i8: ; XOP: # %bb.0: @@ -299,14 +253,23 @@ ; SSE42-NEXT: movq %xmm1, (%rdi) ; SSE42-NEXT: retq ; -; AVX-LABEL: v7i16: -; AVX: # %bb.0: -; AVX-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] -; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,3,8,9,14,15,8,9,6,7,12,13,0,1,14,15] -; AVX-NEXT: vpextrw $0, %xmm1, 12(%rdi) -; AVX-NEXT: vpextrd $2, %xmm0, 8(%rdi) -; AVX-NEXT: vmovq %xmm0, (%rdi) -; AVX-NEXT: retq +; AVX1-LABEL: v7i16: +; AVX1: # %bb.0: +; AVX1-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,3,8,9,14,15,8,9,6,7,12,13,0,1,14,15] +; AVX1-NEXT: vpextrw $0, %xmm1, 12(%rdi) +; AVX1-NEXT: vpextrd $2, %xmm0, 8(%rdi) +; AVX1-NEXT: vmovq %xmm0, (%rdi) +; AVX1-NEXT: retq +; +; AVX2-LABEL: v7i16: +; AVX2: # %bb.0: +; AVX2-NEXT: vpunpcklwd {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] +; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,3,8,9,14,15,8,9,6,7,12,13,0,1,14,15] +; AVX2-NEXT: vpextrw $0, %xmm1, 12(%rdi) +; AVX2-NEXT: vpextrd $2, %xmm0, 8(%rdi) +; AVX2-NEXT: vmovq %xmm0, (%rdi) +; AVX2-NEXT: retq ; ; XOP-LABEL: v7i16: ; XOP: # %bb.0: @@ -357,17 +320,6 @@ ; AVX-NEXT: vmovlps %xmm0, 16(%rdi) ; AVX-NEXT: vmovaps %xmm2, (%rdi) ; AVX-NEXT: retq -; -; XOP-LABEL: v7i32: -; XOP: # %bb.0: -; XOP-NEXT: vblendps {{.*#+}} xmm2 = xmm0[0,1],xmm1[2],xmm0[3] -; XOP-NEXT: vpermilps {{.*#+}} xmm2 = xmm2[0,2,3,2] -; XOP-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] -; XOP-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,3,2,3] -; XOP-NEXT: vmovss %xmm1, 24(%rdi) -; XOP-NEXT: vmovlps %xmm0, 16(%rdi) -; XOP-NEXT: vmovaps %xmm2, (%rdi) -; XOP-NEXT: retq %r = shufflevector <4 x i32> %a, <4 x i32> %b, <7 x i32> store <7 x i32> %r, ptr %p ret void @@ -404,13 +356,21 @@ ; SSE42-NEXT: movq %xmm0, (%rdi) ; SSE42-NEXT: retq ; -; AVX-LABEL: v12i8: -; AVX: # %bb.0: -; AVX-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] -; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,8,1,2,10,3,4,12,5,6,14,7,u,u,u,u] -; AVX-NEXT: vpextrd $2, %xmm0, 8(%rdi) -; AVX-NEXT: vmovq %xmm0, (%rdi) -; AVX-NEXT: retq +; AVX1-LABEL: v12i8: +; AVX1: # %bb.0: +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,8,1,2,10,3,4,12,5,6,14,7,u,u,u,u] +; AVX1-NEXT: vpextrd $2, %xmm0, 8(%rdi) +; AVX1-NEXT: vmovq %xmm0, (%rdi) +; AVX1-NEXT: retq +; +; AVX2-LABEL: v12i8: +; AVX2: # %bb.0: +; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] +; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,8,1,2,10,3,4,12,5,6,14,7,u,u,u,u] +; AVX2-NEXT: vpextrd $2, %xmm0, 8(%rdi) +; AVX2-NEXT: vmovq %xmm0, (%rdi) +; AVX2-NEXT: retq ; ; XOP-LABEL: v12i8: ; XOP: # %bb.0: @@ -531,20 +491,20 @@ ; ; SSE42-LABEL: v12i32: ; SSE42: # %bb.0: -; SSE42-NEXT: pshufd {{.*#+}} xmm3 = xmm1[0,0,1,1] -; SSE42-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,1,0,1] -; SSE42-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1],xmm3[2,3],xmm4[4,5,6,7] -; SSE42-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,1,0,1] -; SSE42-NEXT: pblendw {{.*#+}} xmm3 = xmm4[0,1,2,3],xmm3[4,5],xmm4[6,7] -; SSE42-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,2,2] -; SSE42-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm0[4,5],xmm4[6,7] -; SSE42-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1],xmm2[2,3],xmm4[4,5,6,7] +; SSE42-NEXT: movdqa %xmm0, %xmm3 +; SSE42-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1] +; SSE42-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,1,2,2] +; SSE42-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,1,0,1] +; SSE42-NEXT: pblendw {{.*#+}} xmm4 = xmm3[0,1,2,3],xmm4[4,5],xmm3[6,7] +; SSE42-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,2,2] +; SSE42-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1,2,3],xmm0[4,5],xmm3[6,7] +; SSE42-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0,1],xmm2[2,3],xmm3[4,5,6,7] ; SSE42-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3],xmm1[3,3] ; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,2,3] ; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7] ; SSE42-NEXT: movdqa %xmm1, 32(%rdi) -; SSE42-NEXT: movdqa %xmm4, 16(%rdi) -; SSE42-NEXT: movdqa %xmm3, (%rdi) +; SSE42-NEXT: movdqa %xmm3, 16(%rdi) +; SSE42-NEXT: movdqa %xmm4, (%rdi) ; SSE42-NEXT: retq ; ; AVX1-LABEL: v12i32: @@ -663,14 +623,23 @@ ; SSE42-NEXT: movq %xmm0, (%rdi) ; SSE42-NEXT: retq ; -; AVX-LABEL: pr29025: -; AVX: # %bb.0: -; AVX-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; AVX-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7] -; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,8,1,2,10,3,4,12,5,6,14,7,u,u,u,u] -; AVX-NEXT: vpextrd $2, %xmm0, 8(%rdi) -; AVX-NEXT: vmovq %xmm0, (%rdi) -; AVX-NEXT: retq +; AVX1-LABEL: pr29025: +; AVX1: # %bb.0: +; AVX1-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7] +; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,8,1,2,10,3,4,12,5,6,14,7,u,u,u,u] +; AVX1-NEXT: vpextrd $2, %xmm0, 8(%rdi) +; AVX1-NEXT: vmovq %xmm0, (%rdi) +; AVX1-NEXT: retq +; +; AVX2-LABEL: pr29025: +; AVX2: # %bb.0: +; AVX2-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7] +; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,8,1,2,10,3,4,12,5,6,14,7,u,u,u,u] +; AVX2-NEXT: vpextrd $2, %xmm0, 8(%rdi) +; AVX2-NEXT: vmovq %xmm0, (%rdi) +; AVX2-NEXT: retq ; ; XOP-LABEL: pr29025: ; XOP: # %bb.0: @@ -768,23 +737,41 @@ ; SSE42-NEXT: movq %xmm0, (%rcx) ; SSE42-NEXT: retq ; -; AVX-LABEL: interleave_24i8_out: -; AVX: # %bb.0: -; AVX-NEXT: vmovdqu (%rdi), %xmm0 -; AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero -; AVX-NEXT: vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,xmm1[2,5,u,u,u,u,u,u,u,u] -; AVX-NEXT: vpshufb {{.*#+}} xmm3 = xmm0[0,3,6,9,12,15],zero,zero,xmm0[u,u,u,u,u,u,u,u] -; AVX-NEXT: vpor %xmm2, %xmm3, %xmm2 -; AVX-NEXT: vpshufb {{.*#+}} xmm3 = zero,zero,zero,zero,zero,xmm1[0,3,6,u,u,u,u,u,u,u,u] -; AVX-NEXT: vpshufb {{.*#+}} xmm4 = xmm0[1,4,7,10,13],zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] -; AVX-NEXT: vpor %xmm3, %xmm4, %xmm3 -; AVX-NEXT: vpshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,xmm1[1,4,7,u,u,u,u,u,u,u,u] -; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,5,8,11,14],zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] -; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0 -; AVX-NEXT: vmovq %xmm2, (%rsi) -; AVX-NEXT: vmovq %xmm3, (%rdx) -; AVX-NEXT: vmovq %xmm0, (%rcx) -; AVX-NEXT: retq +; AVX1-LABEL: interleave_24i8_out: +; AVX1: # %bb.0: +; AVX1-NEXT: vmovdqu (%rdi), %xmm0 +; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero +; AVX1-NEXT: vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,xmm1[2,5,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpshufb {{.*#+}} xmm3 = xmm0[0,3,6,9,12,15],zero,zero,xmm0[u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpor %xmm2, %xmm3, %xmm2 +; AVX1-NEXT: vpshufb {{.*#+}} xmm3 = zero,zero,zero,zero,zero,xmm1[0,3,6,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpshufb {{.*#+}} xmm4 = xmm0[1,4,7,10,13],zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3 +; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,xmm1[1,4,7,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,5,8,11,14],zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vmovq %xmm2, (%rsi) +; AVX1-NEXT: vmovq %xmm3, (%rdx) +; AVX1-NEXT: vmovq %xmm0, (%rcx) +; AVX1-NEXT: retq +; +; AVX2-LABEL: interleave_24i8_out: +; AVX2: # %bb.0: +; AVX2-NEXT: vmovdqu (%rdi), %xmm0 +; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero +; AVX2-NEXT: vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,xmm1[2,5,u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpshufb {{.*#+}} xmm3 = xmm0[0,3,6,9,12,15],zero,zero,xmm0[u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpor %xmm2, %xmm3, %xmm2 +; AVX2-NEXT: vpshufb {{.*#+}} xmm3 = zero,zero,zero,zero,zero,xmm1[0,3,6,u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpshufb {{.*#+}} xmm4 = xmm0[1,4,7,10,13],zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpor %xmm3, %xmm4, %xmm3 +; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,xmm1[1,4,7,u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2,5,8,11,14],zero,zero,zero,xmm0[u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vmovq %xmm2, (%rsi) +; AVX2-NEXT: vmovq %xmm3, (%rdx) +; AVX2-NEXT: vmovq %xmm0, (%rcx) +; AVX2-NEXT: retq ; ; XOP-LABEL: interleave_24i8_out: ; XOP: # %bb.0: @@ -867,21 +854,37 @@ ; SSE42-NEXT: movdqu %xmm3, (%rdi) ; SSE42-NEXT: retq ; -; AVX-LABEL: interleave_24i8_in: -; AVX: # %bb.0: -; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero -; AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero -; AVX-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero -; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0] -; AVX-NEXT: vpshufb {{.*#+}} xmm2 = xmm1[0,8],zero,xmm1[1,9],zero,xmm1[2,10],zero,xmm1[3,11],zero,xmm1[4,12],zero,xmm1[5] -; AVX-NEXT: vpshufb {{.*#+}} xmm3 = zero,zero,xmm0[0],zero,zero,xmm0[1],zero,zero,xmm0[2],zero,zero,xmm0[3],zero,zero,xmm0[4],zero -; AVX-NEXT: vpor %xmm3, %xmm2, %xmm2 -; AVX-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[13],zero,xmm1[6,14],zero,xmm1[7,15],zero,xmm1[u,u,u,u,u,u,u,u] -; AVX-NEXT: vpshufb {{.*#+}} xmm0 = zero,xmm0[5],zero,zero,xmm0[6],zero,zero,xmm0[7,u,u,u,u,u,u,u,u] -; AVX-NEXT: vpor %xmm0, %xmm1, %xmm0 -; AVX-NEXT: vmovq %xmm0, 16(%rdi) -; AVX-NEXT: vmovdqu %xmm2, (%rdi) -; AVX-NEXT: retq +; AVX1-LABEL: interleave_24i8_in: +; AVX1: # %bb.0: +; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero +; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero +; AVX1-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero +; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0] +; AVX1-NEXT: vpshufb {{.*#+}} xmm2 = xmm1[0,8],zero,xmm1[1,9],zero,xmm1[2,10],zero,xmm1[3,11],zero,xmm1[4,12],zero,xmm1[5] +; AVX1-NEXT: vpshufb {{.*#+}} xmm3 = zero,zero,xmm0[0],zero,zero,xmm0[1],zero,zero,xmm0[2],zero,zero,xmm0[3],zero,zero,xmm0[4],zero +; AVX1-NEXT: vpor %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[13],zero,xmm1[6,14],zero,xmm1[7,15],zero,xmm1[u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = zero,xmm0[5],zero,zero,xmm0[6],zero,zero,xmm0[7,u,u,u,u,u,u,u,u] +; AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: vmovq %xmm0, 16(%rdi) +; AVX1-NEXT: vmovdqu %xmm2, (%rdi) +; AVX1-NEXT: retq +; +; AVX2-LABEL: interleave_24i8_in: +; AVX2: # %bb.0: +; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero +; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero +; AVX2-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero +; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0] +; AVX2-NEXT: vpshufb {{.*#+}} xmm2 = xmm1[0,8],zero,xmm1[1,9],zero,xmm1[2,10],zero,xmm1[3,11],zero,xmm1[4,12],zero,xmm1[5] +; AVX2-NEXT: vpshufb {{.*#+}} xmm3 = zero,zero,xmm0[0],zero,zero,xmm0[1],zero,zero,xmm0[2],zero,zero,xmm0[3],zero,zero,xmm0[4],zero +; AVX2-NEXT: vpor %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[13],zero,xmm1[6,14],zero,xmm1[7,15],zero,xmm1[u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = zero,xmm0[5],zero,zero,xmm0[6],zero,zero,xmm0[7,u,u,u,u,u,u,u,u] +; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0 +; AVX2-NEXT: vmovq %xmm0, 16(%rdi) +; AVX2-NEXT: vmovdqu %xmm2, (%rdi) +; AVX2-NEXT: retq ; ; XOP-LABEL: interleave_24i8_in: ; XOP: # %bb.0: @@ -1670,37 +1673,37 @@ ; SSE42-LABEL: interleave_24i32_in: ; SSE42: # %bb.0: ; SSE42-NEXT: movdqu (%rsi), %xmm0 -; SSE42-NEXT: movdqu 16(%rsi), %xmm4 -; SSE42-NEXT: movdqu (%rdx), %xmm2 -; SSE42-NEXT: movdqu 16(%rdx), %xmm5 -; SSE42-NEXT: movdqu (%rcx), %xmm3 +; SSE42-NEXT: movdqu 16(%rsi), %xmm2 +; SSE42-NEXT: movdqu (%rdx), %xmm3 +; SSE42-NEXT: movdqu 16(%rdx), %xmm4 +; SSE42-NEXT: movdqu (%rcx), %xmm5 ; SSE42-NEXT: movdqu 16(%rcx), %xmm6 -; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,0,1,1] -; SSE42-NEXT: pshufd {{.*#+}} xmm7 = xmm0[0,1,0,1] -; SSE42-NEXT: pblendw {{.*#+}} xmm7 = xmm7[0,1],xmm1[2,3],xmm7[4,5,6,7] -; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm3[0,1,0,1] +; SSE42-NEXT: movdqa %xmm0, %xmm1 +; SSE42-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] +; SSE42-NEXT: pshufd {{.*#+}} xmm7 = xmm1[0,1,2,2] +; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm5[0,1,0,1] ; SSE42-NEXT: pblendw {{.*#+}} xmm1 = xmm7[0,1,2,3],xmm1[4,5],xmm7[6,7] -; SSE42-NEXT: pshufd {{.*#+}} xmm7 = xmm5[1,1,2,2] -; SSE42-NEXT: pblendw {{.*#+}} xmm7 = xmm7[0,1,2,3],xmm4[4,5],xmm7[6,7] +; SSE42-NEXT: pshufd {{.*#+}} xmm7 = xmm4[1,1,2,2] +; SSE42-NEXT: pblendw {{.*#+}} xmm7 = xmm7[0,1,2,3],xmm2[4,5],xmm7[6,7] ; SSE42-NEXT: pblendw {{.*#+}} xmm7 = xmm7[0,1],xmm6[2,3],xmm7[4,5,6,7] -; SSE42-NEXT: pshufd {{.*#+}} xmm8 = xmm5[0,0,1,1] -; SSE42-NEXT: pshufd {{.*#+}} xmm9 = xmm4[0,1,0,1] -; SSE42-NEXT: pblendw {{.*#+}} xmm9 = xmm9[0,1],xmm8[2,3],xmm9[4,5,6,7] -; SSE42-NEXT: pshufd {{.*#+}} xmm8 = xmm6[0,1,0,1] -; SSE42-NEXT: pblendw {{.*#+}} xmm8 = xmm9[0,1,2,3],xmm8[4,5],xmm9[6,7] -; SSE42-NEXT: pshufd {{.*#+}} xmm9 = xmm2[1,1,2,2] -; SSE42-NEXT: pblendw {{.*#+}} xmm9 = xmm9[0,1,2,3],xmm0[4,5],xmm9[6,7] -; SSE42-NEXT: pblendw {{.*#+}} xmm9 = xmm9[0,1],xmm3[2,3],xmm9[4,5,6,7] -; SSE42-NEXT: shufps {{.*#+}} xmm4 = xmm4[3,3],xmm5[3,3] -; SSE42-NEXT: pshufd {{.*#+}} xmm5 = xmm6[2,3,2,3] -; SSE42-NEXT: pblendw {{.*#+}} xmm5 = xmm5[0,1],xmm4[2,3,4,5],xmm5[6,7] -; SSE42-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3],xmm2[3,3] -; SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm3[2,3,2,3] +; SSE42-NEXT: movdqa %xmm2, %xmm8 +; SSE42-NEXT: punpckldq {{.*#+}} xmm8 = xmm8[0],xmm4[0],xmm8[1],xmm4[1] +; SSE42-NEXT: pshufd {{.*#+}} xmm8 = xmm8[0,1,2,2] +; SSE42-NEXT: pshufd {{.*#+}} xmm9 = xmm6[0,1,0,1] +; SSE42-NEXT: pblendw {{.*#+}} xmm9 = xmm8[0,1,2,3],xmm9[4,5],xmm8[6,7] +; SSE42-NEXT: pshufd {{.*#+}} xmm8 = xmm3[1,1,2,2] +; SSE42-NEXT: pblendw {{.*#+}} xmm8 = xmm8[0,1,2,3],xmm0[4,5],xmm8[6,7] +; SSE42-NEXT: pblendw {{.*#+}} xmm8 = xmm8[0,1],xmm5[2,3],xmm8[4,5,6,7] +; SSE42-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3],xmm4[3,3] +; SSE42-NEXT: pshufd {{.*#+}} xmm4 = xmm6[2,3,2,3] +; SSE42-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1],xmm2[2,3,4,5],xmm4[6,7] +; SSE42-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3],xmm3[3,3] +; SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm5[2,3,2,3] ; SSE42-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3,4,5],xmm2[6,7] ; SSE42-NEXT: movdqu %xmm2, 32(%rdi) -; SSE42-NEXT: movdqu %xmm5, 80(%rdi) -; SSE42-NEXT: movdqu %xmm9, 16(%rdi) -; SSE42-NEXT: movdqu %xmm8, 48(%rdi) +; SSE42-NEXT: movdqu %xmm4, 80(%rdi) +; SSE42-NEXT: movdqu %xmm8, 16(%rdi) +; SSE42-NEXT: movdqu %xmm9, 48(%rdi) ; SSE42-NEXT: movdqu %xmm7, 64(%rdi) ; SSE42-NEXT: movdqu %xmm1, (%rdi) ; SSE42-NEXT: retq @@ -2355,15 +2358,6 @@ ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; AVX-NEXT: vmovdqu %xmm0, (%rax) ; AVX-NEXT: retq -; -; XOP-LABEL: PR41097: -; XOP: # %bb.0: -; XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero -; XOP-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,3,u,u,u,u,u,u,u,u,u,u,u,u,u,u] -; XOP-NEXT: vpmovsxbd %xmm0, %xmm0 -; XOP-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero -; XOP-NEXT: vmovdqu %xmm0, (%rax) -; XOP-NEXT: retq %wide.vec = load <6 x i8>, ptr undef, align 1 %strided.vec = shufflevector <6 x i8> %wide.vec, <6 x i8> undef, <2 x i32> %tmp = sext <2 x i8> %strided.vec to <2 x i32> diff --git a/llvm/test/CodeGen/X86/pr48215.ll b/llvm/test/CodeGen/X86/pr48215.ll --- a/llvm/test/CodeGen/X86/pr48215.ll +++ b/llvm/test/CodeGen/X86/pr48215.ll @@ -57,7 +57,6 @@ ; AVX512-NEXT: kmovw %k0, %eax ; AVX512-NEXT: movzbl %al, %ecx ; AVX512-NEXT: kmovw %k1, %eax -; AVX512-NEXT: andl $15, %eax ; AVX512-NEXT: addl %ecx, %eax ; AVX512-NEXT: vzeroupper ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll --- a/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll @@ -493,10 +493,10 @@ ; AVX2-SLOW-NEXT: vpunpckhdq {{.*#+}} xmm6 = xmm11[2],xmm9[2],xmm11[3],xmm9[3] ; AVX2-SLOW-NEXT: vinserti128 $1, %xmm6, %ymm0, %ymm5 ; AVX2-SLOW-NEXT: vmovdqa (%rcx), %xmm7 -; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm10 = xmm7[0,1,2,2] +; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm10 = xmm7[1,2,2,3] ; AVX2-SLOW-NEXT: vmovdqa (%rdx), %xmm8 -; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm12 = xmm8[1,1,2,3] -; AVX2-SLOW-NEXT: vpblendd {{.*#+}} xmm10 = xmm12[0],xmm10[1],xmm12[2],xmm10[3] +; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm12 = xmm8[1,2,2,3] +; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm10 = xmm12[0],xmm10[0],xmm12[1],xmm10[1] ; AVX2-SLOW-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,1,2,1] ; AVX2-SLOW-NEXT: vpblendd {{.*#+}} ymm5 = ymm10[0,1,2,3],ymm5[4,5],ymm10[6,7] ; AVX2-SLOW-NEXT: vmovdqa (%r8), %xmm10 @@ -574,10 +574,10 @@ ; AVX2-FAST-ALL-NEXT: vpunpckhdq {{.*#+}} xmm7 = xmm11[2],xmm10[2],xmm11[3],xmm10[3] ; AVX2-FAST-ALL-NEXT: vinserti128 $1, %xmm7, %ymm0, %ymm6 ; AVX2-FAST-ALL-NEXT: vmovdqa (%rcx), %xmm8 -; AVX2-FAST-ALL-NEXT: vpshufd {{.*#+}} xmm12 = xmm8[0,1,2,2] +; AVX2-FAST-ALL-NEXT: vpshufd {{.*#+}} xmm12 = xmm8[1,2,2,3] ; AVX2-FAST-ALL-NEXT: vmovdqa (%rdx), %xmm9 -; AVX2-FAST-ALL-NEXT: vpshufd {{.*#+}} xmm13 = xmm9[1,1,2,3] -; AVX2-FAST-ALL-NEXT: vpblendd {{.*#+}} xmm12 = xmm13[0],xmm12[1],xmm13[2],xmm12[3] +; AVX2-FAST-ALL-NEXT: vpshufd {{.*#+}} xmm13 = xmm9[1,2,2,3] +; AVX2-FAST-ALL-NEXT: vpunpckldq {{.*#+}} xmm12 = xmm13[0],xmm12[0],xmm13[1],xmm12[1] ; AVX2-FAST-ALL-NEXT: vpermq {{.*#+}} ymm12 = ymm12[0,1,2,1] ; AVX2-FAST-ALL-NEXT: vpblendd {{.*#+}} ymm6 = ymm12[0,1,2,3],ymm6[4,5],ymm12[6,7] ; AVX2-FAST-ALL-NEXT: vmovdqa (%r8), %xmm12 @@ -653,10 +653,10 @@ ; AVX2-FAST-PERLANE-NEXT: vpunpckhdq {{.*#+}} xmm6 = xmm11[2],xmm9[2],xmm11[3],xmm9[3] ; AVX2-FAST-PERLANE-NEXT: vinserti128 $1, %xmm6, %ymm0, %ymm5 ; AVX2-FAST-PERLANE-NEXT: vmovdqa (%rcx), %xmm7 -; AVX2-FAST-PERLANE-NEXT: vpshufd {{.*#+}} xmm10 = xmm7[0,1,2,2] +; AVX2-FAST-PERLANE-NEXT: vpshufd {{.*#+}} xmm10 = xmm7[1,2,2,3] ; AVX2-FAST-PERLANE-NEXT: vmovdqa (%rdx), %xmm8 -; AVX2-FAST-PERLANE-NEXT: vpshufd {{.*#+}} xmm12 = xmm8[1,1,2,3] -; AVX2-FAST-PERLANE-NEXT: vpblendd {{.*#+}} xmm10 = xmm12[0],xmm10[1],xmm12[2],xmm10[3] +; AVX2-FAST-PERLANE-NEXT: vpshufd {{.*#+}} xmm12 = xmm8[1,2,2,3] +; AVX2-FAST-PERLANE-NEXT: vpunpckldq {{.*#+}} xmm10 = xmm12[0],xmm10[0],xmm12[1],xmm10[1] ; AVX2-FAST-PERLANE-NEXT: vpermq {{.*#+}} ymm10 = ymm10[0,1,2,1] ; AVX2-FAST-PERLANE-NEXT: vpblendd {{.*#+}} ymm5 = ymm10[0,1,2,3],ymm5[4,5],ymm10[6,7] ; AVX2-FAST-PERLANE-NEXT: vmovdqa (%r8), %xmm10 @@ -1116,13 +1116,13 @@ ; AVX2-SLOW-NEXT: vmovdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; AVX2-SLOW-NEXT: vmovdqa 32(%rcx), %xmm3 ; AVX2-SLOW-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[0,1,2,2] +; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,2,2,3] ; AVX2-SLOW-NEXT: vmovdqa (%rdx), %xmm7 ; AVX2-SLOW-NEXT: vmovdqa %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; AVX2-SLOW-NEXT: vmovdqa 32(%rdx), %xmm4 ; AVX2-SLOW-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[1,1,2,3] -; AVX2-SLOW-NEXT: vpblendd {{.*#+}} xmm3 = xmm4[0],xmm3[1],xmm4[2],xmm3[3] +; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[1,2,2,3] +; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1] ; AVX2-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,1,2,1] ; AVX2-SLOW-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5],ymm3[6,7] ; AVX2-SLOW-NEXT: vmovdqa (%r8), %xmm10 @@ -1135,9 +1135,9 @@ ; AVX2-SLOW-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm1[2],xmm0[2],xmm1[3],xmm0[3] ; AVX2-SLOW-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill ; AVX2-SLOW-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 -; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm3 = xmm6[0,1,2,2] -; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm4 = xmm7[1,1,2,3] -; AVX2-SLOW-NEXT: vpblendd {{.*#+}} xmm3 = xmm4[0],xmm3[1],xmm4[2],xmm3[3] +; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm3 = xmm6[1,2,2,3] +; AVX2-SLOW-NEXT: vpshufd {{.*#+}} xmm4 = xmm7[1,2,2,3] +; AVX2-SLOW-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1] ; AVX2-SLOW-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,1,2,1] ; AVX2-SLOW-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5],ymm3[6,7] ; AVX2-SLOW-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm10[0],zero,xmm10[1],zero @@ -1296,12 +1296,12 @@ ; AVX2-FAST-ALL-NEXT: vmovdqa %xmm5, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; AVX2-FAST-ALL-NEXT: vmovdqa 32(%rcx), %xmm3 ; AVX2-FAST-ALL-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX2-FAST-ALL-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[0,1,2,2] +; AVX2-FAST-ALL-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,2,2,3] ; AVX2-FAST-ALL-NEXT: vmovdqa (%rdx), %xmm6 ; AVX2-FAST-ALL-NEXT: vmovdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; AVX2-FAST-ALL-NEXT: vmovdqa 32(%rdx), %xmm8 -; AVX2-FAST-ALL-NEXT: vpshufd {{.*#+}} xmm4 = xmm8[1,1,2,3] -; AVX2-FAST-ALL-NEXT: vpblendd {{.*#+}} xmm3 = xmm4[0],xmm3[1],xmm4[2],xmm3[3] +; AVX2-FAST-ALL-NEXT: vpshufd {{.*#+}} xmm4 = xmm8[1,2,2,3] +; AVX2-FAST-ALL-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1] ; AVX2-FAST-ALL-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,1,2,1] ; AVX2-FAST-ALL-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5],ymm3[6,7] ; AVX2-FAST-ALL-NEXT: vmovdqa (%r8), %xmm3 @@ -1314,9 +1314,9 @@ ; AVX2-FAST-ALL-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm1[2],xmm0[2],xmm1[3],xmm0[3] ; AVX2-FAST-ALL-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill ; AVX2-FAST-ALL-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 -; AVX2-FAST-ALL-NEXT: vpshufd {{.*#+}} xmm4 = xmm5[0,1,2,2] -; AVX2-FAST-ALL-NEXT: vpshufd {{.*#+}} xmm5 = xmm6[1,1,2,3] -; AVX2-FAST-ALL-NEXT: vpblendd {{.*#+}} xmm4 = xmm5[0],xmm4[1],xmm5[2],xmm4[3] +; AVX2-FAST-ALL-NEXT: vpshufd {{.*#+}} xmm4 = xmm5[1,2,2,3] +; AVX2-FAST-ALL-NEXT: vpshufd {{.*#+}} xmm5 = xmm6[1,2,2,3] +; AVX2-FAST-ALL-NEXT: vpunpckldq {{.*#+}} xmm4 = xmm5[0],xmm4[0],xmm5[1],xmm4[1] ; AVX2-FAST-ALL-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,1,2,1] ; AVX2-FAST-ALL-NEXT: vpblendd {{.*#+}} ymm2 = ymm4[0,1,2,3],ymm2[4,5],ymm4[6,7] ; AVX2-FAST-ALL-NEXT: vpmovzxdq {{.*#+}} xmm4 = xmm3[0],zero,xmm3[1],zero @@ -1470,13 +1470,13 @@ ; AVX2-FAST-PERLANE-NEXT: vmovdqa %xmm6, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; AVX2-FAST-PERLANE-NEXT: vmovdqa 32(%rcx), %xmm3 ; AVX2-FAST-PERLANE-NEXT: vmovdqa %xmm3, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX2-FAST-PERLANE-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[0,1,2,2] +; AVX2-FAST-PERLANE-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[1,2,2,3] ; AVX2-FAST-PERLANE-NEXT: vmovdqa (%rdx), %xmm7 ; AVX2-FAST-PERLANE-NEXT: vmovdqa %xmm7, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; AVX2-FAST-PERLANE-NEXT: vmovdqa 32(%rdx), %xmm4 ; AVX2-FAST-PERLANE-NEXT: vmovdqa %xmm4, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; AVX2-FAST-PERLANE-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[1,1,2,3] -; AVX2-FAST-PERLANE-NEXT: vpblendd {{.*#+}} xmm3 = xmm4[0],xmm3[1],xmm4[2],xmm3[3] +; AVX2-FAST-PERLANE-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[1,2,2,3] +; AVX2-FAST-PERLANE-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1] ; AVX2-FAST-PERLANE-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,1,2,1] ; AVX2-FAST-PERLANE-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5],ymm3[6,7] ; AVX2-FAST-PERLANE-NEXT: vmovdqa (%r8), %xmm10 @@ -1489,9 +1489,9 @@ ; AVX2-FAST-PERLANE-NEXT: vpunpckhdq {{.*#+}} xmm2 = xmm1[2],xmm0[2],xmm1[3],xmm0[3] ; AVX2-FAST-PERLANE-NEXT: vmovdqu %ymm2, {{[-0-9]+}}(%r{{[sb]}}p) # 32-byte Spill ; AVX2-FAST-PERLANE-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm2 -; AVX2-FAST-PERLANE-NEXT: vpshufd {{.*#+}} xmm3 = xmm6[0,1,2,2] -; AVX2-FAST-PERLANE-NEXT: vpshufd {{.*#+}} xmm4 = xmm7[1,1,2,3] -; AVX2-FAST-PERLANE-NEXT: vpblendd {{.*#+}} xmm3 = xmm4[0],xmm3[1],xmm4[2],xmm3[3] +; AVX2-FAST-PERLANE-NEXT: vpshufd {{.*#+}} xmm3 = xmm6[1,2,2,3] +; AVX2-FAST-PERLANE-NEXT: vpshufd {{.*#+}} xmm4 = xmm7[1,2,2,3] +; AVX2-FAST-PERLANE-NEXT: vpunpckldq {{.*#+}} xmm3 = xmm4[0],xmm3[0],xmm4[1],xmm3[1] ; AVX2-FAST-PERLANE-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,1,2,1] ; AVX2-FAST-PERLANE-NEXT: vpblendd {{.*#+}} ymm2 = ymm3[0,1,2,3],ymm2[4,5],ymm3[6,7] ; AVX2-FAST-PERLANE-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm10[0],zero,xmm10[1],zero diff --git a/llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll b/llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll --- a/llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll +++ b/llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll @@ -53,7 +53,7 @@ ; AVX512VL-NEXT: vpsllq $63, %xmm0, %xmm0 ; AVX512VL-NEXT: vptestmq %xmm0, %xmm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: testb $3, %al +; AVX512VL-NEXT: testb %al, %al ; AVX512VL-NEXT: setnp %al ; AVX512VL-NEXT: retq %a = trunc <2 x i64> %0 to <2 x i1> @@ -103,7 +103,7 @@ ; AVX512VL-NEXT: vpslld $31, %xmm0, %xmm0 ; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: testb $15, %al +; AVX512VL-NEXT: testb %al, %al ; AVX512VL-NEXT: setnp %al ; AVX512VL-NEXT: retq %a = trunc <4 x i32> %0 to <4 x i1> @@ -248,7 +248,7 @@ ; AVX512VL-NEXT: vpsllq $63, %ymm0, %ymm0 ; AVX512VL-NEXT: vptestmq %ymm0, %ymm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: testb $15, %al +; AVX512VL-NEXT: testb %al, %al ; AVX512VL-NEXT: setnp %al ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: retq @@ -956,7 +956,7 @@ ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vptestnmq %xmm0, %xmm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: testb $3, %al +; AVX512VL-NEXT: testb %al, %al ; AVX512VL-NEXT: setnp %al ; AVX512VL-NEXT: retq %a = icmp eq <2 x i64> %0, zeroinitializer @@ -1007,7 +1007,7 @@ ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vptestnmd %xmm0, %xmm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: testb $15, %al +; AVX512VL-NEXT: testb %al, %al ; AVX512VL-NEXT: setnp %al ; AVX512VL-NEXT: retq %a = icmp eq <4 x i32> %0, zeroinitializer @@ -1198,7 +1198,7 @@ ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vptestnmq %ymm0, %ymm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: testb $15, %al +; AVX512VL-NEXT: testb %al, %al ; AVX512VL-NEXT: setnp %al ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: retq @@ -1897,7 +1897,7 @@ ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpcmpeqq %xmm1, %xmm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: testb $3, %al +; AVX512VL-NEXT: testb %al, %al ; AVX512VL-NEXT: setnp %al ; AVX512VL-NEXT: retq %a = icmp eq <2 x i64> %0, %1 @@ -1948,7 +1948,7 @@ ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: testb $15, %al +; AVX512VL-NEXT: testb %al, %al ; AVX512VL-NEXT: setnp %al ; AVX512VL-NEXT: retq %a = icmp eq <4 x i32> %0, %1 @@ -2134,7 +2134,7 @@ ; AVX512VL: # %bb.0: ; AVX512VL-NEXT: vpcmpeqq %ymm1, %ymm0, %k0 ; AVX512VL-NEXT: kmovd %k0, %eax -; AVX512VL-NEXT: testb $15, %al +; AVX512VL-NEXT: testb %al, %al ; AVX512VL-NEXT: setnp %al ; AVX512VL-NEXT: vzeroupper ; AVX512VL-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll b/llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll --- a/llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll @@ -531,44 +531,17 @@ ret <4 x i32> %shuffle } define <4 x i32> @shuffle_v4i32_0451(<4 x i32> %a, <4 x i32> %b) { -; SSE2-LABEL: shuffle_v4i32_0451: -; SSE2: # %bb.0: -; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,3,2] -; SSE2-NEXT: retq -; -; SSE3-LABEL: shuffle_v4i32_0451: -; SSE3: # %bb.0: -; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,3,2] -; SSE3-NEXT: retq -; -; SSSE3-LABEL: shuffle_v4i32_0451: -; SSSE3: # %bb.0: -; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,3,2] -; SSSE3-NEXT: retq -; -; SSE41-LABEL: shuffle_v4i32_0451: -; SSE41: # %bb.0: -; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] -; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5],xmm0[6,7] -; SSE41-NEXT: retq -; -; AVX1-LABEL: shuffle_v4i32_0451: -; AVX1: # %bb.0: -; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,1,1] -; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,0,1] -; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3] -; AVX1-NEXT: retq +; SSE-LABEL: shuffle_v4i32_0451: +; SSE: # %bb.0: +; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,3,2] +; SSE-NEXT: retq ; -; AVX2-LABEL: shuffle_v4i32_0451: -; AVX2: # %bb.0: -; AVX2-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,1,1] -; AVX2-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] -; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2],xmm0[3] -; AVX2-NEXT: retq +; AVX1OR2-LABEL: shuffle_v4i32_0451: +; AVX1OR2: # %bb.0: +; AVX1OR2-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; AVX1OR2-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,1,3,2] +; AVX1OR2-NEXT: retq ; ; AVX512VL-LABEL: shuffle_v4i32_0451: ; AVX512VL: # %bb.0: @@ -593,44 +566,17 @@ ret <4 x i32> %shuffle } define <4 x i32> @shuffle_v4i32_4015(<4 x i32> %a, <4 x i32> %b) { -; SSE2-LABEL: shuffle_v4i32_4015: -; SSE2: # %bb.0: -; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,2,3] -; SSE2-NEXT: retq -; -; SSE3-LABEL: shuffle_v4i32_4015: -; SSE3: # %bb.0: -; SSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,2,3] -; SSE3-NEXT: retq -; -; SSSE3-LABEL: shuffle_v4i32_4015: -; SSSE3: # %bb.0: -; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] -; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,2,3] -; SSSE3-NEXT: retq -; -; SSE41-LABEL: shuffle_v4i32_4015: -; SSE41: # %bb.0: -; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1] -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1] -; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7] -; SSE41-NEXT: retq -; -; AVX1-LABEL: shuffle_v4i32_4015: -; AVX1: # %bb.0: -; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,1,0,1] -; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1] -; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3] -; AVX1-NEXT: retq +; SSE-LABEL: shuffle_v4i32_4015: +; SSE: # %bb.0: +; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,2,3] +; SSE-NEXT: retq ; -; AVX2-LABEL: shuffle_v4i32_4015: -; AVX2: # %bb.0: -; AVX2-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0] -; AVX2-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,1,1] -; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3] -; AVX2-NEXT: retq +; AVX1OR2-LABEL: shuffle_v4i32_4015: +; AVX1OR2: # %bb.0: +; AVX1OR2-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; AVX1OR2-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[1,0,2,3] +; AVX1OR2-NEXT: retq ; ; AVX512VL-LABEL: shuffle_v4i32_4015: ; AVX512VL: # %bb.0: diff --git a/llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll b/llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll --- a/llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll +++ b/llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll @@ -3802,8 +3802,7 @@ ; AVX1: # %bb.0: ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[2,2,2,2] -; AVX1-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3] -; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] +; AVX1-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; AVX1-NEXT: retq ; ; AVX2-LABEL: lowhalf_v8i32: diff --git a/llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll b/llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll --- a/llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll +++ b/llvm/test/DebugInfo/AMDGPU/code-pointer-size.ll @@ -18,23 +18,23 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) -define amdgpu_kernel void @kernel1(i32 addrspace(1)* %A) !dbg !7 { +define amdgpu_kernel void @kernel1(ptr addrspace(1) %A) !dbg !7 { entry: - %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5) - store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4 - call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !16, metadata !17), !dbg !18 - %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !19 - store i32 11, i32 addrspace(1)* %0, align 4, !dbg !20 + %A.addr = alloca ptr addrspace(1), align 4, addrspace(5) + store ptr addrspace(1) %A, ptr addrspace(5) %A.addr, align 4 + call void @llvm.dbg.declare(metadata ptr addrspace(5) %A.addr, metadata !16, metadata !17), !dbg !18 + %0 = load ptr addrspace(1), ptr addrspace(5) %A.addr, align 4, !dbg !19 + store i32 11, ptr addrspace(1) %0, align 4, !dbg !20 ret void, !dbg !21 } -define amdgpu_kernel void @kernel2(i32 addrspace(1)* %B) !dbg !22 { +define amdgpu_kernel void @kernel2(ptr addrspace(1) %B) !dbg !22 { entry: - %B.addr = alloca i32 addrspace(1)*, align 4, addrspace(5) - store i32 addrspace(1)* %B, i32 addrspace(1)* addrspace(5)* %B.addr, align 4 - call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %B.addr, metadata !23, metadata !17), !dbg !24 - %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %B.addr, align 4, !dbg !25 - store i32 12, i32 addrspace(1)* %0, align 4, !dbg !26 + %B.addr = alloca ptr addrspace(1), align 4, addrspace(5) + store ptr addrspace(1) %B, ptr addrspace(5) %B.addr, align 4 + call void @llvm.dbg.declare(metadata ptr addrspace(5) %B.addr, metadata !23, metadata !17), !dbg !24 + %0 = load ptr addrspace(1), ptr addrspace(5) %B.addr, align 4, !dbg !25 + store i32 12, ptr addrspace(1) %0, align 4, !dbg !26 ret void, !dbg !27 } diff --git a/llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll b/llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll --- a/llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll +++ b/llvm/test/DebugInfo/AMDGPU/dbg-value-sched-crash.ll @@ -20,18 +20,18 @@ ; CHECK-LABEL: {{^}}kernel1: define amdgpu_kernel void @kernel1( - i32 addrspace(1)* nocapture readonly %A, - i32 addrspace(1)* nocapture %B) !dbg !7 { + ptr addrspace(1) nocapture readonly %A, + ptr addrspace(1) nocapture %B) !dbg !7 { entry: - tail call void @llvm.dbg.value(metadata i32 addrspace(1)* %A, metadata !13, metadata !19), !dbg !20 - tail call void @llvm.dbg.value(metadata i32 addrspace(1)* %B, metadata !14, metadata !19), !dbg !21 - %0 = load i32, i32 addrspace(1)* %A, align 4, !dbg !22, !tbaa !24 + tail call void @llvm.dbg.value(metadata ptr addrspace(1) %A, metadata !13, metadata !19), !dbg !20 + tail call void @llvm.dbg.value(metadata ptr addrspace(1) %B, metadata !14, metadata !19), !dbg !21 + %0 = load i32, ptr addrspace(1) %A, align 4, !dbg !22, !tbaa !24 %cmp = icmp eq i32 %0, 1, !dbg !28 br i1 %cmp, label %if.then, label %if.end, !dbg !29 if.then: ; preds = %entry - store i32 12, i32 addrspace(1)* %B, align 4, !dbg !30, !tbaa !24 - %.pr = load i32, i32 addrspace(1)* %A, align 4, !dbg !32, !tbaa !24 + store i32 12, ptr addrspace(1) %B, align 4, !dbg !30, !tbaa !24 + %.pr = load i32, ptr addrspace(1) %A, align 4, !dbg !32, !tbaa !24 br label %if.end, !dbg !34 if.end: ; preds = %if.then, %entry @@ -40,7 +40,7 @@ br i1 %cmp1, label %if.then2, label %if.end3, !dbg !36 if.then2: ; preds = %if.end - store i32 13, i32 addrspace(1)* %B, align 4, !dbg !37, !tbaa !24 + store i32 13, ptr addrspace(1) %B, align 4, !dbg !37, !tbaa !24 br label %if.end3, !dbg !39 if.end3: ; preds = %if.then2, %if.end diff --git a/llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll b/llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll --- a/llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll +++ b/llvm/test/DebugInfo/AMDGPU/dwarfdump-relocs.ll @@ -19,23 +19,23 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) -define amdgpu_kernel void @kernel1(i32 addrspace(1)* %A) !dbg !7 { +define amdgpu_kernel void @kernel1(ptr addrspace(1) %A) !dbg !7 { entry: - %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5) - store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4 - call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !16, metadata !17), !dbg !18 - %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !19 - store i32 11, i32 addrspace(1)* %0, align 4, !dbg !20 + %A.addr = alloca ptr addrspace(1), align 4, addrspace(5) + store ptr addrspace(1) %A, ptr addrspace(5) %A.addr, align 4 + call void @llvm.dbg.declare(metadata ptr addrspace(5) %A.addr, metadata !16, metadata !17), !dbg !18 + %0 = load ptr addrspace(1), ptr addrspace(5) %A.addr, align 4, !dbg !19 + store i32 11, ptr addrspace(1) %0, align 4, !dbg !20 ret void, !dbg !21 } -define amdgpu_kernel void @kernel2(i32 addrspace(1)* %B) !dbg !22 { +define amdgpu_kernel void @kernel2(ptr addrspace(1) %B) !dbg !22 { entry: - %B.addr = alloca i32 addrspace(1)*, align 4, addrspace(5) - store i32 addrspace(1)* %B, i32 addrspace(1)* addrspace(5)* %B.addr, align 4 - call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %B.addr, metadata !23, metadata !17), !dbg !24 - %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %B.addr, align 4, !dbg !25 - store i32 12, i32 addrspace(1)* %0, align 4, !dbg !26 + %B.addr = alloca ptr addrspace(1), align 4, addrspace(5) + store ptr addrspace(1) %B, ptr addrspace(5) %B.addr, align 4 + call void @llvm.dbg.declare(metadata ptr addrspace(5) %B.addr, metadata !23, metadata !17), !dbg !24 + %0 = load ptr addrspace(1), ptr addrspace(5) %B.addr, align 4, !dbg !25 + store i32 12, ptr addrspace(1) %0, align 4, !dbg !26 ret void, !dbg !27 } diff --git a/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll b/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll --- a/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll +++ b/llvm/test/DebugInfo/AMDGPU/pointer-address-space.ll @@ -53,21 +53,21 @@ define amdgpu_kernel void @kernel1() !dbg !7 { entry: - %FuncVar0 = alloca i32 addrspace(1)*, align 4, addrspace(5) - %FuncVar1 = alloca i32 addrspace(4)*, align 4, addrspace(5) - %FuncVar2 = alloca i32 addrspace(3)*, align 4, addrspace(5) - %FuncVar3 = alloca i32 addrspace(5)*, align 4, addrspace(5) - %FuncVar4 = alloca i32*, align 4, addrspace(5) - call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %FuncVar0, metadata !10, metadata !13), !dbg !14 - store i32 addrspace(1)* null, i32 addrspace(1)* addrspace(5)* %FuncVar0, align 4, !dbg !14 - call void @llvm.dbg.declare(metadata i32 addrspace(4)* addrspace(5)* %FuncVar1, metadata !15, metadata !13), !dbg !16 - store i32 addrspace(4)* null, i32 addrspace(4)* addrspace(5)* %FuncVar1, align 4, !dbg !16 - call void @llvm.dbg.declare(metadata i32 addrspace(3)* addrspace(5)* %FuncVar2, metadata !17, metadata !13), !dbg !19 - store i32 addrspace(3)* addrspacecast (i32* null to i32 addrspace(3)*), i32 addrspace(3)* addrspace(5)* %FuncVar2, align 4, !dbg !19 - call void @llvm.dbg.declare(metadata i32 addrspace(5)* addrspace(5)* %FuncVar3, metadata !20, metadata !13), !dbg !22 - store i32 addrspace(5)* addrspacecast (i32* null to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %FuncVar3, align 4, !dbg !22 - call void @llvm.dbg.declare(metadata i32* addrspace(5)* %FuncVar4, metadata !23, metadata !13), !dbg !24 - store i32* null, i32* addrspace(5)* %FuncVar4, align 4, !dbg !24 + %FuncVar0 = alloca ptr addrspace(1), align 4, addrspace(5) + %FuncVar1 = alloca ptr addrspace(4), align 4, addrspace(5) + %FuncVar2 = alloca ptr addrspace(3), align 4, addrspace(5) + %FuncVar3 = alloca ptr addrspace(5), align 4, addrspace(5) + %FuncVar4 = alloca ptr, align 4, addrspace(5) + call void @llvm.dbg.declare(metadata ptr addrspace(5) %FuncVar0, metadata !10, metadata !13), !dbg !14 + store ptr addrspace(1) null, ptr addrspace(5) %FuncVar0, align 4, !dbg !14 + call void @llvm.dbg.declare(metadata ptr addrspace(5) %FuncVar1, metadata !15, metadata !13), !dbg !16 + store ptr addrspace(4) null, ptr addrspace(5) %FuncVar1, align 4, !dbg !16 + call void @llvm.dbg.declare(metadata ptr addrspace(5) %FuncVar2, metadata !17, metadata !13), !dbg !19 + store ptr addrspace(3) addrspacecast (ptr null to ptr addrspace(3)), ptr addrspace(5) %FuncVar2, align 4, !dbg !19 + call void @llvm.dbg.declare(metadata ptr addrspace(5) %FuncVar3, metadata !20, metadata !13), !dbg !22 + store ptr addrspace(5) addrspacecast (ptr null to ptr addrspace(5)), ptr addrspace(5) %FuncVar3, align 4, !dbg !22 + call void @llvm.dbg.declare(metadata ptr addrspace(5) %FuncVar4, metadata !23, metadata !13), !dbg !24 + store ptr null, ptr addrspace(5) %FuncVar4, align 4, !dbg !24 ret void, !dbg !25 } diff --git a/llvm/test/DebugInfo/AMDGPU/variable-locations.ll b/llvm/test/DebugInfo/AMDGPU/variable-locations.ll --- a/llvm/test/DebugInfo/AMDGPU/variable-locations.ll +++ b/llvm/test/DebugInfo/AMDGPU/variable-locations.ll @@ -42,33 +42,33 @@ ; CHECK: {{.*}}DW_TAG_formal_parameter ; CHECK-NEXT: DW_AT_location [DW_FORM_block1] (DW_OP_fbreg +8, DW_OP_lit1, DW_OP_swap, DW_OP_xderef) ; CHECK-NEXT: DW_AT_name {{.*}}"ArgA" - i32 addrspace(1)* %ArgA, + ptr addrspace(1) %ArgA, ; CHECK: {{.*}}DW_TAG_formal_parameter ; CHECK-NEXT: DW_AT_location [DW_FORM_block1] (DW_OP_fbreg +16, DW_OP_lit1, DW_OP_swap, DW_OP_xderef) ; CHECK-NEXT: DW_AT_name {{.*}}"ArgB" - i32 addrspace(1)* %ArgB) !dbg !13 { + ptr addrspace(1) %ArgB) !dbg !13 { entry: %ArgN.addr = alloca i32, align 4, addrspace(5) - %ArgA.addr = alloca i32 addrspace(1)*, align 4, addrspace(5) - %ArgB.addr = alloca i32 addrspace(1)*, align 4, addrspace(5) - store i32 %ArgN, i32 addrspace(5)* %ArgN.addr, align 4 - call void @llvm.dbg.declare(metadata i32 addrspace(5)* %ArgN.addr, metadata !22, metadata !23), !dbg !24 - store i32 addrspace(1)* %ArgA, i32 addrspace(1)* addrspace(5)* %ArgA.addr, align 4 - call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %ArgA.addr, metadata !25, metadata !23), !dbg !26 - store i32 addrspace(1)* %ArgB, i32 addrspace(1)* addrspace(5)* %ArgB.addr, align 4 - call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %ArgB.addr, metadata !27, metadata !23), !dbg !28 - %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %ArgB.addr, align 4, !dbg !29 - %1 = load i32, i32 addrspace(5)* %ArgN.addr, align 4, !dbg !30 + %ArgA.addr = alloca ptr addrspace(1), align 4, addrspace(5) + %ArgB.addr = alloca ptr addrspace(1), align 4, addrspace(5) + store i32 %ArgN, ptr addrspace(5) %ArgN.addr, align 4 + call void @llvm.dbg.declare(metadata ptr addrspace(5) %ArgN.addr, metadata !22, metadata !23), !dbg !24 + store ptr addrspace(1) %ArgA, ptr addrspace(5) %ArgA.addr, align 4 + call void @llvm.dbg.declare(metadata ptr addrspace(5) %ArgA.addr, metadata !25, metadata !23), !dbg !26 + store ptr addrspace(1) %ArgB, ptr addrspace(5) %ArgB.addr, align 4 + call void @llvm.dbg.declare(metadata ptr addrspace(5) %ArgB.addr, metadata !27, metadata !23), !dbg !28 + %0 = load ptr addrspace(1), ptr addrspace(5) %ArgB.addr, align 4, !dbg !29 + %1 = load i32, ptr addrspace(5) %ArgN.addr, align 4, !dbg !30 %idxprom = zext i32 %1 to i64, !dbg !29 - %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 %idxprom, !dbg !29 - %2 = load i32, i32 addrspace(1)* %arrayidx, align 4, !dbg !29 - %3 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %ArgA.addr, align 4, !dbg !31 - %4 = load i32, i32 addrspace(5)* %ArgN.addr, align 4, !dbg !32 + %arrayidx = getelementptr inbounds i32, ptr addrspace(1) %0, i64 %idxprom, !dbg !29 + %2 = load i32, ptr addrspace(1) %arrayidx, align 4, !dbg !29 + %3 = load ptr addrspace(1), ptr addrspace(5) %ArgA.addr, align 4, !dbg !31 + %4 = load i32, ptr addrspace(5) %ArgN.addr, align 4, !dbg !32 %idxprom1 = zext i32 %4 to i64, !dbg !31 - %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %3, i64 %idxprom1, !dbg !31 - %5 = load i32, i32 addrspace(1)* %arrayidx2, align 4, !dbg !33 + %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %3, i64 %idxprom1, !dbg !31 + %5 = load i32, ptr addrspace(1) %arrayidx2, align 4, !dbg !33 %add = add nsw i32 %5, %2, !dbg !33 - store i32 %add, i32 addrspace(1)* %arrayidx2, align 4, !dbg !33 + store i32 %add, ptr addrspace(1) %arrayidx2, align 4, !dbg !33 ret void, !dbg !34 } diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/instcombine/alloca-bitcast.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/instcombine/alloca-bitcast.ll --- a/llvm/test/DebugInfo/Generic/assignment-tracking/instcombine/alloca-bitcast.ll +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/instcombine/alloca-bitcast.ll @@ -23,7 +23,7 @@ ; CHECK: entry: ; CHECK-NEXT: %retval = alloca i64, align 8, !DIAssignID ![[ID:[0-9]+]] ; CHECK-NEXT: %tmpcast = bitcast i64* %retval to %struct.c* -; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef, metadata ![[e:[0-9]+]], metadata !DIExpression(), metadata ![[ID]], metadata %struct.c* %tmpcast, metadata !DIExpression()), !dbg +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef, metadata ![[e:[0-9]+]], metadata !DIExpression(), metadata ![[ID]], metadata i64* %retval, metadata !DIExpression()), !dbg ; CHECK: ![[e]] = !DILocalVariable(name: "e", target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/after-inlining.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/after-inlining.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/after-inlining.ll @@ -0,0 +1,144 @@ +; RUN: opt %s -S -passes=sroa -o - -experimental-assignment-tracking | FileCheck %s + +;; Check that SROA preserves the InlinedAt status of new dbg.assign intriniscs +;; it inserts. + +;; $cat test.c +;; typedef struct { +;; int a; +;; int b[]; +;; } c; +;; int d, e, f; +;; void g(c *h) { +;; if (d) +;; h->a = 1; +;; } +;; void i(c *h) { +;; long j = f = 0; +;; for (; f < h->a; f++) +;; j += h->b[f]; +;; e = j; +;; } +;; void k() { +;; c j; +;; g(&j); +;; i(&j); +;; } +;; void l() { k(); } +;; +;; $ clang test.c -Xclang -fexperimental-assignment-tracking -O2 -g + +; CHECK: call void @llvm.dbg.assign(metadata i1 undef, metadata !{{.+}}, metadata !DIExpression(), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg ![[DBG:[0-9]+]] + +; CHECK-DAG: ![[DBG]] = !DILocation(line: 0, scope: ![[INL_SC:[0-9]+]], inlinedAt: ![[IA:[0-9]+]]) +; CHECK-DAG: ![[IA]] = distinct !DILocation(line: 21, column: 12, scope: ![[SC:[0-9]+]]) +; CHECK-DAG: ![[SC]] = distinct !DISubprogram(name: "l", +; CHECK-DAG: ![[INL_SC]] = distinct !DISubprogram(name: "k" + +%struct.c = type { i32, [0 x i32] } + +@f = dso_local local_unnamed_addr global i32 0, align 4, !dbg !9 +@e = dso_local local_unnamed_addr global i32 0, align 4, !dbg !6 + +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) #1 +declare void @llvm.lifetime.start.p0i8(i64 immarg, ptr nocapture) #2 +declare void @llvm.lifetime.end.p0i8(i64 immarg, ptr nocapture) #2 + +define dso_local void @l() local_unnamed_addr #4 !dbg !73 { +entry: + %j.i = alloca %struct.c, align 4, !DIAssignID !74 + call void @llvm.dbg.assign(metadata i1 undef, metadata !64, metadata !DIExpression(), metadata !74, metadata ptr %j.i, metadata !DIExpression()) #5, !dbg !75 + %0 = bitcast ptr %j.i to ptr, !dbg !77 + call void @llvm.lifetime.start.p0i8(i64 4, ptr nonnull %0) #5, !dbg !77 + %arrayidx.i.i = getelementptr inbounds %struct.c, ptr %j.i, i64 0, i32 1, i64 0, !dbg !78 + %1 = load i32, ptr %arrayidx.i.i, align 4, !dbg !78 + store i32 1, ptr @f, align 4, !dbg !80 + store i32 %1, ptr @e, align 4, !dbg !81 + call void @llvm.lifetime.end.p0i8(i64 4, ptr nonnull %0) #5, !dbg !82 + ret void, !dbg !83 +} + +!llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!11, !12, !13} +!llvm.ident = !{!14} + +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) +!1 = distinct !DIGlobalVariable(name: "d", scope: !2, file: !3, line: 5, type: !8, isLocal: false, isDefinition: true) +!2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, splitDebugInlining: false, nameTableKind: None) +!3 = !DIFile(filename: "test.c", directory: "/") +!4 = !{} +!5 = !{!0, !6, !9} +!6 = !DIGlobalVariableExpression(var: !7, expr: !DIExpression()) +!7 = distinct !DIGlobalVariable(name: "e", scope: !2, file: !3, line: 5, type: !8, isLocal: false, isDefinition: true) +!8 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!9 = !DIGlobalVariableExpression(var: !10, expr: !DIExpression()) +!10 = distinct !DIGlobalVariable(name: "f", scope: !2, file: !3, line: 5, type: !8, isLocal: false, isDefinition: true) +!11 = !{i32 7, !"Dwarf Version", i32 4} +!12 = !{i32 2, !"Debug Info Version", i32 3} +!13 = !{i32 1, !"wchar_size", i32 4} +!14 = !{!"clang version 12.0.0)"} +!15 = distinct !DISubprogram(name: "g", scope: !3, file: !3, line: 6, type: !16, scopeLine: 6, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, retainedNodes: !27) +!16 = !DISubroutineType(types: !17) +!17 = !{null, !18} +!18 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !19, size: 64) +!19 = !DIDerivedType(tag: DW_TAG_typedef, name: "c", file: !3, line: 4, baseType: !20) +!20 = distinct !DICompositeType(tag: DW_TAG_structure_type, file: !3, line: 1, size: 32, elements: !21) +!21 = !{!22, !23} +!22 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !20, file: !3, line: 2, baseType: !8, size: 32) +!23 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !20, file: !3, line: 3, baseType: !24, offset: 32) +!24 = !DICompositeType(tag: DW_TAG_array_type, baseType: !8, elements: !25) +!25 = !{!26} +!26 = !DISubrange(count: -1) +!27 = !{!28} +!28 = !DILocalVariable(name: "h", arg: 1, scope: !15, file: !3, line: 6, type: !18) +!29 = !DILocation(line: 7, column: 7, scope: !30) +!30 = distinct !DILexicalBlock(scope: !15, file: !3, line: 7, column: 7) +!35 = !DILocation(line: 7, column: 7, scope: !15) +!36 = !DILocation(line: 8, column: 8, scope: !30) +!37 = !DILocation(line: 8, column: 10, scope: !30) +!38 = !DILocation(line: 8, column: 5, scope: !30) +!39 = !DILocation(line: 9, column: 1, scope: !15) +!40 = distinct !DISubprogram(name: "i", scope: !3, file: !3, line: 10, type: !16, scopeLine: 10, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, retainedNodes: !41) +!41 = !{!42, !43} +!42 = !DILocalVariable(name: "h", arg: 1, scope: !40, file: !3, line: 10, type: !18) +!43 = !DILocalVariable(name: "j", scope: !40, file: !3, line: 11, type: !44) +!44 = !DIBasicType(name: "long int", size: 64, encoding: DW_ATE_signed) +!45 = !DILocation(line: 0, scope: !40) +!46 = !DILocation(line: 12, column: 17, scope: !47) +!47 = distinct !DILexicalBlock(scope: !48, file: !3, line: 12, column: 3) +!48 = distinct !DILexicalBlock(scope: !40, file: !3, line: 12, column: 3) +!49 = !DILocation(line: 12, column: 12, scope: !47) +!50 = !DILocation(line: 12, column: 3, scope: !48) +!51 = !DILocation(line: 13, column: 10, scope: !47) +!52 = !DILocation(line: 13, column: 7, scope: !47) +!53 = !DILocation(line: 12, column: 21, scope: !47) +!54 = distinct !{!54, !50, !55, !56} +!55 = !DILocation(line: 13, column: 16, scope: !48) +!56 = !{!"llvm.loop.mustprogress"} +!57 = !DILocation(line: 14, column: 7, scope: !40) +!58 = !DILocation(line: 14, column: 5, scope: !40) +!59 = !DILocation(line: 15, column: 1, scope: !40) +!60 = distinct !DISubprogram(name: "k", scope: !3, file: !3, line: 16, type: !61, scopeLine: 16, flags: DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, retainedNodes: !63) +!61 = !DISubroutineType(types: !62) +!62 = !{null} +!63 = !{!64} +!64 = !DILocalVariable(name: "j", scope: !60, file: !3, line: 17, type: !19) +!65 = distinct !DIAssignID() +!66 = !DILocation(line: 0, scope: !60) +!67 = !DILocation(line: 17, column: 3, scope: !60) +!68 = !DILocation(line: 13, column: 10, scope: !47, inlinedAt: !69) +!69 = distinct !DILocation(line: 19, column: 3, scope: !60) +!70 = !DILocation(line: 0, scope: !40, inlinedAt: !69) +!71 = !DILocation(line: 14, column: 5, scope: !40, inlinedAt: !69) +!72 = !DILocation(line: 20, column: 1, scope: !60) +!73 = distinct !DISubprogram(name: "l", scope: !3, file: !3, line: 21, type: !61, scopeLine: 21, flags: DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, retainedNodes: !4) +!74 = distinct !DIAssignID() +!75 = !DILocation(line: 0, scope: !60, inlinedAt: !76) +!76 = distinct !DILocation(line: 21, column: 12, scope: !73) +!77 = !DILocation(line: 17, column: 3, scope: !60, inlinedAt: !76) +!78 = !DILocation(line: 13, column: 10, scope: !47, inlinedAt: !79) +!79 = distinct !DILocation(line: 19, column: 3, scope: !60, inlinedAt: !76) +!80 = !DILocation(line: 0, scope: !40, inlinedAt: !79) +!81 = !DILocation(line: 14, column: 5, scope: !40, inlinedAt: !79) +!82 = !DILocation(line: 20, column: 1, scope: !60, inlinedAt: !76) +!83 = !DILocation(line: 21, column: 17, scope: !73) diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/alloca-single-slice.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/alloca-single-slice.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/alloca-single-slice.ll @@ -0,0 +1,82 @@ +; RUN: opt -passes=sroa,verify -S %s -o - -experimental-assignment-tracking \ +; RUN: | FileCheck %s --implicit-check-not="call void @llvm.dbg" + +; Check that single sliced allocas retain their assignment tracking debug info. + +;; $ cat test.c +;; struct a { +;; char b[8]; +;; }; +;; int c; +;; void d() { +;; struct a a; +;; memcpy(a.b, 0, c); +;; } +;; $ clang test.c -Xclang -disable-llvm-passes -O2 -g -c -S -emit-llvm -o - \ +;; | opt -passes=declare-to-assign -S -o - + +; CHECK: entry: +; CHECK-NEXT: %a.sroa.0 = alloca i64, align 8, !DIAssignID ![[ID_1:[0-9]+]] +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef, metadata ![[VAR:[0-9]+]], metadata !DIExpression(), metadata ![[ID_1]], metadata ptr %a.sroa.0, metadata !DIExpression()), !dbg + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + +%struct.a = type { [8 x i8] } + +@c = dso_local global i32 0, align 4, !dbg !0 + +define dso_local void @d() !dbg !11 { +entry: + %a = alloca %struct.a, align 1, !DIAssignID !23 + call void @llvm.dbg.assign(metadata i1 undef, metadata !15, metadata !DIExpression(), metadata !23, metadata ptr %a, metadata !DIExpression()), !dbg !24 + %0 = bitcast ptr %a to ptr, !dbg !25 + call void @llvm.lifetime.start.p0i8(i64 8, ptr %0), !dbg !25 + %b = getelementptr inbounds %struct.a, ptr %a, i32 0, i32 0, !dbg !26 + %arraydecay = getelementptr inbounds [8 x i8], ptr %b, i64 0, i64 0, !dbg !27 + %1 = load i32, ptr @c, align 4, !dbg !28 + %conv = sext i32 %1 to i64, !dbg !28 + call void @llvm.memcpy.p0i8.p0i8.i64(ptr align 1 %arraydecay, ptr align 1 null, i64 %conv, i1 false), !dbg !27 + %2 = bitcast ptr %a to ptr, !dbg !33 + call void @llvm.lifetime.end.p0i8(i64 8, ptr %2), !dbg !33 + ret void, !dbg !33 +} + +declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg) +declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) + +!llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!7, !8, !9} +!llvm.ident = !{!10} + +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) +!1 = distinct !DIGlobalVariable(name: "c", scope: !2, file: !3, line: 4, type: !6, isLocal: false, isDefinition: true) +!2 = distinct !DICompileUnit(language: DW_LANG_C99, file: !3, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, splitDebugInlining: false, nameTableKind: None) +!3 = !DIFile(filename: "test.c", directory: "/") +!4 = !{} +!5 = !{!0} +!6 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!7 = !{i32 7, !"Dwarf Version", i32 4} +!8 = !{i32 2, !"Debug Info Version", i32 3} +!9 = !{i32 1, !"wchar_size", i32 4} +!10 = !{!"clang version 12.0.0"} +!11 = distinct !DISubprogram(name: "d", scope: !3, file: !3, line: 5, type: !12, scopeLine: 5, flags: DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, retainedNodes: !14) +!12 = !DISubroutineType(types: !13) +!13 = !{null} +!14 = !{!15} +!15 = !DILocalVariable(name: "a", scope: !11, file: !3, line: 6, type: !16) +!16 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "a", file: !3, line: 1, size: 64, elements: !17) +!17 = !{!18} +!18 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !16, file: !3, line: 2, baseType: !19, size: 64) +!19 = !DICompositeType(tag: DW_TAG_array_type, baseType: !20, size: 64, elements: !21) +!20 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) +!21 = !{!22} +!22 = !DISubrange(count: 8) +!23 = distinct !DIAssignID() +!24 = !DILocation(line: 0, scope: !11) +!25 = !DILocation(line: 6, column: 3, scope: !11) +!26 = !DILocation(line: 7, column: 12, scope: !11) +!27 = !DILocation(line: 7, column: 3, scope: !11) +!28 = !DILocation(line: 7, column: 18, scope: !11) +!33 = !DILocation(line: 8, column: 1, scope: !11) diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/complex.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/complex.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/complex.ll @@ -0,0 +1,69 @@ +; RUN: opt -passes=sroa -S -o - %s -experimental-assignment-tracking | FileCheck %s +; +;; Based on llvm/test/DebugInfo/ARM/sroa-complex.ll +;; generated from: +;; $ cat test.c +;; void f(_Complex double c) { c = 0; } +;; $ clang test.c -g -O2 -c -Xclang -disable-llvm-passes -S \ +;; -emit-llvm -o - --target="thumbv7-apple-unknown" +;; +;; Commented out some parts of the function that are not relevant to the test. +;; +;; Check that a split store gets dbg.assigns fragments. Ensure that only the +;; value-expression gets fragment info; that the address-expression remains +;; untouched. + +;; dbg.assigns for the split (then promoted) stores. +; CHECK: %c.coerce.fca.0.extract = extractvalue [2 x i64] %c.coerce, 0 +; CHECK: %c.coerce.fca.1.extract = extractvalue [2 x i64] %c.coerce, 1 +; CHECK: call void @llvm.dbg.assign(metadata i64 %c.coerce.fca.0.extract,{{.+}}, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64),{{.+}}, metadata ptr undef, metadata !DIExpression()) +; CHECK: call void @llvm.dbg.assign(metadata i64 %c.coerce.fca.1.extract,{{.+}}, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64),{{.+}}, metadata ptr undef, {{.+}}) + +target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "armv7-apple-unknown" + +define dso_local arm_aapcscc void @f([2 x i64] %c.coerce) #0 !dbg !8 { +entry: + %c = alloca { double, double }, align 8, !DIAssignID !14 + call void @llvm.dbg.assign(metadata i1 undef, metadata !13, metadata !DIExpression(), metadata !14, metadata ptr %c, metadata !DIExpression()), !dbg !15 + %0 = bitcast ptr %c to [2 x i64]* + store [2 x i64] %c.coerce, [2 x i64]* %0, align 8, !DIAssignID !16 + call void @llvm.dbg.assign(metadata [2 x i64] %c.coerce, metadata !13, metadata !DIExpression(), metadata !16, metadata [2 x i64]* %0, metadata !DIExpression()), !dbg !15 + ; --- The rest of this function isn't useful for the test --- + ;%c.realp = getelementptr inbounds { double, double }, ptr %c, i32 0, i32 0, !dbg !17 + ;%c.imagp = getelementptr inbounds { double, double }, ptr %c, i32 0, i32 1, !dbg !17 + ;store double 0.000000e+00, ptr %c.realp, align 8, !dbg !17, !DIAssignID !18 + ;call void @llvm.dbg.assign(metadata double 0.000000e+00, metadata !13, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata !18, metadata ptr %c.realp, metadata !DIExpression()), !dbg !15 + ;store double 0.000000e+00, ptr %c.imagp, align 8, !dbg !17, !DIAssignID !19 + ;call void @llvm.dbg.assign(metadata double 0.000000e+00, metadata !13, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata !19, metadata ptr %c.imagp, metadata !DIExpression()), !dbg !15 + ret void, !dbg !20 +} + +declare void @llvm.dbg.declare(metadata, metadata, metadata) +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5, !6} +!llvm.ident = !{!7} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.c", directory: "/") +!2 = !{} +!3 = !{i32 7, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!6 = !{i32 1, !"min_enum_size", i32 4} +!7 = !{!"clang version 12.0.0"} +!8 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 2, type: !9, scopeLine: 2, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !12) +!9 = !DISubroutineType(types: !10) +!10 = !{null, !11} +!11 = !DIBasicType(name: "complex", size: 128, encoding: DW_ATE_complex_float) +!12 = !{!13} +!13 = !DILocalVariable(name: "c", arg: 1, scope: !8, file: !1, line: 2, type: !11) +!14 = distinct !DIAssignID() +!15 = !DILocation(line: 0, scope: !8) +!16 = distinct !DIAssignID() +!17 = !DILocation(line: 2, column: 31, scope: !8) +!18 = distinct !DIAssignID() +!19 = distinct !DIAssignID() +!20 = !DILocation(line: 2, column: 36, scope: !8) diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag-2.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag-2.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag-2.ll @@ -0,0 +1,260 @@ +; RUN: opt -passes=sroa -S %s -o - -experimental-assignment-tracking | FileCheck %s + +;; $ cat test.cpp +;; class a { +;; public: +;; float b[4]; +;; void c(); +;; }; +;; class B { +;; public: +;; B(a d) : e(d) {} +;; a &f() { return e; } +;; B operator*(const B &)const; +;; int g; +;; a e; +;; }; +;; B B::operator*(const B &)const { return e; } +;; class h { +;; public: +;; B i(); +;; }; +;; void j() { +;; h convexbody, k; +;; B l = k.i(), m = convexbody.i(), n = l * m; +;; a o = n.f(); // Looking at this store, o[0, 128] <- n[32, 160]. +;; o.c(); +;; } +;; Generated by grabbing IR before sroa in: +;; $ clang++ -O2 -g -c test.cpp -Xclang -fexperimental-assignment-tracking + +;; Check that the store 4xfloat split into 2x store 2xfloat has correct debug +;; info when the source (n, 160 bits of int+5*float) is split beforehand (see +;; comment in test.cpp above). Ensure that only the value-expression gets +;; fragment info; that the address-expression remains untouched. + +;; Check nearby instructions to make sure we're looking in the right place. +; CHECK: define dso_local void @_Z1jv() +; CHECK: call void @_ZN1h1iEv(ptr nonnull sret(%class.B) align 4 %m, + +; CHECK: store <2 x float> %agg.tmp.sroa.0.0.copyload.i, ptr %4, align 4,{{.+}}!DIAssignID ![[id1:[0-9]+]] +; CHECK: store <2 x float> %agg.tmp.sroa.2.0.copyload.i, ptr %n.sroa.4.4..sroa_idx, align 4,{{.+}}!DIAssignID ![[id2:[0-9]+]] +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float> %agg.tmp.sroa.0.0.copyload.i, metadata ![[var:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata ![[id1]], metadata ptr %4, metadata !DIExpression()), !dbg +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float> %agg.tmp.sroa.2.0.copyload.i, metadata ![[var]], metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata ![[id2]], metadata ptr %n.sroa.4.4..sroa_idx, metadata !DIExpression()), !dbg + +; CHECK: ret + +%class.B = type { i32, %class.a } +%class.a = type { [4 x float] } +%class.h = type { i8 } + +$_ZN1BC2E1a = comdat any + +$_ZN1B1fEv = comdat any + +; Function Attrs: nofree norecurse nounwind uwtable +define dso_local void @_ZNK1BmlERKS_(ptr noalias nocapture sret(%class.B) align 4 %agg.result, ptr nocapture readonly %this, ptr nocapture nonnull readnone align 4 dereferenceable(20) %0) local_unnamed_addr #0 align 2 !dbg !7 { +entry: + %agg.tmp.sroa.0.0..sroa_idx = getelementptr inbounds %class.B, ptr %this, i64 0, i32 1, !dbg !42 + %agg.tmp.sroa.0.0..sroa_cast = bitcast ptr %agg.tmp.sroa.0.0..sroa_idx to ptr, !dbg !42 + %agg.tmp.sroa.0.0.copyload = load <2 x float>, ptr %agg.tmp.sroa.0.0..sroa_cast, align 4, !dbg !42 + %agg.tmp.sroa.2.0..sroa_idx2 = getelementptr inbounds %class.B, ptr %this, i64 0, i32 1, i32 0, i64 2, !dbg !42 + %agg.tmp.sroa.2.0..sroa_cast = bitcast ptr %agg.tmp.sroa.2.0..sroa_idx2 to ptr, !dbg !42 + %agg.tmp.sroa.2.0.copyload = load <2 x float>, ptr %agg.tmp.sroa.2.0..sroa_cast, align 4, !dbg !42 + %d.sroa.0.0..sroa_idx.i = getelementptr inbounds %class.B, ptr %agg.result, i64 0, i32 1, !dbg !47 + %d.sroa.0.0..sroa_cast.i = bitcast ptr %d.sroa.0.0..sroa_idx.i to ptr, !dbg !47 + store <2 x float> %agg.tmp.sroa.0.0.copyload, ptr %d.sroa.0.0..sroa_cast.i, align 4, !dbg !47 + %d.sroa.2.0..sroa_idx2.i = getelementptr inbounds %class.B, ptr %agg.result, i64 0, i32 1, i32 0, i64 2, !dbg !47 + %d.sroa.2.0..sroa_cast.i = bitcast ptr %d.sroa.2.0..sroa_idx2.i to ptr, !dbg !47 + store <2 x float> %agg.tmp.sroa.2.0.copyload, ptr %d.sroa.2.0..sroa_cast.i, align 4, !dbg !47 + ret void, !dbg !54 +} + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.memcpy.p0i8.p0i8.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1 + +; Function Attrs: nounwind uwtable +define linkonce_odr dso_local void @_ZN1BC2E1a(ptr %this, <2 x float> %d.coerce0, <2 x float> %d.coerce1) unnamed_addr #2 comdat align 2 !dbg !48 { +entry: + %d.sroa.0.0..sroa_idx = getelementptr inbounds %class.B, ptr %this, i64 0, i32 1, !dbg !55 + %d.sroa.0.0..sroa_cast = bitcast ptr %d.sroa.0.0..sroa_idx to ptr, !dbg !55 + store <2 x float> %d.coerce0, ptr %d.sroa.0.0..sroa_cast, align 4, !dbg !55 + %d.sroa.2.0..sroa_idx2 = getelementptr inbounds %class.B, ptr %this, i64 0, i32 1, i32 0, i64 2, !dbg !55 + %d.sroa.2.0..sroa_cast = bitcast ptr %d.sroa.2.0..sroa_idx2 to ptr, !dbg !55 + store <2 x float> %d.coerce1, ptr %d.sroa.2.0..sroa_cast, align 4, !dbg !55 + ret void, !dbg !56 +} + +; Function Attrs: nofree nosync nounwind readnone speculatable willreturn +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) #3 + +; Function Attrs: uwtable +define dso_local void @_Z1jv() local_unnamed_addr #4 !dbg !57 { +entry: + %convexbody = alloca %class.h, align 1, !DIAssignID !73 + call void @llvm.dbg.assign(metadata i1 undef, metadata !61, metadata !DIExpression(), metadata !73, metadata ptr %convexbody, metadata !DIExpression()), !dbg !74 + %k = alloca %class.h, align 1, !DIAssignID !75 + call void @llvm.dbg.assign(metadata i1 undef, metadata !68, metadata !DIExpression(), metadata !75, metadata ptr %k, metadata !DIExpression()), !dbg !74 + %l = alloca %class.B, align 4, !DIAssignID !76 + call void @llvm.dbg.assign(metadata i1 undef, metadata !69, metadata !DIExpression(), metadata !76, metadata ptr %l, metadata !DIExpression()), !dbg !74 + %m = alloca %class.B, align 4, !DIAssignID !77 + call void @llvm.dbg.assign(metadata i1 undef, metadata !70, metadata !DIExpression(), metadata !77, metadata ptr %m, metadata !DIExpression()), !dbg !74 + %n = alloca %class.B, align 4, !DIAssignID !78 + call void @llvm.dbg.assign(metadata i1 undef, metadata !71, metadata !DIExpression(), metadata !78, metadata ptr %n, metadata !DIExpression()), !dbg !74 + %o = alloca %class.a, align 4, !DIAssignID !79 + call void @llvm.dbg.assign(metadata i1 undef, metadata !72, metadata !DIExpression(), metadata !79, metadata ptr %o, metadata !DIExpression()), !dbg !74 + %0 = getelementptr inbounds %class.h, ptr %convexbody, i64 0, i32 0, !dbg !80 + call void @llvm.lifetime.start.p0i8(i64 1, ptr nonnull %0) #7, !dbg !80 + %1 = getelementptr inbounds %class.h, ptr %k, i64 0, i32 0, !dbg !80 + call void @llvm.lifetime.start.p0i8(i64 1, ptr nonnull %1) #7, !dbg !80 + %2 = bitcast ptr %l to ptr, !dbg !81 + call void @llvm.lifetime.start.p0i8(i64 20, ptr nonnull %2) #7, !dbg !81 + call void @_ZN1h1iEv(ptr nonnull sret(%class.B) align 4 %l, ptr nonnull %k), !dbg !82 + %3 = bitcast ptr %m to ptr, !dbg !81 + call void @llvm.lifetime.start.p0i8(i64 20, ptr nonnull %3) #7, !dbg !81 + call void @_ZN1h1iEv(ptr nonnull sret(%class.B) align 4 %m, ptr nonnull %convexbody), !dbg !83 + %4 = bitcast ptr %n to ptr, !dbg !81 + call void @llvm.lifetime.start.p0i8(i64 20, ptr nonnull %4) #7, !dbg !81 + %agg.tmp.sroa.0.0..sroa_idx.i = getelementptr inbounds %class.B, ptr %l, i64 0, i32 1, !dbg !84 + %agg.tmp.sroa.0.0..sroa_cast.i = bitcast ptr %agg.tmp.sroa.0.0..sroa_idx.i to ptr, !dbg !84 + %agg.tmp.sroa.0.0.copyload.i = load <2 x float>, ptr %agg.tmp.sroa.0.0..sroa_cast.i, align 4, !dbg !84 + %agg.tmp.sroa.2.0..sroa_idx2.i = getelementptr inbounds %class.B, ptr %l, i64 0, i32 1, i32 0, i64 2, !dbg !84 + %agg.tmp.sroa.2.0..sroa_cast.i = bitcast ptr %agg.tmp.sroa.2.0..sroa_idx2.i to ptr, !dbg !84 + %agg.tmp.sroa.2.0.copyload.i = load <2 x float>, ptr %agg.tmp.sroa.2.0..sroa_cast.i, align 4, !dbg !84 + %d.sroa.0.0..sroa_idx.i.i = getelementptr inbounds %class.B, ptr %n, i64 0, i32 1, !dbg !89 + %d.sroa.0.0..sroa_cast.i.i = bitcast ptr %d.sroa.0.0..sroa_idx.i.i to ptr, !dbg !89 + store <2 x float> %agg.tmp.sroa.0.0.copyload.i, ptr %d.sroa.0.0..sroa_cast.i.i, align 4, !dbg !89 + %d.sroa.2.0..sroa_idx2.i.i = getelementptr inbounds %class.B, ptr %n, i64 0, i32 1, i32 0, i64 2, !dbg !89 + %d.sroa.2.0..sroa_cast.i.i = bitcast ptr %d.sroa.2.0..sroa_idx2.i.i to ptr, !dbg !89 + store <2 x float> %agg.tmp.sroa.2.0.copyload.i, ptr %d.sroa.2.0..sroa_cast.i.i, align 4, !dbg !89 + %5 = bitcast ptr %o to ptr, !dbg !91 + call void @llvm.lifetime.start.p0i8(i64 16, ptr nonnull %5) #7, !dbg !91 + %e.i = getelementptr inbounds %class.B, ptr %n, i64 0, i32 1, !dbg !92 + %6 = bitcast ptr %e.i to ptr, !dbg !97 + call void @llvm.memcpy.p0i8.p0i8.i64(ptr nonnull align 4 dereferenceable(16) %5, ptr nonnull align 4 dereferenceable(16) %6, i64 16, i1 false), !dbg !97, !DIAssignID !98 + call void @llvm.dbg.assign(metadata i1 undef, metadata !72, metadata !DIExpression(), metadata !98, metadata ptr %5, metadata !DIExpression()), !dbg !74 + call void @_ZN1a1cEv(ptr nonnull %o), !dbg !99 + call void @llvm.lifetime.end.p0i8(i64 16, ptr nonnull %5) #7, !dbg !100 + call void @llvm.lifetime.end.p0i8(i64 20, ptr nonnull %4) #7, !dbg !100 + call void @llvm.lifetime.end.p0i8(i64 20, ptr nonnull %3) #7, !dbg !100 + call void @llvm.lifetime.end.p0i8(i64 20, ptr nonnull %2) #7, !dbg !100 + call void @llvm.lifetime.end.p0i8(i64 1, ptr nonnull %1) #7, !dbg !100 + call void @llvm.lifetime.end.p0i8(i64 1, ptr nonnull %0) #7, !dbg !100 + ret void, !dbg !100 +} + +declare void @llvm.lifetime.start.p0i8(i64 immarg, ptr nocapture) #1 +declare dso_local void @_ZN1h1iEv(ptr sret(%class.B) align 4, ptr) local_unnamed_addr #5 + +; Function Attrs: nounwind uwtable +define linkonce_odr dso_local nonnull align 4 dereferenceable(16) ptr @_ZN1B1fEv(ptr %this) local_unnamed_addr #6 comdat align 2 !dbg !93 { +entry: + %e = getelementptr inbounds %class.B, ptr %this, i64 0, i32 1, !dbg !101 + ret ptr %e, !dbg !102 +} + +declare dso_local void @_ZN1a1cEv(ptr) local_unnamed_addr #5 + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.end.p0i8(i64 immarg, ptr nocapture) #1 + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5} +!llvm.ident = !{!6} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "reduce.cpp", directory: "/") +!2 = !{} +!3 = !{i32 7, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!6 = !{!"clang version 12.0.0"} +!7 = distinct !DISubprogram(name: "operator*", linkageName: "_ZNK1BmlERKS_", scope: !8, file: !1, line: 14, type: !33, scopeLine: 14, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, declaration: !32, retainedNodes: !38) +!8 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "B", file: !1, line: 6, size: 160, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: !9, identifier: "_ZTS1B") +!9 = !{!10, !12, !24, !28, !32} +!10 = !DIDerivedType(tag: DW_TAG_member, name: "g", scope: !8, file: !1, line: 11, baseType: !11, size: 32, flags: DIFlagPublic) +!11 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!12 = !DIDerivedType(tag: DW_TAG_member, name: "e", scope: !8, file: !1, line: 12, baseType: !13, size: 128, offset: 32, flags: DIFlagPublic) +!13 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "a", file: !1, line: 1, size: 128, flags: DIFlagTypePassByValue, elements: !14, identifier: "_ZTS1a") +!14 = !{!15, !20} +!15 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !13, file: !1, line: 3, baseType: !16, size: 128, flags: DIFlagPublic) +!16 = !DICompositeType(tag: DW_TAG_array_type, baseType: !17, size: 128, elements: !18) +!17 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) +!18 = !{!19} +!19 = !DISubrange(count: 4) +!20 = !DISubprogram(name: "c", linkageName: "_ZN1a1cEv", scope: !13, file: !1, line: 4, type: !21, scopeLine: 4, flags: DIFlagPublic | DIFlagPrototyped, spFlags: DISPFlagOptimized) +!21 = !DISubroutineType(types: !22) +!22 = !{null, !23} +!23 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !13, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer) +!24 = !DISubprogram(name: "B", scope: !8, file: !1, line: 8, type: !25, scopeLine: 8, flags: DIFlagPublic | DIFlagPrototyped, spFlags: DISPFlagOptimized) +!25 = !DISubroutineType(types: !26) +!26 = !{null, !27, !13} +!27 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !8, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer) +!28 = !DISubprogram(name: "f", linkageName: "_ZN1B1fEv", scope: !8, file: !1, line: 9, type: !29, scopeLine: 9, flags: DIFlagPublic | DIFlagPrototyped, spFlags: DISPFlagOptimized) +!29 = !DISubroutineType(types: !30) +!30 = !{!31, !27} +!31 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !13, size: 64) +!32 = !DISubprogram(name: "operator*", linkageName: "_ZNK1BmlERKS_", scope: !8, file: !1, line: 10, type: !33, scopeLine: 10, flags: DIFlagPublic | DIFlagPrototyped, spFlags: DISPFlagOptimized) +!33 = !DISubroutineType(types: !34) +!34 = !{!8, !35, !37} +!35 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !36, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer) +!36 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !8) +!37 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !36, size: 64) +!38 = !{!39, !41} +!39 = !DILocalVariable(name: "this", arg: 1, scope: !7, type: !40, flags: DIFlagArtificial | DIFlagObjectPointer) +!40 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !36, size: 64) +!41 = !DILocalVariable(arg: 2, scope: !7, file: !1, line: 14, type: !37) +!42 = !DILocation(line: 14, column: 41, scope: !7) +!47 = !DILocation(line: 8, column: 12, scope: !48, inlinedAt: !53) +!48 = distinct !DISubprogram(name: "B", linkageName: "_ZN1BC2E1a", scope: !8, file: !1, line: 8, type: !25, scopeLine: 8, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, declaration: !24, retainedNodes: !49) +!49 = !{!50, !52} +!50 = !DILocalVariable(name: "this", arg: 1, scope: !48, type: !51, flags: DIFlagArtificial | DIFlagObjectPointer) +!51 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !8, size: 64) +!52 = !DILocalVariable(name: "d", arg: 2, scope: !48, file: !1, line: 8, type: !13) +!53 = distinct !DILocation(line: 14, column: 41, scope: !7) +!54 = !DILocation(line: 14, column: 34, scope: !7) +!55 = !DILocation(line: 8, column: 12, scope: !48) +!56 = !DILocation(line: 8, column: 18, scope: !48) +!57 = distinct !DISubprogram(name: "j", linkageName: "_Z1jv", scope: !1, file: !1, line: 19, type: !58, scopeLine: 19, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !60) +!58 = !DISubroutineType(types: !59) +!59 = !{null} +!60 = !{!61, !68, !69, !70, !71, !72} +!61 = !DILocalVariable(name: "convexbody", scope: !57, file: !1, line: 20, type: !62) +!62 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "h", file: !1, line: 15, size: 8, flags: DIFlagTypePassByValue, elements: !63, identifier: "_ZTS1h") +!63 = !{!64} +!64 = !DISubprogram(name: "i", linkageName: "_ZN1h1iEv", scope: !62, file: !1, line: 17, type: !65, scopeLine: 17, flags: DIFlagPublic | DIFlagPrototyped, spFlags: DISPFlagOptimized) +!65 = !DISubroutineType(types: !66) +!66 = !{!8, !67} +!67 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !62, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer) +!68 = !DILocalVariable(name: "k", scope: !57, file: !1, line: 20, type: !62) +!69 = !DILocalVariable(name: "l", scope: !57, file: !1, line: 21, type: !8) +!70 = !DILocalVariable(name: "m", scope: !57, file: !1, line: 21, type: !8) +!71 = !DILocalVariable(name: "n", scope: !57, file: !1, line: 21, type: !8) +!72 = !DILocalVariable(name: "o", scope: !57, file: !1, line: 22, type: !13) +!73 = distinct !DIAssignID() +!74 = !DILocation(line: 0, scope: !57) +!75 = distinct !DIAssignID() +!76 = distinct !DIAssignID() +!77 = distinct !DIAssignID() +!78 = distinct !DIAssignID() +!79 = distinct !DIAssignID() +!80 = !DILocation(line: 20, column: 3, scope: !57) +!81 = !DILocation(line: 21, column: 3, scope: !57) +!82 = !DILocation(line: 21, column: 11, scope: !57) +!83 = !DILocation(line: 21, column: 31, scope: !57) +!84 = !DILocation(line: 14, column: 41, scope: !7, inlinedAt: !85) +!85 = distinct !DILocation(line: 21, column: 42, scope: !57) +!89 = !DILocation(line: 8, column: 12, scope: !48, inlinedAt: !90) +!90 = distinct !DILocation(line: 14, column: 41, scope: !7, inlinedAt: !85) +!91 = !DILocation(line: 22, column: 3, scope: !57) +!92 = !DILocation(line: 9, column: 19, scope: !93, inlinedAt: !96) +!93 = distinct !DISubprogram(name: "f", linkageName: "_ZN1B1fEv", scope: !8, file: !1, line: 9, type: !29, scopeLine: 9, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, declaration: !28, retainedNodes: !94) +!94 = !{!95} +!95 = !DILocalVariable(name: "this", arg: 1, scope: !93, type: !51, flags: DIFlagArtificial | DIFlagObjectPointer) +!96 = distinct !DILocation(line: 22, column: 11, scope: !57) +!97 = !DILocation(line: 22, column: 9, scope: !57) +!98 = distinct !DIAssignID() +!99 = !DILocation(line: 23, column: 5, scope: !57) +!100 = !DILocation(line: 24, column: 1, scope: !57) +!101 = !DILocation(line: 9, column: 19, scope: !93) +!102 = !DILocation(line: 9, column: 12, scope: !93) diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag.ll @@ -0,0 +1,113 @@ +; RUN: opt %s -S -passes=sroa -o - -experimental-assignment-tracking | FileCheck %s + +;; $ cat test.cpp +;; class c { +;; float b[4]; +;; }; +;; c fn1(); +;; void d() { +;; c a[3]; +;; a[2] = fn1(); +;; } +;; +;; Generated by grabbing IR before sroa in: +;; $ clang++ -O2 -g -c test.cpp -Xclang -fexperimental-assignment-tracking +;; +;; Check that when the memcpy to fragment(256, 128) is split into two 2xfloat +;; stores, the dbg.assign is split into two with fragment(256, 64) & +;; fragment(320, 64). Ensure that only the value-expression gets fragment info; +;; that the address-expression remains untouched. + +; CHECK: %call = call +; CHECK-NEXT: %0 = extractvalue { <2 x float>, <2 x float> } %call, 0 +; CHECK-NEXT: %1 = extractvalue { <2 x float>, <2 x float> } %call, 1 +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float> %0, metadata ![[var:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 256, 64),{{.+}},{{.+}}undef, metadata !DIExpression()), !dbg +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float> %1, metadata ![[var]], metadata !DIExpression(DW_OP_LLVM_fragment, 320, 64),{{.+}},{{.+}}undef, metadata !DIExpression()), !dbg + +%class.c = type { [4 x float] } + +; Function Attrs: uwtable +define dso_local void @_Z1dv() #0 !dbg !7 { +entry: + %a = alloca [3 x %class.c], align 16, !DIAssignID !22 + call void @llvm.dbg.assign(metadata i1 undef, metadata !11, metadata !DIExpression(), metadata !22, metadata ptr %a, metadata !DIExpression()), !dbg !23 + %ref.tmp = alloca %class.c, align 4 + %0 = bitcast ptr %a to ptr, !dbg !24 + call void @llvm.lifetime.start.p0i8(i64 48, ptr %0) #4, !dbg !24 + %1 = bitcast ptr %ref.tmp to ptr, !dbg !25 + call void @llvm.lifetime.start.p0i8(i64 16, ptr %1) #4, !dbg !25 + %call = call { <2 x float>, <2 x float> } @_Z3fn1v(), !dbg !25 + %coerce.dive = getelementptr inbounds %class.c, ptr %ref.tmp, i32 0, i32 0, !dbg !25 + %2 = bitcast ptr %coerce.dive to ptr, !dbg !25 + %3 = getelementptr inbounds { <2 x float>, <2 x float> }, ptr %2, i32 0, i32 0, !dbg !25 + %4 = extractvalue { <2 x float>, <2 x float> } %call, 0, !dbg !25 + store <2 x float> %4, ptr %3, align 4, !dbg !25 + %5 = getelementptr inbounds { <2 x float>, <2 x float> }, ptr %2, i32 0, i32 1, !dbg !25 + %6 = extractvalue { <2 x float>, <2 x float> } %call, 1, !dbg !25 + store <2 x float> %6, ptr %5, align 4, !dbg !25 + %arrayidx = getelementptr inbounds [3 x %class.c], ptr %a, i64 0, i64 2, !dbg !26 + %7 = bitcast ptr %arrayidx to ptr, !dbg !27 + %8 = bitcast ptr %ref.tmp to ptr, !dbg !27 + call void @llvm.memcpy.p0i8.p0i8.i64(ptr align 16 %7, ptr align 4 %8, i64 16, i1 false), !dbg !27, !DIAssignID !32 + call void @llvm.dbg.assign(metadata i1 undef, metadata !11, metadata !DIExpression(DW_OP_LLVM_fragment, 256, 128), metadata !32, metadata ptr %7, metadata !DIExpression()), !dbg !23 + %9 = bitcast ptr %ref.tmp to ptr, !dbg !26 + call void @llvm.lifetime.end.p0i8(i64 16, ptr %9) #4, !dbg !26 + %10 = bitcast ptr %a to ptr, !dbg !33 + call void @llvm.lifetime.end.p0i8(i64 48, ptr %10) #4, !dbg !33 + ret void, !dbg !33 +} + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.start.p0i8(i64 immarg, ptr nocapture) #1 + +; Function Attrs: nofree nosync nounwind readnone speculatable willreturn +declare void @llvm.dbg.declare(metadata, metadata, metadata) #2 + +declare !dbg !34 dso_local { <2 x float>, <2 x float> } @_Z3fn1v() #3 + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.memcpy.p0i8.p0i8.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1 + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.end.p0i8(i64 immarg, ptr nocapture) #1 + +; Function Attrs: nofree nosync nounwind readnone speculatable willreturn +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) #2 + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5} +!llvm.ident = !{!6} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "reduce.cpp", directory: "/") +!2 = !{} +!3 = !{i32 7, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!6 = !{!"clang version 12.0.0"} +!7 = distinct !DISubprogram(name: "d", linkageName: "_Z1dv", scope: !1, file: !1, line: 5, type: !8, scopeLine: 5, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !10) +!8 = !DISubroutineType(types: !9) +!9 = !{null} +!10 = !{!11} +!11 = !DILocalVariable(name: "a", scope: !7, file: !1, line: 6, type: !12) +!12 = !DICompositeType(tag: DW_TAG_array_type, baseType: !13, size: 384, elements: !20) +!13 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "c", file: !1, line: 1, size: 128, flags: DIFlagTypePassByValue, elements: !14, identifier: "_ZTS1c") +!14 = !{!15} +!15 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !13, file: !1, line: 2, baseType: !16, size: 128) +!16 = !DICompositeType(tag: DW_TAG_array_type, baseType: !17, size: 128, elements: !18) +!17 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) +!18 = !{!19} +!19 = !DISubrange(count: 4) +!20 = !{!21} +!21 = !DISubrange(count: 3) +!22 = distinct !DIAssignID() +!23 = !DILocation(line: 0, scope: !7) +!24 = !DILocation(line: 6, column: 3, scope: !7) +!25 = !DILocation(line: 7, column: 10, scope: !7) +!26 = !DILocation(line: 7, column: 3, scope: !7) +!27 = !DILocation(line: 7, column: 8, scope: !7) +!32 = distinct !DIAssignID() +!33 = !DILocation(line: 8, column: 1, scope: !7) +!34 = !DISubprogram(name: "fn1", linkageName: "_Z3fn1v", scope: !1, file: !1, line: 4, type: !35, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !2) +!35 = !DISubroutineType(types: !36) +!36 = !{!13} diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/id.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/id.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/id.ll @@ -0,0 +1,174 @@ +; RUN: opt -passes=sroa -S %s -o - -experimental-assignment-tracking | FileCheck %s + +;; Check that multiple dbg.assign intrinsics linked to a store that is getting +;; split (or at least that is touched by SROA, causing a replacement store to +;; be generated) are still both linked to the new store(s). +;; +;; Additionally, check that SROA inserts new dbg.assign intrinsics by the +;; originals. + +;; $ cat test.cpp +;; class a { +;; public: +;; a(int, float &) {} +;; }; +;; float b, d; +;; int c; +;; void f() { +;; float e; +;; if (c) +;; e = b; +;; else +;; e = b / d; +;; a(c, e); +;; } +;; +;; Generated by grabbing IR before sroa in: +;; $ clang++ -O2 -g -c test.cpp -Xclang -fexperimental-assignment-tracking + +; CHECK: if.then: +; CHECK-NEXT: %1 = load float +; CHECK-NEXT: call void @llvm.dbg.assign(metadata float %storemerge, metadata ![[var:[0-9]+]], metadata !DIExpression(), metadata ![[id:[0-9]+]], metadata ptr undef, metadata !DIExpression()), !dbg ![[dbg:[0-9]+]] + +; CHECK: if.else: +; CHECK-NEXT: %2 = load float +; CHECK-NEXT: %3 = load float +; CHECK-NEXT: %div = fdiv float +; CHECK: call void @llvm.dbg.assign(metadata float %storemerge, metadata ![[var]], metadata !DIExpression(), metadata ![[id]], metadata ptr undef, metadata !DIExpression()), !dbg ![[dbg]] + +%class.a = type { i8 } + +$_ZN1aC2EiRf = comdat any + +@b = dso_local local_unnamed_addr global float 0.000000e+00, align 4, !dbg !0 +@d = dso_local local_unnamed_addr global float 0.000000e+00, align 4, !dbg !6 +@c = dso_local local_unnamed_addr global i32 0, align 4, !dbg !9 + +; Function Attrs: nounwind readonly uwtable +define dso_local void @_Z1fv() local_unnamed_addr #0 !dbg !16 { +entry: + %e = alloca float, align 4, !DIAssignID !21 + call void @llvm.dbg.assign(metadata i1 undef, metadata !20, metadata !DIExpression(), metadata !21, metadata ptr %e, metadata !DIExpression()), !dbg !22 + %agg.tmp.ensured = alloca %class.a, align 1 + %0 = bitcast ptr %e to ptr, !dbg !23 + call void @llvm.lifetime.start.p0i8(i64 4, ptr nonnull %0) #4, !dbg !23 + %1 = load i32, ptr @c, align 4, !dbg !24 + %tobool.not = icmp eq i32 %1, 0, !dbg !24 + br i1 %tobool.not, label %if.else, label %if.then, !dbg !30 + +if.then: ; preds = %entry + %2 = load float, ptr @b, align 4, !dbg !31 + call void @llvm.dbg.assign(metadata float %2, metadata !20, metadata !DIExpression(), metadata !34, metadata ptr %e, metadata !DIExpression()), !dbg !22 + br label %if.end, !dbg !35 + +if.else: ; preds = %entry + %3 = load float, ptr @b, align 4, !dbg !36 + %4 = load float, ptr @d, align 4, !dbg !37 + %div = fdiv float %3, %4, !dbg !38 + call void @llvm.dbg.assign(metadata float %div, metadata !20, metadata !DIExpression(), metadata !34, metadata ptr %e, metadata !DIExpression()), !dbg !22 + br label %if.end + +if.end: ; preds = %if.else, %if.then + %storemerge = phi float [ %div, %if.else ], [ %2, %if.then ], !dbg !39 + store float %storemerge, ptr %e, align 4, !dbg !39, !DIAssignID !34 + %5 = load i32, ptr @c, align 4, !dbg !40 + call void @llvm.dbg.assign(metadata i1 undef, metadata !41, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !55 + call void @llvm.dbg.assign(metadata i1 undef, metadata !51, metadata !DIExpression(), metadata !57, metadata ptr undef, metadata !DIExpression()), !dbg !55 + call void @llvm.dbg.assign(metadata i1 undef, metadata !52, metadata !DIExpression(), metadata !58, metadata ptr undef, metadata !DIExpression()), !dbg !55 + call void @llvm.dbg.assign(metadata ptr %agg.tmp.ensured, metadata !41, metadata !DIExpression(), metadata !59, metadata ptr undef, metadata !DIExpression()), !dbg !55 + call void @llvm.dbg.assign(metadata i32 %5, metadata !51, metadata !DIExpression(), metadata !60, metadata ptr undef, metadata !DIExpression()), !dbg !55 + call void @llvm.dbg.assign(metadata ptr %e, metadata !52, metadata !DIExpression(), metadata !61, metadata ptr undef, metadata !DIExpression()), !dbg !55 + call void @llvm.lifetime.end.p0i8(i64 4, ptr nonnull %0) #4, !dbg !62 + ret void, !dbg !62 +} + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.start.p0i8(i64 immarg, ptr nocapture) #1 + +; Function Attrs: nounwind uwtable +define linkonce_odr dso_local void @_ZN1aC2EiRf(ptr %this, i32 %0, ptr nonnull align 4 dereferenceable(4) %1) unnamed_addr #2 comdat align 2 !dbg !42 { +entry: + call void @llvm.dbg.assign(metadata i1 undef, metadata !41, metadata !DIExpression(), metadata !63, metadata ptr undef, metadata !DIExpression()), !dbg !64 + call void @llvm.dbg.assign(metadata i1 undef, metadata !51, metadata !DIExpression(), metadata !65, metadata ptr undef, metadata !DIExpression()), !dbg !64 + call void @llvm.dbg.assign(metadata i1 undef, metadata !52, metadata !DIExpression(), metadata !66, metadata ptr undef, metadata !DIExpression()), !dbg !64 + call void @llvm.dbg.assign(metadata ptr %this, metadata !41, metadata !DIExpression(), metadata !67, metadata ptr undef, metadata !DIExpression()), !dbg !64 + call void @llvm.dbg.assign(metadata i32 %0, metadata !51, metadata !DIExpression(), metadata !68, metadata ptr undef, metadata !DIExpression()), !dbg !64 + call void @llvm.dbg.assign(metadata ptr %1, metadata !52, metadata !DIExpression(), metadata !69, metadata ptr undef, metadata !DIExpression()), !dbg !64 + ret void, !dbg !70 +} + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.end.p0i8(i64 immarg, ptr nocapture) #1 + +; Function Attrs: nofree nosync nounwind readnone speculatable willreturn +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) #3 + +!llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!12, !13, !14} +!llvm.ident = !{!15} + +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) +!1 = distinct !DIGlobalVariable(name: "b", scope: !2, file: !3, line: 5, type: !8, isLocal: false, isDefinition: true) +!2 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !3, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, splitDebugInlining: false, nameTableKind: None) +!3 = !DIFile(filename: "reduce.cpp", directory: "") +!4 = !{} +!5 = !{!0, !6, !9} +!6 = !DIGlobalVariableExpression(var: !7, expr: !DIExpression()) +!7 = distinct !DIGlobalVariable(name: "d", scope: !2, file: !3, line: 5, type: !8, isLocal: false, isDefinition: true) +!8 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) +!9 = !DIGlobalVariableExpression(var: !10, expr: !DIExpression()) +!10 = distinct !DIGlobalVariable(name: "c", scope: !2, file: !3, line: 6, type: !11, isLocal: false, isDefinition: true) +!11 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!12 = !{i32 7, !"Dwarf Version", i32 4} +!13 = !{i32 2, !"Debug Info Version", i32 3} +!14 = !{i32 1, !"wchar_size", i32 4} +!15 = !{!"clang version 12.0.0"} +!16 = distinct !DISubprogram(name: "f", linkageName: "_Z1fv", scope: !3, file: !3, line: 7, type: !17, scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, retainedNodes: !19) +!17 = !DISubroutineType(types: !18) +!18 = !{null} +!19 = !{!20} +!20 = !DILocalVariable(name: "e", scope: !16, file: !3, line: 8, type: !8) +!21 = distinct !DIAssignID() +!22 = !DILocation(line: 0, scope: !16) +!23 = !DILocation(line: 8, column: 3, scope: !16) +!24 = !DILocation(line: 9, column: 7, scope: !25) +!25 = distinct !DILexicalBlock(scope: !16, file: !3, line: 9, column: 7) +!30 = !DILocation(line: 9, column: 7, scope: !16) +!31 = !DILocation(line: 10, column: 9, scope: !25) +!34 = distinct !DIAssignID() +!35 = !DILocation(line: 10, column: 5, scope: !25) +!36 = !DILocation(line: 12, column: 9, scope: !25) +!37 = !DILocation(line: 12, column: 13, scope: !25) +!38 = !DILocation(line: 12, column: 11, scope: !25) +!39 = !DILocation(line: 0, scope: !25) +!40 = !DILocation(line: 13, column: 5, scope: !16) +!41 = !DILocalVariable(name: "this", arg: 1, scope: !42, type: !53, flags: DIFlagArtificial | DIFlagObjectPointer) +!42 = distinct !DISubprogram(name: "a", linkageName: "_ZN1aC2EiRf", scope: !43, file: !3, line: 3, type: !46, scopeLine: 3, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, declaration: !45, retainedNodes: !50) +!43 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "a", file: !3, line: 1, size: 8, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: !44, identifier: "_ZTS1a") +!44 = !{!45} +!45 = !DISubprogram(name: "a", scope: !43, file: !3, line: 3, type: !46, scopeLine: 3, flags: DIFlagPublic | DIFlagPrototyped, spFlags: DISPFlagOptimized) +!46 = !DISubroutineType(types: !47) +!47 = !{null, !48, !11, !49} +!48 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !43, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer) +!49 = !DIDerivedType(tag: DW_TAG_reference_type, baseType: !8, size: 64) +!50 = !{!41, !51, !52} +!51 = !DILocalVariable(arg: 2, scope: !42, file: !3, line: 3, type: !11) +!52 = !DILocalVariable(arg: 3, scope: !42, file: !3, line: 3, type: !49) +!53 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !43, size: 64) +!54 = distinct !DIAssignID() +!55 = !DILocation(line: 0, scope: !42, inlinedAt: !56) +!56 = distinct !DILocation(line: 13, column: 3, scope: !16) +!57 = distinct !DIAssignID() +!58 = distinct !DIAssignID() +!59 = distinct !DIAssignID() +!60 = distinct !DIAssignID() +!61 = distinct !DIAssignID() +!62 = !DILocation(line: 14, column: 1, scope: !16) +!63 = distinct !DIAssignID() +!64 = !DILocation(line: 0, scope: !42) +!65 = distinct !DIAssignID() +!66 = distinct !DIAssignID() +!67 = distinct !DIAssignID() +!68 = distinct !DIAssignID() +!69 = distinct !DIAssignID() +!70 = !DILocation(line: 3, column: 20, scope: !42) diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memcpy.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memcpy.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memcpy.ll @@ -0,0 +1,117 @@ +; RUN: opt -passes=sroa,verify -S %s -o - -experimental-assignment-tracking \ +; RUN: | FileCheck %s --implicit-check-not="call void @llvm.dbg" + +;; Check that the new slices of an alloca and memcpy intructions get dbg.assign +;; intrinsics with the correct fragment info. +;; +;; Also check that the new dbg.assign intrinsics are inserted after each split +;; store. See llvm/test/DebugInfo/Generic/dbg-assign-sroa-id.ll for the +;; counterpart check. Ensure that only the value-expression gets fragment info; +;; that the address-expression remains untouched. + +;; $ cat test.cpp +;; struct LargeStruct { +;; int A, B, C; +;; int Var; +;; int D, E, F; +;; }; +;; LargeStruct From; +;; int example() { +;; LargeStruct To = From; +;; return To.Var; +;; } +;; $ clang test.cpp -Xclang -fexperimental-assignment-tracking \ +;; -Xclang -disable-llvm-passes -O2 -g -c -S -emit-llvm -o - + +;; Split alloca. +; CHECK: entry: +; CHECK-NEXT: %To.sroa.0 = alloca { i32, i32, i32 }, align 8, !DIAssignID ![[ID_1:[0-9]+]] +; CHECK-NEXT: call void @llvm.dbg.assign(metadata {{.+}} undef, metadata ![[TO:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96), metadata ![[ID_1]], metadata ptr %To.sroa.0, metadata !DIExpression()), !dbg + +; CHECK-NEXT: %To.sroa.4 = alloca { i32, i32, i32 }, align 8, !DIAssignID ![[ID_3:[0-9]+]] +; CHECK-NEXT: call void @llvm.dbg.assign(metadata {{.+}} undef, metadata ![[TO]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96), metadata ![[ID_3]], metadata ptr %To.sroa.4, metadata !DIExpression()), !dbg + +;; Split memcpy. +; CHECK: call void @llvm.memcpy{{.*}}(ptr align 8 %To.sroa.0, ptr align 4 @From, i64 12, i1 false),{{.*}}!DIAssignID ![[ID_4:[0-9]+]] +;; This slice has been split and is promoted. +; CHECK: %To.sroa.3.0.copyload = load i32, ptr getelementptr inbounds (i8, ptr @From, i64 12) +; CHECK: call void @llvm.memcpy{{.*}}(ptr align 8 %To.sroa.4, ptr align 4 getelementptr inbounds (i8, ptr @From, i64 16), i64 12, i1 false){{.*}}!DIAssignID ![[ID_6:[0-9]+]] + +;; Intrinsics for the splits above. +; CHECK-NEXT: call void @llvm.dbg.assign(metadata {{.+}} undef, metadata ![[TO]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96), metadata ![[ID_4]], metadata ptr %To.sroa.0, metadata !DIExpression()), !dbg +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 %To.sroa.3.0.copyload, metadata ![[TO]], metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg +; CHECK-NEXT: call void @llvm.dbg.assign(metadata {{.+}} undef, metadata ![[TO]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96), metadata ![[ID_6]], metadata ptr %To.sroa.4, metadata !DIExpression()), !dbg + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + +%struct.LargeStruct = type { i32, i32, i32, i32, i32, i32, i32 } + +@From = dso_local global %struct.LargeStruct zeroinitializer, align 4, !dbg !0 + +; Function Attrs: nounwind uwtable mustprogress +define dso_local i32 @_Z7examplev() #0 !dbg !20 { +entry: + %To = alloca %struct.LargeStruct, align 4, !DIAssignID !25 + call void @llvm.dbg.assign(metadata i1 undef, metadata !24, metadata !DIExpression(), metadata !25, metadata ptr %To, metadata !DIExpression()), !dbg !26 + %0 = bitcast ptr %To to ptr, !dbg !27 + call void @llvm.lifetime.start.p0i8(i64 28, ptr %0) #3, !dbg !27 + %1 = bitcast ptr %To to ptr, !dbg !28 + call void @llvm.memcpy.p0i8.p0i8.i64(ptr align 4 %1, ptr align 4 bitcast (ptr @From to ptr), i64 28, i1 false), !dbg !28, !DIAssignID !34 + call void @llvm.dbg.assign(metadata i1 undef, metadata !24, metadata !DIExpression(), metadata !34, metadata ptr %1, metadata !DIExpression()), !dbg !28 + %Var = getelementptr inbounds %struct.LargeStruct, ptr %To, i32 0, i32 3, !dbg !35 + %2 = load i32, ptr %Var, align 4, !dbg !35 + %3 = bitcast ptr %To to ptr, !dbg !38 + call void @llvm.lifetime.end.p0i8(i64 28, ptr %3) #3, !dbg !38 + ret i32 %2, !dbg !39 +} + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.start.p0i8(i64 immarg, ptr nocapture) #1 + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.memcpy.p0i8.p0i8.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1 + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.end.p0i8(i64 immarg, ptr nocapture) #1 + +; Function Attrs: nofree nosync nounwind readnone speculatable willreturn +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) #2 + + +!llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!16, !17, !18} +!llvm.ident = !{!19} + +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) +!1 = distinct !DIGlobalVariable(name: "From", scope: !2, file: !3, line: 6, type: !6, isLocal: false, isDefinition: true) +!2 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !3, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, splitDebugInlining: false, nameTableKind: None) +!3 = !DIFile(filename: "sroa-test.cpp", directory: "/") +!4 = !{} +!5 = !{!0} +!6 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "LargeStruct", file: !3, line: 1, size: 224, flags: DIFlagTypePassByValue, elements: !7, identifier: "_ZTS11LargeStruct") +!7 = !{!8, !10, !11, !12, !13, !14, !15} +!8 = !DIDerivedType(tag: DW_TAG_member, name: "A", scope: !6, file: !3, line: 2, baseType: !9, size: 32) +!9 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!10 = !DIDerivedType(tag: DW_TAG_member, name: "B", scope: !6, file: !3, line: 2, baseType: !9, size: 32, offset: 32) +!11 = !DIDerivedType(tag: DW_TAG_member, name: "C", scope: !6, file: !3, line: 2, baseType: !9, size: 32, offset: 64) +!12 = !DIDerivedType(tag: DW_TAG_member, name: "Var", scope: !6, file: !3, line: 3, baseType: !9, size: 32, offset: 96) +!13 = !DIDerivedType(tag: DW_TAG_member, name: "D", scope: !6, file: !3, line: 4, baseType: !9, size: 32, offset: 128) +!14 = !DIDerivedType(tag: DW_TAG_member, name: "E", scope: !6, file: !3, line: 4, baseType: !9, size: 32, offset: 160) +!15 = !DIDerivedType(tag: DW_TAG_member, name: "F", scope: !6, file: !3, line: 4, baseType: !9, size: 32, offset: 192) +!16 = !{i32 7, !"Dwarf Version", i32 4} +!17 = !{i32 2, !"Debug Info Version", i32 3} +!18 = !{i32 1, !"wchar_size", i32 4} +!19 = !{!"clang version 12.0.0"} +!20 = distinct !DISubprogram(name: "example", linkageName: "_Z7examplev", scope: !3, file: !3, line: 7, type: !21, scopeLine: 7, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, retainedNodes: !23) +!21 = !DISubroutineType(types: !22) +!22 = !{!9} +!23 = !{!24} +!24 = !DILocalVariable(name: "To", scope: !20, file: !3, line: 8, type: !6) +!25 = distinct !DIAssignID() +!26 = !DILocation(line: 0, scope: !20) +!27 = !DILocation(line: 8, column: 3, scope: !20) +!28 = !DILocation(line: 8, column: 20, scope: !20) +!34 = distinct !DIAssignID() +!35 = !DILocation(line: 9, column: 13, scope: !20) +!38 = !DILocation(line: 10, column: 1, scope: !20) +!39 = !DILocation(line: 9, column: 3, scope: !20) diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memmove-to-from-same-alloca.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memmove-to-from-same-alloca.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memmove-to-from-same-alloca.ll @@ -0,0 +1,163 @@ +; RUN: opt %s -passes=sroa -o - -S -experimental-assignment-tracking \ +; RUN: | FileCheck %s + +;; Generated from this C++ source: +;; __attribute__((nodebug)) struct Blob {int P[6];} Glob; +;; __attribute__((nodebug)) int Cond; +;; __attribute__((nodebug)) Blob *C; +;; __attribute__((nodebug)) void call(int); +;; +;; void f() { +;; int A[16]; +;; __attribute__ ((nodebug)) int B[16]; +;; // A[0:6) <- Glob +;; __builtin_memmove(&A[0], &Glob, sizeof(Blob)); +;; call(0); +;; // B[8:14) <- Glob +;; __builtin_memmove(&B[8], &Glob, sizeof(Blob)); +;; call(A[0]); +;; // A[8:14) <- A[0:6) +;; __builtin_memmove(&A[8], &A[0], sizeof(Blob)); +;; call(A[8]); +;; if (Cond) +;; // C <- A[8:14) +;; __builtin_memmove(C, &A[8], sizeof(Blob)); +;; else +;; // C <- B[8:14) +;; __builtin_memmove(C, &B[8], sizeof(Blob)); +;; } +;; +;; using: +;; clang test.cpp -emit-llvm -S -g -O2 -Xclang -disable-llvm-passes -o - \ +;; | opt -passes=declare-to-assign -o test.ll - -S + +;; We're interested in variable A and the second memmove with A as a dest (the +;; third memmove in the source). SROA is going to chop up A so that the only +;; Alloca'd slice remaining is what were originally elements 1 through 5 +;; inclusive (element 0 is promoted). Incidentally, the memmove later becomes a +;; memcpy. Check that the dbg.assign address and fragment are correct and +;; ensure the DIAssignID still links it to the memmove(/memcpy). + +; CHECK: %A.sroa.0.sroa.5 = alloca [5 x i32] +; CHECK: llvm.memcpy{{.*}}(ptr align 4 %A.sroa.0.sroa.5, ptr align 4 getelementptr inbounds (i8, ptr @Glob, i64 4), i64 20, i1 false){{.*}}!DIAssignID ![[ID:[0-9]+]] +;; Here's the dbg.assign for element 0 - it's not important for the test. +; CHECK-NEXT: llvm.dbg.assign({{.*}}!DIExpression(DW_OP_LLVM_fragment, 0, 32){{.*}}) +;; This is the dbg.assign we care about: +; CHECK-NEXT: llvm.dbg.assign(metadata i1 undef, metadata ![[VAR:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 32, 160), metadata ![[ID]], metadata ptr %A.sroa.0.sroa.5, metadata !DIExpression()) + +; CHECK: ![[VAR]] = !DILocalVariable(name: "A" + +source_filename = "test.cpp" +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +%struct.Blob = type { [6 x i32] } + +@Glob = dso_local global %struct.Blob zeroinitializer, align 4 +@Cond = dso_local global i32 0, align 4 +@C = dso_local global ptr null, align 8 + +; Function Attrs: mustprogress uwtable +define dso_local void @_Z1fv() #0 !dbg !9 { +entry: + %A = alloca [16 x i32], align 16, !DIAssignID !18 + call void @llvm.dbg.assign(metadata i1 undef, metadata !13, metadata !DIExpression(), metadata !18, metadata ptr %A, metadata !DIExpression()), !dbg !19 + %B = alloca [16 x i32], align 16 + call void @llvm.lifetime.start.p0(i64 64, ptr %A) #5, !dbg !20 + call void @llvm.lifetime.start.p0(i64 64, ptr %B) #5, !dbg !21 + %arrayidx = getelementptr inbounds [16 x i32], ptr %A, i64 0, i64 0, !dbg !22 + call void @llvm.memmove.p0.p0.i64(ptr align 16 %arrayidx, ptr align 4 @Glob, i64 24, i1 false), !dbg !23, !DIAssignID !24 + call void @llvm.dbg.assign(metadata i1 undef, metadata !13, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 192), metadata !24, metadata ptr %arrayidx, metadata !DIExpression()), !dbg !19 + call void @_Z4calli(i32 noundef 0), !dbg !25 + %arrayidx1 = getelementptr inbounds [16 x i32], ptr %B, i64 0, i64 8, !dbg !26 + call void @llvm.memmove.p0.p0.i64(ptr align 16 %arrayidx1, ptr align 4 @Glob, i64 24, i1 false), !dbg !27 + %arrayidx2 = getelementptr inbounds [16 x i32], ptr %A, i64 0, i64 0, !dbg !28 + %0 = load i32, ptr %arrayidx2, align 16, !dbg !28 + call void @_Z4calli(i32 noundef %0), !dbg !33 + %arrayidx3 = getelementptr inbounds [16 x i32], ptr %A, i64 0, i64 8, !dbg !34 + %arrayidx4 = getelementptr inbounds [16 x i32], ptr %A, i64 0, i64 0, !dbg !35 + call void @llvm.memmove.p0.p0.i64(ptr align 16 %arrayidx3, ptr align 16 %arrayidx4, i64 24, i1 false), !dbg !36, !DIAssignID !37 + call void @llvm.dbg.assign(metadata i1 undef, metadata !13, metadata !DIExpression(DW_OP_LLVM_fragment, 256, 192), metadata !37, metadata ptr %arrayidx3, metadata !DIExpression()), !dbg !19 + %arrayidx5 = getelementptr inbounds [16 x i32], ptr %A, i64 0, i64 8, !dbg !38 + %1 = load i32, ptr %arrayidx5, align 16, !dbg !38 + call void @_Z4calli(i32 noundef %1), !dbg !39 + %2 = load i32, ptr @Cond, align 4, !dbg !40 + %tobool = icmp ne i32 %2, 0, !dbg !40 + br i1 %tobool, label %if.then, label %if.else, !dbg !42 + +if.then: ; preds = %entry + %3 = load ptr, ptr @C, align 8, !dbg !43 + %arrayidx6 = getelementptr inbounds [16 x i32], ptr %A, i64 0, i64 8, !dbg !46 + call void @llvm.memmove.p0.p0.i64(ptr align 4 %3, ptr align 16 %arrayidx6, i64 24, i1 false), !dbg !47 + br label %if.end, !dbg !47 + +if.else: ; preds = %entry + %4 = load ptr, ptr @C, align 8, !dbg !48 + %arrayidx7 = getelementptr inbounds [16 x i32], ptr %B, i64 0, i64 8, !dbg !49 + call void @llvm.memmove.p0.p0.i64(ptr align 4 %4, ptr align 16 %arrayidx7, i64 24, i1 false), !dbg !50 + br label %if.end + +if.end: ; preds = %if.else, %if.then + call void @llvm.lifetime.end.p0(i64 64, ptr %B) #5, !dbg !51 + call void @llvm.lifetime.end.p0(i64 64, ptr %A) #5, !dbg !51 + ret void, !dbg !51 +} + +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.dbg.declare(metadata, metadata, metadata) #2 +declare void @llvm.memmove.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1 immarg) #3 +declare void @_Z4calli(i32 noundef) #4 +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) #2 + + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3, !4, !5, !6, !7} +!llvm.ident = !{!8} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 16.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.cpp", directory: "/") +!2 = !{i32 7, !"Dwarf Version", i32 5} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !{i32 1, !"wchar_size", i32 4} +!5 = !{i32 8, !"PIC Level", i32 2} +!6 = !{i32 7, !"PIE Level", i32 2} +!7 = !{i32 7, !"uwtable", i32 2} +!8 = !{!"clang version 16.0.0"} +!9 = distinct !DISubprogram(name: "f", linkageName: "_Z1fv", scope: !1, file: !1, line: 6, type: !10, scopeLine: 6, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !12) +!10 = !DISubroutineType(types: !11) +!11 = !{null} +!12 = !{!13} +!13 = !DILocalVariable(name: "A", scope: !9, file: !1, line: 7, type: !14) +!14 = !DICompositeType(tag: DW_TAG_array_type, baseType: !15, size: 512, elements: !16) +!15 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!16 = !{!17} +!17 = !DISubrange(count: 16) +!18 = distinct !DIAssignID() +!19 = !DILocation(line: 0, scope: !9) +!20 = !DILocation(line: 7, column: 3, scope: !9) +!21 = !DILocation(line: 8, column: 3, scope: !9) +!22 = !DILocation(line: 10, column: 22, scope: !9) +!23 = !DILocation(line: 10, column: 3, scope: !9) +!24 = distinct !DIAssignID() +!25 = !DILocation(line: 11, column: 3, scope: !9) +!26 = !DILocation(line: 13, column: 22, scope: !9) +!27 = !DILocation(line: 13, column: 3, scope: !9) +!28 = !DILocation(line: 14, column: 8, scope: !9) +!33 = !DILocation(line: 14, column: 3, scope: !9) +!34 = !DILocation(line: 16, column: 22, scope: !9) +!35 = !DILocation(line: 16, column: 29, scope: !9) +!36 = !DILocation(line: 16, column: 3, scope: !9) +!37 = distinct !DIAssignID() +!38 = !DILocation(line: 17, column: 8, scope: !9) +!39 = !DILocation(line: 17, column: 3, scope: !9) +!40 = !DILocation(line: 18, column: 7, scope: !41) +!41 = distinct !DILexicalBlock(scope: !9, file: !1, line: 18, column: 7) +!42 = !DILocation(line: 18, column: 7, scope: !9) +!43 = !DILocation(line: 20, column: 23, scope: !41) +!46 = !DILocation(line: 20, column: 27, scope: !41) +!47 = !DILocation(line: 20, column: 5, scope: !41) +!48 = !DILocation(line: 23, column: 23, scope: !41) +!49 = !DILocation(line: 23, column: 27, scope: !41) +!50 = !DILocation(line: 23, column: 5, scope: !41) +!51 = !DILocation(line: 24, column: 1, scope: !9) diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/rewrite.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/rewrite.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/rewrite.ll @@ -0,0 +1,130 @@ +; RUN: opt -passes=sroa,verify -S %s -experimental-assignment-tracking -o - \ +; RUN: | FileCheck %s --implicit-check-not="call void @llvm.dbg" + +; Check that the new slices of an alloca and memset intructions get dbg.assign +; intrinsics with the correct fragment info. Ensure that only the +; value-expression gets fragment info; that the address-expression remains +; untouched. + +;; $ cat test.cpp +;; void do_something(); +;; struct LargeStruct { +;; int A, B, C; +;; int Var; +;; int D, E, F; +;; }; +;; int Glob; +;; bool Cond; +;; int example() { +;; LargeStruct S = {0}; +;; S.Var = Glob; +;; return S.Var; +;; } +;; $ clang test.cpp -Xclang -disable-llvm-passes -O2 -g -c -S -emit-llvm -o - + +; CHECK: entry: +; CHECK-NEXT: %S.sroa.0 = alloca { i32, i32, i32 }, align 8, !DIAssignID ![[ID_1:[0-9]+]] +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef, metadata ![[VAR:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96), metadata ![[ID_1]], metadata ptr %S.sroa.0, metadata !DIExpression()), !dbg + +;; The middle slice has been promoted, so the alloca has gone away. + +; CHECK-NEXT: %S.sroa.5 = alloca { i32, i32, i32 }, align 8, !DIAssignID ![[ID_3:[0-9]+]] +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef, metadata ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96), metadata ![[ID_3]], metadata ptr %S.sroa.5, metadata !DIExpression()), !dbg + +;; The memset has been sliced up (middle slice removed). +; CHECK: call void @llvm.memset{{.*}}(ptr align 8 %S.sroa.0, i8 0, i64 12, i1 false), !dbg !{{.+}}, !DIAssignID ![[ID_5:[0-9]+]] +; CHECK: call void @llvm.memset{{.*}}(ptr align 8 %S.sroa.5, i8 0, i64 12, i1 false), !dbg !{{.+}}, !DIAssignID ![[ID_6:[0-9]+]] + +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i8 0, metadata ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96), metadata ![[ID_5]], metadata ptr %S.sroa.0, metadata !DIExpression()), !dbg +;; Check the middle slice (no memset) gets a correct dbg.assign. +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 0, metadata ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i8 0, metadata ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96), metadata ![[ID_6]], metadata ptr %S.sroa.5, metadata !DIExpression()), !dbg + +;; mem2reg promotes the load/store to the middle slice created by SROA: +; CHECK-NEXT: %0 = load i32, ptr @Glob, align 4, !dbg !{{.+}} +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 %0, metadata ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32), metadata ![[ID_4:[0-9]+]], metadata ptr undef, metadata !DIExpression()), !dbg + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + +%struct.LargeStruct = type { i32, i32, i32, i32, i32, i32, i32 } + +@Glob = dso_local global i32 0, align 4, !dbg !0 +@Cond = dso_local global i8 0, align 1, !dbg !6 + +; Function Attrs: nounwind uwtable mustprogress +define dso_local i32 @_Z7examplev() #0 !dbg !14 { +entry: + %S = alloca %struct.LargeStruct, align 4, !DIAssignID !28 + call void @llvm.dbg.assign(metadata i1 undef, metadata !18, metadata !DIExpression(), metadata !28, metadata ptr %S, metadata !DIExpression()), !dbg !29 + %0 = bitcast ptr %S to ptr, !dbg !30 + call void @llvm.lifetime.start.p0i8(i64 28, ptr %0) #4, !dbg !30 + %1 = bitcast ptr %S to ptr, !dbg !31 + call void @llvm.memset.p0i8.i64(ptr align 4 %1, i8 0, i64 28, i1 false), !dbg !31, !DIAssignID !32 + call void @llvm.dbg.assign(metadata i8 0, metadata !18, metadata !DIExpression(), metadata !32, metadata ptr %1, metadata !DIExpression()), !dbg !31 + %2 = load i32, ptr @Glob, align 4, !dbg !33 + %Var = getelementptr inbounds %struct.LargeStruct, ptr %S, i32 0, i32 3, !dbg !38 + store i32 %2, ptr %Var, align 4, !dbg !39, !DIAssignID !42 + call void @llvm.dbg.assign(metadata i32 %2, metadata !18, metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32), metadata !42, metadata ptr %Var, metadata !DIExpression()), !dbg !39 + %Var1 = getelementptr inbounds %struct.LargeStruct, ptr %S, i32 0, i32 3, !dbg !43 + %3 = load i32, ptr %Var1, align 4, !dbg !43 + %4 = bitcast ptr %S to ptr, !dbg !44 + call void @llvm.lifetime.end.p0i8(i64 28, ptr %4) #4, !dbg !44 + ret i32 %3, !dbg !45 +} + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.start.p0i8(i64 immarg, ptr nocapture) #1 + +; Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly +declare void @llvm.memset.p0i8.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2 + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.end.p0i8(i64 immarg, ptr nocapture) #1 + +; Function Attrs: nofree nosync nounwind readnone speculatable willreturn +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) #3 + +!llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!10, !11, !12} +!llvm.ident = !{!13} + +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) +!1 = distinct !DIGlobalVariable(name: "Glob", scope: !2, file: !3, line: 7, type: !9, isLocal: false, isDefinition: true) +!2 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !3, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, splitDebugInlining: false, nameTableKind: None) +!3 = !DIFile(filename: "test.cpp", directory: "/") +!4 = !{} +!5 = !{!0, !6} +!6 = !DIGlobalVariableExpression(var: !7, expr: !DIExpression()) +!7 = distinct !DIGlobalVariable(name: "Cond", scope: !2, file: !3, line: 8, type: !8, isLocal: false, isDefinition: true) +!8 = !DIBasicType(name: "bool", size: 8, encoding: DW_ATE_boolean) +!9 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!10 = !{i32 7, !"Dwarf Version", i32 4} +!11 = !{i32 2, !"Debug Info Version", i32 3} +!12 = !{i32 1, !"wchar_size", i32 4} +!13 = !{!"clang version 12.0.0"} +!14 = distinct !DISubprogram(name: "example", linkageName: "_Z7examplev", scope: !3, file: !3, line: 9, type: !15, scopeLine: 9, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, retainedNodes: !17) +!15 = !DISubroutineType(types: !16) +!16 = !{!9} +!17 = !{!18} +!18 = !DILocalVariable(name: "S", scope: !14, file: !3, line: 10, type: !19) +!19 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "LargeStruct", file: !3, line: 2, size: 224, flags: DIFlagTypePassByValue, elements: !20, identifier: "_ZTS11LargeStruct") +!20 = !{!21, !22, !23, !24, !25, !26, !27} +!21 = !DIDerivedType(tag: DW_TAG_member, name: "A", scope: !19, file: !3, line: 3, baseType: !9, size: 32) +!22 = !DIDerivedType(tag: DW_TAG_member, name: "B", scope: !19, file: !3, line: 3, baseType: !9, size: 32, offset: 32) +!23 = !DIDerivedType(tag: DW_TAG_member, name: "C", scope: !19, file: !3, line: 3, baseType: !9, size: 32, offset: 64) +!24 = !DIDerivedType(tag: DW_TAG_member, name: "Var", scope: !19, file: !3, line: 4, baseType: !9, size: 32, offset: 96) +!25 = !DIDerivedType(tag: DW_TAG_member, name: "D", scope: !19, file: !3, line: 5, baseType: !9, size: 32, offset: 128) +!26 = !DIDerivedType(tag: DW_TAG_member, name: "E", scope: !19, file: !3, line: 5, baseType: !9, size: 32, offset: 160) +!27 = !DIDerivedType(tag: DW_TAG_member, name: "F", scope: !19, file: !3, line: 5, baseType: !9, size: 32, offset: 192) +!28 = distinct !DIAssignID() +!29 = !DILocation(line: 0, scope: !14) +!30 = !DILocation(line: 10, column: 3, scope: !14) +!31 = !DILocation(line: 10, column: 15, scope: !14) +!32 = distinct !DIAssignID() +!33 = !DILocation(line: 11, column: 11, scope: !14) +!38 = !DILocation(line: 11, column: 5, scope: !14) +!39 = !DILocation(line: 11, column: 9, scope: !14) +!42 = distinct !DIAssignID() +!43 = !DILocation(line: 12, column: 12, scope: !14) +!44 = !DILocation(line: 13, column: 1, scope: !14) +!45 = !DILocation(line: 12, column: 3, scope: !14) diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/store.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/store.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/store.ll @@ -0,0 +1,150 @@ +; RUN: opt -passes=sroa,verify -S %s -o - -experimental-assignment-tracking \ +; RUN: | FileCheck %s --implicit-check-not="call void @llvm.dbg" + +; Check that the new slices of an alloca and memset intructions get dbg.assign +; intrinsics with the correct fragment info. Ensure that only the +; value-expression gets fragment info; that the address-expression remains +; untouched. + +;; $ cat test.cpp +;; void do_something(); +;; struct LargeStruct { +;; int A, B, C; +;; int Var; +;; int D, E, F; +;; }; +;; int Glob; +;; bool Cond; +;; int use(LargeStruct); +;; int example() { +;; LargeStruct S = {0}; +;; S.Var = Glob; +;; use(S); +;; return S.Var; +;; } +;; $ clang test.cpp -Xclang -disable-llvm-passes -O2 -g -c -S -emit-llvm -o - \ +;; | opt -passes=declare-to-assign -S -o - + +; CHECK: entry: +; CHECK-NEXT: %S.sroa.0 = alloca { i32, i32, i32 }, align 8, !DIAssignID ![[ID_1:[0-9]+]] +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef, metadata ![[VAR:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96), metadata ![[ID_1]], metadata ptr %S.sroa.0, metadata !DIExpression()), !dbg + +; CHECK-NEXT: %S.sroa.6 = alloca { i32, i32, i32 }, align 8, !DIAssignID ![[ID_3:[0-9]+]] +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i1 undef, metadata ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96), metadata ![[ID_3]], metadata ptr %S.sroa.6, metadata !DIExpression()), !dbg + +;; The memset has been split into [0, 96)[96, 128)[128, 224) bit slices. The +;; memset for the middle slice has been removed. +; CHECK: call void @llvm.memset{{.*}}(ptr align 8 %S.sroa.0, i8 0, i64 12, i1 false), !dbg !{{.+}}, !DIAssignID ![[ID_4:[0-9]+]] +; CHECK-NEXT: call void @llvm.memset{{.*}}(ptr align 8 %S.sroa.6, i8 0, i64 12, i1 false), !dbg !{{.+}}, !DIAssignID ![[ID_5:[0-9]+]] + +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i8 0, metadata ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 96), metadata ![[ID_4]], metadata ptr %S.sroa.0, metadata !DIExpression()), !dbg +;; This is the one we care about most in this test: check that a memset->store +;; gets a correct dbg.assign. +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 0, metadata ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i8 0, metadata ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 96), metadata ![[ID_5]], metadata ptr %S.sroa.6, metadata !DIExpression()), !dbg + +;; The load from global+store becomes a load. +;; FIXME: In reality it is actually stored again later on. +; CHECK-NEXT: %0 = load i32, ptr @Glob, align 4, !dbg !{{.+}} +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i32 %0, metadata ![[VAR]], metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg ! + + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" + +%struct.LargeStruct = type { i32, i32, i32, i32, i32, i32, i32 } + +@Glob = dso_local global i32 0, align 4, !dbg !0 +@Cond = dso_local global i8 0, align 1, !dbg !6 + +; Function Attrs: uwtable mustprogress +define dso_local i32 @_Z7examplev() #0 !dbg !14 { +entry: + %S = alloca %struct.LargeStruct, align 4, !DIAssignID !28 + call void @llvm.dbg.assign(metadata i1 undef, metadata !18, metadata !DIExpression(), metadata !28, metadata ptr %S, metadata !DIExpression()), !dbg !29 + %agg.tmp = alloca %struct.LargeStruct, align 8 + %0 = bitcast ptr %S to ptr, !dbg !30 + call void @llvm.lifetime.start.p0i8(i64 28, ptr %0) #5, !dbg !30 + %1 = bitcast ptr %S to ptr, !dbg !31 + call void @llvm.memset.p0i8.i64(ptr align 4 %1, i8 0, i64 28, i1 false), !dbg !31, !DIAssignID !32 + call void @llvm.dbg.assign(metadata i8 0, metadata !18, metadata !DIExpression(), metadata !32, metadata ptr %1, metadata !DIExpression()), !dbg !31 + %2 = load i32, ptr @Glob, align 4, !dbg !33 + %Var = getelementptr inbounds %struct.LargeStruct, ptr %S, i32 0, i32 3, !dbg !38 + store i32 %2, ptr %Var, align 4, !dbg !39, !DIAssignID !42 + call void @llvm.dbg.assign(metadata i32 %2, metadata !18, metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32), metadata !42, metadata ptr %Var, metadata !DIExpression()), !dbg !39 + %3 = bitcast ptr %agg.tmp to ptr, !dbg !43 + %4 = bitcast ptr %S to ptr, !dbg !43 + call void @llvm.memcpy.p0i8.p0i8.i64(ptr align 4 %3, ptr align 4 %4, i64 28, i1 false), !dbg !43 + %call = call i32 @_Z3use11LargeStruct(ptr byval(%struct.LargeStruct) align 8 %agg.tmp), !dbg !45 + %Var1 = getelementptr inbounds %struct.LargeStruct, ptr %S, i32 0, i32 3, !dbg !46 + %5 = load i32, ptr %Var1, align 4, !dbg !46 + %6 = bitcast ptr %S to ptr, !dbg !47 + call void @llvm.lifetime.end.p0i8(i64 28, ptr %6) #5, !dbg !47 + ret i32 %5, !dbg !48 +} + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.start.p0i8(i64 immarg, ptr nocapture) #1 + +; Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly +declare void @llvm.memset.p0i8.i64(ptr nocapture writeonly, i8, i64, i1 immarg) #2 + +declare !dbg !49 dso_local i32 @_Z3use11LargeStruct(ptr byval(%struct.LargeStruct) align 8) #3 + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.memcpy.p0i8.p0i8.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1 + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.end.p0i8(i64 immarg, ptr nocapture) #1 + +; Function Attrs: nofree nosync nounwind readnone speculatable willreturn +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) #4 + +!llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!10, !11, !12} +!llvm.ident = !{!13} + +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) +!1 = distinct !DIGlobalVariable(name: "Glob", scope: !2, file: !3, line: 7, type: !9, isLocal: false, isDefinition: true) +!2 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !3, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, splitDebugInlining: false, nameTableKind: None) +!3 = !DIFile(filename: "test.cpp", directory: "/") +!4 = !{} +!5 = !{!0, !6} +!6 = !DIGlobalVariableExpression(var: !7, expr: !DIExpression()) +!7 = distinct !DIGlobalVariable(name: "Cond", scope: !2, file: !3, line: 8, type: !8, isLocal: false, isDefinition: true) +!8 = !DIBasicType(name: "bool", size: 8, encoding: DW_ATE_boolean) +!9 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!10 = !{i32 7, !"Dwarf Version", i32 4} +!11 = !{i32 2, !"Debug Info Version", i32 3} +!12 = !{i32 1, !"wchar_size", i32 4} +!13 = !{!"clang version 12.0.0"} +!14 = distinct !DISubprogram(name: "example", linkageName: "_Z7examplev", scope: !3, file: !3, line: 10, type: !15, scopeLine: 10, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, retainedNodes: !17) +!15 = !DISubroutineType(types: !16) +!16 = !{!9} +!17 = !{!18} +!18 = !DILocalVariable(name: "S", scope: !14, file: !3, line: 11, type: !19) +!19 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "LargeStruct", file: !3, line: 2, size: 224, flags: DIFlagTypePassByValue, elements: !20, identifier: "_ZTS11LargeStruct") +!20 = !{!21, !22, !23, !24, !25, !26, !27} +!21 = !DIDerivedType(tag: DW_TAG_member, name: "A", scope: !19, file: !3, line: 3, baseType: !9, size: 32) +!22 = !DIDerivedType(tag: DW_TAG_member, name: "B", scope: !19, file: !3, line: 3, baseType: !9, size: 32, offset: 32) +!23 = !DIDerivedType(tag: DW_TAG_member, name: "C", scope: !19, file: !3, line: 3, baseType: !9, size: 32, offset: 64) +!24 = !DIDerivedType(tag: DW_TAG_member, name: "Var", scope: !19, file: !3, line: 4, baseType: !9, size: 32, offset: 96) +!25 = !DIDerivedType(tag: DW_TAG_member, name: "D", scope: !19, file: !3, line: 5, baseType: !9, size: 32, offset: 128) +!26 = !DIDerivedType(tag: DW_TAG_member, name: "E", scope: !19, file: !3, line: 5, baseType: !9, size: 32, offset: 160) +!27 = !DIDerivedType(tag: DW_TAG_member, name: "F", scope: !19, file: !3, line: 5, baseType: !9, size: 32, offset: 192) +!28 = distinct !DIAssignID() +!29 = !DILocation(line: 0, scope: !14) +!30 = !DILocation(line: 11, column: 3, scope: !14) +!31 = !DILocation(line: 11, column: 15, scope: !14) +!32 = distinct !DIAssignID() +!33 = !DILocation(line: 12, column: 11, scope: !14) +!38 = !DILocation(line: 12, column: 5, scope: !14) +!39 = !DILocation(line: 12, column: 9, scope: !14) +!42 = distinct !DIAssignID() +!43 = !DILocation(line: 13, column: 7, scope: !14) +!45 = !DILocation(line: 13, column: 3, scope: !14) +!46 = !DILocation(line: 14, column: 12, scope: !14) +!47 = !DILocation(line: 15, column: 1, scope: !14) +!48 = !DILocation(line: 14, column: 3, scope: !14) +!49 = !DISubprogram(name: "use", linkageName: "_Z3use11LargeStruct", scope: !3, file: !3, line: 9, type: !50, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !4) +!50 = !DISubroutineType(types: !51) +!51 = !{!9, !19} diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/unspecified-var-size.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/unspecified-var-size.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/unspecified-var-size.ll @@ -0,0 +1,54 @@ +; RUN: opt -S %s -passes=sroa -o - -experimental-assignment-tracking | FileCheck %s + +;; $ cat test.cpp +;; #include +;; void fun(std::nullptr_t) {} +;; +;; Check that migrateDebugInfo doesn't crash when encountering an alloca for a +;; variable with a type of unspecified size (e.g. DW_TAG_unspecified_type). + +; CHECK: @llvm.dbg.assign(metadata ptr %0,{{.+}}, metadata !DIExpression(),{{.+}}, metadata ptr undef, {{.+}}) +;; There should be no new fragment and the value component should remain as %0. + +define dso_local void @_Z3funDn(ptr %0) #0 !dbg !14 { +entry: + %.addr = alloca i8*, align 8, !DIAssignID !22 + call void @llvm.dbg.assign(metadata i1 undef, metadata !21, metadata !DIExpression(), metadata !22, metadata ptr %.addr, metadata !DIExpression()), !dbg !23 + store ptr %0, ptr %.addr, align 8, !DIAssignID !28 + call void @llvm.dbg.assign(metadata ptr %0, metadata !21, metadata !DIExpression(), metadata !28, metadata ptr %.addr, metadata !DIExpression()), !dbg !23 + ret void, !dbg !29 +} + +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) #1 + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!10, !11, !12} +!llvm.ident = !{!13} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, imports: !3, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.cpp", directory: "/") +!2 = !{} +!3 = !{!4} +!4 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !6, file: !9, line: 56) +!5 = !DINamespace(name: "std", scope: null) +!6 = !DIDerivedType(tag: DW_TAG_typedef, name: "max_align_t", file: !7, line: 24, baseType: !8) +!7 = !DIFile(filename: "clang/12.0.0/include/__stddef_max_align_t.h", directory: "/") +!8 = !DICompositeType(tag: DW_TAG_structure_type, file: !7, line: 19, size: 256, flags: DIFlagFwdDecl, identifier: "_ZTS11max_align_t") +!9 = !DIFile(filename: "include/c++/7.5.0/cstddef", directory: "") +!10 = !{i32 7, !"Dwarf Version", i32 4} +!11 = !{i32 2, !"Debug Info Version", i32 3} +!12 = !{i32 1, !"wchar_size", i32 4} +!13 = !{!"clang version 12.0.0"} +!14 = distinct !DISubprogram(name: "fun", linkageName: "_Z3funDn", scope: !1, file: !1, line: 20, type: !15, scopeLine: 20, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !20) +!15 = !DISubroutineType(types: !16) +!16 = !{null, !17} +!17 = !DIDerivedType(tag: DW_TAG_typedef, name: "nullptr_t", scope: !5, file: !18, line: 235, baseType: !19) +!18 = !DIFile(filename: "include/x86_64-linux-gnu/c++/7.5.0/bits/c++config.h", directory: "") +!19 = !DIBasicType(tag: DW_TAG_unspecified_type, name: "decltype(nullptr)") +!20 = !{!21} +!21 = !DILocalVariable(arg: 1, scope: !14, file: !1, line: 20, type: !17) +!22 = distinct !DIAssignID() +!23 = !DILocation(line: 0, scope: !14) +!28 = distinct !DIAssignID() +!29 = !DILocation(line: 20, column: 27, scope: !14) diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/user-memcpy.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/user-memcpy.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/user-memcpy.ll @@ -0,0 +1,235 @@ +; RUN: opt -passes=sroa -S %s -o - -experimental-assignment-tracking \ +; RUN: | FileCheck %s --implicit-check-not="call void @llvm.dbg" + +;; Check that the fragments generated in SROA for a split alloca that has a +;; dbg.assign with non-zero-offset fragment already are correct. Ensure that +;; only the value-expression gets fragment info; that the address-expression +;; remains untouched. + +;; $ cat test.cpp +;; #include +;; +;; struct V3i { long x, y, z; }; +;; void fun() { +;; V3i point = {0, 0, 0}; +;; point.z = 5000; +;; V3i other = {10, 9, 8}; +;; std::memcpy(&point.y, &other.x, sizeof(long) * 2); +;; } +;; $ clang++ -c -O2 -g test.cpp -o - -Xclang -disable-llvm-passes -S -emit-llvm \ +;; | opt -passes=declare-to-assign -S -o - + +; CHECK: entry: +;; Allocas have been promoted - the linked dbg.assigns have been removed. + +;; | V3i point = {0, 0, 0}; +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 0, metadata ![[point:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 0, metadata ![[point]], metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 0, metadata ![[point]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 64), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg + +;; point.z = 5000; +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 5000, metadata ![[point]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 64), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg + +;; | V3i other = {10, 9, 8}; +;; other is global const: +;; local.other.x = global.other.x +;; local.other.y = global.other.y +;; local.other.z = global.other.z +; CHECK-NEXT: %other.sroa.0.0.copyload = load i64, ptr @__const._Z3funv.other +; CHECK-NEXT: %other.sroa.4.0.copyload = load i64, ptr getelementptr inbounds (i8, ptr @__const._Z3funv.other, i64 8) +; CHECK-NEXT: %other.sroa.5.0.copyload = load i64, ptr getelementptr inbounds (i8, ptr @__const._Z3funv.other, i64 16) +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 %other.sroa.0.0.copyload, metadata ![[other:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 %other.sroa.4.0.copyload, metadata ![[other]], metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 %other.sroa.5.0.copyload, metadata ![[other]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 64), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg + +;; | std::memcpy(&point.y, &other.x, sizeof(long) * 2); +;; other is now 3 scalars: +;; point.y = other.x +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 %other.sroa.0.0.copyload, metadata ![[point]], metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg +;; +;; point.z = other.y +; CHECK-NEXT: call void @llvm.dbg.assign(metadata i64 %other.sroa.4.0.copyload, metadata ![[point]], metadata !DIExpression(DW_OP_LLVM_fragment, 128, 64), metadata !{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg + +; CHECK: ![[point]] = !DILocalVariable(name: "point", +; CHECK: ![[other]] = !DILocalVariable(name: "other", + +source_filename = "test.cpp" +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +%struct.V3i = type { i64, i64, i64 } + +@__const._Z3funv.other = private unnamed_addr constant %struct.V3i { i64 10, i64 9, i64 8 }, align 8 + +; Function Attrs: nounwind uwtable mustprogress +define dso_local void @_Z3funv() !dbg !100 { +entry: + %point = alloca %struct.V3i, align 8, !DIAssignID !112 + call void @llvm.dbg.assign(metadata i1 undef, metadata !104, metadata !DIExpression(), metadata !112, metadata ptr %point, metadata !DIExpression()), !dbg !113 + %other = alloca %struct.V3i, align 8, !DIAssignID !114 + call void @llvm.dbg.assign(metadata i1 undef, metadata !111, metadata !DIExpression(), metadata !114, metadata ptr %other, metadata !DIExpression()), !dbg !113 + %0 = bitcast ptr %point to ptr, !dbg !115 + call void @llvm.lifetime.start.p0i8(i64 24, ptr %0), !dbg !115 + %1 = bitcast ptr %point to ptr, !dbg !116 + call void @llvm.memset.p0i8.i64(ptr align 8 %1, i8 0, i64 24, i1 false), !dbg !116, !DIAssignID !117 + call void @llvm.dbg.assign(metadata i8 0, metadata !104, metadata !DIExpression(), metadata !117, metadata ptr %1, metadata !DIExpression()), !dbg !116 + %z = getelementptr inbounds %struct.V3i, ptr %point, i32 0, i32 2, !dbg !118 + store i64 5000, ptr %z, align 8, !dbg !119, !DIAssignID !125 + call void @llvm.dbg.assign(metadata i64 5000, metadata !104, metadata !DIExpression(DW_OP_LLVM_fragment, 128, 64), metadata !125, metadata ptr %z, metadata !DIExpression()), !dbg !119 + %2 = bitcast ptr %other to ptr, !dbg !126 + call void @llvm.lifetime.start.p0i8(i64 24, ptr %2), !dbg !126 + %3 = bitcast ptr %other to ptr, !dbg !127 + call void @llvm.memcpy.p0i8.p0i8.i64(ptr align 8 %3, ptr align 8 bitcast (ptr @__const._Z3funv.other to ptr), i64 24, i1 false), !dbg !127, !DIAssignID !128 + call void @llvm.dbg.assign(metadata i1 undef, metadata !111, metadata !DIExpression(), metadata !128, metadata ptr %3, metadata !DIExpression()), !dbg !127 + %y = getelementptr inbounds %struct.V3i, ptr %point, i32 0, i32 1, !dbg !129 + %4 = bitcast ptr %y to ptr, !dbg !130 + %x = getelementptr inbounds %struct.V3i, ptr %other, i32 0, i32 0, !dbg !131 + %5 = bitcast ptr %x to ptr, !dbg !130 + call void @llvm.memcpy.p0i8.p0i8.i64(ptr align 8 %4, ptr align 8 %5, i64 16, i1 false), !dbg !130, !DIAssignID !132 + call void @llvm.dbg.assign(metadata i1 undef, metadata !104, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 128), metadata !132, metadata ptr %4, metadata !DIExpression()), !dbg !130 + %6 = bitcast ptr %other to ptr, !dbg !133 + call void @llvm.lifetime.end.p0i8(i64 24, ptr %6), !dbg !133 + %7 = bitcast ptr %point to ptr, !dbg !133 + call void @llvm.lifetime.end.p0i8(i64 24, ptr %7), !dbg !133 + ret void, !dbg !133 +} + +declare void @llvm.lifetime.start.p0i8(i64 immarg, ptr nocapture) +declare void @llvm.memset.p0i8.i64(ptr nocapture writeonly, i8, i64, i1 immarg) +declare void @llvm.memcpy.p0i8.p0i8.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) +declare void @llvm.lifetime.end.p0i8(i64 immarg, ptr nocapture) +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!96, !97, !98} +!llvm.ident = !{!99} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, imports: !3, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.cpp", directory: "/") +!2 = !{} +!3 = !{!4, !18, !22, !28, !32, !36, !46, !50, !52, !54, !58, !62, !66, !70, !74, !76, !78, !80, !84, !88, !92, !94} +!4 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !6, file: !17, line: 75) +!5 = !DINamespace(name: "std", scope: null) +!6 = !DISubprogram(name: "memchr", scope: !7, file: !7, line: 90, type: !8, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!7 = !DIFile(filename: "/usr/include/string.h", directory: "") +!8 = !DISubroutineType(types: !9) +!9 = !{!10, !11, !13, !14} +!10 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: null, size: 64) +!11 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !12, size: 64) +!12 = !DIDerivedType(tag: DW_TAG_const_type, baseType: null) +!13 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) +!14 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", file: !15, line: 46, baseType: !16) +!15 = !DIFile(filename: "lib/clang/12.0.0/include/stddef.h", directory: "/") +!16 = !DIBasicType(name: "long unsigned int", size: 64, encoding: DW_ATE_unsigned) +!17 = !DIFile(filename: "/usr/lib/gcc/x86_64-linux-gnu/7.5.0/../../../../include/c++/7.5.0/cstring", directory: "") +!18 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !19, file: !17, line: 76) +!19 = !DISubprogram(name: "memcmp", scope: !7, file: !7, line: 63, type: !20, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!20 = !DISubroutineType(types: !21) +!21 = !{!13, !11, !11, !14} +!22 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !23, file: !17, line: 77) +!23 = !DISubprogram(name: "memcpy", scope: !7, file: !7, line: 42, type: !24, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!24 = !DISubroutineType(types: !25) +!25 = !{!10, !26, !27, !14} +!26 = !DIDerivedType(tag: DW_TAG_restrict_type, baseType: !10) +!27 = !DIDerivedType(tag: DW_TAG_restrict_type, baseType: !11) +!28 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !29, file: !17, line: 78) +!29 = !DISubprogram(name: "memmove", scope: !7, file: !7, line: 46, type: !30, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!30 = !DISubroutineType(types: !31) +!31 = !{!10, !10, !11, !14} +!32 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !33, file: !17, line: 79) +!33 = !DISubprogram(name: "memset", scope: !7, file: !7, line: 60, type: !34, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!34 = !DISubroutineType(types: !35) +!35 = !{!10, !10, !13, !14} +!36 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !37, file: !17, line: 80) +!37 = !DISubprogram(name: "strcat", scope: !7, file: !7, line: 129, type: !38, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!38 = !DISubroutineType(types: !39) +!39 = !{!40, !42, !43} +!40 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !41, size: 64) +!41 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) +!42 = !DIDerivedType(tag: DW_TAG_restrict_type, baseType: !40) +!43 = !DIDerivedType(tag: DW_TAG_restrict_type, baseType: !44) +!44 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !45, size: 64) +!45 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !41) +!46 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !47, file: !17, line: 81) +!47 = !DISubprogram(name: "strcmp", scope: !7, file: !7, line: 136, type: !48, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!48 = !DISubroutineType(types: !49) +!49 = !{!13, !44, !44} +!50 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !51, file: !17, line: 82) +!51 = !DISubprogram(name: "strcoll", scope: !7, file: !7, line: 143, type: !48, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!52 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !53, file: !17, line: 83) +!53 = !DISubprogram(name: "strcpy", scope: !7, file: !7, line: 121, type: !38, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!54 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !55, file: !17, line: 84) +!55 = !DISubprogram(name: "strcspn", scope: !7, file: !7, line: 272, type: !56, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!56 = !DISubroutineType(types: !57) +!57 = !{!14, !44, !44} +!58 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !59, file: !17, line: 85) +!59 = !DISubprogram(name: "strerror", scope: !7, file: !7, line: 396, type: !60, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!60 = !DISubroutineType(types: !61) +!61 = !{!40, !13} +!62 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !63, file: !17, line: 86) +!63 = !DISubprogram(name: "strlen", scope: !7, file: !7, line: 384, type: !64, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!64 = !DISubroutineType(types: !65) +!65 = !{!14, !44} +!66 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !67, file: !17, line: 87) +!67 = !DISubprogram(name: "strncat", scope: !7, file: !7, line: 132, type: !68, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!68 = !DISubroutineType(types: !69) +!69 = !{!40, !42, !43, !14} +!70 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !71, file: !17, line: 88) +!71 = !DISubprogram(name: "strncmp", scope: !7, file: !7, line: 139, type: !72, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!72 = !DISubroutineType(types: !73) +!73 = !{!13, !44, !44, !14} +!74 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !75, file: !17, line: 89) +!75 = !DISubprogram(name: "strncpy", scope: !7, file: !7, line: 124, type: !68, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!76 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !77, file: !17, line: 90) +!77 = !DISubprogram(name: "strspn", scope: !7, file: !7, line: 276, type: !56, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!78 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !79, file: !17, line: 91) +!79 = !DISubprogram(name: "strtok", scope: !7, file: !7, line: 335, type: !38, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!80 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !81, file: !17, line: 92) +!81 = !DISubprogram(name: "strxfrm", scope: !7, file: !7, line: 146, type: !82, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!82 = !DISubroutineType(types: !83) +!83 = !{!14, !42, !43, !14} +!84 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !85, file: !17, line: 93) +!85 = !DISubprogram(name: "strchr", scope: !7, file: !7, line: 225, type: !86, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!86 = !DISubroutineType(types: !87) +!87 = !{!40, !44, !13} +!88 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !89, file: !17, line: 94) +!89 = !DISubprogram(name: "strpbrk", scope: !7, file: !7, line: 302, type: !90, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!90 = !DISubroutineType(types: !91) +!91 = !{!40, !44, !44} +!92 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !93, file: !17, line: 95) +!93 = !DISubprogram(name: "strrchr", scope: !7, file: !7, line: 252, type: !86, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!94 = !DIImportedEntity(tag: DW_TAG_imported_declaration, scope: !5, entity: !95, file: !17, line: 96) +!95 = !DISubprogram(name: "strstr", scope: !7, file: !7, line: 329, type: !90, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!96 = !{i32 7, !"Dwarf Version", i32 4} +!97 = !{i32 2, !"Debug Info Version", i32 3} +!98 = !{i32 1, !"wchar_size", i32 4} +!99 = !{!"clang version 12.0.0"} +!100 = distinct !DISubprogram(name: "fun", linkageName: "_Z3funv", scope: !1, file: !1, line: 4, type: !101, scopeLine: 4, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !103) +!101 = !DISubroutineType(types: !102) +!102 = !{null} +!103 = !{!104, !111} +!104 = !DILocalVariable(name: "point", scope: !100, file: !1, line: 5, type: !105) +!105 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "V3i", file: !1, line: 3, size: 192, flags: DIFlagTypePassByValue, elements: !106, identifier: "_ZTS3V3i") +!106 = !{!107, !109, !110} +!107 = !DIDerivedType(tag: DW_TAG_member, name: "x", scope: !105, file: !1, line: 3, baseType: !108, size: 64) +!108 = !DIBasicType(name: "long int", size: 64, encoding: DW_ATE_signed) +!109 = !DIDerivedType(tag: DW_TAG_member, name: "y", scope: !105, file: !1, line: 3, baseType: !108, size: 64, offset: 64) +!110 = !DIDerivedType(tag: DW_TAG_member, name: "z", scope: !105, file: !1, line: 3, baseType: !108, size: 64, offset: 128) +!111 = !DILocalVariable(name: "other", scope: !100, file: !1, line: 7, type: !105) +!112 = distinct !DIAssignID() +!113 = !DILocation(line: 0, scope: !100) +!114 = distinct !DIAssignID() +!115 = !DILocation(line: 5, column: 3, scope: !100) +!116 = !DILocation(line: 5, column: 7, scope: !100) +!117 = distinct !DIAssignID() +!118 = !DILocation(line: 6, column: 9, scope: !100) +!119 = !DILocation(line: 6, column: 11, scope: !100) +!125 = distinct !DIAssignID() +!126 = !DILocation(line: 7, column: 3, scope: !100) +!127 = !DILocation(line: 7, column: 7, scope: !100) +!128 = distinct !DIAssignID() +!129 = !DILocation(line: 8, column: 22, scope: !100) +!130 = !DILocation(line: 8, column: 3, scope: !100) +!131 = !DILocation(line: 8, column: 32, scope: !100) +!132 = distinct !DIAssignID() +!133 = !DILocation(line: 9, column: 1, scope: !100) diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-1.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-1.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-1.ll @@ -0,0 +1,104 @@ +; RUN: opt %s -S -passes=sroa -o - -experimental-assignment-tracking | FileCheck %s + +;; Ensure that only the value-expression gets fragment info; that the +;; address-expression remains untouched. + +;; $ cat test.cpp +;; class a { +;; float b[4]; +;; }; +;; class c { +;; a m_fn1() const; +;; void d() const; +;; }; +;; void c::d() const { a e = m_fn1(); } +;; +;; Generated by grabbing IR before sroa in: +;; $ clang++ -O2 -g -c test.cpp -Xclang -fexperimental-assignment-tracking + +; CHECK: %call = call +; CHECK-NEXT: %0 = extractvalue { <2 x float>, <2 x float> } %call, 0 +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float> %0, metadata ![[var:[0-9]+]], metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata ![[id1:[0-9]+]],{{.+}} undef, metadata !DIExpression()), !dbg +; CHECK-NEXT: %1 = extractvalue { <2 x float>, <2 x float> } %call, 1 +; CHECK-NEXT: call void @llvm.dbg.assign(metadata <2 x float> %1, metadata ![[var]], metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata ![[id2:[0-9]+]], {{.+}} undef, metadata !DIExpression()), !dbg + +%class.c = type { i8 } +%class.a = type { [4 x float] } + +; Function Attrs: uwtable +define dso_local void @_ZNK1c1dEv(ptr %this) #0 align 2 !dbg !7 { +entry: + %this.addr = alloca ptr, align 8, !DIAssignID !29 + call void @llvm.dbg.assign(metadata i1 undef, metadata !26, metadata !DIExpression(), metadata !29, metadata ptr %this.addr, metadata !DIExpression()), !dbg !30 + %e = alloca %class.a, align 4, !DIAssignID !31 + call void @llvm.dbg.assign(metadata i1 undef, metadata !28, metadata !DIExpression(), metadata !31, metadata ptr %e, metadata !DIExpression()), !dbg !30 + store ptr %this, ptr %this.addr, align 8, !DIAssignID !36 + call void @llvm.dbg.assign(metadata ptr %this, metadata !26, metadata !DIExpression(), metadata !36, metadata ptr %this.addr, metadata !DIExpression()), !dbg !30 + %this1 = load ptr, ptr %this.addr, align 8 + %0 = bitcast ptr %e to ptr, !dbg !37 + call void @llvm.lifetime.start.p0i8(i64 16, ptr %0) #4, !dbg !37 + %call = call { <2 x float>, <2 x float> } @_ZNK1c5m_fn1Ev(ptr %this1), !dbg !38 + %coerce.dive = getelementptr inbounds %class.a, ptr %e, i32 0, i32 0, !dbg !38 + %1 = bitcast ptr %coerce.dive to ptr, !dbg !38 + %2 = getelementptr inbounds { <2 x float>, <2 x float> }, ptr %1, i32 0, i32 0, !dbg !38 + %3 = extractvalue { <2 x float>, <2 x float> } %call, 0, !dbg !38 + store <2 x float> %3, ptr %2, align 4, !dbg !38, !DIAssignID !39 + call void @llvm.dbg.assign(metadata <2 x float> %3, metadata !28, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata !39, metadata ptr %2, metadata !DIExpression()), !dbg !30 + %4 = getelementptr inbounds { <2 x float>, <2 x float> }, ptr %1, i32 0, i32 1, !dbg !38 + %5 = extractvalue { <2 x float>, <2 x float> } %call, 1, !dbg !38 + store <2 x float> %5, ptr %4, align 4, !dbg !38, !DIAssignID !40 + call void @llvm.dbg.assign(metadata <2 x float> %5, metadata !28, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata !40, metadata ptr %4, metadata !DIExpression()), !dbg !30 + %6 = bitcast ptr %e to ptr, !dbg !41 + call void @llvm.lifetime.end.p0i8(i64 16, ptr %6) #4, !dbg !41 + ret void, !dbg !41 +} + +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 +declare void @llvm.lifetime.start.p0i8(i64 immarg, ptr nocapture) #2 +declare dso_local { <2 x float>, <2 x float> } @_ZNK1c5m_fn1Ev(ptr) #3 +declare void @llvm.lifetime.end.p0i8(i64 immarg, ptr nocapture) #2 +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) #1 + + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4, !5} +!llvm.ident = !{!6} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "test.cpp", directory: "/") +!2 = !{} +!3 = !{i32 7, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{i32 1, !"wchar_size", i32 4} +!6 = !{!"clang version 12.0.0"} +!7 = distinct !DISubprogram(name: "d", linkageName: "_ZNK1c1dEv", scope: !8, file: !1, line: 8, type: !23, scopeLine: 8, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, declaration: !22, retainedNodes: !25) +!8 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "c", file: !1, line: 4, size: 8, flags: DIFlagTypePassByValue, elements: !9, identifier: "_ZTS1c") +!9 = !{!10, !22} +!10 = !DISubprogram(name: "m_fn1", linkageName: "_ZNK1c5m_fn1Ev", scope: !8, file: !1, line: 5, type: !11, scopeLine: 5, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!11 = !DISubroutineType(types: !12) +!12 = !{!13, !20} +!13 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "a", file: !1, line: 1, size: 128, flags: DIFlagTypePassByValue, elements: !14, identifier: "_ZTS1a") +!14 = !{!15} +!15 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !13, file: !1, line: 2, baseType: !16, size: 128) +!16 = !DICompositeType(tag: DW_TAG_array_type, baseType: !17, size: 128, elements: !18) +!17 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) +!18 = !{!19} +!19 = !DISubrange(count: 4) +!20 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !21, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer) +!21 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !8) +!22 = !DISubprogram(name: "d", linkageName: "_ZNK1c1dEv", scope: !8, file: !1, line: 6, type: !23, scopeLine: 6, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized) +!23 = !DISubroutineType(types: !24) +!24 = !{null, !20} +!25 = !{!26, !28} +!26 = !DILocalVariable(name: "this", arg: 1, scope: !7, type: !27, flags: DIFlagArtificial | DIFlagObjectPointer) +!27 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !21, size: 64) +!28 = !DILocalVariable(name: "e", scope: !7, file: !1, line: 8, type: !13) +!29 = distinct !DIAssignID() +!30 = !DILocation(line: 0, scope: !7) +!31 = distinct !DIAssignID() +!36 = distinct !DIAssignID() +!37 = !DILocation(line: 8, column: 21, scope: !7) +!38 = !DILocation(line: 8, column: 27, scope: !7) +!39 = distinct !DIAssignID() +!40 = distinct !DIAssignID() +!41 = !DILocation(line: 8, column: 36, scope: !7) diff --git a/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-2.ll b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-2.ll new file mode 100644 --- /dev/null +++ b/llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-2.ll @@ -0,0 +1,206 @@ +; RUN: opt %s -S -passes=sroa -o - -experimental-assignment-tracking | FileCheck %s + +;; $ cat test.cpp +;; class a { +;; protected: +;; float b[4]; +;; }; +;; float c; +;; class d : a { +;; public: +;; d() { b[3] = c; } +;; void e() {} +;; }; +;; d f(); +;; void g() { +;; d j = f(), h = j, i = h; +;; i.e(); +;; i = d(); +;; } +;; +;; Generated by grabbing IR before sroa in: +;; $ clang++ -O2 -g -c test.cpp -Xclang -fexperimental-assignment-tracking + +;; Check that the dbg.assign value is scalar rather than a vector value because +;; we don't have a way of indexing a vector from within a +;; dbg.assign/DIExpression. Ensure that only the value-expression gets fragment +;; info; that the address-expression remains untouched. + +; CHECK: %i.sroa.4.12.vec.insert = insertelement <2 x float> %i.sroa.4.0.vec.insert, float %2, i32 1, !dbg +;; There's a few dbg intrinsics we're not interested in testing wedged in here. +; CHECK-NEXT: dbg.value +; CHECK-NEXT: dbg.assign +; CHECK-NEXT: dbg.assign +; CHECK-NEXT: call void @llvm.dbg.assign(metadata float %2,{{.+}}, metadata !DIExpression(DW_OP_LLVM_fragment, 96, 32),{{.+}}, metadata ptr undef, metadata !DIExpression()), !dbg + +%class.d = type { %class.a } +%class.a = type { [4 x float] } + +$_ZN1d1eEv = comdat any + +$_ZN1dC2Ev = comdat any + +@c = dso_local local_unnamed_addr global float 0.000000e+00, align 4, !dbg !0 + +; Function Attrs: uwtable +define dso_local void @_Z1gv() local_unnamed_addr #0 !dbg !11 { +entry: + call void @llvm.dbg.assign(metadata i1 undef, metadata !15, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata !32, metadata ptr undef, metadata !DIExpression()), !dbg !33 + call void @llvm.dbg.assign(metadata i1 undef, metadata !15, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata !34, metadata ptr undef, metadata !DIExpression()), !dbg !33 + call void @llvm.dbg.assign(metadata i1 undef, metadata !30, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata !35, metadata ptr undef, metadata !DIExpression()), !dbg !33 + call void @llvm.dbg.assign(metadata i1 undef, metadata !30, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata !36, metadata ptr undef, metadata !DIExpression()), !dbg !33 + %i = alloca %class.d, align 8, !DIAssignID !37 + call void @llvm.dbg.assign(metadata i1 undef, metadata !31, metadata !DIExpression(), metadata !37, metadata ptr %i, metadata !DIExpression()), !dbg !33 + %ref.tmp = alloca %class.d, align 4 + %call = call { <2 x float>, <2 x float> } @_Z1fv(), !dbg !38 + %0 = extractvalue { <2 x float>, <2 x float> } %call, 0, !dbg !38 + call void @llvm.dbg.assign(metadata <2 x float> %0, metadata !15, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata !39, metadata ptr undef, metadata !DIExpression()), !dbg !33 + %1 = extractvalue { <2 x float>, <2 x float> } %call, 1, !dbg !38 + call void @llvm.dbg.assign(metadata <2 x float> %1, metadata !15, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata !40, metadata ptr undef, metadata !DIExpression()), !dbg !33 + call void @llvm.dbg.assign(metadata <2 x float> %0, metadata !30, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata !41, metadata ptr undef, metadata !DIExpression()), !dbg !33 + call void @llvm.dbg.assign(metadata <2 x float> %1, metadata !30, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata !42, metadata ptr undef, metadata !DIExpression()), !dbg !33 + %2 = bitcast ptr %i to ptr, !dbg !43 + call void @llvm.lifetime.start.p0i8(i64 16, ptr nonnull %2) #5, !dbg !43 + %h.sroa.0.sroa.0.0.h.sroa.0.0..sroa_cast4.sroa_cast = bitcast ptr %i to ptr, !dbg !44 + store <2 x float> %0, ptr %h.sroa.0.sroa.0.0.h.sroa.0.0..sroa_cast4.sroa_cast, align 8, !dbg !44, !DIAssignID !45 + call void @llvm.dbg.assign(metadata <2 x float> %0, metadata !31, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64), metadata !45, metadata ptr %h.sroa.0.sroa.0.0.h.sroa.0.0..sroa_cast4.sroa_cast, metadata !DIExpression()), !dbg !33 + %h.sroa.0.sroa.4.0.h.sroa.0.0..sroa_cast4.sroa_idx13 = getelementptr inbounds %class.d, ptr %i, i64 0, i32 0, i32 0, i64 2, !dbg !44 + %h.sroa.0.sroa.4.0.h.sroa.0.0..sroa_cast4.sroa_cast = bitcast ptr %h.sroa.0.sroa.4.0.h.sroa.0.0..sroa_cast4.sroa_idx13 to ptr, !dbg !44 + store <2 x float> %1, ptr %h.sroa.0.sroa.4.0.h.sroa.0.0..sroa_cast4.sroa_cast, align 8, !dbg !44, !DIAssignID !46 + call void @llvm.dbg.assign(metadata <2 x float> %1, metadata !31, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64), metadata !46, metadata ptr %h.sroa.0.sroa.4.0.h.sroa.0.0..sroa_cast4.sroa_cast, metadata !DIExpression()), !dbg !33 + call void @llvm.dbg.assign(metadata i1 undef, metadata !47, metadata !DIExpression(), metadata !51, metadata ptr undef, metadata !DIExpression()), !dbg !52 + call void @llvm.dbg.assign(metadata ptr %i, metadata !47, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !52 + %3 = bitcast ptr %ref.tmp to ptr, !dbg !55 + call void @llvm.lifetime.start.p0i8(i64 16, ptr nonnull %3) #5, !dbg !55 + call void @llvm.dbg.assign(metadata i1 undef, metadata !56, metadata !DIExpression(), metadata !59, metadata ptr undef, metadata !DIExpression()), !dbg !60 + call void @llvm.dbg.assign(metadata ptr %ref.tmp, metadata !56, metadata !DIExpression(), metadata !62, metadata ptr undef, metadata !DIExpression()), !dbg !60 + %4 = load float, ptr @c, align 4, !dbg !63 + %arrayidx.i = getelementptr inbounds %class.d, ptr %ref.tmp, i64 0, i32 0, i32 0, i64 3, !dbg !69 + store float %4, ptr %arrayidx.i, align 4, !dbg !70 + call void @llvm.memcpy.p0i8.p0i8.i64(ptr nonnull align 8 dereferenceable(16) %2, ptr nonnull align 4 dereferenceable(16) %3, i64 16, i1 false), !dbg !71, !DIAssignID !72 + call void @llvm.dbg.assign(metadata i1 undef, metadata !31, metadata !DIExpression(), metadata !72, metadata ptr %2, metadata !DIExpression()), !dbg !33 + call void @llvm.lifetime.end.p0i8(i64 16, ptr nonnull %3) #5, !dbg !73 + call void @llvm.lifetime.end.p0i8(i64 16, ptr nonnull %2) #5, !dbg !74 + ret void, !dbg !74 +} + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.lifetime.start.p0i8(i64 immarg, ptr nocapture) #1 + +declare !dbg !75 dso_local { <2 x float>, <2 x float> } @_Z1fv() local_unnamed_addr #2 + +; Function Attrs: argmemonly nofree nosync nounwind willreturn +declare void @llvm.memcpy.p0i8.p0i8.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) #1 + +; Function Attrs: nounwind uwtable +define linkonce_odr dso_local void @_ZN1d1eEv(ptr %this) local_unnamed_addr #3 comdat align 2 !dbg !48 { +entry: + call void @llvm.dbg.assign(metadata i1 undef, metadata !47, metadata !DIExpression(), metadata !78, metadata ptr undef, metadata !DIExpression()), !dbg !79 + call void @llvm.dbg.assign(metadata ptr %this, metadata !47, metadata !DIExpression(), metadata !80, metadata ptr undef, metadata !DIExpression()), !dbg !79 + ret void, !dbg !81 +} + +; Function Attrs: nounwind uwtable +define linkonce_odr dso_local void @_ZN1dC2Ev(ptr %this) unnamed_addr #3 comdat align 2 !dbg !57 { +entry: + call void @llvm.dbg.assign(metadata i1 undef, metadata !56, metadata !DIExpression(), metadata !82, metadata ptr undef, metadata !DIExpression()), !dbg !83 + call void @llvm.dbg.assign(metadata ptr %this, metadata !56, metadata !DIExpression(), metadata !84, metadata ptr undef, metadata !DIExpression()), !dbg !83 + %0 = load float, ptr @c, align 4, !dbg !85 + %arrayidx = getelementptr inbounds %class.d, ptr %this, i64 0, i32 0, i32 0, i64 3, !dbg !86 + store float %0, ptr %arrayidx, align 4, !dbg !87 + ret void, !dbg !88 +} + +declare void @llvm.lifetime.end.p0i8(i64 immarg, ptr nocapture) #1 +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) #4 + +!llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!7, !8, !9} +!llvm.ident = !{!10} + +!0 = !DIGlobalVariableExpression(var: !1, expr: !DIExpression()) +!1 = distinct !DIGlobalVariable(name: "c", scope: !2, file: !3, line: 5, type: !6, isLocal: false, isDefinition: true) +!2 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !3, producer: "clang version 12.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !4, globals: !5, splitDebugInlining: false, nameTableKind: None) +!3 = !DIFile(filename: "test.cpp", directory: "/") +!4 = !{} +!5 = !{!0} +!6 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float) +!7 = !{i32 7, !"Dwarf Version", i32 4} +!8 = !{i32 2, !"Debug Info Version", i32 3} +!9 = !{i32 1, !"wchar_size", i32 4} +!10 = !{!"clang version 12.0.0"} +!11 = distinct !DISubprogram(name: "g", linkageName: "_Z1gv", scope: !3, file: !3, line: 12, type: !12, scopeLine: 12, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, retainedNodes: !14) +!12 = !DISubroutineType(types: !13) +!13 = !{null} +!14 = !{!15, !30, !31} +!15 = !DILocalVariable(name: "j", scope: !11, file: !3, line: 13, type: !16) +!16 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "d", file: !3, line: 6, size: 128, flags: DIFlagTypePassByValue | DIFlagNonTrivial, elements: !17, identifier: "_ZTS1d") +!17 = !{!18, !25, !29} +!18 = !DIDerivedType(tag: DW_TAG_inheritance, scope: !16, baseType: !19, extraData: i32 0) +!19 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "a", file: !3, line: 1, size: 128, flags: DIFlagTypePassByValue, elements: !20, identifier: "_ZTS1a") +!20 = !{!21} +!21 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !19, file: !3, line: 3, baseType: !22, size: 128, flags: DIFlagProtected) +!22 = !DICompositeType(tag: DW_TAG_array_type, baseType: !6, size: 128, elements: !23) +!23 = !{!24} +!24 = !DISubrange(count: 4) +!25 = !DISubprogram(name: "d", scope: !16, file: !3, line: 8, type: !26, scopeLine: 8, flags: DIFlagPublic | DIFlagPrototyped, spFlags: DISPFlagOptimized) +!26 = !DISubroutineType(types: !27) +!27 = !{null, !28} +!28 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !16, size: 64, flags: DIFlagArtificial | DIFlagObjectPointer) +!29 = !DISubprogram(name: "e", linkageName: "_ZN1d1eEv", scope: !16, file: !3, line: 9, type: !26, scopeLine: 9, flags: DIFlagPublic | DIFlagPrototyped, spFlags: DISPFlagOptimized) +!30 = !DILocalVariable(name: "h", scope: !11, file: !3, line: 13, type: !16) +!31 = !DILocalVariable(name: "i", scope: !11, file: !3, line: 13, type: !16) +!32 = distinct !DIAssignID() +!33 = !DILocation(line: 0, scope: !11) +!34 = distinct !DIAssignID() +!35 = distinct !DIAssignID() +!36 = distinct !DIAssignID() +!37 = distinct !DIAssignID() +!38 = !DILocation(line: 13, column: 9, scope: !11) +!39 = distinct !DIAssignID() +!40 = distinct !DIAssignID() +!41 = distinct !DIAssignID() +!42 = distinct !DIAssignID() +!43 = !DILocation(line: 13, column: 3, scope: !11) +!44 = !DILocation(line: 13, column: 25, scope: !11) +!45 = distinct !DIAssignID() +!46 = distinct !DIAssignID() +!47 = !DILocalVariable(name: "this", arg: 1, scope: !48, type: !50, flags: DIFlagArtificial | DIFlagObjectPointer) +!48 = distinct !DISubprogram(name: "e", linkageName: "_ZN1d1eEv", scope: !16, file: !3, line: 9, type: !26, scopeLine: 9, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, declaration: !29, retainedNodes: !49) +!49 = !{!47} +!50 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !16, size: 64) +!51 = distinct !DIAssignID() +!52 = !DILocation(line: 0, scope: !48, inlinedAt: !53) +!53 = distinct !DILocation(line: 14, column: 5, scope: !11) +!54 = distinct !DIAssignID() +!55 = !DILocation(line: 15, column: 7, scope: !11) +!56 = !DILocalVariable(name: "this", arg: 1, scope: !57, type: !50, flags: DIFlagArtificial | DIFlagObjectPointer) +!57 = distinct !DISubprogram(name: "d", linkageName: "_ZN1dC2Ev", scope: !16, file: !3, line: 8, type: !26, scopeLine: 8, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, declaration: !25, retainedNodes: !58) +!58 = !{!56} +!59 = distinct !DIAssignID() +!60 = !DILocation(line: 0, scope: !57, inlinedAt: !61) +!61 = distinct !DILocation(line: 15, column: 7, scope: !11) +!62 = distinct !DIAssignID() +!63 = !DILocation(line: 8, column: 16, scope: !64, inlinedAt: !61) +!64 = distinct !DILexicalBlock(scope: !57, file: !3, line: 8, column: 7) +!69 = !DILocation(line: 8, column: 9, scope: !64, inlinedAt: !61) +!70 = !DILocation(line: 8, column: 14, scope: !64, inlinedAt: !61) +!71 = !DILocation(line: 15, column: 5, scope: !11) +!72 = distinct !DIAssignID() +!73 = !DILocation(line: 15, column: 3, scope: !11) +!74 = !DILocation(line: 16, column: 1, scope: !11) +!75 = !DISubprogram(name: "f", linkageName: "_Z1fv", scope: !3, file: !3, line: 11, type: !76, flags: DIFlagPrototyped, spFlags: DISPFlagOptimized, retainedNodes: !4) +!76 = !DISubroutineType(types: !77) +!77 = !{!16} +!78 = distinct !DIAssignID() +!79 = !DILocation(line: 0, scope: !48) +!80 = distinct !DIAssignID() +!81 = !DILocation(line: 9, column: 13, scope: !48) +!82 = distinct !DIAssignID() +!83 = !DILocation(line: 0, scope: !57) +!84 = distinct !DIAssignID() +!85 = !DILocation(line: 8, column: 16, scope: !64) +!86 = !DILocation(line: 8, column: 9, scope: !64) +!87 = !DILocation(line: 8, column: 14, scope: !64) +!88 = !DILocation(line: 8, column: 19, scope: !57) + diff --git a/llvm/test/Examples/OrcV2Examples/lljit-with-thinlto-summaries.test b/llvm/test/Examples/OrcV2Examples/lljit-with-thinlto-summaries.test --- a/llvm/test/Examples/OrcV2Examples/lljit-with-thinlto-summaries.test +++ b/llvm/test/Examples/OrcV2Examples/lljit-with-thinlto-summaries.test @@ -1,14 +1,14 @@ -# RUN: opt -module-summary %p/Inputs/main-mod.ll -o main-mod.bc -# RUN: opt -module-summary %p/Inputs/foo-mod.ll -o foo-mod.bc -# RUN: opt -module-summary %p/Inputs/bar-mod.ll -o bar-mod.bc +# RUN: opt -module-summary %p/Inputs/main-mod.ll -o %T/main-mod.bc +# RUN: opt -module-summary %p/Inputs/foo-mod.ll -o %T/foo-mod.bc +# RUN: opt -module-summary %p/Inputs/bar-mod.ll -o %T/bar-mod.bc # REQUIRES: default_triple -# RUN: llvm-lto -thinlto -o main-foo-bar main-mod.bc foo-mod.bc bar-mod.bc +# RUN: llvm-lto -thinlto -o %T/main-foo-bar %T/main-mod.bc %T/foo-mod.bc %T/bar-mod.bc -# RUN: LLJITWithThinLTOSummaries main-foo-bar.thinlto.bc 2>&1 | FileCheck %s +# RUN: LLJITWithThinLTOSummaries %T/main-foo-bar.thinlto.bc 2>&1 | FileCheck %s -# CHECK: About to load module: main-mod.bc -# CHECK: About to load module: foo-mod.bc -# CHECK: About to load module: bar-mod.bc +# CHECK: About to load module: {{.*}}/main-mod.bc +# CHECK: About to load module: {{.*}}/foo-mod.bc +# CHECK: About to load module: {{.*}}/bar-mod.bc # CHECK: 'main' finished with exit code: 0 diff --git a/llvm/test/Examples/lit.local.cfg b/llvm/test/Examples/lit.local.cfg --- a/llvm/test/Examples/lit.local.cfg +++ b/llvm/test/Examples/lit.local.cfg @@ -3,13 +3,3 @@ # Test discovery should ignore subdirectories that contain test inputs. config.excludes = ['Inputs'] - -# Tests for the C API are disabled temporarily due to failures on sanitizer bots: -# https://green.lab.llvm.org/green/job/clang-stage2-cmake-RgSan/7992/testReport/ -config.excludes += [ - 'orcv2-cbindings-add-object-file.test', - 'orcv2-cbindings-basic-usage.test', - 'orcv2-cbindings-lazy.test', - 'orcv2-cbindings-reflect-process-symbols.test', - 'orcv2-cbindings-removable-code.test', -] diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_instrument_lds.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_instrument_lds.ll --- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_instrument_lds.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_instrument_lds.ll @@ -8,16 +8,20 @@ define protected amdgpu_kernel void @lds_store(i32 %i) sanitize_address { entry: - ; CHECK-NOT: call * __asan_report - %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32] addrspace(3)* @count, i32 0, i32 %i - store i32 0, i32 addrspace(3)* %arrayidx1, align 4 + ; CHECK-LABEL: @lds_store( + ; CHECK-NOT: call + %arrayidx1 = getelementptr inbounds [100 x i32], ptr addrspace(3) @count, i32 0, i32 %i + store i32 0, ptr addrspace(3) %arrayidx1, align 4 ret void } define protected amdgpu_kernel void @lds_load(i32 %i) sanitize_address { entry: - ; CHECK-NOT: call * __asan_report - %arrayidx1 = getelementptr inbounds [100 x i32], [100 x i32] addrspace(3)* @count, i32 0, i32 %i - %0 = load i32, i32 addrspace(3)* %arrayidx1, align 4 + ; CHECK-LABEL: @lds_load( + ; CHECK-NOT: call + %arrayidx1 = getelementptr inbounds [100 x i32], ptr addrspace(3) @count, i32 0, i32 %i + %0 = load i32, ptr addrspace(3) %arrayidx1, align 4 ret void } + +; CHECK-LABEL: define internal void @asan.module_ctor() diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_instrument_scratch.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_instrument_scratch.ll --- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_instrument_scratch.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_do_not_instrument_scratch.ll @@ -8,7 +8,7 @@ entry: ; CHECK-NOT: call * __asan_report %c = alloca i32, align 4, addrspace(5) - store i32 0, i32 addrspace(5)* %c, align 4 + store i32 0, ptr addrspace(5) %c, align 4 ret void } @@ -16,6 +16,6 @@ entry: ; CHECK-NOT: call * __asan_report %c = alloca i32, align 4, addrspace(5) - %0 = load i32, i32 addrspace(5)* %c, align 4 + %0 = load i32, ptr addrspace(5) %c, align 4 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll --- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_constant_address_space.ll @@ -9,11 +9,11 @@ ; CHECK-LABEL: @constant_load ; CHECK-NOT: load ; -; CHECK: %[[LOAD_ADDR:[^ ]*]] = ptrtoint i32 addrspace(4)* %a to i64 +; CHECK: %[[LOAD_ADDR:[^ ]*]] = ptrtoint ptr addrspace(4) %a to i64 ; CHECK: lshr i64 %[[LOAD_ADDR]], 3 ; CHECK: add i64 %{{.*}}, 2147450880 ; CHECK: %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr -; CHECK: %[[LOAD_SHADOW:[^ ]*]] = load i8, i8* %[[LOAD_SHADOW_PTR]] +; CHECK: %[[LOAD_SHADOW:[^ ]*]] = load i8, ptr %[[LOAD_SHADOW_PTR]] ; CHECK: icmp ne i8 ; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}} ; @@ -27,10 +27,10 @@ ; CHECK: unreachable ; ; The actual load. -; CHECK: load i32, i32 addrspace(4)* %a +; CHECK: load i32, ptr addrspace(4) %a ; CHECK: ret void - %a = getelementptr inbounds [2 x i32], [2 x i32] addrspace(4)* @x, i64 0, i64 %i - %q = load i32, i32 addrspace(4)* %a, align 4 + %a = getelementptr inbounds [2 x i32], ptr addrspace(4) @x, i64 0, i64 %i + %q = load i32, ptr addrspace(4) %a, align 4 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll --- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_generic_address_space.ll @@ -2,22 +2,22 @@ target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7" target triple = "amdgcn-amd-amdhsa" -define protected amdgpu_kernel void @generic_store(i32 addrspace(1)* %p, i32 %i) sanitize_address { +define protected amdgpu_kernel void @generic_store(ptr addrspace(1) %p, i32 %i) sanitize_address { entry: ; CHECK-LABEL: @generic_store ; CHECK-NOT: store -; CHECK: %[[GENERIC_ADDR:[^ ]*]] = bitcast i32* %q to i8* -; CHECK: call i1 @llvm.amdgcn.is.shared(i8* %[[GENERIC_ADDR]]) -; CHECK: call i1 @llvm.amdgcn.is.private(i8* %[[GENERIC_ADDR]]) +; CHECK: %[[GENERIC_ADDR:[^ ]*]] = addrspacecast ptr addrspace(1) %p to ptr +; CHECK: call i1 @llvm.amdgcn.is.shared(ptr %[[GENERIC_ADDR]]) +; CHECK: call i1 @llvm.amdgcn.is.private(ptr %[[GENERIC_ADDR]]) ; CHECK: or -; CHECK: icmp ne i1 +; CHECK: icmp ne i1 ; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}} ; -; CHECK: %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %q to i64 +; CHECK: %[[STORE_ADDR:[^ ]*]] = ptrtoint ptr %q to i64 ; CHECK: lshr i64 %[[STORE_ADDR]], 3 ; CHECK: add i64 %{{.*}}, 2147450880 ; CHECK: %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr -; CHECK: %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]] +; CHECK: %[[STORE_SHADOW:[^ ]*]] = load i8, ptr %[[STORE_SHADOW_PTR]] ; CHECK: icmp ne i8 ; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}} ; @@ -31,30 +31,29 @@ ; CHECK: unreachable ; ; The actual store. -; CHECK: store i32 0, i32* %q +; CHECK: store i32 0, ptr %q ; CHECK: ret void - %q = addrspacecast i32 addrspace(1)* %p to i32* - store i32 0, i32* %q, align 4 + %q = addrspacecast ptr addrspace(1) %p to ptr + store i32 0, ptr %q, align 4 ret void } -define protected amdgpu_kernel void @generic_load(i32 addrspace(1)* %p, i32 %i) sanitize_address { +define protected amdgpu_kernel void @generic_load(ptr addrspace(1) %p, i32 %i) sanitize_address { entry: ; CHECK-LABEL: @generic_load ; CHECK-NOT: load -; CHECK: %[[GENERIC_ADDR:[^ ]*]] = bitcast i32* %q to i8* -; CHECK: call i1 @llvm.amdgcn.is.shared(i8* %[[GENERIC_ADDR]]) -; CHECK: call i1 @llvm.amdgcn.is.private(i8* %[[GENERIC_ADDR]]) +; CHECK: call i1 @llvm.amdgcn.is.shared(ptr %[[GENERIC_ADDR]]) +; CHECK: call i1 @llvm.amdgcn.is.private(ptr %[[GENERIC_ADDR]]) ; CHECK: or -; CHECK: icmp ne i1 +; CHECK: icmp ne i1 ; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}} ; -; CHECK: %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %q to i64 +; CHECK: %[[STORE_ADDR:[^ ]*]] = ptrtoint ptr %q to i64 ; CHECK: lshr i64 %[[STORE_ADDR]], 3 ; CHECK: add i64 %{{.*}}, 2147450880 ; CHECK: %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr -; CHECK: %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]] +; CHECK: %[[STORE_SHADOW:[^ ]*]] = load i8, ptr %[[STORE_SHADOW_PTR]] ; CHECK: icmp ne i8 ; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}} ; @@ -68,10 +67,10 @@ ; CHECK: unreachable ; ; The actual store. -; CHECK: load i32, i32* %q +; CHECK: load i32, ptr %q ; CHECK: ret void - %q = addrspacecast i32 addrspace(1)* %p to i32* - %r = load i32, i32* %q, align 4 + %q = addrspacecast ptr addrspace(1) %p to ptr + %r = load i32, ptr %q, align 4 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll --- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/asan_instrument_global_address_space.ll @@ -2,16 +2,16 @@ target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7" target triple = "amdgcn-amd-amdhsa" -define protected amdgpu_kernel void @global_store(i32 addrspace(1)* %p, i32 %i) sanitize_address { +define protected amdgpu_kernel void @global_store(ptr addrspace(1) %p, i32 %i) sanitize_address { entry: ; CHECK-LABEL: @global_store ; CHECK-NOT: store ; -; CHECK: %[[STORE_ADDR:[^ ]*]] = ptrtoint i32 addrspace(1)* %p to i64 +; CHECK: %[[STORE_ADDR:[^ ]*]] = ptrtoint ptr addrspace(1) %p to i64 ; CHECK: lshr i64 %[[STORE_ADDR]], 3 ; CHECK: add i64 %{{.*}}, 2147450880 ; CHECK: %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr -; CHECK: %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]] +; CHECK: %[[STORE_SHADOW:[^ ]*]] = load i8, ptr %[[STORE_SHADOW_PTR]] ; CHECK: icmp ne i8 ; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}} ; @@ -25,23 +25,23 @@ ; CHECK: unreachable ; ; The actual store. -; CHECK: store i32 0, i32 addrspace(1)* %p +; CHECK: store i32 0, ptr addrspace(1) %p ; CHECK: ret void - store i32 0, i32 addrspace(1)* %p, align 4 + store i32 0, ptr addrspace(1) %p, align 4 ret void } -define protected amdgpu_kernel void @global_load(i32 addrspace(1)* %p, i32 %i) sanitize_address { +define protected amdgpu_kernel void @global_load(ptr addrspace(1) %p, i32 %i) sanitize_address { entry: ; CHECK-LABEL: @global_load ; CHECK-NOT: load ; -; CHECK: %[[LOAD_ADDR:[^ ]*]] = ptrtoint i32 addrspace(1)* %p to i64 +; CHECK: %[[LOAD_ADDR:[^ ]*]] = ptrtoint ptr addrspace(1) %p to i64 ; CHECK: lshr i64 %[[LOAD_ADDR]], 3 ; CHECK: add i64 %{{.*}}, 2147450880 ; CHECK: %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr -; CHECK: %[[LOAD_SHADOW:[^ ]*]] = load i8, i8* %[[LOAD_SHADOW_PTR]] +; CHECK: %[[LOAD_SHADOW:[^ ]*]] = load i8, ptr %[[LOAD_SHADOW_PTR]] ; CHECK: icmp ne i8 ; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}} ; @@ -55,9 +55,9 @@ ; CHECK: unreachable ; ; The actual load. -; CHECK: load i32, i32 addrspace(1)* %p +; CHECK: load i32, ptr addrspace(1) %p ; CHECK: ret void - %q = load i32, i32 addrspace(1)* %p, align 4 + %q = load i32, ptr addrspace(1) %p, align 4 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/global_metadata_addrspacecasts.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/global_metadata_addrspacecasts.ll --- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/global_metadata_addrspacecasts.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/global_metadata_addrspacecasts.ll @@ -7,5 +7,5 @@ ;CHECK: llvm.asan.globals !llvm.asan.globals = !{!0, !1} -!0 = !{[1 x i32] addrspace(1)* @g, null, !"name", i1 false, i1 false} -!1 = !{i8* addrspacecast (i8 addrspace(1)* bitcast ( [1 x i32] addrspace(1)* @g to i8 addrspace(1)*) to i8*), null, !"name", i1 false, i1 false} +!0 = !{ptr addrspace(1) @g, null, !"name", i1 false, i1 false} +!1 = !{ptr addrspacecast (ptr addrspace(1) @g to ptr), null, !"name", i1 false, i1 false} diff --git a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/instrument-stack.ll b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/instrument-stack.ll --- a/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/instrument-stack.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/AMDGPU/instrument-stack.ll @@ -5,13 +5,13 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -;@sink = global i32* null, align 4 +;@sink = global ptr null, align 4 ; Ignore direct inbounds stack access. define void @foo() uwtable sanitize_address { entry: %a = alloca i32, align 4 - store i32 42, i32* %a, align 4 + store i32 42, ptr %a, align 4 ret void ; CHECK-LABEL: define void @foo ; CHECK-NOT: __asan_report @@ -22,8 +22,8 @@ define void @baz(i64 %i) sanitize_address { entry: %a = alloca [10 x i32], align 4 - %e = getelementptr inbounds [10 x i32], [10 x i32]* %a, i32 0, i64 %i - store i32 42, i32* %e, align 4 + %e = getelementptr inbounds [10 x i32], ptr %a, i32 0, i64 %i + store i32 42, ptr %e, align 4 ret void ; CHECK-LABEL: define void @baz ; CHECK: __asan_report @@ -33,8 +33,8 @@ define void @bar() sanitize_address { entry: %a = alloca [10 x i32], align 4 - %e = getelementptr inbounds [10 x i32], [10 x i32]* %a, i32 0, i64 12 - store i32 42, i32* %e, align 4 + %e = getelementptr inbounds [10 x i32], ptr %a, i32 0, i64 12 + store i32 42, ptr %e, align 4 ret void ; CHECK-LABEL: define void @bar ; CHECK: __asan_report diff --git a/llvm/test/Instrumentation/AddressSanitizer/X86/asm_cpuid.ll b/llvm/test/Instrumentation/AddressSanitizer/X86/asm_cpuid.ll --- a/llvm/test/Instrumentation/AddressSanitizer/X86/asm_cpuid.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/X86/asm_cpuid.ll @@ -5,30 +5,29 @@ target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-S32" target triple = "i386-pc-windows-msvc" -define void @MyCPUID(i32 %fxn, i32* %out) sanitize_address { +define void @MyCPUID(i32 %fxn, ptr %out) sanitize_address { %fxn.ptr = alloca i32 %a.ptr = alloca i32 %b.ptr = alloca i32 %c.ptr = alloca i32 %d.ptr = alloca i32 - store i32 %fxn, i32* %fxn.ptr - call void asm sideeffect inteldialect "xchg ebx, esi\0A\09mov eax, dword ptr $4\0A\09cpuid\0A\09mov dword ptr $0, eax\0A\09mov dword ptr $1, ebx\0A\09mov dword ptr $2, ecx\0A\09mov dword ptr $3, edx\0A\09xchg ebx, esi", "=*m,=*m,=*m,=*m,*m,~{eax},~{ebx},~{ecx},~{edx},~{esi},~{dirflag},~{fpsr},~{flags}"(i32* elementtype(i32) %a.ptr, i32* elementtype(i32) %b.ptr, i32* elementtype(i32) %c.ptr, i32* elementtype(i32) %d.ptr, i32* elementtype(i32) %fxn.ptr) + store i32 %fxn, ptr %fxn.ptr + call void asm sideeffect inteldialect "xchg ebx, esi\0A\09mov eax, dword ptr $4\0A\09cpuid\0A\09mov dword ptr $0, eax\0A\09mov dword ptr $1, ebx\0A\09mov dword ptr $2, ecx\0A\09mov dword ptr $3, edx\0A\09xchg ebx, esi", "=*m,=*m,=*m,=*m,*m,~{eax},~{ebx},~{ecx},~{edx},~{esi},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) %a.ptr, ptr elementtype(i32) %b.ptr, ptr elementtype(i32) %c.ptr, ptr elementtype(i32) %d.ptr, ptr elementtype(i32) %fxn.ptr) - %a = load i32, i32* %a.ptr - %a.out = getelementptr inbounds i32, i32* %out, i32 0 - store i32 %a, i32* %a.out + %a = load i32, ptr %a.ptr + store i32 %a, ptr %out - %b = load i32, i32* %b.ptr - %b.out = getelementptr inbounds i32, i32* %out, i32 1 - store i32 %b, i32* %b.out + %b = load i32, ptr %b.ptr + %b.out = getelementptr inbounds i32, ptr %out, i32 1 + store i32 %b, ptr %b.out - %c = load i32, i32* %c.ptr - %c.out = getelementptr inbounds i32, i32* %out, i32 2 - store i32 %c, i32* %c.out + %c = load i32, ptr %c.ptr + %c.out = getelementptr inbounds i32, ptr %out, i32 2 + store i32 %c, ptr %c.out - %d = load i32, i32* %d.ptr - %d.out = getelementptr inbounds i32, i32* %out, i32 3 - store i32 %d, i32* %d.out + %d = load i32, ptr %d.ptr + %d.out = getelementptr inbounds i32, ptr %out, i32 3 + store i32 %d, ptr %d.out ret void } @@ -37,7 +36,7 @@ ; out of registers on 32-bit platforms. Therefore, we don't do stack malloc on ; such functions. -; CHECK-LABEL: define void @MyCPUID(i32 %fxn, i32* %out) +; CHECK-LABEL: define void @MyCPUID(i32 %fxn, ptr %out) ; CHECK: %MyAlloca = alloca [96 x i8], align 32 ; CHECK-NOT: call {{.*}} @__asan_stack_malloc diff --git a/llvm/test/Instrumentation/AddressSanitizer/X86/asm_more_registers_than_available.ll b/llvm/test/Instrumentation/AddressSanitizer/X86/asm_more_registers_than_available.ll --- a/llvm/test/Instrumentation/AddressSanitizer/X86/asm_more_registers_than_available.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/X86/asm_more_registers_than_available.ll @@ -4,18 +4,18 @@ ; Don't do stack malloc on functions containing inline assembly on 64-bit ; platforms. It makes LLVM run out of registers. -; CHECK-LABEL: define void @TestAbsenceOfStackMalloc(i8* %S, i32 %pS, i8* %D, i32 %pD, i32 %h) +; CHECK-LABEL: define void @TestAbsenceOfStackMalloc(ptr %S, i32 %pS, ptr %D, i32 %pD, i32 %h) ; CHECK: %MyAlloca ; CHECK-NOT: call {{.*}} @__asan_stack_malloc target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.10.0" -define void @TestAbsenceOfStackMalloc(i8* %S, i32 %pS, i8* %D, i32 %pD, i32 %h) #0 { +define void @TestAbsenceOfStackMalloc(ptr %S, i32 %pS, ptr %D, i32 %pD, i32 %h) #0 { entry: - %S.addr = alloca i8*, align 8 + %S.addr = alloca ptr, align 8 %pS.addr = alloca i32, align 4 - %D.addr = alloca i8*, align 8 + %D.addr = alloca ptr, align 8 %pD.addr = alloca i32, align 4 %h.addr = alloca i32, align 4 %sr = alloca i32, align 4 @@ -23,32 +23,32 @@ %pDiffS = alloca i32, align 4 %flagSA = alloca i8, align 1 %flagDA = alloca i8, align 1 - store i8* %S, i8** %S.addr, align 8 - store i32 %pS, i32* %pS.addr, align 4 - store i8* %D, i8** %D.addr, align 8 - store i32 %pD, i32* %pD.addr, align 4 - store i32 %h, i32* %h.addr, align 4 - store i32 4, i32* %sr, align 4 - %0 = load i32, i32* %pD.addr, align 4 + store ptr %S, ptr %S.addr, align 8 + store i32 %pS, ptr %pS.addr, align 4 + store ptr %D, ptr %D.addr, align 8 + store i32 %pD, ptr %pD.addr, align 4 + store i32 %h, ptr %h.addr, align 4 + store i32 4, ptr %sr, align 4 + %0 = load i32, ptr %pD.addr, align 4 %sub = sub i32 %0, 5 - store i32 %sub, i32* %pDiffD, align 4 - %1 = load i32, i32* %pS.addr, align 4 + store i32 %sub, ptr %pDiffD, align 4 + %1 = load i32, ptr %pS.addr, align 4 %shl = shl i32 %1, 1 %sub1 = sub i32 %shl, 5 - store i32 %sub1, i32* %pDiffS, align 4 - %2 = load i32, i32* %pS.addr, align 4 + store i32 %sub1, ptr %pDiffS, align 4 + %2 = load i32, ptr %pS.addr, align 4 %and = and i32 %2, 15 %cmp = icmp eq i32 %and, 0 %conv = zext i1 %cmp to i32 %conv2 = trunc i32 %conv to i8 - store i8 %conv2, i8* %flagSA, align 1 - %3 = load i32, i32* %pD.addr, align 4 + store i8 %conv2, ptr %flagSA, align 1 + %3 = load i32, ptr %pD.addr, align 4 %and3 = and i32 %3, 15 %cmp4 = icmp eq i32 %and3, 0 %conv5 = zext i1 %cmp4 to i32 %conv6 = trunc i32 %conv5 to i8 - store i8 %conv6, i8* %flagDA, align 1 - call void asm sideeffect "mov\09\09\09$0,\09\09\09\09\09\09\09\09\09\09%rsi\0Amov\09\09\09$2,\09\09\09\09\09\09\09\09\09\09%rcx\0Amov\09\09\09$1,\09\09\09\09\09\09\09\09\09\09%rdi\0Amov\09\09\09$8,\09\09\09\09\09\09\09\09\09\09%rax\0A", "*m,*m,*m,*m,*m,*m,*m,*m,*m,~{rsi},~{rdi},~{rax},~{rcx},~{rdx},~{memory},~{dirflag},~{fpsr},~{flags}"(i8** elementtype(i8*) %S.addr, i8** elementtype(i8*) %D.addr, i32* elementtype(i32) %pS.addr, i32* elementtype(i32) %pDiffS, i32* elementtype(i32) %pDiffD, i32* elementtype(i32) %sr, i8* elementtype(i8) %flagSA, i8* elementtype(i8) %flagDA, i32* elementtype(i32) %h.addr) #1 + store i8 %conv6, ptr %flagDA, align 1 + call void asm sideeffect "mov\09\09\09$0,\09\09\09\09\09\09\09\09\09\09%rsi\0Amov\09\09\09$2,\09\09\09\09\09\09\09\09\09\09%rcx\0Amov\09\09\09$1,\09\09\09\09\09\09\09\09\09\09%rdi\0Amov\09\09\09$8,\09\09\09\09\09\09\09\09\09\09%rax\0A", "*m,*m,*m,*m,*m,*m,*m,*m,*m,~{rsi},~{rdi},~{rax},~{rcx},~{rdx},~{memory},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(ptr) %S.addr, ptr elementtype(ptr) %D.addr, ptr elementtype(i32) %pS.addr, ptr elementtype(i32) %pDiffS, ptr elementtype(i32) %pDiffD, ptr elementtype(i32) %sr, ptr elementtype(i8) %flagSA, ptr elementtype(i8) %flagDA, ptr elementtype(i32) %h.addr) #1 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/X86/bug_11395.ll b/llvm/test/Instrumentation/AddressSanitizer/X86/bug_11395.ll --- a/llvm/test/Instrumentation/AddressSanitizer/X86/bug_11395.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/X86/bug_11395.ll @@ -5,22 +5,22 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S128" target triple = "i386-unknown-linux-gnu" -%struct.DSPContext = type { void (i16*, i8*, i32)*, void (i16*, i8*, i8*, i32)*, void (i16*, i8*, i32)*, void (i16*, i8*, i32)*, void (i16*, i8*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, i32 (i16*)*, void (i8*, i8*, i32, i32, i32, i32, i32)*, void (i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)*, void (i16*)*, void (i16*)*, i32 (i8*, i32)*, i32 (i8*, i32)*, [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], [6 x i32 (i8*, i8*, i8*, i32, i32)*], i32 (i8*, i16*, i32)*, [4 x [4 x void (i8*, i8*, i32, i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [4 x [4 x void (i8*, i8*, i32, i32)*]], [2 x void (i8*, i8*, i8*, i32, i32)*], [11 x void (i8*, i8*, i32, i32, i32)*], [11 x void (i8*, i8*, i32, i32, i32)*], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], [8 x void (i8*, i8*, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [10 x void (i8*, i32, i32, i32, i32)*], [10 x void (i8*, i8*, i32, i32, i32, i32, i32)*], [2 x [16 x void (i8*, i8*, i32)*]], [2 x [16 x void (i8*, i8*, i32)*]], void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32, i32, i32, i32, i32)*, void (i8*, i16*, i32)*, [2 x [4 x i32 (i8*, i8*, i8*, i32, i32)*]], void (i8*, i8*, i32)*, void (i8*, i8*, i8*, i32)*, void (i8*, i8*, i8*, i32)*, void (i8*, i8*, i8*, i32, i32*, i32*)*, void (i8*, i8*, i8*, i32, i32*, i32*)*, i32 (i8*, i8*, i32, i32)*, void (i8*, i8*, i32, i32*, i32*, i32*)*, void (i8*, i8*, i8*, i32, i32)*, void (i32*, i32*, i32)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32)*, void (i8*, i32, i32, i32)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32, i8*)*, void (i8*, i32, i32, i32)*, void (i8*, i32, i32, i32)*, void ([4 x [4 x i16]]*, i8*, [40 x i8]*, [40 x [2 x i16]]*, i32, i32, i32, i32, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32*)*, void (i8*, i32, i32*)*, void (i8*, i8*, i32, i16*, i16*)*, void (float*, float*, i32)*, void ([256 x float]*, [2 x float]*, i32, i32, i32)*, void (i32*, i32, i32, double*)*, void (float*, float*, i32)*, void (float*, float*, float*, i32)*, void (float*, float*, float*, float*, i32)*, void (float*, float*, float*, float*, float, i32)*, void (float*, i32*, float, i32)*, void (float*, float*, float, float, i32)*, void (float*, float*, float, i32)*, [2 x void (float*, float*, float**, float, i32)*], [2 x void (float*, float**, float, i32)*], float (float*, float*, i32)*, void (float*, float*, i32)*, void (i16*, float*, i32)*, void (i16*, float**, i32, i32)*, void (i16*)*, void (i16*)*, void (i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, [64 x i8], i32, i32 (i16*, i16*, i16*, i32)*, void (i16*, i16*, i32)*, void (i8*, i32, i32, i32, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void (i8*, i16*, i32)*, void ([4 x i16]*)*, void (i8*, i32*, i16*, i32, i8*)*, void (i8*, i32*, i16*, i32, i8*)*, void (i8**, i32*, i16*, i32, i8*)*, void (i8*, i32*, i16*, i32, i8*)*, void (i16*, i16*, i16*, i16*, i16*, i16*, i32)*, void (i16*, i32)*, void (i8*, i32, i8**, i32, i32, i32, i32, i32, %struct.slice_buffer_s*, i32, i8*)*, void (i8*, i32, i32)*, [4 x void (i8*, i32, i8*, i32, i32, i32)*], void (i32*, i32*, i32, i32, i32, i32, i32, i32*)*, void (i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32, i16*)*, void (i8*, i32)*, void (i8*, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, void (i8*, i32, i32)*, [16 x void (i8*, i8*, i32, i32)*], [16 x void (i8*, i8*, i32, i32)*], [12 x void (i8*, i8*, i32)*], void (i8*, i8*, i32, i32*, i32*, i32)*, void (i16*, i16*, i32)*, void (i16*, i16*, i32)*, i32 (i16*, i16*, i32, i32)*, [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [4 x [16 x void (i8*, i8*, i32)*]], [3 x void (i8*, i8*, i32, i32, i32, i32)*], [3 x void (i8*, i8*, i32, i32, i32, i32)*] } +%struct.DSPContext = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], [6 x ptr], ptr, [4 x [4 x ptr]], [4 x [4 x ptr]], [4 x [4 x ptr]], [4 x [4 x ptr]], [2 x ptr], [11 x ptr], [11 x ptr], [2 x [16 x ptr]], [2 x [16 x ptr]], [2 x [16 x ptr]], [2 x [16 x ptr]], [8 x ptr], [3 x ptr], [3 x ptr], [3 x ptr], [3 x ptr], [4 x [16 x ptr]], [4 x [16 x ptr]], [4 x [16 x ptr]], [4 x [16 x ptr]], [10 x ptr], [10 x ptr], [2 x [16 x ptr]], [2 x [16 x ptr]], ptr, ptr, ptr, ptr, ptr, [2 x [4 x ptr]], ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, [2 x ptr], [2 x ptr], ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, [64 x i8], i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, [4 x ptr], ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, [16 x ptr], [16 x ptr], [12 x ptr], ptr, ptr, ptr, ptr, [4 x [16 x ptr]], [4 x [16 x ptr]], [4 x [16 x ptr]], [4 x [16 x ptr]], [3 x ptr], [3 x ptr] } %struct.slice_buffer_s = type opaque -%struct.AVCodecContext = type { %struct.AVClass*, i32, i32, i32, i32, i32, i8*, i32, %struct.AVRational, i32, i32, i32, i32, i32, void (%struct.AVCodecContext*, %struct.AVFrame*, i32*, i32, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, %struct.AVCodec*, i8*, i32, void (%struct.AVCodecContext*, i8*, i32, i32)*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, void (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i8*, i8*, float, float, i32, %struct.RcOverride*, i32, i8*, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, i32*, i32, i32, i32, i32, %struct.AVRational, %struct.AVFrame*, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32*)*, i32, i32, i32, i32, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i16*, i16*, i32, i32, i32, i32, %struct.AVPaletteControl*, i32, i32 (%struct.AVCodecContext*, %struct.AVFrame*)*, i32, i32, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*, i8*)*, i8*, i32*, i32, i32)*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i32, float, i64, i32, i64, i64, float, float, %struct.AVHWAccel*, i32, i8*, i32, i32, i32, i32, i32, i32 (%struct.AVCodecContext*, i32 (%struct.AVCodecContext*, i8*, i32, i32)*, i8*, i32*, i32)*, i32, i32, i32, i32, i32, i32, i8*, float, float, float, float, i32, i32, i32, float, float, float, i32, i32, i32, i32, [4 x i32], i8*, i32, i32, i32, i32 } -%struct.AVClass = type { i8*, i8* (i8*)*, %struct.AVOption* } +%struct.AVCodecContext = type { ptr, i32, i32, i32, i32, i32, ptr, i32, %struct.AVRational, i32, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, i32, float, float, i32, i32, i32, i32, float, i32, i32, i32, ptr, ptr, i32, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, [32 x i8], i32, i32, i32, i32, i32, i32, i32, float, i32, ptr, ptr, i32, i32, i32, i32, ptr, ptr, float, float, i32, ptr, i32, ptr, i32, i32, i32, float, float, float, float, i32, float, float, float, float, float, i32, i32, ptr, i32, i32, i32, i32, %struct.AVRational, ptr, i32, i32, [4 x i64], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, ptr, ptr, i32, i32, i32, i32, ptr, i32, ptr, i32, i32, i32, i32, i32, i32, i32, ptr, ptr, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i64, i32, float, i64, i32, i64, i64, float, float, ptr, i32, ptr, i32, i32, i32, i32, i32, ptr, i32, i32, i32, i32, i32, i32, ptr, float, float, float, float, i32, i32, i32, float, float, float, i32, i32, i32, i32, [4 x i32], ptr, i32, i32, i32, i32 } +%struct.AVClass = type { ptr, ptr, ptr } %struct.AVOption = type opaque %struct.AVRational = type { i32, i32 } -%struct.AVFrame = type { [4 x i8*], [4 x i32], [4 x i8*], i32, i32, i64, i32, i32, i32, i32, i32, i8*, i32, i8*, [2 x [2 x i16]*], i32*, i8, i8*, [4 x i64], i32, i32, i32, i32, i32, %struct.AVPanScan*, i32, i32, i16*, [2 x i8*], i64, i8* } +%struct.AVFrame = type { [4 x ptr], [4 x i32], [4 x ptr], i32, i32, i64, i32, i32, i32, i32, i32, ptr, i32, ptr, [2 x ptr], ptr, i8, ptr, [4 x i64], i32, i32, i32, i32, i32, ptr, i32, i32, ptr, [2 x ptr], i64, ptr } %struct.AVPanScan = type { i32, i32, i32, [3 x [2 x i16]] } -%struct.AVCodec = type { i8*, i32, i32, i32, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32, i8*)*, i32 (%struct.AVCodecContext*)*, i32 (%struct.AVCodecContext*, i8*, i32*, %struct.AVPacket*)*, i32, %struct.AVCodec*, void (%struct.AVCodecContext*)*, %struct.AVRational*, i32*, i8*, i32*, i32*, i64* } -%struct.AVPacket = type { i64, i64, i8*, i32, i32, i32, i32, void (%struct.AVPacket*)*, i8*, i64, i64 } +%struct.AVCodec = type { ptr, i32, i32, i32, ptr, ptr, ptr, ptr, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr } +%struct.AVPacket = type { i64, i64, ptr, i32, i32, i32, i32, ptr, ptr, i64, i64 } %struct.RcOverride = type { i32, i32, i32, float } %struct.AVPaletteControl = type { i32, [256 x i32] } -%struct.AVHWAccel = type { i8*, i32, i32, i32, i32, %struct.AVHWAccel*, i32 (%struct.AVCodecContext*, i8*, i32)*, i32 (%struct.AVCodecContext*, i8*, i32)*, i32 (%struct.AVCodecContext*)*, i32 } +%struct.AVHWAccel = type { ptr, i32, i32, i32, i32, ptr, ptr, ptr, ptr, i32 } -@firtable = internal unnamed_addr constant [9 x i8*] [i8* @ff_mlp_firorder_0, i8* @ff_mlp_firorder_1, i8* @ff_mlp_firorder_2, i8* @ff_mlp_firorder_3, i8* @ff_mlp_firorder_4, i8* @ff_mlp_firorder_5, i8* @ff_mlp_firorder_6, i8* @ff_mlp_firorder_7, i8* @ff_mlp_firorder_8], align 4 -@iirtable = internal unnamed_addr constant [5 x i8*] [i8* @ff_mlp_iirorder_0, i8* @ff_mlp_iirorder_1, i8* @ff_mlp_iirorder_2, i8* @ff_mlp_iirorder_3, i8* @ff_mlp_iirorder_4], align 4 +@firtable = internal unnamed_addr constant [9 x ptr] [ptr @ff_mlp_firorder_0, ptr @ff_mlp_firorder_1, ptr @ff_mlp_firorder_2, ptr @ff_mlp_firorder_3, ptr @ff_mlp_firorder_4, ptr @ff_mlp_firorder_5, ptr @ff_mlp_firorder_6, ptr @ff_mlp_firorder_7, ptr @ff_mlp_firorder_8], align 4 +@iirtable = internal unnamed_addr constant [5 x ptr] [ptr @ff_mlp_iirorder_0, ptr @ff_mlp_iirorder_1, ptr @ff_mlp_iirorder_2, ptr @ff_mlp_iirorder_3, ptr @ff_mlp_iirorder_4], align 4 @ff_mlp_iirorder_0 = external global i8 @ff_mlp_iirorder_1 = external global i8 @ff_mlp_iirorder_2 = external global i8 @@ -36,31 +36,31 @@ @ff_mlp_firorder_7 = external global i8 @ff_mlp_firorder_8 = external global i8 -define void @ff_mlp_init_x86(%struct.DSPContext* nocapture %c, %struct.AVCodecContext* nocapture %avctx) nounwind sanitize_address { +define void @ff_mlp_init_x86(ptr nocapture %c, ptr nocapture %avctx) nounwind sanitize_address { entry: - %mlp_filter_channel = getelementptr inbounds %struct.DSPContext, %struct.DSPContext* %c, i32 0, i32 131 - store void (i32*, i32*, i32, i32, i32, i32, i32, i32*)* @mlp_filter_channel_x86, void (i32*, i32*, i32, i32, i32, i32, i32, i32*)** %mlp_filter_channel, align 4, !tbaa !0 + %mlp_filter_channel = getelementptr inbounds %struct.DSPContext, ptr %c, i32 0, i32 131 + store ptr @mlp_filter_channel_x86, ptr %mlp_filter_channel, align 4, !tbaa !0 ret void } -define internal void @mlp_filter_channel_x86(i32* %state, i32* %coeff, i32 %firorder, i32 %iirorder, i32 %filter_shift, i32 %mask, i32 %blocksize, i32* %sample_buffer) nounwind sanitize_address { +define internal void @mlp_filter_channel_x86(ptr %state, ptr %coeff, i32 %firorder, i32 %iirorder, i32 %filter_shift, i32 %mask, i32 %blocksize, ptr %sample_buffer) nounwind sanitize_address { entry: %filter_shift.addr = alloca i32, align 4 %mask.addr = alloca i32, align 4 %blocksize.addr = alloca i32, align 4 - %firjump = alloca i8*, align 4 - %iirjump = alloca i8*, align 4 - store i32 %filter_shift, i32* %filter_shift.addr, align 4, !tbaa !3 - store i32 %mask, i32* %mask.addr, align 4, !tbaa !3 - %arrayidx = getelementptr inbounds [9 x i8*], [9 x i8*]* @firtable, i32 0, i32 %firorder - %0 = load i8*, i8** %arrayidx, align 4, !tbaa !0 - store i8* %0, i8** %firjump, align 4, !tbaa !0 - %arrayidx1 = getelementptr inbounds [5 x i8*], [5 x i8*]* @iirtable, i32 0, i32 %iirorder - %1 = load i8*, i8** %arrayidx1, align 4, !tbaa !0 - store i8* %1, i8** %iirjump, align 4, !tbaa !0 + %firjump = alloca ptr, align 4 + %iirjump = alloca ptr, align 4 + store i32 %filter_shift, ptr %filter_shift.addr, align 4, !tbaa !3 + store i32 %mask, ptr %mask.addr, align 4, !tbaa !3 + %arrayidx = getelementptr inbounds [9 x ptr], ptr @firtable, i32 0, i32 %firorder + %0 = load ptr, ptr %arrayidx, align 4, !tbaa !0 + store ptr %0, ptr %firjump, align 4, !tbaa !0 + %arrayidx1 = getelementptr inbounds [5 x ptr], ptr @iirtable, i32 0, i32 %iirorder + %1 = load ptr, ptr %arrayidx1, align 4, !tbaa !0 + store ptr %1, ptr %iirjump, align 4, !tbaa !0 %sub = sub nsw i32 0, %blocksize - store i32 %sub, i32* %blocksize.addr, align 4, !tbaa !3 - %2 = call { i32*, i32*, i32* } asm sideeffect "1: \0A\09xor %esi, %esi\0A\09xor %ecx, %ecx\0A\09jmp *$5 \0A\09ff_mlp_firorder_8: \0A\09mov 0x1c+0($0), %eax\0A\09imull 0x1c+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_7: \0A\09mov 0x18+0($0), %eax\0A\09imull 0x18+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_6: \0A\09mov 0x14+0($0), %eax\0A\09imull 0x14+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_5: \0A\09mov 0x10+0($0), %eax\0A\09imull 0x10+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_4: \0A\09mov 0x0c+0($0), %eax\0A\09imull 0x0c+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_3: \0A\09mov 0x08+0($0), %eax\0A\09imull 0x08+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_2: \0A\09mov 0x04+0($0), %eax\0A\09imull 0x04+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_1: \0A\09mov 0x00+0($0), %eax\0A\09imull 0x00+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_0:\0A\09jmp *$6 \0A\09ff_mlp_iirorder_4: \0A\09mov 0x0c+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x0c+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_iirorder_3: \0A\09mov 0x08+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x08+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_iirorder_2: \0A\09mov 0x04+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x04+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_iirorder_1: \0A\09mov 0x00+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x00+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_iirorder_0:\0A\09mov %ecx, %edx\0A\09mov %esi, %eax\0A\09movzbl $7 , %ecx\0A\09shrd %cl, %edx, %eax\0A\09mov %eax ,%edx \0A\09add ($2) ,%eax \0A\09and $4 ,%eax \0A\09sub $$4 , $0 \0A\09mov %eax, ($0) \0A\09mov %eax, ($2) \0A\09add $$4* 8 , $2 \0A\09sub %edx ,%eax \0A\09mov %eax,4*(8 + (40 * 4))($0) \0A\09incl $3 \0A\09js 1b \0A\09", "=r,=r,=r,=*m,*m,*m,*m,*m,0,1,2,*m,~{eax},~{edx},~{esi},~{ecx},~{dirflag},~{fpsr},~{flags}"(i32* elementtype(i32) %blocksize.addr, i32* elementtype(i32) %mask.addr, i8** elementtype(i8*) %firjump, i8** elementtype(i8*) %iirjump, i32* elementtype(i32) %filter_shift.addr, i32* %state, i32* %coeff, i32* %sample_buffer, i32* elementtype(i32) %blocksize.addr) nounwind, !srcloc !4 + store i32 %sub, ptr %blocksize.addr, align 4, !tbaa !3 + %2 = call { ptr, ptr, ptr } asm sideeffect "1: \0A\09xor %esi, %esi\0A\09xor %ecx, %ecx\0A\09jmp *$5 \0A\09ff_mlp_firorder_8: \0A\09mov 0x1c+0($0), %eax\0A\09imull 0x1c+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_7: \0A\09mov 0x18+0($0), %eax\0A\09imull 0x18+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_6: \0A\09mov 0x14+0($0), %eax\0A\09imull 0x14+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_5: \0A\09mov 0x10+0($0), %eax\0A\09imull 0x10+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_4: \0A\09mov 0x0c+0($0), %eax\0A\09imull 0x0c+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_3: \0A\09mov 0x08+0($0), %eax\0A\09imull 0x08+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_2: \0A\09mov 0x04+0($0), %eax\0A\09imull 0x04+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_1: \0A\09mov 0x00+0($0), %eax\0A\09imull 0x00+0($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_firorder_0:\0A\09jmp *$6 \0A\09ff_mlp_iirorder_4: \0A\09mov 0x0c+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x0c+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_iirorder_3: \0A\09mov 0x08+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x08+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_iirorder_2: \0A\09mov 0x04+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x04+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_iirorder_1: \0A\09mov 0x00+4*(8 + (40 * 4))($0), %eax\0A\09imull 0x00+4* 8($1) \0A\09add %eax , %esi\0A\09adc %edx , %ecx\0A\09ff_mlp_iirorder_0:\0A\09mov %ecx, %edx\0A\09mov %esi, %eax\0A\09movzbl $7 , %ecx\0A\09shrd %cl, %edx, %eax\0A\09mov %eax ,%edx \0A\09add ($2) ,%eax \0A\09and $4 ,%eax \0A\09sub $$4 , $0 \0A\09mov %eax, ($0) \0A\09mov %eax, ($2) \0A\09add $$4* 8 , $2 \0A\09sub %edx ,%eax \0A\09mov %eax,4*(8 + (40 * 4))($0) \0A\09incl $3 \0A\09js 1b \0A\09", "=r,=r,=r,=*m,*m,*m,*m,*m,0,1,2,*m,~{eax},~{edx},~{esi},~{ecx},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) %blocksize.addr, ptr elementtype(i32) %mask.addr, ptr elementtype(ptr) %firjump, ptr elementtype(ptr) %iirjump, ptr elementtype(i32) %filter_shift.addr, ptr %state, ptr %coeff, ptr %sample_buffer, ptr elementtype(i32) %blocksize.addr) nounwind, !srcloc !4 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/alloca-offset-lifetime.ll b/llvm/test/Instrumentation/AddressSanitizer/alloca-offset-lifetime.ll --- a/llvm/test/Instrumentation/AddressSanitizer/alloca-offset-lifetime.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/alloca-offset-lifetime.ll @@ -5,24 +5,23 @@ target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.15.0" -%t = type { void (%t*)*, void (%t*)*, %sub, i64 } +%t = type { ptr, ptr, %sub, i64 } %sub = type { i32 } define void @foo() sanitize_address { entry: %0 = alloca %t, align 8 - %x = getelementptr inbounds %t, %t* %0, i64 0, i32 2 - %1 = bitcast %sub* %x to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %1) - call void @bar(%sub* nonnull %x) - call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %1) #3 + %x = getelementptr inbounds %t, ptr %0, i64 0, i32 2 + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %x) + call void @bar(ptr nonnull %x) + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %x) #3 ret void } -declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) -declare void @bar(%sub*) -declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) +declare void @bar(ptr) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) -; CHECK: store i64 %[[STACK_BASE:.+]], i64* %asan_local_stack_base, align 8 +; CHECK: store i64 %[[STACK_BASE:.+]], ptr %asan_local_stack_base, align 8 ; CHECK-NOT: store i8 0 -; CHECK: call void @bar(%sub* nonnull %x) +; CHECK: call void @bar(ptr nonnull %x) diff --git a/llvm/test/Instrumentation/AddressSanitizer/asan-detect-invalid-pointer-pair.ll b/llvm/test/Instrumentation/AddressSanitizer/asan-detect-invalid-pointer-pair.ll --- a/llvm/test/Instrumentation/AddressSanitizer/asan-detect-invalid-pointer-pair.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/asan-detect-invalid-pointer-pair.ll @@ -8,24 +8,24 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" -define i32 @mycmp(i8* %p, i8* %q) sanitize_address { +define i32 @mycmp(ptr %p, ptr %q) sanitize_address { ; ALL-LABEL: @mycmp ; NOCMP-NOT: call void @__sanitizer_ptr_cmp -; CMP: [[P:%[0-9A-Za-z]+]] = ptrtoint i8* %p to i64 -; CMP: [[Q:%[0-9A-Za-z]+]] = ptrtoint i8* %q to i64 - %x = icmp ule i8* %p, %q +; CMP: [[P:%[0-9A-Za-z]+]] = ptrtoint ptr %p to i64 +; CMP: [[Q:%[0-9A-Za-z]+]] = ptrtoint ptr %q to i64 + %x = icmp ule ptr %p, %q ; CMP: call void @__sanitizer_ptr_cmp(i64 [[P]], i64 [[Q]]) %y = zext i1 %x to i32 ret i32 %y } -define i32 @mysub(i8* %p, i8* %q) sanitize_address { +define i32 @mysub(ptr %p, ptr %q) sanitize_address { ; ALL-LABEL: @mysub ; NOSUB-NOT: call void @__sanitizer_ptr_sub -; SUB: [[P:%[0-9A-Za-z]+]] = ptrtoint i8* %p to i64 -; SUB: [[Q:%[0-9A-Za-z]+]] = ptrtoint i8* %q to i64 - %x = ptrtoint i8* %p to i64 - %y = ptrtoint i8* %q to i64 +; SUB: [[P:%[0-9A-Za-z]+]] = ptrtoint ptr %p to i64 +; SUB: [[Q:%[0-9A-Za-z]+]] = ptrtoint ptr %q to i64 + %x = ptrtoint ptr %p to i64 + %y = ptrtoint ptr %q to i64 %z = sub i64 %x, %y ; SUB: call void @__sanitizer_ptr_sub(i64 [[P]], i64 [[Q]]) %w = trunc i64 %z to i32 diff --git a/llvm/test/Instrumentation/AddressSanitizer/asan-disable-sanitizer-instrumentation.ll b/llvm/test/Instrumentation/AddressSanitizer/asan-disable-sanitizer-instrumentation.ll --- a/llvm/test/Instrumentation/AddressSanitizer/asan-disable-sanitizer-instrumentation.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/asan-disable-sanitizer-instrumentation.ll @@ -6,11 +6,11 @@ ; Function with sanitize_address is instrumented. ; Function Attrs: nounwind uwtable -define void @instr_sa(i32* %a) sanitize_address { +define void @instr_sa(ptr %a) sanitize_address { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 %tmp2 = add i32 %tmp1, 1 - store i32 %tmp2, i32* %a, align 4 + store i32 %tmp2, ptr %a, align 4 ret void } @@ -20,11 +20,11 @@ ; Function with disable_sanitizer_instrumentation is not instrumented. ; Function Attrs: nounwind uwtable -define void @noinstr_dsi(i32* %a) disable_sanitizer_instrumentation { +define void @noinstr_dsi(ptr %a) disable_sanitizer_instrumentation { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 %tmp2 = add i32 %tmp1, 1 - store i32 %tmp2, i32* %a, align 4 + store i32 %tmp2, ptr %a, align 4 ret void } @@ -34,11 +34,11 @@ ; disable_sanitizer_instrumentation takes precedence over sanitize_address. ; Function Attrs: nounwind uwtable -define void @noinstr_dsi_sa(i32* %a) disable_sanitizer_instrumentation sanitize_address { +define void @noinstr_dsi_sa(ptr %a) disable_sanitizer_instrumentation sanitize_address { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 %tmp2 = add i32 %tmp1, 1 - store i32 %tmp2, i32* %a, align 4 + store i32 %tmp2, ptr %a, align 4 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll b/llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll --- a/llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/asan-masked-load-store.ll @@ -10,74 +10,74 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" -@v4f32 = global <4 x float>* zeroinitializer, align 8 -@v8i32 = global <8 x i32>* zeroinitializer, align 8 -@v4i64 = global <4 x i32*>* zeroinitializer, align 8 +@v4f32 = global ptr zeroinitializer, align 8 +@v8i32 = global ptr zeroinitializer, align 8 +@v4i64 = global ptr zeroinitializer, align 8 ;;;;;;;;;;;;;;;; STORE -declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>) argmemonly nounwind -declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>) argmemonly nounwind -declare void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*>, <4 x i32*>*, i32, <4 x i1>) argmemonly nounwind +declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32, <4 x i1>) argmemonly nounwind +declare void @llvm.masked.store.v8i32.p0(<8 x i32>, ptr, i32, <8 x i1>) argmemonly nounwind +declare void @llvm.masked.store.v4p0.p0(<4 x ptr>, ptr, i32, <4 x i1>) argmemonly nounwind define void @store.v4f32.1110(<4 x float> %arg) sanitize_address { ; ALL-LABEL: @store.v4f32.1110 - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 + %p = load ptr, ptr @v4f32, align 8 ; NOSTORE-NOT: call void @__asan_store -; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 -; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 +; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 0 +; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; STORE: call void @__asan_store4(i64 [[PGEP0]]) -; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1 -; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64 +; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 1 +; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP1]] to i64 ; STORE: call void @__asan_store4(i64 [[PGEP1]]) -; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2 -; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64 +; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 2 +; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP2]] to i64 ; STORE: call void @__asan_store4(i64 [[PGEP2]]) -; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) - tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) +; STORE: tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) + tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) ret void } define void @store.v8i32.10010110(<8 x i32> %arg) sanitize_address { ; ALL-LABEL: @store.v8i32.10010110 - %p = load <8 x i32>*, <8 x i32>** @v8i32, align 8 + %p = load ptr, ptr @v8i32, align 8 ; NOSTORE-NOT: call void @__asan_store -; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0 -; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64 +; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 0 +; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; STORE: call void @__asan_store4(i64 [[PGEP0]]) -; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 3 -; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP3]] to i64 +; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 3 +; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; STORE: call void @__asan_store4(i64 [[PGEP3]]) -; STORE: [[GEP5:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 5 -; STORE: [[PGEP5:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP5]] to i64 +; STORE: [[GEP5:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 5 +; STORE: [[PGEP5:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP5]] to i64 ; STORE: call void @__asan_store4(i64 [[PGEP5]]) -; STORE: [[GEP6:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 6 -; STORE: [[PGEP6:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP6]] to i64 +; STORE: [[GEP6:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 6 +; STORE: [[PGEP6:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP6]] to i64 ; STORE: call void @__asan_store4(i64 [[PGEP6]]) -; STORE: tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> ) - tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> ) +; STORE: tail call void @llvm.masked.store.v8i32.p0(<8 x i32> %arg, ptr %p, i32 8, <8 x i1> ) + tail call void @llvm.masked.store.v8i32.p0(<8 x i32> %arg, ptr %p, i32 8, <8 x i1> ) ret void } -define void @store.v4i64.0001(<4 x i32*> %arg) sanitize_address { +define void @store.v4i64.0001(<4 x ptr> %arg) sanitize_address { ; ALL-LABEL: @store.v4i64.0001 - %p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8 + %p = load ptr, ptr @v4i64, align 8 ; NOSTORE-NOT: call void @__asan_store -; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3 -; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64 +; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x ptr>, ptr %p, i64 0, i64 3 +; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; STORE: call void @__asan_store8(i64 [[PGEP3]]) -; STORE: tail call void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*> %arg, <4 x i32*>* %p, i32 8, <4 x i1> ) - tail call void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*> %arg, <4 x i32*>* %p, i32 8, <4 x i1> ) +; STORE: tail call void @llvm.masked.store.v4p0.p0(<4 x ptr> %arg, ptr %p, i32 8, <4 x i1> ) + tail call void @llvm.masked.store.v4p0.p0(<4 x ptr> %arg, ptr %p, i32 8, <4 x i1> ) ret void } define void @store.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) sanitize_address { ; ALL-LABEL: @store.v4f32.variable - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 + %p = load ptr, ptr @v4f32, align 8 ; STORE: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0 ; STORE: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]] ; STORE: [[THEN0]]: -; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 -; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 +; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 0 +; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; STORE: call void @__asan_store4(i64 [[PGEP0]]) ; STORE: br label %[[AFTER0]] ; STORE: [[AFTER0]]: @@ -85,8 +85,8 @@ ; STORE: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1 ; STORE: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]] ; STORE: [[THEN1]]: -; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1 -; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64 +; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 1 +; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP1]] to i64 ; STORE: call void @__asan_store4(i64 [[PGEP1]]) ; STORE: br label %[[AFTER1]] ; STORE: [[AFTER1]]: @@ -94,8 +94,8 @@ ; STORE: [[MASK2:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 2 ; STORE: br i1 [[MASK2]], label %[[THEN2:[0-9A-Za-z]+]], label %[[AFTER2:[0-9A-Za-z]+]] ; STORE: [[THEN2]]: -; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2 -; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64 +; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 2 +; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP2]] to i64 ; STORE: call void @__asan_store4(i64 [[PGEP2]]) ; STORE: br label %[[AFTER2]] ; STORE: [[AFTER2]]: @@ -103,109 +103,109 @@ ; STORE: [[MASK3:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 3 ; STORE: br i1 [[MASK3]], label %[[THEN3:[0-9A-Za-z]+]], label %[[AFTER3:[0-9A-Za-z]+]] ; STORE: [[THEN3]]: -; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3 -; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64 +; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 3 +; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; STORE: call void @__asan_store4(i64 [[PGEP3]]) ; STORE: br label %[[AFTER3]] ; STORE: [[AFTER3]]: -; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask) - tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask) +; STORE: tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> %mask) + tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> %mask) ret void } ;; Store using two masked.stores, which should instrument them both. define void @store.v4f32.1010.split(<4 x float> %arg) sanitize_address { ; BOTH-LABEL: @store.v4f32.1010.split - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 -; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 -; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 + %p = load ptr, ptr @v4f32, align 8 +; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 0 +; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; STORE: call void @__asan_store4(i64 [[PGEP0]]) -; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) - tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) -; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2 -; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64 +; STORE: tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) + tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) +; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 2 +; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP1]] to i64 ; STORE: call void @__asan_store4(i64 [[PGEP1]]) -; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) - tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) +; STORE: tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) + tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) ret void } ;; Store using a masked.store after a full store. Shouldn't instrument the second one. define void @store.v4f32.0010.after.full.store(<4 x float> %arg) sanitize_address { ; BOTH-LABEL: @store.v4f32.0010.after.full.store - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 -; STORE: [[PTRTOINT:%[0-9A-Za-z]+]] = ptrtoint <4 x float>* %p to i64 + %p = load ptr, ptr @v4f32, align 8 +; STORE: [[PTRTOINT:%[0-9A-Za-z]+]] = ptrtoint ptr %p to i64 ; STORE: call void @__asan_store16(i64 [[PTRTOINT]]) -; STORE: store <4 x float> %arg, <4 x float>* %p - store <4 x float> %arg, <4 x float>* %p +; STORE: store <4 x float> %arg, ptr %p + store <4 x float> %arg, ptr %p ; STORE-NOT: call void @__asan_store -; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) - tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) +; STORE: tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) + tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) ret void } ;;;;;;;;;;;;;;;; LOAD -declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>) argmemonly nounwind -declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) argmemonly nounwind -declare <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>*, i32, <4 x i1>, <4 x i32*>) argmemonly nounwind +declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32, <4 x i1>, <4 x float>) argmemonly nounwind +declare <8 x i32> @llvm.masked.load.v8i32.p0(ptr, i32, <8 x i1>, <8 x i32>) argmemonly nounwind +declare <4 x ptr> @llvm.masked.load.v4p0.p0(ptr, i32, <4 x i1>, <4 x ptr>) argmemonly nounwind define <8 x i32> @load.v8i32.11100001(<8 x i32> %arg) sanitize_address { ; ALL-LABEL: @load.v8i32.11100001 - %p = load <8 x i32>*, <8 x i32>** @v8i32, align 8 + %p = load ptr, ptr @v8i32, align 8 ; NOLOAD-NOT: call void @__asan_load -; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0 -; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64 +; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 0 +; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; LOAD: call void @__asan_load4(i64 [[PGEP0]]) -; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 1 -; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP1]] to i64 +; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 1 +; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP1]] to i64 ; LOAD: call void @__asan_load4(i64 [[PGEP1]]) -; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 2 -; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP2]] to i64 +; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 2 +; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP2]] to i64 ; LOAD: call void @__asan_load4(i64 [[PGEP2]]) -; LOAD: [[GEP7:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 7 -; LOAD: [[PGEP7:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP7]] to i64 +; LOAD: [[GEP7:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 7 +; LOAD: [[PGEP7:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP7]] to i64 ; LOAD: call void @__asan_load4(i64 [[PGEP7]]) -; LOAD: tail call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %p, i32 8, <8 x i1> , <8 x i32> %arg) - %res = tail call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %p, i32 8, <8 x i1> , <8 x i32> %arg) +; LOAD: tail call <8 x i32> @llvm.masked.load.v8i32.p0(ptr %p, i32 8, <8 x i1> , <8 x i32> %arg) + %res = tail call <8 x i32> @llvm.masked.load.v8i32.p0(ptr %p, i32 8, <8 x i1> , <8 x i32> %arg) ret <8 x i32> %res } define <4 x float> @load.v4f32.1001(<4 x float> %arg) sanitize_address { ; ALL-LABEL: @load.v4f32.1001 - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 + %p = load ptr, ptr @v4f32, align 8 ; NOLOAD-NOT: call void @__asan_load -; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 -; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 +; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 0 +; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; LOAD: call void @__asan_load4(i64 [[PGEP0]]) -; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3 -; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64 +; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 3 +; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; LOAD: call void @__asan_load4(i64 [[PGEP3]]) -; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %arg) - %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %arg) +; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %arg) + %res = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %arg) ret <4 x float> %res } -define <4 x i32*> @load.v4i64.0001(<4 x i32*> %arg) sanitize_address { +define <4 x ptr> @load.v4i64.0001(<4 x ptr> %arg) sanitize_address { ; ALL-LABEL: @load.v4i64.0001 - %p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8 + %p = load ptr, ptr @v4i64, align 8 ; NOLOAD-NOT: call void @__asan_load -; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3 -; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64 +; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x ptr>, ptr %p, i64 0, i64 3 +; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; LOAD: call void @__asan_load8(i64 [[PGEP3]]) -; LOAD: tail call <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>* %p, i32 8, <4 x i1> , <4 x i32*> %arg) - %res = tail call <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>* %p, i32 8, <4 x i1> , <4 x i32*> %arg) - ret <4 x i32*> %res +; LOAD: tail call <4 x ptr> @llvm.masked.load.v4p0.p0(ptr %p, i32 8, <4 x i1> , <4 x ptr> %arg) + %res = tail call <4 x ptr> @llvm.masked.load.v4p0.p0(ptr %p, i32 8, <4 x i1> , <4 x ptr> %arg) + ret <4 x ptr> %res } define <4 x float> @load.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) sanitize_address { ; ALL-LABEL: @load.v4f32.variable - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 + %p = load ptr, ptr @v4f32, align 8 ; LOAD: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0 ; LOAD: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]] ; LOAD: [[THEN0]]: -; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 -; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 +; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 0 +; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; LOAD: call void @__asan_load4(i64 [[PGEP0]]) ; LOAD: br label %[[AFTER0]] ; LOAD: [[AFTER0]]: @@ -213,8 +213,8 @@ ; LOAD: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1 ; LOAD: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]] ; LOAD: [[THEN1]]: -; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1 -; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64 +; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 1 +; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP1]] to i64 ; LOAD: call void @__asan_load4(i64 [[PGEP1]]) ; LOAD: br label %[[AFTER1]] ; LOAD: [[AFTER1]]: @@ -222,8 +222,8 @@ ; LOAD: [[MASK2:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 2 ; LOAD: br i1 [[MASK2]], label %[[THEN2:[0-9A-Za-z]+]], label %[[AFTER2:[0-9A-Za-z]+]] ; LOAD: [[THEN2]]: -; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2 -; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64 +; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 2 +; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP2]] to i64 ; LOAD: call void @__asan_load4(i64 [[PGEP2]]) ; LOAD: br label %[[AFTER2]] ; LOAD: [[AFTER2]]: @@ -231,44 +231,44 @@ ; LOAD: [[MASK3:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 3 ; LOAD: br i1 [[MASK3]], label %[[THEN3:[0-9A-Za-z]+]], label %[[AFTER3:[0-9A-Za-z]+]] ; LOAD: [[THEN3]]: -; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3 -; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64 +; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 3 +; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; LOAD: call void @__asan_load4(i64 [[PGEP3]]) ; LOAD: br label %[[AFTER3]] ; LOAD: [[AFTER3]]: -; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg) - %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg) +; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> %mask, <4 x float> %arg) + %res = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> %mask, <4 x float> %arg) ret <4 x float> %res } ;; Load using two masked.loads, which should instrument them both. define <4 x float> @load.v4f32.1001.split(<4 x float> %arg) sanitize_address { ; BOTH-LABEL: @load.v4f32.1001 - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 -; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 -; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 + %p = load ptr, ptr @v4f32, align 8 +; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 0 +; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; LOAD: call void @__asan_load4(i64 [[PGEP0]]) -; LOAD: %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %arg) - %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %arg) -; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3 -; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64 +; LOAD: %res = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %arg) + %res = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %arg) +; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 3 +; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; LOAD: call void @__asan_load4(i64 [[PGEP3]]) -; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %res) - %res2 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %res) +; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %res) + %res2 = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %res) ret <4 x float> %res2 } ;; Load using a masked.load after a full load. Shouldn't instrument the second one. define <4 x float> @load.v4f32.1001.after.full.load(<4 x float> %arg) sanitize_address { ; BOTH-LABEL: @load.v4f32.1001.after.full.load - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 -; LOAD: [[PTRTOINT:%[0-9A-Za-z]+]] = ptrtoint <4 x float>* %p to i64 + %p = load ptr, ptr @v4f32, align 8 +; LOAD: [[PTRTOINT:%[0-9A-Za-z]+]] = ptrtoint ptr %p to i64 ; LOAD: call void @__asan_load16(i64 [[PTRTOINT]]) -; LOAD: %res = load <4 x float>, <4 x float>* %p - %res = load <4 x float>, <4 x float>* %p +; LOAD: %res = load <4 x float>, ptr %p + %res = load <4 x float>, ptr %p ; LOAD-NOT: call void @__asan_load -; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %arg) - %res2 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %arg) +; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %arg) + %res2 = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %arg) ret <4 x float> %res2 } diff --git a/llvm/test/Instrumentation/AddressSanitizer/asan-optimize-callbacks.ll b/llvm/test/Instrumentation/AddressSanitizer/asan-optimize-callbacks.ll --- a/llvm/test/Instrumentation/AddressSanitizer/asan-optimize-callbacks.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/asan-optimize-callbacks.ll @@ -6,81 +6,65 @@ target triple = "x86_64-unknown-linux-gnu" -define void @load(i8* %p1, i16* %p2, i32* %p4, i64* %p8, i128* %p16) +define void @load(ptr %p1, ptr %p2, ptr %p4, ptr %p8, ptr %p16) sanitize_address { - %n1 = load i8, i8* %p1, align 1 - %n2 = load i16, i16* %p2, align 2 - %n4 = load i32, i32* %p4, align 4 - %n8 = load i64, i64* %p8, align 8 - %n16 = load i128, i128* %p16, align 16 -; LOAD: call void @llvm.asan.check.memaccess(i8* %p1, i32 0) -; LOAD-NEXT: %n1 = load i8, i8* %p1, align 1 -; LOAD-NEXT: %1 = bitcast i16* %p2 to i8* -; LOAD-NEXT: call void @llvm.asan.check.memaccess(i8* %1, i32 2) -; LOAD-NEXT: %n2 = load i16, i16* %p2, align 2 -; LOAD-NEXT: %2 = bitcast i32* %p4 to i8* -; LOAD-NEXT: call void @llvm.asan.check.memaccess(i8* %2, i32 4) -; LOAD-NEXT: %n4 = load i32, i32* %p4, align 4 -; LOAD-NEXT: %3 = bitcast i64* %p8 to i8* -; LOAD-NEXT: call void @llvm.asan.check.memaccess(i8* %3, i32 6) -; LOAD-NEXT: %n8 = load i64, i64* %p8, align 8 -; LOAD-NEXT: %4 = bitcast i128* %p16 to i8* -; LOAD-NEXT: call void @llvm.asan.check.memaccess(i8* %4, i32 8) -; LOAD-NEXT: %n16 = load i128, i128* %p16, align 16 + %n1 = load i8, ptr %p1, align 1 + %n2 = load i16, ptr %p2, align 2 + %n4 = load i32, ptr %p4, align 4 + %n8 = load i64, ptr %p8, align 8 + %n16 = load i128, ptr %p16, align 16 +; LOAD: call void @llvm.asan.check.memaccess(ptr %p1, i32 0) +; LOAD-NEXT: %n1 = load i8, ptr %p1, align 1 +; LOAD-NEXT: call void @llvm.asan.check.memaccess(ptr %p2, i32 2) +; LOAD-NEXT: %n2 = load i16, ptr %p2, align 2 +; LOAD-NEXT: call void @llvm.asan.check.memaccess(ptr %p4, i32 4) +; LOAD-NEXT: %n4 = load i32, ptr %p4, align 4 +; LOAD-NEXT: call void @llvm.asan.check.memaccess(ptr %p8, i32 6) +; LOAD-NEXT: %n8 = load i64, ptr %p8, align 8 +; LOAD-NEXT: call void @llvm.asan.check.memaccess(ptr %p16, i32 8) +; LOAD-NEXT: %n16 = load i128, ptr %p16, align 16 -; LOAD-KERNEL: call void @llvm.asan.check.memaccess(i8* %p1, i32 1) -; LOAD-KERNEL-NEXT: %n1 = load i8, i8* %p1, align 1 -; LOAD-KERNEL-NEXT: %1 = bitcast i16* %p2 to i8* -; LOAD-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %1, i32 3) -; LOAD-KERNEL-NEXT: %n2 = load i16, i16* %p2, align 2 -; LOAD-KERNEL-NEXT: %2 = bitcast i32* %p4 to i8* -; LOAD-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %2, i32 5) -; LOAD-KERNEL-NEXT: %n4 = load i32, i32* %p4, align 4 -; LOAD-KERNEL-NEXT: %3 = bitcast i64* %p8 to i8* -; LOAD-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %3, i32 7) -; LOAD-KERNEL-NEXT: %n8 = load i64, i64* %p8, align 8 -; LOAD-KERNEL-NEXT: %4 = bitcast i128* %p16 to i8* -; LOAD-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %4, i32 9) -; LOAD-KERNEL-NEXT: %n16 = load i128, i128* %p16, align 16 +; LOAD-KERNEL: call void @llvm.asan.check.memaccess(ptr %p1, i32 1) +; LOAD-KERNEL-NEXT: %n1 = load i8, ptr %p1, align 1 +; LOAD-KERNEL-NEXT: call void @llvm.asan.check.memaccess(ptr %p2, i32 3) +; LOAD-KERNEL-NEXT: %n2 = load i16, ptr %p2, align 2 +; LOAD-KERNEL-NEXT: call void @llvm.asan.check.memaccess(ptr %p4, i32 5) +; LOAD-KERNEL-NEXT: %n4 = load i32, ptr %p4, align 4 +; LOAD-KERNEL-NEXT: call void @llvm.asan.check.memaccess(ptr %p8, i32 7) +; LOAD-KERNEL-NEXT: %n8 = load i64, ptr %p8, align 8 +; LOAD-KERNEL-NEXT: call void @llvm.asan.check.memaccess(ptr %p16, i32 9) +; LOAD-KERNEL-NEXT: %n16 = load i128, ptr %p16, align 16 ret void } -define void @store(i8* %p1, i16* %p2, i32* %p4, i64* %p8, i128* %p16) +define void @store(ptr %p1, ptr %p2, ptr %p4, ptr %p8, ptr %p16) sanitize_address { - store i8 0, i8* %p1, align 1 - store i16 0, i16* %p2, align 2 - store i32 0, i32* %p4, align 4 - store i64 0, i64* %p8, align 8 - store i128 0, i128* %p16, align 16 -; STORE: call void @llvm.asan.check.memaccess(i8* %p1, i32 32) -; STORE-NEXT: store i8 0, i8* %p1, align 1 -; STORE-NEXT: %1 = bitcast i16* %p2 to i8* -; STORE-NEXT: call void @llvm.asan.check.memaccess(i8* %1, i32 34) -; STORE-NEXT: store i16 0, i16* %p2, align 2 -; STORE-NEXT: %2 = bitcast i32* %p4 to i8* -; STORE-NEXT: call void @llvm.asan.check.memaccess(i8* %2, i32 36) -; STORE-NEXT: store i32 0, i32* %p4, align 4 -; STORE-NEXT: %3 = bitcast i64* %p8 to i8* -; STORE-NEXT: call void @llvm.asan.check.memaccess(i8* %3, i32 38) -; STORE-NEXT: store i64 0, i64* %p8, align 8 -; STORE-NEXT: %4 = bitcast i128* %p16 to i8* -; STORE-NEXT: call void @llvm.asan.check.memaccess(i8* %4, i32 40) -; STORE-NEXT: store i128 0, i128* %p16, align 16 + store i8 0, ptr %p1, align 1 + store i16 0, ptr %p2, align 2 + store i32 0, ptr %p4, align 4 + store i64 0, ptr %p8, align 8 + store i128 0, ptr %p16, align 16 +; STORE: call void @llvm.asan.check.memaccess(ptr %p1, i32 32) +; STORE-NEXT: store i8 0, ptr %p1, align 1 +; STORE-NEXT: call void @llvm.asan.check.memaccess(ptr %p2, i32 34) +; STORE-NEXT: store i16 0, ptr %p2, align 2 +; STORE-NEXT: call void @llvm.asan.check.memaccess(ptr %p4, i32 36) +; STORE-NEXT: store i32 0, ptr %p4, align 4 +; STORE-NEXT: call void @llvm.asan.check.memaccess(ptr %p8, i32 38) +; STORE-NEXT: store i64 0, ptr %p8, align 8 +; STORE-NEXT: call void @llvm.asan.check.memaccess(ptr %p16, i32 40) +; STORE-NEXT: store i128 0, ptr %p16, align 16 -; STORE-KERNEL: call void @llvm.asan.check.memaccess(i8* %p1, i32 33) -; STORE-KERNEL-NEXT: store i8 0, i8* %p1, align 1 -; STORE-KERNEL-NEXT: %1 = bitcast i16* %p2 to i8* -; STORE-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %1, i32 35) -; STORE-KERNEL-NEXT: store i16 0, i16* %p2, align 2 -; STORE-KERNEL-NEXT: %2 = bitcast i32* %p4 to i8* -; STORE-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %2, i32 37) -; STORE-KERNEL-NEXT: store i32 0, i32* %p4, align 4 -; STORE-KERNEL-NEXT: %3 = bitcast i64* %p8 to i8* -; STORE-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %3, i32 39) -; STORE-KERNEL-NEXT: store i64 0, i64* %p8, align 8 -; STORE-KERNEL-NEXT: %4 = bitcast i128* %p16 to i8* -; STORE-KERNEL-NEXT: call void @llvm.asan.check.memaccess(i8* %4, i32 41) -; STORE-KERNEL-NEXT: store i128 0, i128* %p16, align 16 +; STORE-KERNEL: call void @llvm.asan.check.memaccess(ptr %p1, i32 33) +; STORE-KERNEL-NEXT: store i8 0, ptr %p1, align 1 +; STORE-KERNEL-NEXT: call void @llvm.asan.check.memaccess(ptr %p2, i32 35) +; STORE-KERNEL-NEXT: store i16 0, ptr %p2, align 2 +; STORE-KERNEL-NEXT: call void @llvm.asan.check.memaccess(ptr %p4, i32 37) +; STORE-KERNEL-NEXT: store i32 0, ptr %p4, align 4 +; STORE-KERNEL-NEXT: call void @llvm.asan.check.memaccess(ptr %p8, i32 39) +; STORE-KERNEL-NEXT: store i64 0, ptr %p8, align 8 +; STORE-KERNEL-NEXT: call void @llvm.asan.check.memaccess(ptr %p16, i32 41) +; STORE-KERNEL-NEXT: store i128 0, ptr %p16, align 16 ; STORE-KERNEL-NEXT: ret void ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/asan-stack-safety.ll b/llvm/test/Instrumentation/AddressSanitizer/asan-stack-safety.ll --- a/llvm/test/Instrumentation/AddressSanitizer/asan-stack-safety.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/asan-stack-safety.ll @@ -7,8 +7,7 @@ define i32 @load() sanitize_address { %buf = alloca [10 x i8], align 1 ; NOSAFETY: call i64 @__asan_stack_malloc - %arrayidx = getelementptr inbounds [10 x i8], [10 x i8]* %buf, i64 0, i64 0 - %1 = load i8, i8* %arrayidx, align 1 + %1 = load i8, ptr %buf, align 1 ; NOSAFETY: call void @__asan_load1 ret i32 0 } @@ -17,8 +16,7 @@ define i32 @store() sanitize_address { %buf = alloca [10 x i8], align 1 ; NOSAFETY: call i64 @__asan_stack_malloc - %arrayidx = getelementptr inbounds [10 x i8], [10 x i8]* %buf, i64 0, i64 0 - store i8 0, i8* %arrayidx + store i8 0, ptr %buf ; NOSAFETY: call void @__asan_store1 ret i32 0 } @@ -27,11 +25,10 @@ define i32 @unsafe_alloca(i32 %i) sanitize_address { %buf.sroa.0 = alloca [10 x i8], align 4 ; CHECK: call i64 @__asan_stack_malloc - %ptr = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 %i, i32 0 - store volatile i8 0, i8* %ptr, align 4 + %ptr = getelementptr [10 x i8], ptr %buf.sroa.0, i32 %i, i32 0 + store volatile i8 0, ptr %ptr, align 4 ; CHECK: call void @__asan_store1 - %ptr2 = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 0 - store volatile i8 0, i8* %ptr2, align 4 + store volatile i8 0, ptr %buf.sroa.0, align 4 ; NOSAFETY: call void @__asan_store1 ret i32 0 } @@ -40,8 +37,7 @@ define void @atomicrmw() sanitize_address { %buf = alloca [10 x i8], align 1 ; NOSAFETY: call i64 @__asan_stack_malloc - %arrayidx = getelementptr inbounds [10 x i8], [10 x i8]* %buf, i64 0, i64 0 - %1 = atomicrmw add i8* %arrayidx, i8 1 seq_cst + %1 = atomicrmw add ptr %buf, i8 1 seq_cst ; NOSAFETY: call void @__asan_store1 ret void } @@ -50,8 +46,7 @@ define void @cmpxchg(i8 %compare_to, i8 %new_value) sanitize_address { %buf = alloca [10 x i8], align 1 ; NOSAFETY: call i64 @__asan_stack_malloc - %arrayidx = getelementptr inbounds [10 x i8], [10 x i8]* %buf, i64 0, i64 0 - %1 = cmpxchg i8* %arrayidx, i8 %compare_to, i8 %new_value seq_cst seq_cst + %1 = cmpxchg ptr %buf, i8 %compare_to, i8 %new_value seq_cst seq_cst ; NOSAFETY: call void @__asan_store1 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/asan-vs-gvn.ll b/llvm/test/Instrumentation/AddressSanitizer/asan-vs-gvn.ll --- a/llvm/test/Instrumentation/AddressSanitizer/asan-vs-gvn.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/asan-vs-gvn.ll @@ -13,11 +13,11 @@ ; Accessing bytes 4 and 6, not ok to widen to i32 if sanitize_address is set. -define i32 @test_widening_bad(i8* %P) nounwind ssp noredzone sanitize_address { +define i32 @test_widening_bad(ptr %P) nounwind ssp noredzone sanitize_address { entry: - %tmp = load i8, i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned, %struct_of_7_bytes_4_aligned* @f, i64 0, i32 1), align 4 + %tmp = load i8, ptr getelementptr inbounds (%struct_of_7_bytes_4_aligned, ptr @f, i64 0, i32 1), align 4 %conv = zext i8 %tmp to i32 - %tmp1 = load i8, i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned, %struct_of_7_bytes_4_aligned* @f, i64 0, i32 3), align 1 + %tmp1 = load i8, ptr getelementptr inbounds (%struct_of_7_bytes_4_aligned, ptr @f, i64 0, i32 3), align 1 %conv2 = zext i8 %tmp1 to i32 %add = add nsw i32 %conv, %conv2 ret i32 %add @@ -36,11 +36,11 @@ ;; Accessing bytes 4 and 5. No widen to i16. -define i32 @test_widening_ok(i8* %P) nounwind ssp noredzone sanitize_address { +define i32 @test_widening_ok(ptr %P) nounwind ssp noredzone sanitize_address { entry: - %tmp = load i8, i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned, %struct_of_7_bytes_4_aligned* @f, i64 0, i32 1), align 4 + %tmp = load i8, ptr getelementptr inbounds (%struct_of_7_bytes_4_aligned, ptr @f, i64 0, i32 1), align 4 %conv = zext i8 %tmp to i32 - %tmp1 = load i8, i8* getelementptr inbounds (%struct_of_7_bytes_4_aligned, %struct_of_7_bytes_4_aligned* @f, i64 0, i32 2), align 1 + %tmp1 = load i8, ptr getelementptr inbounds (%struct_of_7_bytes_4_aligned, ptr @f, i64 0, i32 2), align 1 %conv2 = zext i8 %tmp1 to i32 %add = add nsw i32 %conv, %conv2 ret i32 %add diff --git a/llvm/test/Instrumentation/AddressSanitizer/asan_address_space_attr.ll b/llvm/test/Instrumentation/AddressSanitizer/asan_address_space_attr.ll --- a/llvm/test/Instrumentation/AddressSanitizer/asan_address_space_attr.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/asan_address_space_attr.ll @@ -5,28 +5,28 @@ ; Checks that we do not instrument loads and stores comming from custom address space. ; These result in invalid (false positive) reports. ; int foo(int argc, const char * argv[]) { -; void *__attribute__((address_space(256))) *gs_base = (((void * __attribute__((address_space(256))) *)0)); -; void *somevalue = gs_base[-1]; +; ptr__attribute__((address_space(256))) *gs_base = (((ptr __attribute__((address_space(256))) *)0)); +; ptr somevalue = gs_base[-1]; ; return somevalue; ; } -define i32 @foo(i32 %argc, i8** %argv) sanitize_address { +define i32 @foo(i32 %argc, ptr %argv) sanitize_address { entry: %retval = alloca i32, align 4 %argc.addr = alloca i32, align 4 - %argv.addr = alloca i8**, align 8 - %gs_base = alloca i8* addrspace(256)*, align 8 - %somevalue = alloca i8*, align 8 - store i32 0, i32* %retval, align 4 - store i32 %argc, i32* %argc.addr, align 4 - store i8** %argv, i8*** %argv.addr, align 8 - store i8* addrspace(256)* null, i8* addrspace(256)** %gs_base, align 8 - %0 = load i8* addrspace(256)*, i8* addrspace(256)** %gs_base, align 8 - %arrayidx = getelementptr inbounds i8*, i8* addrspace(256)* %0, i64 -1 - %1 = load i8*, i8* addrspace(256)* %arrayidx, align 8 - store i8* %1, i8** %somevalue, align 8 - %2 = load i8*, i8** %somevalue, align 8 - %3 = ptrtoint i8* %2 to i32 + %argv.addr = alloca ptr, align 8 + %gs_base = alloca ptr addrspace(256), align 8 + %somevalue = alloca ptr, align 8 + store i32 0, ptr %retval, align 4 + store i32 %argc, ptr %argc.addr, align 4 + store ptr %argv, ptr %argv.addr, align 8 + store ptr addrspace(256) null, ptr %gs_base, align 8 + %0 = load ptr addrspace(256), ptr %gs_base, align 8 + %arrayidx = getelementptr inbounds ptr, ptr addrspace(256) %0, i64 -1 + %1 = load ptr, ptr addrspace(256) %arrayidx, align 8 + store ptr %1, ptr %somevalue, align 8 + %2 = load ptr, ptr %somevalue, align 8 + %3 = ptrtoint ptr %2 to i32 ret i32 %3 } ; CHECK-NOT: call void @__asan_report_load8 diff --git a/llvm/test/Instrumentation/AddressSanitizer/basic-msvc64.ll b/llvm/test/Instrumentation/AddressSanitizer/basic-msvc64.ll --- a/llvm/test/Instrumentation/AddressSanitizer/basic-msvc64.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/basic-msvc64.ll @@ -5,31 +5,31 @@ target triple = "x86_64-pc-windows-msvc" ; CHECK: @llvm.global_ctors = {{.*}}@asan.module_ctor -define i32 @test_load(i32* %a) sanitize_address { +define i32 @test_load(ptr %a) sanitize_address { ; First instrumentation in the function must be to load the dynamic shadow ; address into a local variable. ; CHECK-LABEL: @test_load ; CHECK: entry: -; CHECK-NEXT: %[[SHADOW:[^ ]*]] = load i64, i64* @__asan_shadow_memory_dynamic_address +; CHECK-NEXT: %[[SHADOW:[^ ]*]] = load i64, ptr @__asan_shadow_memory_dynamic_address ; Shadow address is loaded and added into the whole offset computation. ; CHECK: add i64 %{{.*}}, %[[SHADOW]] entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } -define i32 @__asan_options(i32* %a) sanitize_address { +define i32 @__asan_options(ptr %a) sanitize_address { ; Asan functions are not instrumented. Asan function may be called by ; __asan_init before the shadow initialisation, which may lead to incorrect ; behavior of the instrumented code. ; CHECK-LABEL: @__asan_options ; CHECK: entry: -; CHECK-NEXT: %tmp1 = load i32, i32* %a, align 4 +; CHECK-NEXT: %tmp1 = load i32, ptr %a, align 4 ; CHECK-NEXT: ret i32 %tmp1 entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } diff --git a/llvm/test/Instrumentation/AddressSanitizer/basic.ll b/llvm/test/Instrumentation/AddressSanitizer/basic.ll --- a/llvm/test/Instrumentation/AddressSanitizer/basic.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/basic.ll @@ -6,18 +6,18 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -; CHECK: @llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @asan.module_ctor to i8*)] -; CHECK: @llvm.global_ctors = {{.*}}{ i32 1, void ()* @asan.module_ctor, i8* bitcast (void ()* @asan.module_ctor to i8*) } +; CHECK: @llvm.used = appending global [1 x ptr] [ptr @asan.module_ctor] +; CHECK: @llvm.global_ctors = {{.*}}{ i32 1, ptr @asan.module_ctor, ptr @asan.module_ctor } -define i32 @test_load(i32* %a) sanitize_address { +define i32 @test_load(ptr %a) sanitize_address { ; CHECK-LABEL: @test_load ; CHECK-NOT: load -; CHECK: %[[LOAD_ADDR:[^ ]*]] = ptrtoint i32* %a to i64 +; CHECK: %[[LOAD_ADDR:[^ ]*]] = ptrtoint ptr %a to i64 ; CHECK-S3: lshr i64 %[[LOAD_ADDR]], 3 ; CHECK-S5: lshr i64 %[[LOAD_ADDR]], 5 ; CHECK: {{or|add}} ; CHECK: %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr -; CHECK: %[[LOAD_SHADOW:[^ ]*]] = load i8, i8* %[[LOAD_SHADOW_PTR]] +; CHECK: %[[LOAD_SHADOW:[^ ]*]] = load i8, ptr %[[LOAD_SHADOW_PTR]] ; CHECK: icmp ne i8 ; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}}!prof ![[PROF:[0-9]+]] ; @@ -34,25 +34,25 @@ ; CHECK: unreachable ; ; The actual load. -; CHECK: %tmp1 = load i32, i32* %a +; CHECK: %tmp1 = load i32, ptr %a ; CHECK: ret i32 %tmp1 entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } -define void @test_store(i32* %a) sanitize_address { +define void @test_store(ptr %a) sanitize_address { ; CHECK-LABEL: @test_store ; CHECK-NOT: store -; CHECK: %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %a to i64 +; CHECK: %[[STORE_ADDR:[^ ]*]] = ptrtoint ptr %a to i64 ; CHECK-S3: lshr i64 %[[STORE_ADDR]], 3 ; CHECK-S5: lshr i64 %[[STORE_ADDR]], 5 ; CHECK: {{or|add}} ; CHECK: %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr -; CHECK: %[[STORE_SHADOW:[^ ]*]] = load i8, i8* %[[STORE_SHADOW_PTR]] +; CHECK: %[[STORE_SHADOW:[^ ]*]] = load i8, ptr %[[STORE_SHADOW_PTR]] ; CHECK: icmp ne i8 ; CHECK: br i1 %{{.*}}, label %{{.*}}, label %{{.*}} ; @@ -69,26 +69,26 @@ ; CHECK: unreachable ; ; The actual load. -; CHECK: store i32 42, i32* %a +; CHECK: store i32 42, ptr %a ; CHECK: ret void ; entry: - store i32 42, i32* %a, align 4 + store i32 42, ptr %a, align 4 ret void } ; Check that asan leaves just one alloca. -declare void @alloca_test_use([10 x i8]*) +declare void @alloca_test_use(ptr) define void @alloca_test() sanitize_address { entry: %x = alloca [10 x i8], align 1 %y = alloca [10 x i8], align 1 %z = alloca [10 x i8], align 1 - call void @alloca_test_use([10 x i8]* %x) - call void @alloca_test_use([10 x i8]* %y) - call void @alloca_test_use([10 x i8]* %z) + call void @alloca_test_use(ptr %x) + call void @alloca_test_use(ptr %y) + call void @alloca_test_use(ptr %z) ret void } @@ -98,9 +98,9 @@ ; CHECK-NOT: = alloca ; CHECK: ret void -define void @LongDoubleTest(x86_fp80* nocapture %a) nounwind uwtable sanitize_address { +define void @LongDoubleTest(ptr nocapture %a) nounwind uwtable sanitize_address { entry: - store x86_fp80 0xK3FFF8000000000000000, x86_fp80* %a, align 16 + store x86_fp80 0xK3FFF8000000000000000, ptr %a, align 16 ret void } @@ -110,10 +110,10 @@ ; CHECK: ret void -define void @i40test(i40* %a, i40* %b) nounwind uwtable sanitize_address { +define void @i40test(ptr %a, ptr %b) nounwind uwtable sanitize_address { entry: - %t = load i40, i40* %a - store i40 %t, i40* %b, align 8 + %t = load i40, ptr %a + store i40 %t, ptr %b, align 8 ret void } @@ -124,9 +124,9 @@ ; CHECK: __asan_report_store_n{{.*}}, i64 5) ; CHECK: ret void -define void @i64test_align1(i64* %b) nounwind uwtable sanitize_address { +define void @i64test_align1(ptr %b) nounwind uwtable sanitize_address { entry: - store i64 0, i64* %b, align 1 + store i64 0, ptr %b, align 1 ret void } @@ -136,10 +136,10 @@ ; CHECK: ret void -define void @i80test(i80* %a, i80* %b) nounwind uwtable sanitize_address { +define void @i80test(ptr %a, ptr %b) nounwind uwtable sanitize_address { entry: - %t = load i80, i80* %a - store i80 %t, i80* %b, align 8 + %t = load i80, ptr %a + store i80 %t, ptr %b, align 8 ret void } @@ -151,9 +151,9 @@ ; CHECK: ret void ; asan should not instrument functions with available_externally linkage. -define available_externally i32 @f_available_externally(i32* %a) sanitize_address { +define available_externally i32 @f_available_externally(ptr %a) sanitize_address { entry: - %tmp1 = load i32, i32* %a + %tmp1 = load i32, ptr %a ret i32 %tmp1 } ; CHECK-LABEL: @f_available_externally @@ -164,16 +164,16 @@ ; CHECK-LABEL: @test_swifterror ; CHECK-NOT: __asan_report_load ; CHECK: ret void -define void @test_swifterror(i8** swifterror) sanitize_address { - %swifterror_ptr_value = load i8*, i8** %0 +define void @test_swifterror(ptr swifterror) sanitize_address { + %swifterror_ptr_value = load ptr, ptr %0 ret void } ; CHECK-LABEL: @test_swifterror_2 ; CHECK-NOT: __asan_report_store ; CHECK: ret void -define void @test_swifterror_2(i8** swifterror) sanitize_address { - store i8* null, i8** %0 +define void @test_swifterror_2(ptr swifterror) sanitize_address { + store ptr null, ptr %0 ret void } @@ -181,9 +181,9 @@ ; CHECK-NOT: __asan_report_store ; CHECK: ret void define void @test_swifterror_3() sanitize_address { - %swifterror_addr = alloca swifterror i8* - store i8* null, i8** %swifterror_addr - call void @test_swifterror_2(i8** swifterror %swifterror_addr) + %swifterror_addr = alloca swifterror ptr + store ptr null, ptr %swifterror_addr + call void @test_swifterror_2(ptr swifterror %swifterror_addr) ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/byref-args.ll b/llvm/test/Instrumentation/AddressSanitizer/byref-args.ll --- a/llvm/test/Instrumentation/AddressSanitizer/byref-args.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/byref-args.ll @@ -7,14 +7,14 @@ target triple = "x86_64-unknown-linux-gnu" %struct.bar = type { %struct.foo } -%struct.foo = type { i8*, i8*, i8* } +%struct.foo = type { ptr, ptr, ptr } ; CHECK-LABEL: @func2 ; CHECK-NEXT: tail call void @func1( ; CHECK-NEXT: ret void -define dso_local void @func2(%struct.foo* %foo) sanitize_address { - tail call void @func1(%struct.foo* byref(%struct.foo) align 8 %foo) #2 +define dso_local void @func2(ptr %foo) sanitize_address { + tail call void @func1(ptr byref(%struct.foo) align 8 %foo) #2 ret void } -declare dso_local void @func1(%struct.foo* byref(%struct.foo) align 8) +declare dso_local void @func1(ptr byref(%struct.foo) align 8) diff --git a/llvm/test/Instrumentation/AddressSanitizer/byval-args.ll b/llvm/test/Instrumentation/AddressSanitizer/byval-args.ll --- a/llvm/test/Instrumentation/AddressSanitizer/byval-args.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/byval-args.ll @@ -5,14 +5,14 @@ target triple = "x86_64-unknown-linux-gnu" %struct.bar = type { %struct.foo } -%struct.foo = type { i8*, i8*, i8* } -define dso_local void @func2(%struct.foo* %foo) sanitize_address { +%struct.foo = type { ptr, ptr, ptr } +define dso_local void @func2(ptr %foo) sanitize_address { ; CHECK-LABEL: @func2 - tail call void @func1(%struct.foo* byval(%struct.foo) align 8 %foo) #2 + tail call void @func1(ptr byval(%struct.foo) align 8 %foo) #2 ; CHECK: call void @__asan_report_load ret void ; CHECK: ret void } -declare dso_local void @func1(%struct.foo* byval(%struct.foo) align 8) +declare dso_local void @func1(ptr byval(%struct.foo) align 8) !0 = !{i32 1, !"wchar_size", i32 4} diff --git a/llvm/test/Instrumentation/AddressSanitizer/debug-info-alloca.ll b/llvm/test/Instrumentation/AddressSanitizer/debug-info-alloca.ll --- a/llvm/test/Instrumentation/AddressSanitizer/debug-info-alloca.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/debug-info-alloca.ll @@ -14,26 +14,26 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define dso_local i32 @main(i32 %argc, i8** %argv) #0 !dbg !15 { +define dso_local i32 @main(i32 %argc, ptr %argv) #0 !dbg !15 { entry: ; No suffix like !dbg !123 ; CHECK: %asan_local_stack_base = alloca i64, align 8{{$}} ; CHECK: %3 = call i64 @__asan_stack_malloc_0(i64 64){{$}} %argc.addr = alloca i32, align 4 - %argv.addr = alloca i8**, align 8 - store i32 %argc, i32* %argc.addr, align 4 - call void @llvm.dbg.declare(metadata i32* %argc.addr, metadata !21, metadata !DIExpression()), !dbg !22 - store i8** %argv, i8*** %argv.addr, align 8 - call void @llvm.dbg.declare(metadata i8*** %argv.addr, metadata !23, metadata !DIExpression()), !dbg !24 - call void @f(i32* %argc.addr), !dbg !25 + %argv.addr = alloca ptr, align 8 + store i32 %argc, ptr %argc.addr, align 4 + call void @llvm.dbg.declare(metadata ptr %argc.addr, metadata !21, metadata !DIExpression()), !dbg !22 + store ptr %argv, ptr %argv.addr, align 8 + call void @llvm.dbg.declare(metadata ptr %argv.addr, metadata !23, metadata !DIExpression()), !dbg !24 + call void @f(ptr %argc.addr), !dbg !25 ret i32 0, !dbg !26 } -define dso_local void @f(i32* %arg) #0 !dbg !7 { +define dso_local void @f(ptr %arg) #0 !dbg !7 { entry: - %arg.addr = alloca i32*, align 8 - store i32* %arg, i32** %arg.addr, align 8 - call void @llvm.dbg.declare(metadata i32** %arg.addr, metadata !12, metadata !DIExpression()), !dbg !13 + %arg.addr = alloca ptr, align 8 + store ptr %arg, ptr %arg.addr, align 8 + call void @llvm.dbg.declare(metadata ptr %arg.addr, metadata !12, metadata !DIExpression()), !dbg !13 ret void, !dbg !14 } diff --git a/llvm/test/Instrumentation/AddressSanitizer/debug_info.ll b/llvm/test/Instrumentation/AddressSanitizer/debug_info.ll --- a/llvm/test/Instrumentation/AddressSanitizer/debug_info.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/debug_info.ll @@ -13,13 +13,13 @@ entry: %p.addr = alloca i32, align 4 %r = alloca i32, align 4 - store volatile i32 %p, i32* %p.addr, align 4 - call void @llvm.dbg.declare(metadata i32* %p.addr, metadata !17, metadata !DIExpression()), !dbg !18 - call void @llvm.dbg.declare(metadata i32* %r, metadata !19, metadata !DIExpression()), !dbg !21 - %0 = load i32, i32* %p.addr, align 4, !dbg !21 + store volatile i32 %p, ptr %p.addr, align 4 + call void @llvm.dbg.declare(metadata ptr %p.addr, metadata !17, metadata !DIExpression()), !dbg !18 + call void @llvm.dbg.declare(metadata ptr %r, metadata !19, metadata !DIExpression()), !dbg !21 + %0 = load i32, ptr %p.addr, align 4, !dbg !21 %add = add nsw i32 %0, 1, !dbg !21 - store volatile i32 %add, i32* %r, align 4, !dbg !21 - %1 = load i32, i32* %r, align 4, !dbg !22 + store volatile i32 %add, ptr %r, align 4, !dbg !21 + %1 = load i32, ptr %r, align 4, !dbg !22 ret i32 %1, !dbg !22 } @@ -28,8 +28,8 @@ ; Note: these dbg.declares used to contain `ptrtoint` operands. The instruction ; selector would then decline to put the variable in the MachineFunction side ; table. Check that the dbg.declares have `alloca` operands. -; CHECK: call void @llvm.dbg.declare(metadata i8* [[MyAlloca]], metadata ![[ARG_ID:[0-9]+]], metadata !DIExpression(DW_OP_plus_uconst, 32)) -; CHECK: call void @llvm.dbg.declare(metadata i8* [[MyAlloca]], metadata ![[VAR_ID:[0-9]+]], metadata !DIExpression(DW_OP_plus_uconst, 48)) +; CHECK: call void @llvm.dbg.declare(metadata ptr [[MyAlloca]], metadata ![[ARG_ID:[0-9]+]], metadata !DIExpression(DW_OP_plus_uconst, 32)) +; CHECK: call void @llvm.dbg.declare(metadata ptr [[MyAlloca]], metadata ![[VAR_ID:[0-9]+]], metadata !DIExpression(DW_OP_plus_uconst, 48)) declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone diff --git a/llvm/test/Instrumentation/AddressSanitizer/debug_info_noninstrumented_alloca.ll b/llvm/test/Instrumentation/AddressSanitizer/debug_info_noninstrumented_alloca.ll --- a/llvm/test/Instrumentation/AddressSanitizer/debug_info_noninstrumented_alloca.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/debug_info_noninstrumented_alloca.ll @@ -25,7 +25,7 @@ ; Won't be instrumented because of asan-skip-promotable-allocas. %non_instrumented3 = alloca i32, align 4 - %ptr = ptrtoint i32* %instrumented to i32 + %ptr = ptrtoint ptr %instrumented to i32 br label %bb1 bb1: @@ -35,6 +35,6 @@ ; CHECK: entry: ; CHECK: %non_instrumented1 = alloca i32, align 4 ; CHECK: %non_instrumented2 = alloca i32, align 4 -; CHECK: load i32, i32* @__asan_option_detect_stack_use_after_return +; CHECK: load i32, ptr @__asan_option_detect_stack_use_after_return ; CHECK: bb0: ; CHECK: %non_instrumented3 = alloca i32, align 4 diff --git a/llvm/test/Instrumentation/AddressSanitizer/debug_info_noninstrumented_alloca2.ll b/llvm/test/Instrumentation/AddressSanitizer/debug_info_noninstrumented_alloca2.ll --- a/llvm/test/Instrumentation/AddressSanitizer/debug_info_noninstrumented_alloca2.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/debug_info_noninstrumented_alloca2.ll @@ -9,13 +9,13 @@ define i32 @foo() sanitize_address { entry: %non_instrumented1 = alloca i32, align 4 - %t = load i32, i32* %non_instrumented1, align 4 + %t = load i32, ptr %non_instrumented1, align 4 %instrumented = alloca i32, align 4 - %ptr = ptrtoint i32* %instrumented to i32 + %ptr = ptrtoint ptr %instrumented to i32 ret i32 %t } ; CHECK: entry: ; CHECK: %non_instrumented1 = alloca i32, align 4 -; CHECK: load i32, i32* %non_instrumented1 -; CHECK: load i32, i32* @__asan_option_detect_stack_use_after_return +; CHECK: load i32, ptr %non_instrumented1 +; CHECK: load i32, ptr @__asan_option_detect_stack_use_after_return diff --git a/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-globals-linux.ll b/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-globals-linux.ll --- a/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-globals-linux.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-globals-linux.ll @@ -11,9 +11,9 @@ ret void } -@__call_foo = global void ()* @_ZL3foov, section ".preinit_array", align 8 -@__call_foo_2 = global void ()* @_ZL3foov, section ".init_array", align 8 -@__call_foo_3 = global void ()* @_ZL3foov, section ".fini_array", align 8 +@__call_foo = global ptr @_ZL3foov, section ".preinit_array", align 8 +@__call_foo_2 = global ptr @_ZL3foov, section ".init_array", align 8 +@__call_foo_3 = global ptr @_ZL3foov, section ".fini_array", align 8 ; CHECK-NOT: asan_gen{{.*}}__call_foo @@ -21,7 +21,7 @@ define i32 @main() #0 { entry: %retval = alloca i32, align 4 - store i32 0, i32* %retval, align 4 + store i32 0, ptr %retval, align 4 ret i32 0 } diff --git a/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-internal-globals.ll b/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-internal-globals.ll --- a/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-internal-globals.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-internal-globals.ll @@ -8,11 +8,11 @@ define void @_Z3barv() uwtable sanitize_address { entry: %a = alloca i32, align 4 - call void @_Z3fooPi(i32* %a) + call void @_Z3fooPi(ptr %a) ret void } -declare void @_Z3fooPi(i32*) +declare void @_Z3fooPi(ptr) ; We create one global string constant for the stack frame above. ; It should have unnamed_addr and align 1. ; Make sure we don't create any other global constants. diff --git a/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-netbsd-link_set.ll b/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-netbsd-link_set.ll --- a/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-netbsd-link_set.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-netbsd-link_set.ll @@ -8,7 +8,7 @@ @data1 = dso_local global i32 1, align 4 @data2 = dso_local global i32 2, align 4 -@__link_set_test_set_sym_data1 = internal constant i8* bitcast (i32* @data1 to i8*), section "link_set_test_set", align 8 -@__link_set_test_set_sym_data2 = internal constant i8* bitcast (i32* @data2 to i8*), section "link_set_test_set", align 8 -; CHECK: @__link_set_test_set_sym_data1 = internal constant i8*{{.*}}, section "link_set_test_set" -; CHECK-NEXT: @__link_set_test_set_sym_data2 = internal constant i8*{{.*}}, section "link_set_test_set" +@__link_set_test_set_sym_data1 = internal constant ptr @data1, section "link_set_test_set", align 8 +@__link_set_test_set_sym_data2 = internal constant ptr @data2, section "link_set_test_set", align 8 +; CHECK: @__link_set_test_set_sym_data1 = internal constant ptr{{.*}}, section "link_set_test_set" +; CHECK-NEXT: @__link_set_test_set_sym_data2 = internal constant ptr{{.*}}, section "link_set_test_set" diff --git a/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-promotable-allocas.ll b/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-promotable-allocas.ll --- a/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-promotable-allocas.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-promotable-allocas.ll @@ -6,8 +6,8 @@ define i32 @test_promotable_allocas() sanitize_address { entry: ; CHECK: %0 = alloca i32, align 4 -; CHECK: store i32 0, i32* %0, align 4 -; CHECK: %1 = load i32, i32* %0, align 4 +; CHECK: store i32 0, ptr %0, align 4 +; CHECK: %1 = load i32, ptr %0, align 4 ; CHECK: ret i32 %1 ; CHECK-NOT: __asan_stack_malloc_0 @@ -15,7 +15,7 @@ ; CHECK-NOT: call void @__asan_report_store4 %0 = alloca i32, align 4 - store i32 0, i32* %0, align 4 - %1 = load i32, i32* %0, align 4 + store i32 0, ptr %0, align 4 + %1 = load i32, ptr %0, align 4 ret i32 %1 } diff --git a/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-sanitizers.ll b/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-sanitizers.ll --- a/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-sanitizers.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/do-not-instrument-sanitizers.ll @@ -5,11 +5,11 @@ target triple = "x86_64-unknown-linux-gnu" ; Function Attrs: nounwind uwtable -define void @__asan_default_options(i32* %a) sanitize_address { +define void @__asan_default_options(ptr %a) sanitize_address { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 %tmp2 = add i32 %tmp1, 1 - store i32 %tmp2, i32* %a, align 4 + store i32 %tmp2, ptr %a, align 4 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/do-not-touch-comdat-global.ll b/llvm/test/Instrumentation/AddressSanitizer/do-not-touch-comdat-global.ll --- a/llvm/test/Instrumentation/AddressSanitizer/do-not-touch-comdat-global.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/do-not-touch-comdat-global.ll @@ -6,9 +6,9 @@ ; no action should be taken for these globals $global_noinst = comdat largest @aliasee = private unnamed_addr constant [2 x i8] [i8 1, i8 2], comdat($global_noinst) -@global_noinst = unnamed_addr alias [2 x i8], [2 x i8]* @aliasee +@global_noinst = unnamed_addr alias [2 x i8], ptr @aliasee ; CHECK-NOT: {{asan_gen.*global_noinst}} -; CHECK-DAG: @global_noinst = unnamed_addr alias [2 x i8], [2 x i8]* @aliasee +; CHECK-DAG: @global_noinst = unnamed_addr alias [2 x i8], ptr @aliasee @global_inst = private constant [2 x i8] [i8 1, i8 2] ; CHECK-DAG: {{asan_gen.*global_inst}} ; CHECK: @asan.module_ctor diff --git a/llvm/test/Instrumentation/AddressSanitizer/dynamic-shadow-darwin.ll b/llvm/test/Instrumentation/AddressSanitizer/dynamic-shadow-darwin.ll --- a/llvm/test/Instrumentation/AddressSanitizer/dynamic-shadow-darwin.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/dynamic-shadow-darwin.ll @@ -13,18 +13,18 @@ ; // macOS does use dynamic shadow placement on arm64 ; RUN: opt -passes=asan -mtriple=arm64-apple-macosx --data-layout="e-m:o-i64:64-i128:128-n32:64-S128" -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-DYNAMIC -DPTR_SIZE=64 -define i32 @test_load(i32* %a) sanitize_address { +define i32 @test_load(ptr %a) sanitize_address { ; First instrumentation in the function must be to load the dynamic shadow ; address into a local variable. ; CHECK-LABEL: @test_load ; CHECK: entry: -; CHECK-DYNAMIC-NEXT: %[[SHADOW:[^ ]*]] = load i[[PTR_SIZE]], i[[PTR_SIZE]]* @__asan_shadow_memory_dynamic_address +; CHECK-DYNAMIC-NEXT: %[[SHADOW:[^ ]*]] = load i[[PTR_SIZE]], ptr @__asan_shadow_memory_dynamic_address ; CHECK-NONDYNAMIC-NOT: __asan_shadow_memory_dynamic_address ; Shadow address is loaded and added into the whole offset computation. ; CHECK-DYNAMIC: add i[[PTR_SIZE]] %{{.*}}, %[[SHADOW]] entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } diff --git a/llvm/test/Instrumentation/AddressSanitizer/experiment-call.ll b/llvm/test/Instrumentation/AddressSanitizer/experiment-call.ll --- a/llvm/test/Instrumentation/AddressSanitizer/experiment-call.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/experiment-call.ll @@ -4,108 +4,108 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define void @load1(i8* %p) sanitize_address { +define void @load1(ptr %p) sanitize_address { entry: - %t = load i8, i8* %p, align 1 + %t = load i8, ptr %p, align 1 ret void ; CHECK-LABEL: define void @load1 ; CHECK: __asan_exp_load1{{.*}} i32 42 ; CHECK: ret void } -define void @load2(i16* %p) sanitize_address { +define void @load2(ptr %p) sanitize_address { entry: - %t = load i16, i16* %p, align 2 + %t = load i16, ptr %p, align 2 ret void ; CHECK-LABEL: define void @load2 ; CHECK: __asan_exp_load2{{.*}} i32 42 ; CHECK: ret void } -define void @load4(i32* %p) sanitize_address { +define void @load4(ptr %p) sanitize_address { entry: - %t = load i32, i32* %p, align 4 + %t = load i32, ptr %p, align 4 ret void ; CHECK-LABEL: define void @load4 ; CHECK: __asan_exp_load4{{.*}} i32 42 ; CHECK: ret void } -define void @load8(i64* %p) sanitize_address { +define void @load8(ptr %p) sanitize_address { entry: - %t = load i64, i64* %p, align 8 + %t = load i64, ptr %p, align 8 ret void ; CHECK-LABEL: define void @load8 ; CHECK: __asan_exp_load8{{.*}} i32 42 ; CHECK: ret void } -define void @load16(i128* %p) sanitize_address { +define void @load16(ptr %p) sanitize_address { entry: - %t = load i128, i128* %p, align 16 + %t = load i128, ptr %p, align 16 ret void ; CHECK-LABEL: define void @load16 ; CHECK: __asan_exp_load16{{.*}} i32 42 ; CHECK: ret void } -define void @loadN(i48* %p) sanitize_address { +define void @loadN(ptr %p) sanitize_address { entry: - %t = load i48, i48* %p, align 1 + %t = load i48, ptr %p, align 1 ret void ; CHECK-LABEL: define void @loadN ; CHECK: __asan_exp_loadN{{.*}} i32 42 ; CHECK: ret void } -define void @store1(i8* %p) sanitize_address { +define void @store1(ptr %p) sanitize_address { entry: - store i8 1, i8* %p, align 1 + store i8 1, ptr %p, align 1 ret void ; CHECK-LABEL: define void @store1 ; CHECK: __asan_exp_store1{{.*}} i32 42 ; CHECK: ret void } -define void @store2(i16* %p) sanitize_address { +define void @store2(ptr %p) sanitize_address { entry: - store i16 1, i16* %p, align 2 + store i16 1, ptr %p, align 2 ret void ; CHECK-LABEL: define void @store2 ; CHECK: __asan_exp_store2{{.*}} i32 42 ; CHECK: ret void } -define void @store4(i32* %p) sanitize_address { +define void @store4(ptr %p) sanitize_address { entry: - store i32 1, i32* %p, align 4 + store i32 1, ptr %p, align 4 ret void ; CHECK-LABEL: define void @store4 ; CHECK: __asan_exp_store4{{.*}} i32 42 ; CHECK: ret void } -define void @store8(i64* %p) sanitize_address { +define void @store8(ptr %p) sanitize_address { entry: - store i64 1, i64* %p, align 8 + store i64 1, ptr %p, align 8 ret void ; CHECK-LABEL: define void @store8 ; CHECK: __asan_exp_store8{{.*}} i32 42 ; CHECK: ret void } -define void @store16(i128* %p) sanitize_address { +define void @store16(ptr %p) sanitize_address { entry: - store i128 1, i128* %p, align 16 + store i128 1, ptr %p, align 16 ret void ; CHECK-LABEL: define void @store16 ; CHECK: __asan_exp_store16{{.*}} i32 42 ; CHECK: ret void } -define void @storeN(i48* %p) sanitize_address { +define void @storeN(ptr %p) sanitize_address { entry: - store i48 1, i48* %p, align 1 + store i48 1, ptr %p, align 1 ret void ; CHECK-LABEL: define void @storeN ; CHECK: __asan_exp_storeN{{.*}} i32 42 diff --git a/llvm/test/Instrumentation/AddressSanitizer/experiment.ll b/llvm/test/Instrumentation/AddressSanitizer/experiment.ll --- a/llvm/test/Instrumentation/AddressSanitizer/experiment.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/experiment.ll @@ -4,108 +4,108 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define void @load1(i8* %p) sanitize_address { +define void @load1(ptr %p) sanitize_address { entry: - %t = load i8, i8* %p, align 1 + %t = load i8, ptr %p, align 1 ret void ; CHECK-LABEL: define void @load1 ; CHECK: __asan_report_exp_load1{{.*}} i32 42 ; CHECK: ret void } -define void @load2(i16* %p) sanitize_address { +define void @load2(ptr %p) sanitize_address { entry: - %t = load i16, i16* %p, align 2 + %t = load i16, ptr %p, align 2 ret void ; CHECK-LABEL: define void @load2 ; CHECK: __asan_report_exp_load2{{.*}} i32 42 ; CHECK: ret void } -define void @load4(i32* %p) sanitize_address { +define void @load4(ptr %p) sanitize_address { entry: - %t = load i32, i32* %p, align 4 + %t = load i32, ptr %p, align 4 ret void ; CHECK-LABEL: define void @load4 ; CHECK: __asan_report_exp_load4{{.*}} i32 42 ; CHECK: ret void } -define void @load8(i64* %p) sanitize_address { +define void @load8(ptr %p) sanitize_address { entry: - %t = load i64, i64* %p, align 8 + %t = load i64, ptr %p, align 8 ret void ; CHECK-LABEL: define void @load8 ; CHECK: __asan_report_exp_load8{{.*}} i32 42 ; CHECK: ret void } -define void @load16(i128* %p) sanitize_address { +define void @load16(ptr %p) sanitize_address { entry: - %t = load i128, i128* %p, align 16 + %t = load i128, ptr %p, align 16 ret void ; CHECK-LABEL: define void @load16 ; CHECK: __asan_report_exp_load16{{.*}} i32 42 ; CHECK: ret void } -define void @loadN(i48* %p) sanitize_address { +define void @loadN(ptr %p) sanitize_address { entry: - %t = load i48, i48* %p, align 1 + %t = load i48, ptr %p, align 1 ret void ; CHECK-LABEL: define void @loadN ; CHECK: __asan_report_exp_load_n{{.*}} i32 42 ; CHECK: ret void } -define void @store1(i8* %p) sanitize_address { +define void @store1(ptr %p) sanitize_address { entry: - store i8 1, i8* %p, align 1 + store i8 1, ptr %p, align 1 ret void ; CHECK-LABEL: define void @store1 ; CHECK: __asan_report_exp_store1{{.*}} i32 42 ; CHECK: ret void } -define void @store2(i16* %p) sanitize_address { +define void @store2(ptr %p) sanitize_address { entry: - store i16 1, i16* %p, align 2 + store i16 1, ptr %p, align 2 ret void ; CHECK-LABEL: define void @store2 ; CHECK: __asan_report_exp_store2{{.*}} i32 42 ; CHECK: ret void } -define void @store4(i32* %p) sanitize_address { +define void @store4(ptr %p) sanitize_address { entry: - store i32 1, i32* %p, align 4 + store i32 1, ptr %p, align 4 ret void ; CHECK-LABEL: define void @store4 ; CHECK: __asan_report_exp_store4{{.*}} i32 42 ; CHECK: ret void } -define void @store8(i64* %p) sanitize_address { +define void @store8(ptr %p) sanitize_address { entry: - store i64 1, i64* %p, align 8 + store i64 1, ptr %p, align 8 ret void ; CHECK-LABEL: define void @store8 ; CHECK: __asan_report_exp_store8{{.*}} i32 42 ; CHECK: ret void } -define void @store16(i128* %p) sanitize_address { +define void @store16(ptr %p) sanitize_address { entry: - store i128 1, i128* %p, align 16 + store i128 1, ptr %p, align 16 ret void ; CHECK-LABEL: define void @store16 ; CHECK: __asan_report_exp_store16{{.*}} i32 42 ; CHECK: ret void } -define void @storeN(i48* %p) sanitize_address { +define void @storeN(ptr %p) sanitize_address { entry: - store i48 1, i48* %p, align 1 + store i48 1, ptr %p, align 1 ret void ; CHECK-LABEL: define void @storeN ; CHECK: __asan_report_exp_store_n{{.*}} i32 42 diff --git a/llvm/test/Instrumentation/AddressSanitizer/fake-stack.ll b/llvm/test/Instrumentation/AddressSanitizer/fake-stack.ll --- a/llvm/test/Instrumentation/AddressSanitizer/fake-stack.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/fake-stack.ll @@ -5,7 +5,7 @@ target datalayout = "e-i64:64-f80:128-s:64-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare void @Foo(i8*) +declare void @Foo(ptr) define void @Empty() uwtable sanitize_address { ; CHECK-LABEL: @Empty( @@ -20,33 +20,33 @@ ; NEVER-LABEL: @Simple( ; NEVER-NEXT: entry: ; NEVER-NEXT: [[MYALLOCA:%.*]] = alloca i8, i64 64, align 32 -; NEVER-NEXT: [[TMP0:%.*]] = ptrtoint i8* [[MYALLOCA]] to i64 +; NEVER-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[MYALLOCA]] to i64 ; NEVER-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 32 -; NEVER-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to i8* -; NEVER-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP0]] to i64* -; NEVER-NEXT: store i64 1102416563, i64* [[TMP3]], align 8 +; NEVER-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr +; NEVER-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP0]] to ptr +; NEVER-NEXT: store i64 1102416563, ptr [[TMP3]], align 8 ; NEVER-NEXT: [[TMP4:%.*]] = add i64 [[TMP0]], 8 -; NEVER-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i64* -; NEVER-NEXT: store i64 ptrtoint ([11 x i8]* @___asan_gen_ to i64), i64* [[TMP5]], align 8 +; NEVER-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr +; NEVER-NEXT: store i64 ptrtoint (ptr @___asan_gen_ to i64), ptr [[TMP5]], align 8 ; NEVER-NEXT: [[TMP6:%.*]] = add i64 [[TMP0]], 16 -; NEVER-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i64* -; NEVER-NEXT: store i64 ptrtoint (void ()* @Simple to i64), i64* [[TMP7]], align 8 +; NEVER-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; NEVER-NEXT: store i64 ptrtoint (ptr @Simple to i64), ptr [[TMP7]], align 8 ; NEVER-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP0]], 3 ; NEVER-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 2147450880 ; NEVER-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 0 -; NEVER-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to i64* -; NEVER-NEXT: store i64 -868083113472691727, i64* [[TMP11]], align 1 -; NEVER-NEXT: call void @Foo(i8* [[TMP2]]) -; NEVER-NEXT: store i64 1172321806, i64* [[TMP3]], align 8 +; NEVER-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr +; NEVER-NEXT: store i64 -868083113472691727, ptr [[TMP11]], align 1 +; NEVER-NEXT: call void @Foo(ptr [[TMP2]]) +; NEVER-NEXT: store i64 1172321806, ptr [[TMP3]], align 8 ; NEVER-NEXT: [[TMP12:%.*]] = add i64 [[TMP9]], 0 -; NEVER-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to i64* -; NEVER-NEXT: store i64 0, i64* [[TMP13]], align 1 +; NEVER-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr +; NEVER-NEXT: store i64 0, ptr [[TMP13]], align 1 ; NEVER-NEXT: ret void ; ; RUNTIME-LABEL: @Simple( ; RUNTIME-NEXT: entry: ; RUNTIME-NEXT: [[ASAN_LOCAL_STACK_BASE:%.*]] = alloca i64, align 8 -; RUNTIME-NEXT: [[TMP0:%.*]] = load i32, i32* @__asan_option_detect_stack_use_after_return, align 4 +; RUNTIME-NEXT: [[TMP0:%.*]] = load i32, ptr @__asan_option_detect_stack_use_after_return, align 4 ; RUNTIME-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 ; RUNTIME-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP4:%.*]] ; RUNTIME: 2: @@ -58,44 +58,44 @@ ; RUNTIME-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP9:%.*]] ; RUNTIME: 7: ; RUNTIME-NEXT: [[MYALLOCA:%.*]] = alloca i8, i64 64, align 32 -; RUNTIME-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[MYALLOCA]] to i64 +; RUNTIME-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[MYALLOCA]] to i64 ; RUNTIME-NEXT: br label [[TMP9]] ; RUNTIME: 9: ; RUNTIME-NEXT: [[TMP10:%.*]] = phi i64 [ [[TMP5]], [[TMP4]] ], [ [[TMP8]], [[TMP7]] ] -; RUNTIME-NEXT: store i64 [[TMP10]], i64* [[ASAN_LOCAL_STACK_BASE]], align 8 +; RUNTIME-NEXT: store i64 [[TMP10]], ptr [[ASAN_LOCAL_STACK_BASE]], align 8 ; RUNTIME-NEXT: [[TMP11:%.*]] = add i64 [[TMP10]], 32 -; RUNTIME-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to i8* -; RUNTIME-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP10]] to i64* -; RUNTIME-NEXT: store i64 1102416563, i64* [[TMP13]], align 8 +; RUNTIME-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr +; RUNTIME-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP10]] to ptr +; RUNTIME-NEXT: store i64 1102416563, ptr [[TMP13]], align 8 ; RUNTIME-NEXT: [[TMP14:%.*]] = add i64 [[TMP10]], 8 -; RUNTIME-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to i64* -; RUNTIME-NEXT: store i64 ptrtoint ([11 x i8]* @___asan_gen_ to i64), i64* [[TMP15]], align 8 +; RUNTIME-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr +; RUNTIME-NEXT: store i64 ptrtoint (ptr @___asan_gen_ to i64), ptr [[TMP15]], align 8 ; RUNTIME-NEXT: [[TMP16:%.*]] = add i64 [[TMP10]], 16 -; RUNTIME-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to i64* -; RUNTIME-NEXT: store i64 ptrtoint (void ()* @Simple to i64), i64* [[TMP17]], align 8 +; RUNTIME-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to ptr +; RUNTIME-NEXT: store i64 ptrtoint (ptr @Simple to i64), ptr [[TMP17]], align 8 ; RUNTIME-NEXT: [[TMP18:%.*]] = lshr i64 [[TMP10]], 3 ; RUNTIME-NEXT: [[TMP19:%.*]] = add i64 [[TMP18]], 2147450880 ; RUNTIME-NEXT: [[TMP20:%.*]] = add i64 [[TMP19]], 0 -; RUNTIME-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP20]] to i64* -; RUNTIME-NEXT: store i64 -868083113472691727, i64* [[TMP21]], align 1 -; RUNTIME-NEXT: call void @Foo(i8* [[TMP12]]) -; RUNTIME-NEXT: store i64 1172321806, i64* [[TMP13]], align 8 +; RUNTIME-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP20]] to ptr +; RUNTIME-NEXT: store i64 -868083113472691727, ptr [[TMP21]], align 1 +; RUNTIME-NEXT: call void @Foo(ptr [[TMP12]]) +; RUNTIME-NEXT: store i64 1172321806, ptr [[TMP13]], align 8 ; RUNTIME-NEXT: [[TMP22:%.*]] = icmp ne i64 [[TMP5]], 0 ; RUNTIME-NEXT: br i1 [[TMP22]], label [[TMP23:%.*]], label [[TMP30:%.*]] ; RUNTIME: 23: ; RUNTIME-NEXT: [[TMP24:%.*]] = add i64 [[TMP19]], 0 -; RUNTIME-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP24]] to i64* -; RUNTIME-NEXT: store i64 -723401728380766731, i64* [[TMP25]], align 1 +; RUNTIME-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP24]] to ptr +; RUNTIME-NEXT: store i64 -723401728380766731, ptr [[TMP25]], align 1 ; RUNTIME-NEXT: [[TMP26:%.*]] = add i64 [[TMP5]], 56 -; RUNTIME-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP26]] to i64* -; RUNTIME-NEXT: [[TMP28:%.*]] = load i64, i64* [[TMP27]], align 8 -; RUNTIME-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP28]] to i8* -; RUNTIME-NEXT: store i8 0, i8* [[TMP29]], align 1 +; RUNTIME-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP26]] to ptr +; RUNTIME-NEXT: [[TMP28:%.*]] = load i64, ptr [[TMP27]], align 8 +; RUNTIME-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP28]] to ptr +; RUNTIME-NEXT: store i8 0, ptr [[TMP29]], align 1 ; RUNTIME-NEXT: br label [[TMP33:%.*]] ; RUNTIME: 30: ; RUNTIME-NEXT: [[TMP31:%.*]] = add i64 [[TMP19]], 0 -; RUNTIME-NEXT: [[TMP32:%.*]] = inttoptr i64 [[TMP31]] to i64* -; RUNTIME-NEXT: store i64 0, i64* [[TMP32]], align 1 +; RUNTIME-NEXT: [[TMP32:%.*]] = inttoptr i64 [[TMP31]] to ptr +; RUNTIME-NEXT: store i64 0, ptr [[TMP32]], align 1 ; RUNTIME-NEXT: br label [[TMP33]] ; RUNTIME: 33: ; RUNTIME-NEXT: ret void @@ -108,51 +108,51 @@ ; ALWAYS-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP4:%.*]] ; ALWAYS: 2: ; ALWAYS-NEXT: [[MYALLOCA:%.*]] = alloca i8, i64 64, align 32 -; ALWAYS-NEXT: [[TMP3:%.*]] = ptrtoint i8* [[MYALLOCA]] to i64 +; ALWAYS-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[MYALLOCA]] to i64 ; ALWAYS-NEXT: br label [[TMP4]] ; ALWAYS: 4: ; ALWAYS-NEXT: [[TMP5:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP3]], [[TMP2]] ] -; ALWAYS-NEXT: store i64 [[TMP5]], i64* [[ASAN_LOCAL_STACK_BASE]], align 8 +; ALWAYS-NEXT: store i64 [[TMP5]], ptr [[ASAN_LOCAL_STACK_BASE]], align 8 ; ALWAYS-NEXT: [[TMP6:%.*]] = add i64 [[TMP5]], 32 -; ALWAYS-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i8* -; ALWAYS-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP5]] to i64* -; ALWAYS-NEXT: store i64 1102416563, i64* [[TMP8]], align 8 +; ALWAYS-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; ALWAYS-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP5]] to ptr +; ALWAYS-NEXT: store i64 1102416563, ptr [[TMP8]], align 8 ; ALWAYS-NEXT: [[TMP9:%.*]] = add i64 [[TMP5]], 8 -; ALWAYS-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to i64* -; ALWAYS-NEXT: store i64 ptrtoint ([11 x i8]* @___asan_gen_ to i64), i64* [[TMP10]], align 8 +; ALWAYS-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr +; ALWAYS-NEXT: store i64 ptrtoint (ptr @___asan_gen_ to i64), ptr [[TMP10]], align 8 ; ALWAYS-NEXT: [[TMP11:%.*]] = add i64 [[TMP5]], 16 -; ALWAYS-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to i64* -; ALWAYS-NEXT: store i64 ptrtoint (void ()* @Simple to i64), i64* [[TMP12]], align 8 +; ALWAYS-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr +; ALWAYS-NEXT: store i64 ptrtoint (ptr @Simple to i64), ptr [[TMP12]], align 8 ; ALWAYS-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP5]], 3 ; ALWAYS-NEXT: [[TMP14:%.*]] = add i64 [[TMP13]], 2147450880 ; ALWAYS-NEXT: [[TMP15:%.*]] = add i64 [[TMP14]], 0 -; ALWAYS-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP15]] to i64* -; ALWAYS-NEXT: store i64 -868083113472691727, i64* [[TMP16]], align 1 -; ALWAYS-NEXT: call void @Foo(i8* [[TMP7]]) -; ALWAYS-NEXT: store i64 1172321806, i64* [[TMP8]], align 8 +; ALWAYS-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP15]] to ptr +; ALWAYS-NEXT: store i64 -868083113472691727, ptr [[TMP16]], align 1 +; ALWAYS-NEXT: call void @Foo(ptr [[TMP7]]) +; ALWAYS-NEXT: store i64 1172321806, ptr [[TMP8]], align 8 ; ALWAYS-NEXT: [[TMP17:%.*]] = icmp ne i64 [[TMP0]], 0 ; ALWAYS-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP25:%.*]] ; ALWAYS: 18: ; ALWAYS-NEXT: [[TMP19:%.*]] = add i64 [[TMP14]], 0 -; ALWAYS-NEXT: [[TMP20:%.*]] = inttoptr i64 [[TMP19]] to i64* -; ALWAYS-NEXT: store i64 -723401728380766731, i64* [[TMP20]], align 1 +; ALWAYS-NEXT: [[TMP20:%.*]] = inttoptr i64 [[TMP19]] to ptr +; ALWAYS-NEXT: store i64 -723401728380766731, ptr [[TMP20]], align 1 ; ALWAYS-NEXT: [[TMP21:%.*]] = add i64 [[TMP0]], 56 -; ALWAYS-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to i64* -; ALWAYS-NEXT: [[TMP23:%.*]] = load i64, i64* [[TMP22]], align 8 -; ALWAYS-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP23]] to i8* -; ALWAYS-NEXT: store i8 0, i8* [[TMP24]], align 1 +; ALWAYS-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to ptr +; ALWAYS-NEXT: [[TMP23:%.*]] = load i64, ptr [[TMP22]], align 8 +; ALWAYS-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP23]] to ptr +; ALWAYS-NEXT: store i8 0, ptr [[TMP24]], align 1 ; ALWAYS-NEXT: br label [[TMP28:%.*]] ; ALWAYS: 25: ; ALWAYS-NEXT: [[TMP26:%.*]] = add i64 [[TMP14]], 0 -; ALWAYS-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP26]] to i64* -; ALWAYS-NEXT: store i64 0, i64* [[TMP27]], align 1 +; ALWAYS-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP26]] to ptr +; ALWAYS-NEXT: store i64 0, ptr [[TMP27]], align 1 ; ALWAYS-NEXT: br label [[TMP28]] ; ALWAYS: 28: ; ALWAYS-NEXT: ret void ; entry: %x = alloca i8, align 16 - call void @Foo(i8* %x) + call void @Foo(ptr %x) ret void } @@ -160,57 +160,55 @@ ; CHECK-LABEL: @Huge( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[MYALLOCA:%.*]] = alloca i8, i64 100288, align 32 -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i8* [[MYALLOCA]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[MYALLOCA]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 32 -; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to [100000 x i8]* -; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP0]] to i64* -; CHECK-NEXT: store i64 1102416563, i64* [[TMP3]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr +; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP0]] to ptr +; CHECK-NEXT: store i64 1102416563, ptr [[TMP3]], align 8 ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP0]], 8 -; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i64* -; CHECK-NEXT: store i64 ptrtoint ([16 x i8]* @___asan_gen_.1 to i64), i64* [[TMP5]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr +; CHECK-NEXT: store i64 ptrtoint (ptr @___asan_gen_.1 to i64), ptr [[TMP5]], align 8 ; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP0]], 16 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i64* -; CHECK-NEXT: store i64 ptrtoint (void ()* @Huge to i64), i64* [[TMP7]], align 8 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: store i64 ptrtoint (ptr @Huge to i64), ptr [[TMP7]], align 8 ; CHECK-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP0]], 3 ; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 2147450880 ; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 0 -; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to i32* -; CHECK-NEXT: store i32 -235802127, i32* [[TMP11]], align 1 +; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr +; CHECK-NEXT: store i32 -235802127, ptr [[TMP11]], align 1 ; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP9]], 12504 -; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to i64* -; CHECK-NEXT: store i64 -868082074056920077, i64* [[TMP13]], align 1 +; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr +; CHECK-NEXT: store i64 -868082074056920077, ptr [[TMP13]], align 1 ; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP9]], 12512 -; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to i64* -; CHECK-NEXT: store i64 -868082074056920077, i64* [[TMP15]], align 1 +; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr +; CHECK-NEXT: store i64 -868082074056920077, ptr [[TMP15]], align 1 ; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP9]], 12520 -; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to i64* -; CHECK-NEXT: store i64 -868082074056920077, i64* [[TMP17]], align 1 +; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to ptr +; CHECK-NEXT: store i64 -868082074056920077, ptr [[TMP17]], align 1 ; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[TMP9]], 12528 -; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to i64* -; CHECK-NEXT: store i64 -868082074056920077, i64* [[TMP19]], align 1 -; CHECK-NEXT: [[XX:%.*]] = getelementptr inbounds [100000 x i8], [100000 x i8]* [[TMP2]], i64 0, i64 0 -; CHECK-NEXT: call void @Foo(i8* [[XX]]) -; CHECK-NEXT: store i64 1172321806, i64* [[TMP3]], align 8 +; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr +; CHECK-NEXT: store i64 -868082074056920077, ptr [[TMP19]], align 1 +; CHECK-NEXT: call void @Foo(ptr [[TMP2]]) +; CHECK-NEXT: store i64 1172321806, ptr [[TMP3]], align 8 ; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[TMP9]], 0 -; CHECK-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP20]] to i32* -; CHECK-NEXT: store i32 0, i32* [[TMP21]], align 1 +; CHECK-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP20]] to ptr +; CHECK-NEXT: store i32 0, ptr [[TMP21]], align 1 ; CHECK-NEXT: [[TMP22:%.*]] = add i64 [[TMP9]], 12504 -; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to i64* -; CHECK-NEXT: store i64 0, i64* [[TMP23]], align 1 +; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr +; CHECK-NEXT: store i64 0, ptr [[TMP23]], align 1 ; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP9]], 12512 -; CHECK-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP24]] to i64* -; CHECK-NEXT: store i64 0, i64* [[TMP25]], align 1 +; CHECK-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP24]] to ptr +; CHECK-NEXT: store i64 0, ptr [[TMP25]], align 1 ; CHECK-NEXT: [[TMP26:%.*]] = add i64 [[TMP9]], 12520 -; CHECK-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP26]] to i64* -; CHECK-NEXT: store i64 0, i64* [[TMP27]], align 1 +; CHECK-NEXT: [[TMP27:%.*]] = inttoptr i64 [[TMP26]] to ptr +; CHECK-NEXT: store i64 0, ptr [[TMP27]], align 1 ; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP9]], 12528 -; CHECK-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP28]] to i64* -; CHECK-NEXT: store i64 0, i64* [[TMP29]], align 1 +; CHECK-NEXT: [[TMP29:%.*]] = inttoptr i64 [[TMP28]] to ptr +; CHECK-NEXT: store i64 0, ptr [[TMP29]], align 1 ; CHECK-NEXT: ret void ; entry: %x = alloca [100000 x i8], align 16 - %xx = getelementptr inbounds [100000 x i8], [100000 x i8]* %x, i64 0, i64 0 - call void @Foo(i8* %xx) + call void @Foo(ptr %x) ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/force-dynamic-shadow.ll b/llvm/test/Instrumentation/AddressSanitizer/force-dynamic-shadow.ll --- a/llvm/test/Instrumentation/AddressSanitizer/force-dynamic-shadow.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/force-dynamic-shadow.ll @@ -5,18 +5,18 @@ target triple = "x86_64-unknown-linux-gnu" -define i32 @test_load(i32* %a) sanitize_address { +define i32 @test_load(ptr %a) sanitize_address { ; First instrumentation in the function must be to load the dynamic shadow ; address into a local variable. ; CHECK-LABEL: @test_load ; CHECK: entry: -; CHECK-FDS-NEXT: %[[SHADOW:[^ ]*]] = load i64, i64* @__asan_shadow_memory_dynamic_address +; CHECK-FDS-NEXT: %[[SHADOW:[^ ]*]] = load i64, ptr @__asan_shadow_memory_dynamic_address ; CHECK-NDS-NOT: __asan_shadow_memory_dynamic_address ; Shadow address is loaded and added into the whole offset computation. ; CHECK-FDS: add i64 %{{.*}}, %[[SHADOW]] entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } diff --git a/llvm/test/Instrumentation/AddressSanitizer/freebsd.ll b/llvm/test/Instrumentation/AddressSanitizer/freebsd.ll --- a/llvm/test/Instrumentation/AddressSanitizer/freebsd.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/freebsd.ll @@ -18,9 +18,9 @@ ; RUN: -data-layout="E-m:e-i64:64-n32:64-S128" | \ ; RUN: FileCheck --check-prefix=CHECK-MIPS64 %s -define i32 @read_4_bytes(i32* %a) sanitize_address { +define i32 @read_4_bytes(ptr %a) sanitize_address { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } diff --git a/llvm/test/Instrumentation/AddressSanitizer/global_addrspace.ll b/llvm/test/Instrumentation/AddressSanitizer/global_addrspace.ll --- a/llvm/test/Instrumentation/AddressSanitizer/global_addrspace.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/global_addrspace.ll @@ -13,8 +13,8 @@ define void @b(i32 %c) { entry: %conv = sext i32 %c to i64 - %0 = inttoptr i64 %conv to i32 addrspace(42)* - %cmp = icmp ugt i32 addrspace(42)* %0, getelementptr inbounds ([1 x i32], [1 x i32] addrspace(42)* @a, i64 0, i64 0) + %0 = inttoptr i64 %conv to ptr addrspace(42) + %cmp = icmp ugt ptr addrspace(42) %0, @a br i1 %cmp, label %if.then, label %if.end if.then: @@ -28,4 +28,4 @@ declare i32 @e(...) !llvm.asan.globals = !{!0} -!0 = !{[1 x i32] addrspace(42)* @a, null, !"a", i1 false, i1 false} +!0 = !{ptr addrspace(42) @a, null, !"a", i1 false, i1 false} diff --git a/llvm/test/Instrumentation/AddressSanitizer/global_lto_merge.ll b/llvm/test/Instrumentation/AddressSanitizer/global_lto_merge.ll --- a/llvm/test/Instrumentation/AddressSanitizer/global_lto_merge.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/global_lto_merge.ll @@ -13,18 +13,16 @@ ; CHECK: @b = {{.*}} %struct ; CHECK: @llvm.compiler.used = -; CHECK-SAME: i8* bitcast ({ %struct, [16 x i8] }* @a to i8*) -; CHECK-SAME: i8* bitcast ({ %struct, [16 x i8] }* @b to i8*) +; CHECK-SAME: ptr @a +; CHECK-SAME: ptr @b -define i32 @main(i32, i8** nocapture readnone) { +define i32 @main(i32, ptr nocapture readnone) { %3 = alloca %struct, align 8 %4 = alloca %struct, align 8 - %5 = bitcast %struct* %3 to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull %5, i8* bitcast (%struct* @a to i8*), i64 16, i32 8, i1 false) - %6 = bitcast %struct* %4 to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* nonnull %6, i8* bitcast (%struct* @b to i8*), i64 16, i32 8, i1 false) - call void asm sideeffect "", "r,r,~{dirflag},~{fpsr},~{flags}"(%struct* nonnull %3, %struct* nonnull %4) + call void @llvm.memcpy.p0.p0.i64(ptr nonnull %3, ptr @a, i64 16, i32 8, i1 false) + call void @llvm.memcpy.p0.p0.i64(ptr nonnull %4, ptr @b, i64 16, i32 8, i1 false) + call void asm sideeffect "", "r,r,~{dirflag},~{fpsr},~{flags}"(ptr nonnull %3, ptr nonnull %4) ret i32 0 } -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32, i1) +declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32, i1) diff --git a/llvm/test/Instrumentation/AddressSanitizer/global_metadata_array.ll b/llvm/test/Instrumentation/AddressSanitizer/global_metadata_array.ll --- a/llvm/test/Instrumentation/AddressSanitizer/global_metadata_array.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/global_metadata_array.ll @@ -11,7 +11,7 @@ @blocked_global = global i32 0, align 4 @_ZZ4funcvE10static_var = internal global i32 0, align 4 @.str = private unnamed_addr constant [14 x i8] c"Hello, world!\00", align 1 -@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @_GLOBAL__sub_I_asan_globals.cpp, i8* null }] +@llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @_GLOBAL__sub_I_asan_globals.cpp, ptr null }] ; Check that globals were instrumented: ; CHECK: @global = global { i32, [28 x i8] } zeroinitializer, align 32 @@ -21,23 +21,23 @@ ; CHECK: [[VARNAME:@___asan_gen_.[0-9]+]] = private unnamed_addr constant [7 x i8] c"global\00", align 1 ; Check that location descriptors and global names were passed into __asan_register_globals: -; CHECK: i64 ptrtoint ([7 x i8]* [[VARNAME]] to i64) +; CHECK: i64 ptrtoint (ptr [[VARNAME]] to i64) ; Check alignment of metadata_array. ; CHECK-S5-SAME: {{align 32$}} ; Function Attrs: nounwind sanitize_address define internal void @__cxx_global_var_init() #0 section ".text.startup" { entry: - %0 = load i32, i32* @global, align 4 - store i32 %0, i32* @dyn_init_global, align 4 + %0 = load i32, ptr @global, align 4 + store i32 %0, ptr @dyn_init_global, align 4 ret void } ; Function Attrs: nounwind sanitize_address define void @_Z4funcv() #1 { entry: - %literal = alloca i8*, align 8 - store i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str, i32 0, i32 0), i8** %literal, align 8 + %literal = alloca ptr, align 8 + store ptr @.str, ptr %literal, align 8 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/global_metadata_bitcasts.ll b/llvm/test/Instrumentation/AddressSanitizer/global_metadata_bitcasts.ll --- a/llvm/test/Instrumentation/AddressSanitizer/global_metadata_bitcasts.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/global_metadata_bitcasts.ll @@ -9,5 +9,5 @@ @g = global [1 x i32] zeroinitializer, align 4 !llvm.asan.globals = !{!0, !1} -!0 = !{[1 x i32]* @g, null, !"name", i1 false, i1 false} -!1 = !{i8* bitcast ([1 x i32]* @g to i8*), null, !"name", i1 false, i1 false} +!0 = !{ptr @g, null, !"name", i1 false, i1 false} +!1 = !{ptr @g, null, !"name", i1 false, i1 false} diff --git a/llvm/test/Instrumentation/AddressSanitizer/global_metadata_windows.ll b/llvm/test/Instrumentation/AddressSanitizer/global_metadata_windows.ll --- a/llvm/test/Instrumentation/AddressSanitizer/global_metadata_windows.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/global_metadata_windows.ll @@ -20,7 +20,7 @@ ; CHECK: @__asan_global_dead_global = private global { {{.*}} }, section ".ASAN$GL", comdat($dead_global), align 64, !associated ; CHECK: @__asan_global_private_str = private global { {{.*}} }, section ".ASAN$GL", comdat($private_str), align 64, !associated -; CHECK: @llvm.compiler.used {{.*}} @__asan_global_dead_global {{.*}} @__asan_global_private_str {{.*}} section "llvm.metadata" +; CHECK: @llvm.compiler.used = appending global [6 x ptr] [ptr @dead_global, ptr @mystr, ptr @private_str, ptr @__asan_global_dead_global, ptr @__asan_global_mystr, ptr @__asan_global_private_str], section "llvm.metadata" @dead_global = local_unnamed_addr global i32 42, align 4 @mystr = linkonce_odr unnamed_addr constant [5 x i8] c"main\00", comdat, align 1 @@ -31,13 +31,13 @@ ; Function Attrs: nounwind uwtable define i32 @main() local_unnamed_addr #0 { entry: - %call = tail call i32 @puts(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @mystr, i64 0, i64 0)) - %call2 = tail call i32 @puts(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @private_str, i64 0, i64 0)) + %call = tail call i32 @puts(ptr @mystr) + %call2 = tail call i32 @puts(ptr @private_str) ret i32 0 } ; Function Attrs: nounwind -declare i32 @puts(i8* nocapture readonly) local_unnamed_addr #1 +declare i32 @puts(ptr nocapture readonly) local_unnamed_addr #1 attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/Instrumentation/AddressSanitizer/hoist-argument-init-insts.ll b/llvm/test/Instrumentation/AddressSanitizer/hoist-argument-init-insts.ll --- a/llvm/test/Instrumentation/AddressSanitizer/hoist-argument-init-insts.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/hoist-argument-init-insts.ll @@ -18,27 +18,27 @@ ; CHECK-LABEL: define {{.*}} @_Z4swapP1SS0_b( ; First come the argument allocas. -; CHECK: [[argA:%.*]] = alloca %struct.S*, -; CHECK-NEXT: [[argB:%.*]] = alloca %struct.S*, +; CHECK: [[argA:%.*]] = alloca ptr, +; CHECK-NEXT: [[argB:%.*]] = alloca ptr, ; CHECK-NEXT: [[argDoit:%.*]] = alloca i8, ; Next, the stores into the argument allocas. -; CHECK-NEXT: store %struct.S* {{.*}}, %struct.S** [[argA]] -; CHECK-NEXT: store %struct.S* {{.*}}, %struct.S** [[argB]] +; CHECK-NEXT: store ptr {{.*}}, ptr [[argA]] +; CHECK-NEXT: store ptr {{.*}}, ptr [[argB]] ; CHECK-NEXT: [[frombool:%.*]] = zext i1 {{.*}} to i8 -; CHECK-NEXT: store i8 [[frombool]], i8* [[argDoit]] +; CHECK-NEXT: store i8 [[frombool]], ptr [[argDoit]] -define void @_Z4swapP1SS0_b(%struct.S* %a, %struct.S* %b, i1 zeroext %doit) sanitize_address { +define void @_Z4swapP1SS0_b(ptr %a, ptr %b, i1 zeroext %doit) sanitize_address { entry: - %a.addr = alloca %struct.S*, align 8 - %b.addr = alloca %struct.S*, align 8 + %a.addr = alloca ptr, align 8 + %b.addr = alloca ptr, align 8 %doit.addr = alloca i8, align 1 %tmp = alloca %struct.S, align 4 - store %struct.S* %a, %struct.S** %a.addr, align 8 - store %struct.S* %b, %struct.S** %b.addr, align 8 + store ptr %a, ptr %a.addr, align 8 + store ptr %b, ptr %b.addr, align 8 %frombool = zext i1 %doit to i8 - store i8 %frombool, i8* %doit.addr, align 1 - %0 = load i8, i8* %doit.addr, align 1 + store i8 %frombool, ptr %doit.addr, align 1 + %0 = load i8, ptr %doit.addr, align 1 %tobool = trunc i8 %0 to i1 br i1 %tobool, label %if.end, label %if.then @@ -46,19 +46,13 @@ br label %return if.end: ; preds = %entry - %1 = load %struct.S*, %struct.S** %a.addr, align 8 - %2 = bitcast %struct.S* %tmp to i8* - %3 = bitcast %struct.S* %1 to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %2, i8* align 4 %3, i64 8, i1 false) - %4 = load %struct.S*, %struct.S** %b.addr, align 8 - %5 = load %struct.S*, %struct.S** %a.addr, align 8 - %6 = bitcast %struct.S* %5 to i8* - %7 = bitcast %struct.S* %4 to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %6, i8* align 4 %7, i64 8, i1 false) - %8 = load %struct.S*, %struct.S** %b.addr, align 8 - %9 = bitcast %struct.S* %8 to i8* - %10 = bitcast %struct.S* %tmp to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %9, i8* align 4 %10, i64 8, i1 false) + %1 = load ptr, ptr %a.addr, align 8 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %tmp, ptr align 4 %1, i64 8, i1 false) + %2 = load ptr, ptr %b.addr, align 8 + %3 = load ptr, ptr %a.addr, align 8 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %3, ptr align 4 %2, i64 8, i1 false) + %4 = load ptr, ptr %b.addr, align 8 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %4, ptr align 4 %tmp, i64 8, i1 false) br label %return return: ; preds = %if.end, %if.then @@ -68,26 +62,26 @@ ; Synthetic test case, meant to check that we do not reorder instructions past ; a load when attempting to hoist argument init insts. ; CHECK-LABEL: define {{.*}} @func_with_load_in_arginit_sequence -; CHECK: [[argA:%.*]] = alloca %struct.S*, -; CHECK-NEXT: [[argB:%.*]] = alloca %struct.S*, +; CHECK: [[argA:%.*]] = alloca ptr, +; CHECK-NEXT: [[argB:%.*]] = alloca ptr, ; CHECK-NEXT: [[argDoit:%.*]] = alloca i8, -; CHECK-NEXT: store %struct.S* {{.*}}, %struct.S** [[argA]] -; CHECK-NEXT: store %struct.S* {{.*}}, %struct.S** [[argB]] +; CHECK-NEXT: store ptr {{.*}}, ptr [[argA]] +; CHECK-NEXT: store ptr {{.*}}, ptr [[argB]] ; CHECK-NEXT: [[stack_base:%.*]] = alloca i64 -define void @func_with_load_in_arginit_sequence(%struct.S* %a, %struct.S* %b, i1 zeroext %doit) sanitize_address { +define void @func_with_load_in_arginit_sequence(ptr %a, ptr %b, i1 zeroext %doit) sanitize_address { entry: - %a.addr = alloca %struct.S*, align 8 - %b.addr = alloca %struct.S*, align 8 + %a.addr = alloca ptr, align 8 + %b.addr = alloca ptr, align 8 %doit.addr = alloca i8, align 1 %tmp = alloca %struct.S, align 4 - store %struct.S* %a, %struct.S** %a.addr, align 8 - store %struct.S* %b, %struct.S** %b.addr, align 8 + store ptr %a, ptr %a.addr, align 8 + store ptr %b, ptr %b.addr, align 8 ; This load prevents the next argument init sequence from being moved. - %0 = load i8, i8* %doit.addr, align 1 + %0 = load i8, ptr %doit.addr, align 1 %frombool = zext i1 %doit to i8 - store i8 %frombool, i8* %doit.addr, align 1 + store i8 %frombool, ptr %doit.addr, align 1 %tobool = trunc i8 %0 to i1 br i1 %tobool, label %if.end, label %if.then @@ -95,19 +89,13 @@ br label %return if.end: ; preds = %entry - %1 = load %struct.S*, %struct.S** %a.addr, align 8 - %2 = bitcast %struct.S* %tmp to i8* - %3 = bitcast %struct.S* %1 to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %2, i8* align 4 %3, i64 8, i1 false) - %4 = load %struct.S*, %struct.S** %b.addr, align 8 - %5 = load %struct.S*, %struct.S** %a.addr, align 8 - %6 = bitcast %struct.S* %5 to i8* - %7 = bitcast %struct.S* %4 to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %6, i8* align 4 %7, i64 8, i1 false) - %8 = load %struct.S*, %struct.S** %b.addr, align 8 - %9 = bitcast %struct.S* %8 to i8* - %10 = bitcast %struct.S* %tmp to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %9, i8* align 4 %10, i64 8, i1 false) + %1 = load ptr, ptr %a.addr, align 8 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %tmp, ptr align 4 %1, i64 8, i1 false) + %2 = load ptr, ptr %b.addr, align 8 + %3 = load ptr, ptr %a.addr, align 8 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %3, ptr align 4 %2, i64 8, i1 false) + %4 = load ptr, ptr %b.addr, align 8 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %4, ptr align 4 %tmp, i64 8, i1 false) br label %return return: ; preds = %if.end, %if.then @@ -117,25 +105,25 @@ ; Synthetic test case, meant to check that we can handle functions with more ; than one interesting alloca. ; CHECK-LABEL: define {{.*}} @func_with_multiple_interesting_allocas -; CHECK: [[argA:%.*]] = alloca %struct.S*, -; CHECK-NEXT: [[argB:%.*]] = alloca %struct.S*, +; CHECK: [[argA:%.*]] = alloca ptr, +; CHECK-NEXT: [[argB:%.*]] = alloca ptr, ; CHECK-NEXT: [[argDoit:%.*]] = alloca i8, -; CHECK-NEXT: store %struct.S* {{.*}}, %struct.S** [[argA]] -; CHECK-NEXT: store %struct.S* {{.*}}, %struct.S** [[argB]] +; CHECK-NEXT: store ptr {{.*}}, ptr [[argA]] +; CHECK-NEXT: store ptr {{.*}}, ptr [[argB]] ; CHECK-NEXT: [[frombool:%.*]] = zext i1 {{.*}} to i8 -; CHECK-NEXT: store i8 [[frombool]], i8* [[argDoit]] -define void @func_with_multiple_interesting_allocas(%struct.S* %a, %struct.S* %b, i1 zeroext %doit) sanitize_address { +; CHECK-NEXT: store i8 [[frombool]], ptr [[argDoit]] +define void @func_with_multiple_interesting_allocas(ptr %a, ptr %b, i1 zeroext %doit) sanitize_address { entry: - %a.addr = alloca %struct.S*, align 8 - %b.addr = alloca %struct.S*, align 8 + %a.addr = alloca ptr, align 8 + %b.addr = alloca ptr, align 8 %doit.addr = alloca i8, align 1 %tmp = alloca %struct.S, align 4 %tmp2 = alloca %struct.S, align 4 - store %struct.S* %a, %struct.S** %a.addr, align 8 - store %struct.S* %b, %struct.S** %b.addr, align 8 + store ptr %a, ptr %a.addr, align 8 + store ptr %b, ptr %b.addr, align 8 %frombool = zext i1 %doit to i8 - store i8 %frombool, i8* %doit.addr, align 1 - %0 = load i8, i8* %doit.addr, align 1 + store i8 %frombool, ptr %doit.addr, align 1 + %0 = load i8, ptr %doit.addr, align 1 %tobool = trunc i8 %0 to i1 br i1 %tobool, label %if.end, label %if.then @@ -143,31 +131,21 @@ br label %return if.end: ; preds = %entry - %1 = load %struct.S*, %struct.S** %a.addr, align 8 - %2 = bitcast %struct.S* %tmp to i8* - %3 = bitcast %struct.S* %1 to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %2, i8* align 4 %3, i64 8, i1 false) - %4 = load %struct.S*, %struct.S** %b.addr, align 8 - %5 = bitcast %struct.S* %tmp2 to i8* - %6 = bitcast %struct.S* %4 to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %5, i8* align 4 %6, i64 8, i1 false) - %7 = load %struct.S*, %struct.S** %b.addr, align 8 - %8 = load %struct.S*, %struct.S** %a.addr, align 8 - %9 = bitcast %struct.S* %8 to i8* - %10 = bitcast %struct.S* %7 to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %9, i8* align 4 %10, i64 8, i1 false) - %11 = load %struct.S*, %struct.S** %b.addr, align 8 - %12 = bitcast %struct.S* %11 to i8* - %13 = bitcast %struct.S* %tmp to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %12, i8* align 4 %13, i64 8, i1 false) - %14 = load %struct.S*, %struct.S** %a.addr, align 8 - %15 = bitcast %struct.S* %14 to i8* - %16 = bitcast %struct.S* %tmp2 to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %15, i8* align 4 %16, i64 8, i1 false) + %1 = load ptr, ptr %a.addr, align 8 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %tmp, ptr align 4 %1, i64 8, i1 false) + %2 = load ptr, ptr %b.addr, align 8 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %tmp2, ptr align 4 %2, i64 8, i1 false) + %3 = load ptr, ptr %b.addr, align 8 + %4 = load ptr, ptr %a.addr, align 8 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %4, ptr align 4 %3, i64 8, i1 false) + %5 = load ptr, ptr %b.addr, align 8 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %5, ptr align 4 %tmp, i64 8, i1 false) + %6 = load ptr, ptr %a.addr, align 8 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %6, ptr align 4 %tmp2, i64 8, i1 false) br label %return return: ; preds = %if.end, %if.then ret void } -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i64, i1 immarg) +declare void @llvm.memcpy.p0.p0.i64(ptr noalias nocapture writeonly, ptr noalias nocapture readonly, i64, i1 immarg) diff --git a/llvm/test/Instrumentation/AddressSanitizer/instrument-dynamic-allocas.ll b/llvm/test/Instrumentation/AddressSanitizer/instrument-dynamic-allocas.ll --- a/llvm/test/Instrumentation/AddressSanitizer/instrument-dynamic-allocas.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/instrument-dynamic-allocas.ll @@ -12,12 +12,12 @@ ; CHECK-ALLOCA: __asan_allocas_unpoison ; CHECK-ALLOCA: ret void %0 = alloca i32, align 4 - %1 = alloca i8* - store volatile i32 %len, i32* %0, align 4 - %2 = load i32, i32* %0, align 4 + %1 = alloca ptr + store volatile i32 %len, ptr %0, align 4 + %2 = load i32, ptr %0, align 4 %3 = zext i32 %2 to i64 %4 = alloca i8, i64 %3, align 32 - store volatile i8 0, i8* %4 + store volatile i8 0, ptr %4 ret void } @@ -29,9 +29,9 @@ ; CHECK-ALLOCA: ret void entry: %t = alloca inalloca i32 - store i32 42, i32* %t - call void @pass_inalloca(i32* inalloca(i32) %t) + store i32 42, ptr %t + call void @pass_inalloca(ptr inalloca(i32) %t) ret void } -declare void @pass_inalloca(i32* inalloca(i32)) +declare void @pass_inalloca(ptr inalloca(i32)) diff --git a/llvm/test/Instrumentation/AddressSanitizer/instrument-no-return.ll b/llvm/test/Instrumentation/AddressSanitizer/instrument-no-return.ll --- a/llvm/test/Instrumentation/AddressSanitizer/instrument-no-return.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/instrument-no-return.ll @@ -46,7 +46,7 @@ declare i32 @__gxx_personality_v0(...) -define i64 @Invoke1() nounwind uwtable ssp sanitize_address personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +define i64 @Invoke1() nounwind uwtable ssp sanitize_address personality ptr @__gxx_personality_v0 { entry: invoke void @NoReturnFunc() to label %invoke.cont unwind label %lpad @@ -55,8 +55,8 @@ ret i64 0 lpad: - %0 = landingpad { i8*, i32 } - filter [0 x i8*] zeroinitializer + %0 = landingpad { ptr, i32 } + filter [0 x ptr] zeroinitializer ret i64 1 } ; CHECK-LABEL: @Invoke1 diff --git a/llvm/test/Instrumentation/AddressSanitizer/instrument-section-invalid-c-ident.ll b/llvm/test/Instrumentation/AddressSanitizer/instrument-section-invalid-c-ident.ll --- a/llvm/test/Instrumentation/AddressSanitizer/instrument-section-invalid-c-ident.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/instrument-section-invalid-c-ident.ll @@ -9,8 +9,8 @@ @data1 = dso_local global i32 1, align 4 @data2 = dso_local global i32 2, align 4 -@__invalid$c$name_sym_data1 = internal constant i8* bitcast (i32* @data1 to i8*), section "invalid$c$name", align 8 -@__invalid$c$name_sym_data2 = internal constant i8* bitcast (i32* @data2 to i8*), section "invalid$c$name", align 8 +@__invalid$c$name_sym_data1 = internal constant ptr @data1, section "invalid$c$name", align 8 +@__invalid$c$name_sym_data2 = internal constant ptr @data2, section "invalid$c$name", align 8 ; CHECK: @"__invalid$c$name_sym_data1" = internal constant{{.*}}, section "invalid$c$name" ; CHECK-NEXT: @"__invalid$c$name_sym_data2" = internal constant{{.*}}, section "invalid$c$name" ; CHECK: @"__asan_global___invalid$c$name_sym_data1" diff --git a/llvm/test/Instrumentation/AddressSanitizer/instrument-stack.ll b/llvm/test/Instrumentation/AddressSanitizer/instrument-stack.ll --- a/llvm/test/Instrumentation/AddressSanitizer/instrument-stack.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/instrument-stack.ll @@ -5,13 +5,13 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -;@sink = global i32* null, align 4 +;@sink = global ptr null, align 4 ; Ignore direct inbounds stack access. define void @foo() uwtable sanitize_address { entry: %a = alloca i32, align 4 - store i32 42, i32* %a, align 4 + store i32 42, ptr %a, align 4 ret void ; CHECK-LABEL: define void @foo ; CHECK-NOT: __asan_report @@ -22,8 +22,8 @@ define void @baz(i64 %i) sanitize_address { entry: %a = alloca [10 x i32], align 4 - %e = getelementptr inbounds [10 x i32], [10 x i32]* %a, i32 0, i64 %i - store i32 42, i32* %e, align 4 + %e = getelementptr inbounds [10 x i32], ptr %a, i32 0, i64 %i + store i32 42, ptr %e, align 4 ret void ; CHECK-LABEL: define void @baz ; CHECK: __asan_report @@ -33,8 +33,8 @@ define void @bar() sanitize_address { entry: %a = alloca [10 x i32], align 4 - %e = getelementptr inbounds [10 x i32], [10 x i32]* %a, i32 0, i64 12 - store i32 42, i32* %e, align 4 + %e = getelementptr inbounds [10 x i32], ptr %a, i32 0, i64 12 + store i32 42, ptr %e, align 4 ret void ; CHECK-LABEL: define void @bar ; CHECK: __asan_report diff --git a/llvm/test/Instrumentation/AddressSanitizer/instrument_global.ll b/llvm/test/Instrumentation/AddressSanitizer/instrument_global.ll --- a/llvm/test/Instrumentation/AddressSanitizer/instrument_global.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/instrument_global.ll @@ -8,9 +8,9 @@ ; module ctor/dtor ; CHECK: @___asan_gen_ = private constant [8 x i8] c"\00", align 1 -; CHECK: @llvm.used = appending global [2 x i8*] [i8* bitcast (void ()* @asan.module_ctor to i8*), i8* bitcast (void ()* @asan.module_dtor to i8*)], section "llvm.metadata" -; CHECK: @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 1, void ()* @asan.module_ctor, i8* bitcast (void ()* @asan.module_ctor to i8*) }] -; CHECK: @llvm.global_dtors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 1, void ()* @asan.module_dtor, i8* bitcast (void ()* @asan.module_dtor to i8*) }] +; CHECK: @llvm.used = appending global [2 x ptr] [ptr @asan.module_ctor, ptr @asan.module_dtor], section "llvm.metadata" +; CHECK: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @asan.module_ctor, ptr @asan.module_ctor }] +; CHECK: @llvm.global_dtors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @asan.module_dtor, ptr @asan.module_dtor }] ; Test that we don't instrument global arrays with static initializer ; indexed with constants in-bounds. But instrument all other cases. @@ -22,7 +22,7 @@ ; GlobSt is declared here, and has static initializer -- ok to optimize. define i32 @AccessGlobSt_0_2() sanitize_address { entry: - %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @GlobSt, i64 0, i64 2), align 8 + %0 = load i32, ptr getelementptr inbounds ([10 x i32], ptr @GlobSt, i64 0, i64 2), align 8 ret i32 %0 ; CHECK-LABEL: define i32 @AccessGlobSt_0_2 ; CHECK-NOT: __asan_report @@ -32,7 +32,7 @@ ; GlobSt is accessed out of bounds -- can't optimize define i32 @AccessGlobSt_0_12() sanitize_address { entry: - %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @GlobSt, i64 0, i64 12), align 8 + %0 = load i32, ptr getelementptr inbounds ([10 x i32], ptr @GlobSt, i64 0, i64 12), align 8 ret i32 %0 ; CHECK-LABEL: define i32 @AccessGlobSt_0_12 ; CHECK: __asan_report @@ -42,7 +42,7 @@ ; GlobSt is accessed with Gep that has non-0 first index -- can't optimize. define i32 @AccessGlobSt_1_2() sanitize_address { entry: - %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @GlobSt, i64 1, i64 2), align 8 + %0 = load i32, ptr getelementptr inbounds ([10 x i32], ptr @GlobSt, i64 1, i64 2), align 8 ret i32 %0 ; CHECK-LABEL: define i32 @AccessGlobSt_1_2 ; CHECK: __asan_report @@ -52,7 +52,7 @@ ; GlobDy is declared with dynamic initializer -- can't optimize. define i32 @AccessGlobDy_0_2() sanitize_address { entry: - %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @GlobDy, i64 0, i64 2), align 8 + %0 = load i32, ptr getelementptr inbounds ([10 x i32], ptr @GlobDy, i64 0, i64 2), align 8 ret i32 %0 ; CHECK-LABEL: define i32 @AccessGlobDy_0_2 ; CHECK: __asan_report @@ -62,7 +62,7 @@ ; GlobEx is an external global -- can't optimize. define i32 @AccessGlobEx_0_2() sanitize_address { entry: - %0 = load i32, i32* getelementptr inbounds ([10 x i32], [10 x i32]* @GlobEx, i64 0, i64 2), align 8 + %0 = load i32, ptr getelementptr inbounds ([10 x i32], ptr @GlobEx, i64 0, i64 2), align 8 ret i32 %0 ; CHECK-LABEL: define i32 @AccessGlobEx_0_2 ; CHECK: __asan_report diff --git a/llvm/test/Instrumentation/AddressSanitizer/instrument_initializer_metadata.ll b/llvm/test/Instrumentation/AddressSanitizer/instrument_initializer_metadata.ll --- a/llvm/test/Instrumentation/AddressSanitizer/instrument_initializer_metadata.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/instrument_initializer_metadata.ll @@ -15,11 +15,11 @@ define internal void @__cxx_global_var_init() section ".text.startup" { entry: %call = call i32 @initializer() - store i32 %call, i32* @xxx, align 4 + store i32 %call, ptr @xxx, align 4 ret void } -@llvm.global_ctors = appending global [2 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @__late_ctor, i8* null }, { i32, void ()*, i8* } { i32 0, void ()* @__early_ctor, i8* null }] +@llvm.global_ctors = appending global [2 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @__late_ctor, ptr null }, { i32, ptr, ptr } { i32 0, ptr @__early_ctor, ptr null }] define internal void @__late_ctor() sanitize_address section ".text.startup" { entry: @@ -49,7 +49,7 @@ ; Check that xxx is instrumented. define void @touch_xxx() sanitize_address { - store i32 0, i32 *@xxx, align 4 + store i32 0, ptr @xxx, align 4 ret void ; CHECK-LABEL: touch_xxx ; CHECK: call void @__asan_report_store4 @@ -58,7 +58,7 @@ ; Check that XXX is instrumented. define void @touch_XXX() sanitize_address { - store i32 0, i32 *@XXX, align 4 + store i32 0, ptr @XXX, align 4 ret void ; CHECK: define void @touch_XXX ; CHECK: call void @__asan_report_store4 @@ -68,7 +68,7 @@ ; Check that yyy is NOT instrumented (as it does not have dynamic initializer). define void @touch_yyy() sanitize_address { - store i32 0, i32 *@yyy, align 4 + store i32 0, ptr @yyy, align 4 ret void ; CHECK: define void @touch_yyy ; CHECK-NOT: call void @__asan_report_store4 @@ -77,7 +77,7 @@ ; Check that YYY is NOT instrumented (as it does not have dynamic initializer). define void @touch_YYY() sanitize_address { - store i32 0, i32 *@YYY, align 4 + store i32 0, ptr @YYY, align 4 ret void ; CHECK: define void @touch_YYY ; CHECK-NOT: call void @__asan_report_store4 diff --git a/llvm/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll b/llvm/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll --- a/llvm/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/instrument_load_then_store.ll @@ -4,11 +4,11 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define void @IncrementMe(i32* %a) sanitize_address { +define void @IncrementMe(ptr %a) sanitize_address { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 %tmp2 = add i32 %tmp1, 1 - store i32 %tmp2, i32* %a, align 4 + store i32 %tmp2, ptr %a, align 4 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/instrumentation-with-call-threshold.ll b/llvm/test/Instrumentation/AddressSanitizer/instrumentation-with-call-threshold.ll --- a/llvm/test/Instrumentation/AddressSanitizer/instrumentation-with-call-threshold.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/instrumentation-with-call-threshold.ll @@ -10,7 +10,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define void @test_load(i32* %a, i64* %b, i512* %c, i80* %d) sanitize_address { +define void @test_load(ptr %a, ptr %b, ptr %c, ptr %d) sanitize_address { entry: ; CHECK-CALL: call void @__asan_load4 ; CHECK-CALL: call void @__asan_load8 @@ -20,10 +20,10 @@ ; CHECK-CUSTOM-PREFIX: call void @__foo_load8 ; CHECK-CUSTOM-PREFIX: call void @__foo_loadN ; CHECK-INLINE-NOT: call void @__asan_load - %tmp1 = load i32, i32* %a, align 4 - %tmp2 = load i64, i64* %b, align 8 - %tmp3 = load i512, i512* %c, align 32 - %tmp4 = load i80, i80* %d, align 8 + %tmp1 = load i32, ptr %a, align 4 + %tmp2 = load i64, ptr %b, align 8 + %tmp3 = load i512, ptr %c, align 32 + %tmp4 = load i80, ptr %d, align 8 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/keep_going.ll b/llvm/test/Instrumentation/AddressSanitizer/keep_going.ll --- a/llvm/test/Instrumentation/AddressSanitizer/keep_going.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/keep_going.ll @@ -5,10 +5,10 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define i32 @foo(i32* %p) sanitize_address { +define i32 @foo(ptr %p) sanitize_address { ; CHECK: __asan_report_load4_noabort ; CHECK-NOT: unreachable - %1 = load i32, i32* %p, align 4 + %1 = load i32, ptr %p, align 4 ret i32 %1 } diff --git a/llvm/test/Instrumentation/AddressSanitizer/lifetime-throw.ll b/llvm/test/Instrumentation/AddressSanitizer/lifetime-throw.ll --- a/llvm/test/Instrumentation/AddressSanitizer/lifetime-throw.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/lifetime-throw.ll @@ -10,46 +10,45 @@ $_ZTS3ABC = comdat any $_ZTI3ABC = comdat any -@_ZTVN10__cxxabiv117__class_type_infoE = external global i8* +@_ZTVN10__cxxabiv117__class_type_infoE = external global ptr @_ZTS3ABC = linkonce_odr constant [5 x i8] c"3ABC\00", comdat -@_ZTI3ABC = linkonce_odr constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @_ZTS3ABC, i32 0, i32 0) }, comdat +@_ZTI3ABC = linkonce_odr constant { ptr, ptr } { ptr getelementptr inbounds (ptr, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 2), ptr @_ZTS3ABC }, comdat -define void @Throw() sanitize_address personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +define void @Throw() sanitize_address personality ptr @__gxx_personality_v0 { ; CHECK-LABEL: define void @Throw() entry: %x = alloca %struct.ABC, align 4 - %0 = bitcast %struct.ABC* %x to i8* ; Poison memory in prologue: F1F1F1F1F8F3F3F3 - ; CHECK: store i64 -868082052615769615, i64* %{{[0-9]+}} + ; CHECK: store i64 -868082052615769615, ptr %{{[0-9]+}} - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) - ; CHECK: store i8 4, i8* %{{[0-9]+}} + call void @llvm.lifetime.start.p0(i64 4, ptr %x) + ; CHECK: store i8 4, ptr %{{[0-9]+}} ; CHECK-NEXT: @llvm.lifetime.start - %exception = call i8* @__cxa_allocate_exception(i64 4) - invoke void @__cxa_throw(i8* %exception, i8* bitcast ({ i8*, i8* }* @_ZTI3ABC to i8*), i8* bitcast (void (%struct.ABC*)* @_ZN3ABCD2Ev to i8*)) noreturn + %exception = call ptr @__cxa_allocate_exception(i64 4) + invoke void @__cxa_throw(ptr %exception, ptr @_ZTI3ABC, ptr @_ZN3ABCD2Ev) noreturn to label %unreachable unwind label %lpad ; CHECK: call void @__asan_handle_no_return ; CHECK-NEXT: @__cxa_throw lpad: - %1 = landingpad { i8*, i32 } + %0 = landingpad { ptr, i32 } cleanup - call void @_ZN3ABCD2Ev(%struct.ABC* nonnull %x) - call void @llvm.lifetime.end.p0i8(i64 4, i8* %0) - ; CHECK: store i8 -8, i8* %{{[0-9]+}} + call void @_ZN3ABCD2Ev(ptr nonnull %x) + call void @llvm.lifetime.end.p0(i64 4, ptr %x) + ; CHECK: store i8 -8, ptr %{{[0-9]+}} ; CHECK-NEXT: @llvm.lifetime.end - resume { i8*, i32 } %1 - ; CHECK: store i64 0, i64* %{{[0-9]+}} + resume { ptr, i32 } %0 + ; CHECK: store i64 0, ptr %{{[0-9]+}} ; CHECK-NEXT: resume unreachable: unreachable } -%rtti.TypeDescriptor9 = type { i8**, i8*, [10 x i8] } +%rtti.TypeDescriptor9 = type { ptr, ptr, [10 x i8] } %eh.CatchableType = type { i32, i32, i32, i32, i32, i32, i32 } %eh.CatchableTypeArray.1 = type { i32, [1 x i32] } %eh.ThrowInfo = type { i32, i32, i32, i32 } @@ -60,42 +59,40 @@ $"_CTA1?AUABC@@" = comdat any $"_TI1?AUABC@@" = comdat any -@"\01??_7type_info@@6B@" = external constant i8* -@"\01??_R0?AUABC@@@8" = linkonce_odr global %rtti.TypeDescriptor9 { i8** @"\01??_7type_info@@6B@", i8* null, [10 x i8] c".?AUABC@@\00" }, comdat +@"\01??_7type_info@@6B@" = external constant ptr +@"\01??_R0?AUABC@@@8" = linkonce_odr global %rtti.TypeDescriptor9 { ptr @"\01??_7type_info@@6B@", ptr null, [10 x i8] c".?AUABC@@\00" }, comdat @__ImageBase = external constant i8 -@"_CT??_R0?AUABC@@@84" = linkonce_odr unnamed_addr constant %eh.CatchableType { i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%rtti.TypeDescriptor9* @"\01??_R0?AUABC@@@8" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 0, i32 -1, i32 0, i32 4, i32 0 }, section ".xdata", comdat -@"_CTA1?AUABC@@" = linkonce_odr unnamed_addr constant %eh.CatchableTypeArray.1 { i32 1, [1 x i32] [i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableType* @"_CT??_R0?AUABC@@@84" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32)] }, section ".xdata", comdat -@"_TI1?AUABC@@" = linkonce_odr unnamed_addr constant %eh.ThrowInfo { i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (void (%struct.ABC*)* @"\01??1ABC@@QEAA@XZ" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32), i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (%eh.CatchableTypeArray.1* @"_CTA1?AUABC@@" to i64), i64 ptrtoint (i8* @__ImageBase to i64)) to i32) }, section ".xdata", comdat +@"_CT??_R0?AUABC@@@84" = linkonce_odr unnamed_addr constant %eh.CatchableType { i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (ptr @"\01??_R0?AUABC@@@8" to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32), i32 0, i32 -1, i32 0, i32 4, i32 0 }, section ".xdata", comdat +@"_CTA1?AUABC@@" = linkonce_odr unnamed_addr constant %eh.CatchableTypeArray.1 { i32 1, [1 x i32] [i32 trunc (i64 sub nuw nsw (i64 ptrtoint (ptr @"_CT??_R0?AUABC@@@84" to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32)] }, section ".xdata", comdat +@"_TI1?AUABC@@" = linkonce_odr unnamed_addr constant %eh.ThrowInfo { i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (ptr @"\01??1ABC@@QEAA@XZ" to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32), i32 0, i32 trunc (i64 sub nuw nsw (i64 ptrtoint (ptr @"_CTA1?AUABC@@" to i64), i64 ptrtoint (ptr @__ImageBase to i64)) to i32) }, section ".xdata", comdat -define void @ThrowWin() sanitize_address personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) { +define void @ThrowWin() sanitize_address personality ptr @__CxxFrameHandler3 { ; CHECK-LABEL: define void @ThrowWin() entry: %x = alloca %struct.ABC, align 4 %tmp = alloca %struct.ABC, align 4 - %0 = bitcast %struct.ABC* %x to i8* ; Poison memory in prologue: F1F1F1F1F8F304F2 - ; CHECK: store i64 -935355671561244175, i64* %{{[0-9]+}} + ; CHECK: store i64 -935355671561244175, ptr %{{[0-9]+}} - call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) - ; CHECK: store i8 4, i8* %{{[0-9]+}} + call void @llvm.lifetime.start.p0(i64 4, ptr %x) + ; CHECK: store i8 4, ptr %{{[0-9]+}} ; CHECK-NEXT: @llvm.lifetime.start - %1 = bitcast %struct.ABC* %tmp to i8* - invoke void @_CxxThrowException(i8* %1, %eh.ThrowInfo* nonnull @"_TI1?AUABC@@") noreturn + invoke void @_CxxThrowException(ptr %tmp, ptr nonnull @"_TI1?AUABC@@") noreturn to label %unreachable unwind label %ehcleanup ; CHECK: call void @__asan_handle_no_return ; CHECK-NEXT: @_CxxThrowException ehcleanup: - %2 = cleanuppad within none [] - call void @"\01??1ABC@@QEAA@XZ"(%struct.ABC* nonnull %x) [ "funclet"(token %2) ] - call void @llvm.lifetime.end.p0i8(i64 4, i8* %0) - ; CHECK: store i8 -8, i8* %{{[0-9]+}} + %0 = cleanuppad within none [] + call void @"\01??1ABC@@QEAA@XZ"(ptr nonnull %x) [ "funclet"(token %0) ] + call void @llvm.lifetime.end.p0(i64 4, ptr %x) + ; CHECK: store i8 -8, ptr %{{[0-9]+}} ; CHECK-NEXT: @llvm.lifetime.end - cleanupret from %2 unwind to caller - ; CHECK: store i64 0, i64* %{{[0-9]+}} + cleanupret from %0 unwind to caller + ; CHECK: store i64 0, ptr %{{[0-9]+}} ; CHECK-NEXT: cleanupret unreachable: @@ -104,11 +101,11 @@ declare i32 @__gxx_personality_v0(...) -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) -declare void @__cxa_throw(i8*, i8*, i8*) local_unnamed_addr -declare i8* @__cxa_allocate_exception(i64) local_unnamed_addr -declare void @_ZN3ABCD2Ev(%struct.ABC* %this) unnamed_addr -declare void @"\01??1ABC@@QEAA@XZ"(%struct.ABC* %this) -declare void @_CxxThrowException(i8*, %eh.ThrowInfo*) +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) +declare void @__cxa_throw(ptr, ptr, ptr) local_unnamed_addr +declare ptr @__cxa_allocate_exception(i64) local_unnamed_addr +declare void @_ZN3ABCD2Ev(ptr %this) unnamed_addr +declare void @"\01??1ABC@@QEAA@XZ"(ptr %this) +declare void @_CxxThrowException(ptr, ptr) declare i32 @__CxxFrameHandler3(...) diff --git a/llvm/test/Instrumentation/AddressSanitizer/lifetime-uar-uas.ll b/llvm/test/Instrumentation/AddressSanitizer/lifetime-uar-uas.ll --- a/llvm/test/Instrumentation/AddressSanitizer/lifetime-uar-uas.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/lifetime-uar-uas.ll @@ -8,8 +8,8 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) nounwind -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) nounwind +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) nounwind +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) nounwind define i32 @basic_test() sanitize_address { ; CHECK-LABEL: define i32 @basic_test() @@ -19,21 +19,21 @@ %c = alloca i8, align 1 ; Memory is poisoned in prologue: F1F1F1F104F3F8F2 - ; CHECK-UAS: store i64 -866676825215864335, i64* %{{[0-9]+}} + ; CHECK-UAS: store i64 -866676825215864335, ptr %{{[0-9]+}} - call void @llvm.lifetime.start.p0i8(i64 1, i8* %c) + call void @llvm.lifetime.start.p0(i64 1, ptr %c) ; Memory is unpoisoned at llvm.lifetime.start: 01 - ; CHECK-UAS: store i8 1, i8* %{{[0-9]+}} + ; CHECK-UAS: store i8 1, ptr %{{[0-9]+}} - store volatile i32 0, i32* %retval - store volatile i8 0, i8* %c, align 1 + store volatile i32 0, ptr %retval + store volatile i8 0, ptr %c, align 1 - call void @llvm.lifetime.end.p0i8(i64 1, i8* %c) + call void @llvm.lifetime.end.p0(i64 1, ptr %c) ; Memory is poisoned at llvm.lifetime.end: F8 - ; CHECK-UAS: store i8 -8, i8* %{{[0-9]+}} + ; CHECK-UAS: store i8 -8, ptr %{{[0-9]+}} ; Unpoison memory at function exit in UAS mode. - ; CHECK-UAS: store i64 0, i64* %{{[0-9]+}} + ; CHECK-UAS: store i64 0, ptr %{{[0-9]+}} ; CHECK-UAS: ret i32 0 ret i32 0 } diff --git a/llvm/test/Instrumentation/AddressSanitizer/lifetime.ll b/llvm/test/Instrumentation/AddressSanitizer/lifetime.ll --- a/llvm/test/Instrumentation/AddressSanitizer/lifetime.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/lifetime.ll @@ -5,33 +5,32 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) nounwind -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) nounwind +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) nounwind +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) nounwind define void @lifetime_no_size() sanitize_address { ; CHECK-LABEL: define void @lifetime_no_size() entry: %i = alloca i32, align 4 - %i.ptr = bitcast i32* %i to i8* ; Poison memory in prologue: F1F1F1F104F3F3F3 - ; CHECK: store i64 -868083100587789839, i64* %{{[0-9]+}} + ; CHECK: store i64 -868083100587789839, ptr %{{[0-9]+}} - call void @llvm.lifetime.start.p0i8(i64 -1, i8* %i.ptr) + call void @llvm.lifetime.start.p0(i64 -1, ptr %i) ; Check that lifetime with no size are ignored. ; CHECK-NOT: store ; CHECK: call void @llvm.lifetime.start - store volatile i8 0, i8* %i.ptr + store volatile i8 0, ptr %i ; CHECK: store volatile - call void @llvm.lifetime.end.p0i8(i64 -1, i8* %i.ptr) + call void @llvm.lifetime.end.p0(i64 -1, ptr %i) ; Check that lifetime with no size are ignored. ; CHECK-NOT: store ; CHECK: call void @llvm.lifetime.end ; Unpoison stack frame on exit. - ; CHECK: store i64 0, i64* %{{[0-9]+}} + ; CHECK: store i64 0, ptr %{{[0-9]+}} ; CHECK: ret void ret void } @@ -42,57 +41,55 @@ ; Regular variable lifetime intrinsics. %i = alloca i32, align 4 - %i.ptr = bitcast i32* %i to i8* ; Poison memory in prologue: F1F1F1F1F8F3F3F3 - ; CHECK: store i64 -868082052615769615, i64* %{{[0-9]+}} + ; CHECK: store i64 -868082052615769615, ptr %{{[0-9]+}} ; Memory is unpoisoned at llvm.lifetime.start - call void @llvm.lifetime.start.p0i8(i64 3, i8* %i.ptr) - ; CHECK: store i8 4, i8* %{{[0-9]+}} + call void @llvm.lifetime.start.p0(i64 3, ptr %i) + ; CHECK: store i8 4, ptr %{{[0-9]+}} ; CHECK-NEXT: llvm.lifetime.start - store volatile i8 0, i8* %i.ptr + store volatile i8 0, ptr %i ; CHECK: store volatile - call void @llvm.lifetime.end.p0i8(i64 4, i8* %i.ptr) - ; CHECK: store i8 -8, i8* %{{[0-9]+}} + call void @llvm.lifetime.end.p0(i64 4, ptr %i) + ; CHECK: store i8 -8, ptr %{{[0-9]+}} ; CHECK-NEXT: call void @llvm.lifetime.end ; Memory is poisoned at every call to llvm.lifetime.end - call void @llvm.lifetime.end.p0i8(i64 2, i8* %i.ptr) - ; CHECK: store i8 -8, i8* %{{[0-9]+}} + call void @llvm.lifetime.end.p0(i64 2, ptr %i) + ; CHECK: store i8 -8, ptr %{{[0-9]+}} ; CHECK-NEXT: call void @llvm.lifetime.end ; Lifetime intrinsics for array. %arr = alloca [10 x i32], align 16 - %arr.ptr = bitcast [10 x i32]* %arr to i8* - call void @llvm.lifetime.start.p0i8(i64 40, i8* %arr.ptr) + call void @llvm.lifetime.start.p0(i64 40, ptr %arr) ; CHECK-DEFAULT: call void @__asan_unpoison_stack_memory(i64 %{{[^ ]+}}, i64 40) ; CHECK-NO-DYNAMIC-NOT: call void @__asan_unpoison_stack_memory(i64 %{{[^ ]+}}, i64 40) - store volatile i8 0, i8* %arr.ptr + store volatile i8 0, ptr %arr ; CHECK: store volatile - call void @llvm.lifetime.end.p0i8(i64 40, i8* %arr.ptr) + call void @llvm.lifetime.end.p0(i64 40, ptr %arr) ; CHECK-DEFAULT: call void @__asan_poison_stack_memory(i64 %{{[^ ]+}}, i64 40) ; CHECK-NO-DYNAMIC-NOT: call void @__asan_poison_stack_memory(i64 %{{[^ ]+}}, i64 40) ; One more lifetime start/end for the same variable %i. - call void @llvm.lifetime.start.p0i8(i64 2, i8* %i.ptr) - ; CHECK: store i8 4, i8* %{{[0-9]+}} + call void @llvm.lifetime.start.p0(i64 2, ptr %i) + ; CHECK: store i8 4, ptr %{{[0-9]+}} ; CHECK-NEXT: llvm.lifetime.start - store volatile i8 0, i8* %i.ptr + store volatile i8 0, ptr %i ; CHECK: store volatile - call void @llvm.lifetime.end.p0i8(i64 4, i8* %i.ptr) - ; CHECK: store i8 -8, i8* %{{[0-9]+}} + call void @llvm.lifetime.end.p0(i64 4, ptr %i) + ; CHECK: store i8 -8, ptr %{{[0-9]+}} ; CHECK-NEXT: llvm.lifetime.end ; Memory is unpoisoned at function exit (only once). - ; CHECK: store i64 0, i64* %{{[0-9]+}} + ; CHECK: store i64 0, ptr %{{[0-9]+}} ; CHECK-NEXT: ret void ret void } @@ -103,32 +100,30 @@ entry: %i = alloca i64, align 4 - %i.ptr = bitcast i64* %i to i8* ; Poison memory in prologue: F1F1F1F1F8F3F3F3 - ; CHECK: store i64 -868082052615769615, i64* %{{[0-9]+}} + ; CHECK: store i64 -868082052615769615, ptr %{{[0-9]+}} - call void @llvm.lifetime.start.p0i8(i64 8, i8* %i.ptr) - ; CHECK: store i8 0, i8* %{{[0-9]+}} + call void @llvm.lifetime.start.p0(i64 8, ptr %i) + ; CHECK: store i8 0, ptr %{{[0-9]+}} ; CHECK-NEXT: llvm.lifetime.start - store volatile i8 0, i8* %i.ptr + store volatile i8 0, ptr %i ; CHECK: store volatile br i1 %x, label %bb0, label %bb1 bb0: - %i.ptr2 = bitcast i64* %i to i8* br label %bb1 bb1: - %i.phi = phi i8* [ %i.ptr, %entry ], [ %i.ptr2, %bb0 ] - call void @llvm.lifetime.end.p0i8(i64 8, i8* %i.phi) - ; CHECK: store i8 -8, i8* %{{[0-9]+}} + %i.phi = phi ptr [ %i, %entry ], [ %i, %bb0 ] + call void @llvm.lifetime.end.p0(i64 8, ptr %i.phi) + ; CHECK: store i8 -8, ptr %{{[0-9]+}} ; CHECK-NEXT: llvm.lifetime.end ret void - ; CHECK: store i64 0, i64* %{{[0-9]+}} + ; CHECK: store i64 0, ptr %{{[0-9]+}} ; CHECK-NEXT: ret void } @@ -137,24 +132,23 @@ ; CHECK-LABEL: define void @getelementptr_args entry: %x = alloca [1024 x i8], align 16 - %d = alloca i8*, align 8 + %d = alloca ptr, align 8 ; F1F1F1F1 - ; CHECK: store i32 -235802127, i32* %{{[0-9]+}} + ; CHECK: store i32 -235802127, ptr %{{[0-9]+}} ; F3F3F3F3F3F3F3F3 - ; CHECK: store i64 -868082074056920077, i64* %{{[0-9]+}} + ; CHECK: store i64 -868082074056920077, ptr %{{[0-9]+}} ; F3F3F3F3F3F3F3F3 - ; CHECK: store i64 -868082074056920077, i64* %{{[0-9]+}} + ; CHECK: store i64 -868082074056920077, ptr %{{[0-9]+}} - %0 = getelementptr inbounds [1024 x i8], [1024 x i8]* %x, i64 0, i64 0 - call void @llvm.lifetime.start.p0i8(i64 1024, i8* %0) + call void @llvm.lifetime.start.p0(i64 1024, ptr %x) ; CHECK: call void @__asan_set_shadow_00(i64 %{{[0-9]+}}, i64 128) ; CHECK-NEXT: call void @llvm.lifetime.start - store i8* %0, i8** %d, align 8 - ; CHECK: store i8 + store ptr %x, ptr %d, align 8 + ; CHECK: store ptr - call void @llvm.lifetime.end.p0i8(i64 1024, i8* %0) + call void @llvm.lifetime.end.p0(i64 1024, ptr %x) ; CHECK: call void @__asan_set_shadow_f8(i64 %{{[0-9]+}}, i64 128) ; CHECK-NEXT: call void @llvm.lifetime.end @@ -169,17 +163,13 @@ entry: %a.addr = alloca i64, align 8 %b = alloca [0 x i8], align 1 - store i64 %a, i64* %a.addr, align 8 + store i64 %a, ptr %a.addr, align 8 - %0 = bitcast [0 x i8]* %b to i8* - call void @llvm.lifetime.start.p0i8(i64 0, i8* %0) #2 - ; CHECK: %{{[0-9]+}} = bitcast - ; CHECK-NEXT: call void @llvm.lifetime.start + call void @llvm.lifetime.start.p0(i64 0, ptr %b) #2 + ; CHECK: call void @llvm.lifetime.start - %1 = bitcast [0 x i8]* %b to i8* - call void @llvm.lifetime.end.p0i8(i64 0, i8* %1) #2 - ; CHECK-NEXT: %{{[0-9]+}} = bitcast - ; CHECK-NEXT: call void @llvm.lifetime.end + call void @llvm.lifetime.end.p0(i64 0, ptr %b) #2 + ; CHECK: call void @llvm.lifetime.end ret void ; CHECK-NEXT: ret void diff --git a/llvm/test/Instrumentation/AddressSanitizer/localescape.ll b/llvm/test/Instrumentation/AddressSanitizer/localescape.ll --- a/llvm/test/Instrumentation/AddressSanitizer/localescape.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/localescape.ll @@ -8,43 +8,42 @@ target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" target triple = "i686-pc-windows-msvc18.0.0" -declare i32 @llvm.eh.typeid.for(i8*) #2 -declare i8* @llvm.frameaddress(i32) -declare i8* @llvm.eh.recoverfp(i8*, i8*) -declare i8* @llvm.localrecover(i8*, i8*, i32) +declare i32 @llvm.eh.typeid.for(ptr) #2 +declare ptr @llvm.frameaddress(i32) +declare ptr @llvm.eh.recoverfp(ptr, ptr) +declare ptr @llvm.localrecover(ptr, ptr, i32) declare void @llvm.localescape(...) #1 declare i32 @_except_handler3(...) -declare void @may_throw(i32* %r) +declare void @may_throw(ptr %r) -define i32 @main() sanitize_address personality i8* bitcast (i32 (...)* @_except_handler3 to i8*) { +define i32 @main() sanitize_address personality ptr @_except_handler3 { entry: %r = alloca i32, align 4 %__exception_code = alloca i32, align 4 - call void (...) @llvm.localescape(i32* nonnull %__exception_code) - %0 = bitcast i32* %r to i8* - store i32 0, i32* %r, align 4 - invoke void @may_throw(i32* nonnull %r) #4 + call void (...) @llvm.localescape(ptr nonnull %__exception_code) + store i32 0, ptr %r, align 4 + invoke void @may_throw(ptr nonnull %r) #4 to label %__try.cont unwind label %lpad lpad: ; preds = %entry - %1 = landingpad { i8*, i32 } - catch i8* bitcast (i32 ()* @"\01?filt$0@0@main@@" to i8*) - %2 = extractvalue { i8*, i32 } %1, 1 - %3 = call i32 @llvm.eh.typeid.for(i8* bitcast (i32 ()* @"\01?filt$0@0@main@@" to i8*)) #1 - %matches = icmp eq i32 %2, %3 + %0 = landingpad { ptr, i32 } + catch ptr @"\01?filt$0@0@main@@" + %1 = extractvalue { ptr, i32 } %0, 1 + %2 = call i32 @llvm.eh.typeid.for(ptr @"\01?filt$0@0@main@@") #1 + %matches = icmp eq i32 %1, %2 br i1 %matches, label %__except, label %eh.resume __except: ; preds = %lpad - store i32 1, i32* %r, align 4 + store i32 1, ptr %r, align 4 br label %__try.cont __try.cont: ; preds = %entry, %__except - %4 = load i32, i32* %r, align 4 - ret i32 %4 + %3 = load i32, ptr %r, align 4 + ret i32 %3 eh.resume: ; preds = %lpad - resume { i8*, i32 } %1 + resume { ptr, i32 } %0 } ; Check that the alloca remains static and the localescape call remains in the @@ -54,33 +53,31 @@ ; CHECK-NOT: br {{.*}}label ; CHECK: %__exception_code = alloca i32, align 4 ; CHECK-NOT: br {{.*}}label -; CHECK: call void (...) @llvm.localescape(i32* nonnull %__exception_code) +; CHECK: call void (...) @llvm.localescape(ptr nonnull %__exception_code) ; Function Attrs: nounwind define internal i32 @"\01?filt$0@0@main@@"() #1 { entry: - %0 = tail call i8* @llvm.frameaddress(i32 1) - %1 = tail call i8* @llvm.eh.recoverfp(i8* bitcast (i32 ()* @main to i8*), i8* %0) - %2 = tail call i8* @llvm.localrecover(i8* bitcast (i32 ()* @main to i8*), i8* %1, i32 0) - %__exception_code = bitcast i8* %2 to i32* - %3 = getelementptr inbounds i8, i8* %0, i32 -20 - %4 = bitcast i8* %3 to { i32*, i8* }** - %5 = load { i32*, i8* }*, { i32*, i8* }** %4, align 4 - %6 = getelementptr inbounds { i32*, i8* }, { i32*, i8* }* %5, i32 0, i32 0 - %7 = load i32*, i32** %6, align 4 - %8 = load i32, i32* %7, align 4 - store i32 %8, i32* %__exception_code, align 4 + %0 = tail call ptr @llvm.frameaddress(i32 1) + %1 = tail call ptr @llvm.eh.recoverfp(ptr @main, ptr %0) + %2 = tail call ptr @llvm.localrecover(ptr @main, ptr %1, i32 0) + %3 = getelementptr inbounds i8, ptr %0, i32 -20 + %4 = load ptr, ptr %3, align 4 + %5 = getelementptr inbounds { ptr, ptr }, ptr %4, i32 0, i32 0 + %6 = load ptr, ptr %5, align 4 + %7 = load i32, ptr %6, align 4 + store i32 %7, ptr %2, align 4 ret i32 1 } ; CHECK-LABEL: define internal i32 @"\01?filt$0@0@main@@"() -; CHECK: tail call i8* @llvm.localrecover(i8* bitcast (i32 ()* @main to i8*), i8* {{.*}}, i32 0) +; CHECK: tail call ptr @llvm.localrecover(ptr @main, ptr {{.*}}, i32 0) -define void @ScaleFilterCols_SSSE3(i8* %dst_ptr, i8* %src_ptr, i32 %dst_width, i32 %x, i32 %dx) sanitize_address { +define void @ScaleFilterCols_SSSE3(ptr %dst_ptr, ptr %src_ptr, i32 %dst_width, i32 %x, i32 %dx) sanitize_address { entry: %dst_width.addr = alloca i32, align 4 - store i32 %dst_width, i32* %dst_width.addr, align 4 - %0 = call { i8*, i8*, i32, i32, i32 } asm sideeffect "", "=r,=r,={ax},=r,=r,=*rm,rm,rm,0,1,2,3,4,5,~{memory},~{cc},~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{dirflag},~{fpsr},~{flags}"(i32* elementtype(i32) nonnull %dst_width.addr, i32 %x, i32 %dx, i8* %dst_ptr, i8* %src_ptr, i32 0, i32 0, i32 0, i32 %dst_width) + store i32 %dst_width, ptr %dst_width.addr, align 4 + %0 = call { ptr, ptr, i32, i32, i32 } asm sideeffect "", "=r,=r,={ax},=r,=r,=*rm,rm,rm,0,1,2,3,4,5,~{memory},~{cc},~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) nonnull %dst_width.addr, i32 %x, i32 %dx, ptr %dst_ptr, ptr %src_ptr, i32 0, i32 0, i32 0, i32 %dst_width) ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/mem-intrinsics.ll b/llvm/test/Instrumentation/AddressSanitizer/mem-intrinsics.ll --- a/llvm/test/Instrumentation/AddressSanitizer/mem-intrinsics.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/mem-intrinsics.ll @@ -7,17 +7,17 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind -declare void @llvm.memset.inline.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind -declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) nounwind -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) nounwind -declare void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) nounwind +declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind +declare void @llvm.memset.inline.p0.i64(ptr nocapture, i8, i64, i1) nounwind +declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1) nounwind +declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1) nounwind +declare void @llvm.memcpy.inline.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1) nounwind -define void @memintr_test(i8* %a, i8* %b) nounwind uwtable sanitize_address { +define void @memintr_test(ptr %a, ptr %b) nounwind uwtable sanitize_address { entry: - tail call void @llvm.memset.p0i8.i64(i8* %a, i8 0, i64 100, i1 false) - tail call void @llvm.memmove.p0i8.p0i8.i64(i8* %a, i8* %b, i64 100, i1 false) - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 100, i1 false) + tail call void @llvm.memset.p0.i64(ptr %a, i8 0, i64 100, i1 false) + tail call void @llvm.memmove.p0.p0.i64(ptr %a, ptr %b, i64 100, i1 false) + tail call void @llvm.memcpy.p0.p0.i64(ptr %a, ptr %b, i64 100, i1 false) ret void } ; CHECK-LABEL: memintr_test @@ -29,10 +29,10 @@ ; CHECK-NOPREFIX: @memcpy ; CHECK: ret void -define void @memintr_inline_test(i8* %a, i8* %b) nounwind uwtable sanitize_address { +define void @memintr_inline_test(ptr %a, ptr %b) nounwind uwtable sanitize_address { entry: - tail call void @llvm.memset.inline.p0i8.i64(i8* %a, i8 0, i64 100, i1 false) - tail call void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* %a, i8* %b, i64 100, i1 false) + tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 0, i64 100, i1 false) + tail call void @llvm.memcpy.inline.p0.p0.i64(ptr %a, ptr %b, i64 100, i1 false) ret void } ; CHECK-LABEL: memintr_inline_test @@ -42,11 +42,11 @@ ; CHECK-NOPREFIX: @memcpy ; CHECK: ret void -define void @memintr_test_nosanitize(i8* %a, i8* %b) nounwind uwtable { +define void @memintr_test_nosanitize(ptr %a, ptr %b) nounwind uwtable { entry: - tail call void @llvm.memset.p0i8.i64(i8* %a, i8 0, i64 100, i1 false) - tail call void @llvm.memmove.p0i8.p0i8.i64(i8* %a, i8* %b, i64 100, i1 false) - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 100, i1 false) + tail call void @llvm.memset.p0.i64(ptr %a, i8 0, i64 100, i1 false) + tail call void @llvm.memmove.p0.p0.i64(ptr %a, ptr %b, i64 100, i1 false) + tail call void @llvm.memcpy.p0.p0.i64(ptr %a, ptr %b, i64 100, i1 false) ret void } ; CHECK-LABEL: memintr_test_nosanitize @@ -55,21 +55,21 @@ ; CHECK: @llvm.memcpy ; CHECK: ret void -declare void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* nocapture writeonly, i8, i64, i32) nounwind -declare void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind -declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind +declare void @llvm.memset.element.unordered.atomic.p0.i64(ptr nocapture writeonly, i8, i64, i32) nounwind +declare void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind +declare void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind -define void @memintr_element_atomic_test(i8* %a, i8* %b) nounwind uwtable sanitize_address { +define void @memintr_element_atomic_test(ptr %a, ptr %b) nounwind uwtable sanitize_address { ; This is a canary test to make sure that these don't get lowered into calls that don't ; have the element-atomic property. Eventually, asan will have to be enhanced to lower ; these properly. ; CHECK-LABEL: memintr_element_atomic_test - ; CHECK-NEXT: tail call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %a, i8 0, i64 100, i32 1) - ; CHECK-NEXT: tail call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1) - ; CHECK-NEXT: tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1) + ; CHECK-NEXT: tail call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 %a, i8 0, i64 100, i32 1) + ; CHECK-NEXT: tail call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 %a, ptr align 1 %b, i64 100, i32 1) + ; CHECK-NEXT: tail call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 %a, ptr align 1 %b, i64 100, i32 1) ; CHECK-NEXT: ret void - tail call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %a, i8 0, i64 100, i32 1) - tail call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1) - tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1) + tail call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 %a, i8 0, i64 100, i32 1) + tail call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 %a, ptr align 1 %b, i64 100, i32 1) + tail call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 %a, ptr align 1 %b, i64 100, i32 1) ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/module-flags.ll b/llvm/test/Instrumentation/AddressSanitizer/module-flags.ll --- a/llvm/test/Instrumentation/AddressSanitizer/module-flags.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/module-flags.ll @@ -6,7 +6,7 @@ define i32 @test_load() sanitize_address { entry: - %tmp = load i32, i32* @g, align 4 + %tmp = load i32, ptr @g, align 4 ret i32 %tmp } diff --git a/llvm/test/Instrumentation/AddressSanitizer/musttail.ll b/llvm/test/Instrumentation/AddressSanitizer/musttail.ll --- a/llvm/test/Instrumentation/AddressSanitizer/musttail.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/musttail.ll @@ -2,33 +2,33 @@ ; ; RUN: opt < %s -passes=asan -S | FileCheck %s -define internal i32 @foo(i32* %p) sanitize_address { - %rv = load i32, i32* %p +define internal i32 @foo(ptr %p) sanitize_address { + %rv = load i32, ptr %p ret i32 %rv } -declare void @alloca_test_use([10 x i8]*) -define i32 @call_foo(i32* %a) sanitize_address { +declare void @alloca_test_use(ptr) +define i32 @call_foo(ptr %a) sanitize_address { %x = alloca [10 x i8], align 1 - call void @alloca_test_use([10 x i8]* %x) - %r = musttail call i32 @foo(i32* %a) + call void @alloca_test_use(ptr %x) + %r = musttail call i32 @foo(ptr %a) ret i32 %r } -; CHECK-LABEL: define i32 @call_foo(i32* %a) -; CHECK: %r = musttail call i32 @foo(i32* %a) +; CHECK-LABEL: define i32 @call_foo(ptr %a) +; CHECK: %r = musttail call i32 @foo(ptr %a) ; CHECK-NEXT: ret i32 %r -define i32 @call_foo_cast(i32* %a) sanitize_address { +define i32 @call_foo_cast(ptr %a) sanitize_address { %x = alloca [10 x i8], align 1 - call void @alloca_test_use([10 x i8]* %x) - %r = musttail call i32 @foo(i32* %a) + call void @alloca_test_use(ptr %x) + %r = musttail call i32 @foo(ptr %a) %t = bitcast i32 %r to i32 ret i32 %t } -; CHECK-LABEL: define i32 @call_foo_cast(i32* %a) -; CHECK: %r = musttail call i32 @foo(i32* %a) +; CHECK-LABEL: define i32 @call_foo_cast(ptr %a) +; CHECK: %r = musttail call i32 @foo(ptr %a) ; CHECK-NEXT: %t = bitcast i32 %r to i32 ; CHECK-NEXT: ret i32 %t diff --git a/llvm/test/Instrumentation/AddressSanitizer/ps4.ll b/llvm/test/Instrumentation/AddressSanitizer/ps4.ll --- a/llvm/test/Instrumentation/AddressSanitizer/ps4.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/ps4.ll @@ -1,9 +1,9 @@ ; RUN: opt < %s -passes=asan -S -mtriple=x86_64-scei-ps4 | FileCheck %s ; RUN: opt < %s -passes=asan -S -mtriple=x86_64-sie-ps5 | FileCheck %s -define i32 @read_4_bytes(i32* %a) sanitize_address { +define i32 @read_4_bytes(ptr %a) sanitize_address { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } diff --git a/llvm/test/Instrumentation/AddressSanitizer/scale-offset.ll b/llvm/test/Instrumentation/AddressSanitizer/scale-offset.ll --- a/llvm/test/Instrumentation/AddressSanitizer/scale-offset.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/scale-offset.ll @@ -5,9 +5,9 @@ ; RUN: opt < %s -passes=asan -asan-mapping-offset 0xc0ffee -asan-mapping-scale 0 -S | FileCheck --check-prefix=CHECK-BOTH %s target triple = "x86_64-unknown-linux-gnu" -define i32 @read_offset(i32* %a) sanitize_address { +define i32 @read_offset(ptr %a) sanitize_address { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } ; CHECK-OFFSET-LABEL: @read_offset @@ -16,9 +16,9 @@ ; CHECK-OFFSET-NEXT: add{{.*}}3735928559 ; CHECK-OFFSET: ret -define i32 @read_scale(i32* %a) sanitize_address { +define i32 @read_scale(ptr %a) sanitize_address { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } ; CHECK-SCALE-LABEL: @read_scale @@ -27,9 +27,9 @@ ; CHECK-SCALE-NEXT: add{{.*}} ; CHECK-SCALE: ret -define i32 @read_both(i32* %a) sanitize_address { +define i32 @read_both(ptr %a) sanitize_address { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } ; CHECK-BOTH-LABEL: @read_both diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll --- a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime-be.ll @@ -7,55 +7,55 @@ target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" -declare void @Foo(i8*) +declare void @Foo(ptr) define void @Bar() uwtable sanitize_address { entry: %x = alloca [650 x i8], align 16 - %xx = getelementptr inbounds [650 x i8], [650 x i8]* %x, i64 0, i64 0 + %xx = getelementptr inbounds [650 x i8], ptr %x, i64 0, i64 0 %y = alloca [13 x i8], align 1 - %yy = getelementptr inbounds [13 x i8], [13 x i8]* %y, i64 0, i64 0 + %yy = getelementptr inbounds [13 x i8], ptr %y, i64 0, i64 0 %z = alloca [40 x i8], align 1 - %zz = getelementptr inbounds [40 x i8], [40 x i8]* %z, i64 0, i64 0 + %zz = getelementptr inbounds [40 x i8], ptr %z, i64 0, i64 0 ; CHECK: [[SHADOW_BASE:%[0-9]+]] = add i64 %{{[0-9]+}}, 17592186044416 ; F1F1F1F1 ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0 - ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; ENTRY-NEXT: store [[TYPE]] -235802127, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-NEXT: store i32 -235802127, ptr [[PTR]], align 1 ; 02F2F2F2F2F2F2F2 ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 85 - ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; ENTRY-NEXT: store [[TYPE]] 212499257711850226, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-NEXT: store i64 212499257711850226, ptr [[PTR]], align 1 ; F2F2F2F2F2F2F2F2 ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 93 - ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; ENTRY-NEXT: store [[TYPE]] -940422246894996750, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-NEXT: store i64 -940422246894996750, ptr [[PTR]], align 1 ; F20005F2F2000000 ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 101 - ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; ENTRY-NEXT: store [[TYPE]] -1008799775530680320, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-NEXT: store i64 -1008799775530680320, ptr [[PTR]], align 1 ; F3F3F3F3 ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 111 - ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; ENTRY-NEXT: store [[TYPE]] -202116109, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-NEXT: store i32 -202116109, ptr [[PTR]], align 1 ; F3 ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 115 - ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i8]]* - ; ENTRY-NEXT: store [[TYPE]] -13, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-NEXT: store i8 -13, ptr [[PTR]], align 1 ; F1F1F1F1 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -235802127, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i32 -235802127, ptr [[PTR]], align 1 ; F8F8F8... ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 4 @@ -63,101 +63,101 @@ ; F2F2F2F2F2F2F2F2 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 86 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -940422246894996750, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i64 -940422246894996750, ptr [[PTR]], align 1 ; F2F2F2F2F2F2F2F2 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 94 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -940422246894996750, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i64 -940422246894996750, ptr [[PTR]], align 1 ; F8F8F2F2F8F8F8F8 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 102 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -506387832706107144, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i64 -506387832706107144, ptr [[PTR]], align 1 ; F8F3F3F3 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 110 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -118230029, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i32 -118230029, ptr [[PTR]], align 1 ; F3F3 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 114 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i16]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -3085, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i16 -3085, ptr [[PTR]], align 1 ; CHECK-LABEL: %xx = getelementptr inbounds ; CHECK-NEXT: %yy = getelementptr inbounds ; CHECK-NEXT: %zz = getelementptr inbounds - call void @llvm.lifetime.start.p0i8(i64 650, i8* %xx) + call void @llvm.lifetime.start.p0(i64 650, ptr %xx) ; 0000... ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 4 ; ENTRY-UAS-NEXT: call void @__asan_set_shadow_00(i64 [[OFFSET]], i64 81) ; 02 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 85 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i8]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] 2, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i8 2, ptr [[PTR]], align 1 - ; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 650, i8* %xx) + ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 650, ptr %xx) - call void @Foo(i8* %xx) - ; CHECK-NEXT: call void @Foo(i8* %xx) + call void @Foo(ptr %xx) + ; CHECK-NEXT: call void @Foo(ptr %xx) - call void @llvm.lifetime.end.p0i8(i64 650, i8* %xx) + call void @llvm.lifetime.end.p0(i64 650, ptr %xx) ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 4 ; ENTRY-UAS-NEXT: call void @__asan_set_shadow_f8(i64 [[OFFSET]], i64 82) - ; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 650, i8* %xx) + ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 650, ptr %xx) - call void @llvm.lifetime.start.p0i8(i64 13, i8* %yy) + call void @llvm.lifetime.start.p0(i64 13, ptr %yy) ; 0005 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 102 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i16]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] 5, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i16 5, ptr [[PTR]], align 1 - ; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 13, i8* %yy) + ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 13, ptr %yy) - call void @Foo(i8* %yy) - ; CHECK-NEXT: call void @Foo(i8* %yy) + call void @Foo(ptr %yy) + ; CHECK-NEXT: call void @Foo(ptr %yy) - call void @llvm.lifetime.end.p0i8(i64 13, i8* %yy) + call void @llvm.lifetime.end.p0(i64 13, ptr %yy) ; F8F8 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 102 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i16]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -1800, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i16 -1800, ptr [[PTR]], align 1 - ; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 13, i8* %yy) + ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 13, ptr %yy) - call void @llvm.lifetime.start.p0i8(i64 40, i8* %zz) + call void @llvm.lifetime.start.p0(i64 40, ptr %zz) ; 00000000 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 106 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i32 0, ptr [[PTR]], align 1 ; 00 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 110 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i8]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i8 0, ptr [[PTR]], align 1 - ; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 40, i8* %zz) + ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 40, ptr %zz) - call void @Foo(i8* %zz) - ; CHECK-NEXT: call void @Foo(i8* %zz) + call void @Foo(ptr %zz) + ; CHECK-NEXT: call void @Foo(ptr %zz) - call void @llvm.lifetime.end.p0i8(i64 40, i8* %zz) + call void @llvm.lifetime.end.p0(i64 40, ptr %zz) ; F8F8F8F8 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 106 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -117901064, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i32 -117901064, ptr [[PTR]], align 1 ; F8 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 110 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i8]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -8, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i8 -8, ptr [[PTR]], align 1 - ; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 40, i8* %zz) + ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 40, ptr %zz) ; CHECK: {{^[0-9]+}}: @@ -170,33 +170,33 @@ ; 00000000 ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0 - ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; EXIT-NEXT: store i32 0, ptr [[PTR]], align 1 ; 0000000000000000 ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 85 - ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; EXIT-NEXT: store i64 0, ptr [[PTR]], align 1 ; 0000000000000000 ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 93 - ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; EXIT-NEXT: store i64 0, ptr [[PTR]], align 1 ; 0000000000000000 ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 101 - ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; EXIT-NEXT: store i64 0, ptr [[PTR]], align 1 ; 00000000 ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 111 - ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; EXIT-NEXT: store i32 0, ptr [[PTR]], align 1 ; 00 ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 115 - ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i8]]* - ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; EXIT-NEXT: store i8 0, ptr [[PTR]], align 1 ; 0000... ; EXIT-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0 @@ -209,8 +209,8 @@ ; CHECK: ret void } -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) ; CHECK-ON: declare void @__asan_set_shadow_00(i64, i64) ; CHECK-ON: declare void @__asan_set_shadow_f1(i64, i64) diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll --- a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-and-lifetime.ll @@ -7,55 +7,55 @@ target datalayout = "e-i64:64-f80:128-s:64-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare void @Foo(i8*) +declare void @Foo(ptr) define void @Bar() uwtable sanitize_address { entry: %x = alloca [650 x i8], align 16 - %xx = getelementptr inbounds [650 x i8], [650 x i8]* %x, i64 0, i64 0 + %xx = getelementptr inbounds [650 x i8], ptr %x, i64 0, i64 0 %y = alloca [13 x i8], align 1 - %yy = getelementptr inbounds [13 x i8], [13 x i8]* %y, i64 0, i64 0 + %yy = getelementptr inbounds [13 x i8], ptr %y, i64 0, i64 0 %z = alloca [40 x i8], align 1 - %zz = getelementptr inbounds [40 x i8], [40 x i8]* %z, i64 0, i64 0 + %zz = getelementptr inbounds [40 x i8], ptr %z, i64 0, i64 0 ; CHECK: [[SHADOW_BASE:%[0-9]+]] = add i64 %{{[0-9]+}}, 2147450880 ; F1F1F1F1 ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0 - ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; ENTRY-NEXT: store [[TYPE]] -235802127, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-NEXT: store i32 -235802127, ptr [[PTR]], align 1 ; 02F2F2F2F2F2F2F2 ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 85 - ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; ENTRY-NEXT: store [[TYPE]] -940422246894996990, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-NEXT: store i64 -940422246894996990, ptr [[PTR]], align 1 ; F2F2F2F2F2F2F2F2 ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 93 - ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; ENTRY-NEXT: store [[TYPE]] -940422246894996750, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-NEXT: store i64 -940422246894996750, ptr [[PTR]], align 1 ; F20005F2F2000000 ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 101 - ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; ENTRY-NEXT: store [[TYPE]] 1043442499826, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-NEXT: store i64 1043442499826, ptr [[PTR]], align 1 ; F3F3F3F3 ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 111 - ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; ENTRY-NEXT: store [[TYPE]] -202116109, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-NEXT: store i32 -202116109, ptr [[PTR]], align 1 ; F3 ; ENTRY-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 115 - ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i8]]* - ; ENTRY-NEXT: store [[TYPE]] -13, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-NEXT: store i8 -13, ptr [[PTR]], align 1 ; F1F1F1F1 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -235802127, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i32 -235802127, ptr [[PTR]], align 1 ; F8F8F8... ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 4 @@ -63,101 +63,101 @@ ; F2F2F2F2F2F2F2F2 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 86 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -940422246894996750, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i64 -940422246894996750, ptr [[PTR]], align 1 ; F2F2F2F2F2F2F2F2 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 94 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -940422246894996750, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i64 -940422246894996750, ptr [[PTR]], align 1 ; F8F8F2F2F8F8F8F8 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 102 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -506381209967593224, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i64 -506381209967593224, ptr [[PTR]], align 1 ; F8F3F3F3 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 110 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -202116104, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i32 -202116104, ptr [[PTR]], align 1 ; F3F3 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 114 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i16]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -3085, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i16 -3085, ptr [[PTR]], align 1 ; CHECK-LABEL: %xx = getelementptr inbounds ; CHECK-NEXT: %yy = getelementptr inbounds ; CHECK-NEXT: %zz = getelementptr inbounds - call void @llvm.lifetime.start.p0i8(i64 650, i8* %xx) + call void @llvm.lifetime.start.p0(i64 650, ptr %xx) ; 0000... ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 4 ; ENTRY-UAS-NEXT: call void @__asan_set_shadow_00(i64 [[OFFSET]], i64 81) ; 02 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 85 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i8]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] 2, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i8 2, ptr [[PTR]], align 1 - ; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 650, i8* %xx) + ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 650, ptr %xx) - call void @Foo(i8* %xx) - ; CHECK-NEXT: call void @Foo(i8* %xx) + call void @Foo(ptr %xx) + ; CHECK-NEXT: call void @Foo(ptr %xx) - call void @llvm.lifetime.end.p0i8(i64 650, i8* %xx) + call void @llvm.lifetime.end.p0(i64 650, ptr %xx) ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 4 ; ENTRY-UAS-NEXT: call void @__asan_set_shadow_f8(i64 [[OFFSET]], i64 82) - ; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 650, i8* %xx) + ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 650, ptr %xx) - call void @llvm.lifetime.start.p0i8(i64 13, i8* %yy) + call void @llvm.lifetime.start.p0(i64 13, ptr %yy) ; 0005 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 102 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i16]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] 1280, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i16 1280, ptr [[PTR]], align 1 - ; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 13, i8* %yy) + ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 13, ptr %yy) - call void @Foo(i8* %yy) - ; CHECK-NEXT: call void @Foo(i8* %yy) + call void @Foo(ptr %yy) + ; CHECK-NEXT: call void @Foo(ptr %yy) - call void @llvm.lifetime.end.p0i8(i64 13, i8* %yy) + call void @llvm.lifetime.end.p0(i64 13, ptr %yy) ; F8F8 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 102 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i16]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -1800, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i16 -1800, ptr [[PTR]], align 1 - ; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 13, i8* %yy) + ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 13, ptr %yy) - call void @llvm.lifetime.start.p0i8(i64 40, i8* %zz) + call void @llvm.lifetime.start.p0(i64 40, ptr %zz) ; 00000000 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 106 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i32 0, ptr [[PTR]], align 1 ; 00 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 110 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i8]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i8 0, ptr [[PTR]], align 1 - ; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 40, i8* %zz) + ; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 40, ptr %zz) - call void @Foo(i8* %zz) - ; CHECK-NEXT: call void @Foo(i8* %zz) + call void @Foo(ptr %zz) + ; CHECK-NEXT: call void @Foo(ptr %zz) - call void @llvm.lifetime.end.p0i8(i64 40, i8* %zz) + call void @llvm.lifetime.end.p0(i64 40, ptr %zz) ; F8F8F8F8 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 106 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -117901064, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i32 -117901064, ptr [[PTR]], align 1 ; F8 ; ENTRY-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 110 - ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i8]]* - ; ENTRY-UAS-NEXT: store [[TYPE]] -8, [[TYPE]]* [[PTR]], align 1 + ; ENTRY-UAS-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; ENTRY-UAS-NEXT: store i8 -8, ptr [[PTR]], align 1 - ; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 40, i8* %zz) + ; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 40, ptr %zz) ; CHECK: {{^[0-9]+}}: @@ -170,33 +170,33 @@ ; 00000000 ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0 - ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; EXIT-NEXT: store i32 0, ptr [[PTR]], align 1 ; 0000000000000000 ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 85 - ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; EXIT-NEXT: store i64 0, ptr [[PTR]], align 1 ; 0000000000000000 ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 93 - ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; EXIT-NEXT: store i64 0, ptr [[PTR]], align 1 ; 0000000000000000 ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 101 - ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i64]]* - ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; EXIT-NEXT: store i64 0, ptr [[PTR]], align 1 ; 00000000 ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 111 - ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i32]]* - ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; EXIT-NEXT: store i32 0, ptr [[PTR]], align 1 ; 00 ; EXIT-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 115 - ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to [[TYPE:i8]]* - ; EXIT-NEXT: store [[TYPE]] 0, [[TYPE]]* [[PTR]], align 1 + ; EXIT-NEXT: [[PTR:%[0-9]+]] = inttoptr i64 [[OFFSET]] to ptr + ; EXIT-NEXT: store i8 0, ptr [[PTR]], align 1 ; 0000... ; EXIT-UAS-NEXT: [[OFFSET:%[0-9]+]] = add i64 [[SHADOW_BASE]], 0 @@ -209,14 +209,12 @@ ; CHECK: ret void } -declare void @foo(i32*) +declare void @foo(ptr) define void @PR41481(i1 %b) sanitize_address { ; CHECK-LABEL: @PR41481 entry: %p1 = alloca i32 %p2 = alloca i32 - %q1 = bitcast i32* %p1 to i8* - %q2 = bitcast i32* %p2 to i8* br label %bb1 ; Since we cannot account for all lifetime intrinsics in this function, we @@ -226,18 +224,18 @@ ; ENTRY-UAS: store i64 -935356719533264399 bb1: - %p = select i1 %b, i32* %p1, i32* %p2 - %q = select i1 %b, i8* %q1, i8* %q2 - call void @llvm.lifetime.start.p0i8(i64 4, i8* %q) - call void @foo(i32* %p) + %p = select i1 %b, ptr %p1, ptr %p2 + %q = select i1 %b, ptr %p1, ptr %p2 + call void @llvm.lifetime.start.p0(i64 4, ptr %q) + call void @foo(ptr %p) br i1 %b, label %bb2, label %bb3 bb2: - call void @llvm.lifetime.end.p0i8(i64 4, i8* %q1) + call void @llvm.lifetime.end.p0(i64 4, ptr %p1) br label %end bb3: - call void @llvm.lifetime.end.p0i8(i64 4, i8* %q2) + call void @llvm.lifetime.end.p0(i64 4, ptr %p2) br label %end end: @@ -245,8 +243,8 @@ } -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) ; CHECK-ON: declare void @__asan_set_shadow_00(i64, i64) ; CHECK-ON: declare void @__asan_set_shadow_f1(i64, i64) diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-byval-args.ll b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-byval-args.ll --- a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-byval-args.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning-byval-args.ll @@ -10,23 +10,21 @@ %struct.A = type { [8 x i32] } -declare i32 @bar(%struct.A*) +declare i32 @bar(ptr) ; Test behavior for named argument with explicit alignment. The memcpy and ; alloca alignments should match the explicit alignment of 64. -define void @foo(%struct.A* byval(%struct.A) align 64 %a) sanitize_address { +define void @foo(ptr byval(%struct.A) align 64 %a) sanitize_address { entry: ; CHECK-LABEL: foo ; CHECK: call i64 @__asan_stack_malloc ; CHECK: alloca i8, i64 {{.*}} align 64 -; CHECK: [[copyPtr:%[^ \t]+]] = inttoptr i64 %{{[^ \t]+}} to %struct.A* -; CHECK: [[copyBytePtr:%[^ \t]+]] = bitcast %struct.A* [[copyPtr]] -; CHECK: [[aBytePtr:%[^ \t]+]] = bitcast %struct.A* %a -; CHECK: call void @llvm.memcpy{{[^%]+}}[[copyBytePtr]]{{[^%]+}} align 64 [[aBytePtr]],{{[^,]+}}, -; CHECK: call i32 @bar(%struct.A* [[copyPtr]]) +; CHECK: [[copyPtr:%[^ \t]+]] = inttoptr i64 %{{[^ \t]+}} to ptr +; CHECK: call void @llvm.memcpy{{[^%]+}}[[copyPtr]]{{[^%]+}} align 64 %a,{{[^,]+}}, +; CHECK: call i32 @bar(ptr [[copyPtr]]) ; CHECK: ret void - %call = call i32 @bar(%struct.A* %a) + %call = call i32 @bar(ptr %a) ret void } @@ -35,18 +33,16 @@ ; minimum alignment of 4 bytes since struct.A contains i32s which have 4-byte ; alignment. However, the alloca alignment will be 32 since that is the value ; passed via the -asan-realign-stack option, which is greater than 4. -define void @baz(%struct.A* byval(%struct.A)) sanitize_address { +define void @baz(ptr byval(%struct.A)) sanitize_address { entry: ; CHECK-LABEL: baz ; CHECK: call i64 @__asan_stack_malloc ; CHECK: alloca i8, i64 {{.*}} align 32 -; CHECK: [[copyPtr:%[^ \t]+]] = inttoptr i64 %{{[^ \t]+}} to %struct.A* -; CHECK: [[copyBytePtr:%[^ \t]+]] = bitcast %struct.A* [[copyPtr]] -; CHECK: [[aBytePtr:%[^ \t]+]] = bitcast %struct.A* %0 -; CHECK: call void @llvm.memcpy{{[^%]+}}[[copyBytePtr]]{{[^%]+}} align 4 [[aBytePtr]],{{[^,]+}} -; CHECK: call i32 @bar(%struct.A* [[copyPtr]]) +; CHECK: [[copyPtr:%[^ \t]+]] = inttoptr i64 %{{[^ \t]+}} to ptr +; CHECK: call void @llvm.memcpy{{[^%]+}}[[copyPtr]]{{[^%]+}} align 4 %0,{{[^,]+}} +; CHECK: call i32 @bar(ptr [[copyPtr]]) ; CHECK: ret void - %call = call i32 @bar(%struct.A* %0) + %call = call i32 @bar(ptr %0) ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning.ll b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning.ll --- a/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/stack-poisoning.ll @@ -4,7 +4,7 @@ target datalayout = "e-i64:64-f80:128-s:64-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare void @Foo(i8*) +declare void @Foo(ptr) define void @Bar() uwtable sanitize_address { entry: @@ -13,7 +13,7 @@ ; CHECK-PLAIN: ret void ; CHECK-UAR-LABEL: Bar -; CHECK-UAR-RUNTIME: load i32, i32* @__asan_option_detect_stack_use_after_return +; CHECK-UAR-RUNTIME: load i32, ptr @__asan_option_detect_stack_use_after_return ; CHECK-UAR-RUNTIME: label ; CHECK-UAR-RUNTIME: call i64 @__asan_stack_malloc_4 ; CHECK-UAR-ALWAYS: call i64 @__asan_stack_malloc_always_4 @@ -48,12 +48,9 @@ %x = alloca [20 x i8], align 16 %y = alloca [25 x i8], align 1 %z = alloca [500 x i8], align 1 - %xx = getelementptr inbounds [20 x i8], [20 x i8]* %x, i64 0, i64 0 - call void @Foo(i8* %xx) - %yy = getelementptr inbounds [25 x i8], [25 x i8]* %y, i64 0, i64 0 - call void @Foo(i8* %yy) - %zz = getelementptr inbounds [500 x i8], [500 x i8]* %z, i64 0, i64 0 - call void @Foo(i8* %zz) + call void @Foo(ptr %x) + call void @Foo(ptr %y) + call void @Foo(ptr %z) ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll b/llvm/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll --- a/llvm/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/stack_dynamic_alloca.ll @@ -20,8 +20,8 @@ ; CHECK-LABEL: Func1 ; CHECK: entry: -; CHECK-RUNTIME: load i32, i32* @__asan_option_detect_stack_use_after_return -; COM: CHECK-NORUNTIME-NOT: load i32, i32* @__asan_option_detect_stack_use_after_return +; CHECK-RUNTIME: load i32, ptr @__asan_option_detect_stack_use_after_return +; COM: CHECK-NORUNTIME-NOT: load i32, ptr @__asan_option_detect_stack_use_after_return ; CHECK-RUNTIME: [[UAR_ENABLED_BB:^[0-9]+]]: ; CHECK-RUNTIME: [[FAKE_STACK_RT:%[0-9]+]] = call i64 @__asan_stack_malloc_ @@ -34,7 +34,7 @@ ; CHECK: [[NO_FAKE_STACK_BB:^[0-9]+]]: ; CHECK: %MyAlloca = alloca i8, i64 -; CHECK: [[ALLOCA:%[0-9]+]] = ptrtoint i8* %MyAlloca +; CHECK: [[ALLOCA:%[0-9]+]] = ptrtoint ptr %MyAlloca ; CHECK-RUNTIME: phi i64 [ [[FAKE_STACK]], %[[FAKE_STACK_BB]] ], [ [[ALLOCA]], %[[NO_FAKE_STACK_BB]] ] ; CHECK-ALWAYS: phi i64 [ [[FAKE_STACK_RT]], %entry ], [ [[ALLOCA]], %[[NO_FAKE_STACK_BB]] ] @@ -42,8 +42,7 @@ ; CHECK: ret void %XXX = alloca [20 x i8], align 1 - %arr.ptr = bitcast [20 x i8]* %XXX to i8* - store volatile i8 0, i8* %arr.ptr + store volatile i8 0, ptr %XXX ret void } @@ -55,8 +54,7 @@ ; CHECK: ret void %XXX = alloca [20 x i8], align 1 - %arr.ptr = bitcast [20 x i8]* %XXX to i8* - store volatile i8 0, i8* %arr.ptr + store volatile i8 0, ptr %XXX call void asm sideeffect "mov %%rbx, %%rcx", "~{dirflag},~{fpsr},~{flags}"() nounwind ret void } @@ -75,19 +73,19 @@ ; CHECK: ret void entry: %a = alloca i32, align 4 - %call = call i32 @_setjmp(%struct.__jmp_buf_tag* getelementptr inbounds ([1 x %struct.__jmp_buf_tag], [1 x %struct.__jmp_buf_tag]* @_ZL3buf, i32 0, i32 0)) nounwind returns_twice + %call = call i32 @_setjmp(ptr @_ZL3buf) nounwind returns_twice %cmp = icmp eq i32 0, %call br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - call void @longjmp(%struct.__jmp_buf_tag* getelementptr inbounds ([1 x %struct.__jmp_buf_tag], [1 x %struct.__jmp_buf_tag]* @_ZL3buf, i32 0, i32 0), i32 1) noreturn nounwind + call void @longjmp(ptr @_ZL3buf, i32 1) noreturn nounwind unreachable if.end: ; preds = %entry - call void @_Z10escape_ptrPi(i32* %a) + call void @_Z10escape_ptrPi(ptr %a) ret void } -declare i32 @_setjmp(%struct.__jmp_buf_tag*) nounwind returns_twice -declare void @longjmp(%struct.__jmp_buf_tag*, i32) noreturn nounwind -declare void @_Z10escape_ptrPi(i32*) +declare i32 @_setjmp(ptr) nounwind returns_twice +declare void @longjmp(ptr, i32) noreturn nounwind +declare void @_Z10escape_ptrPi(ptr) diff --git a/llvm/test/Instrumentation/AddressSanitizer/stack_layout.ll b/llvm/test/Instrumentation/AddressSanitizer/stack_layout.ll --- a/llvm/test/Instrumentation/AddressSanitizer/stack_layout.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/stack_layout.ll @@ -8,9 +8,9 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare void @Use(i8*) -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) nounwind -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) nounwind +declare void @Use(ptr) +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) nounwind +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) nounwind ; CHECK: private unnamed_addr constant{{.*}}3 32 10 3 XXX 64 20 3 YYY 128 30 3 ZZZ\0 ; CHECK: private unnamed_addr constant{{.*}}3 32 5 3 AAA 64 55 3 BBB 160 555 3 CCC\0 @@ -30,12 +30,9 @@ %XXX = alloca [10 x i8], align 1 %YYY = alloca [20 x i8], align 1 %ZZZ = alloca [30 x i8], align 1 - %arr1.ptr = bitcast [10 x i8]* %XXX to i8* - store volatile i8 0, i8* %arr1.ptr - %arr2.ptr = bitcast [20 x i8]* %YYY to i8* - store volatile i8 0, i8* %arr2.ptr - %arr3.ptr = bitcast [30 x i8]* %ZZZ to i8* - store volatile i8 0, i8* %arr3.ptr + store volatile i8 0, ptr %XXX + store volatile i8 0, ptr %YYY + store volatile i8 0, ptr %ZZZ ret void } @@ -52,12 +49,9 @@ %AAA = alloca [5 x i8], align 1 %BBB = alloca [55 x i8], align 1 %CCC = alloca [555 x i8], align 1 - %arr1.ptr = bitcast [5 x i8]* %AAA to i8* - store volatile i8 0, i8* %arr1.ptr - %arr2.ptr = bitcast [55 x i8]* %BBB to i8* - store volatile i8 0, i8* %arr2.ptr - %arr3.ptr = bitcast [555 x i8]* %CCC to i8* - store volatile i8 0, i8* %arr3.ptr + store volatile i8 0, ptr %AAA + store volatile i8 0, ptr %BBB + store volatile i8 0, ptr %CCC ret void } @@ -75,12 +69,9 @@ %AAA = alloca [128 x i8], align 16 %BBB = alloca [128 x i8], align 64 %CCC = alloca [128 x i8], align 256 - %arr1.ptr = bitcast [128 x i8]* %AAA to i8* - store volatile i8 0, i8* %arr1.ptr - %arr2.ptr = bitcast [128 x i8]* %BBB to i8* - store volatile i8 0, i8* %arr2.ptr - %arr3.ptr = bitcast [128 x i8]* %CCC to i8* - store volatile i8 0, i8* %arr3.ptr + store volatile i8 0, ptr %AAA + store volatile i8 0, ptr %BBB + store volatile i8 0, ptr %CCC ret void } @@ -89,14 +80,12 @@ define void @Func5() sanitize_address #0 !dbg !11 { %AAA = alloca i32, align 4 ; File is not the same as !11 %BBB = alloca i32, align 4 ; File is the same as !11 - %BBB.ptr = bitcast i32* %BBB to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %BBB.ptr), !dbg !12 - store volatile i32 5, i32* %BBB, align 4 - %AAA.ptr = bitcast i32* %AAA to i8* - call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %AAA.ptr), !dbg !14 - store volatile i32 3, i32* %AAA, align 4 - call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %AAA.ptr), !dbg !17 - call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %BBB.ptr), !dbg !18 + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %BBB), !dbg !12 + store volatile i32 5, ptr %BBB, align 4 + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %AAA), !dbg !14 + store volatile i32 3, ptr %AAA, align 4 + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %AAA), !dbg !17 + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %BBB), !dbg !18 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/str-nobuiltin.ll b/llvm/test/Instrumentation/AddressSanitizer/str-nobuiltin.ll --- a/llvm/test/Instrumentation/AddressSanitizer/str-nobuiltin.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/str-nobuiltin.ll @@ -4,13 +4,13 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -declare i8* @memchr(i8* %a, i32 %b, i64 %c) -declare i32 @memcmp(i8* %a, i8* %b, i64 %c) -declare i32 @strcmp(i8* %a, i8* %b) -declare i8* @strcpy(i8* %a, i8* %b) -declare i8* @stpcpy(i8* %a, i8* %b) -declare i64 @strlen(i8* %a) -declare i64 @strnlen(i8* %a, i64 %b) +declare ptr @memchr(ptr %a, i32 %b, i64 %c) +declare i32 @memcmp(ptr %a, ptr %b, i64 %c) +declare i32 @strcmp(ptr %a, ptr %b) +declare ptr @strcpy(ptr %a, ptr %b) +declare ptr @stpcpy(ptr %a, ptr %b) +declare i64 @strlen(ptr %a) +declare i64 @strnlen(ptr %a, i64 %b) ; CHECK: call{{.*}}@memchr{{.*}} #[[ATTR:[0-9]+]] ; CHECK: call{{.*}}@memcmp{{.*}} #[[ATTR]] @@ -21,13 +21,13 @@ ; CHECK: call{{.*}}@strnlen{{.*}} #[[ATTR]] ; attributes #[[ATTR]] = { nobuiltin } -define void @f1(i8* %a, i8* %b) nounwind uwtable sanitize_address { - tail call i8* @memchr(i8* %a, i32 1, i64 12) - tail call i32 @memcmp(i8* %a, i8* %b, i64 12) - tail call i32 @strcmp(i8* %a, i8* %b) - tail call i8* @strcpy(i8* %a, i8* %b) - tail call i8* @stpcpy(i8* %a, i8* %b) - tail call i64 @strlen(i8* %a) - tail call i64 @strnlen(i8* %a, i64 12) +define void @f1(ptr %a, ptr %b) nounwind uwtable sanitize_address { + tail call ptr @memchr(ptr %a, i32 1, i64 12) + tail call i32 @memcmp(ptr %a, ptr %b, i64 12) + tail call i32 @strcmp(ptr %a, ptr %b) + tail call ptr @strcpy(ptr %a, ptr %b) + tail call ptr @stpcpy(ptr %a, ptr %b) + tail call i64 @strlen(ptr %a) + tail call i64 @strnlen(ptr %a, i64 12) ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/test64.ll b/llvm/test/Instrumentation/AddressSanitizer/test64.ll --- a/llvm/test/Instrumentation/AddressSanitizer/test64.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/test64.ll @@ -2,9 +2,9 @@ ; RUN: opt < %s -passes=asan -asan-mapping-scale=5 -S | FileCheck --check-prefixes=CHECK,CHECK-S5 %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define i32 @read_4_bytes(i32* %a) sanitize_address { +define i32 @read_4_bytes(ptr %a) sanitize_address { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } ; CHECK-LABEL: @read_4_bytes @@ -16,9 +16,9 @@ ; CHECK-S5-NEXT: add{{.*}}2147352576 ; CHECK: ret -define void @example_atomicrmw(i64* %ptr) nounwind uwtable sanitize_address { +define void @example_atomicrmw(ptr %ptr) nounwind uwtable sanitize_address { entry: - %0 = atomicrmw add i64* %ptr, i64 1 seq_cst + %0 = atomicrmw add ptr %ptr, i64 1 seq_cst ret void } @@ -30,9 +30,9 @@ ; CHECK: atomicrmw ; CHECK: ret -define void @example_cmpxchg(i64* %ptr, i64 %compare_to, i64 %new_value) nounwind uwtable sanitize_address { +define void @example_cmpxchg(ptr %ptr, i64 %compare_to, i64 %new_value) nounwind uwtable sanitize_address { entry: - %0 = cmpxchg i64* %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst + %0 = cmpxchg ptr %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/twice.ll b/llvm/test/Instrumentation/AddressSanitizer/twice.ll --- a/llvm/test/Instrumentation/AddressSanitizer/twice.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/twice.ll @@ -1,8 +1,8 @@ ; Check that the address sanitizer pass can be reused ; RUN: opt < %s -S -run-twice -passes=asan -define void @foo(i64* %b) nounwind uwtable sanitize_address { +define void @foo(ptr %b) nounwind uwtable sanitize_address { entry: - store i64 0, i64* %b, align 1 + store i64 0, ptr %b, align 1 ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/ubsan.ll b/llvm/test/Instrumentation/AddressSanitizer/ubsan.ll --- a/llvm/test/Instrumentation/AddressSanitizer/ubsan.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/ubsan.ll @@ -7,48 +7,47 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -%struct.A = type { i32 (...)** } -declare void @__ubsan_handle_dynamic_type_cache_miss(i8*, i64, i64) uwtable -declare void @__ubsan_handle_pointer_overflow(i8*, i64, i64) uwtable +%struct.A = type { ptr } +declare void @__ubsan_handle_dynamic_type_cache_miss(ptr, i64, i64) uwtable +declare void @__ubsan_handle_pointer_overflow(ptr, i64, i64) uwtable @__ubsan_vptr_type_cache = external global [128 x i64] @.src = private unnamed_addr constant [19 x i8] c"tmp/ubsan/vptr.cpp\00", align 1 @0 = private unnamed_addr constant { i16, i16, [4 x i8] } { i16 -1, i16 0, [4 x i8] c"'A'\00" } -@_ZTI1A = external constant i8* -@1 = private unnamed_addr global { { [19 x i8]*, i32, i32 }, { i16, i16, [4 x i8] }*, i8*, i8 } { { [19 x i8]*, i32, i32 } { [19 x i8]* @.src, i32 2, i32 18 }, { i16, i16, [4 x i8] }* @0, i8* bitcast (i8** @_ZTI1A to i8*), i8 4 } -@2 = private unnamed_addr global { { [19 x i8]*, i32, i32 } } { { [19 x i8]*, i32, i32 } { [19 x i8]* @.src, i32 24, i32 25 } } +@_ZTI1A = external constant ptr +@1 = private unnamed_addr global { { ptr, i32, i32 }, ptr, ptr, i8 } { { ptr, i32, i32 } { ptr @.src, i32 2, i32 18 }, ptr @0, ptr @_ZTI1A, i8 4 } +@2 = private unnamed_addr global { { ptr, i32, i32 } } { { ptr, i32, i32 } { ptr @.src, i32 24, i32 25 } } -define void @_Z3BarP1A(%struct.A* %a) uwtable sanitize_address { +define void @_Z3BarP1A(ptr %a) uwtable sanitize_address { ; CHECK-LABEL: define void @_Z3BarP1A entry: - %0 = bitcast %struct.A* %a to void (%struct.A*)*** - %vtable = load void (%struct.A*)**, void (%struct.A*)*** %0, align 8 + %vtable = load ptr, ptr %a, align 8 ; CHECK: __asan_report_load8 - %1 = load void (%struct.A*)*, void (%struct.A*)** %vtable, align 8 + %0 = load ptr, ptr %vtable, align 8 ; CHECK: __asan_report_load8 - %2 = ptrtoint void (%struct.A*)** %vtable to i64 - %3 = xor i64 %2, -303164226014115343, !nosanitize !0 - %4 = mul i64 %3, -7070675565921424023, !nosanitize !0 - %5 = lshr i64 %4, 47, !nosanitize !0 - %6 = xor i64 %4, %2, !nosanitize !0 - %7 = xor i64 %6, %5, !nosanitize !0 - %8 = mul i64 %7, -7070675565921424023, !nosanitize !0 - %9 = lshr i64 %8, 47, !nosanitize !0 - %10 = xor i64 %9, %8, !nosanitize !0 - %11 = mul i64 %10, -7070675565921424023, !nosanitize !0 - %12 = and i64 %11, 127, !nosanitize !0 - %13 = getelementptr inbounds [128 x i64], [128 x i64]* @__ubsan_vptr_type_cache, i64 0, i64 %12, !nosanitize !0 + %1 = ptrtoint ptr %vtable to i64 + %2 = xor i64 %1, -303164226014115343, !nosanitize !0 + %3 = mul i64 %2, -7070675565921424023, !nosanitize !0 + %4 = lshr i64 %3, 47, !nosanitize !0 + %5 = xor i64 %3, %1, !nosanitize !0 + %6 = xor i64 %5, %4, !nosanitize !0 + %7 = mul i64 %6, -7070675565921424023, !nosanitize !0 + %8 = lshr i64 %7, 47, !nosanitize !0 + %9 = xor i64 %8, %7, !nosanitize !0 + %10 = mul i64 %9, -7070675565921424023, !nosanitize !0 + %11 = and i64 %10, 127, !nosanitize !0 + %12 = getelementptr inbounds [128 x i64], ptr @__ubsan_vptr_type_cache, i64 0, i64 %11, !nosanitize !0 ; CHECK-NOT: __asan_report_load8 - %14 = load i64, i64* %13, align 8, !nosanitize !0 - %15 = icmp eq i64 %14, %11, !nosanitize !0 - br i1 %15, label %cont, label %handler.dynamic_type_cache_miss, !nosanitize !0 + %13 = load i64, ptr %12, align 8, !nosanitize !0 + %14 = icmp eq i64 %13, %10, !nosanitize !0 + br i1 %14, label %cont, label %handler.dynamic_type_cache_miss, !nosanitize !0 handler.dynamic_type_cache_miss: ; preds = %entry - %16 = ptrtoint %struct.A* %a to i64, !nosanitize !0 - tail call void @__ubsan_handle_dynamic_type_cache_miss(i8* bitcast ({ { [19 x i8]*, i32, i32 }, { i16, i16, [4 x i8] }*, i8*, i8 }* @1 to i8*), i64 %16, i64 %11) #2, !nosanitize !0 + %15 = ptrtoint ptr %a to i64, !nosanitize !0 + tail call void @__ubsan_handle_dynamic_type_cache_miss(ptr @1, i64 %15, i64 %10) #2, !nosanitize !0 br label %cont, !nosanitize !0 cont: ; preds = %handler.dynamic_type_cache_miss, %entry - tail call void %1(%struct.A* %a) + tail call void %0(ptr %a) ; CHECK: ret void ret void } @@ -57,19 +56,19 @@ ; NOCMP-LABEL: define void @_Z3foov entry: %bar = alloca [10 x i8], align 1 - %arrayidx = getelementptr inbounds [10 x i8], [10 x i8]* %bar, i64 0, i64 4 - %0 = ptrtoint [10 x i8]* %bar to i64, !nosanitize !0 + %arrayidx = getelementptr inbounds [10 x i8], ptr %bar, i64 0, i64 4 + %0 = ptrtoint ptr %bar to i64, !nosanitize !0 ; NOCMP-NOT: call void @__sanitizer_ptr_cmp - %1 = icmp ult [10 x i8]* %bar, inttoptr (i64 -4 to [10 x i8]*), !nosanitize !0 + %1 = icmp ult ptr %bar, inttoptr (i64 -4 to ptr), !nosanitize !0 br i1 %1, label %cont, label %handler.pointer_overflow, !nosanitize !0 handler.pointer_overflow: ; preds = %entry %2 = add i64 %0, 4, !nosanitize !0 - call void @__ubsan_handle_pointer_overflow(i8* bitcast ({ { [19 x i8]*, i32, i32 } }* @2 to i8*), i64 %0, i64 %2), !nosanitize !0 + call void @__ubsan_handle_pointer_overflow(ptr @2, i64 %0, i64 %2), !nosanitize !0 br label %cont, !nosanitize !0 cont: ; preds = %handler.pointer_overflow, %entry - store i8 0, i8* %arrayidx, align 1 + store i8 0, ptr %arrayidx, align 1 ; NOCMP: ret void ret void } diff --git a/llvm/test/Instrumentation/AddressSanitizer/win-sorted-sections.ll b/llvm/test/Instrumentation/AddressSanitizer/win-sorted-sections.ll --- a/llvm/test/Instrumentation/AddressSanitizer/win-sorted-sections.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/win-sorted-sections.ll @@ -18,35 +18,35 @@ $__crt_init_callback = comdat any $__crt_init_end = comdat any -@__pobjMapEntryFirst = weak_odr dso_local constant i8* null, section "ATL$__a", comdat, align 8 -@__pobjMapEntryMiddle = weak_odr dso_local constant i8* null, section "ATL$__m", comdat, align 8 -@__pobjMapEntryLast = weak_odr dso_local constant i8* null, section "ATL$__z", comdat, align 8 -@__crt_init_begin = weak_odr dso_local constant i8* null, section ".CRT$XCA", comdat, align 8 -@__crt_init_callback = weak_odr dso_local constant i8* null, section ".CRT$XCU", comdat, align 8 -@__crt_init_end = weak_odr dso_local constant i8* null, section ".CRT$XCZ", comdat, align 8 +@__pobjMapEntryFirst = weak_odr dso_local constant ptr null, section "ATL$__a", comdat, align 8 +@__pobjMapEntryMiddle = weak_odr dso_local constant ptr null, section "ATL$__m", comdat, align 8 +@__pobjMapEntryLast = weak_odr dso_local constant ptr null, section "ATL$__z", comdat, align 8 +@__crt_init_begin = weak_odr dso_local constant ptr null, section ".CRT$XCA", comdat, align 8 +@__crt_init_callback = weak_odr dso_local constant ptr null, section ".CRT$XCU", comdat, align 8 +@__crt_init_end = weak_odr dso_local constant ptr null, section ".CRT$XCZ", comdat, align 8 -; CHECK: @__pobjMapEntryFirst = weak_odr dso_local constant i8* null, section "ATL$__a", comdat, align 8 -; CHECK: @__pobjMapEntryMiddle = weak_odr dso_local constant i8* null, section "ATL$__m", comdat, align 8 -; CHECK: @__pobjMapEntryLast = weak_odr dso_local constant i8* null, section "ATL$__z", comdat, align 8 -; CHECK: @__crt_init_begin = weak_odr dso_local constant i8* null, section ".CRT$XCA", comdat, align 8 -; CHECK: @__crt_init_callback = weak_odr dso_local constant i8* null, section ".CRT$XCU", comdat, align 8 -; CHECK: @__crt_init_end = weak_odr dso_local constant i8* null, section ".CRT$XCZ", comdat, align 8 +; CHECK: @__pobjMapEntryFirst = weak_odr dso_local constant ptr null, section "ATL$__a", comdat, align 8 +; CHECK: @__pobjMapEntryMiddle = weak_odr dso_local constant ptr null, section "ATL$__m", comdat, align 8 +; CHECK: @__pobjMapEntryLast = weak_odr dso_local constant ptr null, section "ATL$__z", comdat, align 8 +; CHECK: @__crt_init_begin = weak_odr dso_local constant ptr null, section ".CRT$XCA", comdat, align 8 +; CHECK: @__crt_init_callback = weak_odr dso_local constant ptr null, section ".CRT$XCU", comdat, align 8 +; CHECK: @__crt_init_end = weak_odr dso_local constant ptr null, section ".CRT$XCZ", comdat, align 8 !llvm.asan.globals = !{!0, !2, !4, !6, !8, !10} !llvm.module.flags = !{!12, !13} !llvm.ident = !{!14} -!0 = !{i8** @__pobjMapEntryFirst, !1, !"__pobjMapEntryFirst", i1 false, i1 false} +!0 = !{ptr @__pobjMapEntryFirst, !1, !"__pobjMapEntryFirst", i1 false, i1 false} !1 = !{!"t.c", i32 6, i32 61} -!2 = !{i8** @__pobjMapEntryMiddle, !3, !"__pobjMapEntryMiddle", i1 false, i1 false} +!2 = !{ptr @__pobjMapEntryMiddle, !3, !"__pobjMapEntryMiddle", i1 false, i1 false} !3 = !{!"t.c", i32 7, i32 61} -!4 = !{i8** @__pobjMapEntryLast, !5, !"__pobjMapEntryLast", i1 false, i1 false} +!4 = !{ptr @__pobjMapEntryLast, !5, !"__pobjMapEntryLast", i1 false, i1 false} !5 = !{!"t.c", i32 8, i32 61} -!6 = !{i8** @__crt_init_begin, !7, !"__crt_init_begin", i1 false, i1 false} +!6 = !{ptr @__crt_init_begin, !7, !"__crt_init_begin", i1 false, i1 false} !7 = !{!"t.c", i32 16, i32 62} -!8 = !{i8** @__crt_init_callback, !9, !"__crt_init_callback", i1 false, i1 false} +!8 = !{ptr @__crt_init_callback, !9, !"__crt_init_callback", i1 false, i1 false} !9 = !{!"t.c", i32 17, i32 62} -!10 = !{i8** @__crt_init_end, !11, !"__crt_init_end", i1 false, i1 false} +!10 = !{ptr @__crt_init_end, !11, !"__crt_init_end", i1 false, i1 false} !11 = !{!"t.c", i32 18, i32 62} !12 = !{i32 1, !"wchar_size", i32 2} !13 = !{i32 7, !"PIC Level", i32 2} diff --git a/llvm/test/Instrumentation/AddressSanitizer/win-string-literal.ll b/llvm/test/Instrumentation/AddressSanitizer/win-string-literal.ll --- a/llvm/test/Instrumentation/AddressSanitizer/win-string-literal.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/win-string-literal.ll @@ -12,9 +12,8 @@ ; CHECK: @"__asan_global_??_C@_04JIHMPGLA@asdf?$AA@" = ; CHECK-SAME: private global { i64, i64, i64, i64, i64, i64, i64, i64 } -; CHECK-SAME: { i64 ptrtoint ({ [5 x i8], [27 x i8] }* @"??_C@_04JIHMPGLA@asdf?$AA@" to i64), -; CHECK-SAME: i64 5, i64 32, i64 ptrtoint ([7 x i8]* @___asan_gen_.1 to i64), i64 ptrtoint ([8 -; CHECK-SAME: x i8]* @___asan_gen_ to i64), i64 0, i64 0, i64 0 }, section ".ASAN$GL", +; CHECK-SAME: { i64 ptrtoint (ptr @"??_C@_04JIHMPGLA@asdf?$AA@" to i64), +; CHECK-SAME: i64 5, i64 32, i64 ptrtoint (ptr @___asan_gen_.1 to i64), i64 ptrtoint (ptr @___asan_gen_ to i64), i64 0, i64 0, i64 0 }, section ".ASAN$GL", ; CHECK-SAME: comdat($"??_C@_04JIHMPGLA@asdf?$AA@"), align 64 ; ModuleID = 't.cpp' @@ -27,9 +26,9 @@ @"??_C@_04JIHMPGLA@asdf?$AA@" = linkonce_odr dso_local unnamed_addr constant [5 x i8] c"asdf\00", comdat, align 1 ; Function Attrs: nounwind sanitize_address uwtable -define dso_local i8* @"?getstr@@YAPEBDXZ"() #0 { +define dso_local ptr @"?getstr@@YAPEBDXZ"() #0 { entry: - ret i8* getelementptr inbounds ([5 x i8], [5 x i8]* @"??_C@_04JIHMPGLA@asdf?$AA@", i32 0, i32 0) + ret ptr @"??_C@_04JIHMPGLA@asdf?$AA@" } attributes #0 = { nounwind sanitize_address uwtable } diff --git a/llvm/test/Instrumentation/AddressSanitizer/with-ifunc.ll b/llvm/test/Instrumentation/AddressSanitizer/with-ifunc.ll --- a/llvm/test/Instrumentation/AddressSanitizer/with-ifunc.ll +++ b/llvm/test/Instrumentation/AddressSanitizer/with-ifunc.ll @@ -21,27 +21,27 @@ ; CHECK-IFUNC: @__asan_shadow = external global [0 x i8] ; CHECK-NOIFUNC: @__asan_shadow_memory_dynamic_address = external global i32 -define i32 @test_load(i32* %a) sanitize_address { +define i32 @test_load(ptr %a) sanitize_address { ; First instrumentation in the function must be to load the dynamic shadow ; address into a local variable. ; CHECK-LABEL: @test_load ; CHECK: entry: -; CHECK-IFUNC-NEXT: %[[A:[^ ]*]] = ptrtoint i32* %a to i32 +; CHECK-IFUNC-NEXT: %[[A:[^ ]*]] = ptrtoint ptr %a to i32 ; CHECK-IFUNC-NEXT: %[[B:[^ ]*]] = lshr i32 %[[A]], 3 -; CHECK-IFUNC-NEXT: %[[C:[^ ]*]] = add i32 %[[B]], ptrtoint ([0 x i8]* @__asan_shadow to i32) +; CHECK-IFUNC-NEXT: %[[C:[^ ]*]] = add i32 %[[B]], ptrtoint (ptr @__asan_shadow to i32) -; CHECK-IFUNC-NOREMAT-NEXT: %[[S:[^ ]*]] = call i32 asm "", "=r,0"([0 x i8]* @__asan_shadow) -; CHECK-IFUNC-NOREMAT-NEXT: %[[A:[^ ]*]] = ptrtoint i32* %a to i32 +; CHECK-IFUNC-NOREMAT-NEXT: %[[S:[^ ]*]] = call i32 asm "", "=r,0"(ptr @__asan_shadow) +; CHECK-IFUNC-NOREMAT-NEXT: %[[A:[^ ]*]] = ptrtoint ptr %a to i32 ; CHECK-IFUNC-NOREMAT-NEXT: %[[B:[^ ]*]] = lshr i32 %[[A]], 3 ; CHECK-IFUNC-NOREMAT-NEXT: %[[C:[^ ]*]] = add i32 %[[B]], %[[S]] -; CHECK-NOIFUNC-NEXT: %[[SHADOW:[^ ]*]] = load i32, i32* @__asan_shadow_memory_dynamic_address -; CHECK-NOIFUNC-NEXT: %[[A:[^ ]*]] = ptrtoint i32* %a to i32 +; CHECK-NOIFUNC-NEXT: %[[SHADOW:[^ ]*]] = load i32, ptr @__asan_shadow_memory_dynamic_address +; CHECK-NOIFUNC-NEXT: %[[A:[^ ]*]] = ptrtoint ptr %a to i32 ; CHECK-NOIFUNC-NEXT: %[[B:[^ ]*]] = lshr i32 %[[A]], 3 ; CHECK-NOIFUNC-NEXT: %[[C:[^ ]*]] = add i32 %[[B]], %[[SHADOW]] entry: - %x = load i32, i32* %a, align 4 + %x = load i32, ptr %a, align 4 ret i32 %x } diff --git a/llvm/test/Instrumentation/BoundsChecking/many-trap.ll b/llvm/test/Instrumentation/BoundsChecking/many-trap.ll --- a/llvm/test/Instrumentation/BoundsChecking/many-trap.ll +++ b/llvm/test/Instrumentation/BoundsChecking/many-trap.ll @@ -5,8 +5,8 @@ ; CHECK: @f1 define void @f1(i64 %x) nounwind { %1 = alloca i128, i64 %x - %2 = load i128, i128* %1, align 4 - %3 = load i128, i128* %1, align 4 + %2 = load i128, ptr %1, align 4 + %3 = load i128, ptr %1, align 4 ret void ; CHECK: call void @llvm.trap() ; CHECK: call void @llvm.trap() diff --git a/llvm/test/Instrumentation/BoundsChecking/many-traps-2.ll b/llvm/test/Instrumentation/BoundsChecking/many-traps-2.ll --- a/llvm/test/Instrumentation/BoundsChecking/many-traps-2.ll +++ b/llvm/test/Instrumentation/BoundsChecking/many-traps-2.ll @@ -8,18 +8,18 @@ br label %bb19 bb20: - %_tmp819 = load i16, i16* null + %_tmp819 = load i16, ptr null ; CHECK: br {{.*}} %trap %_tmp820 = sub nsw i16 9, %_tmp819 %_tmp821 = sext i16 %_tmp820 to i64 - %_tmp822 = getelementptr [10 x i16], [10 x i16]* @offsets, i16 0, i64 %_tmp821 - %_tmp823 = load i16, i16* %_tmp822 + %_tmp822 = getelementptr [10 x i16], ptr @offsets, i16 0, i64 %_tmp821 + %_tmp823 = load i16, ptr %_tmp822 br label %bb33 bb34: %_tmp907 = zext i16 %i__7.107.0 to i64 - %_tmp908 = getelementptr [1819 x i16], [1819 x i16]* @array, i16 0, i64 %_tmp907 - store i16 0, i16* %_tmp908 + %_tmp908 = getelementptr [1819 x i16], ptr @array, i16 0, i64 %_tmp907 + store i16 0, ptr %_tmp908 ; CHECK: br {{.*}} %trap %_tmp910 = add i16 %i__7.107.0, 1 br label %bb33 @@ -47,15 +47,15 @@ while.cond1.preheader: %0 = phi i16 [ undef, %entry ], [ %inc, %while.end ] - %1 = load i16, i16* undef, align 1 + %1 = load i16, ptr undef, align 1 ; CHECK: br {{.*}} %trap br label %while.end while.end: %inc = add nsw i16 %0, 1 - %arrayidx = getelementptr inbounds [1 x i16], [1 x i16]* @e, i16 0, i16 + %arrayidx = getelementptr inbounds [1 x i16], ptr @e, i16 0, i16 %0 - %2 = load i16, i16* %arrayidx, align 1 + %2 = load i16, ptr %arrayidx, align 1 ; CHECK: or i1 ; CHECK-NEXT: br {{.*}} %trap br i1 false, label %while.end6, label %while.cond1.preheader diff --git a/llvm/test/Instrumentation/BoundsChecking/nosanitize-bounds.ll b/llvm/test/Instrumentation/BoundsChecking/nosanitize-bounds.ll --- a/llvm/test/Instrumentation/BoundsChecking/nosanitize-bounds.ll +++ b/llvm/test/Instrumentation/BoundsChecking/nosanitize-bounds.ll @@ -6,11 +6,11 @@ entry: %i.addr = alloca i32, align 4 %b = alloca [64 x i32], align 16 - store i32 %i, i32* %i.addr, align 4 - %0 = load i32, i32* %i.addr, align 4 + store i32 %i, ptr %i.addr, align 4 + %0 = load i32, ptr %i.addr, align 4 %idxprom = sext i32 %0 to i64 - %arrayidx = getelementptr inbounds [64 x i32], [64 x i32]* %b, i64 0, i64 %idxprom - %1 = load i32, i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds [64 x i32], ptr %b, i64 0, i64 %idxprom + %1 = load i32, ptr %arrayidx, align 4 ret i32 %1 ; CHECK-NOT: call void @llvm.trap() } diff --git a/llvm/test/Instrumentation/BoundsChecking/opt.ll b/llvm/test/Instrumentation/BoundsChecking/opt.ll --- a/llvm/test/Instrumentation/BoundsChecking/opt.ll +++ b/llvm/test/Instrumentation/BoundsChecking/opt.ll @@ -5,61 +5,57 @@ define dso_local i32 @sumSize(i32 %n) { entry: %foo = alloca [1000 x i32], align 16 - %0 = bitcast [1000 x i32]* %foo to i8* - call void @llvm.lifetime.start.p0i8(i64 4000, i8* nonnull %0) - %arraydecay = getelementptr inbounds [1000 x i32], [1000 x i32]* %foo, i64 0, i64 0 - call void @fill(i32* nonnull %arraydecay, i32 %n) + call void @llvm.lifetime.start.p0(i64 4000, ptr nonnull %foo) + call void @fill(ptr nonnull %foo, i32 %n) br label %for.body.i for.body.i: ; preds = %for.body.i, %entry %indvars.iv.i = phi i64 [ 0, %entry ], [ %indvars.iv.next.i, %for.body.i ] %sum.07.i = phi i32 [ 0, %entry ], [ %add.i, %for.body.i ] - %arrayidx.i = getelementptr inbounds [1000 x i32], [1000 x i32]* %foo, i64 0, i64 %indvars.iv.i + %arrayidx.i = getelementptr inbounds [1000 x i32], ptr %foo, i64 0, i64 %indvars.iv.i ; CHECK-NOT: trap - %1 = load i32, i32* %arrayidx.i, align 4 - %add.i = add nsw i32 %1, %sum.07.i + %0 = load i32, ptr %arrayidx.i, align 4 + %add.i = add nsw i32 %0, %sum.07.i %indvars.iv.next.i = add nuw nsw i64 %indvars.iv.i, 1 %exitcond.i = icmp eq i64 %indvars.iv.next.i, 1000 br i1 %exitcond.i, label %accumulate.exit, label %for.body.i accumulate.exit: ; preds = %for.body.i - call void @llvm.lifetime.end.p0i8(i64 4000, i8* nonnull %0) + call void @llvm.lifetime.end.p0(i64 4000, ptr nonnull %foo) ret i32 %add.i } -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) -declare dso_local void @fill(i32*, i32) +declare dso_local void @fill(ptr, i32) -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) ; CHECK-LABEL: @sumSizePlusOne define dso_local i32 @sumSizePlusOne(i32 %n) { entry: %foo = alloca [1000 x i32], align 16 - %0 = bitcast [1000 x i32]* %foo to i8* - call void @llvm.lifetime.start.p0i8(i64 4000, i8* nonnull %0) - %arraydecay = getelementptr inbounds [1000 x i32], [1000 x i32]* %foo, i64 0, i64 0 - call void @fill(i32* nonnull %arraydecay, i32 %n) + call void @llvm.lifetime.start.p0(i64 4000, ptr nonnull %foo) + call void @fill(ptr nonnull %foo, i32 %n) br label %for.body.i for.body.i: ; preds = %for.body.i, %entry %indvars.iv.i = phi i64 [ 0, %entry ], [ %indvars.iv.next.i, %for.body.i ] %sum.01.i = phi i32 [ 0, %entry ], [ %add.i, %for.body.i ] - %arrayidx.i = getelementptr inbounds [1000 x i32], [1000 x i32]* %foo, i64 0, i64 %indvars.iv.i + %arrayidx.i = getelementptr inbounds [1000 x i32], ptr %foo, i64 0, i64 %indvars.iv.i ; CHECK: mul i64 {{.*}}, 4 ; CHECK: sub i64 4000, % ; CHECK-NEXT: icmp ult i64 {{.*}}, 4 ; CHECK-NEXT: or i1 ; CHECK: trap - %1 = load i32, i32* %arrayidx.i, align 4 - %add.i = add nsw i32 %1, %sum.01.i + %0 = load i32, ptr %arrayidx.i, align 4 + %add.i = add nsw i32 %0, %sum.01.i %indvars.iv.next.i = add nuw nsw i64 %indvars.iv.i, 1 %exitcond.i = icmp eq i64 %indvars.iv.next.i, 1001 br i1 %exitcond.i, label %accumulate.exit, label %for.body.i accumulate.exit: ; preds = %for.body.i - call void @llvm.lifetime.end.p0i8(i64 4000, i8* nonnull %0) + call void @llvm.lifetime.end.p0(i64 4000, ptr nonnull %foo) ret i32 %add.i } @@ -67,30 +63,28 @@ define dso_local i32 @sumLarger(i32 %n) { entry: %foo = alloca [1000 x i32], align 16 - %0 = bitcast [1000 x i32]* %foo to i8* - call void @llvm.lifetime.start.p0i8(i64 4000, i8* nonnull %0) - %arraydecay = getelementptr inbounds [1000 x i32], [1000 x i32]* %foo, i64 0, i64 0 - call void @fill(i32* nonnull %arraydecay, i32 %n) + call void @llvm.lifetime.start.p0(i64 4000, ptr nonnull %foo) + call void @fill(ptr nonnull %foo, i32 %n) br label %for.body.i for.body.i: ; preds = %for.body.i, %entry %indvars.iv.i = phi i64 [ 0, %entry ], [ %indvars.iv.next.i, %for.body.i ] %sum.07.i = phi i32 [ 0, %entry ], [ %add.i, %for.body.i ] - %arrayidx.i = getelementptr inbounds [1000 x i32], [1000 x i32]* %foo, i64 0, i64 %indvars.iv.i + %arrayidx.i = getelementptr inbounds [1000 x i32], ptr %foo, i64 0, i64 %indvars.iv.i ; CHECK: mul i64 {{.*}}, 4 ; CHECK: sub i64 4000, % ; CHECK-NEXT: icmp ult i64 4000, % ; CHECK-NEXT: icmp ult i64 {{.*}}, 4 ; CHECK-NEXT: or i1 ; CHECK: trap - %1 = load i32, i32* %arrayidx.i, align 4 - %add.i = add nsw i32 %1, %sum.07.i + %0 = load i32, ptr %arrayidx.i, align 4 + %add.i = add nsw i32 %0, %sum.07.i %indvars.iv.next.i = add nuw nsw i64 %indvars.iv.i, 1 %exitcond.i = icmp eq i64 %indvars.iv.next.i, 2000 br i1 %exitcond.i, label %accumulate.exit, label %for.body.i accumulate.exit: ; preds = %for.body.i - call void @llvm.lifetime.end.p0i8(i64 4000, i8* nonnull %0) + call void @llvm.lifetime.end.p0(i64 4000, ptr nonnull %foo) ret i32 %add.i } @@ -98,10 +92,8 @@ define dso_local i32 @sumUnknown(i32 %n) { entry: %foo = alloca [1000 x i32], align 16 - %0 = bitcast [1000 x i32]* %foo to i8* - call void @llvm.lifetime.start.p0i8(i64 4000, i8* nonnull %0) - %arraydecay = getelementptr inbounds [1000 x i32], [1000 x i32]* %foo, i64 0, i64 0 - call void @fill(i32* nonnull %arraydecay, i32 %n) + call void @llvm.lifetime.start.p0(i64 4000, ptr nonnull %foo) + call void @fill(ptr nonnull %foo, i32 %n) %cmp6.i = icmp eq i32 %n, 0 br i1 %cmp6.i, label %accumulate.exit, label %for.body.preheader.i @@ -112,22 +104,22 @@ for.body.i: ; preds = %for.body.i, %for.body.preheader.i %indvars.iv.i = phi i64 [ 0, %for.body.preheader.i ], [ %indvars.iv.next.i, %for.body.i ] %sum.07.i = phi i32 [ 0, %for.body.preheader.i ], [ %add.i, %for.body.i ] - %arrayidx.i = getelementptr inbounds [1000 x i32], [1000 x i32]* %foo, i64 0, i64 %indvars.iv.i + %arrayidx.i = getelementptr inbounds [1000 x i32], ptr %foo, i64 0, i64 %indvars.iv.i ; CHECK: mul i64 {{.*}}, 4 ; CHECK: sub i64 4000, % ; CHECK-NEXT: icmp ult i64 4000, % ; CHECK-NEXT: icmp ult i64 {{.*}}, 4 ; CHECK-NEXT: or i1 ; CHECK: trap - %1 = load i32, i32* %arrayidx.i, align 4 - %add.i = add nsw i32 %1, %sum.07.i + %0 = load i32, ptr %arrayidx.i, align 4 + %add.i = add nsw i32 %0, %sum.07.i %indvars.iv.next.i = add nuw nsw i64 %indvars.iv.i, 1 %exitcond.i = icmp eq i64 %indvars.iv.next.i, %wide.trip.count.i br i1 %exitcond.i, label %accumulate.exit, label %for.body.i accumulate.exit: ; preds = %for.body.i, %entry %sum.0.lcssa.i = phi i32 [ 0, %entry ], [ %add.i, %for.body.i ] - call void @llvm.lifetime.end.p0i8(i64 4000, i8* nonnull %0) + call void @llvm.lifetime.end.p0(i64 4000, ptr nonnull %foo) ret i32 %sum.0.lcssa.i } @@ -135,10 +127,8 @@ define dso_local i32 @twoDimSize(i32 %n) { entry: %foo = alloca [2 x [2 x i32]], align 16 - %0 = bitcast [2 x [2 x i32]]* %foo to i8* - call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %0) - %arraydecay = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %foo, i64 0, i64 0, i64 0 - call void @fill(i32* nonnull %arraydecay, i32 %n) + call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %foo) + call void @fill(ptr nonnull %foo, i32 %n) br label %for.cond1.preheader for.cond1.preheader: ; preds = %for.cond.cleanup3, %entry @@ -147,7 +137,7 @@ br label %for.body4 for.cond.cleanup: ; preds = %for.cond.cleanup3 - call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %0) + call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %foo) ret i32 %add for.cond.cleanup3: ; preds = %for.body4 @@ -158,10 +148,10 @@ for.body4: ; preds = %for.body4, %for.cond1.preheader %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body4 ] %sum.119 = phi i32 [ %sum.021, %for.cond1.preheader ], [ %add, %for.body4 ] - %arrayidx7 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %foo, i64 0, i64 %indvars.iv23, i64 %indvars.iv + %arrayidx7 = getelementptr inbounds [2 x [2 x i32]], ptr %foo, i64 0, i64 %indvars.iv23, i64 %indvars.iv ; CHECK-NOT: trap - %1 = load i32, i32* %arrayidx7, align 4 - %add = add nsw i32 %1, %sum.119 + %0 = load i32, ptr %arrayidx7, align 4 + %add = add nsw i32 %0, %sum.119 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %exitcond = icmp eq i64 %indvars.iv.next, 2 br i1 %exitcond, label %for.cond.cleanup3, label %for.body4 @@ -171,10 +161,8 @@ define dso_local i32 @twoDimLarger1(i32 %n) { entry: %foo = alloca [2 x [2 x i32]], align 16 - %0 = bitcast [2 x [2 x i32]]* %foo to i8* - call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %0) - %arraydecay = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %foo, i64 0, i64 0, i64 0 - call void @fill(i32* nonnull %arraydecay, i32 %n) + call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %foo) + call void @fill(ptr nonnull %foo, i32 %n) br label %for.cond1.preheader for.cond1.preheader: ; preds = %for.cond.cleanup3, %entry @@ -183,7 +171,7 @@ br label %for.body4 for.cond.cleanup: ; preds = %for.cond.cleanup3 - call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %0) + call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %foo) ret i32 %add for.cond.cleanup3: ; preds = %for.body4 @@ -194,7 +182,7 @@ for.body4: ; preds = %for.body4, %for.cond1.preheader %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body4 ] %sum.119 = phi i32 [ %sum.021, %for.cond1.preheader ], [ %add, %for.body4 ] - %arrayidx7 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %foo, i64 0, i64 %indvars.iv23, i64 %indvars.iv + %arrayidx7 = getelementptr inbounds [2 x [2 x i32]], ptr %foo, i64 0, i64 %indvars.iv23, i64 %indvars.iv ; CHECK: mul i64 {{.*}}, 8 ; CHECK: mul i64 {{.*}}, 4 ; CHECK: add i64 @@ -203,8 +191,8 @@ ; CHECK-NEXT: icmp ult i64 {{.*}}, 4 ; CHECK-NEXT: or i1 ; CHECK: trap - %1 = load i32, i32* %arrayidx7, align 4 - %add = add nsw i32 %1, %sum.119 + %0 = load i32, ptr %arrayidx7, align 4 + %add = add nsw i32 %0, %sum.119 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %exitcond = icmp eq i64 %indvars.iv.next, 2 br i1 %exitcond, label %for.cond.cleanup3, label %for.body4 @@ -214,10 +202,8 @@ define dso_local i32 @twoDimLarger2(i32 %n) { entry: %foo = alloca [2 x [2 x i32]], align 16 - %0 = bitcast [2 x [2 x i32]]* %foo to i8* - call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %0) - %arraydecay = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %foo, i64 0, i64 0, i64 0 - call void @fill(i32* nonnull %arraydecay, i32 %n) + call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %foo) + call void @fill(ptr nonnull %foo, i32 %n) br label %for.cond1.preheader for.cond1.preheader: ; preds = %for.cond.cleanup3, %entry @@ -226,7 +212,7 @@ br label %for.body4 for.cond.cleanup: ; preds = %for.cond.cleanup3 - call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %0) + call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %foo) ret i32 %add for.cond.cleanup3: ; preds = %for.body4 @@ -237,7 +223,7 @@ for.body4: ; preds = %for.body4, %for.cond1.preheader %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.body4 ] %sum.119 = phi i32 [ %sum.021, %for.cond1.preheader ], [ %add, %for.body4 ] - %arrayidx7 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %foo, i64 0, i64 %indvars.iv23, i64 %indvars.iv + %arrayidx7 = getelementptr inbounds [2 x [2 x i32]], ptr %foo, i64 0, i64 %indvars.iv23, i64 %indvars.iv ; CHECK: mul i64 {{.*}}, 8 ; CHECK: mul i64 {{.*}}, 4 ; CHECK: add i64 @@ -245,8 +231,8 @@ ; CHECK-NEXT: icmp ult i64 {{.*}}, 4 ; CHECK-NEXT: or i1 ; CHECK: trap - %1 = load i32, i32* %arrayidx7, align 4 - %add = add nsw i32 %1, %sum.119 + %0 = load i32, ptr %arrayidx7, align 4 + %add = add nsw i32 %0, %sum.119 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %exitcond = icmp eq i64 %indvars.iv.next, 3 br i1 %exitcond, label %for.cond.cleanup3, label %for.body4 @@ -256,10 +242,8 @@ define dso_local i32 @twoDimUnknown(i32 %n) { entry: %foo = alloca [2 x [2 x i32]], align 16 - %0 = bitcast [2 x [2 x i32]]* %foo to i8* - call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull %0) - %arraydecay = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %foo, i64 0, i64 0, i64 0 - call void @fill(i32* nonnull %arraydecay, i32 %n) + call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %foo) + call void @fill(ptr nonnull %foo, i32 %n) %cmp24 = icmp eq i32 %n, 0 br i1 %cmp24, label %for.cond.cleanup, label %for.cond1.preheader.lr.ph @@ -275,7 +259,7 @@ for.cond.cleanup: ; preds = %for.cond.cleanup3, %entry %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.cond.cleanup3 ] - call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull %0) + call void @llvm.lifetime.end.p0(i64 16, ptr nonnull %foo) ret i32 %sum.0.lcssa for.cond.cleanup3: ; preds = %for.body4 @@ -286,7 +270,7 @@ for.body4: ; preds = %for.body4, %for.body4.lr.ph %indvars.iv = phi i64 [ 0, %for.body4.lr.ph ], [ %indvars.iv.next, %for.body4 ] %sum.122 = phi i32 [ %sum.025, %for.body4.lr.ph ], [ %add, %for.body4 ] - %arrayidx7 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %foo, i64 0, i64 %indvars.iv28, i64 %indvars.iv + %arrayidx7 = getelementptr inbounds [2 x [2 x i32]], ptr %foo, i64 0, i64 %indvars.iv28, i64 %indvars.iv ; CHECK: mul i64 {{.*}}, 8 ; CHECK: mul i64 {{.*}}, 4 ; CHECK: add i64 @@ -295,8 +279,8 @@ ; CHECK-NEXT: icmp ult i64 {{.*}}, 4 ; CHECK-NEXT: or i1 ; CHECK: trap - %1 = load i32, i32* %arrayidx7, align 4 - %add = add nsw i32 %1, %sum.122 + %0 = load i32, ptr %arrayidx7, align 4 + %add = add nsw i32 %0, %sum.122 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 %exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count br i1 %exitcond, label %for.cond.cleanup3, label %for.body4 @@ -306,23 +290,21 @@ define dso_local i32 @countDownGood(i32 %n) { entry: %foo = alloca [1000 x i32], align 16 - %0 = bitcast [1000 x i32]* %foo to i8* - call void @llvm.lifetime.start.p0i8(i64 4000, i8* nonnull %0) - %arraydecay = getelementptr inbounds [1000 x i32], [1000 x i32]* %foo, i64 0, i64 0 - call void @fill(i32* nonnull %arraydecay, i32 %n) + call void @llvm.lifetime.start.p0(i64 4000, ptr nonnull %foo) + call void @fill(ptr nonnull %foo, i32 %n) br label %for.body for.cond.cleanup: ; preds = %for.body - call void @llvm.lifetime.end.p0i8(i64 4000, i8* nonnull %0) + call void @llvm.lifetime.end.p0(i64 4000, ptr nonnull %foo) ret i32 %add for.body: ; preds = %for.body, %entry %indvars.iv = phi i64 [ 999, %entry ], [ %indvars.iv.next, %for.body ] %sum.06 = phi i32 [ 0, %entry ], [ %add, %for.body ] - %arrayidx = getelementptr inbounds [1000 x i32], [1000 x i32]* %foo, i64 0, i64 %indvars.iv + %arrayidx = getelementptr inbounds [1000 x i32], ptr %foo, i64 0, i64 %indvars.iv ; CHECK-NOT: trap - %1 = load i32, i32* %arrayidx, align 4 - %add = add nsw i32 %1, %sum.06 + %0 = load i32, ptr %arrayidx, align 4 + %add = add nsw i32 %0, %sum.06 %indvars.iv.next = add nsw i64 %indvars.iv, -1 %cmp = icmp eq i64 %indvars.iv, 0 br i1 %cmp, label %for.cond.cleanup, label %for.body @@ -332,26 +314,24 @@ define dso_local i32 @countDownBad(i32 %n) { entry: %foo = alloca [1000 x i32], align 16 - %0 = bitcast [1000 x i32]* %foo to i8* - call void @llvm.lifetime.start.p0i8(i64 4000, i8* nonnull %0) - %arraydecay = getelementptr inbounds [1000 x i32], [1000 x i32]* %foo, i64 0, i64 0 - call void @fill(i32* nonnull %arraydecay, i32 %n) + call void @llvm.lifetime.start.p0(i64 4000, ptr nonnull %foo) + call void @fill(ptr nonnull %foo, i32 %n) br label %for.body for.cond.cleanup: ; preds = %for.body - call void @llvm.lifetime.end.p0i8(i64 4000, i8* nonnull %0) + call void @llvm.lifetime.end.p0(i64 4000, ptr nonnull %foo) ret i32 %add for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ 999, %entry ], [ %indvars.iv.next, %for.body ] %sum.06 = phi i32 [ 0, %entry ], [ %add, %for.body ] - %arrayidx = getelementptr inbounds [1000 x i32], [1000 x i32]* %foo, i64 0, i64 %indvars.iv + %arrayidx = getelementptr inbounds [1000 x i32], ptr %foo, i64 0, i64 %indvars.iv ; CHECK: mul i64 {{.*}}, 4 ; CHECK: sub i64 4000, % ; CHECK-NEXT: icmp ult i64 4000, % ; CHECK: trap - %1 = load i32, i32* %arrayidx, align 4 - %add = add nsw i32 %1, %sum.06 + %0 = load i32, ptr %arrayidx, align 4 + %add = add nsw i32 %0, %sum.06 %indvars.iv.next = add nsw i64 %indvars.iv, -1 %cmp = icmp sgt i64 %indvars.iv, -1 br i1 %cmp, label %for.body, label %for.cond.cleanup diff --git a/llvm/test/Instrumentation/BoundsChecking/phi.ll b/llvm/test/Instrumentation/BoundsChecking/phi.ll --- a/llvm/test/Instrumentation/BoundsChecking/phi.ll +++ b/llvm/test/Instrumentation/BoundsChecking/phi.ll @@ -6,17 +6,17 @@ ; CHECK: f1 ; no checks are possible here ; CHECK-NOT: trap -define void @f1(i8* nocapture %c) { +define void @f1(ptr nocapture %c) { entry: - %0 = load i8, i8* %c, align 1 + %0 = load i8, ptr %c, align 1 %tobool1 = icmp eq i8 %0, 0 br i1 %tobool1, label %while.end, label %while.body while.body: - %c.addr.02 = phi i8* [ %incdec.ptr, %while.body ], [ %c, %entry ] - %incdec.ptr = getelementptr inbounds i8, i8* %c.addr.02, i64 -1 - store i8 100, i8* %c.addr.02, align 1 - %1 = load i8, i8* %incdec.ptr, align 1 + %c.addr.02 = phi ptr [ %incdec.ptr, %while.body ], [ %c, %entry ] + %incdec.ptr = getelementptr inbounds i8, ptr %c.addr.02, i64 -1 + store i8 100, ptr %c.addr.02, align 1 + %1 = load i8, ptr %incdec.ptr, align 1 %tobool = icmp eq i8 %1, 0 br i1 %tobool, label %while.end, label %while.body @@ -28,22 +28,22 @@ ; CHECK: f2 define void @f2() { while.body.i.preheader: - %addr = getelementptr inbounds [10 x i8], [10 x i8]* @global, i64 0, i64 9 + %addr = getelementptr inbounds [10 x i8], ptr @global, i64 0, i64 9 br label %while.body.i while.body.i: ; CHECK: phi ; CHECK-NEXT: phi ; CHECK-NOT: phi - %c.addr.02.i = phi i8* [ %incdec.ptr.i, %while.body.i ], [ %addr, %while.body.i.preheader ] - %incdec.ptr.i = getelementptr inbounds i8, i8* %c.addr.02.i, i64 -1 + %c.addr.02.i = phi ptr [ %incdec.ptr.i, %while.body.i ], [ %addr, %while.body.i.preheader ] + %incdec.ptr.i = getelementptr inbounds i8, ptr %c.addr.02.i, i64 -1 ; CHECK: sub i64 10, %0 ; CHECK-NEXT: icmp ult i64 10, %0 ; CHECK-NEXT: icmp ult i64 {{.*}}, 1 ; CHECK-NEXT: or i1 ; CHECK-NEXT: br {{.*}}, label %trap - store i8 100, i8* %c.addr.02.i, align 1 - %0 = load i8, i8* %incdec.ptr.i, align 1 + store i8 100, ptr %c.addr.02.i, align 1 + %0 = load i8, ptr %incdec.ptr.i, align 1 %tobool.i = icmp eq i8 %0, 0 br i1 %tobool.i, label %fn.exit, label %while.body.i @@ -54,20 +54,20 @@ @global_as1 = private unnamed_addr addrspace(1) constant [10 x i8] c"ola\00mundo\00", align 1 -define void @f1_as1(i8 addrspace(1)* nocapture %c) { +define void @f1_as1(ptr addrspace(1) nocapture %c) { ; CHECK: @f1_as1 ; no checks are possible here ; CHECK-NOT: trap entry: - %0 = load i8, i8 addrspace(1)* %c, align 1 + %0 = load i8, ptr addrspace(1) %c, align 1 %tobool1 = icmp eq i8 %0, 0 br i1 %tobool1, label %while.end, label %while.body while.body: - %c.addr.02 = phi i8 addrspace(1)* [ %incdec.ptr, %while.body ], [ %c, %entry ] - %incdec.ptr = getelementptr inbounds i8, i8 addrspace(1)* %c.addr.02, i64 -1 - store i8 100, i8 addrspace(1)* %c.addr.02, align 1 - %1 = load i8, i8 addrspace(1)* %incdec.ptr, align 1 + %c.addr.02 = phi ptr addrspace(1) [ %incdec.ptr, %while.body ], [ %c, %entry ] + %incdec.ptr = getelementptr inbounds i8, ptr addrspace(1) %c.addr.02, i64 -1 + store i8 100, ptr addrspace(1) %c.addr.02, align 1 + %1 = load i8, ptr addrspace(1) %incdec.ptr, align 1 %tobool = icmp eq i8 %1, 0 br i1 %tobool, label %while.end, label %while.body @@ -79,22 +79,22 @@ define void @f2_as1() { ; CHECK: @f2_as1 while.body.i.preheader: - %addr = getelementptr inbounds [10 x i8], [10 x i8] addrspace(1)* @global_as1, i16 0, i16 9 + %addr = getelementptr inbounds [10 x i8], ptr addrspace(1) @global_as1, i16 0, i16 9 br label %while.body.i while.body.i: ; CHECK: phi ; CHECK-NEXT: phi ; CHECK-NOT: phi - %c.addr.02.i = phi i8 addrspace(1)* [ %incdec.ptr.i, %while.body.i ], [ %addr, %while.body.i.preheader ] - %incdec.ptr.i = getelementptr inbounds i8, i8 addrspace(1)* %c.addr.02.i, i16 -1 + %c.addr.02.i = phi ptr addrspace(1) [ %incdec.ptr.i, %while.body.i ], [ %addr, %while.body.i.preheader ] + %incdec.ptr.i = getelementptr inbounds i8, ptr addrspace(1) %c.addr.02.i, i16 -1 ; CHECK: sub i16 10, %0 ; CHECK-NEXT: icmp ult i16 10, %0 ; CHECK-NEXT: icmp ult i16 {{.*}}, 1 ; CHECK-NEXT: or i1 ; CHECK-NEXT: br {{.*}}, label %trap - store i8 100, i8 addrspace(1)* %c.addr.02.i, align 1 - %0 = load i8, i8 addrspace(1)* %incdec.ptr.i, align 1 + store i8 100, ptr addrspace(1) %c.addr.02.i, align 1 + %0 = load i8, ptr addrspace(1) %incdec.ptr.i, align 1 %tobool.i = icmp eq i8 %0, 0 br i1 %tobool.i, label %fn.exit, label %while.body.i diff --git a/llvm/test/Instrumentation/BoundsChecking/simple-32.ll b/llvm/test/Instrumentation/BoundsChecking/simple-32.ll --- a/llvm/test/Instrumentation/BoundsChecking/simple-32.ll +++ b/llvm/test/Instrumentation/BoundsChecking/simple-32.ll @@ -9,9 +9,8 @@ define i16 @f() { entry: %packed1 = alloca %struct.s2_packed, align 8 - %gep = getelementptr inbounds %struct.s2_packed, %struct.s2_packed* %packed1, i32 0, i32 4 - %ptr = bitcast i16* %gep to i32* - %val = load i32, i32* %ptr, align 4 + %gep = getelementptr inbounds %struct.s2_packed, ptr %packed1, i32 0, i32 4 + %val = load i32, ptr %gep, align 4 %valt = trunc i32 %val to i16 ret i16 %valt } @@ -21,9 +20,8 @@ define i16 @f2() { entry: %packed1 = alloca %struct.s2_packed, align 8 - %gep = getelementptr inbounds %struct.s2_packed, %struct.s2_packed* %packed1, i32 0, i32 4 - %ptr = bitcast i16* %gep to i48* - %val = load i48, i48* %ptr, align 4 + %gep = getelementptr inbounds %struct.s2_packed, ptr %packed1, i32 0, i32 4 + %val = load i48, ptr %gep, align 4 %valt = trunc i48 %val to i16 ret i16 %valt } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/abilist.ll b/llvm/test/Instrumentation/DataFlowSanitizer/abilist.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/abilist.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/abilist.ll @@ -1,4 +1,4 @@ -; RUN: opt < %s -passes=dfsan -dfsan-abilist=%S/Inputs/abilist.txt -S | FileCheck %s +; RUN: opt < %s -passes=dfsan -dfsan-abilist=%S/Inputs/abilist.txt -S | FileCheck -enable-var-scope %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @@ -16,7 +16,7 @@ ret i32 %c } -@discardg = alias i32 (i32, i32)* (i32), i32 (i32, i32)* (i32)* @g +@discardg = alias ptr (i32), ptr @g declare void @custom1(i32 %a, i32 %b) @@ -26,7 +26,7 @@ declare i32 @custom4(i32 %a, ...) -declare void @customcb(i32 (i32)* %cb) +declare void @customcb(ptr %cb) declare i32 @cb(i32) @@ -39,59 +39,60 @@ ; CHECK: call void @__dfsw_custom1(i32 1, i32 2, i[[#SBITS]] zeroext 0, i[[#SBITS]] zeroext 0) call void @custom1(i32 1, i32 2) - ; CHECK: call i32 @__dfsw_custom2(i32 1, i32 2, i[[#SBITS]] zeroext 0, i[[#SBITS]] zeroext 0, i[[#SBITS]]* %[[LABELRETURN]]) + ; CHECK: call i32 @__dfsw_custom2(i32 1, i32 2, i[[#SBITS]] zeroext 0, i[[#SBITS]] zeroext 0, ptr %[[LABELRETURN]]) call i32 @custom2(i32 1, i32 2) ; CHECK: call void @__dfsw_customcb({{.*}} @cb.dfsan, i[[#SBITS]] zeroext 0) - call void @customcb(i32 (i32)* @cb) - - ; CHECK: %[[LABELVA1_0:.*]] = getelementptr inbounds [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* %[[LABELVA1]], i32 0, i32 0 - ; CHECK: store i[[#SBITS]] 0, i[[#SBITS]]* %[[LABELVA1_0]] - ; CHECK: %[[LABELVA1_1:.*]] = getelementptr inbounds [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* %[[LABELVA1]], i32 0, i32 1 - ; CHECK: store i[[#SBITS]] %{{.*}}, i[[#SBITS]]* %[[LABELVA1_1]] - ; CHECK: %[[LABELVA1_0A:.*]] = getelementptr inbounds [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* %[[LABELVA1]], i32 0, i32 0 - ; CHECK: call void (i32, i[[#SBITS]], i[[#SBITS]]*, ...) @__dfsw_custom3(i32 1, i[[#SBITS]] zeroext 0, i[[#SBITS]]* %[[LABELVA1_0A]], i32 2, i32 %{{.*}}) + call void @customcb(ptr @cb) + + ; CHECK: %[[LABELVA1_0:.*]] = getelementptr inbounds [2 x i[[#SBITS]]], ptr %[[LABELVA1]], i32 0, i32 0 + ; CHECK: store i[[#SBITS]] 0, ptr %[[LABELVA1_0]] + ; CHECK: %[[LABELVA1_1:.*]] = getelementptr inbounds [2 x i[[#SBITS]]], ptr %[[LABELVA1]], i32 0, i32 1 + ; CHECK: store i[[#SBITS]] %{{.*}}, ptr %[[LABELVA1_1]] + ; CHECK: %[[LABELVA1_0A:.*]] = getelementptr inbounds [2 x i[[#SBITS]]], ptr %[[LABELVA1]], i32 0, i32 0 + ; CHECK: call void (i32, i[[#SBITS]], ptr, ...) @__dfsw_custom3(i32 1, i[[#SBITS]] zeroext 0, ptr %[[LABELVA1_0A]], i32 2, i32 %{{.*}}) + call void (i32, ...) @custom3(i32 1, i32 2, i32 %x) - ; CHECK: %[[LABELVA2_0:.*]] = getelementptr inbounds [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* %[[LABELVA2]], i32 0, i32 0 - ; CHECK: %[[LABELVA2_0A:.*]] = getelementptr inbounds [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* %[[LABELVA2]], i32 0, i32 0 - ; CHECK: call i32 (i32, i[[#SBITS]], i[[#SBITS]]*, i[[#SBITS]]*, ...) @__dfsw_custom4(i32 1, i[[#SBITS]] zeroext 0, i[[#SBITS]]* %[[LABELVA2_0A]], i[[#SBITS]]* %[[LABELRETURN]], i32 2, i32 3) + ; CHECK: %[[LABELVA2_0:.*]] = getelementptr inbounds [2 x i[[#SBITS]]], ptr %[[LABELVA2]], i32 0, i32 0 + ; CHECK: %[[LABELVA2_0A:.*]] = getelementptr inbounds [2 x i[[#SBITS]]], ptr %[[LABELVA2]], i32 0, i32 0 + ; CHECK: call i32 (i32, i[[#SBITS]], ptr, ptr, ...) @__dfsw_custom4(i32 1, i[[#SBITS]] zeroext 0, ptr %[[LABELVA2_0A]], ptr %[[LABELRETURN]], i32 2, i32 3) call i32 (i32, ...) @custom4(i32 1, i32 2, i32 3) ret void } ; CHECK: @g.dfsan -define i32 (i32, i32)* @g(i32) { +define ptr @g(i32) { ; CHECK: ret {{.*}} @"dfsw$custom2" - ret i32 (i32, i32)* @custom2 + ret ptr @custom2 } -; CHECK: define i32 (i32, i32)* @discardg(i32 %0) -; CHECK: %[[CALL:.*]] = call i32 (i32, i32)* @g.dfsan(i32 %0) +; CHECK: define ptr @discardg(i32 %0) +; CHECK: %[[CALL:.*]] = call ptr @g.dfsan(i32 %0) ; CHECK: load {{.*}} @__dfsan_retval_tls ; CHECK: ret {{.*}} ; CHECK: define i32 @adiscard.dfsan(i32 %0, i32 %1) ; CHECK: %[[CALL:.*]] = call i32 @discard(i32 %0, i32 %1) ; CHECK: ret i32 -@adiscard = alias i32 (i32, i32), i32 (i32, i32)* @discard +@adiscard = alias i32 (i32, i32), ptr @discard ; CHECK: define linkonce_odr i32 @"dfsw$custom2"(i32 %0, i32 %1) ; CHECK: %[[LABELRETURN2:.*]] = alloca i[[#SBITS]] -; CHECK: %[[RV:.*]] = call i32 @__dfsw_custom2(i32 {{.*}}, i32 {{.*}}, i[[#SBITS]] {{.*}}, i[[#SBITS]] {{.*}}, i[[#SBITS]]* %[[LABELRETURN2]]) -; CHECK: %[[RVSHADOW:.*]] = load i[[#SBITS]], i[[#SBITS]]* %[[LABELRETURN2]] +; CHECK: %[[RV:.*]] = call i32 @__dfsw_custom2(i32 {{.*}}, i32 {{.*}}, i[[#SBITS]] {{.*}}, i[[#SBITS]] {{.*}}, ptr %[[LABELRETURN2]]) +; CHECK: %[[RVSHADOW:.*]] = load i[[#SBITS]], ptr %[[LABELRETURN2]] ; CHECK: store {{.*}} @__dfsan_retval_tls ; CHECK: ret i32 ; CHECK: define linkonce_odr void @"dfsw$custom3"(i32 %0, ...) -; CHECK: call void @__dfsan_vararg_wrapper(i8* +; CHECK: call void @__dfsan_vararg_wrapper(ptr ; CHECK: unreachable ; CHECK: define linkonce_odr i32 @"dfsw$custom4"(i32 %0, ...) ; CHECK: declare void @__dfsw_custom1(i32, i32, i[[#SBITS]], i[[#SBITS]]) -; CHECK: declare i32 @__dfsw_custom2(i32, i32, i[[#SBITS]], i[[#SBITS]], i[[#SBITS]]*) +; CHECK: declare i32 @__dfsw_custom2(i32, i32, i[[#SBITS]], i[[#SBITS]], ptr) -; CHECK: declare void @__dfsw_custom3(i32, i[[#SBITS]], i[[#SBITS]]*, ...) -; CHECK: declare i32 @__dfsw_custom4(i32, i[[#SBITS]], i[[#SBITS]]*, i[[#SBITS]]*, ...) +; CHECK: declare void @__dfsw_custom3(i32, i[[#SBITS]], ptr, ...) +; CHECK: declare i32 @__dfsw_custom4(i32, i[[#SBITS]], ptr, ptr, ...) diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/abilist_aggregate.ll b/llvm/test/Instrumentation/DataFlowSanitizer/abilist_aggregate.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/abilist_aggregate.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/abilist_aggregate.ll @@ -16,8 +16,8 @@ define {i1, i7} @call_functional({i32, i1} %a, [2 x i7] %b) { ; CHECK-LABEL: @call_functional.dfsan - ; CHECK-NEXT: %[[#REG:]] = load [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to [2 x i[[#SBITS]]]*), align [[ALIGN:2]] - ; CHECK-NEXT: %[[#REG+1]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; CHECK-NEXT: %[[#REG:]] = load [2 x i[[#SBITS]]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to ptr), align [[ALIGN:2]] + ; CHECK-NEXT: %[[#REG+1]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN]] ; CHECK-NEXT: %[[#REG+2]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } %[[#REG+1]], 0 ; CHECK-NEXT: %[[#REG+3]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } %[[#REG+1]], 1 ; CHECK-NEXT: %[[#REG+4]] = or i[[#SBITS]] %[[#REG+2]], %[[#REG+3]] @@ -27,7 +27,7 @@ ; CHECK-NEXT: %[[#REG+8]] = or i[[#SBITS]] %[[#REG+4]], %[[#REG+7]] ; CHECK-NEXT: %[[#REG+9]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } undef, i[[#SBITS]] %[[#REG+8]], 0 ; CHECK-NEXT: %[[#REG+10]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } %[[#REG+9]], i[[#SBITS]] %[[#REG+8]], 1 - ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } %[[#REG+10]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } %[[#REG+10]], ptr @__dfsan_retval_tls, align [[ALIGN]] %r = call {i1, i7} @functional({i32, i1} %a, [2 x i7] %b) ret {i1, i7} %r @@ -44,7 +44,7 @@ define {i1, i7} @call_discard({i32, i1} %a, [2 x i7] %b) { ; CHECK: @call_discard.dfsan - ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } zeroinitializer, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align 2 + ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } zeroinitializer, ptr @__dfsan_retval_tls, align 2 %r = call {i1, i7} @discard({i32, i1} %a, [2 x i7] %b) ret {i1, i7} %r @@ -62,7 +62,7 @@ define {i1, i7} @call_uninstrumented({i32, i1} %a, [2 x i7] %b) { ; CHECK: @call_uninstrumented.dfsan ; CHECK: call void @__dfsan_unimplemented - ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } zeroinitializer, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align 2 + ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } zeroinitializer, ptr @__dfsan_retval_tls, align 2 %r = call {i1, i7} @uninstrumented({i32, i1} %a, [2 x i7] %b) ret {i1, i7} %r @@ -71,19 +71,19 @@ define {i1, i7} @call_custom_with_ret({i32, i1} %a, [2 x i7] %b) { ; CHECK: @call_custom_with_ret.dfsan ; CHECK: %labelreturn = alloca i[[#SBITS]], align [[#SBYTES]] - ; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to [2 x i[[#SBITS]]]*), align [[ALIGN:2]] - ; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to ptr), align [[ALIGN:2]] + ; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN]] ; CHECK: [[A0:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 0 ; CHECK: [[A1:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 1 ; CHECK: [[A01:%.*]] = or i[[#SBITS]] [[A0]], [[A1]] ; CHECK: [[B0:%.*]] = extractvalue [2 x i[[#SBITS]]] [[B]], 0 ; CHECK: [[B1:%.*]] = extractvalue [2 x i[[#SBITS]]] [[B]], 1 ; CHECK: [[B01:%.*]] = or i[[#SBITS]] [[B0]], [[B1]] - ; CHECK: [[R:%.*]] = call { i1, i7 } @__dfsw_custom_with_ret({ i32, i1 } %a, [2 x i7] %b, i[[#SBITS]] zeroext [[A01]], i[[#SBITS]] zeroext [[B01]], i[[#SBITS]]* %labelreturn) - ; CHECK: [[RE:%.*]] = load i[[#SBITS]], i[[#SBITS]]* %labelreturn, align [[#SBYTES]] + ; CHECK: [[R:%.*]] = call { i1, i7 } @__dfsw_custom_with_ret({ i32, i1 } %a, [2 x i7] %b, i[[#SBITS]] zeroext [[A01]], i[[#SBITS]] zeroext [[B01]], ptr %labelreturn) + ; CHECK: [[RE:%.*]] = load i[[#SBITS]], ptr %labelreturn, align [[#SBYTES]] ; CHECK: [[RS0:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } undef, i[[#SBITS]] [[RE]], 0 ; CHECK: [[RS1:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } [[RS0]], i[[#SBITS]] [[RE]], 1 - ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } [[RS1]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } [[RS1]], ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK: ret { i1, i7 } [[R]] %r = call {i1, i7} @custom_with_ret({i32, i1} %a, [2 x i7] %b) @@ -92,8 +92,8 @@ define void @call_custom_without_ret({i32, i1} %a, [2 x i7] %b) { ; CHECK: @call_custom_without_ret.dfsan - ; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to [2 x i[[#SBITS]]]*), align [[ALIGN:2]] - ; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to ptr), align [[ALIGN:2]] + ; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN]] ; CHECK: [[A0:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 0 ; CHECK: [[A1:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 1 ; CHECK: [[A01:%.*]] = or i[[#SBITS]] [[A0]], [[A1]] @@ -108,19 +108,19 @@ define void @call_custom_varg({i32, i1} %a, [2 x i7] %b) { ; CHECK: @call_custom_varg.dfsan - ; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to [2 x i[[#SBITS]]]*), align [[ALIGN:2]] + ; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to ptr), align [[ALIGN:2]] ; CHECK: %labelva = alloca [1 x i[[#SBITS]]], align [[#SBYTES]] - ; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN]] ; CHECK: [[A0:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 0 ; CHECK: [[A1:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 1 ; CHECK: [[A01:%.*]] = or i[[#SBITS]] [[A0]], [[A1]] - ; CHECK: [[V0:%.*]] = getelementptr inbounds [1 x i[[#SBITS]]], [1 x i[[#SBITS]]]* %labelva, i32 0, i32 0 + ; CHECK: [[V0:%.*]] = getelementptr inbounds [1 x i[[#SBITS]]], ptr %labelva, i32 0, i32 0 ; CHECK: [[B0:%.*]] = extractvalue [2 x i[[#SBITS]]] [[B]], 0 ; CHECK: [[B1:%.*]] = extractvalue [2 x i[[#SBITS]]] [[B]], 1 ; CHECK: [[B01:%.*]] = or i[[#SBITS]] [[B0]], [[B1]] - ; CHECK: store i[[#SBITS]] [[B01]], i[[#SBITS]]* [[V0]], align [[#SBYTES]] - ; CHECK: [[V:%.*]] = getelementptr inbounds [1 x i[[#SBITS]]], [1 x i[[#SBITS]]]* %labelva, i32 0, i32 0 - ; CHECK: call void ({ i32, i1 }, i[[#SBITS]], i[[#SBITS]]*, ...) @__dfsw_custom_varg({ i32, i1 } %a, i[[#SBITS]] zeroext [[A01]], i[[#SBITS]]* [[V]], [2 x i7] %b) + ; CHECK: store i[[#SBITS]] [[B01]], ptr [[V0]], align [[#SBYTES]] + ; CHECK: [[V:%.*]] = getelementptr inbounds [1 x i[[#SBITS]]], ptr %labelva, i32 0, i32 0 + ; CHECK: call void ({ i32, i1 }, i[[#SBITS]], ptr, ...) @__dfsw_custom_varg({ i32, i1 } %a, i[[#SBITS]] zeroext [[A01]], ptr [[V]], [2 x i7] %b) call void ({i32, i1}, ...) @custom_varg({i32, i1} %a, [2 x i7] %b) ret void @@ -129,26 +129,26 @@ define {i1, i7} @call_custom_cb({i32, i1} %a, [2 x i7] %b) { ; CHECK: define { i1, i7 } @call_custom_cb.dfsan({ i32, i1 } %a, [2 x i7] %b) { ; CHECK: %labelreturn = alloca i[[#SBITS]], align [[#SBYTES]] - ; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to [2 x i[[#SBITS]]]*), align [[ALIGN:2]] - ; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to ptr), align [[ALIGN:2]] + ; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN]] ; CHECK: [[A0:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 0 ; CHECK: [[A1:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 1 ; CHECK: [[A01:%.*]] = or i[[#SBITS]] [[A0]], [[A1]] ; CHECK: [[B0:%.*]] = extractvalue [2 x i[[#SBITS]]] [[B]], 0 ; CHECK: [[B1:%.*]] = extractvalue [2 x i[[#SBITS]]] [[B]], 1 ; CHECK: [[B01:%.*]] = or i[[#SBITS]] [[B0]], [[B1]] - ; CHECK: [[R:%.*]] = call { i1, i7 } @__dfsw_custom_cb({ i1, i7 } ({ i32, i1 }, [2 x i7])* @cb.dfsan, { i32, i1 } %a, [2 x i7] %b, i[[#SBITS]] zeroext 0, i[[#SBITS]] zeroext [[A01]], i[[#SBITS]] zeroext [[B01]], i[[#SBITS]]* %labelreturn) - ; CHECK: [[RE:%.*]] = load i[[#SBITS]], i[[#SBITS]]* %labelreturn, align [[#SBYTES]] + ; CHECK: [[R:%.*]] = call { i1, i7 } @__dfsw_custom_cb(ptr @cb.dfsan, { i32, i1 } %a, [2 x i7] %b, i[[#SBITS]] zeroext 0, i[[#SBITS]] zeroext [[A01]], i[[#SBITS]] zeroext [[B01]], ptr %labelreturn) + ; CHECK: [[RE:%.*]] = load i[[#SBITS]], ptr %labelreturn, align [[#SBYTES]] ; CHECK: [[RS0:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } undef, i[[#SBITS]] [[RE]], 0 ; CHECK: [[RS1:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } [[RS0]], i[[#SBITS]] [[RE]], 1 - ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } [[RS1]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } [[RS1]], ptr @__dfsan_retval_tls, align [[ALIGN]] - %r = call {i1, i7} @custom_cb({i1, i7} ({i32, i1}, [2 x i7])* @cb, {i32, i1} %a, [2 x i7] %b) + %r = call {i1, i7} @custom_cb(ptr @cb, {i32, i1} %a, [2 x i7] %b) ret {i1, i7} %r } -define {i1, i7} @custom_cb({i1, i7} ({i32, i1}, [2 x i7])* %cb, {i32, i1} %a, [2 x i7] %b) { - ; CHECK: define { i1, i7 } @custom_cb({ i1, i7 } ({ i32, i1 }, [2 x i7])* %cb, { i32, i1 } %a, [2 x i7] %b) +define {i1, i7} @custom_cb(ptr %cb, {i32, i1} %a, [2 x i7] %b) { + ; CHECK: define { i1, i7 } @custom_cb(ptr %cb, { i32, i1 } %a, [2 x i7] %b) %r = call {i1, i7} %cb({i32, i1} %a, [2 x i7] %b) ret {i1, i7} %r @@ -156,13 +156,13 @@ define {i1, i7} @cb({i32, i1} %a, [2 x i7] %b) { ; CHECK: define { i1, i7 } @cb.dfsan({ i32, i1 } %a, [2 x i7] %b) - ; CHECK: [[BL:%.*]] = load [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to [2 x i[[#SBITS]]]*), align [[ALIGN:2]] - ; CHECK: [[AL:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; CHECK: [[BL:%.*]] = load [2 x i[[#SBITS]]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to ptr), align [[ALIGN:2]] + ; CHECK: [[AL:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN]] ; CHECK: [[AL1:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[AL]], 1 ; CHECK: [[BL0:%.*]] = extractvalue [2 x i[[#SBITS]]] [[BL]], 0 ; CHECK: [[RL0:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } zeroinitializer, i[[#SBITS]] [[AL1]], 0 ; CHECK: [[RL:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } [[RL0]], i[[#SBITS]] [[BL0]], 1 - ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } [[RL]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } [[RL]], ptr @__dfsan_retval_tls, align [[ALIGN]] %a1 = extractvalue {i32, i1} %a, 1 %b0 = extractvalue [2 x i7] %b, 0 @@ -171,49 +171,49 @@ ret {i1, i7} %r1 } -define {i1, i7} ({i32, i1}, [2 x i7])* @ret_custom() { +define ptr @ret_custom() { ; CHECK: @ret_custom.dfsan - ; CHECK: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 + ; CHECK: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align 2 ; CHECK: ret {{.*}} @"dfsw$custom_with_ret" - ret {i1, i7} ({i32, i1}, [2 x i7])* @custom_with_ret + ret ptr @custom_with_ret } -; CHECK: define linkonce_odr { i1, i7 } @"dfsw$custom_cb"({ i1, i7 } ({ i32, i1 }, [2 x i7])* %0, { i32, i1 } %1, [2 x i7] %2) { +; CHECK: define linkonce_odr { i1, i7 } @"dfsw$custom_cb"(ptr %0, { i32, i1 } %1, [2 x i7] %2) { ; CHECK: %labelreturn = alloca i[[#SBITS]], align [[#SBYTES]] ; COMM: TODO simplify the expression [[#mul(2,SBYTES) + max(SBYTES,2)]] to ; COMM: [[#mul(3,SBYTES)]], if shadow-tls-alignment is updated to match shadow ; COMM: width bytes. -; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES) + max(SBYTES,2)]]) to [2 x i[[#SBITS]]]*), align [[ALIGN:2]] -; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] -; CHECK: [[CB:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] +; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES) + max(SBYTES,2)]]) to ptr), align [[ALIGN:2]] +; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]] +; CHECK: [[CB:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] ; CHECK: [[A0:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 0 ; CHECK: [[A1:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 1 ; CHECK: [[A01:%.*]] = or i[[#SBITS]] [[A0]], [[A1]] ; CHECK: [[B0:%.*]] = extractvalue [2 x i[[#SBITS]]] [[B]], 0 ; CHECK: [[B1:%.*]] = extractvalue [2 x i[[#SBITS]]] [[B]], 1 ; CHECK: [[B01:%.*]] = or i[[#SBITS]] [[B0]], [[B1]] -; CHECK: [[R:%.*]] = call { i1, i7 } @__dfsw_custom_cb({ i1, i7 } ({ i32, i1 }, [2 x i7])* %0, { i32, i1 } %1, [2 x i7] %2, i[[#SBITS]] zeroext [[CB]], i[[#SBITS]] zeroext [[A01]], i[[#SBITS]] zeroext [[B01]], i[[#SBITS]]* %labelreturn) -; CHECK: [[RE:%.*]] = load i[[#SBITS]], i[[#SBITS]]* %labelreturn, align [[#SBYTES]] +; CHECK: [[R:%.*]] = call { i1, i7 } @__dfsw_custom_cb(ptr %0, { i32, i1 } %1, [2 x i7] %2, i[[#SBITS]] zeroext [[CB]], i[[#SBITS]] zeroext [[A01]], i[[#SBITS]] zeroext [[B01]], ptr %labelreturn) +; CHECK: [[RE:%.*]] = load i[[#SBITS]], ptr %labelreturn, align [[#SBYTES]] ; CHECK: [[RS0:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } undef, i[[#SBITS]] [[RE]], 0 ; CHECK: [[RS1:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } [[RS0]], i[[#SBITS]] [[RE]], 1 -; CHECK: store { i[[#SBITS]], i[[#SBITS]] } [[RS1]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] +; CHECK: store { i[[#SBITS]], i[[#SBITS]] } [[RS1]], ptr @__dfsan_retval_tls, align [[ALIGN]] define {i1, i7} @custom_with_ret({i32, i1} %a, [2 x i7] %b) { ; CHECK: define linkonce_odr { i1, i7 } @"dfsw$custom_with_ret"({ i32, i1 } %0, [2 x i7] %1) ; CHECK: %labelreturn = alloca i[[#SBITS]], align [[#SBYTES]] - ; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to [2 x i[[#SBITS]]]*), align [[ALIGN:2]] - ; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to ptr), align [[ALIGN:2]] + ; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN]] ; CHECK: [[A0:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 0 ; CHECK: [[A1:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 1 ; CHECK: [[A01:%.*]] = or i[[#SBITS]] [[A0]], [[A1]] ; CHECK: [[B0:%.*]] = extractvalue [2 x i[[#SBITS]]] [[B]], 0 ; CHECK: [[B1:%.*]] = extractvalue [2 x i[[#SBITS]]] [[B]], 1 ; CHECK: [[B01:%.*]] = or i[[#SBITS]] [[B0]], [[B1]] - ; CHECK: [[R:%.*]] = call { i1, i7 } @__dfsw_custom_with_ret({ i32, i1 } %0, [2 x i7] %1, i[[#SBITS]] zeroext [[A01]], i[[#SBITS]] zeroext [[B01]], i[[#SBITS]]* %labelreturn) - ; CHECK: [[RE:%.*]] = load i[[#SBITS]], i[[#SBITS]]* %labelreturn, align [[#SBYTES]] + ; CHECK: [[R:%.*]] = call { i1, i7 } @__dfsw_custom_with_ret({ i32, i1 } %0, [2 x i7] %1, i[[#SBITS]] zeroext [[A01]], i[[#SBITS]] zeroext [[B01]], ptr %labelreturn) + ; CHECK: [[RE:%.*]] = load i[[#SBITS]], ptr %labelreturn, align [[#SBYTES]] ; CHECK: [[RS0:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } undef, i[[#SBITS]] [[RE]], 0 ; CHECK: [[RS1:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } [[RS0]], i[[#SBITS]] [[RE]], 1 - ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } [[RS1]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; CHECK: store { i[[#SBITS]], i[[#SBITS]] } [[RS1]], ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK: ret { i1, i7 } [[R]] %a1 = extractvalue {i32, i1} %a, 1 %b0 = extractvalue [2 x i7] %b, 0 @@ -224,8 +224,8 @@ define void @custom_without_ret({i32, i1} %a, [2 x i7] %b) { ; CHECK: define linkonce_odr void @"dfsw$custom_without_ret"({ i32, i1 } %0, [2 x i7] %1) - ; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to [2 x i[[#SBITS]]]*), align [[ALIGN:2]] - ; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([100 x i64]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; CHECK: [[B:%.*]] = load [2 x i[[#SBITS]]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES)]]) to ptr), align [[ALIGN:2]] + ; CHECK: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN]] ; CHECK: [[A0:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 0 ; CHECK: [[A1:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[A]], 1 ; CHECK: [[A01:%.*]] = or i[[#SBITS]] [[A0]], [[A1]] @@ -244,8 +244,8 @@ ret void } -; CHECK: declare { i1, i7 } @__dfsw_custom_with_ret({ i32, i1 }, [2 x i7], i[[#SBITS]], i[[#SBITS]], i[[#SBITS]]*) +; CHECK: declare { i1, i7 } @__dfsw_custom_with_ret({ i32, i1 }, [2 x i7], i[[#SBITS]], i[[#SBITS]], ptr) ; CHECK: declare void @__dfsw_custom_without_ret({ i32, i1 }, [2 x i7], i[[#SBITS]], i[[#SBITS]]) -; CHECK: declare void @__dfsw_custom_varg({ i32, i1 }, i[[#SBITS]], i[[#SBITS]]*, ...) +; CHECK: declare void @__dfsw_custom_varg({ i32, i1 }, i[[#SBITS]], ptr, ...) -; CHECK: declare { i1, i7 } @__dfsw_custom_cb({ i1, i7 } ({ i32, i1 }, [2 x i7])*, { i32, i1 }, [2 x i7], i[[#SBITS]], i[[#SBITS]], i[[#SBITS]], i[[#SBITS]]*) +; CHECK: declare { i1, i7 } @__dfsw_custom_cb(ptr, { i32, i1 }, [2 x i7], i[[#SBITS]], i[[#SBITS]], i[[#SBITS]], ptr) diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/array.ll b/llvm/test/Instrumentation/DataFlowSanitizer/array.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/array.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/array.ll @@ -13,11 +13,11 @@ define [4 x i8] @pass_array([4 x i8] %a) { ; NO_COMBINE_LOAD_PTR: @pass_array.dfsan - ; NO_COMBINE_LOAD_PTR: %1 = load [4 x i[[#SBITS]]], [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to [4 x i[[#SBITS]]]*), align [[ALIGN:2]] - ; NO_COMBINE_LOAD_PTR: store [4 x i[[#SBITS]]] %1, [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [4 x i[[#SBITS]]]*), align [[ALIGN]] + ; NO_COMBINE_LOAD_PTR: %1 = load [4 x i[[#SBITS]]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] + ; NO_COMBINE_LOAD_PTR: store [4 x i[[#SBITS]]] %1, ptr @__dfsan_retval_tls, align [[ALIGN]] ; DEBUG_NONZERO_LABELS: @pass_array.dfsan - ; DEBUG_NONZERO_LABELS: [[L:%.*]] = load [4 x i[[#SBITS]]], [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to [4 x i[[#SBITS]]]*), align [[ALIGN:2]] + ; DEBUG_NONZERO_LABELS: [[L:%.*]] = load [4 x i[[#SBITS]]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] ; DEBUG_NONZERO_LABELS: [[L0:%.*]] = extractvalue [4 x i[[#SBITS]]] [[L]], 0 ; DEBUG_NONZERO_LABELS: [[L1:%.*]] = extractvalue [4 x i[[#SBITS]]] [[L]], 1 ; DEBUG_NONZERO_LABELS: [[L01:%.*]] = or i[[#SBITS]] [[L0]], [[L1]] @@ -31,110 +31,110 @@ ret [4 x i8] %a } -%ArrayOfStruct = type [4 x {i8*, i32}] +%ArrayOfStruct = type [4 x {ptr, i32}] define %ArrayOfStruct @pass_array_of_struct(%ArrayOfStruct %as) { ; NO_COMBINE_LOAD_PTR: @pass_array_of_struct.dfsan - ; NO_COMBINE_LOAD_PTR: %1 = load [4 x { i[[#SBITS]], i[[#SBITS]] }], [4 x { i[[#SBITS]], i[[#SBITS]] }]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to [4 x { i[[#SBITS]], i[[#SBITS]] }]*), align [[ALIGN:2]] - ; NO_COMBINE_LOAD_PTR: store [4 x { i[[#SBITS]], i[[#SBITS]] }] %1, [4 x { i[[#SBITS]], i[[#SBITS]] }]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [4 x { i[[#SBITS]], i[[#SBITS]] }]*), align [[ALIGN]] + ; NO_COMBINE_LOAD_PTR: %1 = load [4 x { i[[#SBITS]], i[[#SBITS]] }], ptr @__dfsan_arg_tls, align [[ALIGN:2]] + ; NO_COMBINE_LOAD_PTR: store [4 x { i[[#SBITS]], i[[#SBITS]] }] %1, ptr @__dfsan_retval_tls, align [[ALIGN]] ret %ArrayOfStruct %as } -define [4 x i1]* @alloca_ret_array() { +define ptr @alloca_ret_array() { ; NO_COMBINE_LOAD_PTR: @alloca_ret_array.dfsan - ; NO_COMBINE_LOAD_PTR: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 + ; NO_COMBINE_LOAD_PTR: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align 2 %p = alloca [4 x i1] - ret [4 x i1]* %p + ret ptr %p } define [4 x i1] @load_alloca_array() { ; NO_COMBINE_LOAD_PTR-LABEL: @load_alloca_array.dfsan ; NO_COMBINE_LOAD_PTR-NEXT: %[[#R:]] = alloca i[[#SBITS]], align [[#SBYTES]] ; NO_COMBINE_LOAD_PTR-NEXT: %p = alloca [4 x i1] - ; NO_COMBINE_LOAD_PTR-NEXT: %[[#R+1]] = load i[[#SBITS]], i[[#SBITS]]* %[[#R]], align [[#SBYTES]] + ; NO_COMBINE_LOAD_PTR-NEXT: %[[#R+1]] = load i[[#SBITS]], ptr %[[#R]], align [[#SBYTES]] ; NO_COMBINE_LOAD_PTR-NEXT: %[[#R+2]] = insertvalue [4 x i[[#SBITS]]] undef, i[[#SBITS]] %[[#R+1]], 0 ; NO_COMBINE_LOAD_PTR-NEXT: %[[#R+3]] = insertvalue [4 x i[[#SBITS]]] %[[#R+2]], i[[#SBITS]] %[[#R+1]], 1 ; NO_COMBINE_LOAD_PTR-NEXT: %[[#R+4]] = insertvalue [4 x i[[#SBITS]]] %[[#R+3]], i[[#SBITS]] %[[#R+1]], 2 ; NO_COMBINE_LOAD_PTR-NEXT: %[[#R+5]] = insertvalue [4 x i[[#SBITS]]] %[[#R+4]], i[[#SBITS]] %[[#R+1]], 3 - ; NO_COMBINE_LOAD_PTR-NEXT: %a = load [4 x i1], [4 x i1]* %p - ; NO_COMBINE_LOAD_PTR-NEXT: store [4 x i[[#SBITS]]] %[[#R+5]], [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [4 x i[[#SBITS]]]*), align 2 + ; NO_COMBINE_LOAD_PTR-NEXT: %a = load [4 x i1], ptr %p + ; NO_COMBINE_LOAD_PTR-NEXT: store [4 x i[[#SBITS]]] %[[#R+5]], ptr @__dfsan_retval_tls, align 2 ; NO_COMBINE_LOAD_PTR-NEXT: ret [4 x i1] %a %p = alloca [4 x i1] - %a = load [4 x i1], [4 x i1]* %p + %a = load [4 x i1], ptr %p ret [4 x i1] %a } -define [0 x i1] @load_array0([0 x i1]* %p) { +define [0 x i1] @load_array0(ptr %p) { ; NO_COMBINE_LOAD_PTR: @load_array0.dfsan - ; NO_COMBINE_LOAD_PTR: store [0 x i[[#SBITS]]] zeroinitializer, [0 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [0 x i[[#SBITS]]]*), align 2 - %a = load [0 x i1], [0 x i1]* %p + ; NO_COMBINE_LOAD_PTR: store [0 x i[[#SBITS]]] zeroinitializer, ptr @__dfsan_retval_tls, align 2 + %a = load [0 x i1], ptr %p ret [0 x i1] %a } -define [1 x i1] @load_array1([1 x i1]* %p) { +define [1 x i1] @load_array1(ptr %p) { ; NO_COMBINE_LOAD_PTR: @load_array1.dfsan ; NO_COMBINE_LOAD_PTR: [[L:%.*]] = load i[[#SBITS]], ; NO_COMBINE_LOAD_PTR: [[S:%.*]] = insertvalue [1 x i[[#SBITS]]] undef, i[[#SBITS]] [[L]], 0 - ; NO_COMBINE_LOAD_PTR: store [1 x i[[#SBITS]]] [[S]], [1 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [1 x i[[#SBITS]]]*), align 2 + ; NO_COMBINE_LOAD_PTR: store [1 x i[[#SBITS]]] [[S]], ptr @__dfsan_retval_tls, align 2 ; EVENT_CALLBACKS: @load_array1.dfsan ; EVENT_CALLBACKS: [[L:%.*]] = or i[[#SBITS]] - ; EVENT_CALLBACKS: call void @__dfsan_load_callback(i[[#SBITS]] [[L]], i8* {{.*}}) + ; EVENT_CALLBACKS: call void @__dfsan_load_callback(i[[#SBITS]] [[L]], ptr {{.*}}) ; FAST: @load_array1.dfsan - ; FAST: [[P:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]] - ; FAST: [[L:%.*]] = load i[[#SBITS]], i[[#SBITS]]* {{.*}}, align [[#SBYTES]] + ; FAST: [[P:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] + ; FAST: [[L:%.*]] = load i[[#SBITS]], ptr {{.*}}, align [[#SBYTES]] ; FAST: [[U:%.*]] = or i[[#SBITS]] [[L]], [[P]] ; FAST: [[S1:%.*]] = insertvalue [1 x i[[#SBITS]]] undef, i[[#SBITS]] [[U]], 0 - ; FAST: store [1 x i[[#SBITS]]] [[S1]], [1 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [1 x i[[#SBITS]]]*), align [[ALIGN]] + ; FAST: store [1 x i[[#SBITS]]] [[S1]], ptr @__dfsan_retval_tls, align [[ALIGN]] - %a = load [1 x i1], [1 x i1]* %p + %a = load [1 x i1], ptr %p ret [1 x i1] %a } -define [2 x i1] @load_array2([2 x i1]* %p) { +define [2 x i1] @load_array2(ptr %p) { ; NO_COMBINE_LOAD_PTR: @load_array2.dfsan - ; NO_COMBINE_LOAD_PTR: [[P1:%.*]] = getelementptr i[[#SBITS]], i[[#SBITS]]* [[P0:%.*]], i64 1 - ; NO_COMBINE_LOAD_PTR-DAG: [[E1:%.*]] = load i[[#SBITS]], i[[#SBITS]]* [[P1]], align [[#SBYTES]] - ; NO_COMBINE_LOAD_PTR-DAG: [[E0:%.*]] = load i[[#SBITS]], i[[#SBITS]]* [[P0]], align [[#SBYTES]] + ; NO_COMBINE_LOAD_PTR: [[P1:%.*]] = getelementptr i[[#SBITS]], ptr [[P0:%.*]], i64 1 + ; NO_COMBINE_LOAD_PTR-DAG: [[E1:%.*]] = load i[[#SBITS]], ptr [[P1]], align [[#SBYTES]] + ; NO_COMBINE_LOAD_PTR-DAG: [[E0:%.*]] = load i[[#SBITS]], ptr [[P0]], align [[#SBYTES]] ; NO_COMBINE_LOAD_PTR: [[U:%.*]] = or i[[#SBITS]] [[E0]], [[E1]] ; NO_COMBINE_LOAD_PTR: [[S1:%.*]] = insertvalue [2 x i[[#SBITS]]] undef, i[[#SBITS]] [[U]], 0 ; NO_COMBINE_LOAD_PTR: [[S2:%.*]] = insertvalue [2 x i[[#SBITS]]] [[S1]], i[[#SBITS]] [[U]], 1 - ; NO_COMBINE_LOAD_PTR: store [2 x i[[#SBITS]]] [[S2]], [2 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [2 x i[[#SBITS]]]*), align [[ALIGN:2]] + ; NO_COMBINE_LOAD_PTR: store [2 x i[[#SBITS]]] [[S2]], ptr @__dfsan_retval_tls, align [[ALIGN:2]] ; EVENT_CALLBACKS: @load_array2.dfsan ; EVENT_CALLBACKS: [[O1:%.*]] = or i[[#SBITS]] ; EVENT_CALLBACKS: [[O2:%.*]] = or i[[#SBITS]] [[O1]] - ; EVENT_CALLBACKS: call void @__dfsan_load_callback(i[[#SBITS]] [[O2]], i8* {{.*}}) + ; EVENT_CALLBACKS: call void @__dfsan_load_callback(i[[#SBITS]] [[O2]], ptr {{.*}}) ; FAST: @load_array2.dfsan - ; FAST: [[P:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]] + ; FAST: [[P:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] ; FAST: [[O:%.*]] = or i[[#SBITS]] ; FAST: [[U:%.*]] = or i[[#SBITS]] [[O]], [[P]] ; FAST: [[S:%.*]] = insertvalue [2 x i[[#SBITS]]] undef, i[[#SBITS]] [[U]], 0 ; FAST: [[S1:%.*]] = insertvalue [2 x i[[#SBITS]]] [[S]], i[[#SBITS]] [[U]], 1 - ; FAST: store [2 x i[[#SBITS]]] [[S1]], [2 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [2 x i[[#SBITS]]]*), align [[ALIGN]] - %a = load [2 x i1], [2 x i1]* %p + ; FAST: store [2 x i[[#SBITS]]] [[S1]], ptr @__dfsan_retval_tls, align [[ALIGN]] + %a = load [2 x i1], ptr %p ret [2 x i1] %a } -define [4 x i1] @load_array4([4 x i1]* %p) { +define [4 x i1] @load_array4(ptr %p) { ; NO_COMBINE_LOAD_PTR: @load_array4.dfsan ; NO_COMBINE_LOAD_PTR: [[T:%.*]] = trunc i[[#mul(4, SBITS)]] {{.*}} to i[[#SBITS]] ; NO_COMBINE_LOAD_PTR: [[S1:%.*]] = insertvalue [4 x i[[#SBITS]]] undef, i[[#SBITS]] [[T]], 0 ; NO_COMBINE_LOAD_PTR: [[S2:%.*]] = insertvalue [4 x i[[#SBITS]]] [[S1]], i[[#SBITS]] [[T]], 1 ; NO_COMBINE_LOAD_PTR: [[S3:%.*]] = insertvalue [4 x i[[#SBITS]]] [[S2]], i[[#SBITS]] [[T]], 2 ; NO_COMBINE_LOAD_PTR: [[S4:%.*]] = insertvalue [4 x i[[#SBITS]]] [[S3]], i[[#SBITS]] [[T]], 3 - ; NO_COMBINE_LOAD_PTR: store [4 x i[[#SBITS]]] [[S4]], [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [4 x i[[#SBITS]]]*), align 2 + ; NO_COMBINE_LOAD_PTR: store [4 x i[[#SBITS]]] [[S4]], ptr @__dfsan_retval_tls, align 2 ; EVENT_CALLBACKS: @load_array4.dfsan ; EVENT_CALLBACKS: [[O0:%.*]] = or i[[#mul(4, SBITS)]] ; EVENT_CALLBACKS: [[O1:%.*]] = or i[[#mul(4, SBITS)]] [[O0]] ; EVENT_CALLBACKS: [[O2:%.*]] = trunc i[[#mul(4, SBITS)]] [[O1]] to i[[#SBITS]] ; EVENT_CALLBACKS: [[O3:%.*]] = or i[[#SBITS]] [[O2]] - ; EVENT_CALLBACKS: call void @__dfsan_load_callback(i[[#SBITS]] [[O3]], i8* {{.*}}) + ; EVENT_CALLBACKS: call void @__dfsan_load_callback(i[[#SBITS]] [[O3]], ptr {{.*}}) ; FAST: @load_array4.dfsan ; FAST: [[T:%.*]] = trunc i[[#mul(4, SBITS)]] {{.*}} to i[[#SBITS]] @@ -143,35 +143,35 @@ ; FAST: [[S2:%.*]] = insertvalue [4 x i[[#SBITS]]] [[S1]], i[[#SBITS]] [[O]], 1 ; FAST: [[S3:%.*]] = insertvalue [4 x i[[#SBITS]]] [[S2]], i[[#SBITS]] [[O]], 2 ; FAST: [[S4:%.*]] = insertvalue [4 x i[[#SBITS]]] [[S3]], i[[#SBITS]] [[O]], 3 - ; FAST: store [4 x i[[#SBITS]]] [[S4]], [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [4 x i[[#SBITS]]]*), align 2 + ; FAST: store [4 x i[[#SBITS]]] [[S4]], ptr @__dfsan_retval_tls, align 2 - %a = load [4 x i1], [4 x i1]* %p + %a = load [4 x i1], ptr %p ret [4 x i1] %a } define i1 @extract_array([4 x i1] %a) { ; NO_COMBINE_LOAD_PTR: @extract_array.dfsan - ; NO_COMBINE_LOAD_PTR: [[AM:%.*]] = load [4 x i[[#SBITS]]], [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to [4 x i[[#SBITS]]]*), align [[ALIGN:2]] + ; NO_COMBINE_LOAD_PTR: [[AM:%.*]] = load [4 x i[[#SBITS]]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] ; NO_COMBINE_LOAD_PTR: [[EM:%.*]] = extractvalue [4 x i[[#SBITS]]] [[AM]], 2 - ; NO_COMBINE_LOAD_PTR: store i[[#SBITS]] [[EM]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 + ; NO_COMBINE_LOAD_PTR: store i[[#SBITS]] [[EM]], ptr @__dfsan_retval_tls, align 2 %e2 = extractvalue [4 x i1] %a, 2 ret i1 %e2 } define [4 x i1] @insert_array([4 x i1] %a, i1 %e2) { ; NO_COMBINE_LOAD_PTR: @insert_array.dfsan - ; NO_COMBINE_LOAD_PTR: [[EM:%.*]] = load i[[#SBITS]], i[[#SBITS]]* - ; NO_COMBINE_LOAD_PTR-SAME: inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 [[#mul(4, SBYTES)]]) to i[[#SBITS]]*), align [[ALIGN:2]] - ; NO_COMBINE_LOAD_PTR: [[AM:%.*]] = load [4 x i[[#SBITS]]], [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to [4 x i[[#SBITS]]]*), align [[ALIGN]] + ; NO_COMBINE_LOAD_PTR: [[EM:%.*]] = load i[[#SBITS]], ptr + ; NO_COMBINE_LOAD_PTR-SAME: inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(4, SBYTES)]]) to ptr), align [[ALIGN:2]] + ; NO_COMBINE_LOAD_PTR: [[AM:%.*]] = load [4 x i[[#SBITS]]], ptr @__dfsan_arg_tls, align [[ALIGN]] ; NO_COMBINE_LOAD_PTR: [[AM1:%.*]] = insertvalue [4 x i[[#SBITS]]] [[AM]], i[[#SBITS]] [[EM]], 0 - ; NO_COMBINE_LOAD_PTR: store [4 x i[[#SBITS]]] [[AM1]], [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [4 x i[[#SBITS]]]*), align [[ALIGN]] + ; NO_COMBINE_LOAD_PTR: store [4 x i[[#SBITS]]] [[AM1]], ptr @__dfsan_retval_tls, align [[ALIGN]] %a1 = insertvalue [4 x i1] %a, i1 %e2, 0 ret [4 x i1] %a1 } define void @store_alloca_array([4 x i1] %a) { ; FAST: @store_alloca_array.dfsan - ; FAST: [[S:%.*]] = load [4 x i[[#SBITS]]], [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to [4 x i[[#SBITS]]]*), align [[ALIGN:2]] + ; FAST: [[S:%.*]] = load [4 x i[[#SBITS]]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] ; FAST: [[SP:%.*]] = alloca i[[#SBITS]], align [[#SBYTES]] ; FAST: [[E0:%.*]] = extractvalue [4 x i[[#SBITS]]] [[S]], 0 ; FAST: [[E1:%.*]] = extractvalue [4 x i[[#SBITS]]] [[S]], 1 @@ -180,50 +180,49 @@ ; FAST: [[E012:%.*]] = or i[[#SBITS]] [[E01]], [[E2]] ; FAST: [[E3:%.*]] = extractvalue [4 x i[[#SBITS]]] [[S]], 3 ; FAST: [[E0123:%.*]] = or i[[#SBITS]] [[E012]], [[E3]] - ; FAST: store i[[#SBITS]] [[E0123]], i[[#SBITS]]* [[SP]], align [[#SBYTES]] + ; FAST: store i[[#SBITS]] [[E0123]], ptr [[SP]], align [[#SBYTES]] %p = alloca [4 x i1] - store [4 x i1] %a, [4 x i1]* %p + store [4 x i1] %a, ptr %p ret void } -define void @store_zero_array([4 x i1]* %p) { +define void @store_zero_array(ptr %p) { ; FAST: @store_zero_array.dfsan - ; FAST: store i[[#mul(4, SBITS)]] 0, i[[#mul(4, SBITS)]]* {{.*}} - store [4 x i1] zeroinitializer, [4 x i1]* %p + ; FAST: store i[[#mul(4, SBITS)]] 0, ptr {{.*}} + store [4 x i1] zeroinitializer, ptr %p ret void } -define void @store_array2([2 x i1] %a, [2 x i1]* %p) { +define void @store_array2([2 x i1] %a, ptr %p) { ; EVENT_CALLBACKS: @store_array2.dfsan ; EVENT_CALLBACKS: [[E12:%.*]] = or i[[#SBITS]] - ; EVENT_CALLBACKS: [[P:%.*]] = bitcast [2 x i1]* %p to i8* - ; EVENT_CALLBACKS: call void @__dfsan_store_callback(i[[#SBITS]] [[E12]], i8* [[P]]) + ; EVENT_CALLBACKS: call void @__dfsan_store_callback(i[[#SBITS]] [[E12]], ptr %p) ; FAST: @store_array2.dfsan - ; FAST: [[S:%.*]] = load [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to [2 x i[[#SBITS]]]*), align [[ALIGN:2]] + ; FAST: [[S:%.*]] = load [2 x i[[#SBITS]]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] ; FAST: [[E1:%.*]] = extractvalue [2 x i[[#SBITS]]] [[S]], 0 ; FAST: [[E2:%.*]] = extractvalue [2 x i[[#SBITS]]] [[S]], 1 ; FAST: [[E12:%.*]] = or i[[#SBITS]] [[E1]], [[E2]] - ; FAST: [[SP0:%.*]] = getelementptr i[[#SBITS]], i[[#SBITS]]* [[SP:%.*]], i32 0 - ; FAST: store i[[#SBITS]] [[E12]], i[[#SBITS]]* [[SP0]], align [[#SBYTES]] - ; FAST: [[SP1:%.*]] = getelementptr i[[#SBITS]], i[[#SBITS]]* [[SP]], i32 1 - ; FAST: store i[[#SBITS]] [[E12]], i[[#SBITS]]* [[SP1]], align [[#SBYTES]] + ; FAST: [[SP0:%.*]] = getelementptr i[[#SBITS]], ptr [[SP:%.*]], i32 0 + ; FAST: store i[[#SBITS]] [[E12]], ptr [[SP0]], align [[#SBYTES]] + ; FAST: [[SP1:%.*]] = getelementptr i[[#SBITS]], ptr [[SP]], i32 1 + ; FAST: store i[[#SBITS]] [[E12]], ptr [[SP1]], align [[#SBYTES]] ; COMBINE_STORE_PTR: @store_array2.dfsan ; COMBINE_STORE_PTR: [[O:%.*]] = or i[[#SBITS]] ; COMBINE_STORE_PTR: [[U:%.*]] = or i[[#SBITS]] [[O]] - ; COMBINE_STORE_PTR: [[P1:%.*]] = getelementptr i[[#SBITS]], i[[#SBITS]]* [[P:%.*]], i32 0 - ; COMBINE_STORE_PTR: store i[[#SBITS]] [[U]], i[[#SBITS]]* [[P1]], align [[#SBYTES]] - ; COMBINE_STORE_PTR: [[P2:%.*]] = getelementptr i[[#SBITS]], i[[#SBITS]]* [[P]], i32 1 - ; COMBINE_STORE_PTR: store i[[#SBITS]] [[U]], i[[#SBITS]]* [[P2]], align [[#SBYTES]] + ; COMBINE_STORE_PTR: [[P1:%.*]] = getelementptr i[[#SBITS]], ptr [[P:%.*]], i32 0 + ; COMBINE_STORE_PTR: store i[[#SBITS]] [[U]], ptr [[P1]], align [[#SBYTES]] + ; COMBINE_STORE_PTR: [[P2:%.*]] = getelementptr i[[#SBITS]], ptr [[P]], i32 1 + ; COMBINE_STORE_PTR: store i[[#SBITS]] [[U]], ptr [[P2]], align [[#SBYTES]] - store [2 x i1] %a, [2 x i1]* %p + store [2 x i1] %a, ptr %p ret void } -define void @store_array17([17 x i1] %a, [17 x i1]* %p) { +define void @store_array17([17 x i1] %a, ptr %p) { ; FAST: @store_array17.dfsan - ; FAST: %[[#R:]] = load [17 x i[[#SBITS]]], [17 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to [17 x i[[#SBITS]]]*), align 2 + ; FAST: %[[#R:]] = load [17 x i[[#SBITS]]], ptr @__dfsan_arg_tls, align 2 ; FAST: %[[#R+1]] = extractvalue [17 x i[[#SBITS]]] %[[#R]], 0 ; FAST: %[[#R+2]] = extractvalue [17 x i[[#SBITS]]] %[[#R]], 1 ; FAST: %[[#R+3]] = or i[[#SBITS]] %[[#R+1]], %[[#R+2]] @@ -265,29 +264,28 @@ ; FAST: %[[#VREG+5]] = insertelement <8 x i[[#SBITS]]> %[[#VREG+4]], i[[#SBITS]] %[[#R+33]], i32 5 ; FAST: %[[#VREG+6]] = insertelement <8 x i[[#SBITS]]> %[[#VREG+5]], i[[#SBITS]] %[[#R+33]], i32 6 ; FAST: %[[#VREG+7]] = insertelement <8 x i[[#SBITS]]> %[[#VREG+6]], i[[#SBITS]] %[[#R+33]], i32 7 - ; FAST: %[[#VREG+8]] = bitcast i[[#SBITS]]* %[[P:.*]] to <8 x i[[#SBITS]]>* - ; FAST: %[[#VREG+9]] = getelementptr <8 x i[[#SBITS]]>, <8 x i[[#SBITS]]>* %[[#VREG+8]], i32 0 - ; FAST: store <8 x i[[#SBITS]]> %[[#VREG+7]], <8 x i[[#SBITS]]>* %[[#VREG+9]], align [[#SBYTES]] - ; FAST: %[[#VREG+10]] = getelementptr <8 x i[[#SBITS]]>, <8 x i[[#SBITS]]>* %[[#VREG+8]], i32 1 - ; FAST: store <8 x i[[#SBITS]]> %[[#VREG+7]], <8 x i[[#SBITS]]>* %[[#VREG+10]], align [[#SBYTES]] - ; FAST: %[[#VREG+11]] = getelementptr i[[#SBITS]], i[[#SBITS]]* %[[P]], i32 16 - ; FAST: store i[[#SBITS]] %[[#R+33]], i[[#SBITS]]* %[[#VREG+11]], align [[#SBYTES]] - store [17 x i1] %a, [17 x i1]* %p + ; FAST: %[[#VREG+8]] = getelementptr <8 x i[[#SBITS]]>, ptr %[[P:.*]], i32 0 + ; FAST: store <8 x i[[#SBITS]]> %[[#VREG+7]], ptr %[[#VREG+8]], align [[#SBYTES]] + ; FAST: %[[#VREG+9]] = getelementptr <8 x i[[#SBITS]]>, ptr %[[P]], i32 1 + ; FAST: store <8 x i[[#SBITS]]> %[[#VREG+7]], ptr %[[#VREG+9]], align [[#SBYTES]] + ; FAST: %[[#VREG+10]] = getelementptr i[[#SBITS]], ptr %[[P]], i32 16 + ; FAST: store i[[#SBITS]] %[[#R+33]], ptr %[[#VREG+10]], align [[#SBYTES]] + store [17 x i1] %a, ptr %p ret void } define [2 x i32] @const_array() { ; FAST: @const_array.dfsan - ; FAST: store [2 x i[[#SBITS]]] zeroinitializer, [2 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [2 x i[[#SBITS]]]*), align 2 + ; FAST: store [2 x i[[#SBITS]]] zeroinitializer, ptr @__dfsan_retval_tls, align 2 ret [2 x i32] [ i32 42, i32 11 ] } define [4 x i8] @call_array([4 x i8] %a) { ; FAST-LABEL: @call_array.dfsan - ; FAST: %[[#R:]] = load [4 x i[[#SBITS]]], [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to [4 x i[[#SBITS]]]*), align [[ALIGN:2]] - ; FAST: store [4 x i[[#SBITS]]] %[[#R]], [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to [4 x i[[#SBITS]]]*), align [[ALIGN]] - ; FAST: %_dfsret = load [4 x i[[#SBITS]]], [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [4 x i[[#SBITS]]]*), align [[ALIGN]] - ; FAST: store [4 x i[[#SBITS]]] %_dfsret, [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [4 x i[[#SBITS]]]*), align [[ALIGN]] + ; FAST: %[[#R:]] = load [4 x i[[#SBITS]]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] + ; FAST: store [4 x i[[#SBITS]]] %[[#R]], ptr @__dfsan_arg_tls, align [[ALIGN]] + ; FAST: %_dfsret = load [4 x i[[#SBITS]]], ptr @__dfsan_retval_tls, align [[ALIGN]] + ; FAST: store [4 x i[[#SBITS]]] %_dfsret, ptr @__dfsan_retval_tls, align [[ALIGN]] %r = call [4 x i8] @pass_array([4 x i8] %a) ret [4 x i8] %r @@ -297,7 +295,7 @@ define i8 @fun_with_large_args(i1 %i, %LargeArr %a) { ; FAST: @fun_with_large_args.dfsan - ; FAST: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 + ; FAST: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align 2 %r = extractvalue %LargeArr %a, 0 ret i8 %r } @@ -310,7 +308,7 @@ define i8 @call_fun_with_large_ret() { ; FAST: @call_fun_with_large_ret.dfsan - ; FAST: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 + ; FAST: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align 2 %r = call %LargeArr @fun_with_large_ret() %e = extractvalue %LargeArr %r, 0 ret i8 %e @@ -318,8 +316,8 @@ define i8 @call_fun_with_large_args(i1 %i, %LargeArr %a) { ; FAST: @call_fun_with_large_args.dfsan - ; FAST: [[I:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]] - ; FAST: store i[[#SBITS]] [[I]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; FAST: [[I:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] + ; FAST: store i[[#SBITS]] [[I]], ptr @__dfsan_arg_tls, align [[ALIGN]] ; FAST: %r = call i8 @fun_with_large_args.dfsan(i1 %i, [1000 x i8] %a) %r = call i8 @fun_with_large_args(i1 %i, %LargeArr %a) diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/atomics.ll b/llvm/test/Instrumentation/DataFlowSanitizer/atomics.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/atomics.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/atomics.ll @@ -9,270 +9,258 @@ ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] -define i32 @AtomicRmwXchg(i32* %p, i32 %x) { +define i32 @AtomicRmwXchg(ptr %p, i32 %x) { entry: ; COMM: atomicrmw xchg: store clean shadow/origin, return clean shadow/origin ; CHECK-LABEL: @AtomicRmwXchg.dfsan ; CHECK-NOT: @__dfsan_arg_origin_tls ; CHECK-NOT: @__dfsan_arg_tls - ; CHECK: %[[#INTP:]] = ptrtoint i32* %p to i64 + ; CHECK: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#%.10d,MASK:]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#SHADOW_PTR64:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#NUM_BITS:mul(SBITS,4)]]* - ; CHECK-NEXT: store i[[#NUM_BITS]] 0, i[[#NUM_BITS]]* %[[#SHADOW_PTR64]], align [[#SBYTES]] - ; CHECK-NEXT: atomicrmw xchg i32* %p, i32 %x seq_cst - ; CHECK-NEXT: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 - ; CHECK_ORIGIN-NEXT: store i32 0, i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: store i[[#NUM_BITS:mul(SBITS,4)]] 0, ptr %[[#SHADOW_PTR]], align [[#SBYTES]] + ; CHECK-NEXT: atomicrmw xchg ptr %p, i32 %x seq_cst + ; CHECK-NEXT: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align 2 + ; CHECK_ORIGIN-NEXT: store i32 0, ptr @__dfsan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 - %0 = atomicrmw xchg i32* %p, i32 %x seq_cst + %0 = atomicrmw xchg ptr %p, i32 %x seq_cst ret i32 %0 } -define i32 @AtomicRmwMax(i32* %p, i32 %x) { +define i32 @AtomicRmwMax(ptr %p, i32 %x) { ; COMM: atomicrmw max: exactly the same as above ; CHECK-LABEL: @AtomicRmwMax.dfsan ; CHECK-NOT: @__dfsan_arg_origin_tls ; CHECK-NOT: @__dfsan_arg_tls - ; CHECK: %[[#INTP:]] = ptrtoint i32* %p to i64 + ; CHECK: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#%.10d,MASK:]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#SHADOW_PTR64:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#NUM_BITS:mul(SBITS,4)]]* - ; CHECK-NEXT: store i[[#NUM_BITS]] 0, i[[#NUM_BITS]]* %[[#SHADOW_PTR64]], align [[#SBYTES]] - ; CHECK-NEXT: atomicrmw max i32* %p, i32 %x seq_cst - ; CHECK-NEXT: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 - ; CHECK_ORIGIN-NEXT: store i32 0, i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: store i[[#NUM_BITS]] 0, ptr %[[#SHADOW_PTR]], align [[#SBYTES]] + ; CHECK-NEXT: atomicrmw max ptr %p, i32 %x seq_cst + ; CHECK-NEXT: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align 2 + ; CHECK_ORIGIN-NEXT: store i32 0, ptr @__dfsan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 entry: - %0 = atomicrmw max i32* %p, i32 %x seq_cst + %0 = atomicrmw max ptr %p, i32 %x seq_cst ret i32 %0 } -define i32 @Cmpxchg(i32* %p, i32 %a, i32 %b) { +define i32 @Cmpxchg(ptr %p, i32 %a, i32 %b) { ; COMM: cmpxchg: store clean shadow/origin, return clean shadow/origin ; CHECK-LABEL: @Cmpxchg.dfsan ; CHECK-NOT: @__dfsan_arg_origin_tls ; CHECK-NOT: @__dfsan_arg_tls - ; CHECK: %[[#INTP:]] = ptrtoint i32* %p to i64 + ; CHECK: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#%.10d,MASK:]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#SHADOW_PTR64:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#NUM_BITS:mul(SBITS,4)]]* - ; CHECK-NEXT: store i[[#NUM_BITS]] 0, i[[#NUM_BITS]]* %[[#SHADOW_PTR64]], align [[#SBYTES]] - ; CHECK-NEXT: %pair = cmpxchg i32* %p, i32 %a, i32 %b seq_cst seq_cst - ; CHECK: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 - ; CHECK_ORIGIN-NEXT: store i32 0, i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: store i[[#NUM_BITS]] 0, ptr %[[#SHADOW_PTR]], align [[#SBYTES]] + ; CHECK-NEXT: %pair = cmpxchg ptr %p, i32 %a, i32 %b seq_cst seq_cst + ; CHECK: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align 2 + ; CHECK_ORIGIN-NEXT: store i32 0, ptr @__dfsan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 entry: - %pair = cmpxchg i32* %p, i32 %a, i32 %b seq_cst seq_cst + %pair = cmpxchg ptr %p, i32 %a, i32 %b seq_cst seq_cst %0 = extractvalue { i32, i1 } %pair, 0 ret i32 %0 } -define i32 @CmpxchgMonotonic(i32* %p, i32 %a, i32 %b) { +define i32 @CmpxchgMonotonic(ptr %p, i32 %a, i32 %b) { ; COMM: relaxed cmpxchg: bump up to "release monotonic" ; CHECK-LABEL: @CmpxchgMonotonic.dfsan ; CHECK-NOT: @__dfsan_arg_origin_tls ; CHECK-NOT: @__dfsan_arg_tls - ; CHECK: %[[#INTP:]] = ptrtoint i32* %p to i64 + ; CHECK: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#%.10d,MASK:]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#SHADOW_PTR64:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#NUM_BITS:mul(SBITS,4)]]* - ; CHECK-NEXT: store i[[#NUM_BITS]] 0, i[[#NUM_BITS]]* %[[#SHADOW_PTR64]], align [[#SBYTES]] - ; CHECK-NEXT: %pair = cmpxchg i32* %p, i32 %a, i32 %b release monotonic - ; CHECK: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 - ; CHECK_ORIGIN-NEXT: store i32 0, i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: store i[[#NUM_BITS]] 0, ptr %[[#SHADOW_PTR]], align [[#SBYTES]] + ; CHECK-NEXT: %pair = cmpxchg ptr %p, i32 %a, i32 %b release monotonic + ; CHECK: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align 2 + ; CHECK_ORIGIN-NEXT: store i32 0, ptr @__dfsan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 entry: - %pair = cmpxchg i32* %p, i32 %a, i32 %b monotonic monotonic + %pair = cmpxchg ptr %p, i32 %a, i32 %b monotonic monotonic %0 = extractvalue { i32, i1 } %pair, 0 ret i32 %0 } -define i32 @AtomicLoad(i32* %p) { +define i32 @AtomicLoad(ptr %p) { ; COMM: atomic load: load shadow value after app value ; CHECK-LABEL: @AtomicLoad.dfsan - ; CHECK_ORIGIN: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 - ; CHECK: %a = load atomic i32, i32* %p seq_cst, align 16 - ; CHECK: %[[#SHADOW_PTR:]] = inttoptr i64 {{.*}} to i[[#SBITS]]* - ; CHECK_ORIGIN: %[[#ORIGIN_PTR:]] = inttoptr i64 {{.*}} to i32* - ; CHECK_ORIGIN: %[[#AO:]] = load i32, i32* %[[#ORIGIN_PTR]], align 16 - ; CHECK: %[[#SHADOW_PTR64:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#NUM_BITS:mul(SBITS,4)]]* - ; CHECK: load i[[#NUM_BITS]], i[[#NUM_BITS]]* %[[#SHADOW_PTR64]], align [[#SBYTES]] + ; CHECK_ORIGIN: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 + ; CHECK: %a = load atomic i32, ptr %p seq_cst, align 16 + ; CHECK: %[[#SHADOW_PTR:]] = inttoptr i64 {{.*}} to ptr + ; CHECK_ORIGIN: %[[#ORIGIN_PTR:]] = inttoptr i64 {{.*}} to ptr + ; CHECK_ORIGIN: %[[#AO:]] = load i32, ptr %[[#ORIGIN_PTR]], align 16 + ; CHECK: load i[[#NUM_BITS]], ptr %[[#SHADOW_PTR]], align [[#SBYTES]] ; CHECK: %[[#AP_S:]] = or i[[#SBITS]] {{.*}}, %[[#PS]] ; CHECK_ORIGIN: %[[#PS_NZ:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 ; CHECK_ORIGIN: %[[#AP_O:]] = select i1 %[[#PS_NZ]], i32 %[[#PO]], i32 %[[#AO]] - ; CHECK: store i[[#SBITS]] %[[#AP_S]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 - ; CHECK_ORIGIN: store i32 %[[#AP_O]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i[[#SBITS]] %[[#AP_S]], ptr @__dfsan_retval_tls, align 2 + ; CHECK_ORIGIN: store i32 %[[#AP_O]], ptr @__dfsan_retval_origin_tls, align 4 ; CHECK: ret i32 %a entry: - %a = load atomic i32, i32* %p seq_cst, align 16 + %a = load atomic i32, ptr %p seq_cst, align 16 ret i32 %a } -define i32 @AtomicLoadAcquire(i32* %p) { +define i32 @AtomicLoadAcquire(ptr %p) { ; COMM: atomic load: load shadow value after app value ; CHECK-LABEL: @AtomicLoadAcquire.dfsan - ; CHECK_ORIGIN: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 - ; CHECK: %a = load atomic i32, i32* %p acquire, align 16 - ; CHECK: %[[#SHADOW_PTR:]] = inttoptr i64 {{.*}} to i[[#SBITS]]* - ; CHECK_ORIGIN: %[[#ORIGIN_PTR:]] = inttoptr i64 {{.*}} to i32* - ; CHECK_ORIGIN: %[[#AO:]] = load i32, i32* %[[#ORIGIN_PTR]], align 16 - ; CHECK: %[[#SHADOW_PTR64:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#NUM_BITS:mul(SBITS,4)]]* - ; CHECK: load i[[#NUM_BITS]], i[[#NUM_BITS]]* %[[#SHADOW_PTR64]], align [[#SBYTES]] + ; CHECK_ORIGIN: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 + ; CHECK: %a = load atomic i32, ptr %p acquire, align 16 + ; CHECK: %[[#SHADOW_PTR:]] = inttoptr i64 {{.*}} to ptr + ; CHECK_ORIGIN: %[[#ORIGIN_PTR:]] = inttoptr i64 {{.*}} to ptr + ; CHECK_ORIGIN: %[[#AO:]] = load i32, ptr %[[#ORIGIN_PTR]], align 16 + ; CHECK: load i[[#NUM_BITS]], ptr %[[#SHADOW_PTR]], align [[#SBYTES]] ; CHECK: %[[#AP_S:]] = or i[[#SBITS]] {{.*}}, %[[#PS]] ; CHECK_ORIGIN: %[[#PS_NZ:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 ; CHECK_ORIGIN: %[[#AP_O:]] = select i1 %[[#PS_NZ]], i32 %[[#PO]], i32 %[[#AO]] - ; CHECK: store i[[#SBITS]] %[[#AP_S]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 - ; CHECK_ORIGIN: store i32 %[[#AP_O]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i[[#SBITS]] %[[#AP_S]], ptr @__dfsan_retval_tls, align 2 + ; CHECK_ORIGIN: store i32 %[[#AP_O]], ptr @__dfsan_retval_origin_tls, align 4 ; CHECK: ret i32 %a entry: - %a = load atomic i32, i32* %p acquire, align 16 + %a = load atomic i32, ptr %p acquire, align 16 ret i32 %a } -define i32 @AtomicLoadMonotonic(i32* %p) { +define i32 @AtomicLoadMonotonic(ptr %p) { ; COMM: atomic load monotonic: bump up to load acquire ; CHECK-LABEL: @AtomicLoadMonotonic.dfsan - ; CHECK_ORIGIN: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 - ; CHECK: %a = load atomic i32, i32* %p acquire, align 16 - ; CHECK: %[[#SHADOW_PTR:]] = inttoptr i64 {{.*}} to i[[#SBITS]]* - ; CHECK_ORIGIN: %[[#ORIGIN_PTR:]] = inttoptr i64 {{.*}} to i32* - ; CHECK_ORIGIN: %[[#AO:]] = load i32, i32* %[[#ORIGIN_PTR]], align 16 - ; CHECK: %[[#SHADOW_PTR64:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#NUM_BITS:mul(SBITS,4)]]* - ; CHECK: load i[[#NUM_BITS]], i[[#NUM_BITS]]* %[[#SHADOW_PTR64]], align [[#SBYTES]] + ; CHECK_ORIGIN: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 + ; CHECK: %a = load atomic i32, ptr %p acquire, align 16 + ; CHECK: %[[#SHADOW_PTR:]] = inttoptr i64 {{.*}} to ptr + ; CHECK_ORIGIN: %[[#ORIGIN_PTR:]] = inttoptr i64 {{.*}} to ptr + ; CHECK_ORIGIN: %[[#AO:]] = load i32, ptr %[[#ORIGIN_PTR]], align 16 + ; CHECK: load i[[#NUM_BITS]], ptr %[[#SHADOW_PTR]], align [[#SBYTES]] ; CHECK: %[[#AP_S:]] = or i[[#SBITS]] {{.*}}, %[[#PS]] ; CHECK_ORIGIN: %[[#PS_NZ:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 ; CHECK_ORIGIN: %[[#AP_O:]] = select i1 %[[#PS_NZ]], i32 %[[#PO]], i32 %[[#AO]] - ; CHECK: store i[[#SBITS]] %[[#AP_S]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 - ; CHECK_ORIGIN: store i32 %[[#AP_O]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i[[#SBITS]] %[[#AP_S]], ptr @__dfsan_retval_tls, align 2 + ; CHECK_ORIGIN: store i32 %[[#AP_O]], ptr @__dfsan_retval_origin_tls, align 4 ; CHECK: ret i32 %a entry: - %a = load atomic i32, i32* %p monotonic, align 16 + %a = load atomic i32, ptr %p monotonic, align 16 ret i32 %a } -define i32 @AtomicLoadUnordered(i32* %p) { +define i32 @AtomicLoadUnordered(ptr %p) { ; COMM: atomic load unordered: bump up to load acquire ; CHECK-LABEL: @AtomicLoadUnordered.dfsan - ; CHECK_ORIGIN: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 - ; CHECK: %a = load atomic i32, i32* %p acquire, align 16 - ; CHECK: %[[#SHADOW_PTR:]] = inttoptr i64 {{.*}} to i[[#SBITS]]* - ; CHECK_ORIGIN: %[[#ORIGIN_PTR:]] = inttoptr i64 {{.*}} to i32* - ; CHECK_ORIGIN: %[[#AO:]] = load i32, i32* %[[#ORIGIN_PTR]], align 16 - ; CHECK: %[[#SHADOW_PTR64:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#NUM_BITS:mul(SBITS,4)]]* - ; CHECK: load i[[#NUM_BITS]], i[[#NUM_BITS]]* %[[#SHADOW_PTR64]], align [[#SBYTES]] + ; CHECK_ORIGIN: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 + ; CHECK: %a = load atomic i32, ptr %p acquire, align 16 + ; CHECK: %[[#SHADOW_PTR:]] = inttoptr i64 {{.*}} to ptr + ; CHECK_ORIGIN: %[[#ORIGIN_PTR:]] = inttoptr i64 {{.*}} to ptr + ; CHECK_ORIGIN: %[[#AO:]] = load i32, ptr %[[#ORIGIN_PTR]], align 16 + ; CHECK: load i[[#NUM_BITS]], ptr %[[#SHADOW_PTR]], align [[#SBYTES]] ; CHECK: %[[#AP_S:]] = or i[[#SBITS]] {{.*}}, %[[#PS]] ; CHECK_ORIGIN: %[[#PS_NZ:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 ; CHECK_ORIGIN: %[[#AP_O:]] = select i1 %[[#PS_NZ]], i32 %[[#PO]], i32 %[[#AO]] - ; CHECK: store i[[#SBITS]] %[[#AP_S]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 - ; CHECK_ORIGIN: store i32 %[[#AP_O]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i[[#SBITS]] %[[#AP_S]], ptr @__dfsan_retval_tls, align 2 + ; CHECK_ORIGIN: store i32 %[[#AP_O]], ptr @__dfsan_retval_origin_tls, align 4 ; CHECK: ret i32 %a entry: - %a = load atomic i32, i32* %p unordered, align 16 + %a = load atomic i32, ptr %p unordered, align 16 ret i32 %a } -define void @AtomicStore(i32* %p, i32 %x) { +define void @AtomicStore(ptr %p, i32 %x) { ; COMM: atomic store: store clean shadow value before app value ; CHECK-LABEL: @AtomicStore.dfsan ; CHECK-NOT: @__dfsan_arg_origin_tls ; CHECK-NOT: @__dfsan_arg_tls ; CHECK_ORIGIN-NOT: 35184372088832 - ; CHECK: %[[#INTP:]] = ptrtoint i32* %p to i64 + ; CHECK: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#%.10d,MASK:]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#SHADOW_PTR64:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#NUM_BITS:mul(SBITS,4)]]* - ; CHECK-NEXT: store i[[#NUM_BITS]] 0, i[[#NUM_BITS]]* %[[#SHADOW_PTR64]], align [[#SBYTES]] - ; CHECK: store atomic i32 %x, i32* %p seq_cst, align 16 + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: store i[[#NUM_BITS]] 0, ptr %[[#SHADOW_PTR]], align [[#SBYTES]] + ; CHECK: store atomic i32 %x, ptr %p seq_cst, align 16 ; CHECK: ret void entry: - store atomic i32 %x, i32* %p seq_cst, align 16 + store atomic i32 %x, ptr %p seq_cst, align 16 ret void } -define void @AtomicStoreRelease(i32* %p, i32 %x) { +define void @AtomicStoreRelease(ptr %p, i32 %x) { ; COMM: atomic store: store clean shadow value before app value ; CHECK-LABEL: @AtomicStoreRelease.dfsan ; CHECK-NOT: @__dfsan_arg_origin_tls ; CHECK-NOT: @__dfsan_arg_tls ; CHECK_ORIGIN-NOT: 35184372088832 - ; CHECK: %[[#INTP:]] = ptrtoint i32* %p to i64 + ; CHECK: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#%.10d,MASK:]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#SHADOW_PTR64:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#NUM_BITS:mul(SBITS,4)]]* - ; CHECK-NEXT: store i[[#NUM_BITS]] 0, i[[#NUM_BITS]]* %[[#SHADOW_PTR64]], align [[#SBYTES]] - ; CHECK: store atomic i32 %x, i32* %p release, align 16 + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: store i[[#NUM_BITS]] 0, ptr %[[#SHADOW_PTR]], align [[#SBYTES]] + ; CHECK: store atomic i32 %x, ptr %p release, align 16 ; CHECK: ret void entry: - store atomic i32 %x, i32* %p release, align 16 + store atomic i32 %x, ptr %p release, align 16 ret void } -define void @AtomicStoreMonotonic(i32* %p, i32 %x) { +define void @AtomicStoreMonotonic(ptr %p, i32 %x) { ; COMM: atomic store monotonic: bumped up to store release ; CHECK-LABEL: @AtomicStoreMonotonic.dfsan ; CHECK-NOT: @__dfsan_arg_origin_tls ; CHECK-NOT: @__dfsan_arg_tls ; CHECK_ORIGIN-NOT: 35184372088832 - ; CHECK: %[[#INTP:]] = ptrtoint i32* %p to i64 + ; CHECK: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#%.10d,MASK:]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#SHADOW_PTR64:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#NUM_BITS:mul(SBITS,4)]]* - ; CHECK-NEXT: store i[[#NUM_BITS]] 0, i[[#NUM_BITS]]* %[[#SHADOW_PTR64]], align [[#SBYTES]] - ; CHECK: store atomic i32 %x, i32* %p release, align 16 + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: store i[[#NUM_BITS]] 0, ptr %[[#SHADOW_PTR]], align [[#SBYTES]] + ; CHECK: store atomic i32 %x, ptr %p release, align 16 ; CHECK: ret void entry: - store atomic i32 %x, i32* %p monotonic, align 16 + store atomic i32 %x, ptr %p monotonic, align 16 ret void } -define void @AtomicStoreUnordered(i32* %p, i32 %x) { +define void @AtomicStoreUnordered(ptr %p, i32 %x) { ; COMM: atomic store unordered: bumped up to store release ; CHECK-LABEL: @AtomicStoreUnordered.dfsan ; CHECK-NOT: @__dfsan_arg_origin_tls ; CHECK-NOT: @__dfsan_arg_tls ; CHECK_ORIGIN-NOT: 35184372088832 - ; CHECK: %[[#INTP:]] = ptrtoint i32* %p to i64 + ; CHECK: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#%.10d,MASK:]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#SHADOW_PTR64:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#NUM_BITS:mul(SBITS,4)]]* - ; CHECK-NEXT: store i[[#NUM_BITS]] 0, i[[#NUM_BITS]]* %[[#SHADOW_PTR64]], align [[#SBYTES]] - ; CHECK: store atomic i32 %x, i32* %p release, align 16 + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: store i[[#NUM_BITS]] 0, ptr %[[#SHADOW_PTR]], align [[#SBYTES]] + ; CHECK: store atomic i32 %x, ptr %p release, align 16 ; CHECK: ret void entry: - store atomic i32 %x, i32* %p unordered, align 16 + store atomic i32 %x, ptr %p unordered, align 16 ret void } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/basic.ll b/llvm/test/Instrumentation/DataFlowSanitizer/basic.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/basic.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/basic.ll @@ -14,38 +14,38 @@ ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] -define i8 @load(i8* %p) { +define i8 @load(ptr %p) { ; CHECK-LABEL: define i8 @load.dfsan ; CHECK: xor i64 {{.*}}, [[SHADOW_XOR_MASK]] ; CHECK: ret i8 %a - %a = load i8, i8* %p + %a = load i8, ptr %p ret i8 %a } -define void @store(i8* %p) { +define void @store(ptr %p) { ; CHECK-LABEL: define void @store.dfsan ; CHECK: xor i64 {{.*}}, [[SHADOW_XOR_MASK]] ; CHECK: ret void - store i8 0, i8* %p + store i8 0, ptr %p ret void } -; CHECK: declare void @__dfsan_load_callback(i[[#SBITS]], i8*) -; CHECK: declare void @__dfsan_store_callback(i[[#SBITS]], i8*) -; CHECK: declare void @__dfsan_mem_transfer_callback(i[[#SBITS]]*, i64) +; CHECK: declare void @__dfsan_load_callback(i[[#SBITS]], ptr) +; CHECK: declare void @__dfsan_store_callback(i[[#SBITS]], ptr) +; CHECK: declare void @__dfsan_mem_transfer_callback(ptr, i64) ; CHECK: declare void @__dfsan_cmp_callback(i[[#SBITS]]) ; CHECK: ; Function Attrs: nounwind memory(read) -; CHECK-NEXT: declare zeroext i[[#SBITS]] @__dfsan_union_load(i[[#SBITS]]*, i64) +; CHECK-NEXT: declare zeroext i[[#SBITS]] @__dfsan_union_load(ptr, i64) ; CHECK: ; Function Attrs: nounwind memory(read) -; CHECK-NEXT: declare zeroext i64 @__dfsan_load_label_and_origin(i8*, i64) +; CHECK-NEXT: declare zeroext i64 @__dfsan_load_label_and_origin(ptr, i64) -; CHECK: declare void @__dfsan_unimplemented(i8*) -; CHECK: declare void @__dfsan_set_label(i[[#SBITS]] zeroext, i32 zeroext, i8*, i64) +; CHECK: declare void @__dfsan_unimplemented(ptr) +; CHECK: declare void @__dfsan_set_label(i[[#SBITS]] zeroext, i32 zeroext, ptr, i64) ; CHECK: declare void @__dfsan_nonzero_label() -; CHECK: declare void @__dfsan_vararg_wrapper(i8*) +; CHECK: declare void @__dfsan_vararg_wrapper(ptr) ; CHECK: declare zeroext i32 @__dfsan_chain_origin(i32 zeroext) ; CHECK: declare zeroext i32 @__dfsan_chain_origin_if_tainted(i[[#SBITS]] zeroext, i32 zeroext) -; CHECK: declare void @__dfsan_mem_origin_transfer(i8*, i8*, i64) -; CHECK: declare void @__dfsan_maybe_store_origin(i[[#SBITS]] zeroext, i8*, i64, i32 zeroext) +; CHECK: declare void @__dfsan_mem_origin_transfer(ptr, ptr, i64) +; CHECK: declare void @__dfsan_maybe_store_origin(i[[#SBITS]] zeroext, ptr, i64, i32 zeroext) diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/call.ll b/llvm/test/Instrumentation/DataFlowSanitizer/call.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/call.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/call.ll @@ -28,29 +28,29 @@ declare i32 @__gxx_personality_v0(...) -declare i8* @__cxa_begin_catch(i8*) +declare ptr @__cxa_begin_catch(ptr) declare void @__cxa_end_catch() declare void @g(...) ; CHECK-LABEL: @h.dfsan -; CHECK: personality {{.*}} @__gxx_personality_v0.dfsan {{.*}} { -define i32 @h() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +; CHECK: personality {{.*}} @__gxx_personality_v0.dfsan { +define i32 @h() personality ptr @__gxx_personality_v0 { entry: ; CHECK: invoke void (...) @g.dfsan(i32 42) invoke void (...) @g(i32 42) to label %try.cont unwind label %lpad lpad: - %0 = landingpad { i8*, i32 } - catch i8* null - %1 = extractvalue { i8*, i32 } %0, 0 + %0 = landingpad { ptr, i32 } + catch ptr null + %1 = extractvalue { ptr, i32 } %0, 0 - ; CHECK: store {{.*}} @__dfsan_arg_tls + ; CHECK: store {{.*}} @__dfsan_arg_tls ; CHECK: call {{.*}} @__cxa_begin_catch.dfsan ; CHECK: load {{.*}} @__dfsan_retval_tls - %2 = tail call i8* @__cxa_begin_catch(i8* %1) + %2 = tail call ptr @__cxa_begin_catch(ptr %1) ; CHECK: call {{.*}} @__cxa_end_catch.dfsan tail call void @__cxa_end_catch() diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/callback.ll b/llvm/test/Instrumentation/DataFlowSanitizer/callback.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/callback.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/callback.ll @@ -5,29 +5,29 @@ ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] -define i8 @load8(i8* %p) { - ; CHECK: call void @__dfsan_load_callback(i[[#SBITS]] %[[LABEL:.*]], i8* %p) - ; CHECK: %a = load i8, i8* %p - ; CHECK: store i[[#SBITS]] %[[LABEL]], i[[#SBITS]]* bitcast ({{.*}}* @__dfsan_retval_tls to i[[#SBITS]]*) +define i8 @load8(ptr %p) { + ; CHECK: call void @__dfsan_load_callback(i[[#SBITS]] %[[LABEL:.*]], ptr %p) + ; CHECK: %a = load i8, ptr %p + ; CHECK: store i[[#SBITS]] %[[LABEL]], ptr @__dfsan_retval_tls - %a = load i8, i8* %p + %a = load i8, ptr %p ret i8 %a } -define void @store8(i8* %p, i8 %a) { - ; CHECK: store i[[#SBITS]] %[[LABEL:.*]], i[[#SBITS]]* %{{.*}} - ; CHECK: call void @__dfsan_store_callback(i[[#SBITS]] %[[LABEL]], i8* %p) - ; CHECK: store i8 %a, i8* %p +define void @store8(ptr %p, i8 %a) { + ; CHECK: store i[[#SBITS]] %[[LABEL:.*]], ptr %{{.*}} + ; CHECK: call void @__dfsan_store_callback(i[[#SBITS]] %[[LABEL]], ptr %p) + ; CHECK: store i8 %a, ptr %p - store i8 %a, i8* %p + store i8 %a, ptr %p ret void } define i1 @cmp(i8 %a, i8 %b) { ; CHECK: call void @__dfsan_cmp_callback(i[[#SBITS]] %[[CMPLABEL:.*]]) ; CHECK: %c = icmp ne i8 %a, %b - ; CHECK: store i[[#SBITS]] %[[CMPLABEL]], i[[#SBITS]]* bitcast ({{.*}}* @__dfsan_retval_tls to i[[#SBITS]]*) + ; CHECK: store i[[#SBITS]] %[[CMPLABEL]], ptr @__dfsan_retval_tls %c = icmp ne i8 %a, %b ret i1 %c } \ No newline at end of file diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/custom_fun_callback_attributes.ll b/llvm/test/Instrumentation/DataFlowSanitizer/custom_fun_callback_attributes.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/custom_fun_callback_attributes.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/custom_fun_callback_attributes.ll @@ -3,30 +3,30 @@ ; Declare custom functions. Inputs/abilist.txt causes any function with a ; name matching /custom.*/ to be a custom function. -declare i32 @custom_fun_one_callback(i8 (i32, double)* %callback_arg) +declare i32 @custom_fun_one_callback(ptr %callback_arg) declare i32 @custom_fun_two_callbacks( - i8 (i32, double)* %callback_arg1, + ptr %callback_arg1, i64 %an_int, - i8 (i32, double)* %callback_arg2 + ptr %callback_arg2 ) declare i8 @a_callback_fun(i32, double) ; CHECK-LABEL: @call_custom_funs_with_callbacks.dfsan -define void @call_custom_funs_with_callbacks(i8 (i32, double)* %callback_arg) { +define void @call_custom_funs_with_callbacks(ptr %callback_arg) { ;; The callback should have attribute 'nonnull': ; CHECK: call signext i32 @__dfsw_custom_fun_one_callback( %call1 = call signext i32 @custom_fun_one_callback( - i8 (i32, double)* nonnull @a_callback_fun + ptr nonnull @a_callback_fun ) ;; Call a custom function with two callbacks. Check their annotations. ; CHECK: call i32 @__dfsw_custom_fun_two_callbacks( ; CHECK: i64 12345 %call2 = call i32 @custom_fun_two_callbacks( - i8 (i32, double)* nonnull @a_callback_fun, + ptr nonnull @a_callback_fun, i64 12345, - i8 (i32, double)* noalias @a_callback_fun + ptr noalias @a_callback_fun ) ret void } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/custom_fun_varargs_attributes.ll b/llvm/test/Instrumentation/DataFlowSanitizer/custom_fun_varargs_attributes.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/custom_fun_varargs_attributes.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/custom_fun_varargs_attributes.ll @@ -8,19 +8,19 @@ declare i16 @custom_varargs(i64, ...) ; CHECK-LABEL: @call_custom_varargs.dfsan -define void @call_custom_varargs(i8* %buf) { +define void @call_custom_varargs(ptr %buf) { ;; All arguments have an annotation. Check that the transformed function ;; preserves each annotation. - ; CHECK: call zeroext i16 (i64, i[[#SBITS]], i[[#SBITS]]*, i[[#SBITS]]*, ...) + ; CHECK: call zeroext i16 (i64, i[[#SBITS]], ptr, ptr, ...) ; CHECK-SAME: @__dfsw_custom_varargs ; CHECK-SAME: i64 signext 200 - ; CHECK-SAME: i8* nonnull + ; CHECK-SAME: ptr nonnull ; CHECK-SAME: i64 zeroext 20 ; CHECK-SAME: i32 signext 1 %call = call zeroext i16 (i64, ...) @custom_varargs( i64 signext 200, - i8* nonnull %buf, + ptr nonnull %buf, i64 zeroext 20, i32 signext 1 ) diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/debug-nonzero-labels.ll b/llvm/test/Instrumentation/DataFlowSanitizer/debug-nonzero-labels.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/debug-nonzero-labels.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/debug-nonzero-labels.ll @@ -18,15 +18,15 @@ ; CHECK: [[ARGCMP2:%.*]] = icmp ne i[[#SBITS]] [[ARGLABEL2]], 0 ; CHECK: br i1 [[ARGCMP2]] %x = add i32 %0, %1 - store i32 %x, i32* %i + store i32 %x, ptr %i ; CHECK: [[CALL:%.*]] = call i32 @g.dfsan() ; CHECK: [[RETLABEL:%.*]] = load i[[#SBITS]], {{.*}} @__dfsan_retval_tls ; CHECK: [[CALLCMP:%.*]] = icmp ne i[[#SBITS]] [[RETLABEL]], 0 ; CHECK: br i1 [[CALLCMP]] %call = call i32 @g() - ; CHECK: [[LOCALLABEL:%.*]] = load i[[#SBITS]], i[[#SBITS]]* [[LOCALLABELALLOCA]] + ; CHECK: [[LOCALLABEL:%.*]] = load i[[#SBITS]], ptr [[LOCALLABELALLOCA]] ; CHECK: [[LOCALCMP:%.*]] = icmp ne i[[#SBITS]] [[LOCALLABEL]], 0 ; CHECK: br i1 [[LOCALCMP]] - %load = load i32, i32* %i + %load = load i32, ptr %i ret i32 %load } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/dont_combine_offset_labels_on_gep.ll b/llvm/test/Instrumentation/DataFlowSanitizer/dont_combine_offset_labels_on_gep.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/dont_combine_offset_labels_on_gep.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/dont_combine_offset_labels_on_gep.ll @@ -7,15 +7,15 @@ ; CHECK: @__dfsan_retval_tls = external thread_local(initialexec) global [[TLS_ARR]] ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] -define i32* @gepop([10 x [20 x i32]]* %p, i32 %a, i32 %b, i32 %c) { +define ptr @gepop(ptr %p, i32 %a, i32 %b, i32 %c) { ; CHECK: @gepop.dfsan - ; CHECK_ORIGIN: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align [[ALIGN_O:4]] - ; CHECK: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN_S:2]] - ; CHECK: %e = getelementptr [10 x [20 x i32]], [10 x [20 x i32]]* %p, i32 %a, i32 %b, i32 %c - ; CHECK: store i[[#SBITS]] %[[#PS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN_S]] - ; CHECK_ORIGIN: store i32 %[[#PO]], i32* @__dfsan_retval_origin_tls, align [[ALIGN_O]] + ; CHECK_ORIGIN: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align [[ALIGN_O:4]] + ; CHECK: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN_S:2]] + ; CHECK: %e = getelementptr [10 x [20 x i32]], ptr %p, i32 %a, i32 %b, i32 %c + ; CHECK: store i[[#SBITS]] %[[#PS]], ptr @__dfsan_retval_tls, align [[ALIGN_S]] + ; CHECK_ORIGIN: store i32 %[[#PO]], ptr @__dfsan_retval_origin_tls, align [[ALIGN_O]] - %e = getelementptr [10 x [20 x i32]], [10 x [20 x i32]]* %p, i32 %a, i32 %b, i32 %c - ret i32* %e + %e = getelementptr [10 x [20 x i32]], ptr %p, i32 %a, i32 %b, i32 %c + ret ptr %e } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/extern_weak.ll b/llvm/test/Instrumentation/DataFlowSanitizer/extern_weak.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/extern_weak.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/extern_weak.ll @@ -13,7 +13,7 @@ ; CHECK-LABEL: @call_if_exists.dfsan ; Ensure comparison is preserved ; CHECK: br i1 icmp ne ([[FUNCPTRTY:.*]] @ExternWeak, [[FUNCPTRTY]] null), label %use_func, label %avoid_func - br i1 icmp ne (i8 (i8)* @ExternWeak, i8 (i8)* null), label %use_func, label %avoid_func + br i1 icmp ne (ptr @ExternWeak, ptr null), label %use_func, label %avoid_func use_func: ; CHECK: use_func: diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/force_zero.ll b/llvm/test/Instrumentation/DataFlowSanitizer/force_zero.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/force_zero.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/force_zero.ll @@ -2,14 +2,13 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-linux-gnu" -define i32 @function_to_force_zero(i32 %0, i32* %1) { +define i32 @function_to_force_zero(i32 %0, ptr %1) { ; CHECK-LABEL: define i32 @function_to_force_zero.dfsan ; CHECK: %[[#SHADOW_XOR:]] = xor i64 {{.*}}, [[SHADOW_XOR_MASK]] - ; CHECK: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_XOR]] to i8* - ; CHECK: %[[#SHADOW_BITCAST:]] = bitcast i8* %[[#SHADOW_PTR]] to i32* - ; CHECK: store i32 0, i32* %[[#SHADOW_BITCAST]] + ; CHECK: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_XOR]] to ptr + ; CHECK: store i32 0, ptr %[[#SHADOW_PTR]] ; CHECK: store i32 %{{.*}} - store i32 %0, i32* %1, align 4 + store i32 %0, ptr %1, align 4 ; CHECK: store i8 0, {{.*}}@__dfsan_retval_tls ; CHECK: ret i32 ret i32 %0 diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/ignore_persnality_routine.ll b/llvm/test/Instrumentation/DataFlowSanitizer/ignore_persnality_routine.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/ignore_persnality_routine.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/ignore_persnality_routine.ll @@ -6,7 +6,7 @@ declare i32 @__gxx_personality_v0(...) -declare i8* @__cxa_begin_catch(i8*) +declare ptr @__cxa_begin_catch(ptr) declare void @__cxa_end_catch() @@ -16,15 +16,15 @@ ; CHECK-SAME: personality {{.*}}@"dfsw$__gxx_personality_v0"{{.*}} ; CHECK-IGNORE-LABEL: @h.dfsan ; CHECK-IGNORE-SAME: personality {{.*}}__gxx_personality_v0{{.*}} -define i32 @h() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +define i32 @h() personality ptr @__gxx_personality_v0 { invoke void (...) @g(i32 42) to label %try.cont unwind label %lpad lpad: - %1 = landingpad { i8*, i32 } - catch i8* null - %2 = extractvalue { i8*, i32 } %1, 0 - %3 = tail call i8* @__cxa_begin_catch(i8* %2) + %1 = landingpad { ptr, i32 } + catch ptr null + %2 = extractvalue { ptr, i32 } %1, 0 + %3 = tail call ptr @__cxa_begin_catch(ptr %2) tail call void @__cxa_end_catch() br label %try.cont diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/load.ll b/llvm/test/Instrumentation/DataFlowSanitizer/load.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/load.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/load.ll @@ -9,82 +9,80 @@ ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] -define {} @load0({}* %p) { +define {} @load0(ptr %p) { ; CHECK-LABEL: @load0.dfsan - ; CHECK-NEXT: %a = load {}, {}* %p, align 1 - ; CHECK-NEXT: store {} zeroinitializer, {}* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to {}*), align [[ALIGN:2]] + ; CHECK-NEXT: %a = load {}, ptr %p, align 1 + ; CHECK-NEXT: store {} zeroinitializer, ptr @__dfsan_retval_tls, align [[ALIGN:2]] ; CHECK-NEXT: ret {} %a - %a = load {}, {}* %p + %a = load {}, ptr %p ret {} %a } -define i8 @load8(i8* %p) { +define i8 @load8(ptr %p) { ; CHECK-LABEL: @load8.dfsan - ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: %[[#INTP:]] = ptrtoint i8* %p to i64 + ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] + ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#%.10d,MASK:]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#SHADOW:]] = load i[[#SBITS]], i[[#SBITS]]* %[[#SHADOW_PTR]] + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: %[[#SHADOW:]] = load i[[#SBITS]], ptr %[[#SHADOW_PTR]] ; COMBINE_LOAD_PTR-NEXT: %[[#SHADOW:]] = or i[[#SBITS]] %[[#SHADOW]], %[[#PS]] - ; CHECK-NEXT: %a = load i8, i8* %p - ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %a = load i8, ptr %p + ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK-NEXT: ret i8 %a - %a = load i8, i8* %p + %a = load i8, ptr %p ret i8 %a } -define i16 @load16(i16* %p) { +define i16 @load16(ptr %p) { ; CHECK-LABEL: @load16.dfsan - ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: %[[#INTP:]] = ptrtoint i16* %p to i64 + ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] + ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#SHADOW_PTR+1]] = getelementptr i[[#SBITS]], i[[#SBITS]]* %[[#SHADOW_PTR]], i64 1 - ; CHECK-NEXT: %[[#SHADOW:]] = load i[[#SBITS]], i[[#SBITS]]* %[[#SHADOW_PTR]] - ; CHECK-NEXT: %[[#SHADOW+1]] = load i[[#SBITS]], i[[#SBITS]]* %[[#SHADOW_PTR+1]] + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: %[[#SHADOW_PTR+1]] = getelementptr i[[#SBITS]], ptr %[[#SHADOW_PTR]], i64 1 + ; CHECK-NEXT: %[[#SHADOW:]] = load i[[#SBITS]], ptr %[[#SHADOW_PTR]] + ; CHECK-NEXT: %[[#SHADOW+1]] = load i[[#SBITS]], ptr %[[#SHADOW_PTR+1]] ; CHECK-NEXT: %[[#SHADOW:]] = or i[[#SBITS]] %[[#SHADOW]], %[[#SHADOW+1]] ; COMBINE_LOAD_PTR-NEXT: %[[#SHADOW:]] = or i[[#SBITS]] %[[#SHADOW]], %[[#PS]] - ; CHECK-NEXT: %a = load i16, i16* %p - ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %a = load i16, ptr %p + ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK-NEXT: ret i16 %a - %a = load i16, i16* %p + %a = load i16, ptr %p ret i16 %a } -define i32 @load32(i32* %p) { +define i32 @load32(ptr %p) { ; CHECK-LABEL: @load32.dfsan - ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: %[[#INTP:]] = ptrtoint i32* %p to i64 + ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] + ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#WIDE_SHADOW_PTR:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#WSBITS:mul(SBITS,4)]]* - ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = load i[[#WSBITS]], i[[#WSBITS]]* %[[#WIDE_SHADOW_PTR]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = load i[[#WSBITS:mul(SBITS,4)]], ptr %[[#SHADOW_PTR]], align [[#SBYTES]] ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i[[#WSBITS]] %[[#WIDE_SHADOW]], [[#mul(SBITS,2)]] ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i[[#WSBITS]] %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]] ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i[[#WSBITS]] %[[#WIDE_SHADOW]], [[#SBITS]] ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i[[#WSBITS]] %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]] ; CHECK-NEXT: %[[#SHADOW:]] = trunc i[[#WSBITS]] %[[#WIDE_SHADOW]] to i[[#SBITS]] ; COMBINE_LOAD_PTR-NEXT: %[[#SHADOW:]] = or i[[#SBITS]] %[[#SHADOW]], %[[#PS]] - ; CHECK-NEXT: %a = load i32, i32* %p, align 4 - ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %a = load i32, ptr %p, align 4 + ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK-NEXT: ret i32 %a - %a = load i32, i32* %p + %a = load i32, ptr %p ret i32 %a } -define i64 @load64(i64* %p) { +define i64 @load64(ptr %p) { ; CHECK-LABEL: @load64.dfsan - ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: %[[#INTP:]] = ptrtoint i64* %p to i64 + ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] + ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#WIDE_SHADOW_PTR:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i64* - ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = load i64, i64* %[[#WIDE_SHADOW_PTR]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = load i64, ptr %[[#SHADOW_PTR]], align [[#SBYTES]] ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i64 %[[#WIDE_SHADOW]], 32 ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]] ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i64 %[[#WIDE_SHADOW]], 16 @@ -93,24 +91,23 @@ ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]] ; CHECK-NEXT: %[[#SHADOW:]] = trunc i64 %[[#WIDE_SHADOW]] to i[[#SBITS]] ; COMBINE_LOAD_PTR-NEXT: %[[#SHADOW:]] = or i[[#SBITS]] %[[#SHADOW]], %[[#PS]] - ; CHECK-NEXT: %a = load i64, i64* %p, align 8 - ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %a = load i64, ptr %p, align 8 + ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK-NEXT: ret i64 %a - %a = load i64, i64* %p + %a = load i64, ptr %p ret i64 %a } -define i128 @load128(i128* %p) { +define i128 @load128(ptr %p) { ; CHECK-LABEL: @load128.dfsan - ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: %[[#INTP:]] = ptrtoint i128* %p to i64 + ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] + ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#WIDE_SHADOW_PTR:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i64* - ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = load i64, i64* %[[#WIDE_SHADOW_PTR]], align [[#SBYTES]] - ; CHECK-NEXT: %[[#WIDE_SHADOW_PTR2:]] = getelementptr i64, i64* %[[#WIDE_SHADOW_PTR]], i64 1 - ; CHECK-NEXT: %[[#WIDE_SHADOW2:]] = load i64, i64* %[[#WIDE_SHADOW_PTR2]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = load i64, ptr %[[#SHADOW_PTR]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#WIDE_SHADOW_PTR2:]] = getelementptr i64, ptr %[[#SHADOW_PTR]], i64 1 + ; CHECK-NEXT: %[[#WIDE_SHADOW2:]] = load i64, ptr %[[#WIDE_SHADOW_PTR2]], align [[#SBYTES]] ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW2]] ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i64 %[[#WIDE_SHADOW]], 32 ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]] @@ -120,38 +117,38 @@ ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]] ; CHECK-NEXT: %[[#SHADOW:]] = trunc i64 %[[#WIDE_SHADOW]] to i[[#SBITS]] ; COMBINE_LOAD_PTR-NEXT: %[[#SHADOW:]] = or i[[#SBITS]] %[[#SHADOW]], %[[#PS]] - ; CHECK-NEXT: %a = load i128, i128* %p, align 8 - ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %a = load i128, ptr %p, align 8 + ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK-NEXT: ret i128 %a - %a = load i128, i128* %p + %a = load i128, ptr %p ret i128 %a } -define i17 @load17(i17* %p) { +define i17 @load17(ptr %p) { ; CHECK-LABEL: @load17.dfsan - ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: %[[#INTP:]] = ptrtoint i17* %p to i64 + ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] + ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* - ; CHECK-NEXT: %[[#SHADOW:]] = call zeroext i8 @__dfsan_union_load(i[[#SBITS]]* %[[#SHADOW_PTR]], i64 3) + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr + ; CHECK-NEXT: %[[#SHADOW:]] = call zeroext i8 @__dfsan_union_load(ptr %[[#SHADOW_PTR]], i64 3) ; COMBINE_LOAD_PTR-NEXT: %[[#SHADOW:]] = or i[[#SBITS]] %[[#SHADOW]], %[[#PS]] - ; CHECK-NEXT: %a = load i17, i17* %p - ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %a = load i17, ptr %p + ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK-NEXT: ret i17 %a - %a = load i17, i17* %p + %a = load i17, ptr %p ret i17 %a } @X = constant i1 1 define i1 @load_global() { ; CHECK-LABEL: @load_global.dfsan - ; CHECK-NEXT: %a = load i1, i1* @X - ; CHECK-NEXT: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %a = load i1, ptr @X + ; CHECK-NEXT: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK-NEXT: ret i1 %a - %a = load i1, i1* @X + %a = load i1, ptr @X ret i1 %a } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/lookup_table.ll b/llvm/test/Instrumentation/DataFlowSanitizer/lookup_table.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/lookup_table.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/lookup_table.ll @@ -13,33 +13,33 @@ define i8 @load_lookup_table_a(i8 %p) { ; CHECK-LABEL: @load_lookup_table_a.dfsan - ; CHECK-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]] + ; CHECK-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] ; CHECK-NEXT: %c = zext i8 %p to i64 - ; CHECK-NEXT: %b = getelementptr inbounds [256 x i8], [256 x i8]* @lookup_table_a, i64 0, i64 %c - ; CHECK-NEXT: %a = load i8, i8* %b, align 1 + ; CHECK-NEXT: %b = getelementptr inbounds [256 x i8], ptr @lookup_table_a, i64 0, i64 %c + ; CHECK-NEXT: %a = load i8, ptr %b, align 1 ; Propagates p shadow when lookup_table_a flag is provided, otherwise propagates 0 shadow - ; LOOKUP_A-NEXT: store i[[#SBITS]] %[[#PS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] - ; NO_LOOKUP_A-NEXT: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; LOOKUP_A-NEXT: store i[[#SBITS]] %[[#PS]], ptr @__dfsan_retval_tls, align [[ALIGN]] + ; NO_LOOKUP_A-NEXT: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK-NEXT: ret i8 %a %c = zext i8 %p to i64 - %b = getelementptr inbounds [256 x i8], [256 x i8]* @lookup_table_a, i64 0, i64 %c - %a = load i8, i8* %b + %b = getelementptr inbounds [256 x i8], ptr @lookup_table_a, i64 0, i64 %c + %a = load i8, ptr %b ret i8 %a } define i8 @load_lookup_table_b(i8 %p) { ; CHECK-LABEL: @load_lookup_table_b.dfsan - ; CHECK-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 + ; CHECK-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 ; CHECK-NEXT: %c = zext i8 %p to i64 - ; CHECK-NEXT: %b = getelementptr inbounds [256 x i8], [256 x i8]* @lookup_table_b, i64 0, i64 %c - ; CHECK-NEXT: %a = load i8, i8* %b, align 1 + ; CHECK-NEXT: %b = getelementptr inbounds [256 x i8], ptr @lookup_table_b, i64 0, i64 %c + ; CHECK-NEXT: %a = load i8, ptr %b, align 1 ; Propagates 0 shadow - ; CHECK-NEXT: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK-NEXT: ret i8 %a %c = zext i8 %p to i64 - %b = getelementptr inbounds [256 x i8], [256 x i8]* @lookup_table_b, i64 0, i64 %c - %a = load i8, i8* %b, align 1 + %b = getelementptr inbounds [256 x i8], ptr @lookup_table_b, i64 0, i64 %c + %a = load i8, ptr %b, align 1 ret i8 %a } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/memset.ll b/llvm/test/Instrumentation/DataFlowSanitizer/memset.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/memset.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/memset.ll @@ -5,13 +5,13 @@ ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] -declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) +declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) -define void @ms(i8* %p, i8 %v) { +define void @ms(ptr %p, i8 %v) { ; CHECK-LABEL: @ms.dfsan - ; CHECK-SAME: (i8* %p, i8 %v) + ; CHECK-SAME: (ptr %p, i8 %v) ; CHECK: %[[ARGLABEL:.*]] = load i[[#SBITS]], {{.*}} @__dfsan_arg_tls - ; CHECK: call void @__dfsan_set_label(i[[#SBITS]] %[[ARGLABEL]], i32 0, i8* %p, i64 1) - call void @llvm.memset.p0i8.i64(i8* %p, i8 %v, i64 1, i1 1) + ; CHECK: call void @__dfsan_set_label(i[[#SBITS]] %[[ARGLABEL]], i32 0, ptr %p, i64 1) + call void @llvm.memset.p0.i64(ptr %p, i8 %v, i64 1, i1 1) ret void } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/musttailcall.ll b/llvm/test/Instrumentation/DataFlowSanitizer/musttailcall.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/musttailcall.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/musttailcall.ll @@ -45,15 +45,13 @@ ret i32 %r } -declare i32* @mismatching_callee(i32) +declare ptr @mismatching_callee(i32) -; CHECK-LABEL: define i8* @mismatching_musttail_call.dfsan -define i8* @mismatching_musttail_call(i32) { - %r = musttail call i32* @mismatching_callee(i32 %0) - ; CHECK: musttail call i32* @mismatching_callee.dfsan +; CHECK-LABEL: define ptr @mismatching_musttail_call.dfsan +define ptr @mismatching_musttail_call(i32) { + %r = musttail call ptr @mismatching_callee(i32 %0) + ; CHECK: musttail call ptr @mismatching_callee.dfsan ; COMM: No instrumentation between call and ret. - ; CHECK-NEXT: bitcast i32* {{.*}} to i8* - %c = bitcast i32* %r to i8* - ; CHECK-NEXT: ret i8* - ret i8* %c + ; CHECK-NEXT: ret ptr + ret ptr %r } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_abilist.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_abilist.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_abilist.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_abilist.ll @@ -13,7 +13,7 @@ define i32 @call_discard(i32 %a, i32 %b) { ; CHECK: @call_discard.dfsan ; CHECK: %r = call i32 @discard(i32 %a, i32 %b) - ; CHECK: store i32 0, i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i32 0, ptr @__dfsan_retval_origin_tls, align 4 ; CHECK: ret i32 %r %r = call i32 @discard(i32 %a, i32 %b) @@ -27,11 +27,11 @@ } define i32 @call_functional(i32 %a, i32 %b) { - ; CHECK: @call_functional.dfsan - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 + ; CHECK-LABEL: @call_functional.dfsan + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls ; CHECK: [[RO:%.*]] = select i1 {{.*}}, i32 [[BO]], i32 [[AO]] - ; CHECK: store i32 [[RO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i32 [[RO]], ptr @__dfsan_retval_origin_tls, align 4 %r = call i32 @functional(i32 %a, i32 %b) ret i32 %r @@ -43,9 +43,9 @@ } define i32 @call_uninstrumented(i32 %a, i32 %b) { - ; CHECK: @call_uninstrumented.dfsan + ; CHECK-LABEL: @call_uninstrumented.dfsan ; CHECK: %r = call i32 @uninstrumented(i32 %a, i32 %b) - ; CHECK: store i32 0, i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i32 0, ptr @__dfsan_retval_origin_tls, align 4 ; CHECK: ret i32 %r %r = call i32 @uninstrumented(i32 %a, i32 %b) @@ -57,12 +57,12 @@ ret i32 %c } -@discardg = alias i32 (i32, i32), i32 (i32, i32)* @g +@discardg = alias i32 (i32, i32), ptr @g define i32 @call_discardg(i32 %a, i32 %b) { ; CHECK: @call_discardg.dfsan ; CHECK: %r = call i32 @discardg(i32 %a, i32 %b) - ; CHECK: store i32 0, i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i32 0, ptr @__dfsan_retval_origin_tls, align 4 ; CHECK: ret i32 %r %r = call i32 @discardg(i32 %a, i32 %b) @@ -87,7 +87,7 @@ ret i32 %c } -define i32 @custom_cb_with_ret(i32 (i32, i32)* %cb, i32 %a, i32 %b) { +define i32 @custom_cb_with_ret(ptr %cb, i32 %a, i32 %b) { %r = call i32 %cb(i32 %a, i32 %b) ret i32 %r } @@ -97,7 +97,7 @@ ret i32 %c } -define void @custom_cb_without_ret(void (i32, i32)* %cb, i32 %a, i32 %b) { +define void @custom_cb_without_ret(ptr %cb, i32 %a, i32 %b) { call void %cb(i32 %a, i32 %b) ret void } @@ -106,19 +106,19 @@ ret void } -define i32 (i32, i32)* @ret_custom() { +define ptr @ret_custom() { ; CHECK: @ret_custom.dfsan - ; CHECK: store i32 0, i32* @__dfsan_retval_origin_tls, align 4 - - ret i32 (i32, i32)* @custom_with_ret + ; CHECK: store i32 0, ptr @__dfsan_retval_origin_tls, align 4 + + ret ptr @custom_with_ret } define void @call_custom_without_ret(i32 %a, i32 %b) { ; CHECK: @call_custom_without_ret.dfsan - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 - ; CHECK: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 + ; CHECK: [[AS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 ; CHECK: call void @__dfso_custom_without_ret(i32 %a, i32 %b, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], i32 zeroext [[AO]], i32 zeroext [[BO]]) ; CHECK-NEXT: ret void @@ -129,16 +129,16 @@ define i32 @call_custom_with_ret(i32 %a, i32 %b) { ; CHECK: @call_custom_with_ret.dfsan ; CHECK: %originreturn = alloca i32, align 4 - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 ; CHECK: %labelreturn = alloca i[[#SBITS]], align [[#SBYTES]] - ; CHECK: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 - ; CHECK: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 - ; CHECK: {{.*}} = call i32 @__dfso_custom_with_ret(i32 %a, i32 %b, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], i[[#SBITS]]* %labelreturn, i32 zeroext [[AO]], i32 zeroext [[BO]], i32* %originreturn) - ; CHECK: [[RS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* %labelreturn, align [[#SBYTES]] - ; CHECK: [[RO:%.*]] = load i32, i32* %originreturn, align 4 - ; CHECK: store i[[#SBITS]] [[RS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 - ; CHECK: store i32 [[RO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 + ; CHECK: [[AS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 + ; CHECK: {{.*}} = call i32 @__dfso_custom_with_ret(i32 %a, i32 %b, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], ptr %labelreturn, i32 zeroext [[AO]], i32 zeroext [[BO]], ptr %originreturn) + ; CHECK: [[RS:%.*]] = load i[[#SBITS]], ptr %labelreturn, align [[#SBYTES]] + ; CHECK: [[RO:%.*]] = load i32, ptr %originreturn, align 4 + ; CHECK: store i[[#SBITS]] [[RS]], ptr @__dfsan_retval_tls, align 2 + ; CHECK: store i32 [[RO]], ptr @__dfsan_retval_origin_tls, align 4 %r = call i32 @custom_with_ret(i32 %a, i32 %b) ret i32 %r @@ -147,18 +147,18 @@ define void @call_custom_varg_without_ret(i32 %a, i32 %b) { ; CHECK: @call_custom_varg_without_ret.dfsan ; CHECK: %originva = alloca [1 x i32], align 4 - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 ; CHECK: %labelva = alloca [1 x i[[#SBITS]]], align [[#SBYTES]] - ; CHECK: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 - ; CHECK: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 - ; CHECK: [[VS0:%.*]] = getelementptr inbounds [1 x i[[#SBITS]]], [1 x i[[#SBITS]]]* %labelva, i32 0, i32 0 - ; CHECK: store i[[#SBITS]] [[AS]], i[[#SBITS]]* [[VS0]], align [[#SBYTES]] - ; CHECK: [[VS0:%.*]] = getelementptr inbounds [1 x i[[#SBITS]]], [1 x i[[#SBITS]]]* %labelva, i32 0, i32 0 - ; CHECK: [[VO0:%.*]] = getelementptr inbounds [1 x i32], [1 x i32]* %originva, i32 0, i32 0 - ; CHECK: store i32 [[AO]], i32* [[VO0]], align 4 - ; CHECK: [[VO0:%.*]] = getelementptr inbounds [1 x i32], [1 x i32]* %originva, i32 0, i32 0 - ; CHECK: call void (i32, i32, i[[#SBITS]], i[[#SBITS]], i[[#SBITS]]*, i32, i32, i32*, ...) @__dfso_custom_varg_without_ret(i32 %a, i32 %b, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], i[[#SBITS]]* [[VS0]], i32 zeroext [[AO]], i32 zeroext [[BO]], i32* [[VO0]], i32 %a) + ; CHECK: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 + ; CHECK: [[AS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 + ; CHECK: [[VS0:%.*]] = getelementptr inbounds [1 x i[[#SBITS]]], ptr %labelva, i32 0, i32 0 + ; CHECK: store i[[#SBITS]] [[AS]], ptr [[VS0]], align [[#SBYTES]] + ; CHECK: [[VS0:%.*]] = getelementptr inbounds [1 x i[[#SBITS]]], ptr %labelva, i32 0, i32 0 + ; CHECK: [[VO0:%.*]] = getelementptr inbounds [1 x i32], ptr %originva, i32 0, i32 0 + ; CHECK: store i32 [[AO]], ptr [[VO0]], align 4 + ; CHECK: [[VO0:%.*]] = getelementptr inbounds [1 x i32], ptr %originva, i32 0, i32 0 + ; CHECK: call void (i32, i32, i[[#SBITS]], i[[#SBITS]], ptr, i32, i32, ptr, ...) @__dfso_custom_varg_without_ret(i32 %a, i32 %b, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], ptr [[VS0]], i32 zeroext [[AO]], i32 zeroext [[BO]], ptr [[VO0]], i32 %a) ; CHECK-NEXT: ret void call void (i32, i32, ...) @custom_varg_without_ret(i32 %a, i32 %b, i32 %a) @@ -169,23 +169,23 @@ ; CHECK: @call_custom_varg_with_ret.dfsan ; CHECK: %originreturn = alloca i32, align 4 ; CHECK: %originva = alloca [1 x i32], align 4 - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls ; CHECK: %labelreturn = alloca i[[#SBITS]], align [[#SBYTES]] ; CHECK: %labelva = alloca [1 x i[[#SBITS]]], align [[#SBYTES]] - ; CHECK: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 - ; CHECK: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 - ; CHECK: [[VS0:%.*]] = getelementptr inbounds [1 x i[[#SBITS]]], [1 x i[[#SBITS]]]* %labelva, i32 0, i32 0 - ; CHECK: store i[[#SBITS]] [[BS]], i[[#SBITS]]* [[VS0]], align [[#SBYTES]] - ; CHECK: [[VS0:%.*]] = getelementptr inbounds [1 x i[[#SBITS]]], [1 x i[[#SBITS]]]* %labelva, i32 0, i32 0 - ; CHECK: [[VO0:%.*]] = getelementptr inbounds [1 x i32], [1 x i32]* %originva, i32 0, i32 0 - ; CHECK: store i32 [[BO]], i32* [[VO0]], align 4 - ; CHECK: [[VO0:%.*]] = getelementptr inbounds [1 x i32], [1 x i32]* %originva, i32 0, i32 0 - ; CHECK: {{.*}} = call i32 (i32, i32, i[[#SBITS]], i[[#SBITS]], i[[#SBITS]]*, i[[#SBITS]]*, i32, i32, i32*, i32*, ...) @__dfso_custom_varg_with_ret(i32 %a, i32 %b, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], i[[#SBITS]]* [[VS0]], i[[#SBITS]]* %labelreturn, i32 zeroext [[AO]], i32 zeroext [[BO]], i32* [[VO0]], i32* %originreturn, i32 %b) - ; CHECK: [[RS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* %labelreturn, align [[#SBYTES]] - ; CHECK: [[RO:%.*]] = load i32, i32* %originreturn, align 4 - ; CHECK: store i[[#SBITS]] [[RS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 - ; CHECK: store i32 [[RO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 + ; CHECK: [[AS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 + ; CHECK: [[VS0:%.*]] = getelementptr inbounds [1 x i[[#SBITS]]], ptr %labelva, i32 0, i32 0 + ; CHECK: store i[[#SBITS]] [[BS]], ptr [[VS0]], align [[#SBYTES]] + ; CHECK: [[VS0:%.*]] = getelementptr inbounds [1 x i[[#SBITS]]], ptr %labelva, i32 0, i32 0 + ; CHECK: [[VO0:%.*]] = getelementptr inbounds [1 x i32], ptr %originva, i32 0, i32 0 + ; CHECK: store i32 [[BO]], ptr [[VO0]], align 4 + ; CHECK: [[VO0:%.*]] = getelementptr inbounds [1 x i32], ptr %originva, i32 0, i32 0 + ; CHECK: {{.*}} = call i32 (i32, i32, i[[#SBITS]], i[[#SBITS]], ptr, ptr, i32, i32, ptr, ptr, ...) @__dfso_custom_varg_with_ret(i32 %a, i32 %b, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], ptr [[VS0]], ptr %labelreturn, i32 zeroext [[AO]], i32 zeroext [[BO]], ptr [[VO0]], ptr %originreturn, i32 %b) + ; CHECK: [[RS:%.*]] = load i[[#SBITS]], ptr %labelreturn, align [[#SBYTES]] + ; CHECK: [[RO:%.*]] = load i32, ptr %originreturn, align 4 + ; CHECK: store i[[#SBITS]] [[RS]], ptr @__dfsan_retval_tls, align 2 + ; CHECK: store i32 [[RO]], ptr @__dfsan_retval_origin_tls, align 4 %r = call i32 (i32, i32, ...) @custom_varg_with_ret(i32 %a, i32 %b, i32 %b) ret i32 %r @@ -194,104 +194,104 @@ define i32 @call_custom_cb_with_ret(i32 %a, i32 %b) { ; CHECK: @call_custom_cb_with_ret.dfsan ; CHECK: %originreturn = alloca i32, align 4 - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 ; CHECK: %labelreturn = alloca i[[#SBITS]], align [[#SBYTES]] - ; CHECK: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 - ; CHECK: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 - ; CHECK: {{.*}} = call i32 @__dfso_custom_cb_with_ret(i32 (i32, i32)* @cb_with_ret.dfsan, i32 %a, i32 %b, i[[#SBITS]] zeroext 0, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], i[[#SBITS]]* %labelreturn, i32 zeroext 0, i32 zeroext [[AO]], i32 zeroext [[BO]], i32* %originreturn) - ; CHECK: [[RS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* %labelreturn, align [[#SBYTES]] - ; CHECK: [[RO:%.*]] = load i32, i32* %originreturn, align 4 - ; CHECK: store i[[#SBITS]] [[RS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 - ; CHECK: store i32 [[RO]], i32* @__dfsan_retval_origin_tls, align 4 - - %r = call i32 @custom_cb_with_ret(i32 (i32, i32)* @cb_with_ret, i32 %a, i32 %b) + ; CHECK: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 + ; CHECK: [[AS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 + ; CHECK: {{.*}} = call i32 @__dfso_custom_cb_with_ret(ptr @cb_with_ret.dfsan, i32 %a, i32 %b, i[[#SBITS]] zeroext 0, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], ptr %labelreturn, i32 zeroext 0, i32 zeroext [[AO]], i32 zeroext [[BO]], ptr %originreturn) + ; CHECK: [[RS:%.*]] = load i[[#SBITS]], ptr %labelreturn, align [[#SBYTES]] + ; CHECK: [[RO:%.*]] = load i32, ptr %originreturn, align 4 + ; CHECK: store i[[#SBITS]] [[RS]], ptr @__dfsan_retval_tls, align 2 + ; CHECK: store i32 [[RO]], ptr @__dfsan_retval_origin_tls, align 4 + + %r = call i32 @custom_cb_with_ret(ptr @cb_with_ret, i32 %a, i32 %b) ret i32 %r } define void @call_custom_cb_without_ret(i32 %a, i32 %b) { - ; CHECK: @call_custom_cb_without_ret.dfsan - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 - ; CHECK: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 - ; CHECK: call void @__dfso_custom_cb_without_ret(void (i32, i32)* @cb_without_ret.dfsan, i32 %a, i32 %b, i[[#SBITS]] zeroext 0, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], i32 zeroext 0, i32 zeroext [[AO]], i32 zeroext [[BO]]) + ; CHECK-LABEL: @call_custom_cb_without_ret.dfsan + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 + ; CHECK: [[AS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 + ; CHECK: call void @__dfso_custom_cb_without_ret(ptr @cb_without_ret.dfsan, i32 %a, i32 %b, i[[#SBITS]] zeroext 0, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], i32 zeroext 0, i32 zeroext [[AO]], i32 zeroext [[BO]]) ; CHECK-NEXT: ret void - call void @custom_cb_without_ret(void (i32, i32)* @cb_without_ret, i32 %a, i32 %b) + call void @custom_cb_without_ret(ptr @cb_without_ret, i32 %a, i32 %b) ret void } ; CHECK: define i32 @discardg(i32 %0, i32 %1) ; CHECK: [[R:%.*]] = call i32 @g.dfsan -; CHECK-NEXT: %_dfsret = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 -; CHECK-NEXT: %_dfsret_o = load i32, i32* @__dfsan_retval_origin_tls, align 4 +; CHECK-NEXT: %_dfsret = load i[[#SBITS]], ptr @__dfsan_retval_tls, align 2 +; CHECK-NEXT: %_dfsret_o = load i32, ptr @__dfsan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 [[R]] ; CHECK: define linkonce_odr void @"dfso$custom_without_ret"(i32 %0, i32 %1) -; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 -; CHECK-NEXT: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 -; CHECK-NEXT: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 -; CHECK-NEXT: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 +; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 +; CHECK-NEXT: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 +; CHECK-NEXT: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 +; CHECK-NEXT: [[AS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 ; CHECK-NEXT: call void @__dfso_custom_without_ret(i32 %0, i32 %1, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], i32 zeroext [[AO]], i32 zeroext [[BO]]) ; CHECK-NEXT: ret void ; CHECK: define linkonce_odr i32 @"dfso$custom_with_ret"(i32 %0, i32 %1) ; CHECK: %originreturn = alloca i32, align 4 -; CHECK-NEXT: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 -; CHECK-NEXT: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 +; CHECK-NEXT: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 +; CHECK-NEXT: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 ; CHECK-NEXT: %labelreturn = alloca i[[#SBITS]], align [[#SBYTES]] -; CHECK-NEXT: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 -; CHECK-NEXT: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 -; CHECK-NEXT: [[R:%.*]] = call i32 @__dfso_custom_with_ret(i32 %0, i32 %1, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], i[[#SBITS]]* %labelreturn, i32 zeroext [[AO]], i32 zeroext [[BO]], i32* %originreturn) -; CHECK-NEXT: [[RS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* %labelreturn, align [[#SBYTES]] -; CHECK-NEXT: [[RO:%.*]] = load i32, i32* %originreturn, align 4 -; CHECK-NEXT: store i[[#SBITS]] [[RS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 -; CHECK-NEXT: store i32 [[RO]], i32* @__dfsan_retval_origin_tls, align 4 +; CHECK-NEXT: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 +; CHECK-NEXT: [[AS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 +; CHECK-NEXT: [[R:%.*]] = call i32 @__dfso_custom_with_ret(i32 %0, i32 %1, i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], ptr %labelreturn, i32 zeroext [[AO]], i32 zeroext [[BO]], ptr %originreturn) +; CHECK-NEXT: [[RS:%.*]] = load i[[#SBITS]], ptr %labelreturn, align [[#SBYTES]] +; CHECK-NEXT: [[RO:%.*]] = load i32, ptr %originreturn, align 4 +; CHECK-NEXT: store i[[#SBITS]] [[RS]], ptr @__dfsan_retval_tls, align 2 +; CHECK-NEXT: store i32 [[RO]], ptr @__dfsan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 [[R]] ; CHECK: define linkonce_odr void @"dfso$custom_varg_without_ret"(i32 %0, i32 %1, ...) -; CHECK: call void @__dfsan_vararg_wrapper(i8* getelementptr inbounds ([24 x i8], [24 x i8]* @0, i32 0, i32 0)) +; CHECK: call void @__dfsan_vararg_wrapper(ptr @0) ; CHECK-NEXT: unreachable ; CHECK: define linkonce_odr i32 @"dfso$custom_varg_with_ret"(i32 %0, i32 %1, ...) -; CHECK: call void @__dfsan_vararg_wrapper(i8* getelementptr inbounds ([21 x i8], [21 x i8]* @1, i32 0, i32 0)) +; CHECK: call void @__dfsan_vararg_wrapper(ptr @1) ; CHECK-NEXT: unreachable -; CHECK: define linkonce_odr i32 @"dfso$custom_cb_with_ret"(i32 (i32, i32)* %0, i32 %1, i32 %2) +; CHECK: define linkonce_odr i32 @"dfso$custom_cb_with_ret"(ptr %0, i32 %1, i32 %2) ; CHECK: %originreturn = alloca i32, align 4 -; CHECK-NEXT: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 2), align 4 -; CHECK-NEXT: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 -; CHECK-NEXT: [[CO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 +; CHECK-NEXT: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4 +; CHECK-NEXT: [[AO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 +; CHECK-NEXT: [[CO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 ; CHECK-NEXT: %labelreturn = alloca i[[#SBITS]], align [[#SBYTES]] -; CHECK-NEXT: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 4) to i[[#SBITS]]*), align 2 -; CHECK-NEXT: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 -; CHECK-NEXT: [[CS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 -; CHECK-NEXT: [[R:%.*]] = call i32 @__dfso_custom_cb_with_ret(i32 (i32, i32)* %0, i32 %1, i32 %2, i[[#SBITS]] zeroext [[CS]], i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], i[[#SBITS]]* %labelreturn, i32 zeroext [[CO]], i32 zeroext [[AO]], i32 zeroext [[BO]], i32* %originreturn) -; CHECK-NEXT: [[RS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* %labelreturn, align [[#SBYTES]] -; CHECK-NEXT: [[RO:%.*]] = load i32, i32* %originreturn, align 4 -; CHECK-NEXT: store i[[#SBITS]] [[RS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 -; CHECK-NEXT: store i32 [[RO]], i32* @__dfsan_retval_origin_tls, align 4 +; CHECK-NEXT: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 4) to ptr), align 2 +; CHECK-NEXT: [[AS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 +; CHECK-NEXT: [[CS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 +; CHECK-NEXT: [[R:%.*]] = call i32 @__dfso_custom_cb_with_ret(ptr %0, i32 %1, i32 %2, i[[#SBITS]] zeroext [[CS]], i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], ptr %labelreturn, i32 zeroext [[CO]], i32 zeroext [[AO]], i32 zeroext [[BO]], ptr %originreturn) +; CHECK-NEXT: [[RS:%.*]] = load i[[#SBITS]], ptr %labelreturn, align [[#SBYTES]] +; CHECK-NEXT: [[RO:%.*]] = load i32, ptr %originreturn, align 4 +; CHECK-NEXT: store i[[#SBITS]] [[RS]], ptr @__dfsan_retval_tls, align 2 +; CHECK-NEXT: store i32 [[RO]], ptr @__dfsan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 [[R]] -; CHECK: define linkonce_odr void @"dfso$custom_cb_without_ret"(void (i32, i32)* %0, i32 %1, i32 %2) -; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 2), align 4 -; CHECK-NEXT: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 -; CHECK-NEXT: [[CO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 -; CHECK-NEXT: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 4) to i[[#SBITS]]*), align 2 -; CHECK-NEXT: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 -; CHECK-NEXT: [[CS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 -; CHECK-NEXT: call void @__dfso_custom_cb_without_ret(void (i32, i32)* %0, i32 %1, i32 %2, i[[#SBITS]] zeroext [[CS]], i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], i32 zeroext [[CO]], i32 zeroext [[AO]], i32 zeroext [[BO]]) +; CHECK: define linkonce_odr void @"dfso$custom_cb_without_ret"(ptr %0, i32 %1, i32 %2) +; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4 +; CHECK-NEXT: [[AO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 +; CHECK-NEXT: [[CO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 +; CHECK-NEXT: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 4) to ptr), align 2 +; CHECK-NEXT: [[AS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 +; CHECK-NEXT: [[CS:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 +; CHECK-NEXT: call void @__dfso_custom_cb_without_ret(ptr %0, i32 %1, i32 %2, i[[#SBITS]] zeroext [[CS]], i[[#SBITS]] zeroext [[AS]], i[[#SBITS]] zeroext [[BS]], i32 zeroext [[CO]], i32 zeroext [[AO]], i32 zeroext [[BO]]) ; CHECK-NEXT: ret void ; CHECK: declare void @__dfso_custom_without_ret(i32, i32, i[[#SBITS]], i[[#SBITS]], i32, i32) -; CHECK: declare i32 @__dfso_custom_with_ret(i32, i32, i[[#SBITS]], i[[#SBITS]], i[[#SBITS]]*, i32, i32, i32*) +; CHECK: declare i32 @__dfso_custom_with_ret(i32, i32, i[[#SBITS]], i[[#SBITS]], ptr, i32, i32, ptr) -; CHECK: declare i32 @__dfso_custom_cb_with_ret(i32 (i32, i32)*, i32, i32, i[[#SBITS]], i[[#SBITS]], i[[#SBITS]], i[[#SBITS]]*, i32, i32, i32, i32*) +; CHECK: declare i32 @__dfso_custom_cb_with_ret(ptr, i32, i32, i[[#SBITS]], i[[#SBITS]], i[[#SBITS]], ptr, i32, i32, i32, ptr) -; CHECK: declare void @__dfso_custom_cb_without_ret(void (i32, i32)*, i32, i32, i[[#SBITS]], i[[#SBITS]], i[[#SBITS]], i32, i32, i32) +; CHECK: declare void @__dfso_custom_cb_without_ret(ptr, i32, i32, i[[#SBITS]], i[[#SBITS]], i[[#SBITS]], i32, i32, i32) -; CHECK: declare void @__dfso_custom_varg_without_ret(i32, i32, i[[#SBITS]], i[[#SBITS]], i[[#SBITS]]*, i32, i32, i32*, ...) +; CHECK: declare void @__dfso_custom_varg_without_ret(i32, i32, i[[#SBITS]], i[[#SBITS]], ptr, i32, i32, ptr, ...) -; CHECK: declare i32 @__dfso_custom_varg_with_ret(i32, i32, i[[#SBITS]], i[[#SBITS]], i[[#SBITS]]*, i[[#SBITS]]*, i32, i32, i32*, i32*, ...) +; CHECK: declare i32 @__dfso_custom_varg_with_ret(i32, i32, i[[#SBITS]], i[[#SBITS]], ptr, ptr, i32, i32, ptr, ptr, ...) diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_cached_shadows.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_cached_shadows.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_cached_shadows.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_cached_shadows.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -S | FileCheck %s ; -; %15 and %17 have the same key in shadow cache. They should not reuse the same +; %i13 and %i15 have the same key in shadow cache. They should not reuse the same ; shadow because their blocks do not dominate each other. Origin tracking ; splt blocks. This test ensures DT is updated correctly, and cached shadows ; are not mis-used. @@ -11,78 +11,78 @@ ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] -define void @cached_shadows(double %0) { +define void @cached_shadows(double %arg) { ; CHECK: @cached_shadows.dfsan - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 + ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align ; CHECK: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]] - ; CHECK: [[L1:[0-9]+]]: + ; CHECK: [[L1:.+]]: ; CHECK: {{.*}} = phi i[[#SBITS]] ; CHECK: {{.*}} = phi i32 ; CHECK: {{.*}} = phi double [ 3.000000e+00 - ; CHECK: [[S_L1:%.*]] = phi i[[#SBITS]] [ 0, %[[L0:[0-9]+]] ], [ [[S_L7:%.*]], %[[L7:[0-9]+]] ] + ; CHECK: [[S_L1:%.*]] = phi i[[#SBITS]] [ 0, %[[L0:.*]] ], [ [[S_L7:%.*]], %[[L7:.*]] ] ; CHECK: [[O_L1:%.*]] = phi i32 [ 0, %[[L0]] ], [ [[O_L7:%.*]], %[[L7]] ] ; CHECK: [[V_L1:%.*]] = phi double [ 4.000000e+00, %[[L0]] ], [ [[V_L7:%.*]], %[[L7]] ] - ; CHECK: br i1 {{%[0-9]+}}, label %[[L2:[0-9]+]], label %[[L4:[0-9]+]] + ; CHECK: br i1 {{%.+}}, label %[[L2:.*]], label %[[L4:.*]] ; CHECK: [[L2]]: - ; CHECK: br i1 {{%[0-9]+}}, label %[[L3:[0-9]+]], label %[[L7]] + ; CHECK: br i1 {{%.+}}, label %[[L3:.+]], label %[[L7]] ; CHECK: [[L3]]: ; CHECK: [[S_L3:%.*]] = or i[[#SBITS]] ; CHECK: [[AS_NE_L3:%.*]] = icmp ne i[[#SBITS]] [[AS]], 0 - ; CHECK: [[O_L3:%.*]] = select i1 [[AS_NE_L3]], i32 %2, i32 [[O_L1]] - ; CHECK: [[V_L3:%.*]] = fsub double [[V_L1]], %0 + ; CHECK: [[O_L3:%.*]] = select i1 [[AS_NE_L3]], i32 %{{[0-9]+}}, i32 [[O_L1]] + ; CHECK: [[V_L3:%.*]] = fsub double [[V_L1]], %{{.+}} ; CHECK: br label %[[L7]] ; CHECK: [[L4]]: - ; CHECK: br i1 %_dfscmp, label %[[L5:[0-9]+]], label %[[L6:[0-9]+]] + ; CHECK: br i1 %_dfscmp, label %[[L5:.+]], label %[[L6:.+]], ; CHECK: [[L5]]: ; CHECK: br label %[[L6]] ; CHECK: [[L6]]: ; CHECK: [[S_L6:%.*]] = or i[[#SBITS]] ; CHECK: [[AS_NE_L6:%.*]] = icmp ne i[[#SBITS]] [[AS]], 0 ; CHECK: [[O_L6:%.*]] = select i1 [[AS_NE_L6]], i32 [[AO]], i32 [[O_L1]] - ; CHECK: [[V_L6:%.*]] = fadd double [[V_L1]], %0 + ; CHECK: [[V_L6:%.*]] = fadd double [[V_L1]], %{{.+}} ; CHECK: br label %[[L7]] ; CHECK: [[L7]]: ; CHECK: [[S_L7]] = phi i[[#SBITS]] [ [[S_L3]], %[[L3]] ], [ [[S_L1]], %[[L2]] ], [ [[S_L6]], %[[L6]] ] ; CHECK: [[O_L7]] = phi i32 [ [[O_L3]], %[[L3]] ], [ [[O_L1]], %[[L2]] ], [ [[O_L6]], %[[L6]] ] ; CHECK: [[V_L7]] = phi double [ [[V_L3]], %[[L3]] ], [ [[V_L1]], %[[L2]] ], [ [[V_L6]], %[[L6]] ] - ; CHECK: br i1 {{%[0-9]+}}, label %[[L1]], label %[[L8:[0-9]+]] + ; CHECK: br i1 %{{.+}}, label %[[L1]], label %[[L8:.+]] ; CHECK: [[L8]]: - - %2 = alloca double, align 8 - %3 = alloca double, align 8 - %4 = bitcast double* %2 to i8* - store volatile double 1.000000e+00, double* %2, align 8 - %5 = bitcast double* %3 to i8* - store volatile double 2.000000e+00, double* %3, align 8 - br label %6 +bb: + %i = alloca double, align 8 + %i1 = alloca double, align 8 + %i2 = bitcast double* %i to i8* + store volatile double 1.000000e+00, double* %i, align 8 + %i3 = bitcast double* %i1 to i8* + store volatile double 2.000000e+00, double* %i1, align 8 + br label %bb4 -6: ; preds = %18, %1 - %7 = phi double [ 3.000000e+00, %1 ], [ %19, %18 ] - %8 = phi double [ 4.000000e+00, %1 ], [ %20, %18 ] - %9 = load volatile double, double* %3, align 8 - %10 = fcmp une double %9, 0.000000e+00 - %11 = load volatile double, double* %3, align 8 - br i1 %10, label %12, label %16 +bb4: ; preds = %bb16, %bb + %i5 = phi double [ 3.000000e+00, %bb ], [ %i17, %bb16 ] + %i6 = phi double [ 4.000000e+00, %bb ], [ %i18, %bb16 ] + %i7 = load volatile double, double* %i1, align 8 + %i8 = fcmp une double %i7, 0.000000e+00 + %i9 = load volatile double, double* %i1, align 8 + br i1 %i8, label %bb10, label %bb14 -12: ; preds = %6 - %13 = fcmp une double %11, 0.000000e+00 - br i1 %13, label %14, label %18 +bb10: ; preds = %bb4 + %i11 = fcmp une double %i9, 0.000000e+00 + br i1 %i11, label %bb12, label %bb16 -14: ; preds = %12 - %15 = fsub double %8, %0 - br label %18 +bb12: ; preds = %bb10 + %i13 = fsub double %i6, %arg + br label %bb16 -16: ; preds = %6 - store volatile double %11, double* %2, align 8 - %17 = fadd double %8, %0 - br label %18 +bb14: ; preds = %bb4 + store volatile double %i9, double* %i, align 8 + %i15 = fadd double %i6, %arg + br label %bb16 -18: ; preds = %16, %14, %12 - %19 = phi double [ %8, %14 ], [ %7, %12 ], [ %8, %16 ] - %20 = phi double [ %15, %14 ], [ %8, %12 ], [ %17, %16 ] - %21 = fcmp olt double %19, 9.900000e+01 - br i1 %21, label %6, label %22 +bb16: ; preds = %bb14, %bb12, %bb10 + %i17 = phi double [ %i6, %bb12 ], [ %i5, %bb10 ], [ %i6, %bb14 ] + %i18 = phi double [ %i13, %bb12 ], [ %i6, %bb10 ], [ %i15, %bb14 ] + %i19 = fcmp olt double %i17, 9.900000e+01 + br i1 %i19, label %bb4, label %bb20 -22: ; preds = %18 +bb20: ; preds = %bb16 ret void -} \ No newline at end of file +} diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll @@ -6,14 +6,14 @@ ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] -define {} @load0({}* %p) { +define {} @load0(ptr %p) { ; CHECK-LABEL: @load0.dfsan - ; CHECK-NEXT: %a = load {}, {}* %p, align 1 - ; CHECK-NEXT: store {} zeroinitializer, {}* bitcast ([100 x i64]* @__dfsan_retval_tls to {}*), align [[ALIGN:2]] - ; CHECK-NEXT: store i32 0, i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK-NEXT: %a = load {}, ptr %p, align 1 + ; CHECK-NEXT: store {} zeroinitializer, ptr @__dfsan_retval_tls, align [[ALIGN:2]] + ; CHECK-NEXT: store i32 0, ptr @__dfsan_retval_origin_tls, align 4 ; CHECK-NEXT: ret {} %a - %a = load {}, {}* %p + %a = load {}, ptr %p ret {} %a } @@ -21,121 +21,120 @@ ; CHECK-LABEL: @load_non_escaped_alloca.dfsan ; CHECK-NEXT: %[[#S_ALLOCA:]] = alloca i[[#SBITS]], align [[#SBYTES]] ; CHECK-NEXT: %_dfsa = alloca i32, align 4 - ; CHECK: %[[#SHADOW:]] = load i[[#SBITS]], i[[#SBITS]]* %[[#S_ALLOCA]], align [[#SBYTES]] - ; CHECK-NEXT: %[[#ORIGIN:]] = load i32, i32* %_dfsa, align 4 - ; CHECK-NEXT: %a = load i16, i16* %p, align 2 - ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: store i32 %[[#ORIGIN]], i32* @__dfsan_retval_origin_tls, align 4 - + ; CHECK: %[[#SHADOW:]] = load i[[#SBITS]], ptr %[[#S_ALLOCA]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#ORIGIN:]] = load i32, ptr %_dfsa, align 4 + ; CHECK-NEXT: %a = load i16, ptr %p, align 2 + ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]] + ; CHECK-NEXT: store i32 %[[#ORIGIN]], ptr @__dfsan_retval_origin_tls, align 4 + %p = alloca i16 - %a = load i16, i16* %p + %a = load i16, ptr %p ret i16 %a } -define i16* @load_escaped_alloca() { +define ptr @load_escaped_alloca() { ; CHECK-LABEL: @load_escaped_alloca.dfsan - ; CHECK: %[[#INTP:]] = ptrtoint i16* %p to i64 + ; CHECK: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#%.10d,MASK:]] - ; CHECK-NEXT: %[[#SHADOW_PTR0:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* + ; CHECK-NEXT: %[[#SHADOW_PTR0:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr ; CHECK-NEXT: %[[#ORIGIN_OFFSET:]] = add i64 %[[#SHADOW_OFFSET]], [[#%.10d,ORIGIN_BASE:]] ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = and i64 %[[#ORIGIN_OFFSET]], -4 - ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to i32* - ; CHECK-NEXT: {{%.*}} = load i32, i32* %[[#ORIGIN_PTR]], align 4 - ; CHECK-NEXT: %[[#SHADOW_PTR1:]] = getelementptr i[[#SBITS]], i[[#SBITS]]* %[[#SHADOW_PTR0]], i64 1 - ; CHECK-NEXT: %[[#SHADOW:]] = load i[[#SBITS]], i[[#SBITS]]* %[[#SHADOW_PTR0]], align [[#SBYTES]] - ; CHECK-NEXT: %[[#SHADOW+1]] = load i[[#SBITS]], i[[#SBITS]]* %[[#SHADOW_PTR1]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr + ; CHECK-NEXT: {{%.*}} = load i32, ptr %[[#ORIGIN_PTR]], align 4 + ; CHECK-NEXT: %[[#SHADOW_PTR1:]] = getelementptr i[[#SBITS]], ptr %[[#SHADOW_PTR0]], i64 1 + ; CHECK-NEXT: %[[#SHADOW:]] = load i[[#SBITS]], ptr %[[#SHADOW_PTR0]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#SHADOW+1]] = load i[[#SBITS]], ptr %[[#SHADOW_PTR1]], align [[#SBYTES]] ; CHECK-NEXT: {{%.*}} = or i[[#SBITS]] %[[#SHADOW]], %[[#SHADOW+1]] - ; CHECK-NEXT: %a = load i16, i16* %p, align 2 - ; CHECK-NEXT: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: store i32 0, i32* @__dfsan_retval_origin_tls, align 4 - + ; CHECK-NEXT: %a = load i16, ptr %p, align 2 + ; CHECK-NEXT: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align [[ALIGN]] + ; CHECK-NEXT: store i32 0, ptr @__dfsan_retval_origin_tls, align 4 + %p = alloca i16 - %a = load i16, i16* %p - ret i16* %p + %a = load i16, ptr %p + ret ptr %p } @X = constant i1 1 define i1 @load_global() { ; CHECK-LABEL: @load_global.dfsan - ; CHECK: %a = load i1, i1* @X, align 1 - ; CHECK-NEXT: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: store i32 0, i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: %a = load i1, ptr @X, align 1 + ; CHECK-NEXT: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align [[ALIGN]] + ; CHECK-NEXT: store i32 0, ptr @__dfsan_retval_origin_tls, align 4 - %a = load i1, i1* @X + %a = load i1, ptr @X ret i1 %a } -define i1 @load1(i1* %p) { +define i1 @load1(ptr %p) { ; CHECK-LABEL: @load1.dfsan - ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] - ; CHECK-NEXT: %[[#INTP:]] = ptrtoint i1* %p to i64 + ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr ; CHECK-NEXT: %[[#ORIGIN_OFFSET:]] = add i64 %[[#SHADOW_OFFSET]], [[#ORIGIN_BASE]] ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = and i64 %[[#ORIGIN_OFFSET]], -4 - ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to i32* - ; CHECK-NEXT: %[[#AO:]] = load i32, i32* %[[#ORIGIN_PTR]], align 4 - ; CHECK-NEXT: %[[#AS:]] = load i[[#SBITS]], i[[#SBITS]]* %[[#SHADOW_PTR]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr + ; CHECK-NEXT: %[[#AO:]] = load i32, ptr %[[#ORIGIN_PTR]], align 4 + ; CHECK-NEXT: %[[#AS:]] = load i[[#SBITS]], ptr %[[#SHADOW_PTR]], align [[#SBYTES]] ; COMBINE_LOAD_PTR-NEXT: %[[#AS:]] = or i[[#SBITS]] %[[#AS]], %[[#PS]] ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 ; COMBINE_LOAD_PTR-NEXT: %[[#AO:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#AO]] - ; CHECK-NEXT: %a = load i1, i1* %p, align 1 - ; CHECK-NEXT: store i[[#SBITS]] %[[#AS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: store i32 %[[#AO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK-NEXT: %a = load i1, ptr %p, align 1 + ; CHECK-NEXT: store i[[#SBITS]] %[[#AS]], ptr @__dfsan_retval_tls, align [[ALIGN]] + ; CHECK-NEXT: store i32 %[[#AO]], ptr @__dfsan_retval_origin_tls, align 4 - %a = load i1, i1* %p + %a = load i1, ptr %p ret i1 %a } -define i16 @load16(i1 %i, i16* %p) { +define i16 @load16(i1 %i, ptr %p) { ; CHECK-LABEL: @load16.dfsan - ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN]] + ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]] - ; CHECK-NEXT: %[[#INTP:]] = ptrtoint i16* %p to i64 + ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]] - ; CHECK-NEXT: %[[#SHADOW_PTR0:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* + ; CHECK-NEXT: %[[#SHADOW_PTR0:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr ; CHECK-NEXT: %[[#ORIGIN_OFFSET:]] = add i64 %[[#SHADOW_OFFSET]], [[#ORIGIN_BASE]] ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = and i64 %[[#ORIGIN_OFFSET]], -4 - ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to i32* - ; CHECK-NEXT: %[[#AO:]] = load i32, i32* %[[#ORIGIN_PTR]], align 4 - ; CHECK-NEXT: %[[#SHADOW_PTR1:]] = getelementptr i[[#SBITS]], i[[#SBITS]]* %[[#SHADOW_PTR0]], i64 1 - ; CHECK-NEXT: %[[#SHADOW:]] = load i[[#SBITS]], i[[#SBITS]]* %[[#SHADOW_PTR0]], align [[#SBYTES]] - ; CHECK-NEXT: %[[#SHADOW+1]] = load i[[#SBITS]], i[[#SBITS]]* %[[#SHADOW_PTR1]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr + ; CHECK-NEXT: %[[#AO:]] = load i32, ptr %[[#ORIGIN_PTR]], align 4 + ; CHECK-NEXT: %[[#SHADOW_PTR1:]] = getelementptr i[[#SBITS]], ptr %[[#SHADOW_PTR0]], i64 1 + ; CHECK-NEXT: %[[#SHADOW:]] = load i[[#SBITS]], ptr %[[#SHADOW_PTR0]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#SHADOW+1]] = load i[[#SBITS]], ptr %[[#SHADOW_PTR1]], align [[#SBYTES]] ; CHECK-NEXT: %[[#AS:]] = or i[[#SBITS]] %[[#SHADOW]], %[[#SHADOW+1]] ; COMBINE_LOAD_PTR-NEXT: %[[#AS:]] = or i[[#SBITS]] %[[#AS]], %[[#PS]] ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 ; COMBINE_LOAD_PTR-NEXT: %[[#AO:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#AO]] - ; CHECK-NEXT: %a = load i16, i16* %p, align 2 - ; CHECK-NEXT: store i[[#SBITS]] %[[#AS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: store i32 %[[#AO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK-NEXT: %a = load i16, ptr %p, align 2 + ; CHECK-NEXT: store i[[#SBITS]] %[[#AS]], ptr @__dfsan_retval_tls, align [[ALIGN]] + ; CHECK-NEXT: store i32 %[[#AO]], ptr @__dfsan_retval_origin_tls, align 4 - %a = load i16, i16* %p + %a = load i16, ptr %p ret i16 %a } -define i32 @load32(i32* %p) { +define i32 @load32(ptr %p) { ; CHECK-LABEL: @load32.dfsan - ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] - ; CHECK-NEXT: %[[#INTP:]] = ptrtoint i32* %p to i64 + ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = add i64 %[[#SHADOW_OFFSET]], [[#ORIGIN_BASE]] - ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to i32* - ; CHECK-NEXT: %[[#AO:]] = load i32, i32* %[[#ORIGIN_PTR]], align 4 - ; CHECK-NEXT: %[[#WIDE_SHADOW_PTR:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i[[#WSBITS:mul(SBITS,4)]]* - ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = load i[[#WSBITS]], i[[#WSBITS]]* %[[#WIDE_SHADOW_PTR]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr + ; CHECK-NEXT: %[[#AO:]] = load i32, ptr %[[#ORIGIN_PTR]], align 4 + ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = load i[[#WSBITS:mul(SBITS,4)]], ptr %[[#SHADOW_PTR]], align [[#SBYTES]] ; CHECK-NEXT: %[[#WIDE_SHADOW+1]] = lshr i[[#WSBITS]] %[[#WIDE_SHADOW]], [[#mul(SBITS,2)]] ; CHECK-NEXT: %[[#WIDE_SHADOW+2]] = or i[[#WSBITS]] %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW+1]] ; CHECK-NEXT: %[[#WIDE_SHADOW+3]] = lshr i[[#WSBITS]] %[[#WIDE_SHADOW+2]], [[#SBITS]] @@ -146,31 +145,30 @@ ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 ; COMBINE_LOAD_PTR-NEXT: %[[#AO:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#AO]] - ; CHECK-NEXT: %a = load i32, i32* %p, align 4 - ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: store i32 %[[#AO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK-NEXT: %a = load i32, ptr %p, align 4 + ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]] + ; CHECK-NEXT: store i32 %[[#AO]], ptr @__dfsan_retval_origin_tls, align 4 - %a = load i32, i32* %p + %a = load i32, ptr %p ret i32 %a } -define i64 @load64(i64* %p) { +define i64 @load64(ptr %p) { ; CHECK-LABEL: @load64.dfsan - ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] - ; CHECK-NEXT: %[[#INTP:]] = ptrtoint i64* %p to i64 + ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = add i64 %[[#SHADOW_OFFSET]], [[#ORIGIN_BASE]] - ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to i32* - ; CHECK-NEXT: %[[#ORIGIN:]] = load i32, i32* %[[#ORIGIN_PTR]], align 8 - ; CHECK-NEXT: %[[#WIDE_SHADOW_PTR:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i64* - ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = load i64, i64* %[[#WIDE_SHADOW_PTR]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr + ; CHECK-NEXT: %[[#ORIGIN:]] = load i32, ptr %[[#ORIGIN_PTR]], align 8 + ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = load i64, ptr %[[#SHADOW_PTR]], align [[#SBYTES]] ; CHECK-NEXT: %[[#WIDE_SHADOW_LO:]] = shl i64 %[[#WIDE_SHADOW]], 32 - ; CHECK-NEXT: %[[#ORIGIN2_PTR:]] = getelementptr i32, i32* %[[#ORIGIN_PTR]], i64 1 - ; CHECK-NEXT: %[[#ORIGIN2:]] = load i32, i32* %[[#ORIGIN2_PTR]], align 8 + ; CHECK-NEXT: %[[#ORIGIN2_PTR:]] = getelementptr i32, ptr %[[#ORIGIN_PTR]], i64 1 + ; CHECK-NEXT: %[[#ORIGIN2:]] = load i32, ptr %[[#ORIGIN2_PTR]], align 8 ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i64 %[[#WIDE_SHADOW]], 32 ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]] ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i64 %[[#WIDE_SHADOW]], 16 @@ -187,22 +185,21 @@ ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 ; COMBINE_LOAD_PTR-NEXT: %[[#ORIGIN:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#ORIGIN]] - ; CHECK-NEXT: %a = load i64, i64* %p, align 8 - ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: store i32 %[[#ORIGIN]], i32* @__dfsan_retval_origin_tls, align 4 - - %a = load i64, i64* %p + ; CHECK-NEXT: %a = load i64, ptr %p, align 8 + ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]] + ; CHECK-NEXT: store i32 %[[#ORIGIN]], ptr @__dfsan_retval_origin_tls, align 4 + + %a = load i64, ptr %p ret i64 %a } -define i64 @load64_align2(i64* %p) { +define i64 @load64_align2(ptr %p) { ; CHECK-LABEL: @load64_align2.dfsan - ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] - ; CHECK-NEXT: %[[#INTP:]] = bitcast i64* %p to i8* - ; CHECK-NEXT: %[[#LABEL_ORIGIN:]] = call zeroext i64 @__dfsan_load_label_and_origin(i8* %[[#INTP]], i64 8) + ; CHECK-NEXT: %[[#LABEL_ORIGIN:]] = call zeroext i64 @__dfsan_load_label_and_origin(ptr %p, i64 8) ; CHECK-NEXT: %[[#LABEL_ORIGIN+1]] = lshr i64 %[[#LABEL_ORIGIN]], 32 ; CHECK-NEXT: %[[#LABEL:]] = trunc i64 %[[#LABEL_ORIGIN+1]] to i[[#SBITS]] ; CHECK-NEXT: %[[#ORIGIN:]] = trunc i64 %[[#LABEL_ORIGIN]] to i32 @@ -211,39 +208,38 @@ ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 ; COMBINE_LOAD_PTR-NEXT: %[[#ORIGIN:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#ORIGIN]] - ; CHECK-NEXT: %a = load i64, i64* %p, align 2 - ; CHECK-NEXT: store i[[#SBITS]] %[[#LABEL]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: store i32 %[[#ORIGIN]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK-NEXT: %a = load i64, ptr %p, align 2 + ; CHECK-NEXT: store i[[#SBITS]] %[[#LABEL]], ptr @__dfsan_retval_tls, align [[ALIGN]] + ; CHECK-NEXT: store i32 %[[#ORIGIN]], ptr @__dfsan_retval_origin_tls, align 4 - %a = load i64, i64* %p, align 2 + %a = load i64, ptr %p, align 2 ret i64 %a } -define i128 @load128(i128* %p) { +define i128 @load128(ptr %p) { ; CHECK-LABEL: @load128.dfsan - ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] - ; CHECK-NEXT: %[[#INTP:]] = ptrtoint i128* %p to i64 + ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]] - ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* + ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = add i64 %[[#SHADOW_OFFSET]], [[#ORIGIN_BASE]] - ; CHECK-NEXT: %[[#ORIGIN1_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to i32* - ; CHECK-NEXT: %[[#ORIGIN1:]] = load i32, i32* %[[#ORIGIN1_PTR]], align 8 - ; CHECK-NEXT: %[[#WIDE_SHADOW1_PTR:]] = bitcast i[[#SBITS]]* %[[#SHADOW_PTR]] to i64* - ; CHECK-NEXT: %[[#WIDE_SHADOW1:]] = load i64, i64* %[[#WIDE_SHADOW1_PTR]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#ORIGIN1_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr + ; CHECK-NEXT: %[[#ORIGIN1:]] = load i32, ptr %[[#ORIGIN1_PTR]], align 8 + ; CHECK-NEXT: %[[#WIDE_SHADOW1:]] = load i64, ptr %[[#SHADOW_PTR]], align [[#SBYTES]] ; CHECK-NEXT: %[[#WIDE_SHADOW1_LO:]] = shl i64 %[[#WIDE_SHADOW1]], 32 - ; CHECK-NEXT: %[[#ORIGIN2_PTR:]] = getelementptr i32, i32* %[[#ORIGIN1_PTR]], i64 1 - ; CHECK-NEXT: %[[#ORIGIN2:]] = load i32, i32* %[[#ORIGIN2_PTR]], align 8 - ; CHECK-NEXT: %[[#WIDE_SHADOW2_PTR:]] = getelementptr i64, i64* %[[#WIDE_SHADOW1_PTR]], i64 1 - ; CHECK-NEXT: %[[#WIDE_SHADOW2:]] = load i64, i64* %[[#WIDE_SHADOW2_PTR]], align [[#SBYTES]] + ; CHECK-NEXT: %[[#ORIGIN2_PTR:]] = getelementptr i32, ptr %[[#ORIGIN1_PTR]], i64 1 + ; CHECK-NEXT: %[[#ORIGIN2:]] = load i32, ptr %[[#ORIGIN2_PTR]], align 8 + ; CHECK-NEXT: %[[#WIDE_SHADOW2_PTR:]] = getelementptr i64, ptr %[[#SHADOW_PTR]], i64 1 + ; CHECK-NEXT: %[[#WIDE_SHADOW2:]] = load i64, ptr %[[#WIDE_SHADOW2_PTR]], align [[#SBYTES]] ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW1]], %[[#WIDE_SHADOW2]] - ; CHECK-NEXT: %[[#ORIGIN3_PTR:]] = getelementptr i32, i32* %[[#ORIGIN2_PTR]], i64 1 - ; CHECK-NEXT: %[[#ORIGIN3:]] = load i32, i32* %[[#ORIGIN3_PTR]], align 8 + ; CHECK-NEXT: %[[#ORIGIN3_PTR:]] = getelementptr i32, ptr %[[#ORIGIN2_PTR]], i64 1 + ; CHECK-NEXT: %[[#ORIGIN3:]] = load i32, ptr %[[#ORIGIN3_PTR]], align 8 ; CHECK-NEXT: %[[#WIDE_SHADOW2_LO:]] = shl i64 %[[#WIDE_SHADOW2]], 32 - ; CHECK-NEXT: %[[#ORIGIN4_PTR:]] = getelementptr i32, i32* %[[#ORIGIN3_PTR]], i64 1 - ; CHECK-NEXT: %[[#ORIGIN4:]] = load i32, i32* %[[#ORIGIN4_PTR]], align 8 + ; CHECK-NEXT: %[[#ORIGIN4_PTR:]] = getelementptr i32, ptr %[[#ORIGIN3_PTR]], i64 1 + ; CHECK-NEXT: %[[#ORIGIN4:]] = load i32, ptr %[[#ORIGIN4_PTR]], align 8 ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i64 %[[#WIDE_SHADOW]], 32 ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]] ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i64 %[[#WIDE_SHADOW]], 16 @@ -262,22 +258,21 @@ ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 ; COMBINE_LOAD_PTR-NEXT: %[[#ORIGIN:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#ORIGIN]] - ; CHECK-NEXT: %a = load i128, i128* %p, align 8 - ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: store i32 %[[#ORIGIN]], i32* @__dfsan_retval_origin_tls, align 4 - - %a = load i128, i128* %p + ; CHECK-NEXT: %a = load i128, ptr %p, align 8 + ; CHECK-NEXT: store i[[#SBITS]] %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]] + ; CHECK-NEXT: store i32 %[[#ORIGIN]], ptr @__dfsan_retval_origin_tls, align 4 + + %a = load i128, ptr %p ret i128 %a } -define i17 @load17(i17* %p) { +define i17 @load17(ptr %p) { ; CHECK-LABEL: @load17.dfsan - ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] - ; CHECK-NEXT: %[[#INTP:]] = bitcast i17* %p to i8* - ; CHECK-NEXT: %[[#LABEL_ORIGIN:]] = call zeroext i64 @__dfsan_load_label_and_origin(i8* %[[#INTP]], i64 3) + ; CHECK-NEXT: %[[#LABEL_ORIGIN:]] = call zeroext i64 @__dfsan_load_label_and_origin(ptr %p, i64 3) ; CHECK-NEXT: %[[#LABEL_ORIGIN_H32:]] = lshr i64 %[[#LABEL_ORIGIN]], 32 ; CHECK-NEXT: %[[#LABEL:]] = trunc i64 %[[#LABEL_ORIGIN_H32]] to i[[#SBITS]] ; CHECK-NEXT: %[[#ORIGIN:]] = trunc i64 %[[#LABEL_ORIGIN]] to i32 @@ -286,10 +281,10 @@ ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 ; COMBINE_LOAD_PTR-NEXT: %[[#ORIGIN:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#ORIGIN]] - ; CHECK-NEXT: %a = load i17, i17* %p, align 4 - ; CHECK-NEXT: store i[[#SBITS]] %[[#LABEL]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: store i32 %[[#ORIGIN]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK-NEXT: %a = load i17, ptr %p, align 4 + ; CHECK-NEXT: store i[[#SBITS]] %[[#LABEL]], ptr @__dfsan_retval_tls, align [[ALIGN]] + ; CHECK-NEXT: store i32 %[[#ORIGIN]], ptr @__dfsan_retval_origin_tls, align 4 - %a = load i17, i17* %p, align 4 + %a = load i17, ptr %p, align 4 ret i17 %a } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_mem_intrinsic.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_mem_intrinsic.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_mem_intrinsic.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_mem_intrinsic.ll @@ -5,37 +5,37 @@ ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] -declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i1) -declare void @llvm.memmove.p0i8.p0i8.i32(i8*, i8*, i32, i1) -declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) +declare void @llvm.memcpy.p0.p0.i32(ptr, ptr, i32, i1) +declare void @llvm.memmove.p0.p0.i32(ptr, ptr, i32, i1) +declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) -define void @memcpy(i8* %d, i8* %s, i32 %l) { +define void @memcpy(ptr %d, ptr %s, i32 %l) { ; CHECK: @memcpy.dfsan ; CHECK: [[L64:%.*]] = zext i32 %l to i64 - ; CHECK: call void @__dfsan_mem_origin_transfer(i8* %d, i8* %s, i64 [[L64]]) - ; CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align [[#SBYTES]] {{.*}}, i8* align [[#SBYTES]] {{.*}}, i32 {{.*}}, i1 false) - ; CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %d, i8* %s, i32 %l, i1 false) + ; CHECK: call void @__dfsan_mem_origin_transfer(ptr %d, ptr %s, i64 [[L64]]) + ; CHECK: call void @llvm.memcpy.p0.p0.i32(ptr align [[#SBYTES]] {{.*}}, ptr align [[#SBYTES]] {{.*}}, i32 {{.*}}, i1 false) + ; CHECK: call void @llvm.memcpy.p0.p0.i32(ptr %d, ptr %s, i32 %l, i1 false) - call void @llvm.memcpy.p0i8.p0i8.i32(i8* %d, i8* %s, i32 %l, i1 0) + call void @llvm.memcpy.p0.p0.i32(ptr %d, ptr %s, i32 %l, i1 0) ret void } -define void @memmove(i8* %d, i8* %s, i32 %l) { +define void @memmove(ptr %d, ptr %s, i32 %l) { ; CHECK: @memmove.dfsan ; CHECK: [[L64:%.*]] = zext i32 %l to i64 - ; CHECK: call void @__dfsan_mem_origin_transfer(i8* %d, i8* %s, i64 [[L64]]) - ; CHECK: call void @llvm.memmove.p0i8.p0i8.i32(i8* align [[#SBYTES]] {{.*}}, i8* align [[#SBYTES]] {{.*}}, i32 {{.*}}, i1 false) - ; CHECK: call void @llvm.memmove.p0i8.p0i8.i32(i8* %d, i8* %s, i32 %l, i1 false) + ; CHECK: call void @__dfsan_mem_origin_transfer(ptr %d, ptr %s, i64 [[L64]]) + ; CHECK: call void @llvm.memmove.p0.p0.i32(ptr align [[#SBYTES]] {{.*}}, ptr align [[#SBYTES]] {{.*}}, i32 {{.*}}, i1 false) + ; CHECK: call void @llvm.memmove.p0.p0.i32(ptr %d, ptr %s, i32 %l, i1 false) - call void @llvm.memmove.p0i8.p0i8.i32(i8* %d, i8* %s, i32 %l, i1 0) + call void @llvm.memmove.p0.p0.i32(ptr %d, ptr %s, i32 %l, i1 0) ret void } -define void @memset(i8* %p, i8 %v) { +define void @memset(ptr %p, i8 %v) { ; CHECK: @memset.dfsan - ; CHECK: [[O:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[S:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN:2]] - ; CHECK: call void @__dfsan_set_label(i[[#SBITS]] [[S]], i32 [[O]], i8* %p, i64 1) - call void @llvm.memset.p0i8.i64(i8* %p, i8 %v, i64 1, i1 1) + ; CHECK: [[O:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[S:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN:2]] + ; CHECK: call void @__dfsan_set_label(i[[#SBITS]] [[S]], i32 [[O]], ptr %p, i64 1) + call void @llvm.memset.p0.i64(ptr %p, i8 %v, i64 1, i1 1) ret void } \ No newline at end of file diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_other_ops.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_other_ops.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_other_ops.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_other_ops.ll @@ -9,8 +9,8 @@ define float @unop(float %f) { ; CHECK: @unop.dfsan - ; CHECK: [[FO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: store i32 [[FO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: [[FO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: store i32 [[FO]], ptr @__dfsan_retval_origin_tls, align 4 %r = fneg float %f ret float %r @@ -18,68 +18,68 @@ define i1 @binop(i1 %a, i1 %b) { ; CHECK: @binop.dfsan - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 ; CHECK: [[NE:%.*]] = icmp ne i[[#SBITS]] [[BS]], 0 ; CHECK: [[MO:%.*]] = select i1 [[NE]], i32 [[BO]], i32 [[AO]] - ; CHECK: store i32 [[MO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i32 [[MO]], ptr @__dfsan_retval_origin_tls, align 4 %r = add i1 %a, %b ret i1 %r } -define i8 @castop(i32* %p) { +define i8 @castop(ptr %p) { ; CHECK: @castop.dfsan - ; CHECK: [[PO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: store i32 [[PO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: [[PO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: store i32 [[PO]], ptr @__dfsan_retval_origin_tls, align 4 - %r = ptrtoint i32* %p to i8 + %r = ptrtoint ptr %p to i8 ret i8 %r } define i1 @cmpop(i1 %a, i1 %b) { ; CHECK: @cmpop.dfsan - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 ; CHECK: [[NE:%.*]] = icmp ne i[[#SBITS]] [[BS]], 0 ; CHECK: [[MO:%.*]] = select i1 [[NE]], i32 [[BO]], i32 [[AO]] - ; CHECK: store i32 [[MO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i32 [[MO]], ptr @__dfsan_retval_origin_tls, align 4 %r = icmp eq i1 %a, %b ret i1 %r } -define i32* @gepop([10 x [20 x i32]]* %p, i32 %a, i32 %b, i32 %c) { +define ptr @gepop(ptr %p, i32 %a, i32 %b, i32 %c) { ; CHECK: @gepop.dfsan - ; CHECK: [[CO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 3), align 4 - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 2), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[PO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: [[CS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 6) to i[[#SBITS]]*), align 2 - ; CHECK: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 4) to i[[#SBITS]]*), align 2 - ; CHECK: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 + ; CHECK: [[CO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 3), align 4 + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[PO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: [[CS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 6) to ptr), align 2 + ; CHECK: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 4) to ptr), align 2 + ; CHECK: [[AS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 ; CHECK: [[AS_NE:%.*]] = icmp ne i[[#SBITS]] [[AS]], 0 ; CHECK: [[APO:%.*]] = select i1 [[AS_NE]], i32 [[AO]], i32 [[PO]] ; CHECK: [[BS_NE:%.*]] = icmp ne i[[#SBITS]] [[BS]], 0 ; CHECK: [[ABPO:%.*]] = select i1 [[BS_NE]], i32 [[BO]], i32 [[APO]] ; CHECK: [[CS_NE:%.*]] = icmp ne i[[#SBITS]] [[CS]], 0 ; CHECK: [[ABCPO:%.*]] = select i1 [[CS_NE]], i32 [[CO]], i32 [[ABPO]] - ; CHECK: store i32 [[ABCPO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i32 [[ABCPO]], ptr @__dfsan_retval_origin_tls, align 4 - %e = getelementptr [10 x [20 x i32]], [10 x [20 x i32]]* %p, i32 %a, i32 %b, i32 %c - ret i32* %e + %e = getelementptr [10 x [20 x i32]], ptr %p, i32 %a, i32 %b, i32 %c + ret ptr %e } define i32 @eeop(<4 x i32> %a, i32 %b) { ; CHECK: @eeop.dfsan - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 ; CHECK: [[NE:%.*]] = icmp ne i[[#SBITS]] [[BS]], 0 ; CHECK: [[MO:%.*]] = select i1 [[NE]], i32 [[BO]], i32 [[AO]] - ; CHECK: store i32 [[MO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i32 [[MO]], ptr @__dfsan_retval_origin_tls, align 4 %e = extractelement <4 x i32> %a, i32 %b ret i32 %e @@ -87,16 +87,16 @@ define <4 x i32> @ieop(<4 x i32> %p, i32 %a, i32 %b) { ; CHECK: @ieop.dfsan - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 2), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[PO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 4) to i[[#SBITS]]*), align 2 - ; CHECK: [[AS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[PO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 4) to ptr), align 2 + ; CHECK: [[AS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 ; CHECK: [[AS_NE:%.*]] = icmp ne i[[#SBITS]] [[AS]], 0 ; CHECK: [[APO:%.*]] = select i1 [[AS_NE]], i32 [[AO]], i32 [[PO]] ; CHECK: [[BS_NE:%.*]] = icmp ne i[[#SBITS]] [[BS]], 0 ; CHECK: [[ABPO:%.*]] = select i1 [[BS_NE]], i32 [[BO]], i32 [[APO]] - ; CHECK: store i32 [[ABPO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i32 [[ABPO]], ptr @__dfsan_retval_origin_tls, align 4 %e = insertelement <4 x i32> %p, i32 %a, i32 %b ret <4 x i32> %e @@ -104,12 +104,12 @@ define <4 x i32> @svop(<4 x i32> %a, <4 x i32> %b) { ; CHECK: @svop.dfsan - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: [[BS:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align 2 + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: [[BS:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 ; CHECK: [[NE:%.*]] = icmp ne i[[#SBITS]] [[BS]], 0 ; CHECK: [[MO:%.*]] = select i1 [[NE]], i32 [[BO]], i32 [[AO]] - ; CHECK: store i32 [[MO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i32 [[MO]], ptr @__dfsan_retval_origin_tls, align 4 %e = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> ret <4 x i32> %e @@ -117,8 +117,8 @@ define i32 @evop({i32, float} %a) { ; CHECK: @evop.dfsan - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK: store i32 [[AO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK: store i32 [[AO]], ptr @__dfsan_retval_origin_tls, align 4 %e = extractvalue {i32, float} %a, 0 ret i32 %e @@ -126,18 +126,18 @@ define {i32, {float, float}} @ivop({i32, {float, float}} %a, {float, float} %b) { ; CHECK: @ivop.dfsan - ; CHECK: [[BO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 + ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 ; COMM: TODO simplify the expression [[#mul(2,SBYTES) + max(SBYTES,2)]] to ; COMM: [[#mul(3,SBYTES)]], if shadow-tls-alignment is updated to match shadow - ; CHECK: [[BS:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES) + max(SBYTES,2)]]) to { i[[#SBITS]], i[[#SBITS]] }*), align 2 + ; CHECK: [[BS:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2,SBYTES) + max(SBYTES,2)]]) to ptr), align 2 ; CHECK: [[BS0:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[BS]], 0 ; CHECK: [[BS1:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[BS]], 1 ; CHECK: [[BS01:%.*]] = or i[[#SBITS]] [[BS0]], [[BS1]] ; CHECK: [[NE:%.*]] = icmp ne i[[#SBITS]] [[BS01]], 0 ; CHECK: [[MO:%.*]] = select i1 [[NE]], i32 [[BO]], i32 [[AO]] - ; CHECK: store i32 [[MO]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK: store i32 [[MO]], ptr @__dfsan_retval_origin_tls, align 4 %e = insertvalue {i32, {float, float}} %a, {float, float} %b, 1 ret {i32, {float, float}} %e } \ No newline at end of file diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll @@ -11,75 +11,74 @@ ; CHECK-NEXT: [[A:%.*]] = alloca i[[#SBITS]], align [[#SBYTES]] ; CHECK-NEXT: %_dfsa = alloca i32, align 4 ; CHECK-NEXT: %p = alloca i16, align 2 - ; CHECK-NEXT: store i[[#SBITS]] 0, i[[#SBITS]]* [[A]], align [[#SBYTES]] - ; CHECK-NEXT: store i16 1, i16* %p, align 2 + ; CHECK-NEXT: store i[[#SBITS]] 0, ptr [[A]], align [[#SBYTES]] + ; CHECK-NEXT: store i16 1, ptr %p, align 2 ; CHECK-NEXT: ret void - + %p = alloca i16 - store i16 1, i16* %p + store i16 1, ptr %p ret void } define void @store_nonzero_to_non_escaped_alloca(i16 %a) { ; CHECK-LABEL: @store_nonzero_to_non_escaped_alloca.dfsan - ; CHECK: %[[#AO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 + ; CHECK: %[[#AO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 ; CHECK: %_dfsa = alloca i32, align 4 - ; CHECK: store i32 %[[#AO]], i32* %_dfsa, align 4 - + ; CHECK: store i32 %[[#AO]], ptr %_dfsa, align 4 + %p = alloca i16 - store i16 %a, i16* %p + store i16 %a, ptr %p ret void } -declare void @foo(i16* %p) +declare void @foo(ptr %p) define void @store_zero_to_escaped_alloca() { ; CHECK-LABEL: @store_zero_to_escaped_alloca.dfsan - ; CHECK: %[[#SA:]] = bitcast i[[#SBITS]]* {{.*}} to i[[#NUM_BITS:mul(SBITS,2)]]* - ; CHECK-NEXT: store i[[#NUM_BITS]] 0, i[[#NUM_BITS]]* %[[#SA]], align [[#SBYTES]] - ; CHECK-NEXT: store i16 1, i16* %p, align 2 - ; CHECK-NEXT: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]] - ; CHECK-NEXT: call void @foo.dfsan(i16* %p) + ; CHECK: store i[[#NUM_BITS:mul(SBITS,2)]] 0, ptr {{.*}}, align [[#SBYTES]] + ; CHECK-NEXT: store i16 1, ptr %p, align 2 + ; CHECK-NEXT: store i[[#SBITS]] 0, ptr @__dfsan_arg_tls, align [[ALIGN:2]] + ; CHECK-NEXT: call void @foo.dfsan(ptr %p) %p = alloca i16 - store i16 1, i16* %p - call void @foo(i16* %p) + store i16 1, ptr %p + call void @foo(ptr %p) ret void } define void @store_nonzero_to_escaped_alloca(i16 %a) { ; CHECK-LABEL: @store_nonzero_to_escaped_alloca.dfsan - ; CHECK-NEXT: %[[#AO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK-NEXT: %[[#AS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK: %[[#INTP:]] = ptrtoint i16* %p to i64 + ; CHECK-NEXT: %[[#AO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK-NEXT: %[[#AS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] + ; CHECK: %[[#INTP:]] = ptrtoint ptr %p to i64 ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#%.10d,MASK:]] - ; CHECK-NEXT: %[[#SHADOW_PTR0:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to i[[#SBITS]]* + ; CHECK-NEXT: %[[#SHADOW_PTR0:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr ; CHECK-NEXT: %[[#ORIGIN_OFFSET:]] = add i64 %[[#SHADOW_OFFSET]], [[#%.10d,ORIGIN_BASE:]] ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = and i64 %[[#ORIGIN_OFFSET]], -4 - ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to i32* + ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr ; CHECK: %_dfscmp = icmp ne i[[#SBITS]] %[[#AS]], 0 ; CHECK-NEXT: br i1 %_dfscmp, label %[[L1:.*]], label %[[L2:.*]], ; CHECK: [[L1]]: ; CHECK-NEXT: %[[#NO:]] = call i32 @__dfsan_chain_origin(i32 %[[#AO]]) - ; CHECK-NEXT: store i32 %[[#NO]], i32* %[[#ORIGIN_PTR]], align 4 + ; CHECK-NEXT: store i32 %[[#NO]], ptr %[[#ORIGIN_PTR]], align 4 ; CHECK-NEXT: br label %[[L2]] ; CHECK: [[L2]]: - ; CHECK-NEXT: store i16 %a, i16* %p, align 2 - + ; CHECK-NEXT: store i16 %a, ptr %p, align 2 + %p = alloca i16 - store i16 %a, i16* %p - call void @foo(i16* %p) + store i16 %a, ptr %p + call void @foo(ptr %p) ret void } -define void @store64_align8(i64* %p, i64 %a) { +define void @store64_align8(ptr %p, i64 %a) { ; CHECK-LABEL: @store64_align8.dfsan - ; COMBINE_STORE_PTR-NEXT: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; COMBINE_STORE_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; COMBINE_STORE_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; COMBINE_STORE_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] - ; CHECK-NEXT: %[[#AO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK-NEXT: %[[#AS:]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %[[#AO:]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK-NEXT: %[[#AS:]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]] ; COMBINE_STORE_PTR-NEXT: %[[#AS:]] = or i[[#SBITS]] %[[#AS]], %[[#PS]] ; COMBINE_STORE_PTR-NEXT: %[[#NE:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 @@ -92,24 +91,23 @@ ; CHECK-NEXT: %[[#NO_ZEXT:]] = zext i32 %[[#NO]] to i64 ; CHECK-NEXT: %[[#NO_SHL:]] = shl i64 %[[#NO_ZEXT]], 32 ; CHECK-NEXT: %[[#NO2:]] = or i64 %[[#NO_ZEXT]], %[[#NO_SHL]] - ; CHECK-NEXT: %[[#O_PTR:]] = bitcast i32* {{.*}} to i64* - ; CHECK-NEXT: store i64 %[[#NO2]], i64* %[[#O_PTR]], align 8 + ; CHECK-NEXT: store i64 %[[#NO2]], ptr {{.*}}, align 8 ; CHECK-NEXT: br label %[[L2]] ; CHECK: [[L2]]: - ; CHECK-NEXT: store i64 %a, i64* %p, align 8 - - store i64 %a, i64* %p + ; CHECK-NEXT: store i64 %a, ptr %p, align 8 + + store i64 %a, ptr %p ret void } -define void @store64_align2(i64* %p, i64 %a) { +define void @store64_align2(ptr %p, i64 %a) { ; CHECK-LABEL: @store64_align2.dfsan - ; COMBINE_STORE_PTR-NEXT: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; COMBINE_STORE_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; COMBINE_STORE_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; COMBINE_STORE_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] - ; CHECK-NEXT: %[[#AO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK-NEXT: %[[#AS:]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %[[#AO:]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK-NEXT: %[[#AS:]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]] ; COMBINE_STORE_PTR-NEXT: %[[#AS:]] = or i[[#SBITS]] %[[#AS]], %[[#PS]] ; COMBINE_STORE_PTR-NEXT: %[[#NE:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 @@ -119,24 +117,24 @@ ; CHECK-NEXT: br i1 %_dfscmp, label %[[L1:.*]], label %[[L2:.*]], ; CHECK: [[L1]]: ; CHECK-NEXT: %[[#NO:]] = call i32 @__dfsan_chain_origin(i32 %[[#AO]]) - ; CHECK-NEXT: store i32 %[[#NO]], i32* %[[#O_PTR0:]], align 4 - ; CHECK-NEXT: %[[#O_PTR1:]] = getelementptr i32, i32* %[[#O_PTR0]], i32 1 - ; CHECK-NEXT: store i32 %[[#NO]], i32* %[[#O_PTR1]], align 4 + ; CHECK-NEXT: store i32 %[[#NO]], ptr %[[#O_PTR0:]], align 4 + ; CHECK-NEXT: %[[#O_PTR1:]] = getelementptr i32, ptr %[[#O_PTR0]], i32 1 + ; CHECK-NEXT: store i32 %[[#NO]], ptr %[[#O_PTR1]], align 4 ; CHECK: [[L2]]: - ; CHECK-NEXT: store i64 %a, i64* %p, align 2 - - store i64 %a, i64* %p, align 2 + ; CHECK-NEXT: store i64 %a, ptr %p, align 2 + + store i64 %a, ptr %p, align 2 ret void } -define void @store96_align8(i96* %p, i96 %a) { +define void @store96_align8(ptr %p, i96 %a) { ; CHECK-LABEL: @store96_align8.dfsan - ; COMBINE_STORE_PTR-NEXT: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; COMBINE_STORE_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; COMBINE_STORE_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; COMBINE_STORE_PTR-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] - ; CHECK-NEXT: %[[#AO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK-NEXT: %[[#AS:]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %[[#AO:]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK-NEXT: %[[#AS:]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]] ; COMBINE_STORE_PTR-NEXT: %[[#AS:]] = or i[[#SBITS]] %[[#AS]], %[[#PS]] ; COMBINE_STORE_PTR-NEXT: %[[#NE:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 @@ -149,13 +147,12 @@ ; CHECK-NEXT: %[[#NO_ZEXT:]] = zext i32 %[[#NO]] to i64 ; CHECK-NEXT: %[[#NO_SHL:]] = shl i64 %[[#NO_ZEXT]], 32 ; CHECK-NEXT: %[[#NO2:]] = or i64 %[[#NO_ZEXT]], %[[#NO_SHL]] - ; CHECK-NEXT: %[[#O_PTR64:]] = bitcast i32* %[[#O_PTR0:]] to i64* - ; CHECK-NEXT: store i64 %[[#NO2]], i64* %[[#O_PTR64]], align 8 - ; CHECK-NEXT: %[[#O_PTR1:]] = getelementptr i32, i32* %[[#O_PTR0]], i32 2 - ; CHECK-NEXT: store i32 %[[#NO]], i32* %[[#O_PTR1]], align 8 + ; CHECK-NEXT: store i64 %[[#NO2]], ptr %[[#O_PTR0:]], align 8 + ; CHECK-NEXT: %[[#O_PTR1:]] = getelementptr i32, ptr %[[#O_PTR0]], i32 2 + ; CHECK-NEXT: store i32 %[[#NO]], ptr %[[#O_PTR1]], align 8 ; CHECK: [[L2]]: - ; CHECK-NEXT: store i96 %a, i96* %p, align 8 - - store i96 %a, i96* %p, align 8 + ; CHECK-NEXT: store i96 %a, ptr %p, align 8 + + store i96 %a, ptr %p, align 8 ret void } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_store_threshold.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_store_threshold.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_store_threshold.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_store_threshold.ll @@ -5,17 +5,16 @@ ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] -define void @store_threshold([2 x i64]* %p, [2 x i64] %a) { +define void @store_threshold(ptr %p, [2 x i64] %a) { ; CHECK: @store_threshold.dfsan - ; CHECK: [[AO:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 - ; CHECK: [[AS:%.*]] = load [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to [2 x i[[#SBITS]]]*), align 2 + ; CHECK: [[AO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4 + ; CHECK: [[AS:%.*]] = load [2 x i[[#SBITS]]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 ; CHECK: [[AS0:%.*]] = extractvalue [2 x i[[#SBITS]]] [[AS]], 0 ; CHECK: [[AS1:%.*]] = extractvalue [2 x i[[#SBITS]]] [[AS]], 1 ; CHECK: [[AS01:%.*]] = or i[[#SBITS]] [[AS0]], [[AS1]] - ; CHECK: [[ADDR:%.*]] = bitcast [2 x i64]* %p to i8* - ; CHECK: call void @__dfsan_maybe_store_origin(i[[#SBITS]] [[AS01]], i8* [[ADDR]], i64 16, i32 [[AO]]) - ; CHECK: store [2 x i64] %a, [2 x i64]* %p, align 8 + ; CHECK: call void @__dfsan_maybe_store_origin(i[[#SBITS]] [[AS01]], ptr %p, i64 16, i32 [[AO]]) + ; CHECK: store [2 x i64] %a, ptr %p, align 8 - store [2 x i64] %a, [2 x i64]* %p + store [2 x i64] %a, ptr %p ret void } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_track_load.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_track_load.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_track_load.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_track_load.ll @@ -5,14 +5,13 @@ ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] -define i64 @load64(i64* %p) { +define i64 @load64(ptr %p) { ; CHECK-LABEL: @load64.dfsan - ; CHECK-NEXT: %[[#PO:]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__dfsan_arg_origin_tls, i64 0, i64 0), align 4 - ; CHECK-NEXT: %[[#PS:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]] + ; CHECK-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4 + ; CHECK-NEXT: %[[#PS:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] - ; CHECK-NEXT: %[[#INTP:]] = bitcast i64* %p to i8* - ; CHECK-NEXT: %[[#LABEL_ORIGIN:]] = call zeroext i64 @__dfsan_load_label_and_origin(i8* %[[#INTP]], i64 8) + ; CHECK-NEXT: %[[#LABEL_ORIGIN:]] = call zeroext i64 @__dfsan_load_label_and_origin(ptr %p, i64 8) ; CHECK-NEXT: %[[#LABEL_ORIGIN_H32:]] = lshr i64 %[[#LABEL_ORIGIN]], 32 ; CHECK-NEXT: %[[#LABEL:]] = trunc i64 %[[#LABEL_ORIGIN_H32]] to i[[#SBITS]] ; CHECK-NEXT: %[[#ORIGIN:]] = trunc i64 %[[#LABEL_ORIGIN]] to i32 @@ -22,10 +21,10 @@ ; CHECK-NEXT: %[[#NZ:]] = icmp ne i[[#SBITS]] %[[#PS]], 0 ; CHECK-NEXT: %[[#ORIGIN_SEL:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#ORIGIN_CHAINED]] - ; CHECK-NEXT: %a = load i64, i64* %p - ; CHECK-NEXT: store i[[#SBITS]] %[[#LABEL]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: store i32 %[[#ORIGIN_SEL]], i32* @__dfsan_retval_origin_tls, align 4 + ; CHECK-NEXT: %a = load i64, ptr %p + ; CHECK-NEXT: store i[[#SBITS]] %[[#LABEL]], ptr @__dfsan_retval_tls, align [[ALIGN]] + ; CHECK-NEXT: store i32 %[[#ORIGIN_SEL]], ptr @__dfsan_retval_origin_tls, align 4 - %a = load i64, i64* %p + %a = load i64, ptr %p ret i64 %a } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/prefix-rename.ll b/llvm/test/Instrumentation/DataFlowSanitizer/prefix-rename.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/prefix-rename.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/prefix-rename.ll @@ -6,10 +6,10 @@ module asm ".symver f1,f@@version1" ; CHECK: @f2.dfsan = alias {{.*}} @f1.dfsan -@f2 = alias void (), void ()* @f1 +@f2 = alias void (), ptr @f1 ; CHECK: @g2.dfsan = alias {{.*}} @g1.dfsan -@g2 = alias void (i16*), bitcast (void (i8*)* @g1 to void (i16*)*) +@g2 = alias void (ptr), ptr @g1 ; CHECK: define void @f1.dfsan define void @f1() { @@ -17,6 +17,6 @@ } ; CHECK: define void @g1.dfsan -define void @g1(i8*) { +define void @g1(ptr) { ret void } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/store.ll b/llvm/test/Instrumentation/DataFlowSanitizer/store.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/store.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/store.ll @@ -6,98 +6,101 @@ ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] -define void @store0({} %v, {}* %p) { +define void @store0({} %v, ptr %p) { ; CHECK-LABEL: @store0.dfsan - ; CHECK: store {} %v, {}* %p + ; CHECK: store {} %v, ptr %p ; CHECK-NOT: store ; CHECK: ret void - store {} %v, {}* %p + store {} %v, ptr %p ret void } -define void @store8(i8 %v, i8* %p) { +define void @store8(i8 %v, ptr %p) { ; CHECK-LABEL: @store8.dfsan - ; CHECK: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls - ; COMBINE_PTR_LABEL: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls + ; NO_COMBINE_PTR_LABEL: load i[[#SBITS]], ptr @__dfsan_arg_tls + ; COMBINE_PTR_LABEL: load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 + + ; COMBINE_PTR_LABEL: load i[[#SBITS]], ptr @__dfsan_arg_tls ; COMBINE_PTR_LABEL: or i[[#SBITS]] - ; CHECK: ptrtoint i8* {{.*}} i64 + ; CHECK: ptrtoint ptr {{.*}} i64 ; CHECK-NEXT: xor i64 - ; CHECK-NEXT: inttoptr i64 {{.*}} i[[#SBITS]]* - ; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]* + ; CHECK-NEXT: inttoptr i64 {{.*}} ptr + ; CHECK-NEXT: getelementptr i[[#SBITS]], ptr ; CHECK-NEXT: store i[[#SBITS]] - ; CHECK-NEXT: store i8 %v, i8* %p + ; CHECK-NEXT: store i8 %v, ptr %p ; CHECK-NEXT: ret void - store i8 %v, i8* %p + store i8 %v, ptr %p ret void } -define void @store16(i16 %v, i16* %p) { +define void @store16(i16 %v, ptr %p) { ; CHECK-LABEL: @store16.dfsan - ; CHECK: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls - ; COMBINE_PTR_LABEL: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls + ; NO_COMBINE_PTR_LABEL: load i[[#SBITS]], ptr @__dfsan_arg_tls + ; COMBINE_PTR_LABEL: load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 + ; COMBINE_PTR_LABEL: load i[[#SBITS]], ptr @__dfsan_arg_tls ; COMBINE_PTR_LABEL: or i[[#SBITS]] - ; CHECK: ptrtoint i16* {{.*}} i64 + ; CHECK: ptrtoint ptr {{.*}} i64 ; CHECK-NEXT: xor i64 - ; CHECK-NEXT: inttoptr i64 {{.*}} i[[#SBITS]]* - ; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]* + ; CHECK-NEXT: inttoptr i64 {{.*}} ptr + ; CHECK-NEXT: getelementptr i[[#SBITS]], ptr ; CHECK-NEXT: store i[[#SBITS]] - ; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]* + ; CHECK-NEXT: getelementptr i[[#SBITS]], ptr ; CHECK-NEXT: store i[[#SBITS]] - ; CHECK-NEXT: store i16 %v, i16* %p + ; CHECK-NEXT: store i16 %v, ptr %p ; CHECK-NEXT: ret void - store i16 %v, i16* %p + store i16 %v, ptr %p ret void } -define void @store32(i32 %v, i32* %p) { +define void @store32(i32 %v, ptr %p) { ; CHECK-LABEL: @store32.dfsan - ; CHECK: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls - ; COMBINE_PTR_LABEL: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls + ; NO_COMBINE_PTR_LABEL: load i[[#SBITS]], ptr @__dfsan_arg_tls + ; COMBINE_PTR_LABEL: load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 + ; COMBINE_PTR_LABEL: load i[[#SBITS]], ptr @__dfsan_arg_tls ; COMBINE_PTR_LABEL: or i[[#SBITS]] - ; CHECK: ptrtoint i32* {{.*}} i64 + ; CHECK: ptrtoint ptr {{.*}} i64 ; CHECK-NEXT: xor i64 - ; CHECK-NEXT: inttoptr i64 {{.*}} i[[#SBITS]]* - ; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]* + ; CHECK-NEXT: inttoptr i64 {{.*}} ptr + ; CHECK-NEXT: getelementptr i[[#SBITS]], ptr ; CHECK-NEXT: store i[[#SBITS]] - ; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]* + ; CHECK-NEXT: getelementptr i[[#SBITS]], ptr ; CHECK-NEXT: store i[[#SBITS]] - ; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]* + ; CHECK-NEXT: getelementptr i[[#SBITS]], ptr ; CHECK-NEXT: store i[[#SBITS]] - ; CHECK-NEXT: getelementptr i[[#SBITS]], i[[#SBITS]]* + ; CHECK-NEXT: getelementptr i[[#SBITS]], ptr ; CHECK-NEXT: store i[[#SBITS]] - ; CHECK-NEXT: store i32 %v, i32* %p + ; CHECK-NEXT: store i32 %v, ptr %p ; CHECK-NEXT: ret void - store i32 %v, i32* %p + store i32 %v, ptr %p ret void } -define void @store64(i64 %v, i64* %p) { +define void @store64(i64 %v, ptr %p) { ; CHECK-LABEL: @store64.dfsan - ; CHECK: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls - ; COMBINE_PTR_LABEL: load i[[#SBITS]], i[[#SBITS]]* {{.*}} @__dfsan_arg_tls + ; NO_COMBINE_PTR_LABEL: load i[[#SBITS]], ptr @__dfsan_arg_tls + ; COMBINE_PTR_LABEL: load i8, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align 2 + ; COMBINE_PTR_LABEL: load i[[#SBITS]], ptr @__dfsan_arg_tls ; COMBINE_PTR_LABEL: or i[[#SBITS]] - ; CHECK: ptrtoint i64* {{.*}} i64 + ; CHECK: ptrtoint ptr {{.*}} i64 ; CHECK-NEXT: xor i64 - ; CHECK-NEXT: inttoptr i64 {{.*}} i[[#SBITS]]* + ; CHECK-NEXT: inttoptr i64 {{.*}} ptr ; CHECK-COUNT-8: insertelement {{.*}} i[[#SBITS]] - ; CHECK-NEXT: bitcast i[[#SBITS]]* {{.*}} <8 x i[[#SBITS]]>* ; CHECK-NEXT: getelementptr <8 x i[[#SBITS]]> ; CHECK-NEXT: store <8 x i[[#SBITS]]> - ; CHECK-NEXT: store i64 %v, i64* %p + ; CHECK-NEXT: store i64 %v, ptr %p ; CHECK-NEXT: ret void - store i64 %v, i64* %p + store i64 %v, ptr %p ret void } -define void @store_zero(i32* %p) { +define void @store_zero(ptr %p) { ; CHECK-LABEL: @store_zero.dfsan - ; NO_COMBINE_PTR_LABEL: bitcast i[[#SBITS]]* {{.*}} to i[[#mul(4, SBITS)]]* - ; NO_COMBINE_PTR_LABEL: store i[[#mul(4, SBITS)]] 0, i[[#mul(4, SBITS)]]* {{.*}} - store i32 0, i32* %p + ; NO_COMBINE_PTR_LABEL: store i[[#mul(4, SBITS)]] 0, ptr {{.*}} + store i32 0, ptr %p ret void } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/struct.ll b/llvm/test/Instrumentation/DataFlowSanitizer/struct.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/struct.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/struct.ll @@ -12,38 +12,38 @@ ; CHECK: @__dfsan_shadow_width_bits = weak_odr constant i32 [[#SBITS:]] ; CHECK: @__dfsan_shadow_width_bytes = weak_odr constant i32 [[#SBYTES:]] -define {i8*, i32} @pass_struct({i8*, i32} %s) { +define {ptr, i32} @pass_struct({ptr, i32} %s) { ; NO_COMBINE_LOAD_PTR: @pass_struct.dfsan - ; NO_COMBINE_LOAD_PTR: [[L:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN:2]] - ; NO_COMBINE_LOAD_PTR: store { i[[#SBITS]], i[[#SBITS]] } [[L]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; NO_COMBINE_LOAD_PTR: [[L:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN:2]] + ; NO_COMBINE_LOAD_PTR: store { i[[#SBITS]], i[[#SBITS]] } [[L]], ptr @__dfsan_retval_tls, align [[ALIGN]] ; DEBUG_NONZERO_LABELS: @pass_struct.dfsan - ; DEBUG_NONZERO_LABELS: [[L:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN:2]] + ; DEBUG_NONZERO_LABELS: [[L:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN:2]] ; DEBUG_NONZERO_LABELS: [[L0:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[L]], 0 ; DEBUG_NONZERO_LABELS: [[L1:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[L]], 1 ; DEBUG_NONZERO_LABELS: [[L01:%.*]] = or i[[#SBITS]] [[L0]], [[L1]] ; DEBUG_NONZERO_LABELS: {{.*}} = icmp ne i[[#SBITS]] [[L01]], 0 ; DEBUG_NONZERO_LABELS: call void @__dfsan_nonzero_label() - ; DEBUG_NONZERO_LABELS: store { i[[#SBITS]], i[[#SBITS]] } [[L]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; DEBUG_NONZERO_LABELS: store { i[[#SBITS]], i[[#SBITS]] } [[L]], ptr @__dfsan_retval_tls, align [[ALIGN]] - ret {i8*, i32} %s + ret {ptr, i32} %s } -%StructOfAggr = type {i8*, [4 x i2], <4 x i3>, {i1, i1}} +%StructOfAggr = type {ptr, [4 x i2], <4 x i3>, {i1, i1}} define %StructOfAggr @pass_struct_of_aggregate(%StructOfAggr %s) { ; NO_COMBINE_LOAD_PTR: @pass_struct_of_aggregate.dfsan - ; NO_COMBINE_LOAD_PTR: %1 = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }*), align [[ALIGN:2]] - ; NO_COMBINE_LOAD_PTR: store { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } } %1, { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }*), align [[ALIGN]] + ; NO_COMBINE_LOAD_PTR: %1 = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, ptr @__dfsan_arg_tls, align [[ALIGN:2]] + ; NO_COMBINE_LOAD_PTR: store { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } } %1, ptr @__dfsan_retval_tls, align [[ALIGN]] ret %StructOfAggr %s } -define {} @load_empty_struct({}* %p) { +define {} @load_empty_struct(ptr %p) { ; NO_COMBINE_LOAD_PTR: @load_empty_struct.dfsan - ; NO_COMBINE_LOAD_PTR: store {} zeroinitializer, {}* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to {}*), align 2 + ; NO_COMBINE_LOAD_PTR: store {} zeroinitializer, ptr @__dfsan_retval_tls, align 2 - %a = load {}, {}* %p + %a = load {}, ptr %p ret {} %a } @@ -51,24 +51,24 @@ define {i1, i32} @load_global_struct() { ; NO_COMBINE_LOAD_PTR: @load_global_struct.dfsan - ; NO_COMBINE_LOAD_PTR: store { i[[#SBITS]], i[[#SBITS]] } zeroinitializer, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align 2 + ; NO_COMBINE_LOAD_PTR: store { i[[#SBITS]], i[[#SBITS]] } zeroinitializer, ptr @__dfsan_retval_tls, align 2 - %a = load {i1, i32}, {i1, i32}* @Y + %a = load {i1, i32}, ptr @Y ret {i1, i32} %a } define {i1, i32} @select_struct(i1 %c, {i1, i32} %a, {i1, i32} %b) { ; NO_SELECT_CONTROL: @select_struct.dfsan - ; NO_SELECT_CONTROL: [[B:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 [[#mul(2, SBYTES) + 2]]) to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN:2]] - ; NO_SELECT_CONTROL: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] - ; NO_SELECT_CONTROL: [[C:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; NO_SELECT_CONTROL: [[B:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2, SBYTES) + 2]]) to ptr), align [[ALIGN:2]] + ; NO_SELECT_CONTROL: [[A:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]] + ; NO_SELECT_CONTROL: [[C:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] ; NO_SELECT_CONTROL: [[S:%.*]] = select i1 %c, { i[[#SBITS]], i[[#SBITS]] } [[A]], { i[[#SBITS]], i[[#SBITS]] } [[B]] - ; NO_SELECT_CONTROL: store { i[[#SBITS]], i[[#SBITS]] } [[S]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; NO_SELECT_CONTROL: store { i[[#SBITS]], i[[#SBITS]] } [[S]], ptr @__dfsan_retval_tls, align [[ALIGN]] ; FAST: @select_struct.dfsan - ; FAST: %[[#R:]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 [[#mul(2, SBYTES) + 2]]) to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN:2]] - ; FAST: %[[#R+1]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] - ; FAST: %[[#R+2]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; FAST: %[[#R:]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2, SBYTES) + 2]]) to ptr), align [[ALIGN:2]] + ; FAST: %[[#R+1]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]] + ; FAST: %[[#R+2]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] ; FAST: %[[#R+3]] = select i1 %c, { i[[#SBITS]], i[[#SBITS]] } %[[#R+1]], { i[[#SBITS]], i[[#SBITS]] } %[[#R]] ; FAST: %[[#R+4]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } %[[#R+3]], 0 ; FAST: %[[#R+5]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } %[[#R+3]], 1 @@ -76,7 +76,7 @@ ; FAST: %[[#R+7]] = or i[[#SBITS]] %[[#R+2]], %[[#R+6]] ; FAST: %[[#R+8]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } undef, i[[#SBITS]] %[[#R+7]], 0 ; FAST: %[[#R+9]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } %[[#R+8]], i[[#SBITS]] %[[#R+7]], 1 - ; FAST: store { i[[#SBITS]], i[[#SBITS]] } %[[#R+9]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; FAST: store { i[[#SBITS]], i[[#SBITS]] } %[[#R+9]], ptr @__dfsan_retval_tls, align [[ALIGN]] %s = select i1 %c, {i1, i32} %a, {i1, i32} %b ret {i1, i32} %s @@ -84,12 +84,12 @@ define { i32, i32 } @asm_struct(i32 %0, i32 %1) { ; FAST: @asm_struct.dfsan - ; FAST: [[E1:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN:2]] - ; FAST: [[E0:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; FAST: [[E1:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN:2]] + ; FAST: [[E0:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] ; FAST: [[E01:%.*]] = or i[[#SBITS]] [[E0]], [[E1]] ; FAST: [[S0:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } undef, i[[#SBITS]] [[E01]], 0 ; FAST: [[S1:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } [[S0]], i[[#SBITS]] [[E01]], 1 - ; FAST: store { i[[#SBITS]], i[[#SBITS]] } [[S1]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; FAST: store { i[[#SBITS]], i[[#SBITS]] } [[S1]], ptr @__dfsan_retval_tls, align [[ALIGN]] entry: %a = call { i32, i32 } asm "", "=r,=r,r,r,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1) @@ -98,15 +98,15 @@ define {i32, i32} @const_struct() { ; FAST: @const_struct.dfsan - ; FAST: store { i[[#SBITS]], i[[#SBITS]] } zeroinitializer, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align 2 + ; FAST: store { i[[#SBITS]], i[[#SBITS]] } zeroinitializer, ptr @__dfsan_retval_tls, align 2 ret {i32, i32} { i32 42, i32 11 } } define i1 @extract_struct({i1, i5} %s) { ; FAST: @extract_struct.dfsan - ; FAST: [[SM:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN:2]] + ; FAST: [[SM:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN:2]] ; FAST: [[EM:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[SM]], 0 - ; FAST: store i[[#SBITS]] [[EM]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; FAST: store i[[#SBITS]] [[EM]], ptr @__dfsan_retval_tls, align [[ALIGN]] %e2 = extractvalue {i1, i5} %s, 0 ret i1 %e2 @@ -114,20 +114,20 @@ define {i1, i5} @insert_struct({i1, i5} %s, i5 %e1) { ; FAST: @insert_struct.dfsan - ; FAST: [[EM:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 [[#mul(2, SBYTES)]]) to i[[#SBITS]]*), align [[ALIGN:2]] - ; FAST: [[SM:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; FAST: [[EM:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2, SBYTES)]]) to ptr), align [[ALIGN:2]] + ; FAST: [[SM:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN]] ; FAST: [[SM1:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } [[SM]], i[[#SBITS]] [[EM]], 1 - ; FAST: store { i[[#SBITS]], i[[#SBITS]] } [[SM1]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; FAST: store { i[[#SBITS]], i[[#SBITS]] } [[SM1]], ptr @__dfsan_retval_tls, align [[ALIGN]] %s1 = insertvalue {i1, i5} %s, i5 %e1, 1 ret {i1, i5} %s1 } -define {i1, i1} @load_struct({i1, i1}* %p) { +define {i1, i1} @load_struct(ptr %p) { ; NO_COMBINE_LOAD_PTR: @load_struct.dfsan ; NO_COMBINE_LOAD_PTR: [[OL:%.*]] = or i[[#SBITS]] ; NO_COMBINE_LOAD_PTR: [[S0:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } undef, i[[#SBITS]] [[OL]], 0 ; NO_COMBINE_LOAD_PTR: [[S1:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } [[S0]], i[[#SBITS]] [[OL]], 1 - ; NO_COMBINE_LOAD_PTR: store { i[[#SBITS]], i[[#SBITS]] } [[S1]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align 2 + ; NO_COMBINE_LOAD_PTR: store { i[[#SBITS]], i[[#SBITS]] } [[S1]], ptr @__dfsan_retval_tls, align 2 ; EVENT_CALLBACKS: @load_struct.dfsan ; EVENT_CALLBACKS: [[OL0:%.*]] = or i[[#SBITS]] @@ -135,46 +135,46 @@ ; EVENT_CALLBACKS: [[S0:%.*]] = insertvalue { i[[#SBITS]], i[[#SBITS]] } undef, i[[#SBITS]] [[OL1]], 0 ; EVENT_CALLBACKS: call void @__dfsan_load_callback(i[[#SBITS]] [[OL1]] - %s = load {i1, i1}, {i1, i1}* %p + %s = load {i1, i1}, ptr %p ret {i1, i1} %s } -define void @store_struct({i1, i1}* %p, {i1, i1} %s) { +define void @store_struct(ptr %p, {i1, i1} %s) { ; FAST: @store_struct.dfsan - ; FAST: [[S:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN:2]] + ; FAST: [[S:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN:2]] ; FAST: [[E0:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[S]], 0 ; FAST: [[E1:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[S]], 1 ; FAST: [[E:%.*]] = or i[[#SBITS]] [[E0]], [[E1]] - ; FAST: [[P0:%.*]] = getelementptr i[[#SBITS]], i[[#SBITS]]* [[P:%.*]], i32 0 - ; FAST: store i[[#SBITS]] [[E]], i[[#SBITS]]* [[P0]], align [[#SBYTES]] - ; FAST: [[P1:%.*]] = getelementptr i[[#SBITS]], i[[#SBITS]]* [[P]], i32 1 - ; FAST: store i[[#SBITS]] [[E]], i[[#SBITS]]* [[P1]], align [[#SBYTES]] + ; FAST: [[P0:%.*]] = getelementptr i[[#SBITS]], ptr [[P:%.*]], i32 0 + ; FAST: store i[[#SBITS]] [[E]], ptr [[P0]], align [[#SBYTES]] + ; FAST: [[P1:%.*]] = getelementptr i[[#SBITS]], ptr [[P]], i32 1 + ; FAST: store i[[#SBITS]] [[E]], ptr [[P1]], align [[#SBYTES]] ; EVENT_CALLBACKS: @store_struct.dfsan ; EVENT_CALLBACKS: [[OL:%.*]] = or i[[#SBITS]] ; EVENT_CALLBACKS: call void @__dfsan_store_callback(i[[#SBITS]] [[OL]] ; COMBINE_STORE_PTR: @store_struct.dfsan - ; COMBINE_STORE_PTR: [[PL:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]] - ; COMBINE_STORE_PTR: [[SL:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; COMBINE_STORE_PTR: [[PL:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] + ; COMBINE_STORE_PTR: [[SL:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]] ; COMBINE_STORE_PTR: [[SL0:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[SL]], 0 ; COMBINE_STORE_PTR: [[SL1:%.*]] = extractvalue { i[[#SBITS]], i[[#SBITS]] } [[SL]], 1 ; COMBINE_STORE_PTR: [[SL01:%.*]] = or i[[#SBITS]] [[SL0]], [[SL1]] ; COMBINE_STORE_PTR: [[E:%.*]] = or i[[#SBITS]] [[SL01]], [[PL]] - ; COMBINE_STORE_PTR: [[P0:%.*]] = getelementptr i[[#SBITS]], i[[#SBITS]]* [[P:%.*]], i32 0 - ; COMBINE_STORE_PTR: store i[[#SBITS]] [[E]], i[[#SBITS]]* [[P0]], align [[#SBYTES]] - ; COMBINE_STORE_PTR: [[P1:%.*]] = getelementptr i[[#SBITS]], i[[#SBITS]]* [[P]], i32 1 - ; COMBINE_STORE_PTR: store i[[#SBITS]] [[E]], i[[#SBITS]]* [[P1]], align [[#SBYTES]] + ; COMBINE_STORE_PTR: [[P0:%.*]] = getelementptr i[[#SBITS]], ptr [[P:%.*]], i32 0 + ; COMBINE_STORE_PTR: store i[[#SBITS]] [[E]], ptr [[P0]], align [[#SBYTES]] + ; COMBINE_STORE_PTR: [[P1:%.*]] = getelementptr i[[#SBITS]], ptr [[P]], i32 1 + ; COMBINE_STORE_PTR: store i[[#SBITS]] [[E]], ptr [[P1]], align [[#SBYTES]] - store {i1, i1} %s, {i1, i1}* %p + store {i1, i1} %s, ptr %p ret void } define i2 @extract_struct_of_aggregate11(%StructOfAggr %s) { ; FAST: @extract_struct_of_aggregate11.dfsan - ; FAST: [[E:%.*]] = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }*), align [[ALIGN:2]] + ; FAST: [[E:%.*]] = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, ptr @__dfsan_arg_tls, align [[ALIGN:2]] ; FAST: [[E11:%.*]] = extractvalue { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } } [[E]], 1, 1 - ; FAST: store i[[#SBITS]] [[E11]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; FAST: store i[[#SBITS]] [[E11]], ptr @__dfsan_retval_tls, align [[ALIGN]] %e11 = extractvalue %StructOfAggr %s, 1, 1 ret i2 %e11 @@ -182,74 +182,74 @@ define [4 x i2] @extract_struct_of_aggregate1(%StructOfAggr %s) { ; FAST: @extract_struct_of_aggregate1.dfsan - ; FAST: [[E:%.*]] = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }*), align [[ALIGN:2]] + ; FAST: [[E:%.*]] = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, ptr @__dfsan_arg_tls, align [[ALIGN:2]] ; FAST: [[E1:%.*]] = extractvalue { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } } [[E]], 1 - ; FAST: store [4 x i[[#SBITS]]] [[E1]], [4 x i[[#SBITS]]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to [4 x i[[#SBITS]]]*), align [[ALIGN]] + ; FAST: store [4 x i[[#SBITS]]] [[E1]], ptr @__dfsan_retval_tls, align [[ALIGN]] %e1 = extractvalue %StructOfAggr %s, 1 ret [4 x i2] %e1 } define <4 x i3> @extract_struct_of_aggregate2(%StructOfAggr %s) { ; FAST: @extract_struct_of_aggregate2.dfsan - ; FAST: [[E:%.*]] = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }*), align [[ALIGN:2]] + ; FAST: [[E:%.*]] = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, ptr @__dfsan_arg_tls, align [[ALIGN:2]] ; FAST: [[E2:%.*]] = extractvalue { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } } [[E]], 2 - ; FAST: store i[[#SBITS]] [[E2]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; FAST: store i[[#SBITS]] [[E2]], ptr @__dfsan_retval_tls, align [[ALIGN]] %e2 = extractvalue %StructOfAggr %s, 2 ret <4 x i3> %e2 } define { i1, i1 } @extract_struct_of_aggregate3(%StructOfAggr %s) { ; FAST: @extract_struct_of_aggregate3.dfsan - ; FAST: [[E:%.*]] = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }*), align [[ALIGN:2]] + ; FAST: [[E:%.*]] = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, ptr @__dfsan_arg_tls, align [[ALIGN:2]] ; FAST: [[E3:%.*]] = extractvalue { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } } [[E]], 3 - ; FAST: store { i[[#SBITS]], i[[#SBITS]] } [[E3]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; FAST: store { i[[#SBITS]], i[[#SBITS]] } [[E3]], ptr @__dfsan_retval_tls, align [[ALIGN]] %e3 = extractvalue %StructOfAggr %s, 3 ret { i1, i1 } %e3 } define i1 @extract_struct_of_aggregate31(%StructOfAggr %s) { ; FAST: @extract_struct_of_aggregate31.dfsan - ; FAST: [[E:%.*]] = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }*), align [[ALIGN:2]] + ; FAST: [[E:%.*]] = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, ptr @__dfsan_arg_tls, align [[ALIGN:2]] ; FAST: [[E31:%.*]] = extractvalue { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } } [[E]], 3, 1 - ; FAST: store i[[#SBITS]] [[E31]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; FAST: store i[[#SBITS]] [[E31]], ptr @__dfsan_retval_tls, align [[ALIGN]] %e31 = extractvalue %StructOfAggr %s, 3, 1 ret i1 %e31 } define %StructOfAggr @insert_struct_of_aggregate11(%StructOfAggr %s, i2 %e11) { ; FAST: @insert_struct_of_aggregate11.dfsan - ; FAST: [[E11:%.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 [[#mul(8, SBYTES)]]) to i[[#SBITS]]*), align [[ALIGN:2]] - ; FAST: [[S:%.*]] = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }*), align [[ALIGN]] + ; FAST: [[E11:%.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(8, SBYTES)]]) to ptr), align [[ALIGN:2]] + ; FAST: [[S:%.*]] = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, ptr @__dfsan_arg_tls, align [[ALIGN]] ; FAST: [[S1:%.*]] = insertvalue { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } } [[S]], i[[#SBITS]] [[E11]], 1, 1 - ; FAST: store { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } } [[S1]], { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }*), align [[ALIGN]] + ; FAST: store { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } } [[S1]], ptr @__dfsan_retval_tls, align [[ALIGN]] %s1 = insertvalue %StructOfAggr %s, i2 %e11, 1, 1 ret %StructOfAggr %s1 } -define {i8*, i32} @call_struct({i8*, i32} %s) { +define {ptr, i32} @call_struct({ptr, i32} %s) { ; FAST: @call_struct.dfsan - ; FAST: [[S:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN:2]] - ; FAST: store { i[[#SBITS]], i[[#SBITS]] } [[S]], { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] - ; FAST: %_dfsret = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] - ; FAST: store { i[[#SBITS]], i[[#SBITS]] } %_dfsret, { i[[#SBITS]], i[[#SBITS]] }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] + ; FAST: [[S:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_arg_tls, align [[ALIGN:2]] + ; FAST: store { i[[#SBITS]], i[[#SBITS]] } [[S]], ptr @__dfsan_arg_tls, align [[ALIGN]] + ; FAST: %_dfsret = load { i[[#SBITS]], i[[#SBITS]] }, ptr @__dfsan_retval_tls, align [[ALIGN]] + ; FAST: store { i[[#SBITS]], i[[#SBITS]] } %_dfsret, ptr @__dfsan_retval_tls, align [[ALIGN]] - %r = call {i8*, i32} @pass_struct({i8*, i32} %s) - ret {i8*, i32} %r + %r = call {ptr, i32} @pass_struct({ptr, i32} %s) + ret {ptr, i32} %r } declare %StructOfAggr @fun_with_many_aggr_args(<2 x i7> %v, [2 x i5] %a, {i3, i3} %s) define %StructOfAggr @call_many_aggr_args(<2 x i7> %v, [2 x i5] %a, {i3, i3} %s) { ; FAST: @call_many_aggr_args.dfsan - ; FAST: [[S:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, { i[[#SBITS]], i[[#SBITS]] }* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 [[#mul(2, SBYTES) + 2]]) to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN:2]] - ; FAST: [[A:%.*]] = load [2 x i[[#SBITS]]], [2 x i[[#SBITS]]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to [2 x i[[#SBITS]]]*), align [[ALIGN]] - ; FAST: [[V:%.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] - ; FAST: store i[[#SBITS]] [[V]], i[[#SBITS]]* bitcast ([[TLS_ARR]]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] - ; FAST: store [2 x i[[#SBITS]]] [[A]], [2 x i[[#SBITS]]]* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 2) to [2 x i[[#SBITS]]]*), align [[ALIGN]] - ; FAST: store { i[[#SBITS]], i[[#SBITS]] } [[S]], { i[[#SBITS]], i[[#SBITS]] }* inttoptr (i64 add (i64 ptrtoint ([[TLS_ARR]]* @__dfsan_arg_tls to i64), i64 [[#mul(2, SBYTES) + 2]]) to { i[[#SBITS]], i[[#SBITS]] }*), align [[ALIGN]] - ; FAST: %_dfsret = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }*), align [[ALIGN]] - ; FAST: store { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } } %_dfsret, { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }* bitcast ([[TLS_ARR]]* @__dfsan_retval_tls to { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }*), align [[ALIGN]] + ; FAST: [[S:%.*]] = load { i[[#SBITS]], i[[#SBITS]] }, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2, SBYTES) + 2]]) to ptr), align [[ALIGN:2]] + ; FAST: [[A:%.*]] = load [2 x i[[#SBITS]]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]] + ; FAST: [[V:%.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] + ; FAST: store i[[#SBITS]] [[V]], ptr @__dfsan_arg_tls, align [[ALIGN]] + ; FAST: store [2 x i[[#SBITS]]] [[A]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN]] + ; FAST: store { i[[#SBITS]], i[[#SBITS]] } [[S]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 [[#mul(2, SBYTES) + 2]]) to ptr), align [[ALIGN]] + ; FAST: %_dfsret = load { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } }, ptr @__dfsan_retval_tls, align [[ALIGN]] + ; FAST: store { i[[#SBITS]], [4 x i[[#SBITS]]], i[[#SBITS]], { i[[#SBITS]], i[[#SBITS]] } } %_dfsret, ptr @__dfsan_retval_tls, align [[ALIGN]] %r = call %StructOfAggr @fun_with_many_aggr_args(<2 x i7> %v, [2 x i5] %a, {i3, i3} %s) ret %StructOfAggr %r diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/union.ll b/llvm/test/Instrumentation/DataFlowSanitizer/union.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/union.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/union.ll @@ -14,10 +14,10 @@ define void @f(i32 %x, i32 %y) { ; CHECK: or i[[#SBITS]] %xay = add i32 %x, %y - store i32 %xay, i32* @a + store i32 %xay, ptr @a ; CHECK-NOT: or i[[#SBITS]] %xmy = mul i32 %x, %y - store i32 %xmy, i32* @b + store i32 %xmy, ptr @b ret void } @@ -31,13 +31,13 @@ l1: ; CHECK: or i[[#SBITS]] %xay = add i32 %x, %y - store i32 %xay, i32* @a + store i32 %xay, ptr @a br label %l3 l2: ; CHECK: or i[[#SBITS]] %xmy = mul i32 %x, %y - store i32 %xmy, i32* @b + store i32 %xmy, ptr @b br label %l3 l3: diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/unordered_atomic_mem_intrins.ll b/llvm/test/Instrumentation/DataFlowSanitizer/unordered_atomic_mem_intrins.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/unordered_atomic_mem_intrins.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/unordered_atomic_mem_intrins.ll @@ -8,30 +8,30 @@ ;; verify that dfsan handles these intrinsics properly once they have been ;; added to that class hierarchy. -declare void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* nocapture writeonly, i8, i64, i32) nounwind -declare void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind -declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind +declare void @llvm.memset.element.unordered.atomic.p0.i64(ptr nocapture writeonly, i8, i64, i32) nounwind +declare void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind +declare void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind -define void @test_memcpy(i8* nocapture, i8* nocapture) { +define void @test_memcpy(ptr nocapture, ptr nocapture) { ; CHECK-LABEL: test_memcpy.dfsan - ; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %0, i8* align 1 %1, i64 16, i32 1) + ; CHECK: call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 16, i32 1) ; CHECK: ret void - call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %0, i8* align 1 %1, i64 16, i32 1) + call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 16, i32 1) ret void } -define void @test_memmove(i8* nocapture, i8* nocapture) { +define void @test_memmove(ptr nocapture, ptr nocapture) { ; CHECK-LABEL: test_memmove.dfsan - ; CHECK: call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %0, i8* align 1 %1, i64 16, i32 1) + ; CHECK: call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 16, i32 1) ; CHECK: ret void - call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %0, i8* align 1 %1, i64 16, i32 1) + call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 %0, ptr align 1 %1, i64 16, i32 1) ret void } -define void @test_memset(i8* nocapture) { +define void @test_memset(ptr nocapture) { ; CHECK-LABEL: test_memset.dfsan - ; CHECK: call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %0, i8 88, i64 16, i32 1) + ; CHECK: call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 %0, i8 88, i64 16, i32 1) ; CHECK: ret void - call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %0, i8 88, i64 16, i32 1) + call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 %0, i8 88, i64 16, i32 1) ret void } diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/vector.ll b/llvm/test/Instrumentation/DataFlowSanitizer/vector.ll --- a/llvm/test/Instrumentation/DataFlowSanitizer/vector.ll +++ b/llvm/test/Instrumentation/DataFlowSanitizer/vector.ll @@ -7,31 +7,31 @@ define <4 x i4> @pass_vector(<4 x i4> %v) { ; CHECK-LABEL: @pass_vector.dfsan - ; CHECK-NEXT: %[[#REG:]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]] - ; CHECK-NEXT: store i[[#SBITS]] %[[#REG]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %[[#REG:]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] + ; CHECK-NEXT: store i[[#SBITS]] %[[#REG]], ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK-NEXT: ret <4 x i4> %v ret <4 x i4> %v } -define void @load_update_store_vector(<4 x i4>* %p) { +define void @load_update_store_vector(ptr %p) { ; CHECK-LABEL: @load_update_store_vector.dfsan - ; CHECK: {{.*}} = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align 2 + ; CHECK: {{.*}} = load i[[#SBITS]], ptr @__dfsan_arg_tls, align 2 - %v = load <4 x i4>, <4 x i4>* %p + %v = load <4 x i4>, ptr %p %e2 = extractelement <4 x i4> %v, i32 2 %v1 = insertelement <4 x i4> %v, i4 %e2, i32 0 - store <4 x i4> %v1, <4 x i4>* %p + store <4 x i4> %v1, ptr %p ret void } define <4 x i1> @icmp_vector(<4 x i8> %a, <4 x i8> %b) { ; CHECK-LABEL: @icmp_vector.dfsan - ; CHECK-NEXT: %[[B:.*]] = load i[[#SBITS]], i[[#SBITS]]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__dfsan_arg_tls to i64), i64 2) to i[[#SBITS]]*), align [[ALIGN:2]] - ; CHECK-NEXT: %[[A:.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %[[B:.*]] = load i[[#SBITS]], ptr inttoptr (i64 add (i64 ptrtoint (ptr @__dfsan_arg_tls to i64), i64 2) to ptr), align [[ALIGN:2]] + ; CHECK-NEXT: %[[A:.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN]] ; CHECK: %[[L:.*]] = or i[[#SBITS]] %[[A]], %[[B]] ; CHECK: %r = icmp eq <4 x i8> %a, %b - ; CHECK: store i[[#SBITS]] %[[L]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK: store i[[#SBITS]] %[[L]], ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK: ret <4 x i1> %r %r = icmp eq <4 x i8> %a, %b @@ -40,7 +40,7 @@ define <2 x i32> @const_vector() { ; CHECK-LABEL: @const_vector.dfsan - ; CHECK-NEXT: store i[[#SBITS]] 0, i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align 2 + ; CHECK-NEXT: store i[[#SBITS]] 0, ptr @__dfsan_retval_tls, align 2 ; CHECK-NEXT: ret <2 x i32> ret <2 x i32> < i32 42, i32 11 > @@ -48,11 +48,11 @@ define <4 x i4> @call_vector(<4 x i4> %v) { ; CHECK-LABEL: @call_vector.dfsan - ; CHECK-NEXT: %[[V:.*]] = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN:2]] - ; CHECK-NEXT: store i[[#SBITS]] %[[V]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_arg_tls to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %[[V:.*]] = load i[[#SBITS]], ptr @__dfsan_arg_tls, align [[ALIGN:2]] + ; CHECK-NEXT: store i[[#SBITS]] %[[V]], ptr @__dfsan_arg_tls, align [[ALIGN]] ; CHECK-NEXT: %r = call <4 x i4> @pass_vector.dfsan(<4 x i4> %v) - ; CHECK-NEXT: %_dfsret = load i[[#SBITS]], i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] - ; CHECK-NEXT: store i[[#SBITS]] %_dfsret, i[[#SBITS]]* bitcast ([100 x i64]* @__dfsan_retval_tls to i[[#SBITS]]*), align [[ALIGN]] + ; CHECK-NEXT: %_dfsret = load i[[#SBITS]], ptr @__dfsan_retval_tls, align [[ALIGN]] + ; CHECK-NEXT: store i[[#SBITS]] %_dfsret, ptr @__dfsan_retval_tls, align [[ALIGN]] ; CHECK-NEXT: ret <4 x i4> %r %r = call <4 x i4> @pass_vector(<4 x i4> %v) diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-array.ll b/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-array.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-array.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-array.ll @@ -3,13 +3,13 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare void @use(i8*, i8*) +declare void @use(ptr, ptr) define void @test_alloca() sanitize_hwaddress { ; CHECK: alloca { [4 x i8], [12 x i8] }, align 16 %x = alloca i8, i64 4 ; CHECK: alloca i8, i64 16, align 16 %y = alloca i8, i64 16 - call void @use(i8* %x, i8* %y) + call void @use(ptr %x, ptr %y) ret void } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-with-calls.ll b/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-with-calls.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-with-calls.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca-with-calls.ll @@ -5,19 +5,18 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare void @use32(i32*) +declare void @use32(ptr) define void @test_alloca() sanitize_hwaddress { ; CHECK-LABEL: @test_alloca( -; CHECK: %[[BC:[^ ]*]] = bitcast { i32, [12 x i8] }* %x to i32* ; CHECK: %[[T1:[^ ]*]] = call i8 @__hwasan_generate_tag() ; CHECK: %[[A:[^ ]*]] = zext i8 %[[T1]] to i64 -; CHECK: %[[B:[^ ]*]] = ptrtoint i32* %[[BC]] to i64 +; CHECK: %[[B:[^ ]*]] = ptrtoint ptr %x to i64 ; CHECK: %[[C:[^ ]*]] = shl i64 %[[A]], 57 ; CHECK: or i64 %[[B]], %[[C]] entry: %x = alloca i32, align 4 - call void @use32(i32* nonnull %x) + call void @use32(ptr nonnull %x) ret void } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll b/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/X86/alloca.ll @@ -6,40 +6,37 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare void @use32(i32*) +declare void @use32(ptr) define void @test_alloca() sanitize_hwaddress { ; CHECK-LABEL: @test_alloca( -; CHECK: %[[FP:[^ ]*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %[[FP]] to i64 +; CHECK: %[[FP:[^ ]*]] = call ptr @llvm.frameaddress.p0(i32 0) +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %[[FP]] to i64 ; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 20 ; CHECK: %[[A_XOR_B:[^ ]*]] = xor i64 %[[A]], %[[B]] ; CHECK: %[[BASE_TAG:[^ ]*]] = and i64 %[[A_XOR_B]], 63 ; CHECK: %[[X:[^ ]*]] = alloca { i32, [12 x i8] }, align 16 -; CHECK: %[[X_BC:[^ ]*]] = bitcast { i32, [12 x i8] }* %[[X]] to i32* ; CHECK: %[[X_TAG:[^ ]*]] = xor i64 %[[BASE_TAG]], 0 -; CHECK: %[[X1:[^ ]*]] = ptrtoint i32* %[[X_BC]] to i64 +; CHECK: %[[X1:[^ ]*]] = ptrtoint ptr %[[X]] to i64 ; CHECK: %[[C:[^ ]*]] = shl i64 %[[X_TAG]], 57 ; CHECK: %[[D:[^ ]*]] = or i64 %[[X1]], %[[C]] -; CHECK: %[[X_HWASAN:[^ ]*]] = inttoptr i64 %[[D]] to i32* +; CHECK: %[[X_HWASAN:[^ ]*]] = inttoptr i64 %[[D]] to ptr ; CHECK: %[[X_TAG2:[^ ]*]] = trunc i64 %[[X_TAG]] to i8 -; CHECK: %[[X_I8:[^ ]*]] = bitcast i32* %[[X_BC]] to i8* -; CHECK: call void @__hwasan_tag_memory(i8* %[[X_I8]], i8 %[[X_TAG2]], i64 16) +; CHECK: call void @__hwasan_tag_memory(ptr %[[X]], i8 %[[X_TAG2]], i64 16) -; CHECK: call void @use32(i32* nonnull %[[X_HWASAN]]) +; CHECK: call void @use32(ptr nonnull %[[X_HWASAN]]) ; UAR-TAGS: %[[BASE_TAG_COMPL:[^ ]*]] = xor i64 %[[BASE_TAG]], 63 ; UAR-TAGS: %[[X_TAG_UAR:[^ ]*]] = trunc i64 %[[BASE_TAG_COMPL]] to i8 -; CHECK: %[[X_I8_2:[^ ]*]] = bitcast i32* %[[X_BC]] to i8* -; NO-UAR-TAGS: call void @__hwasan_tag_memory(i8* %[[X_I8_2]], i8 0, i64 16) -; UAR-TAGS: call void @__hwasan_tag_memory(i8* %[[X_I8_2]], i8 %[[X_TAG_UAR]], i64 16) +; NO-UAR-TAGS: call void @__hwasan_tag_memory(ptr %[[X]], i8 0, i64 16) +; UAR-TAGS: call void @__hwasan_tag_memory(ptr %[[X]], i8 %[[X_TAG_UAR]], i64 16) ; CHECK: ret void entry: %x = alloca i32, align 4 - call void @use32(i32* nonnull %x) + call void @use32(ptr nonnull %x) ret void } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/X86/atomic.ll b/llvm/test/Instrumentation/HWAddressSanitizer/X86/atomic.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/X86/atomic.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/X86/atomic.ll @@ -5,30 +5,30 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define void @atomicrmw(i64* %ptr) sanitize_hwaddress { +define void @atomicrmw(ptr %ptr) sanitize_hwaddress { ; CHECK-LABEL: @atomicrmw( -; CHECK: %[[A:[^ ]*]] = ptrtoint i64* %ptr to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %ptr to i64 ; CHECK: call void @__hwasan_store8(i64 %[[A]]) -; CHECK: atomicrmw add i64* %ptr, i64 1 seq_cst +; CHECK: atomicrmw add ptr %ptr, i64 1 seq_cst ; CHECK: ret void entry: - %0 = atomicrmw add i64* %ptr, i64 1 seq_cst + %0 = atomicrmw add ptr %ptr, i64 1 seq_cst ret void } -define void @cmpxchg(i64* %ptr, i64 %compare_to, i64 %new_value) sanitize_hwaddress { +define void @cmpxchg(ptr %ptr, i64 %compare_to, i64 %new_value) sanitize_hwaddress { ; CHECK-LABEL: @cmpxchg( -; CHECK: %[[A:[^ ]*]] = ptrtoint i64* %ptr to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %ptr to i64 ; CHECK: call void @__hwasan_store8(i64 %[[A]]) -; CHECK: cmpxchg i64* %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst +; CHECK: cmpxchg ptr %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst ; CHECK: ret void entry: - %0 = cmpxchg i64* %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst + %0 = cmpxchg ptr %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst ret void } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll b/llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/X86/basic.ll @@ -8,77 +8,77 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define i8 @test_load8(i8* %a) sanitize_hwaddress { +define i8 @test_load8(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load8( -; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_load1(i64 %[[A]]) ; RECOVER: call void @__hwasan_load1_noabort(i64 %[[A]]) -; CHECK: %[[G:[^ ]*]] = load i8, i8* %a, align 4 +; CHECK: %[[G:[^ ]*]] = load i8, ptr %a, align 4 ; CHECK: ret i8 %[[G]] entry: - %b = load i8, i8* %a, align 4 + %b = load i8, ptr %a, align 4 ret i8 %b } -define i40 @test_load40(i40* %a) sanitize_hwaddress { +define i40 @test_load40(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load40( -; CHECK: %[[A:[^ ]*]] = ptrtoint i40* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_loadN(i64 %[[A]], i64 5) ; RECOVER: call void @__hwasan_loadN_noabort(i64 %[[A]], i64 5) -; CHECK: %[[B:[^ ]*]] = load i40, i40* %a +; CHECK: %[[B:[^ ]*]] = load i40, ptr %a ; CHECK: ret i40 %[[B]] entry: - %b = load i40, i40* %a, align 4 + %b = load i40, ptr %a, align 4 ret i40 %b } -define void @test_store8(i8* %a, i8 %b) sanitize_hwaddress { +define void @test_store8(ptr %a, i8 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store8( -; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_store1(i64 %[[A]]) ; RECOVER: call void @__hwasan_store1_noabort(i64 %[[A]]) -; CHECK: store i8 %b, i8* %a, align 4 +; CHECK: store i8 %b, ptr %a, align 4 ; CHECK: ret void entry: - store i8 %b, i8* %a, align 4 + store i8 %b, ptr %a, align 4 ret void } -define void @test_store40(i40* %a, i40 %b) sanitize_hwaddress { +define void @test_store40(ptr %a, i40 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store40( -; CHECK: %[[A:[^ ]*]] = ptrtoint i40* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_storeN(i64 %[[A]], i64 5) ; RECOVER: call void @__hwasan_storeN_noabort(i64 %[[A]], i64 5) -; CHECK: store i40 %b, i40* %a +; CHECK: store i40 %b, ptr %a ; CHECK: ret void entry: - store i40 %b, i40* %a, align 4 + store i40 %b, ptr %a, align 4 ret void } -define void @test_store_unaligned(i64* %a, i64 %b) sanitize_hwaddress { +define void @test_store_unaligned(ptr %a, i64 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store_unaligned( -; CHECK: %[[A:[^ ]*]] = ptrtoint i64* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_storeN(i64 %[[A]], i64 8) ; RECOVER: call void @__hwasan_storeN_noabort(i64 %[[A]], i64 8) -; CHECK: store i64 %b, i64* %a, align 4 +; CHECK: store i64 %b, ptr %a, align 4 ; CHECK: ret void entry: - store i64 %b, i64* %a, align 4 + store i64 %b, ptr %a, align 4 ret void } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/X86/kernel.ll b/llvm/test/Instrumentation/HWAddressSanitizer/X86/kernel.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/X86/kernel.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/X86/kernel.ll @@ -11,18 +11,18 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define i8 @test_load(i8* %a) sanitize_hwaddress { +define i8 @test_load(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load( -; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_load1(i64 %[[A]]) ; RECOVER: call void @__hwasan_load1_noabort(i64 %[[A]]) -; CHECK: %[[G:[^ ]*]] = load i8, i8* %a, align 4 +; CHECK: %[[G:[^ ]*]] = load i8, ptr %a, align 4 ; CHECK: ret i8 %[[G]] entry: - %b = load i8, i8* %a, align 4 + %b = load i8, ptr %a, align 4 ret i8 %b } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/X86/with-calls.ll b/llvm/test/Instrumentation/HWAddressSanitizer/X86/with-calls.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/X86/with-calls.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/X86/with-calls.ll @@ -6,62 +6,62 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define i8 @test_load8(i8* %a) sanitize_hwaddress { +define i8 @test_load8(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load8( -; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_load1(i64 %[[A]]) ; RECOVER: call void @__hwasan_load1_noabort(i64 %[[A]]) -; CHECK: %[[B:[^ ]*]] = load i8, i8* %a +; CHECK: %[[B:[^ ]*]] = load i8, ptr %a ; CHECK: ret i8 %[[B]] entry: - %b = load i8, i8* %a, align 4 + %b = load i8, ptr %a, align 4 ret i8 %b } -define i40 @test_load40(i40* %a) sanitize_hwaddress { +define i40 @test_load40(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load40( -; CHECK: %[[A:[^ ]*]] = ptrtoint i40* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_loadN(i64 %[[A]], i64 5) ; RECOVER: call void @__hwasan_loadN_noabort(i64 %[[A]], i64 5) -; CHECK: %[[B:[^ ]*]] = load i40, i40* %a +; CHECK: %[[B:[^ ]*]] = load i40, ptr %a ; CHECK: ret i40 %[[B]] entry: - %b = load i40, i40* %a, align 4 + %b = load i40, ptr %a, align 4 ret i40 %b } -define void @test_store8(i8* %a, i8 %b) sanitize_hwaddress { +define void @test_store8(ptr %a, i8 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store8( -; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_store1(i64 %[[A]]) ; RECOVER: call void @__hwasan_store1_noabort(i64 %[[A]]) -; CHECK: store i8 %b, i8* %a +; CHECK: store i8 %b, ptr %a ; CHECK: ret void entry: - store i8 %b, i8* %a, align 4 + store i8 %b, ptr %a, align 4 ret void } -define void @test_store40(i40* %a, i40 %b) sanitize_hwaddress { +define void @test_store40(ptr %a, i40 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store40( -; CHECK: %[[A:[^ ]*]] = ptrtoint i40* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_storeN(i64 %[[A]], i64 5) ; RECOVER: call void @__hwasan_storeN_noabort(i64 %[[A]], i64 5) -; CHECK: store i40 %b, i40* %a +; CHECK: store i40 %b, ptr %a ; CHECK: ret void entry: - store i40 %b, i40* %a, align 4 + store i40 %b, ptr %a, align 4 ret void } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/alloca-array.ll b/llvm/test/Instrumentation/HWAddressSanitizer/alloca-array.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/alloca-array.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/alloca-array.ll @@ -3,13 +3,13 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android" -declare void @use(i8*, i8*) +declare void @use(ptr, ptr) define void @test_alloca() sanitize_hwaddress { ; CHECK: alloca { [4 x i8], [12 x i8] }, align 16 %x = alloca i8, i64 4 ; CHECK: alloca i8, i64 16, align 16 %y = alloca i8, i64 16 - call void @use(i8* %x, i8* %y) + call void @use(ptr %x, ptr %y) ret void } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/alloca-compat.ll b/llvm/test/Instrumentation/HWAddressSanitizer/alloca-compat.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/alloca-compat.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/alloca-compat.ll @@ -5,13 +5,13 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android" -declare void @use32(i32*) +declare void @use32(ptr) define void @test_alloca() sanitize_hwaddress { ; CHECK-LABEL: @test_alloca( ; CHECK: %[[X_TAG:[^ ]*]] = trunc i64 {{.*}} to i8 -; CHECK: call void @llvm.memset.p0i8.i64(i8* align 1 {{.*}}, i8 %[[X_TAG]], i64 1, i1 false) +; CHECK: call void @llvm.memset.p0.i64(ptr align 1 {{.*}}, i8 %[[X_TAG]], i64 1, i1 false) %x = alloca i32, align 4 - call void @use32(i32* nonnull %x) + call void @use32(ptr nonnull %x) ret void } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/alloca-uninteresting.ll b/llvm/test/Instrumentation/HWAddressSanitizer/alloca-uninteresting.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/alloca-uninteresting.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/alloca-uninteresting.ll @@ -7,21 +7,21 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android10000" -declare void @use32(i32*) +declare void @use32(ptr) define void @test_dyn_alloca(i32 %n) sanitize_hwaddress !dbg !15 { ; CHECK-LABEL: @test_dyn_alloca( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[X:%.*]] = alloca i32, i32 [[N:%.*]], align 4 -; CHECK-NEXT: call void @llvm.dbg.value(metadata !DIArgList(i32* [[X]], i32* [[X]]), metadata [[META10:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_deref)), !dbg [[DBG12:![0-9]+]] -; CHECK-NEXT: call void @use32(i32* nonnull [[X]]), !dbg [[DBG13:![0-9]+]] +; CHECK-NEXT: call void @llvm.dbg.value(metadata !DIArgList(ptr [[X]], ptr [[X]]), metadata [[META10:![0-9]+]], metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_deref)), !dbg [[DBG12:![0-9]+]] +; CHECK-NEXT: call void @use32(ptr nonnull [[X]]), !dbg [[DBG13:![0-9]+]] ; CHECK-NEXT: ret void, !dbg [[DBG14:![0-9]+]] ; entry: %x = alloca i32, i32 %n, align 4 - call void @llvm.dbg.value(metadata !DIArgList(i32* %x, i32* %x), metadata !22, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_deref)), !dbg !21 - call void @use32(i32* nonnull %x), !dbg !23 + call void @llvm.dbg.value(metadata !DIArgList(ptr %x, ptr %x), metadata !22, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_deref)), !dbg !21 + call void @use32(ptr nonnull %x), !dbg !23 ret void, !dbg !24 } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/alloca-with-calls.ll b/llvm/test/Instrumentation/HWAddressSanitizer/alloca-with-calls.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/alloca-with-calls.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/alloca-with-calls.ll @@ -5,19 +5,18 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android" -declare void @use32(i32*) +declare void @use32(ptr) define void @test_alloca() sanitize_hwaddress { ; CHECK-LABEL: @test_alloca( -; CHECK: %[[BC:[^ ]*]] = bitcast { i32, [12 x i8] }* %x to i32* ; CHECK: %[[T1:[^ ]*]] = call i8 @__hwasan_generate_tag() ; CHECK: %[[A:[^ ]*]] = zext i8 %[[T1]] to i64 -; CHECK: %[[B:[^ ]*]] = ptrtoint i32* %[[BC]] to i64 +; CHECK: %[[B:[^ ]*]] = ptrtoint ptr %x to i64 ; CHECK: %[[C:[^ ]*]] = shl i64 %[[A]], 56 ; CHECK: or i64 %[[B]], %[[C]] entry: %x = alloca i32, align 4 - call void @use32(i32* nonnull %x) + call void @use32(ptr nonnull %x) ret void } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll b/llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll @@ -7,53 +7,51 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android10000" -declare void @use32(i32*) +declare void @use32(ptr) define void @test_alloca() sanitize_hwaddress !dbg !15 { ; CHECK-LABEL: @test_alloca( -; CHECK: %[[FP:[^ ]*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %[[FP]] to i64 +; CHECK: %[[FP:[^ ]*]] = call ptr @llvm.frameaddress.p0(i32 0) +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %[[FP]] to i64 ; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 20 ; CHECK: %[[BASE_TAG:[^ ]*]] = xor i64 %[[A]], %[[B]] ; CHECK: %[[X:[^ ]*]] = alloca { i32, [12 x i8] }, align 16 -; CHECK: %[[X_BC:[^ ]*]] = bitcast { i32, [12 x i8] }* %[[X]] to i32* ; CHECK: %[[X_TAG:[^ ]*]] = xor i64 %[[BASE_TAG]], 0 -; CHECK: %[[X1:[^ ]*]] = ptrtoint i32* %[[X_BC]] to i64 +; CHECK: %[[X1:[^ ]*]] = ptrtoint ptr %[[X]] to i64 ; CHECK: %[[C:[^ ]*]] = shl i64 %[[X_TAG]], 56 ; CHECK: %[[D:[^ ]*]] = or i64 %[[X1]], %[[C]] -; CHECK: %[[X_HWASAN:[^ ]*]] = inttoptr i64 %[[D]] to i32* +; CHECK: %[[X_HWASAN:[^ ]*]] = inttoptr i64 %[[D]] to ptr ; CHECK: %[[X_TAG2:[^ ]*]] = trunc i64 %[[X_TAG]] to i8 -; CHECK: %[[E:[^ ]*]] = ptrtoint i32* %[[X_BC]] to i64 +; CHECK: %[[E:[^ ]*]] = ptrtoint ptr %[[X]] to i64 ; CHECK: %[[F:[^ ]*]] = lshr i64 %[[E]], 4 -; DYNAMIC-SHADOW: %[[X_SHADOW:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %[[F]] -; ZERO-BASED-SHADOW: %[[X_SHADOW:[^ ]*]] = inttoptr i64 %[[F]] to i8* -; CHECK: %[[X_SHADOW_GEP:[^ ]*]] = getelementptr i8, i8* %[[X_SHADOW]], i32 0 -; CHECK: store i8 4, i8* %[[X_SHADOW_GEP]] -; CHECK: %[[X_I8:[^ ]*]] = bitcast i32* %[[X_BC]] to i8* -; CHECK: %[[X_I8_GEP:[^ ]*]] = getelementptr i8, i8* %[[X_I8]], i32 15 -; CHECK: store i8 %[[X_TAG2]], i8* %[[X_I8_GEP]] +; DYNAMIC-SHADOW: %[[X_SHADOW:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %[[F]] +; ZERO-BASED-SHADOW: %[[X_SHADOW:[^ ]*]] = inttoptr i64 %[[F]] to ptr +; CHECK: %[[X_SHADOW_GEP:[^ ]*]] = getelementptr i8, ptr %[[X_SHADOW]], i32 0 +; CHECK: store i8 4, ptr %[[X_SHADOW_GEP]] +; CHECK: %[[X_I8_GEP:[^ ]*]] = getelementptr i8, ptr %[[X]], i32 15 +; CHECK: store i8 %[[X_TAG2]], ptr %[[X_I8_GEP]] ; CHECK: call void @llvm.dbg.value( -; CHECK-SAME: metadata !DIArgList(i32* %[[X_BC]], i32* %[[X_BC]]) +; CHECK-SAME: metadata !DIArgList(ptr %[[X]], ptr %[[X]]) ; CHECK-SAME: metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_tag_offset, 0, DW_OP_LLVM_arg, 1, DW_OP_LLVM_tag_offset, 0, -; CHECK: call void @use32(i32* nonnull %[[X_HWASAN]]) +; CHECK: call void @use32(ptr nonnull %[[X_HWASAN]]) ; UAR-TAGS: %[[BASE_TAG_COMPL:[^ ]*]] = xor i64 %[[BASE_TAG]], 255 ; UAR-TAGS: %[[X_TAG_UAR:[^ ]*]] = trunc i64 %[[BASE_TAG_COMPL]] to i8 -; CHECK: %[[E2:[^ ]*]] = ptrtoint i32* %[[X_BC]] to i64 +; CHECK: %[[E2:[^ ]*]] = ptrtoint ptr %[[X]] to i64 ; CHECK: %[[F2:[^ ]*]] = lshr i64 %[[E2]], 4 -; DYNAMIC-SHADOW: %[[X_SHADOW2:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %[[F2]] -; ZERO-BASED-SHADOW: %[[X_SHADOW2:[^ ]*]] = inttoptr i64 %[[F2]] to i8* -; NO-UAR-TAGS: call void @llvm.memset.p0i8.i64(i8* align 1 %[[X_SHADOW2]], i8 0, i64 1, i1 false) -; UAR-TAGS: call void @llvm.memset.p0i8.i64(i8* align 1 %[[X_SHADOW2]], i8 %[[X_TAG_UAR]], i64 1, i1 false) +; DYNAMIC-SHADOW: %[[X_SHADOW2:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %[[F2]] +; ZERO-BASED-SHADOW: %[[X_SHADOW2:[^ ]*]] = inttoptr i64 %[[F2]] to ptr +; NO-UAR-TAGS: call void @llvm.memset.p0.i64(ptr align 1 %[[X_SHADOW2]], i8 0, i64 1, i1 false) +; UAR-TAGS: call void @llvm.memset.p0.i64(ptr align 1 %[[X_SHADOW2]], i8 %[[X_TAG_UAR]], i64 1, i1 false) ; CHECK: ret void entry: %x = alloca i32, align 4 - call void @llvm.dbg.value(metadata !DIArgList(i32* %x, i32* %x), metadata !22, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_deref)), !dbg !21 - call void @use32(i32* nonnull %x), !dbg !23 + call void @llvm.dbg.value(metadata !DIArgList(ptr %x, ptr %x), metadata !22, metadata !DIExpression(DW_OP_LLVM_arg, 0, DW_OP_LLVM_arg, 1, DW_OP_plus, DW_OP_deref)), !dbg !21 + call void @use32(ptr nonnull %x), !dbg !23 ret void, !dbg !24 } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/atomic.ll b/llvm/test/Instrumentation/HWAddressSanitizer/atomic.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/atomic.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/atomic.ll @@ -5,26 +5,24 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android" -define void @atomicrmw(i64* %ptr) sanitize_hwaddress { +define void @atomicrmw(ptr %ptr) sanitize_hwaddress { ; CHECK-LABEL: @atomicrmw( -; CHECK: [[PTRI8:%[^ ]*]] = bitcast i64* %ptr to i8* -; CHECK: call void @llvm.hwasan.check.memaccess({{.*}}, i8* [[PTRI8]], i32 19) -; CHECK: atomicrmw add i64* %ptr, i64 1 seq_cst +; CHECK: call void @llvm.hwasan.check.memaccess({{.*}}, ptr %ptr, i32 19) +; CHECK: atomicrmw add ptr %ptr, i64 1 seq_cst ; CHECK: ret void entry: - %0 = atomicrmw add i64* %ptr, i64 1 seq_cst + %0 = atomicrmw add ptr %ptr, i64 1 seq_cst ret void } -define void @cmpxchg(i64* %ptr, i64 %compare_to, i64 %new_value) sanitize_hwaddress { +define void @cmpxchg(ptr %ptr, i64 %compare_to, i64 %new_value) sanitize_hwaddress { ; CHECK-LABEL: @cmpxchg( -; CHECK: [[PTRI8:%[^ ]*]] = bitcast i64* %ptr to i8* -; CHECK: call void @llvm.hwasan.check.memaccess({{.*}}, i8* [[PTRI8]], i32 19) -; CHECK: cmpxchg i64* %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst +; CHECK: call void @llvm.hwasan.check.memaccess({{.*}}, ptr %ptr, i32 19) +; CHECK: cmpxchg ptr %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst ; CHECK: ret void entry: - %0 = cmpxchg i64* %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst + %0 = cmpxchg ptr %ptr, i64 %compare_to, i64 %new_value seq_cst seq_cst ret void } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/basic-compat.ll b/llvm/test/Instrumentation/HWAddressSanitizer/basic-compat.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/basic-compat.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/basic-compat.ll @@ -5,9 +5,9 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android" -define i8 @test_load8(i8* %a) sanitize_hwaddress { +define i8 @test_load8(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load8( -; CHECK: call void @llvm.hwasan.check.memaccess(i8* {{.*}}, i8* {{.*}}, i32 0) - %b = load i8, i8* %a, align 4 +; CHECK: call void @llvm.hwasan.check.memaccess(ptr {{.*}}, ptr {{.*}}, i32 0) + %b = load i8, ptr %a, align 4 ret i8 %b } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/basic.ll b/llvm/test/Instrumentation/HWAddressSanitizer/basic.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/basic.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/basic.ll @@ -5,22 +5,22 @@ ; RUN: opt < %s -passes=hwasan -hwasan-recover=0 -hwasan-mapping-offset=0 -S | FileCheck %s --check-prefixes=CHECK,ABORT ; RUN: opt < %s -passes=hwasan -hwasan-recover=1 -hwasan-mapping-offset=0 -S | FileCheck %s --check-prefixes=CHECK,RECOVER,RECOVER-ZERO-BASED-SHADOW -; CHECK: @llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @hwasan.module_ctor to i8*)] -; CHECK: @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 0, void ()* @hwasan.module_ctor, i8* bitcast (void ()* @hwasan.module_ctor to i8*) }] +; CHECK: @llvm.used = appending global [1 x ptr] [ptr @hwasan.module_ctor] +; CHECK: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 0, ptr @hwasan.module_ctor, ptr @hwasan.module_ctor }] target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android10000" -define i8 @test_load8(i8* %a) sanitize_hwaddress { +define i8 @test_load8(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load8( -; RECOVER: %[[A:[^ ]*]] = ptrtoint i8* %a to i64 +; RECOVER: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; RECOVER: %[[B:[^ ]*]] = lshr i64 %[[A]], 56 ; RECOVER: %[[PTRTAG:[^ ]*]] = trunc i64 %[[B]] to i8 ; RECOVER: %[[C:[^ ]*]] = and i64 %[[A]], 72057594037927935 ; RECOVER: %[[D:[^ ]*]] = lshr i64 %[[C]], 4 -; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %4 -; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to i8* -; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, i8* %[[E]] +; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %4 +; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to ptr +; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, ptr %[[E]] ; RECOVER: %[[F:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[MEMTAG]] ; RECOVER: br i1 %[[F]], label %[[MISMATCH:[0-9]*]], label %[[CONT:[0-9]*]], !prof {{.*}} @@ -41,8 +41,8 @@ ; RECOVER: [[INBOUNDS]]: ; RECOVER: %[[EOG_ADDR:[^ ]*]] = or i64 %[[C]], 15 -; RECOVER: %[[EOG_PTR:[^ ]*]] = inttoptr i64 %[[EOG_ADDR]] to i8* -; RECOVER: %[[EOGTAG:[^ ]*]] = load i8, i8* %[[EOG_PTR]] +; RECOVER: %[[EOG_PTR:[^ ]*]] = inttoptr i64 %[[EOG_ADDR]] to ptr +; RECOVER: %[[EOGTAG:[^ ]*]] = load i8, ptr %[[EOG_PTR]] ; RECOVER: %[[EOG_MISMATCH:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[EOGTAG]] ; RECOVER: br i1 %[[EOG_MISMATCH]], label %[[FAIL]], label %[[CONT1:[0-9]*]], !prof {{.*}} @@ -51,26 +51,26 @@ ; RECOVER: [[CONT]]: -; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %a, i32 0) +; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr %.hwasan.shadow, ptr %a, i32 0) -; CHECK: %[[G:[^ ]*]] = load i8, i8* %a, align 4 +; CHECK: %[[G:[^ ]*]] = load i8, ptr %a, align 4 ; CHECK: ret i8 %[[G]] entry: - %b = load i8, i8* %a, align 4 + %b = load i8, ptr %a, align 4 ret i8 %b } -define i16 @test_load16(i16* %a) sanitize_hwaddress { +define i16 @test_load16(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load16( -; RECOVER: %[[A:[^ ]*]] = ptrtoint i16* %a to i64 +; RECOVER: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; RECOVER: %[[B:[^ ]*]] = lshr i64 %[[A]], 56 ; RECOVER: %[[PTRTAG:[^ ]*]] = trunc i64 %[[B]] to i8 ; RECOVER: %[[C:[^ ]*]] = and i64 %[[A]], 72057594037927935 ; RECOVER: %[[D:[^ ]*]] = lshr i64 %[[C]], 4 -; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %4 -; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to i8* -; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, i8* %[[E]] +; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %4 +; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to ptr +; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, ptr %[[E]] ; RECOVER: %[[F:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[MEMTAG]] ; RECOVER: br i1 %[[F]], label %[[MISMATCH:[0-9]*]], label %[[CONT:[0-9]*]], !prof {{.*}} @@ -91,8 +91,8 @@ ; RECOVER: [[INBOUNDS]]: ; RECOVER: %[[EOG_ADDR:[^ ]*]] = or i64 %[[C]], 15 -; RECOVER: %[[EOG_PTR:[^ ]*]] = inttoptr i64 %[[EOG_ADDR]] to i8* -; RECOVER: %[[EOGTAG:[^ ]*]] = load i8, i8* %[[EOG_PTR]] +; RECOVER: %[[EOG_PTR:[^ ]*]] = inttoptr i64 %[[EOG_ADDR]] to ptr +; RECOVER: %[[EOGTAG:[^ ]*]] = load i8, ptr %[[EOG_PTR]] ; RECOVER: %[[EOG_MISMATCH:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[EOGTAG]] ; RECOVER: br i1 %[[EOG_MISMATCH]], label %[[FAIL]], label %[[CONT1:[0-9]*]], !prof {{.*}} @@ -101,301 +101,293 @@ ; RECOVER: [[CONT]]: -; ABORT: %[[A:[^ ]*]] = bitcast i16* %a to i8* -; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 1) +; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr %.hwasan.shadow, ptr %a, i32 1) -; CHECK: %[[G:[^ ]*]] = load i16, i16* %a, align 4 +; CHECK: %[[G:[^ ]*]] = load i16, ptr %a, align 4 ; CHECK: ret i16 %[[G]] entry: - %b = load i16, i16* %a, align 4 + %b = load i16, ptr %a, align 4 ret i16 %b } -define i32 @test_load32(i32* %a) sanitize_hwaddress { +define i32 @test_load32(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load32( -; RECOVER: %[[A:[^ ]*]] = ptrtoint i32* %a to i64 +; RECOVER: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; RECOVER: %[[B:[^ ]*]] = lshr i64 %[[A]], 56 ; RECOVER: %[[PTRTAG:[^ ]*]] = trunc i64 %[[B]] to i8 ; RECOVER: %[[C:[^ ]*]] = and i64 %[[A]], 72057594037927935 ; RECOVER: %[[D:[^ ]*]] = lshr i64 %[[C]], 4 -; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %4 -; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to i8* -; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, i8* %[[E]] +; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %4 +; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to ptr +; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, ptr %[[E]] ; RECOVER: %[[F:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[MEMTAG]] ; RECOVER: br i1 %[[F]], label {{.*}}, label {{.*}}, !prof {{.*}} ; RECOVER: call void asm sideeffect "brk #2338", "{x0}"(i64 %[[A]]) ; RECOVER: br label -; ABORT: %[[A:[^ ]*]] = bitcast i32* %a to i8* -; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 2) +; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr %.hwasan.shadow, ptr %a, i32 2) -; CHECK: %[[G:[^ ]*]] = load i32, i32* %a, align 4 +; CHECK: %[[G:[^ ]*]] = load i32, ptr %a, align 4 ; CHECK: ret i32 %[[G]] entry: - %b = load i32, i32* %a, align 4 + %b = load i32, ptr %a, align 4 ret i32 %b } -define i64 @test_load64(i64* %a) sanitize_hwaddress { +define i64 @test_load64(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load64( -; RECOVER: %[[A:[^ ]*]] = ptrtoint i64* %a to i64 +; RECOVER: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; RECOVER: %[[B:[^ ]*]] = lshr i64 %[[A]], 56 ; RECOVER: %[[PTRTAG:[^ ]*]] = trunc i64 %[[B]] to i8 ; RECOVER: %[[C:[^ ]*]] = and i64 %[[A]], 72057594037927935 ; RECOVER: %[[D:[^ ]*]] = lshr i64 %[[C]], 4 -; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %4 -; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to i8* -; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, i8* %[[E]] +; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %4 +; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to ptr +; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, ptr %[[E]] ; RECOVER: %[[F:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[MEMTAG]] ; RECOVER: br i1 %[[F]], label {{.*}}, label {{.*}}, !prof {{.*}} ; RECOVER: call void asm sideeffect "brk #2339", "{x0}"(i64 %[[A]]) ; RECOVER: br label -; ABORT: %[[A:[^ ]*]] = bitcast i64* %a to i8* -; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 3) +; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr %.hwasan.shadow, ptr %a, i32 3) -; CHECK: %[[G:[^ ]*]] = load i64, i64* %a, align 8 +; CHECK: %[[G:[^ ]*]] = load i64, ptr %a, align 8 ; CHECK: ret i64 %[[G]] entry: - %b = load i64, i64* %a, align 8 + %b = load i64, ptr %a, align 8 ret i64 %b } -define i128 @test_load128(i128* %a) sanitize_hwaddress { +define i128 @test_load128(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load128( -; RECOVER: %[[A:[^ ]*]] = ptrtoint i128* %a to i64 +; RECOVER: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; RECOVER: %[[B:[^ ]*]] = lshr i64 %[[A]], 56 ; RECOVER: %[[PTRTAG:[^ ]*]] = trunc i64 %[[B]] to i8 ; RECOVER: %[[C:[^ ]*]] = and i64 %[[A]], 72057594037927935 ; RECOVER: %[[D:[^ ]*]] = lshr i64 %[[C]], 4 -; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %4 -; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to i8* -; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, i8* %[[E]] +; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %4 +; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to ptr +; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, ptr %[[E]] ; RECOVER: %[[F:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[MEMTAG]] ; RECOVER: br i1 %[[F]], label {{.*}}, label {{.*}}, !prof {{.*}} ; RECOVER: call void asm sideeffect "brk #2340", "{x0}"(i64 %[[A]]) ; RECOVER: br label -; ABORT: %[[A:[^ ]*]] = bitcast i128* %a to i8* -; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 4) +; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr %.hwasan.shadow, ptr %a, i32 4) -; CHECK: %[[G:[^ ]*]] = load i128, i128* %a, align 16 +; CHECK: %[[G:[^ ]*]] = load i128, ptr %a, align 16 ; CHECK: ret i128 %[[G]] entry: - %b = load i128, i128* %a, align 16 + %b = load i128, ptr %a, align 16 ret i128 %b } -define i40 @test_load40(i40* %a) sanitize_hwaddress { +define i40 @test_load40(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load40( -; CHECK: %[[A:[^ ]*]] = ptrtoint i40* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_loadN(i64 %[[A]], i64 5) ; RECOVER: call void @__hwasan_loadN_noabort(i64 %[[A]], i64 5) -; CHECK: %[[B:[^ ]*]] = load i40, i40* %a +; CHECK: %[[B:[^ ]*]] = load i40, ptr %a ; CHECK: ret i40 %[[B]] entry: - %b = load i40, i40* %a, align 4 + %b = load i40, ptr %a, align 4 ret i40 %b } -define void @test_store8(i8* %a, i8 %b) sanitize_hwaddress { +define void @test_store8(ptr %a, i8 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store8( -; RECOVER: %[[A:[^ ]*]] = ptrtoint i8* %a to i64 +; RECOVER: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; RECOVER: %[[B:[^ ]*]] = lshr i64 %[[A]], 56 ; RECOVER: %[[PTRTAG:[^ ]*]] = trunc i64 %[[B]] to i8 ; RECOVER: %[[C:[^ ]*]] = and i64 %[[A]], 72057594037927935 ; RECOVER: %[[D:[^ ]*]] = lshr i64 %[[C]], 4 -; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %4 -; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to i8* -; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, i8* %[[E]] +; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %4 +; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to ptr +; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, ptr %[[E]] ; RECOVER: %[[F:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[MEMTAG]] ; RECOVER: br i1 %[[F]], label {{.*}}, label {{.*}}, !prof {{.*}} ; RECOVER: call void asm sideeffect "brk #2352", "{x0}"(i64 %[[A]]) ; RECOVER: br label -; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %a, i32 16) +; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr %.hwasan.shadow, ptr %a, i32 16) -; CHECK: store i8 %b, i8* %a, align 4 +; CHECK: store i8 %b, ptr %a, align 4 ; CHECK: ret void entry: - store i8 %b, i8* %a, align 4 + store i8 %b, ptr %a, align 4 ret void } -define void @test_store16(i16* %a, i16 %b) sanitize_hwaddress { +define void @test_store16(ptr %a, i16 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store16( -; RECOVER: %[[A:[^ ]*]] = ptrtoint i16* %a to i64 +; RECOVER: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; RECOVER: %[[B:[^ ]*]] = lshr i64 %[[A]], 56 ; RECOVER: %[[PTRTAG:[^ ]*]] = trunc i64 %[[B]] to i8 ; RECOVER: %[[C:[^ ]*]] = and i64 %[[A]], 72057594037927935 ; RECOVER: %[[D:[^ ]*]] = lshr i64 %[[C]], 4 -; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %4 -; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to i8* -; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, i8* %[[E]] +; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %4 +; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to ptr +; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, ptr %[[E]] ; RECOVER: %[[F:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[MEMTAG]] ; RECOVER: br i1 %[[F]], label {{.*}}, label {{.*}}, !prof {{.*}} ; RECOVER: call void asm sideeffect "brk #2353", "{x0}"(i64 %[[A]]) ; RECOVER: br label -; ABORT: %[[A:[^ ]*]] = bitcast i16* %a to i8* -; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 17) +; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr %.hwasan.shadow, ptr %a, i32 17) -; CHECK: store i16 %b, i16* %a, align 4 +; CHECK: store i16 %b, ptr %a, align 4 ; CHECK: ret void entry: - store i16 %b, i16* %a, align 4 + store i16 %b, ptr %a, align 4 ret void } -define void @test_store32(i32* %a, i32 %b) sanitize_hwaddress { +define void @test_store32(ptr %a, i32 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store32( -; RECOVER: %[[A:[^ ]*]] = ptrtoint i32* %a to i64 +; RECOVER: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; RECOVER: %[[B:[^ ]*]] = lshr i64 %[[A]], 56 ; RECOVER: %[[PTRTAG:[^ ]*]] = trunc i64 %[[B]] to i8 ; RECOVER: %[[C:[^ ]*]] = and i64 %[[A]], 72057594037927935 ; RECOVER: %[[D:[^ ]*]] = lshr i64 %[[C]], 4 -; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %4 -; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to i8* -; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, i8* %[[E]] +; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %4 +; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to ptr +; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, ptr %[[E]] ; RECOVER: %[[F:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[MEMTAG]] ; RECOVER: br i1 %[[F]], label {{.*}}, label {{.*}}, !prof {{.*}} ; RECOVER: call void asm sideeffect "brk #2354", "{x0}"(i64 %[[A]]) ; RECOVER: br label -; ABORT: %[[A:[^ ]*]] = bitcast i32* %a to i8* -; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 18) +; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr %.hwasan.shadow, ptr %a, i32 18) -; CHECK: store i32 %b, i32* %a, align 4 +; CHECK: store i32 %b, ptr %a, align 4 ; CHECK: ret void entry: - store i32 %b, i32* %a, align 4 + store i32 %b, ptr %a, align 4 ret void } -define void @test_store64(i64* %a, i64 %b) sanitize_hwaddress { +define void @test_store64(ptr %a, i64 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store64( -; RECOVER: %[[A:[^ ]*]] = ptrtoint i64* %a to i64 +; RECOVER: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; RECOVER: %[[B:[^ ]*]] = lshr i64 %[[A]], 56 ; RECOVER: %[[PTRTAG:[^ ]*]] = trunc i64 %[[B]] to i8 ; RECOVER: %[[C:[^ ]*]] = and i64 %[[A]], 72057594037927935 ; RECOVER: %[[D:[^ ]*]] = lshr i64 %[[C]], 4 -; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %4 -; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to i8* -; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, i8* %[[E]] +; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %4 +; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to ptr +; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, ptr %[[E]] ; RECOVER: %[[F:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[MEMTAG]] ; RECOVER: br i1 %[[F]], label {{.*}}, label {{.*}}, !prof {{.*}} ; RECOVER: call void asm sideeffect "brk #2355", "{x0}"(i64 %[[A]]) ; RECOVER: br label -; ABORT: %[[A:[^ ]*]] = bitcast i64* %a to i8* -; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 19) +; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr %.hwasan.shadow, ptr %a, i32 19) -; CHECK: store i64 %b, i64* %a, align 8 +; CHECK: store i64 %b, ptr %a, align 8 ; CHECK: ret void entry: - store i64 %b, i64* %a, align 8 + store i64 %b, ptr %a, align 8 ret void } -define void @test_store128(i128* %a, i128 %b) sanitize_hwaddress { +define void @test_store128(ptr %a, i128 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store128( -; RECOVER: %[[A:[^ ]*]] = ptrtoint i128* %a to i64 +; RECOVER: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; RECOVER: %[[B:[^ ]*]] = lshr i64 %[[A]], 56 ; RECOVER: %[[PTRTAG:[^ ]*]] = trunc i64 %[[B]] to i8 ; RECOVER: %[[C:[^ ]*]] = and i64 %[[A]], 72057594037927935 ; RECOVER: %[[D:[^ ]*]] = lshr i64 %[[C]], 4 -; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, i8* %.hwasan.shadow, i64 %4 -; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to i8* -; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, i8* %[[E]] +; RECOVER-DYNAMIC-SHADOW: %[[E:[^ ]*]] = getelementptr i8, ptr %.hwasan.shadow, i64 %4 +; RECOVER-ZERO-BASED-SHADOW: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to ptr +; RECOVER: %[[MEMTAG:[^ ]*]] = load i8, ptr %[[E]] ; RECOVER: %[[F:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[MEMTAG]] ; RECOVER: br i1 %[[F]], label {{.*}}, label {{.*}}, !prof {{.*}} ; RECOVER: call void asm sideeffect "brk #2356", "{x0}"(i64 %[[A]]) ; RECOVER: br label -; ABORT: %[[A:[^ ]*]] = bitcast i128* %a to i8* -; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 20) +; ABORT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr %.hwasan.shadow, ptr %a, i32 20) -; CHECK: store i128 %b, i128* %a, align 16 +; CHECK: store i128 %b, ptr %a, align 16 ; CHECK: ret void entry: - store i128 %b, i128* %a, align 16 + store i128 %b, ptr %a, align 16 ret void } -define void @test_store40(i40* %a, i40 %b) sanitize_hwaddress { +define void @test_store40(ptr %a, i40 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store40( -; CHECK: %[[A:[^ ]*]] = ptrtoint i40* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_storeN(i64 %[[A]], i64 5) ; RECOVER: call void @__hwasan_storeN_noabort(i64 %[[A]], i64 5) -; CHECK: store i40 %b, i40* %a +; CHECK: store i40 %b, ptr %a ; CHECK: ret void entry: - store i40 %b, i40* %a, align 4 + store i40 %b, ptr %a, align 4 ret void } -define void @test_store_unaligned(i64* %a, i64 %b) sanitize_hwaddress { +define void @test_store_unaligned(ptr %a, i64 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store_unaligned( -; CHECK: %[[A:[^ ]*]] = ptrtoint i64* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_storeN(i64 %[[A]], i64 8) ; RECOVER: call void @__hwasan_storeN_noabort(i64 %[[A]], i64 8) -; CHECK: store i64 %b, i64* %a, align 4 +; CHECK: store i64 %b, ptr %a, align 4 ; CHECK: ret void entry: - store i64 %b, i64* %a, align 4 + store i64 %b, ptr %a, align 4 ret void } -define i8 @test_load_noattr(i8* %a) { +define i8 @test_load_noattr(ptr %a) { ; CHECK-LABEL: @test_load_noattr( ; CHECK-NEXT: entry: -; CHECK-NEXT: %[[B:[^ ]*]] = load i8, i8* %a +; CHECK-NEXT: %[[B:[^ ]*]] = load i8, ptr %a ; CHECK-NEXT: ret i8 %[[B]] entry: - %b = load i8, i8* %a, align 4 + %b = load i8, ptr %a, align 4 ret i8 %b } -define i8 @test_load_notmyattr(i8* %a) sanitize_address { +define i8 @test_load_notmyattr(ptr %a) sanitize_address { ; CHECK-LABEL: @test_load_notmyattr( ; CHECK-NEXT: entry: -; CHECK-NEXT: %[[B:[^ ]*]] = load i8, i8* %a +; CHECK-NEXT: %[[B:[^ ]*]] = load i8, ptr %a ; CHECK-NEXT: ret i8 %[[B]] entry: - %b = load i8, i8* %a, align 4 + %b = load i8, ptr %a, align 4 ret i8 %b } -define i8 @test_load_addrspace(i8 addrspace(256)* %a) sanitize_hwaddress { +define i8 @test_load_addrspace(ptr addrspace(256) %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load_addrspace( ; CHECK-NEXT: entry: -; CHECK-NEXT: %[[B:[^ ]*]] = load i8, i8 addrspace(256)* %a +; CHECK-NEXT: %[[B:[^ ]*]] = load i8, ptr addrspace(256) %a ; CHECK-NEXT: ret i8 %[[B]] entry: - %b = load i8, i8 addrspace(256)* %a, align 4 + %b = load i8, ptr addrspace(256) %a, align 4 ret i8 %b } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/dbg-declare-tag-offset.ll b/llvm/test/Instrumentation/HWAddressSanitizer/dbg-declare-tag-offset.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/dbg-declare-tag-offset.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/dbg-declare-tag-offset.ll @@ -3,25 +3,25 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android" -declare void @g(i8**, i8**, i8**, i8**, i8**, i8**) +declare void @g(ptr, ptr, ptr, ptr, ptr, ptr) define void @f() sanitize_hwaddress !dbg !6 { entry: - %nodebug0 = alloca i8* - %nodebug1 = alloca i8* - %nodebug2 = alloca i8* - %nodebug3 = alloca i8* - %a = alloca i8* - %b = alloca i8* + %nodebug0 = alloca ptr + %nodebug1 = alloca ptr + %nodebug2 = alloca ptr + %nodebug3 = alloca ptr + %a = alloca ptr + %b = alloca ptr ; CHECK: @llvm.dbg.declare{{.*}} !DIExpression(DW_OP_LLVM_tag_offset, 32) - call void @llvm.dbg.declare(metadata i8** %a, metadata !12, metadata !DIExpression()), !dbg !14 + call void @llvm.dbg.declare(metadata ptr %a, metadata !12, metadata !DIExpression()), !dbg !14 ; CHECK: @llvm.dbg.declare{{.*}} !DIExpression(DW_OP_LLVM_tag_offset, 32) - call void @llvm.dbg.declare(metadata i8** %a, metadata !12, metadata !DIExpression()), !dbg !14 + call void @llvm.dbg.declare(metadata ptr %a, metadata !12, metadata !DIExpression()), !dbg !14 ; CHECK: @llvm.dbg.declare{{.*}} !DIExpression(DW_OP_LLVM_tag_offset, 96) - call void @llvm.dbg.declare(metadata i8** %b, metadata !13, metadata !DIExpression()), !dbg !14 + call void @llvm.dbg.declare(metadata ptr %b, metadata !13, metadata !DIExpression()), !dbg !14 ; CHECK: @llvm.dbg.declare{{.*}} !DIExpression(DW_OP_LLVM_tag_offset, 96) - call void @llvm.dbg.declare(metadata i8** %b, metadata !13, metadata !DIExpression()), !dbg !14 - call void @g(i8** %nodebug0, i8** %nodebug1, i8** %nodebug2, i8** %nodebug3, i8** %a, i8** %b) + call void @llvm.dbg.declare(metadata ptr %b, metadata !13, metadata !DIExpression()), !dbg !14 + call void @g(ptr %nodebug0, ptr %nodebug1, ptr %nodebug2, ptr %nodebug3, ptr %a, ptr %b) ret void, !dbg !15 } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/dbg-value-tag-offset-nopad.ll b/llvm/test/Instrumentation/HWAddressSanitizer/dbg-value-tag-offset-nopad.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/dbg-value-tag-offset-nopad.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/dbg-value-tag-offset-nopad.ll @@ -6,21 +6,19 @@ define dso_local void @f() sanitize_hwaddress !dbg !14 { %a1 = alloca i128, align 4 %a2 = alloca i128, align 4 - %1 = bitcast i128* %a1 to i8*, !dbg !21 - %2 = bitcast i128* %a2 to i8*, !dbg !21 ; CHECK: call void @llvm.dbg.value(metadata i128 1, {{.*}}, metadata !DIExpression()) call void @llvm.dbg.value(metadata i128 1, metadata !20, metadata !DIExpression()), !dbg !22 - store i128 1, i128* %a2, align 4, !dbg !23, !tbaa !24 -; CHECK: call void @llvm.dbg.value(metadata i128* %a1, {{.*}}, metadata !DIExpression(DW_OP_LLVM_tag_offset, 0, DW_OP_deref)) - call void @llvm.dbg.value(metadata i128* %a1, metadata !18, metadata !DIExpression(DW_OP_deref)), !dbg !22 - call void @use(i8* nonnull %1), !dbg !28 -; CHECK: call void @llvm.dbg.value(metadata i128* %a2, {{.*}}, metadata !DIExpression(DW_OP_LLVM_tag_offset, 128, DW_OP_deref)) - call void @llvm.dbg.value(metadata i128* %a2, metadata !20, metadata !DIExpression(DW_OP_deref)), !dbg !22 - call void @use(i8* nonnull %2), !dbg !29 + store i128 1, ptr %a2, align 4, !dbg !23, !tbaa !24 +; CHECK: call void @llvm.dbg.value(metadata ptr %a1, {{.*}}, metadata !DIExpression(DW_OP_LLVM_tag_offset, 0, DW_OP_deref)) + call void @llvm.dbg.value(metadata ptr %a1, metadata !18, metadata !DIExpression(DW_OP_deref)), !dbg !22 + call void @use(ptr nonnull %a1), !dbg !28 +; CHECK: call void @llvm.dbg.value(metadata ptr %a2, {{.*}}, metadata !DIExpression(DW_OP_LLVM_tag_offset, 128, DW_OP_deref)) + call void @llvm.dbg.value(metadata ptr %a2, metadata !20, metadata !DIExpression(DW_OP_deref)), !dbg !22 + call void @use(ptr nonnull %a2), !dbg !29 ret void, !dbg !30 } -declare !dbg !5 void @use(i8*) +declare !dbg !5 void @use(ptr) declare void @llvm.dbg.value(metadata, metadata, metadata) diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/dbg-value-tag-offset.ll b/llvm/test/Instrumentation/HWAddressSanitizer/dbg-value-tag-offset.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/dbg-value-tag-offset.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/dbg-value-tag-offset.ll @@ -6,23 +6,19 @@ define dso_local void @f() sanitize_hwaddress !dbg !14 { %a1 = alloca i32, align 4 %a2 = alloca i32, align 4 - %1 = bitcast i32* %a1 to i8*, !dbg !21 - %2 = bitcast i32* %a2 to i8*, !dbg !21 -; CHECK: {{[ ]*}}[[BITCASTa1:.*]] = bitcast { i32, [12 x i8] }* %a1 to i32* -; CHECK: {{[ ]*}}[[BITCASTa2:.*]] = bitcast { i32, [12 x i8] }* %a2 to i32* ; CHECK: call void @llvm.dbg.value(metadata i32 1, {{.*}}, metadata !DIExpression()) call void @llvm.dbg.value(metadata i32 1, metadata !20, metadata !DIExpression()), !dbg !22 - store i32 1, i32* %a2, align 4, !dbg !23, !tbaa !24 -; CHECK: call void @llvm.dbg.value(metadata i32* {{.*}}[[BITCASTa1]], {{.*}} metadata !DIExpression(DW_OP_LLVM_tag_offset, 0, DW_OP_deref)) - call void @llvm.dbg.value(metadata i32* %a1, metadata !18, metadata !DIExpression(DW_OP_deref)), !dbg !22 - call void @use(i8* nonnull %1), !dbg !28 -; CHECK: call void @llvm.dbg.value(metadata i32* {{.*}}[[BITCASTa2]], {{.*}} metadata !DIExpression(DW_OP_LLVM_tag_offset, 128, DW_OP_deref)) - call void @llvm.dbg.value(metadata i32* %a2, metadata !20, metadata !DIExpression(DW_OP_deref)), !dbg !22 - call void @use(i8* nonnull %2), !dbg !29 + store i32 1, ptr %a2, align 4, !dbg !23, !tbaa !24 +; CHECK: call void @llvm.dbg.value(metadata ptr %a1, {{.*}} metadata !DIExpression(DW_OP_LLVM_tag_offset, 0, DW_OP_deref)) + call void @llvm.dbg.value(metadata ptr %a1, metadata !18, metadata !DIExpression(DW_OP_deref)), !dbg !22 + call void @use(ptr nonnull %a1), !dbg !28 +; CHECK: call void @llvm.dbg.value(metadata ptr %a2, {{.*}} metadata !DIExpression(DW_OP_LLVM_tag_offset, 128, DW_OP_deref)) + call void @llvm.dbg.value(metadata ptr %a2, metadata !20, metadata !DIExpression(DW_OP_deref)), !dbg !22 + call void @use(ptr nonnull %a2), !dbg !29 ret void, !dbg !30 } -declare !dbg !5 void @use(i8*) +declare !dbg !5 void @use(ptr) declare void @llvm.dbg.value(metadata, metadata, metadata) diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/exception-lifetime.ll b/llvm/test/Instrumentation/HWAddressSanitizer/exception-lifetime.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/exception-lifetime.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/exception-lifetime.ll @@ -6,55 +6,50 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android" -declare void @mayFail(i32* %x) sanitize_hwaddress -declare void @onExcept(i32* %x) sanitize_hwaddress +declare void @mayFail(ptr %x) sanitize_hwaddress +declare void @onExcept(ptr %x) sanitize_hwaddress -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) nounwind -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) nounwind +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) nounwind +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) nounwind declare i32 @__gxx_personality_v0(...) -define void @test() sanitize_hwaddress personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +define void @test() sanitize_hwaddress personality ptr @__gxx_personality_v0 { entry: %x = alloca i32, align 8 - %exn.slot = alloca i8*, align 8 + %exn.slot = alloca ptr, align 8 %ehselector.slot = alloca i32, align 4 - %0 = bitcast i32* %x to i8* - call void @llvm.lifetime.start.p0i8(i64 8, i8* %0) - invoke void @mayFail(i32* %x) to label %invoke.cont unwind label %lpad -; CHECK: [[CAST:%.*]] = bitcast { i32, [12 x i8] }* %x to i32* -; CHECK: [[TMP1:%.*]] = bitcast i32* {{.*}}[[CAST]] to i8* + call void @llvm.lifetime.start.p0(i64 8, ptr %x) + invoke void @mayFail(ptr %x) to label %invoke.cont unwind label %lpad invoke.cont: ; preds = %entry ; CHECK: invoke.cont: -; CHECK: call void @llvm.memset.p0i8.i64(i8* align 1 %{{.*}}, i8 0, i64 1, i1 false) -; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* {{.*}}[[TMP1]]) +; CHECK: call void @llvm.memset.p0.i64(ptr align 1 %{{.*}}, i8 0, i64 1, i1 false) +; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr {{.*}}{{.*}}%x) ; CHECK: ret void - %1 = bitcast i32* %x to i8* - call void @llvm.lifetime.end.p0i8(i64 8, i8* %1) + call void @llvm.lifetime.end.p0(i64 8, ptr %x) ret void lpad: ; preds = %entry ; CHECK: lpad -; CHECK: call void @llvm.memset.p0i8.i64(i8* align 1 %{{.*}}, i8 0, i64 1, i1 false) -; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* {{.*}}[[TMP1]]) +; CHECK: call void @llvm.memset.p0.i64(ptr align 1 %{{.*}}, i8 0, i64 1, i1 false) +; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr {{.*}}{{.*}}%x) ; CHECK: br label %eh.resume - %2 = landingpad { i8*, i32 } + %0 = landingpad { ptr, i32 } cleanup - %3 = extractvalue { i8*, i32 } %2, 0 - store i8* %3, i8** %exn.slot, align 8 - %4 = extractvalue { i8*, i32 } %2, 1 - store i32 %4, i32* %ehselector.slot, align 4 - call void @onExcept(i32* %x) #18 - %5 = bitcast i32* %x to i8* - call void @llvm.lifetime.end.p0i8(i64 8, i8* %5) + %1 = extractvalue { ptr, i32 } %0, 0 + store ptr %1, ptr %exn.slot, align 8 + %2 = extractvalue { ptr, i32 } %0, 1 + store i32 %2, ptr %ehselector.slot, align 4 + call void @onExcept(ptr %x) #18 + call void @llvm.lifetime.end.p0(i64 8, ptr %x) br label %eh.resume eh.resume: ; preds = %lpad - %exn = load i8*, i8** %exn.slot, align 8 - %sel = load i32, i32* %ehselector.slot, align 4 - %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn, 0 - %lpad.val1 = insertvalue { i8*, i32 } %lpad.val, i32 %sel, 1 - resume { i8*, i32 } %lpad.val1 + %exn = load ptr, ptr %exn.slot, align 8 + %sel = load i32, ptr %ehselector.slot, align 4 + %lpad.val = insertvalue { ptr, i32 } undef, ptr %exn, 0 + %lpad.val1 = insertvalue { ptr, i32 } %lpad.val, i32 %sel, 1 + resume { ptr, i32 } %lpad.val1 } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/fuchsia.ll b/llvm/test/Instrumentation/HWAddressSanitizer/fuchsia.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/fuchsia.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/fuchsia.ll @@ -1,9 +1,9 @@ ; Check HWASan shadow mapping on Fuchsia. ; RUN: opt -passes=hwasan -S -mtriple=aarch64-unknown-fuchsia < %s | FileCheck %s -define i32 @test_load(i32* %a) sanitize_hwaddress { -; CHECK: %.hwasan.shadow = call i8* asm "", "=r,0"(i8* null) +define i32 @test_load(ptr %a) sanitize_hwaddress { +; CHECK: %.hwasan.shadow = call ptr asm "", "=r,0"(ptr null) entry: - %x = load i32, i32* %a, align 4 + %x = load i32, ptr %a, align 4 ret i32 %x } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/kernel-alloca.ll b/llvm/test/Instrumentation/HWAddressSanitizer/kernel-alloca.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/kernel-alloca.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/kernel-alloca.ll @@ -5,26 +5,25 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android" -declare void @use32(i32*) +declare void @use32(ptr) define void @test_alloca() sanitize_hwaddress { ; CHECK-LABEL: @test_alloca( -; CHECK: %[[FP:[^ ]*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %[[FP]] to i64 +; CHECK: %[[FP:[^ ]*]] = call ptr @llvm.frameaddress.p0(i32 0) +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %[[FP]] to i64 ; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 20 ; CHECK: %[[BASE_TAG:[^ ]*]] = xor i64 %[[A]], %[[B]] ; CHECK: %[[X:[^ ]*]] = alloca { i32, [12 x i8] }, align 16 -; CHECK: %[[X_BC:[^ ]*]] = bitcast { i32, [12 x i8] }* %[[X]] to i32* ; CHECK: %[[X_TAG:[^ ]*]] = xor i64 %[[BASE_TAG]], 0 -; CHECK: %[[X1:[^ ]*]] = ptrtoint i32* %[[X_BC]] to i64 +; CHECK: %[[X1:[^ ]*]] = ptrtoint ptr %[[X]] to i64 ; CHECK: %[[C:[^ ]*]] = shl i64 %[[X_TAG]], 56 ; CHECK: %[[D:[^ ]*]] = or i64 %[[C]], 72057594037927935 ; CHECK: %[[E:[^ ]*]] = and i64 %[[X1]], %[[D]] -; CHECK: %[[X_HWASAN:[^ ]*]] = inttoptr i64 %[[E]] to i32* +; CHECK: %[[X_HWASAN:[^ ]*]] = inttoptr i64 %[[E]] to ptr entry: %x = alloca i32, align 4 - call void @use32(i32* nonnull %x) + call void @use32(ptr nonnull %x) ret void } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/kernel-inline.ll b/llvm/test/Instrumentation/HWAddressSanitizer/kernel-inline.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/kernel-inline.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/kernel-inline.ll @@ -6,12 +6,12 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define void @test_load(i32* %a, i64* %b, i512* %c, i80* %d) sanitize_address { +define void @test_load(ptr %a, ptr %b, ptr %c, ptr %d) sanitize_address { entry: - %tmp1 = load i32, i32* %a, align 4 - %tmp2 = load i64, i64* %b, align 8 - %tmp3 = load i512, i512* %c, align 32 - %tmp4 = load i80, i80* %d, align 8 + %tmp1 = load i32, ptr %a, align 4 + %tmp2 = load i64, ptr %b, align 8 + %tmp3 = load i512, ptr %c, align 32 + %tmp4 = load i80, ptr %d, align 8 ret void } ; CHECK-INLINE: call void @__asan_report_load4_noabort diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/kernel.ll b/llvm/test/Instrumentation/HWAddressSanitizer/kernel.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/kernel.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/kernel.ll @@ -9,20 +9,20 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android" -define i8 @test_load(i8* %a) sanitize_hwaddress { +define i8 @test_load(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load( -; OFFSET: %[[SHADOW:[^ ]*]] = call i8* asm "", "=r,0"(i8* inttoptr (i64 12345678 to i8*)) -; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %a to i64 +; OFFSET: %[[SHADOW:[^ ]*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 12345678 to ptr)) +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; CHECK: %[[B:[^ ]*]] = lshr i64 %[[A]], 56 ; CHECK: %[[PTRTAG:[^ ]*]] = trunc i64 %[[B]] to i8 ; CHECK: %[[C:[^ ]*]] = or i64 %[[A]], -72057594037927936 ; CHECK: %[[D:[^ ]*]] = lshr i64 %[[C]], 4 -; NOOFFSET: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to i8* +; NOOFFSET: %[[E:[^ ]*]] = inttoptr i64 %[[D]] to ptr -; OFFSET: %[[E:[^ ]*]] = getelementptr i8, i8* %[[SHADOW]], i64 %[[D]] +; OFFSET: %[[E:[^ ]*]] = getelementptr i8, ptr %[[SHADOW]], i64 %[[D]] -; CHECK: %[[MEMTAG:[^ ]*]] = load i8, i8* %[[E]] +; CHECK: %[[MEMTAG:[^ ]*]] = load i8, ptr %[[E]] ; CHECK: %[[F:[^ ]*]] = icmp ne i8 %[[PTRTAG]], %[[MEMTAG]] ; MATCH-ALL: %[[G:[^ ]*]] = icmp ne i8 %[[PTRTAG]], -1 @@ -34,13 +34,13 @@ ; CHECK: call void asm sideeffect "brk #2336", "{x0}"(i64 %[[A]]) ; CHECK: br label -; CHECK: %[[G:[^ ]*]] = load i8, i8* %a, align 4 +; CHECK: %[[G:[^ ]*]] = load i8, ptr %a, align 4 ; CHECK: ret i8 %[[G]] -; OUTLINE: %[[SHADOW:[^ ]*]] = call i8* asm "", "=r,0"(i8* inttoptr (i64 12345678 to i8*)) -; OUTLINE: call void @llvm.hwasan.check.memaccess(i8* %[[SHADOW]], i8* %a, i32 67043360) +; OUTLINE: %[[SHADOW:[^ ]*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 12345678 to ptr)) +; OUTLINE: call void @llvm.hwasan.check.memaccess(ptr %[[SHADOW]], ptr %a, i32 67043360) entry: - %b = load i8, i8* %a, align 4 + %b = load i8, ptr %a, align 4 ret i8 %b } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/landingpad.ll b/llvm/test/Instrumentation/HWAddressSanitizer/landingpad.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/landingpad.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/landingpad.ll @@ -5,23 +5,23 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64-unknown-linux-android" -define i32 @f() local_unnamed_addr sanitize_hwaddress personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +define i32 @f() local_unnamed_addr sanitize_hwaddress personality ptr @__gxx_personality_v0 { entry: invoke void @g() to label %return unwind label %lpad lpad: - ; COMMON: landingpad { i8*, i32 } - ; COMMON-NEXT: catch i8* null - %0 = landingpad { i8*, i32 } - catch i8* null + ; COMMON: landingpad { ptr, i32 } + ; COMMON-NEXT: catch ptr null + %0 = landingpad { ptr, i32 } + catch ptr null ; NOLP-NOT: call void @__hwasan_handle_vfork ; LP-NEXT: %[[X:[^ ]*]] = call i64 @llvm.read_register.i64(metadata ![[META:[^ ]*]]) ; LP-NEXT: call void @__hwasan_handle_vfork(i64 %[[X]]) - %1 = extractvalue { i8*, i32 } %0, 0 - %2 = tail call i8* @__cxa_begin_catch(i8* %1) + %1 = extractvalue { ptr, i32 } %0, 0 + %2 = tail call ptr @__cxa_begin_catch(ptr %1) tail call void @__cxa_end_catch() br label %return return: @@ -32,7 +32,7 @@ declare void @g() local_unnamed_addr declare i32 @__gxx_personality_v0(...) -declare i8* @__cxa_begin_catch(i8*) local_unnamed_addr +declare ptr @__cxa_begin_catch(ptr) local_unnamed_addr declare void @__cxa_end_catch() local_unnamed_addr ; ARM: ![[META]] = !{!"sp"} diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/mem-intrinsics.ll b/llvm/test/Instrumentation/HWAddressSanitizer/mem-intrinsics.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/mem-intrinsics.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/mem-intrinsics.ll @@ -12,44 +12,39 @@ %retval = alloca i32, align 4 %Q = alloca [10 x i8], align 1 %P = alloca [10 x i8], align 1 - store i32 0, i32* %retval, align 4 - %arraydecay = getelementptr inbounds [10 x i8], [10 x i8]* %Q, i32 0, i32 0 + store i32 0, ptr %retval, align 4 - call void @llvm.memset.p0i8.i64(i8* align 1 %arraydecay, i8 0, i64 10, i1 false) -; CHECK-PREFIX: call i8* @__hwasan_memset -; CHECK-NOPREFIX: call i8* @memset + call void @llvm.memset.p0.i64(ptr align 1 %Q, i8 0, i64 10, i1 false) +; CHECK-PREFIX: call ptr @__hwasan_memset +; CHECK-NOPREFIX: call ptr @memset - %arraydecay1 = getelementptr inbounds [10 x i8], [10 x i8]* %Q, i32 0, i32 0 - %arraydecay2 = getelementptr inbounds [10 x i8], [10 x i8]* %Q, i32 0, i32 0 - %add.ptr = getelementptr inbounds i8, i8* %arraydecay2, i64 5 + %add.ptr = getelementptr inbounds i8, ptr %Q, i64 5 - call void @llvm.memmove.p0i8.p0i8.i64(i8* align 1 %arraydecay1, i8* align 1 %add.ptr, i64 5, i1 false) -; CHECK-PREFIX: call i8* @__hwasan_memmove -; CHECK-NOPREFIX: call i8* @memmove + call void @llvm.memmove.p0.p0.i64(ptr align 1 %Q, ptr align 1 %add.ptr, i64 5, i1 false) +; CHECK-PREFIX: call ptr @__hwasan_memmove +; CHECK-NOPREFIX: call ptr @memmove - %arraydecay3 = getelementptr inbounds [10 x i8], [10 x i8]* %P, i32 0, i32 0 - %arraydecay4 = getelementptr inbounds [10 x i8], [10 x i8]* %Q, i32 0, i32 0 - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 %arraydecay3, i8* align 1 %arraydecay4, i64 10, i1 false) -; CHECK-PREFIX: call i8* @__hwasan_memcpy -; CHECK-NOPREFIX: call i8* @memcpy + call void @llvm.memcpy.p0.p0.i64(ptr align 1 %P, ptr align 1 %Q, i64 10, i1 false) +; CHECK-PREFIX: call ptr @__hwasan_memcpy +; CHECK-NOPREFIX: call ptr @memcpy ret i32 0 } ; Function Attrs: argmemonly nounwind -declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1) #1 +declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1) #1 ; Function Attrs: argmemonly nounwind -declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) #1 +declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1) #1 ; Function Attrs: argmemonly nounwind -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) #1 +declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1) #1 -define void @memintr_test_nosanitize(i8* %a, i8* %b) nounwind uwtable { +define void @memintr_test_nosanitize(ptr %a, ptr %b) nounwind uwtable { entry: - tail call void @llvm.memset.p0i8.i64(i8* %a, i8 0, i64 100, i1 false) - tail call void @llvm.memmove.p0i8.p0i8.i64(i8* %a, i8* %b, i64 100, i1 false) - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 100, i1 false) + tail call void @llvm.memset.p0.i64(ptr %a, i8 0, i64 100, i1 false) + tail call void @llvm.memmove.p0.p0.i64(ptr %a, ptr %b, i64 100, i1 false) + tail call void @llvm.memcpy.p0.p0.i64(ptr %a, ptr %b, i64 100, i1 false) ret void } ; CHECK-LABEL: memintr_test_nosanitize diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/memaccess-clobber.ll b/llvm/test/Instrumentation/HWAddressSanitizer/memaccess-clobber.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/memaccess-clobber.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/memaccess-clobber.ll @@ -5,19 +5,19 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android10000" -declare void @use32(i32*) +declare void @use32(ptr) define i32 @test_alloca() sanitize_hwaddress { entry: %x = alloca i32, align 4 ; CHECK: call void @use32 - call void @use32(i32* nonnull %x) + call void @use32(ptr nonnull %x) ; CHECK: [[A:[0-9]+]] = MemoryDef({{[0-9]+}}) ; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules ; CHECK: MemoryUse([[A]]) - ; CHECK-NEXT: load i32, i32* %x.hwasan - %y = load i32, i32* %x + ; CHECK-NEXT: load i32, ptr %x.hwasan + %y = load i32, ptr %x ; CHECK: {{[0-9]+}} = MemoryDef([[A]]) - ; CHECK-NEXT: call void @llvm.memset.p0i8.i64 + ; CHECK-NEXT: call void @llvm.memset.p0.i64 ret i32 %y } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/musttail.ll b/llvm/test/Instrumentation/HWAddressSanitizer/musttail.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/musttail.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/musttail.ll @@ -8,23 +8,23 @@ define dso_local noundef i32 @_Z3bari(i32 noundef %0) sanitize_hwaddress { %2 = alloca i32, align 4 - store i32 %0, i32* %2, align 4 - %3 = load i32, i32* %2, align 4 + store i32 %0, ptr %2, align 4 + %3 = load i32, ptr %2, align 4 ret i32 %3 } define dso_local noundef i32 @_Z3fooi(i32 noundef %0) sanitize_hwaddress { %2 = alloca i32, align 4 %3 = alloca i32, align 4 - store i32 %0, i32* %2, align 4 - store volatile i32 5, i32* %3, align 4 - %4 = load i32, i32* %2, align 4 - %5 = load volatile i32, i32* %3, align 4 + store i32 %0, ptr %2, align 4 + store volatile i32 5, ptr %3, align 4 + %4 = load i32, ptr %2, align 4 + %5 = load volatile i32, ptr %3, align 4 %6 = add nsw i32 %4, %5 ; Check we untag before the musttail. - ; CHECK: call void @llvm.memset.p0i8.i64 + ; CHECK: call void @llvm.memset.p0.i64 ; CHECK: musttail call - ; CHECK-NOT: call void @llvm.memset.p0i8.i64 + ; CHECK-NOT: call void @llvm.memset.p0.i64 %7 = musttail call noundef i32 @_Z3bari(i32 noundef %6) ret i32 %7 } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/personality.ll b/llvm/test/Instrumentation/HWAddressSanitizer/personality.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/personality.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/personality.ll @@ -11,16 +11,16 @@ ; PERS: personality {{.*}} @__hwasan_personality_thunk define void @stack1() sanitize_hwaddress { %p = alloca i8 - call void @sink(i8* %p) + call void @sink(ptr %p) ret void } -; NOPERS: personality void ()* @global +; NOPERS: personality ptr @global ; PERS: personality {{.*}} @__hwasan_personality_thunk.global -define void @stack2() sanitize_hwaddress personality void ()* @global { +define void @stack2() sanitize_hwaddress personality ptr @global { %p = alloca i8 - call void @sink(i8* %p) + call void @sink(ptr %p) ret void } @@ -28,63 +28,63 @@ ret void } -@local_alias = internal alias void (), void ()* @local +@local_alias = internal alias void (), ptr @local -; NOPERS: personality void ()* @local +; NOPERS: personality ptr @local ; PERS: personality {{.*}} @__hwasan_personality_thunk.local -define void @stack3() sanitize_hwaddress personality void ()* @local { +define void @stack3() sanitize_hwaddress personality ptr @local { %p = alloca i8 - call void @sink(i8* %p) + call void @sink(ptr %p) ret void } -; NOPERS: personality void ()* @local_alias +; NOPERS: personality ptr @local_alias ; PERS: personality {{.*}} @__hwasan_personality_thunk.local_alias -define void @stack4() sanitize_hwaddress personality void ()* @local_alias { +define void @stack4() sanitize_hwaddress personality ptr @local_alias { %p = alloca i8 - call void @sink(i8* %p) + call void @sink(ptr %p) ret void } -; NOPERS: personality void ()* inttoptr (i64 1 to void ()*) -; PERS: personality i32 (i32, i32, i64, i8*, i8*)* @__hwasan_personality_thunk. -define void @stack5() sanitize_hwaddress personality void ()* inttoptr (i64 1 to void ()*) { +; NOPERS: personality ptr inttoptr (i64 1 to ptr) +; PERS: personality ptr @__hwasan_personality_thunk. +define void @stack5() sanitize_hwaddress personality ptr inttoptr (i64 1 to ptr) { %p = alloca i8 - call void @sink(i8* %p) + call void @sink(ptr %p) ret void } -; NOPERS: personality void ()* inttoptr (i64 2 to void ()*) -; PERS: personality i32 (i32, i32, i64, i8*, i8*)* @__hwasan_personality_thunk..1 -define void @stack6() sanitize_hwaddress personality void ()* inttoptr (i64 2 to void ()*) { +; NOPERS: personality ptr inttoptr (i64 2 to ptr) +; PERS: personality ptr @__hwasan_personality_thunk..1 +define void @stack6() sanitize_hwaddress personality ptr inttoptr (i64 2 to ptr) { %p = alloca i8 - call void @sink(i8* %p) + call void @sink(ptr %p) ret void } declare void @global() -declare void @sink(i8*) +declare void @sink(ptr) -; PERS: define linkonce_odr hidden i32 @__hwasan_personality_thunk(i32 %0, i32 %1, i64 %2, i8* %3, i8* %4) comdat -; PERS: %5 = tail call i32 @__hwasan_personality_wrapper(i32 %0, i32 %1, i64 %2, i8* %3, i8* %4, i8* null, i8* bitcast (void ()* @_Unwind_GetGR to i8*), i8* bitcast (void ()* @_Unwind_GetCFA to i8*)) +; PERS: define linkonce_odr hidden i32 @__hwasan_personality_thunk(i32 %0, i32 %1, i64 %2, ptr %3, ptr %4) comdat +; PERS: %5 = tail call i32 @__hwasan_personality_wrapper(i32 %0, i32 %1, i64 %2, ptr %3, ptr %4, ptr null, ptr @_Unwind_GetGR, ptr @_Unwind_GetCFA) ; PERS: ret i32 %5 -; PERS: define linkonce_odr hidden i32 @__hwasan_personality_thunk.global(i32 %0, i32 %1, i64 %2, i8* %3, i8* %4) comdat -; PERS: %5 = tail call i32 @__hwasan_personality_wrapper(i32 %0, i32 %1, i64 %2, i8* %3, i8* %4, i8* bitcast (void ()* @global to i8*), i8* bitcast (void ()* @_Unwind_GetGR to i8*), i8* bitcast (void ()* @_Unwind_GetCFA to i8*)) +; PERS: define linkonce_odr hidden i32 @__hwasan_personality_thunk.global(i32 %0, i32 %1, i64 %2, ptr %3, ptr %4) comdat +; PERS: %5 = tail call i32 @__hwasan_personality_wrapper(i32 %0, i32 %1, i64 %2, ptr %3, ptr %4, ptr @global, ptr @_Unwind_GetGR, ptr @_Unwind_GetCFA) ; PERS: ret i32 %5 -; PERS: define internal i32 @__hwasan_personality_thunk.local(i32 %0, i32 %1, i64 %2, i8* %3, i8* %4) -; PERS: %5 = tail call i32 @__hwasan_personality_wrapper(i32 %0, i32 %1, i64 %2, i8* %3, i8* %4, i8* bitcast (void ()* @local to i8*), i8* bitcast (void ()* @_Unwind_GetGR to i8*), i8* bitcast (void ()* @_Unwind_GetCFA to i8*)) +; PERS: define internal i32 @__hwasan_personality_thunk.local(i32 %0, i32 %1, i64 %2, ptr %3, ptr %4) +; PERS: %5 = tail call i32 @__hwasan_personality_wrapper(i32 %0, i32 %1, i64 %2, ptr %3, ptr %4, ptr @local, ptr @_Unwind_GetGR, ptr @_Unwind_GetCFA) ; PERS: ret i32 %5 -; PERS: define internal i32 @__hwasan_personality_thunk.local_alias(i32 %0, i32 %1, i64 %2, i8* %3, i8* %4) -; PERS: %5 = tail call i32 @__hwasan_personality_wrapper(i32 %0, i32 %1, i64 %2, i8* %3, i8* %4, i8* bitcast (void ()* @local_alias to i8*), i8* bitcast (void ()* @_Unwind_GetGR to i8*), i8* bitcast (void ()* @_Unwind_GetCFA to i8*)) +; PERS: define internal i32 @__hwasan_personality_thunk.local_alias(i32 %0, i32 %1, i64 %2, ptr %3, ptr %4) +; PERS: %5 = tail call i32 @__hwasan_personality_wrapper(i32 %0, i32 %1, i64 %2, ptr %3, ptr %4, ptr @local_alias, ptr @_Unwind_GetGR, ptr @_Unwind_GetCFA) ; PERS: ret i32 %5 -; PERS: define internal i32 @__hwasan_personality_thunk.(i32 %0, i32 %1, i64 %2, i8* %3, i8* %4) { -; PERS: %5 = tail call i32 @__hwasan_personality_wrapper(i32 %0, i32 %1, i64 %2, i8* %3, i8* %4, i8* inttoptr (i64 1 to i8*), i8* bitcast (void ()* @_Unwind_GetGR to i8*), i8* bitcast (void ()* @_Unwind_GetCFA to i8*)) +; PERS: define internal i32 @__hwasan_personality_thunk.(i32 %0, i32 %1, i64 %2, ptr %3, ptr %4) { +; PERS: %5 = tail call i32 @__hwasan_personality_wrapper(i32 %0, i32 %1, i64 %2, ptr %3, ptr %4, ptr inttoptr (i64 1 to ptr), ptr @_Unwind_GetGR, ptr @_Unwind_GetCFA) ; PERS: ret i32 %5 -; PERS: define internal i32 @__hwasan_personality_thunk..1(i32 %0, i32 %1, i64 %2, i8* %3, i8* %4) { -; PERS: %5 = tail call i32 @__hwasan_personality_wrapper(i32 %0, i32 %1, i64 %2, i8* %3, i8* %4, i8* inttoptr (i64 2 to i8*), i8* bitcast (void ()* @_Unwind_GetGR to i8*), i8* bitcast (void ()* @_Unwind_GetCFA to i8*)) +; PERS: define internal i32 @__hwasan_personality_thunk..1(i32 %0, i32 %1, i64 %2, ptr %3, ptr %4) { +; PERS: %5 = tail call i32 @__hwasan_personality_wrapper(i32 %0, i32 %1, i64 %2, ptr %3, ptr %4, ptr inttoptr (i64 2 to ptr), ptr @_Unwind_GetGR, ptr @_Unwind_GetCFA) ; PERS: ret i32 %5 diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll b/llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll @@ -21,18 +21,18 @@ ; CHECK-IFUNC: @__hwasan_shadow = external global [0 x i8] ; CHECK-NOIFUNC: @__hwasan_shadow_memory_dynamic_address = external global i64 -define i32 @test_load(i32* %a) sanitize_hwaddress { +define i32 @test_load(ptr %a) sanitize_hwaddress { ; First instrumentation in the function must be to load the dynamic shadow ; address into a local variable. ; CHECK-LABEL: @test_load ; CHECK: entry: -; CHECK-NOGLOBAL: %[[A:[^ ]*]] = call i8* asm "", "=r,0"([0 x i8]* @__hwasan_shadow) -; CHECK-NOGLOBAL: @llvm.hwasan.check.memaccess(i8* %[[A]] -; CHECK-ZERO-OFFSET: %[[A:[^ ]*]] = call i8* asm "", "=r,0"(i8* null) -; CHECK-SHORT-GRANULES: @llvm.hwasan.check.memaccess.shortgranules(i8* %[[A]] +; CHECK-NOGLOBAL: %[[A:[^ ]*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow) +; CHECK-NOGLOBAL: @llvm.hwasan.check.memaccess(ptr %[[A]] +; CHECK-ZERO-OFFSET: %[[A:[^ ]*]] = call ptr asm "", "=r,0"(ptr null) +; CHECK-SHORT-GRANULES: @llvm.hwasan.check.memaccess.shortgranules(ptr %[[A]] -; CHECK-GLOBAL: load i8*, i8** @__hwasan_shadow_memory_dynamic_address +; CHECK-GLOBAL: load ptr, ptr @__hwasan_shadow_memory_dynamic_address ; "store i64" is only used to update stack history (this input IR intentionally does not use any i64) ; W/o any allocas, the history is not updated, even if it is enabled explicitly with -hwasan-record-stack-history=1 @@ -41,11 +41,11 @@ ; CHECK: ret i32 entry: - %x = load i32, i32* %a, align 4 + %x = load i32, ptr %a, align 4 ret i32 %x } -declare void @use(i32* %p) +declare void @use(ptr %p) define void @test_alloca() sanitize_hwaddress { ; First instrumentation in the function must be to load the dynamic shadow @@ -53,37 +53,36 @@ ; CHECK-LABEL: @test_alloca ; CHECK: entry: -; CHECK-IFUNC: %[[A:[^ ]*]] = call i8* asm "", "=r,0"([0 x i8]* @__hwasan_shadow) -; CHECK-IFUNC: getelementptr i8, i8* %[[A]] +; CHECK-IFUNC: %[[A:[^ ]*]] = call ptr asm "", "=r,0"(ptr @__hwasan_shadow) +; CHECK-IFUNC: getelementptr i8, ptr %[[A]] -; CHECK-GLOBAL: load i8*, i8** @__hwasan_shadow_memory_dynamic_address +; CHECK-GLOBAL: load ptr, ptr @__hwasan_shadow_memory_dynamic_address -; CHECK-TLS-SLOT: %[[A:[^ ]*]] = call i8* @llvm.thread.pointer() -; CHECK-TLS-SLOT: %[[B:[^ ]*]] = getelementptr i8, i8* %[[A]], i32 48 -; CHECK-TLS-SLOT: %[[C:[^ ]*]] = bitcast i8* %[[B]] to i64* -; CHECK-TLS-SLOT: %[[D:[^ ]*]] = load i64, i64* %[[C]] +; CHECK-TLS-SLOT: %[[A:[^ ]*]] = call ptr @llvm.thread.pointer() +; CHECK-TLS-SLOT: %[[B:[^ ]*]] = getelementptr i8, ptr %[[A]], i32 48 +; CHECK-TLS-SLOT: %[[D:[^ ]*]] = load i64, ptr %[[B]] ; CHECK-TLS-SLOT: %[[E:[^ ]*]] = ashr i64 %[[D]], 3 -; CHECK-HWASAN-TLS: %[[D:[^ ]*]] = load i64, i64* @__hwasan_tls, align 8 +; CHECK-HWASAN-TLS: %[[D:[^ ]*]] = load i64, ptr @__hwasan_tls, align 8 ; CHECK-HWASAN-TLS: %[[E:[^ ]*]] = ashr i64 %[[D]], 3 ; CHECK-NOHISTORY-NOT: store i64 ; When watching stack history, all code paths attempt to get PC and SP and mix them together. ; CHECK-HISTORY: %[[PC:[^ ]*]] = call i64 @llvm.read_register.i64(metadata [[MD:![0-9]*]]) -; CHECK-HISTORY: %[[SP0:[^ ]*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; CHECK-HISTORY: %[[SP1:[^ ]*]] = ptrtoint i8* %[[SP0]] to i64 +; CHECK-HISTORY: %[[SP0:[^ ]*]] = call ptr @llvm.frameaddress.p0(i32 0) +; CHECK-HISTORY: %[[SP1:[^ ]*]] = ptrtoint ptr %[[SP0]] to i64 ; CHECK-HISTORY: %[[SP2:[^ ]*]] = shl i64 %[[SP1]], 44 ; CHECK-HISTORY: %[[MIX:[^ ]*]] = or i64 %[[PC]], %[[SP2]] -; CHECK-HISTORY-TLS: %[[PTR:[^ ]*]] = inttoptr i64 %[[D]] to i64* -; CHECK-HISTORY-TLS: store i64 %[[MIX]], i64* %[[PTR]] +; CHECK-HISTORY-TLS: %[[PTR:[^ ]*]] = inttoptr i64 %[[D]] to ptr +; CHECK-HISTORY-TLS: store i64 %[[MIX]], ptr %[[PTR]] ; CHECK-HISTORY-TLS: %[[D1:[^ ]*]] = ashr i64 %[[D]], 56 ; CHECK-HISTORY-TLS: %[[D2:[^ ]*]] = shl nuw nsw i64 %[[D1]], 12 ; CHECK-HISTORY-TLS: %[[D3:[^ ]*]] = xor i64 %[[D2]], -1 ; CHECK-HISTORY-TLS: %[[D4:[^ ]*]] = add i64 %[[D]], 8 ; CHECK-HISTORY-TLS: %[[D5:[^ ]*]] = and i64 %[[D4]], %[[D3]] -; CHECK-HISTORY-TLS-SLOT: store i64 %[[D5]], i64* %[[C]] -; CHECK-HISTORY-HWASAN-TLS: store i64 %[[D5]], i64* @__hwasan_tls +; CHECK-HISTORY-TLS-SLOT: store i64 %[[D5]], ptr %[[B]] +; CHECK-HISTORY-HWASAN-TLS: store i64 %[[D5]], ptr @__hwasan_tls ; CHECK-HISTORY-LIBCALL: call void @__hwasan_add_frame_record(i64 %[[MIX]]) ; CHECK-TLS: %[[F:[^ ]*]] = or i64 %[[D]], 4294967295 @@ -97,7 +96,7 @@ entry: %x = alloca i32, align 4 - call void @use(i32* %x) + call void @use(ptr %x) ret void } diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/stack-coloring.ll b/llvm/test/Instrumentation/HWAddressSanitizer/stack-coloring.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/stack-coloring.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/stack-coloring.ll @@ -18,26 +18,24 @@ define i32 @myCall_w2(i32 %in) sanitize_hwaddress { entry: - %a = alloca [17 x i8*], align 8 - %a2 = alloca [16 x i8*], align 8 - %b = bitcast [17 x i8*]* %a to i8* - %b2 = bitcast [16 x i8*]* %a2 to i8* - call void @llvm.lifetime.start.p0i8(i64 136, i8* %b) - %t1 = call i32 @foo(i32 %in, i8* %b) - %t2 = call i32 @foo(i32 %in, i8* %b) - call void @llvm.lifetime.end.p0i8(i64 136, i8* %b) - call void @llvm.lifetime.start.p0i8(i64 128, i8* %b2) - %t3 = call i32 @foo(i32 %in, i8* %b2) - %t4 = call i32 @foo(i32 %in, i8* %b2) - call void @llvm.lifetime.end.p0i8(i64 128, i8* %b2) + %a = alloca [17 x ptr], align 8 + %a2 = alloca [16 x ptr], align 8 + call void @llvm.lifetime.start.p0(i64 136, ptr %a) + %t1 = call i32 @foo(i32 %in, ptr %a) + %t2 = call i32 @foo(i32 %in, ptr %a) + call void @llvm.lifetime.end.p0(i64 136, ptr %a) + call void @llvm.lifetime.start.p0(i64 128, ptr %a2) + %t3 = call i32 @foo(i32 %in, ptr %a2) + %t4 = call i32 @foo(i32 %in, ptr %a2) + call void @llvm.lifetime.end.p0(i64 128, ptr %a2) %t5 = add i32 %t1, %t2 %t6 = add i32 %t3, %t4 %t7 = add i32 %t5, %t6 ret i32 %t7 } -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) nounwind +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) nounwind -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) nounwind +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) nounwind -declare i32 @foo(i32, i8*) +declare i32 @foo(i32, ptr) diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/stack-safety-analysis.ll b/llvm/test/Instrumentation/HWAddressSanitizer/stack-safety-analysis.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/stack-safety-analysis.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/stack-safety-analysis.ll @@ -7,7 +7,7 @@ target triple = "aarch64-unknown-linux-gnu" ; Check a safe alloca to ensure it does not get a tag. -define i32 @test_simple(i32* %a) sanitize_hwaddress { +define i32 @test_simple(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_simple ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -17,14 +17,14 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK-NOT: call {{.*}}__hwasan_store %buf.sroa.0 = alloca i8, align 4 - call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %buf.sroa.0) - store volatile i8 0, i8* %buf.sroa.0, align 4, !tbaa !8 - call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %buf.sroa.0) + call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %buf.sroa.0) + store volatile i8 0, ptr %buf.sroa.0, align 4, !tbaa !8 + call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %buf.sroa.0) ret i32 0 } ; Check a non-safe alloca to ensure it gets a tag. -define i32 @test_use(i32* %a) sanitize_hwaddress { +define i32 @test_use(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_use ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -34,15 +34,15 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK-NOT: call {{.*}}__hwasan_store %buf.sroa.0 = alloca i8, align 4 - call void @use(i8* nonnull %buf.sroa.0) - call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %buf.sroa.0) - store volatile i8 0, i8* %buf.sroa.0, align 4, !tbaa !8 - call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %buf.sroa.0) + call void @use(ptr nonnull %buf.sroa.0) + call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %buf.sroa.0) + store volatile i8 0, ptr %buf.sroa.0, align 4, !tbaa !8 + call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %buf.sroa.0) ret i32 0 } ; Check an alloca with in range GEP to ensure it does not get a tag or check. -define i32 @test_in_range(i32* %a) sanitize_hwaddress { +define i32 @test_in_range(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_in_range ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -52,15 +52,14 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK-NOT: call {{.*}}__hwasan_store %buf.sroa.0 = alloca [10 x i8], align 4 - %ptr = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 0 - call void @llvm.lifetime.start.p0i8(i64 10, i8* nonnull %ptr) - store volatile i8 0, i8* %ptr, align 4, !tbaa !8 - call void @llvm.lifetime.end.p0i8(i64 10, i8* nonnull %ptr) + call void @llvm.lifetime.start.p0(i64 10, ptr nonnull %buf.sroa.0) + store volatile i8 0, ptr %buf.sroa.0, align 4, !tbaa !8 + call void @llvm.lifetime.end.p0(i64 10, ptr nonnull %buf.sroa.0) ret i32 0 } ; Check an alloca with in range GEP to ensure it does not get a tag or check. -define i32 @test_in_range2(i32* %a) sanitize_hwaddress { +define i32 @test_in_range2(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_in_range2 ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -70,15 +69,14 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK-NOT: call {{.*}}__hwasan_store %buf.sroa.0 = alloca [10 x i8], align 4 - %ptr = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 9 - %x = bitcast [10 x i8]* %buf.sroa.0 to i8* - call void @llvm.lifetime.start.p0i8(i64 10, i8* nonnull %x) - store volatile i8 0, i8* %ptr, align 4, !tbaa !8 - call void @llvm.lifetime.end.p0i8(i64 10, i8* nonnull %x) + %ptr = getelementptr [10 x i8], ptr %buf.sroa.0, i32 0, i32 9 + call void @llvm.lifetime.start.p0(i64 10, ptr nonnull %buf.sroa.0) + store volatile i8 0, ptr %ptr, align 4, !tbaa !8 + call void @llvm.lifetime.end.p0(i64 10, ptr nonnull %buf.sroa.0) ret i32 0 } -define i32 @test_in_range3(i32* %a) sanitize_hwaddress { +define i32 @test_in_range3(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_in_range3 ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -88,13 +86,12 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK-NOT: call {{.*}}__hwasan_memset %buf.sroa.0 = alloca [10 x i8], align 4 - %ptr = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 9 - %x = bitcast [10 x i8]* %buf.sroa.0 to i8* - call void @llvm.memset.p0i8.i32(i8* %ptr, i8 0, i32 1, i1 true) + %ptr = getelementptr [10 x i8], ptr %buf.sroa.0, i32 0, i32 9 + call void @llvm.memset.p0.i32(ptr %ptr, i8 0, i32 1, i1 true) ret i32 0 } -define i32 @test_in_range4(i32* %a) sanitize_hwaddress { +define i32 @test_in_range4(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_in_range4 ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -104,13 +101,12 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK-NOT: call {{.*}}__hwasan_memmove %buf.sroa.0 = alloca [10 x i8], align 4 - %ptr = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 9 - %x = bitcast [10 x i8]* %buf.sroa.0 to i8* - call void @llvm.memmove.p0i8.p0i8.i32(i8* %ptr, i8* %ptr, i32 1, i1 true) + %ptr = getelementptr [10 x i8], ptr %buf.sroa.0, i32 0, i32 9 + call void @llvm.memmove.p0.p0.i32(ptr %ptr, ptr %ptr, i32 1, i1 true) ret i32 0 } -define i32 @test_in_range5(i32* %a) sanitize_hwaddress { +define i32 @test_in_range5(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_in_range5 ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -120,17 +116,15 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK-NOT: call {{.*}}__hwasan_memmove %buf.sroa.0 = alloca [10 x i8], align 4 - %ptr = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 9 - %x = bitcast [10 x i8]* %buf.sroa.0 to i8* + %ptr = getelementptr [10 x i8], ptr %buf.sroa.0, i32 0, i32 9 %buf.sroa.1 = alloca [10 x i8], align 4 - %ptr1 = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 9 - %y = bitcast [10 x i8]* %buf.sroa.1 to i8* - call void @llvm.memmove.p0i8.p0i8.i32(i8* %ptr, i8* %ptr1, i32 1, i1 true) + %ptr1 = getelementptr [10 x i8], ptr %buf.sroa.0, i32 0, i32 9 + call void @llvm.memmove.p0.p0.i32(ptr %ptr, ptr %ptr1, i32 1, i1 true) ret i32 0 } ; Check an alloca with out of range GEP to ensure it gets a tag and check. -define i32 @test_out_of_range(i32* %a) sanitize_hwaddress { +define i32 @test_out_of_range(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_out_of_range ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -140,15 +134,14 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK-NOT: call {{.*}}__hwasan_store %buf.sroa.0 = alloca [10 x i8], align 4 - %ptr = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 10 - %x = bitcast [10 x i8]* %buf.sroa.0 to i8* - call void @llvm.lifetime.start.p0i8(i64 10, i8* nonnull %x) - store volatile i8 0, i8* %ptr, align 4, !tbaa !8 - call void @llvm.lifetime.end.p0i8(i64 10, i8* nonnull %x) + %ptr = getelementptr [10 x i8], ptr %buf.sroa.0, i32 0, i32 10 + call void @llvm.lifetime.start.p0(i64 10, ptr nonnull %buf.sroa.0) + store volatile i8 0, ptr %ptr, align 4, !tbaa !8 + call void @llvm.lifetime.end.p0(i64 10, ptr nonnull %buf.sroa.0) ret i32 0 } -define i32 @test_out_of_range3(i32* %a) sanitize_hwaddress { +define i32 @test_out_of_range3(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_out_of_range3 ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -158,13 +151,12 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK-NOT: call {{.*}}__hwasan_memset %buf.sroa.0 = alloca [10 x i8], align 4 - %ptr = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 9 - %x = bitcast [10 x i8]* %buf.sroa.0 to i8* - call void @llvm.memset.p0i8.i32(i8* %ptr, i8 0, i32 2, i1 true) + %ptr = getelementptr [10 x i8], ptr %buf.sroa.0, i32 0, i32 9 + call void @llvm.memset.p0.i32(ptr %ptr, i8 0, i32 2, i1 true) ret i32 0 } -define i32 @test_out_of_range4(i32* %a) sanitize_hwaddress { +define i32 @test_out_of_range4(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_out_of_range4 ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -174,13 +166,12 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK-NOT: call {{.*}}__hwasan_memmove %buf.sroa.0 = alloca [10 x i8], align 4 - %ptr = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 9 - %x = bitcast [10 x i8]* %buf.sroa.0 to i8* - call void @llvm.memmove.p0i8.p0i8.i32(i8* %ptr, i8* %ptr, i32 2, i1 true) + %ptr = getelementptr [10 x i8], ptr %buf.sroa.0, i32 0, i32 9 + call void @llvm.memmove.p0.p0.i32(ptr %ptr, ptr %ptr, i32 2, i1 true) ret i32 0 } -define i32 @test_out_of_range5(i32* %a) sanitize_hwaddress { +define i32 @test_out_of_range5(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_out_of_range5 ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -190,22 +181,20 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK-NOT: call {{.*}}__hwasan_memmove %buf.sroa.0 = alloca [10 x i8], align 4 - %ptr = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 9 - %x = bitcast [10 x i8]* %buf.sroa.0 to i8* + %ptr = getelementptr [10 x i8], ptr %buf.sroa.0, i32 0, i32 9 %buf.sroa.1 = alloca [10 x i8], align 4 - %ptr1 = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 9 - %y = bitcast [10 x i8]* %buf.sroa.1 to i8* - call void @llvm.lifetime.start.p0i8(i64 10, i8* nonnull %x) - call void @llvm.lifetime.end.p0i8(i64 10, i8* nonnull %x) - call void @llvm.lifetime.start.p0i8(i64 10, i8* nonnull %y) - call void @llvm.memmove.p0i8.p0i8.i32(i8* %ptr, i8* %ptr1, i32 1, i1 true) - call void @llvm.lifetime.end.p0i8(i64 10, i8* nonnull %y) + %ptr1 = getelementptr [10 x i8], ptr %buf.sroa.0, i32 0, i32 9 + call void @llvm.lifetime.start.p0(i64 10, ptr nonnull %buf.sroa.0) + call void @llvm.lifetime.end.p0(i64 10, ptr nonnull %buf.sroa.0) + call void @llvm.lifetime.start.p0(i64 10, ptr nonnull %buf.sroa.1) + call void @llvm.memmove.p0.p0.i32(ptr %ptr, ptr %ptr1, i32 1, i1 true) + call void @llvm.lifetime.end.p0(i64 10, ptr nonnull %buf.sroa.1) ret i32 0 } ; Check an alloca with potentially out of range GEP to ensure it gets a tag and ; check. -define i32 @test_potentially_out_of_range(i32* %a) sanitize_hwaddress { +define i32 @test_potentially_out_of_range(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_potentially_out_of_range ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -216,14 +205,14 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_store %buf.sroa.0 = alloca [10 x i8], align 4 %off = call i32 @getoffset() - %ptr = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 %off - call void @llvm.lifetime.start.p0i8(i64 10, i8* nonnull %ptr) - store volatile i8 0, i8* %ptr, align 4, !tbaa !8 - call void @llvm.lifetime.end.p0i8(i64 10, i8* nonnull %ptr) + %ptr = getelementptr [10 x i8], ptr %buf.sroa.0, i32 0, i32 %off + call void @llvm.lifetime.start.p0(i64 10, ptr nonnull %ptr) + store volatile i8 0, ptr %ptr, align 4, !tbaa !8 + call void @llvm.lifetime.end.p0(i64 10, ptr nonnull %ptr) ret i32 0 } -define i32 @test_potentially_out_of_range2(i8* %a) sanitize_hwaddress { +define i32 @test_potentially_out_of_range2(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_potentially_out_of_range2 ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -233,14 +222,13 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK: call {{.*}}__hwasan_memmove %buf.sroa.0 = alloca [10 x i8], align 4 - %ptr = getelementptr [10 x i8], [10 x i8]* %buf.sroa.0, i32 0, i32 9 - %x = bitcast [10 x i8]* %buf.sroa.0 to i8* - call void @llvm.memmove.p0i8.p0i8.i32(i8* %ptr, i8* %a, i32 1, i1 true) + %ptr = getelementptr [10 x i8], ptr %buf.sroa.0, i32 0, i32 9 + call void @llvm.memmove.p0.p0.i32(ptr %ptr, ptr %a, i32 1, i1 true) ret i32 0 } ; Check an alloca with potentially out of range GEP to ensure it gets a tag and ; check. -define i32 @test_unclear(i32* %a) sanitize_hwaddress { +define i32 @test_unclear(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_unclear ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -250,14 +238,14 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK: call {{.*}}__hwasan_store %buf.sroa.0 = alloca i8, align 4 - %ptr = call i8* @getptr(i8* %buf.sroa.0) - call void @llvm.lifetime.start.p0i8(i64 10, i8* nonnull %ptr) - store volatile i8 0, i8* %ptr, align 4, !tbaa !8 - call void @llvm.lifetime.end.p0i8(i64 10, i8* nonnull %ptr) + %ptr = call ptr @getptr(ptr %buf.sroa.0) + call void @llvm.lifetime.start.p0(i64 10, ptr nonnull %ptr) + store volatile i8 0, ptr %ptr, align 4, !tbaa !8 + call void @llvm.lifetime.end.p0(i64 10, ptr nonnull %ptr) ret i32 0 } -define i32 @test_select(i8* %a) sanitize_hwaddress { +define i32 @test_select(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_select ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -266,18 +254,18 @@ ; SAFETY: call {{.*}}__hwasan_store ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK: call {{.*}}__hwasan_store - %x = call i8* @getptr(i8* %a) + %x = call ptr @getptr(ptr %a) %buf.sroa.0 = alloca i8, align 4 - call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %buf.sroa.0) + call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %buf.sroa.0) %c = call i1 @cond() - %ptr = select i1 %c, i8* %x, i8* %buf.sroa.0 - store volatile i8 0, i8* %ptr, align 4, !tbaa !8 - call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %buf.sroa.0) + %ptr = select i1 %c, ptr %x, ptr %buf.sroa.0 + store volatile i8 0, ptr %ptr, align 4, !tbaa !8 + call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %buf.sroa.0) ret i32 0 } ; Check whether we see through the returns attribute of functions. -define i32 @test_retptr(i32* %a) sanitize_hwaddress { +define i32 @test_retptr(ptr %a) sanitize_hwaddress { entry: ; CHECK-LABEL: @test_retptr ; NOSAFETY: call {{.*}}__hwasan_generate_tag @@ -287,28 +275,28 @@ ; NOSTACK-NOT: call {{.*}}__hwasan_generate_tag ; NOSTACK-NOT: call {{.*}}__hwasan_store %buf.sroa.0 = alloca i8, align 4 - call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %buf.sroa.0) - %ptr = call i8* @retptr(i8* %buf.sroa.0) - store volatile i8 0, i8* %ptr, align 4, !tbaa !8 - call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %buf.sroa.0) + call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %buf.sroa.0) + %ptr = call ptr @retptr(ptr %buf.sroa.0) + store volatile i8 0, ptr %ptr, align 4, !tbaa !8 + call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %buf.sroa.0) ret i32 0 } ; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn -declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) ; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn -declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) -declare void @llvm.memset.p0i8.i32(i8*, i8, i32, i1) -declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i1) -declare void @llvm.memmove.p0i8.p0i8.i32(i8*, i8*, i32, i1) +declare void @llvm.memset.p0.i32(ptr, i8, i32, i1) +declare void @llvm.memcpy.p0.p0.i32(ptr, ptr, i32, i1) +declare void @llvm.memmove.p0.p0.i32(ptr, ptr, i32, i1) declare i1 @cond() -declare void @use(i8* nocapture) +declare void @use(ptr nocapture) declare i32 @getoffset() -declare i8* @getptr(i8* nocapture) -declare i8* @retptr(i8* returned) +declare ptr @getptr(ptr nocapture) +declare ptr @retptr(ptr returned) !8 = !{!9, !9, i64 0} !9 = !{!"omnipotent char", !10, i64 0} diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope-setjmp.ll b/llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope-setjmp.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope-setjmp.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope-setjmp.ll @@ -2,7 +2,7 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64-unknown-linux-android29" -@stackbuf = dso_local local_unnamed_addr global i8* null, align 8 +@stackbuf = dso_local local_unnamed_addr global ptr null, align 8 @jbuf = dso_local global [32 x i64] zeroinitializer, align 8 declare void @may_jump() @@ -10,7 +10,7 @@ define dso_local noundef i1 @_Z6targetv() sanitize_hwaddress { entry: %buf = alloca [4096 x i8], align 1 - %call = call i32 @setjmp(i64* noundef getelementptr inbounds ([32 x i64], [32 x i64]* @jbuf, i64 0, i64 0)) + %call = call i32 @setjmp(ptr noundef @jbuf) switch i32 %call, label %while.body [ i32 1, label %return i32 2, label %sw.bb1 @@ -20,24 +20,23 @@ br label %return while.body: ; preds = %entry - %0 = getelementptr inbounds [4096 x i8], [4096 x i8]* %buf, i64 0, i64 0 - call void @llvm.lifetime.start.p0i8(i64 4096, i8* nonnull %0) #10 - store i8* %0, i8** @stackbuf, align 8 + call void @llvm.lifetime.start.p0(i64 4096, ptr nonnull %buf) #10 + store ptr %buf, ptr @stackbuf, align 8 ; may_jump may call longjmp, going back to the switch (and then the return), ; bypassing the lifetime.end. This is why we need to untag on the return, ; rather than the lifetime.end. call void @may_jump() - call void @llvm.lifetime.end.p0i8(i64 4096, i8* nonnull %0) #10 + call void @llvm.lifetime.end.p0(i64 4096, ptr nonnull %buf) #10 br label %return ; CHECK-LABEL: return: -; CHECK: void @llvm.memset.p0i8.i64({{.*}}, i8 0, i64 256, i1 false) +; CHECK: void @llvm.memset.p0.i64({{.*}}, i8 0, i64 256, i1 false) return: ; preds = %entry, %while.body, %sw.bb1 %retval.0 = phi i1 [ true, %while.body ], [ true, %sw.bb1 ], [ false, %entry ] ret i1 %retval.0 } -declare i32 @setjmp(i64* noundef) returns_twice +declare i32 @setjmp(ptr noundef) returns_twice -declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) -declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll b/llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/use-after-scope.ll @@ -24,245 +24,235 @@ define dso_local i32 @standard_lifetime() local_unnamed_addr sanitize_hwaddress { ; X86-SCOPE-LABEL: @standard_lifetime( -; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call i8* asm "", "=r,0"(i8* null) +; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-SCOPE-NEXT: [[TMP1:%.*]] = alloca { i8, [15 x i8] }, align 16 -; X86-SCOPE-NEXT: [[TMP2:%.*]] = bitcast { i8, [15 x i8] }* [[TMP1]] to i8* -; X86-SCOPE-NEXT: [[TMP3:%.*]] = call i8 @__hwasan_generate_tag() -; X86-SCOPE-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 -; X86-SCOPE-NEXT: [[TMP5:%.*]] = ptrtoint i8* [[TMP2]] to i64 -; X86-SCOPE-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 57 -; X86-SCOPE-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]] -; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to i8* -; X86-SCOPE-NEXT: br label [[TMP8:%.*]] -; X86-SCOPE: 8: -; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull [[TMP2]]) -; X86-SCOPE-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP4]] to i8 -; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 [[TMP9]], i64 16) -; X86-SCOPE-NEXT: [[TMP10:%.*]] = tail call i1 (...) @cond() -; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 0, i64 16) -; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull [[TMP2]]) -; X86-SCOPE-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP8]] -; X86-SCOPE: 11: -; X86-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) +; X86-SCOPE-NEXT: [[TMP2:%.*]] = call i8 @__hwasan_generate_tag() +; X86-SCOPE-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 +; X86-SCOPE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; X86-SCOPE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 57 +; X86-SCOPE-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]] +; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr +; X86-SCOPE-NEXT: br label [[TMP7:%.*]] +; X86-SCOPE: 7: +; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP1]]) +; X86-SCOPE-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP3]] to i8 +; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 [[TMP8]], i64 16) +; X86-SCOPE-NEXT: [[TMP9:%.*]] = tail call i1 (...) @cond() +; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 0, i64 16) +; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP1]]) +; X86-SCOPE-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP7]] +; X86-SCOPE: 10: +; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-SCOPE-NEXT: ret i32 0 ; ; X86-NOSCOPE-LABEL: @standard_lifetime( -; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call i8* asm "", "=r,0"(i8* null) +; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = alloca { i8, [15 x i8] }, align 16 -; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = bitcast { i8, [15 x i8] }* [[TMP1]] to i8* -; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = call i8 @__hwasan_generate_tag() -; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 -; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = ptrtoint i8* [[TMP2]] to i64 -; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 57 -; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]] -; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to i8* -; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP4]] to i8 -; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 [[TMP8]], i64 16) -; X86-NOSCOPE-NEXT: br label [[TMP9:%.*]] -; X86-NOSCOPE: 9: -; X86-NOSCOPE-NEXT: [[TMP10:%.*]] = tail call i1 (...) @cond() -; X86-NOSCOPE-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP9]] -; X86-NOSCOPE: 11: -; X86-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 0, i64 16) +; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = call i8 @__hwasan_generate_tag() +; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 +; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 57 +; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]] +; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr +; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8 +; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 [[TMP7]], i64 16) +; X86-NOSCOPE-NEXT: br label [[TMP8:%.*]] +; X86-NOSCOPE: 8: +; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = tail call i1 (...) @cond() +; X86-NOSCOPE-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP8]] +; X86-NOSCOPE: 10: +; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 0, i64 16) ; X86-NOSCOPE-NEXT: ret i32 0 ; ; AARCH64-SCOPE-LABEL: @standard_lifetime( -; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) -; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SCOPE-NEXT: br label [[TMP26:%.*]] -; AARCH64-SCOPE: 26: -; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP29:%.*]] = lshr i64 [[TMP28]], 4 -; AARCH64-SCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP29]] -; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP30]], i8 [[TMP27]], i64 1, i1 false) -; AARCH64-SCOPE-NEXT: [[TMP31:%.*]] = tail call i1 (...) @cond() -; AARCH64-SCOPE-NEXT: [[TMP32:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4 -; AARCH64-SCOPE-NEXT: [[TMP34:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP33]] -; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP34]], i8 0, i64 1, i1 false) -; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SCOPE-NEXT: br i1 [[TMP31]], label [[TMP35:%.*]], label [[TMP26]] -; AARCH64-SCOPE: 35: -; AARCH64-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) +; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SCOPE-NEXT: br label [[TMP24:%.*]] +; AARCH64-SCOPE: 24: +; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP26]], 4 +; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP27]] +; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP28]], i8 [[TMP25]], i64 1, i1 false) +; AARCH64-SCOPE-NEXT: [[TMP29:%.*]] = tail call i1 (...) @cond() +; AARCH64-SCOPE-NEXT: [[TMP30:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 4 +; AARCH64-SCOPE-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP31]] +; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP32]], i8 0, i64 1, i1 false) +; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SCOPE-NEXT: br i1 [[TMP29]], label [[TMP33:%.*]], label [[TMP24]] +; AARCH64-SCOPE: 33: +; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SCOPE-NEXT: ret i32 0 ; ; AARCH64-NOSCOPE-LABEL: @standard_lifetime( -; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) -; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-NOSCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-NOSCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP29]], i8 [[TMP26]], i64 1, i1 false) -; AARCH64-NOSCOPE-NEXT: br label [[TMP30:%.*]] +; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) +; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP27]], i8 [[TMP24]], i64 1, i1 false) +; AARCH64-NOSCOPE-NEXT: br label [[TMP28:%.*]] +; AARCH64-NOSCOPE: 28: +; AARCH64-NOSCOPE-NEXT: [[TMP29:%.*]] = tail call i1 (...) @cond() +; AARCH64-NOSCOPE-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP28]] ; AARCH64-NOSCOPE: 30: -; AARCH64-NOSCOPE-NEXT: [[TMP31:%.*]] = tail call i1 (...) @cond() -; AARCH64-NOSCOPE-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP30]] -; AARCH64-NOSCOPE: 32: -; AARCH64-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-NOSCOPE-NEXT: [[TMP33:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP34:%.*]] = lshr i64 [[TMP33]], 4 -; AARCH64-NOSCOPE-NEXT: [[TMP35:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP34]] -; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP35]], i8 0, i64 1, i1 false) +; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-NOSCOPE-NEXT: [[TMP31:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP32:%.*]] = lshr i64 [[TMP31]], 4 +; AARCH64-NOSCOPE-NEXT: [[TMP33:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP32]] +; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP33]], i8 0, i64 1, i1 false) ; AARCH64-NOSCOPE-NEXT: ret i32 0 ; ; AARCH64-SHORT-SCOPE-LABEL: @standard_lifetime( -; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP26:%.*]] -; AARCH64-SHORT-SCOPE: 26: -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = lshr i64 [[TMP28]], 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP29]] -; AARCH64-SHORT-SCOPE-NEXT: [[TMP31:%.*]] = getelementptr i8, i8* [[TMP30]], i32 0 -; AARCH64-SHORT-SCOPE-NEXT: store i8 1, i8* [[TMP31]], align 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP32:%.*]] = getelementptr i8, i8* [[TMP20]], i32 15 -; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP27]], i8* [[TMP32]], align 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP33:%.*]] = tail call i1 (...) @cond() -; AARCH64-SHORT-SCOPE-NEXT: [[TMP34:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP35:%.*]] = lshr i64 [[TMP34]], 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP36:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP35]] -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP36]], i8 0, i64 1, i1 false) -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP33]], label [[TMP37:%.*]], label [[TMP26]] -; AARCH64-SHORT-SCOPE: 37: -; AARCH64-SHORT-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP24:%.*]] +; AARCH64-SHORT-SCOPE: 24: +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP26]], 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP27]] +; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP28]], i32 0 +; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP29]], align 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 +; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP25]], ptr [[TMP30]], align 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP31:%.*]] = tail call i1 (...) @cond() +; AARCH64-SHORT-SCOPE-NEXT: [[TMP32:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP34:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP33]] +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP34]], i8 0, i64 1, i1 false) +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP31]], label [[TMP35:%.*]], label [[TMP24]] +; AARCH64-SHORT-SCOPE: 35: +; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-SCOPE-NEXT: ret i32 0 ; ; AARCH64-SHORT-NOSCOPE-LABEL: @standard_lifetime( -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, i8* [[TMP29]], i32 0 -; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, i8* [[TMP30]], align 1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP31:%.*]] = getelementptr i8, i8* [[TMP20]], i32 15 -; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP26]], i8* [[TMP31]], align 1 -; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP32:%.*]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP27]], i32 0 +; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP28]], align 1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 +; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP24]], ptr [[TMP29]], align 1 +; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP30:%.*]] +; AARCH64-SHORT-NOSCOPE: 30: +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP31:%.*]] = tail call i1 (...) @cond() +; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP30]] ; AARCH64-SHORT-NOSCOPE: 32: -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP33:%.*]] = tail call i1 (...) @cond() -; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP33]], label [[TMP34:%.*]], label [[TMP32]] -; AARCH64-SHORT-NOSCOPE: 34: -; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP35:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP36:%.*]] = lshr i64 [[TMP35]], 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP37:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP36]] -; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP37]], i8 0, i64 1, i1 false) +; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP34:%.*]] = lshr i64 [[TMP33]], 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP35:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP34]] +; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP35]], i8 0, i64 1, i1 false) ; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0 ; %1 = alloca i8, align 1 @@ -270,258 +260,248 @@ 2: ; preds = %2, %0 ; We should tag the memory after the br (in the loop). - call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %1) + call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1) %3 = tail call i1 (...) @cond() #2 ; We should tag the memory before the next br (before the jump back). - call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %1) + call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1) br i1 %3, label %4, label %2 4: ; preds = %2 - call void @use(i8* nonnull %1) #2 + call void @use(ptr nonnull %1) #2 ret i32 0 } define dso_local i32 @standard_lifetime_optnone() local_unnamed_addr optnone noinline sanitize_hwaddress { ; X86-SCOPE-LABEL: @standard_lifetime_optnone( -; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call i8* asm "", "=r,0"(i8* null) +; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-SCOPE-NEXT: [[TMP1:%.*]] = alloca { i8, [15 x i8] }, align 16 -; X86-SCOPE-NEXT: [[TMP2:%.*]] = bitcast { i8, [15 x i8] }* [[TMP1]] to i8* -; X86-SCOPE-NEXT: [[TMP3:%.*]] = call i8 @__hwasan_generate_tag() -; X86-SCOPE-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 -; X86-SCOPE-NEXT: [[TMP5:%.*]] = ptrtoint i8* [[TMP2]] to i64 -; X86-SCOPE-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 57 -; X86-SCOPE-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]] -; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to i8* -; X86-SCOPE-NEXT: br label [[TMP8:%.*]] -; X86-SCOPE: 8: -; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull [[TMP2]]) -; X86-SCOPE-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP4]] to i8 -; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 [[TMP9]], i64 16) -; X86-SCOPE-NEXT: [[TMP10:%.*]] = tail call i1 (...) @cond() -; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 0, i64 16) -; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull [[TMP2]]) -; X86-SCOPE-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP8]] -; X86-SCOPE: 11: -; X86-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) +; X86-SCOPE-NEXT: [[TMP2:%.*]] = call i8 @__hwasan_generate_tag() +; X86-SCOPE-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 +; X86-SCOPE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; X86-SCOPE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 57 +; X86-SCOPE-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]] +; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr +; X86-SCOPE-NEXT: br label [[TMP7:%.*]] +; X86-SCOPE: 7: +; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP1]]) +; X86-SCOPE-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP3]] to i8 +; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 [[TMP8]], i64 16) +; X86-SCOPE-NEXT: [[TMP9:%.*]] = tail call i1 (...) @cond() +; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 0, i64 16) +; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP1]]) +; X86-SCOPE-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP7]] +; X86-SCOPE: 10: +; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; X86-SCOPE-NEXT: ret i32 0 ; ; X86-NOSCOPE-LABEL: @standard_lifetime_optnone( -; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call i8* asm "", "=r,0"(i8* null) +; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = alloca { i8, [15 x i8] }, align 16 -; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = bitcast { i8, [15 x i8] }* [[TMP1]] to i8* -; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = call i8 @__hwasan_generate_tag() -; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 -; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = ptrtoint i8* [[TMP2]] to i64 -; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 57 -; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]] -; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to i8* -; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP4]] to i8 -; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 [[TMP8]], i64 16) -; X86-NOSCOPE-NEXT: br label [[TMP9:%.*]] -; X86-NOSCOPE: 9: -; X86-NOSCOPE-NEXT: [[TMP10:%.*]] = tail call i1 (...) @cond() -; X86-NOSCOPE-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP9]] -; X86-NOSCOPE: 11: -; X86-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 0, i64 16) +; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = call i8 @__hwasan_generate_tag() +; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 +; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 57 +; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]] +; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr +; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8 +; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 [[TMP7]], i64 16) +; X86-NOSCOPE-NEXT: br label [[TMP8:%.*]] +; X86-NOSCOPE: 8: +; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = tail call i1 (...) @cond() +; X86-NOSCOPE-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP8]] +; X86-NOSCOPE: 10: +; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 0, i64 16) ; X86-NOSCOPE-NEXT: ret i32 0 ; ; AARCH64-SCOPE-LABEL: @standard_lifetime_optnone( -; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SCOPE-NEXT: br label [[TMP26:%.*]] -; AARCH64-SCOPE: 26: -; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP29:%.*]] = lshr i64 [[TMP28]], 4 -; AARCH64-SCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP29]] -; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP30]], i8 [[TMP27]], i64 1, i1 false) -; AARCH64-SCOPE-NEXT: [[TMP31:%.*]] = tail call i1 (...) @cond() -; AARCH64-SCOPE-NEXT: [[TMP32:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4 -; AARCH64-SCOPE-NEXT: [[TMP34:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP33]] -; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP34]], i8 0, i64 1, i1 false) -; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SCOPE-NEXT: br i1 [[TMP31]], label [[TMP35:%.*]], label [[TMP26]] -; AARCH64-SCOPE: 35: -; AARCH64-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SCOPE-NEXT: br label [[TMP24:%.*]] +; AARCH64-SCOPE: 24: +; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP26]], 4 +; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP27]] +; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP28]], i8 [[TMP25]], i64 1, i1 false) +; AARCH64-SCOPE-NEXT: [[TMP29:%.*]] = tail call i1 (...) @cond() +; AARCH64-SCOPE-NEXT: [[TMP30:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 4 +; AARCH64-SCOPE-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP31]] +; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP32]], i8 0, i64 1, i1 false) +; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SCOPE-NEXT: br i1 [[TMP29]], label [[TMP33:%.*]], label [[TMP24]] +; AARCH64-SCOPE: 33: +; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SCOPE-NEXT: ret i32 0 ; ; AARCH64-NOSCOPE-LABEL: @standard_lifetime_optnone( -; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-NOSCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-NOSCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP29]], i8 [[TMP26]], i64 1, i1 false) -; AARCH64-NOSCOPE-NEXT: br label [[TMP30:%.*]] +; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP27]], i8 [[TMP24]], i64 1, i1 false) +; AARCH64-NOSCOPE-NEXT: br label [[TMP28:%.*]] +; AARCH64-NOSCOPE: 28: +; AARCH64-NOSCOPE-NEXT: [[TMP29:%.*]] = tail call i1 (...) @cond() +; AARCH64-NOSCOPE-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP28]] ; AARCH64-NOSCOPE: 30: -; AARCH64-NOSCOPE-NEXT: [[TMP31:%.*]] = tail call i1 (...) @cond() -; AARCH64-NOSCOPE-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP30]] -; AARCH64-NOSCOPE: 32: -; AARCH64-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-NOSCOPE-NEXT: [[TMP33:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP34:%.*]] = lshr i64 [[TMP33]], 4 -; AARCH64-NOSCOPE-NEXT: [[TMP35:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP34]] -; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP35]], i8 0, i64 1, i1 false) +; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-NOSCOPE-NEXT: [[TMP31:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP32:%.*]] = lshr i64 [[TMP31]], 4 +; AARCH64-NOSCOPE-NEXT: [[TMP33:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP32]] +; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP33]], i8 0, i64 1, i1 false) ; AARCH64-NOSCOPE-NEXT: ret i32 0 ; ; AARCH64-SHORT-SCOPE-LABEL: @standard_lifetime_optnone( -; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP26:%.*]] -; AARCH64-SHORT-SCOPE: 26: -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = lshr i64 [[TMP28]], 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP29]] -; AARCH64-SHORT-SCOPE-NEXT: [[TMP31:%.*]] = getelementptr i8, i8* [[TMP30]], i32 0 -; AARCH64-SHORT-SCOPE-NEXT: store i8 1, i8* [[TMP31]], align 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP32:%.*]] = getelementptr i8, i8* [[TMP20]], i32 15 -; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP27]], i8* [[TMP32]], align 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP33:%.*]] = tail call i1 (...) @cond() -; AARCH64-SHORT-SCOPE-NEXT: [[TMP34:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP35:%.*]] = lshr i64 [[TMP34]], 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP36:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP35]] -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP36]], i8 0, i64 1, i1 false) -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP33]], label [[TMP37:%.*]], label [[TMP26]] -; AARCH64-SHORT-SCOPE: 37: -; AARCH64-SHORT-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP24:%.*]] +; AARCH64-SHORT-SCOPE: 24: +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = lshr i64 [[TMP26]], 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP27]] +; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP28]], i32 0 +; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP29]], align 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 +; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP25]], ptr [[TMP30]], align 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP31:%.*]] = tail call i1 (...) @cond() +; AARCH64-SHORT-SCOPE-NEXT: [[TMP32:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP34:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP33]] +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP34]], i8 0, i64 1, i1 false) +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP31]], label [[TMP35:%.*]], label [[TMP24]] +; AARCH64-SHORT-SCOPE: 35: +; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) ; AARCH64-SHORT-SCOPE-NEXT: ret i32 0 ; ; AARCH64-SHORT-NOSCOPE-LABEL: @standard_lifetime_optnone( -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, i8* [[TMP29]], i32 0 -; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, i8* [[TMP30]], align 1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP31:%.*]] = getelementptr i8, i8* [[TMP20]], i32 15 -; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP26]], i8* [[TMP31]], align 1 -; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP32:%.*]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP27]], i32 0 +; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP28]], align 1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 +; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP24]], ptr [[TMP29]], align 1 +; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP30:%.*]] +; AARCH64-SHORT-NOSCOPE: 30: +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP31:%.*]] = tail call i1 (...) @cond() +; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP31]], label [[TMP32:%.*]], label [[TMP30]] ; AARCH64-SHORT-NOSCOPE: 32: -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP33:%.*]] = tail call i1 (...) @cond() -; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP33]], label [[TMP34:%.*]], label [[TMP32]] -; AARCH64-SHORT-NOSCOPE: 34: -; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP35:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP36:%.*]] = lshr i64 [[TMP35]], 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP37:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP36]] -; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP37]], i8 0, i64 1, i1 false) +; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP33:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP34:%.*]] = lshr i64 [[TMP33]], 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP35:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP34]] +; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP35]], i8 0, i64 1, i1 false) ; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0 ; %1 = alloca i8, align 1 @@ -529,508 +509,488 @@ 2: ; preds = %2, %0 ; We should tag the memory after the br (in the loop). - call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %1) + call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1) %3 = tail call i1 (...) @cond() #2 ; We should tag the memory before the next br (before the jump back). - call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %1) + call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1) br i1 %3, label %4, label %2 4: ; preds = %2 - call void @use(i8* nonnull %1) #2 + call void @use(ptr nonnull %1) #2 ret i32 0 } define dso_local i32 @multiple_lifetimes() local_unnamed_addr sanitize_hwaddress { ; X86-SCOPE-LABEL: @multiple_lifetimes( -; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call i8* asm "", "=r,0"(i8* null) +; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-SCOPE-NEXT: [[TMP1:%.*]] = alloca { i8, [15 x i8] }, align 16 -; X86-SCOPE-NEXT: [[TMP2:%.*]] = bitcast { i8, [15 x i8] }* [[TMP1]] to i8* -; X86-SCOPE-NEXT: [[TMP3:%.*]] = call i8 @__hwasan_generate_tag() -; X86-SCOPE-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 -; X86-SCOPE-NEXT: [[TMP5:%.*]] = ptrtoint i8* [[TMP2]] to i64 -; X86-SCOPE-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 57 -; X86-SCOPE-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]] -; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to i8* -; X86-SCOPE-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP4]] to i8 -; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 [[TMP8]], i64 16) -; X86-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; X86-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 0, i64 16) +; X86-SCOPE-NEXT: [[TMP2:%.*]] = call i8 @__hwasan_generate_tag() +; X86-SCOPE-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 +; X86-SCOPE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; X86-SCOPE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 57 +; X86-SCOPE-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]] +; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr +; X86-SCOPE-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8 +; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 [[TMP7]], i64 16) +; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 0, i64 16) ; X86-SCOPE-NEXT: ret i32 0 ; ; X86-NOSCOPE-LABEL: @multiple_lifetimes( -; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call i8* asm "", "=r,0"(i8* null) +; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = alloca { i8, [15 x i8] }, align 16 -; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = bitcast { i8, [15 x i8] }* [[TMP1]] to i8* -; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = call i8 @__hwasan_generate_tag() -; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 -; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = ptrtoint i8* [[TMP2]] to i64 -; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 57 -; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]] -; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to i8* -; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP4]] to i8 -; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 [[TMP8]], i64 16) -; X86-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; X86-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 0, i64 16) +; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = call i8 @__hwasan_generate_tag() +; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 +; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 57 +; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]] +; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr +; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8 +; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 [[TMP7]], i64 16) +; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 0, i64 16) ; X86-NOSCOPE-NEXT: ret i32 0 ; ; AARCH64-SCOPE-LABEL: @multiple_lifetimes( -; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-SCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP29]], i8 [[TMP26]], i64 1, i1 false) -; AARCH64-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SCOPE-NEXT: [[TMP30:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 4 -; AARCH64-SCOPE-NEXT: [[TMP32:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP31]] -; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP32]], i8 0, i64 1, i1 false) +; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP27]], i8 [[TMP24]], i64 1, i1 false) +; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP29:%.*]] = lshr i64 [[TMP28]], 4 +; AARCH64-SCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP29]] +; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP30]], i8 0, i64 1, i1 false) ; AARCH64-SCOPE-NEXT: ret i32 0 ; ; AARCH64-NOSCOPE-LABEL: @multiple_lifetimes( -; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-NOSCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-NOSCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP29]], i8 [[TMP26]], i64 1, i1 false) -; AARCH64-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-NOSCOPE-NEXT: [[TMP30:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 4 -; AARCH64-NOSCOPE-NEXT: [[TMP32:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP31]] -; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP32]], i8 0, i64 1, i1 false) +; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP27]], i8 [[TMP24]], i64 1, i1 false) +; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-NOSCOPE-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP29:%.*]] = lshr i64 [[TMP28]], 4 +; AARCH64-NOSCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP29]] +; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP30]], i8 0, i64 1, i1 false) ; AARCH64-NOSCOPE-NEXT: ret i32 0 ; ; AARCH64-SHORT-SCOPE-LABEL: @multiple_lifetimes( -; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, i8* [[TMP29]], i32 0 -; AARCH64-SHORT-SCOPE-NEXT: store i8 1, i8* [[TMP30]], align 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP31:%.*]] = getelementptr i8, i8* [[TMP20]], i32 15 -; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP26]], i8* [[TMP31]], align 1 -; AARCH64-SHORT-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SHORT-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP32:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP34:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP33]] -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP34]], i8 0, i64 1, i1 false) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP27]], i32 0 +; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP28]], align 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 +; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP24]], ptr [[TMP29]], align 1 +; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP31]] +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP32]], i8 0, i64 1, i1 false) ; AARCH64-SHORT-SCOPE-NEXT: ret i32 0 ; ; AARCH64-SHORT-NOSCOPE-LABEL: @multiple_lifetimes( -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, i8* [[TMP29]], i32 0 -; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, i8* [[TMP30]], align 1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP31:%.*]] = getelementptr i8, i8* [[TMP20]], i32 15 -; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP26]], i8* [[TMP31]], align 1 -; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP32:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP34:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP33]] -; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP34]], i8 0, i64 1, i1 false) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP27]], i32 0 +; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP28]], align 1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 +; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP24]], ptr [[TMP29]], align 1 +; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP30:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP31]] +; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP32]], i8 0, i64 1, i1 false) ; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0 ; %1 = alloca i8, align 1 ; We erase lifetime markers if we insert instrumentation outside of the ; lifetime. - call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %1) - call void @use(i8* nonnull %1) #2 - call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %1) - call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %1) - call void @use(i8* nonnull %1) #2 - call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %1) + call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1) + call void @use(ptr nonnull %1) #2 + call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1) + call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1) + call void @use(ptr nonnull %1) #2 + call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1) ret i32 0 } define dso_local i32 @unreachable_exit() local_unnamed_addr sanitize_hwaddress { ; X86-SCOPE-LABEL: @unreachable_exit( -; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call i8* asm "", "=r,0"(i8* null) +; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-SCOPE-NEXT: [[TMP1:%.*]] = alloca { i8, [15 x i8] }, align 16 -; X86-SCOPE-NEXT: [[TMP2:%.*]] = bitcast { i8, [15 x i8] }* [[TMP1]] to i8* -; X86-SCOPE-NEXT: [[TMP3:%.*]] = call i8 @__hwasan_generate_tag() -; X86-SCOPE-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 -; X86-SCOPE-NEXT: [[TMP5:%.*]] = ptrtoint i8* [[TMP2]] to i64 -; X86-SCOPE-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 57 -; X86-SCOPE-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]] -; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to i8* -; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull [[TMP2]]) -; X86-SCOPE-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP4]] to i8 -; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 [[TMP8]], i64 16) -; X86-SCOPE-NEXT: [[TMP9:%.*]] = tail call i1 (...) @cond() -; X86-SCOPE-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP11:%.*]] -; X86-SCOPE: 10: -; X86-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 0, i64 16) +; X86-SCOPE-NEXT: [[TMP2:%.*]] = call i8 @__hwasan_generate_tag() +; X86-SCOPE-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 +; X86-SCOPE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; X86-SCOPE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 57 +; X86-SCOPE-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]] +; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr +; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP1]]) +; X86-SCOPE-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8 +; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 [[TMP7]], i64 16) +; X86-SCOPE-NEXT: [[TMP8:%.*]] = tail call i1 (...) @cond() +; X86-SCOPE-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP10:%.*]] +; X86-SCOPE: 9: +; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 0, i64 16) ; X86-SCOPE-NEXT: ret i32 0 -; X86-SCOPE: 11: -; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 0, i64 16) +; X86-SCOPE: 10: +; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 0, i64 16) ; X86-SCOPE-NEXT: ret i32 0 ; ; X86-NOSCOPE-LABEL: @unreachable_exit( -; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call i8* asm "", "=r,0"(i8* null) +; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = alloca { i8, [15 x i8] }, align 16 -; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = bitcast { i8, [15 x i8] }* [[TMP1]] to i8* -; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = call i8 @__hwasan_generate_tag() -; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 -; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = ptrtoint i8* [[TMP2]] to i64 -; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 57 -; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]] -; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to i8* -; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP4]] to i8 -; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 [[TMP8]], i64 16) -; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = tail call i1 (...) @cond() -; X86-NOSCOPE-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP11:%.*]] -; X86-NOSCOPE: 10: -; X86-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 0, i64 16) +; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = call i8 @__hwasan_generate_tag() +; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 +; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 57 +; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]] +; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr +; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8 +; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 [[TMP7]], i64 16) +; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = tail call i1 (...) @cond() +; X86-NOSCOPE-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP10:%.*]] +; X86-NOSCOPE: 9: +; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 0, i64 16) ; X86-NOSCOPE-NEXT: ret i32 0 -; X86-NOSCOPE: 11: -; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 0, i64 16) +; X86-NOSCOPE: 10: +; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 0, i64 16) ; X86-NOSCOPE-NEXT: ret i32 0 ; ; AARCH64-SCOPE-LABEL: @unreachable_exit( -; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-SCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP29]], i8 [[TMP26]], i64 1, i1 false) -; AARCH64-SCOPE-NEXT: [[TMP30:%.*]] = tail call i1 (...) @cond() -; AARCH64-SCOPE-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP35:%.*]] -; AARCH64-SCOPE: 31: -; AARCH64-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SCOPE-NEXT: [[TMP32:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4 -; AARCH64-SCOPE-NEXT: [[TMP34:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP33]] -; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP34]], i8 0, i64 1, i1 false) +; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP27]], i8 [[TMP24]], i64 1, i1 false) +; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = tail call i1 (...) @cond() +; AARCH64-SCOPE-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP33:%.*]] +; AARCH64-SCOPE: 29: +; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SCOPE-NEXT: [[TMP30:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 4 +; AARCH64-SCOPE-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP31]] +; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP32]], i8 0, i64 1, i1 false) ; AARCH64-SCOPE-NEXT: ret i32 0 -; AARCH64-SCOPE: 35: -; AARCH64-SCOPE-NEXT: [[TMP36:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP37:%.*]] = lshr i64 [[TMP36]], 4 -; AARCH64-SCOPE-NEXT: [[TMP38:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP37]] -; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP38]], i8 0, i64 1, i1 false) +; AARCH64-SCOPE: 33: +; AARCH64-SCOPE-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP35:%.*]] = lshr i64 [[TMP34]], 4 +; AARCH64-SCOPE-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP35]] +; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP36]], i8 0, i64 1, i1 false) ; AARCH64-SCOPE-NEXT: ret i32 0 ; ; AARCH64-NOSCOPE-LABEL: @unreachable_exit( -; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-NOSCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-NOSCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP29]], i8 [[TMP26]], i64 1, i1 false) -; AARCH64-NOSCOPE-NEXT: [[TMP30:%.*]] = tail call i1 (...) @cond() -; AARCH64-NOSCOPE-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP35:%.*]] -; AARCH64-NOSCOPE: 31: -; AARCH64-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-NOSCOPE-NEXT: [[TMP32:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4 -; AARCH64-NOSCOPE-NEXT: [[TMP34:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP33]] -; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP34]], i8 0, i64 1, i1 false) +; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP27]], i8 [[TMP24]], i64 1, i1 false) +; AARCH64-NOSCOPE-NEXT: [[TMP28:%.*]] = tail call i1 (...) @cond() +; AARCH64-NOSCOPE-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP33:%.*]] +; AARCH64-NOSCOPE: 29: +; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-NOSCOPE-NEXT: [[TMP30:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 4 +; AARCH64-NOSCOPE-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP31]] +; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP32]], i8 0, i64 1, i1 false) ; AARCH64-NOSCOPE-NEXT: ret i32 0 -; AARCH64-NOSCOPE: 35: -; AARCH64-NOSCOPE-NEXT: [[TMP36:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP37:%.*]] = lshr i64 [[TMP36]], 4 -; AARCH64-NOSCOPE-NEXT: [[TMP38:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP37]] -; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP38]], i8 0, i64 1, i1 false) +; AARCH64-NOSCOPE: 33: +; AARCH64-NOSCOPE-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP35:%.*]] = lshr i64 [[TMP34]], 4 +; AARCH64-NOSCOPE-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP35]] +; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP36]], i8 0, i64 1, i1 false) ; AARCH64-NOSCOPE-NEXT: ret i32 0 ; ; AARCH64-SHORT-SCOPE-LABEL: @unreachable_exit( -; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, i8* [[TMP29]], i32 0 -; AARCH64-SHORT-SCOPE-NEXT: store i8 1, i8* [[TMP30]], align 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP31:%.*]] = getelementptr i8, i8* [[TMP20]], i32 15 -; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP26]], i8* [[TMP31]], align 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP32:%.*]] = tail call i1 (...) @cond() -; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP37:%.*]] -; AARCH64-SHORT-SCOPE: 33: -; AARCH64-SHORT-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP34:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP35:%.*]] = lshr i64 [[TMP34]], 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP36:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP35]] -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP36]], i8 0, i64 1, i1 false) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP27]], i32 0 +; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP28]], align 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 +; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP24]], ptr [[TMP29]], align 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = tail call i1 (...) @cond() +; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP35:%.*]] +; AARCH64-SHORT-SCOPE: 31: +; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP32:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP34:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP33]] +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP34]], i8 0, i64 1, i1 false) ; AARCH64-SHORT-SCOPE-NEXT: ret i32 0 -; AARCH64-SHORT-SCOPE: 37: -; AARCH64-SHORT-SCOPE-NEXT: [[TMP38:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP39:%.*]] = lshr i64 [[TMP38]], 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP40:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP39]] -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP40]], i8 0, i64 1, i1 false) +; AARCH64-SHORT-SCOPE: 35: +; AARCH64-SHORT-SCOPE-NEXT: [[TMP36:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP37:%.*]] = lshr i64 [[TMP36]], 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP37]] +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP38]], i8 0, i64 1, i1 false) ; AARCH64-SHORT-SCOPE-NEXT: ret i32 0 ; ; AARCH64-SHORT-NOSCOPE-LABEL: @unreachable_exit( -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, i8* [[TMP29]], i32 0 -; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, i8* [[TMP30]], align 1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP31:%.*]] = getelementptr i8, i8* [[TMP20]], i32 15 -; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP26]], i8* [[TMP31]], align 1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP32:%.*]] = tail call i1 (...) @cond() -; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP37:%.*]] -; AARCH64-SHORT-NOSCOPE: 33: -; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP34:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP35:%.*]] = lshr i64 [[TMP34]], 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP36:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP35]] -; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP36]], i8 0, i64 1, i1 false) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP27]], i32 0 +; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP28]], align 1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 +; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP24]], ptr [[TMP29]], align 1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP30:%.*]] = tail call i1 (...) @cond() +; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP35:%.*]] +; AARCH64-SHORT-NOSCOPE: 31: +; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP32:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP34:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP33]] +; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP34]], i8 0, i64 1, i1 false) ; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0 -; AARCH64-SHORT-NOSCOPE: 37: -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP38:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP39:%.*]] = lshr i64 [[TMP38]], 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP40:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP39]] -; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP40]], i8 0, i64 1, i1 false) +; AARCH64-SHORT-NOSCOPE: 35: +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP36:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP37:%.*]] = lshr i64 [[TMP36]], 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP37]] +; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP38]], i8 0, i64 1, i1 false) ; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0 ; %1 = alloca i8, align 1 - call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %1) + call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1) %2 = tail call i1 (...) @cond() #2 br i1 %2, label %3, label %4 3: - call void @use(i8* nonnull %1) #2 - call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %1) + call void @use(ptr nonnull %1) #2 + call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1) ret i32 0 4: @@ -1039,283 +999,273 @@ define dso_local i32 @diamond_lifetime() local_unnamed_addr sanitize_hwaddress { ; X86-SCOPE-LABEL: @diamond_lifetime( -; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call i8* asm "", "=r,0"(i8* null) +; X86-SCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-SCOPE-NEXT: [[TMP1:%.*]] = alloca { i8, [15 x i8] }, align 16 -; X86-SCOPE-NEXT: [[TMP2:%.*]] = bitcast { i8, [15 x i8] }* [[TMP1]] to i8* -; X86-SCOPE-NEXT: [[TMP3:%.*]] = call i8 @__hwasan_generate_tag() -; X86-SCOPE-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 -; X86-SCOPE-NEXT: [[TMP5:%.*]] = ptrtoint i8* [[TMP2]] to i64 -; X86-SCOPE-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 57 -; X86-SCOPE-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]] -; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to i8* -; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull [[TMP2]]) -; X86-SCOPE-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP4]] to i8 -; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 [[TMP8]], i64 16) -; X86-SCOPE-NEXT: [[TMP9:%.*]] = tail call i1 (...) @cond() -; X86-SCOPE-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP11:%.*]] +; X86-SCOPE-NEXT: [[TMP2:%.*]] = call i8 @__hwasan_generate_tag() +; X86-SCOPE-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 +; X86-SCOPE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; X86-SCOPE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 57 +; X86-SCOPE-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]] +; X86-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr +; X86-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP1]]) +; X86-SCOPE-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8 +; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 [[TMP7]], i64 16) +; X86-SCOPE-NEXT: [[TMP8:%.*]] = tail call i1 (...) @cond() +; X86-SCOPE-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP10:%.*]] +; X86-SCOPE: 9: +; X86-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 0, i64 16) +; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP1]]) +; X86-SCOPE-NEXT: br label [[TMP11:%.*]] ; X86-SCOPE: 10: -; X86-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 0, i64 16) -; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull [[TMP2]]) -; X86-SCOPE-NEXT: br label [[TMP12:%.*]] +; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 0, i64 16) +; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP1]]) +; X86-SCOPE-NEXT: br label [[TMP11]] ; X86-SCOPE: 11: -; X86-SCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 0, i64 16) -; X86-SCOPE-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull [[TMP2]]) -; X86-SCOPE-NEXT: br label [[TMP12]] -; X86-SCOPE: 12: ; X86-SCOPE-NEXT: ret i32 0 ; ; X86-NOSCOPE-LABEL: @diamond_lifetime( -; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call i8* asm "", "=r,0"(i8* null) +; X86-NOSCOPE-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) ; X86-NOSCOPE-NEXT: [[TMP1:%.*]] = alloca { i8, [15 x i8] }, align 16 -; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = bitcast { i8, [15 x i8] }* [[TMP1]] to i8* -; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = call i8 @__hwasan_generate_tag() -; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = zext i8 [[TMP3]] to i64 -; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = ptrtoint i8* [[TMP2]] to i64 -; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = shl i64 [[TMP4]], 57 -; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = or i64 [[TMP5]], [[TMP6]] -; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP7]] to i8* -; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP4]] to i8 -; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 [[TMP8]], i64 16) -; X86-NOSCOPE-NEXT: [[TMP9:%.*]] = tail call i1 (...) @cond() -; X86-NOSCOPE-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP11:%.*]] +; X86-NOSCOPE-NEXT: [[TMP2:%.*]] = call i8 @__hwasan_generate_tag() +; X86-NOSCOPE-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i64 +; X86-NOSCOPE-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[TMP1]] to i64 +; X86-NOSCOPE-NEXT: [[TMP5:%.*]] = shl i64 [[TMP3]], 57 +; X86-NOSCOPE-NEXT: [[TMP6:%.*]] = or i64 [[TMP4]], [[TMP5]] +; X86-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP6]] to ptr +; X86-NOSCOPE-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP3]] to i8 +; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 [[TMP7]], i64 16) +; X86-NOSCOPE-NEXT: [[TMP8:%.*]] = tail call i1 (...) @cond() +; X86-NOSCOPE-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP10:%.*]] +; X86-NOSCOPE: 9: +; X86-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; X86-NOSCOPE-NEXT: br label [[TMP11:%.*]] ; X86-NOSCOPE: 10: -; X86-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; X86-NOSCOPE-NEXT: br label [[TMP12:%.*]] +; X86-NOSCOPE-NEXT: br label [[TMP11]] ; X86-NOSCOPE: 11: -; X86-NOSCOPE-NEXT: br label [[TMP12]] -; X86-NOSCOPE: 12: -; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(i8* [[TMP2]], i8 0, i64 16) +; X86-NOSCOPE-NEXT: call void @__hwasan_tag_memory(ptr [[TMP1]], i8 0, i64 16) ; X86-NOSCOPE-NEXT: ret i32 0 ; ; AARCH64-SCOPE-LABEL: @diamond_lifetime( -; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-SCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP29]], i8 [[TMP26]], i64 1, i1 false) -; AARCH64-SCOPE-NEXT: [[TMP30:%.*]] = tail call i1 (...) @cond() -; AARCH64-SCOPE-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP35:%.*]] -; AARCH64-SCOPE: 31: -; AARCH64-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SCOPE-NEXT: [[TMP32:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4 -; AARCH64-SCOPE-NEXT: [[TMP34:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP33]] -; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP34]], i8 0, i64 1, i1 false) -; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SCOPE-NEXT: br label [[TMP39:%.*]] -; AARCH64-SCOPE: 35: -; AARCH64-SCOPE-NEXT: [[TMP36:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SCOPE-NEXT: [[TMP37:%.*]] = lshr i64 [[TMP36]], 4 -; AARCH64-SCOPE-NEXT: [[TMP38:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP37]] -; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP38]], i8 0, i64 1, i1 false) -; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SCOPE-NEXT: br label [[TMP39]] -; AARCH64-SCOPE: 39: +; AARCH64-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP27]], i8 [[TMP24]], i64 1, i1 false) +; AARCH64-SCOPE-NEXT: [[TMP28:%.*]] = tail call i1 (...) @cond() +; AARCH64-SCOPE-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP33:%.*]] +; AARCH64-SCOPE: 29: +; AARCH64-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SCOPE-NEXT: [[TMP30:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 4 +; AARCH64-SCOPE-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP31]] +; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP32]], i8 0, i64 1, i1 false) +; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SCOPE-NEXT: br label [[TMP37:%.*]] +; AARCH64-SCOPE: 33: +; AARCH64-SCOPE-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SCOPE-NEXT: [[TMP35:%.*]] = lshr i64 [[TMP34]], 4 +; AARCH64-SCOPE-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP35]] +; AARCH64-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP36]], i8 0, i64 1, i1 false) +; AARCH64-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SCOPE-NEXT: br label [[TMP37]] +; AARCH64-SCOPE: 37: ; AARCH64-SCOPE-NEXT: ret i32 0 ; ; AARCH64-NOSCOPE-LABEL: @diamond_lifetime( -; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-NOSCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-NOSCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP29]], i8 [[TMP26]], i64 1, i1 false) -; AARCH64-NOSCOPE-NEXT: [[TMP30:%.*]] = tail call i1 (...) @cond() -; AARCH64-NOSCOPE-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP32:%.*]] +; AARCH64-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-NOSCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-NOSCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-NOSCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP27]], i8 [[TMP24]], i64 1, i1 false) +; AARCH64-NOSCOPE-NEXT: [[TMP28:%.*]] = tail call i1 (...) @cond() +; AARCH64-NOSCOPE-NEXT: br i1 [[TMP28]], label [[TMP29:%.*]], label [[TMP30:%.*]] +; AARCH64-NOSCOPE: 29: +; AARCH64-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-NOSCOPE-NEXT: br label [[TMP31:%.*]] +; AARCH64-NOSCOPE: 30: +; AARCH64-NOSCOPE-NEXT: br label [[TMP31]] ; AARCH64-NOSCOPE: 31: -; AARCH64-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-NOSCOPE-NEXT: br label [[TMP33:%.*]] -; AARCH64-NOSCOPE: 32: -; AARCH64-NOSCOPE-NEXT: br label [[TMP33]] -; AARCH64-NOSCOPE: 33: -; AARCH64-NOSCOPE-NEXT: [[TMP34:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-NOSCOPE-NEXT: [[TMP35:%.*]] = lshr i64 [[TMP34]], 4 -; AARCH64-NOSCOPE-NEXT: [[TMP36:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP35]] -; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP36]], i8 0, i64 1, i1 false) +; AARCH64-NOSCOPE-NEXT: [[TMP32:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-NOSCOPE-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4 +; AARCH64-NOSCOPE-NEXT: [[TMP34:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP33]] +; AARCH64-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP34]], i8 0, i64 1, i1 false) ; AARCH64-NOSCOPE-NEXT: ret i32 0 ; ; AARCH64-SHORT-SCOPE-LABEL: @diamond_lifetime( -; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, i8* [[TMP29]], i32 0 -; AARCH64-SHORT-SCOPE-NEXT: store i8 1, i8* [[TMP30]], align 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP31:%.*]] = getelementptr i8, i8* [[TMP20]], i32 15 -; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP26]], i8* [[TMP31]], align 1 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP32:%.*]] = tail call i1 (...) @cond() -; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP37:%.*]] -; AARCH64-SHORT-SCOPE: 33: -; AARCH64-SHORT-SCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SHORT-SCOPE-NEXT: [[TMP34:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP35:%.*]] = lshr i64 [[TMP34]], 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP36:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP35]] -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP36]], i8 0, i64 1, i1 false) -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP41:%.*]] -; AARCH64-SHORT-SCOPE: 37: -; AARCH64-SHORT-SCOPE-NEXT: [[TMP38:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP39:%.*]] = lshr i64 [[TMP38]], 4 -; AARCH64-SHORT-SCOPE-NEXT: [[TMP40:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP39]] -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP40]], i8 0, i64 1, i1 false) -; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* nonnull [[TMP20]]) -; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP41]] -; AARCH64-SHORT-SCOPE: 41: +; AARCH64-SHORT-SCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SHORT-SCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SHORT-SCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SHORT-SCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SHORT-SCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SHORT-SCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SHORT-SCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-SHORT-SCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP27]], i32 0 +; AARCH64-SHORT-SCOPE-NEXT: store i8 1, ptr [[TMP28]], align 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 +; AARCH64-SHORT-SCOPE-NEXT: store i8 [[TMP24]], ptr [[TMP29]], align 1 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP30:%.*]] = tail call i1 (...) @cond() +; AARCH64-SHORT-SCOPE-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP35:%.*]] +; AARCH64-SHORT-SCOPE: 31: +; AARCH64-SHORT-SCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SHORT-SCOPE-NEXT: [[TMP32:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP33:%.*]] = lshr i64 [[TMP32]], 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP34:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP33]] +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP34]], i8 0, i64 1, i1 false) +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP39:%.*]] +; AARCH64-SHORT-SCOPE: 35: +; AARCH64-SHORT-SCOPE-NEXT: [[TMP36:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP37:%.*]] = lshr i64 [[TMP36]], 4 +; AARCH64-SHORT-SCOPE-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP37]] +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP38]], i8 0, i64 1, i1 false) +; AARCH64-SHORT-SCOPE-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr nonnull [[TMP18]]) +; AARCH64-SHORT-SCOPE-NEXT: br label [[TMP39]] +; AARCH64-SHORT-SCOPE: 39: ; AARCH64-SHORT-SCOPE-NEXT: ret i32 0 ; ; AARCH64-SHORT-NOSCOPE-LABEL: @diamond_lifetime( -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call i8* @llvm.thread.pointer() -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, i8* [[TMP1]], i32 48 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i64* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = ashr i64 [[TMP4]], 3 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = ptrtoint i8* [[TMP7]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 44 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = or i64 [[TMP6]], [[TMP9]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP4]] to i64* -; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP10]], i64* [[TMP11]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = ashr i64 [[TMP4]], 56 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = shl nuw nsw i64 [[TMP12]], 12 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], -1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = add i64 [[TMP4]], 8 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = and i64 [[TMP15]], [[TMP14]] -; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP16]], i64* [[TMP3]], align 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = or i64 [[TMP4]], 4294967295 -; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP17]], 1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = alloca { i8, [15 x i8] }, align 16 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = bitcast { i8, [15 x i8] }* [[TMP19]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = call i8 @__hwasan_generate_tag() -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = zext i8 [[TMP21]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = shl i64 [[TMP22]], 56 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP25]] to i8* -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP22]] to i8 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = lshr i64 [[TMP27]], 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP28]] -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP30:%.*]] = getelementptr i8, i8* [[TMP29]], i32 0 -; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, i8* [[TMP30]], align 1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP31:%.*]] = getelementptr i8, i8* [[TMP20]], i32 15 -; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP26]], i8* [[TMP31]], align 1 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP32:%.*]] = tail call i1 (...) @cond() -; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP32]], label [[TMP33:%.*]], label [[TMP34:%.*]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer() +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 48 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 3 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1]]) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 44 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 56 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 12 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 8 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]] +; AARCH64-SHORT-NOSCOPE-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 4294967295 +; AARCH64-SHORT-NOSCOPE-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP18:%.*]] = alloca { i8, [15 x i8] }, align 16 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP19:%.*]] = call i8 @__hwasan_generate_tag() +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP20:%.*]] = zext i8 [[TMP19]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP22:%.*]] = shl i64 [[TMP20]], 56 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP23:%.*]] = or i64 [[TMP21]], [[TMP22]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[ALLOCA_0_HWASAN:%.*]] = inttoptr i64 [[TMP23]] to ptr +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP20]] to i8 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]] +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP28:%.*]] = getelementptr i8, ptr [[TMP27]], i32 0 +; AARCH64-SHORT-NOSCOPE-NEXT: store i8 1, ptr [[TMP28]], align 1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[TMP18]], i32 15 +; AARCH64-SHORT-NOSCOPE-NEXT: store i8 [[TMP24]], ptr [[TMP29]], align 1 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP30:%.*]] = tail call i1 (...) @cond() +; AARCH64-SHORT-NOSCOPE-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP32:%.*]] +; AARCH64-SHORT-NOSCOPE: 31: +; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(ptr nonnull [[ALLOCA_0_HWASAN]]) +; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP33:%.*]] +; AARCH64-SHORT-NOSCOPE: 32: +; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP33]] ; AARCH64-SHORT-NOSCOPE: 33: -; AARCH64-SHORT-NOSCOPE-NEXT: call void @use(i8* nonnull [[ALLOCA_0_HWASAN]]) -; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP35:%.*]] -; AARCH64-SHORT-NOSCOPE: 34: -; AARCH64-SHORT-NOSCOPE-NEXT: br label [[TMP35]] -; AARCH64-SHORT-NOSCOPE: 35: -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP36:%.*]] = ptrtoint i8* [[TMP20]] to i64 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP37:%.*]] = lshr i64 [[TMP36]], 4 -; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP38:%.*]] = getelementptr i8, i8* [[TMP18]], i64 [[TMP37]] -; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP38]], i8 0, i64 1, i1 false) +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP34:%.*]] = ptrtoint ptr [[TMP18]] to i64 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP35:%.*]] = lshr i64 [[TMP34]], 4 +; AARCH64-SHORT-NOSCOPE-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP35]] +; AARCH64-SHORT-NOSCOPE-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP36]], i8 0, i64 1, i1 false) ; AARCH64-SHORT-NOSCOPE-NEXT: ret i32 0 ; %1 = alloca i8, align 1 - call void @llvm.lifetime.start.p0i8(i64 1, i8* nonnull %1) + call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %1) %2 = tail call i1 (...) @cond() #2 br i1 %2, label %3, label %4 3: - call void @use(i8* nonnull %1) #2 - call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %1) + call void @use(ptr nonnull %1) #2 + call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1) br label %5 4: - call void @llvm.lifetime.end.p0i8(i64 1, i8* nonnull %1) + call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %1) br label %5 5: @@ -1324,10 +1274,10 @@ declare dso_local i1 @cond(...) local_unnamed_addr -declare dso_local void @use(i8*) local_unnamed_addr +declare dso_local void @use(ptr) local_unnamed_addr ; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn -declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) ; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn -declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/with-calls.ll b/llvm/test/Instrumentation/HWAddressSanitizer/with-calls.ll --- a/llvm/test/Instrumentation/HWAddressSanitizer/with-calls.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/with-calls.ll @@ -6,192 +6,192 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android" -define i8 @test_load8(i8* %a) sanitize_hwaddress { +define i8 @test_load8(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load8( -; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_load1(i64 %[[A]]) ; RECOVER: call void @__hwasan_load1_noabort(i64 %[[A]]) -; CHECK: %[[B:[^ ]*]] = load i8, i8* %a +; CHECK: %[[B:[^ ]*]] = load i8, ptr %a ; CHECK: ret i8 %[[B]] entry: - %b = load i8, i8* %a, align 4 + %b = load i8, ptr %a, align 4 ret i8 %b } -define i16 @test_load16(i16* %a) sanitize_hwaddress { +define i16 @test_load16(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load16( -; CHECK: %[[A:[^ ]*]] = ptrtoint i16* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_load2(i64 %[[A]]) ; RECOVER: call void @__hwasan_load2_noabort(i64 %[[A]]) -; CHECK: %[[B:[^ ]*]] = load i16, i16* %a +; CHECK: %[[B:[^ ]*]] = load i16, ptr %a ; CHECK: ret i16 %[[B]] entry: - %b = load i16, i16* %a, align 4 + %b = load i16, ptr %a, align 4 ret i16 %b } -define i32 @test_load32(i32* %a) sanitize_hwaddress { +define i32 @test_load32(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load32( -; CHECK: %[[A:[^ ]*]] = ptrtoint i32* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_load4(i64 %[[A]]) ; RECOVER: call void @__hwasan_load4_noabort(i64 %[[A]]) -; CHECK: %[[B:[^ ]*]] = load i32, i32* %a +; CHECK: %[[B:[^ ]*]] = load i32, ptr %a ; CHECK: ret i32 %[[B]] entry: - %b = load i32, i32* %a, align 4 + %b = load i32, ptr %a, align 4 ret i32 %b } -define i64 @test_load64(i64* %a) sanitize_hwaddress { +define i64 @test_load64(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load64( -; CHECK: %[[A:[^ ]*]] = ptrtoint i64* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_load8(i64 %[[A]]) ; RECOVER: call void @__hwasan_load8_noabort(i64 %[[A]]) -; CHECK: %[[B:[^ ]*]] = load i64, i64* %a +; CHECK: %[[B:[^ ]*]] = load i64, ptr %a ; CHECK: ret i64 %[[B]] entry: - %b = load i64, i64* %a, align 8 + %b = load i64, ptr %a, align 8 ret i64 %b } -define i128 @test_load128(i128* %a) sanitize_hwaddress { +define i128 @test_load128(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load128( -; CHECK: %[[A:[^ ]*]] = ptrtoint i128* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_load16(i64 %[[A]]) ; RECOVER: call void @__hwasan_load16_noabort(i64 %[[A]]) -; CHECK: %[[B:[^ ]*]] = load i128, i128* %a +; CHECK: %[[B:[^ ]*]] = load i128, ptr %a ; CHECK: ret i128 %[[B]] entry: - %b = load i128, i128* %a, align 16 + %b = load i128, ptr %a, align 16 ret i128 %b } -define i40 @test_load40(i40* %a) sanitize_hwaddress { +define i40 @test_load40(ptr %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load40( -; CHECK: %[[A:[^ ]*]] = ptrtoint i40* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_loadN(i64 %[[A]], i64 5) ; RECOVER: call void @__hwasan_loadN_noabort(i64 %[[A]], i64 5) -; CHECK: %[[B:[^ ]*]] = load i40, i40* %a +; CHECK: %[[B:[^ ]*]] = load i40, ptr %a ; CHECK: ret i40 %[[B]] entry: - %b = load i40, i40* %a, align 4 + %b = load i40, ptr %a, align 4 ret i40 %b } -define void @test_store8(i8* %a, i8 %b) sanitize_hwaddress { +define void @test_store8(ptr %a, i8 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store8( -; CHECK: %[[A:[^ ]*]] = ptrtoint i8* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_store1(i64 %[[A]]) ; RECOVER: call void @__hwasan_store1_noabort(i64 %[[A]]) -; CHECK: store i8 %b, i8* %a +; CHECK: store i8 %b, ptr %a ; CHECK: ret void entry: - store i8 %b, i8* %a, align 4 + store i8 %b, ptr %a, align 4 ret void } -define void @test_store16(i16* %a, i16 %b) sanitize_hwaddress { +define void @test_store16(ptr %a, i16 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store16( -; CHECK: %[[A:[^ ]*]] = ptrtoint i16* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_store2(i64 %[[A]]) ; RECOVER: call void @__hwasan_store2_noabort(i64 %[[A]]) -; CHECK: store i16 %b, i16* %a +; CHECK: store i16 %b, ptr %a ; CHECK: ret void entry: - store i16 %b, i16* %a, align 4 + store i16 %b, ptr %a, align 4 ret void } -define void @test_store32(i32* %a, i32 %b) sanitize_hwaddress { +define void @test_store32(ptr %a, i32 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store32( -; CHECK: %[[A:[^ ]*]] = ptrtoint i32* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_store4(i64 %[[A]]) ; RECOVER: call void @__hwasan_store4_noabort(i64 %[[A]]) -; CHECK: store i32 %b, i32* %a +; CHECK: store i32 %b, ptr %a ; CHECK: ret void entry: - store i32 %b, i32* %a, align 4 + store i32 %b, ptr %a, align 4 ret void } -define void @test_store64(i64* %a, i64 %b) sanitize_hwaddress { +define void @test_store64(ptr %a, i64 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store64( -; CHECK: %[[A:[^ ]*]] = ptrtoint i64* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_store8(i64 %[[A]]) ; RECOVER: call void @__hwasan_store8_noabort(i64 %[[A]]) -; CHECK: store i64 %b, i64* %a +; CHECK: store i64 %b, ptr %a ; CHECK: ret void entry: - store i64 %b, i64* %a, align 8 + store i64 %b, ptr %a, align 8 ret void } -define void @test_store128(i128* %a, i128 %b) sanitize_hwaddress { +define void @test_store128(ptr %a, i128 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store128( -; CHECK: %[[A:[^ ]*]] = ptrtoint i128* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_store16(i64 %[[A]]) ; RECOVER: call void @__hwasan_store16_noabort(i64 %[[A]]) -; CHECK: store i128 %b, i128* %a +; CHECK: store i128 %b, ptr %a ; CHECK: ret void entry: - store i128 %b, i128* %a, align 16 + store i128 %b, ptr %a, align 16 ret void } -define void @test_store40(i40* %a, i40 %b) sanitize_hwaddress { +define void @test_store40(ptr %a, i40 %b) sanitize_hwaddress { ; CHECK-LABEL: @test_store40( -; CHECK: %[[A:[^ ]*]] = ptrtoint i40* %a to i64 +; CHECK: %[[A:[^ ]*]] = ptrtoint ptr %a to i64 ; ABORT: call void @__hwasan_storeN(i64 %[[A]], i64 5) ; RECOVER: call void @__hwasan_storeN_noabort(i64 %[[A]], i64 5) -; CHECK: store i40 %b, i40* %a +; CHECK: store i40 %b, ptr %a ; CHECK: ret void entry: - store i40 %b, i40* %a, align 4 + store i40 %b, ptr %a, align 4 ret void } -define i8 @test_load_noattr(i8* %a) { +define i8 @test_load_noattr(ptr %a) { ; CHECK-LABEL: @test_load_noattr( ; CHECK-NEXT: entry: -; CHECK-NEXT: %[[B:[^ ]*]] = load i8, i8* %a +; CHECK-NEXT: %[[B:[^ ]*]] = load i8, ptr %a ; CHECK-NEXT: ret i8 %[[B]] entry: - %b = load i8, i8* %a, align 4 + %b = load i8, ptr %a, align 4 ret i8 %b } -define i8 @test_load_notmyattr(i8* %a) sanitize_address { +define i8 @test_load_notmyattr(ptr %a) sanitize_address { ; CHECK-LABEL: @test_load_notmyattr( ; CHECK-NEXT: entry: -; CHECK-NEXT: %[[B:[^ ]*]] = load i8, i8* %a +; CHECK-NEXT: %[[B:[^ ]*]] = load i8, ptr %a ; CHECK-NEXT: ret i8 %[[B]] entry: - %b = load i8, i8* %a, align 4 + %b = load i8, ptr %a, align 4 ret i8 %b } -define i8 @test_load_addrspace(i8 addrspace(256)* %a) sanitize_hwaddress { +define i8 @test_load_addrspace(ptr addrspace(256) %a) sanitize_hwaddress { ; CHECK-LABEL: @test_load_addrspace( ; CHECK-NEXT: entry: -; CHECK-NEXT: %[[B:[^ ]*]] = load i8, i8 addrspace(256)* %a +; CHECK-NEXT: %[[B:[^ ]*]] = load i8, ptr addrspace(256) %a ; CHECK-NEXT: ret i8 %[[B]] entry: - %b = load i8, i8 addrspace(256)* %a, align 4 + %b = load i8, ptr addrspace(256) %a, align 4 ret i8 %b } diff --git a/llvm/test/Instrumentation/HeapProfiler/basic.ll b/llvm/test/Instrumentation/HeapProfiler/basic.ll --- a/llvm/test/Instrumentation/HeapProfiler/basic.ll +++ b/llvm/test/Instrumentation/HeapProfiler/basic.ll @@ -10,52 +10,52 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -; CHECK: @llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @memprof.module_ctor to i8*)] -; CHECK: @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 1, void ()* @memprof.module_ctor, i8* null }] +; CHECK: @llvm.used = appending global [1 x ptr] [ptr @memprof.module_ctor] +; CHECK: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @memprof.module_ctor, ptr null }] -define i32 @test_load(i32* %a) { +define i32 @test_load(ptr %a) { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } ; CHECK-LABEL: @test_load -; CHECK: %[[SHADOW_OFFSET:[^ ]*]] = load i64, i64* @__memprof_shadow_memory_dynamic_address -; CHECK-NEXT: %[[LOAD_ADDR:[^ ]*]] = ptrtoint i32* %a to i64 +; CHECK: %[[SHADOW_OFFSET:[^ ]*]] = load i64, ptr @__memprof_shadow_memory_dynamic_address +; CHECK-NEXT: %[[LOAD_ADDR:[^ ]*]] = ptrtoint ptr %a to i64 ; CHECK-NEXT: %[[MASKED_ADDR:[^ ]*]] = and i64 %[[LOAD_ADDR]], -64 ; CHECK-S3-NEXT: %[[SHIFTED_ADDR:[^ ]*]] = lshr i64 %[[MASKED_ADDR]], 3 ; CHECK-S5-NEXT: %[[SHIFTED_ADDR:[^ ]*]] = lshr i64 %[[MASKED_ADDR]], 5 ; CHECK-NEXT: add i64 %[[SHIFTED_ADDR]], %[[SHADOW_OFFSET]] ; CHECK-NEXT: %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr -; CHECK-NEXT: %[[LOAD_SHADOW:[^ ]*]] = load i64, i64* %[[LOAD_SHADOW_PTR]] +; CHECK-NEXT: %[[LOAD_SHADOW:[^ ]*]] = load i64, ptr %[[LOAD_SHADOW_PTR]] ; CHECK-NEXT: %[[NEW_SHADOW:[^ ]*]] = add i64 %[[LOAD_SHADOW]], 1 -; CHECK-NEXT: store i64 %[[NEW_SHADOW]], i64* %[[LOAD_SHADOW_PTR]] +; CHECK-NEXT: store i64 %[[NEW_SHADOW]], ptr %[[LOAD_SHADOW_PTR]] ; The actual load. -; CHECK-NEXT: %tmp1 = load i32, i32* %a +; CHECK-NEXT: %tmp1 = load i32, ptr %a ; CHECK-NEXT: ret i32 %tmp1 -define void @test_store(i32* %a) { +define void @test_store(ptr %a) { entry: - store i32 42, i32* %a, align 4 + store i32 42, ptr %a, align 4 ret void } ; CHECK-LABEL: @test_store -; CHECK: %[[SHADOW_OFFSET:[^ ]*]] = load i64, i64* @__memprof_shadow_memory_dynamic_address -; CHECK-NEXT: %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %a to i64 +; CHECK: %[[SHADOW_OFFSET:[^ ]*]] = load i64, ptr @__memprof_shadow_memory_dynamic_address +; CHECK-NEXT: %[[STORE_ADDR:[^ ]*]] = ptrtoint ptr %a to i64 ; CHECK-NEXT: %[[MASKED_ADDR:[^ ]*]] = and i64 %[[STORE_ADDR]], -64 ; CHECK-S3-NEXT: %[[SHIFTED_ADDR:[^ ]*]] = lshr i64 %[[MASKED_ADDR]], 3 ; CHECK-S5-NEXT: %[[SHIFTED_ADDR:[^ ]*]] = lshr i64 %[[MASKED_ADDR]], 5 ; CHECK-NEXT: add i64 %[[SHIFTED_ADDR]], %[[SHADOW_OFFSET]] ; CHECK-NEXT: %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr -; CHECK-NEXT: %[[STORE_SHADOW:[^ ]*]] = load i64, i64* %[[STORE_SHADOW_PTR]] +; CHECK-NEXT: %[[STORE_SHADOW:[^ ]*]] = load i64, ptr %[[STORE_SHADOW_PTR]] ; CHECK-NEXT: %[[NEW_SHADOW:[^ ]*]] = add i64 %[[STORE_SHADOW]], 1 -; CHECK-NEXT: store i64 %[[NEW_SHADOW]], i64* %[[STORE_SHADOW_PTR]] +; CHECK-NEXT: store i64 %[[NEW_SHADOW]], ptr %[[STORE_SHADOW_PTR]] ; The actual store. -; CHECK-NEXT: store i32 42, i32* %a +; CHECK-NEXT: store i32 42, ptr %a ; CHECK-NEXT: ret void -define void @FP80Test(x86_fp80* nocapture %a) nounwind uwtable { +define void @FP80Test(ptr nocapture %a) nounwind uwtable { entry: - store x86_fp80 0xK3FFF8000000000000000, x86_fp80* %a, align 16 + store x86_fp80 0xK3FFF8000000000000000, ptr %a, align 16 ret void } ; CHECK-LABEL: @FP80Test @@ -65,13 +65,13 @@ ; CHECK-NEXT: store i64 %[[NEW_ST_SHADOW]] ; CHECK-NOT: store i64 ; The actual store. -; CHECK: store x86_fp80 0xK3FFF8000000000000000, x86_fp80* %a +; CHECK: store x86_fp80 0xK3FFF8000000000000000, ptr %a ; CHECK: ret void -define void @i40test(i40* %a, i40* %b) nounwind uwtable { +define void @i40test(ptr %a, ptr %b) nounwind uwtable { entry: - %t = load i40, i40* %a - store i40 %t, i40* %b, align 8 + %t = load i40, ptr %a + store i40 %t, ptr %b, align 8 ret void } ; CHECK-LABEL: @i40test @@ -81,19 +81,19 @@ ; CHECK-NEXT: store i64 %[[NEW_LD_SHADOW]] ; CHECK-NOT: store i64 ; The actual load. -; CHECK: %t = load i40, i40* %a +; CHECK: %t = load i40, ptr %a ; Exactly one shadow update for store access. ; CHECK-NOT: store i64 ; CHECK: %[[NEW_ST_SHADOW:[^ ]*]] = add i64 %{{.*}}, 1 ; CHECK-NEXT: store i64 %[[NEW_ST_SHADOW]] ; CHECK-NOT: store i64 ; The actual store. -; CHECK: store i40 %t, i40* %b +; CHECK: store i40 %t, ptr %b ; CHECK: ret void -define void @i64test_align1(i64* %b) nounwind uwtable { +define void @i64test_align1(ptr %b) nounwind uwtable { entry: - store i64 0, i64* %b, align 1 + store i64 0, ptr %b, align 1 ret void } ; CHECK-LABEL: @i64test @@ -103,13 +103,13 @@ ; CHECK-NEXT: store i64 %[[NEW_ST_SHADOW]] ; CHECK-NOT: store i64 ; The actual store. -; CHECK: store i64 0, i64* %b +; CHECK: store i64 0, ptr %b ; CHECK: ret void -define void @i80test(i80* %a, i80* %b) nounwind uwtable { +define void @i80test(ptr %a, ptr %b) nounwind uwtable { entry: - %t = load i80, i80* %a - store i80 %t, i80* %b, align 8 + %t = load i80, ptr %a + store i80 %t, ptr %b, align 8 ret void } ; CHECK-LABEL: i80test @@ -119,35 +119,35 @@ ; CHECK-NEXT: store i64 %[[NEW_LD_SHADOW]] ; CHECK-NOT: store i64 ; The actual load. -; CHECK: %t = load i80, i80* %a +; CHECK: %t = load i80, ptr %a ; Exactly one shadow update for store access. ; CHECK-NOT: store i64 ; CHECK: %[[NEW_ST_SHADOW:[^ ]*]] = add i64 %{{.*}}, 1 ; CHECK-NEXT: store i64 %[[NEW_ST_SHADOW]] ; CHECK-NOT: store i64 ; The actual store. -; CHECK: store i80 %t, i80* %b +; CHECK: store i80 %t, ptr %b ; CHECK: ret void ; memprof should not instrument functions with available_externally linkage. -define available_externally i32 @f_available_externally(i32* %a) { +define available_externally i32 @f_available_externally(ptr %a) { entry: - %tmp1 = load i32, i32* %a + %tmp1 = load i32, ptr %a ret i32 %tmp1 } ; CHECK-LABEL: @f_available_externally ; CHECK-NOT: __memprof_shadow_memory_dynamic_address ; CHECK: ret i32 -declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind -declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) nounwind -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i1) nounwind +declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind +declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1) nounwind +declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1) nounwind -define void @memintr_test(i8* %a, i8* %b) nounwind uwtable { +define void @memintr_test(ptr %a, ptr %b) nounwind uwtable { entry: - tail call void @llvm.memset.p0i8.i64(i8* %a, i8 0, i64 100, i1 false) - tail call void @llvm.memmove.p0i8.p0i8.i64(i8* %a, i8* %b, i64 100, i1 false) - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 100, i1 false) + tail call void @llvm.memset.p0.i64(ptr %a, i8 0, i64 100, i1 false) + tail call void @llvm.memmove.p0.p0.i64(ptr %a, ptr %b, i64 100, i1 false) + tail call void @llvm.memcpy.p0.p0.i64(ptr %a, ptr %b, i64 100, i1 false) ret void } @@ -157,22 +157,22 @@ ; CHECK: __memprof_memcpy ; CHECK: ret void -declare void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* nocapture writeonly, i8, i64, i32) nounwind -declare void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind -declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind +declare void @llvm.memset.element.unordered.atomic.p0.i64(ptr nocapture writeonly, i8, i64, i32) nounwind +declare void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind +declare void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind -define void @memintr_element_atomic_test(i8* %a, i8* %b) nounwind uwtable { +define void @memintr_element_atomic_test(ptr %a, ptr %b) nounwind uwtable { ; This is a canary test to make sure that these don't get lowered into calls that don't ; have the element-atomic property. Eventually, memprof will have to be enhanced to lower ; these properly. ; CHECK-LABEL: memintr_element_atomic_test - ; CHECK: tail call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %a, i8 0, i64 100, i32 1) - ; CHECK: tail call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1) - ; CHECK: tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1) + ; CHECK: tail call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 %a, i8 0, i64 100, i32 1) + ; CHECK: tail call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 %a, ptr align 1 %b, i64 100, i32 1) + ; CHECK: tail call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 %a, ptr align 1 %b, i64 100, i32 1) ; CHECK: ret void - tail call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %a, i8 0, i64 100, i32 1) - tail call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1) - tail call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %a, i8* align 1 %b, i64 100, i32 1) + tail call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 %a, i8 0, i64 100, i32 1) + tail call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 %a, ptr align 1 %b, i64 100, i32 1) + tail call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 %a, ptr align 1 %b, i64 100, i32 1) ret void } diff --git a/llvm/test/Instrumentation/HeapProfiler/instrumentation-use-callbacks.ll b/llvm/test/Instrumentation/HeapProfiler/instrumentation-use-callbacks.ll --- a/llvm/test/Instrumentation/HeapProfiler/instrumentation-use-callbacks.ll +++ b/llvm/test/Instrumentation/HeapProfiler/instrumentation-use-callbacks.ll @@ -9,27 +9,27 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define void @test_load(i32* %a, i64* %b, i512* %c, i80* %d) { +define void @test_load(ptr %a, ptr %b, ptr %c, ptr %d) { entry: -; CHECK-CALL: %[[LOAD_ADDR1:[^ ]*]] = ptrtoint i32* %a to i64 +; CHECK-CALL: %[[LOAD_ADDR1:[^ ]*]] = ptrtoint ptr %a to i64 ; CHECK-CALL-DEFAULT: call void @__memprof_load(i64 %[[LOAD_ADDR1]]) ; CHECK-CALL-CUSTOM: call void @__foo_load(i64 %[[LOAD_ADDR1]]) -; CHECK-CALL: %[[LOAD_ADDR2:[^ ]*]] = ptrtoint i64* %b to i64 +; CHECK-CALL: %[[LOAD_ADDR2:[^ ]*]] = ptrtoint ptr %b to i64 ; CHECK-CALL-DEFAULT: call void @__memprof_load(i64 %[[LOAD_ADDR2]]) ; CHECK-CALL-CUSTOM: call void @__foo_load(i64 %[[LOAD_ADDR2]]) -; CHECK-CALL: %[[LOAD_ADDR3:[^ ]*]] = ptrtoint i512* %c to i64 +; CHECK-CALL: %[[LOAD_ADDR3:[^ ]*]] = ptrtoint ptr %c to i64 ; CHECK-CALL-DEFAULT: call void @__memprof_load(i64 %[[LOAD_ADDR3]]) ; CHECK-CALL-CUSTOM: call void @__foo_load(i64 %[[LOAD_ADDR3]]) -; CHECK-CALL: %[[LOAD_ADDR4:[^ ]*]] = ptrtoint i80* %d to i64 +; CHECK-CALL: %[[LOAD_ADDR4:[^ ]*]] = ptrtoint ptr %d to i64 ; CHECK-CALL-DEFAULT: call void @__memprof_load(i64 %[[LOAD_ADDR4]]) ; CHECK-CALL-CUSTOM: call void @__foo_load(i64 %[[LOAD_ADDR4]]) ; CHECK-CALL-DEFAULT-NOT: call void @__memprof_load ; CHECK-CALL-CUSTOM-NOT: call void @__foo_load ; CHECK-INLINE-NOT: call void @__memprof_load - %tmp1 = load i32, i32* %a, align 4 - %tmp2 = load i64, i64* %b, align 8 - %tmp3 = load i512, i512* %c, align 32 - %tmp4 = load i80, i80* %d, align 8 + %tmp1 = load i32, ptr %a, align 4 + %tmp2 = load i64, ptr %b, align 8 + %tmp3 = load i512, ptr %c, align 32 + %tmp4 = load i80, ptr %d, align 8 ret void } diff --git a/llvm/test/Instrumentation/HeapProfiler/masked-load-store.ll b/llvm/test/Instrumentation/HeapProfiler/masked-load-store.ll --- a/llvm/test/Instrumentation/HeapProfiler/masked-load-store.ll +++ b/llvm/test/Instrumentation/HeapProfiler/masked-load-store.ll @@ -10,74 +10,74 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" -@v4f32 = global <4 x float>* zeroinitializer, align 8 -@v8i32 = global <8 x i32>* zeroinitializer, align 8 -@v4i64 = global <4 x i32*>* zeroinitializer, align 8 +@v4f32 = global ptr zeroinitializer, align 8 +@v8i32 = global ptr zeroinitializer, align 8 +@v4i64 = global ptr zeroinitializer, align 8 ;;;;;;;;;;;;;;;; STORE -declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>) argmemonly nounwind -declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>) argmemonly nounwind -declare void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*>, <4 x i32*>*, i32, <4 x i1>) argmemonly nounwind +declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32, <4 x i1>) argmemonly nounwind +declare void @llvm.masked.store.v8i32.p0(<8 x i32>, ptr, i32, <8 x i1>) argmemonly nounwind +declare void @llvm.masked.store.v4p0.p0(<4 x ptr>, ptr, i32, <4 x i1>) argmemonly nounwind define void @store.v4f32.1110(<4 x float> %arg) { ; ALL-LABEL: @store.v4f32.1110 - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 + %p = load ptr, ptr @v4f32, align 8 ; NOSTORE-NOT: call void @__memprof_store -; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 -; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 +; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 0 +; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP0]]) -; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1 -; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64 +; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 1 +; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP1]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP1]]) -; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2 -; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64 +; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 2 +; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP2]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP2]]) -; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) - tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) +; STORE: tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) + tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) ret void } define void @store.v8i32.10010110(<8 x i32> %arg) { ; ALL-LABEL: @store.v8i32.10010110 - %p = load <8 x i32>*, <8 x i32>** @v8i32, align 8 + %p = load ptr, ptr @v8i32, align 8 ; NOSTORE-NOT: call void @__memprof_store -; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0 -; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64 +; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 0 +; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP0]]) -; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 3 -; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP3]] to i64 +; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 3 +; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP3]]) -; STORE: [[GEP5:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 5 -; STORE: [[PGEP5:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP5]] to i64 +; STORE: [[GEP5:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 5 +; STORE: [[PGEP5:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP5]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP5]]) -; STORE: [[GEP6:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 6 -; STORE: [[PGEP6:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP6]] to i64 +; STORE: [[GEP6:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 6 +; STORE: [[PGEP6:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP6]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP6]]) -; STORE: tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> ) - tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> ) +; STORE: tail call void @llvm.masked.store.v8i32.p0(<8 x i32> %arg, ptr %p, i32 8, <8 x i1> ) + tail call void @llvm.masked.store.v8i32.p0(<8 x i32> %arg, ptr %p, i32 8, <8 x i1> ) ret void } -define void @store.v4i64.0001(<4 x i32*> %arg) { +define void @store.v4i64.0001(<4 x ptr> %arg) { ; ALL-LABEL: @store.v4i64.0001 - %p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8 + %p = load ptr, ptr @v4i64, align 8 ; NOSTORE-NOT: call void @__memprof_store -; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3 -; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64 +; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x ptr>, ptr %p, i64 0, i64 3 +; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP3]]) -; STORE: tail call void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*> %arg, <4 x i32*>* %p, i32 8, <4 x i1> ) - tail call void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*> %arg, <4 x i32*>* %p, i32 8, <4 x i1> ) +; STORE: tail call void @llvm.masked.store.v4p0.p0(<4 x ptr> %arg, ptr %p, i32 8, <4 x i1> ) + tail call void @llvm.masked.store.v4p0.p0(<4 x ptr> %arg, ptr %p, i32 8, <4 x i1> ) ret void } define void @store.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) { ; ALL-LABEL: @store.v4f32.variable - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 + %p = load ptr, ptr @v4f32, align 8 ; STORE: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0 ; STORE: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]] ; STORE: [[THEN0]]: -; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 -; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 +; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 0 +; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP0]]) ; STORE: br label %[[AFTER0]] ; STORE: [[AFTER0]]: @@ -85,8 +85,8 @@ ; STORE: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1 ; STORE: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]] ; STORE: [[THEN1]]: -; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1 -; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64 +; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 1 +; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP1]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP1]]) ; STORE: br label %[[AFTER1]] ; STORE: [[AFTER1]]: @@ -94,8 +94,8 @@ ; STORE: [[MASK2:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 2 ; STORE: br i1 [[MASK2]], label %[[THEN2:[0-9A-Za-z]+]], label %[[AFTER2:[0-9A-Za-z]+]] ; STORE: [[THEN2]]: -; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2 -; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64 +; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 2 +; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP2]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP2]]) ; STORE: br label %[[AFTER2]] ; STORE: [[AFTER2]]: @@ -103,95 +103,95 @@ ; STORE: [[MASK3:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 3 ; STORE: br i1 [[MASK3]], label %[[THEN3:[0-9A-Za-z]+]], label %[[AFTER3:[0-9A-Za-z]+]] ; STORE: [[THEN3]]: -; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3 -; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64 +; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 3 +; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP3]]) ; STORE: br label %[[AFTER3]] ; STORE: [[AFTER3]]: -; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask) - tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask) +; STORE: tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> %mask) + tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> %mask) ret void } ;; Store using two masked.stores, which should instrument them both. define void @store.v4f32.1010.split(<4 x float> %arg) { ; BOTH-LABEL: @store.v4f32.1010.split - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 -; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 -; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 + %p = load ptr, ptr @v4f32, align 8 +; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 0 +; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP0]]) -; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) - tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) -; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2 -; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64 +; STORE: tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) + tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) +; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 2 +; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP1]] to i64 ; STORE: call void @__memprof_store(i64 [[PGEP1]]) -; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) - tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> ) +; STORE: tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) + tail call void @llvm.masked.store.v4f32.p0(<4 x float> %arg, ptr %p, i32 4, <4 x i1> ) ret void } ;;;;;;;;;;;;;;;; LOAD -declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>) argmemonly nounwind -declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) argmemonly nounwind -declare <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>*, i32, <4 x i1>, <4 x i32*>) argmemonly nounwind +declare <4 x float> @llvm.masked.load.v4f32.p0(ptr, i32, <4 x i1>, <4 x float>) argmemonly nounwind +declare <8 x i32> @llvm.masked.load.v8i32.p0(ptr, i32, <8 x i1>, <8 x i32>) argmemonly nounwind +declare <4 x ptr> @llvm.masked.load.v4p0.p0(ptr, i32, <4 x i1>, <4 x ptr>) argmemonly nounwind define <8 x i32> @load.v8i32.11100001(<8 x i32> %arg) { ; ALL-LABEL: @load.v8i32.11100001 - %p = load <8 x i32>*, <8 x i32>** @v8i32, align 8 + %p = load ptr, ptr @v8i32, align 8 ; NOLOAD-NOT: call void @__memprof_load -; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0 -; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64 +; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 0 +; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; LOAD: call void @__memprof_load(i64 [[PGEP0]]) -; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 1 -; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP1]] to i64 +; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 1 +; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP1]] to i64 ; LOAD: call void @__memprof_load(i64 [[PGEP1]]) -; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 2 -; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP2]] to i64 +; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 2 +; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP2]] to i64 ; LOAD: call void @__memprof_load(i64 [[PGEP2]]) -; LOAD: [[GEP7:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 7 -; LOAD: [[PGEP7:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP7]] to i64 +; LOAD: [[GEP7:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, ptr %p, i64 0, i64 7 +; LOAD: [[PGEP7:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP7]] to i64 ; LOAD: call void @__memprof_load(i64 [[PGEP7]]) -; LOAD: tail call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %p, i32 8, <8 x i1> , <8 x i32> %arg) - %res = tail call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %p, i32 8, <8 x i1> , <8 x i32> %arg) +; LOAD: tail call <8 x i32> @llvm.masked.load.v8i32.p0(ptr %p, i32 8, <8 x i1> , <8 x i32> %arg) + %res = tail call <8 x i32> @llvm.masked.load.v8i32.p0(ptr %p, i32 8, <8 x i1> , <8 x i32> %arg) ret <8 x i32> %res } define <4 x float> @load.v4f32.1001(<4 x float> %arg) { ; ALL-LABEL: @load.v4f32.1001 - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 + %p = load ptr, ptr @v4f32, align 8 ; NOLOAD-NOT: call void @__memprof_load -; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 -; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 +; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 0 +; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; LOAD: call void @__memprof_load(i64 [[PGEP0]]) -; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3 -; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64 +; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 3 +; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; LOAD: call void @__memprof_load(i64 [[PGEP3]]) -; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %arg) - %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %arg) +; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %arg) + %res = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %arg) ret <4 x float> %res } -define <4 x i32*> @load.v4i64.0001(<4 x i32*> %arg) { +define <4 x ptr> @load.v4i64.0001(<4 x ptr> %arg) { ; ALL-LABEL: @load.v4i64.0001 - %p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8 + %p = load ptr, ptr @v4i64, align 8 ; NOLOAD-NOT: call void @__memprof_load -; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3 -; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64 +; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x ptr>, ptr %p, i64 0, i64 3 +; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; LOAD: call void @__memprof_load(i64 [[PGEP3]]) -; LOAD: tail call <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>* %p, i32 8, <4 x i1> , <4 x i32*> %arg) - %res = tail call <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>* %p, i32 8, <4 x i1> , <4 x i32*> %arg) - ret <4 x i32*> %res +; LOAD: tail call <4 x ptr> @llvm.masked.load.v4p0.p0(ptr %p, i32 8, <4 x i1> , <4 x ptr> %arg) + %res = tail call <4 x ptr> @llvm.masked.load.v4p0.p0(ptr %p, i32 8, <4 x i1> , <4 x ptr> %arg) + ret <4 x ptr> %res } define <4 x float> @load.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) { ; ALL-LABEL: @load.v4f32.variable - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 + %p = load ptr, ptr @v4f32, align 8 ; LOAD: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0 ; LOAD: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]] ; LOAD: [[THEN0]]: -; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 -; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 +; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 0 +; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; LOAD: call void @__memprof_load(i64 [[PGEP0]]) ; LOAD: br label %[[AFTER0]] ; LOAD: [[AFTER0]]: @@ -199,8 +199,8 @@ ; LOAD: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1 ; LOAD: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]] ; LOAD: [[THEN1]]: -; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1 -; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64 +; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 1 +; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP1]] to i64 ; LOAD: call void @__memprof_load(i64 [[PGEP1]]) ; LOAD: br label %[[AFTER1]] ; LOAD: [[AFTER1]]: @@ -208,8 +208,8 @@ ; LOAD: [[MASK2:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 2 ; LOAD: br i1 [[MASK2]], label %[[THEN2:[0-9A-Za-z]+]], label %[[AFTER2:[0-9A-Za-z]+]] ; LOAD: [[THEN2]]: -; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2 -; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64 +; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 2 +; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP2]] to i64 ; LOAD: call void @__memprof_load(i64 [[PGEP2]]) ; LOAD: br label %[[AFTER2]] ; LOAD: [[AFTER2]]: @@ -217,30 +217,30 @@ ; LOAD: [[MASK3:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 3 ; LOAD: br i1 [[MASK3]], label %[[THEN3:[0-9A-Za-z]+]], label %[[AFTER3:[0-9A-Za-z]+]] ; LOAD: [[THEN3]]: -; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3 -; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64 +; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 3 +; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; LOAD: call void @__memprof_load(i64 [[PGEP3]]) ; LOAD: br label %[[AFTER3]] ; LOAD: [[AFTER3]]: -; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg) - %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg) +; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> %mask, <4 x float> %arg) + %res = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> %mask, <4 x float> %arg) ret <4 x float> %res } ;; Load using two masked.loads, which should instrument them both. define <4 x float> @load.v4f32.1001.split(<4 x float> %arg) { ; BOTH-LABEL: @load.v4f32.1001 - %p = load <4 x float>*, <4 x float>** @v4f32, align 8 -; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 -; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 + %p = load ptr, ptr @v4f32, align 8 +; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 0 +; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP0]] to i64 ; LOAD: call void @__memprof_load(i64 [[PGEP0]]) -; LOAD: %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %arg) - %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %arg) -; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3 -; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64 +; LOAD: %res = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %arg) + %res = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %arg) +; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, ptr %p, i64 0, i64 3 +; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint ptr [[GEP3]] to i64 ; LOAD: call void @__memprof_load(i64 [[PGEP3]]) -; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %res) - %res2 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %res) +; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %res) + %res2 = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %p, i32 4, <4 x i1> , <4 x float> %res) ret <4 x float> %res2 } diff --git a/llvm/test/Instrumentation/HeapProfiler/scale-granularity.ll b/llvm/test/Instrumentation/HeapProfiler/scale-granularity.ll --- a/llvm/test/Instrumentation/HeapProfiler/scale-granularity.ll +++ b/llvm/test/Instrumentation/HeapProfiler/scale-granularity.ll @@ -5,9 +5,9 @@ ; RUN: opt < %s -passes='function(memprof),memprof-module' -memprof-mapping-granularity 16 -memprof-mapping-scale 0 -S | FileCheck --check-prefix=CHECK-BOTH %s target triple = "x86_64-unknown-linux-gnu" -define i32 @read(i32* %a) { +define i32 @read(ptr %a) { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } ; CHECK-GRAN-LABEL: @read diff --git a/llvm/test/Instrumentation/HeapProfiler/shadow.ll b/llvm/test/Instrumentation/HeapProfiler/shadow.ll --- a/llvm/test/Instrumentation/HeapProfiler/shadow.ll +++ b/llvm/test/Instrumentation/HeapProfiler/shadow.ll @@ -7,8 +7,8 @@ ; STATIC: @__memprof_shadow_memory_dynamic_address = external dso_local global i64 ; PIC: @__memprof_shadow_memory_dynamic_address = external global i64 -define i32 @test_load(i32* %a) { +define i32 @test_load(ptr %a) { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } diff --git a/llvm/test/Instrumentation/HeapProfiler/skip-compiler-inserted.ll b/llvm/test/Instrumentation/HeapProfiler/skip-compiler-inserted.ll --- a/llvm/test/Instrumentation/HeapProfiler/skip-compiler-inserted.ll +++ b/llvm/test/Instrumentation/HeapProfiler/skip-compiler-inserted.ll @@ -10,38 +10,38 @@ @__profc__Z3foov = private global [1 x i64] zeroinitializer, section "__llvm_prf_cnts", comdat, align 8 @__llvm_gcov_ctr = internal global [1 x i64] zeroinitializer -define void @_Z3foov(i32* %a) { +define void @_Z3foov(ptr %a) { entry: ;; Load that should get instrumentation. - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ;; PGO counter update - %pgocount = load i64, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__profc__Z3foov, i64 0, i64 0), align 8 + %pgocount = load i64, ptr @__profc__Z3foov, align 8 %0 = add i64 %pgocount, 1 - store i64 %0, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__profc__Z3foov, i64 0, i64 0), align 8 + store i64 %0, ptr @__profc__Z3foov, align 8 ;; Gcov counter update - %gcovcount = load i64, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__llvm_gcov_ctr, i64 0, i64 0), align 8 + %gcovcount = load i64, ptr @__llvm_gcov_ctr, align 8 %1 = add i64 %gcovcount, 1 - store i64 %1, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__llvm_gcov_ctr, i64 0, i64 0), align 8 + store i64 %1, ptr @__llvm_gcov_ctr, align 8 ret void } ;; We should only add memory profile instrumentation for the first load. ; CHECK: define void @_Z3foov ; CHECK-NEXT: entry: -; CHECK-NEXT: %0 = load i64, i64* @__memprof_shadow_memory_dynamic_address, align 8 -; CHECK-NEXT: %1 = ptrtoint i32* %a to i64 +; CHECK-NEXT: %0 = load i64, ptr @__memprof_shadow_memory_dynamic_address, align 8 +; CHECK-NEXT: %1 = ptrtoint ptr %a to i64 ; CHECK-NEXT: %2 = and i64 %1, -64 ; CHECK-NEXT: %3 = lshr i64 %2, 3 ; CHECK-NEXT: %4 = add i64 %3, %0 -; CHECK-NEXT: %5 = inttoptr i64 %4 to i64* -; CHECK-NEXT: %6 = load i64, i64* %5, align 8 +; CHECK-NEXT: %5 = inttoptr i64 %4 to ptr +; CHECK-NEXT: %6 = load i64, ptr %5, align 8 ; CHECK-NEXT: %7 = add i64 %6, 1 -; CHECK-NEXT: store i64 %7, i64* %5, align 8 -; CHECK-NEXT: %tmp1 = load i32, i32* %a, align 4 -; CHECK-NEXT: %pgocount = load i64, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__profc__Z3foov, i64 0, i64 0) +; CHECK-NEXT: store i64 %7, ptr %5, align 8 +; CHECK-NEXT: %tmp1 = load i32, ptr %a, align 4 +; CHECK-NEXT: %pgocount = load i64, ptr @__profc__Z3foov ; CHECK-NEXT: %8 = add i64 %pgocount, 1 -; CHECK-NEXT: store i64 %8, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__profc__Z3foov, i64 0, i64 0) -; CHECK-NEXT: %gcovcount = load i64, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__llvm_gcov_ctr, i64 0, i64 0) +; CHECK-NEXT: store i64 %8, ptr @__profc__Z3foov +; CHECK-NEXT: %gcovcount = load i64, ptr @__llvm_gcov_ctr ; CHECK-NEXT: %9 = add i64 %gcovcount, 1 -; CHECK-NEXT: store i64 %9, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__llvm_gcov_ctr, i64 0, i64 0) +; CHECK-NEXT: store i64 %9, ptr @__llvm_gcov_ctr ; CHECK-NEXT: ret void diff --git a/llvm/test/Instrumentation/HeapProfiler/stack.ll b/llvm/test/Instrumentation/HeapProfiler/stack.ll --- a/llvm/test/Instrumentation/HeapProfiler/stack.ll +++ b/llvm/test/Instrumentation/HeapProfiler/stack.ll @@ -9,41 +9,41 @@ define i32 @test_stack_load() { entry: %x = alloca i32, align 4 - %tmp1 = load i32, i32* %x, align 4 + %tmp1 = load i32, ptr %x, align 4 ret i32 %tmp1 } ; CHECK-LABEL: @test_stack_load -; CHECK: %[[SHADOW_OFFSET:[^ ]*]] = load i64, i64* @__memprof_shadow_memory_dynamic_address +; CHECK: %[[SHADOW_OFFSET:[^ ]*]] = load i64, ptr @__memprof_shadow_memory_dynamic_address ; CHECK-NEXT: %x = alloca i32 -; STACK-NEXT: %[[LOAD_ADDR:[^ ]*]] = ptrtoint i32* %x to i64 +; STACK-NEXT: %[[LOAD_ADDR:[^ ]*]] = ptrtoint ptr %x to i64 ; STACK-NEXT: %[[MASKED_ADDR:[^ ]*]] = and i64 %[[LOAD_ADDR]], -64 ; STACK-NEXT: %[[SHIFTED_ADDR:[^ ]*]] = lshr i64 %[[MASKED_ADDR]], 3 ; STACK-NEXT: add i64 %[[SHIFTED_ADDR]], %[[SHADOW_OFFSET]] ; STACK-NEXT: %[[LOAD_SHADOW_PTR:[^ ]*]] = inttoptr -; STACK-NEXT: %[[LOAD_SHADOW:[^ ]*]] = load i64, i64* %[[LOAD_SHADOW_PTR]] +; STACK-NEXT: %[[LOAD_SHADOW:[^ ]*]] = load i64, ptr %[[LOAD_SHADOW_PTR]] ; STACK-NEXT: %[[NEW_SHADOW:[^ ]*]] = add i64 %[[LOAD_SHADOW]], 1 -; STACK-NEXT: store i64 %[[NEW_SHADOW]], i64* %[[LOAD_SHADOW_PTR]] +; STACK-NEXT: store i64 %[[NEW_SHADOW]], ptr %[[LOAD_SHADOW_PTR]] ; The actual load. -; CHECK-NEXT: %tmp1 = load i32, i32* %x +; CHECK-NEXT: %tmp1 = load i32, ptr %x ; CHECK-NEXT: ret i32 %tmp1 define void @test_stack_store() { entry: %x = alloca i32, align 4 - store i32 1, i32* %x, align 4 + store i32 1, ptr %x, align 4 ret void } ; CHECK-LABEL: @test_stack_store -; CHECK: %[[SHADOW_OFFSET:[^ ]*]] = load i64, i64* @__memprof_shadow_memory_dynamic_address +; CHECK: %[[SHADOW_OFFSET:[^ ]*]] = load i64, ptr @__memprof_shadow_memory_dynamic_address ; CHECK-NEXT: %x = alloca i32 -; STACK-NEXT: %[[STORE_ADDR:[^ ]*]] = ptrtoint i32* %x to i64 +; STACK-NEXT: %[[STORE_ADDR:[^ ]*]] = ptrtoint ptr %x to i64 ; STACK-NEXT: %[[MASKED_ADDR:[^ ]*]] = and i64 %[[STORE_ADDR]], -64 ; STACK-NEXT: %[[SHIFTED_ADDR:[^ ]*]] = lshr i64 %[[MASKED_ADDR]], 3 ; STACK-NEXT: add i64 %[[SHIFTED_ADDR]], %[[SHADOW_OFFSET]] ; STACK-NEXT: %[[STORE_SHADOW_PTR:[^ ]*]] = inttoptr -; STACK-NEXT: %[[STORE_SHADOW:[^ ]*]] = load i64, i64* %[[STORE_SHADOW_PTR]] +; STACK-NEXT: %[[STORE_SHADOW:[^ ]*]] = load i64, ptr %[[STORE_SHADOW_PTR]] ; STACK-NEXT: %[[NEW_SHADOW:[^ ]*]] = add i64 %[[STORE_SHADOW]], 1 -; STACK-NEXT: store i64 %[[NEW_SHADOW]], i64* %[[STORE_SHADOW_PTR]] +; STACK-NEXT: store i64 %[[NEW_SHADOW]], ptr %[[STORE_SHADOW_PTR]] ; The actual store. -; CHECK-NEXT: store i32 1, i32* %x +; CHECK-NEXT: store i32 1, ptr %x ; CHECK-NEXT: ret void diff --git a/llvm/test/Instrumentation/MemorySanitizer/AArch64/vararg.ll b/llvm/test/Instrumentation/MemorySanitizer/AArch64/vararg.ll --- a/llvm/test/Instrumentation/MemorySanitizer/AArch64/vararg.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/AArch64/vararg.ll @@ -3,15 +3,14 @@ target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" target triple = "aarch64-unknown-linux-gnu" -%struct.__va_list = type { i8*, i8*, i8*, i32, i32 } +%struct.__va_list = type { ptr, ptr, ptr, i32, i32 } define i32 @foo(i32 %guard, ...) { %vl = alloca %struct.__va_list, align 8 - %1 = bitcast %struct.__va_list* %vl to i8* - call void @llvm.lifetime.start.p0i8(i64 32, i8* %1) - call void @llvm.va_start(i8* %1) - call void @llvm.va_end(i8* %1) - call void @llvm.lifetime.end.p0i8(i64 32, i8* %1) + call void @llvm.lifetime.start.p0(i64 32, ptr %vl) + call void @llvm.va_start(ptr %vl) + call void @llvm.va_end(ptr %vl) + call void @llvm.lifetime.end.p0(i64 32, ptr %vl) ret i32 0 } @@ -30,26 +29,26 @@ ; Propagate the GR shadow values on for the va_list::__gp_top, adjust the ; offset in the __msan_va_arg_tls based on va_list:__gp_off, and finally ; issue the memcpy. -; CHECK: [[GRP:%.*]] = getelementptr inbounds i8, i8* {{%.*}}, i64 {{%.*}} +; CHECK: [[GRP:%.*]] = getelementptr inbounds i8, ptr {{%.*}}, i64 {{%.*}} ; CHECK: [[GRSIZE:%.*]] = sub i64 64, {{%.*}} -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 {{%.*}}, i8* align 8 [[GRP]], i64 [[GRSIZE]], i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 {{%.*}}, ptr align 8 [[GRP]], i64 [[GRSIZE]], i1 false) ; Propagate the VR shadow values on for the va_list::__vr_top, adjust the ; offset in the __msan_va_arg_tls based on va_list:__vr_off, and finally ; issue the memcpy. -; CHECK: [[VRP:%.*]] = getelementptr inbounds i8, i8* {{%.*}}, i64 {{%.*}} +; CHECK: [[VRP:%.*]] = getelementptr inbounds i8, ptr {{%.*}}, i64 {{%.*}} ; CHECK: [[VRSIZE:%.*]] = sub i64 128, {{%.*}} -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 {{%.*}}, i8* align 8 [[VRP]], i64 [[VRSIZE]], i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 {{%.*}}, ptr align 8 [[VRP]], i64 [[VRSIZE]], i1 false) ; Copy the remaining shadow values on the va_list::__stack position (it is ; on the constant offset of 192 from __msan_va_arg_tls). -; CHECK: [[STACK:%.*]] = getelementptr inbounds i8, i8* {{%.*}}, i32 192 -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 {{%.*}}, i8* align 16 [[STACK]], i64 {{%.*}}, i1 false) +; CHECK: [[STACK:%.*]] = getelementptr inbounds i8, ptr {{%.*}}, i32 192 +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 16 {{%.*}}, ptr align 16 [[STACK]], i64 {{%.*}}, i1 false) -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 -declare void @llvm.va_start(i8*) #2 -declare void @llvm.va_end(i8*) #2 -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #1 +declare void @llvm.va_start(ptr) #2 +declare void @llvm.va_end(ptr) #2 +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1 define i32 @bar() { %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i32 2, double 3.000000e+00, @@ -98,6 +97,6 @@ } ; If the size of __msan_va_arg_tls changes the second argument of `add` must also be changed. -; CHECK: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 792) -; CHECK-NOT: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 800) +; CHECK: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 792) +; CHECK-NOT: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 800) declare i64 @sum(i64 %n, ...) diff --git a/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll b/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll --- a/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll @@ -4,12 +4,11 @@ target triple = "mips64--linux" define i32 @foo(i32 %guard, ...) { - %vl = alloca i8*, align 8 - %1 = bitcast i8** %vl to i8* - call void @llvm.lifetime.start.p0i8(i64 32, i8* %1) - call void @llvm.va_start(i8* %1) - call void @llvm.va_end(i8* %1) - call void @llvm.lifetime.end.p0i8(i64 32, i8* %1) + %vl = alloca ptr, align 8 + call void @llvm.lifetime.start.p0(i64 32, ptr %vl) + call void @llvm.va_start(ptr %vl) + call void @llvm.va_end(ptr %vl) + call void @llvm.lifetime.end.p0(i64 32, ptr %vl) ret i32 0 } @@ -20,12 +19,12 @@ ; CHECK: [[B:%.*]] = add i64 0, [[A]] ; CHECK: [[C:%.*]] = alloca {{.*}} [[B]] -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[B]], i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C]], ptr align 8 @__msan_va_arg_tls, i64 [[B]], i1 false) -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 -declare void @llvm.va_start(i8*) #2 -declare void @llvm.va_end(i8*) #2 -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #1 +declare void @llvm.va_start(ptr) #2 +declare void @llvm.va_end(ptr) #2 +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1 define i32 @bar() { %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i64 2, double 3.000000e+00) @@ -36,9 +35,9 @@ ; array. The first argument is stored at position 4, since it's right ; justified. ; CHECK-LABEL: @bar -; CHECK: store i32 0, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 4) to i32*), align 8 -; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 8) to i64*), align 8 -; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 16) to i64*), align 8 +; CHECK: store i32 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 4) to ptr), align 8 +; CHECK: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), align 8 +; CHECK: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 16) to ptr), align 8 ; CHECK: store {{.*}} 24, {{.*}} @__msan_va_arg_overflow_size_tls ; Check multiple fixed arguments. @@ -49,8 +48,8 @@ } ; CHECK-LABEL: @bar2 -; CHECK: store i64 0, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_va_arg_tls, i32 0, i32 0), align 8 -; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 8) to i64*), align 8 +; CHECK: store i64 0, ptr @__msan_va_arg_tls, align 8 +; CHECK: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), align 8 ; CHECK: store {{.*}} 16, {{.*}} @__msan_va_arg_overflow_size_tls ; Test that MSan doesn't generate code overflowing __msan_va_arg_tls when too many arguments are @@ -76,6 +75,6 @@ ; If the size of __msan_va_arg_tls changes the second argument of `add` must also be changed. ; CHECK-LABEL: @many_args -; CHECK: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 792) -; CHECK-NOT: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 800) +; CHECK: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 792) +; CHECK-NOT: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 800) declare i64 @sum(i64 %n, ...) diff --git a/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll b/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll --- a/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll @@ -4,12 +4,11 @@ target triple = "mips64el--linux" define i32 @foo(i32 %guard, ...) { - %vl = alloca i8*, align 8 - %1 = bitcast i8** %vl to i8* - call void @llvm.lifetime.start.p0i8(i64 32, i8* %1) - call void @llvm.va_start(i8* %1) - call void @llvm.va_end(i8* %1) - call void @llvm.lifetime.end.p0i8(i64 32, i8* %1) + %vl = alloca ptr, align 8 + call void @llvm.lifetime.start.p0(i64 32, ptr %vl) + call void @llvm.va_start(ptr %vl) + call void @llvm.va_end(ptr %vl) + call void @llvm.lifetime.end.p0(i64 32, ptr %vl) ret i32 0 } @@ -20,12 +19,12 @@ ; CHECK: [[B:%.*]] = add i64 0, [[A]] ; CHECK: [[C:%.*]] = alloca {{.*}} [[B]] -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[B]], i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C]], ptr align 8 @__msan_va_arg_tls, i64 [[B]], i1 false) -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 -declare void @llvm.va_start(i8*) #2 -declare void @llvm.va_end(i8*) #2 -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #1 +declare void @llvm.va_start(ptr) #2 +declare void @llvm.va_end(ptr) #2 +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1 define i32 @bar() { %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i64 2, double 3.000000e+00) @@ -35,9 +34,9 @@ ; Save the incoming shadow value from the arguments in the __msan_va_arg_tls ; array. ; CHECK-LABEL: @bar -; CHECK: store i32 0, i32* bitcast ([100 x i64]* @__msan_va_arg_tls to i32*), align 8 -; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 8) to i64*), align 8 -; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 16) to i64*), align 8 +; CHECK: store i32 0, ptr @__msan_va_arg_tls, align 8 +; CHECK: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), align 8 +; CHECK: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 16) to ptr), align 8 ; CHECK: store {{.*}} 24, {{.*}} @__msan_va_arg_overflow_size_tls ; Check multiple fixed arguments. @@ -48,8 +47,8 @@ } ; CHECK-LABEL: @bar2 -; CHECK: store i64 0, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_va_arg_tls, i32 0, i32 0), align 8 -; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 8) to i64*), align 8 +; CHECK: store i64 0, ptr @__msan_va_arg_tls, align 8 +; CHECK: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), align 8 ; CHECK: store {{.*}} 16, {{.*}} @__msan_va_arg_overflow_size_tls ; Test that MSan doesn't generate code overflowing __msan_va_arg_tls when too many arguments are @@ -75,6 +74,6 @@ ; If the size of __msan_va_arg_tls changes the second argument of `add` must also be changed. ; CHECK-LABEL: @many_args -; CHECK: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 792) -; CHECK-NOT: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 800) +; CHECK: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 792) +; CHECK-NOT: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 800) declare i64 @sum(i64 %n, ...) diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll --- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll @@ -4,12 +4,11 @@ target triple = "powerpc64--linux" define i32 @foo(i32 %guard, ...) { - %vl = alloca i8*, align 8 - %1 = bitcast i8** %vl to i8* - call void @llvm.lifetime.start.p0i8(i64 32, i8* %1) - call void @llvm.va_start(i8* %1) - call void @llvm.va_end(i8* %1) - call void @llvm.lifetime.end.p0i8(i64 32, i8* %1) + %vl = alloca ptr, align 8 + call void @llvm.lifetime.start.p0(i64 32, ptr %vl) + call void @llvm.va_start(ptr %vl) + call void @llvm.va_end(ptr %vl) + call void @llvm.lifetime.end.p0(i64 32, ptr %vl) ret i32 0 } @@ -20,12 +19,12 @@ ; CHECK: [[B:%.*]] = add i64 0, [[A]] ; CHECK: [[C:%.*]] = alloca {{.*}} [[B]] -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[B]], i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C]], ptr align 8 @__msan_va_arg_tls, i64 [[B]], i1 false) -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 -declare void @llvm.va_start(i8*) #2 -declare void @llvm.va_end(i8*) #2 -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #1 +declare void @llvm.va_start(ptr) #2 +declare void @llvm.va_end(ptr) #2 +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1 define i32 @bar() { %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i64 2, double 3.000000e+00) @@ -36,9 +35,9 @@ ; array. The first argument is stored at position 4, since it's right ; justified. ; CHECK-LABEL: @bar -; CHECK: store i32 0, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 4) to i32*), align 8 -; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 8) to i64*), align 8 -; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 16) to i64*), align 8 +; CHECK: store i32 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 4) to ptr), align 8 +; CHECK: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), align 8 +; CHECK: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 16) to ptr), align 8 ; CHECK: store {{.*}} 24, {{.*}} @__msan_va_arg_overflow_size_tls ; Check vector argument. @@ -51,7 +50,7 @@ ; corresponds to offset 8+ of parameter save area - so the offset from ; __msan_va_arg_tls is actually misaligned. ; CHECK-LABEL: @bar2 -; CHECK: store <2 x i64> zeroinitializer, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 8) to <2 x i64>*), align 8 +; CHECK: store <2 x i64> zeroinitializer, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), align 8 ; CHECK: store {{.*}} 24, {{.*}} @__msan_va_arg_overflow_size_tls ; Check i64 array. @@ -61,7 +60,7 @@ } ; CHECK-LABEL: @bar4 -; CHECK: store [2 x i64] zeroinitializer, [2 x i64]* bitcast ([100 x i64]* @__msan_va_arg_tls to [2 x i64]*), align 8 +; CHECK: store [2 x i64] zeroinitializer, ptr @__msan_va_arg_tls, align 8 ; CHECK: store {{.*}} 16, {{.*}} @__msan_va_arg_overflow_size_tls ; Check i128 array. @@ -71,27 +70,27 @@ } ; CHECK-LABEL: @bar5 -; CHECK: store [2 x i128] zeroinitializer, [2 x i128]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 8) to [2 x i128]*), align 8 +; CHECK: store [2 x i128] zeroinitializer, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), align 8 ; CHECK: store {{.*}} 40, {{.*}} @__msan_va_arg_overflow_size_tls ; Check 8-aligned byval. -define i32 @bar6([2 x i64]* %arg) { - %1 = call i32 (i32, ...) @foo(i32 0, [2 x i64]* byval([2 x i64]) align 8 %arg) +define i32 @bar6(ptr %arg) { + %1 = call i32 (i32, ...) @foo(i32 0, ptr byval([2 x i64]) align 8 %arg) ret i32 %1 } ; CHECK-LABEL: @bar6 -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 bitcast ([100 x i64]* @__msan_va_arg_tls to i8*), i8* align 8 {{.*}}, i64 16, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 @__msan_va_arg_tls, ptr align 8 {{.*}}, i64 16, i1 false) ; CHECK: store {{.*}} 16, {{.*}} @__msan_va_arg_overflow_size_tls ; Check 16-aligned byval. -define i32 @bar7([4 x i64]* %arg) { - %1 = call i32 (i32, ...) @foo(i32 0, [4 x i64]* byval([4 x i64]) align 16 %arg) +define i32 @bar7(ptr %arg) { + %1 = call i32 (i32, ...) @foo(i32 0, ptr byval([4 x i64]) align 16 %arg) ret i32 %1 } ; CHECK-LABEL: @bar7 -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 8) to i8*), i8* align 8 {{.*}}, i64 32, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), ptr align 8 {{.*}}, i64 32, i1 false) ; CHECK: store {{.*}} 40, {{.*}} @__msan_va_arg_overflow_size_tls @@ -118,6 +117,6 @@ ; If the size of __msan_va_arg_tls changes the second argument of `add` must also be changed. ; CHECK-LABEL: @many_args -; CHECK: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 792) -; CHECK-NOT: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 800) +; CHECK: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 792) +; CHECK-NOT: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 800) declare i64 @sum(i64 %n, ...) diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll --- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll @@ -4,12 +4,11 @@ target triple = "powerpc64le--linux" define i32 @foo(i32 %guard, ...) { - %vl = alloca i8*, align 8 - %1 = bitcast i8** %vl to i8* - call void @llvm.lifetime.start.p0i8(i64 32, i8* %1) - call void @llvm.va_start(i8* %1) - call void @llvm.va_end(i8* %1) - call void @llvm.lifetime.end.p0i8(i64 32, i8* %1) + %vl = alloca ptr, align 8 + call void @llvm.lifetime.start.p0(i64 32, ptr %vl) + call void @llvm.va_start(ptr %vl) + call void @llvm.va_end(ptr %vl) + call void @llvm.lifetime.end.p0(i64 32, ptr %vl) ret i32 0 } @@ -20,12 +19,12 @@ ; CHECK: [[B:%.*]] = add i64 0, [[A]] ; CHECK: [[C:%.*]] = alloca {{.*}} [[B]] -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[C]], i8* align 8 bitcast ({{.*}} @__msan_va_arg_tls to i8*), i64 [[B]], i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C]], ptr align 8 @__msan_va_arg_tls, i64 [[B]], i1 false) -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 -declare void @llvm.va_start(i8*) #2 -declare void @llvm.va_end(i8*) #2 -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #1 +declare void @llvm.va_start(ptr) #2 +declare void @llvm.va_end(ptr) #2 +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1 define i32 @bar() { %1 = call i32 (i32, ...) @foo(i32 0, i32 1, i64 2, double 3.000000e+00) @@ -35,9 +34,9 @@ ; Save the incoming shadow value from the arguments in the __msan_va_arg_tls ; array. ; CHECK-LABEL: @bar -; CHECK: store i32 0, i32* bitcast ([100 x i64]* @__msan_va_arg_tls to i32*), align 8 -; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 8) to i64*), align 8 -; CHECK: store i64 0, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 16) to i64*), align 8 +; CHECK: store i32 0, ptr @__msan_va_arg_tls, align 8 +; CHECK: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), align 8 +; CHECK: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 16) to ptr), align 8 ; CHECK: store {{.*}} 24, {{.*}} @__msan_va_arg_overflow_size_tls ; Check vector argument. @@ -50,7 +49,7 @@ ; corresponds to offset 8+ of parameter save area - so the offset from ; __msan_va_arg_tls is actually misaligned. ; CHECK-LABEL: @bar2 -; CHECK: store <2 x i64> zeroinitializer, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 8) to <2 x i64>*), align 8 +; CHECK: store <2 x i64> zeroinitializer, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), align 8 ; CHECK: store {{.*}} 24, {{.*}} @__msan_va_arg_overflow_size_tls ; Check i64 array. @@ -60,7 +59,7 @@ } ; CHECK-LABEL: @bar4 -; CHECK: store [2 x i64] zeroinitializer, [2 x i64]* bitcast ([100 x i64]* @__msan_va_arg_tls to [2 x i64]*), align 8 +; CHECK: store [2 x i64] zeroinitializer, ptr @__msan_va_arg_tls, align 8 ; CHECK: store {{.*}} 16, {{.*}} @__msan_va_arg_overflow_size_tls ; Check i128 array. @@ -70,27 +69,27 @@ } ; CHECK-LABEL: @bar5 -; CHECK: store [2 x i128] zeroinitializer, [2 x i128]* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 8) to [2 x i128]*), align 8 +; CHECK: store [2 x i128] zeroinitializer, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), align 8 ; CHECK: store {{.*}} 40, {{.*}} @__msan_va_arg_overflow_size_tls ; Check 8-aligned byval. -define i32 @bar6([2 x i64]* %arg) { - %1 = call i32 (i32, ...) @foo(i32 0, [2 x i64]* byval([2 x i64]) align 8 %arg) +define i32 @bar6(ptr %arg) { + %1 = call i32 (i32, ...) @foo(i32 0, ptr byval([2 x i64]) align 8 %arg) ret i32 %1 } ; CHECK-LABEL: @bar6 -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 bitcast ([100 x i64]* @__msan_va_arg_tls to i8*), i8* align 8 {{.*}}, i64 16, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 @__msan_va_arg_tls, ptr align 8 {{.*}}, i64 16, i1 false) ; CHECK: store {{.*}} 16, {{.*}} @__msan_va_arg_overflow_size_tls ; Check 16-aligned byval. -define i32 @bar7([4 x i64]* %arg) { - %1 = call i32 (i32, ...) @foo(i32 0, [4 x i64]* byval([4 x i64]) align 16 %arg) +define i32 @bar7(ptr %arg) { + %1 = call i32 (i32, ...) @foo(i32 0, ptr byval([4 x i64]) align 16 %arg) ret i32 %1 } ; CHECK-LABEL: @bar7 -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 8) to i8*), i8* align 8 {{.*}}, i64 32, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 8) to ptr), ptr align 8 {{.*}}, i64 32, i1 false) ; CHECK: store {{.*}} 40, {{.*}} @__msan_va_arg_overflow_size_tls ; Test that MSan doesn't generate code overflowing __msan_va_arg_tls when too many arguments are @@ -116,6 +115,6 @@ ; If the size of __msan_va_arg_tls changes the second argument of `add` must also be changed. ; CHECK-LABEL: @many_args -; CHECK: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 792) -; CHECK-NOT: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 800) +; CHECK: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 792) +; CHECK-NOT: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 800) declare i64 @sum(i64 %n, ...) diff --git a/llvm/test/Instrumentation/MemorySanitizer/SystemZ/vararg.ll b/llvm/test/Instrumentation/MemorySanitizer/SystemZ/vararg.ll --- a/llvm/test/Instrumentation/MemorySanitizer/SystemZ/vararg.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/SystemZ/vararg.ll @@ -3,15 +3,14 @@ target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64" target triple = "s390x-unknown-linux-gnu" -%struct.__va_list = type { i64, i64, i8*, i8* } +%struct.__va_list = type { i64, i64, ptr, ptr } define i64 @foo(i64 %guard, ...) { %vl = alloca %struct.__va_list, align 8 - %1 = bitcast %struct.__va_list* %vl to i8* - call void @llvm.lifetime.start.p0i8(i64 32, i8* %1) - call void @llvm.va_start(i8* %1) - call void @llvm.va_end(i8* %1) - call void @llvm.lifetime.end.p0i8(i64 32, i8* %1) + call void @llvm.lifetime.start.p0(i64 32, ptr %vl) + call void @llvm.va_start(ptr %vl) + call void @llvm.va_end(ptr %vl) + call void @llvm.lifetime.end.p0(i64 32, ptr %vl) ret i64 0 } @@ -26,13 +25,13 @@ ; We expect two memcpy operations: one for the register save area, and one for ; the overflow arg area. -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 {{%.*}}, i8* align 8 {{%.*}}, i64 160, i1 false) -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 {{%.*}}, i8* align 8 {{%.*}}, i64 [[A]], i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 {{%.*}}, ptr align 8 {{%.*}}, i64 160, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 {{%.*}}, ptr align 8 {{%.*}}, i64 [[A]], i1 false) -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 -declare void @llvm.va_start(i8*) #2 -declare void @llvm.va_end(i8*) #2 -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #1 +declare void @llvm.va_start(ptr) #2 +declare void @llvm.va_end(ptr) #2 +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1 declare i32 @random_i32() declare i64 @random_i64() @@ -119,8 +118,8 @@ ; If the size of __msan_va_arg_tls changes the second argument of `add` must also be changed. ; CHECK-LABEL: @many_args -; CHECK: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 792) -; CHECK-NOT: i64 add (i64 ptrtoint ([100 x i64]* @__msan_va_arg_tls to i64), i64 800) +; CHECK: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 792) +; CHECK-NOT: i64 add (i64 ptrtoint (ptr @__msan_va_arg_tls to i64), i64 800) declare i64 @sum(i64 %n, ...) diff --git a/llvm/test/Instrumentation/MemorySanitizer/X86/vararg.ll b/llvm/test/Instrumentation/MemorySanitizer/X86/vararg.ll --- a/llvm/test/Instrumentation/MemorySanitizer/X86/vararg.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/X86/vararg.ll @@ -4,12 +4,11 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S128" target triple = "i386-unknown-linux-gnu" -define void @VaStart(i8* %s, ...) { +define void @VaStart(ptr %s, ...) { entry: - %vl = alloca i8*, align 4 - %vl1 = bitcast i8** %vl to i8* - call void @llvm.va_start(i8* %vl1) + %vl = alloca ptr, align 4 + call void @llvm.va_start(ptr %vl) ret void } -declare void @llvm.va_start(i8*) +declare void @llvm.va_start(ptr) diff --git a/llvm/test/Instrumentation/MemorySanitizer/X86/vararg_call.ll b/llvm/test/Instrumentation/MemorySanitizer/X86/vararg_call.ll --- a/llvm/test/Instrumentation/MemorySanitizer/X86/vararg_call.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/X86/vararg_call.ll @@ -12,7 +12,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -%struct.__va_list_tag = type { i32, i32, i8*, i8* } +%struct.__va_list_tag = type { i32, i32, ptr, ptr } define dso_local i32 @test(i32 %a, i32 %b, i32 %c) local_unnamed_addr { entry: @@ -33,29 +33,27 @@ define dso_local i32 @sum(i32 %n, ...) local_unnamed_addr #0 { entry: %args = alloca [1 x %struct.__va_list_tag], align 16 - %0 = bitcast [1 x %struct.__va_list_tag]* %args to i8* - call void @llvm.lifetime.start.p0i8(i64 24, i8* nonnull %0) #2 - call void @llvm.va_start(i8* nonnull %0) + call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %args) #2 + call void @llvm.va_start(ptr nonnull %args) %cmp9 = icmp sgt i32 %n, 0 br i1 %cmp9, label %for.body.lr.ph, label %for.end -; CHECK: call void @llvm.memcpy.{{.*}} [[SHADOW_COPY:%[_0-9a-z]+]], {{.*}} bitcast ({{.*}} @__msan_va_arg_tls to i8*) -; CHECK-ORIGIN: call void @llvm.memcpy{{.*}} [[ORIGIN_COPY:%[_0-9a-z]+]], {{.*}} bitcast ({{.*}} @__msan_va_arg_origin_tls to i8*) +; CHECK: call void @llvm.memcpy.{{.*}} [[SHADOW_COPY:%[_0-9a-z]+]], {{.*}} @__msan_va_arg_tls +; CHECK-ORIGIN: call void @llvm.memcpy{{.*}} [[ORIGIN_COPY:%[_0-9a-z]+]], {{.*}} @__msan_va_arg_origin_tls ; CHECK: call void @llvm.va_start ; CHECK: call void @llvm.memcpy.{{.*}}, {{.*}} [[SHADOW_COPY]], i{{.*}} [[REGSAVE:[0-9]+]] ; CHECK-ORIGIN: call void @llvm.memcpy.{{.*}}, {{.*}} [[ORIGIN_COPY]], i{{.*}} [[REGSAVE]] -; CHECK: [[OVERFLOW_SHADOW:%[_0-9a-z]+]] = getelementptr i8, i8* [[SHADOW_COPY]], i{{.*}} [[REGSAVE]] +; CHECK: [[OVERFLOW_SHADOW:%[_0-9a-z]+]] = getelementptr i8, ptr [[SHADOW_COPY]], i{{.*}} [[REGSAVE]] ; CHECK: call void @llvm.memcpy.{{.*}}[[OVERFLOW_SHADOW]] -; CHECK-ORIGIN: [[OVERFLOW_ORIGIN:%[_0-9a-z]+]] = getelementptr i8, i8* [[ORIGIN_COPY]], i{{.*}} [[REGSAVE]] +; CHECK-ORIGIN: [[OVERFLOW_ORIGIN:%[_0-9a-z]+]] = getelementptr i8, ptr [[ORIGIN_COPY]], i{{.*}} [[REGSAVE]] ; CHECK-ORIGIN: call void @llvm.memcpy.{{.*}}[[OVERFLOW_ORIGIN]] for.body.lr.ph: ; preds = %entry - %gp_offset_p = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %args, i64 0, i64 0, i32 0 - %1 = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %args, i64 0, i64 0, i32 3 - %overflow_arg_area_p = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %args, i64 0, i64 0, i32 2 - %gp_offset.pre = load i32, i32* %gp_offset_p, align 16 + %0 = getelementptr inbounds [1 x %struct.__va_list_tag], ptr %args, i64 0, i64 0, i32 3 + %overflow_arg_area_p = getelementptr inbounds [1 x %struct.__va_list_tag], ptr %args, i64 0, i64 0, i32 2 + %gp_offset.pre = load i32, ptr %args, align 16 br label %for.body for.body: ; preds = %vaarg.end, %for.body.lr.ph @@ -66,48 +64,47 @@ br i1 %fits_in_gp, label %vaarg.in_reg, label %vaarg.in_mem vaarg.in_reg: ; preds = %for.body - %reg_save_area = load i8*, i8** %1, align 16 - %2 = sext i32 %gp_offset to i64 - %3 = getelementptr i8, i8* %reg_save_area, i64 %2 - %4 = add i32 %gp_offset, 8 - store i32 %4, i32* %gp_offset_p, align 16 + %reg_save_area = load ptr, ptr %0, align 16 + %1 = sext i32 %gp_offset to i64 + %2 = getelementptr i8, ptr %reg_save_area, i64 %1 + %3 = add i32 %gp_offset, 8 + store i32 %3, ptr %args, align 16 br label %vaarg.end vaarg.in_mem: ; preds = %for.body - %overflow_arg_area = load i8*, i8** %overflow_arg_area_p, align 8 - %overflow_arg_area.next = getelementptr i8, i8* %overflow_arg_area, i64 8 - store i8* %overflow_arg_area.next, i8** %overflow_arg_area_p, align 8 + %overflow_arg_area = load ptr, ptr %overflow_arg_area_p, align 8 + %overflow_arg_area.next = getelementptr i8, ptr %overflow_arg_area, i64 8 + store ptr %overflow_arg_area.next, ptr %overflow_arg_area_p, align 8 br label %vaarg.end vaarg.end: ; preds = %vaarg.in_mem, %vaarg.in_reg - %gp_offset12 = phi i32 [ %4, %vaarg.in_reg ], [ %gp_offset, %vaarg.in_mem ] - %vaarg.addr.in = phi i8* [ %3, %vaarg.in_reg ], [ %overflow_arg_area, %vaarg.in_mem ] - %vaarg.addr = bitcast i8* %vaarg.addr.in to i32* - %5 = load i32, i32* %vaarg.addr, align 4 - %add = add nsw i32 %5, %sum.011 + %gp_offset12 = phi i32 [ %3, %vaarg.in_reg ], [ %gp_offset, %vaarg.in_mem ] + %vaarg.addr.in = phi ptr [ %2, %vaarg.in_reg ], [ %overflow_arg_area, %vaarg.in_mem ] + %4 = load i32, ptr %vaarg.addr.in, align 4 + %add = add nsw i32 %4, %sum.011 %inc = add nuw nsw i32 %i.010, 1 %exitcond = icmp eq i32 %inc, %n br i1 %exitcond, label %for.end, label %for.body for.end: ; preds = %vaarg.end, %entry %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %vaarg.end ] - call void @llvm.va_end(i8* nonnull %0) - call void @llvm.lifetime.end.p0i8(i64 24, i8* nonnull %0) #2 + call void @llvm.va_end(ptr nonnull %args) + call void @llvm.lifetime.end.p0(i64 24, ptr nonnull %args) #2 ret i32 %sum.0.lcssa } ; Function Attrs: argmemonly nounwind -declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 +declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #1 ; Function Attrs: nounwind -declare void @llvm.va_start(i8*) #2 +declare void @llvm.va_start(ptr) #2 ; Function Attrs: nounwind -declare void @llvm.va_end(i8*) #2 +declare void @llvm.va_end(ptr) #2 ; Function Attrs: argmemonly nounwind -declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 +declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1 declare dso_local i80 @sum_i80(i32, ...) local_unnamed_addr diff --git a/llvm/test/Instrumentation/MemorySanitizer/alloca.ll b/llvm/test/Instrumentation/MemorySanitizer/alloca.ll --- a/llvm/test/Instrumentation/MemorySanitizer/alloca.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/alloca.ll @@ -20,11 +20,11 @@ } ; CHECK-LABEL: define void @static( -; INLINE: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 4, i1 false) -; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 4) -; ORIGIN: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 4, i8* {{.*}} [[IDPTR]] {{.*}}, i8* {{.*}} [[DESCR]], -; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 4, i8* {{.*}} [[IDPTR]] -; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 4, +; INLINE: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 4, i1 false) +; CALL: call void @__msan_poison_stack(ptr {{.*}}, i64 4) +; ORIGIN: call void @__msan_set_alloca_origin_with_descr(ptr %unique_x, i64 4, ptr [[IDPTR]], ptr [[DESCR]]) +; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(ptr %unique_x, i64 4, ptr [[IDPTR]]) +; KMSAN: call void @__msan_poison_alloca(ptr {{.*}}, i64 4, ; CHECK: ret void @@ -37,11 +37,11 @@ } ; CHECK-LABEL: define void @dynamic( -; INLINE: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 4, i1 false) -; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 4) -; ORIGIN: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 4, -; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 4, -; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 4, +; INLINE: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 4, i1 false) +; CALL: call void @__msan_poison_stack(ptr {{.*}}, i64 4) +; ORIGIN: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 4, +; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 4, +; KMSAN: call void @__msan_poison_alloca(ptr {{.*}}, i64 4, ; CHECK: ret void define void @array() sanitize_memory { @@ -51,11 +51,11 @@ } ; CHECK-LABEL: define void @array( -; INLINE: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 20, i1 false) -; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 20) -; ORIGIN: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 20, -; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 20, -; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 20, +; INLINE: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 20, i1 false) +; CALL: call void @__msan_poison_stack(ptr {{.*}}, i64 20) +; ORIGIN: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 20, +; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 20, +; KMSAN: call void @__msan_poison_alloca(ptr {{.*}}, i64 20, ; CHECK: ret void define void @array32() sanitize_memory { @@ -65,11 +65,11 @@ } ; CHECK-LABEL: define void @array32( -; INLINE: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 20, i1 false) -; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 20) -; ORIGIN: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 20, -; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 20, -; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 20, +; INLINE: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 20, i1 false) +; CALL: call void @__msan_poison_stack(ptr {{.*}}, i64 20) +; ORIGIN: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 20, +; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 20, +; KMSAN: call void @__msan_poison_alloca(ptr {{.*}}, i64 20, ; CHECK: ret void define void @array_non_const(i64 %cnt) sanitize_memory { @@ -80,11 +80,11 @@ ; CHECK-LABEL: define void @array_non_const( ; CHECK: %[[A:.*]] = mul i64 4, %cnt -; INLINE: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 %[[A]], i1 false) -; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 %[[A]]) -; ORIGIN: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 %[[A]], -; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 %[[A]], -; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 %[[A]], +; INLINE: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 %[[A]], i1 false) +; CALL: call void @__msan_poison_stack(ptr {{.*}}, i64 %[[A]]) +; ORIGIN: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 %[[A]], +; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 %[[A]], +; KMSAN: call void @__msan_poison_alloca(ptr {{.*}}, i64 %[[A]], ; CHECK: ret void define void @array_non_const32(i32 %cnt) sanitize_memory { @@ -96,11 +96,11 @@ ; CHECK-LABEL: define void @array_non_const32( ; CHECK: %[[Z:.*]] = zext i32 %cnt to i64 ; CHECK: %[[A:.*]] = mul i64 4, %[[Z]] -; INLINE: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 %[[A]], i1 false) -; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 %[[A]]) -; ORIGIN: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 %[[A]], -; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 %[[A]], -; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 %[[A]], +; INLINE: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 %[[A]], i1 false) +; CALL: call void @__msan_poison_stack(ptr {{.*}}, i64 %[[A]]) +; ORIGIN: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 %[[A]], +; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 %[[A]], +; KMSAN: call void @__msan_poison_alloca(ptr {{.*}}, i64 %[[A]], ; CHECK: ret void ; Check that the local is unpoisoned in the absence of sanitize_memory @@ -111,27 +111,26 @@ } ; CHECK-LABEL: define void @unpoison_local( -; INLINE: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 0, i64 20, i1 false) -; CALL: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 0, i64 20, i1 false) -; ORIGIN-NOT: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 20, -; ORIGIN-LEAN-NOT: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 20, -; KMSAN: call void @__msan_unpoison_alloca(i8* {{.*}}, i64 20) +; INLINE: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 0, i64 20, i1 false) +; CALL: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 0, i64 20, i1 false) +; ORIGIN-NOT: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 20, +; ORIGIN-LEAN-NOT: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 20, +; KMSAN: call void @__msan_unpoison_alloca(ptr {{.*}}, i64 20) ; CHECK: ret void ; Check that every llvm.lifetime.start() causes poisoning of locals. define void @lifetime_start() sanitize_memory { entry: %x = alloca i32, align 4 - %c = bitcast i32* %x to i8* br label %another_bb another_bb: - call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %c) - store i32 7, i32* %x - call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %c) - call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %c) - store i32 8, i32* %x - call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %c) + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %x) + store i32 7, ptr %x + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %x) + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %x) + store i32 8, ptr %x + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %x) ret void } @@ -141,27 +140,26 @@ ; CHECK-LABEL: another_bb: ; CHECK: call void @llvm.lifetime.start -; INLINE: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 4, i1 false) -; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 4) -; ORIGIN: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 4, -; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 4, -; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 4, +; INLINE: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 4, i1 false) +; CALL: call void @__msan_poison_stack(ptr {{.*}}, i64 4) +; ORIGIN: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 4, +; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 4, +; KMSAN: call void @__msan_poison_alloca(ptr {{.*}}, i64 4, ; CHECK: call void @llvm.lifetime.start -; INLINE: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 4, i1 false) -; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 4) -; ORIGIN: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 4, -; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 4, -; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 4, +; INLINE: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 4, i1 false) +; CALL: call void @__msan_poison_stack(ptr {{.*}}, i64 4) +; ORIGIN: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 4, +; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 4, +; KMSAN: call void @__msan_poison_alloca(ptr {{.*}}, i64 4, ; CHECK: ret void ; Make sure variable-length arrays are handled correctly. define void @lifetime_start_var(i64 %cnt) sanitize_memory { entry: %x = alloca i32, i64 %cnt, align 4 - %c = bitcast i32* %x to i8* - call void @llvm.lifetime.start.p0i8(i64 -1, i8* nonnull %c) - call void @llvm.lifetime.end.p0i8(i64 -1, i8* nonnull %c) + call void @llvm.lifetime.start.p0(i64 -1, ptr nonnull %x) + call void @llvm.lifetime.end.p0(i64 -1, ptr nonnull %x) ret void } @@ -170,11 +168,11 @@ ; CHECK: %x = alloca i32, i64 %cnt ; CHECK: call void @llvm.lifetime.start ; CHECK: %[[A:.*]] = mul i64 4, %cnt -; INLINE: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 %[[A]], i1 false) -; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 %[[A]]) -; ORIGIN: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 %[[A]], -; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 %[[A]], -; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 %[[A]], +; INLINE: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 %[[A]], i1 false) +; CALL: call void @__msan_poison_stack(ptr {{.*}}, i64 %[[A]]) +; ORIGIN: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 %[[A]], +; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 %[[A]], +; KMSAN: call void @__msan_poison_alloca(ptr {{.*}}, i64 %[[A]], ; CHECK: call void @llvm.lifetime.end ; CHECK: ret void @@ -187,72 +185,69 @@ %x = alloca i32, align 4 %y = alloca i32, align 4 %z = alloca i32, align 4 - %cx = bitcast i32* %x to i8* - %cy = bitcast i32* %y to i8* - %cz = bitcast i32* %z to i8* %tobool = icmp eq i8 %v, 0 - %xy = select i1 %tobool, i32* %x, i32* %y - %cxcy = select i1 %tobool, i8* %cx, i8* %cy + %xy = select i1 %tobool, ptr %x, ptr %y + %cxcy = select i1 %tobool, ptr %x, ptr %y br label %another_bb another_bb: - call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %cz) - store i32 7, i32* %z - call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %cz) - call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %cz) - store i32 7, i32* %z - call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %cz) - call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %cxcy) - store i32 8, i32* %xy - call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %cxcy) + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %z) + store i32 7, ptr %z + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %z) + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %z) + store i32 7, ptr %z + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %z) + call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %cxcy) + store i32 8, ptr %xy + call void @llvm.lifetime.end.p0(i64 4, ptr nonnull %cxcy) ret void } ; CHECK-LABEL: define void @lifetime_no_alloca( ; CHECK-LABEL: entry: ; CHECK: %x = alloca i32 -; INLINE: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 4, i1 false) -; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 4) -; ORIGIN: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 4, -; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 4, -; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 4, +; INLINE: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 4, i1 false) +; CALL: call void @__msan_poison_stack(ptr {{.*}}, i64 4) +; ORIGIN: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 4, +; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 4, +; KMSAN: call void @__msan_poison_alloca(ptr {{.*}}, i64 4, ; CHECK: %y = alloca i32 -; INLINE: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 4, i1 false) -; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 4) -; ORIGIN: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 4, -; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 4, -; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 4, +; INLINE: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 4, i1 false) +; CALL: call void @__msan_poison_stack(ptr {{.*}}, i64 4) +; ORIGIN: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 4, +; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 4, +; KMSAN: call void @__msan_poison_alloca(ptr {{.*}}, i64 4, ; CHECK: %z = alloca i32 -; INLINE: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 4, i1 false) -; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 4) -; ORIGIN: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 4, -; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 4, -; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 4, +; INLINE: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 4, i1 false) +; CALL: call void @__msan_poison_stack(ptr {{.*}}, i64 4) +; ORIGIN: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 4, +; ORIGIN-LEAN: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 4, +; KMSAN: call void @__msan_poison_alloca(ptr {{.*}}, i64 4, ; There're two lifetime intrinsics for %z, but we must instrument it only once. -; INLINE-NOT: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 4, i1 false) -; CALL-NOT: call void @__msan_poison_stack(i8* {{.*}}, i64 4) -; ORIGIN-NOT: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 4, -; ORIGIN-LEAN-NOT: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 4, -; KMSAN-NOT: call void @__msan_poison_alloca(i8* {{.*}}, i64 4, +; INLINE-NOT: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 4, i1 false) +; CALL-NOT: call void @__msan_poison_stack(ptr {{.*}}, i64 4) +; ORIGIN-NOT: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 4, +; ORIGIN-LEAN-NOT: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 4, +; KMSAN-NOT: call void @__msan_poison_alloca(ptr {{.*}}, i64 4, ; CHECK-LABEL: another_bb: ; CHECK: call void @llvm.lifetime.start -; INLINE-NOT: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 4, i1 false) -; CALL-NOT: call void @__msan_poison_stack(i8* {{.*}}, i64 4) -; ORIGIN-NOT: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 4, -; ORIGIN-LEAN-NOT: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 4, -; KMSAN-NOT: call void @__msan_poison_alloca(i8* {{.*}}, i64 4, +; INLINE-NOT: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 4, i1 false) +; CALL-NOT: call void @__msan_poison_stack(ptr {{.*}}, i64 4) +; ORIGIN-NOT: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 4, +; ORIGIN-LEAN-NOT: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 4, +; KMSAN-NOT: call void @__msan_poison_alloca(ptr {{.*}}, i64 4, ; CHECK: call void @llvm.lifetime.end ; CHECK: call void @llvm.lifetime.start -; INLINE-NOT: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 -1, i64 4, i1 false) -; CALL-NOT: call void @__msan_poison_stack(i8* {{.*}}, i64 4) -; ORIGIN-NOT: call void @__msan_set_alloca_origin_with_descr(i8* {{.*}}, i64 4, -; ORIGIN-LEAN-NOT: call void @__msan_set_alloca_origin_no_descr(i8* {{.*}}, i64 4, -; KMSAN-NOT: call void @__msan_poison_alloca(i8* {{.*}}, i64 4, +; INLINE-NOT: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 -1, i64 4, i1 false) +; CALL-NOT: call void @__msan_poison_stack(ptr {{.*}}, i64 4) +; ORIGIN-NOT: call void @__msan_set_alloca_origin_with_descr(ptr {{.*}}, i64 4, +; ORIGIN-LEAN-NOT: call void @__msan_set_alloca_origin_no_descr(ptr {{.*}}, i64 4, +; KMSAN-NOT: call void @__msan_poison_alloca(ptr {{.*}}, i64 4, ; CHECK: call void @llvm.lifetime.end -declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) -declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) diff --git a/llvm/test/Instrumentation/MemorySanitizer/atomics.ll b/llvm/test/Instrumentation/MemorySanitizer/atomics.ll --- a/llvm/test/Instrumentation/MemorySanitizer/atomics.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/atomics.ll @@ -7,9 +7,9 @@ ; atomicrmw xchg: store clean shadow, return clean shadow -define i32 @AtomicRmwXchg(i32* %p, i32 %x) sanitize_memory { +define i32 @AtomicRmwXchg(ptr %p, i32 %x) sanitize_memory { entry: - %0 = atomicrmw xchg i32* %p, i32 %x seq_cst + %0 = atomicrmw xchg ptr %p, i32 %x seq_cst ret i32 %0 } @@ -21,24 +21,24 @@ ; atomicrmw xchg ptr: exactly the same as above -define i32* @AtomicRmwXchgPtr(i32** %p, i32* %x) sanitize_memory { +define ptr @AtomicRmwXchgPtr(ptr %p, ptr %x) sanitize_memory { entry: - %0 = atomicrmw xchg i32** %p, i32* %x seq_cst - ret i32* %0 + %0 = atomicrmw xchg ptr %p, ptr %x seq_cst + ret ptr %0 } ; CHECK-LABEL: @AtomicRmwXchgPtr ; CHECK: store i64 0, ; CHECK: atomicrmw xchg {{.*}} seq_cst ; CHECK: store i64 0, {{.*}} @__msan_retval_tls -; CHECK: ret i32* +; CHECK: ret ptr ; atomicrmw max: exactly the same as above -define i32 @AtomicRmwMax(i32* %p, i32 %x) sanitize_memory { +define i32 @AtomicRmwMax(ptr %p, i32 %x) sanitize_memory { entry: - %0 = atomicrmw max i32* %p, i32 %x seq_cst + %0 = atomicrmw max ptr %p, i32 %x seq_cst ret i32 %0 } @@ -51,9 +51,9 @@ ; cmpxchg: the same as above, but also check %a shadow -define i32 @Cmpxchg(i32* %p, i32 %a, i32 %b) sanitize_memory { +define i32 @Cmpxchg(ptr %p, i32 %a, i32 %b) sanitize_memory { entry: - %pair = cmpxchg i32* %p, i32 %a, i32 %b seq_cst seq_cst + %pair = cmpxchg ptr %p, i32 %a, i32 %b seq_cst seq_cst %0 = extractvalue { i32, i1 } %pair, 0 ret i32 %0 } @@ -71,9 +71,9 @@ ; relaxed cmpxchg: bump up to "release monotonic" -define i32 @CmpxchgMonotonic(i32* %p, i32 %a, i32 %b) sanitize_memory { +define i32 @CmpxchgMonotonic(ptr %p, i32 %a, i32 %b) sanitize_memory { entry: - %pair = cmpxchg i32* %p, i32 %a, i32 %b monotonic monotonic + %pair = cmpxchg ptr %p, i32 %a, i32 %b monotonic monotonic %0 = extractvalue { i32, i1 } %pair, 0 ret i32 %0 } @@ -91,119 +91,119 @@ ; atomic load: preserve alignment, load shadow value after app value -define i32 @AtomicLoad(i32* %p) sanitize_memory { +define i32 @AtomicLoad(ptr %p) sanitize_memory { entry: - %0 = load atomic i32, i32* %p seq_cst, align 16 + %0 = load atomic i32, ptr %p seq_cst, align 16 ret i32 %0 } ; CHECK-LABEL: @AtomicLoad -; CHECK: load atomic i32, i32* {{.*}} seq_cst, align 16 -; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16 +; CHECK: load atomic i32, ptr {{.*}} seq_cst, align 16 +; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, ptr {{.*}}, align 16 ; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls ; CHECK: ret i32 ; atomic load: preserve alignment, load shadow value after app value -define i32 @AtomicLoadAcquire(i32* %p) sanitize_memory { +define i32 @AtomicLoadAcquire(ptr %p) sanitize_memory { entry: - %0 = load atomic i32, i32* %p acquire, align 16 + %0 = load atomic i32, ptr %p acquire, align 16 ret i32 %0 } ; CHECK-LABEL: @AtomicLoadAcquire -; CHECK: load atomic i32, i32* {{.*}} acquire, align 16 -; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16 +; CHECK: load atomic i32, ptr {{.*}} acquire, align 16 +; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, ptr {{.*}}, align 16 ; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls ; CHECK: ret i32 ; atomic load monotonic: bump up to load acquire -define i32 @AtomicLoadMonotonic(i32* %p) sanitize_memory { +define i32 @AtomicLoadMonotonic(ptr %p) sanitize_memory { entry: - %0 = load atomic i32, i32* %p monotonic, align 16 + %0 = load atomic i32, ptr %p monotonic, align 16 ret i32 %0 } ; CHECK-LABEL: @AtomicLoadMonotonic -; CHECK: load atomic i32, i32* {{.*}} acquire, align 16 -; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16 +; CHECK: load atomic i32, ptr {{.*}} acquire, align 16 +; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, ptr {{.*}}, align 16 ; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls ; CHECK: ret i32 ; atomic load unordered: bump up to load acquire -define i32 @AtomicLoadUnordered(i32* %p) sanitize_memory { +define i32 @AtomicLoadUnordered(ptr %p) sanitize_memory { entry: - %0 = load atomic i32, i32* %p unordered, align 16 + %0 = load atomic i32, ptr %p unordered, align 16 ret i32 %0 } ; CHECK-LABEL: @AtomicLoadUnordered -; CHECK: load atomic i32, i32* {{.*}} acquire, align 16 -; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, i32* {{.*}}, align 16 +; CHECK: load atomic i32, ptr {{.*}} acquire, align 16 +; CHECK: [[SHADOW:%[01-9a-z_]+]] = load i32, ptr {{.*}}, align 16 ; CHECK: store i32 {{.*}}[[SHADOW]], {{.*}} @__msan_retval_tls ; CHECK: ret i32 ; atomic store: preserve alignment, store clean shadow value before app value -define void @AtomicStore(i32* %p, i32 %x) sanitize_memory { +define void @AtomicStore(ptr %p, i32 %x) sanitize_memory { entry: - store atomic i32 %x, i32* %p seq_cst, align 16 + store atomic i32 %x, ptr %p seq_cst, align 16 ret void } ; CHECK-LABEL: @AtomicStore ; CHECK-NOT: @__msan_param_tls -; CHECK: store i32 0, i32* {{.*}}, align 16 -; CHECK: store atomic i32 %x, i32* %p seq_cst, align 16 +; CHECK: store i32 0, ptr {{.*}}, align 16 +; CHECK: store atomic i32 %x, ptr %p seq_cst, align 16 ; CHECK: ret void ; atomic store: preserve alignment, store clean shadow value before app value -define void @AtomicStoreRelease(i32* %p, i32 %x) sanitize_memory { +define void @AtomicStoreRelease(ptr %p, i32 %x) sanitize_memory { entry: - store atomic i32 %x, i32* %p release, align 16 + store atomic i32 %x, ptr %p release, align 16 ret void } ; CHECK-LABEL: @AtomicStoreRelease ; CHECK-NOT: @__msan_param_tls -; CHECK: store i32 0, i32* {{.*}}, align 16 -; CHECK: store atomic i32 %x, i32* %p release, align 16 +; CHECK: store i32 0, ptr {{.*}}, align 16 +; CHECK: store atomic i32 %x, ptr %p release, align 16 ; CHECK: ret void ; atomic store monotonic: bumped up to store release -define void @AtomicStoreMonotonic(i32* %p, i32 %x) sanitize_memory { +define void @AtomicStoreMonotonic(ptr %p, i32 %x) sanitize_memory { entry: - store atomic i32 %x, i32* %p monotonic, align 16 + store atomic i32 %x, ptr %p monotonic, align 16 ret void } ; CHECK-LABEL: @AtomicStoreMonotonic ; CHECK-NOT: @__msan_param_tls -; CHECK: store i32 0, i32* {{.*}}, align 16 -; CHECK: store atomic i32 %x, i32* %p release, align 16 +; CHECK: store i32 0, ptr {{.*}}, align 16 +; CHECK: store atomic i32 %x, ptr %p release, align 16 ; CHECK: ret void ; atomic store unordered: bumped up to store release -define void @AtomicStoreUnordered(i32* %p, i32 %x) sanitize_memory { +define void @AtomicStoreUnordered(ptr %p, i32 %x) sanitize_memory { entry: - store atomic i32 %x, i32* %p unordered, align 16 + store atomic i32 %x, ptr %p unordered, align 16 ret void } ; CHECK-LABEL: @AtomicStoreUnordered ; CHECK-NOT: @__msan_param_tls -; CHECK: store i32 0, i32* {{.*}}, align 16 -; CHECK: store atomic i32 %x, i32* %p release, align 16 +; CHECK: store i32 0, ptr {{.*}}, align 16 +; CHECK: store atomic i32 %x, ptr %p release, align 16 ; CHECK: ret void diff --git a/llvm/test/Instrumentation/MemorySanitizer/attributes.ll b/llvm/test/Instrumentation/MemorySanitizer/attributes.ll --- a/llvm/test/Instrumentation/MemorySanitizer/attributes.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/attributes.ll @@ -7,7 +7,7 @@ declare void @a_() sanitize_memory readnone declare void @b_() sanitize_memory readonly declare void @c_() sanitize_memory writeonly -declare void @d_(i32* %p) sanitize_memory writeonly argmemonly +declare void @d_(ptr %p) sanitize_memory writeonly argmemonly declare void @e_() sanitize_memory speculatable define void @a() sanitize_memory readnone { @@ -31,10 +31,10 @@ ret void } -define void @d(i32* %p) sanitize_memory writeonly argmemonly { +define void @d(ptr %p) sanitize_memory writeonly argmemonly { entry: - call void @d_(i32* %p) - call void @d_(i32* %p) writeonly argmemonly + call void @d_(ptr %p) + call void @d_(ptr %p) writeonly argmemonly ret void } diff --git a/llvm/test/Instrumentation/MemorySanitizer/avx-intrinsics-x86.ll b/llvm/test/Instrumentation/MemorySanitizer/avx-intrinsics-x86.ll --- a/llvm/test/Instrumentation/MemorySanitizer/avx-intrinsics-x86.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/avx-intrinsics-x86.ll @@ -6,12 +6,12 @@ define <4 x double> @test_x86_avx_addsub_pd_256(<4 x double> %a0, <4 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_addsub_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i64> [[_MSPROP]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[RES]] ; %res = call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1] @@ -22,12 +22,12 @@ define <8 x float> @test_x86_avx_addsub_ps_256(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_addsub_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i32> [[_MSPROP]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1] @@ -38,14 +38,14 @@ define <4 x double> @test_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) #0 { ; CHECK-LABEL: @test_x86_avx_blendv_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 64) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], [[TMP3]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], <4 x double> [[A2:%.*]]) -; CHECK-NEXT: store <4 x i64> [[_MSPROP1]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[RES]] ; %res = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) ; <<4 x double>> [#uses=1] @@ -56,14 +56,14 @@ define <8 x float> @test_x86_avx_blendv_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) #0 { ; CHECK-LABEL: @test_x86_avx_blendv_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 64) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[_MSPROP]], [[TMP3]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], <8 x float> [[A2:%.*]]) -; CHECK-NEXT: store <8 x i32> [[_MSPROP1]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) ; <<8 x float>> [#uses=1] @@ -74,14 +74,14 @@ define <4 x double> @test_x86_avx_cmp_pd_256(<4 x double> %a0, <4 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_cmp_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = sext <4 x i1> [[TMP4]] to <4 x i64> ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]], i8 7) -; CHECK-NEXT: store <4 x i64> [[TMP5]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[RES]] ; %res = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> %a0, <4 x double> %a1, i8 7) ; <<4 x double>> [#uses=1] @@ -92,14 +92,14 @@ define <8 x float> @test_x86_avx_cmp_ps_256(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_cmp_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <8 x i32> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = sext <8 x i1> [[TMP4]] to <8 x i32> ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], i8 7) -; CHECK-NEXT: store <8 x i32> [[TMP5]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1] @@ -108,8 +108,8 @@ define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_cmp_ps_256_pseudo_op( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <8 x i32> [[TMP3]], zeroinitializer @@ -239,7 +239,7 @@ ; CHECK-NEXT: [[TMP97:%.*]] = icmp ne <8 x i32> [[TMP96]], zeroinitializer ; CHECK-NEXT: [[TMP98:%.*]] = sext <8 x i1> [[TMP97]] to <8 x i32> ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> [[A0]], <8 x float> [[A32]], i8 31) -; CHECK-NEXT: store <8 x i32> [[TMP98]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP98]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %a2 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 0) ; <<8 x float>> [#uses=1] @@ -281,7 +281,7 @@ define <4 x float> @test_x86_avx_cvt_pd2_ps_256(<4 x double> %a0) #0 { ; CHECK-LABEL: @test_x86_avx_cvt_pd2_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 @@ -291,7 +291,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double> [[A0:%.*]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double> %a0) ; <<4 x float>> [#uses=1] @@ -302,7 +302,7 @@ define <4 x i32> @test_x86_avx_cvt_pd2dq_256(<4 x double> %a0) #0 { ; CHECK-LABEL: @test_x86_avx_cvt_pd2dq_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 @@ -312,7 +312,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double> [[A0:%.*]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1] @@ -323,7 +323,7 @@ define <8 x i32> @test_x86_avx_cvt_ps2dq_256(<8 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_avx_cvt_ps2dq_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i32> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 @@ -333,7 +333,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> [[A0:%.*]]) -; CHECK-NEXT: store <8 x i32> zeroinitializer, <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1] @@ -344,7 +344,7 @@ define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) #0 { ; CHECK-LABEL: @test_x86_avx_cvtt_pd2dq_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 @@ -354,7 +354,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> [[A0:%.*]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1] @@ -365,7 +365,7 @@ define <8 x i32> @test_x86_avx_cvtt_ps2dq_256(<8 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_avx_cvtt_ps2dq_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i32> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 @@ -375,7 +375,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> [[A0:%.*]]) -; CHECK-NEXT: store <8 x i32> zeroinitializer, <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1] @@ -386,8 +386,8 @@ define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_dp_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 0 @@ -400,7 +400,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]], i8 7) -; CHECK-NEXT: store <8 x i32> zeroinitializer, <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1] @@ -411,12 +411,12 @@ define <4 x double> @test_x86_avx_hadd_pd_256(<4 x double> %a0, <4 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_hadd_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i64> [[_MSPROP]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[RES]] ; %res = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1] @@ -427,12 +427,12 @@ define <8 x float> @test_x86_avx_hadd_ps_256(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_hadd_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i32> [[_MSPROP]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1] @@ -443,12 +443,12 @@ define <4 x double> @test_x86_avx_hsub_pd_256(<4 x double> %a0, <4 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_hsub_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i64> [[_MSPROP]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[RES]] ; %res = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1] @@ -459,12 +459,12 @@ define <8 x float> @test_x86_avx_hsub_ps_256(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_hsub_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i32> [[_MSPROP]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1] @@ -473,34 +473,34 @@ declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind readnone -define <32 x i8> @test_x86_avx_ldu_dq_256(i8* %a0) #0 { +define <32 x i8> @test_x86_avx_ldu_dq_256(ptr %a0) #0 { ; CHECK-LABEL: @test_x86_avx_ldu_dq_256( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint i8* [[A0:%.*]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A0:%.*]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 -; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to <32 x i8>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <32 x i8>, <32 x i8>* [[TMP4]], align 1 +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <32 x i8>, ptr [[TMP4]], align 1 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 6: -; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx.ldu.dq.256(i8* [[A0]]) -; CHECK-NEXT: store <32 x i8> [[_MSLD]], <32 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <32 x i8>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx.ldu.dq.256(ptr [[A0]]) +; CHECK-NEXT: store <32 x i8> [[_MSLD]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <32 x i8> [[RES]] ; - %res = call <32 x i8> @llvm.x86.avx.ldu.dq.256(i8* %a0) ; <<32 x i8>> [#uses=1] + %res = call <32 x i8> @llvm.x86.avx.ldu.dq.256(ptr %a0) ; <<32 x i8>> [#uses=1] ret <32 x i8> %res } -declare <32 x i8> @llvm.x86.avx.ldu.dq.256(i8*) nounwind readonly +declare <32 x i8> @llvm.x86.avx.ldu.dq.256(ptr) nounwind readonly -define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x i64> %mask) #0 { +define <2 x double> @test_x86_avx_maskload_pd(ptr %a0, <2 x i64> %mask) #0 { ; CHECK-LABEL: @test_x86_avx_maskload_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i128 @@ -511,20 +511,20 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 5: -; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx.maskload.pd(i8* [[A0:%.*]], <2 x i64> [[MASK:%.*]]) -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx.maskload.pd(ptr [[A0:%.*]], <2 x i64> [[MASK:%.*]]) +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; - %res = call <2 x double> @llvm.x86.avx.maskload.pd(i8* %a0, <2 x i64> %mask) ; <<2 x double>> [#uses=1] + %res = call <2 x double> @llvm.x86.avx.maskload.pd(ptr %a0, <2 x i64> %mask) ; <<2 x double>> [#uses=1] ret <2 x double> %res } -declare <2 x double> @llvm.x86.avx.maskload.pd(i8*, <2 x i64>) nounwind readonly +declare <2 x double> @llvm.x86.avx.maskload.pd(ptr, <2 x i64>) nounwind readonly -define <4 x double> @test_x86_avx_maskload_pd_256(i8* %a0, <4 x i64> %mask) #0 { +define <4 x double> @test_x86_avx_maskload_pd_256(ptr %a0, <4 x i64> %mask) #0 { ; CHECK-LABEL: @test_x86_avx_maskload_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP2]] to i256 @@ -535,20 +535,20 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 5: -; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8* [[A0:%.*]], <4 x i64> [[MASK:%.*]]) -; CHECK-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.maskload.pd.256(ptr [[A0:%.*]], <4 x i64> [[MASK:%.*]]) +; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[RES]] ; - %res = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8* %a0, <4 x i64> %mask) ; <<4 x double>> [#uses=1] + %res = call <4 x double> @llvm.x86.avx.maskload.pd.256(ptr %a0, <4 x i64> %mask) ; <<4 x double>> [#uses=1] ret <4 x double> %res } -declare <4 x double> @llvm.x86.avx.maskload.pd.256(i8*, <4 x i64>) nounwind readonly +declare <4 x double> @llvm.x86.avx.maskload.pd.256(ptr, <4 x i64>) nounwind readonly -define <4 x float> @test_x86_avx_maskload_ps(i8* %a0, <4 x i32> %mask) #0 { +define <4 x float> @test_x86_avx_maskload_ps(ptr %a0, <4 x i32> %mask) #0 { ; CHECK-LABEL: @test_x86_avx_maskload_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 @@ -559,20 +559,20 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 5: -; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx.maskload.ps(i8* [[A0:%.*]], <4 x i32> [[MASK:%.*]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx.maskload.ps(ptr [[A0:%.*]], <4 x i32> [[MASK:%.*]]) +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; - %res = call <4 x float> @llvm.x86.avx.maskload.ps(i8* %a0, <4 x i32> %mask) ; <<4 x float>> [#uses=1] + %res = call <4 x float> @llvm.x86.avx.maskload.ps(ptr %a0, <4 x i32> %mask) ; <<4 x float>> [#uses=1] ret <4 x float> %res } -declare <4 x float> @llvm.x86.avx.maskload.ps(i8*, <4 x i32>) nounwind readonly +declare <4 x float> @llvm.x86.avx.maskload.ps(ptr, <4 x i32>) nounwind readonly -define <8 x float> @test_x86_avx_maskload_ps_256(i8* %a0, <8 x i32> %mask) #0 { +define <8 x float> @test_x86_avx_maskload_ps_256(ptr %a0, <8 x i32> %mask) #0 { ; CHECK-LABEL: @test_x86_avx_maskload_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP2]] to i256 @@ -583,21 +583,21 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 5: -; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8* [[A0:%.*]], <8 x i32> [[MASK:%.*]]) -; CHECK-NEXT: store <8 x i32> zeroinitializer, <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.maskload.ps.256(ptr [[A0:%.*]], <8 x i32> [[MASK:%.*]]) +; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; - %res = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8* %a0, <8 x i32> %mask) ; <<8 x float>> [#uses=1] + %res = call <8 x float> @llvm.x86.avx.maskload.ps.256(ptr %a0, <8 x i32> %mask) ; <<8 x float>> [#uses=1] ret <8 x float> %res } -declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x i32>) nounwind readonly +declare <8 x float> @llvm.x86.avx.maskload.ps.256(ptr, <8 x i32>) nounwind readonly -define void @test_x86_avx_maskstore_pd(i8* %a0, <2 x i64> %mask, <2 x double> %a2) #0 { +define void @test_x86_avx_maskstore_pd(ptr %a0, <2 x i64> %mask, <2 x double> %a2) #0 { ; CHECK-LABEL: @test_x86_avx_maskstore_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i128 @@ -611,20 +611,20 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 7: -; CHECK-NEXT: call void @llvm.x86.avx.maskstore.pd(i8* [[A0:%.*]], <2 x i64> [[MASK:%.*]], <2 x double> [[A2:%.*]]) +; CHECK-NEXT: call void @llvm.x86.avx.maskstore.pd(ptr [[A0:%.*]], <2 x i64> [[MASK:%.*]], <2 x double> [[A2:%.*]]) ; CHECK-NEXT: ret void ; - call void @llvm.x86.avx.maskstore.pd(i8* %a0, <2 x i64> %mask, <2 x double> %a2) + call void @llvm.x86.avx.maskstore.pd(ptr %a0, <2 x i64> %mask, <2 x double> %a2) ret void } -declare void @llvm.x86.avx.maskstore.pd(i8*, <2 x i64>, <2 x double>) nounwind +declare void @llvm.x86.avx.maskstore.pd(ptr, <2 x i64>, <2 x double>) nounwind -define void @test_x86_avx_maskstore_pd_256(i8* %a0, <4 x i64> %mask, <4 x double> %a2) #0 { +define void @test_x86_avx_maskstore_pd_256(ptr %a0, <4 x i64> %mask, <4 x double> %a2) #0 { ; CHECK-LABEL: @test_x86_avx_maskstore_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i256 @@ -638,20 +638,20 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 7: -; CHECK-NEXT: call void @llvm.x86.avx.maskstore.pd.256(i8* [[A0:%.*]], <4 x i64> [[MASK:%.*]], <4 x double> [[A2:%.*]]) +; CHECK-NEXT: call void @llvm.x86.avx.maskstore.pd.256(ptr [[A0:%.*]], <4 x i64> [[MASK:%.*]], <4 x double> [[A2:%.*]]) ; CHECK-NEXT: ret void ; - call void @llvm.x86.avx.maskstore.pd.256(i8* %a0, <4 x i64> %mask, <4 x double> %a2) + call void @llvm.x86.avx.maskstore.pd.256(ptr %a0, <4 x i64> %mask, <4 x double> %a2) ret void } -declare void @llvm.x86.avx.maskstore.pd.256(i8*, <4 x i64>, <4 x double>) nounwind +declare void @llvm.x86.avx.maskstore.pd.256(ptr, <4 x i64>, <4 x double>) nounwind -define void @test_x86_avx_maskstore_ps(i8* %a0, <4 x i32> %mask, <4 x float> %a2) #0 { +define void @test_x86_avx_maskstore_ps(ptr %a0, <4 x i32> %mask, <4 x float> %a2) #0 { ; CHECK-LABEL: @test_x86_avx_maskstore_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 @@ -665,20 +665,20 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 7: -; CHECK-NEXT: call void @llvm.x86.avx.maskstore.ps(i8* [[A0:%.*]], <4 x i32> [[MASK:%.*]], <4 x float> [[A2:%.*]]) +; CHECK-NEXT: call void @llvm.x86.avx.maskstore.ps(ptr [[A0:%.*]], <4 x i32> [[MASK:%.*]], <4 x float> [[A2:%.*]]) ; CHECK-NEXT: ret void ; - call void @llvm.x86.avx.maskstore.ps(i8* %a0, <4 x i32> %mask, <4 x float> %a2) + call void @llvm.x86.avx.maskstore.ps(ptr %a0, <4 x i32> %mask, <4 x float> %a2) ret void } -declare void @llvm.x86.avx.maskstore.ps(i8*, <4 x i32>, <4 x float>) nounwind +declare void @llvm.x86.avx.maskstore.ps(ptr, <4 x i32>, <4 x float>) nounwind -define void @test_x86_avx_maskstore_ps_256(i8* %a0, <8 x i32> %mask, <8 x float> %a2) #0 { +define void @test_x86_avx_maskstore_ps_256(ptr %a0, <8 x i32> %mask, <8 x float> %a2) #0 { ; CHECK-LABEL: @test_x86_avx_maskstore_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i256 @@ -692,23 +692,23 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 7: -; CHECK-NEXT: call void @llvm.x86.avx.maskstore.ps.256(i8* [[A0:%.*]], <8 x i32> [[MASK:%.*]], <8 x float> [[A2:%.*]]) +; CHECK-NEXT: call void @llvm.x86.avx.maskstore.ps.256(ptr [[A0:%.*]], <8 x i32> [[MASK:%.*]], <8 x float> [[A2:%.*]]) ; CHECK-NEXT: ret void ; - call void @llvm.x86.avx.maskstore.ps.256(i8* %a0, <8 x i32> %mask, <8 x float> %a2) + call void @llvm.x86.avx.maskstore.ps.256(ptr %a0, <8 x i32> %mask, <8 x float> %a2) ret void } -declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x i32>, <8 x float>) nounwind +declare void @llvm.x86.avx.maskstore.ps.256(ptr, <8 x i32>, <8 x float>) nounwind define <4 x double> @test_x86_avx_max_pd_256(<4 x double> %a0, <4 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_max_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.max.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i64> [[_MSPROP]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[RES]] ; %res = call <4 x double> @llvm.x86.avx.max.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1] @@ -719,12 +719,12 @@ define <8 x float> @test_x86_avx_max_ps_256(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_max_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i32> [[_MSPROP]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1] @@ -735,12 +735,12 @@ define <4 x double> @test_x86_avx_min_pd_256(<4 x double> %a0, <4 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_min_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.min.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i64> [[_MSPROP]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[RES]] ; %res = call <4 x double> @llvm.x86.avx.min.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1] @@ -751,12 +751,12 @@ define <8 x float> @test_x86_avx_min_ps_256(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_min_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i32> [[_MSPROP]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1] @@ -767,7 +767,7 @@ define i32 @test_x86_avx_movmsk_pd_256(<4 x double> %a0) #0 { ; CHECK-LABEL: @test_x86_avx_movmsk_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 @@ -777,7 +777,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> [[A0:%.*]]) -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %a0) ; [#uses=1] @@ -788,7 +788,7 @@ define i32 @test_x86_avx_movmsk_ps_256(<8 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_avx_movmsk_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i32> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 @@ -798,7 +798,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> [[A0:%.*]]) -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %a0) ; [#uses=1] @@ -809,15 +809,15 @@ define i32 @test_x86_avx_ptestc_256(<4 x i64> %a0, <4 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_ptestc_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 ; CHECK-NEXT: [[TMP6:%.*]] = zext i4 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> [[A0:%.*]], <4 x i64> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a0, <4 x i64> %a1) ; [#uses=1] @@ -828,15 +828,15 @@ define i32 @test_x86_avx_ptestnzc_256(<4 x i64> %a0, <4 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_ptestnzc_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 ; CHECK-NEXT: [[TMP6:%.*]] = zext i4 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> [[A0:%.*]], <4 x i64> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %a0, <4 x i64> %a1) ; [#uses=1] @@ -847,15 +847,15 @@ define i32 @test_x86_avx_ptestz_256(<4 x i64> %a0, <4 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_ptestz_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 ; CHECK-NEXT: [[TMP6:%.*]] = zext i4 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> [[A0:%.*]], <4 x i64> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a0, <4 x i64> %a1) ; [#uses=1] @@ -866,10 +866,10 @@ define <8 x float> @test_x86_avx_rcp_ps_256(<8 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_avx_rcp_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float> [[A0:%.*]]) -; CHECK-NEXT: store <8 x i32> [[TMP1]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1] @@ -880,7 +880,7 @@ define <4 x double> @test_x86_avx_round_pd_256(<4 x double> %a0) #0 { ; CHECK-LABEL: @test_x86_avx_round_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 @@ -890,7 +890,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.round.pd.256(<4 x double> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[RES]] ; %res = call <4 x double> @llvm.x86.avx.round.pd.256(<4 x double> %a0, i32 7) ; <<4 x double>> [#uses=1] @@ -901,7 +901,7 @@ define <8 x float> @test_x86_avx_round_ps_256(<8 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_avx_round_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i32> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 @@ -911,7 +911,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <8 x i32> zeroinitializer, <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> %a0, i32 7) ; <<8 x float>> [#uses=1] @@ -922,10 +922,10 @@ define <8 x float> @test_x86_avx_rsqrt_ps_256(<8 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_avx_rsqrt_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float> [[A0:%.*]]) -; CHECK-NEXT: store <8 x i32> [[TMP1]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1] @@ -935,8 +935,8 @@ define <2 x double> @test_x86_avx_vpermilvar_pd(<2 x double> %a0, <2 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vpermilvar_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 @@ -949,7 +949,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> [[A0:%.*]], <2 x i64> [[A1:%.*]]) -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; %res = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> %a1) ; <<2 x double>> [#uses=1] @@ -960,8 +960,8 @@ define <4 x double> @test_x86_avx_vpermilvar_pd_256(<4 x double> %a0, <4 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vpermilvar_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 0 @@ -974,7 +974,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> [[A0:%.*]], <4 x i64> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[RES]] ; %res = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> %a1) ; <<4 x double>> [#uses=1] @@ -984,7 +984,7 @@ define <4 x double> @test_x86_avx_vpermilvar_pd_256_2(<4 x double> %a0) #0 { ; CHECK-LABEL: @test_x86_avx_vpermilvar_pd_256_2( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 @@ -994,7 +994,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> [[A0:%.*]], <4 x i64> ) -; CHECK-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[RES]] ; %res = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> ) ; <<4 x double>> [#uses=1] @@ -1003,8 +1003,8 @@ define <4 x float> @test_x86_avx_vpermilvar_ps(<4 x float> %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vpermilvar_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 @@ -1017,16 +1017,16 @@ ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> [[A0:%.*]], <4 x i32> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a1) ; <<4 x float>> [#uses=1] ret <4 x float> %res } -define <4 x float> @test_x86_avx_vpermilvar_ps_load(<4 x float> %a0, <4 x i32>* %a1) #0 { +define <4 x float> @test_x86_avx_vpermilvar_ps_load(<4 x float> %a0, ptr %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vpermilvar_ps_load( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] @@ -1034,11 +1034,11 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: -; CHECK-NEXT: [[A2:%.*]] = load <4 x i32>, <4 x i32>* [[A1:%.*]], align 16 -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <4 x i32>* [[A1]] to i64 +; CHECK-NEXT: [[A2:%.*]] = load <4 x i32>, ptr [[A1:%.*]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A1]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to <4 x i32>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP7]], align 16 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16 ; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP8]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i32> [[_MSLD]] to i128 @@ -1050,10 +1050,10 @@ ; CHECK-NEXT: unreachable ; CHECK: 11: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> [[A0:%.*]], <4 x i32> [[A2]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; - %a2 = load <4 x i32>, <4 x i32>* %a1 + %a2 = load <4 x i32>, ptr %a1 %res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a2) ; <<4 x float>> [#uses=1] ret <4 x float> %res } @@ -1062,8 +1062,8 @@ define <8 x float> @test_x86_avx_vpermilvar_ps_256(<8 x float> %a0, <8 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vpermilvar_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 0 @@ -1076,7 +1076,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> [[A0:%.*]], <8 x i32> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i32> zeroinitializer, <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> %a1) ; <<8 x float>> [#uses=1] @@ -1087,15 +1087,15 @@ define i32 @test_x86_avx_vtestc_pd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vtestc_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i1> [[TMP4]] to i2 ; CHECK-NEXT: [[TMP6:%.*]] = zext i2 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestc.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.vtestc.pd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -1106,15 +1106,15 @@ define i32 @test_x86_avx_vtestc_pd_256(<4 x double> %a0, <4 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vtestc_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 ; CHECK-NEXT: [[TMP6:%.*]] = zext i4 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestc.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.vtestc.pd.256(<4 x double> %a0, <4 x double> %a1) ; [#uses=1] @@ -1125,15 +1125,15 @@ define i32 @test_x86_avx_vtestc_ps(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vtestc_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 ; CHECK-NEXT: [[TMP6:%.*]] = zext i4 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestc.ps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.vtestc.ps(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -1144,15 +1144,15 @@ define i32 @test_x86_avx_vtestc_ps_256(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vtestc_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <8 x i32> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i1> [[TMP4]] to i8 ; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestc.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.vtestc.ps.256(<8 x float> %a0, <8 x float> %a1) ; [#uses=1] @@ -1163,15 +1163,15 @@ define i32 @test_x86_avx_vtestnzc_pd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vtestnzc_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i1> [[TMP4]] to i2 ; CHECK-NEXT: [[TMP6:%.*]] = zext i2 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -1182,15 +1182,15 @@ define i32 @test_x86_avx_vtestnzc_pd_256(<4 x double> %a0, <4 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vtestnzc_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 ; CHECK-NEXT: [[TMP6:%.*]] = zext i4 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %a0, <4 x double> %a1) ; [#uses=1] @@ -1201,15 +1201,15 @@ define i32 @test_x86_avx_vtestnzc_ps(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vtestnzc_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 ; CHECK-NEXT: [[TMP6:%.*]] = zext i4 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -1220,15 +1220,15 @@ define i32 @test_x86_avx_vtestnzc_ps_256(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vtestnzc_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <8 x i32> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i1> [[TMP4]] to i8 ; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %a0, <8 x float> %a1) ; [#uses=1] @@ -1239,15 +1239,15 @@ define i32 @test_x86_avx_vtestz_pd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vtestz_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i1> [[TMP4]] to i2 ; CHECK-NEXT: [[TMP6:%.*]] = zext i2 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -1258,15 +1258,15 @@ define i32 @test_x86_avx_vtestz_pd_256(<4 x double> %a0, <4 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vtestz_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 ; CHECK-NEXT: [[TMP6:%.*]] = zext i4 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> [[A0:%.*]], <4 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %a0, <4 x double> %a1) ; [#uses=1] @@ -1277,15 +1277,15 @@ define i32 @test_x86_avx_vtestz_ps(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vtestz_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 ; CHECK-NEXT: [[TMP6:%.*]] = zext i4 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -1296,15 +1296,15 @@ define i32 @test_x86_avx_vtestz_ps_256(<8 x float> %a0, <8 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_avx_vtestz_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <8 x i32> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i1> [[TMP4]] to i8 ; CHECK-NEXT: [[TMP6:%.*]] = zext i8 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> [[A0:%.*]], <8 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %a0, <8 x float> %a1) ; [#uses=1] @@ -1336,99 +1336,96 @@ } declare void @llvm.x86.avx.vzeroupper() nounwind -define void @movnt_dq(i8* %p, <2 x i64> %a1) nounwind #0 { +define void @movnt_dq(ptr %p, <2 x i64> %a1) nounwind #0 { ; CHECK-LABEL: @movnt_dq( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[A2:%.*]] = add <2 x i64> [[A1:%.*]], ; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[_MSPROP]], <2 x i64> , <4 x i32> ; CHECK-NEXT: [[A3:%.*]] = shufflevector <2 x i64> [[A2]], <2 x i64> undef, <4 x i32> -; CHECK-NEXT: [[CAST:%.*]] = bitcast i8* [[P:%.*]] to <4 x i64>* ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <4 x i64>* [[CAST]] to i64 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to <4 x i64>* -; CHECK-NEXT: store <4 x i64> [[_MSPROP1]], <4 x i64>* [[TMP7]], align 32 -; CHECK-NEXT: store <4 x i64> [[A3]], <4 x i64>* [[CAST]], align 32, !nontemporal !1 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: store <4 x i64> [[_MSPROP1]], ptr [[TMP7]], align 32 +; CHECK-NEXT: store <4 x i64> [[A3]], ptr [[P]], align 32, !nontemporal !1 ; CHECK-NEXT: ret void ; %a2 = add <2 x i64> %a1, %a3 = shufflevector <2 x i64> %a2, <2 x i64> undef, <4 x i32> - tail call void @llvm.x86.avx.movnt.dq.256(i8* %p, <4 x i64> %a3) nounwind + tail call void @llvm.x86.avx.movnt.dq.256(ptr %p, <4 x i64> %a3) nounwind ret void } -declare void @llvm.x86.avx.movnt.dq.256(i8*, <4 x i64>) nounwind +declare void @llvm.x86.avx.movnt.dq.256(ptr, <4 x i64>) nounwind -define void @movnt_ps(i8* %p, <8 x float> %a) nounwind #0 { +define void @movnt_ps(ptr %p, <8 x float> %a) nounwind #0 { ; CHECK-LABEL: @movnt_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[CAST:%.*]] = bitcast i8* [[P:%.*]] to <8 x float>* ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <8 x float>* [[CAST]] to i64 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to <8 x i32>* -; CHECK-NEXT: store <8 x i32> [[TMP2]], <8 x i32>* [[TMP7]], align 32 -; CHECK-NEXT: store <8 x float> [[A:%.*]], <8 x float>* [[CAST]], align 32, !nontemporal !1 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: store <8 x i32> [[TMP2]], ptr [[TMP7]], align 32 +; CHECK-NEXT: store <8 x float> [[A:%.*]], ptr [[P]], align 32, !nontemporal !1 ; CHECK-NEXT: ret void ; - tail call void @llvm.x86.avx.movnt.ps.256(i8* %p, <8 x float> %a) nounwind + tail call void @llvm.x86.avx.movnt.ps.256(ptr %p, <8 x float> %a) nounwind ret void } -declare void @llvm.x86.avx.movnt.ps.256(i8*, <8 x float>) nounwind +declare void @llvm.x86.avx.movnt.ps.256(ptr, <8 x float>) nounwind -define void @movnt_pd(i8* %p, <4 x double> %a1) nounwind #0 { +define void @movnt_pd(ptr %p, <4 x double> %a1) nounwind #0 { ; add operation forces the execution domain. ; CHECK-LABEL: @movnt_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[A2:%.*]] = fadd <4 x double> [[A1:%.*]], zeroinitializer -; CHECK-NEXT: [[CAST:%.*]] = bitcast i8* [[P:%.*]] to <4 x double>* ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]] ; CHECK-NEXT: unreachable ; CHECK: 4: -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <4 x double>* [[CAST]] to i64 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to <4 x i64>* -; CHECK-NEXT: store <4 x i64> [[_MSPROP]], <4 x i64>* [[TMP7]], align 32 -; CHECK-NEXT: store <4 x double> [[A2]], <4 x double>* [[CAST]], align 32, !nontemporal !1 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: store <4 x i64> [[_MSPROP]], ptr [[TMP7]], align 32 +; CHECK-NEXT: store <4 x double> [[A2]], ptr [[P]], align 32, !nontemporal !1 ; CHECK-NEXT: ret void ; %a2 = fadd <4 x double> %a1, - tail call void @llvm.x86.avx.movnt.pd.256(i8* %p, <4 x double> %a2) nounwind + tail call void @llvm.x86.avx.movnt.pd.256(ptr %p, <4 x double> %a2) nounwind ret void } -declare void @llvm.x86.avx.movnt.pd.256(i8*, <4 x double>) nounwind +declare void @llvm.x86.avx.movnt.pd.256(ptr, <4 x double>) nounwind define <2 x i64> @test_x86_pclmulqdq(<2 x i64> %a0, <2 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_pclmulqdq( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP3]], [[TMP4]] ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]], i8 0) -; CHECK-NEXT: store <2 x i64> [[_MSPROP]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %res = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a0, <2 x i64> %a1, i8 0) ; <<2 x i64>> [#uses=1] diff --git a/llvm/test/Instrumentation/MemorySanitizer/avx2-intrinsics-x86.ll b/llvm/test/Instrumentation/MemorySanitizer/avx2-intrinsics-x86.ll --- a/llvm/test/Instrumentation/MemorySanitizer/avx2-intrinsics-x86.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/avx2-intrinsics-x86.ll @@ -6,8 +6,8 @@ define <16 x i16> @test_x86_avx2_packssdw(<8 x i32> %a0, <8 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_packssdw( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i32> @@ -15,7 +15,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i32> ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[TMP4]], <8 x i32> [[TMP6]]) ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i16> [[_MSPROP_VECTOR_PACK]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %a0, <8 x i32> %a1) ; <<16 x i16>> [#uses=1] @@ -29,7 +29,7 @@ ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> zeroinitializer) ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> ) -; CHECK-NEXT: store <16 x i16> [[_MSPROP_VECTOR_PACK]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> ) @@ -39,8 +39,8 @@ define <32 x i8> @test_x86_avx2_packsswb(<16 x i16> %a0, <16 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_packsswb( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <16 x i16> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <16 x i1> [[TMP3]] to <16 x i16> @@ -48,7 +48,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = sext <16 x i1> [[TMP5]] to <16 x i16> ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> [[TMP4]], <16 x i16> [[TMP6]]) ; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <32 x i8> [[_MSPROP_VECTOR_PACK]], <32 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <32 x i8>*), align 8 +; CHECK-NEXT: store <32 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <32 x i8> [[RES]] ; %res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> %a0, <16 x i16> %a1) ; <<32 x i8>> [#uses=1] @@ -62,7 +62,7 @@ ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> zeroinitializer, <16 x i16> zeroinitializer) ; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> , <16 x i16> zeroinitializer) -; CHECK-NEXT: store <32 x i8> [[_MSPROP_VECTOR_PACK]], <32 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <32 x i8>*), align 8 +; CHECK-NEXT: store <32 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <32 x i8> [[RES]] ; %res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> , <16 x i16> zeroinitializer) @@ -72,8 +72,8 @@ define <32 x i8> @test_x86_avx2_packuswb(<16 x i16> %a0, <16 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_packuswb( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <16 x i16> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <16 x i1> [[TMP3]] to <16 x i16> @@ -81,7 +81,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = sext <16 x i1> [[TMP5]] to <16 x i16> ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> [[TMP4]], <16 x i16> [[TMP6]]) ; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <32 x i8> [[_MSPROP_VECTOR_PACK]], <32 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <32 x i8>*), align 8 +; CHECK-NEXT: store <32 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <32 x i8> [[RES]] ; %res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %a0, <16 x i16> %a1) ; <<32 x i8>> [#uses=1] @@ -95,7 +95,7 @@ ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> zeroinitializer, <16 x i16> zeroinitializer) ; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> , <16 x i16> zeroinitializer) -; CHECK-NEXT: store <32 x i8> [[_MSPROP_VECTOR_PACK]], <32 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <32 x i8>*), align 8 +; CHECK-NEXT: store <32 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <32 x i8> [[RES]] ; %res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> , <16 x i16> zeroinitializer) @@ -105,12 +105,12 @@ define <32 x i8> @test_x86_avx2_pavg_b(<32 x i8> %a0, <32 x i8> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_pavg_b( -; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, <32 x i8>* bitcast ([100 x i64]* @__msan_param_tls to <32 x i8>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <32 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <32 x i8> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.pavg.b(<32 x i8> [[A0:%.*]], <32 x i8> [[A1:%.*]]) -; CHECK-NEXT: store <32 x i8> [[_MSPROP]], <32 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <32 x i8>*), align 8 +; CHECK-NEXT: store <32 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <32 x i8> [[RES]] ; %res = call <32 x i8> @llvm.x86.avx2.pavg.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1] @@ -121,12 +121,12 @@ define <16 x i16> @test_x86_avx2_pavg_w(<16 x i16> %a0, <16 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_pavg_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pavg.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i16> [[_MSPROP]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.pavg.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1] @@ -137,15 +137,15 @@ define <8 x i32> @test_x86_avx2_pmadd_wd(<16 x i16> %a0, <16 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_pmadd_wd( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i16> [[TMP3]] to <8 x i32> ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <8 x i32> [[TMP4]], zeroinitializer ; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i32> ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i32> [[TMP6]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.pmadd.wd(<16 x i16> %a0, <16 x i16> %a1) ; <<8 x i32>> [#uses=1] @@ -156,17 +156,17 @@ define i32 @test_x86_avx2_pmovmskb(<32 x i8> %a0) #0 { ; CHECK-LABEL: @test_x86_avx2_pmovmskb( -; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, <32 x i8>* bitcast ([100 x i64]* @__msan_param_tls to <32 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <32 x i8> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP2]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0:![0-9]+]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7:[0-9]+]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6:[0-9]+]] ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.avx2.pmovmskb(<32 x i8> [[A0:%.*]]) -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.avx2.pmovmskb(<32 x i8> %a0) ; [#uses=1] @@ -177,12 +177,12 @@ define <16 x i16> @test_x86_avx2_pmulh_w(<16 x i16> %a0, <16 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_pmulh_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i16> [[_MSPROP]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.pmulh.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1] @@ -193,12 +193,12 @@ define <16 x i16> @test_x86_avx2_pmulhu_w(<16 x i16> %a0, <16 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_pmulhu_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i16> [[_MSPROP]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.pmulhu.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1] @@ -209,8 +209,8 @@ define <4 x i64> @test_x86_avx2_psad_bw(<32 x i8> %a0, <32 x i8> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psad_bw( -; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, <32 x i8>* bitcast ([100 x i64]* @__msan_param_tls to <32 x i8>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <32 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <32 x i8> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <32 x i8> [[TMP3]] to <4 x i64> @@ -218,7 +218,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i1> [[TMP5]] to <4 x i64> ; CHECK-NEXT: [[TMP7:%.*]] = lshr <4 x i64> [[TMP6]], ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> [[A0:%.*]], <32 x i8> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i64> [[TMP7]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[TMP7]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i64> [[RES]] ; %res = call <4 x i64> @llvm.x86.avx2.psad.bw(<32 x i8> %a0, <32 x i8> %a1) ; <<4 x i64>> [#uses=1] @@ -229,8 +229,8 @@ define <8 x i32> @test_x86_avx2_psll_d(<8 x i32> %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psll_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -240,7 +240,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> [[TMP1]], <4 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i32> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> [[A0:%.*]], <4 x i32> [[A1]]) -; CHECK-NEXT: store <8 x i32> [[TMP9]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1] @@ -251,8 +251,8 @@ define <4 x i64> @test_x86_avx2_psll_q(<4 x i64> %a0, <2 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psll_q( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -262,7 +262,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> [[TMP1]], <2 x i64> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i64> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> [[A0:%.*]], <2 x i64> [[A1]]) -; CHECK-NEXT: store <4 x i64> [[TMP9]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i64> [[RES]] ; %res = call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1] @@ -273,8 +273,8 @@ define <16 x i16> @test_x86_avx2_psll_w(<16 x i16> %a0, <8 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psll_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -284,7 +284,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> [[TMP1]], <8 x i16> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> [[A0:%.*]], <8 x i16> [[A1]]) -; CHECK-NEXT: store <16 x i16> [[TMP9]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1] @@ -295,12 +295,12 @@ define <8 x i32> @test_x86_avx2_pslli_d(<8 x i32> %a0) #0 { ; CHECK-LABEL: @test_x86_avx2_pslli_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <8 x i32> [[TMP3]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1] @@ -311,12 +311,12 @@ define <4 x i64> @test_x86_avx2_pslli_q(<4 x i64> %a0) #0 { ; CHECK-LABEL: @test_x86_avx2_pslli_q( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i64> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <4 x i64> [[TMP3]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i64> [[RES]] ; %res = call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1] @@ -327,12 +327,12 @@ define <16 x i16> @test_x86_avx2_pslli_w(<16 x i16> %a0) #0 { ; CHECK-LABEL: @test_x86_avx2_pslli_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i16> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <16 x i16> [[TMP3]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1] @@ -343,8 +343,8 @@ define <8 x i32> @test_x86_avx2_psra_d(<8 x i32> %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psra_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -354,7 +354,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> [[TMP1]], <4 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i32> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> [[A0:%.*]], <4 x i32> [[A1]]) -; CHECK-NEXT: store <8 x i32> [[TMP9]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1] @@ -365,8 +365,8 @@ define <16 x i16> @test_x86_avx2_psra_w(<16 x i16> %a0, <8 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psra_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -376,7 +376,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> [[TMP1]], <8 x i16> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> [[A0:%.*]], <8 x i16> [[A1]]) -; CHECK-NEXT: store <16 x i16> [[TMP9]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1] @@ -387,12 +387,12 @@ define <8 x i32> @test_x86_avx2_psrai_d(<8 x i32> %a0) #0 { ; CHECK-LABEL: @test_x86_avx2_psrai_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <8 x i32> [[TMP3]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1] @@ -403,12 +403,12 @@ define <16 x i16> @test_x86_avx2_psrai_w(<16 x i16> %a0) #0 { ; CHECK-LABEL: @test_x86_avx2_psrai_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i16> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <16 x i16> [[TMP3]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1] @@ -419,8 +419,8 @@ define <8 x i32> @test_x86_avx2_psrl_d(<8 x i32> %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psrl_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -430,7 +430,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> [[TMP1]], <4 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i32> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> [[A0:%.*]], <4 x i32> [[A1]]) -; CHECK-NEXT: store <8 x i32> [[TMP9]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %a0, <4 x i32> %a1) ; <<8 x i32>> [#uses=1] @@ -441,8 +441,8 @@ define <4 x i64> @test_x86_avx2_psrl_q(<4 x i64> %a0, <2 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psrl_q( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -452,7 +452,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> [[TMP1]], <2 x i64> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i64> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> [[A0:%.*]], <2 x i64> [[A1]]) -; CHECK-NEXT: store <4 x i64> [[TMP9]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i64> [[RES]] ; %res = call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %a0, <2 x i64> %a1) ; <<4 x i64>> [#uses=1] @@ -463,8 +463,8 @@ define <16 x i16> @test_x86_avx2_psrl_w(<16 x i16> %a0, <8 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psrl_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -474,7 +474,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> [[TMP1]], <8 x i16> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i16> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> [[A0:%.*]], <8 x i16> [[A1]]) -; CHECK-NEXT: store <16 x i16> [[TMP9]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1] @@ -483,22 +483,22 @@ declare <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16>, <8 x i16>) nounwind readnone -define <16 x i16> @test_x86_avx2_psrl_w_load(<16 x i16> %a0, <8 x i16>* %p) #0 { +define <16 x i16> @test_x86_avx2_psrl_w_load(<16 x i16> %a0, ptr %p) #0 { ; CHECK-LABEL: @test_x86_avx2_psrl_w_load( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to i64*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: -; CHECK-NEXT: [[A1:%.*]] = load <8 x i16>, <8 x i16>* [[P:%.*]], align 16 -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <8 x i16>* [[P]] to i64 +; CHECK-NEXT: [[A1:%.*]] = load <8 x i16>, ptr [[P:%.*]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to <8 x i16>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, <8 x i16>* [[TMP7]], align 16 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16 ; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[_MSLD]] to i128 ; CHECK-NEXT: [[TMP9:%.*]] = trunc i128 [[TMP8]] to i64 ; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i64 [[TMP9]], 0 @@ -507,10 +507,10 @@ ; CHECK-NEXT: [[TMP13:%.*]] = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> [[TMP2]], <8 x i16> [[A1]]) ; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i16> [[TMP13]], [[TMP12]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> [[A0:%.*]], <8 x i16> [[A1]]) -; CHECK-NEXT: store <16 x i16> [[TMP14]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[TMP14]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; - %a1 = load <8 x i16>, <8 x i16>* %p + %a1 = load <8 x i16>, ptr %p %res = call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %a0, <8 x i16> %a1) ; <<16 x i16>> [#uses=1] ret <16 x i16> %res } @@ -518,12 +518,12 @@ define <8 x i32> @test_x86_avx2_psrli_d(<8 x i32> %a0) #0 { ; CHECK-LABEL: @test_x86_avx2_psrli_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <8 x i32> [[TMP3]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %a0, i32 7) ; <<8 x i32>> [#uses=1] @@ -534,12 +534,12 @@ define <4 x i64> @test_x86_avx2_psrli_q(<4 x i64> %a0) #0 { ; CHECK-LABEL: @test_x86_avx2_psrli_q( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i64> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <4 x i64> [[TMP3]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i64> [[RES]] ; %res = call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %a0, i32 7) ; <<4 x i64>> [#uses=1] @@ -550,12 +550,12 @@ define <16 x i16> @test_x86_avx2_psrli_w(<16 x i16> %a0) #0 { ; CHECK-LABEL: @test_x86_avx2_psrli_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i16> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <16 x i16> [[TMP3]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %a0, i32 7) ; <<16 x i16>> [#uses=1] @@ -566,12 +566,12 @@ define <8 x i32> @test_x86_avx2_phadd_d(<8 x i32> %a0, <8 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_phadd_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i32> [[_MSPROP]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.phadd.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1] @@ -582,12 +582,12 @@ define <16 x i16> @test_x86_avx2_phadd_sw(<16 x i16> %a0, <16 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_phadd_sw( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i16> [[_MSPROP]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.phadd.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1] @@ -598,12 +598,12 @@ define <16 x i16> @test_x86_avx2_phadd_w(<16 x i16> %a0, <16 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_phadd_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i16> [[_MSPROP]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.phadd.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1] @@ -614,12 +614,12 @@ define <8 x i32> @test_x86_avx2_phsub_d(<8 x i32> %a0, <8 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_phsub_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i32> [[_MSPROP]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.phsub.d(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1] @@ -630,12 +630,12 @@ define <16 x i16> @test_x86_avx2_phsub_sw(<16 x i16> %a0, <16 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_phsub_sw( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i16> [[_MSPROP]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.phsub.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1] @@ -646,12 +646,12 @@ define <16 x i16> @test_x86_avx2_phsub_w(<16 x i16> %a0, <16 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_phsub_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i16> [[_MSPROP]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.phsub.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1] @@ -662,15 +662,15 @@ define <16 x i16> @test_x86_avx2_pmadd_ub_sw(<32 x i8> %a0, <32 x i8> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_pmadd_ub_sw( -; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, <32 x i8>* bitcast ([100 x i64]* @__msan_param_tls to <32 x i8>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <32 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <32 x i8> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <32 x i8> [[TMP3]] to <16 x i16> ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <16 x i16> [[TMP4]], zeroinitializer ; CHECK-NEXT: [[TMP6:%.*]] = sext <16 x i1> [[TMP5]] to <16 x i16> ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> [[A0:%.*]], <32 x i8> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i16> [[TMP6]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i16>> [#uses=1] @@ -678,43 +678,43 @@ } declare <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8>, <32 x i8>) nounwind readnone -define <16 x i16> @test_x86_avx2_pmadd_ub_sw_load_op0(<32 x i8>* %ptr, <32 x i8> %a1) #0 { +define <16 x i16> @test_x86_avx2_pmadd_ub_sw_load_op0(ptr %ptr, <32 x i8> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_pmadd_ub_sw_load_op0( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <32 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: -; CHECK-NEXT: [[A0:%.*]] = load <32 x i8>, <32 x i8>* [[PTR:%.*]], align 32 -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <32 x i8>* [[PTR]] to i64 +; CHECK-NEXT: [[A0:%.*]] = load <32 x i8>, ptr [[PTR:%.*]], align 32 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[PTR]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to <32 x i8>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <32 x i8>, <32 x i8>* [[TMP7]], align 32 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <32 x i8>, ptr [[TMP7]], align 32 ; CHECK-NEXT: [[TMP8:%.*]] = or <32 x i8> [[_MSLD]], [[TMP2]] ; CHECK-NEXT: [[TMP9:%.*]] = bitcast <32 x i8> [[TMP8]] to <16 x i16> ; CHECK-NEXT: [[TMP10:%.*]] = icmp ne <16 x i16> [[TMP9]], zeroinitializer ; CHECK-NEXT: [[TMP11:%.*]] = sext <16 x i1> [[TMP10]] to <16 x i16> ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> [[A0]], <32 x i8> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i16> [[TMP11]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[TMP11]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; - %a0 = load <32 x i8>, <32 x i8>* %ptr + %a0 = load <32 x i8>, ptr %ptr %res = call <16 x i16> @llvm.x86.avx2.pmadd.ub.sw(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i16>> [#uses=1] ret <16 x i16> %res } define <16 x i16> @test_x86_avx2_pmul_hr_sw(<16 x i16> %a0, <16 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_pmul_hr_sw( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i16> [[_MSPROP]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.pmul.hr.sw(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1] @@ -725,12 +725,12 @@ define <32 x i8> @test_x86_avx2_pshuf_b(<32 x i8> %a0, <32 x i8> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_pshuf_b( -; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, <32 x i8>* bitcast ([100 x i64]* @__msan_param_tls to <32 x i8>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <32 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <32 x i8> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> [[A0:%.*]], <32 x i8> [[A1:%.*]]) -; CHECK-NEXT: store <32 x i8> [[_MSPROP]], <32 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <32 x i8>*), align 8 +; CHECK-NEXT: store <32 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <32 x i8> [[RES]] ; %res = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -741,12 +741,12 @@ define <32 x i8> @test_x86_avx2_psign_b(<32 x i8> %a0, <32 x i8> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psign_b( -; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, <32 x i8>* bitcast ([100 x i64]* @__msan_param_tls to <32 x i8>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <32 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <32 x i8> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8> [[A0:%.*]], <32 x i8> [[A1:%.*]]) -; CHECK-NEXT: store <32 x i8> [[_MSPROP]], <32 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <32 x i8>*), align 8 +; CHECK-NEXT: store <32 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <32 x i8> [[RES]] ; %res = call <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8> %a0, <32 x i8> %a1) ; <<32 x i8>> [#uses=1] @@ -757,12 +757,12 @@ define <8 x i32> @test_x86_avx2_psign_d(<8 x i32> %a0, <8 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psign_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i32> [[_MSPROP]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32> %a0, <8 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -773,12 +773,12 @@ define <16 x i16> @test_x86_avx2_psign_w(<16 x i16> %a0, <16 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psign_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i16> [[_MSPROP]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16> %a0, <16 x i16> %a1) ; <<16 x i16>> [#uses=1] @@ -789,8 +789,8 @@ define <16 x i16> @test_x86_avx2_mpsadbw(<32 x i8> %a0, <32 x i8> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_mpsadbw( -; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, <32 x i8>* bitcast ([100 x i64]* @__msan_param_tls to <32 x i8>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <32 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <32 x i8> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 0 @@ -799,11 +799,11 @@ ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> [[A0:%.*]], <32 x i8> [[A1:%.*]], i8 7) -; CHECK-NEXT: store <16 x i16> zeroinitializer, <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %a0, <32 x i8> %a1, i8 7) ; <<16 x i16>> [#uses=1] @@ -811,22 +811,22 @@ } declare <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8>, <32 x i8>, i8) nounwind readnone -define <16 x i16> @test_x86_avx2_mpsadbw_load_op0(<32 x i8>* %ptr, <32 x i8> %a1) #0 { +define <16 x i16> @test_x86_avx2_mpsadbw_load_op0(ptr %ptr, <32 x i8> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_mpsadbw_load_op0( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <32 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] ; CHECK: 3: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: -; CHECK-NEXT: [[A0:%.*]] = load <32 x i8>, <32 x i8>* [[PTR:%.*]], align 32 -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <32 x i8>* [[PTR]] to i64 +; CHECK-NEXT: [[A0:%.*]] = load <32 x i8>, ptr [[PTR:%.*]], align 32 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[PTR]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to <32 x i8>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <32 x i8>, <32 x i8>* [[TMP7]], align 32 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <32 x i8>, ptr [[TMP7]], align 32 ; CHECK-NEXT: [[TMP8:%.*]] = bitcast <32 x i8> [[_MSLD]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP8]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = bitcast <32 x i8> [[TMP2]] to i256 @@ -834,22 +834,22 @@ ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF0]] ; CHECK: 10: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 11: ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> [[A0]], <32 x i8> [[A1:%.*]], i8 7) -; CHECK-NEXT: store <16 x i16> zeroinitializer, <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; - %a0 = load <32 x i8>, <32 x i8>* %ptr + %a0 = load <32 x i8>, ptr %ptr %res = call <16 x i16> @llvm.x86.avx2.mpsadbw(<32 x i8> %a0, <32 x i8> %a1, i8 7) ; <<16 x i16>> [#uses=1] ret <16 x i16> %res } define <16 x i16> @test_x86_avx2_packusdw(<8 x i32> %a0, <8 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_packusdw( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i32> @@ -857,7 +857,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i32> ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[TMP4]], <8 x i32> [[TMP6]]) ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i16> [[_MSPROP_VECTOR_PACK]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> %a0, <8 x i32> %a1) ; <<16 x i16>> [#uses=1] @@ -871,7 +871,7 @@ ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> zeroinitializer) ; CHECK-NEXT: [[RES:%.*]] = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> zeroinitializer, <8 x i32> ) -; CHECK-NEXT: store <16 x i16> [[_MSPROP_VECTOR_PACK]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[RES]] ; %res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> zeroinitializer, <8 x i32> ) @@ -881,14 +881,14 @@ define <32 x i8> @test_x86_avx2_pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) #0 { ; CHECK-LABEL: @test_x86_avx2_pblendvb( -; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, <32 x i8>* bitcast ([100 x i64]* @__msan_param_tls to <32 x i8>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <32 x i8>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <32 x i8>, <32 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 64) to <32 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <32 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <32 x i8> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[_MSPROP1:%.*]] = or <32 x i8> [[_MSPROP]], [[TMP3]] ; CHECK-NEXT: [[RES:%.*]] = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> [[A0:%.*]], <32 x i8> [[A1:%.*]], <32 x i8> [[A2:%.*]]) -; CHECK-NEXT: store <32 x i8> [[_MSPROP1]], <32 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <32 x i8>*), align 8 +; CHECK-NEXT: store <32 x i8> [[_MSPROP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <32 x i8> [[RES]] ; %res = call <32 x i8> @llvm.x86.avx2.pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) ; <<32 x i8>> [#uses=1] @@ -899,12 +899,12 @@ define <16 x i16> @test_x86_avx2_pblendw(<16 x i16> %a0, <16 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_pblendw( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, <16 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> [[TMP2]], <16 x i32> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i16> [[A0:%.*]], <16 x i16> [[A1:%.*]], <16 x i32> -; CHECK-NEXT: store <16 x i16> [[_MSPROP]], <16 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i16>*), align 8 +; CHECK-NEXT: store <16 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i16> [[TMP3]] ; %res = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %a0, <16 x i16> %a1, i8 7) ; <<16 x i16>> [#uses=1] @@ -915,12 +915,12 @@ define <4 x i32> @test_x86_avx2_pblendd_128(<4 x i32> %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_pblendd_128( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]], <4 x i32> -; CHECK-NEXT: store <4 x i32> [[_MSPROP]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[TMP3]] ; %res = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %a0, <4 x i32> %a1, i8 7) ; <<4 x i32>> [#uses=1] @@ -931,12 +931,12 @@ define <8 x i32> @test_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_pblendd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]], <8 x i32> -; CHECK-NEXT: store <8 x i32> [[_MSPROP]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[TMP3]] ; %res = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %a0, <8 x i32> %a1, i8 7) ; <<8 x i32>> [#uses=1] @@ -947,12 +947,12 @@ define <8 x i32> @test_x86_avx2_permd(<8 x i32> %a0, <8 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_permd( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> [[A0:%.*]], <8 x i32> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i32> [[_MSPROP]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1] @@ -963,8 +963,8 @@ define <8 x float> @test_x86_avx2_permps(<8 x float> %a0, <8 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_permps( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP3]], 0 @@ -973,11 +973,11 @@ ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx2.permps(<8 x float> [[A0:%.*]], <8 x i32> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i32> zeroinitializer, <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> %a1) ; <<8 x float>> [#uses=1] @@ -986,10 +986,10 @@ declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x i32>) nounwind readonly -define <2 x i64> @test_x86_avx2_maskload_q(i8* %a0, <2 x i64> %a1) #0 { +define <2 x i64> @test_x86_avx2_maskload_q(ptr %a0, <2 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_maskload_q( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i128 @@ -997,23 +997,23 @@ ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]] ; CHECK: 4: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 5: -; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.maskload.q(i8* [[A0:%.*]], <2 x i64> [[A1:%.*]]) -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.maskload.q(ptr [[A0:%.*]], <2 x i64> [[A1:%.*]]) +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; - %res = call <2 x i64> @llvm.x86.avx2.maskload.q(i8* %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] + %res = call <2 x i64> @llvm.x86.avx2.maskload.q(ptr %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] ret <2 x i64> %res } -declare <2 x i64> @llvm.x86.avx2.maskload.q(i8*, <2 x i64>) nounwind readonly +declare <2 x i64> @llvm.x86.avx2.maskload.q(ptr, <2 x i64>) nounwind readonly -define <4 x i64> @test_x86_avx2_maskload_q_256(i8* %a0, <4 x i64> %a1) #0 { +define <4 x i64> @test_x86_avx2_maskload_q_256(ptr %a0, <4 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_maskload_q_256( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[TMP2]] to i256 @@ -1021,23 +1021,23 @@ ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]] ; CHECK: 4: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 5: -; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.maskload.q.256(i8* [[A0:%.*]], <4 x i64> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.maskload.q.256(ptr [[A0:%.*]], <4 x i64> [[A1:%.*]]) +; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i64> [[RES]] ; - %res = call <4 x i64> @llvm.x86.avx2.maskload.q.256(i8* %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1] + %res = call <4 x i64> @llvm.x86.avx2.maskload.q.256(ptr %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1] ret <4 x i64> %res } -declare <4 x i64> @llvm.x86.avx2.maskload.q.256(i8*, <4 x i64>) nounwind readonly +declare <4 x i64> @llvm.x86.avx2.maskload.q.256(ptr, <4 x i64>) nounwind readonly -define <4 x i32> @test_x86_avx2_maskload_d(i8* %a0, <4 x i32> %a1) #0 { +define <4 x i32> @test_x86_avx2_maskload_d(ptr %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_maskload_d( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 @@ -1045,23 +1045,23 @@ ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]] ; CHECK: 4: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 5: -; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.maskload.d(i8* [[A0:%.*]], <4 x i32> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.maskload.d(ptr [[A0:%.*]], <4 x i32> [[A1:%.*]]) +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; - %res = call <4 x i32> @llvm.x86.avx2.maskload.d(i8* %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] + %res = call <4 x i32> @llvm.x86.avx2.maskload.d(ptr %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] ret <4 x i32> %res } -declare <4 x i32> @llvm.x86.avx2.maskload.d(i8*, <4 x i32>) nounwind readonly +declare <4 x i32> @llvm.x86.avx2.maskload.d(ptr, <4 x i32>) nounwind readonly -define <8 x i32> @test_x86_avx2_maskload_d_256(i8* %a0, <8 x i32> %a1) #0 { +define <8 x i32> @test_x86_avx2_maskload_d_256(ptr %a0, <8 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_maskload_d_256( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP2]] to i256 @@ -1069,24 +1069,24 @@ ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]] ; CHECK: 4: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 5: -; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.maskload.d.256(i8* [[A0:%.*]], <8 x i32> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i32> zeroinitializer, <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.maskload.d.256(ptr [[A0:%.*]], <8 x i32> [[A1:%.*]]) +; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; - %res = call <8 x i32> @llvm.x86.avx2.maskload.d.256(i8* %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1] + %res = call <8 x i32> @llvm.x86.avx2.maskload.d.256(ptr %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1] ret <8 x i32> %res } -declare <8 x i32> @llvm.x86.avx2.maskload.d.256(i8*, <8 x i32>) nounwind readonly +declare <8 x i32> @llvm.x86.avx2.maskload.d.256(ptr, <8 x i32>) nounwind readonly -define void @test_x86_avx2_maskstore_q(i8* %a0, <2 x i64> %a1, <2 x i64> %a2) #0 { +define void @test_x86_avx2_maskstore_q(ptr %a0, <2 x i64> %a1, <2 x i64> %a2) #0 { ; CHECK-LABEL: @test_x86_avx2_maskstore_q( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i128 @@ -1097,23 +1097,23 @@ ; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF0]] ; CHECK: 6: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 7: -; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.q(i8* [[A0:%.*]], <2 x i64> [[A1:%.*]], <2 x i64> [[A2:%.*]]) +; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.q(ptr [[A0:%.*]], <2 x i64> [[A1:%.*]], <2 x i64> [[A2:%.*]]) ; CHECK-NEXT: ret void ; - call void @llvm.x86.avx2.maskstore.q(i8* %a0, <2 x i64> %a1, <2 x i64> %a2) + call void @llvm.x86.avx2.maskstore.q(ptr %a0, <2 x i64> %a1, <2 x i64> %a2) ret void } -declare void @llvm.x86.avx2.maskstore.q(i8*, <2 x i64>, <2 x i64>) nounwind +declare void @llvm.x86.avx2.maskstore.q(ptr, <2 x i64>, <2 x i64>) nounwind -define void @test_x86_avx2_maskstore_q_256(i8* %a0, <4 x i64> %a1, <4 x i64> %a2) #0 { +define void @test_x86_avx2_maskstore_q_256(ptr %a0, <4 x i64> %a1, <4 x i64> %a2) #0 { ; CHECK-LABEL: @test_x86_avx2_maskstore_q_256( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i64> [[TMP2]] to i256 @@ -1124,23 +1124,23 @@ ; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF0]] ; CHECK: 6: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 7: -; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.q.256(i8* [[A0:%.*]], <4 x i64> [[A1:%.*]], <4 x i64> [[A2:%.*]]) +; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.q.256(ptr [[A0:%.*]], <4 x i64> [[A1:%.*]], <4 x i64> [[A2:%.*]]) ; CHECK-NEXT: ret void ; - call void @llvm.x86.avx2.maskstore.q.256(i8* %a0, <4 x i64> %a1, <4 x i64> %a2) + call void @llvm.x86.avx2.maskstore.q.256(ptr %a0, <4 x i64> %a1, <4 x i64> %a2) ret void } -declare void @llvm.x86.avx2.maskstore.q.256(i8*, <4 x i64>, <4 x i64>) nounwind +declare void @llvm.x86.avx2.maskstore.q.256(ptr, <4 x i64>, <4 x i64>) nounwind -define void @test_x86_avx2_maskstore_d(i8* %a0, <4 x i32> %a1, <4 x i32> %a2) #0 { +define void @test_x86_avx2_maskstore_d(ptr %a0, <4 x i32> %a1, <4 x i32> %a2) #0 { ; CHECK-LABEL: @test_x86_avx2_maskstore_d( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 @@ -1151,23 +1151,23 @@ ; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF0]] ; CHECK: 6: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 7: -; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.d(i8* [[A0:%.*]], <4 x i32> [[A1:%.*]], <4 x i32> [[A2:%.*]]) +; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.d(ptr [[A0:%.*]], <4 x i32> [[A1:%.*]], <4 x i32> [[A2:%.*]]) ; CHECK-NEXT: ret void ; - call void @llvm.x86.avx2.maskstore.d(i8* %a0, <4 x i32> %a1, <4 x i32> %a2) + call void @llvm.x86.avx2.maskstore.d(ptr %a0, <4 x i32> %a1, <4 x i32> %a2) ret void } -declare void @llvm.x86.avx2.maskstore.d(i8*, <4 x i32>, <4 x i32>) nounwind +declare void @llvm.x86.avx2.maskstore.d(ptr, <4 x i32>, <4 x i32>) nounwind -define void @test_x86_avx2_maskstore_d_256(i8* %a0, <8 x i32> %a1, <8 x i32> %a2) #0 { +define void @test_x86_avx2_maskstore_d_256(ptr %a0, <8 x i32> %a1, <8 x i32> %a2) #0 { ; CHECK-LABEL: @test_x86_avx2_maskstore_d_256( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i256 @@ -1178,29 +1178,29 @@ ; CHECK-NEXT: [[_MSOR3:%.*]] = or i1 [[_MSOR]], [[_MSCMP2]] ; CHECK-NEXT: br i1 [[_MSOR3]], label [[TMP6:%.*]], label [[TMP7:%.*]], !prof [[PROF0]] ; CHECK: 6: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 7: -; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.d.256(i8* [[A0:%.*]], <8 x i32> [[A1:%.*]], <8 x i32> [[A2:%.*]]) +; CHECK-NEXT: call void @llvm.x86.avx2.maskstore.d.256(ptr [[A0:%.*]], <8 x i32> [[A1:%.*]], <8 x i32> [[A2:%.*]]) ; CHECK-NEXT: ret void ; - call void @llvm.x86.avx2.maskstore.d.256(i8* %a0, <8 x i32> %a1, <8 x i32> %a2) + call void @llvm.x86.avx2.maskstore.d.256(ptr %a0, <8 x i32> %a1, <8 x i32> %a2) ret void } -declare void @llvm.x86.avx2.maskstore.d.256(i8*, <8 x i32>, <8 x i32>) nounwind +declare void @llvm.x86.avx2.maskstore.d.256(ptr, <8 x i32>, <8 x i32>) nounwind define <4 x i32> @test_x86_avx2_psllv_d(<4 x i32> %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psllv_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32> ; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP5]], [[TMP4]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]]) -; CHECK-NEXT: store <4 x i32> [[TMP6]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -1218,7 +1218,7 @@ ; CHECK-NEXT: [[RES1:%.*]] = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> , <4 x i32> ) ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP2]], [[TMP4]] ; CHECK-NEXT: [[RES2:%.*]] = add <4 x i32> [[RES0]], [[RES1]] -; CHECK-NEXT: store <4 x i32> [[_MSPROP]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES2]] ; %res0 = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> , <4 x i32> ) @@ -1231,15 +1231,15 @@ define <8 x i32> @test_x86_avx2_psllv_d_256(<8 x i32> %a0, <8 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psllv_d_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i32> ; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> [[TMP1]], <8 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i32> [[TMP5]], [[TMP4]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> [[A0:%.*]], <8 x i32> [[A1]]) -; CHECK-NEXT: store <8 x i32> [[TMP6]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1] @@ -1257,7 +1257,7 @@ ; CHECK-NEXT: [[RES1:%.*]] = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> , <8 x i32> ) ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP2]], [[TMP4]] ; CHECK-NEXT: [[RES2:%.*]] = add <8 x i32> [[RES0]], [[RES1]] -; CHECK-NEXT: store <8 x i32> [[_MSPROP]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES2]] ; %res0 = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> , <8 x i32> ) @@ -1270,15 +1270,15 @@ define <2 x i64> @test_x86_avx2_psllv_q(<2 x i64> %a0, <2 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psllv_q( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <2 x i1> [[TMP3]] to <2 x i64> ; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> [[TMP1]], <2 x i64> [[A1:%.*]]) ; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP5]], [[TMP4]] ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> [[A0:%.*]], <2 x i64> [[A1]]) -; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] @@ -1290,7 +1290,7 @@ ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> zeroinitializer, <2 x i64> ) ; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> , <2 x i64> ) -; CHECK-NEXT: store <2 x i64> [[TMP2]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP2]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> , <2 x i64> ) @@ -1301,15 +1301,15 @@ define <4 x i64> @test_x86_avx2_psllv_q_256(<4 x i64> %a0, <4 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psllv_q_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i64> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i64> ; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> [[TMP1]], <4 x i64> [[A1:%.*]]) ; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], [[TMP4]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> [[A0:%.*]], <4 x i64> [[A1]]) -; CHECK-NEXT: store <4 x i64> [[TMP6]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i64> [[RES]] ; %res = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1] @@ -1322,7 +1322,7 @@ ; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> zeroinitializer, <4 x i64> ) ; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i64> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> , <4 x i64> ) -; CHECK-NEXT: store <4 x i64> [[TMP2]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[TMP2]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i64> [[RES]] ; %res = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> , <4 x i64> ) @@ -1333,15 +1333,15 @@ define <4 x i32> @test_x86_avx2_psrlv_d(<4 x i32> %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psrlv_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32> ; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP5]], [[TMP4]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]]) -; CHECK-NEXT: store <4 x i32> [[TMP6]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -1359,7 +1359,7 @@ ; CHECK-NEXT: [[RES1:%.*]] = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> , <4 x i32> ) ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP2]], [[TMP4]] ; CHECK-NEXT: [[RES2:%.*]] = add <4 x i32> [[RES0]], [[RES1]] -; CHECK-NEXT: store <4 x i32> [[_MSPROP]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES2]] ; %res0 = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> , <4 x i32> ) @@ -1372,15 +1372,15 @@ define <8 x i32> @test_x86_avx2_psrlv_d_256(<8 x i32> %a0, <8 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psrlv_d_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i32> ; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> [[TMP1]], <8 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i32> [[TMP5]], [[TMP4]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> [[A0:%.*]], <8 x i32> [[A1]]) -; CHECK-NEXT: store <8 x i32> [[TMP6]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1] @@ -1398,7 +1398,7 @@ ; CHECK-NEXT: [[RES1:%.*]] = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> , <8 x i32> ) ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP2]], [[TMP4]] ; CHECK-NEXT: [[RES2:%.*]] = add <8 x i32> [[RES0]], [[RES1]] -; CHECK-NEXT: store <8 x i32> [[_MSPROP]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES2]] ; %res0 = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> , <8 x i32> ) @@ -1411,15 +1411,15 @@ define <2 x i64> @test_x86_avx2_psrlv_q(<2 x i64> %a0, <2 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psrlv_q( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <2 x i1> [[TMP3]] to <2 x i64> ; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> [[TMP1]], <2 x i64> [[A1:%.*]]) ; CHECK-NEXT: [[TMP6:%.*]] = or <2 x i64> [[TMP5]], [[TMP4]] ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> [[A0:%.*]], <2 x i64> [[A1]]) -; CHECK-NEXT: store <2 x i64> [[TMP6]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %res = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] @@ -1432,7 +1432,7 @@ ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> zeroinitializer, <2 x i64> ) ; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> , <2 x i64> ) -; CHECK-NEXT: store <2 x i64> [[TMP2]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP2]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %res = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> , <2 x i64> ) @@ -1443,15 +1443,15 @@ define <4 x i64> @test_x86_avx2_psrlv_q_256(<4 x i64> %a0, <4 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psrlv_q_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i64> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i64> ; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> [[TMP1]], <4 x i64> [[A1:%.*]]) ; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i64> [[TMP5]], [[TMP4]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> [[A0:%.*]], <4 x i64> [[A1]]) -; CHECK-NEXT: store <4 x i64> [[TMP6]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i64> [[RES]] ; %res = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %a0, <4 x i64> %a1) ; <<4 x i64>> [#uses=1] @@ -1465,7 +1465,7 @@ ; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> zeroinitializer, <4 x i64> ) ; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i64> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> , <4 x i64> ) -; CHECK-NEXT: store <4 x i64> [[TMP2]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: store <4 x i64> [[TMP2]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i64> [[RES]] ; %res = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> , <4 x i64> ) @@ -1476,15 +1476,15 @@ define <4 x i32> @test_x86_avx2_psrav_d(<4 x i32> %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psrav_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32> ; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP5]], [[TMP4]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]]) -; CHECK-NEXT: store <4 x i32> [[TMP6]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -1497,7 +1497,7 @@ ; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> zeroinitializer, <4 x i32> ) ; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> , <4 x i32> ) -; CHECK-NEXT: store <4 x i32> [[TMP2]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> , <4 x i32> ) @@ -1507,15 +1507,15 @@ define <8 x i32> @test_x86_avx2_psrav_d_256(<8 x i32> %a0, <8 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_avx2_psrav_d_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i32> ; CHECK-NEXT: [[TMP5:%.*]] = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> [[TMP1]], <8 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP6:%.*]] = or <8 x i32> [[TMP5]], [[TMP4]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> [[A0:%.*]], <8 x i32> [[A1]]) -; CHECK-NEXT: store <8 x i32> [[TMP6]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %a0, <8 x i32> %a1) ; <<8 x i32>> [#uses=1] @@ -1528,7 +1528,7 @@ ; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> zeroinitializer, <8 x i32> ) ; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> , <8 x i32> ) -; CHECK-NEXT: store <8 x i32> [[TMP2]], <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: store <8 x i32> [[TMP2]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> , <8 x i32> ) @@ -1536,12 +1536,12 @@ } declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) nounwind readnone -define <2 x double> @test_x86_avx2_gather_d_pd(<2 x double> %a0, i8* %a1, <4 x i32> %idx, <2 x double> %mask) #0 { +define <2 x double> @test_x86_avx2_gather_d_pd(<2 x double> %a0, ptr %a1, <4 x i32> %idx, <2 x double> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_d_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0 @@ -1555,26 +1555,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> [[A0:%.*]], i8* [[A1:%.*]], <4 x i32> [[IDX:%.*]], <2 x double> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> [[A0:%.*]], ptr [[A1:%.*]], <4 x i32> [[IDX:%.*]], <2 x double> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; %res = call <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double> %a0, - i8* %a1, <4 x i32> %idx, <2 x double> %mask, i8 2) ; + ptr %a1, <4 x i32> %idx, <2 x double> %mask, i8 2) ; ret <2 x double> %res } -declare <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double>, i8*, +declare <2 x double> @llvm.x86.avx2.gather.d.pd(<2 x double>, ptr, <4 x i32>, <2 x double>, i8) nounwind readonly -define <4 x double> @test_x86_avx2_gather_d_pd_256(<4 x double> %a0, i8* %a1, <4 x i32> %idx, <4 x double> %mask) #0 { +define <4 x double> @test_x86_avx2_gather_d_pd_256(<4 x double> %a0, ptr %a1, <4 x i32> %idx, <4 x double> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_d_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 56) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 56) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 0 @@ -1588,26 +1588,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> [[A0:%.*]], i8* [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x double> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> [[A0:%.*]], ptr [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x double> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[RES]] ; %res = call <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double> %a0, - i8* %a1, <4 x i32> %idx, <4 x double> %mask, i8 2) ; + ptr %a1, <4 x i32> %idx, <4 x double> %mask, i8 2) ; ret <4 x double> %res } -declare <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double>, i8*, +declare <4 x double> @llvm.x86.avx2.gather.d.pd.256(<4 x double>, ptr, <4 x i32>, <4 x double>, i8) nounwind readonly -define <2 x double> @test_x86_avx2_gather_q_pd(<2 x double> %a0, i8* %a1, <2 x i64> %idx, <2 x double> %mask) #0 { +define <2 x double> @test_x86_avx2_gather_q_pd(<2 x double> %a0, ptr %a1, <2 x i64> %idx, <2 x double> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_q_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0 @@ -1621,26 +1621,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> [[A0:%.*]], i8* [[A1:%.*]], <2 x i64> [[IDX:%.*]], <2 x double> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> [[A0:%.*]], ptr [[A1:%.*]], <2 x i64> [[IDX:%.*]], <2 x double> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; %res = call <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double> %a0, - i8* %a1, <2 x i64> %idx, <2 x double> %mask, i8 2) ; + ptr %a1, <2 x i64> %idx, <2 x double> %mask, i8 2) ; ret <2 x double> %res } -declare <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double>, i8*, +declare <2 x double> @llvm.x86.avx2.gather.q.pd(<2 x double>, ptr, <2 x i64>, <2 x double>, i8) nounwind readonly -define <4 x double> @test_x86_avx2_gather_q_pd_256(<4 x double> %a0, i8* %a1, <4 x i64> %idx, <4 x double> %mask) #0 { +define <4 x double> @test_x86_avx2_gather_q_pd_256(<4 x double> %a0, ptr %a1, <4 x i64> %idx, <4 x double> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_q_pd_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 72) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 72) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 0 @@ -1654,26 +1654,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> [[A0:%.*]], i8* [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x double> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> [[A0:%.*]], ptr [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x double> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[RES]] ; %res = call <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double> %a0, - i8* %a1, <4 x i64> %idx, <4 x double> %mask, i8 2) ; + ptr %a1, <4 x i64> %idx, <4 x double> %mask, i8 2) ; ret <4 x double> %res } -declare <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double>, i8*, +declare <4 x double> @llvm.x86.avx2.gather.q.pd.256(<4 x double>, ptr, <4 x i64>, <4 x double>, i8) nounwind readonly -define <4 x float> @test_x86_avx2_gather_d_ps(<4 x float> %a0, i8* %a1, <4 x i32> %idx, <4 x float> %mask) #0 { +define <4 x float> @test_x86_avx2_gather_d_ps(<4 x float> %a0, ptr %a1, <4 x i32> %idx, <4 x float> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_d_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0 @@ -1687,26 +1687,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> [[A0:%.*]], i8* [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x float> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> [[A0:%.*]], ptr [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x float> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float> %a0, - i8* %a1, <4 x i32> %idx, <4 x float> %mask, i8 2) ; + ptr %a1, <4 x i32> %idx, <4 x float> %mask, i8 2) ; ret <4 x float> %res } -declare <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float>, i8*, +declare <4 x float> @llvm.x86.avx2.gather.d.ps(<4 x float>, ptr, <4 x i32>, <4 x float>, i8) nounwind readonly -define <8 x float> @test_x86_avx2_gather_d_ps_256(<8 x float> %a0, i8* %a1, <8 x i32> %idx, <8 x float> %mask) #0 { +define <8 x float> @test_x86_avx2_gather_d_ps_256(<8 x float> %a0, ptr %a1, <8 x i32> %idx, <8 x float> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_d_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 72) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 72) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 0 @@ -1720,26 +1720,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> [[A0:%.*]], i8* [[A1:%.*]], <8 x i32> [[IDX:%.*]], <8 x float> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <8 x i32> zeroinitializer, <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> [[A0:%.*]], ptr [[A1:%.*]], <8 x i32> [[IDX:%.*]], <8 x float> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; %res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0, - i8* %a1, <8 x i32> %idx, <8 x float> %mask, i8 2) ; + ptr %a1, <8 x i32> %idx, <8 x float> %mask, i8 2) ; ret <8 x float> %res } -declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, i8*, +declare <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float>, ptr, <8 x i32>, <8 x float>, i8) nounwind readonly -define <4 x float> @test_x86_avx2_gather_q_ps(<4 x float> %a0, i8* %a1, <2 x i64> %idx, <4 x float> %mask) #0 { +define <4 x float> @test_x86_avx2_gather_q_ps(<4 x float> %a0, ptr %a1, <2 x i64> %idx, <4 x float> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_q_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0 @@ -1753,26 +1753,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float> [[A0:%.*]], i8* [[A1:%.*]], <2 x i64> [[IDX:%.*]], <4 x float> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float> [[A0:%.*]], ptr [[A1:%.*]], <2 x i64> [[IDX:%.*]], <4 x float> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float> %a0, - i8* %a1, <2 x i64> %idx, <4 x float> %mask, i8 2) ; + ptr %a1, <2 x i64> %idx, <4 x float> %mask, i8 2) ; ret <4 x float> %res } -declare <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float>, i8*, +declare <4 x float> @llvm.x86.avx2.gather.q.ps(<4 x float>, ptr, <2 x i64>, <4 x float>, i8) nounwind readonly -define <4 x float> @test_x86_avx2_gather_q_ps_256(<4 x float> %a0, i8* %a1, <4 x i64> %idx, <4 x float> %mask) #0 { +define <4 x float> @test_x86_avx2_gather_q_ps_256(<4 x float> %a0, ptr %a1, <4 x i64> %idx, <4 x float> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_q_ps_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 56) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 56) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0 @@ -1786,26 +1786,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> [[A0:%.*]], i8* [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x float> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> [[A0:%.*]], ptr [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x float> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float> %a0, - i8* %a1, <4 x i64> %idx, <4 x float> %mask, i8 2) ; + ptr %a1, <4 x i64> %idx, <4 x float> %mask, i8 2) ; ret <4 x float> %res } -declare <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float>, i8*, +declare <4 x float> @llvm.x86.avx2.gather.q.ps.256(<4 x float>, ptr, <4 x i64>, <4 x float>, i8) nounwind readonly -define <2 x i64> @test_x86_avx2_gather_d_q(<2 x i64> %a0, i8* %a1, <4 x i32> %idx, <2 x i64> %mask) #0 { +define <2 x i64> @test_x86_avx2_gather_d_q(<2 x i64> %a0, ptr %a1, <4 x i32> %idx, <2 x i64> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_d_q( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0 @@ -1819,26 +1819,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> [[A0:%.*]], i8* [[A1:%.*]], <4 x i32> [[IDX:%.*]], <2 x i64> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> [[A0:%.*]], ptr [[A1:%.*]], <4 x i32> [[IDX:%.*]], <2 x i64> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %res = call <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64> %a0, - i8* %a1, <4 x i32> %idx, <2 x i64> %mask, i8 2) ; + ptr %a1, <4 x i32> %idx, <2 x i64> %mask, i8 2) ; ret <2 x i64> %res } -declare <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64>, i8*, +declare <2 x i64> @llvm.x86.avx2.gather.d.q(<2 x i64>, ptr, <4 x i32>, <2 x i64>, i8) nounwind readonly -define <4 x i64> @test_x86_avx2_gather_d_q_256(<4 x i64> %a0, i8* %a1, <4 x i32> %idx, <4 x i64> %mask) #0 { +define <4 x i64> @test_x86_avx2_gather_d_q_256(<4 x i64> %a0, ptr %a1, <4 x i32> %idx, <4 x i64> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_d_q_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 56) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 56) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 0 @@ -1852,26 +1852,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> [[A0:%.*]], i8* [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x i64> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> [[A0:%.*]], ptr [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x i64> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i64> [[RES]] ; %res = call <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64> %a0, - i8* %a1, <4 x i32> %idx, <4 x i64> %mask, i8 2) ; + ptr %a1, <4 x i32> %idx, <4 x i64> %mask, i8 2) ; ret <4 x i64> %res } -declare <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64>, i8*, +declare <4 x i64> @llvm.x86.avx2.gather.d.q.256(<4 x i64>, ptr, <4 x i32>, <4 x i64>, i8) nounwind readonly -define <2 x i64> @test_x86_avx2_gather_q_q(<2 x i64> %a0, i8* %a1, <2 x i64> %idx, <2 x i64> %mask) #0 { +define <2 x i64> @test_x86_avx2_gather_q_q(<2 x i64> %a0, ptr %a1, <2 x i64> %idx, <2 x i64> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_q_q( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0 @@ -1885,26 +1885,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> [[A0:%.*]], i8* [[A1:%.*]], <2 x i64> [[IDX:%.*]], <2 x i64> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> [[A0:%.*]], ptr [[A1:%.*]], <2 x i64> [[IDX:%.*]], <2 x i64> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %res = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> %a0, - i8* %a1, <2 x i64> %idx, <2 x i64> %mask, i8 2) ; + ptr %a1, <2 x i64> %idx, <2 x i64> %mask, i8 2) ; ret <2 x i64> %res } -declare <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64>, i8*, +declare <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64>, ptr, <2 x i64>, <2 x i64>, i8) nounwind readonly -define <4 x i64> @test_x86_avx2_gather_q_q_256(<4 x i64> %a0, i8* %a1, <4 x i64> %idx, <4 x i64> %mask) #0 { +define <4 x i64> @test_x86_avx2_gather_q_q_256(<4 x i64> %a0, ptr %a1, <4 x i64> %idx, <4 x i64> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_q_q_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 72) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 72) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i64> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 0 @@ -1918,26 +1918,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> [[A0:%.*]], i8* [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x i64> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> [[A0:%.*]], ptr [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x i64> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i64> [[RES]] ; %res = call <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64> %a0, - i8* %a1, <4 x i64> %idx, <4 x i64> %mask, i8 2) ; + ptr %a1, <4 x i64> %idx, <4 x i64> %mask, i8 2) ; ret <4 x i64> %res } -declare <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64>, i8*, +declare <4 x i64> @llvm.x86.avx2.gather.q.q.256(<4 x i64>, ptr, <4 x i64>, <4 x i64>, i8) nounwind readonly -define <4 x i32> @test_x86_avx2_gather_d_d(<4 x i32> %a0, i8* %a1, <4 x i32> %idx, <4 x i32> %mask) #0 { +define <4 x i32> @test_x86_avx2_gather_d_d(<4 x i32> %a0, ptr %a1, <4 x i32> %idx, <4 x i32> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_d_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0 @@ -1951,26 +1951,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32> [[A0:%.*]], i8* [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x i32> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32> [[A0:%.*]], ptr [[A1:%.*]], <4 x i32> [[IDX:%.*]], <4 x i32> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32> %a0, - i8* %a1, <4 x i32> %idx, <4 x i32> %mask, i8 2) ; + ptr %a1, <4 x i32> %idx, <4 x i32> %mask, i8 2) ; ret <4 x i32> %res } -declare <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32>, i8*, +declare <4 x i32> @llvm.x86.avx2.gather.d.d(<4 x i32>, ptr, <4 x i32>, <4 x i32>, i8) nounwind readonly -define <8 x i32> @test_x86_avx2_gather_d_d_256(<8 x i32> %a0, i8* %a1, <8 x i32> %idx, <8 x i32> %mask) #0 { +define <8 x i32> @test_x86_avx2_gather_d_d_256(<8 x i32> %a0, ptr %a1, <8 x i32> %idx, <8 x i32> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_d_d_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 72) to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 72) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i32> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP5]], 0 @@ -1984,26 +1984,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32> [[A0:%.*]], i8* [[A1:%.*]], <8 x i32> [[IDX:%.*]], <8 x i32> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <8 x i32> zeroinitializer, <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32> [[A0:%.*]], ptr [[A1:%.*]], <8 x i32> [[IDX:%.*]], <8 x i32> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i32> [[RES]] ; %res = call <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32> %a0, - i8* %a1, <8 x i32> %idx, <8 x i32> %mask, i8 2) ; + ptr %a1, <8 x i32> %idx, <8 x i32> %mask, i8 2) ; ret <8 x i32> %res } -declare <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32>, i8*, +declare <8 x i32> @llvm.x86.avx2.gather.d.d.256(<8 x i32>, ptr, <8 x i32>, <8 x i32>, i8) nounwind readonly -define <4 x i32> @test_x86_avx2_gather_q_d(<4 x i32> %a0, i8* %a1, <2 x i64> %idx, <4 x i32> %mask) #0 { +define <4 x i32> @test_x86_avx2_gather_q_d(<4 x i32> %a0, ptr %a1, <2 x i64> %idx, <4 x i32> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_q_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0 @@ -2017,26 +2017,26 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32> [[A0:%.*]], i8* [[A1:%.*]], <2 x i64> [[IDX:%.*]], <4 x i32> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32> [[A0:%.*]], ptr [[A1:%.*]], <2 x i64> [[IDX:%.*]], <4 x i32> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32> %a0, - i8* %a1, <2 x i64> %idx, <4 x i32> %mask, i8 2) ; + ptr %a1, <2 x i64> %idx, <4 x i32> %mask, i8 2) ; ret <4 x i32> %res } -declare <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32>, i8*, +declare <4 x i32> @llvm.x86.avx2.gather.q.d(<4 x i32>, ptr, <2 x i64>, <4 x i32>, i8) nounwind readonly -define <4 x i32> @test_x86_avx2_gather_q_d_256(<4 x i32> %a0, i8* %a1, <4 x i64> %idx, <4 x i32> %mask) #0 { +define <4 x i32> @test_x86_avx2_gather_q_d_256(<4 x i32> %a0, ptr %a1, <4 x i64> %idx, <4 x i32> %mask) #0 { ; CHECK-LABEL: @test_x86_avx2_gather_q_d_256( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <4 x i64>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 56) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 56) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP5]], 0 @@ -2050,32 +2050,31 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> [[A0:%.*]], i8* [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x i32> [[MASK:%.*]], i8 2) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> [[A0:%.*]], ptr [[A1:%.*]], <4 x i64> [[IDX:%.*]], <4 x i32> [[MASK:%.*]], i8 2) +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32> %a0, - i8* %a1, <4 x i64> %idx, <4 x i32> %mask, i8 2) ; + ptr %a1, <4 x i64> %idx, <4 x i32> %mask, i8 2) ; ret <4 x i32> %res } -declare <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32>, i8*, +declare <4 x i32> @llvm.x86.avx2.gather.q.d.256(<4 x i32>, ptr, <4 x i64>, <4 x i32>, i8) nounwind readonly -define <8 x float> @test_gather_mask(<8 x float> %a0, float* %a, <8 x i32> %idx, <8 x float> %mask, float* nocapture %out) #0 { +define <8 x float> @test_gather_mask(<8 x float> %a0, ptr %a, <8 x i32> %idx, <8 x float> %mask, ptr nocapture %out) #0 { ; CHECK-LABEL: @test_gather_mask( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to i64*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, <8 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 72) to <8 x i32>*), align 8 -; CHECK-NEXT: [[TMP5:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 104) to i64*), align 8 -; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[A_I8:%.*]] = bitcast float* [[A:%.*]] to i8* -; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP2]] to i256 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 72) to ptr), align 8 +; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 104) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i32> [[TMP1]] to i256 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP6]], 0 -; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP1]], 0 +; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0 ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] ; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i32> [[TMP3]] to i256 ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i256 [[TMP7]], 0 @@ -2085,41 +2084,38 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF0]] ; CHECK: 9: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 10: -; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> [[A0:%.*]], i8* [[A_I8]], <8 x i32> [[IDX:%.*]], <8 x float> [[MASK:%.*]], i8 4) -; CHECK-NEXT: [[OUT_PTR:%.*]] = bitcast float* [[OUT:%.*]] to <8 x float>* +; CHECK-NEXT: [[RES:%.*]] = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> [[A0:%.*]], ptr [[A:%.*]], <8 x i32> [[IDX:%.*]], <8 x float> [[MASK:%.*]], i8 4) ; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP5]], 0 ; CHECK-NEXT: br i1 [[_MSCMP6]], label [[TMP11:%.*]], label [[TMP12:%.*]], !prof [[PROF0]] ; CHECK: 11: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 12: -; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint <8 x float>* [[OUT_PTR]] to i64 +; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[OUT:%.*]] to i64 ; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 87960930222080 -; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to <8 x i32>* -; CHECK-NEXT: store <8 x i32> [[TMP4]], <8 x i32>* [[TMP15]], align 4 -; CHECK-NEXT: store <8 x float> [[MASK]], <8 x float>* [[OUT_PTR]], align 4 -; CHECK-NEXT: store <8 x i32> zeroinitializer, <8 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr +; CHECK-NEXT: store <8 x i32> [[TMP4]], ptr [[TMP15]], align 4 +; CHECK-NEXT: store <8 x float> [[MASK]], ptr [[OUT]], align 4 +; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x float> [[RES]] ; - %a_i8 = bitcast float* %a to i8* %res = call <8 x float> @llvm.x86.avx2.gather.d.ps.256(<8 x float> %a0, - i8* %a_i8, <8 x i32> %idx, <8 x float> %mask, i8 4) ; + ptr %a, <8 x i32> %idx, <8 x float> %mask, i8 4) ; - %out_ptr = bitcast float * %out to <8 x float> * - store <8 x float> %mask, <8 x float> * %out_ptr, align 4 + store <8 x float> %mask, ptr %out, align 4 ret <8 x float> %res } -define <2 x i64> @test_mask_demanded_bits(<2 x i64> %a0, i8* %a1, <2 x i64> %idx, <2 x i1> %mask) #0 { +define <2 x i64> @test_mask_demanded_bits(<2 x i64> %a0, ptr %a1, <2 x i64> %idx, <2 x i1> %mask) #0 { ; CHECK-LABEL: @test_mask_demanded_bits( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i1>, <2 x i1>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <2 x i1>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i1>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[MASK1:%.*]] = sext <2 x i1> [[MASK:%.*]] to <2 x i64> @@ -2135,16 +2131,16 @@ ; CHECK-NEXT: [[_MSOR5:%.*]] = or i1 [[_MSOR3]], [[_MSCMP4]] ; CHECK-NEXT: br i1 [[_MSOR5]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 9: -; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> [[A0:%.*]], i8* [[A1:%.*]], <2 x i64> [[IDX:%.*]], <2 x i64> [[MASK1]], i8 2) -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> [[A0:%.*]], ptr [[A1:%.*]], <2 x i64> [[IDX:%.*]], <2 x i64> [[MASK1]], i8 2) +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %mask1 = sext <2 x i1> %mask to <2 x i64> %res = call <2 x i64> @llvm.x86.avx2.gather.q.q(<2 x i64> %a0, - i8* %a1, <2 x i64> %idx, <2 x i64> %mask1, i8 2) ; + ptr %a1, <2 x i64> %idx, <2 x i64> %mask1, i8 2) ; ret <2 x i64> %res } diff --git a/llvm/test/Instrumentation/MemorySanitizer/byval-alignment.ll b/llvm/test/Instrumentation/MemorySanitizer/byval-alignment.ll --- a/llvm/test/Instrumentation/MemorySanitizer/byval-alignment.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/byval-alignment.ll @@ -8,13 +8,13 @@ %struct.S = type { i64, i64, i64, [8 x i8] } -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 {{.*}} add {{.*}} ptrtoint {{.*}} @__msan_param_tls {{.*}} i64 8) {{.*}}, i8* align 8 {{.*}}, i64 32, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 {{.*}} add {{.*}} ptrtoint {{.*}} @__msan_param_tls {{.*}} i64 8) {{.*}}, ptr align 8 {{.*}}, i64 32, i1 false) define void @Caller() sanitize_memory { entry: %agg.tmp = alloca %struct.S, align 16 - call void @Callee(i32 1, %struct.S* byval(%struct.S) align 16 %agg.tmp) + call void @Callee(i32 1, ptr byval(%struct.S) align 16 %agg.tmp) ret void } -declare void @Callee(i32, %struct.S* byval(%struct.S) align 16) +declare void @Callee(i32, ptr byval(%struct.S) align 16) diff --git a/llvm/test/Instrumentation/MemorySanitizer/byval.ll b/llvm/test/Instrumentation/MemorySanitizer/byval.ll --- a/llvm/test/Instrumentation/MemorySanitizer/byval.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/byval.ll @@ -3,181 +3,181 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare void @FnByVal(i128* byval(i128) %p); -declare void @Fn(i128* %p); +declare void @FnByVal(ptr byval(i128) %p); +declare void @Fn(ptr %p); -define i128 @ByValArgument(i32, i128* byval(i128) %p) sanitize_memory { +define i128 @ByValArgument(i32, ptr byval(i128) %p) sanitize_memory { ; CHECK-LABEL: @ByValArgument( ; CHECK-NEXT: entry: -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[#]], i8* align 8 inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i8*), i64 16, i1 false) -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %[[#]], i8* align 4 inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i8*), i64 16, i1 false) -; CHECK: [[X:%.*]] = load i128, i128* %p, align 8 -; CHECK: [[_MSLD:%.*]] = load i128, i128* %[[#]], align 8 -; CHECK: %[[#]] = load i32, i32* %[[#]], align 8 -; CHECK: store i128 [[_MSLD]], i128* bitcast ([100 x i64]* @__msan_retval_tls to i128*), align 8 -; CHECK: store i32 %[[#]], i32* @__msan_retval_origin_tls, align 4 +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[#]], ptr align 8 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), i64 16, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 4 %[[#]], ptr align 4 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), i64 16, i1 false) +; CHECK: [[X:%.*]] = load i128, ptr %p, align 8 +; CHECK: [[_MSLD:%.*]] = load i128, ptr %[[#]], align 8 +; CHECK: %[[#]] = load i32, ptr %[[#]], align 8 +; CHECK: store i128 [[_MSLD]], ptr @__msan_retval_tls, align 8 +; CHECK: store i32 %[[#]], ptr @__msan_retval_origin_tls, align 4 ; CHECK: ret i128 [[X]] ; entry: - %x = load i128, i128* %p + %x = load i128, ptr %p ret i128 %x } -define i128 @ByValArgumentNoSanitize(i32, i128* byval(i128) %p) { +define i128 @ByValArgumentNoSanitize(i32, ptr byval(i128) %p) { ; CHECK-LABEL: @ByValArgumentNoSanitize( ; CHECK-NEXT: entry: -; CHECK: call void @llvm.memset.p0i8.i64(i8* align 8 %[[#]], i8 0, i64 16, i1 false) -; CHECK: [[X:%.*]] = load i128, i128* %p, align 8 -; CHECK: store i128 0, i128* bitcast ([100 x i64]* @__msan_retval_tls to i128*), align 8 -; CHECK: store i32 0, i32* @__msan_retval_origin_tls, align 4 +; CHECK: call void @llvm.memset.p0.i64(ptr align 8 %[[#]], i8 0, i64 16, i1 false) +; CHECK: [[X:%.*]] = load i128, ptr %p, align 8 +; CHECK: store i128 0, ptr @__msan_retval_tls, align 8 +; CHECK: store i32 0, ptr @__msan_retval_origin_tls, align 4 ; CHECK: ret i128 [[X]] ; entry: - %x = load i128, i128* %p + %x = load i128, ptr %p ret i128 %x } -define void @ByValForward(i32, i128* byval(i128) %p) sanitize_memory { +define void @ByValForward(i32, ptr byval(i128) %p) sanitize_memory { ; CHECK-LABEL: @ByValForward( ; CHECK-NEXT: entry: -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[#]], i8* align 8 inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i8*), i64 16, i1 false) -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %[[#]], i8* align 4 inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i8*), i64 16, i1 false) -; CHECK: store i64 0, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK: call void @Fn(i128* %p) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[#]], ptr align 8 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), i64 16, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 4 %[[#]], ptr align 4 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), i64 16, i1 false) +; CHECK: store i64 0, ptr @__msan_param_tls, align 8 +; CHECK: call void @Fn(ptr %p) ; CHECK: ret void ; entry: - call void @Fn(i128* %p) + call void @Fn(ptr %p) ret void } -define void @ByValForwardNoSanitize(i32, i128* byval(i128) %p) { +define void @ByValForwardNoSanitize(i32, ptr byval(i128) %p) { ; CHECK-LABEL: @ByValForwardNoSanitize( ; CHECK-NEXT: entry: -; CHECK: call void @llvm.memset.p0i8.i64(i8* align 8 %[[#]], i8 0, i64 16, i1 false) -; CHECK: store i64 0, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK: call void @Fn(i128* %p) +; CHECK: call void @llvm.memset.p0.i64(ptr align 8 %[[#]], i8 0, i64 16, i1 false) +; CHECK: store i64 0, ptr @__msan_param_tls, align 8 +; CHECK: call void @Fn(ptr %p) ; CHECK: ret void ; entry: - call void @Fn(i128* %p) + call void @Fn(ptr %p) ret void } -define void @ByValForwardByVal(i32, i128* byval(i128) %p) sanitize_memory { +define void @ByValForwardByVal(i32, ptr byval(i128) %p) sanitize_memory { ; CHECK-LABEL: @ByValForwardByVal( ; CHECK-NEXT: entry: -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 %[[#]], i8* align 8 inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i8*), i64 16, i1 false) -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %[[#]], i8* align 4 inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i8*), i64 16, i1 false) -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast ([100 x i64]* @__msan_param_tls to i8*), i8* %[[#]], i64 16, i1 false) -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([200 x i32]* @__msan_param_origin_tls to i8*), i8* align 4 %[[#]], i64 16, i1 false) -; CHECK: call void @FnByVal(i128* byval(i128) %p) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 %[[#]], ptr align 8 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), i64 16, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 4 %[[#]], ptr align 4 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), i64 16, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr @__msan_param_tls, ptr %[[#]], i64 16, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 4 @__msan_param_origin_tls, ptr align 4 %[[#]], i64 16, i1 false) +; CHECK: call void @FnByVal(ptr byval(i128) %p) ; CHECK: ret void ; entry: - call void @FnByVal(i128* byval(i128) %p) + call void @FnByVal(ptr byval(i128) %p) ret void } -define void @ByValForwardByValNoSanitize(i32, i128* byval(i128) %p) { +define void @ByValForwardByValNoSanitize(i32, ptr byval(i128) %p) { ; CHECK-LABEL: @ByValForwardByValNoSanitize( ; CHECK-NEXT: entry: -; CHECK: call void @llvm.memset.p0i8.i64(i8* align 8 %[[#]], i8 0, i64 16, i1 false) -; CHECK: call void @llvm.memset.p0i8.i64(i8* bitcast ([100 x i64]* @__msan_param_tls to i8*), i8 0, i64 16, i1 false) -; CHECK: call void @FnByVal(i128* byval(i128) %p) +; CHECK: call void @llvm.memset.p0.i64(ptr align 8 %[[#]], i8 0, i64 16, i1 false) +; CHECK: call void @llvm.memset.p0.i64(ptr @__msan_param_tls, i8 0, i64 16, i1 false) +; CHECK: call void @FnByVal(ptr byval(i128) %p) ; CHECK: ret void ; entry: - call void @FnByVal(i128* byval(i128) %p) + call void @FnByVal(ptr byval(i128) %p) ret void } -declare void @FnByVal8(i8* byval(i8) %p); -declare void @Fn8(i8* %p); +declare void @FnByVal8(ptr byval(i8) %p); +declare void @Fn8(ptr %p); -define i8 @ByValArgument8(i32, i8* byval(i8) %p) sanitize_memory { +define i8 @ByValArgument8(i32, ptr byval(i8) %p) sanitize_memory { ; CHECK-LABEL: @ByValArgument8( ; CHECK-NEXT: entry: -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 %[[#]], i8* align 1 inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i8*), i64 1, i1 false) -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %[[#]], i8* align 4 inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i8*), i64 4, i1 false) -; CHECK: [[X:%.*]] = load i8, i8* %p, align 1 -; CHECK: [[_MSLD:%.*]] = load i8, i8* %[[#]], align 1 -; CHECK: %[[#]] = load i32, i32* %[[#]], align 4 -; CHECK: store i8 [[_MSLD]], i8* bitcast ([100 x i64]* @__msan_retval_tls to i8*), align 8 -; CHECK: store i32 %[[#]], i32* @__msan_retval_origin_tls, align 4 +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 1 %[[#]], ptr align 1 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), i64 1, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 4 %[[#]], ptr align 4 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), i64 4, i1 false) +; CHECK: [[X:%.*]] = load i8, ptr %p, align 1 +; CHECK: [[_MSLD:%.*]] = load i8, ptr %[[#]], align 1 +; CHECK: %[[#]] = load i32, ptr %[[#]], align 4 +; CHECK: store i8 [[_MSLD]], ptr @__msan_retval_tls, align 8 +; CHECK: store i32 %[[#]], ptr @__msan_retval_origin_tls, align 4 ; CHECK: ret i8 [[X]] ; entry: - %x = load i8, i8* %p + %x = load i8, ptr %p ret i8 %x } -define i8 @ByValArgumentNoSanitize8(i32, i8* byval(i8) %p) { +define i8 @ByValArgumentNoSanitize8(i32, ptr byval(i8) %p) { ; CHECK-LABEL: @ByValArgumentNoSanitize8( ; CHECK-NEXT: entry: -; CHECK: call void @llvm.memset.p0i8.i64(i8* align 1 %[[#]], i8 0, i64 1, i1 false) -; CHECK: [[X:%.*]] = load i8, i8* %p, align 1 -; CHECK: store i8 0, i8* bitcast ([100 x i64]* @__msan_retval_tls to i8*), align 8 -; CHECK: store i32 0, i32* @__msan_retval_origin_tls, align 4 +; CHECK: call void @llvm.memset.p0.i64(ptr align 1 %[[#]], i8 0, i64 1, i1 false) +; CHECK: [[X:%.*]] = load i8, ptr %p, align 1 +; CHECK: store i8 0, ptr @__msan_retval_tls, align 8 +; CHECK: store i32 0, ptr @__msan_retval_origin_tls, align 4 ; CHECK: ret i8 [[X]] ; entry: - %x = load i8, i8* %p + %x = load i8, ptr %p ret i8 %x } -define void @ByValForward8(i32, i8* byval(i8) %p) sanitize_memory { +define void @ByValForward8(i32, ptr byval(i8) %p) sanitize_memory { ; CHECK-LABEL: @ByValForward8( ; CHECK-NEXT: entry: -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 %[[#]], i8* align 1 inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i8*), i64 1, i1 false) -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %[[#]], i8* align 4 inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i8*), i64 4, i1 false) -; CHECK: store i64 0, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK: call void @Fn8(i8* %p) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 1 %[[#]], ptr align 1 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), i64 1, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 4 %[[#]], ptr align 4 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), i64 4, i1 false) +; CHECK: store i64 0, ptr @__msan_param_tls, align 8 +; CHECK: call void @Fn8(ptr %p) ; CHECK: ret void ; entry: - call void @Fn8(i8* %p) + call void @Fn8(ptr %p) ret void } -define void @ByValForwardNoSanitize8(i32, i8* byval(i8) %p) { +define void @ByValForwardNoSanitize8(i32, ptr byval(i8) %p) { ; CHECK-LABEL: @ByValForwardNoSanitize8( ; CHECK-NEXT: entry: -; CHECK: call void @llvm.memset.p0i8.i64(i8* align 1 %[[#]], i8 0, i64 1, i1 false) -; CHECK: store i64 0, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK: call void @Fn8(i8* %p) +; CHECK: call void @llvm.memset.p0.i64(ptr align 1 %[[#]], i8 0, i64 1, i1 false) +; CHECK: store i64 0, ptr @__msan_param_tls, align 8 +; CHECK: call void @Fn8(ptr %p) ; CHECK: ret void ; entry: - call void @Fn8(i8* %p) + call void @Fn8(ptr %p) ret void } -define void @ByValForwardByVal8(i32, i8* byval(i8) %p) sanitize_memory { +define void @ByValForwardByVal8(i32, ptr byval(i8) %p) sanitize_memory { ; CHECK-LABEL: @ByValForwardByVal8( ; CHECK-NEXT: entry: -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 %[[#]], i8* align 1 inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i8*), i64 1, i1 false) -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %[[#]], i8* align 4 inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i8*), i64 4, i1 false) -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast ([100 x i64]* @__msan_param_tls to i8*), i8* %[[#]], i64 1, i1 false) -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([200 x i32]* @__msan_param_origin_tls to i8*), i8* align 4 %[[#]], i64 4, i1 false) -; CHECK: call void @FnByVal8(i8* byval(i8) %p) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 1 %[[#]], ptr align 1 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), i64 1, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 4 %[[#]], ptr align 4 inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), i64 4, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr @__msan_param_tls, ptr %[[#]], i64 1, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 4 @__msan_param_origin_tls, ptr align 4 %[[#]], i64 4, i1 false) +; CHECK: call void @FnByVal8(ptr byval(i8) %p) ; CHECK: ret void ; entry: - call void @FnByVal8(i8* byval(i8) %p) + call void @FnByVal8(ptr byval(i8) %p) ret void } -define void @ByValForwardByValNoSanitize8(i32, i8* byval(i8) %p) { +define void @ByValForwardByValNoSanitize8(i32, ptr byval(i8) %p) { ; CHECK-LABEL: @ByValForwardByValNoSanitize8( ; CHECK-NEXT: entry: -; CHECK: call void @llvm.memset.p0i8.i64(i8* align 1 %[[#]], i8 0, i64 1, i1 false) -; CHECK: call void @llvm.memset.p0i8.i64(i8* bitcast ([100 x i64]* @__msan_param_tls to i8*), i8 0, i64 1, i1 false) -; CHECK: call void @FnByVal8(i8* byval(i8) %p) +; CHECK: call void @llvm.memset.p0.i64(ptr align 1 %[[#]], i8 0, i64 1, i1 false) +; CHECK: call void @llvm.memset.p0.i64(ptr @__msan_param_tls, i8 0, i64 1, i1 false) +; CHECK: call void @FnByVal8(ptr byval(i8) %p) ; CHECK: ret void ; entry: - call void @FnByVal8(i8* byval(i8) %p) + call void @FnByVal8(ptr byval(i8) %p) ret void } diff --git a/llvm/test/Instrumentation/MemorySanitizer/check-array.ll b/llvm/test/Instrumentation/MemorySanitizer/check-array.ll --- a/llvm/test/Instrumentation/MemorySanitizer/check-array.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/check-array.ll @@ -4,10 +4,10 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define noundef [2 x i24] @check_array([2 x i24]* %p) sanitize_memory { -; CHECK: @check_array([2 x i24]* [[P:%.*]]) -; CHECK: [[O:%.*]] = load [2 x i24], [2 x i24]* [[P]] - %o = load [2 x i24], [2 x i24]* %p +define noundef [2 x i24] @check_array(ptr %p) sanitize_memory { +; CHECK: @check_array(ptr [[P:%.*]]) +; CHECK: [[O:%.*]] = load [2 x i24], ptr [[P]] + %o = load [2 x i24], ptr %p ; CHECK: [[FIELD0:%.+]] = extractvalue [2 x i24] %_msld, 0 ; CHECK: [[FIELD1:%.+]] = extractvalue [2 x i24] %_msld, 1 ; CHECK: [[F1_OR:%.+]] = or i24 [[FIELD0]], [[FIELD1]] diff --git a/llvm/test/Instrumentation/MemorySanitizer/check-constant-shadow.ll b/llvm/test/Instrumentation/MemorySanitizer/check-constant-shadow.ll --- a/llvm/test/Instrumentation/MemorySanitizer/check-constant-shadow.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/check-constant-shadow.ll @@ -13,16 +13,16 @@ } ; CHECK-LABEL: @main -; CHECK: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*) +; CHECK: store i32 0, ptr @__msan_retval_tls ; CONST: call void @__msan_warning_with_origin_noreturn ; CHECK: ret i32 undef ; This function stores known initialized value. ; Expect 2 stores: one for the shadow (0), one for the value (42), but no origin. -define void @StoreConstant(i32* nocapture %p) nounwind uwtable sanitize_memory { +define void @StoreConstant(ptr nocapture %p) nounwind uwtable sanitize_memory { entry: - store i32 42, i32* %p, align 4 + store i32 42, ptr %p, align 4 ret void } @@ -35,9 +35,9 @@ ; This function stores known uninitialized value. ; Expect 3 stores: shadow, value and origin. ; Expect no icmp(s): everything here is unconditional. -define void @StoreUndef(i32* nocapture %p) nounwind uwtable sanitize_memory { +define void @StoreUndef(ptr nocapture %p) nounwind uwtable sanitize_memory { entry: - store i32 undef, i32* %p, align 4 + store i32 undef, ptr %p, align 4 ret void } @@ -59,8 +59,8 @@ } ; CHECK-LABEL: @MaybeUninitialized -; CHECK: store i32 extractelement (<4 x i32> bitcast (<2 x i64> to <4 x i32>), i64 0), i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 -; CHECK: store i32 0, i32* @__msan_retval_origin_tls +; CHECK: store i32 extractelement (<4 x i32> bitcast (<2 x i64> to <4 x i32>), i64 0), ptr @__msan_retval_tls, align 8 +; CHECK: store i32 0, ptr @__msan_retval_origin_tls ; This function stores known initialized value, but msan can't prove this. define noundef i32 @MaybeUninitializedRetNoUndef(<2 x i64> noundef %acc) nounwind uwtable sanitize_memory { diff --git a/llvm/test/Instrumentation/MemorySanitizer/check-struct.ll b/llvm/test/Instrumentation/MemorySanitizer/check-struct.ll --- a/llvm/test/Instrumentation/MemorySanitizer/check-struct.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/check-struct.ll @@ -6,10 +6,10 @@ ; CHECK-LABEL: @main define { i32, i8 } @main() sanitize_memory { -; CHECK: [[P:%.*]] = inttoptr i64 0 to { i32, i8 }* - %p = inttoptr i64 0 to { i32, i8 } * -; CHECK: [[O:%.*]] = load { i32, i8 }, { i32, i8 }* [[P]] - %o = load { i32, i8 }, { i32, i8 } *%p +; CHECK: [[P:%.*]] = inttoptr i64 0 to ptr + %p = inttoptr i64 0 to ptr +; CHECK: [[O:%.*]] = load { i32, i8 }, ptr [[P]] + %o = load { i32, i8 }, ptr %p ; CHECK: [[FIELD0:%.+]] = extractvalue { i32, i8 } %_msld, 0 ; CHECK: [[F0_POISONED:%.+]] = icmp ne i32 [[FIELD0]] ; CHECK: [[FIELD1:%.+]] = extractvalue { i32, i8 } %_msld, 1 diff --git a/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll b/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll --- a/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/check_access_address.ll @@ -6,33 +6,33 @@ ; Test byval argument shadow alignment -define <2 x i64> @ByValArgumentShadowLargeAlignment(<2 x i64>* byval(<2 x i64>) %p) sanitize_memory { +define <2 x i64> @ByValArgumentShadowLargeAlignment(ptr byval(<2 x i64>) %p) sanitize_memory { entry: - %x = load <2 x i64>, <2 x i64>* %p + %x = load <2 x i64>, ptr %p ret <2 x i64> %x } ; CHECK-LABEL: @ByValArgumentShadowLargeAlignment -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 {{.*}}, i8* align 8 {{.*}}, i64 16, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 {{.*}}, ptr align 8 {{.*}}, i64 16, i1 false) ; CHECK: ret <2 x i64> -define i16 @ByValArgumentShadowSmallAlignment(i16* byval(i16) %p) sanitize_memory { +define i16 @ByValArgumentShadowSmallAlignment(ptr byval(i16) %p) sanitize_memory { entry: - %x = load i16, i16* %p + %x = load i16, ptr %p ret i16 %x } ; CHECK-LABEL: @ByValArgumentShadowSmallAlignment -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 {{.*}}, i8* align 2 {{.*}}, i64 2, i1 false) +; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 2 {{.*}}, ptr align 2 {{.*}}, i64 2, i1 false) ; CHECK: ret i16 ; Check instrumentation of stores. The check must precede the shadow store. -define void @Store(i32* nocapture %p, i32 %x) nounwind uwtable sanitize_memory { +define void @Store(ptr nocapture %p, i32 %x) nounwind uwtable sanitize_memory { entry: - store i32 %x, i32* %p, align 4 + store i32 %x, ptr %p, align 4 ret void } diff --git a/llvm/test/Instrumentation/MemorySanitizer/clmul.ll b/llvm/test/Instrumentation/MemorySanitizer/clmul.ll --- a/llvm/test/Instrumentation/MemorySanitizer/clmul.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/clmul.ll @@ -67,4 +67,4 @@ ; ORIGIN: %[[I:.*]] = icmp ne i512 %[[FLAT]], 0 ; ORIGIN: %[[O:.*]] = select i1 %[[I]], ; CHECK: store <8 x i64> %[[SRET]], ptr {{.*}}@__msan_retval_tls -; ORIGIN: store i32 %[[O]], i32* @__msan_retval_origin_tls +; ORIGIN: store i32 %[[O]], ptr @__msan_retval_origin_tls diff --git a/llvm/test/Instrumentation/MemorySanitizer/csr.ll b/llvm/test/Instrumentation/MemorySanitizer/csr.ll --- a/llvm/test/Instrumentation/MemorySanitizer/csr.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/csr.ll @@ -6,23 +6,22 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare void @llvm.x86.sse.stmxcsr(i8*) -declare void @llvm.x86.sse.ldmxcsr(i8*) +declare void @llvm.x86.sse.stmxcsr(ptr) +declare void @llvm.x86.sse.ldmxcsr(ptr) -define void @getcsr(i32 *%p) sanitize_memory { +define void @getcsr(ptr %p) sanitize_memory { entry: - %0 = bitcast i32* %p to i8* - call void @llvm.x86.sse.stmxcsr(i8* %0) + call void @llvm.x86.sse.stmxcsr(ptr %p) ret void } ; CHECK-LABEL: @getcsr( -; CHECK: store i32 0, i32* +; CHECK: store i32 0, ptr ; CHECK: call void @llvm.x86.sse.stmxcsr( ; CHECK: ret void ; ADDR-LABEL: @getcsr( -; ADDR: %[[A:.*]] = load i64, i64* getelementptr inbounds {{.*}} @__msan_param_tls, i32 0, i32 0), align 8 +; ADDR: %[[A:.*]] = load i64, ptr @__msan_param_tls, align 8 ; ADDR: %[[B:.*]] = icmp ne i64 %[[A]], 0 ; ADDR: br i1 %[[B]], label {{.*}}, label ; ADDR: call void @__msan_warning_noreturn() @@ -30,15 +29,14 @@ ; ADDR: ret void ; Function Attrs: nounwind uwtable -define void @setcsr(i32 *%p) sanitize_memory { +define void @setcsr(ptr %p) sanitize_memory { entry: - %0 = bitcast i32* %p to i8* - call void @llvm.x86.sse.ldmxcsr(i8* %0) + call void @llvm.x86.sse.ldmxcsr(ptr %p) ret void } ; CHECK-LABEL: @setcsr( -; CHECK: %[[A:.*]] = load i32, i32* %{{.*}}, align 1 +; CHECK: %[[A:.*]] = load i32, ptr %{{.*}}, align 1 ; CHECK: %[[B:.*]] = icmp ne i32 %[[A]], 0 ; CHECK: br i1 %[[B]], label {{.*}}, label ; CHECK: call void @__msan_warning_noreturn() @@ -46,8 +44,8 @@ ; CHECK: ret void ; ADDR-LABEL: @setcsr( -; ADDR: %[[A:.*]] = load i64, i64* getelementptr inbounds {{.*}} @__msan_param_tls, i32 0, i32 0), align 8 -; ADDR: %[[C:.*]] = load i32, i32* +; ADDR: %[[A:.*]] = load i64, ptr @__msan_param_tls, align 8 +; ADDR: %[[C:.*]] = load i32, ptr ; ADDR: %[[B:.*]] = icmp ne i64 %[[A]], 0 ; ADDR: %[[D:.*]] = icmp ne i32 %[[C]], 0 ; ADDR: %[[E:.*]] = or i1 %[[B]], %[[D]] diff --git a/llvm/test/Instrumentation/MemorySanitizer/disambiguate-origin.ll b/llvm/test/Instrumentation/MemorySanitizer/disambiguate-origin.ll --- a/llvm/test/Instrumentation/MemorySanitizer/disambiguate-origin.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/disambiguate-origin.ll @@ -20,18 +20,18 @@ declare void @OneArg(i32 noundef %a) nounwind uwtable sanitize_memory; declare void @ManyArgs(i32 noundef %a, i32 noundef %b, i32 noundef %c) nounwind uwtable sanitize_memory; -define void @TestOne(i32* noundef %a) nounwind uwtable sanitize_memory { +define void @TestOne(ptr noundef %a) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @TestOne( ; CHECK-NEXT: entry: ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1:![0-9]+]] -; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[A:%.*]], align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i32* [[A]] to i64, !dbg [[DBG1]] +; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[A:%.*]], align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to i32*, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP1]], 17592186044416, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to i32*, !dbg [[DBG1]] -; CHECK-NEXT: [[_MSLD:%.*]] = load i32, i32* [[TMP2]], align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr, !dbg [[DBG1]] +; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG1]] ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[_MSLD]], 0, !dbg [[DBG7:![0-9]+]] ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP6:%.*]], label [[TMP7:%.*]], !dbg [[DBG7]], !prof [[PROF8:![0-9]+]] ; CHECK: 6: @@ -42,39 +42,39 @@ ; CHECK-NEXT: ret void ; entry: - %v = load i32, i32* %a, !dbg !11 + %v = load i32, ptr %a, !dbg !11 call void @OneArg(i32 noundef %v), !dbg !10 ret void } -define void @TestMany(i32* noundef %a) nounwind uwtable sanitize_memory { +define void @TestMany(ptr noundef %a) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @TestMany( ; CHECK-NEXT: entry: ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] -; CHECK-NEXT: [[X:%.*]] = load i32, i32* [[A:%.*]], align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i32* [[A]] to i64, !dbg [[DBG1]] +; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[A:%.*]], align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to i32*, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP1]], 17592186044416, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to i32*, !dbg [[DBG1]] -; CHECK-NEXT: [[_MSLD:%.*]] = load i32, i32* [[TMP2]], align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[Y:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG9:![0-9]+]] -; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint i32* [[A]] to i64, !dbg [[DBG9]] +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr, !dbg [[DBG1]] +; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP2]], align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[Y:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG9:![0-9]+]] +; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i64, !dbg [[DBG9]] ; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 87960930222080, !dbg [[DBG9]] -; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to i32*, !dbg [[DBG9]] +; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr, !dbg [[DBG9]] ; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP7]], 17592186044416, !dbg [[DBG9]] -; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to i32*, !dbg [[DBG9]] -; CHECK-NEXT: [[_MSLD1:%.*]] = load i32, i32* [[TMP8]], align 4, !dbg [[DBG9]] -; CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4, !dbg [[DBG9]] -; CHECK-NEXT: [[Z:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG10:![0-9]+]] -; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint i32* [[A]] to i64, !dbg [[DBG10]] +; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr, !dbg [[DBG9]] +; CHECK-NEXT: [[_MSLD1:%.*]] = load i32, ptr [[TMP8]], align 4, !dbg [[DBG9]] +; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG9]] +; CHECK-NEXT: [[Z:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG10:![0-9]+]] +; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[A]] to i64, !dbg [[DBG10]] ; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 87960930222080, !dbg [[DBG10]] -; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to i32*, !dbg [[DBG10]] +; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr, !dbg [[DBG10]] ; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP13]], 17592186044416, !dbg [[DBG10]] -; CHECK-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP15]] to i32*, !dbg [[DBG10]] -; CHECK-NEXT: [[_MSLD2:%.*]] = load i32, i32* [[TMP14]], align 4, !dbg [[DBG10]] -; CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4, !dbg [[DBG10]] +; CHECK-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP15]] to ptr, !dbg [[DBG10]] +; CHECK-NEXT: [[_MSLD2:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG10]] +; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4, !dbg [[DBG10]] ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[_MSLD]], 0, !dbg [[DBG7]] ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP18:%.*]], label [[TMP20:%.*]], !dbg [[DBG7]], !prof [[PROF8]] ; CHECK: 18: @@ -100,9 +100,9 @@ ; CHECK-NEXT: ret void ; entry: - %x = load i32, i32* %a, !dbg !11 - %y = load i32, i32* %a, !dbg !12 - %z = load i32, i32* %a, !dbg !13 + %x = load i32, ptr %a, !dbg !11 + %y = load i32, ptr %a, !dbg !12 + %z = load i32, ptr %a, !dbg !13 call void @ManyArgs(i32 noundef %x, i32 noundef %y, i32 noundef %z), !dbg !10 ret void } diff --git a/llvm/test/Instrumentation/MemorySanitizer/freeze.ll b/llvm/test/Instrumentation/MemorySanitizer/freeze.ll --- a/llvm/test/Instrumentation/MemorySanitizer/freeze.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/freeze.ll @@ -3,18 +3,18 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define i32 @nofreeze(i32* %ptr) sanitize_memory { +define i32 @nofreeze(ptr %ptr) sanitize_memory { ; CHECK-LABEL: @nofreeze - %val = load i32, i32* %ptr + %val = load i32, ptr %ptr ; CHECK: [[SHADOW_PTR:%.*]] = inttoptr - ; CHECK: [[SHADOW:%.*]] = load i32, i32* [[SHADOW_PTR]] + ; CHECK: [[SHADOW:%.*]] = load i32, ptr [[SHADOW_PTR]] ; CHECK: store i32 [[SHADOW]], {{.*}} @__msan_retval_tls ret i32 %val } -define i32 @freeze_inst(i32* %ptr) sanitize_memory { +define i32 @freeze_inst(ptr %ptr) sanitize_memory { ; CHECK-LABEL: @freeze_inst - %val = load i32, i32* %ptr + %val = load i32, ptr %ptr %freeze_val = freeze i32 %val ; CHECK-NOT: __msan_warning ; CHECK: store i32 0, {{.*}} @__msan_retval_tls diff --git a/llvm/test/Instrumentation/MemorySanitizer/instrumentation-with-call-threshold.ll b/llvm/test/Instrumentation/MemorySanitizer/instrumentation-with-call-threshold.ll --- a/llvm/test/Instrumentation/MemorySanitizer/instrumentation-with-call-threshold.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/instrumentation-with-call-threshold.ll @@ -17,9 +17,9 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define void @LoadAndCmp(i32* nocapture %a) nounwind uwtable sanitize_memory { +define void @LoadAndCmp(ptr nocapture %a) nounwind uwtable sanitize_memory { entry: - %0 = load i32, i32* %a, align 4 + %0 = load i32, ptr %a, align 4 %tobool = icmp eq i32 %0, 0 br i1 %tobool, label %if.end, label %if.then @@ -42,9 +42,9 @@ ; CHECK: ret void -define void @Store(i64* nocapture %p, i64 %x) nounwind uwtable sanitize_memory { +define void @Store(ptr nocapture %p, i64 %x) nounwind uwtable sanitize_memory { entry: - store i64 %x, i64* %p, align 4 + store i64 %x, ptr %p, align 4 ret void } @@ -53,9 +53,7 @@ ; CHECK-ORIGINS: load {{.*}} @__msan_param_origin_tls ; CHECK: store ; CHECK-ORIGINS-NOT: __msan_chain_origin -; CHECK-ORIGINS: bitcast i64* {{.*}} to i8* -; CHECK-ORIGINS-NOT: __msan_chain_origin -; CHECK-ORIGINS: call void @__msan_maybe_store_origin_8(i64 zeroext {{.*}}, i8* {{.*}}, i32 zeroext {{.*}}) +; CHECK-ORIGINS: call void @__msan_maybe_store_origin_8(i64 zeroext {{.*}}, ptr {{.*}}, i32 zeroext {{.*}}) ; CHECK-ORIGINS-NOT: __msan_chain_origin ; CHECK: store i64 ; CHECK: ret void diff --git a/llvm/test/Instrumentation/MemorySanitizer/libatomic.ll b/llvm/test/Instrumentation/MemorySanitizer/libatomic.ll --- a/llvm/test/Instrumentation/MemorySanitizer/libatomic.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/libatomic.ll @@ -3,66 +3,58 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare void @__atomic_load(i64, i8*, i8*, i32) -declare void @__atomic_store(i64, i8*, i8*, i32) +declare void @__atomic_load(i64, ptr, ptr, i32) +declare void @__atomic_store(i64, ptr, ptr, i32) -define i24 @odd_sized_load(i24* %ptr) sanitize_memory { -; CHECK: @odd_sized_load(i24* {{.*}}[[PTR:%.+]]) +define i24 @odd_sized_load(ptr %ptr) sanitize_memory { +; CHECK: @odd_sized_load(ptr {{.*}}[[PTR:%.+]]) ; CHECK: [[VAL_PTR:%.*]] = alloca i24, align 1 ; CHECK-ORIGIN: @__msan_set_alloca_origin -; CHECK: [[VAL_PTR_I8:%.*]] = bitcast i24* [[VAL_PTR]] to i8* -; CHECK: [[PTR_I8:%.*]] = bitcast i24* [[PTR]] to i8* -; CHECK: call void @__atomic_load(i64 3, i8* [[PTR_I8]], i8* [[VAL_PTR_I8]], i32 2) +; CHECK: call void @__atomic_load(i64 3, ptr [[PTR]], ptr [[VAL_PTR]], i32 2) -; CHECK: ptrtoint i8* [[PTR_I8]] +; CHECK: ptrtoint ptr [[PTR]] ; CHECK: xor ; CHECK: [[SPTR_I8:%.*]] = inttoptr ; CHECK-ORIGIN: add ; CHECK-ORIGIN: and ; CHECK-ORIGIN: [[OPTR:%.*]] = inttoptr -; CHECK: ptrtoint i8* [[VAL_PTR_I8]] +; CHECK: ptrtoint ptr [[VAL_PTR]] ; CHECK: xor ; CHECK: [[VAL_SPTR_I8:%.*]] = inttoptr ; CHECK-ORIGIN: add ; CHECK-ORIGIN: and ; CHECK-ORIGIN: [[VAL_OPTR:%.*]] = inttoptr -; CHECK: call void @llvm.memcpy{{.*}}(i8* align 1 [[VAL_SPTR_I8]], i8* align 1 [[SPTR_I8]], i64 3 +; CHECK: call void @llvm.memcpy{{.*}}(ptr align 1 [[VAL_SPTR_I8]], ptr align 1 [[SPTR_I8]], i64 3 -; CHECK-ORIGIN: [[ARG_ORIGIN:%.*]] = load i32, i32* [[OPTR]] +; CHECK-ORIGIN: [[ARG_ORIGIN:%.*]] = load i32, ptr [[OPTR]] ; CHECK-ORIGIN: [[VAL_ORIGIN:%.*]] = call i32 @__msan_chain_origin(i32 [[ARG_ORIGIN]]) -; CHECK-ORIGIN: call void @__msan_set_origin(i8* [[VAL_PTR_I8]], i64 3, i32 [[VAL_ORIGIN]]) +; CHECK-ORIGIN: call void @__msan_set_origin(ptr [[VAL_PTR]], i64 3, i32 [[VAL_ORIGIN]]) -; CHECK: [[VAL:%.*]] = load i24, i24* [[VAL_PTR]] +; CHECK: [[VAL:%.*]] = load i24, ptr [[VAL_PTR]] ; CHECK: ret i24 [[VAL]] %val_ptr = alloca i24, align 1 - %val_ptr_i8 = bitcast i24* %val_ptr to i8* - %ptr_i8 = bitcast i24* %ptr to i8* - call void @__atomic_load(i64 3, i8* %ptr_i8, i8* %val_ptr_i8, i32 0) - %val = load i24, i24* %val_ptr + call void @__atomic_load(i64 3, ptr %ptr, ptr %val_ptr, i32 0) + %val = load i24, ptr %val_ptr ret i24 %val } -define void @odd_sized_store(i24* %ptr, i24 %val) sanitize_memory { -; CHECK: @odd_sized_store(i24* {{.*}}[[PTR:%.+]], i24 {{.*}}[[VAL:%.+]]) +define void @odd_sized_store(ptr %ptr, i24 %val) sanitize_memory { +; CHECK: @odd_sized_store(ptr {{.*}}[[PTR:%.+]], i24 {{.*}}[[VAL:%.+]]) ; CHECK: [[VAL_PTR:%.*]] = alloca i24, align 1 -; CHECK: store i24 [[VAL]], i24* [[VAL_PTR]] -; CHECK: [[VAL_PTR_I8:%.*]] = bitcast i24* [[VAL_PTR]] to i8* -; CHECK: [[PTR_I8:%.*]] = bitcast i24* [[PTR]] to i8* +; CHECK: store i24 [[VAL]], ptr [[VAL_PTR]] -; CHECK: ptrtoint i8* [[PTR_I8]] +; CHECK: ptrtoint ptr [[PTR]] ; CHECK: xor ; CHECK: [[SPTR_I8:%.*]] = inttoptr -; CHECK: call void @llvm.memset{{.*}}(i8* align 1 [[SPTR_I8]], i8 0, i64 3 +; CHECK: call void @llvm.memset{{.*}}(ptr align 1 [[SPTR_I8]], i8 0, i64 3 -; CHECK: call void @__atomic_store(i64 3, i8* [[VAL_PTR_I8]], i8* [[PTR_I8]], i32 3) +; CHECK: call void @__atomic_store(i64 3, ptr [[VAL_PTR]], ptr [[PTR]], i32 3) ; CHECK: ret void %val_ptr = alloca i24, align 1 - store i24 %val, i24* %val_ptr - %val_ptr_i8 = bitcast i24* %val_ptr to i8* - %ptr_i8 = bitcast i24* %ptr to i8* - call void @__atomic_store(i64 3, i8* %val_ptr_i8, i8* %ptr_i8, i32 0) + store i24 %val, ptr %val_ptr + call void @__atomic_store(i64 3, ptr %val_ptr, ptr %ptr, i32 0) ret void } diff --git a/llvm/test/Instrumentation/MemorySanitizer/manual-shadow.ll b/llvm/test/Instrumentation/MemorySanitizer/manual-shadow.ll --- a/llvm/test/Instrumentation/MemorySanitizer/manual-shadow.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/manual-shadow.ll @@ -14,9 +14,9 @@ target triple = "x86_64-unknown-linux-gnu" -define i32 @read_value(i32* %a) sanitize_memory { +define i32 @read_value(ptr %a) sanitize_memory { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } ; CHECK-BASE-LABEL: @read_value diff --git a/llvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll b/llvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll --- a/llvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/masked-store-load.ll @@ -9,35 +9,35 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare void @llvm.masked.store.v4i64.p0v4i64(<4 x i64>, <4 x i64>*, i32, <4 x i1>) -declare <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>*, i32, <4 x i1>, <4 x double>) -declare <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x float*>, i32, <16 x i1>, <16 x float>) -declare void @llvm.masked.scatter.v8i32.v8p0 (<8 x i32>, <8 x i32*>, i32, <8 x i1>) -declare <16 x float> @llvm.masked.expandload.v16f32(float*, <16 x i1>, <16 x float>) -declare void @llvm.masked.compressstore.v16f32(<16 x float>, float*, <16 x i1>) +declare void @llvm.masked.store.v4i64.p0(<4 x i64>, ptr, i32, <4 x i1>) +declare <4 x double> @llvm.masked.load.v4f64.p0(ptr, i32, <4 x i1>, <4 x double>) +declare <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr>, i32, <16 x i1>, <16 x float>) +declare void @llvm.masked.scatter.v8i32.v8p0 (<8 x i32>, <8 x ptr>, i32, <8 x i1>) +declare <16 x float> @llvm.masked.expandload.v16f32(ptr, <16 x i1>, <16 x float>) +declare void @llvm.masked.compressstore.v16f32(<16 x float>, ptr, <16 x i1>) -define void @Store(<4 x i64>* %p, <4 x i64> %v, <4 x i1> %mask) sanitize_memory { +define void @Store(ptr %p, <4 x i64> %v, <4 x i1> %mask) sanitize_memory { ; CHECK-LABEL: @Store( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint <4 x i64>* [[P:%.*]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080 -; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to <4 x i64>* -; CHECK-NEXT: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> [[TMP0]], <4 x i64>* [[TMP3]], i32 1, <4 x i1> [[MASK:%.*]]) -; CHECK-NEXT: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> [[V:%.*]], <4 x i64>* [[P]], i32 1, <4 x i1> [[MASK]]) +; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; CHECK-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[TMP0]], ptr [[TMP3]], i32 1, <4 x i1> [[MASK:%.*]]) +; CHECK-NEXT: tail call void @llvm.masked.store.v4i64.p0(<4 x i64> [[V:%.*]], ptr [[P]], i32 1, <4 x i1> [[MASK]]) ; CHECK-NEXT: ret void ; ; ADDR-LABEL: @Store( ; ADDR-NEXT: entry: -; ADDR-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i64>*), align 8 -; ADDR-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; ADDR-NEXT: [[TMP2:%.*]] = load <4 x i1>, <4 x i1>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i1>*), align 8 +; ADDR-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; ADDR-NEXT: [[TMP2:%.*]] = load <4 x i1>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 ; ADDR-NEXT: call void @llvm.donothing() -; ADDR-NEXT: [[TMP3:%.*]] = ptrtoint <4 x i64>* [[P:%.*]] to i64 +; ADDR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; ADDR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080 -; ADDR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to <4 x i64>* -; ADDR-NEXT: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> [[TMP0]], <4 x i64>* [[TMP5]], i32 1, <4 x i1> [[MASK:%.*]]) +; ADDR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr +; ADDR-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[TMP0]], ptr [[TMP5]], i32 1, <4 x i1> [[MASK:%.*]]) ; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; ADDR-NEXT: [[TMP6:%.*]] = bitcast <4 x i1> [[TMP2]] to i4 ; ADDR-NEXT: [[_MSCMP1:%.*]] = icmp ne i4 [[TMP6]], 0 @@ -47,67 +47,67 @@ ; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR7:[0-9]+]] ; ADDR-NEXT: unreachable ; ADDR: 8: -; ADDR-NEXT: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> [[V:%.*]], <4 x i64>* [[P]], i32 1, <4 x i1> [[MASK]]) +; ADDR-NEXT: tail call void @llvm.masked.store.v4i64.p0(<4 x i64> [[V:%.*]], ptr [[P]], i32 1, <4 x i1> [[MASK]]) ; ADDR-NEXT: ret void ; ; ORIGINS-LABEL: @Store( ; ORIGINS-NEXT: entry: -; ORIGINS-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i64>*), align 8 -; ORIGINS-NEXT: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i32*), align 4 +; ORIGINS-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; ORIGINS-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4 ; ORIGINS-NEXT: call void @llvm.donothing() -; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint <4 x i64>* [[P:%.*]] to i64 +; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 -; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to <4 x i64>* +; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr ; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416 ; ORIGINS-NEXT: [[TMP6:%.*]] = and i64 [[TMP5]], -4 -; ORIGINS-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i32* -; ORIGINS-NEXT: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> [[TMP0]], <4 x i64>* [[TMP4]], i32 1, <4 x i1> [[MASK:%.*]]) -; ORIGINS-NEXT: store i32 [[TMP1]], i32* [[TMP7]], align 4 -; ORIGINS-NEXT: [[TMP8:%.*]] = getelementptr i32, i32* [[TMP7]], i32 1 -; ORIGINS-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 -; ORIGINS-NEXT: [[TMP9:%.*]] = getelementptr i32, i32* [[TMP7]], i32 2 -; ORIGINS-NEXT: store i32 [[TMP1]], i32* [[TMP9]], align 4 -; ORIGINS-NEXT: [[TMP10:%.*]] = getelementptr i32, i32* [[TMP7]], i32 3 -; ORIGINS-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 -; ORIGINS-NEXT: [[TMP11:%.*]] = getelementptr i32, i32* [[TMP7]], i32 4 -; ORIGINS-NEXT: store i32 [[TMP1]], i32* [[TMP11]], align 4 -; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, i32* [[TMP7]], i32 5 -; ORIGINS-NEXT: store i32 [[TMP1]], i32* [[TMP12]], align 4 -; ORIGINS-NEXT: [[TMP13:%.*]] = getelementptr i32, i32* [[TMP7]], i32 6 -; ORIGINS-NEXT: store i32 [[TMP1]], i32* [[TMP13]], align 4 -; ORIGINS-NEXT: [[TMP14:%.*]] = getelementptr i32, i32* [[TMP7]], i32 7 -; ORIGINS-NEXT: store i32 [[TMP1]], i32* [[TMP14]], align 4 -; ORIGINS-NEXT: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> [[V:%.*]], <4 x i64>* [[P]], i32 1, <4 x i1> [[MASK]]) +; ORIGINS-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; ORIGINS-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> [[TMP0]], ptr [[TMP4]], i32 1, <4 x i1> [[MASK:%.*]]) +; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4 +; ORIGINS-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i32 1 +; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4 +; ORIGINS-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP7]], i32 2 +; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP9]], align 4 +; ORIGINS-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP7]], i32 3 +; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP10]], align 4 +; ORIGINS-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP7]], i32 4 +; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP11]], align 4 +; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP7]], i32 5 +; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP12]], align 4 +; ORIGINS-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP7]], i32 6 +; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP13]], align 4 +; ORIGINS-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP7]], i32 7 +; ORIGINS-NEXT: store i32 [[TMP1]], ptr [[TMP14]], align 4 +; ORIGINS-NEXT: tail call void @llvm.masked.store.v4i64.p0(<4 x i64> [[V:%.*]], ptr [[P]], i32 1, <4 x i1> [[MASK]]) ; ORIGINS-NEXT: ret void ; entry: - tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1> %mask) + tail call void @llvm.masked.store.v4i64.p0(<4 x i64> %v, ptr %p, i32 1, <4 x i1> %mask) ret void } -define <4 x double> @Load(<4 x double>* %p, <4 x double> %v, <4 x i1> %mask) sanitize_memory { +define <4 x double> @Load(ptr %p, <4 x double> %v, <4 x i1> %mask) sanitize_memory { ; CHECK-LABEL: @Load( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint <4 x double>* [[P:%.*]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080 -; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to <4 x i64>* -; CHECK-NEXT: [[_MSMASKEDLD:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* [[TMP3]], i32 1, <4 x i1> [[MASK:%.*]], <4 x i64> [[TMP0]]) -; CHECK-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* [[P]], i32 1, <4 x i1> [[MASK]], <4 x double> [[V:%.*]]) -; CHECK-NEXT: store <4 x i64> [[_MSMASKEDLD]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; CHECK-NEXT: [[_MSMASKEDLD:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr [[TMP3]], i32 1, <4 x i1> [[MASK:%.*]], <4 x i64> [[TMP0]]) +; CHECK-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr [[P]], i32 1, <4 x i1> [[MASK]], <4 x double> [[V:%.*]]) +; CHECK-NEXT: store <4 x i64> [[_MSMASKEDLD]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[X]] ; ; ADDR-LABEL: @Load( ; ADDR-NEXT: entry: -; ADDR-NEXT: [[TMP0:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; ADDR-NEXT: [[TMP1:%.*]] = load <4 x i1>, <4 x i1>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 40) to <4 x i1>*), align 8 -; ADDR-NEXT: [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i64>*), align 8 +; ADDR-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; ADDR-NEXT: [[TMP1:%.*]] = load <4 x i1>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 40) to ptr), align 8 +; ADDR-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; ADDR-NEXT: call void @llvm.donothing() -; ADDR-NEXT: [[TMP3:%.*]] = ptrtoint <4 x double>* [[P:%.*]] to i64 +; ADDR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; ADDR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080 -; ADDR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to <4 x i64>* -; ADDR-NEXT: [[_MSMASKEDLD:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* [[TMP5]], i32 1, <4 x i1> [[MASK:%.*]], <4 x i64> [[TMP2]]) +; ADDR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr +; ADDR-NEXT: [[_MSMASKEDLD:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr [[TMP5]], i32 1, <4 x i1> [[MASK:%.*]], <4 x i64> [[TMP2]]) ; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP0]], 0 ; ADDR-NEXT: [[TMP6:%.*]] = bitcast <4 x i1> [[TMP1]] to i4 ; ADDR-NEXT: [[_MSCMP1:%.*]] = icmp ne i4 [[TMP6]], 0 @@ -117,144 +117,144 @@ ; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] ; ADDR-NEXT: unreachable ; ADDR: 8: -; ADDR-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* [[P]], i32 1, <4 x i1> [[MASK]], <4 x double> [[V:%.*]]) -; ADDR-NEXT: store <4 x i64> [[_MSMASKEDLD]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; ADDR-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr [[P]], i32 1, <4 x i1> [[MASK]], <4 x double> [[V:%.*]]) +; ADDR-NEXT: store <4 x i64> [[_MSMASKEDLD]], ptr @__msan_retval_tls, align 8 ; ADDR-NEXT: ret <4 x double> [[X]] ; ; ORIGINS-LABEL: @Load( ; ORIGINS-NEXT: entry: -; ORIGINS-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <4 x i64>*), align 8 -; ORIGINS-NEXT: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i32*), align 4 +; ORIGINS-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; ORIGINS-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4 ; ORIGINS-NEXT: call void @llvm.donothing() -; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint <4 x double>* [[P:%.*]] to i64 +; ORIGINS-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; ORIGINS-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 -; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to <4 x i64>* +; ORIGINS-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr ; ORIGINS-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], 17592186044416 ; ORIGINS-NEXT: [[TMP6:%.*]] = and i64 [[TMP5]], -4 -; ORIGINS-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i32* -; ORIGINS-NEXT: [[_MSMASKEDLD:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* [[TMP4]], i32 1, <4 x i1> [[MASK:%.*]], <4 x i64> [[TMP0]]) +; ORIGINS-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; ORIGINS-NEXT: [[_MSMASKEDLD:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0(ptr [[TMP4]], i32 1, <4 x i1> [[MASK:%.*]], <4 x i64> [[TMP0]]) ; ORIGINS-NEXT: [[TMP8:%.*]] = sub <4 x i1> zeroinitializer, [[MASK]] ; ORIGINS-NEXT: [[TMP9:%.*]] = sext <4 x i1> [[TMP8]] to <4 x i64> ; ORIGINS-NEXT: [[TMP10:%.*]] = and <4 x i64> [[TMP0]], [[TMP9]] ; ORIGINS-NEXT: [[TMP11:%.*]] = bitcast <4 x i64> [[TMP10]] to i256 ; ORIGINS-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP11]], 0 -; ORIGINS-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP7]], align 4 +; ORIGINS-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP7]], align 4 ; ORIGINS-NEXT: [[TMP13:%.*]] = select i1 [[_MSCMP]], i32 [[TMP1]], i32 [[TMP12]] -; ORIGINS-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* [[P]], i32 1, <4 x i1> [[MASK]], <4 x double> [[V:%.*]]) -; ORIGINS-NEXT: store <4 x i64> [[_MSMASKEDLD]], <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 -; ORIGINS-NEXT: store i32 [[TMP13]], i32* @__msan_retval_origin_tls, align 4 +; ORIGINS-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr [[P]], i32 1, <4 x i1> [[MASK]], <4 x double> [[V:%.*]]) +; ORIGINS-NEXT: store <4 x i64> [[_MSMASKEDLD]], ptr @__msan_retval_tls, align 8 +; ORIGINS-NEXT: store i32 [[TMP13]], ptr @__msan_retval_origin_tls, align 4 ; ORIGINS-NEXT: ret <4 x double> [[X]] ; entry: - %x = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %p, i32 1, <4 x i1> %mask, <4 x double> %v) + %x = call <4 x double> @llvm.masked.load.v4f64.p0(ptr %p, i32 1, <4 x i1> %mask, <4 x double> %v) ret <4 x double> %x } -define void @StoreNoSanitize(<4 x i64>* %p, <4 x i64> %v, <4 x i1> %mask) { +define void @StoreNoSanitize(ptr %p, <4 x i64> %v, <4 x i1> %mask) { ; CHECK-LABEL: @StoreNoSanitize( ; CHECK-NEXT: entry: ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint <4 x i64>* [[P:%.*]] to i64 +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080 -; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to <4 x i64>* -; CHECK-NEXT: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> zeroinitializer, <4 x i64>* [[TMP2]], i32 1, <4 x i1> [[MASK:%.*]]) -; CHECK-NEXT: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> [[V:%.*]], <4 x i64>* [[P]], i32 1, <4 x i1> [[MASK]]) +; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr +; CHECK-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr [[TMP2]], i32 1, <4 x i1> [[MASK:%.*]]) +; CHECK-NEXT: tail call void @llvm.masked.store.v4i64.p0(<4 x i64> [[V:%.*]], ptr [[P]], i32 1, <4 x i1> [[MASK]]) ; CHECK-NEXT: ret void ; ; ADDR-LABEL: @StoreNoSanitize( ; ADDR-NEXT: entry: ; ADDR-NEXT: call void @llvm.donothing() -; ADDR-NEXT: [[TMP0:%.*]] = ptrtoint <4 x i64>* [[P:%.*]] to i64 +; ADDR-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; ADDR-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080 -; ADDR-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to <4 x i64>* -; ADDR-NEXT: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> zeroinitializer, <4 x i64>* [[TMP2]], i32 1, <4 x i1> [[MASK:%.*]]) -; ADDR-NEXT: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> [[V:%.*]], <4 x i64>* [[P]], i32 1, <4 x i1> [[MASK]]) +; ADDR-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr +; ADDR-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr [[TMP2]], i32 1, <4 x i1> [[MASK:%.*]]) +; ADDR-NEXT: tail call void @llvm.masked.store.v4i64.p0(<4 x i64> [[V:%.*]], ptr [[P]], i32 1, <4 x i1> [[MASK]]) ; ADDR-NEXT: ret void ; ; ORIGINS-LABEL: @StoreNoSanitize( ; ORIGINS-NEXT: entry: ; ORIGINS-NEXT: call void @llvm.donothing() -; ORIGINS-NEXT: [[TMP0:%.*]] = ptrtoint <4 x i64>* [[P:%.*]] to i64 +; ORIGINS-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[P:%.*]] to i64 ; ORIGINS-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080 -; ORIGINS-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to <4 x i64>* +; ORIGINS-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr ; ORIGINS-NEXT: [[TMP3:%.*]] = add i64 [[TMP1]], 17592186044416 ; ORIGINS-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], -4 -; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32* -; ORIGINS-NEXT: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> zeroinitializer, <4 x i64>* [[TMP2]], i32 1, <4 x i1> [[MASK:%.*]]) -; ORIGINS-NEXT: store i32 0, i32* [[TMP5]], align 4 -; ORIGINS-NEXT: [[TMP6:%.*]] = getelementptr i32, i32* [[TMP5]], i32 1 -; ORIGINS-NEXT: store i32 0, i32* [[TMP6]], align 4 -; ORIGINS-NEXT: [[TMP7:%.*]] = getelementptr i32, i32* [[TMP5]], i32 2 -; ORIGINS-NEXT: store i32 0, i32* [[TMP7]], align 4 -; ORIGINS-NEXT: [[TMP8:%.*]] = getelementptr i32, i32* [[TMP5]], i32 3 -; ORIGINS-NEXT: store i32 0, i32* [[TMP8]], align 4 -; ORIGINS-NEXT: [[TMP9:%.*]] = getelementptr i32, i32* [[TMP5]], i32 4 -; ORIGINS-NEXT: store i32 0, i32* [[TMP9]], align 4 -; ORIGINS-NEXT: [[TMP10:%.*]] = getelementptr i32, i32* [[TMP5]], i32 5 -; ORIGINS-NEXT: store i32 0, i32* [[TMP10]], align 4 -; ORIGINS-NEXT: [[TMP11:%.*]] = getelementptr i32, i32* [[TMP5]], i32 6 -; ORIGINS-NEXT: store i32 0, i32* [[TMP11]], align 4 -; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, i32* [[TMP5]], i32 7 -; ORIGINS-NEXT: store i32 0, i32* [[TMP12]], align 4 -; ORIGINS-NEXT: tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> [[V:%.*]], <4 x i64>* [[P]], i32 1, <4 x i1> [[MASK]]) +; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr +; ORIGINS-NEXT: call void @llvm.masked.store.v4i64.p0(<4 x i64> zeroinitializer, ptr [[TMP2]], i32 1, <4 x i1> [[MASK:%.*]]) +; ORIGINS-NEXT: store i32 0, ptr [[TMP5]], align 4 +; ORIGINS-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP5]], i32 1 +; ORIGINS-NEXT: store i32 0, ptr [[TMP6]], align 4 +; ORIGINS-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP5]], i32 2 +; ORIGINS-NEXT: store i32 0, ptr [[TMP7]], align 4 +; ORIGINS-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP5]], i32 3 +; ORIGINS-NEXT: store i32 0, ptr [[TMP8]], align 4 +; ORIGINS-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP5]], i32 4 +; ORIGINS-NEXT: store i32 0, ptr [[TMP9]], align 4 +; ORIGINS-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[TMP5]], i32 5 +; ORIGINS-NEXT: store i32 0, ptr [[TMP10]], align 4 +; ORIGINS-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP5]], i32 6 +; ORIGINS-NEXT: store i32 0, ptr [[TMP11]], align 4 +; ORIGINS-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP5]], i32 7 +; ORIGINS-NEXT: store i32 0, ptr [[TMP12]], align 4 +; ORIGINS-NEXT: tail call void @llvm.masked.store.v4i64.p0(<4 x i64> [[V:%.*]], ptr [[P]], i32 1, <4 x i1> [[MASK]]) ; ORIGINS-NEXT: ret void ; entry: - tail call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %v, <4 x i64>* %p, i32 1, <4 x i1> %mask) + tail call void @llvm.masked.store.v4i64.p0(<4 x i64> %v, ptr %p, i32 1, <4 x i1> %mask) ret void } -define <4 x double> @LoadNoSanitize(<4 x double>* %p, <4 x double> %v, <4 x i1> %mask) { +define <4 x double> @LoadNoSanitize(ptr %p, <4 x double> %v, <4 x i1> %mask) { ; CHECK-LABEL: @LoadNoSanitize( ; CHECK-NEXT: entry: ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* [[P:%.*]], i32 1, <4 x i1> [[MASK:%.*]], <4 x double> [[V:%.*]]) -; CHECK-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; CHECK-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr [[P:%.*]], i32 1, <4 x i1> [[MASK:%.*]], <4 x double> [[V:%.*]]) +; CHECK-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x double> [[X]] ; ; ADDR-LABEL: @LoadNoSanitize( ; ADDR-NEXT: entry: ; ADDR-NEXT: call void @llvm.donothing() -; ADDR-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* [[P:%.*]], i32 1, <4 x i1> [[MASK:%.*]], <4 x double> [[V:%.*]]) -; ADDR-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 +; ADDR-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr [[P:%.*]], i32 1, <4 x i1> [[MASK:%.*]], <4 x double> [[V:%.*]]) +; ADDR-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; ADDR-NEXT: ret <4 x double> [[X]] ; ; ORIGINS-LABEL: @LoadNoSanitize( ; ORIGINS-NEXT: entry: ; ORIGINS-NEXT: call void @llvm.donothing() -; ORIGINS-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* [[P:%.*]], i32 1, <4 x i1> [[MASK:%.*]], <4 x double> [[V:%.*]]) -; ORIGINS-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8 -; ORIGINS-NEXT: store i32 0, i32* @__msan_retval_origin_tls, align 4 +; ORIGINS-NEXT: [[X:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0(ptr [[P:%.*]], i32 1, <4 x i1> [[MASK:%.*]], <4 x double> [[V:%.*]]) +; ORIGINS-NEXT: store <4 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 +; ORIGINS-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4 ; ORIGINS-NEXT: ret <4 x double> [[X]] ; entry: - %x = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* %p, i32 1, <4 x i1> %mask, <4 x double> %v) + %x = call <4 x double> @llvm.masked.load.v4f64.p0(ptr %p, i32 1, <4 x i1> %mask, <4 x double> %v) ret <4 x double> %x } ; FIXME: Provide real implementation. -define <16 x float> @Gather(<16 x float*> %ptrs, <16 x i1> %mask, <16 x float> %passthru) sanitize_memory { +define <16 x float> @Gather(<16 x ptr> %ptrs, <16 x i1> %mask, <16 x float> %passthru) sanitize_memory { ; CHECK-LABEL: @Gather( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 136) to <16 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 136) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint <16 x float*> [[PTRS:%.*]] to <16 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint <16 x ptr> [[PTRS:%.*]] to <16 x i64> ; CHECK-NEXT: [[TMP3:%.*]] = xor <16 x i64> [[TMP2]], -; CHECK-NEXT: [[TMP4:%.*]] = inttoptr <16 x i64> [[TMP3]] to <16 x i32*> -; CHECK-NEXT: [[_MSMASKEDGATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> [[TMP4]], i32 4, <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP1]]) -; CHECK-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> [[PTRS]], i32 4, <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) -; CHECK-NEXT: store <16 x i32> [[_MSMASKEDGATHER]], <16 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i32>*), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr <16 x i64> [[TMP3]] to <16 x ptr> +; CHECK-NEXT: [[_MSMASKEDGATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> [[TMP4]], i32 4, <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP1]]) +; CHECK-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> [[PTRS]], i32 4, <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) +; CHECK-NEXT: store <16 x i32> [[_MSMASKEDGATHER]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x float> [[RET]] ; ; ADDR-LABEL: @Gather( -; ADDR-NEXT: [[TMP1:%.*]] = load <16 x i1>, <16 x i1>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 128) to <16 x i1>*), align 8 -; ADDR-NEXT: [[TMP2:%.*]] = load <16 x i64>, <16 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i64>*), align 8 -; ADDR-NEXT: [[TMP3:%.*]] = load <16 x i32>, <16 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 136) to <16 x i32>*), align 8 +; ADDR-NEXT: [[TMP1:%.*]] = load <16 x i1>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 128) to ptr), align 8 +; ADDR-NEXT: [[TMP2:%.*]] = load <16 x i64>, ptr @__msan_param_tls, align 8 +; ADDR-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 136) to ptr), align 8 ; ADDR-NEXT: call void @llvm.donothing() ; ADDR-NEXT: [[_MSMASKEDPTRS:%.*]] = select <16 x i1> [[MASK:%.*]], <16 x i64> [[TMP2]], <16 x i64> zeroinitializer -; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint <16 x float*> [[PTRS:%.*]] to <16 x i64> +; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint <16 x ptr> [[PTRS:%.*]] to <16 x i64> ; ADDR-NEXT: [[TMP5:%.*]] = xor <16 x i64> [[TMP4]], -; ADDR-NEXT: [[TMP6:%.*]] = inttoptr <16 x i64> [[TMP5]] to <16 x i32*> -; ADDR-NEXT: [[_MSMASKEDGATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> [[TMP6]], i32 4, <16 x i1> [[MASK]], <16 x i32> [[TMP3]]) +; ADDR-NEXT: [[TMP6:%.*]] = inttoptr <16 x i64> [[TMP5]] to <16 x ptr> +; ADDR-NEXT: [[_MSMASKEDGATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> [[TMP6]], i32 4, <16 x i1> [[MASK]], <16 x i32> [[TMP3]]) ; ADDR-NEXT: [[TMP7:%.*]] = bitcast <16 x i1> [[TMP1]] to i16 ; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i16 [[TMP7]], 0 ; ADDR-NEXT: [[TMP8:%.*]] = bitcast <16 x i64> [[_MSMASKEDPTRS]] to i1024 @@ -265,76 +265,76 @@ ; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] ; ADDR-NEXT: unreachable ; ADDR: 10: -; ADDR-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> [[PTRS]], i32 4, <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) -; ADDR-NEXT: store <16 x i32> [[_MSMASKEDGATHER]], <16 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i32>*), align 8 +; ADDR-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> [[PTRS]], i32 4, <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) +; ADDR-NEXT: store <16 x i32> [[_MSMASKEDGATHER]], ptr @__msan_retval_tls, align 8 ; ADDR-NEXT: ret <16 x float> [[RET]] ; ; ORIGINS-LABEL: @Gather( -; ORIGINS-NEXT: [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 136) to <16 x i32>*), align 8 -; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 136) to i32*), align 4 +; ORIGINS-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 136) to ptr), align 8 +; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 136) to ptr), align 4 ; ORIGINS-NEXT: call void @llvm.donothing() -; ORIGINS-NEXT: [[TMP3:%.*]] = ptrtoint <16 x float*> [[PTRS:%.*]] to <16 x i64> +; ORIGINS-NEXT: [[TMP3:%.*]] = ptrtoint <16 x ptr> [[PTRS:%.*]] to <16 x i64> ; ORIGINS-NEXT: [[TMP4:%.*]] = xor <16 x i64> [[TMP3]], -; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr <16 x i64> [[TMP4]] to <16 x i32*> +; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr <16 x i64> [[TMP4]] to <16 x ptr> ; ORIGINS-NEXT: [[TMP6:%.*]] = add <16 x i64> [[TMP4]], -; ORIGINS-NEXT: [[TMP7:%.*]] = inttoptr <16 x i64> [[TMP6]] to <16 x i32*> -; ORIGINS-NEXT: [[_MSMASKEDGATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> [[TMP5]], i32 4, <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP1]]) -; ORIGINS-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> [[PTRS]], i32 4, <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) -; ORIGINS-NEXT: store <16 x i32> [[_MSMASKEDGATHER]], <16 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i32>*), align 8 -; ORIGINS-NEXT: store i32 0, i32* @__msan_retval_origin_tls, align 4 +; ORIGINS-NEXT: [[TMP7:%.*]] = inttoptr <16 x i64> [[TMP6]] to <16 x ptr> +; ORIGINS-NEXT: [[_MSMASKEDGATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0(<16 x ptr> [[TMP5]], i32 4, <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP1]]) +; ORIGINS-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> [[PTRS]], i32 4, <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) +; ORIGINS-NEXT: store <16 x i32> [[_MSMASKEDGATHER]], ptr @__msan_retval_tls, align 8 +; ORIGINS-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4 ; ORIGINS-NEXT: ret <16 x float> [[RET]] ; - %ret = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x float*> %ptrs, i32 4, <16 x i1> %mask, <16 x float> %passthru) + %ret = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %ptrs, i32 4, <16 x i1> %mask, <16 x float> %passthru) ret <16 x float> %ret } -define <16 x float> @GatherNoSanitize(<16 x float*> %ptrs, <16 x i1> %mask, <16 x float> %passthru) { +define <16 x float> @GatherNoSanitize(<16 x ptr> %ptrs, <16 x i1> %mask, <16 x float> %passthru) { ; CHECK-LABEL: @GatherNoSanitize( ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> [[PTRS:%.*]], i32 4, <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]]) -; CHECK-NEXT: store <16 x i32> zeroinitializer, <16 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i32>*), align 8 +; CHECK-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> [[PTRS:%.*]], i32 4, <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]]) +; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x float> [[RET]] ; ; ADDR-LABEL: @GatherNoSanitize( ; ADDR-NEXT: call void @llvm.donothing() ; ADDR-NEXT: [[_MSMASKEDPTRS:%.*]] = select <16 x i1> [[MASK:%.*]], <16 x i64> zeroinitializer, <16 x i64> zeroinitializer -; ADDR-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> [[PTRS:%.*]], i32 4, <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) -; ADDR-NEXT: store <16 x i32> zeroinitializer, <16 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i32>*), align 8 +; ADDR-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> [[PTRS:%.*]], i32 4, <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) +; ADDR-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; ADDR-NEXT: ret <16 x float> [[RET]] ; ; ORIGINS-LABEL: @GatherNoSanitize( ; ORIGINS-NEXT: call void @llvm.donothing() -; ORIGINS-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> [[PTRS:%.*]], i32 4, <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]]) -; ORIGINS-NEXT: store <16 x i32> zeroinitializer, <16 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i32>*), align 8 -; ORIGINS-NEXT: store i32 0, i32* @__msan_retval_origin_tls, align 4 +; ORIGINS-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> [[PTRS:%.*]], i32 4, <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]]) +; ORIGINS-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 +; ORIGINS-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4 ; ORIGINS-NEXT: ret <16 x float> [[RET]] ; - %ret = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x float*> %ptrs, i32 4, <16 x i1> %mask, <16 x float> %passthru) + %ret = call <16 x float> @llvm.masked.gather.v16f32.v16p0(<16 x ptr> %ptrs, i32 4, <16 x i1> %mask, <16 x float> %passthru) ret <16 x float> %ret } ; FIXME: Provide real implementation. -define void @Scatter(<8 x i32> %value, <8 x i32*> %ptrs, <8 x i1> %mask) sanitize_memory { +define void @Scatter(<8 x i32> %value, <8 x ptr> %ptrs, <8 x i1> %mask) sanitize_memory { ; CHECK-LABEL: @Scatter( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint <8 x i32*> [[PTRS:%.*]] to <8 x i64> +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint <8 x ptr> [[PTRS:%.*]] to <8 x i64> ; CHECK-NEXT: [[TMP3:%.*]] = xor <8 x i64> [[TMP2]], -; CHECK-NEXT: [[TMP4:%.*]] = inttoptr <8 x i64> [[TMP3]] to <8 x i32*> -; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> [[TMP1]], <8 x i32*> [[TMP4]], i32 8, <8 x i1> [[MASK:%.*]]) -; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> [[VALUE:%.*]], <8 x i32*> [[PTRS]], i32 8, <8 x i1> [[MASK]]) +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr <8 x i64> [[TMP3]] to <8 x ptr> +; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[TMP1]], <8 x ptr> [[TMP4]], i32 8, <8 x i1> [[MASK:%.*]]) +; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[VALUE:%.*]], <8 x ptr> [[PTRS]], i32 8, <8 x i1> [[MASK]]) ; CHECK-NEXT: ret void ; ; ADDR-LABEL: @Scatter( -; ADDR-NEXT: [[TMP1:%.*]] = load <8 x i1>, <8 x i1>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 96) to <8 x i1>*), align 8 -; ADDR-NEXT: [[TMP2:%.*]] = load <8 x i64>, <8 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i64>*), align 8 -; ADDR-NEXT: [[TMP3:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 +; ADDR-NEXT: [[TMP1:%.*]] = load <8 x i1>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 96) to ptr), align 8 +; ADDR-NEXT: [[TMP2:%.*]] = load <8 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 +; ADDR-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 ; ADDR-NEXT: call void @llvm.donothing() ; ADDR-NEXT: [[_MSMASKEDPTRS:%.*]] = select <8 x i1> [[MASK:%.*]], <8 x i64> [[TMP2]], <8 x i64> zeroinitializer -; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint <8 x i32*> [[PTRS:%.*]] to <8 x i64> +; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint <8 x ptr> [[PTRS:%.*]] to <8 x i64> ; ADDR-NEXT: [[TMP5:%.*]] = xor <8 x i64> [[TMP4]], -; ADDR-NEXT: [[TMP6:%.*]] = inttoptr <8 x i64> [[TMP5]] to <8 x i32*> -; ADDR-NEXT: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> [[TMP3]], <8 x i32*> [[TMP6]], i32 8, <8 x i1> [[MASK]]) +; ADDR-NEXT: [[TMP6:%.*]] = inttoptr <8 x i64> [[TMP5]] to <8 x ptr> +; ADDR-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[TMP3]], <8 x ptr> [[TMP6]], i32 8, <8 x i1> [[MASK]]) ; ADDR-NEXT: [[TMP7:%.*]] = bitcast <8 x i1> [[TMP1]] to i8 ; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i8 [[TMP7]], 0 ; ADDR-NEXT: [[TMP8:%.*]] = bitcast <8 x i64> [[_MSMASKEDPTRS]] to i512 @@ -345,83 +345,83 @@ ; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] ; ADDR-NEXT: unreachable ; ADDR: 10: -; ADDR-NEXT: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> [[VALUE:%.*]], <8 x i32*> [[PTRS]], i32 8, <8 x i1> [[MASK]]) +; ADDR-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[VALUE:%.*]], <8 x ptr> [[PTRS]], i32 8, <8 x i1> [[MASK]]) ; ADDR-NEXT: ret void ; ; ORIGINS-LABEL: @Scatter( -; ORIGINS-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i32>*), align 8 -; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4 +; ORIGINS-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8 +; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGINS-NEXT: call void @llvm.donothing() -; ORIGINS-NEXT: [[TMP3:%.*]] = ptrtoint <8 x i32*> [[PTRS:%.*]] to <8 x i64> +; ORIGINS-NEXT: [[TMP3:%.*]] = ptrtoint <8 x ptr> [[PTRS:%.*]] to <8 x i64> ; ORIGINS-NEXT: [[TMP4:%.*]] = xor <8 x i64> [[TMP3]], -; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr <8 x i64> [[TMP4]] to <8 x i32*> +; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr <8 x i64> [[TMP4]] to <8 x ptr> ; ORIGINS-NEXT: [[TMP6:%.*]] = add <8 x i64> [[TMP4]], -; ORIGINS-NEXT: [[TMP7:%.*]] = inttoptr <8 x i64> [[TMP6]] to <8 x i32*> -; ORIGINS-NEXT: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> [[TMP1]], <8 x i32*> [[TMP5]], i32 8, <8 x i1> [[MASK:%.*]]) -; ORIGINS-NEXT: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> [[VALUE:%.*]], <8 x i32*> [[PTRS]], i32 8, <8 x i1> [[MASK]]) +; ORIGINS-NEXT: [[TMP7:%.*]] = inttoptr <8 x i64> [[TMP6]] to <8 x ptr> +; ORIGINS-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[TMP1]], <8 x ptr> [[TMP5]], i32 8, <8 x i1> [[MASK:%.*]]) +; ORIGINS-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[VALUE:%.*]], <8 x ptr> [[PTRS]], i32 8, <8 x i1> [[MASK]]) ; ORIGINS-NEXT: ret void ; - call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %value, <8 x i32*> %ptrs, i32 8, <8 x i1> %mask) + call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %value, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask) ret void } -define void @ScatterNoSanitize(<8 x i32> %value, <8 x i32*> %ptrs, <8 x i1> %mask) { +define void @ScatterNoSanitize(<8 x i32> %value, <8 x ptr> %ptrs, <8 x i1> %mask) { ; CHECK-LABEL: @ScatterNoSanitize( ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint <8 x i32*> [[PTRS:%.*]] to <8 x i64> +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint <8 x ptr> [[PTRS:%.*]] to <8 x i64> ; CHECK-NEXT: [[TMP2:%.*]] = xor <8 x i64> [[TMP1]], -; CHECK-NEXT: [[TMP3:%.*]] = inttoptr <8 x i64> [[TMP2]] to <8 x i32*> -; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> zeroinitializer, <8 x i32*> [[TMP3]], i32 8, <8 x i1> [[MASK:%.*]]) -; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> [[VALUE:%.*]], <8 x i32*> [[PTRS]], i32 8, <8 x i1> [[MASK]]) +; CHECK-NEXT: [[TMP3:%.*]] = inttoptr <8 x i64> [[TMP2]] to <8 x ptr> +; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> zeroinitializer, <8 x ptr> [[TMP3]], i32 8, <8 x i1> [[MASK:%.*]]) +; CHECK-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[VALUE:%.*]], <8 x ptr> [[PTRS]], i32 8, <8 x i1> [[MASK]]) ; CHECK-NEXT: ret void ; ; ADDR-LABEL: @ScatterNoSanitize( ; ADDR-NEXT: call void @llvm.donothing() ; ADDR-NEXT: [[_MSMASKEDPTRS:%.*]] = select <8 x i1> [[MASK:%.*]], <8 x i64> zeroinitializer, <8 x i64> zeroinitializer -; ADDR-NEXT: [[TMP1:%.*]] = ptrtoint <8 x i32*> [[PTRS:%.*]] to <8 x i64> +; ADDR-NEXT: [[TMP1:%.*]] = ptrtoint <8 x ptr> [[PTRS:%.*]] to <8 x i64> ; ADDR-NEXT: [[TMP2:%.*]] = xor <8 x i64> [[TMP1]], -; ADDR-NEXT: [[TMP3:%.*]] = inttoptr <8 x i64> [[TMP2]] to <8 x i32*> -; ADDR-NEXT: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> zeroinitializer, <8 x i32*> [[TMP3]], i32 8, <8 x i1> [[MASK]]) -; ADDR-NEXT: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> [[VALUE:%.*]], <8 x i32*> [[PTRS]], i32 8, <8 x i1> [[MASK]]) +; ADDR-NEXT: [[TMP3:%.*]] = inttoptr <8 x i64> [[TMP2]] to <8 x ptr> +; ADDR-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> zeroinitializer, <8 x ptr> [[TMP3]], i32 8, <8 x i1> [[MASK]]) +; ADDR-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[VALUE:%.*]], <8 x ptr> [[PTRS]], i32 8, <8 x i1> [[MASK]]) ; ADDR-NEXT: ret void ; ; ORIGINS-LABEL: @ScatterNoSanitize( ; ORIGINS-NEXT: call void @llvm.donothing() -; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint <8 x i32*> [[PTRS:%.*]] to <8 x i64> +; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint <8 x ptr> [[PTRS:%.*]] to <8 x i64> ; ORIGINS-NEXT: [[TMP2:%.*]] = xor <8 x i64> [[TMP1]], -; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr <8 x i64> [[TMP2]] to <8 x i32*> +; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr <8 x i64> [[TMP2]] to <8 x ptr> ; ORIGINS-NEXT: [[TMP4:%.*]] = add <8 x i64> [[TMP2]], -; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr <8 x i64> [[TMP4]] to <8 x i32*> -; ORIGINS-NEXT: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> zeroinitializer, <8 x i32*> [[TMP3]], i32 8, <8 x i1> [[MASK:%.*]]) -; ORIGINS-NEXT: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> [[VALUE:%.*]], <8 x i32*> [[PTRS]], i32 8, <8 x i1> [[MASK]]) +; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr <8 x i64> [[TMP4]] to <8 x ptr> +; ORIGINS-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> zeroinitializer, <8 x ptr> [[TMP3]], i32 8, <8 x i1> [[MASK:%.*]]) +; ORIGINS-NEXT: call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> [[VALUE:%.*]], <8 x ptr> [[PTRS]], i32 8, <8 x i1> [[MASK]]) ; ORIGINS-NEXT: ret void ; - call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %value, <8 x i32*> %ptrs, i32 8, <8 x i1> %mask) + call void @llvm.masked.scatter.v8i32.v8p0(<8 x i32> %value, <8 x ptr> %ptrs, i32 8, <8 x i1> %mask) ret void } ; FIXME: Provide real implementation. -define <16 x float> @ExpandLoad(float* %ptr, <16 x i1> %mask, <16 x float> %passthru) sanitize_memory { +define <16 x float> @ExpandLoad(ptr %ptr, <16 x i1> %mask, <16 x float> %passthru) sanitize_memory { ; CHECK-LABEL: @ExpandLoad( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <16 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint float* [[PTR:%.*]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 -; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to i32* -; CHECK-NEXT: [[_MSMASKEDEXPLOAD:%.*]] = call <16 x i32> @llvm.masked.expandload.v16i32(i32* [[TMP4]], <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP1]]) -; CHECK-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(float* [[PTR]], <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) -; CHECK-NEXT: store <16 x i32> [[_MSMASKEDEXPLOAD]], <16 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i32>*), align 8 +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; CHECK-NEXT: [[_MSMASKEDEXPLOAD:%.*]] = call <16 x i32> @llvm.masked.expandload.v16i32(ptr [[TMP4]], <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP1]]) +; CHECK-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(ptr [[PTR]], <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) +; CHECK-NEXT: store <16 x i32> [[_MSMASKEDEXPLOAD]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x float> [[RET]] ; ; ADDR-LABEL: @ExpandLoad( -; ADDR-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; ADDR-NEXT: [[TMP2:%.*]] = load <16 x i1>, <16 x i1>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <16 x i1>*), align 8 -; ADDR-NEXT: [[TMP3:%.*]] = load <16 x i32>, <16 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <16 x i32>*), align 8 +; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; ADDR-NEXT: [[TMP2:%.*]] = load <16 x i1>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; ADDR-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; ADDR-NEXT: call void @llvm.donothing() -; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint float* [[PTR:%.*]] to i64 +; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64 ; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080 -; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to i32* -; ADDR-NEXT: [[_MSMASKEDEXPLOAD:%.*]] = call <16 x i32> @llvm.masked.expandload.v16i32(i32* [[TMP6]], <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP3]]) +; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr +; ADDR-NEXT: [[_MSMASKEDEXPLOAD:%.*]] = call <16 x i32> @llvm.masked.expandload.v16i32(ptr [[TMP6]], <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP3]]) ; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; ADDR-NEXT: [[TMP7:%.*]] = bitcast <16 x i1> [[TMP2]] to i16 ; ADDR-NEXT: [[_MSCMP1:%.*]] = icmp ne i16 [[TMP7]], 0 @@ -431,75 +431,75 @@ ; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] ; ADDR-NEXT: unreachable ; ADDR: 9: -; ADDR-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(float* [[PTR]], <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) -; ADDR-NEXT: store <16 x i32> [[_MSMASKEDEXPLOAD]], <16 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i32>*), align 8 +; ADDR-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(ptr [[PTR]], <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) +; ADDR-NEXT: store <16 x i32> [[_MSMASKEDEXPLOAD]], ptr @__msan_retval_tls, align 8 ; ADDR-NEXT: ret <16 x float> [[RET]] ; ; ORIGINS-LABEL: @ExpandLoad( -; ORIGINS-NEXT: [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <16 x i32>*), align 8 -; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 16) to i32*), align 4 +; ORIGINS-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 16) to ptr), align 4 ; ORIGINS-NEXT: call void @llvm.donothing() -; ORIGINS-NEXT: [[TMP3:%.*]] = ptrtoint float* [[PTR:%.*]] to i64 +; ORIGINS-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64 ; ORIGINS-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080 -; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32* +; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr ; ORIGINS-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416 ; ORIGINS-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], -4 -; ORIGINS-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to i32* -; ORIGINS-NEXT: [[_MSMASKEDEXPLOAD:%.*]] = call <16 x i32> @llvm.masked.expandload.v16i32(i32* [[TMP5]], <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP1]]) -; ORIGINS-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(float* [[PTR]], <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) -; ORIGINS-NEXT: store <16 x i32> [[_MSMASKEDEXPLOAD]], <16 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i32>*), align 8 -; ORIGINS-NEXT: store i32 0, i32* @__msan_retval_origin_tls, align 4 +; ORIGINS-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr +; ORIGINS-NEXT: [[_MSMASKEDEXPLOAD:%.*]] = call <16 x i32> @llvm.masked.expandload.v16i32(ptr [[TMP5]], <16 x i1> [[MASK:%.*]], <16 x i32> [[TMP1]]) +; ORIGINS-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(ptr [[PTR]], <16 x i1> [[MASK]], <16 x float> [[PASSTHRU:%.*]]) +; ORIGINS-NEXT: store <16 x i32> [[_MSMASKEDEXPLOAD]], ptr @__msan_retval_tls, align 8 +; ORIGINS-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4 ; ORIGINS-NEXT: ret <16 x float> [[RET]] ; - %ret = call <16 x float> @llvm.masked.expandload.v16f32(float* %ptr, <16 x i1> %mask, <16 x float> %passthru) + %ret = call <16 x float> @llvm.masked.expandload.v16f32(ptr %ptr, <16 x i1> %mask, <16 x float> %passthru) ret <16 x float> %ret } -define <16 x float> @ExpandLoadNoSanitize(float* %ptr, <16 x i1> %mask, <16 x float> %passthru) { +define <16 x float> @ExpandLoadNoSanitize(ptr %ptr, <16 x i1> %mask, <16 x float> %passthru) { ; CHECK-LABEL: @ExpandLoadNoSanitize( ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(float* [[PTR:%.*]], <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]]) -; CHECK-NEXT: store <16 x i32> zeroinitializer, <16 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i32>*), align 8 +; CHECK-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(ptr [[PTR:%.*]], <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]]) +; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x float> [[RET]] ; ; ADDR-LABEL: @ExpandLoadNoSanitize( ; ADDR-NEXT: call void @llvm.donothing() -; ADDR-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(float* [[PTR:%.*]], <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]]) -; ADDR-NEXT: store <16 x i32> zeroinitializer, <16 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i32>*), align 8 +; ADDR-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(ptr [[PTR:%.*]], <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]]) +; ADDR-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; ADDR-NEXT: ret <16 x float> [[RET]] ; ; ORIGINS-LABEL: @ExpandLoadNoSanitize( ; ORIGINS-NEXT: call void @llvm.donothing() -; ORIGINS-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(float* [[PTR:%.*]], <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]]) -; ORIGINS-NEXT: store <16 x i32> zeroinitializer, <16 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i32>*), align 8 -; ORIGINS-NEXT: store i32 0, i32* @__msan_retval_origin_tls, align 4 +; ORIGINS-NEXT: [[RET:%.*]] = call <16 x float> @llvm.masked.expandload.v16f32(ptr [[PTR:%.*]], <16 x i1> [[MASK:%.*]], <16 x float> [[PASSTHRU:%.*]]) +; ORIGINS-NEXT: store <16 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 +; ORIGINS-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4 ; ORIGINS-NEXT: ret <16 x float> [[RET]] ; - %ret = call <16 x float> @llvm.masked.expandload.v16f32(float* %ptr, <16 x i1> %mask, <16 x float> %passthru) + %ret = call <16 x float> @llvm.masked.expandload.v16f32(ptr %ptr, <16 x i1> %mask, <16 x float> %passthru) ret <16 x float> %ret } ; FIXME: Provide real implementation. -define void @CompressStore(<16 x float> %value, float* %ptr, <16 x i1> %mask) sanitize_memory { +define void @CompressStore(<16 x float> %value, ptr %ptr, <16 x i1> %mask) sanitize_memory { ; CHECK-LABEL: @CompressStore( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint float* [[PTR:%.*]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 -; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to i32* -; CHECK-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> [[TMP1]], i32* [[TMP4]], <16 x i1> [[MASK:%.*]]) -; CHECK-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], float* [[PTR]], <16 x i1> [[MASK]]) +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; CHECK-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> [[TMP1]], ptr [[TMP4]], <16 x i1> [[MASK:%.*]]) +; CHECK-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], ptr [[PTR]], <16 x i1> [[MASK]]) ; CHECK-NEXT: ret void ; ; ADDR-LABEL: @CompressStore( -; ADDR-NEXT: [[TMP1:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 64) to i64*), align 8 -; ADDR-NEXT: [[TMP2:%.*]] = load <16 x i1>, <16 x i1>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 72) to <16 x i1>*), align 8 -; ADDR-NEXT: [[TMP3:%.*]] = load <16 x i32>, <16 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i32>*), align 8 +; ADDR-NEXT: [[TMP1:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 64) to ptr), align 8 +; ADDR-NEXT: [[TMP2:%.*]] = load <16 x i1>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 72) to ptr), align 8 +; ADDR-NEXT: [[TMP3:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8 ; ADDR-NEXT: call void @llvm.donothing() -; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint float* [[PTR:%.*]] to i64 +; ADDR-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64 ; ADDR-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080 -; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to i32* -; ADDR-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> [[TMP3]], i32* [[TMP6]], <16 x i1> [[MASK:%.*]]) +; ADDR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr +; ADDR-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> [[TMP3]], ptr [[TMP6]], <16 x i1> [[MASK:%.*]]) ; ADDR-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; ADDR-NEXT: [[TMP7:%.*]] = bitcast <16 x i1> [[TMP2]] to i16 ; ADDR-NEXT: [[_MSCMP1:%.*]] = icmp ne i16 [[TMP7]], 0 @@ -509,58 +509,58 @@ ; ADDR-NEXT: call void @__msan_warning_noreturn() #[[ATTR7]] ; ADDR-NEXT: unreachable ; ADDR: 9: -; ADDR-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], float* [[PTR]], <16 x i1> [[MASK]]) +; ADDR-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], ptr [[PTR]], <16 x i1> [[MASK]]) ; ADDR-NEXT: ret void ; ; ORIGINS-LABEL: @CompressStore( -; ORIGINS-NEXT: [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i32>*), align 8 -; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4 +; ORIGINS-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @__msan_param_tls, align 8 +; ORIGINS-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; ORIGINS-NEXT: call void @llvm.donothing() -; ORIGINS-NEXT: [[TMP3:%.*]] = ptrtoint float* [[PTR:%.*]] to i64 +; ORIGINS-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64 ; ORIGINS-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080 -; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32* +; ORIGINS-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr ; ORIGINS-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416 ; ORIGINS-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], -4 -; ORIGINS-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to i32* -; ORIGINS-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> [[TMP1]], i32* [[TMP5]], <16 x i1> [[MASK:%.*]]) -; ORIGINS-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], float* [[PTR]], <16 x i1> [[MASK]]) +; ORIGINS-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr +; ORIGINS-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> [[TMP1]], ptr [[TMP5]], <16 x i1> [[MASK:%.*]]) +; ORIGINS-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], ptr [[PTR]], <16 x i1> [[MASK]]) ; ORIGINS-NEXT: ret void ; - call void @llvm.masked.compressstore.v16f32(<16 x float> %value, float* %ptr, <16 x i1> %mask) + call void @llvm.masked.compressstore.v16f32(<16 x float> %value, ptr %ptr, <16 x i1> %mask) ret void } -define void @CompressStoreNoSanitize(<16 x float> %value, float* %ptr, <16 x i1> %mask) { +define void @CompressStoreNoSanitize(<16 x float> %value, ptr %ptr, <16 x i1> %mask) { ; CHECK-LABEL: @CompressStoreNoSanitize( ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint float* [[PTR:%.*]] to i64 +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080 -; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to i32* -; CHECK-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> zeroinitializer, i32* [[TMP3]], <16 x i1> [[MASK:%.*]]) -; CHECK-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], float* [[PTR]], <16 x i1> [[MASK]]) +; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; CHECK-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> zeroinitializer, ptr [[TMP3]], <16 x i1> [[MASK:%.*]]) +; CHECK-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], ptr [[PTR]], <16 x i1> [[MASK]]) ; CHECK-NEXT: ret void ; ; ADDR-LABEL: @CompressStoreNoSanitize( ; ADDR-NEXT: call void @llvm.donothing() -; ADDR-NEXT: [[TMP1:%.*]] = ptrtoint float* [[PTR:%.*]] to i64 +; ADDR-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64 ; ADDR-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080 -; ADDR-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to i32* -; ADDR-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> zeroinitializer, i32* [[TMP3]], <16 x i1> [[MASK:%.*]]) -; ADDR-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], float* [[PTR]], <16 x i1> [[MASK]]) +; ADDR-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; ADDR-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> zeroinitializer, ptr [[TMP3]], <16 x i1> [[MASK:%.*]]) +; ADDR-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], ptr [[PTR]], <16 x i1> [[MASK]]) ; ADDR-NEXT: ret void ; ; ORIGINS-LABEL: @CompressStoreNoSanitize( ; ORIGINS-NEXT: call void @llvm.donothing() -; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint float* [[PTR:%.*]] to i64 +; ORIGINS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64 ; ORIGINS-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080 -; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to i32* +; ORIGINS-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr ; ORIGINS-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416 ; ORIGINS-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -4 -; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to i32* -; ORIGINS-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> zeroinitializer, i32* [[TMP3]], <16 x i1> [[MASK:%.*]]) -; ORIGINS-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], float* [[PTR]], <16 x i1> [[MASK]]) +; ORIGINS-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr +; ORIGINS-NEXT: call void @llvm.masked.compressstore.v16i32(<16 x i32> zeroinitializer, ptr [[TMP3]], <16 x i1> [[MASK:%.*]]) +; ORIGINS-NEXT: call void @llvm.masked.compressstore.v16f32(<16 x float> [[VALUE:%.*]], ptr [[PTR]], <16 x i1> [[MASK]]) ; ORIGINS-NEXT: ret void ; - call void @llvm.masked.compressstore.v16f32(<16 x float> %value, float* %ptr, <16 x i1> %mask) + call void @llvm.masked.compressstore.v16f32(<16 x float> %value, ptr %ptr, <16 x i1> %mask) ret void } diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll --- a/llvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_asm_conservative.ll @@ -20,10 +20,10 @@ @pair1 = common dso_local global %struct.pair zeroinitializer, align 4 @c2 = common dso_local global i8 0, align 1 @c1 = common dso_local global i8 0, align 1 -@memcpy_d1 = common dso_local global i8* (i8*, i8*, i32)* null, align 8 -@memcpy_d2 = common dso_local global i8* (i8*, i8*, i32)* null, align 8 -@memcpy_s1 = common dso_local global i8* (i8*, i8*, i32)* null, align 8 -@memcpy_s2 = common dso_local global i8* (i8*, i8*, i32)* null, align 8 +@memcpy_d1 = common dso_local global ptr null, align 8 +@memcpy_d2 = common dso_local global ptr null, align 8 +@memcpy_s1 = common dso_local global ptr null, align 8 +@memcpy_s2 = common dso_local global ptr null, align 8 ; The functions below were generated from a C source that contains declarations like follows: ; void f1() { @@ -36,190 +36,180 @@ ; asm("" : "=r" (id1) : "r" (is1)); define dso_local void @f_1i_1o_reg() sanitize_memory { entry: - %0 = load i32, i32* @is1, align 4 + %0 = load i32, ptr @is1, align 4 %1 = call i32 asm "", "=r,r,~{dirflag},~{fpsr},~{flags}"(i32 %0) - store i32 %1, i32* @id1, align 4 + store i32 %1, ptr @id1, align 4 ret void } ; CHECK-LABEL: @f_1i_1o_reg -; CHECK: [[IS1_F1:%.*]] = load i32, i32* @is1, align 4 +; CHECK: [[IS1_F1:%.*]] = load i32, ptr @is1, align 4 ; CHECK: call void @__msan_warning ; CHECK: call i32 asm "",{{.*}}(i32 [[IS1_F1]]) ; CHECK: [[PACK1_F1:%.*]] = call {{.*}} @__msan_metadata_ptr_for_store_4({{.*}}@id1{{.*}}) -; CHECK: [[EXT1_F1:%.*]] = extractvalue { i8*, i32* } [[PACK1_F1]], 0 -; CHECK: [[CAST1_F1:%.*]] = bitcast i8* [[EXT1_F1]] to i32* -; CHECK: store i32 0, i32* [[CAST1_F1]] +; CHECK: [[EXT1_F1:%.*]] = extractvalue { ptr, ptr } [[PACK1_F1]], 0 +; CHECK: store i32 0, ptr [[EXT1_F1]] ; Two input registers, two output registers: ; asm("" : "=r" (id1), "=r" (id2) : "r" (is1), "r"(is2)); define dso_local void @f_2i_2o_reg() sanitize_memory { entry: - %0 = load i32, i32* @is1, align 4 - %1 = load i32, i32* @is2, align 4 + %0 = load i32, ptr @is1, align 4 + %1 = load i32, ptr @is2, align 4 %2 = call { i32, i32 } asm "", "=r,=r,r,r,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1) %asmresult = extractvalue { i32, i32 } %2, 0 %asmresult1 = extractvalue { i32, i32 } %2, 1 - store i32 %asmresult, i32* @id1, align 4 - store i32 %asmresult1, i32* @id2, align 4 + store i32 %asmresult, ptr @id1, align 4 + store i32 %asmresult1, ptr @id2, align 4 ret void } ; CHECK-LABEL: @f_2i_2o_reg -; CHECK: [[IS1_F2:%.*]] = load i32, i32* @is1, align 4 -; CHECK: [[IS2_F2:%.*]] = load i32, i32* @is2, align 4 +; CHECK: [[IS1_F2:%.*]] = load i32, ptr @is1, align 4 +; CHECK: [[IS2_F2:%.*]] = load i32, ptr @is2, align 4 ; CHECK: call void @__msan_warning ; CHECK: call void @__msan_warning ; CHECK: call { i32, i32 } asm "",{{.*}}(i32 [[IS1_F2]], i32 [[IS2_F2]]) ; CHECK: [[PACK1_F2:%.*]] = call {{.*}} @__msan_metadata_ptr_for_store_4({{.*}}@id1{{.*}}) -; CHECK: [[EXT1_F2:%.*]] = extractvalue { i8*, i32* } [[PACK1_F2]], 0 -; CHECK: [[CAST1_F2:%.*]] = bitcast i8* [[EXT1_F2]] to i32* -; CHECK: store i32 0, i32* [[CAST1_F2]] +; CHECK: [[EXT1_F2:%.*]] = extractvalue { ptr, ptr } [[PACK1_F2]], 0 +; CHECK: store i32 0, ptr [[EXT1_F2]] ; CHECK: [[PACK2_F2:%.*]] = call {{.*}} @__msan_metadata_ptr_for_store_4({{.*}}@id2{{.*}}) -; CHECK: [[EXT2_F2:%.*]] = extractvalue { i8*, i32* } [[PACK2_F2]], 0 -; CHECK: [[CAST2_F2:%.*]] = bitcast i8* [[EXT2_F2]] to i32* -; CHECK: store i32 0, i32* [[CAST2_F2]] +; CHECK: [[EXT2_F2:%.*]] = extractvalue { ptr, ptr } [[PACK2_F2]], 0 +; CHECK: store i32 0, ptr [[EXT2_F2]] ; Input same as output, used twice: ; asm("" : "=r" (id1), "=r" (id2) : "r" (id1), "r" (id2)); define dso_local void @f_2i_2o_reuse2_reg() sanitize_memory { entry: - %0 = load i32, i32* @id1, align 4 - %1 = load i32, i32* @id2, align 4 + %0 = load i32, ptr @id1, align 4 + %1 = load i32, ptr @id2, align 4 %2 = call { i32, i32 } asm "", "=r,=r,r,r,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1) %asmresult = extractvalue { i32, i32 } %2, 0 %asmresult1 = extractvalue { i32, i32 } %2, 1 - store i32 %asmresult, i32* @id1, align 4 - store i32 %asmresult1, i32* @id2, align 4 + store i32 %asmresult, ptr @id1, align 4 + store i32 %asmresult1, ptr @id2, align 4 ret void } ; CHECK-LABEL: @f_2i_2o_reuse2_reg -; CHECK: [[ID1_F3:%.*]] = load i32, i32* @id1, align 4 -; CHECK: [[ID2_F3:%.*]] = load i32, i32* @id2, align 4 +; CHECK: [[ID1_F3:%.*]] = load i32, ptr @id1, align 4 +; CHECK: [[ID2_F3:%.*]] = load i32, ptr @id2, align 4 ; CHECK: call void @__msan_warning ; CHECK: call void @__msan_warning ; CHECK: call { i32, i32 } asm "",{{.*}}(i32 [[ID1_F3]], i32 [[ID2_F3]]) ; CHECK: [[PACK1_F3:%.*]] = call {{.*}} @__msan_metadata_ptr_for_store_4({{.*}}@id1{{.*}}) -; CHECK: [[EXT1_F3:%.*]] = extractvalue { i8*, i32* } [[PACK1_F3]], 0 -; CHECK: [[CAST1_F3:%.*]] = bitcast i8* [[EXT1_F3]] to i32* -; CHECK: store i32 0, i32* [[CAST1_F3]] +; CHECK: [[EXT1_F3:%.*]] = extractvalue { ptr, ptr } [[PACK1_F3]], 0 +; CHECK: store i32 0, ptr [[EXT1_F3]] ; CHECK: [[PACK2_F3:%.*]] = call {{.*}} @__msan_metadata_ptr_for_store_4({{.*}}@id2{{.*}}) -; CHECK: [[EXT2_F3:%.*]] = extractvalue { i8*, i32* } [[PACK2_F3]], 0 -; CHECK: [[CAST2_F3:%.*]] = bitcast i8* [[EXT2_F3]] to i32* -; CHECK: store i32 0, i32* [[CAST2_F3]] +; CHECK: [[EXT2_F3:%.*]] = extractvalue { ptr, ptr } [[PACK2_F3]], 0 +; CHECK: store i32 0, ptr [[EXT2_F3]] ; One of the input registers is also an output: ; asm("" : "=r" (id1), "=r" (id2) : "r" (id1), "r"(is1)); define dso_local void @f_2i_2o_reuse1_reg() sanitize_memory { entry: - %0 = load i32, i32* @id1, align 4 - %1 = load i32, i32* @is1, align 4 + %0 = load i32, ptr @id1, align 4 + %1 = load i32, ptr @is1, align 4 %2 = call { i32, i32 } asm "", "=r,=r,r,r,~{dirflag},~{fpsr},~{flags}"(i32 %0, i32 %1) %asmresult = extractvalue { i32, i32 } %2, 0 %asmresult1 = extractvalue { i32, i32 } %2, 1 - store i32 %asmresult, i32* @id1, align 4 - store i32 %asmresult1, i32* @id2, align 4 + store i32 %asmresult, ptr @id1, align 4 + store i32 %asmresult1, ptr @id2, align 4 ret void } ; CHECK-LABEL: @f_2i_2o_reuse1_reg -; CHECK: [[ID1_F4:%.*]] = load i32, i32* @id1, align 4 -; CHECK: [[IS1_F4:%.*]] = load i32, i32* @is1, align 4 +; CHECK: [[ID1_F4:%.*]] = load i32, ptr @id1, align 4 +; CHECK: [[IS1_F4:%.*]] = load i32, ptr @is1, align 4 ; CHECK: call void @__msan_warning ; CHECK: call void @__msan_warning ; CHECK: call { i32, i32 } asm "",{{.*}}(i32 [[ID1_F4]], i32 [[IS1_F4]]) ; CHECK: [[PACK1_F4:%.*]] = call {{.*}} @__msan_metadata_ptr_for_store_4({{.*}}@id1{{.*}}) -; CHECK: [[EXT1_F4:%.*]] = extractvalue { i8*, i32* } [[PACK1_F4]], 0 -; CHECK: [[CAST1_F4:%.*]] = bitcast i8* [[EXT1_F4]] to i32* -; CHECK: store i32 0, i32* [[CAST1_F4]] +; CHECK: [[EXT1_F4:%.*]] = extractvalue { ptr, ptr } [[PACK1_F4]], 0 +; CHECK: store i32 0, ptr [[EXT1_F4]] ; CHECK: [[PACK2_F4:%.*]] = call {{.*}} @__msan_metadata_ptr_for_store_4({{.*}}@id2{{.*}}) -; CHECK: [[EXT2_F4:%.*]] = extractvalue { i8*, i32* } [[PACK2_F4]], 0 -; CHECK: [[CAST2_F4:%.*]] = bitcast i8* [[EXT2_F4]] to i32* -; CHECK: store i32 0, i32* [[CAST2_F4]] +; CHECK: [[EXT2_F4:%.*]] = extractvalue { ptr, ptr } [[PACK2_F4]], 0 +; CHECK: store i32 0, ptr [[EXT2_F4]] ; One input register, three output registers: ; asm("" : "=r" (id1), "=r" (id2), "=r" (id3) : "r" (is1)); define dso_local void @f_1i_3o_reg() sanitize_memory { entry: - %0 = load i32, i32* @is1, align 4 + %0 = load i32, ptr @is1, align 4 %1 = call { i32, i32, i32 } asm "", "=r,=r,=r,r,~{dirflag},~{fpsr},~{flags}"(i32 %0) %asmresult = extractvalue { i32, i32, i32 } %1, 0 %asmresult1 = extractvalue { i32, i32, i32 } %1, 1 %asmresult2 = extractvalue { i32, i32, i32 } %1, 2 - store i32 %asmresult, i32* @id1, align 4 - store i32 %asmresult1, i32* @id2, align 4 - store i32 %asmresult2, i32* @id3, align 4 + store i32 %asmresult, ptr @id1, align 4 + store i32 %asmresult1, ptr @id2, align 4 + store i32 %asmresult2, ptr @id3, align 4 ret void } ; CHECK-LABEL: @f_1i_3o_reg -; CHECK: [[IS1_F5:%.*]] = load i32, i32* @is1, align 4 +; CHECK: [[IS1_F5:%.*]] = load i32, ptr @is1, align 4 ; CHECK: call void @__msan_warning ; CHECK: call { i32, i32, i32 } asm "",{{.*}}(i32 [[IS1_F5]]) ; CHECK: [[PACK1_F5:%.*]] = call {{.*}} @__msan_metadata_ptr_for_store_4({{.*}}@id1{{.*}}) -; CHECK: [[EXT1_F5:%.*]] = extractvalue { i8*, i32* } [[PACK1_F5]], 0 -; CHECK: [[CAST1_F5:%.*]] = bitcast i8* [[EXT1_F5]] to i32* -; CHECK: store i32 0, i32* [[CAST1_F5]] +; CHECK: [[EXT1_F5:%.*]] = extractvalue { ptr, ptr } [[PACK1_F5]], 0 +; CHECK: store i32 0, ptr [[EXT1_F5]] ; CHECK: [[PACK2_F5:%.*]] = call {{.*}} @__msan_metadata_ptr_for_store_4({{.*}}@id2{{.*}}) -; CHECK: [[EXT2_F5:%.*]] = extractvalue { i8*, i32* } [[PACK2_F5]], 0 -; CHECK: [[CAST2_F5:%.*]] = bitcast i8* [[EXT2_F5]] to i32* -; CHECK: store i32 0, i32* [[CAST2_F5]] +; CHECK: [[EXT2_F5:%.*]] = extractvalue { ptr, ptr } [[PACK2_F5]], 0 +; CHECK: store i32 0, ptr [[EXT2_F5]] ; CHECK: [[PACK3_F5:%.*]] = call {{.*}} @__msan_metadata_ptr_for_store_4({{.*}}@id3{{.*}}) -; CHECK: [[EXT3_F5:%.*]] = extractvalue { i8*, i32* } [[PACK3_F5]], 0 -; CHECK: [[CAST3_F5:%.*]] = bitcast i8* [[EXT3_F5]] to i32* -; CHECK: store i32 0, i32* [[CAST3_F5]] +; CHECK: [[EXT3_F5:%.*]] = extractvalue { ptr, ptr } [[PACK3_F5]], 0 +; CHECK: store i32 0, ptr [[EXT3_F5]] ; 2 input memory args, 2 output memory args: ; asm("" : "=m" (id1), "=m" (id2) : "m" (is1), "m"(is2)) define dso_local void @f_2i_2o_mem() sanitize_memory { entry: - call void asm "", "=*m,=*m,*m,*m,~{dirflag},~{fpsr},~{flags}"(i32* elementtype(i32) @id1, i32* elementtype(i32) @id2, i32* elementtype(i32) @is1, i32* elementtype(i32) @is2) + call void asm "", "=*m,=*m,*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @id1, ptr elementtype(i32) @id2, ptr elementtype(i32) @is1, ptr elementtype(i32) @is2) ret void } ; CHECK-LABEL: @f_2i_2o_mem ; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@id1{{.*}}, i64 4) ; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@id2{{.*}}, i64 4) -; CHECK: call void asm "", "=*m,=*m,*m,*m,~{dirflag},~{fpsr},~{flags}"(i32* elementtype(i32) @id1, i32* elementtype(i32) @id2, i32* elementtype(i32) @is1, i32* elementtype(i32) @is2) +; CHECK: call void asm "", "=*m,=*m,*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @id1, ptr elementtype(i32) @id2, ptr elementtype(i32) @is1, ptr elementtype(i32) @is2) ; Same input and output passed as both memory and register: ; asm("" : "=r" (id1), "=m"(id1) : "r"(is1), "m"(is1)); define dso_local void @f_1i_1o_memreg() sanitize_memory { entry: - %0 = load i32, i32* @is1, align 4 - %1 = call i32 asm "", "=r,=*m,r,*m,~{dirflag},~{fpsr},~{flags}"(i32* elementtype(i32) @id1, i32 %0, i32* elementtype(i32) @is1) - store i32 %1, i32* @id1, align 4 + %0 = load i32, ptr @is1, align 4 + %1 = call i32 asm "", "=r,=*m,r,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @id1, i32 %0, ptr elementtype(i32) @is1) + store i32 %1, ptr @id1, align 4 ret void } ; CHECK-LABEL: @f_1i_1o_memreg -; CHECK: [[IS1_F7:%.*]] = load i32, i32* @is1, align 4 +; CHECK: [[IS1_F7:%.*]] = load i32, ptr @is1, align 4 ; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@id1{{.*}}, i64 4) ; CHECK: call void @__msan_warning -; CHECK: call i32 asm "", "=r,=*m,r,*m,~{dirflag},~{fpsr},~{flags}"(i32* elementtype(i32) @id1, i32 [[IS1_F7]], i32* elementtype(i32) @is1) +; CHECK: call i32 asm "", "=r,=*m,r,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @id1, i32 [[IS1_F7]], ptr elementtype(i32) @is1) ; Three outputs, first and last returned via regs, second via mem: ; asm("" : "=r" (id1), "=m"(id2), "=r" (id3):); define dso_local void @f_3o_reg_mem_reg() sanitize_memory { entry: - %0 = call { i32, i32 } asm "", "=r,=*m,=r,~{dirflag},~{fpsr},~{flags}"(i32* elementtype(i32) @id2) + %0 = call { i32, i32 } asm "", "=r,=*m,=r,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @id2) %asmresult = extractvalue { i32, i32 } %0, 0 %asmresult1 = extractvalue { i32, i32 } %0, 1 - store i32 %asmresult, i32* @id1, align 4 - store i32 %asmresult1, i32* @id3, align 4 + store i32 %asmresult, ptr @id1, align 4 + store i32 %asmresult1, ptr @id3, align 4 ret void } ; CHECK-LABEL: @f_3o_reg_mem_reg -; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@id2{{.*}}), i64 4) -; CHECK: call { i32, i32 } asm "", "=r,=*m,=r,~{dirflag},~{fpsr},~{flags}"(i32* elementtype(i32) @id2) +; CHECK-CONS: call void @__msan_instrument_asm_store(ptr @id2, i64 4) +; CHECK: call { i32, i32 } asm "", "=r,=*m,=r,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) @id2) ; Three inputs and three outputs of different types: a pair, a char, a function pointer. @@ -227,14 +217,14 @@ ; asm("" : "=r" (pair2), "=r" (c2), "=r" (memcpy_d1) : "r"(pair1), "r"(c1), "r"(memcpy_s1)); define dso_local void @f_3i_3o_complex_reg() sanitize_memory { entry: - %0 = load i64, i64* bitcast (%struct.pair* @pair1 to i64*), align 4 - %1 = load i8, i8* @c1, align 1 - %2 = load i8* (i8*, i8*, i32)*, i8* (i8*, i8*, i32)** @memcpy_s1, align 8 - %3 = call { i8, i8* (i8*, i8*, i32)* } asm "", "=*r,=r,=r,r,r,r,~{dirflag},~{fpsr},~{flags}"(%struct.pair* elementtype(%struct.pair) @pair2, i64 %0, i8 %1, i8* (i8*, i8*, i32)* %2) - %asmresult = extractvalue { i8, i8* (i8*, i8*, i32)* } %3, 0 - %asmresult1 = extractvalue { i8, i8* (i8*, i8*, i32)* } %3, 1 - store i8 %asmresult, i8* @c2, align 1 - store i8* (i8*, i8*, i32)* %asmresult1, i8* (i8*, i8*, i32)** @memcpy_d1, align 8 + %0 = load i64, ptr @pair1, align 4 + %1 = load i8, ptr @c1, align 1 + %2 = load ptr, ptr @memcpy_s1, align 8 + %3 = call { i8, ptr } asm "", "=*r,=r,=r,r,r,r,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(%struct.pair) @pair2, i64 %0, i8 %1, ptr %2) + %asmresult = extractvalue { i8, ptr } %3, 0 + %asmresult1 = extractvalue { i8, ptr } %3, 1 + store i8 %asmresult, ptr @c2, align 1 + store ptr %asmresult1, ptr @memcpy_d1, align 8 ret void } @@ -246,14 +236,14 @@ ; CHECK: call void @__msan_warning ; CHECK: call void @__msan_warning ; CHECK: call void @__msan_warning -; CHECK: call { i8, i8* (i8*, i8*, i32)* } asm "", "=*r,=r,=r,r,r,r,~{dirflag},~{fpsr},~{flags}"(%struct.pair* elementtype(%struct.pair) @pair2, {{.*}}[[PAIR1_F9]], i8 [[C1_F9]], {{.*}} [[MEMCPY_S1_F9]]) +; CHECK: call { i8, ptr } asm "", "=*r,=r,=r,r,r,r,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(%struct.pair) @pair2, {{.*}}[[PAIR1_F9]], i8 [[C1_F9]], {{.*}} [[MEMCPY_S1_F9]]) ; Three inputs and three outputs of different types: a pair, a char, a function pointer. ; Everything is passed in memory: ; asm("" : "=m" (pair2), "=m" (c2), "=m" (memcpy_d1) : "m"(pair1), "m"(c1), "m"(memcpy_s1)); define dso_local void @f_3i_3o_complex_mem() sanitize_memory { entry: - call void asm "", "=*m,=*m,=*m,*m,*m,*m,~{dirflag},~{fpsr},~{flags}"(%struct.pair* elementtype(%struct.pair) @pair2, i8* elementtype(i8) @c2, i8* (i8*, i8*, i32)** elementtype(i8* (i8*, i8*, i32)*) @memcpy_d1, %struct.pair* elementtype(%struct.pair) @pair1, i8* elementtype(i8) @c1, i8* (i8*, i8*, i32)** elementtype(i8* (i8*, i8*, i32)*) @memcpy_s1) + call void asm "", "=*m,=*m,=*m,*m,*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(%struct.pair) @pair2, ptr elementtype(i8) @c2, ptr elementtype(ptr) @memcpy_d1, ptr elementtype(%struct.pair) @pair1, ptr elementtype(i8) @c1, ptr elementtype(ptr) @memcpy_s1) ret void } @@ -261,7 +251,7 @@ ; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@pair2{{.*}}, i64 8) ; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@c2{{.*}}, i64 1) ; CHECK-CONS: call void @__msan_instrument_asm_store({{.*}}@memcpy_d1{{.*}}, i64 8) -; CHECK: call void asm "", "=*m,=*m,=*m,*m,*m,*m,~{dirflag},~{fpsr},~{flags}"(%struct.pair* elementtype(%struct.pair) @pair2, i8* elementtype(i8) @c2, i8* (i8*, i8*, i32)** elementtype(i8* (i8*, i8*, i32)*) @memcpy_d1, %struct.pair* elementtype(%struct.pair) @pair1, i8* elementtype(i8) @c1, i8* (i8*, i8*, i32)** elementtype(i8* (i8*, i8*, i32)*) @memcpy_s1) +; CHECK: call void asm "", "=*m,=*m,=*m,*m,*m,*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(%struct.pair) @pair2, ptr elementtype(i8) @c2, ptr elementtype(ptr) @memcpy_d1, ptr elementtype(%struct.pair) @pair1, ptr elementtype(i8) @c1, ptr elementtype(ptr) @memcpy_s1) ; A simple asm goto construct to check that callbr is handled correctly: diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll --- a/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_basic.ll @@ -7,8 +7,8 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -; CHECK: @llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @msan.module_ctor to i8*)] -; CHECK: @llvm.global_ctors {{.*}} { i32 0, void ()* @msan.module_ctor, i8* null } +; CHECK: @llvm.used = appending global [1 x ptr] [ptr @msan.module_ctor] +; CHECK: @llvm.global_ctors {{.*}} { i32 0, ptr @msan.module_ctor, ptr null } ; Check the presence and the linkage type of __msan_track_origins and ; other interface symbols. @@ -25,9 +25,9 @@ ; Check instrumentation of stores -define void @Store(i32* nocapture %p, i32 %x) nounwind uwtable sanitize_memory { +define void @Store(ptr nocapture %p, i32 %x) nounwind uwtable sanitize_memory { entry: - store i32 %x, i32* %p, align 4 + store i32 %x, ptr %p, align 4 ret void } @@ -49,9 +49,9 @@ ; Shadow store has the same alignment as the original store; origin store ; does not specify explicit alignment. -define void @AlignedStore(i32* nocapture %p, i32 %x) nounwind uwtable sanitize_memory { +define void @AlignedStore(ptr nocapture %p, i32 %x) nounwind uwtable sanitize_memory { entry: - store i32 %x, i32* %p, align 32 + store i32 %x, ptr %p, align 32 ret void } @@ -70,9 +70,9 @@ ; load followed by cmp: check that we load the shadow and call __msan_warning_with_origin. -define void @LoadAndCmp(i32* nocapture %a) nounwind uwtable sanitize_memory { +define void @LoadAndCmp(ptr nocapture %a) nounwind uwtable sanitize_memory { entry: - %0 = load i32, i32* %a, align 4 + %0 = load i32, ptr %a, align 4 %tobool = icmp eq i32 %0, 0 br i1 %tobool, label %if.end, label %if.then @@ -108,10 +108,10 @@ ; CHECK: ret i32 ; Check that we get the shadow for the retval. -define void @CopyRetVal(i32* nocapture %a) nounwind uwtable sanitize_memory { +define void @CopyRetVal(ptr nocapture %a) nounwind uwtable sanitize_memory { entry: %call = tail call i32 @ReturnInt() nounwind - store i32 %call, i32* %a, align 4 + store i32 %call, ptr %a, align 4 ret void } @@ -123,22 +123,22 @@ ; Check that we generate PHIs for shadow. -define void @FuncWithPhi(i32* nocapture %a, i32* %b, i32* nocapture %c) nounwind uwtable sanitize_memory { +define void @FuncWithPhi(ptr nocapture %a, ptr %b, ptr nocapture %c) nounwind uwtable sanitize_memory { entry: - %tobool = icmp eq i32* %b, null + %tobool = icmp eq ptr %b, null br i1 %tobool, label %if.else, label %if.then if.then: ; preds = %entry - %0 = load i32, i32* %b, align 4 + %0 = load i32, ptr %b, align 4 br label %if.end if.else: ; preds = %entry - %1 = load i32, i32* %c, align 4 + %1 = load i32, ptr %c, align 4 br label %if.end if.end: ; preds = %if.else, %if.then %t.0 = phi i32 [ %0, %if.then ], [ %1, %if.else ] - store i32 %t.0, i32* %a, align 4 + store i32 %t.0, ptr %a, align 4 ret void } @@ -152,11 +152,11 @@ ; CHECK: ret void ; Compute shadow for "x << 10" -define void @ShlConst(i32* nocapture %x) nounwind uwtable sanitize_memory { +define void @ShlConst(ptr nocapture %x) nounwind uwtable sanitize_memory { entry: - %0 = load i32, i32* %x, align 4 + %0 = load i32, ptr %x, align 4 %1 = shl i32 %0, 10 - store i32 %1, i32* %x, align 4 + store i32 %1, ptr %x, align 4 ret void } @@ -170,11 +170,11 @@ ; CHECK: ret void ; Compute shadow for "10 << x": it should have 'sext i1'. -define void @ShlNonConst(i32* nocapture %x) nounwind uwtable sanitize_memory { +define void @ShlNonConst(ptr nocapture %x) nounwind uwtable sanitize_memory { entry: - %0 = load i32, i32* %x, align 4 + %0 = load i32, ptr %x, align 4 %1 = shl i32 10, %0 - store i32 %1, i32* %x, align 4 + store i32 %1, ptr %x, align 4 ret void } @@ -187,11 +187,11 @@ ; CHECK: ret void ; SExt -define void @SExt(i32* nocapture %a, i16* nocapture %b) nounwind uwtable sanitize_memory { +define void @SExt(ptr nocapture %a, ptr nocapture %b) nounwind uwtable sanitize_memory { entry: - %0 = load i16, i16* %b, align 2 + %0 = load i16, ptr %b, align 2 %1 = sext i16 %0 to i32 - store i32 %1, i32* %a, align 4 + store i32 %1, ptr %a, align 4 ret void } @@ -206,69 +206,69 @@ ; memset -define void @MemSet(i8* nocapture %x) nounwind uwtable sanitize_memory { +define void @MemSet(ptr nocapture %x) nounwind uwtable sanitize_memory { entry: - call void @llvm.memset.p0i8.i64(i8* %x, i8 42, i64 10, i1 false) + call void @llvm.memset.p0.i64(ptr %x, i8 42, i64 10, i1 false) ret void } -declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind +declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind ; CHECK-LABEL: @MemSet -; CHECK: call i8* @__msan_memset +; CHECK: call ptr @__msan_memset ; CHECK: ret void ; memcpy -define void @MemCpy(i8* nocapture %x, i8* nocapture %y) nounwind uwtable sanitize_memory { +define void @MemCpy(ptr nocapture %x, ptr nocapture %y) nounwind uwtable sanitize_memory { entry: - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %x, i8* %y, i64 10, i1 false) + call void @llvm.memcpy.p0.p0.i64(ptr %x, ptr %y, i64 10, i1 false) ret void } -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind +declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind ; CHECK-LABEL: @MemCpy -; CHECK: call i8* @__msan_memcpy +; CHECK: call ptr @__msan_memcpy ; CHECK: ret void ; memset.inline -define void @MemSetInline(i8* nocapture %x) nounwind uwtable sanitize_memory { +define void @MemSetInline(ptr nocapture %x) nounwind uwtable sanitize_memory { entry: - call void @llvm.memset.inline.p0i8.i64(i8* %x, i8 42, i64 10, i1 false) + call void @llvm.memset.inline.p0.i64(ptr %x, i8 42, i64 10, i1 false) ret void } -declare void @llvm.memset.inline.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind +declare void @llvm.memset.inline.p0.i64(ptr nocapture, i8, i64, i1) nounwind ; CHECK-LABEL: @MemSetInline -; CHECK: call i8* @__msan_memset +; CHECK: call ptr @__msan_memset ; CHECK: ret void ; memcpy.inline -define void @MemCpyInline(i8* nocapture %x, i8* nocapture %y) nounwind uwtable sanitize_memory { +define void @MemCpyInline(ptr nocapture %x, ptr nocapture %y) nounwind uwtable sanitize_memory { entry: - call void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* %x, i8* %y, i64 10, i1 false) + call void @llvm.memcpy.inline.p0.p0.i64(ptr %x, ptr %y, i64 10, i1 false) ret void } -declare void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind +declare void @llvm.memcpy.inline.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind ; CHECK-LABEL: @MemCpyInline -; CHECK: call i8* @__msan_memcpy +; CHECK: call ptr @__msan_memcpy ; CHECK: ret void ; memmove is lowered to a call -define void @MemMove(i8* nocapture %x, i8* nocapture %y) nounwind uwtable sanitize_memory { +define void @MemMove(ptr nocapture %x, ptr nocapture %y) nounwind uwtable sanitize_memory { entry: - call void @llvm.memmove.p0i8.p0i8.i64(i8* %x, i8* %y, i64 10, i1 false) + call void @llvm.memmove.p0.p0.i64(ptr %x, ptr %y, i64 10, i1 false) ret void } -declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind +declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind ; CHECK-LABEL: @MemMove -; CHECK: call i8* @__msan_memmove +; CHECK: call ptr @__msan_memmove ; CHECK: ret void ;; ------------ @@ -276,34 +276,34 @@ ;; been added to the MemIntrinsic class hierarchy. These will act as a reminder to ;; verify that MSAN handles these intrinsics properly once they have been ;; added to that class hierarchy. -declare void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* nocapture writeonly, i8, i64, i32) nounwind -declare void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind -declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind +declare void @llvm.memset.element.unordered.atomic.p0.i64(ptr nocapture writeonly, i8, i64, i32) nounwind +declare void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind +declare void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind -define void @atomic_memcpy(i8* nocapture %x, i8* nocapture %y) nounwind { +define void @atomic_memcpy(ptr nocapture %x, ptr nocapture %y) nounwind { ; CHECK-LABEL: atomic_memcpy ; CHECK-NEXT: call void @llvm.donothing - ; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %x, i8* align 2 %y, i64 16, i32 1) + ; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 %x, ptr align 2 %y, i64 16, i32 1) ; CHECK-NEXT: ret void - call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %x, i8* align 2 %y, i64 16, i32 1) + call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 %x, ptr align 2 %y, i64 16, i32 1) ret void } -define void @atomic_memmove(i8* nocapture %x, i8* nocapture %y) nounwind { +define void @atomic_memmove(ptr nocapture %x, ptr nocapture %y) nounwind { ; CHECK-LABEL: atomic_memmove ; CHECK-NEXT: call void @llvm.donothing - ; CHECK-NEXT: call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %x, i8* align 2 %y, i64 16, i32 1) + ; CHECK-NEXT: call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 %x, ptr align 2 %y, i64 16, i32 1) ; CHECK-NEXT: ret void - call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %x, i8* align 2 %y, i64 16, i32 1) + call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 %x, ptr align 2 %y, i64 16, i32 1) ret void } -define void @atomic_memset(i8* nocapture %x) nounwind { +define void @atomic_memset(ptr nocapture %x) nounwind { ; CHECK-LABEL: atomic_memset ; CHECK-NEXT: call void @llvm.donothing - ; CHECK-NEXT: call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %x, i8 88, i64 16, i32 1) + ; CHECK-NEXT: call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 %x, i8 88, i64 16, i32 1) ; CHECK-NEXT: ret void - call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %x, i8 88, i64 16, i32 1) + call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 %x, i8 88, i64 16, i32 1) ret void } @@ -393,10 +393,10 @@ ; CHECK: ret { i64, i64 } -define { i64*, double } @SelectStruct2(i1 zeroext %x, { i64*, double } %a, { i64*, double } %b) readnone sanitize_memory { +define { ptr, double } @SelectStruct2(i1 zeroext %x, { ptr, double } %a, { ptr, double } %b) readnone sanitize_memory { entry: - %c = select i1 %x, { i64*, double } %a, { i64*, double } %b - ret { i64*, double } %c + %c = select i1 %x, { ptr, double } %a, { ptr, double } %b + ret { ptr, double } %c } ; CHECK-LABEL: @SelectStruct2 @@ -404,37 +404,37 @@ ; CHECK-NEXT: select i1 {{.*}}, { i64, i64 } { i64 -1, i64 -1 }, { i64, i64 } ; ORIGINS: select i1 ; ORIGINS: select i1 -; CHECK-NEXT: select i1 {{.*}}, { i64*, double } -; CHECK: ret { i64*, double } +; CHECK-NEXT: select i1 {{.*}}, { ptr, double } +; CHECK: ret { ptr, double } -define i8* @IntToPtr(i64 %x) nounwind uwtable readnone sanitize_memory { +define ptr @IntToPtr(i64 %x) nounwind uwtable readnone sanitize_memory { entry: - %0 = inttoptr i64 %x to i8* - ret i8* %0 + %0 = inttoptr i64 %x to ptr + ret ptr %0 } ; CHECK-LABEL: @IntToPtr -; CHECK: load i64, i64*{{.*}}__msan_param_tls -; ORIGINS-NEXT: load i32, i32*{{.*}}__msan_param_origin_tls +; CHECK: load i64, ptr{{.*}}__msan_param_tls +; ORIGINS-NEXT: load i32, ptr{{.*}}__msan_param_origin_tls ; CHECK-NEXT: call void @llvm.donothing ; CHECK-NEXT: inttoptr ; CHECK-NEXT: store i64{{.*}}__msan_retval_tls -; CHECK: ret i8* +; CHECK: ret ptr -define i8* @IntToPtr_ZExt(i16 %x) nounwind uwtable readnone sanitize_memory { +define ptr @IntToPtr_ZExt(i16 %x) nounwind uwtable readnone sanitize_memory { entry: - %0 = inttoptr i16 %x to i8* - ret i8* %0 + %0 = inttoptr i16 %x to ptr + ret ptr %0 } ; CHECK-LABEL: @IntToPtr_ZExt -; CHECK: load i16, i16*{{.*}}__msan_param_tls +; CHECK: load i16, ptr{{.*}}__msan_param_tls ; CHECK: zext ; CHECK-NEXT: inttoptr ; CHECK-NEXT: store i64{{.*}}__msan_retval_tls -; CHECK: ret i8* +; CHECK: ret ptr ; Check that we insert exactly one check on udiv @@ -468,7 +468,7 @@ ; CHECK: %[[SB:.*]] = load i32,{{.*}}@__msan_param_tls ; CHECK: %[[SC:.*]] = or i32 %[[SA]], %[[SB]] ; CHECK: = fdiv float -; CHECK: store i32 %[[SC]], i32* {{.*}}@__msan_retval_tls +; CHECK: store i32 %[[SC]], ptr {{.*}}@__msan_retval_tls ; CHECK: ret float ; Check that fneg simply propagates shadow. @@ -483,7 +483,7 @@ ; CHECK: %[[SA:.*]] = load i32,{{.*}}@__msan_param_tls ; ORIGINS: %[[SB:.*]] = load i32,{{.*}}@__msan_param_origin_tls ; CHECK: = fneg float -; CHECK: store i32 %[[SA]], i32* {{.*}}@__msan_retval_tls +; CHECK: store i32 %[[SA]], ptr {{.*}}@__msan_retval_tls ; ORIGINS: store i32{{.*}}@__msan_retval_origin_tls ; CHECK: ret float @@ -592,15 +592,15 @@ ; Check that we propagate shadow for x<0, x>=0, etc (i.e. sign bit tests) ; of the vector arguments. -define <2 x i1> @ICmpSLT_vector_Zero(<2 x i32*> %x) nounwind uwtable readnone sanitize_memory { - %1 = icmp slt <2 x i32*> %x, zeroinitializer +define <2 x i1> @ICmpSLT_vector_Zero(<2 x ptr> %x) nounwind uwtable readnone sanitize_memory { + %1 = icmp slt <2 x ptr> %x, zeroinitializer ret <2 x i1> %1 } ; CHECK-LABEL: @ICmpSLT_vector_Zero ; CHECK: icmp slt <2 x i64> ; CHECK-NOT: call void @__msan_warning -; CHECK: icmp slt <2 x i32*> +; CHECK: icmp slt <2 x ptr> ; CHECK-NOT: call void @__msan_warning ; CHECK: ret <2 x i1> @@ -644,25 +644,25 @@ define i32 @ShadowLoadAlignmentLarge() nounwind uwtable sanitize_memory { %y = alloca i32, align 64 - %1 = load volatile i32, i32* %y, align 64 + %1 = load volatile i32, ptr %y, align 64 ret i32 %1 } ; CHECK-LABEL: @ShadowLoadAlignmentLarge -; CHECK: load volatile i32, i32* {{.*}} align 64 -; CHECK: load i32, i32* {{.*}} align 64 +; CHECK: load volatile i32, ptr {{.*}} align 64 +; CHECK: load i32, ptr {{.*}} align 64 ; CHECK: ret i32 define i32 @ShadowLoadAlignmentSmall() nounwind uwtable sanitize_memory { %y = alloca i32, align 2 - %1 = load volatile i32, i32* %y, align 2 + %1 = load volatile i32, ptr %y, align 2 ret i32 %1 } ; CHECK-LABEL: @ShadowLoadAlignmentSmall -; CHECK: load volatile i32, i32* {{.*}} align 2 -; CHECK: load i32, i32* {{.*}} align 2 -; ORIGINS: load i32, i32* {{.*}} align 4 +; CHECK: load volatile i32, ptr {{.*}} align 2 +; CHECK: load i32, ptr {{.*}} align 2 +; ORIGINS: load i32, ptr {{.*}} align 4 ; CHECK: ret i32 @@ -726,46 +726,44 @@ ; Test handling of vectors of pointers. ; Check that shadow of such vector is a vector of integers. -define <8 x i8*> @VectorOfPointers(<8 x i8*>* %p) nounwind uwtable sanitize_memory { - %x = load <8 x i8*>, <8 x i8*>* %p - ret <8 x i8*> %x +define <8 x ptr> @VectorOfPointers(ptr %p) nounwind uwtable sanitize_memory { + %x = load <8 x ptr>, ptr %p + ret <8 x ptr> %x } ; CHECK-LABEL: @VectorOfPointers -; CHECK: load <8 x i8*>, <8 x i8*>* -; CHECK: load <8 x i64>, <8 x i64>* +; CHECK: load <8 x ptr>, ptr +; CHECK: load <8 x i64>, ptr ; CHECK: store <8 x i64> {{.*}} @__msan_retval_tls -; CHECK: ret <8 x i8*> +; CHECK: ret <8 x ptr> ; Test handling of va_copy. -declare void @llvm.va_copy(i8*, i8*) nounwind +declare void @llvm.va_copy(ptr, ptr) nounwind -define void @VACopy(i8* %p1, i8* %p2) nounwind uwtable sanitize_memory { - call void @llvm.va_copy(i8* %p1, i8* %p2) nounwind +define void @VACopy(ptr %p1, ptr %p2) nounwind uwtable sanitize_memory { + call void @llvm.va_copy(ptr %p1, ptr %p2) nounwind ret void } ; CHECK-LABEL: @VACopy -; CHECK: call void @llvm.memset.p0i8.i64({{.*}}, i8 0, i64 24, i1 false) +; CHECK: call void @llvm.memset.p0.i64({{.*}}, i8 0, i64 24, i1 false) ; CHECK: ret void ; Test that va_start instrumentation does not use va_arg_tls*. ; It should work with a local stack copy instead. -%struct.__va_list_tag = type { i32, i32, i8*, i8* } -declare void @llvm.va_start(i8*) nounwind +%struct.__va_list_tag = type { i32, i32, ptr, ptr } +declare void @llvm.va_start(ptr) nounwind ; Function Attrs: nounwind uwtable define void @VAStart(i32 %x, ...) sanitize_memory { entry: %x.addr = alloca i32, align 4 %va = alloca [1 x %struct.__va_list_tag], align 16 - store i32 %x, i32* %x.addr, align 4 - %arraydecay = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i32 0, i32 0 - %arraydecay1 = bitcast %struct.__va_list_tag* %arraydecay to i8* - call void @llvm.va_start(i8* %arraydecay1) + store i32 %x, ptr %x.addr, align 4 + call void @llvm.va_start(ptr %va) ret void } @@ -779,9 +777,9 @@ ; Test handling of volatile stores. ; Check that MemorySanitizer does not add a check of the value being stored. -define void @VolatileStore(i32* nocapture %p, i32 %x) nounwind uwtable sanitize_memory { +define void @VolatileStore(ptr nocapture %p, i32 %x) nounwind uwtable sanitize_memory { entry: - store volatile i32 %x, i32* %p, align 4 + store volatile i32 %x, ptr %p, align 4 ret void } @@ -821,15 +819,15 @@ define i32 @NoSanitizeMemoryAlloca() { entry: %p = alloca i32, align 4 - %x = call i32 @NoSanitizeMemoryAllocaHelper(i32* %p) + %x = call i32 @NoSanitizeMemoryAllocaHelper(ptr %p) ret i32 %x } -declare i32 @NoSanitizeMemoryAllocaHelper(i32* %p) +declare i32 @NoSanitizeMemoryAllocaHelper(ptr %p) ; CHECK-LABEL: @NoSanitizeMemoryAlloca -; CHECK: call void @llvm.memset.p0i8.i64(i8* align 4 {{.*}}, i8 0, i64 4, i1 false) -; CHECK: call i32 @NoSanitizeMemoryAllocaHelper(i32* +; CHECK: call void @llvm.memset.p0.i64(ptr align 4 {{.*}}, i8 0, i64 4, i1 false) +; CHECK: call i32 @NoSanitizeMemoryAllocaHelper(ptr ; CHECK: ret i32 @@ -845,7 +843,7 @@ declare i32 @NoSanitizeMemoryUndefHelper(i32 %x) ; CHECK-LABEL: @NoSanitizeMemoryUndef -; CHECK: store i32 0, i32* {{.*}} @__msan_param_tls +; CHECK: store i32 0, ptr @__msan_param_tls ; CHECK: call i32 @NoSanitizeMemoryUndefHelper(i32 undef) ; CHECK: ret i32 @@ -869,7 +867,7 @@ } ; CHECK: [[A:%.*]] = phi i32 [ undef, %cond.true ], [ undef, %cond.false ] -; CHECK: store i32 0, i32* bitcast {{.*}} @__msan_retval_tls +; CHECK: store i32 0, ptr @__msan_retval_tls ; CHECK: ret i32 [[A]] @@ -877,9 +875,9 @@ ; argument shadow is a compile-time zero constant (which is always the case ; in functions missing sanitize_memory attribute). -define i32 @NoSanitizeMemoryParamTLS(i32* nocapture readonly %x) { +define i32 @NoSanitizeMemoryParamTLS(ptr nocapture readonly %x) { entry: - %0 = load i32, i32* %x, align 4 + %0 = load i32, ptr %x, align 4 %call = tail call i32 @NoSanitizeMemoryParamTLSHelper(i32 %0) ret i32 %call } @@ -899,8 +897,8 @@ } ; CHECK-LABEL: @ArgumentShadowAlignment -; CHECK: load <2 x i64>, <2 x i64>* {{.*}} @__msan_param_tls {{.*}}, align 8 -; CHECK: store <2 x i64> {{.*}} @__msan_retval_tls {{.*}}, align 8 +; CHECK: load <2 x i64>, ptr {{.*}} @__msan_param_tls {{.*}}, align 8 +; CHECK: store <2 x i64> {{.*}}, ptr @__msan_retval_tls, align 8 ; CHECK: ret <2 x i64> @@ -937,18 +935,14 @@ declare void @VAArgStructFn(i32 %guard, ...) -define void @VAArgStruct(%struct.StructByVal* nocapture %s) sanitize_memory { +define void @VAArgStruct(ptr nocapture %s) sanitize_memory { entry: %agg.tmp2 = alloca %struct.StructByVal, align 8 - %0 = bitcast %struct.StructByVal* %s to i8* - %agg.tmp.sroa.0.0..sroa_cast = bitcast %struct.StructByVal* %s to i64* - %agg.tmp.sroa.0.0.copyload = load i64, i64* %agg.tmp.sroa.0.0..sroa_cast, align 4 - %agg.tmp.sroa.2.0..sroa_idx = getelementptr inbounds %struct.StructByVal, %struct.StructByVal* %s, i64 0, i32 2 - %agg.tmp.sroa.2.0..sroa_cast = bitcast i32* %agg.tmp.sroa.2.0..sroa_idx to i64* - %agg.tmp.sroa.2.0.copyload = load i64, i64* %agg.tmp.sroa.2.0..sroa_cast, align 4 - %1 = bitcast %struct.StructByVal* %agg.tmp2 to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %1, i8* align 4 %0, i64 16, i1 false) - call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, %struct.StructByVal* byval(%struct.StructByVal) align 8 %agg.tmp2) + %agg.tmp.sroa.0.0.copyload = load i64, ptr %s, align 4 + %agg.tmp.sroa.2.0..sroa_idx = getelementptr inbounds %struct.StructByVal, ptr %s, i64 0, i32 2 + %agg.tmp.sroa.2.0.copyload = load i64, ptr %agg.tmp.sroa.2.0..sroa_idx, align 4 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp2, ptr align 4 %s, i64 16, i1 false) + call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, ptr byval(%struct.StructByVal) align 8 %agg.tmp2) ret void } @@ -958,38 +952,34 @@ ; CHECK-LABEL: @VAArgStruct ; undef not stored to __msan_va_arg_tls - it's a fixed argument ; first struct through general purpose registers -; CHECK: store i64 {{.*}}, i64* {{.*}}@__msan_va_arg_tls{{.*}}, i64 8){{.*}}, align 8 -; CHECK: store i64 {{.*}}, i64* {{.*}}@__msan_va_arg_tls{{.*}}, i64 16){{.*}}, align 8 +; CHECK: store i64 {{.*}}, ptr {{.*}}@__msan_va_arg_tls{{.*}}, i64 8){{.*}}, align 8 +; CHECK: store i64 {{.*}}, ptr {{.*}}@__msan_va_arg_tls{{.*}}, i64 16){{.*}}, align 8 ; second struct through general purpose registers -; CHECK: store i64 {{.*}}, i64* {{.*}}@__msan_va_arg_tls{{.*}}, i64 24){{.*}}, align 8 -; CHECK: store i64 {{.*}}, i64* {{.*}}@__msan_va_arg_tls{{.*}}, i64 32){{.*}}, align 8 +; CHECK: store i64 {{.*}}, ptr {{.*}}@__msan_va_arg_tls{{.*}}, i64 24){{.*}}, align 8 +; CHECK: store i64 {{.*}}, ptr {{.*}}@__msan_va_arg_tls{{.*}}, i64 32){{.*}}, align 8 ; third struct through the overflow area byval -; CHECK: ptrtoint %struct.StructByVal* {{.*}} to i64 -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64{{.*}}@__msan_va_arg_tls {{.*}}, i64 176 -; CHECK: store i64 16, i64* @__msan_va_arg_overflow_size_tls +; CHECK: ptrtoint ptr {{.*}} to i64 +; CHECK: call void @llvm.memcpy.p0.p0.i64{{.*}}@__msan_va_arg_tls {{.*}}, i64 176 +; CHECK: store i64 16, ptr @__msan_va_arg_overflow_size_tls ; CHECK: call void (i32, ...) @VAArgStructFn ; CHECK: ret void ; Same code compiled without SSE (see attributes below). ; The register save area is only 48 bytes instead of 176. -define void @VAArgStructNoSSE(%struct.StructByVal* nocapture %s) sanitize_memory #0 { +define void @VAArgStructNoSSE(ptr nocapture %s) sanitize_memory #0 { entry: %agg.tmp2 = alloca %struct.StructByVal, align 8 - %0 = bitcast %struct.StructByVal* %s to i8* - %agg.tmp.sroa.0.0..sroa_cast = bitcast %struct.StructByVal* %s to i64* - %agg.tmp.sroa.0.0.copyload = load i64, i64* %agg.tmp.sroa.0.0..sroa_cast, align 4 - %agg.tmp.sroa.2.0..sroa_idx = getelementptr inbounds %struct.StructByVal, %struct.StructByVal* %s, i64 0, i32 2 - %agg.tmp.sroa.2.0..sroa_cast = bitcast i32* %agg.tmp.sroa.2.0..sroa_idx to i64* - %agg.tmp.sroa.2.0.copyload = load i64, i64* %agg.tmp.sroa.2.0..sroa_cast, align 4 - %1 = bitcast %struct.StructByVal* %agg.tmp2 to i8* - call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %1, i8* align 4 %0, i64 16, i1 false) - call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, %struct.StructByVal* byval(%struct.StructByVal) align 8 %agg.tmp2) + %agg.tmp.sroa.0.0.copyload = load i64, ptr %s, align 4 + %agg.tmp.sroa.2.0..sroa_idx = getelementptr inbounds %struct.StructByVal, ptr %s, i64 0, i32 2 + %agg.tmp.sroa.2.0.copyload = load i64, ptr %agg.tmp.sroa.2.0..sroa_idx, align 4 + call void @llvm.memcpy.p0.p0.i64(ptr align 4 %agg.tmp2, ptr align 4 %s, i64 16, i1 false) + call void (i32, ...) @VAArgStructFn(i32 undef, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, i64 %agg.tmp.sroa.0.0.copyload, i64 %agg.tmp.sroa.2.0.copyload, ptr byval(%struct.StructByVal) align 8 %agg.tmp2) ret void } attributes #0 = { "target-features"="+fxsr,+x87,-sse" } -; CHECK: call void @llvm.memcpy.p0i8.p0i8.i64{{.*}}@__msan_va_arg_tls {{.*}}, i64 48 +; CHECK: call void @llvm.memcpy.p0.p0.i64{{.*}}@__msan_va_arg_tls {{.*}}, i64 48 declare i32 @InnerTailCall(i32 %a) @@ -1022,35 +1012,33 @@ ; No instrumentation between call and ret. ; CHECK-NEXT: ret i32 -declare i32* @MismatchingMustTailCall(i32 %a) +declare ptr @MismatchingMustTailCall(i32 %a) -define i8* @MismatchingCallMustTailCall(i32 %a) sanitize_memory { - %b = musttail call i32* @MismatchingMustTailCall(i32 %a) - %c = bitcast i32* %b to i8* - ret i8* %c +define ptr @MismatchingCallMustTailCall(i32 %a) sanitize_memory { + %b = musttail call ptr @MismatchingMustTailCall(i32 %a) + ret ptr %b } ; For "musttail" calls we can not insert any shadow manipulating code between ; call and the return instruction. And we don't need to, because everything is ; taken care of in the callee. -; CHECK-LABEL: define i8* @MismatchingCallMustTailCall -; CHECK: musttail call i32* @MismatchingMustTailCall +; CHECK-LABEL: define ptr @MismatchingCallMustTailCall +; CHECK: musttail call ptr @MismatchingMustTailCall ; No instrumentation between call and ret. -; CHECK-NEXT: bitcast i32* {{.*}} to i8* -; CHECK-NEXT: ret i8* +; CHECK-NEXT: ret ptr ; CHECK-LABEL: define internal void @msan.module_ctor() #[[#ATTR:]] { ; CHECK: call void @__msan_init() ; CHECK-CALLS: declare void @__msan_maybe_warning_1(i8 zeroext, i32 zeroext) -; CHECK-CALLS: declare void @__msan_maybe_store_origin_1(i8 zeroext, i8*, i32 zeroext) +; CHECK-CALLS: declare void @__msan_maybe_store_origin_1(i8 zeroext, ptr, i32 zeroext) ; CHECK-CALLS: declare void @__msan_maybe_warning_2(i16 zeroext, i32 zeroext) -; CHECK-CALLS: declare void @__msan_maybe_store_origin_2(i16 zeroext, i8*, i32 zeroext) +; CHECK-CALLS: declare void @__msan_maybe_store_origin_2(i16 zeroext, ptr, i32 zeroext) ; CHECK-CALLS: declare void @__msan_maybe_warning_4(i32 zeroext, i32 zeroext) -; CHECK-CALLS: declare void @__msan_maybe_store_origin_4(i32 zeroext, i8*, i32 zeroext) +; CHECK-CALLS: declare void @__msan_maybe_store_origin_4(i32 zeroext, ptr, i32 zeroext) ; CHECK-CALLS: declare void @__msan_maybe_warning_8(i64 zeroext, i32 zeroext) -; CHECK-CALLS: declare void @__msan_maybe_store_origin_8(i64 zeroext, i8*, i32 zeroext) +; CHECK-CALLS: declare void @__msan_maybe_store_origin_8(i64 zeroext, ptr, i32 zeroext) ; CHECK: attributes #[[#ATTR]] = { nounwind } diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_debug_info.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_debug_info.ll --- a/llvm/test/Instrumentation/MemorySanitizer/msan_debug_info.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_debug_info.ll @@ -19,46 +19,45 @@ !14 = !DILocation(line: 9, column: 4, scope: !2) !15 = !DILocation(line: 9, column: 5, scope: !2) -define void @Store(i32* nocapture %p, i32 %x) nounwind uwtable sanitize_memory { +define void @Store(ptr nocapture %p, i32 %x) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @Store( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8, !dbg [[DBG1:![0-9]+]] -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i32*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i32*), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG1:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] ; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG1]] -; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint i32* [[P:%.*]] to i64, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to i32*, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP5]], 17592186044416, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to i32*, !dbg [[DBG1]] -; CHECK-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP9:%.*]] = bitcast i32* [[P]] to i8*, !dbg [[DBG1]] -; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[TMP2]], i8* [[TMP9]], i32 zeroext [[TMP3]]), !dbg [[DBG1]] -; CHECK-NEXT: store i32 [[X:%.*]], i32* [[P]], align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr, !dbg [[DBG1]] +; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4, !dbg [[DBG1]] +; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[TMP2]], ptr [[P]], i32 zeroext [[TMP3]]), !dbg [[DBG1]] +; CHECK-NEXT: store i32 [[X:%.*]], ptr [[P]], align 4, !dbg [[DBG1]] ; CHECK-NEXT: ret void ; entry: - store i32 %x, i32* %p, align 4, !dbg !10 + store i32 %x, ptr %p, align 4, !dbg !10 ret void } -define void @LoadAndCmp(i32* nocapture %a) nounwind uwtable sanitize_memory { +define void @LoadAndCmp(ptr nocapture %a) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @LoadAndCmp( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] ; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[A:%.*]], align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint i32* [[A]] to i64, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A:%.*]], align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[A]] to i64, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32*, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i32*, !dbg [[DBG1]] -; CHECK-NEXT: [[_MSLD:%.*]] = load i32, i32* [[TMP5]], align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG1]] +; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP9:%.*]] = xor i32 [[TMP2]], 0, !dbg [[DBG7:![0-9]+]] ; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[_MSLD]], 0, !dbg [[DBG7]] ; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0, !dbg [[DBG7]] @@ -71,14 +70,14 @@ ; CHECK-NEXT: call void @__msan_maybe_warning_1(i8 zeroext [[TMP15]], i32 zeroext [[TMP8]]), !dbg [[DBG8]] ; CHECK-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]], !dbg [[DBG8]] ; CHECK: if.then: -; CHECK-NEXT: store i64 0, i64* @__msan_va_arg_overflow_size_tls, align 8 +; CHECK-NEXT: store i64 0, ptr @__msan_va_arg_overflow_size_tls, align 8 ; CHECK-NEXT: tail call void (...) @foo() #[[ATTR5:[0-9]+]] ; CHECK-NEXT: br label [[IF_END]] ; CHECK: if.end: ; CHECK-NEXT: ret void ; entry: - %0 = load i32, i32* %a, align 4, !dbg !10 + %0 = load i32, ptr %a, align 4, !dbg !10 %tobool = icmp eq i32 %0, 0, !dbg !11 br i1 %tobool, label %if.end, label %if.then, !dbg !12 @@ -94,196 +93,194 @@ ; CHECK-LABEL: @ReturnInt( ; CHECK-NEXT: entry: ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: store i32 0, i32* @__msan_retval_origin_tls, align 4, !dbg [[DBG1]] +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4, !dbg [[DBG1]] ; CHECK-NEXT: ret i32 123, !dbg [[DBG1]] ; entry: ret i32 123, !dbg !10 } -define void @CopyRetVal(i32* nocapture %a) nounwind uwtable sanitize_memory { +define void @CopyRetVal(ptr nocapture %a) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @CopyRetVal( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8, !dbg [[DBG1]] +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8, !dbg [[DBG1]] ; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @ReturnInt() #[[ATTR5]], !dbg [[DBG1]] -; CHECK-NEXT: [[_MSRET:%.*]] = load i32, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8, !dbg [[DBG7]] -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* @__msan_retval_origin_tls, align 4, !dbg [[DBG7]] +; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8, !dbg [[DBG7]] +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 4, !dbg [[DBG7]] ; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG7]] -; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint i32* [[A:%.*]] to i64, !dbg [[DBG7]] +; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[A:%.*]] to i64, !dbg [[DBG7]] ; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080, !dbg [[DBG7]] -; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32*, !dbg [[DBG7]] +; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr, !dbg [[DBG7]] ; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416, !dbg [[DBG7]] -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i32*, !dbg [[DBG7]] -; CHECK-NEXT: store i32 [[_MSRET]], i32* [[TMP5]], align 4, !dbg [[DBG7]] -; CHECK-NEXT: [[TMP8:%.*]] = bitcast i32* [[A]] to i8*, !dbg [[DBG7]] -; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[_MSRET]], i8* [[TMP8]], i32 zeroext [[TMP2]]), !dbg [[DBG7]] -; CHECK-NEXT: store i32 [[CALL]], i32* [[A]], align 4, !dbg [[DBG7]] +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG7]] +; CHECK-NEXT: store i32 [[_MSRET]], ptr [[TMP5]], align 4, !dbg [[DBG7]] +; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[_MSRET]], ptr [[A]], i32 zeroext [[TMP2]]), !dbg [[DBG7]] +; CHECK-NEXT: store i32 [[CALL]], ptr [[A]], align 4, !dbg [[DBG7]] ; CHECK-NEXT: ret void ; entry: %call = tail call i32 @ReturnInt() nounwind, !dbg !10 - store i32 %call, i32* %a, align 4, !dbg !11 + store i32 %call, ptr %a, align 4, !dbg !11 ret void } -define void @SExt(i32* nocapture %a, i16* nocapture %b) nounwind uwtable sanitize_memory { +define void @SExt(ptr nocapture %a, ptr nocapture %b) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @SExt( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i64*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i32*), align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] ; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG1]] -; CHECK-NEXT: [[TMP4:%.*]] = load i16, i16* [[B:%.*]], align 2, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint i16* [[B]] to i64, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr [[B:%.*]], align 2, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[B]] to i64, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i16*, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], 17592186044416, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], -4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to i32*, !dbg [[DBG1]] -; CHECK-NEXT: [[_MSLD:%.*]] = load i16, i16* [[TMP7]], align 2, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr, !dbg [[DBG1]] +; CHECK-NEXT: [[_MSLD:%.*]] = load i16, ptr [[TMP7]], align 2, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG1]] ; CHECK-NEXT: [[_MSPROP:%.*]] = sext i16 [[_MSLD]] to i32, !dbg [[DBG7]] ; CHECK-NEXT: [[TMP12:%.*]] = sext i16 [[TMP4]] to i32, !dbg [[DBG7]] ; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP2]], i32 zeroext [[TMP3]]), !dbg [[DBG8]] -; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint i32* [[A:%.*]] to i64, !dbg [[DBG8]] +; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[A:%.*]] to i64, !dbg [[DBG8]] ; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 87960930222080, !dbg [[DBG8]] -; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to i32*, !dbg [[DBG8]] +; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr, !dbg [[DBG8]] ; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP14]], 17592186044416, !dbg [[DBG8]] -; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to i32*, !dbg [[DBG8]] -; CHECK-NEXT: store i32 [[_MSPROP]], i32* [[TMP15]], align 4, !dbg [[DBG8]] -; CHECK-NEXT: [[TMP18:%.*]] = bitcast i32* [[A]] to i8*, !dbg [[DBG8]] -; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[_MSPROP]], i8* [[TMP18]], i32 zeroext [[TMP11]]), !dbg [[DBG8]] -; CHECK-NEXT: store i32 [[TMP12]], i32* [[A]], align 4, !dbg [[DBG8]] +; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to ptr, !dbg [[DBG8]] +; CHECK-NEXT: store i32 [[_MSPROP]], ptr [[TMP15]], align 4, !dbg [[DBG8]] +; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[_MSPROP]], ptr [[A]], i32 zeroext [[TMP11]]), !dbg [[DBG8]] +; CHECK-NEXT: store i32 [[TMP12]], ptr [[A]], align 4, !dbg [[DBG8]] ; CHECK-NEXT: ret void ; entry: - %0 = load i16, i16* %b, align 2, !dbg !10 + %0 = load i16, ptr %b, align 2, !dbg !10 %1 = sext i16 %0 to i32, !dbg !11 - store i32 %1, i32* %a, align 4, !dbg !12 + store i32 %1, ptr %a, align 4, !dbg !12 ret void } -define void @MemSet(i8* nocapture %x) nounwind uwtable sanitize_memory { +define void @MemSet(ptr nocapture %x) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @MemSet( ; CHECK-NEXT: entry: ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] -; CHECK-NEXT: [[TMP0:%.*]] = call i8* @__msan_memset(i8* [[X:%.*]], i32 42, i64 10), !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = call ptr @__msan_memset(ptr [[X:%.*]], i32 42, i64 10), !dbg [[DBG1]] ; CHECK-NEXT: ret void ; entry: - call void @llvm.memset.p0i8.i64(i8* %x, i8 42, i64 10, i1 false), !dbg !10 + call void @llvm.memset.p0.i64(ptr %x, i8 42, i64 10, i1 false), !dbg !10 ret void } -declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind +declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind -define void @MemCpy(i8* nocapture %x, i8* nocapture %y) nounwind uwtable sanitize_memory { +define void @MemCpy(ptr nocapture %x, ptr nocapture %y) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @MemCpy( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i64*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i32*), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = call i8* @__msan_memcpy(i8* [[X:%.*]], i8* [[Y:%.*]], i64 10), !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = call ptr @__msan_memcpy(ptr [[X:%.*]], ptr [[Y:%.*]], i64 10), !dbg [[DBG1]] ; CHECK-NEXT: ret void ; entry: - call void @llvm.memcpy.p0i8.p0i8.i64(i8* %x, i8* %y, i64 10, i1 false), !dbg !10 + call void @llvm.memcpy.p0.p0.i64(ptr %x, ptr %y, i64 10, i1 false), !dbg !10 ret void } -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind +declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind -define void @MemSetInline(i8* nocapture %x) nounwind uwtable sanitize_memory { +define void @MemSetInline(ptr nocapture %x) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @MemSetInline( ; CHECK-NEXT: entry: ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] -; CHECK-NEXT: [[TMP0:%.*]] = call i8* @__msan_memset(i8* [[X:%.*]], i32 42, i64 10), !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = call ptr @__msan_memset(ptr [[X:%.*]], i32 42, i64 10), !dbg [[DBG1]] ; CHECK-NEXT: ret void ; entry: - call void @llvm.memset.inline.p0i8.i64(i8* %x, i8 42, i64 10, i1 false), !dbg !10 + call void @llvm.memset.inline.p0.i64(ptr %x, i8 42, i64 10, i1 false), !dbg !10 ret void } -declare void @llvm.memset.inline.p0i8.i64(i8* nocapture, i8, i64, i1) nounwind +declare void @llvm.memset.inline.p0.i64(ptr nocapture, i8, i64, i1) nounwind -define void @MemCpyInline(i8* nocapture %x, i8* nocapture %y) nounwind uwtable sanitize_memory { +define void @MemCpyInline(ptr nocapture %x, ptr nocapture %y) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @MemCpyInline( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i64*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i32*), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = call i8* @__msan_memcpy(i8* [[X:%.*]], i8* [[Y:%.*]], i64 10), !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = call ptr @__msan_memcpy(ptr [[X:%.*]], ptr [[Y:%.*]], i64 10), !dbg [[DBG1]] ; CHECK-NEXT: ret void ; entry: - call void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* %x, i8* %y, i64 10, i1 false), !dbg !10 + call void @llvm.memcpy.inline.p0.p0.i64(ptr %x, ptr %y, i64 10, i1 false), !dbg !10 ret void } -declare void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind +declare void @llvm.memcpy.inline.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind -define void @MemMove(i8* nocapture %x, i8* nocapture %y) nounwind uwtable sanitize_memory { +define void @MemMove(ptr nocapture %x, ptr nocapture %y) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @MemMove( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i64*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i32*), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = call i8* @__msan_memmove(i8* [[X:%.*]], i8* [[Y:%.*]], i64 10), !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = call ptr @__msan_memmove(ptr [[X:%.*]], ptr [[Y:%.*]], i64 10), !dbg [[DBG1]] ; CHECK-NEXT: ret void ; entry: - call void @llvm.memmove.p0i8.p0i8.i64(i8* %x, i8* %y, i64 10, i1 false), !dbg !10 + call void @llvm.memmove.p0.p0.i64(ptr %x, ptr %y, i64 10, i1 false), !dbg !10 ret void } -declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) nounwind +declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind -declare void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* nocapture writeonly, i8, i64, i32) nounwind -declare void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind -declare void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i32) nounwind +declare void @llvm.memset.element.unordered.atomic.p0.i64(ptr nocapture writeonly, i8, i64, i32) nounwind +declare void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind +declare void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind -define void @atomic_memcpy(i8* nocapture %x, i8* nocapture %y) nounwind { +define void @atomic_memcpy(ptr nocapture %x, ptr nocapture %y) nounwind { ; CHECK-LABEL: @atomic_memcpy( ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] -; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 [[X:%.*]], i8* align 2 [[Y:%.*]], i64 16, i32 1), !dbg [[DBG1]] +; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 [[X:%.*]], ptr align 2 [[Y:%.*]], i64 16, i32 1), !dbg [[DBG1]] ; CHECK-NEXT: ret void ; - call void @llvm.memcpy.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %x, i8* align 2 %y, i64 16, i32 1), !dbg !10 + call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 %x, ptr align 2 %y, i64 16, i32 1), !dbg !10 ret void } -define void @atomic_memmove(i8* nocapture %x, i8* nocapture %y) nounwind { +define void @atomic_memmove(ptr nocapture %x, ptr nocapture %y) nounwind { ; CHECK-LABEL: @atomic_memmove( ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] -; CHECK-NEXT: call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 [[X:%.*]], i8* align 2 [[Y:%.*]], i64 16, i32 1), !dbg [[DBG1]] +; CHECK-NEXT: call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 [[X:%.*]], ptr align 2 [[Y:%.*]], i64 16, i32 1), !dbg [[DBG1]] ; CHECK-NEXT: ret void ; - call void @llvm.memmove.element.unordered.atomic.p0i8.p0i8.i64(i8* align 1 %x, i8* align 2 %y, i64 16, i32 1), !dbg !10 + call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 %x, ptr align 2 %y, i64 16, i32 1), !dbg !10 ret void } -define void @atomic_memset(i8* nocapture %x) nounwind { +define void @atomic_memset(ptr nocapture %x) nounwind { ; CHECK-LABEL: @atomic_memset( ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] -; CHECK-NEXT: call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 [[X:%.*]], i8 88, i64 16, i32 1), !dbg [[DBG1]] +; CHECK-NEXT: call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 [[X:%.*]], i8 88, i64 16, i32 1), !dbg [[DBG1]] ; CHECK-NEXT: ret void ; - call void @llvm.memset.element.unordered.atomic.p0i8.i64(i8* align 1 %x, i8 88, i64 16, i32 1), !dbg !10 + call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 %x, i8 88, i64 16, i32 1), !dbg !10 ret void } @@ -293,12 +290,12 @@ define i32 @Select(i32 %a, i32 %b, i1 %c) nounwind uwtable readnone sanitize_memory { ; CHECK-LABEL: @Select( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i1, i1* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i1*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 16) to i32*), align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* bitcast ([100 x i64]* @__msan_param_tls to i32*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i32*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i32*), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = load i1, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 16) to ptr), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] ; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[C:%.*]], i32 [[TMP2]], i32 [[TMP4]], !dbg [[DBG1]] ; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[A:%.*]], [[B:%.*]], !dbg [[DBG1]] @@ -308,8 +305,8 @@ ; CHECK-NEXT: [[TMP10:%.*]] = select i1 [[C]], i32 [[TMP3]], i32 [[TMP5]], !dbg [[DBG1]] ; CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP0]], i32 [[TMP1]], i32 [[TMP10]], !dbg [[DBG1]] ; CHECK-NEXT: [[COND:%.*]] = select i1 [[C]], i32 [[A]], i32 [[B]], !dbg [[DBG1]] -; CHECK-NEXT: store i32 [[_MSPROP_SELECT]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 -; CHECK-NEXT: store i32 [[TMP11]], i32* @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: store i32 [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i32 [[TMP11]], ptr @__msan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 [[COND]] ; entry: @@ -323,12 +320,12 @@ define <8 x i16> @SelectVector(<8 x i16> %a, <8 x i16> %b, <8 x i1> %c) nounwind uwtable readnone sanitize_memory { ; CHECK-LABEL: @SelectVector( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i1>, <8 x i1>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <8 x i1>*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 32) to i32*), align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <8 x i16>*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 16) to i32*), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i1>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 32) to ptr), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 16) to ptr), align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] ; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[C:%.*]], <8 x i16> [[TMP2]], <8 x i16> [[TMP4]], !dbg [[DBG1]] ; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i16> [[A:%.*]], [[B:%.*]], !dbg [[DBG1]] @@ -342,8 +339,8 @@ ; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP11]], i32 [[TMP3]], i32 [[TMP5]], !dbg [[DBG1]] ; CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP13]], i32 [[TMP1]], i32 [[TMP14]], !dbg [[DBG1]] ; CHECK-NEXT: [[COND:%.*]] = select <8 x i1> [[C]], <8 x i16> [[A]], <8 x i16> [[B]], !dbg [[DBG1]] -; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 -; CHECK-NEXT: store i32 [[TMP15]], i32* @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i32 [[TMP15]], ptr @__msan_retval_origin_tls, align 4 ; CHECK-NEXT: ret <8 x i16> [[COND]] ; entry: @@ -354,20 +351,20 @@ -define i8* @IntToPtr(i64 %x) nounwind uwtable readnone sanitize_memory { +define ptr @IntToPtr(i64 %x) nounwind uwtable readnone sanitize_memory { ; CHECK-LABEL: @IntToPtr( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[X:%.*]] to i8*, !dbg [[DBG1]] -; CHECK-NEXT: store i64 [[TMP0]], i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_retval_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: store i32 [[TMP1]], i32* @__msan_retval_origin_tls, align 4 -; CHECK-NEXT: ret i8* [[TMP2]] +; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[X:%.*]] to ptr, !dbg [[DBG1]] +; CHECK-NEXT: store i64 [[TMP0]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: ret ptr [[TMP2]] ; entry: - %0 = inttoptr i64 %x to i8*, !dbg !10 - ret i8* %0 + %0 = inttoptr i64 %x to ptr, !dbg !10 + ret ptr %0 } @@ -377,15 +374,15 @@ define i32 @Div(i32 %a, i32 %b) nounwind uwtable readnone sanitize_memory { ; CHECK-LABEL: @Div( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i32*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i32*), align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* bitcast ([100 x i64]* @__msan_param_tls to i32*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] ; CHECK-NEXT: call void @__msan_maybe_warning_4(i32 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG1]] ; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[A:%.*]], [[B:%.*]], !dbg [[DBG1]] -; CHECK-NEXT: store i32 [[TMP2]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 -; CHECK-NEXT: store i32 [[TMP3]], i32* @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 [[DIV]] ; entry: @@ -403,29 +400,28 @@ ; CHECK-LABEL: @ShadowLoadAlignmentLarge( ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] ; CHECK-NEXT: [[Y:%.*]] = alloca i32, align 64, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[Y]] to i64, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[Y]] to i64, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to i8*, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to i32*, !dbg [[DBG1]] -; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 64 [[TMP3]], i8 -1, i64 4, i1 false), !dbg [[DBG1]] -; CHECK-NEXT: [[TMP7:%.*]] = bitcast i32* [[Y]] to i8*, !dbg [[DBG1]] -; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(i8* [[TMP7]], i64 4, i8* bitcast (i32* @[[GLOB0:[0-9]+]] to i8*), i8* getelementptr inbounds ([2 x i8], [2 x i8]* @[[GLOB1:[0-9]+]], i32 0, i32 0)), !dbg [[DBG1]] -; CHECK-NEXT: [[TMP8:%.*]] = load volatile i32, i32* [[Y]], align 64, !dbg [[DBG7]] -; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint i32* [[Y]] to i64, !dbg [[DBG7]] +; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr, !dbg [[DBG1]] +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 64 [[TMP3]], i8 -1, i64 4, i1 false), !dbg [[DBG1]] +; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[Y]], i64 4, ptr @[[GLOB0:[0-9]+]], ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG1]] +; CHECK-NEXT: [[TMP8:%.*]] = load volatile i32, ptr [[Y]], align 64, !dbg [[DBG7]] +; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[Y]] to i64, !dbg [[DBG7]] ; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], 87960930222080, !dbg [[DBG7]] -; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to i32*, !dbg [[DBG7]] +; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr, !dbg [[DBG7]] ; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP10]], 17592186044416, !dbg [[DBG7]] -; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to i32*, !dbg [[DBG7]] -; CHECK-NEXT: [[_MSLD:%.*]] = load i32, i32* [[TMP11]], align 64, !dbg [[DBG7]] -; CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 64, !dbg [[DBG7]] -; CHECK-NEXT: store i32 [[_MSLD]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 -; CHECK-NEXT: store i32 [[TMP14]], i32* @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG7]] +; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP11]], align 64, !dbg [[DBG7]] +; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 64, !dbg [[DBG7]] +; CHECK-NEXT: store i32 [[_MSLD]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i32 [[TMP14]], ptr @__msan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 [[TMP8]] ; %y = alloca i32, align 64, !dbg !10 - %1 = load volatile i32, i32* %y, align 64, !dbg !11 + %1 = load volatile i32, ptr %y, align 64, !dbg !11 ret i32 %1 } @@ -433,16 +429,16 @@ define i32 @ExtractElement(<4 x i32> %vec, i32 %idx) sanitize_memory { ; CHECK-LABEL: @ExtractElement( -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i32*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 16) to i32*), align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 16) to ptr), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] ; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <4 x i32> [[TMP3]], i32 [[IDX:%.*]], !dbg [[DBG1]] ; CHECK-NEXT: call void @__msan_maybe_warning_4(i32 zeroext [[TMP1]], i32 zeroext [[TMP2]]), !dbg [[DBG1]] ; CHECK-NEXT: [[X:%.*]] = extractelement <4 x i32> [[VEC:%.*]], i32 [[IDX]], !dbg [[DBG1]] -; CHECK-NEXT: store i32 [[_MSPROP]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 -; CHECK-NEXT: store i32 [[TMP4]], i32* @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: store i32 [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 [[X]] ; %x = extractelement <4 x i32> %vec, i32 %idx, !dbg !10 @@ -452,12 +448,12 @@ define <4 x i32> @InsertElement(<4 x i32> %vec, i32 %idx, i32 %x) sanitize_memory { ; CHECK-LABEL: @InsertElement( -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i32*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 16) to i32*), align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 24) to i32*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 24) to i32*), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 16) to ptr), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 24) to ptr), align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] ; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[TMP5]], i32 [[IDX:%.*]], !dbg [[DBG1]] ; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG1]] @@ -466,8 +462,8 @@ ; CHECK-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 [[TMP2]], i32 [[TMP8]], !dbg [[DBG1]] ; CHECK-NEXT: call void @__msan_maybe_warning_4(i32 zeroext [[TMP1]], i32 zeroext [[TMP2]]), !dbg [[DBG1]] ; CHECK-NEXT: [[VEC1:%.*]] = insertelement <4 x i32> [[VEC:%.*]], i32 [[X:%.*]], i32 [[IDX]], !dbg [[DBG1]] -; CHECK-NEXT: store <4 x i32> [[_MSPROP]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 -; CHECK-NEXT: store i32 [[TMP10]], i32* @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i32 [[TMP10]], ptr @__msan_retval_origin_tls, align 4 ; CHECK-NEXT: ret <4 x i32> [[VEC1]] ; %vec1 = insertelement <4 x i32> %vec, i32 %x, i32 %idx, !dbg !10 @@ -477,18 +473,18 @@ define <4 x i32> @ShuffleVector(<4 x i32> %vec, <4 x i32> %vec1) sanitize_memory { ; CHECK-LABEL: @ShuffleVector( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 16) to i32*), align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 16) to ptr), align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] ; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP3]], <4 x i32> , !dbg [[DBG1]] ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP3]] to i128, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i128 [[TMP5]], 0, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP4]], i32 [[TMP2]], !dbg [[DBG1]] ; CHECK-NEXT: [[VEC2:%.*]] = shufflevector <4 x i32> [[VEC:%.*]], <4 x i32> [[VEC1:%.*]], <4 x i32> , !dbg [[DBG1]] -; CHECK-NEXT: store <4 x i32> [[_MSPROP]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 -; CHECK-NEXT: store i32 [[TMP7]], i32* @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i32 [[TMP7]], ptr @__msan_retval_origin_tls, align 4 ; CHECK-NEXT: ret <4 x i32> [[VEC2]] ; %vec2 = shufflevector <4 x i32> %vec, <4 x i32> %vec1, <4 x i32> , !dbg !10 @@ -497,94 +493,85 @@ -%struct.__va_list_tag = type { i32, i32, i8*, i8* } -declare void @llvm.va_start(i8*) nounwind +%struct.__va_list_tag = type { i32, i32, ptr, ptr } +declare void @llvm.va_start(ptr) nounwind define void @VAStart(i32 %x, ...) sanitize_memory { ; CHECK-LABEL: @VAStart( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @__msan_va_arg_overflow_size_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP1:%.*]] = add i64 176, [[TMP0]], !dbg [[DBG1]] ; CHECK-NEXT: [[TMP2:%.*]] = alloca i8, i64 [[TMP1]], align 1, !dbg [[DBG1]] -; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP2]], i8* align 8 bitcast ([100 x i64]* @__msan_va_arg_tls to i8*), i64 [[TMP1]], i1 false), !dbg [[DBG1]] +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP2]], ptr align 8 @__msan_va_arg_tls, i64 [[TMP1]], i1 false), !dbg [[DBG1]] ; CHECK-NEXT: [[TMP3:%.*]] = alloca i8, i64 [[TMP1]], align 1, !dbg [[DBG1]] -; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP3]], i8* align 8 bitcast ([200 x i32]* @__msan_va_arg_origin_tls to i8*), i64 [[TMP1]], i1 false), !dbg [[DBG1]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* bitcast ([100 x i64]* @__msan_param_tls to i32*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4, !dbg [[DBG1]] +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP3]], ptr align 8 @__msan_va_arg_origin_tls, i64 [[TMP1]], i1 false), !dbg [[DBG1]] +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] ; CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint i32* [[X_ADDR]] to i64, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[X_ADDR]] to i64, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 87960930222080, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to i8*, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP7]], 17592186044416, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP10:%.*]] = and i64 [[TMP9]], -4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to i32*, !dbg [[DBG1]] -; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 4 [[TMP8]], i8 -1, i64 4, i1 false), !dbg [[DBG1]] -; CHECK-NEXT: [[TMP12:%.*]] = bitcast i32* [[X_ADDR]] to i8*, !dbg [[DBG1]] -; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(i8* [[TMP12]], i64 4, i8* bitcast (i32* @[[GLOB2:[0-9]+]] to i8*), i8* getelementptr inbounds ([7 x i8], [7 x i8]* @[[GLOB3:[0-9]+]], i32 0, i32 0)), !dbg [[DBG1]] +; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr, !dbg [[DBG1]] +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[TMP8]], i8 -1, i64 4, i1 false), !dbg [[DBG1]] +; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[X_ADDR]], i64 4, ptr @[[GLOB2:[0-9]+]], ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG1]] ; CHECK-NEXT: [[VA:%.*]] = alloca [1 x %struct.__va_list_tag], align 16, !dbg [[DBG7]] -; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint [1 x %struct.__va_list_tag]* [[VA]] to i64, !dbg [[DBG7]] +; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[VA]] to i64, !dbg [[DBG7]] ; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 87960930222080, !dbg [[DBG7]] -; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to i8*, !dbg [[DBG7]] +; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr, !dbg [[DBG7]] ; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP14]], 17592186044416, !dbg [[DBG7]] ; CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], -4, !dbg [[DBG7]] -; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to i32*, !dbg [[DBG7]] -; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP15]], i8 -1, i64 24, i1 false), !dbg [[DBG7]] -; CHECK-NEXT: [[TMP19:%.*]] = bitcast [1 x %struct.__va_list_tag]* [[VA]] to i8*, !dbg [[DBG7]] -; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(i8* [[TMP19]], i64 24, i8* bitcast (i32* @[[GLOB4:[0-9]+]] to i8*), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @[[GLOB5:[0-9]+]], i32 0, i32 0)), !dbg [[DBG7]] -; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint i32* [[X_ADDR]] to i64, !dbg [[DBG8]] +; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr, !dbg [[DBG7]] +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[TMP15]], i8 -1, i64 24, i1 false), !dbg [[DBG7]] +; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[VA]], i64 24, ptr @[[GLOB4:[0-9]+]], ptr @[[GLOB5:[0-9]+]]), !dbg [[DBG7]] +; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[X_ADDR]] to i64, !dbg [[DBG8]] ; CHECK-NEXT: [[TMP21:%.*]] = xor i64 [[TMP20]], 87960930222080, !dbg [[DBG8]] -; CHECK-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to i32*, !dbg [[DBG8]] +; CHECK-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to ptr, !dbg [[DBG8]] ; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP21]], 17592186044416, !dbg [[DBG8]] -; CHECK-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP23]] to i32*, !dbg [[DBG8]] -; CHECK-NEXT: store i32 [[TMP4]], i32* [[TMP22]], align 4, !dbg [[DBG8]] -; CHECK-NEXT: [[TMP25:%.*]] = bitcast i32* [[X_ADDR]] to i8*, !dbg [[DBG8]] -; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[TMP4]], i8* [[TMP25]], i32 zeroext [[TMP5]]), !dbg [[DBG8]] -; CHECK-NEXT: store i32 [[X:%.*]], i32* [[X_ADDR]], align 4, !dbg [[DBG8]] -; CHECK-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* [[VA]], i32 0, i32 0, !dbg [[DBG9:![0-9]+]] -; CHECK-NEXT: [[ARRAYDECAY1:%.*]] = bitcast %struct.__va_list_tag* [[ARRAYDECAY]] to i8*, !dbg [[DBG10:![0-9]+]] -; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint i8* [[ARRAYDECAY1]] to i64, !dbg [[DBG11:![0-9]+]] +; CHECK-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP23]] to ptr, !dbg [[DBG8]] +; CHECK-NEXT: store i32 [[TMP4]], ptr [[TMP22]], align 4, !dbg [[DBG8]] +; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[TMP4]], ptr [[X_ADDR]], i32 zeroext [[TMP5]]), !dbg [[DBG8]] +; CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4, !dbg [[DBG8]] +; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[VA]] to i64, !dbg [[DBG11:![0-9]+]] ; CHECK-NEXT: [[TMP27:%.*]] = xor i64 [[TMP26]], 87960930222080, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP27]] to i8*, !dbg [[DBG11]] +; CHECK-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP27]] to ptr, !dbg [[DBG11]] ; CHECK-NEXT: [[TMP29:%.*]] = add i64 [[TMP27]], 17592186044416, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP30:%.*]] = inttoptr i64 [[TMP29]] to i32*, !dbg [[DBG11]] -; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 8 [[TMP28]], i8 0, i64 24, i1 false), !dbg [[DBG11]] -; CHECK-NEXT: call void @llvm.va_start(i8* [[ARRAYDECAY1]]), !dbg [[DBG11]] -; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint i8* [[ARRAYDECAY1]] to i64, !dbg [[DBG11]] +; CHECK-NEXT: [[TMP30:%.*]] = inttoptr i64 [[TMP29]] to ptr, !dbg [[DBG11]] +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP28]], i8 0, i64 24, i1 false), !dbg [[DBG11]] +; CHECK-NEXT: call void @llvm.va_start(ptr [[VA]]), !dbg [[DBG11]] +; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint ptr [[VA]] to i64, !dbg [[DBG11]] ; CHECK-NEXT: [[TMP32:%.*]] = add i64 [[TMP31]], 16, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP33:%.*]] = inttoptr i64 [[TMP32]] to i64**, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP34:%.*]] = load i64*, i64** [[TMP33]], align 8, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint i64* [[TMP34]] to i64, !dbg [[DBG11]] +; CHECK-NEXT: [[TMP33:%.*]] = inttoptr i64 [[TMP32]] to ptr, !dbg [[DBG11]] +; CHECK-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8, !dbg [[DBG11]] +; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr [[TMP34]] to i64, !dbg [[DBG11]] ; CHECK-NEXT: [[TMP36:%.*]] = xor i64 [[TMP35]], 87960930222080, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP37:%.*]] = inttoptr i64 [[TMP36]] to i8*, !dbg [[DBG11]] +; CHECK-NEXT: [[TMP37:%.*]] = inttoptr i64 [[TMP36]] to ptr, !dbg [[DBG11]] ; CHECK-NEXT: [[TMP38:%.*]] = add i64 [[TMP36]], 17592186044416, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP39:%.*]] = inttoptr i64 [[TMP38]] to i32*, !dbg [[DBG11]] -; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP37]], i8* align 16 [[TMP2]], i64 176, i1 false), !dbg [[DBG11]] -; CHECK-NEXT: [[TMP40:%.*]] = bitcast i32* [[TMP39]] to i8*, !dbg [[DBG11]] -; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP40]], i8* align 16 [[TMP3]], i64 176, i1 false), !dbg [[DBG11]] -; CHECK-NEXT: [[TMP41:%.*]] = ptrtoint i8* [[ARRAYDECAY1]] to i64, !dbg [[DBG11]] +; CHECK-NEXT: [[TMP39:%.*]] = inttoptr i64 [[TMP38]] to ptr, !dbg [[DBG11]] +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP37]], ptr align 16 [[TMP2]], i64 176, i1 false), !dbg [[DBG11]] +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP39]], ptr align 16 [[TMP3]], i64 176, i1 false), !dbg [[DBG11]] +; CHECK-NEXT: [[TMP41:%.*]] = ptrtoint ptr [[VA]] to i64, !dbg [[DBG11]] ; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP41]], 8, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP43:%.*]] = inttoptr i64 [[TMP42]] to i64**, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP44:%.*]] = load i64*, i64** [[TMP43]], align 8, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint i64* [[TMP44]] to i64, !dbg [[DBG11]] +; CHECK-NEXT: [[TMP43:%.*]] = inttoptr i64 [[TMP42]] to ptr, !dbg [[DBG11]] +; CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[TMP43]], align 8, !dbg [[DBG11]] +; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64, !dbg [[DBG11]] ; CHECK-NEXT: [[TMP46:%.*]] = xor i64 [[TMP45]], 87960930222080, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP47:%.*]] = inttoptr i64 [[TMP46]] to i8*, !dbg [[DBG11]] +; CHECK-NEXT: [[TMP47:%.*]] = inttoptr i64 [[TMP46]] to ptr, !dbg [[DBG11]] ; CHECK-NEXT: [[TMP48:%.*]] = add i64 [[TMP46]], 17592186044416, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP49:%.*]] = inttoptr i64 [[TMP48]] to i32*, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i8, i8* [[TMP2]], i32 176, !dbg [[DBG11]] -; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP47]], i8* align 16 [[TMP50]], i64 [[TMP0]], i1 false), !dbg [[DBG11]] -; CHECK-NEXT: [[TMP51:%.*]] = getelementptr i8, i8* [[TMP3]], i32 176, !dbg [[DBG11]] -; CHECK-NEXT: [[TMP52:%.*]] = bitcast i32* [[TMP49]] to i8*, !dbg [[DBG11]] -; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP52]], i8* align 16 [[TMP51]], i64 [[TMP0]], i1 false), !dbg [[DBG11]] +; CHECK-NEXT: [[TMP49:%.*]] = inttoptr i64 [[TMP48]] to ptr, !dbg [[DBG11]] +; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr [[TMP2]], i32 176, !dbg [[DBG11]] +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP47]], ptr align 16 [[TMP50]], i64 [[TMP0]], i1 false), !dbg [[DBG11]] +; CHECK-NEXT: [[TMP51:%.*]] = getelementptr i8, ptr [[TMP3]], i32 176, !dbg [[DBG11]] +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP49]], ptr align 16 [[TMP51]], i64 [[TMP0]], i1 false), !dbg [[DBG11]] ; CHECK-NEXT: ret void ; entry: %x.addr = alloca i32, align 4, !dbg !10 %va = alloca [1 x %struct.__va_list_tag], align 16, !dbg !11 - store i32 %x, i32* %x.addr, align 4, !dbg !12 - %arraydecay = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %va, i32 0, i32 0, !dbg !13 - %arraydecay1 = bitcast %struct.__va_list_tag* %arraydecay to i8*, !dbg !14 - call void @llvm.va_start(i8* %arraydecay1), !dbg !15 + store i32 %x, ptr %x.addr, align 4, !dbg !12 + call void @llvm.va_start(ptr %va), !dbg !15 ret void } @@ -604,8 +591,8 @@ ; CHECK-NEXT: tail call void @bar(), !dbg [[DBG8]] ; CHECK-NEXT: br label [[IF_END]] ; CHECK: if.end: -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 -; CHECK-NEXT: store i32 0, i32* @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 [[X]] ; entry: @@ -628,29 +615,29 @@ ; CHECK-NEXT: entry: ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] ; CHECK-NEXT: [[P:%.*]] = alloca i32, align 4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i32* [[P]] to i64, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[P]] to i64, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to i8*, !dbg [[DBG1]] +; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP1]], 17592186044416, !dbg [[DBG1]] ; CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], -4, !dbg [[DBG1]] -; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32*, !dbg [[DBG1]] -; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 4 [[TMP2]], i8 0, i64 4, i1 false), !dbg [[DBG1]] -; CHECK-NEXT: store i64 0, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8, !dbg [[DBG7]] -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8, !dbg [[DBG7]] -; CHECK-NEXT: [[X:%.*]] = call i32 @NoSanitizeMemoryAllocaHelper(i32* [[P]]), !dbg [[DBG7]] -; CHECK-NEXT: [[_MSRET:%.*]] = load i32, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 -; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* @__msan_retval_origin_tls, align 4 -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 -; CHECK-NEXT: store i32 0, i32* @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr, !dbg [[DBG1]] +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[TMP2]], i8 0, i64 4, i1 false), !dbg [[DBG1]] +; CHECK-NEXT: store i64 0, ptr @__msan_param_tls, align 8, !dbg [[DBG7]] +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8, !dbg [[DBG7]] +; CHECK-NEXT: [[X:%.*]] = call i32 @NoSanitizeMemoryAllocaHelper(ptr [[P]]), !dbg [[DBG7]] +; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 [[X]] ; entry: %p = alloca i32, align 4, !dbg !10 - %x = call i32 @NoSanitizeMemoryAllocaHelper(i32* %p), !dbg !11 + %x = call i32 @NoSanitizeMemoryAllocaHelper(ptr %p), !dbg !11 ret i32 %x } -declare i32 @NoSanitizeMemoryAllocaHelper(i32* %p) +declare i32 @NoSanitizeMemoryAllocaHelper(ptr %p) @@ -659,13 +646,13 @@ ; CHECK-LABEL: @NoSanitizeMemoryUndef( ; CHECK-NEXT: entry: ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_param_tls to i32*), align 8, !dbg [[DBG1]] -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8, !dbg [[DBG1]] +; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8, !dbg [[DBG1]] ; CHECK-NEXT: [[X:%.*]] = call i32 @NoSanitizeMemoryUndefHelper(i32 undef), !dbg [[DBG1]] -; CHECK-NEXT: [[_MSRET:%.*]] = load i32, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @__msan_retval_origin_tls, align 4 -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 -; CHECK-NEXT: store i32 0, i32* @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 [[X]] ; entry: @@ -675,9 +662,9 @@ declare i32 @NoSanitizeMemoryUndefHelper(i32 %x) -declare void @llvm.lifetime.start.p0i8(i64 immarg %0, i8* nocapture %1) -declare void @llvm.lifetime.end.p0i8(i64 immarg %0, i8* nocapture %1) -declare void @foo8(i8* nocapture) +declare void @llvm.lifetime.start.p0(i64 immarg %0, ptr nocapture %1) +declare void @llvm.lifetime.end.p0(i64 immarg %0, ptr nocapture %1) +declare void @foo8(ptr nocapture) define void @msan() sanitize_memory { @@ -685,24 +672,24 @@ ; CHECK-NEXT: entry: ; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] ; CHECK-NEXT: [[TEXT:%.*]] = alloca i8, align 1, !dbg [[DBG1]] -; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 1, i8* [[TEXT]]), !dbg [[DBG7]] -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i8* [[TEXT]] to i64, !dbg [[DBG7]] +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TEXT]]), !dbg [[DBG7]] +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[TEXT]] to i64, !dbg [[DBG7]] ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080, !dbg [[DBG7]] -; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to i8*, !dbg [[DBG7]] +; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr, !dbg [[DBG7]] ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP1]], 17592186044416, !dbg [[DBG7]] ; CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], -4, !dbg [[DBG7]] -; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32*, !dbg [[DBG7]] -; CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* align 1 [[TMP2]], i8 -1, i64 1, i1 false), !dbg [[DBG7]] -; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(i8* [[TEXT]], i64 1, i8* bitcast (i32* @[[GLOB6:[0-9]+]] to i8*), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @[[GLOB7:[0-9]+]], i32 0, i32 0)), !dbg [[DBG7]] -; CHECK-NEXT: store i64 0, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8, !dbg [[DBG8]] -; CHECK-NEXT: call void @foo8(i8* [[TEXT]]), !dbg [[DBG8]] -; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 1, i8* [[TEXT]]), !dbg [[DBG9]] -; CHECK-NEXT: ret void, !dbg [[DBG10]] +; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr, !dbg [[DBG7]] +; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP2]], i8 -1, i64 1, i1 false), !dbg [[DBG7]] +; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[TEXT]], i64 1, ptr @[[GLOB6:[0-9]+]], ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG7]] +; CHECK-NEXT: store i64 0, ptr @__msan_param_tls, align 8, !dbg [[DBG8]] +; CHECK-NEXT: call void @foo8(ptr [[TEXT]]), !dbg [[DBG8]] +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TEXT]]), !dbg +; CHECK-NEXT: ret void, !dbg ; entry: %text = alloca i8, align 1, !dbg !10 - call void @llvm.lifetime.start.p0i8(i64 1, i8* %text), !dbg !11 - call void @foo8(i8* %text), !dbg !12 - call void @llvm.lifetime.end.p0i8(i64 1, i8* %text), !dbg !13 + call void @llvm.lifetime.start.p0(i64 1, ptr %text), !dbg !11 + call void @foo8(ptr %text), !dbg !12 + call void @llvm.lifetime.end.p0(i64 1, ptr %text), !dbg !13 ret void, !dbg !14 } diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_eager.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_eager.ll --- a/llvm/test/Instrumentation/MemorySanitizer/msan_eager.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_eager.ll @@ -18,8 +18,8 @@ define i32 @PartialRet() nounwind uwtable sanitize_memory { ; CHECK-LABEL: @PartialRet( ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 -; CHECK-NEXT: store i32 0, i32* @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4 ; CHECK-NEXT: ret i32 123 ; ret i32 123 @@ -28,15 +28,15 @@ define noundef i32 @LoadedRet() nounwind uwtable sanitize_memory { ; CHECK-LABEL: @LoadedRet( ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to i32* -; CHECK-NEXT: [[O:%.*]] = load i32, i32* [[P]], align 4 -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[P]] to i64 +; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to ptr +; CHECK-NEXT: [[O:%.*]] = load i32, ptr [[P]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080 -; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to i32* +; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416 -; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32* -; CHECK-NEXT: [[_MSLD:%.*]] = load i32, i32* [[TMP3]], align 4 -; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP3]], align 4 +; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[_MSLD]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF0:![0-9]+]] ; CHECK: 7: @@ -45,8 +45,8 @@ ; CHECK: 8: ; CHECK-NEXT: ret i32 [[O]] ; - %p = inttoptr i64 0 to i32 * - %o = load i32, i32 *%p + %p = inttoptr i64 0 to ptr + %o = load i32, ptr %p ret i32 %o } @@ -54,70 +54,70 @@ define void @NormalArg(i32 noundef %a) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @NormalArg( ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to i32* -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[P]] to i64 +; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to ptr +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080 -; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to i32* +; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416 -; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32* -; CHECK-NEXT: store i32 0, i32* [[TMP3]], align 4 -; CHECK-NEXT: store i32 [[A:%.*]], i32* [[P]], align 4 +; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr +; CHECK-NEXT: store i32 0, ptr [[TMP3]], align 4 +; CHECK-NEXT: store i32 [[A:%.*]], ptr [[P]], align 4 ; CHECK-NEXT: ret void ; - %p = inttoptr i64 0 to i32 * - store i32 %a, i32 *%p + %p = inttoptr i64 0 to ptr + store i32 %a, ptr %p ret void } define void @NormalArgAfterNoUndef(i32 noundef %a, i32 %b) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @NormalArgAfterNoUndef( -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i32*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* inttoptr (i64 add (i64 ptrtoint ([200 x i32]* @__msan_param_origin_tls to i64), i64 8) to i32*), align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to i32* -; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint i32* [[P]] to i64 +; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to ptr +; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080 -; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32* +; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr ; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i32* -; CHECK-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: store i32 [[TMP2]], i32* [[TMP7]], align 4 +; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4 ; CHECK-NEXT: br label [[TMP9]] ; CHECK: 9: -; CHECK-NEXT: store i32 [[B:%.*]], i32* [[P]], align 4 +; CHECK-NEXT: store i32 [[B:%.*]], ptr [[P]], align 4 ; CHECK-NEXT: ret void ; - %p = inttoptr i64 0 to i32 * - store i32 %b, i32 *%p + %p = inttoptr i64 0 to ptr + store i32 %b, ptr %p ret void } define void @PartialArg(i32 %a) nounwind uwtable sanitize_memory { ; CHECK-LABEL: @PartialArg( -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* bitcast ([100 x i64]* @__msan_param_tls to i32*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to i32* -; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint i32* [[P]] to i64 +; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to ptr +; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080 -; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32* +; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr ; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to i32* -; CHECK-NEXT: store i32 [[TMP1]], i32* [[TMP5]], align 4 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] ; CHECK: 8: -; CHECK-NEXT: store i32 [[TMP2]], i32* [[TMP7]], align 4 +; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4 ; CHECK-NEXT: br label [[TMP9]] ; CHECK: 9: -; CHECK-NEXT: store i32 [[A:%.*]], i32* [[P]], align 4 +; CHECK-NEXT: store i32 [[A:%.*]], ptr [[P]], align 4 ; CHECK-NEXT: ret void ; - %p = inttoptr i64 0 to i32 * - store i32 %a, i32 *%p + %p = inttoptr i64 0 to ptr + store i32 %a, ptr %p ret void } @@ -137,7 +137,7 @@ ; CHECK-LABEL: @CallNormalArgAfterNoUndef( ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[R:%.*]] = call i32 @NormalRet() #[[ATTR0]] -; CHECK-NEXT: store i32 0, i32* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to i32*), align 8 +; CHECK-NEXT: store i32 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @NormalArgAfterNoUndef(i32 [[R]], i32 [[R]]) #[[ATTR0]] ; CHECK-NEXT: ret void ; @@ -149,15 +149,15 @@ define void @CallWithLoaded() nounwind uwtable sanitize_memory { ; CHECK-LABEL: @CallWithLoaded( ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to i32* -; CHECK-NEXT: [[O:%.*]] = load i32, i32* [[P]], align 4 -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i32* [[P]] to i64 +; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to ptr +; CHECK-NEXT: [[O:%.*]] = load i32, ptr [[P]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080 -; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to i32* +; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416 -; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to i32* -; CHECK-NEXT: [[_MSLD:%.*]] = load i32, i32* [[TMP3]], align 4 -; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 +; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP3]], align 4 +; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[_MSLD]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF0]] ; CHECK: 7: @@ -167,8 +167,8 @@ ; CHECK-NEXT: call void @NormalArg(i32 [[O]]) #[[ATTR0]] ; CHECK-NEXT: ret void ; - %p = inttoptr i64 0 to i32 * - %o = load i32, i32 *%p + %p = inttoptr i64 0 to ptr + %o = load i32, ptr %p call void @NormalArg(i32 %o) nounwind uwtable sanitize_memory ret void } @@ -176,12 +176,12 @@ define void @CallPartial() nounwind uwtable sanitize_memory { ; CHECK-LABEL: @CallPartial( ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: [[R:%.*]] = call i32 @PartialRet() #[[ATTR0]] -; CHECK-NEXT: [[_MSRET:%.*]] = load i32, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @__msan_retval_origin_tls, align 4 -; CHECK-NEXT: store i32 [[_MSRET]], i32* bitcast ([100 x i64]* @__msan_param_tls to i32*), align 8 -; CHECK-NEXT: store i32 [[TMP1]], i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4 +; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 4 +; CHECK-NEXT: store i32 [[_MSRET]], ptr @__msan_param_tls, align 8 +; CHECK-NEXT: store i32 [[TMP1]], ptr @__msan_param_origin_tls, align 4 ; CHECK-NEXT: call void @PartialArg(i32 [[R]]) #[[ATTR0]] ; CHECK-NEXT: ret void ; diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_kernel_basic.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_kernel_basic.ll --- a/llvm/test/Instrumentation/MemorySanitizer/msan_kernel_basic.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_kernel_basic.ll @@ -31,9 +31,9 @@ ; Check instrumentation of stores -define void @Store1(i8* nocapture %p, i8 %x) nounwind uwtable sanitize_memory { +define void @Store1(ptr nocapture %p, i8 %x) nounwind uwtable sanitize_memory { entry: - store i8 %x, i8* %p + store i8 %x, ptr %p ret void } @@ -43,13 +43,13 @@ ; CHECK: [[PARAM_SHADOW:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 0 ; CHECK: [[BASE:%[0-9]+]] = ptrtoint {{.*}} [[PARAM_SHADOW]] ; CHECK: [[SHADOW_PTR:%[a-z0-9_]+]] = inttoptr {{.*}} [[BASE]] -; CHECK: [[SHADOW:%[a-z0-9]+]] = load i64, i64* [[SHADOW_PTR]] +; CHECK: [[SHADOW:%[a-z0-9]+]] = load i64, ptr [[SHADOW_PTR]] ; CHECK: [[BASE2:%[0-9]+]] = ptrtoint {{.*}} [[PARAM_SHADOW]] ; Load the shadow of %p and check it ; CHECK: icmp ne i64 [[SHADOW]] ; CHECK: br i1 ; CHECK: {{^[0-9]+}}: -; CHECK: @__msan_metadata_ptr_for_store_1(i8* %p) +; CHECK: @__msan_metadata_ptr_for_store_1(ptr %p) ; CHECK: store i8 ; If the new shadow is non-zero, jump to __msan_chain_origin() ; CHECK: icmp @@ -63,9 +63,9 @@ ; CHECK: store i8 ; CHECK: ret void -define void @Store2(i16* nocapture %p, i16 %x) nounwind uwtable sanitize_memory { +define void @Store2(ptr nocapture %p, i16 %x) nounwind uwtable sanitize_memory { entry: - store i16 %x, i16* %p + store i16 %x, ptr %p ret void } @@ -79,8 +79,7 @@ ; CHECK: icmp ; CHECK: br i1 ; CHECK: {{^[0-9]+}}: -; CHECK: [[REG:%[0-9]+]] = bitcast i16* %p to i8* -; CHECK: @__msan_metadata_ptr_for_store_2(i8* [[REG]]) +; CHECK: @__msan_metadata_ptr_for_store_2(ptr %p) ; CHECK: store i16 ; If the new shadow is non-zero, jump to __msan_chain_origin() ; CHECK: icmp @@ -95,9 +94,9 @@ ; CHECK: ret void -define void @Store4(i32* nocapture %p, i32 %x) nounwind uwtable sanitize_memory { +define void @Store4(ptr nocapture %p, i32 %x) nounwind uwtable sanitize_memory { entry: - store i32 %x, i32* %p + store i32 %x, ptr %p ret void } @@ -111,8 +110,7 @@ ; CHECK: icmp ; CHECK: br i1 ; CHECK: {{^[0-9]+}}: -; CHECK: [[REG:%[0-9]+]] = bitcast i32* %p to i8* -; CHECK: @__msan_metadata_ptr_for_store_4(i8* [[REG]]) +; CHECK: @__msan_metadata_ptr_for_store_4(ptr %p) ; CHECK: store i32 ; If the new shadow is non-zero, jump to __msan_chain_origin() ; CHECK: icmp @@ -126,9 +124,9 @@ ; CHECK: store i32 ; CHECK: ret void -define void @Store8(i64* nocapture %p, i64 %x) nounwind uwtable sanitize_memory { +define void @Store8(ptr nocapture %p, i64 %x) nounwind uwtable sanitize_memory { entry: - store i64 %x, i64* %p + store i64 %x, ptr %p ret void } @@ -142,8 +140,7 @@ ; CHECK: icmp ; CHECK: br i1 ; CHECK: {{^[0-9]+}}: -; CHECK: [[REG:%[0-9]+]] = bitcast i64* %p to i8* -; CHECK: @__msan_metadata_ptr_for_store_8(i8* [[REG]]) +; CHECK: @__msan_metadata_ptr_for_store_8(ptr %p) ; CHECK: store i64 ; If the new shadow is non-zero, jump to __msan_chain_origin() ; CHECK: icmp @@ -157,9 +154,9 @@ ; CHECK: store i64 ; CHECK: ret void -define void @Store16(i128* nocapture %p, i128 %x) nounwind uwtable sanitize_memory { +define void @Store16(ptr nocapture %p, i128 %x) nounwind uwtable sanitize_memory { entry: - store i128 %x, i128* %p + store i128 %x, ptr %p ret void } @@ -173,8 +170,7 @@ ; CHECK: icmp ; CHECK: br i1 ; CHECK: {{^[0-9]+}}: -; CHECK: [[REG:%[0-9]+]] = bitcast i128* %p to i8* -; CHECK: @__msan_metadata_ptr_for_store_n(i8* [[REG]], i64 16) +; CHECK: @__msan_metadata_ptr_for_store_n(ptr %p, i64 16) ; CHECK: store i128 ; If the new shadow is non-zero, jump to __msan_chain_origin() ; CHECK: icmp @@ -191,9 +187,9 @@ ; Check instrumentation of loads -define i8 @Load1(i8* nocapture %p) nounwind uwtable sanitize_memory { +define i8 @Load1(ptr nocapture %p) nounwind uwtable sanitize_memory { entry: - %0 = load i8, i8* %p + %0 = load i8, ptr %p ret i8 %0 } @@ -210,15 +206,15 @@ ; Load the value from %p. This is done before accessing the shadow ; to ease atomic handling. ; CHECK: load i8 -; CHECK: @__msan_metadata_ptr_for_load_1(i8* %p) +; CHECK: @__msan_metadata_ptr_for_load_1(ptr %p) ; Load the shadow and origin. ; CHECK: load i8 ; CHECK: load i32 -define i16 @Load2(i16* nocapture %p) nounwind uwtable sanitize_memory { +define i16 @Load2(ptr nocapture %p) nounwind uwtable sanitize_memory { entry: - %0 = load i16, i16* %p + %0 = load i16, ptr %p ret i16 %0 } @@ -235,16 +231,15 @@ ; Load the value from %p. This is done before accessing the shadow ; to ease atomic handling. ; CHECK: load i16 -; CHECK: [[REG:%[0-9]+]] = bitcast i16* %p to i8* -; CHECK: @__msan_metadata_ptr_for_load_2(i8* [[REG]]) +; CHECK: @__msan_metadata_ptr_for_load_2(ptr %p) ; Load the shadow and origin. ; CHECK: load i16 ; CHECK: load i32 -define i32 @Load4(i32* nocapture %p) nounwind uwtable sanitize_memory { +define i32 @Load4(ptr nocapture %p) nounwind uwtable sanitize_memory { entry: - %0 = load i32, i32* %p + %0 = load i32, ptr %p ret i32 %0 } @@ -261,15 +256,14 @@ ; Load the value from %p. This is done before accessing the shadow ; to ease atomic handling. ; CHECK: load i32 -; CHECK: [[REG:%[0-9]+]] = bitcast i32* %p to i8* -; CHECK: @__msan_metadata_ptr_for_load_4(i8* [[REG]]) +; CHECK: @__msan_metadata_ptr_for_load_4(ptr %p) ; Load the shadow and origin. ; CHECK: load i32 ; CHECK: load i32 -define i64 @Load8(i64* nocapture %p) nounwind uwtable sanitize_memory { +define i64 @Load8(ptr nocapture %p) nounwind uwtable sanitize_memory { entry: - %0 = load i64, i64* %p + %0 = load i64, ptr %p ret i64 %0 } @@ -286,15 +280,14 @@ ; Load the value from %p. This is done before accessing the shadow ; to ease atomic handling. ; CHECK: load i64 -; CHECK: [[REG:%[0-9]+]] = bitcast i64* %p to i8* -; CHECK: @__msan_metadata_ptr_for_load_8(i8* [[REG]]) +; CHECK: @__msan_metadata_ptr_for_load_8(ptr %p) ; Load the shadow and origin. ; CHECK: load i64 ; CHECK: load i32 -define i128 @Load16(i128* nocapture %p) nounwind uwtable sanitize_memory { +define i128 @Load16(ptr nocapture %p) nounwind uwtable sanitize_memory { entry: - %0 = load i128, i128* %p + %0 = load i128, ptr %p ret i128 %0 } @@ -311,8 +304,7 @@ ; Load the value from %p. This is done before accessing the shadow ; to ease atomic handling. ; CHECK: load i128 -; CHECK: [[REG:%[0-9]+]] = bitcast i128* %p to i8* -; CHECK: @__msan_metadata_ptr_for_load_n(i8* [[REG]], i64 16) +; CHECK: @__msan_metadata_ptr_for_load_n(ptr %p, i64 16) ; Load the shadow and origin. ; CHECK: load i128 ; CHECK: load i32 @@ -320,21 +312,19 @@ ; Test kernel-specific va_list instrumentation -%struct.__va_list_tag = type { i32, i32, i8*, i8* } -declare void @llvm.va_start(i8*) nounwind -declare void @llvm.va_end(i8*) +%struct.__va_list_tag = type { i32, i32, ptr, ptr } +declare void @llvm.va_start(ptr) nounwind +declare void @llvm.va_end(ptr) @.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1 -declare dso_local i32 @VAListFn(i8*, %struct.__va_list_tag*) local_unnamed_addr +declare dso_local i32 @VAListFn(ptr, ptr) local_unnamed_addr ; Function Attrs: nounwind uwtable -define dso_local i32 @VarArgFn(i8* %fmt, ...) local_unnamed_addr sanitize_memory #0 { +define dso_local i32 @VarArgFn(ptr %fmt, ...) local_unnamed_addr sanitize_memory #0 { entry: %args = alloca [1 x %struct.__va_list_tag], align 16 - %0 = bitcast [1 x %struct.__va_list_tag]* %args to i8* - %arraydecay = getelementptr inbounds [1 x %struct.__va_list_tag], [1 x %struct.__va_list_tag]* %args, i64 0, i64 0 - call void @llvm.va_start(i8* nonnull %0) - %call = call i32 @VAListFn(i8* %fmt, %struct.__va_list_tag* nonnull %arraydecay) - call void @llvm.va_end(i8* nonnull %0) + call void @llvm.va_start(ptr nonnull %args) + %call = call i32 @VAListFn(ptr %fmt, ptr nonnull %args) + call void @llvm.va_end(ptr nonnull %args) ret i32 %call } @@ -347,21 +337,19 @@ ; CHECK: [[VA_ARG_ORIGIN:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 3 ; CHECK: [[VA_ARG_OVERFLOW_SIZE:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 4 -; CHECK: [[OSIZE:%[0-9]+]] = load i64, i64* [[VA_ARG_OVERFLOW_SIZE]] +; CHECK: [[OSIZE:%[0-9]+]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]] ; Register save area is 48 bytes for non-SSE builds. ; CHECK: [[SIZE:%[0-9]+]] = add i64 48, [[OSIZE]] ; CHECK: [[SHADOWS:%[0-9]+]] = alloca i8, i64 [[SIZE]] -; CHECK: [[VA_ARG_SHADOW]] -; CHECK: call void @llvm.memcpy{{.*}}(i8* align 8 [[SHADOWS]], {{.*}}, i64 [[SIZE]] +; CHECK: call void @llvm.memcpy{{.*}}(ptr align 8 [[SHADOWS]], ptr align 8 [[VA_ARG_SHADOW]], i64 [[SIZE]] ; CHECK: [[ORIGINS:%[0-9]+]] = alloca i8, i64 [[SIZE]] -; CHECK: [[VA_ARG_ORIGIN]] -; CHECK: call void @llvm.memcpy{{.*}}(i8* align 8 [[ORIGINS]], {{.*}}, i64 [[SIZE]] +; CHECK: call void @llvm.memcpy{{.*}}(ptr align 8 [[ORIGINS]], ptr align 8 [[VA_ARG_ORIGIN]], i64 [[SIZE]] ; CHECK: call i32 @VAListFn ; Function Attrs: nounwind uwtable define dso_local void @VarArgCaller() local_unnamed_addr sanitize_memory { entry: - %call = tail call i32 (i8*, ...) @VarArgFn(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 123) + %call = tail call i32 (ptr, ...) @VarArgFn(ptr @.str, i32 123) ret void } @@ -374,19 +362,19 @@ ; CHECK: [[VA_ARG_OVERFLOW_SIZE:%[a-z0-9_]+]] = getelementptr {{.*}} i32 0, i32 4 ; CHECK: [[PARAM_SI:%[_a-z0-9]+]] = ptrtoint {{.*}} [[PARAM_SHADOW]] -; CHECK: [[ARG1_S:%[_a-z0-9]+]] = inttoptr i64 [[PARAM_SI]] to i64* +; CHECK: [[ARG1_S:%[_a-z0-9]+]] = inttoptr i64 [[PARAM_SI]] to ptr ; First argument is initialized -; CHECK: store i64 0, i64* [[ARG1_S]] +; CHECK: store i64 0, ptr [[ARG1_S]] ; Dangling cast of va_arg_shadow[0], unused because the first argument is fixed. ; CHECK: [[VA_CAST0:%[_a-z0-9]+]] = ptrtoint {{.*}} [[VA_ARG_SHADOW]] to i64 ; CHECK: [[VA_CAST1:%[_a-z0-9]+]] = ptrtoint {{.*}} [[VA_ARG_SHADOW]] to i64 ; CHECK: [[ARG1_SI:%[_a-z0-9]+]] = add i64 [[VA_CAST1]], 8 -; CHECK: [[PARG1_S:%[_a-z0-9]+]] = inttoptr i64 [[ARG1_SI]] to i32* +; CHECK: [[PARG1_S:%[_a-z0-9]+]] = inttoptr i64 [[ARG1_SI]] to ptr ; Shadow for 123 is 0. -; CHECK: store i32 0, i32* [[ARG1_S]] +; CHECK: store i32 0, ptr [[ARG1_S]] -; CHECK: store i64 0, i64* [[VA_ARG_OVERFLOW_SIZE]] -; CHECK: call i32 (i8*, ...) @VarArgFn({{.*}} @.str{{.*}} i32 123) +; CHECK: store i64 0, ptr [[VA_ARG_OVERFLOW_SIZE]] +; CHECK: call i32 (ptr, ...) @VarArgFn({{.*}} @.str{{.*}} i32 123) diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_launder_invariant.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_launder_invariant.ll --- a/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_launder_invariant.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_launder_invariant.ll @@ -6,33 +6,31 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -%class.Foo = type { i32 (...)** } +%class.Foo = type { ptr } @flag = dso_local local_unnamed_addr global i8 0, align 1 -define dso_local %class.Foo* @_Z1fv() local_unnamed_addr #0 { +define dso_local ptr @_Z1fv() local_unnamed_addr #0 { entry: - %p = alloca i8*, align 8 - %0 = bitcast i8** %p to i8* - call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0) - %1 = load i8, i8* @flag, align 1 - %tobool = icmp ne i8 %1, 0 - %call = call zeroext i1 @_Z2f1PPvb(i8** nonnull %p, i1 zeroext %tobool) - %2 = load i8*, i8** %p, align 8 - %3 = call i8* @llvm.launder.invariant.group.p0i8(i8* %2) - %4 = bitcast i8* %3 to %class.Foo* - %retval.0 = select i1 %call, %class.Foo* %4, %class.Foo* null - call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0) - ret %class.Foo* %retval.0 + %p = alloca ptr, align 8 + call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %p) + %0 = load i8, ptr @flag, align 1 + %tobool = icmp ne i8 %0, 0 + %call = call zeroext i1 @_Z2f1PPvb(ptr nonnull %p, i1 zeroext %tobool) + %1 = load ptr, ptr %p, align 8 + %2 = call ptr @llvm.launder.invariant.group.p0(ptr %1) + %retval.0 = select i1 %call, ptr %2, ptr null + call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %p) + ret ptr %retval.0 } ; CHECK-NOT: call void @__msan_warning_with_origin_noreturn -declare dso_local zeroext i1 @_Z2f1PPvb(i8**, i1 zeroext) local_unnamed_addr +declare dso_local zeroext i1 @_Z2f1PPvb(ptr, i1 zeroext) local_unnamed_addr -declare i8* @llvm.launder.invariant.group.p0i8(i8*) +declare ptr @llvm.launder.invariant.group.p0(ptr) -declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) -declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) attributes #0 = { sanitize_memory uwtable } diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_strip_invariant.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_strip_invariant.ll --- a/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_strip_invariant.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_llvm_strip_invariant.ll @@ -8,14 +8,14 @@ @flag = dso_local local_unnamed_addr global i8 0, align 1 -define dso_local i8* @f(i8* %x) local_unnamed_addr #0 { +define dso_local ptr @f(ptr %x) local_unnamed_addr #0 { entry: - %0 = call i8* @llvm.strip.invariant.group.p0i8(i8* %x) - ret i8* %0 + %0 = call ptr @llvm.strip.invariant.group.p0(ptr %x) + ret ptr %0 } ; CHECK-NOT: call void @__msan_warning_with_origin_noreturn -declare i8* @llvm.strip.invariant.group.p0i8(i8*) +declare ptr @llvm.strip.invariant.group.p0(ptr) attributes #0 = { sanitize_memory uwtable } diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_x86_bts_asm.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_x86_bts_asm.ll --- a/llvm/test/Instrumentation/MemorySanitizer/msan_x86_bts_asm.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_x86_bts_asm.ll @@ -38,14 +38,14 @@ %bit = alloca i8, align 1 %value = alloca i64, align 8 %nr = alloca i64, align 8 - %addr = alloca i64*, align 8 - store i32 0, i32* %retval, align 4 - store i64 2, i64* %value, align 8 - store i64 0, i64* %nr, align 8 - store i64* %value, i64** %addr, align 8 - %0 = load i64, i64* %nr, align 8 - call void asm "btsq $2, $1; setc $0", "=*qm,=*m,Ir,~{dirflag},~{fpsr},~{flags}"(i8* elementtype(i8) %bit, i64** elementtype(i64*) %addr, i64 %0) - %1 = load i8, i8* %bit, align 1 + %addr = alloca ptr, align 8 + store i32 0, ptr %retval, align 4 + store i64 2, ptr %value, align 8 + store i64 0, ptr %nr, align 8 + store ptr %value, ptr %addr, align 8 + %0 = load i64, ptr %nr, align 8 + call void asm "btsq $2, $1; setc $0", "=*qm,=*m,Ir,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i8) %bit, ptr elementtype(ptr) %addr, i64 %0) + %1 = load i8, ptr %bit, align 1 %tobool = trunc i8 %1 to i1 br i1 %tobool, label %if.then, label %if.else @@ -57,20 +57,16 @@ } ; %nr is first poisoned, then unpoisoned (written to). Need to optimize this in the future. -; CHECK: [[NRC1:%.*]] = bitcast i64* %nr to i8* -; CHECK: call void @__msan_poison_alloca(i8* [[NRC1]]{{.*}}) -; CHECK: [[NRC2:%.*]] = bitcast i64* %nr to i8* -; CHECK: call { i8*, i32* } @__msan_metadata_ptr_for_store_8(i8* [[NRC2]]) +; CHECK: call void @__msan_poison_alloca(ptr %nr{{.*}}) +; CHECK: call { ptr, ptr } @__msan_metadata_ptr_for_store_8(ptr %nr) ; Hooks for inputs usually go before the assembly statement. But here we have none, ; because %nr is passed by value. However we check %nr for being initialized. -; CHECK-CONS: [[NRC3:%.*]] = bitcast i64* %nr to i8* -; CHECK-CONS: call { i8*, i32* } @__msan_metadata_ptr_for_load_8(i8* [[NRC3]]) +; CHECK-CONS: call { ptr, ptr } @__msan_metadata_ptr_for_load_8(ptr %nr) ; In the conservative mode, call the store hooks for %bit and %addr: -; CHECK-CONS: call void @__msan_instrument_asm_store(i8* %bit, i64 1) -; CHECK-CONS: [[ADDR8S:%.*]] = bitcast i64** %addr to i8* -; CHECK-CONS: call void @__msan_instrument_asm_store(i8* [[ADDR8S]], i64 8) +; CHECK-CONS: call void @__msan_instrument_asm_store(ptr %bit, i64 1) +; CHECK-CONS: call void @__msan_instrument_asm_store(ptr %addr, i64 8) ; Landing pad for the %nr check above. ; CHECK-CONS: call void @__msan_warning @@ -82,8 +78,8 @@ ; CHECKz: [[SH_NUM:%.*]] = xor i64 [[PTR]] ; CHECKz: [[SHADOW:%.*]] = inttoptr i64 [[SH_NUM]] {{.*}} -; CHECK: [[META:%.*]] = call {{.*}} @__msan_metadata_ptr_for_load_1(i8* %bit) -; CHECK: [[SHADOW:%.*]] = extractvalue { i8*, i32* } [[META]], 0 +; CHECK: [[META:%.*]] = call {{.*}} @__msan_metadata_ptr_for_load_1(ptr %bit) +; CHECK: [[SHADOW:%.*]] = extractvalue { ptr, ptr } [[META]], 0 ; Now load the shadow value for the boolean. ; CHECK: [[MSLD:%.*]] = load {{.*}} [[SHADOW]] diff --git a/llvm/test/Instrumentation/MemorySanitizer/msan_x86intrinsics.ll b/llvm/test/Instrumentation/MemorySanitizer/msan_x86intrinsics.ll --- a/llvm/test/Instrumentation/MemorySanitizer/msan_x86intrinsics.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/msan_x86intrinsics.ll @@ -10,38 +10,38 @@ ; Store intrinsic. -define void @StoreIntrinsic(i8* %p, <4 x float> %x) nounwind uwtable sanitize_memory { - call void @llvm.x86.sse.storeu.ps(i8* %p, <4 x float> %x) +define void @StoreIntrinsic(ptr %p, <4 x float> %x) nounwind uwtable sanitize_memory { + call void @llvm.x86.sse.storeu.ps(ptr %p, <4 x float> %x) ret void } -declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind +declare void @llvm.x86.sse.storeu.ps(ptr, <4 x float>) nounwind ; CHECK-LABEL: @StoreIntrinsic ; CHECK-NOT: br ; CHECK-NOT: = or ; CHECK: store <4 x i32> {{.*}} align 1 -; CHECK: store <4 x float> %{{.*}}, <4 x float>* %{{.*}}, align 1{{$}} +; CHECK: store <4 x float> %{{.*}}, ptr %{{.*}}, align 1{{$}} ; CHECK: ret void ; Load intrinsic. -define <16 x i8> @LoadIntrinsic(i8* %p) nounwind uwtable sanitize_memory { - %call = call <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p) +define <16 x i8> @LoadIntrinsic(ptr %p) nounwind uwtable sanitize_memory { + %call = call <16 x i8> @llvm.x86.sse3.ldu.dq(ptr %p) ret <16 x i8> %call } -declare <16 x i8> @llvm.x86.sse3.ldu.dq(i8* %p) nounwind +declare <16 x i8> @llvm.x86.sse3.ldu.dq(ptr %p) nounwind ; CHECK-LABEL: @LoadIntrinsic -; CHECK: load <16 x i8>, <16 x i8>* {{.*}} align 1 -; CHECK-ORIGINS: [[ORIGIN:%[01-9a-z]+]] = load i32, i32* {{.*}} +; CHECK: load <16 x i8>, ptr {{.*}} align 1 +; CHECK-ORIGINS: [[ORIGIN:%[01-9a-z]+]] = load i32, ptr {{.*}} ; CHECK-NOT: br ; CHECK-NOT: = or ; CHECK: call <16 x i8> @llvm.x86.sse3.ldu.dq ; CHECK: store <16 x i8> {{.*}} @__msan_retval_tls -; CHECK-ORIGINS: store i32 {{.*}}[[ORIGIN]], i32* @__msan_retval_origin_tls +; CHECK-ORIGINS: store i32 {{.*}}[[ORIGIN]], ptr @__msan_retval_origin_tls ; CHECK: ret <16 x i8> @@ -57,10 +57,10 @@ declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a, <8 x i16> %b) nounwind ; CHECK-LABEL: @Pmulhuw128 -; CHECK-NEXT: load <8 x i16>, <8 x i16>* {{.*}} @__msan_param_tls -; CHECK-ORIGINS: load i32, i32* {{.*}} @__msan_param_origin_tls -; CHECK-NEXT: load <8 x i16>, <8 x i16>* {{.*}} @__msan_param_tls -; CHECK-ORIGINS: load i32, i32* {{.*}} @__msan_param_origin_tls +; CHECK-NEXT: load <8 x i16>, ptr @__msan_param_tls +; CHECK-ORIGINS: load i32, ptr @__msan_param_origin_tls +; CHECK-NEXT: load <8 x i16>, ptr {{.*}} @__msan_param_tls +; CHECK-ORIGINS: load i32, ptr {{.*}} @__msan_param_origin_tls ; CHECK-NEXT: call void @llvm.donothing ; CHECK-NEXT: = or <8 x i16> ; CHECK-ORIGINS: = bitcast <8 x i16> {{.*}} to i128 diff --git a/llvm/test/Instrumentation/MemorySanitizer/mul_by_constant.ll b/llvm/test/Instrumentation/MemorySanitizer/mul_by_constant.ll --- a/llvm/test/Instrumentation/MemorySanitizer/mul_by_constant.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/mul_by_constant.ll @@ -19,7 +19,7 @@ ; CHECK-LABEL: @MulConst( ; CHECK: [[A:%.*]] = load {{.*}} @__msan_param_tls ; CHECK: [[B:%.*]] = mul i64 [[A]], 68719476736 -; CHECK: store i64 [[B]], i64* {{.*}} @__msan_retval_tls +; CHECK: store i64 [[B]], ptr @__msan_retval_tls define i64 @MulZero(i64 %x) sanitize_memory { @@ -31,7 +31,7 @@ ; CHECK-LABEL: @MulZero( ; CHECK: [[A:%.*]] = load {{.*}} @__msan_param_tls ; CHECK: [[B:%.*]] = mul i64 [[A]], 0{{$}} -; CHECK: store i64 [[B]], i64* {{.*}} @__msan_retval_tls +; CHECK: store i64 [[B]], ptr @__msan_retval_tls define i64 @MulNeg(i64 %x) sanitize_memory { @@ -43,7 +43,7 @@ ; CHECK-LABEL: @MulNeg( ; CHECK: [[A:%.*]] = load {{.*}} @__msan_param_tls ; CHECK: [[B:%.*]] = mul i64 [[A]], 16 -; CHECK: store i64 [[B]], i64* {{.*}} @__msan_retval_tls +; CHECK: store i64 [[B]], ptr @__msan_retval_tls define i64 @MulNeg2(i64 %x) sanitize_memory { @@ -55,7 +55,7 @@ ; CHECK-LABEL: @MulNeg2( ; CHECK: [[A:%.*]] = load {{.*}} @__msan_param_tls ; CHECK: [[B:%.*]] = mul i64 [[A]], 16 -; CHECK: store i64 [[B]], i64* {{.*}} @__msan_retval_tls +; CHECK: store i64 [[B]], ptr @__msan_retval_tls define i64 @MulOdd(i64 %x) sanitize_memory { @@ -67,7 +67,7 @@ ; CHECK-LABEL: @MulOdd( ; CHECK: [[A:%.*]] = load {{.*}} @__msan_param_tls ; CHECK: [[B:%.*]] = mul i64 [[A]], 1 -; CHECK: store i64 [[B]], i64* {{.*}} @__msan_retval_tls +; CHECK: store i64 [[B]], ptr @__msan_retval_tls define i64 @MulLarge(i64 %x) sanitize_memory { @@ -81,7 +81,7 @@ ; CHECK-LABEL: @MulLarge( ; CHECK: [[A:%.*]] = load {{.*}} @__msan_param_tls ; CHECK: [[B:%.*]] = mul i64 [[A]], -9223372036854775808 -; CHECK: store i64 [[B]], i64* {{.*}} @__msan_retval_tls +; CHECK: store i64 [[B]], ptr @__msan_retval_tls define <4 x i32> @MulVectorConst(<4 x i32> %x) sanitize_memory { entry: @@ -92,13 +92,13 @@ ; CHECK-LABEL: @MulVectorConst( ; CHECK: [[A:%.*]] = load {{.*}} @__msan_param_tls ; CHECK: [[B:%.*]] = mul <4 x i32> [[A]], -; CHECK: store <4 x i32> [[B]], <4 x i32>* {{.*}} @__msan_retval_tls +; CHECK: store <4 x i32> [[B]], ptr @__msan_retval_tls ; The constant in multiplication does not have to be a literal integer constant. -@X = linkonce_odr global i8* null +@X = linkonce_odr global ptr null define i64 @MulNonIntegerConst(i64 %a) sanitize_memory { - %mul = mul i64 %a, ptrtoint (i8** @X to i64) + %mul = mul i64 %a, ptrtoint (ptr @X to i64) ret i64 %mul } @@ -108,7 +108,7 @@ ; CHECK: store i64 [[B]], {{.*}}@__msan_retval_tls define <2 x i64> @MulNonIntegerVectorConst(<2 x i64> %a) sanitize_memory { - %mul = mul <2 x i64> %a, + %mul = mul <2 x i64> %a, ret <2 x i64> %mul } diff --git a/llvm/test/Instrumentation/MemorySanitizer/no-check-rt-unaligned.ll b/llvm/test/Instrumentation/MemorySanitizer/no-check-rt-unaligned.ll --- a/llvm/test/Instrumentation/MemorySanitizer/no-check-rt-unaligned.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/no-check-rt-unaligned.ll @@ -3,14 +3,14 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare noundef i8 @__sanitizer_unaligned_load8(i8* noundef) -declare void @__sanitizer_unaligned_store8(i8* noundef, i8 noundef) +declare noundef i8 @__sanitizer_unaligned_load8(ptr noundef) +declare void @__sanitizer_unaligned_store8(ptr noundef, i8 noundef) -define noundef i8 @unaligned_load(i8* noundef %ptr) sanitize_memory { -; CHECK: @unaligned_load(i8* {{.*}}[[PTR:%.+]]) +define noundef i8 @unaligned_load(ptr noundef %ptr) sanitize_memory { +; CHECK: @unaligned_load(ptr {{.*}}[[PTR:%.+]]) ; CHECK: store i64 0, {{.*}} @__msan_param_tls -; CHECK: [[VAL:%.*]] = call noundef i8 @__sanitizer_unaligned_load8(i8* noundef [[PTR]]) - %val = call noundef i8 @__sanitizer_unaligned_load8(i8* noundef %ptr) +; CHECK: [[VAL:%.*]] = call noundef i8 @__sanitizer_unaligned_load8(ptr noundef [[PTR]]) + %val = call noundef i8 @__sanitizer_unaligned_load8(ptr noundef %ptr) ; CHECK: load {{.*}} @__msan_retval_tls ; CHECK-ORIGIN: load {{.*}} @__msan_retval_origin_tls ; CHECK: call void @__msan_warning_{{.*}}noreturn @@ -18,12 +18,12 @@ ret i8 %val } -define void @unaligned_store(i8* noundef %ptr, i8 noundef %val) sanitize_memory { -; CHECK: @unaligned_store(i8* {{.*}}[[PTR:%.+]], i8 {{.*}}[[VAL:%.+]]) +define void @unaligned_store(ptr noundef %ptr, i8 noundef %val) sanitize_memory { +; CHECK: @unaligned_store(ptr {{.*}}[[PTR:%.+]], i8 {{.*}}[[VAL:%.+]]) ; CHECK: store i64 0, {{.*}} @__msan_param_tls ; CHECK: store i8 0, {{.*}} @__msan_param_tls -; CHECK: call void @__sanitizer_unaligned_store8(i8* noundef [[PTR]], i8 noundef [[VAL]]) - call void @__sanitizer_unaligned_store8(i8* noundef %ptr, i8 noundef %val) +; CHECK: call void @__sanitizer_unaligned_store8(ptr noundef [[PTR]], i8 noundef [[VAL]]) + call void @__sanitizer_unaligned_store8(ptr noundef %ptr, i8 noundef %val) ; CHECK: ret void ret void } diff --git a/llvm/test/Instrumentation/MemorySanitizer/nosanitize.ll b/llvm/test/Instrumentation/MemorySanitizer/nosanitize.ll --- a/llvm/test/Instrumentation/MemorySanitizer/nosanitize.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/nosanitize.ll @@ -20,9 +20,9 @@ @__sancov_gen_ = private global [1 x i8] zeroinitializer, section "__sancov_cntrs", align 1 define void @sancov() sanitize_memory { entry: - %0 = load i8, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @__sancov_gen_, i64 0, i64 0), !nosanitize !{} + %0 = load i8, ptr @__sancov_gen_, !nosanitize !{} %1 = add i8 %0, 1 - store i8 %1, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @__sancov_gen_, i64 0, i64 0), !nosanitize !{} + store i8 %1, ptr @__sancov_gen_, !nosanitize !{} ret void } @@ -35,10 +35,10 @@ define void @load_store() sanitize_memory { entry: %x = alloca i32, align 4, !nosanitize !{} - store i32 4, i32* %x, align 4, !nosanitize !{} - %0 = load i32, i32* %x, align 4, !nosanitize !{} + store i32 4, ptr %x, align 4, !nosanitize !{} + %0 = load i32, ptr %x, align 4, !nosanitize !{} %add = add nsw i32 %0, %0 - store i32 %add, i32* %x, align 4, !nosanitize !{} + store i32 %add, ptr %x, align 4, !nosanitize !{} ret void } diff --git a/llvm/test/Instrumentation/MemorySanitizer/opaque-ptr.ll b/llvm/test/Instrumentation/MemorySanitizer/opaque-ptr.ll --- a/llvm/test/Instrumentation/MemorySanitizer/opaque-ptr.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/opaque-ptr.ll @@ -13,7 +13,7 @@ ; CHECK-NEXT: [[TMP4:%.*]] = call ptr @__msan_memcpy(ptr [[P:%.*]], ptr [[P2]], i64 4) ; CHECK-NEXT: ret void ; - call void @llvm.memcpy.p0.p0.i64(i8* %p, i8* %p2, i64 4, i1 false) + call void @llvm.memcpy.p0.p0.i64(ptr %p, ptr %p2, i64 4, i1 false) ret void } @@ -27,9 +27,9 @@ ; CHECK-NEXT: [[TMP4:%.*]] = call ptr @__msan_memmove(ptr [[P:%.*]], ptr [[P2]], i64 4) ; CHECK-NEXT: ret void ; - call void @llvm.memmove.p0.p0.i64(i8* %p, i8* %p2, i64 4, i1 false) + call void @llvm.memmove.p0.p0.i64(ptr %p, ptr %p2, i64 4, i1 false) ret void } -declare void @llvm.memcpy.p0.p0.i64(i8*, i8*, i64, i1) -declare void @llvm.memmove.p0.p0.i64(i8*, i8*, i64, i1) +declare void @llvm.memcpy.p0.p0.i64(ptr, ptr, i64, i1) +declare void @llvm.memmove.p0.p0.i64(ptr, ptr, i64, i1) diff --git a/llvm/test/Instrumentation/MemorySanitizer/origin-alignment.ll b/llvm/test/Instrumentation/MemorySanitizer/origin-alignment.ll --- a/llvm/test/Instrumentation/MemorySanitizer/origin-alignment.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/origin-alignment.ll @@ -20,7 +20,7 @@ ; 8-aligned store => 8-aligned origin store, origin address is not realigned define void @Store8(i8 %x) sanitize_memory { entry: - store i8 %x, i8* @a8, align 8 + store i8 %x, ptr @a8, align 8 ret void } @@ -35,7 +35,7 @@ ; 4-aligned store => 4-aligned origin store, origin address is not realigned define void @Store4(i8 %x) sanitize_memory { entry: - store i8 %x, i8* @a4, align 4 + store i8 %x, ptr @a4, align 4 ret void } @@ -50,7 +50,7 @@ ; 2-aligned store => 4-aligned origin store, origin address is realigned define void @Store2(i8 %x) sanitize_memory { entry: - store i8 %x, i8* @a2, align 2 + store i8 %x, ptr @a2, align 2 ret void } @@ -65,7 +65,7 @@ ; 1-aligned store => 4-aligned origin store, origin address is realigned define void @Store1(i8 %x) sanitize_memory { entry: - store i8 %x, i8* @a1, align 1 + store i8 %x, ptr @a1, align 1 ret void } diff --git a/llvm/test/Instrumentation/MemorySanitizer/origin-array.ll b/llvm/test/Instrumentation/MemorySanitizer/origin-array.ll --- a/llvm/test/Instrumentation/MemorySanitizer/origin-array.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/origin-array.ll @@ -6,9 +6,9 @@ ; Check origin handling of array types. -define void @foo([2 x i64] %v, [2 x i64]* %p) sanitize_memory { +define void @foo([2 x i64] %v, ptr %p) sanitize_memory { entry: - store [2 x i64] %v, [2 x i64]* %p, align 8 + store [2 x i64] %v, ptr %p, align 8 ret void } @@ -18,7 +18,7 @@ ; CHECK: [[TMP1:%[01-9a-z]+]] = ptrtoint ; CHECK: [[TMP2:%[01-9a-z]+]] = xor i64 [[TMP1]] -; CHECK: [[TMP3:%[01-9a-z]+]] = inttoptr i64 [[TMP2]] to [2 x i64]* -; CHECK: store [2 x i64] [[PARAM]], [2 x i64]* [[TMP3]] +; CHECK: [[TMP3:%[01-9a-z]+]] = inttoptr i64 [[TMP2]] to ptr +; CHECK: store [2 x i64] [[PARAM]], ptr [[TMP3]] ; CHECK: {{.*}} call i32 @__msan_chain_origin(i32 {{.*}}[[ORIGIN]]) diff --git a/llvm/test/Instrumentation/MemorySanitizer/reduce.ll b/llvm/test/Instrumentation/MemorySanitizer/reduce.ll --- a/llvm/test/Instrumentation/MemorySanitizer/reduce.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/reduce.ll @@ -11,12 +11,12 @@ ; CHECK-LABEL: @reduce_add define i32 @reduce_add() sanitize_memory { -; CHECK: [[P:%.*]] = inttoptr i64 0 to <3 x i32>* - %p = inttoptr i64 0 to <3 x i32> * -; CHECK: [[O:%.*]] = load <3 x i32>, <3 x i32>* [[P]] - %o = load <3 x i32>, <3 x i32> *%p -; CHECK: [[O_SHADOW:%.*]] = load <3 x i32>, <3 x i32>* -; CHECK: [[O_ORIGIN:%.*]] = load i32, i32* +; CHECK: [[P:%.*]] = inttoptr i64 0 to ptr + %p = inttoptr i64 0 to ptr +; CHECK: [[O:%.*]] = load <3 x i32>, ptr [[P]] + %o = load <3 x i32>, ptr %p +; CHECK: [[O_SHADOW:%.*]] = load <3 x i32>, ptr +; CHECK: [[O_ORIGIN:%.*]] = load i32, ptr ; CHECK: [[R_SHADOW:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[O_SHADOW]]) ; CHECK: [[R:%.*]] = call i32 @llvm.vector.reduce.add.v3i32(<3 x i32> [[O]]) %r = call i32 @llvm.vector.reduce.add(<3 x i32> %o) @@ -28,12 +28,12 @@ ; CHECK-LABEL: @reduce_and define i32 @reduce_and() sanitize_memory { -; CHECK: [[P:%.*]] = inttoptr i64 0 to <3 x i32>* - %p = inttoptr i64 0 to <3 x i32> * -; CHECK: [[O:%.*]] = load <3 x i32>, <3 x i32>* [[P]] - %o = load <3 x i32>, <3 x i32> *%p -; CHECK: [[O_SHADOW:%.*]] = load <3 x i32>, <3 x i32>* -; CHECK: [[O_ORIGIN:%.*]] = load i32, i32* +; CHECK: [[P:%.*]] = inttoptr i64 0 to ptr + %p = inttoptr i64 0 to ptr +; CHECK: [[O:%.*]] = load <3 x i32>, ptr [[P]] + %o = load <3 x i32>, ptr %p +; CHECK: [[O_SHADOW:%.*]] = load <3 x i32>, ptr +; CHECK: [[O_ORIGIN:%.*]] = load i32, ptr ; CHECK: [[O_SHADOW_1:%.*]] = or <3 x i32> [[O]], [[O_SHADOW]] ; CHECK: [[O_SHADOW_2:%.*]] = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> [[O_SHADOW_1]] ; CHECK: [[O_SHADOW_3:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[O_SHADOW]]) @@ -48,12 +48,12 @@ ; CHECK-LABEL: @reduce_or define i32 @reduce_or() sanitize_memory { -; CHECK: [[P:%.*]] = inttoptr i64 0 to <3 x i32>* - %p = inttoptr i64 0 to <3 x i32> * -; CHECK: [[O:%.*]] = load <3 x i32>, <3 x i32>* [[P]] - %o = load <3 x i32>, <3 x i32> *%p -; CHECK: [[O_SHADOW:%.*]] = load <3 x i32>, <3 x i32>* -; CHECK: [[O_ORIGIN:%.*]] = load i32, i32* +; CHECK: [[P:%.*]] = inttoptr i64 0 to ptr + %p = inttoptr i64 0 to ptr +; CHECK: [[O:%.*]] = load <3 x i32>, ptr [[P]] + %o = load <3 x i32>, ptr %p +; CHECK: [[O_SHADOW:%.*]] = load <3 x i32>, ptr +; CHECK: [[O_ORIGIN:%.*]] = load i32, ptr ; CHECK: [[NOT_O:%.*]] = xor <3 x i32> [[O]], ; CHECK: [[O_SHADOW_1:%.*]] = or <3 x i32> [[NOT_O]], [[O_SHADOW]] ; CHECK: [[O_SHADOW_2:%.*]] = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> [[O_SHADOW_1]] diff --git a/llvm/test/Instrumentation/MemorySanitizer/sse-intrinsics-x86.ll b/llvm/test/Instrumentation/MemorySanitizer/sse-intrinsics-x86.ll --- a/llvm/test/Instrumentation/MemorySanitizer/sse-intrinsics-x86.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/sse-intrinsics-x86.ll @@ -6,14 +6,14 @@ define <4 x float> @test_x86_sse_cmp_ps(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_cmp_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = sext <4 x i1> [[TMP4]] to <4 x i32> ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 7) -; CHECK-NEXT: store <4 x i32> [[TMP5]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse.cmp.ps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1] @@ -24,8 +24,8 @@ define <4 x float> @test_x86_sse_cmp_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_cmp_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 @@ -33,7 +33,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i128 ; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <4 x i32> ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 7) -; CHECK-NEXT: store <4 x i32> [[TMP7]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP7]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1] @@ -44,15 +44,15 @@ define i32 @test_x86_sse_comieq_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_comieq_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.comieq.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.comieq.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -63,15 +63,15 @@ define i32 @test_x86_sse_comige_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_comige_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.comige.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.comige.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -82,15 +82,15 @@ define i32 @test_x86_sse_comigt_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_comigt_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.comigt.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.comigt.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -101,15 +101,15 @@ define i32 @test_x86_sse_comile_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_comile_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.comile.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.comile.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -120,15 +120,15 @@ define i32 @test_x86_sse_comilt_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_comilt_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.comilt.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.comilt.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -139,15 +139,15 @@ define i32 @test_x86_sse_comineq_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_comineq_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.comineq.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.comineq.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -158,7 +158,7 @@ define i32 @test_x86_sse_cvtss2si(<4 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_sse_cvtss2si( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0 @@ -168,7 +168,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.cvtss2si(<4 x float> [[A0:%.*]]) -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.cvtss2si(<4 x float> %a0) ; [#uses=1] @@ -179,7 +179,7 @@ define i32 @test_x86_sse_cvttss2si(<4 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_sse_cvttss2si( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0 @@ -189,7 +189,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.cvttss2si(<4 x float> [[A0:%.*]]) -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %a0) ; [#uses=1] @@ -198,14 +198,14 @@ declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone -define void @test_x86_sse_ldmxcsr(i8* %a0) #0 { +define void @test_x86_sse_ldmxcsr(ptr %a0) #0 { ; CHECK-LABEL: @test_x86_sse_ldmxcsr( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint i8* [[A0:%.*]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A0:%.*]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 -; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to i32* -; CHECK-NEXT: [[_LDMXCSR:%.*]] = load i32, i32* [[TMP4]], align 1 +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; CHECK-NEXT: [[_LDMXCSR:%.*]] = load i32, ptr [[TMP4]], align 1 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[_LDMXCSR]], 0 ; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]] @@ -214,24 +214,24 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]] ; CHECK-NEXT: unreachable ; CHECK: 6: -; CHECK-NEXT: call void @llvm.x86.sse.ldmxcsr(i8* [[A0]]) +; CHECK-NEXT: call void @llvm.x86.sse.ldmxcsr(ptr [[A0]]) ; CHECK-NEXT: ret void ; - call void @llvm.x86.sse.ldmxcsr(i8* %a0) + call void @llvm.x86.sse.ldmxcsr(ptr %a0) ret void } -declare void @llvm.x86.sse.ldmxcsr(i8*) nounwind +declare void @llvm.x86.sse.ldmxcsr(ptr) nounwind define <4 x float> @test_x86_sse_max_ps(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_max_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i32> [[_MSPROP]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse.max.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -242,13 +242,13 @@ define <4 x float> @test_x86_sse_max_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_max_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP3]], <4 x i32> ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i32> [[TMP4]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -259,12 +259,12 @@ define <4 x float> @test_x86_sse_min_ps(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_min_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i32> [[_MSPROP]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse.min.ps(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -275,13 +275,13 @@ define <4 x float> @test_x86_sse_min_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_min_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP3]], <4 x i32> ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i32> [[TMP4]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %a0, <4 x float> %a1) ; <<4 x float>> [#uses=1] @@ -292,7 +292,7 @@ define i32 @test_x86_sse_movmsk_ps(<4 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_sse_movmsk_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 @@ -302,7 +302,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> [[A0:%.*]]) -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %a0) ; [#uses=1] @@ -314,10 +314,10 @@ define <4 x float> @test_x86_sse_rcp_ps(<4 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_sse_rcp_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> [[A0:%.*]]) -; CHECK-NEXT: store <4 x i32> [[TMP1]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse.rcp.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1] @@ -328,10 +328,10 @@ define <4 x float> @test_x86_sse_rcp_ss(<4 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_sse_rcp_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> [[A0:%.*]]) -; CHECK-NEXT: store <4 x i32> [[TMP1]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1] @@ -342,10 +342,10 @@ define <4 x float> @test_x86_sse_rsqrt_ps(<4 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_sse_rsqrt_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> [[A0:%.*]]) -; CHECK-NEXT: store <4 x i32> [[TMP1]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse.rsqrt.ps(<4 x float> %a0) ; <<4 x float>> [#uses=1] @@ -356,10 +356,10 @@ define <4 x float> @test_x86_sse_rsqrt_ss(<4 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_sse_rsqrt_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> [[A0:%.*]]) -; CHECK-NEXT: store <4 x i32> [[TMP1]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %a0) ; <<4 x float>> [#uses=1] @@ -368,40 +368,40 @@ declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>) nounwind readnone -define void @test_x86_sse_stmxcsr(i8* %a0) #0 { +define void @test_x86_sse_stmxcsr(ptr %a0) #0 { ; CHECK-LABEL: @test_x86_sse_stmxcsr( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() -; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint i8* [[A0:%.*]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A0:%.*]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 -; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to i32* -; CHECK-NEXT: store i32 0, i32* [[TMP4]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; CHECK-NEXT: store i32 0, ptr [[TMP4]], align 4 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]] ; CHECK: 5: ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]] ; CHECK-NEXT: unreachable ; CHECK: 6: -; CHECK-NEXT: call void @llvm.x86.sse.stmxcsr(i8* [[A0]]) +; CHECK-NEXT: call void @llvm.x86.sse.stmxcsr(ptr [[A0]]) ; CHECK-NEXT: ret void ; - call void @llvm.x86.sse.stmxcsr(i8* %a0) + call void @llvm.x86.sse.stmxcsr(ptr %a0) ret void } -declare void @llvm.x86.sse.stmxcsr(i8*) nounwind +declare void @llvm.x86.sse.stmxcsr(ptr) nounwind define i32 @test_x86_sse_ucomieq_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_ucomieq_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -412,15 +412,15 @@ define i32 @test_x86_sse_ucomige_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_ucomige_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -431,15 +431,15 @@ define i32 @test_x86_sse_ucomigt_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_ucomigt_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -450,15 +450,15 @@ define i32 @test_x86_sse_ucomile_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_ucomile_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -469,15 +469,15 @@ define i32 @test_x86_sse_ucomilt_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_ucomilt_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] @@ -488,15 +488,15 @@ define i32 @test_x86_sse_ucomineq_ss(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse_ucomineq_ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i32 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %a0, <4 x float> %a1) ; [#uses=1] diff --git a/llvm/test/Instrumentation/MemorySanitizer/sse2-intrinsics-x86.ll b/llvm/test/Instrumentation/MemorySanitizer/sse2-intrinsics-x86.ll --- a/llvm/test/Instrumentation/MemorySanitizer/sse2-intrinsics-x86.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/sse2-intrinsics-x86.ll @@ -6,14 +6,14 @@ define <2 x double> @test_x86_sse2_cmp_pd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_cmp_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = sext <2 x i1> [[TMP4]] to <2 x i64> ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i8 7) -; CHECK-NEXT: store <2 x i64> [[TMP5]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; %res = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1] @@ -24,8 +24,8 @@ define <2 x double> @test_x86_sse2_cmp_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_cmp_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0 @@ -33,7 +33,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i128 ; CHECK-NEXT: [[TMP7:%.*]] = bitcast i128 [[TMP6]] to <2 x i64> ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i8 7) -; CHECK-NEXT: store <2 x i64> [[TMP7]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; %res = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1] @@ -44,15 +44,15 @@ define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_comieq_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -63,15 +63,15 @@ define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_comige_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comige.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -82,15 +82,15 @@ define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_comigt_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -101,15 +101,15 @@ define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_comile_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comile.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -120,15 +120,15 @@ define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_comilt_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -139,15 +139,15 @@ define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_comineq_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -158,7 +158,7 @@ define <4 x i32> @test_x86_sse2_cvtpd2dq(<2 x double> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_cvtpd2dq( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 @@ -168,7 +168,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> [[A0:%.*]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1] @@ -179,7 +179,7 @@ define <2 x i64> @test_mm_cvtpd_epi32_zext(<2 x double> %a0) nounwind #0 { ; CHECK-LABEL: @test_mm_cvtpd_epi32_zext( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 @@ -191,7 +191,7 @@ ; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> [[A0:%.*]]) ; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i32> [[CVT]], <4 x i32> zeroinitializer, <4 x i32> ; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[RES]] to <2 x i64> -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[BC]] ; %cvt = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0) @@ -201,9 +201,9 @@ } -define <2 x i64> @test_mm_cvtpd_epi32_zext_load(<2 x double>* %p0) nounwind #0 { +define <2 x i64> @test_mm_cvtpd_epi32_zext_load(ptr %p0) nounwind #0 { ; CHECK-LABEL: @test_mm_cvtpd_epi32_zext_load( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]] @@ -211,11 +211,11 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 3: -; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, <2 x double>* [[P0:%.*]], align 16 -; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint <2 x double>* [[P0]] to i64 +; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, ptr [[P0:%.*]], align 16 +; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P0]] to i64 ; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080 -; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to <2 x i64>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, <2 x i64>* [[TMP6]], align 16 +; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 16 ; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[_MSLD]] to i128 ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0 ; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] @@ -226,10 +226,10 @@ ; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> [[A0]]) ; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i32> [[CVT]], <4 x i32> zeroinitializer, <4 x i32> ; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[RES]] to <2 x i64> -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[BC]] ; - %a0 = load <2 x double>, <2 x double>* %p0 + %a0 = load <2 x double>, ptr %p0 %cvt = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0) %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> %bc = bitcast <4 x i32> %res to <2 x i64> @@ -239,7 +239,7 @@ define <4 x float> @test_x86_sse2_cvtpd2ps(<2 x double> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_cvtpd2ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 @@ -249,7 +249,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> [[A0:%.*]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0) ; <<4 x float>> [#uses=1] @@ -259,7 +259,7 @@ define <4 x float> @test_x86_sse2_cvtpd2ps_zext(<2 x double> %a0) nounwind #0 { ; CHECK-LABEL: @test_x86_sse2_cvtpd2ps_zext( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 @@ -270,7 +270,7 @@ ; CHECK: 4: ; CHECK-NEXT: [[CVT:%.*]] = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> [[A0:%.*]]) ; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x float> [[CVT]], <4 x float> zeroinitializer, <4 x i32> -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %cvt = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0) @@ -278,9 +278,9 @@ ret <4 x float> %res } -define <4 x float> @test_x86_sse2_cvtpd2ps_zext_load(<2 x double>* %p0) nounwind #0 { +define <4 x float> @test_x86_sse2_cvtpd2ps_zext_load(ptr %p0) nounwind #0 { ; CHECK-LABEL: @test_x86_sse2_cvtpd2ps_zext_load( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]] @@ -288,11 +288,11 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 3: -; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, <2 x double>* [[P0:%.*]], align 16 -; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint <2 x double>* [[P0]] to i64 +; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, ptr [[P0:%.*]], align 16 +; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P0]] to i64 ; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080 -; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to <2 x i64>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, <2 x i64>* [[TMP6]], align 16 +; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 16 ; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[_MSLD]] to i128 ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0 ; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] @@ -302,10 +302,10 @@ ; CHECK: 9: ; CHECK-NEXT: [[CVT:%.*]] = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> [[A0]]) ; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x float> [[CVT]], <4 x float> zeroinitializer, <4 x i32> -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; - %a0 = load <2 x double>, <2 x double>* %p0 + %a0 = load <2 x double>, ptr %p0 %cvt = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0) %res = shufflevector <4 x float> %cvt, <4 x float> zeroinitializer, <4 x i32> ret <4 x float> %res @@ -313,7 +313,7 @@ define <4 x i32> @test_x86_sse2_cvtps2dq(<4 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_cvtps2dq( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 @@ -323,7 +323,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> [[A0:%.*]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1] @@ -334,7 +334,7 @@ define i32 @test_x86_sse2_cvtsd2si(<2 x double> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_cvtsd2si( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0 @@ -344,7 +344,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> [[A0:%.*]]) -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %a0) ; [#uses=1] @@ -355,8 +355,8 @@ define <4 x float> @test_x86_sse2_cvtsd2ss(<4 x float> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_cvtsd2ss( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0 ; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i32 0 @@ -367,7 +367,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i32> [[TMP4]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1] @@ -376,10 +376,10 @@ declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>) nounwind readnone -define <4 x float> @test_x86_sse2_cvtsd2ss_load(<4 x float> %a0, <2 x double>* %p1) #0 { +define <4 x float> @test_x86_sse2_cvtsd2ss_load(<4 x float> %a0, ptr %p1) #0 { ; CHECK-LABEL: @test_x86_sse2_cvtsd2ss_load( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] @@ -387,11 +387,11 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: -; CHECK-NEXT: [[A1:%.*]] = load <2 x double>, <2 x double>* [[P1:%.*]], align 16 -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <2 x double>* [[P1]] to i64 +; CHECK-NEXT: [[A1:%.*]] = load <2 x double>, ptr [[P1:%.*]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P1]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to <2 x i64>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, <2 x i64>* [[TMP7]], align 16 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16 ; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[_MSLD]], i32 0 ; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i32 0 ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP8]], 0 @@ -401,19 +401,19 @@ ; CHECK-NEXT: unreachable ; CHECK: 11: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> [[A0:%.*]], <2 x double> [[A1]]) -; CHECK-NEXT: store <4 x i32> [[TMP9]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; - %a1 = load <2 x double>, <2 x double>* %p1 + %a1 = load <2 x double>, ptr %p1 %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1] ret <4 x float> %res } -define <4 x float> @test_x86_sse2_cvtsd2ss_load_optsize(<4 x float> %a0, <2 x double>* %p1) optsize #0 { +define <4 x float> @test_x86_sse2_cvtsd2ss_load_optsize(<4 x float> %a0, ptr %p1) optsize #0 { ; CHECK-LABEL: @test_x86_sse2_cvtsd2ss_load_optsize( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] @@ -421,11 +421,11 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: -; CHECK-NEXT: [[A1:%.*]] = load <2 x double>, <2 x double>* [[P1:%.*]], align 16 -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <2 x double>* [[P1]] to i64 +; CHECK-NEXT: [[A1:%.*]] = load <2 x double>, ptr [[P1:%.*]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P1]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to <2 x i64>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, <2 x i64>* [[TMP7]], align 16 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16 ; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i64> [[_MSLD]], i32 0 ; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP2]], i32 0, i32 0 ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP8]], 0 @@ -435,10 +435,10 @@ ; CHECK-NEXT: unreachable ; CHECK: 11: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> [[A0:%.*]], <2 x double> [[A1]]) -; CHECK-NEXT: store <4 x i32> [[TMP9]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; - %a1 = load <2 x double>, <2 x double>* %p1 + %a1 = load <2 x double>, ptr %p1 %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1] ret <4 x float> %res } @@ -446,7 +446,7 @@ define <4 x i32> @test_x86_sse2_cvttpd2dq(<2 x double> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_cvttpd2dq( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 @@ -456,7 +456,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> [[A0:%.*]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1] @@ -467,7 +467,7 @@ define <2 x i64> @test_mm_cvttpd_epi32_zext(<2 x double> %a0) nounwind #0 { ; CHECK-LABEL: @test_mm_cvttpd_epi32_zext( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 @@ -479,7 +479,7 @@ ; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> [[A0:%.*]]) ; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i32> [[CVT]], <4 x i32> zeroinitializer, <4 x i32> ; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[RES]] to <2 x i64> -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[BC]] ; %cvt = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0) @@ -489,9 +489,9 @@ } -define <2 x i64> @test_mm_cvttpd_epi32_zext_load(<2 x double>* %p0) nounwind #0 { +define <2 x i64> @test_mm_cvttpd_epi32_zext_load(ptr %p0) nounwind #0 { ; CHECK-LABEL: @test_mm_cvttpd_epi32_zext_load( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]] @@ -499,11 +499,11 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 3: -; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, <2 x double>* [[P0:%.*]], align 16 -; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint <2 x double>* [[P0]] to i64 +; CHECK-NEXT: [[A0:%.*]] = load <2 x double>, ptr [[P0:%.*]], align 16 +; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P0]] to i64 ; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080 -; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to <2 x i64>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, <2 x i64>* [[TMP6]], align 16 +; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 16 ; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[_MSLD]] to i128 ; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP7]], 0 ; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF0]] @@ -514,10 +514,10 @@ ; CHECK-NEXT: [[CVT:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> [[A0]]) ; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i32> [[CVT]], <4 x i32> zeroinitializer, <4 x i32> ; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[RES]] to <2 x i64> -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[BC]] ; - %a0 = load <2 x double>, <2 x double>* %p0 + %a0 = load <2 x double>, ptr %p0 %cvt = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0) %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> %bc = bitcast <4 x i32> %res to <2 x i64> @@ -527,7 +527,7 @@ define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_cvttps2dq( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 @@ -537,7 +537,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> [[A0:%.*]]) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1] @@ -548,7 +548,7 @@ define i32 @test_x86_sse2_cvttsd2si(<2 x double> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_cvttsd2si( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0 @@ -558,7 +558,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> [[A0:%.*]]) -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %a0) ; [#uses=1] @@ -569,12 +569,12 @@ define <2 x double> @test_x86_sse2_max_pd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_max_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store <2 x i64> [[_MSPROP]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; %res = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -585,13 +585,13 @@ define <2 x double> @test_x86_sse2_max_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_max_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP3]], <2 x i32> ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store <2 x i64> [[TMP4]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; %res = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -602,12 +602,12 @@ define <2 x double> @test_x86_sse2_min_pd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_min_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store <2 x i64> [[_MSPROP]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; %res = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -618,13 +618,13 @@ define <2 x double> @test_x86_sse2_min_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_min_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP3]], <2 x i32> ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store <2 x i64> [[TMP4]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP4]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; %res = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1] @@ -635,7 +635,7 @@ define i32 @test_x86_sse2_movmsk_pd(<2 x double> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_movmsk_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 @@ -645,7 +645,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> [[A0:%.*]]) -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0) ; [#uses=1] @@ -656,8 +656,8 @@ define <8 x i16> @test_x86_sse2_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_packssdw_128( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32> @@ -665,7 +665,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i1> [[TMP5]] to <4 x i32> ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[TMP4]], <4 x i32> [[TMP6]]) ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i16> [[_MSPROP_VECTOR_PACK]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %a0, <4 x i32> %a1) ; <<8 x i16>> [#uses=1] @@ -679,7 +679,7 @@ ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> zeroinitializer, <4 x i32> zeroinitializer) ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> zeroinitializer, <4 x i32> ) -; CHECK-NEXT: store <8 x i16> [[_MSPROP_VECTOR_PACK]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> zeroinitializer, <4 x i32> ) @@ -689,8 +689,8 @@ define <16 x i8> @test_x86_sse2_packsswb_128(<8 x i16> %a0, <8 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_packsswb_128( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i16> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i16> @@ -698,7 +698,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i16> ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> [[TMP4]], <8 x i16> [[TMP6]]) ; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], <16 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i8>*), align 8 +; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i8> [[RES]] ; %res = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1] @@ -712,7 +712,7 @@ ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> zeroinitializer, <8 x i16> zeroinitializer) ; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> , <8 x i16> zeroinitializer) -; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], <16 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i8>*), align 8 +; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i8> [[RES]] ; %res = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> , <8 x i16> zeroinitializer) @@ -722,8 +722,8 @@ define <16 x i8> @test_x86_sse2_packuswb_128(<8 x i16> %a0, <8 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_packuswb_128( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <8 x i16> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <8 x i1> [[TMP3]] to <8 x i16> @@ -731,7 +731,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i1> [[TMP5]] to <8 x i16> ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> [[TMP4]], <8 x i16> [[TMP6]]) ; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], <16 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i8>*), align 8 +; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i8> [[RES]] ; %res = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1] @@ -745,7 +745,7 @@ ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> zeroinitializer, <8 x i16> zeroinitializer) ; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> , <8 x i16> zeroinitializer) -; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], <16 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i8>*), align 8 +; CHECK-NEXT: store <16 x i8> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i8> [[RES]] ; %res = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> , <8 x i16> zeroinitializer) @@ -755,12 +755,12 @@ define <16 x i8> @test_x86_sse2_pavg_b(<16 x i8> %a0, <16 x i8> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_pavg_b( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i8>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <16 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> [[A0:%.*]], <16 x i8> [[A1:%.*]]) -; CHECK-NEXT: store <16 x i8> [[_MSPROP]], <16 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i8>*), align 8 +; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i8> [[RES]] ; %res = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1] @@ -771,12 +771,12 @@ define <8 x i16> @test_x86_sse2_pavg_w(<8 x i16> %a0, <8 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_pavg_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i16> [[_MSPROP]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -787,15 +787,15 @@ define <4 x i32> @test_x86_sse2_pmadd_wd(<8 x i16> %a0, <8 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_pmadd_wd( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP3]] to <4 x i32> ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne <4 x i32> [[TMP4]], zeroinitializer ; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i1> [[TMP5]] to <4 x i32> ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <4 x i32> [[TMP6]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a0, <8 x i16> %a1) ; <<4 x i32>> [#uses=1] @@ -806,7 +806,7 @@ define i32 @test_x86_sse2_pmovmskb_128(<16 x i8> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_pmovmskb_128( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 @@ -816,7 +816,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> [[A0:%.*]]) -; CHECK-NEXT: store i32 0, i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %a0) ; [#uses=1] @@ -827,12 +827,12 @@ define <8 x i16> @test_x86_sse2_pmulh_w(<8 x i16> %a0, <8 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_pmulh_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i16> [[_MSPROP]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -843,12 +843,12 @@ define <8 x i16> @test_x86_sse2_pmulhu_w(<8 x i16> %a0, <8 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_pmulhu_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i16> [[_MSPROP]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -859,8 +859,8 @@ define <2 x i64> @test_x86_sse2_psad_bw(<16 x i8> %a0, <16 x i8> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_psad_bw( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i8>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <16 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i8> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP3]] to <2 x i64> @@ -868,7 +868,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = sext <2 x i1> [[TMP5]] to <2 x i64> ; CHECK-NEXT: [[TMP7:%.*]] = lshr <2 x i64> [[TMP6]], ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> [[A0:%.*]], <16 x i8> [[A1:%.*]]) -; CHECK-NEXT: store <2 x i64> [[TMP7]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %res = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %a0, <16 x i8> %a1) ; <<2 x i64>> [#uses=1] @@ -879,8 +879,8 @@ define <4 x i32> @test_x86_sse2_psll_d(<4 x i32> %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_psll_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -890,7 +890,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]]) -; CHECK-NEXT: store <4 x i32> [[TMP9]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -901,8 +901,8 @@ define <2 x i64> @test_x86_sse2_psll_q(<2 x i64> %a0, <2 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_psll_q( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -912,7 +912,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> [[TMP1]], <2 x i64> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i64> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> [[A0:%.*]], <2 x i64> [[A1]]) -; CHECK-NEXT: store <2 x i64> [[TMP9]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %res = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] @@ -923,8 +923,8 @@ define <8 x i16> @test_x86_sse2_psll_w(<8 x i16> %a0, <8 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_psll_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -934,7 +934,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> [[TMP1]], <8 x i16> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1]]) -; CHECK-NEXT: store <8 x i16> [[TMP9]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -945,12 +945,12 @@ define <4 x i32> @test_x86_sse2_pslli_d(<4 x i32> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_pslli_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <4 x i32> [[TMP3]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1] @@ -961,12 +961,12 @@ define <2 x i64> @test_x86_sse2_pslli_q(<2 x i64> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_pslli_q( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <2 x i64> [[TMP3]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %res = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1] @@ -977,12 +977,12 @@ define <8 x i16> @test_x86_sse2_pslli_w(<8 x i16> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_pslli_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <8 x i16> [[TMP3]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1] @@ -993,8 +993,8 @@ define <4 x i32> @test_x86_sse2_psra_d(<4 x i32> %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_psra_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -1004,7 +1004,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]]) -; CHECK-NEXT: store <4 x i32> [[TMP9]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -1015,8 +1015,8 @@ define <8 x i16> @test_x86_sse2_psra_w(<8 x i16> %a0, <8 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_psra_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -1026,7 +1026,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> [[TMP1]], <8 x i16> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1]]) -; CHECK-NEXT: store <8 x i16> [[TMP9]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -1037,12 +1037,12 @@ define <4 x i32> @test_x86_sse2_psrai_d(<4 x i32> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_psrai_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <4 x i32> [[TMP3]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1] @@ -1053,12 +1053,12 @@ define <8 x i16> @test_x86_sse2_psrai_w(<8 x i16> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_psrai_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <8 x i16> [[TMP3]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1] @@ -1069,8 +1069,8 @@ define <4 x i32> @test_x86_sse2_psrl_d(<4 x i32> %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_psrl_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -1080,7 +1080,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> [[TMP1]], <4 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> [[A0:%.*]], <4 x i32> [[A1]]) -; CHECK-NEXT: store <4 x i32> [[TMP9]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1] @@ -1091,8 +1091,8 @@ define <2 x i64> @test_x86_sse2_psrl_q(<2 x i64> %a0, <2 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_psrl_q( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -1102,7 +1102,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> [[TMP1]], <2 x i64> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i64> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> [[A0:%.*]], <2 x i64> [[A1]]) -; CHECK-NEXT: store <2 x i64> [[TMP9]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %res = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] @@ -1113,8 +1113,8 @@ define <8 x i16> @test_x86_sse2_psrl_w(<8 x i16> %a0, <8 x i16> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_psrl_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i128 [[TMP3]] to i64 @@ -1124,7 +1124,7 @@ ; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> [[TMP1]], <8 x i16> [[A1:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1]]) -; CHECK-NEXT: store <8 x i16> [[TMP9]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[TMP9]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] @@ -1133,10 +1133,10 @@ declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone -define <8 x i16> @test_x86_sse2_psrl_w_load(<8 x i16> %a0, <8 x i16>* %p) #0 { +define <8 x i16> @test_x86_sse2_psrl_w_load(<8 x i16> %a0, ptr %p) #0 { ; CHECK-LABEL: @test_x86_sse2_psrl_w_load( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] @@ -1144,11 +1144,11 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 4: -; CHECK-NEXT: [[A1:%.*]] = load <8 x i16>, <8 x i16>* [[P:%.*]], align 16 -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <8 x i16>* [[P]] to i64 +; CHECK-NEXT: [[A1:%.*]] = load <8 x i16>, ptr [[P:%.*]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[P]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to <8 x i16>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, <8 x i16>* [[TMP7]], align 16 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16 ; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[_MSLD]] to i128 ; CHECK-NEXT: [[TMP9:%.*]] = trunc i128 [[TMP8]] to i64 ; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i64 [[TMP9]], 0 @@ -1157,10 +1157,10 @@ ; CHECK-NEXT: [[TMP13:%.*]] = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> [[TMP2]], <8 x i16> [[A1]]) ; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i16> [[TMP13]], [[TMP12]] ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> [[A0:%.*]], <8 x i16> [[A1]]) -; CHECK-NEXT: store <8 x i16> [[TMP14]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[TMP14]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; - %a1 = load <8 x i16>, <8 x i16>* %p + %a1 = load <8 x i16>, ptr %p %res = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1] ret <8 x i16> %res } @@ -1168,12 +1168,12 @@ define <4 x i32> @test_x86_sse2_psrli_d(<4 x i32> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_psrli_d( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <4 x i32> [[TMP3]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x i32> [[RES]] ; %res = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1] @@ -1184,12 +1184,12 @@ define <2 x i64> @test_x86_sse2_psrli_q(<2 x i64> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_psrli_q( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <2 x i64> [[TMP3]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x i64> [[RES]] ; %res = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1] @@ -1200,12 +1200,12 @@ define <8 x i16> @test_x86_sse2_psrli_w(<8 x i16> %a0) #0 { ; CHECK-LABEL: @test_x86_sse2_psrli_w( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> [[TMP1]], i32 7) ; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <8 x i16> [[TMP3]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1] @@ -1216,15 +1216,15 @@ define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_ucomieq_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -1235,15 +1235,15 @@ define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_ucomige_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -1254,15 +1254,15 @@ define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_ucomigt_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -1273,15 +1273,15 @@ define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_ucomile_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -1292,15 +1292,15 @@ define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_ucomilt_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -1311,15 +1311,15 @@ define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse2_ucomineq_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP4]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = sext i1 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %a0, <2 x double> %a1) ; [#uses=1] @@ -1360,9 +1360,9 @@ } declare void @llvm.x86.sse2.mfence() nounwind -define void @clflush(i8* %p) nounwind #0 { +define void @clflush(ptr %p) nounwind #0 { ; CHECK-LABEL: @clflush( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]] @@ -1370,12 +1370,12 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR6]] ; CHECK-NEXT: unreachable ; CHECK: 3: -; CHECK-NEXT: tail call void @llvm.x86.sse2.clflush(i8* [[P:%.*]]) +; CHECK-NEXT: tail call void @llvm.x86.sse2.clflush(ptr [[P:%.*]]) ; CHECK-NEXT: ret void ; - tail call void @llvm.x86.sse2.clflush(i8* %p) + tail call void @llvm.x86.sse2.clflush(ptr %p) ret void } -declare void @llvm.x86.sse2.clflush(i8*) nounwind +declare void @llvm.x86.sse2.clflush(ptr) nounwind attributes #0 = { sanitize_memory } diff --git a/llvm/test/Instrumentation/MemorySanitizer/sse41-intrinsics-x86.ll b/llvm/test/Instrumentation/MemorySanitizer/sse41-intrinsics-x86.ll --- a/llvm/test/Instrumentation/MemorySanitizer/sse41-intrinsics-x86.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/sse41-intrinsics-x86.ll @@ -6,14 +6,14 @@ define <2 x double> @test_x86_sse41_blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) #0 { ; CHECK-LABEL: @test_x86_sse41_blendvpd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[_MSPROP]], [[TMP3]] ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse41.blendvpd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], <2 x double> [[A2:%.*]]) -; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; %res = call <2 x double> @llvm.x86.sse41.blendvpd(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2) ; <<2 x double>> [#uses=1] @@ -24,14 +24,14 @@ define <4 x float> @test_x86_sse41_blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) #0 { ; CHECK-LABEL: @test_x86_sse41_blendvps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], [[TMP3]] ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], <4 x float> [[A2:%.*]]) -; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) ; <<4 x float>> [#uses=1] @@ -42,8 +42,8 @@ define <2 x double> @test_x86_sse41_dppd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse41_dppd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 @@ -56,7 +56,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i8 7) -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; %res = call <2 x double> @llvm.x86.sse41.dppd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1] @@ -67,8 +67,8 @@ define <4 x float> @test_x86_sse41_dpps(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse41_dpps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 @@ -81,7 +81,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 7) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse41.dpps(<4 x float> %a0, <4 x float> %a1, i8 7) ; <<4 x float>> [#uses=1] @@ -92,8 +92,8 @@ define <4 x float> @test_x86_sse41_insertps(<4 x float> %a0, <4 x float> %a1) #0 { ; CHECK-LABEL: @test_x86_sse41_insertps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 @@ -106,7 +106,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> [[A0:%.*]], <4 x float> [[A1:%.*]], i8 17) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 17) ; <<4 x float>> [#uses=1] @@ -118,8 +118,8 @@ define <8 x i16> @test_x86_sse41_mpsadbw(<16 x i8> %a0, <16 x i8> %a1) #0 { ; CHECK-LABEL: @test_x86_sse41_mpsadbw( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i8>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <16 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0 @@ -132,7 +132,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 6: ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> [[A0:%.*]], <16 x i8> [[A1:%.*]], i8 7) -; CHECK-NEXT: store <8 x i16> zeroinitializer, <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <<8 x i16>> [#uses=1] @@ -140,10 +140,10 @@ } declare <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8>, <16 x i8>, i8) nounwind readnone -define <8 x i16> @test_x86_sse41_mpsadbw_load_op0(<16 x i8>* %ptr, <16 x i8> %a1) #0 { +define <8 x i16> @test_x86_sse41_mpsadbw_load_op0(ptr %ptr, <16 x i8> %a1) #0 { ; CHECK-LABEL: @test_x86_sse41_mpsadbw_load_op0( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* getelementptr inbounds ([100 x i64], [100 x i64]* @__msan_param_tls, i32 0, i32 0), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 8) to <16 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] @@ -151,11 +151,11 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: 4: -; CHECK-NEXT: [[A0:%.*]] = load <16 x i8>, <16 x i8>* [[PTR:%.*]], align 16 -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <16 x i8>* [[PTR]] to i64 +; CHECK-NEXT: [[A0:%.*]] = load <16 x i8>, ptr [[PTR:%.*]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[PTR]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to <16 x i8>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, <16 x i8>* [[TMP7]], align 16 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 16 ; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i8> [[_MSLD]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP8]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = bitcast <16 x i8> [[TMP2]] to i128 @@ -167,18 +167,18 @@ ; CHECK-NEXT: unreachable ; CHECK: 11: ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> [[A0]], <16 x i8> [[A1:%.*]], i8 7) -; CHECK-NEXT: store <8 x i16> zeroinitializer, <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; - %a0 = load <16 x i8>, <16 x i8>* %ptr + %a0 = load <16 x i8>, ptr %ptr %res = call <8 x i16> @llvm.x86.sse41.mpsadbw(<16 x i8> %a0, <16 x i8> %a1, i8 7) ; <<8 x i16>> [#uses=1] ret <8 x i16> %res } define <8 x i16> @test_x86_sse41_packusdw(<4 x i32> %a0, <4 x i32> %a1) #0 { ; CHECK-LABEL: @test_x86_sse41_packusdw( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer ; CHECK-NEXT: [[TMP4:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32> @@ -186,7 +186,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = sext <4 x i1> [[TMP5]] to <4 x i32> ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[TMP4]], <4 x i32> [[TMP6]]) ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]]) -; CHECK-NEXT: store <8 x i16> [[_MSPROP_VECTOR_PACK]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %a0, <4 x i32> %a1) ; <<8 x i16>> [#uses=1] @@ -200,7 +200,7 @@ ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP_VECTOR_PACK:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> zeroinitializer, <4 x i32> zeroinitializer) ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> zeroinitializer, <4 x i32> ) -; CHECK-NEXT: store <8 x i16> [[_MSPROP_VECTOR_PACK]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[_MSPROP_VECTOR_PACK]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> zeroinitializer, <4 x i32> ) @@ -210,14 +210,14 @@ define <16 x i8> @test_x86_sse41_pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) #0 { ; CHECK-LABEL: @test_x86_sse41_pblendvb( -; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* bitcast ([100 x i64]* @__msan_param_tls to <16 x i8>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <16 x i8>*), align 8 -; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, <16 x i8>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 32) to <16 x i8>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i8> [[_MSPROP]], [[TMP3]] ; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> [[A0:%.*]], <16 x i8> [[A1:%.*]], <16 x i8> [[A2:%.*]]) -; CHECK-NEXT: store <16 x i8> [[_MSPROP1]], <16 x i8>* bitcast ([100 x i64]* @__msan_retval_tls to <16 x i8>*), align 8 +; CHECK-NEXT: store <16 x i8> [[_MSPROP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <16 x i8> [[RES]] ; %res = call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %a2) ; <<16 x i8>> [#uses=1] @@ -228,10 +228,10 @@ define <8 x i16> @test_x86_sse41_phminposuw(<8 x i16> %a0) #0 { ; CHECK-LABEL: @test_x86_sse41_phminposuw( -; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([100 x i64]* @__msan_param_tls to <8 x i16>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16> [[A0:%.*]]) -; CHECK-NEXT: store <8 x i16> [[TMP1]], <8 x i16>* bitcast ([100 x i64]* @__msan_retval_tls to <8 x i16>*), align 8 +; CHECK-NEXT: store <8 x i16> [[TMP1]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <8 x i16> [[RES]] ; %res = call <8 x i16> @llvm.x86.sse41.phminposuw(<8 x i16> %a0) ; <<8 x i16>> [#uses=1] @@ -242,15 +242,15 @@ define i32 @test_x86_sse41_ptestc(<2 x i64> %a0, <2 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_sse41_ptestc( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i1> [[TMP4]] to i2 ; CHECK-NEXT: [[TMP6:%.*]] = zext i2 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse41.ptestc(<2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %a0, <2 x i64> %a1) ; [#uses=1] @@ -261,15 +261,15 @@ define i32 @test_x86_sse41_ptestnzc(<2 x i64> %a0, <2 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_sse41_ptestnzc( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i1> [[TMP4]] to i2 ; CHECK-NEXT: [[TMP6:%.*]] = zext i2 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %a0, <2 x i64> %a1) ; [#uses=1] @@ -280,15 +280,15 @@ define i32 @test_x86_sse41_ptestz(<2 x i64> %a0, <2 x i64> %a1) #0 { ; CHECK-LABEL: @test_x86_sse41_ptestz( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP1]], [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <2 x i64> [[TMP3]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i1> [[TMP4]] to i2 ; CHECK-NEXT: [[TMP6:%.*]] = zext i2 [[TMP5]] to i32 ; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.x86.sse41.ptestz(<2 x i64> [[A0:%.*]], <2 x i64> [[A1:%.*]]) -; CHECK-NEXT: store i32 [[TMP6]], i32* bitcast ([100 x i64]* @__msan_retval_tls to i32*), align 8 +; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret i32 [[RES]] ; %res = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %a0, <2 x i64> %a1) ; [#uses=1] @@ -299,7 +299,7 @@ define <2 x double> @test_x86_sse41_round_pd(<2 x double> %a0) #0 { ; CHECK-LABEL: @test_x86_sse41_round_pd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 @@ -309,7 +309,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse41.round.pd(<2 x double> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <2 x i64> zeroinitializer, <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; %res = call <2 x double> @llvm.x86.sse41.round.pd(<2 x double> %a0, i32 7) ; <<2 x double>> [#uses=1] @@ -320,7 +320,7 @@ define <4 x float> @test_x86_sse41_round_ps(<4 x float> %a0) #0 { ; CHECK-LABEL: @test_x86_sse41_round_ps( -; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to i128 ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 0 @@ -330,7 +330,7 @@ ; CHECK-NEXT: unreachable ; CHECK: 4: ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> [[A0:%.*]], i32 7) -; CHECK-NEXT: store <4 x i32> zeroinitializer, <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; %res = call <4 x float> @llvm.x86.sse41.round.ps(<4 x float> %a0, i32 7) ; <<4 x float>> [#uses=1] @@ -341,12 +341,12 @@ define <2 x double> @test_x86_sse41_round_sd(<2 x double> %a0, <2 x double> %a1) #0 { ; CHECK-LABEL: @test_x86_sse41_round_sd( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> [[TMP2]], <2 x i32> ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1:%.*]], i32 7) -; CHECK-NEXT: store <2 x i64> [[TMP3]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; %res = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %a0, <2 x double> %a1, i32 7) ; <<2 x double>> [#uses=1] @@ -355,10 +355,10 @@ declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone -define <2 x double> @test_x86_sse41_round_sd_load(<2 x double> %a0, <2 x double>* %a1) #0 { +define <2 x double> @test_x86_sse41_round_sd_load(<2 x double> %a0, ptr %a1) #0 { ; CHECK-LABEL: @test_x86_sse41_round_sd_load( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <2 x i64>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] @@ -366,26 +366,26 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: 4: -; CHECK-NEXT: [[A1B:%.*]] = load <2 x double>, <2 x double>* [[A1:%.*]], align 16 -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <2 x double>* [[A1]] to i64 +; CHECK-NEXT: [[A1B:%.*]] = load <2 x double>, ptr [[A1:%.*]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A1]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to <2 x i64>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, <2 x i64>* [[TMP7]], align 16 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16 ; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> [[_MSLD]], <2 x i32> ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> [[A0:%.*]], <2 x double> [[A1B]], i32 7) -; CHECK-NEXT: store <2 x i64> [[TMP8]], <2 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <2 x i64>*), align 8 +; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <2 x double> [[RES]] ; - %a1b = load <2 x double>, <2 x double>* %a1 + %a1b = load <2 x double>, ptr %a1 %res = call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %a0, <2 x double> %a1b, i32 7) ; <<2 x double>> [#uses=1] ret <2 x double> %res } -define <4 x float> @test_x86_sse41_round_ss_load(<4 x float> %a0, <4 x float>* %a1) #0 { +define <4 x float> @test_x86_sse41_round_ss_load(<4 x float> %a0, ptr %a1) #0 { ; CHECK-LABEL: @test_x86_sse41_round_ss_load( -; CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* inttoptr (i64 add (i64 ptrtoint ([100 x i64]* @__msan_param_tls to i64), i64 16) to i64*), align 8 -; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i32>*), align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8 ; CHECK-NEXT: call void @llvm.donothing() ; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]] @@ -393,17 +393,17 @@ ; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]] ; CHECK-NEXT: unreachable ; CHECK: 4: -; CHECK-NEXT: [[A1B:%.*]] = load <4 x float>, <4 x float>* [[A1:%.*]], align 16 -; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint <4 x float>* [[A1]] to i64 +; CHECK-NEXT: [[A1B:%.*]] = load <4 x float>, ptr [[A1:%.*]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A1]] to i64 ; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 -; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to <4 x i32>* -; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP7]], align 16 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16 ; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[_MSLD]], <4 x i32> ; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> [[A0:%.*]], <4 x float> [[A1B]], i32 7) -; CHECK-NEXT: store <4 x i32> [[TMP8]], <4 x i32>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i32>*), align 8 +; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr @__msan_retval_tls, align 8 ; CHECK-NEXT: ret <4 x float> [[RES]] ; - %a1b = load <4 x float>, <4 x float>* %a1 + %a1b = load <4 x float>, ptr %a1 %res = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %a0, <4 x float> %a1b, i32 7) ; <<4 x float>> [#uses=1] ret <4 x float> %res } diff --git a/llvm/test/Instrumentation/MemorySanitizer/store-long-origin.ll b/llvm/test/Instrumentation/MemorySanitizer/store-long-origin.ll --- a/llvm/test/Instrumentation/MemorySanitizer/store-long-origin.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/store-long-origin.ll @@ -7,9 +7,9 @@ ; Test origin for longer stores. -define void @Store8(i64* nocapture %p, i64 %x) sanitize_memory { +define void @Store8(ptr nocapture %p, i64 %x) sanitize_memory { entry: - store i64 %x, i64* %p, align 8 + store i64 %x, ptr %p, align 8 ret void } @@ -20,9 +20,9 @@ ; CHECK: store i64 {{.*}}, align 8 ; CHECK: ret void -define void @Store8_align4(i64* nocapture %p, i64 %x) sanitize_memory { +define void @Store8_align4(ptr nocapture %p, i64 %x) sanitize_memory { entry: - store i64 %x, i64* %p, align 4 + store i64 %x, ptr %p, align 4 ret void } @@ -30,16 +30,16 @@ ; CHECK-LABEL: define void @Store8_align4( ; CHECK: store i64 {{.*}}, align 4 ; CHECK: store i32 {{.*}}, align 4 -; CHECK: getelementptr i32, i32* {{.*}}, i32 1 +; CHECK: getelementptr i32, ptr {{.*}}, i32 1 ; CHECK: store i32 {{.*}}, align 4 ; CHECK: store i64 {{.*}}, align 4 ; CHECK: ret void %struct.S = type { i32, i32, i32 } -define void @StoreAgg(%struct.S* nocapture %p, %struct.S %x) sanitize_memory { +define void @StoreAgg(ptr nocapture %p, %struct.S %x) sanitize_memory { entry: - store %struct.S %x, %struct.S* %p, align 4 + store %struct.S %x, ptr %p, align 4 ret void } @@ -47,17 +47,17 @@ ; CHECK-LABEL: define void @StoreAgg( ; CHECK: store { i32, i32, i32 } {{.*}}, align 4 ; CHECK: store i32 {{.*}}, align 4 -; CHECK: getelementptr i32, i32* {{.*}}, i32 1 +; CHECK: getelementptr i32, ptr {{.*}}, i32 1 ; CHECK: store i32 {{.*}}, align 4 -; CHECK: getelementptr i32, i32* {{.*}}, i32 2 +; CHECK: getelementptr i32, ptr {{.*}}, i32 2 ; CHECK: store i32 {{.*}}, align 4 ; CHECK: store %struct.S {{.*}}, align 4 ; CHECK: ret void -define void @StoreAgg8(%struct.S* nocapture %p, %struct.S %x) sanitize_memory { +define void @StoreAgg8(ptr nocapture %p, %struct.S %x) sanitize_memory { entry: - store %struct.S %x, %struct.S* %p, align 8 + store %struct.S %x, ptr %p, align 8 ret void } @@ -65,16 +65,16 @@ ; CHECK-LABEL: define void @StoreAgg8( ; CHECK: store { i32, i32, i32 } {{.*}}, align 8 ; CHECK: store i64 {{.*}}, align 8 -; CHECK: getelementptr i32, i32* {{.*}}, i32 2 +; CHECK: getelementptr i32, ptr {{.*}}, i32 2 ; CHECK: store i32 {{.*}}, align 8 ; CHECK: store %struct.S {{.*}}, align 8 ; CHECK: ret void %struct.Q = type { i64, i64, i64 } -define void @StoreAgg24(%struct.Q* nocapture %p, %struct.Q %x) sanitize_memory { +define void @StoreAgg24(ptr nocapture %p, %struct.Q %x) sanitize_memory { entry: - store %struct.Q %x, %struct.Q* %p, align 8 + store %struct.Q %x, ptr %p, align 8 ret void } @@ -82,9 +82,9 @@ ; CHECK-LABEL: define void @StoreAgg24( ; CHECK: store { i64, i64, i64 } {{.*}}, align 8 ; CHECK: store i64 {{.*}}, align 8 -; CHECK: getelementptr i64, i64* {{.*}}, i32 1 +; CHECK: getelementptr i64, ptr {{.*}}, i32 1 ; CHECK: store i64 {{.*}}, align 8 -; CHECK: getelementptr i64, i64* {{.*}}, i32 2 +; CHECK: getelementptr i64, ptr {{.*}}, i32 2 ; CHECK: store i64 {{.*}}, align 8 ; CHECK: store %struct.Q {{.*}}, align 8 ; CHECK: ret void diff --git a/llvm/test/Instrumentation/MemorySanitizer/store-origin.ll b/llvm/test/Instrumentation/MemorySanitizer/store-origin.ll --- a/llvm/test/Instrumentation/MemorySanitizer/store-origin.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/store-origin.ll @@ -10,11 +10,11 @@ ; Check that debug info for origin propagation code is set correctly. ; Function Attrs: nounwind -define void @Store(i32* nocapture %p, i32 %x) #0 !dbg !4 { +define void @Store(ptr nocapture %p, i32 %x) #0 !dbg !4 { entry: - tail call void @llvm.dbg.value(metadata i32* %p, i64 0, metadata !11, metadata !DIExpression()), !dbg !16 + tail call void @llvm.dbg.value(metadata ptr %p, i64 0, metadata !11, metadata !DIExpression()), !dbg !16 tail call void @llvm.dbg.value(metadata i32 %x, i64 0, metadata !12, metadata !DIExpression()), !dbg !16 - store i32 %x, i32* %p, align 4, !dbg !17, !tbaa !18 + store i32 %x, ptr %p, align 4, !dbg !17, !tbaa !18 ret void, !dbg !22 } @@ -58,9 +58,9 @@ ; CHECK-MSAN: [[ORIGIN:%[0-9a-z]+]] = load {{.*}} @__msan_param_origin_tls ; CHECK-KMSAN: %param_shadow -; CHECK-KMSAN: load i32, i32* +; CHECK-KMSAN: load i32, ptr ; CHECK-KMSAN: %param_origin -; CHECK-KMSAN: [[ORIGIN:%[0-9a-z]+]] = load i32, i32* +; CHECK-KMSAN: [[ORIGIN:%[0-9a-z]+]] = load i32, ptr ; CHECK: store {{.*}}!dbg ![[DBG:[0-9]+]] ; CHECK: icmp diff --git a/llvm/test/Instrumentation/MemorySanitizer/str-nobuiltin.ll b/llvm/test/Instrumentation/MemorySanitizer/str-nobuiltin.ll --- a/llvm/test/Instrumentation/MemorySanitizer/str-nobuiltin.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/str-nobuiltin.ll @@ -4,13 +4,13 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -declare i8* @memchr(i8* %a, i32 %b, i64 %c) -declare i32 @memcmp(i8* %a, i8* %b, i64 %c) -declare i32 @strcmp(i8* %a, i8* %b) -declare i8* @strcpy(i8* %a, i8* %b) -declare i8* @stpcpy(i8* %a, i8* %b) -declare i64 @strlen(i8* %a) -declare i64 @strnlen(i8* %a, i64 %b) +declare ptr @memchr(ptr %a, i32 %b, i64 %c) +declare i32 @memcmp(ptr %a, ptr %b, i64 %c) +declare i32 @strcmp(ptr %a, ptr %b) +declare ptr @strcpy(ptr %a, ptr %b) +declare ptr @stpcpy(ptr %a, ptr %b) +declare i64 @strlen(ptr %a) +declare i64 @strnlen(ptr %a, i64 %b) ; CHECK: call{{.*}}@memchr{{.*}} #[[ATTR:[0-9]+]] ; CHECK: call{{.*}}@memcmp{{.*}} #[[ATTR]] @@ -21,13 +21,13 @@ ; CHECK: call{{.*}}@strnlen{{.*}} #[[ATTR]] ; attributes #[[ATTR]] = { nobuiltin } -define void @f1(i8* %a, i8* %b) nounwind uwtable sanitize_memory { - tail call i8* @memchr(i8* %a, i32 1, i64 12) - tail call i32 @memcmp(i8* %a, i8* %b, i64 12) - tail call i32 @strcmp(i8* %a, i8* %b) - tail call i8* @strcpy(i8* %a, i8* %b) - tail call i8* @stpcpy(i8* %a, i8* %b) - tail call i64 @strlen(i8* %a) - tail call i64 @strnlen(i8* %a, i64 12) +define void @f1(ptr %a, ptr %b) nounwind uwtable sanitize_memory { + tail call ptr @memchr(ptr %a, i32 1, i64 12) + tail call i32 @memcmp(ptr %a, ptr %b, i64 12) + tail call i32 @strcmp(ptr %a, ptr %b) + tail call ptr @strcpy(ptr %a, ptr %b) + tail call ptr @stpcpy(ptr %a, ptr %b) + tail call i64 @strlen(ptr %a) + tail call i64 @strnlen(ptr %a, i64 12) ret void } diff --git a/llvm/test/Instrumentation/MemorySanitizer/unreachable.ll b/llvm/test/Instrumentation/MemorySanitizer/unreachable.ll --- a/llvm/test/Instrumentation/MemorySanitizer/unreachable.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/unreachable.ll @@ -5,12 +5,12 @@ ; Test that MemorySanitizer correctly handles unreachable blocks. -define i32 @Func(i32* %p) nounwind uwtable { +define i32 @Func(ptr %p) nounwind uwtable { entry: br label %exit unreachable: - %x = load i32, i32* %p + %x = load i32, ptr %p br label %exit exit: diff --git a/llvm/test/Instrumentation/MemorySanitizer/unsized_type.ll b/llvm/test/Instrumentation/MemorySanitizer/unsized_type.ll --- a/llvm/test/Instrumentation/MemorySanitizer/unsized_type.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/unsized_type.ll @@ -5,12 +5,12 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare token @llvm.coro.id(i32, i8* readnone, i8* nocapture readonly, i8*) +declare token @llvm.coro.id(i32, ptr readnone, ptr nocapture readonly, ptr) declare i1 @llvm.coro.alloc(token) define void @foo() sanitize_memory { entry: - %id = call token @llvm.coro.id(i32 0, i8* null, i8* null, i8* null) + %id = call token @llvm.coro.id(i32 0, ptr null, ptr null, ptr null) %dyn.alloc.reqd = call i1 @llvm.coro.alloc(token %id) ret void } diff --git a/llvm/test/Instrumentation/MemorySanitizer/with-call-type-size.ll b/llvm/test/Instrumentation/MemorySanitizer/with-call-type-size.ll --- a/llvm/test/Instrumentation/MemorySanitizer/with-call-type-size.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/with-call-type-size.ll @@ -90,9 +90,9 @@ ; CHECK: call void @__msan_warning_noreturn ; CHECK: ret <4 x i32> -declare <256 x i16> @llvm.masked.load.v256i16.p0v256i16(<256 x i16>*, i32, <256 x i1>, <256 x i16>) -define <256 x i16> @testCombine(<256 x i16>* %vec, <256 x i1> %mask) sanitize_memory { - %vec1 = call <256 x i16> @llvm.masked.load.v256i16.p0v256i16(<256 x i16>* %vec, i32 16, <256 x i1> %mask, <256 x i16> zeroinitializer) +declare <256 x i16> @llvm.masked.load.v256i16.p0(ptr, i32, <256 x i1>, <256 x i16>) +define <256 x i16> @testCombine(ptr %vec, <256 x i1> %mask) sanitize_memory { + %vec1 = call <256 x i16> @llvm.masked.load.v256i16.p0(ptr %vec, i32 16, <256 x i1> %mask, <256 x i16> zeroinitializer) ret <256 x i16> %vec1 } ; CHECK-LABEL: @testCombine( diff --git a/llvm/test/Instrumentation/PoisonChecking/ub-checks.ll b/llvm/test/Instrumentation/PoisonChecking/ub-checks.ll --- a/llvm/test/Instrumentation/PoisonChecking/ub-checks.ll +++ b/llvm/test/Instrumentation/PoisonChecking/ub-checks.ll @@ -5,75 +5,75 @@ ; a potential source of UB. The UB source is kept simple; we focus on the ; UB triggering instructions here. -define void @store(i8* %base, i32 %a) { +define void @store(ptr %base, i32 %a) { ; CHECK-LABEL: @store( ; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[A:%.*]], i32 1) ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[A]], 1 -; CHECK-NEXT: [[P:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i32 [[ADD]] +; CHECK-NEXT: [[P:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i32 [[ADD]] ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true ; CHECK-NEXT: call void @__poison_checker_assert(i1 [[TMP3]]) -; CHECK-NEXT: store i8 0, i8* [[P]] +; CHECK-NEXT: store i8 0, ptr [[P]] ; CHECK-NEXT: ret void ; %add = add nsw i32 %a, 1 - %p = getelementptr i8, i8* %base, i32 %add - store i8 0, i8* %p + %p = getelementptr i8, ptr %base, i32 %add + store i8 0, ptr %p ret void } -define void @load(i8* %base, i32 %a) { +define void @load(ptr %base, i32 %a) { ; CHECK-LABEL: @load( ; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[A:%.*]], i32 1) ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[A]], 1 -; CHECK-NEXT: [[P:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i32 [[ADD]] +; CHECK-NEXT: [[P:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i32 [[ADD]] ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true ; CHECK-NEXT: call void @__poison_checker_assert(i1 [[TMP3]]) -; CHECK-NEXT: [[TMP4:%.*]] = load volatile i8, i8* [[P]] +; CHECK-NEXT: [[TMP4:%.*]] = load volatile i8, ptr [[P]] ; CHECK-NEXT: ret void ; %add = add nsw i32 %a, 1 - %p = getelementptr i8, i8* %base, i32 %add - load volatile i8, i8* %p + %p = getelementptr i8, ptr %base, i32 %add + load volatile i8, ptr %p ret void } -define void @atomicrmw(i8* %base, i32 %a) { +define void @atomicrmw(ptr %base, i32 %a) { ; CHECK-LABEL: @atomicrmw( ; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[A:%.*]], i32 1) ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[A]], 1 -; CHECK-NEXT: [[P:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i32 [[ADD]] +; CHECK-NEXT: [[P:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i32 [[ADD]] ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true ; CHECK-NEXT: call void @__poison_checker_assert(i1 [[TMP3]]) -; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw add i8* [[P]], i8 1 seq_cst +; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw add ptr [[P]], i8 1 seq_cst ; CHECK-NEXT: ret void ; %add = add nsw i32 %a, 1 - %p = getelementptr i8, i8* %base, i32 %add - atomicrmw add i8* %p, i8 1 seq_cst + %p = getelementptr i8, ptr %base, i32 %add + atomicrmw add ptr %p, i8 1 seq_cst ret void } -define void @cmpxchg(i8* %base, i32 %a) { +define void @cmpxchg(ptr %base, i32 %a) { ; CHECK-LABEL: @cmpxchg( ; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 [[A:%.*]], i32 1) ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[A]], 1 -; CHECK-NEXT: [[P:%.*]] = getelementptr i8, i8* [[BASE:%.*]], i32 [[ADD]] +; CHECK-NEXT: [[P:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i32 [[ADD]] ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true ; CHECK-NEXT: call void @__poison_checker_assert(i1 [[TMP3]]) -; CHECK-NEXT: [[TMP4:%.*]] = cmpxchg i8* [[P]], i8 1, i8 0 seq_cst seq_cst +; CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr [[P]], i8 1, i8 0 seq_cst seq_cst ; CHECK-NEXT: ret void ; %add = add nsw i32 %a, 1 - %p = getelementptr i8, i8* %base, i32 %add - cmpxchg i8* %p, i8 1, i8 0 seq_cst seq_cst + %p = getelementptr i8, ptr %base, i32 %add + cmpxchg ptr %p, i8 1, i8 0 seq_cst seq_cst ret void } -define i32 @udiv(i8* %base, i32 %a) { +define i32 @udiv(ptr %base, i32 %a) { ; CHECK-LABEL: @udiv( ; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[A:%.*]], i32 1) ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1 @@ -88,7 +88,7 @@ ret i32 %res } -define i32 @sdiv(i8* %base, i32 %a) { +define i32 @sdiv(ptr %base, i32 %a) { ; CHECK-LABEL: @sdiv( ; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[A:%.*]], i32 1) ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1 @@ -103,7 +103,7 @@ ret i32 %res } -define i32 @urem(i8* %base, i32 %a) { +define i32 @urem(ptr %base, i32 %a) { ; CHECK-LABEL: @urem( ; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[A:%.*]], i32 1) ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1 @@ -118,7 +118,7 @@ ret i32 %res } -define i32 @srem(i8* %base, i32 %a) { +define i32 @srem(ptr %base, i32 %a) { ; CHECK-LABEL: @srem( ; CHECK-NEXT: [[TMP1:%.*]] = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 [[A:%.*]], i32 1) ; CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1 diff --git a/llvm/test/Instrumentation/SanitizerCoverage/backedge-pruning.ll b/llvm/test/Instrumentation/SanitizerCoverage/backedge-pruning.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/backedge-pruning.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/backedge-pruning.ll @@ -5,7 +5,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define dso_local void @foo(i32* nocapture readnone %a, i32 %n) local_unnamed_addr { +define dso_local void @foo(ptr nocapture readnone %a, i32 %n) local_unnamed_addr { entry: br label %do.body diff --git a/llvm/test/Instrumentation/SanitizerCoverage/control-flow.ll b/llvm/test/Instrumentation/SanitizerCoverage/control-flow.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/control-flow.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/control-flow.ll @@ -5,12 +5,12 @@ target triple = "x86_64-unknown-linux-gnu" define void @foo(ptr %a) sanitize_address { entry: - %tobool = icmp eq i32* %a, null + %tobool = icmp eq ptr %a, null br i1 %tobool, label %if.end, label %if.then if.then: ; preds = %entry - store i32 0, i32* %a, align 4 - call void @foo(i32* %a) + store i32 0, ptr %a, align 4 + call void @foo(ptr %a) br label %if.end if.end: ; preds = %entry, %if.then diff --git a/llvm/test/Instrumentation/SanitizerCoverage/coverage-dbg.ll b/llvm/test/Instrumentation/SanitizerCoverage/coverage-dbg.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/coverage-dbg.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/coverage-dbg.ll @@ -15,7 +15,7 @@ ; and add sanitize_address to @_ZN1A1fEv ; Test that __sanitizer_cov_trace_pc_guard call has !dbg pointing to the opening { of A::f(). -; CHECK: call void @__sanitizer_cov_trace_pc_guard(i32*{{.*}}) #{{.*}}, !dbg [[A:!.*]] +; CHECK: call void @__sanitizer_cov_trace_pc_guard(ptr{{.*}}) #{{.*}}, !dbg [[A:!.*]] ; CHECK: [[A]] = !DILocation(line: 6, scope: !{{.*}}) @@ -25,11 +25,10 @@ %struct.A = type { i32 } ; Function Attrs: nounwind readonly uwtable -define i32 @_ZN1A1fEv(%struct.A* nocapture readonly %this) #0 align 2 !dbg !13 { +define i32 @_ZN1A1fEv(ptr nocapture readonly %this) #0 align 2 !dbg !13 { entry: - tail call void @llvm.dbg.value(metadata %struct.A* %this, i64 0, metadata !15, metadata !DIExpression()), !dbg !20 - %x = getelementptr inbounds %struct.A, %struct.A* %this, i64 0, i32 0, !dbg !21 - %0 = load i32, i32* %x, align 4, !dbg !21 + tail call void @llvm.dbg.value(metadata ptr %this, i64 0, metadata !15, metadata !DIExpression()), !dbg !20 + %0 = load i32, ptr %this, align 4, !dbg !21 ret i32 %0, !dbg !21 } diff --git a/llvm/test/Instrumentation/SanitizerCoverage/coverage.ll b/llvm/test/Instrumentation/SanitizerCoverage/coverage.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/coverage.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/coverage.ll @@ -4,31 +4,31 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define void @foo(i32* %a) sanitize_address { +define void @foo(ptr %a) sanitize_address { entry: - %tobool = icmp eq i32* %a, null + %tobool = icmp eq ptr %a, null br i1 %tobool, label %if.end, label %if.then if.then: ; preds = %entry - store i32 0, i32* %a, align 4 + store i32 0, ptr %a, align 4 br label %if.end if.end: ; preds = %entry, %if.then ret void } -; CHECK0-NOT: @llvm.global_ctors = {{.*}}{ i32 2, void ()* @sancov.module_ctor } -; CHECK1: @llvm.global_ctors = {{.*}}{ i32 2, void ()* @sancov.module_ctor, i8* null } -; CHECK2: @llvm.global_ctors = {{.*}}{ i32 2, void ()* @sancov.module_ctor, i8* null } +; CHECK0-NOT: @llvm.global_ctors = {{.*}}{ i32 2, ptr @sancov.module_ctor } +; CHECK1: @llvm.global_ctors = {{.*}}{ i32 2, ptr @sancov.module_ctor, ptr null } +; CHECK2: @llvm.global_ctors = {{.*}}{ i32 2, ptr @sancov.module_ctor, ptr null } ; CHECK0-NOT: call void @__sanitizer_cov( ; CHECK0-NOT: call void @__sanitizer_cov_module_init( ; CHECK1-LABEL: define void @foo -; CHECK1: %0 = load atomic i32, i32* {{.*}} monotonic, align 4, !nosanitize +; CHECK1: %0 = load atomic i32, ptr {{.*}} monotonic, align 4, !nosanitize ; CHECK1: %1 = icmp sge i32 0, %0 ; CHECK1: br i1 %1, label %2, label %3 -; CHECK1: call void @__sanitizer_cov(i32*{{.*}}) +; CHECK1: call void @__sanitizer_cov(ptr{{.*}}) ; CHECK1: call void asm sideeffect "", ""() ; CHECK1-NOT: call void @__sanitizer_cov ; CHECK1: ret void @@ -68,15 +68,14 @@ ; CHECK3-NOT: call void @__sanitizer_cov ; CHECK3: ret void -%struct.StructWithVptr = type { i32 (...)** } +%struct.StructWithVptr = type { ptr } -define void @CallViaVptr(%struct.StructWithVptr* %foo) uwtable sanitize_address { +define void @CallViaVptr(ptr %foo) uwtable sanitize_address { entry: - %0 = bitcast %struct.StructWithVptr* %foo to void (%struct.StructWithVptr*)*** - %vtable = load void (%struct.StructWithVptr*)**, void (%struct.StructWithVptr*)*** %0, align 8 - %1 = load void (%struct.StructWithVptr*)*, void (%struct.StructWithVptr*)** %vtable, align 8 - tail call void %1(%struct.StructWithVptr* %foo) - tail call void %1(%struct.StructWithVptr* %foo) + %vtable = load ptr, ptr %foo, align 8 + %0 = load ptr, ptr %vtable, align 8 + tail call void %0(ptr %foo) + tail call void %0(ptr %foo) tail call void asm sideeffect "", ""() ret void } diff --git a/llvm/test/Instrumentation/SanitizerCoverage/coverage2-dbg.ll b/llvm/test/Instrumentation/SanitizerCoverage/coverage2-dbg.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/coverage2-dbg.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/coverage2-dbg.ll @@ -17,20 +17,20 @@ ; Check that __sanitizer_cov call has !dgb pointing to the beginning ; of appropriate basic blocks. ; CHECK-LABEL:_Z3fooPi -; CHECK: call void @__sanitizer_cov{{.*}}(i32*{{.*}}) #{{.*}}, !dbg [[A:!.*]] -; CHECK: call void @__sanitizer_cov{{.*}}(i32*{{.*}}) #{{.*}}, !dbg [[B:!.*]] +; CHECK: call void @__sanitizer_cov{{.*}}(ptr{{.*}}) #{{.*}}, !dbg [[A:!.*]] +; CHECK: call void @__sanitizer_cov{{.*}}(ptr{{.*}}) #{{.*}}, !dbg [[B:!.*]] ; CHECK: ret void ; CHECK: [[A]] = !DILocation(line: 1, scope: !{{.*}}) ; CHECK: [[B]] = !DILocation(line: 3, column: 5, scope: !{{.*}}) -define void @_Z3fooPi(i32* %a) #0 !dbg !4 { +define void @_Z3fooPi(ptr %a) #0 !dbg !4 { entry: - tail call void @llvm.dbg.value(metadata i32* %a, i64 0, metadata !11, metadata !DIExpression()), !dbg !15 - %tobool = icmp eq i32* %a, null, !dbg !16 + tail call void @llvm.dbg.value(metadata ptr %a, i64 0, metadata !11, metadata !DIExpression()), !dbg !15 + %tobool = icmp eq ptr %a, null, !dbg !16 br i1 %tobool, label %if.end, label %if.then, !dbg !16 if.then: ; preds = %entry - store i32 0, i32* %a, align 4, !dbg !18, !tbaa !19 + store i32 0, ptr %a, align 4, !dbg !18, !tbaa !19 br label %if.end, !dbg !18 if.end: ; preds = %entry, %if.then diff --git a/llvm/test/Instrumentation/SanitizerCoverage/gep-tracing.ll b/llvm/test/Instrumentation/SanitizerCoverage/gep-tracing.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/gep-tracing.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/gep-tracing.ll @@ -4,37 +4,37 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define void @gep_1(i32* nocapture %a, i32 %i) { +define void @gep_1(ptr nocapture %a, i32 %i) { entry: %idxprom = sext i32 %i to i64 - %arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom - store i32 0, i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, ptr %a, i64 %idxprom + store i32 0, ptr %arrayidx, align 4 ret void } -; CHECK-LABEL: define void @gep_1(i32* nocapture %a, i32 %i) +; CHECK-LABEL: define void @gep_1(ptr nocapture %a, i32 %i) ; CHECK: call void @__sanitizer_cov_trace_gep(i64 %idxprom) ; CHECK: ret void -define void @gep_2([1000 x i32]* nocapture %a, i32 %i, i32 %j) { +define void @gep_2(ptr nocapture %a, i32 %i, i32 %j) { entry: %idxprom = sext i32 %j to i64 %idxprom1 = sext i32 %i to i64 - %arrayidx2 = getelementptr inbounds [1000 x i32], [1000 x i32]* %a, i64 %idxprom1, i64 %idxprom - store i32 0, i32* %arrayidx2, align 4 + %arrayidx2 = getelementptr inbounds [1000 x i32], ptr %a, i64 %idxprom1, i64 %idxprom + store i32 0, ptr %arrayidx2, align 4 ret void } -; CHECK-LABEL: define void @gep_2([1000 x i32]* nocapture %a, i32 %i, i32 %j) +; CHECK-LABEL: define void @gep_2(ptr nocapture %a, i32 %i, i32 %j) ; CHECK: call void @__sanitizer_cov_trace_gep(i64 %idxprom1) ; CHECK: call void @__sanitizer_cov_trace_gep(i64 %idxprom) ; CHECK: ret void ; Just make sure we don't insturment this one and don't crash -define void @gep_3(<2 x i8*> %a, i32 %i, i32 %j) { +define void @gep_3(<2 x ptr> %a, i32 %i, i32 %j) { entry: - %0 = getelementptr i8, <2 x i8*> %a, <2 x i64> + %0 = getelementptr i8, <2 x ptr> %a, <2 x i64> ret void } diff --git a/llvm/test/Instrumentation/SanitizerCoverage/opaque-ptr.ll b/llvm/test/Instrumentation/SanitizerCoverage/opaque-ptr.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/opaque-ptr.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/opaque-ptr.ll @@ -9,7 +9,7 @@ ; CHECK: @[[LLVM_GLOBAL_CTORS:[a-zA-Z0-9_$"\\.-]+]] = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 2, ptr @sancov.module_ctor_trace_pc_guard, ptr @sancov.module_ctor_trace_pc_guard }] ; CHECK: @[[LLVM_COMPILER_USED:[a-zA-Z0-9_$"\\.-]+]] = appending global [1 x ptr] [ptr @__sancov_gen_], section "llvm.metadata" ;. -define void @foo(i32* %a) { +define void @foo(ptr %a) { ; CHECK-LABEL: @foo( ; CHECK-NEXT: call void @__sanitizer_cov_trace_pc_guard(ptr @__sancov_gen_) #[[ATTR1:[0-9]+]] ; CHECK-NEXT: ret void diff --git a/llvm/test/Instrumentation/SanitizerCoverage/pc-table.ll b/llvm/test/Instrumentation/SanitizerCoverage/pc-table.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/pc-table.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/pc-table.ll @@ -5,20 +5,20 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define void @foo(i32* %a) sanitize_address { +define void @foo(ptr %a) sanitize_address { entry: - %tobool = icmp eq i32* %a, null + %tobool = icmp eq ptr %a, null br i1 %tobool, label %if.end, label %if.then if.then: ; preds = %entry - store i32 0, i32* %a, align 4 + store i32 0, ptr %a, align 4 br label %if.end if.end: ; preds = %entry, %if.then ret void } -; CHECK: private constant [6 x i64*] [i64* bitcast (void (i32*)* @foo to i64*), i64* inttoptr (i64 1 to i64*), i64* bitcast (i8* blockaddress(@foo, %entry.if.end_crit_edge) to i64*), i64* null, i64* bitcast (i8* blockaddress(@foo, %if.then) to i64*), i64* null], section "__sancov_pcs", comdat($foo), align 8 +; CHECK: private constant [6 x ptr] [ptr @foo, ptr inttoptr (i64 1 to ptr), ptr blockaddress(@foo, %entry.if.end_crit_edge), ptr null, ptr blockaddress(@foo, %if.then), ptr null], section "__sancov_pcs", comdat($foo), align 8 ; CHECK: @__start___sancov_pcs = extern_weak hidden global i64 ; CHECK-NEXT: @__stop___sancov_pcs = extern_weak hidden global i64 ; CHECK: define internal void @sancov.module_ctor diff --git a/llvm/test/Instrumentation/SanitizerCoverage/seh.ll b/llvm/test/Instrumentation/SanitizerCoverage/seh.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/seh.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/seh.ll @@ -5,77 +5,74 @@ target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" target triple = "i686-pc-windows-msvc18.0.0" -declare i32 @llvm.eh.typeid.for(i8*) #2 -declare i8* @llvm.frameaddress(i32) -declare i8* @llvm.eh.recoverfp(i8*, i8*) -declare i8* @llvm.localrecover(i8*, i8*, i32) +declare i32 @llvm.eh.typeid.for(ptr) #2 +declare ptr @llvm.frameaddress(i32) +declare ptr @llvm.eh.recoverfp(ptr, ptr) +declare ptr @llvm.localrecover(ptr, ptr, i32) declare void @llvm.localescape(...) #1 declare i32 @_except_handler3(...) -declare void @may_throw(i32* %r) +declare void @may_throw(ptr %r) -define i32 @main() sanitize_address personality i8* bitcast (i32 (...)* @_except_handler3 to i8*) { +define i32 @main() sanitize_address personality ptr @_except_handler3 { entry: %r = alloca i32, align 4 %__exception_code = alloca i32, align 4 - call void (...) @llvm.localescape(i32* nonnull %__exception_code) - %0 = bitcast i32* %r to i8* - store i32 0, i32* %r, align 4 - invoke void @may_throw(i32* nonnull %r) #4 + call void (...) @llvm.localescape(ptr nonnull %__exception_code) + store i32 0, ptr %r, align 4 + invoke void @may_throw(ptr nonnull %r) #4 to label %__try.cont unwind label %lpad lpad: ; preds = %entry - %1 = landingpad { i8*, i32 } - catch i8* bitcast (i32 ()* @"\01?filt$0@0@main@@" to i8*) - %2 = extractvalue { i8*, i32 } %1, 1 - %3 = call i32 @llvm.eh.typeid.for(i8* bitcast (i32 ()* @"\01?filt$0@0@main@@" to i8*)) #1 - %matches = icmp eq i32 %2, %3 + %0 = landingpad { ptr, i32 } + catch ptr @"\01?filt$0@0@main@@" + %1 = extractvalue { ptr, i32 } %0, 1 + %2 = call i32 @llvm.eh.typeid.for(ptr @"\01?filt$0@0@main@@") #1 + %matches = icmp eq i32 %1, %2 br i1 %matches, label %__except, label %eh.resume __except: ; preds = %lpad - store i32 1, i32* %r, align 4 + store i32 1, ptr %r, align 4 br label %__try.cont __try.cont: ; preds = %entry, %__except - %4 = load i32, i32* %r, align 4 - ret i32 %4 + %3 = load i32, ptr %r, align 4 + ret i32 %3 eh.resume: ; preds = %lpad - resume { i8*, i32 } %1 + resume { ptr, i32 } %0 } ; Check that we don't do any instrumentation. ; CHECK-LABEL: define i32 @main() -; CHECK-NOT: load atomic i32, i32* {{.*}} monotonic, align 4, !nosanitize +; CHECK-NOT: load atomic i32, ptr {{.*}} monotonic, align 4, !nosanitize ; CHECK-NOT: call void @__sanitizer_cov ; CHECK: ret i32 ; Function Attrs: nounwind define internal i32 @"\01?filt$0@0@main@@"() #1 { entry: - %0 = tail call i8* @llvm.frameaddress(i32 1) - %1 = tail call i8* @llvm.eh.recoverfp(i8* bitcast (i32 ()* @main to i8*), i8* %0) - %2 = tail call i8* @llvm.localrecover(i8* bitcast (i32 ()* @main to i8*), i8* %1, i32 0) - %__exception_code = bitcast i8* %2 to i32* - %3 = getelementptr inbounds i8, i8* %0, i32 -20 - %4 = bitcast i8* %3 to { i32*, i8* }** - %5 = load { i32*, i8* }*, { i32*, i8* }** %4, align 4 - %6 = getelementptr inbounds { i32*, i8* }, { i32*, i8* }* %5, i32 0, i32 0 - %7 = load i32*, i32** %6, align 4 - %8 = load i32, i32* %7, align 4 - store i32 %8, i32* %__exception_code, align 4 + %0 = tail call ptr @llvm.frameaddress(i32 1) + %1 = tail call ptr @llvm.eh.recoverfp(ptr @main, ptr %0) + %2 = tail call ptr @llvm.localrecover(ptr @main, ptr %1, i32 0) + %3 = getelementptr inbounds i8, ptr %0, i32 -20 + %4 = load ptr, ptr %3, align 4 + %5 = getelementptr inbounds { ptr, ptr }, ptr %4, i32 0, i32 0 + %6 = load ptr, ptr %5, align 4 + %7 = load i32, ptr %6, align 4 + store i32 %7, ptr %2, align 4 ret i32 1 } ; CHECK-LABEL: define internal i32 @"\01?filt$0@0@main@@"() -; CHECK: tail call i8* @llvm.localrecover(i8* bitcast (i32 ()* @main to i8*), i8* {{.*}}, i32 0) +; CHECK: tail call ptr @llvm.localrecover(ptr @main, ptr {{.*}}, i32 0) -define void @ScaleFilterCols_SSSE3(i8* %dst_ptr, i8* %src_ptr, i32 %dst_width, i32 %x, i32 %dx) sanitize_address { +define void @ScaleFilterCols_SSSE3(ptr %dst_ptr, ptr %src_ptr, i32 %dst_width, i32 %x, i32 %dx) sanitize_address { entry: %dst_width.addr = alloca i32, align 4 - store i32 %dst_width, i32* %dst_width.addr, align 4 - %0 = call { i8*, i8*, i32, i32, i32 } asm sideeffect "", "=r,=r,={ax},=r,=r,=*rm,rm,rm,0,1,2,3,4,5,~{memory},~{cc},~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{dirflag},~{fpsr},~{flags}"(i32* elementtype(i32) nonnull %dst_width.addr, i32 %x, i32 %dx, i8* %dst_ptr, i8* %src_ptr, i32 0, i32 0, i32 0, i32 %dst_width) + store i32 %dst_width, ptr %dst_width.addr, align 4 + %0 = call { ptr, ptr, i32, i32, i32 } asm sideeffect "", "=r,=r,={ax},=r,=r,=*rm,rm,rm,0,1,2,3,4,5,~{memory},~{cc},~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) nonnull %dst_width.addr, i32 %x, i32 %dx, ptr %dst_ptr, ptr %src_ptr, i32 0, i32 0, i32 0, i32 %dst_width) ret void } diff --git a/llvm/test/Instrumentation/SanitizerCoverage/stack-depth.ll b/llvm/test/Instrumentation/SanitizerCoverage/stack-depth.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/stack-depth.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/stack-depth.ll @@ -14,7 +14,7 @@ define i32 @foo() { entry: ; CHECK-LABEL: define i32 @foo -; CHECK-NOT: call i8* @llvm.frameaddress.p0i8(i32 0) +; CHECK-NOT: call ptr @llvm.frameaddress.p0(i32 0) ; CHECK-NOT: @__sancov_lowest_stack ; CHECK: ret i32 7 @@ -24,13 +24,13 @@ define i32 @bar() { entry: ; CHECK-LABEL: define i32 @bar -; CHECK: [[framePtr:%[^ \t]+]] = call i8* @llvm.frameaddress.p0i8(i32 0) -; CHECK: [[frameInt:%[^ \t]+]] = ptrtoint i8* [[framePtr]] to [[intType:i[0-9]+]] -; CHECK: [[lowest:%[^ \t]+]] = load [[intType]], [[intType]]* @__sancov_lowest_stack +; CHECK: [[framePtr:%[^ \t]+]] = call ptr @llvm.frameaddress.p0(i32 0) +; CHECK: [[frameInt:%[^ \t]+]] = ptrtoint ptr [[framePtr]] to [[intType:i[0-9]+]] +; CHECK: [[lowest:%[^ \t]+]] = load [[intType]], ptr @__sancov_lowest_stack ; CHECK: [[cmp:%[^ \t]+]] = icmp ult [[intType]] [[frameInt]], [[lowest]] ; CHECK: br i1 [[cmp]], label %[[ifLabel:[^ \t]+]], label ; CHECK: [[ifLabel]]: -; CHECK: store [[intType]] [[frameInt]], [[intType]]* @__sancov_lowest_stack +; CHECK: store [[intType]] [[frameInt]], ptr @__sancov_lowest_stack ; CHECK: %call = call i32 @foo() ; CHECK: ret i32 %call @@ -38,6 +38,6 @@ ret i32 %call } -define weak_odr hidden i64* @_ZTW21__sancov_lowest_stack() { - ret i64* @__sancov_lowest_stack +define weak_odr hidden ptr @_ZTW21__sancov_lowest_stack() { + ret ptr @__sancov_lowest_stack } diff --git a/llvm/test/Instrumentation/SanitizerCoverage/trace-loads-stores.ll b/llvm/test/Instrumentation/SanitizerCoverage/trace-loads-stores.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/trace-loads-stores.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/trace-loads-stores.ll @@ -4,30 +4,30 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define void @foo(i8* %p1, i16* %p2, i32* %p4, i64* %p8, i128* %p16) { +define void @foo(ptr %p1, ptr %p2, ptr %p4, ptr %p8, ptr %p16) { ; =================== loads - %1 = load i8, i8* %p1 - %2 = load i16, i16* %p2 - %3 = load i32, i32* %p4 - %4 = load i64, i64* %p8 - %5 = load i128, i128* %p16 -; LOADS: call void @__sanitizer_cov_load1(i8* %p1) -; LOADS: call void @__sanitizer_cov_load2(i16* %p2) -; LOADS: call void @__sanitizer_cov_load4(i32* %p4) -; LOADS: call void @__sanitizer_cov_load8(i64* %p8) -; LOADS: call void @__sanitizer_cov_load16(i128* %p16) + %1 = load i8, ptr %p1 + %2 = load i16, ptr %p2 + %3 = load i32, ptr %p4 + %4 = load i64, ptr %p8 + %5 = load i128, ptr %p16 +; LOADS: call void @__sanitizer_cov_load1(ptr %p1) +; LOADS: call void @__sanitizer_cov_load2(ptr %p2) +; LOADS: call void @__sanitizer_cov_load4(ptr %p4) +; LOADS: call void @__sanitizer_cov_load8(ptr %p8) +; LOADS: call void @__sanitizer_cov_load16(ptr %p16) ; =================== stores - store i8 %1, i8* %p1 - store i16 %2, i16* %p2 - store i32 %3, i32* %p4 - store i64 %4, i64* %p8 - store i128 %5, i128* %p16 -; STORES: call void @__sanitizer_cov_store1(i8* %p1) -; STORES: call void @__sanitizer_cov_store2(i16* %p2) -; STORES: call void @__sanitizer_cov_store4(i32* %p4) -; STORES: call void @__sanitizer_cov_store8(i64* %p8) -; STORES: call void @__sanitizer_cov_store16(i128* %p16) + store i8 %1, ptr %p1 + store i16 %2, ptr %p2 + store i32 %3, ptr %p4 + store i64 %4, ptr %p8 + store i128 %5, ptr %p16 +; STORES: call void @__sanitizer_cov_store1(ptr %p1) +; STORES: call void @__sanitizer_cov_store2(ptr %p2) +; STORES: call void @__sanitizer_cov_store4(ptr %p4) +; STORES: call void @__sanitizer_cov_store8(ptr %p8) +; STORES: call void @__sanitizer_cov_store16(ptr %p16) ret void } diff --git a/llvm/test/Instrumentation/SanitizerCoverage/trace-pc-guard.ll b/llvm/test/Instrumentation/SanitizerCoverage/trace-pc-guard.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/trace-pc-guard.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/trace-pc-guard.ll @@ -20,24 +20,24 @@ ; WIN-NEXT: @__sancov_gen_.1 = private global [1 x i32] zeroinitializer, section ".SCOV$GM", comdat($CallViaVptr), align 4{{$}} ; WIN-NEXT: @__sancov_gen_.2 = private global [1 x i32] zeroinitializer, section ".SCOV$GM", comdat($DirectBitcastCall), align 4{{$}} -; ELF: @llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @sancov.module_ctor_trace_pc_guard to i8*)] -; ELF: @llvm.compiler.used = appending global [3 x i8*] [i8* bitcast ([3 x i32]* @__sancov_gen_ to i8*), i8* bitcast ([1 x i32]* @__sancov_gen_.1 to i8*), i8* bitcast ([1 x i32]* @__sancov_gen_.2 to i8*)], section "llvm.metadata" -; MACHO: @llvm.used = appending global [4 x i8*] [i8* bitcast (void ()* @sancov.module_ctor_trace_pc_guard to i8*), i8* bitcast ([3 x i32]* @__sancov_gen_ to i8*), i8* bitcast ([1 x i32]* @__sancov_gen_.1 to i8*), i8* bitcast ([1 x i32]* @__sancov_gen_.2 to i8*)] +; ELF: @llvm.used = appending global [1 x ptr] [ptr @sancov.module_ctor_trace_pc_guard] +; ELF: @llvm.compiler.used = appending global [3 x ptr] [ptr @__sancov_gen_, ptr @__sancov_gen_.1, ptr @__sancov_gen_.2], section "llvm.metadata" +; MACHO: @llvm.used = appending global [4 x ptr] [ptr @sancov.module_ctor_trace_pc_guard, ptr @__sancov_gen_, ptr @__sancov_gen_.1, ptr @__sancov_gen_.2] ; MACHO-NOT: @llvm.compiler.used = -; WIN: @llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @sancov.module_ctor_trace_pc_guard to i8*)], section "llvm.metadata" -; WIN-NEXT: @llvm.compiler.used = appending global [3 x i8*] [i8* bitcast ([3 x i32]* @__sancov_gen_ to i8*), i8* bitcast ([1 x i32]* @__sancov_gen_.1 to i8*), i8* bitcast ([1 x i32]* @__sancov_gen_.2 to i8*)], section "llvm.metadata" +; WIN: @llvm.used = appending global [1 x ptr] [ptr @sancov.module_ctor_trace_pc_guard], section "llvm.metadata" +; WIN-NEXT: @llvm.compiler.used = appending global [3 x ptr] [ptr @__sancov_gen_, ptr @__sancov_gen_.1, ptr @__sancov_gen_.2], section "llvm.metadata" ; CHECK-LABEL: define void @foo ; CHECK: call void @__sanitizer_cov_trace_pc ; CHECK: ret void -define void @foo(i32* %a) sanitize_address { +define void @foo(ptr %a) sanitize_address { entry: - %tobool = icmp eq i32* %a, null + %tobool = icmp eq ptr %a, null br i1 %tobool, label %if.end, label %if.then if.then: ; preds = %entry - store i32 0, i32* %a, align 4 + store i32 0, ptr %a, align 4 br label %if.end if.end: ; preds = %entry, %if.then @@ -49,28 +49,27 @@ ; CHECK: call void @__sanitizer_cov_trace_pc_indir ; CHECK: ret void -%struct.StructWithVptr = type { i32 (...)** } +%struct.StructWithVptr = type { ptr } -define void @CallViaVptr(%struct.StructWithVptr* %foo) uwtable sanitize_address { +define void @CallViaVptr(ptr %foo) uwtable sanitize_address { entry: - %0 = bitcast %struct.StructWithVptr* %foo to void (%struct.StructWithVptr*)*** - %vtable = load void (%struct.StructWithVptr*)**, void (%struct.StructWithVptr*)*** %0, align 8 - %1 = load void (%struct.StructWithVptr*)*, void (%struct.StructWithVptr*)** %vtable, align 8 - tail call void %1(%struct.StructWithVptr* %foo) - tail call void %1(%struct.StructWithVptr* %foo) + %vtable = load ptr, ptr %foo, align 8 + %0 = load ptr, ptr %vtable, align 8 + tail call void %0(ptr %foo) + tail call void %0(ptr %foo) tail call void asm sideeffect "", ""() ret void } ; CHECK-LABEL: define void @DirectBitcastCall ; CHECK-NEXT: call void @__sanitizer_cov_trace_pc_guard -; CHECK-NEXT: call void bitcast (i32 ()* @direct_callee to void ()*)() +; CHECK-NEXT: call void @direct_callee() ; CHECK-NEXT: ret void declare i32 @direct_callee() define void @DirectBitcastCall() sanitize_address { - call void bitcast (i32 ()* @direct_callee to void ()*)() + call void @direct_callee() ret void } diff --git a/llvm/test/Instrumentation/SanitizerCoverage/tracing.ll b/llvm/test/Instrumentation/SanitizerCoverage/tracing.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/tracing.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/tracing.ll @@ -6,34 +6,34 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define void @foo(i32* %a) sanitize_address { +define void @foo(ptr %a) sanitize_address { entry: - %tobool = icmp eq i32* %a, null + %tobool = icmp eq ptr %a, null br i1 %tobool, label %if.end, label %if.then if.then: ; preds = %entry - store i32 0, i32* %a, align 4 + store i32 0, ptr %a, align 4 br label %if.end if.end: ; preds = %entry, %if.then ret void } -define available_externally void @external_bar(i32* %a) sanitize_address { +define available_externally void @external_bar(ptr %a) sanitize_address { entry: ret void } -declare void @longjmp(i8*) noreturn +declare void @longjmp(ptr) noreturn ; We expect three coverage points here for each BB. -define void @cond_longjmp(i1 %cond, i8* %jmp_buf) sanitize_address { +define void @cond_longjmp(i1 %cond, ptr %jmp_buf) sanitize_address { entry: br i1 %cond, label %lj, label %done done: ret void lj: - call void @longjmp(i8* %jmp_buf) + call void @longjmp(ptr %jmp_buf) unreachable } @@ -71,7 +71,7 @@ ; CHECK_PC_GUARD: call void @longjmp ; CHECK_PC_GUARD: unreachable -; CHECK_PC_GUARD: call void @__sanitizer_cov_trace_pc_guard_init(i32* @__start___sancov_guards, i32* @__stop___sancov_guards) +; CHECK_PC_GUARD: call void @__sanitizer_cov_trace_pc_guard_init(ptr @__start___sancov_guards, ptr @__stop___sancov_guards) ; CHECK_PC_GUARD_DARWIN-LABEL: define void @foo ; CHECK_PC_GUARD_DARWIN: call void @__sanitizer_cov_trace_pc_guard @@ -79,4 +79,4 @@ ; CHECK_PC_GUARD_DARWIN: call void @__sanitizer_cov_trace_pc_guard ; CHECK_PC_GUARD_DARWIN-NOT: call void @__sanitizer_cov_trace_pc ; CHECK_PC_GUARD_DARWIN: ret void -; CHECK_PC_GUARD_DARWIN: call void @__sanitizer_cov_trace_pc_guard_init(i32* @"\01section$start$__DATA$__sancov_guards", i32* @"\01section$end$__DATA$__sancov_guards") +; CHECK_PC_GUARD_DARWIN: call void @__sanitizer_cov_trace_pc_guard_init(ptr @"\01section$start$__DATA$__sancov_guards", ptr @"\01section$end$__DATA$__sancov_guards") diff --git a/llvm/test/Instrumentation/SanitizerCoverage/wineh.ll b/llvm/test/Instrumentation/SanitizerCoverage/wineh.ll --- a/llvm/test/Instrumentation/SanitizerCoverage/wineh.ll +++ b/llvm/test/Instrumentation/SanitizerCoverage/wineh.ll @@ -29,22 +29,21 @@ target datalayout = "e-m:w-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-windows-msvc19.10.24728" -%rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] } +%rtti.TypeDescriptor2 = type { ptr, ptr, [3 x i8] } %struct.Foo = type { i8 } $"\01??_R0H@8" = comdat any -@"\01??_7type_info@@6B@" = external constant i8* -@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { i8** @"\01??_7type_info@@6B@", i8* null, [3 x i8] c".H\00" }, comdat +@"\01??_7type_info@@6B@" = external constant ptr +@"\01??_R0H@8" = linkonce_odr global %rtti.TypeDescriptor2 { ptr @"\01??_7type_info@@6B@", ptr null, [3 x i8] c".H\00" }, comdat ; Function Attrs: uwtable -define i32 @"\01?f@@YAHXZ"() local_unnamed_addr #0 personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) { +define i32 @"\01?f@@YAHXZ"() local_unnamed_addr #0 personality ptr @__CxxFrameHandler3 { entry: %v = alloca %struct.Foo, align 1 %e = alloca i32, align 4 - %0 = getelementptr inbounds %struct.Foo, %struct.Foo* %v, i64 0, i32 0 - call void @llvm.lifetime.start(i64 1, i8* nonnull %0) #4 - %call = call %struct.Foo* @"\01??0Foo@@QEAA@XZ"(%struct.Foo* nonnull %v) + call void @llvm.lifetime.start(i64 1, ptr nonnull %v) #4 + %call = call ptr @"\01??0Foo@@QEAA@XZ"(ptr nonnull %v) invoke void @"\01?g@@YAXXZ"() to label %invoke.cont unwind label %ehcleanup @@ -53,50 +52,50 @@ to label %try.cont unwind label %catch.dispatch catch.dispatch: ; preds = %invoke.cont - %1 = catchswitch within none [label %catch3, label %catch] unwind label %ehcleanup + %0 = catchswitch within none [label %catch3, label %catch] unwind label %ehcleanup catch3: ; preds = %catch.dispatch - %2 = catchpad within %1 [%rtti.TypeDescriptor2* @"\01??_R0H@8", i32 0, i32* %e] - invoke void @"\01?g@@YAXXZ"() [ "funclet"(token %2) ] + %1 = catchpad within %0 [ptr @"\01??_R0H@8", i32 0, ptr %e] + invoke void @"\01?g@@YAXXZ"() [ "funclet"(token %1) ] to label %invoke.cont4 unwind label %ehcleanup invoke.cont4: ; preds = %catch3 - catchret from %2 to label %try.cont + catchret from %1 to label %try.cont try.cont: ; preds = %invoke.cont, %invoke.cont2, %invoke.cont4 - call void @"\01??1Foo@@QEAA@XZ"(%struct.Foo* nonnull %v) #4 - call void @llvm.lifetime.end(i64 1, i8* nonnull %0) #4 + call void @"\01??1Foo@@QEAA@XZ"(ptr nonnull %v) #4 + call void @llvm.lifetime.end(i64 1, ptr nonnull %v) #4 ret i32 0 catch: ; preds = %catch.dispatch - %3 = catchpad within %1 [i8* null, i32 64, i8* null] - invoke void @"\01?g@@YAXXZ"() [ "funclet"(token %3) ] + %2 = catchpad within %0 [ptr null, i32 64, ptr null] + invoke void @"\01?g@@YAXXZ"() [ "funclet"(token %2) ] to label %invoke.cont2 unwind label %ehcleanup invoke.cont2: ; preds = %catch - catchret from %3 to label %try.cont + catchret from %2 to label %try.cont ehcleanup: ; preds = %catch3, %catch, %catch.dispatch, %entry - %4 = cleanuppad within none [] - call void @"\01??1Foo@@QEAA@XZ"(%struct.Foo* nonnull %v) #4 [ "funclet"(token %4) ] - call void @llvm.lifetime.end(i64 1, i8* nonnull %0) #4 - cleanupret from %4 unwind to caller + %3 = cleanuppad within none [] + call void @"\01??1Foo@@QEAA@XZ"(ptr nonnull %v) #4 [ "funclet"(token %3) ] + call void @llvm.lifetime.end(i64 1, ptr nonnull %v) #4 + cleanupret from %3 unwind to caller } ; Function Attrs: argmemonly nounwind -declare void @llvm.lifetime.start(i64, i8* nocapture) #1 +declare void @llvm.lifetime.start(i64, ptr nocapture) #1 -declare %struct.Foo* @"\01??0Foo@@QEAA@XZ"(%struct.Foo* returned) unnamed_addr #2 +declare ptr @"\01??0Foo@@QEAA@XZ"(ptr returned) unnamed_addr #2 declare void @"\01?g@@YAXXZ"() local_unnamed_addr #2 declare i32 @__CxxFrameHandler3(...) ; Function Attrs: nounwind -declare void @"\01??1Foo@@QEAA@XZ"(%struct.Foo*) unnamed_addr #3 +declare void @"\01??1Foo@@QEAA@XZ"(ptr) unnamed_addr #3 ; Function Attrs: argmemonly nounwind -declare void @llvm.lifetime.end(i64, i8* nocapture) #1 +declare void @llvm.lifetime.end(i64, ptr nocapture) #1 attributes #0 = { uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } diff --git a/llvm/test/Instrumentation/ThreadSanitizer/atomic-non-integer.ll b/llvm/test/Instrumentation/ThreadSanitizer/atomic-non-integer.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/atomic-non-integer.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/atomic-non-integer.ll @@ -2,50 +2,50 @@ ; Check that atomic memory operations on floating-point types are converted to calls into ThreadSanitizer runtime. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -define float @load_float(float* %fptr) { - %v = load atomic float, float* %fptr unordered, align 4 +define float @load_float(ptr %fptr) { + %v = load atomic float, ptr %fptr unordered, align 4 ret float %v ; CHECK-LABEL: load_float - ; CHECK: call i32 @__tsan_atomic32_load(i32* %{{.+}}, i32 0) + ; CHECK: call i32 @__tsan_atomic32_load(ptr %{{.+}}, i32 0) ; CHECK: bitcast i32 {{.+}} to float } -define double @load_double(double* %fptr) { - %v = load atomic double, double* %fptr unordered, align 8 +define double @load_double(ptr %fptr) { + %v = load atomic double, ptr %fptr unordered, align 8 ret double %v ; CHECK-LABEL: load_double - ; CHECK: call i64 @__tsan_atomic64_load(i64* %{{.+}}, i32 0) + ; CHECK: call i64 @__tsan_atomic64_load(ptr %{{.+}}, i32 0) ; CHECK: bitcast i64 {{.+}} to double } -define fp128 @load_fp128(fp128* %fptr) { - %v = load atomic fp128, fp128* %fptr unordered, align 16 +define fp128 @load_fp128(ptr %fptr) { + %v = load atomic fp128, ptr %fptr unordered, align 16 ret fp128 %v ; CHECK-LABEL: load_fp128 - ; CHECK: call i128 @__tsan_atomic128_load(i128* %{{.+}}, i32 0) + ; CHECK: call i128 @__tsan_atomic128_load(ptr %{{.+}}, i32 0) ; CHECK: bitcast i128 {{.+}} to fp128 } -define void @store_float(float* %fptr, float %v) { - store atomic float %v, float* %fptr unordered, align 4 +define void @store_float(ptr %fptr, float %v) { + store atomic float %v, ptr %fptr unordered, align 4 ret void ; CHECK-LABEL: store_float ; CHECK: bitcast float %v to i32 - ; CHECK: call void @__tsan_atomic32_store(i32* %{{.+}}, i32 %{{.+}}, i32 0) + ; CHECK: call void @__tsan_atomic32_store(ptr %{{.+}}, i32 %{{.+}}, i32 0) } -define void @store_double(double* %fptr, double %v) { - store atomic double %v, double* %fptr unordered, align 8 +define void @store_double(ptr %fptr, double %v) { + store atomic double %v, ptr %fptr unordered, align 8 ret void ; CHECK-LABEL: store_double ; CHECK: bitcast double %v to i64 - ; CHECK: call void @__tsan_atomic64_store(i64* %{{.+}}, i64 %{{.+}}, i32 0) + ; CHECK: call void @__tsan_atomic64_store(ptr %{{.+}}, i64 %{{.+}}, i32 0) } -define void @store_fp128(fp128* %fptr, fp128 %v) { - store atomic fp128 %v, fp128* %fptr unordered, align 16 +define void @store_fp128(ptr %fptr, fp128 %v) { + store atomic fp128 %v, ptr %fptr unordered, align 16 ret void ; CHECK-LABEL: store_fp128 ; CHECK: bitcast fp128 %v to i128 - ; CHECK: call void @__tsan_atomic128_store(i128* %{{.+}}, i128 %{{.+}}, i32 0) + ; CHECK: call void @__tsan_atomic128_store(ptr %{{.+}}, i128 %{{.+}}, i32 0) } diff --git a/llvm/test/Instrumentation/ThreadSanitizer/atomic.ll b/llvm/test/Instrumentation/ThreadSanitizer/atomic.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/atomic.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/atomic.ll @@ -2,2040 +2,2035 @@ ; Check that atomic memory operations are converted to calls into ThreadSanitizer runtime. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -define i8 @atomic8_load_unordered(i8* %a) nounwind uwtable { +define i8 @atomic8_load_unordered(ptr %a) nounwind uwtable { entry: - %0 = load atomic i8, i8* %a unordered, align 1, !dbg !7 + %0 = load atomic i8, ptr %a unordered, align 1, !dbg !7 ret i8 %0, !dbg !7 } ; CHECK-LABEL: atomic8_load_unordered -; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_load(ptr %a, i32 0), !dbg -define i8 @atomic8_load_monotonic(i8* %a) nounwind uwtable { +define i8 @atomic8_load_monotonic(ptr %a) nounwind uwtable { entry: - %0 = load atomic i8, i8* %a monotonic, align 1, !dbg !7 + %0 = load atomic i8, ptr %a monotonic, align 1, !dbg !7 ret i8 %0, !dbg !7 } ; CHECK-LABEL: atomic8_load_monotonic -; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_load(ptr %a, i32 0), !dbg -define i8 @atomic8_load_acquire(i8* %a) nounwind uwtable { +define i8 @atomic8_load_acquire(ptr %a) nounwind uwtable { entry: - %0 = load atomic i8, i8* %a acquire, align 1, !dbg !7 + %0 = load atomic i8, ptr %a acquire, align 1, !dbg !7 ret i8 %0, !dbg !7 } ; CHECK-LABEL: atomic8_load_acquire -; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 2), !dbg +; CHECK: call i8 @__tsan_atomic8_load(ptr %a, i32 2), !dbg -define i8 @atomic8_load_seq_cst(i8* %a) nounwind uwtable { +define i8 @atomic8_load_seq_cst(ptr %a) nounwind uwtable { entry: - %0 = load atomic i8, i8* %a seq_cst, align 1, !dbg !7 + %0 = load atomic i8, ptr %a seq_cst, align 1, !dbg !7 ret i8 %0, !dbg !7 } ; CHECK-LABEL: atomic8_load_seq_cst -; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 5), !dbg +; CHECK: call i8 @__tsan_atomic8_load(ptr %a, i32 5), !dbg -define void @atomic8_store_unordered(i8* %a) nounwind uwtable { +define void @atomic8_store_unordered(ptr %a) nounwind uwtable { entry: - store atomic i8 0, i8* %a unordered, align 1, !dbg !7 + store atomic i8 0, ptr %a unordered, align 1, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_store_unordered -; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 0), !dbg +; CHECK: call void @__tsan_atomic8_store(ptr %a, i8 0, i32 0), !dbg -define void @atomic8_store_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_store_monotonic(ptr %a) nounwind uwtable { entry: - store atomic i8 0, i8* %a monotonic, align 1, !dbg !7 + store atomic i8 0, ptr %a monotonic, align 1, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_store_monotonic -; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 0), !dbg +; CHECK: call void @__tsan_atomic8_store(ptr %a, i8 0, i32 0), !dbg -define void @atomic8_store_release(i8* %a) nounwind uwtable { +define void @atomic8_store_release(ptr %a) nounwind uwtable { entry: - store atomic i8 0, i8* %a release, align 1, !dbg !7 + store atomic i8 0, ptr %a release, align 1, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_store_release -; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 3), !dbg +; CHECK: call void @__tsan_atomic8_store(ptr %a, i8 0, i32 3), !dbg -define void @atomic8_store_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_store_seq_cst(ptr %a) nounwind uwtable { entry: - store atomic i8 0, i8* %a seq_cst, align 1, !dbg !7 + store atomic i8 0, ptr %a seq_cst, align 1, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_store_seq_cst -; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 5), !dbg +; CHECK: call void @__tsan_atomic8_store(ptr %a, i8 0, i32 5), !dbg -define void @atomic8_xchg_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_xchg_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i8* %a, i8 0 monotonic, !dbg !7 + atomicrmw xchg ptr %a, i8 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_xchg_monotonic -; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_exchange(ptr %a, i8 0, i32 0), !dbg -define void @atomic8_add_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_add_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw add i8* %a, i8 0 monotonic, !dbg !7 + atomicrmw add ptr %a, i8 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_add_monotonic -; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_add(ptr %a, i8 0, i32 0), !dbg -define void @atomic8_sub_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_sub_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw sub i8* %a, i8 0 monotonic, !dbg !7 + atomicrmw sub ptr %a, i8 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_sub_monotonic -; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_sub(ptr %a, i8 0, i32 0), !dbg -define void @atomic8_and_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_and_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw and i8* %a, i8 0 monotonic, !dbg !7 + atomicrmw and ptr %a, i8 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_and_monotonic -; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_and(ptr %a, i8 0, i32 0), !dbg -define void @atomic8_or_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_or_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw or i8* %a, i8 0 monotonic, !dbg !7 + atomicrmw or ptr %a, i8 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_or_monotonic -; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_or(ptr %a, i8 0, i32 0), !dbg -define void @atomic8_xor_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_xor_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw xor i8* %a, i8 0 monotonic, !dbg !7 + atomicrmw xor ptr %a, i8 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_xor_monotonic -; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_xor(ptr %a, i8 0, i32 0), !dbg -define void @atomic8_nand_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_nand_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw nand i8* %a, i8 0 monotonic, !dbg !7 + atomicrmw nand ptr %a, i8 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_nand_monotonic -; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_nand(ptr %a, i8 0, i32 0), !dbg -define void @atomic8_xchg_acquire(i8* %a) nounwind uwtable { +define void @atomic8_xchg_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i8* %a, i8 0 acquire, !dbg !7 + atomicrmw xchg ptr %a, i8 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_xchg_acquire -; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 2), !dbg +; CHECK: call i8 @__tsan_atomic8_exchange(ptr %a, i8 0, i32 2), !dbg -define void @atomic8_add_acquire(i8* %a) nounwind uwtable { +define void @atomic8_add_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw add i8* %a, i8 0 acquire, !dbg !7 + atomicrmw add ptr %a, i8 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_add_acquire -; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 2), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_add(ptr %a, i8 0, i32 2), !dbg -define void @atomic8_sub_acquire(i8* %a) nounwind uwtable { +define void @atomic8_sub_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw sub i8* %a, i8 0 acquire, !dbg !7 + atomicrmw sub ptr %a, i8 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_sub_acquire -; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 2), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_sub(ptr %a, i8 0, i32 2), !dbg -define void @atomic8_and_acquire(i8* %a) nounwind uwtable { +define void @atomic8_and_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw and i8* %a, i8 0 acquire, !dbg !7 + atomicrmw and ptr %a, i8 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_and_acquire -; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 2), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_and(ptr %a, i8 0, i32 2), !dbg -define void @atomic8_or_acquire(i8* %a) nounwind uwtable { +define void @atomic8_or_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw or i8* %a, i8 0 acquire, !dbg !7 + atomicrmw or ptr %a, i8 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_or_acquire -; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 2), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_or(ptr %a, i8 0, i32 2), !dbg -define void @atomic8_xor_acquire(i8* %a) nounwind uwtable { +define void @atomic8_xor_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw xor i8* %a, i8 0 acquire, !dbg !7 + atomicrmw xor ptr %a, i8 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_xor_acquire -; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 2), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_xor(ptr %a, i8 0, i32 2), !dbg -define void @atomic8_nand_acquire(i8* %a) nounwind uwtable { +define void @atomic8_nand_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw nand i8* %a, i8 0 acquire, !dbg !7 + atomicrmw nand ptr %a, i8 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_nand_acquire -; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 2), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_nand(ptr %a, i8 0, i32 2), !dbg -define void @atomic8_xchg_release(i8* %a) nounwind uwtable { +define void @atomic8_xchg_release(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i8* %a, i8 0 release, !dbg !7 + atomicrmw xchg ptr %a, i8 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_xchg_release -; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 3), !dbg +; CHECK: call i8 @__tsan_atomic8_exchange(ptr %a, i8 0, i32 3), !dbg -define void @atomic8_add_release(i8* %a) nounwind uwtable { +define void @atomic8_add_release(ptr %a) nounwind uwtable { entry: - atomicrmw add i8* %a, i8 0 release, !dbg !7 + atomicrmw add ptr %a, i8 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_add_release -; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 3), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_add(ptr %a, i8 0, i32 3), !dbg -define void @atomic8_sub_release(i8* %a) nounwind uwtable { +define void @atomic8_sub_release(ptr %a) nounwind uwtable { entry: - atomicrmw sub i8* %a, i8 0 release, !dbg !7 + atomicrmw sub ptr %a, i8 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_sub_release -; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 3), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_sub(ptr %a, i8 0, i32 3), !dbg -define void @atomic8_and_release(i8* %a) nounwind uwtable { +define void @atomic8_and_release(ptr %a) nounwind uwtable { entry: - atomicrmw and i8* %a, i8 0 release, !dbg !7 + atomicrmw and ptr %a, i8 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_and_release -; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 3), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_and(ptr %a, i8 0, i32 3), !dbg -define void @atomic8_or_release(i8* %a) nounwind uwtable { +define void @atomic8_or_release(ptr %a) nounwind uwtable { entry: - atomicrmw or i8* %a, i8 0 release, !dbg !7 + atomicrmw or ptr %a, i8 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_or_release -; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 3), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_or(ptr %a, i8 0, i32 3), !dbg -define void @atomic8_xor_release(i8* %a) nounwind uwtable { +define void @atomic8_xor_release(ptr %a) nounwind uwtable { entry: - atomicrmw xor i8* %a, i8 0 release, !dbg !7 + atomicrmw xor ptr %a, i8 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_xor_release -; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 3), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_xor(ptr %a, i8 0, i32 3), !dbg -define void @atomic8_nand_release(i8* %a) nounwind uwtable { +define void @atomic8_nand_release(ptr %a) nounwind uwtable { entry: - atomicrmw nand i8* %a, i8 0 release, !dbg !7 + atomicrmw nand ptr %a, i8 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_nand_release -; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 3), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_nand(ptr %a, i8 0, i32 3), !dbg -define void @atomic8_xchg_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_xchg_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i8* %a, i8 0 acq_rel, !dbg !7 + atomicrmw xchg ptr %a, i8 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_xchg_acq_rel -; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 4), !dbg +; CHECK: call i8 @__tsan_atomic8_exchange(ptr %a, i8 0, i32 4), !dbg -define void @atomic8_add_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_add_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw add i8* %a, i8 0 acq_rel, !dbg !7 + atomicrmw add ptr %a, i8 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_add_acq_rel -; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 4), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_add(ptr %a, i8 0, i32 4), !dbg -define void @atomic8_sub_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_sub_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw sub i8* %a, i8 0 acq_rel, !dbg !7 + atomicrmw sub ptr %a, i8 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_sub_acq_rel -; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 4), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_sub(ptr %a, i8 0, i32 4), !dbg -define void @atomic8_and_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_and_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw and i8* %a, i8 0 acq_rel, !dbg !7 + atomicrmw and ptr %a, i8 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_and_acq_rel -; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 4), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_and(ptr %a, i8 0, i32 4), !dbg -define void @atomic8_or_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_or_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw or i8* %a, i8 0 acq_rel, !dbg !7 + atomicrmw or ptr %a, i8 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_or_acq_rel -; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 4), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_or(ptr %a, i8 0, i32 4), !dbg -define void @atomic8_xor_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_xor_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw xor i8* %a, i8 0 acq_rel, !dbg !7 + atomicrmw xor ptr %a, i8 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_xor_acq_rel -; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 4), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_xor(ptr %a, i8 0, i32 4), !dbg -define void @atomic8_nand_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_nand_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw nand i8* %a, i8 0 acq_rel, !dbg !7 + atomicrmw nand ptr %a, i8 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_nand_acq_rel -; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 4), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_nand(ptr %a, i8 0, i32 4), !dbg -define void @atomic8_xchg_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_xchg_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i8* %a, i8 0 seq_cst, !dbg !7 + atomicrmw xchg ptr %a, i8 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_xchg_seq_cst -; CHECK: call i8 @__tsan_atomic8_exchange(i8* %a, i8 0, i32 5), !dbg +; CHECK: call i8 @__tsan_atomic8_exchange(ptr %a, i8 0, i32 5), !dbg -define void @atomic8_add_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_add_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw add i8* %a, i8 0 seq_cst, !dbg !7 + atomicrmw add ptr %a, i8 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_add_seq_cst -; CHECK: call i8 @__tsan_atomic8_fetch_add(i8* %a, i8 0, i32 5), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_add(ptr %a, i8 0, i32 5), !dbg -define void @atomic8_sub_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_sub_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw sub i8* %a, i8 0 seq_cst, !dbg !7 + atomicrmw sub ptr %a, i8 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_sub_seq_cst -; CHECK: call i8 @__tsan_atomic8_fetch_sub(i8* %a, i8 0, i32 5), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_sub(ptr %a, i8 0, i32 5), !dbg -define void @atomic8_and_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_and_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw and i8* %a, i8 0 seq_cst, !dbg !7 + atomicrmw and ptr %a, i8 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_and_seq_cst -; CHECK: call i8 @__tsan_atomic8_fetch_and(i8* %a, i8 0, i32 5), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_and(ptr %a, i8 0, i32 5), !dbg -define void @atomic8_or_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_or_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw or i8* %a, i8 0 seq_cst, !dbg !7 + atomicrmw or ptr %a, i8 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_or_seq_cst -; CHECK: call i8 @__tsan_atomic8_fetch_or(i8* %a, i8 0, i32 5), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_or(ptr %a, i8 0, i32 5), !dbg -define void @atomic8_xor_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_xor_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw xor i8* %a, i8 0 seq_cst, !dbg !7 + atomicrmw xor ptr %a, i8 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_xor_seq_cst -; CHECK: call i8 @__tsan_atomic8_fetch_xor(i8* %a, i8 0, i32 5), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_xor(ptr %a, i8 0, i32 5), !dbg -define void @atomic8_nand_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_nand_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw nand i8* %a, i8 0 seq_cst, !dbg !7 + atomicrmw nand ptr %a, i8 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_nand_seq_cst -; CHECK: call i8 @__tsan_atomic8_fetch_nand(i8* %a, i8 0, i32 5), !dbg +; CHECK: call i8 @__tsan_atomic8_fetch_nand(ptr %a, i8 0, i32 5), !dbg -define void @atomic8_cas_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_cas_monotonic(ptr %a) nounwind uwtable { entry: - cmpxchg i8* %a, i8 0, i8 1 monotonic monotonic, !dbg !7 - cmpxchg i8* %a, i8 0, i8 1 monotonic acquire, !dbg !7 - cmpxchg i8* %a, i8 0, i8 1 monotonic seq_cst, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 monotonic monotonic, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 monotonic acquire, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 monotonic seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_cas_monotonic -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 0, i32 0), !dbg -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 0, i32 2), !dbg -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 0, i32 5), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 0, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 0, i32 2), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 0, i32 5), !dbg -define void @atomic8_cas_acquire(i8* %a) nounwind uwtable { +define void @atomic8_cas_acquire(ptr %a) nounwind uwtable { entry: - cmpxchg i8* %a, i8 0, i8 1 acquire monotonic, !dbg !7 - cmpxchg i8* %a, i8 0, i8 1 acquire acquire, !dbg !7 - cmpxchg i8* %a, i8 0, i8 1 acquire seq_cst, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 acquire monotonic, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 acquire acquire, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 acquire seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_cas_acquire -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 2, i32 0), !dbg -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 2, i32 2), !dbg -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 2, i32 5), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 2, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 2, i32 2), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 2, i32 5), !dbg -define void @atomic8_cas_release(i8* %a) nounwind uwtable { +define void @atomic8_cas_release(ptr %a) nounwind uwtable { entry: - cmpxchg i8* %a, i8 0, i8 1 release monotonic, !dbg !7 - cmpxchg i8* %a, i8 0, i8 1 release acquire, !dbg !7 - cmpxchg i8* %a, i8 0, i8 1 release seq_cst, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 release monotonic, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 release acquire, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 release seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_cas_release -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 3, i32 0), !dbg -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 3, i32 2), !dbg -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 3, i32 5), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 3, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 3, i32 2), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 3, i32 5), !dbg -define void @atomic8_cas_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_cas_acq_rel(ptr %a) nounwind uwtable { entry: - cmpxchg i8* %a, i8 0, i8 1 acq_rel monotonic, !dbg !7 - cmpxchg i8* %a, i8 0, i8 1 acq_rel acquire, !dbg !7 - cmpxchg i8* %a, i8 0, i8 1 acq_rel seq_cst, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 acq_rel monotonic, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 acq_rel acquire, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 acq_rel seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_cas_acq_rel -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 4, i32 0), !dbg -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 4, i32 2), !dbg -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 4, i32 5), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 4, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 4, i32 2), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 4, i32 5), !dbg -define void @atomic8_cas_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_cas_seq_cst(ptr %a) nounwind uwtable { entry: - cmpxchg i8* %a, i8 0, i8 1 seq_cst monotonic, !dbg !7 - cmpxchg i8* %a, i8 0, i8 1 seq_cst acquire, !dbg !7 - cmpxchg i8* %a, i8 0, i8 1 seq_cst seq_cst, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 seq_cst monotonic, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 seq_cst acquire, !dbg !7 + cmpxchg ptr %a, i8 0, i8 1 seq_cst seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic8_cas_seq_cst -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 5, i32 0), !dbg -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 5, i32 2), !dbg -; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(i8* %a, i8 0, i8 1, i32 5, i32 5), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 5, i32 0), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 5, i32 2), !dbg +; CHECK: call i8 @__tsan_atomic8_compare_exchange_val(ptr %a, i8 0, i8 1, i32 5, i32 5), !dbg -define i16 @atomic16_load_unordered(i16* %a) nounwind uwtable { +define i16 @atomic16_load_unordered(ptr %a) nounwind uwtable { entry: - %0 = load atomic i16, i16* %a unordered, align 2, !dbg !7 + %0 = load atomic i16, ptr %a unordered, align 2, !dbg !7 ret i16 %0, !dbg !7 } ; CHECK-LABEL: atomic16_load_unordered -; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_load(ptr %a, i32 0), !dbg -define i16 @atomic16_load_monotonic(i16* %a) nounwind uwtable { +define i16 @atomic16_load_monotonic(ptr %a) nounwind uwtable { entry: - %0 = load atomic i16, i16* %a monotonic, align 2, !dbg !7 + %0 = load atomic i16, ptr %a monotonic, align 2, !dbg !7 ret i16 %0, !dbg !7 } ; CHECK-LABEL: atomic16_load_monotonic -; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_load(ptr %a, i32 0), !dbg -define i16 @atomic16_load_acquire(i16* %a) nounwind uwtable { +define i16 @atomic16_load_acquire(ptr %a) nounwind uwtable { entry: - %0 = load atomic i16, i16* %a acquire, align 2, !dbg !7 + %0 = load atomic i16, ptr %a acquire, align 2, !dbg !7 ret i16 %0, !dbg !7 } ; CHECK-LABEL: atomic16_load_acquire -; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 2), !dbg +; CHECK: call i16 @__tsan_atomic16_load(ptr %a, i32 2), !dbg -define i16 @atomic16_load_seq_cst(i16* %a) nounwind uwtable { +define i16 @atomic16_load_seq_cst(ptr %a) nounwind uwtable { entry: - %0 = load atomic i16, i16* %a seq_cst, align 2, !dbg !7 + %0 = load atomic i16, ptr %a seq_cst, align 2, !dbg !7 ret i16 %0, !dbg !7 } ; CHECK-LABEL: atomic16_load_seq_cst -; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 5), !dbg +; CHECK: call i16 @__tsan_atomic16_load(ptr %a, i32 5), !dbg -define void @atomic16_store_unordered(i16* %a) nounwind uwtable { +define void @atomic16_store_unordered(ptr %a) nounwind uwtable { entry: - store atomic i16 0, i16* %a unordered, align 2, !dbg !7 + store atomic i16 0, ptr %a unordered, align 2, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_store_unordered -; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 0), !dbg +; CHECK: call void @__tsan_atomic16_store(ptr %a, i16 0, i32 0), !dbg -define void @atomic16_store_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_store_monotonic(ptr %a) nounwind uwtable { entry: - store atomic i16 0, i16* %a monotonic, align 2, !dbg !7 + store atomic i16 0, ptr %a monotonic, align 2, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_store_monotonic -; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 0), !dbg +; CHECK: call void @__tsan_atomic16_store(ptr %a, i16 0, i32 0), !dbg -define void @atomic16_store_release(i16* %a) nounwind uwtable { +define void @atomic16_store_release(ptr %a) nounwind uwtable { entry: - store atomic i16 0, i16* %a release, align 2, !dbg !7 + store atomic i16 0, ptr %a release, align 2, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_store_release -; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 3), !dbg +; CHECK: call void @__tsan_atomic16_store(ptr %a, i16 0, i32 3), !dbg -define void @atomic16_store_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_store_seq_cst(ptr %a) nounwind uwtable { entry: - store atomic i16 0, i16* %a seq_cst, align 2, !dbg !7 + store atomic i16 0, ptr %a seq_cst, align 2, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_store_seq_cst -; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 5), !dbg +; CHECK: call void @__tsan_atomic16_store(ptr %a, i16 0, i32 5), !dbg -define void @atomic16_xchg_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_xchg_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i16* %a, i16 0 monotonic, !dbg !7 + atomicrmw xchg ptr %a, i16 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_xchg_monotonic -; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_exchange(ptr %a, i16 0, i32 0), !dbg -define void @atomic16_add_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_add_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw add i16* %a, i16 0 monotonic, !dbg !7 + atomicrmw add ptr %a, i16 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_add_monotonic -; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_add(ptr %a, i16 0, i32 0), !dbg -define void @atomic16_sub_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_sub_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw sub i16* %a, i16 0 monotonic, !dbg !7 + atomicrmw sub ptr %a, i16 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_sub_monotonic -; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_sub(ptr %a, i16 0, i32 0), !dbg -define void @atomic16_and_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_and_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw and i16* %a, i16 0 monotonic, !dbg !7 + atomicrmw and ptr %a, i16 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_and_monotonic -; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_and(ptr %a, i16 0, i32 0), !dbg -define void @atomic16_or_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_or_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw or i16* %a, i16 0 monotonic, !dbg !7 + atomicrmw or ptr %a, i16 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_or_monotonic -; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_or(ptr %a, i16 0, i32 0), !dbg -define void @atomic16_xor_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_xor_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw xor i16* %a, i16 0 monotonic, !dbg !7 + atomicrmw xor ptr %a, i16 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_xor_monotonic -; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_xor(ptr %a, i16 0, i32 0), !dbg -define void @atomic16_nand_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_nand_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw nand i16* %a, i16 0 monotonic, !dbg !7 + atomicrmw nand ptr %a, i16 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_nand_monotonic -; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_nand(ptr %a, i16 0, i32 0), !dbg -define void @atomic16_xchg_acquire(i16* %a) nounwind uwtable { +define void @atomic16_xchg_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i16* %a, i16 0 acquire, !dbg !7 + atomicrmw xchg ptr %a, i16 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_xchg_acquire -; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 2), !dbg +; CHECK: call i16 @__tsan_atomic16_exchange(ptr %a, i16 0, i32 2), !dbg -define void @atomic16_add_acquire(i16* %a) nounwind uwtable { +define void @atomic16_add_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw add i16* %a, i16 0 acquire, !dbg !7 + atomicrmw add ptr %a, i16 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_add_acquire -; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 2), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_add(ptr %a, i16 0, i32 2), !dbg -define void @atomic16_sub_acquire(i16* %a) nounwind uwtable { +define void @atomic16_sub_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw sub i16* %a, i16 0 acquire, !dbg !7 + atomicrmw sub ptr %a, i16 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_sub_acquire -; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 2), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_sub(ptr %a, i16 0, i32 2), !dbg -define void @atomic16_and_acquire(i16* %a) nounwind uwtable { +define void @atomic16_and_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw and i16* %a, i16 0 acquire, !dbg !7 + atomicrmw and ptr %a, i16 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_and_acquire -; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 2), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_and(ptr %a, i16 0, i32 2), !dbg -define void @atomic16_or_acquire(i16* %a) nounwind uwtable { +define void @atomic16_or_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw or i16* %a, i16 0 acquire, !dbg !7 + atomicrmw or ptr %a, i16 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_or_acquire -; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 2), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_or(ptr %a, i16 0, i32 2), !dbg -define void @atomic16_xor_acquire(i16* %a) nounwind uwtable { +define void @atomic16_xor_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw xor i16* %a, i16 0 acquire, !dbg !7 + atomicrmw xor ptr %a, i16 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_xor_acquire -; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 2), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_xor(ptr %a, i16 0, i32 2), !dbg -define void @atomic16_nand_acquire(i16* %a) nounwind uwtable { +define void @atomic16_nand_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw nand i16* %a, i16 0 acquire, !dbg !7 + atomicrmw nand ptr %a, i16 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_nand_acquire -; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 2), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_nand(ptr %a, i16 0, i32 2), !dbg -define void @atomic16_xchg_release(i16* %a) nounwind uwtable { +define void @atomic16_xchg_release(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i16* %a, i16 0 release, !dbg !7 + atomicrmw xchg ptr %a, i16 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_xchg_release -; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 3), !dbg +; CHECK: call i16 @__tsan_atomic16_exchange(ptr %a, i16 0, i32 3), !dbg -define void @atomic16_add_release(i16* %a) nounwind uwtable { +define void @atomic16_add_release(ptr %a) nounwind uwtable { entry: - atomicrmw add i16* %a, i16 0 release, !dbg !7 + atomicrmw add ptr %a, i16 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_add_release -; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 3), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_add(ptr %a, i16 0, i32 3), !dbg -define void @atomic16_sub_release(i16* %a) nounwind uwtable { +define void @atomic16_sub_release(ptr %a) nounwind uwtable { entry: - atomicrmw sub i16* %a, i16 0 release, !dbg !7 + atomicrmw sub ptr %a, i16 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_sub_release -; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 3), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_sub(ptr %a, i16 0, i32 3), !dbg -define void @atomic16_and_release(i16* %a) nounwind uwtable { +define void @atomic16_and_release(ptr %a) nounwind uwtable { entry: - atomicrmw and i16* %a, i16 0 release, !dbg !7 + atomicrmw and ptr %a, i16 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_and_release -; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 3), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_and(ptr %a, i16 0, i32 3), !dbg -define void @atomic16_or_release(i16* %a) nounwind uwtable { +define void @atomic16_or_release(ptr %a) nounwind uwtable { entry: - atomicrmw or i16* %a, i16 0 release, !dbg !7 + atomicrmw or ptr %a, i16 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_or_release -; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 3), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_or(ptr %a, i16 0, i32 3), !dbg -define void @atomic16_xor_release(i16* %a) nounwind uwtable { +define void @atomic16_xor_release(ptr %a) nounwind uwtable { entry: - atomicrmw xor i16* %a, i16 0 release, !dbg !7 + atomicrmw xor ptr %a, i16 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_xor_release -; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 3), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_xor(ptr %a, i16 0, i32 3), !dbg -define void @atomic16_nand_release(i16* %a) nounwind uwtable { +define void @atomic16_nand_release(ptr %a) nounwind uwtable { entry: - atomicrmw nand i16* %a, i16 0 release, !dbg !7 + atomicrmw nand ptr %a, i16 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_nand_release -; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 3), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_nand(ptr %a, i16 0, i32 3), !dbg -define void @atomic16_xchg_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_xchg_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i16* %a, i16 0 acq_rel, !dbg !7 + atomicrmw xchg ptr %a, i16 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_xchg_acq_rel -; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 4), !dbg +; CHECK: call i16 @__tsan_atomic16_exchange(ptr %a, i16 0, i32 4), !dbg -define void @atomic16_add_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_add_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw add i16* %a, i16 0 acq_rel, !dbg !7 + atomicrmw add ptr %a, i16 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_add_acq_rel -; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 4), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_add(ptr %a, i16 0, i32 4), !dbg -define void @atomic16_sub_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_sub_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw sub i16* %a, i16 0 acq_rel, !dbg !7 + atomicrmw sub ptr %a, i16 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_sub_acq_rel -; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 4), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_sub(ptr %a, i16 0, i32 4), !dbg -define void @atomic16_and_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_and_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw and i16* %a, i16 0 acq_rel, !dbg !7 + atomicrmw and ptr %a, i16 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_and_acq_rel -; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 4), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_and(ptr %a, i16 0, i32 4), !dbg -define void @atomic16_or_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_or_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw or i16* %a, i16 0 acq_rel, !dbg !7 + atomicrmw or ptr %a, i16 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_or_acq_rel -; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 4), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_or(ptr %a, i16 0, i32 4), !dbg -define void @atomic16_xor_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_xor_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw xor i16* %a, i16 0 acq_rel, !dbg !7 + atomicrmw xor ptr %a, i16 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_xor_acq_rel -; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 4), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_xor(ptr %a, i16 0, i32 4), !dbg -define void @atomic16_nand_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_nand_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw nand i16* %a, i16 0 acq_rel, !dbg !7 + atomicrmw nand ptr %a, i16 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_nand_acq_rel -; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 4), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_nand(ptr %a, i16 0, i32 4), !dbg -define void @atomic16_xchg_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_xchg_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i16* %a, i16 0 seq_cst, !dbg !7 + atomicrmw xchg ptr %a, i16 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_xchg_seq_cst -; CHECK: call i16 @__tsan_atomic16_exchange(i16* %a, i16 0, i32 5), !dbg +; CHECK: call i16 @__tsan_atomic16_exchange(ptr %a, i16 0, i32 5), !dbg -define void @atomic16_add_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_add_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw add i16* %a, i16 0 seq_cst, !dbg !7 + atomicrmw add ptr %a, i16 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_add_seq_cst -; CHECK: call i16 @__tsan_atomic16_fetch_add(i16* %a, i16 0, i32 5), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_add(ptr %a, i16 0, i32 5), !dbg -define void @atomic16_sub_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_sub_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw sub i16* %a, i16 0 seq_cst, !dbg !7 + atomicrmw sub ptr %a, i16 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_sub_seq_cst -; CHECK: call i16 @__tsan_atomic16_fetch_sub(i16* %a, i16 0, i32 5), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_sub(ptr %a, i16 0, i32 5), !dbg -define void @atomic16_and_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_and_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw and i16* %a, i16 0 seq_cst, !dbg !7 + atomicrmw and ptr %a, i16 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_and_seq_cst -; CHECK: call i16 @__tsan_atomic16_fetch_and(i16* %a, i16 0, i32 5), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_and(ptr %a, i16 0, i32 5), !dbg -define void @atomic16_or_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_or_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw or i16* %a, i16 0 seq_cst, !dbg !7 + atomicrmw or ptr %a, i16 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_or_seq_cst -; CHECK: call i16 @__tsan_atomic16_fetch_or(i16* %a, i16 0, i32 5), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_or(ptr %a, i16 0, i32 5), !dbg -define void @atomic16_xor_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_xor_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw xor i16* %a, i16 0 seq_cst, !dbg !7 + atomicrmw xor ptr %a, i16 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_xor_seq_cst -; CHECK: call i16 @__tsan_atomic16_fetch_xor(i16* %a, i16 0, i32 5), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_xor(ptr %a, i16 0, i32 5), !dbg -define void @atomic16_nand_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_nand_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw nand i16* %a, i16 0 seq_cst, !dbg !7 + atomicrmw nand ptr %a, i16 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_nand_seq_cst -; CHECK: call i16 @__tsan_atomic16_fetch_nand(i16* %a, i16 0, i32 5), !dbg +; CHECK: call i16 @__tsan_atomic16_fetch_nand(ptr %a, i16 0, i32 5), !dbg -define void @atomic16_cas_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_cas_monotonic(ptr %a) nounwind uwtable { entry: - cmpxchg i16* %a, i16 0, i16 1 monotonic monotonic, !dbg !7 - cmpxchg i16* %a, i16 0, i16 1 monotonic acquire, !dbg !7 - cmpxchg i16* %a, i16 0, i16 1 monotonic seq_cst, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 monotonic monotonic, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 monotonic acquire, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 monotonic seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_cas_monotonic -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 0, i32 0), !dbg -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 0, i32 2), !dbg -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 0, i32 5), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 0, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 0, i32 2), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 0, i32 5), !dbg -define void @atomic16_cas_acquire(i16* %a) nounwind uwtable { +define void @atomic16_cas_acquire(ptr %a) nounwind uwtable { entry: - cmpxchg i16* %a, i16 0, i16 1 acquire monotonic, !dbg !7 - cmpxchg i16* %a, i16 0, i16 1 acquire acquire, !dbg !7 - cmpxchg i16* %a, i16 0, i16 1 acquire seq_cst, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 acquire monotonic, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 acquire acquire, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 acquire seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_cas_acquire -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 2, i32 0), !dbg -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 2, i32 2), !dbg -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 2, i32 5), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 2, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 2, i32 2), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 2, i32 5), !dbg -define void @atomic16_cas_release(i16* %a) nounwind uwtable { +define void @atomic16_cas_release(ptr %a) nounwind uwtable { entry: - cmpxchg i16* %a, i16 0, i16 1 release monotonic, !dbg !7 - cmpxchg i16* %a, i16 0, i16 1 release acquire, !dbg !7 - cmpxchg i16* %a, i16 0, i16 1 release seq_cst, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 release monotonic, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 release acquire, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 release seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_cas_release -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 3, i32 0), !dbg -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 3, i32 2), !dbg -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 3, i32 5), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 3, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 3, i32 2), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 3, i32 5), !dbg -define void @atomic16_cas_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_cas_acq_rel(ptr %a) nounwind uwtable { entry: - cmpxchg i16* %a, i16 0, i16 1 acq_rel monotonic, !dbg !7 - cmpxchg i16* %a, i16 0, i16 1 acq_rel acquire, !dbg !7 - cmpxchg i16* %a, i16 0, i16 1 acq_rel seq_cst, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 acq_rel monotonic, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 acq_rel acquire, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 acq_rel seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_cas_acq_rel -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 4, i32 0), !dbg -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 4, i32 2), !dbg -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 4, i32 5), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 4, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 4, i32 2), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 4, i32 5), !dbg -define void @atomic16_cas_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_cas_seq_cst(ptr %a) nounwind uwtable { entry: - cmpxchg i16* %a, i16 0, i16 1 seq_cst monotonic, !dbg !7 - cmpxchg i16* %a, i16 0, i16 1 seq_cst acquire, !dbg !7 - cmpxchg i16* %a, i16 0, i16 1 seq_cst seq_cst, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 seq_cst monotonic, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 seq_cst acquire, !dbg !7 + cmpxchg ptr %a, i16 0, i16 1 seq_cst seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic16_cas_seq_cst -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 5, i32 0), !dbg -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 5, i32 2), !dbg -; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(i16* %a, i16 0, i16 1, i32 5, i32 5), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 5, i32 0), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 5, i32 2), !dbg +; CHECK: call i16 @__tsan_atomic16_compare_exchange_val(ptr %a, i16 0, i16 1, i32 5, i32 5), !dbg -define i32 @atomic32_load_unordered(i32* %a) nounwind uwtable { +define i32 @atomic32_load_unordered(ptr %a) nounwind uwtable { entry: - %0 = load atomic i32, i32* %a unordered, align 4, !dbg !7 + %0 = load atomic i32, ptr %a unordered, align 4, !dbg !7 ret i32 %0, !dbg !7 } ; CHECK-LABEL: atomic32_load_unordered -; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_load(ptr %a, i32 0), !dbg -define i32 @atomic32_load_monotonic(i32* %a) nounwind uwtable { +define i32 @atomic32_load_monotonic(ptr %a) nounwind uwtable { entry: - %0 = load atomic i32, i32* %a monotonic, align 4, !dbg !7 + %0 = load atomic i32, ptr %a monotonic, align 4, !dbg !7 ret i32 %0, !dbg !7 } ; CHECK-LABEL: atomic32_load_monotonic -; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_load(ptr %a, i32 0), !dbg -define i32 @atomic32_load_acquire(i32* %a) nounwind uwtable { +define i32 @atomic32_load_acquire(ptr %a) nounwind uwtable { entry: - %0 = load atomic i32, i32* %a acquire, align 4, !dbg !7 + %0 = load atomic i32, ptr %a acquire, align 4, !dbg !7 ret i32 %0, !dbg !7 } ; CHECK-LABEL: atomic32_load_acquire -; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 2), !dbg +; CHECK: call i32 @__tsan_atomic32_load(ptr %a, i32 2), !dbg -define i32 @atomic32_load_seq_cst(i32* %a) nounwind uwtable { +define i32 @atomic32_load_seq_cst(ptr %a) nounwind uwtable { entry: - %0 = load atomic i32, i32* %a seq_cst, align 4, !dbg !7 + %0 = load atomic i32, ptr %a seq_cst, align 4, !dbg !7 ret i32 %0, !dbg !7 } ; CHECK-LABEL: atomic32_load_seq_cst -; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 5), !dbg +; CHECK: call i32 @__tsan_atomic32_load(ptr %a, i32 5), !dbg -define void @atomic32_store_unordered(i32* %a) nounwind uwtable { +define void @atomic32_store_unordered(ptr %a) nounwind uwtable { entry: - store atomic i32 0, i32* %a unordered, align 4, !dbg !7 + store atomic i32 0, ptr %a unordered, align 4, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_store_unordered -; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 0), !dbg +; CHECK: call void @__tsan_atomic32_store(ptr %a, i32 0, i32 0), !dbg -define void @atomic32_store_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_store_monotonic(ptr %a) nounwind uwtable { entry: - store atomic i32 0, i32* %a monotonic, align 4, !dbg !7 + store atomic i32 0, ptr %a monotonic, align 4, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_store_monotonic -; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 0), !dbg +; CHECK: call void @__tsan_atomic32_store(ptr %a, i32 0, i32 0), !dbg -define void @atomic32_store_release(i32* %a) nounwind uwtable { +define void @atomic32_store_release(ptr %a) nounwind uwtable { entry: - store atomic i32 0, i32* %a release, align 4, !dbg !7 + store atomic i32 0, ptr %a release, align 4, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_store_release -; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 3), !dbg +; CHECK: call void @__tsan_atomic32_store(ptr %a, i32 0, i32 3), !dbg -define void @atomic32_store_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_store_seq_cst(ptr %a) nounwind uwtable { entry: - store atomic i32 0, i32* %a seq_cst, align 4, !dbg !7 + store atomic i32 0, ptr %a seq_cst, align 4, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_store_seq_cst -; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 5), !dbg +; CHECK: call void @__tsan_atomic32_store(ptr %a, i32 0, i32 5), !dbg -define void @atomic32_xchg_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_xchg_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i32* %a, i32 0 monotonic, !dbg !7 + atomicrmw xchg ptr %a, i32 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_xchg_monotonic -; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_exchange(ptr %a, i32 0, i32 0), !dbg -define void @atomic32_add_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_add_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw add i32* %a, i32 0 monotonic, !dbg !7 + atomicrmw add ptr %a, i32 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_add_monotonic -; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_add(ptr %a, i32 0, i32 0), !dbg -define void @atomic32_sub_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_sub_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw sub i32* %a, i32 0 monotonic, !dbg !7 + atomicrmw sub ptr %a, i32 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_sub_monotonic -; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_sub(ptr %a, i32 0, i32 0), !dbg -define void @atomic32_and_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_and_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw and i32* %a, i32 0 monotonic, !dbg !7 + atomicrmw and ptr %a, i32 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_and_monotonic -; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_and(ptr %a, i32 0, i32 0), !dbg -define void @atomic32_or_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_or_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw or i32* %a, i32 0 monotonic, !dbg !7 + atomicrmw or ptr %a, i32 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_or_monotonic -; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_or(ptr %a, i32 0, i32 0), !dbg -define void @atomic32_xor_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_xor_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw xor i32* %a, i32 0 monotonic, !dbg !7 + atomicrmw xor ptr %a, i32 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_xor_monotonic -; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_xor(ptr %a, i32 0, i32 0), !dbg -define void @atomic32_nand_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_nand_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw nand i32* %a, i32 0 monotonic, !dbg !7 + atomicrmw nand ptr %a, i32 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_nand_monotonic -; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_nand(ptr %a, i32 0, i32 0), !dbg -define void @atomic32_xchg_acquire(i32* %a) nounwind uwtable { +define void @atomic32_xchg_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i32* %a, i32 0 acquire, !dbg !7 + atomicrmw xchg ptr %a, i32 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_xchg_acquire -; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 2), !dbg +; CHECK: call i32 @__tsan_atomic32_exchange(ptr %a, i32 0, i32 2), !dbg -define void @atomic32_add_acquire(i32* %a) nounwind uwtable { +define void @atomic32_add_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw add i32* %a, i32 0 acquire, !dbg !7 + atomicrmw add ptr %a, i32 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_add_acquire -; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 2), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_add(ptr %a, i32 0, i32 2), !dbg -define void @atomic32_sub_acquire(i32* %a) nounwind uwtable { +define void @atomic32_sub_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw sub i32* %a, i32 0 acquire, !dbg !7 + atomicrmw sub ptr %a, i32 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_sub_acquire -; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 2), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_sub(ptr %a, i32 0, i32 2), !dbg -define void @atomic32_and_acquire(i32* %a) nounwind uwtable { +define void @atomic32_and_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw and i32* %a, i32 0 acquire, !dbg !7 + atomicrmw and ptr %a, i32 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_and_acquire -; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 2), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_and(ptr %a, i32 0, i32 2), !dbg -define void @atomic32_or_acquire(i32* %a) nounwind uwtable { +define void @atomic32_or_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw or i32* %a, i32 0 acquire, !dbg !7 + atomicrmw or ptr %a, i32 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_or_acquire -; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 2), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_or(ptr %a, i32 0, i32 2), !dbg -define void @atomic32_xor_acquire(i32* %a) nounwind uwtable { +define void @atomic32_xor_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw xor i32* %a, i32 0 acquire, !dbg !7 + atomicrmw xor ptr %a, i32 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_xor_acquire -; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 2), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_xor(ptr %a, i32 0, i32 2), !dbg -define void @atomic32_nand_acquire(i32* %a) nounwind uwtable { +define void @atomic32_nand_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw nand i32* %a, i32 0 acquire, !dbg !7 + atomicrmw nand ptr %a, i32 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_nand_acquire -; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 2), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_nand(ptr %a, i32 0, i32 2), !dbg -define void @atomic32_xchg_release(i32* %a) nounwind uwtable { +define void @atomic32_xchg_release(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i32* %a, i32 0 release, !dbg !7 + atomicrmw xchg ptr %a, i32 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_xchg_release -; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 3), !dbg +; CHECK: call i32 @__tsan_atomic32_exchange(ptr %a, i32 0, i32 3), !dbg -define void @atomic32_add_release(i32* %a) nounwind uwtable { +define void @atomic32_add_release(ptr %a) nounwind uwtable { entry: - atomicrmw add i32* %a, i32 0 release, !dbg !7 + atomicrmw add ptr %a, i32 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_add_release -; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 3), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_add(ptr %a, i32 0, i32 3), !dbg -define void @atomic32_sub_release(i32* %a) nounwind uwtable { +define void @atomic32_sub_release(ptr %a) nounwind uwtable { entry: - atomicrmw sub i32* %a, i32 0 release, !dbg !7 + atomicrmw sub ptr %a, i32 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_sub_release -; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 3), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_sub(ptr %a, i32 0, i32 3), !dbg -define void @atomic32_and_release(i32* %a) nounwind uwtable { +define void @atomic32_and_release(ptr %a) nounwind uwtable { entry: - atomicrmw and i32* %a, i32 0 release, !dbg !7 + atomicrmw and ptr %a, i32 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_and_release -; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 3), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_and(ptr %a, i32 0, i32 3), !dbg -define void @atomic32_or_release(i32* %a) nounwind uwtable { +define void @atomic32_or_release(ptr %a) nounwind uwtable { entry: - atomicrmw or i32* %a, i32 0 release, !dbg !7 + atomicrmw or ptr %a, i32 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_or_release -; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 3), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_or(ptr %a, i32 0, i32 3), !dbg -define void @atomic32_xor_release(i32* %a) nounwind uwtable { +define void @atomic32_xor_release(ptr %a) nounwind uwtable { entry: - atomicrmw xor i32* %a, i32 0 release, !dbg !7 + atomicrmw xor ptr %a, i32 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_xor_release -; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 3), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_xor(ptr %a, i32 0, i32 3), !dbg -define void @atomic32_nand_release(i32* %a) nounwind uwtable { +define void @atomic32_nand_release(ptr %a) nounwind uwtable { entry: - atomicrmw nand i32* %a, i32 0 release, !dbg !7 + atomicrmw nand ptr %a, i32 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_nand_release -; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 3), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_nand(ptr %a, i32 0, i32 3), !dbg -define void @atomic32_xchg_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_xchg_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i32* %a, i32 0 acq_rel, !dbg !7 + atomicrmw xchg ptr %a, i32 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_xchg_acq_rel -; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 4), !dbg +; CHECK: call i32 @__tsan_atomic32_exchange(ptr %a, i32 0, i32 4), !dbg -define void @atomic32_add_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_add_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw add i32* %a, i32 0 acq_rel, !dbg !7 + atomicrmw add ptr %a, i32 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_add_acq_rel -; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 4), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_add(ptr %a, i32 0, i32 4), !dbg -define void @atomic32_sub_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_sub_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw sub i32* %a, i32 0 acq_rel, !dbg !7 + atomicrmw sub ptr %a, i32 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_sub_acq_rel -; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 4), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_sub(ptr %a, i32 0, i32 4), !dbg -define void @atomic32_and_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_and_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw and i32* %a, i32 0 acq_rel, !dbg !7 + atomicrmw and ptr %a, i32 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_and_acq_rel -; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 4), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_and(ptr %a, i32 0, i32 4), !dbg -define void @atomic32_or_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_or_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw or i32* %a, i32 0 acq_rel, !dbg !7 + atomicrmw or ptr %a, i32 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_or_acq_rel -; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 4), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_or(ptr %a, i32 0, i32 4), !dbg -define void @atomic32_xor_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_xor_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw xor i32* %a, i32 0 acq_rel, !dbg !7 + atomicrmw xor ptr %a, i32 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_xor_acq_rel -; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 4), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_xor(ptr %a, i32 0, i32 4), !dbg -define void @atomic32_nand_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_nand_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw nand i32* %a, i32 0 acq_rel, !dbg !7 + atomicrmw nand ptr %a, i32 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_nand_acq_rel -; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 4), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_nand(ptr %a, i32 0, i32 4), !dbg -define void @atomic32_xchg_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_xchg_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i32* %a, i32 0 seq_cst, !dbg !7 + atomicrmw xchg ptr %a, i32 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_xchg_seq_cst -; CHECK: call i32 @__tsan_atomic32_exchange(i32* %a, i32 0, i32 5), !dbg +; CHECK: call i32 @__tsan_atomic32_exchange(ptr %a, i32 0, i32 5), !dbg -define void @atomic32_add_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_add_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw add i32* %a, i32 0 seq_cst, !dbg !7 + atomicrmw add ptr %a, i32 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_add_seq_cst -; CHECK: call i32 @__tsan_atomic32_fetch_add(i32* %a, i32 0, i32 5), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_add(ptr %a, i32 0, i32 5), !dbg -define void @atomic32_sub_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_sub_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw sub i32* %a, i32 0 seq_cst, !dbg !7 + atomicrmw sub ptr %a, i32 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_sub_seq_cst -; CHECK: call i32 @__tsan_atomic32_fetch_sub(i32* %a, i32 0, i32 5), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_sub(ptr %a, i32 0, i32 5), !dbg -define void @atomic32_and_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_and_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw and i32* %a, i32 0 seq_cst, !dbg !7 + atomicrmw and ptr %a, i32 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_and_seq_cst -; CHECK: call i32 @__tsan_atomic32_fetch_and(i32* %a, i32 0, i32 5), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_and(ptr %a, i32 0, i32 5), !dbg -define void @atomic32_or_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_or_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw or i32* %a, i32 0 seq_cst, !dbg !7 + atomicrmw or ptr %a, i32 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_or_seq_cst -; CHECK: call i32 @__tsan_atomic32_fetch_or(i32* %a, i32 0, i32 5), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_or(ptr %a, i32 0, i32 5), !dbg -define void @atomic32_xor_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_xor_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw xor i32* %a, i32 0 seq_cst, !dbg !7 + atomicrmw xor ptr %a, i32 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_xor_seq_cst -; CHECK: call i32 @__tsan_atomic32_fetch_xor(i32* %a, i32 0, i32 5), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_xor(ptr %a, i32 0, i32 5), !dbg -define void @atomic32_nand_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_nand_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw nand i32* %a, i32 0 seq_cst, !dbg !7 + atomicrmw nand ptr %a, i32 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_nand_seq_cst -; CHECK: call i32 @__tsan_atomic32_fetch_nand(i32* %a, i32 0, i32 5), !dbg +; CHECK: call i32 @__tsan_atomic32_fetch_nand(ptr %a, i32 0, i32 5), !dbg -define void @atomic32_cas_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_cas_monotonic(ptr %a) nounwind uwtable { entry: - cmpxchg i32* %a, i32 0, i32 1 monotonic monotonic, !dbg !7 - cmpxchg i32* %a, i32 0, i32 1 monotonic acquire, !dbg !7 - cmpxchg i32* %a, i32 0, i32 1 monotonic seq_cst, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 monotonic monotonic, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 monotonic acquire, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 monotonic seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_cas_monotonic -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 0, i32 0), !dbg -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 0, i32 2), !dbg -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 0, i32 5), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 0, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 0, i32 2), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 0, i32 5), !dbg -define void @atomic32_cas_acquire(i32* %a) nounwind uwtable { +define void @atomic32_cas_acquire(ptr %a) nounwind uwtable { entry: - cmpxchg i32* %a, i32 0, i32 1 acquire monotonic, !dbg !7 - cmpxchg i32* %a, i32 0, i32 1 acquire acquire, !dbg !7 - cmpxchg i32* %a, i32 0, i32 1 acquire seq_cst, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 acquire monotonic, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 acquire acquire, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 acquire seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_cas_acquire -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 2, i32 0), !dbg -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 2, i32 2), !dbg -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 2, i32 5), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 2, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 2, i32 2), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 2, i32 5), !dbg -define void @atomic32_cas_release(i32* %a) nounwind uwtable { +define void @atomic32_cas_release(ptr %a) nounwind uwtable { entry: - cmpxchg i32* %a, i32 0, i32 1 release monotonic, !dbg !7 - cmpxchg i32* %a, i32 0, i32 1 release acquire, !dbg !7 - cmpxchg i32* %a, i32 0, i32 1 release seq_cst, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 release monotonic, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 release acquire, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 release seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_cas_release -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 3, i32 0), !dbg -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 3, i32 2), !dbg -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 3, i32 5), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 3, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 3, i32 2), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 3, i32 5), !dbg -define void @atomic32_cas_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_cas_acq_rel(ptr %a) nounwind uwtable { entry: - cmpxchg i32* %a, i32 0, i32 1 acq_rel monotonic, !dbg !7 - cmpxchg i32* %a, i32 0, i32 1 acq_rel acquire, !dbg !7 - cmpxchg i32* %a, i32 0, i32 1 acq_rel seq_cst, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 acq_rel monotonic, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 acq_rel acquire, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 acq_rel seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_cas_acq_rel -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 4, i32 0), !dbg -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 4, i32 2), !dbg -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 4, i32 5), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 4, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 4, i32 2), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 4, i32 5), !dbg -define void @atomic32_cas_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_cas_seq_cst(ptr %a) nounwind uwtable { entry: - cmpxchg i32* %a, i32 0, i32 1 seq_cst monotonic, !dbg !7 - cmpxchg i32* %a, i32 0, i32 1 seq_cst acquire, !dbg !7 - cmpxchg i32* %a, i32 0, i32 1 seq_cst seq_cst, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 seq_cst monotonic, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 seq_cst acquire, !dbg !7 + cmpxchg ptr %a, i32 0, i32 1 seq_cst seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic32_cas_seq_cst -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 5, i32 0), !dbg -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 5, i32 2), !dbg -; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(i32* %a, i32 0, i32 1, i32 5, i32 5), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 5, i32 0), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 5, i32 2), !dbg +; CHECK: call i32 @__tsan_atomic32_compare_exchange_val(ptr %a, i32 0, i32 1, i32 5, i32 5), !dbg -define i64 @atomic64_load_unordered(i64* %a) nounwind uwtable { +define i64 @atomic64_load_unordered(ptr %a) nounwind uwtable { entry: - %0 = load atomic i64, i64* %a unordered, align 8, !dbg !7 + %0 = load atomic i64, ptr %a unordered, align 8, !dbg !7 ret i64 %0, !dbg !7 } ; CHECK-LABEL: atomic64_load_unordered -; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_load(ptr %a, i32 0), !dbg -define i64 @atomic64_load_monotonic(i64* %a) nounwind uwtable { +define i64 @atomic64_load_monotonic(ptr %a) nounwind uwtable { entry: - %0 = load atomic i64, i64* %a monotonic, align 8, !dbg !7 + %0 = load atomic i64, ptr %a monotonic, align 8, !dbg !7 ret i64 %0, !dbg !7 } ; CHECK-LABEL: atomic64_load_monotonic -; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_load(ptr %a, i32 0), !dbg -define i64 @atomic64_load_acquire(i64* %a) nounwind uwtable { +define i64 @atomic64_load_acquire(ptr %a) nounwind uwtable { entry: - %0 = load atomic i64, i64* %a acquire, align 8, !dbg !7 + %0 = load atomic i64, ptr %a acquire, align 8, !dbg !7 ret i64 %0, !dbg !7 } ; CHECK-LABEL: atomic64_load_acquire -; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 2), !dbg +; CHECK: call i64 @__tsan_atomic64_load(ptr %a, i32 2), !dbg -define i64 @atomic64_load_seq_cst(i64* %a) nounwind uwtable { +define i64 @atomic64_load_seq_cst(ptr %a) nounwind uwtable { entry: - %0 = load atomic i64, i64* %a seq_cst, align 8, !dbg !7 + %0 = load atomic i64, ptr %a seq_cst, align 8, !dbg !7 ret i64 %0, !dbg !7 } ; CHECK-LABEL: atomic64_load_seq_cst -; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 5), !dbg +; CHECK: call i64 @__tsan_atomic64_load(ptr %a, i32 5), !dbg -define i8* @atomic64_load_seq_cst_ptr_ty(i8** %a) nounwind uwtable { +define ptr @atomic64_load_seq_cst_ptr_ty(ptr %a) nounwind uwtable { entry: - %0 = load atomic i8*, i8** %a seq_cst, align 8, !dbg !7 - ret i8* %0, !dbg !7 + %0 = load atomic ptr, ptr %a seq_cst, align 8, !dbg !7 + ret ptr %0, !dbg !7 } ; CHECK-LABEL: atomic64_load_seq_cst -; CHECK: bitcast i8** %{{.+}} to i64* -; CHECK-NEXT: call i64 @__tsan_atomic64_load(i64* %{{.+}}, i32 5), !dbg -; CHECK-NEXT: inttoptr i64 %{{.+}} to i8* +; CHECK: call i64 @__tsan_atomic64_load(ptr %a, i32 5), !dbg +; CHECK-NEXT: inttoptr i64 %{{.+}} to ptr -define void @atomic64_store_unordered(i64* %a) nounwind uwtable { +define void @atomic64_store_unordered(ptr %a) nounwind uwtable { entry: - store atomic i64 0, i64* %a unordered, align 8, !dbg !7 + store atomic i64 0, ptr %a unordered, align 8, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_store_unordered -; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 0), !dbg +; CHECK: call void @__tsan_atomic64_store(ptr %a, i64 0, i32 0), !dbg -define void @atomic64_store_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_store_monotonic(ptr %a) nounwind uwtable { entry: - store atomic i64 0, i64* %a monotonic, align 8, !dbg !7 + store atomic i64 0, ptr %a monotonic, align 8, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_store_monotonic -; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 0), !dbg +; CHECK: call void @__tsan_atomic64_store(ptr %a, i64 0, i32 0), !dbg -define void @atomic64_store_release(i64* %a) nounwind uwtable { +define void @atomic64_store_release(ptr %a) nounwind uwtable { entry: - store atomic i64 0, i64* %a release, align 8, !dbg !7 + store atomic i64 0, ptr %a release, align 8, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_store_release -; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 3), !dbg +; CHECK: call void @__tsan_atomic64_store(ptr %a, i64 0, i32 3), !dbg -define void @atomic64_store_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_store_seq_cst(ptr %a) nounwind uwtable { entry: - store atomic i64 0, i64* %a seq_cst, align 8, !dbg !7 + store atomic i64 0, ptr %a seq_cst, align 8, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_store_seq_cst -; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 5), !dbg +; CHECK: call void @__tsan_atomic64_store(ptr %a, i64 0, i32 5), !dbg -define void @atomic64_store_seq_cst_ptr_ty(i8** %a, i8* %v) nounwind uwtable { +define void @atomic64_store_seq_cst_ptr_ty(ptr %a, ptr %v) nounwind uwtable { entry: - store atomic i8* %v, i8** %a seq_cst, align 8, !dbg !7 + store atomic ptr %v, ptr %a seq_cst, align 8, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_store_seq_cst -; CHECK: %{{.*}} = bitcast i8** %{{.*}} to i64* -; CHECK-NEXT: %{{.*}} = ptrtoint i8* %{{.*}} to i64 -; CHECK-NEXT: call void @__tsan_atomic64_store(i64* %{{.*}}, i64 %{{.*}}, i32 5), !dbg - -define void @atomic64_xchg_monotonic(i64* %a) nounwind uwtable { +; CHECK: call void @__tsan_atomic64_store(ptr %a, i64 %{{.*}}, i32 5), !dbg +define void @atomic64_xchg_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i64* %a, i64 0 monotonic, !dbg !7 + atomicrmw xchg ptr %a, i64 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_xchg_monotonic -; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_exchange(ptr %a, i64 0, i32 0), !dbg -define void @atomic64_add_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_add_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw add i64* %a, i64 0 monotonic, !dbg !7 + atomicrmw add ptr %a, i64 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_add_monotonic -; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_add(ptr %a, i64 0, i32 0), !dbg -define void @atomic64_sub_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_sub_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw sub i64* %a, i64 0 monotonic, !dbg !7 + atomicrmw sub ptr %a, i64 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_sub_monotonic -; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_sub(ptr %a, i64 0, i32 0), !dbg -define void @atomic64_and_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_and_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw and i64* %a, i64 0 monotonic, !dbg !7 + atomicrmw and ptr %a, i64 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_and_monotonic -; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_and(ptr %a, i64 0, i32 0), !dbg -define void @atomic64_or_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_or_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw or i64* %a, i64 0 monotonic, !dbg !7 + atomicrmw or ptr %a, i64 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_or_monotonic -; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_or(ptr %a, i64 0, i32 0), !dbg -define void @atomic64_xor_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_xor_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw xor i64* %a, i64 0 monotonic, !dbg !7 + atomicrmw xor ptr %a, i64 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_xor_monotonic -; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_xor(ptr %a, i64 0, i32 0), !dbg -define void @atomic64_nand_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_nand_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw nand i64* %a, i64 0 monotonic, !dbg !7 + atomicrmw nand ptr %a, i64 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_nand_monotonic -; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_nand(ptr %a, i64 0, i32 0), !dbg -define void @atomic64_xchg_acquire(i64* %a) nounwind uwtable { +define void @atomic64_xchg_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i64* %a, i64 0 acquire, !dbg !7 + atomicrmw xchg ptr %a, i64 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_xchg_acquire -; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 2), !dbg +; CHECK: call i64 @__tsan_atomic64_exchange(ptr %a, i64 0, i32 2), !dbg -define void @atomic64_add_acquire(i64* %a) nounwind uwtable { +define void @atomic64_add_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw add i64* %a, i64 0 acquire, !dbg !7 + atomicrmw add ptr %a, i64 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_add_acquire -; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 2), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_add(ptr %a, i64 0, i32 2), !dbg -define void @atomic64_sub_acquire(i64* %a) nounwind uwtable { +define void @atomic64_sub_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw sub i64* %a, i64 0 acquire, !dbg !7 + atomicrmw sub ptr %a, i64 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_sub_acquire -; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 2), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_sub(ptr %a, i64 0, i32 2), !dbg -define void @atomic64_and_acquire(i64* %a) nounwind uwtable { +define void @atomic64_and_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw and i64* %a, i64 0 acquire, !dbg !7 + atomicrmw and ptr %a, i64 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_and_acquire -; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 2), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_and(ptr %a, i64 0, i32 2), !dbg -define void @atomic64_or_acquire(i64* %a) nounwind uwtable { +define void @atomic64_or_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw or i64* %a, i64 0 acquire, !dbg !7 + atomicrmw or ptr %a, i64 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_or_acquire -; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 2), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_or(ptr %a, i64 0, i32 2), !dbg -define void @atomic64_xor_acquire(i64* %a) nounwind uwtable { +define void @atomic64_xor_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw xor i64* %a, i64 0 acquire, !dbg !7 + atomicrmw xor ptr %a, i64 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_xor_acquire -; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 2), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_xor(ptr %a, i64 0, i32 2), !dbg -define void @atomic64_nand_acquire(i64* %a) nounwind uwtable { +define void @atomic64_nand_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw nand i64* %a, i64 0 acquire, !dbg !7 + atomicrmw nand ptr %a, i64 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_nand_acquire -; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 2), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_nand(ptr %a, i64 0, i32 2), !dbg -define void @atomic64_xchg_release(i64* %a) nounwind uwtable { +define void @atomic64_xchg_release(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i64* %a, i64 0 release, !dbg !7 + atomicrmw xchg ptr %a, i64 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_xchg_release -; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 3), !dbg +; CHECK: call i64 @__tsan_atomic64_exchange(ptr %a, i64 0, i32 3), !dbg -define void @atomic64_add_release(i64* %a) nounwind uwtable { +define void @atomic64_add_release(ptr %a) nounwind uwtable { entry: - atomicrmw add i64* %a, i64 0 release, !dbg !7 + atomicrmw add ptr %a, i64 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_add_release -; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 3), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_add(ptr %a, i64 0, i32 3), !dbg -define void @atomic64_sub_release(i64* %a) nounwind uwtable { +define void @atomic64_sub_release(ptr %a) nounwind uwtable { entry: - atomicrmw sub i64* %a, i64 0 release, !dbg !7 + atomicrmw sub ptr %a, i64 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_sub_release -; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 3), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_sub(ptr %a, i64 0, i32 3), !dbg -define void @atomic64_and_release(i64* %a) nounwind uwtable { +define void @atomic64_and_release(ptr %a) nounwind uwtable { entry: - atomicrmw and i64* %a, i64 0 release, !dbg !7 + atomicrmw and ptr %a, i64 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_and_release -; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 3), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_and(ptr %a, i64 0, i32 3), !dbg -define void @atomic64_or_release(i64* %a) nounwind uwtable { +define void @atomic64_or_release(ptr %a) nounwind uwtable { entry: - atomicrmw or i64* %a, i64 0 release, !dbg !7 + atomicrmw or ptr %a, i64 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_or_release -; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 3), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_or(ptr %a, i64 0, i32 3), !dbg -define void @atomic64_xor_release(i64* %a) nounwind uwtable { +define void @atomic64_xor_release(ptr %a) nounwind uwtable { entry: - atomicrmw xor i64* %a, i64 0 release, !dbg !7 + atomicrmw xor ptr %a, i64 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_xor_release -; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 3), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_xor(ptr %a, i64 0, i32 3), !dbg -define void @atomic64_nand_release(i64* %a) nounwind uwtable { +define void @atomic64_nand_release(ptr %a) nounwind uwtable { entry: - atomicrmw nand i64* %a, i64 0 release, !dbg !7 + atomicrmw nand ptr %a, i64 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_nand_release -; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 3), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_nand(ptr %a, i64 0, i32 3), !dbg -define void @atomic64_xchg_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_xchg_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i64* %a, i64 0 acq_rel, !dbg !7 + atomicrmw xchg ptr %a, i64 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_xchg_acq_rel -; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 4), !dbg +; CHECK: call i64 @__tsan_atomic64_exchange(ptr %a, i64 0, i32 4), !dbg -define void @atomic64_add_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_add_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw add i64* %a, i64 0 acq_rel, !dbg !7 + atomicrmw add ptr %a, i64 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_add_acq_rel -; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 4), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_add(ptr %a, i64 0, i32 4), !dbg -define void @atomic64_sub_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_sub_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw sub i64* %a, i64 0 acq_rel, !dbg !7 + atomicrmw sub ptr %a, i64 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_sub_acq_rel -; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 4), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_sub(ptr %a, i64 0, i32 4), !dbg -define void @atomic64_and_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_and_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw and i64* %a, i64 0 acq_rel, !dbg !7 + atomicrmw and ptr %a, i64 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_and_acq_rel -; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 4), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_and(ptr %a, i64 0, i32 4), !dbg -define void @atomic64_or_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_or_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw or i64* %a, i64 0 acq_rel, !dbg !7 + atomicrmw or ptr %a, i64 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_or_acq_rel -; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 4), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_or(ptr %a, i64 0, i32 4), !dbg -define void @atomic64_xor_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_xor_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw xor i64* %a, i64 0 acq_rel, !dbg !7 + atomicrmw xor ptr %a, i64 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_xor_acq_rel -; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 4), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_xor(ptr %a, i64 0, i32 4), !dbg -define void @atomic64_nand_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_nand_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw nand i64* %a, i64 0 acq_rel, !dbg !7 + atomicrmw nand ptr %a, i64 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_nand_acq_rel -; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 4), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_nand(ptr %a, i64 0, i32 4), !dbg -define void @atomic64_xchg_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_xchg_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i64* %a, i64 0 seq_cst, !dbg !7 + atomicrmw xchg ptr %a, i64 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_xchg_seq_cst -; CHECK: call i64 @__tsan_atomic64_exchange(i64* %a, i64 0, i32 5), !dbg +; CHECK: call i64 @__tsan_atomic64_exchange(ptr %a, i64 0, i32 5), !dbg -define void @atomic64_add_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_add_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw add i64* %a, i64 0 seq_cst, !dbg !7 + atomicrmw add ptr %a, i64 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_add_seq_cst -; CHECK: call i64 @__tsan_atomic64_fetch_add(i64* %a, i64 0, i32 5), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_add(ptr %a, i64 0, i32 5), !dbg -define void @atomic64_sub_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_sub_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw sub i64* %a, i64 0 seq_cst, !dbg !7 + atomicrmw sub ptr %a, i64 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_sub_seq_cst -; CHECK: call i64 @__tsan_atomic64_fetch_sub(i64* %a, i64 0, i32 5), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_sub(ptr %a, i64 0, i32 5), !dbg -define void @atomic64_and_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_and_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw and i64* %a, i64 0 seq_cst, !dbg !7 + atomicrmw and ptr %a, i64 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_and_seq_cst -; CHECK: call i64 @__tsan_atomic64_fetch_and(i64* %a, i64 0, i32 5), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_and(ptr %a, i64 0, i32 5), !dbg -define void @atomic64_or_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_or_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw or i64* %a, i64 0 seq_cst, !dbg !7 + atomicrmw or ptr %a, i64 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_or_seq_cst -; CHECK: call i64 @__tsan_atomic64_fetch_or(i64* %a, i64 0, i32 5), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_or(ptr %a, i64 0, i32 5), !dbg -define void @atomic64_xor_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_xor_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw xor i64* %a, i64 0 seq_cst, !dbg !7 + atomicrmw xor ptr %a, i64 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_xor_seq_cst -; CHECK: call i64 @__tsan_atomic64_fetch_xor(i64* %a, i64 0, i32 5), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_xor(ptr %a, i64 0, i32 5), !dbg -define void @atomic64_nand_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_nand_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw nand i64* %a, i64 0 seq_cst, !dbg !7 + atomicrmw nand ptr %a, i64 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_nand_seq_cst -; CHECK: call i64 @__tsan_atomic64_fetch_nand(i64* %a, i64 0, i32 5), !dbg +; CHECK: call i64 @__tsan_atomic64_fetch_nand(ptr %a, i64 0, i32 5), !dbg -define void @atomic64_cas_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_cas_monotonic(ptr %a) nounwind uwtable { entry: - cmpxchg i64* %a, i64 0, i64 1 monotonic monotonic, !dbg !7 - cmpxchg i64* %a, i64 0, i64 1 monotonic acquire, !dbg !7 - cmpxchg i64* %a, i64 0, i64 1 monotonic seq_cst, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 monotonic monotonic, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 monotonic acquire, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 monotonic seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_cas_monotonic -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 0, i32 0), !dbg -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 0, i32 2), !dbg -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 0, i32 5), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 0, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 0, i32 2), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 0, i32 5), !dbg -define void @atomic64_cas_acquire(i64* %a) nounwind uwtable { +define void @atomic64_cas_acquire(ptr %a) nounwind uwtable { entry: - cmpxchg i64* %a, i64 0, i64 1 acquire monotonic, !dbg !7 - cmpxchg i64* %a, i64 0, i64 1 acquire acquire, !dbg !7 - cmpxchg i64* %a, i64 0, i64 1 acquire seq_cst, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 acquire monotonic, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 acquire acquire, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 acquire seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_cas_acquire -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 2, i32 0), !dbg -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 2, i32 2), !dbg -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 2, i32 5), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 2, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 2, i32 2), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 2, i32 5), !dbg -define void @atomic64_cas_release(i64* %a) nounwind uwtable { +define void @atomic64_cas_release(ptr %a) nounwind uwtable { entry: - cmpxchg i64* %a, i64 0, i64 1 release monotonic, !dbg !7 - cmpxchg i64* %a, i64 0, i64 1 release acquire, !dbg !7 - cmpxchg i64* %a, i64 0, i64 1 release seq_cst, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 release monotonic, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 release acquire, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 release seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_cas_release -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 3, i32 0), !dbg -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 3, i32 2), !dbg -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 3, i32 5), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 3, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 3, i32 2), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 3, i32 5), !dbg -define void @atomic64_cas_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_cas_acq_rel(ptr %a) nounwind uwtable { entry: - cmpxchg i64* %a, i64 0, i64 1 acq_rel monotonic, !dbg !7 - cmpxchg i64* %a, i64 0, i64 1 acq_rel acquire, !dbg !7 - cmpxchg i64* %a, i64 0, i64 1 acq_rel seq_cst, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 acq_rel monotonic, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 acq_rel acquire, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 acq_rel seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_cas_acq_rel -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 4, i32 0), !dbg -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 4, i32 2), !dbg -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 4, i32 5), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 4, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 4, i32 2), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 4, i32 5), !dbg -define void @atomic64_cas_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_cas_seq_cst(ptr %a) nounwind uwtable { entry: - cmpxchg i64* %a, i64 0, i64 1 seq_cst monotonic, !dbg !7 - cmpxchg i64* %a, i64 0, i64 1 seq_cst acquire, !dbg !7 - cmpxchg i64* %a, i64 0, i64 1 seq_cst seq_cst, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 seq_cst monotonic, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 seq_cst acquire, !dbg !7 + cmpxchg ptr %a, i64 0, i64 1 seq_cst seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic64_cas_seq_cst -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 5, i32 0), !dbg -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 5, i32 2), !dbg -; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(i64* %a, i64 0, i64 1, i32 5, i32 5), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 5, i32 0), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 5, i32 2), !dbg +; CHECK: call i64 @__tsan_atomic64_compare_exchange_val(ptr %a, i64 0, i64 1, i32 5, i32 5), !dbg -define void @atomic64_cas_seq_cst_ptr_ty(i8** %a, i8* %v1, i8* %v2) nounwind uwtable { +define void @atomic64_cas_seq_cst_ptr_ty(ptr %a, ptr %v1, ptr %v2) nounwind uwtable { entry: - cmpxchg i8** %a, i8* %v1, i8* %v2 seq_cst seq_cst, !dbg !7 + cmpxchg ptr %a, ptr %v1, ptr %v2 seq_cst seq_cst, !dbg !7 ret void } ; CHECK-LABEL: atomic64_cas_seq_cst -; CHECK: {{.*}} = ptrtoint i8* %v1 to i64 -; CHECK-NEXT: {{.*}} = ptrtoint i8* %v2 to i64 -; CHECK-NEXT: {{.*}} = bitcast i8** %a to i64* -; CHECK-NEXT: {{.*}} = call i64 @__tsan_atomic64_compare_exchange_val(i64* {{.*}}, i64 {{.*}}, i64 {{.*}}, i32 5, i32 5), !dbg +; CHECK: {{.*}} = ptrtoint ptr %v1 to i64 +; CHECK-NEXT: {{.*}} = ptrtoint ptr %v2 to i64 +; CHECK-NEXT: {{.*}} = call i64 @__tsan_atomic64_compare_exchange_val(ptr {{.*}}, i64 {{.*}}, i64 {{.*}}, i32 5, i32 5), !dbg ; CHECK-NEXT: {{.*}} = icmp eq i64 -; CHECK-NEXT: {{.*}} = inttoptr i64 {{.*}} to i8* -; CHECK-NEXT: {{.*}} = insertvalue { i8*, i1 } undef, i8* {{.*}}, 0 -; CHECK-NEXT: {{.*}} = insertvalue { i8*, i1 } {{.*}}, i1 {{.*}}, 1 +; CHECK-NEXT: {{.*}} = inttoptr i64 {{.*}} to ptr +; CHECK-NEXT: {{.*}} = insertvalue { ptr, i1 } undef, ptr {{.*}}, 0 +; CHECK-NEXT: {{.*}} = insertvalue { ptr, i1 } {{.*}}, i1 {{.*}}, 1 -define i128 @atomic128_load_unordered(i128* %a) nounwind uwtable { +define i128 @atomic128_load_unordered(ptr %a) nounwind uwtable { entry: - %0 = load atomic i128, i128* %a unordered, align 16, !dbg !7 + %0 = load atomic i128, ptr %a unordered, align 16, !dbg !7 ret i128 %0, !dbg !7 } ; CHECK-LABEL: atomic128_load_unordered -; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 0), !dbg +; CHECK: call i128 @__tsan_atomic128_load(ptr %a, i32 0), !dbg -define i128 @atomic128_load_monotonic(i128* %a) nounwind uwtable { +define i128 @atomic128_load_monotonic(ptr %a) nounwind uwtable { entry: - %0 = load atomic i128, i128* %a monotonic, align 16, !dbg !7 + %0 = load atomic i128, ptr %a monotonic, align 16, !dbg !7 ret i128 %0, !dbg !7 } ; CHECK-LABEL: atomic128_load_monotonic -; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 0), !dbg +; CHECK: call i128 @__tsan_atomic128_load(ptr %a, i32 0), !dbg -define i128 @atomic128_load_acquire(i128* %a) nounwind uwtable { +define i128 @atomic128_load_acquire(ptr %a) nounwind uwtable { entry: - %0 = load atomic i128, i128* %a acquire, align 16, !dbg !7 + %0 = load atomic i128, ptr %a acquire, align 16, !dbg !7 ret i128 %0, !dbg !7 } ; CHECK-LABEL: atomic128_load_acquire -; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 2), !dbg +; CHECK: call i128 @__tsan_atomic128_load(ptr %a, i32 2), !dbg -define i128 @atomic128_load_seq_cst(i128* %a) nounwind uwtable { +define i128 @atomic128_load_seq_cst(ptr %a) nounwind uwtable { entry: - %0 = load atomic i128, i128* %a seq_cst, align 16, !dbg !7 + %0 = load atomic i128, ptr %a seq_cst, align 16, !dbg !7 ret i128 %0, !dbg !7 } ; CHECK-LABEL: atomic128_load_seq_cst -; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 5), !dbg +; CHECK: call i128 @__tsan_atomic128_load(ptr %a, i32 5), !dbg -define void @atomic128_store_unordered(i128* %a) nounwind uwtable { +define void @atomic128_store_unordered(ptr %a) nounwind uwtable { entry: - store atomic i128 0, i128* %a unordered, align 16, !dbg !7 + store atomic i128 0, ptr %a unordered, align 16, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_store_unordered -; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 0), !dbg +; CHECK: call void @__tsan_atomic128_store(ptr %a, i128 0, i32 0), !dbg -define void @atomic128_store_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_store_monotonic(ptr %a) nounwind uwtable { entry: - store atomic i128 0, i128* %a monotonic, align 16, !dbg !7 + store atomic i128 0, ptr %a monotonic, align 16, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_store_monotonic -; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 0), !dbg +; CHECK: call void @__tsan_atomic128_store(ptr %a, i128 0, i32 0), !dbg -define void @atomic128_store_release(i128* %a) nounwind uwtable { +define void @atomic128_store_release(ptr %a) nounwind uwtable { entry: - store atomic i128 0, i128* %a release, align 16, !dbg !7 + store atomic i128 0, ptr %a release, align 16, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_store_release -; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 3), !dbg +; CHECK: call void @__tsan_atomic128_store(ptr %a, i128 0, i32 3), !dbg -define void @atomic128_store_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_store_seq_cst(ptr %a) nounwind uwtable { entry: - store atomic i128 0, i128* %a seq_cst, align 16, !dbg !7 + store atomic i128 0, ptr %a seq_cst, align 16, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_store_seq_cst -; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 5), !dbg +; CHECK: call void @__tsan_atomic128_store(ptr %a, i128 0, i32 5), !dbg -define void @atomic128_xchg_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_xchg_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i128* %a, i128 0 monotonic, !dbg !7 + atomicrmw xchg ptr %a, i128 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_xchg_monotonic -; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 0), !dbg +; CHECK: call i128 @__tsan_atomic128_exchange(ptr %a, i128 0, i32 0), !dbg -define void @atomic128_add_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_add_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw add i128* %a, i128 0 monotonic, !dbg !7 + atomicrmw add ptr %a, i128 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_add_monotonic -; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 0), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_add(ptr %a, i128 0, i32 0), !dbg -define void @atomic128_sub_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_sub_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw sub i128* %a, i128 0 monotonic, !dbg !7 + atomicrmw sub ptr %a, i128 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_sub_monotonic -; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 0), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_sub(ptr %a, i128 0, i32 0), !dbg -define void @atomic128_and_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_and_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw and i128* %a, i128 0 monotonic, !dbg !7 + atomicrmw and ptr %a, i128 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_and_monotonic -; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 0), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_and(ptr %a, i128 0, i32 0), !dbg -define void @atomic128_or_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_or_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw or i128* %a, i128 0 monotonic, !dbg !7 + atomicrmw or ptr %a, i128 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_or_monotonic -; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 0), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_or(ptr %a, i128 0, i32 0), !dbg -define void @atomic128_xor_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_xor_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw xor i128* %a, i128 0 monotonic, !dbg !7 + atomicrmw xor ptr %a, i128 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_xor_monotonic -; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 0), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_xor(ptr %a, i128 0, i32 0), !dbg -define void @atomic128_nand_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_nand_monotonic(ptr %a) nounwind uwtable { entry: - atomicrmw nand i128* %a, i128 0 monotonic, !dbg !7 + atomicrmw nand ptr %a, i128 0 monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_nand_monotonic -; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 0), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_nand(ptr %a, i128 0, i32 0), !dbg -define void @atomic128_xchg_acquire(i128* %a) nounwind uwtable { +define void @atomic128_xchg_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i128* %a, i128 0 acquire, !dbg !7 + atomicrmw xchg ptr %a, i128 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_xchg_acquire -; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 2), !dbg +; CHECK: call i128 @__tsan_atomic128_exchange(ptr %a, i128 0, i32 2), !dbg -define void @atomic128_add_acquire(i128* %a) nounwind uwtable { +define void @atomic128_add_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw add i128* %a, i128 0 acquire, !dbg !7 + atomicrmw add ptr %a, i128 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_add_acquire -; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 2), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_add(ptr %a, i128 0, i32 2), !dbg -define void @atomic128_sub_acquire(i128* %a) nounwind uwtable { +define void @atomic128_sub_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw sub i128* %a, i128 0 acquire, !dbg !7 + atomicrmw sub ptr %a, i128 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_sub_acquire -; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 2), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_sub(ptr %a, i128 0, i32 2), !dbg -define void @atomic128_and_acquire(i128* %a) nounwind uwtable { +define void @atomic128_and_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw and i128* %a, i128 0 acquire, !dbg !7 + atomicrmw and ptr %a, i128 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_and_acquire -; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 2), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_and(ptr %a, i128 0, i32 2), !dbg -define void @atomic128_or_acquire(i128* %a) nounwind uwtable { +define void @atomic128_or_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw or i128* %a, i128 0 acquire, !dbg !7 + atomicrmw or ptr %a, i128 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_or_acquire -; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 2), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_or(ptr %a, i128 0, i32 2), !dbg -define void @atomic128_xor_acquire(i128* %a) nounwind uwtable { +define void @atomic128_xor_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw xor i128* %a, i128 0 acquire, !dbg !7 + atomicrmw xor ptr %a, i128 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_xor_acquire -; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 2), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_xor(ptr %a, i128 0, i32 2), !dbg -define void @atomic128_nand_acquire(i128* %a) nounwind uwtable { +define void @atomic128_nand_acquire(ptr %a) nounwind uwtable { entry: - atomicrmw nand i128* %a, i128 0 acquire, !dbg !7 + atomicrmw nand ptr %a, i128 0 acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_nand_acquire -; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 2), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_nand(ptr %a, i128 0, i32 2), !dbg -define void @atomic128_xchg_release(i128* %a) nounwind uwtable { +define void @atomic128_xchg_release(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i128* %a, i128 0 release, !dbg !7 + atomicrmw xchg ptr %a, i128 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_xchg_release -; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 3), !dbg +; CHECK: call i128 @__tsan_atomic128_exchange(ptr %a, i128 0, i32 3), !dbg -define void @atomic128_add_release(i128* %a) nounwind uwtable { +define void @atomic128_add_release(ptr %a) nounwind uwtable { entry: - atomicrmw add i128* %a, i128 0 release, !dbg !7 + atomicrmw add ptr %a, i128 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_add_release -; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 3), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_add(ptr %a, i128 0, i32 3), !dbg -define void @atomic128_sub_release(i128* %a) nounwind uwtable { +define void @atomic128_sub_release(ptr %a) nounwind uwtable { entry: - atomicrmw sub i128* %a, i128 0 release, !dbg !7 + atomicrmw sub ptr %a, i128 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_sub_release -; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 3), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_sub(ptr %a, i128 0, i32 3), !dbg -define void @atomic128_and_release(i128* %a) nounwind uwtable { +define void @atomic128_and_release(ptr %a) nounwind uwtable { entry: - atomicrmw and i128* %a, i128 0 release, !dbg !7 + atomicrmw and ptr %a, i128 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_and_release -; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 3), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_and(ptr %a, i128 0, i32 3), !dbg -define void @atomic128_or_release(i128* %a) nounwind uwtable { +define void @atomic128_or_release(ptr %a) nounwind uwtable { entry: - atomicrmw or i128* %a, i128 0 release, !dbg !7 + atomicrmw or ptr %a, i128 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_or_release -; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 3), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_or(ptr %a, i128 0, i32 3), !dbg -define void @atomic128_xor_release(i128* %a) nounwind uwtable { +define void @atomic128_xor_release(ptr %a) nounwind uwtable { entry: - atomicrmw xor i128* %a, i128 0 release, !dbg !7 + atomicrmw xor ptr %a, i128 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_xor_release -; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 3), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_xor(ptr %a, i128 0, i32 3), !dbg -define void @atomic128_nand_release(i128* %a) nounwind uwtable { +define void @atomic128_nand_release(ptr %a) nounwind uwtable { entry: - atomicrmw nand i128* %a, i128 0 release, !dbg !7 + atomicrmw nand ptr %a, i128 0 release, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_nand_release -; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 3), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_nand(ptr %a, i128 0, i32 3), !dbg -define void @atomic128_xchg_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_xchg_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i128* %a, i128 0 acq_rel, !dbg !7 + atomicrmw xchg ptr %a, i128 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_xchg_acq_rel -; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 4), !dbg +; CHECK: call i128 @__tsan_atomic128_exchange(ptr %a, i128 0, i32 4), !dbg -define void @atomic128_add_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_add_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw add i128* %a, i128 0 acq_rel, !dbg !7 + atomicrmw add ptr %a, i128 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_add_acq_rel -; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 4), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_add(ptr %a, i128 0, i32 4), !dbg -define void @atomic128_sub_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_sub_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw sub i128* %a, i128 0 acq_rel, !dbg !7 + atomicrmw sub ptr %a, i128 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_sub_acq_rel -; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 4), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_sub(ptr %a, i128 0, i32 4), !dbg -define void @atomic128_and_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_and_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw and i128* %a, i128 0 acq_rel, !dbg !7 + atomicrmw and ptr %a, i128 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_and_acq_rel -; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 4), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_and(ptr %a, i128 0, i32 4), !dbg -define void @atomic128_or_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_or_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw or i128* %a, i128 0 acq_rel, !dbg !7 + atomicrmw or ptr %a, i128 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_or_acq_rel -; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 4), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_or(ptr %a, i128 0, i32 4), !dbg -define void @atomic128_xor_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_xor_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw xor i128* %a, i128 0 acq_rel, !dbg !7 + atomicrmw xor ptr %a, i128 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_xor_acq_rel -; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 4), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_xor(ptr %a, i128 0, i32 4), !dbg -define void @atomic128_nand_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_nand_acq_rel(ptr %a) nounwind uwtable { entry: - atomicrmw nand i128* %a, i128 0 acq_rel, !dbg !7 + atomicrmw nand ptr %a, i128 0 acq_rel, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_nand_acq_rel -; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 4), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_nand(ptr %a, i128 0, i32 4), !dbg -define void @atomic128_xchg_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_xchg_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw xchg i128* %a, i128 0 seq_cst, !dbg !7 + atomicrmw xchg ptr %a, i128 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_xchg_seq_cst -; CHECK: call i128 @__tsan_atomic128_exchange(i128* %a, i128 0, i32 5), !dbg +; CHECK: call i128 @__tsan_atomic128_exchange(ptr %a, i128 0, i32 5), !dbg -define void @atomic128_add_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_add_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw add i128* %a, i128 0 seq_cst, !dbg !7 + atomicrmw add ptr %a, i128 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_add_seq_cst -; CHECK: call i128 @__tsan_atomic128_fetch_add(i128* %a, i128 0, i32 5), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_add(ptr %a, i128 0, i32 5), !dbg -define void @atomic128_sub_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_sub_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw sub i128* %a, i128 0 seq_cst, !dbg !7 + atomicrmw sub ptr %a, i128 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_sub_seq_cst -; CHECK: call i128 @__tsan_atomic128_fetch_sub(i128* %a, i128 0, i32 5), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_sub(ptr %a, i128 0, i32 5), !dbg -define void @atomic128_and_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_and_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw and i128* %a, i128 0 seq_cst, !dbg !7 + atomicrmw and ptr %a, i128 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_and_seq_cst -; CHECK: call i128 @__tsan_atomic128_fetch_and(i128* %a, i128 0, i32 5), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_and(ptr %a, i128 0, i32 5), !dbg -define void @atomic128_or_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_or_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw or i128* %a, i128 0 seq_cst, !dbg !7 + atomicrmw or ptr %a, i128 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_or_seq_cst -; CHECK: call i128 @__tsan_atomic128_fetch_or(i128* %a, i128 0, i32 5), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_or(ptr %a, i128 0, i32 5), !dbg -define void @atomic128_xor_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_xor_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw xor i128* %a, i128 0 seq_cst, !dbg !7 + atomicrmw xor ptr %a, i128 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_xor_seq_cst -; CHECK: call i128 @__tsan_atomic128_fetch_xor(i128* %a, i128 0, i32 5), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_xor(ptr %a, i128 0, i32 5), !dbg -define void @atomic128_nand_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_nand_seq_cst(ptr %a) nounwind uwtable { entry: - atomicrmw nand i128* %a, i128 0 seq_cst, !dbg !7 + atomicrmw nand ptr %a, i128 0 seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_nand_seq_cst -; CHECK: call i128 @__tsan_atomic128_fetch_nand(i128* %a, i128 0, i32 5), !dbg +; CHECK: call i128 @__tsan_atomic128_fetch_nand(ptr %a, i128 0, i32 5), !dbg -define void @atomic128_cas_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_cas_monotonic(ptr %a) nounwind uwtable { entry: - cmpxchg i128* %a, i128 0, i128 1 monotonic monotonic, !dbg !7 + cmpxchg ptr %a, i128 0, i128 1 monotonic monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_cas_monotonic -; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 0, i32 0), !dbg +; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(ptr %a, i128 0, i128 1, i32 0, i32 0), !dbg -define void @atomic128_cas_acquire(i128* %a) nounwind uwtable { +define void @atomic128_cas_acquire(ptr %a) nounwind uwtable { entry: - cmpxchg i128* %a, i128 0, i128 1 acquire acquire, !dbg !7 + cmpxchg ptr %a, i128 0, i128 1 acquire acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_cas_acquire -; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 2, i32 2), !dbg +; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(ptr %a, i128 0, i128 1, i32 2, i32 2), !dbg -define void @atomic128_cas_release(i128* %a) nounwind uwtable { +define void @atomic128_cas_release(ptr %a) nounwind uwtable { entry: - cmpxchg i128* %a, i128 0, i128 1 release monotonic, !dbg !7 + cmpxchg ptr %a, i128 0, i128 1 release monotonic, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_cas_release -; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 3, i32 0), !dbg +; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(ptr %a, i128 0, i128 1, i32 3, i32 0), !dbg -define void @atomic128_cas_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_cas_acq_rel(ptr %a) nounwind uwtable { entry: - cmpxchg i128* %a, i128 0, i128 1 acq_rel acquire, !dbg !7 + cmpxchg ptr %a, i128 0, i128 1 acq_rel acquire, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_cas_acq_rel -; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 4, i32 2), !dbg +; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(ptr %a, i128 0, i128 1, i32 4, i32 2), !dbg -define void @atomic128_cas_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_cas_seq_cst(ptr %a) nounwind uwtable { entry: - cmpxchg i128* %a, i128 0, i128 1 seq_cst seq_cst, !dbg !7 + cmpxchg ptr %a, i128 0, i128 1 seq_cst seq_cst, !dbg !7 ret void, !dbg !7 } ; CHECK-LABEL: atomic128_cas_seq_cst -; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(i128* %a, i128 0, i128 1, i32 5, i32 5), !dbg +; CHECK: call i128 @__tsan_atomic128_compare_exchange_val(ptr %a, i128 0, i128 1, i32 5, i32 5), !dbg define void @atomic_signal_fence_acquire() nounwind uwtable { entry: diff --git a/llvm/test/Instrumentation/ThreadSanitizer/capture.ll b/llvm/test/Instrumentation/ThreadSanitizer/capture.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/capture.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/capture.ll @@ -2,16 +2,16 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -declare void @escape(i32*) +declare void @escape(ptr) -@sink = global i32* null, align 4 +@sink = global ptr null, align 4 define void @captured0() nounwind uwtable sanitize_thread { entry: %ptr = alloca i32, align 4 ; escapes due to call - call void @escape(i32* %ptr) - store i32 42, i32* %ptr, align 4 + call void @escape(ptr %ptr) + store i32 42, ptr %ptr, align 4 ret void } ; CHECK-LABEL: define void @captured0 @@ -22,8 +22,8 @@ entry: %ptr = alloca i32, align 4 ; escapes due to store into global - store i32* %ptr, i32** @sink, align 8 - store i32 42, i32* %ptr, align 4 + store ptr %ptr, ptr @sink, align 8 + store i32 42, ptr %ptr, align 4 ret void } ; CHECK-LABEL: define void @captured1 @@ -34,12 +34,12 @@ define void @captured2() nounwind uwtable sanitize_thread { entry: %ptr = alloca i32, align 4 - %tmp = alloca i32*, align 8 + %tmp = alloca ptr, align 8 ; transitive escape - store i32* %ptr, i32** %tmp, align 8 - %0 = load i32*, i32** %tmp, align 8 - store i32* %0, i32** @sink, align 8 - store i32 42, i32* %ptr, align 4 + store ptr %ptr, ptr %tmp, align 8 + %0 = load ptr, ptr %tmp, align 8 + store ptr %0, ptr @sink, align 8 + store i32 42, ptr %ptr, align 4 ret void } ; CHECK-LABEL: define void @captured2 @@ -50,9 +50,9 @@ define void @notcaptured0() nounwind uwtable sanitize_thread { entry: %ptr = alloca i32, align 4 - store i32 42, i32* %ptr, align 4 + store i32 42, ptr %ptr, align 4 ; escapes due to call - call void @escape(i32* %ptr) + call void @escape(ptr %ptr) ret void } ; CHECK-LABEL: define void @notcaptured0 @@ -62,9 +62,9 @@ define void @notcaptured1() nounwind uwtable sanitize_thread { entry: %ptr = alloca i32, align 4 - store i32 42, i32* %ptr, align 4 + store i32 42, ptr %ptr, align 4 ; escapes due to store into global - store i32* %ptr, i32** @sink, align 8 + store ptr %ptr, ptr @sink, align 8 ret void } ; CHECK-LABEL: define void @notcaptured1 @@ -75,12 +75,12 @@ define void @notcaptured2() nounwind uwtable sanitize_thread { entry: %ptr = alloca i32, align 4 - %tmp = alloca i32*, align 8 - store i32 42, i32* %ptr, align 4 + %tmp = alloca ptr, align 8 + store i32 42, ptr %ptr, align 4 ; transitive escape - store i32* %ptr, i32** %tmp, align 8 - %0 = load i32*, i32** %tmp, align 8 - store i32* %0, i32** @sink, align 8 + store ptr %ptr, ptr %tmp, align 8 + %0 = load ptr, ptr %tmp, align 8 + store ptr %0, ptr @sink, align 8 ret void } ; CHECK-LABEL: define void @notcaptured2 diff --git a/llvm/test/Instrumentation/ThreadSanitizer/debug_calls.ll b/llvm/test/Instrumentation/ThreadSanitizer/debug_calls.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/debug_calls.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/debug_calls.ll @@ -2,12 +2,12 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" -define void @Increment(i32* nocapture %0) local_unnamed_addr sanitize_thread !dbg !7 { - call void @llvm.dbg.value(metadata i32* %0, metadata !14, metadata !DIExpression()), !dbg !16 - %2 = load i32, i32* %0, align 4, !dbg !17, !tbaa !18 +define void @Increment(ptr nocapture %0) local_unnamed_addr sanitize_thread !dbg !7 { + call void @llvm.dbg.value(metadata ptr %0, metadata !14, metadata !DIExpression()), !dbg !16 + %2 = load i32, ptr %0, align 4, !dbg !17, !tbaa !18 call void @llvm.dbg.value(metadata i32 %2, metadata !15, metadata !DIExpression()), !dbg !16 %3 = add nsw i32 %2, 1, !dbg !22 - store i32 %3, i32* %0, align 4, !dbg !23, !tbaa !18 + store i32 %3, ptr %0, align 4, !dbg !23, !tbaa !18 ret void, !dbg !24 } ; CHECK-LABEL: define void @Increment diff --git a/llvm/test/Instrumentation/ThreadSanitizer/do-not-instrument-memory-access.ll b/llvm/test/Instrumentation/ThreadSanitizer/do-not-instrument-memory-access.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/do-not-instrument-memory-access.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/do-not-instrument-memory-access.ll @@ -18,39 +18,39 @@ define i32 @test_gep() sanitize_thread { entry: - %pgocount = load i64, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__profc_test_gep, i64 0, i64 0) + %pgocount = load i64, ptr @__profc_test_gep %0 = add i64 %pgocount, 1 - store i64 %0, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__profc_test_gep, i64 0, i64 0) + store i64 %0, ptr @__profc_test_gep - %gcovcount = load i64, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__llvm_gcov_ctr, i64 0, i64 0) + %gcovcount = load i64, ptr @__llvm_gcov_ctr %1 = add i64 %gcovcount, 1 - store i64 %1, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__llvm_gcov_ctr, i64 0, i64 0) + store i64 %1, ptr @__llvm_gcov_ctr - %gcovcount.1 = load i64, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__llvm_gcov_ctr.1, i64 0, i64 0) + %gcovcount.1 = load i64, ptr @__llvm_gcov_ctr.1 %2 = add i64 %gcovcount.1, 1 - store i64 %2, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__llvm_gcov_ctr.1, i64 0, i64 0) + store i64 %2, ptr @__llvm_gcov_ctr.1 ret i32 1 } define i32 @test_bitcast() sanitize_thread { entry: - %0 = load <2 x i64>, <2 x i64>* bitcast ([2 x i64]* @__profc_test_bitcast to <2 x i64>*), align 8 - %.promoted5 = load i64, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__profc_test_bitcast_foo, i64 0, i64 0), align 8 + %0 = load <2 x i64>, ptr @__profc_test_bitcast, align 8 + %.promoted5 = load i64, ptr @__profc_test_bitcast_foo, align 8 %1 = add i64 %.promoted5, 10 %2 = add <2 x i64> %0, - store <2 x i64> %2, <2 x i64>* bitcast ([2 x i64]* @__profc_test_bitcast to <2 x i64>*), align 8 - store i64 %1, i64* getelementptr inbounds ([1 x i64], [1 x i64]* @__profc_test_bitcast_foo, i64 0, i64 0), align 8 + store <2 x i64> %2, ptr @__profc_test_bitcast, align 8 + store i64 %1, ptr @__profc_test_bitcast_foo, align 8 ret i32 undef } define void @test_load() sanitize_thread { entry: - %0 = load i32, i32* @__llvm_gcov_global_state_pred - store i32 1, i32* @__llvm_gcov_global_state_pred + %0 = load i32, ptr @__llvm_gcov_global_state_pred + store i32 1, ptr @__llvm_gcov_global_state_pred - %1 = load i32, i32* @__llvm_gcda_foo - store i32 1, i32* @__llvm_gcda_foo + %1 = load i32, ptr @__llvm_gcda_foo + store i32 1, ptr @__llvm_gcda_foo ret void } diff --git a/llvm/test/Instrumentation/ThreadSanitizer/eh.ll b/llvm/test/Instrumentation/ThreadSanitizer/eh.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/eh.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/eh.ll @@ -35,13 +35,13 @@ ; CHECK: ret i32 0 } -define i32 @func3(i32* %p) sanitize_thread { - %a = load i32, i32* %p +define i32 @func3(ptr %p) sanitize_thread { + %a = load i32, ptr %p ret i32 %a - ; CHECK: define i32 @func3(i32* %p) + ; CHECK: define i32 @func3(ptr %p) ; CHECK: call void @__tsan_func_entry ; CHECK: call void @__tsan_read4 - ; CHECK: %a = load i32, i32* %p + ; CHECK: %a = load i32, ptr %p ; CHECK: call void @__tsan_func_exit() ; CHECK: ret i32 %a } diff --git a/llvm/test/Instrumentation/ThreadSanitizer/missing_dbg.ll b/llvm/test/Instrumentation/ThreadSanitizer/missing_dbg.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/missing_dbg.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/missing_dbg.ll @@ -2,29 +2,29 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -define i32 @with_dbg(i32* %a) sanitize_thread !dbg !3 { +define i32 @with_dbg(ptr %a) sanitize_thread !dbg !3 { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } ; CHECK-LABEL: @with_dbg ; CHECK-NEXT: entry: -; CHECK: call void @__tsan_func_entry(i8* %0), !dbg [[DBG:![0-9]+]] -; CHECK: call void @__tsan_read4(i8* %1), !dbg [[DBG]] +; CHECK: call void @__tsan_func_entry(ptr %0), !dbg [[DBG:![0-9]+]] +; CHECK: call void @__tsan_read4(ptr %a), !dbg [[DBG]] ; CHECK: call void @__tsan_func_exit(), !dbg [[DBG]] -define i32 @without_dbg(i32* %a) sanitize_thread { +define i32 @without_dbg(ptr %a) sanitize_thread { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } ; CHECK-LABEL: @without_dbg ; CHECK-NEXT: entry: -; CHECK-NOT: call void @__tsan_func_entry(i8* %0), !dbg -; CHECK-NOT: call void @__tsan_read4(i8* %1), !dbg +; CHECK-NOT: call void @__tsan_func_entry(ptr %0), !dbg +; CHECK-NOT: call void @__tsan_read4(ptr %1), !dbg ; CHECK-NOT: call void @__tsan_func_exit(), !dbg -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK: call void @__tsan_read4(i8* %1) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK: call void @__tsan_read4(ptr %a) ; CHECK: call void @__tsan_func_exit() !llvm.dbg.cu = !{!0} diff --git a/llvm/test/Instrumentation/ThreadSanitizer/no_sanitize_thread.ll b/llvm/test/Instrumentation/ThreadSanitizer/no_sanitize_thread.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/no_sanitize_thread.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/no_sanitize_thread.ll @@ -4,31 +4,31 @@ target triple = "x86_64-unknown-linux-gnu" ; no sanitize_thread attribute here -define i32 @read_4_bytes(i32* %a) { +define i32 @read_4_bytes(ptr %a) { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } -; CHECK: define i32 @read_4_bytes(i32* %a) { +; CHECK: define i32 @read_4_bytes(ptr %a) { ; CHECK-NEXT: entry: -; CHECK-NEXT: %tmp1 = load i32, i32* %a, align 4 +; CHECK-NEXT: %tmp1 = load i32, ptr %a, align 4 ; CHECK: ret i32 %tmp1 ; no sanitize_thread attribute here -define i32 @read_4_bytes_and_call(i32* %a) { +define i32 @read_4_bytes_and_call(ptr %a) { entry: call void @foo() - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } -; CHECK: define i32 @read_4_bytes_and_call(i32* %a) { +; CHECK: define i32 @read_4_bytes_and_call(ptr %a) { ; CHECK-NEXT: entry: -; CHECK-NEXT: %0 = call i8* @llvm.returnaddress(i32 0) -; CHECK-NEXT: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %0 = call ptr @llvm.returnaddress(i32 0) +; CHECK-NEXT: call void @__tsan_func_entry(ptr %0) ; CHECK-NEXT: call void @foo() -; CHECK-NEXT: %tmp1 = load i32, i32* %a, align 4 +; CHECK-NEXT: %tmp1 = load i32, ptr %a, align 4 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK-NEXT: ret i32 %tmp1 diff --git a/llvm/test/Instrumentation/ThreadSanitizer/read_before_write.ll b/llvm/test/Instrumentation/ThreadSanitizer/read_before_write.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/read_before_write.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/read_before_write.ll @@ -5,11 +5,11 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -define void @IncrementMe(i32* nocapture %ptr) nounwind uwtable sanitize_thread { +define void @IncrementMe(ptr nocapture %ptr) nounwind uwtable sanitize_thread { entry: - %0 = load i32, i32* %ptr, align 4 + %0 = load i32, ptr %ptr, align 4 %inc = add nsw i32 %0, 1 - store i32 %inc, i32* %ptr, align 4 + store i32 %inc, ptr %ptr, align 4 ret void } ; CHECK-LABEL: define void @IncrementMe @@ -21,12 +21,12 @@ ; CHECK-COMPOUND: __tsan_read_write4 ; CHECK: ret void -define void @IncrementMeWithCallInBetween(i32* nocapture %ptr) nounwind uwtable sanitize_thread { +define void @IncrementMeWithCallInBetween(ptr nocapture %ptr) nounwind uwtable sanitize_thread { entry: - %0 = load i32, i32* %ptr, align 4 + %0 = load i32, ptr %ptr, align 4 %inc = add nsw i32 %0, 1 call void @foo() - store i32 %inc, i32* %ptr, align 4 + store i32 %inc, ptr %ptr, align 4 ret void } @@ -37,11 +37,11 @@ declare void @foo() -define void @VolatileLoad(i32* nocapture %ptr) nounwind uwtable sanitize_thread { +define void @VolatileLoad(ptr nocapture %ptr) nounwind uwtable sanitize_thread { entry: - %0 = load volatile i32, i32* %ptr, align 4 + %0 = load volatile i32, ptr %ptr, align 4 %inc = add nsw i32 %0, 1 - store i32 %inc, i32* %ptr, align 4 + store i32 %inc, ptr %ptr, align 4 ret void } ; CHECK-LABEL: define void @VolatileLoad @@ -51,11 +51,11 @@ ; CHECK-COMPOUND-VOLATILE: __tsan_write4 ; CHECK: ret void -define void @VolatileStore(i32* nocapture %ptr) nounwind uwtable sanitize_thread { +define void @VolatileStore(ptr nocapture %ptr) nounwind uwtable sanitize_thread { entry: - %0 = load i32, i32* %ptr, align 4 + %0 = load i32, ptr %ptr, align 4 %inc = add nsw i32 %0, 1 - store volatile i32 %inc, i32* %ptr, align 4 + store volatile i32 %inc, ptr %ptr, align 4 ret void } ; CHECK-LABEL: define void @VolatileStore @@ -65,11 +65,11 @@ ; CHECK-COMPOUND-VOLATILE: __tsan_volatile_write4 ; CHECK: ret void -define void @VolatileBoth(i32* nocapture %ptr) nounwind uwtable sanitize_thread { +define void @VolatileBoth(ptr nocapture %ptr) nounwind uwtable sanitize_thread { entry: - %0 = load volatile i32, i32* %ptr, align 4 + %0 = load volatile i32, ptr %ptr, align 4 %inc = add nsw i32 %0, 1 - store volatile i32 %inc, i32* %ptr, align 4 + store volatile i32 %inc, ptr %ptr, align 4 ret void } ; CHECK-LABEL: define void @VolatileBoth diff --git a/llvm/test/Instrumentation/ThreadSanitizer/read_from_global.ll b/llvm/test/Instrumentation/ThreadSanitizer/read_from_global.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/read_from_global.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/read_from_global.ll @@ -6,7 +6,7 @@ @const_global = external constant i32 define i32 @read_from_const_global() nounwind uwtable sanitize_thread readnone { entry: - %0 = load i32, i32* @const_global, align 4 + %0 = load i32, ptr @const_global, align 4 ret i32 %0 } ; CHECK: define i32 @read_from_const_global @@ -16,7 +16,7 @@ @non_const_global = global i32 0, align 4 define i32 @read_from_non_const_global() nounwind uwtable sanitize_thread readonly { entry: - %0 = load i32, i32* @non_const_global, align 4 + %0 = load i32, ptr @non_const_global, align 4 ret i32 %0 } @@ -28,8 +28,8 @@ define i32 @read_from_const_global_array(i32 %idx) nounwind uwtable sanitize_thread readnone { entry: %idxprom = sext i32 %idx to i64 - %arrayidx = getelementptr inbounds [10 x i32], [10 x i32]* @const_global_array, i64 0, i64 %idxprom - %0 = load i32, i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds [10 x i32], ptr @const_global_array, i64 0, i64 %idxprom + %0 = load i32, ptr %arrayidx, align 4 ret i32 %0 } @@ -37,13 +37,12 @@ ; CHECK-NOT: __tsan ; CHECK: ret i32 -%struct.Foo = type { i32 (...)** } -define void @call_virtual_func(%struct.Foo* %f) uwtable sanitize_thread { +%struct.Foo = type { ptr } +define void @call_virtual_func(ptr %f) uwtable sanitize_thread { entry: - %0 = bitcast %struct.Foo* %f to void (%struct.Foo*)*** - %vtable = load void (%struct.Foo*)**, void (%struct.Foo*)*** %0, align 8, !tbaa !2 - %1 = load void (%struct.Foo*)*, void (%struct.Foo*)** %vtable, align 8 - call void %1(%struct.Foo* %f) + %vtable = load ptr, ptr %f, align 8, !tbaa !2 + %0 = load ptr, ptr %vtable, align 8 + call void %0(ptr %f) ret void } diff --git a/llvm/test/Instrumentation/ThreadSanitizer/sanitize-thread-no-checking.ll b/llvm/test/Instrumentation/ThreadSanitizer/sanitize-thread-no-checking.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/sanitize-thread-no-checking.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/sanitize-thread-no-checking.ll @@ -3,32 +3,32 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define i32 @"\01-[NoCalls dealloc]"(i32* %a) "sanitize_thread_no_checking_at_run_time" { +define i32 @"\01-[NoCalls dealloc]"(ptr %a) "sanitize_thread_no_checking_at_run_time" { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } -; CHECK: define i32 @"\01-[NoCalls dealloc]"(i32* %a) +; CHECK: define i32 @"\01-[NoCalls dealloc]"(ptr %a) ; CHECK-NEXT: entry: -; CHECK-NEXT: %tmp1 = load i32, i32* %a, align 4 +; CHECK-NEXT: %tmp1 = load i32, ptr %a, align 4 ; CHECK-NEXT: ret i32 %tmp1 declare void @"foo"() nounwind -define i32 @"\01-[WithCalls dealloc]"(i32* %a) "sanitize_thread_no_checking_at_run_time" { +define i32 @"\01-[WithCalls dealloc]"(ptr %a) "sanitize_thread_no_checking_at_run_time" { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 call void @foo() ret i32 %tmp1 } -; CHECK: define i32 @"\01-[WithCalls dealloc]"(i32* %a) +; CHECK: define i32 @"\01-[WithCalls dealloc]"(ptr %a) ; CHECK-NEXT: entry: -; CHECK-NEXT: %0 = call i8* @llvm.returnaddress(i32 0) -; CHECK-NEXT: call void @__tsan_func_entry(i8* %0) +; CHECK-NEXT: %0 = call ptr @llvm.returnaddress(i32 0) +; CHECK-NEXT: call void @__tsan_func_entry(ptr %0) ; CHECK-NEXT: call void @__tsan_ignore_thread_begin() -; CHECK-NEXT: %tmp1 = load i32, i32* %a, align 4 +; CHECK-NEXT: %tmp1 = load i32, ptr %a, align 4 ; CHECK-NEXT: call void @foo() ; CHECK-NEXT: call void @__tsan_ignore_thread_end() ; CHECK-NEXT: call void @__tsan_func_exit() diff --git a/llvm/test/Instrumentation/ThreadSanitizer/str-nobuiltin.ll b/llvm/test/Instrumentation/ThreadSanitizer/str-nobuiltin.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/str-nobuiltin.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/str-nobuiltin.ll @@ -4,13 +4,13 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -declare i8* @memchr(i8* %a, i32 %b, i64 %c) nounwind -declare i32 @memcmp(i8* %a, i8* %b, i64 %c) nounwind -declare i32 @strcmp(i8* %a, i8* %b) nounwind -declare i8* @strcpy(i8* %a, i8* %b) nounwind -declare i8* @stpcpy(i8* %a, i8* %b) nounwind -declare i64 @strlen(i8* %a) nounwind -declare i64 @strnlen(i8* %a, i64 %b) nounwind +declare ptr @memchr(ptr %a, i32 %b, i64 %c) nounwind +declare i32 @memcmp(ptr %a, ptr %b, i64 %c) nounwind +declare i32 @strcmp(ptr %a, ptr %b) nounwind +declare ptr @strcpy(ptr %a, ptr %b) nounwind +declare ptr @stpcpy(ptr %a, ptr %b) nounwind +declare i64 @strlen(ptr %a) nounwind +declare i64 @strnlen(ptr %a, i64 %b) nounwind ; CHECK: call{{.*}}@memchr{{.*}} #[[ATTR:[0-9]+]] ; CHECK: call{{.*}}@memcmp{{.*}} #[[ATTR]] @@ -21,13 +21,13 @@ ; CHECK: call{{.*}}@strnlen{{.*}} #[[ATTR]] ; attributes #[[ATTR]] = { nobuiltin } -define void @f1(i8* %a, i8* %b) nounwind uwtable sanitize_thread { - tail call i8* @memchr(i8* %a, i32 1, i64 12) - tail call i32 @memcmp(i8* %a, i8* %b, i64 12) - tail call i32 @strcmp(i8* %a, i8* %b) - tail call i8* @strcpy(i8* %a, i8* %b) - tail call i8* @stpcpy(i8* %a, i8* %b) - tail call i64 @strlen(i8* %a) - tail call i64 @strnlen(i8* %a, i64 12) +define void @f1(ptr %a, ptr %b) nounwind uwtable sanitize_thread { + tail call ptr @memchr(ptr %a, i32 1, i64 12) + tail call i32 @memcmp(ptr %a, ptr %b, i64 12) + tail call i32 @strcmp(ptr %a, ptr %b) + tail call ptr @strcpy(ptr %a, ptr %b) + tail call ptr @stpcpy(ptr %a, ptr %b) + tail call i64 @strlen(ptr %a) + tail call i64 @strnlen(ptr %a, i64 12) ret void } diff --git a/llvm/test/Instrumentation/ThreadSanitizer/tsan-vs-gvn.ll b/llvm/test/Instrumentation/ThreadSanitizer/tsan-vs-gvn.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/tsan-vs-gvn.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/tsan-vs-gvn.ll @@ -10,11 +10,11 @@ ; Accessing bytes 4 and 6, not ok to widen to i32 if sanitize_thread is set. -define i32 @test_widening_bad(i8* %P) nounwind ssp noredzone sanitize_thread { +define i32 @test_widening_bad(ptr %P) nounwind ssp noredzone sanitize_thread { entry: - %tmp = load i8, i8* getelementptr inbounds (%struct_of_8_bytes_4_aligned, %struct_of_8_bytes_4_aligned* @f, i64 0, i32 1), align 4 + %tmp = load i8, ptr getelementptr inbounds (%struct_of_8_bytes_4_aligned, ptr @f, i64 0, i32 1), align 4 %conv = zext i8 %tmp to i32 - %tmp1 = load i8, i8* getelementptr inbounds (%struct_of_8_bytes_4_aligned, %struct_of_8_bytes_4_aligned* @f, i64 0, i32 3), align 1 + %tmp1 = load i8, ptr getelementptr inbounds (%struct_of_8_bytes_4_aligned, ptr @f, i64 0, i32 3), align 1 %conv2 = zext i8 %tmp1 to i32 %add = add nsw i32 %conv, %conv2 ret i32 %add diff --git a/llvm/test/Instrumentation/ThreadSanitizer/tsan_address_space_attr.ll b/llvm/test/Instrumentation/ThreadSanitizer/tsan_address_space_attr.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/tsan_address_space_attr.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/tsan_address_space_attr.ll @@ -5,28 +5,28 @@ ; Checks that we do not instrument loads and stores comming from custom address space. ; These result in crashing the compiler. ; int foo(int argc, const char * argv[]) { -; void *__attribute__((address_space(256))) *gs_base = (((void * __attribute__((address_space(256))) *)0)); -; void *somevalue = gs_base[-1]; +; ptr__attribute__((address_space(256))) *gs_base = (((ptr __attribute__((address_space(256))) *)0)); +; ptr somevalue = gs_base[-1]; ; return somevalue; ; } -define i32 @foo(i32 %argc, i8** %argv) sanitize_thread { +define i32 @foo(i32 %argc, ptr %argv) sanitize_thread { entry: %retval = alloca i32, align 4 %argc.addr = alloca i32, align 4 - %argv.addr = alloca i8**, align 8 - %gs_base = alloca i8* addrspace(256)*, align 8 - %somevalue = alloca i8*, align 8 - store i32 0, i32* %retval, align 4 - store i32 %argc, i32* %argc.addr, align 4 - store i8** %argv, i8*** %argv.addr, align 8 - store i8* addrspace(256)* null, i8* addrspace(256)** %gs_base, align 8 - %0 = load i8* addrspace(256)*, i8* addrspace(256)** %gs_base, align 8 - %arrayidx = getelementptr inbounds i8*, i8* addrspace(256)* %0, i64 -1 - %1 = load i8*, i8* addrspace(256)* %arrayidx, align 8 - store i8* %1, i8** %somevalue, align 8 - %2 = load i8*, i8** %somevalue, align 8 - %3 = ptrtoint i8* %2 to i32 + %argv.addr = alloca ptr, align 8 + %gs_base = alloca ptr addrspace(256), align 8 + %somevalue = alloca ptr, align 8 + store i32 0, ptr %retval, align 4 + store i32 %argc, ptr %argc.addr, align 4 + store ptr %argv, ptr %argv.addr, align 8 + store ptr addrspace(256) null, ptr %gs_base, align 8 + %0 = load ptr addrspace(256), ptr %gs_base, align 8 + %arrayidx = getelementptr inbounds ptr, ptr addrspace(256) %0, i64 -1 + %1 = load ptr, ptr addrspace(256) %arrayidx, align 8 + store ptr %1, ptr %somevalue, align 8 + %2 = load ptr, ptr %somevalue, align 8 + %3 = ptrtoint ptr %2 to i32 ret i32 %3 } ; CHECK-NOT: call void @__tsan_read diff --git a/llvm/test/Instrumentation/ThreadSanitizer/tsan_basic.ll b/llvm/test/Instrumentation/ThreadSanitizer/tsan_basic.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/tsan_basic.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/tsan_basic.ll @@ -3,75 +3,74 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-unknown-linux-gnu" -define i32 @read_4_bytes(i32* %a) sanitize_thread { +define i32 @read_4_bytes(ptr %a) sanitize_thread { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } -; CHECK: @llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @tsan.module_ctor to i8*)] +; CHECK: @llvm.used = appending global [1 x ptr] [ptr @tsan.module_ctor] ; CHECK: @llvm.global_ctors = {{.*}}@tsan.module_ctor -; CHECK: define i32 @read_4_bytes(i32* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i32* %a to i8* -; CHECK-NEXT: call void @__tsan_read4(i8* %1) -; CHECK-NEXT: %tmp1 = load i32, i32* %a, align 4 +; CHECK: define i32 @read_4_bytes(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_read4(ptr %a) +; CHECK-NEXT: %tmp1 = load i32, ptr %a, align 4 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret i32 -declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) -declare void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) -declare void @llvm.memmove.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i1) -declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1) -declare void @llvm.memset.inline.p0i8.i64(i8* nocapture, i8, i64, i1) +declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) +declare void @llvm.memcpy.inline.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) +declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) +declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) +declare void @llvm.memset.inline.p0.i64(ptr nocapture, i8, i64, i1) ; Check that tsan converts mem intrinsics back to function calls. -define void @MemCpyTest(i8* nocapture %x, i8* nocapture %y) sanitize_thread { +define void @MemCpyTest(ptr nocapture %x, ptr nocapture %y) sanitize_thread { entry: - tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %x, i8* align 4 %y, i64 16, i1 false) + tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 %x, ptr align 4 %y, i64 16, i1 false) ret void ; CHECK: define void @MemCpyTest -; CHECK: call i8* @__tsan_memcpy +; CHECK: call ptr @__tsan_memcpy ; CHECK: ret void } -define void @MemCpyInlineTest(i8* nocapture %x, i8* nocapture %y) sanitize_thread { +define void @MemCpyInlineTest(ptr nocapture %x, ptr nocapture %y) sanitize_thread { entry: - tail call void @llvm.memcpy.inline.p0i8.p0i8.i64(i8* align 4 %x, i8* align 4 %y, i64 16, i1 false) + tail call void @llvm.memcpy.inline.p0.p0.i64(ptr align 4 %x, ptr align 4 %y, i64 16, i1 false) ret void ; CHECK: define void @MemCpyInlineTest -; CHECK: call i8* @__tsan_memcpy +; CHECK: call ptr @__tsan_memcpy ; CHECK: ret void } -define void @MemMoveTest(i8* nocapture %x, i8* nocapture %y) sanitize_thread { +define void @MemMoveTest(ptr nocapture %x, ptr nocapture %y) sanitize_thread { entry: - tail call void @llvm.memmove.p0i8.p0i8.i64(i8* align 4 %x, i8* align 4 %y, i64 16, i1 false) + tail call void @llvm.memmove.p0.p0.i64(ptr align 4 %x, ptr align 4 %y, i64 16, i1 false) ret void ; CHECK: define void @MemMoveTest -; CHECK: call i8* @__tsan_memmove +; CHECK: call ptr @__tsan_memmove ; CHECK: ret void } -define void @MemSetTest(i8* nocapture %x) sanitize_thread { +define void @MemSetTest(ptr nocapture %x) sanitize_thread { entry: - tail call void @llvm.memset.p0i8.i64(i8* align 4 %x, i8 77, i64 16, i1 false) + tail call void @llvm.memset.p0.i64(ptr align 4 %x, i8 77, i64 16, i1 false) ret void ; CHECK: define void @MemSetTest -; CHECK: call i8* @__tsan_memset +; CHECK: call ptr @__tsan_memset ; CHECK: ret void } -define void @MemSetInlineTest(i8* nocapture %x) sanitize_thread { +define void @MemSetInlineTest(ptr nocapture %x) sanitize_thread { entry: - tail call void @llvm.memset.inline.p0i8.i64(i8* align 4 %x, i8 77, i64 16, i1 false) + tail call void @llvm.memset.inline.p0.i64(ptr align 4 %x, i8 77, i64 16, i1 false) ret void ; CHECK: define void @MemSetInlineTest -; CHECK: call i8* @__tsan_memset +; CHECK: call ptr @__tsan_memset ; CHECK: ret void } @@ -79,12 +78,12 @@ ; CHECK-NOT: __tsan_read ; CHECK-NOT: __tsan_write ; CHECK: ret -define void @SwiftError(i8** swifterror) sanitize_thread { - %swifterror_ptr_value = load i8*, i8** %0 - store i8* null, i8** %0 - %swifterror_addr = alloca swifterror i8* - %swifterror_ptr_value_2 = load i8*, i8** %swifterror_addr - store i8* null, i8** %swifterror_addr +define void @SwiftError(ptr swifterror) sanitize_thread { + %swifterror_ptr_value = load ptr, ptr %0 + store ptr null, ptr %0 + %swifterror_addr = alloca swifterror ptr + %swifterror_ptr_value_2 = load ptr, ptr %swifterror_addr + store ptr null, ptr %swifterror_addr ret void } @@ -92,20 +91,20 @@ ; CHECK-NOT: __tsan_read ; CHECK-NOT: __tsan_write ; CHECK: ret -define void @SwiftErrorCall(i8** swifterror) sanitize_thread { - %swifterror_addr = alloca swifterror i8* - store i8* null, i8** %0 - call void @SwiftError(i8** %0) +define void @SwiftErrorCall(ptr swifterror) sanitize_thread { + %swifterror_addr = alloca swifterror ptr + store ptr null, ptr %0 + call void @SwiftError(ptr %0) ret void } -; CHECK-LABEL: @NakedTest(i32* %a) +; CHECK-LABEL: @NakedTest(ptr %a) ; CHECK-NEXT: call void @foo() -; CHECK-NEXT: %tmp1 = load i32, i32* %a, align 4 +; CHECK-NEXT: %tmp1 = load i32, ptr %a, align 4 ; CHECK-NEXT: ret i32 %tmp1 -define i32 @NakedTest(i32* %a) naked sanitize_thread { +define i32 @NakedTest(ptr %a) naked sanitize_thread { call void @foo() - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } diff --git a/llvm/test/Instrumentation/ThreadSanitizer/tsan_musttail.ll b/llvm/test/Instrumentation/ThreadSanitizer/tsan_musttail.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/tsan_musttail.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/tsan_musttail.ll @@ -1,30 +1,30 @@ ; To test that __tsan_func_exit always happen before musttaill call and no exception handling code. ; RUN: opt < %s -passes=tsan -S | FileCheck %s -define internal i32 @preallocated_musttail(i32* preallocated(i32) %p) sanitize_thread { - %rv = load i32, i32* %p +define internal i32 @preallocated_musttail(ptr preallocated(i32) %p) sanitize_thread { + %rv = load i32, ptr %p ret i32 %rv } -define i32 @call_preallocated_musttail(i32* preallocated(i32) %a) sanitize_thread { - %r = musttail call i32 @preallocated_musttail(i32* preallocated(i32) %a) +define i32 @call_preallocated_musttail(ptr preallocated(i32) %a) sanitize_thread { + %r = musttail call i32 @preallocated_musttail(ptr preallocated(i32) %a) ret i32 %r } -; CHECK-LABEL: define i32 @call_preallocated_musttail(i32* preallocated(i32) %a) +; CHECK-LABEL: define i32 @call_preallocated_musttail(ptr preallocated(i32) %a) ; CHECK: call void @__tsan_func_exit() -; CHECK-NEXT: %r = musttail call i32 @preallocated_musttail(i32* preallocated(i32) %a) +; CHECK-NEXT: %r = musttail call i32 @preallocated_musttail(ptr preallocated(i32) %a) ; CHECK-NEXT: ret i32 %r -define i32 @call_preallocated_musttail_cast(i32* preallocated(i32) %a) sanitize_thread { - %r = musttail call i32 @preallocated_musttail(i32* preallocated(i32) %a) +define i32 @call_preallocated_musttail_cast(ptr preallocated(i32) %a) sanitize_thread { + %r = musttail call i32 @preallocated_musttail(ptr preallocated(i32) %a) %t = bitcast i32 %r to i32 ret i32 %t } -; CHECK-LABEL: define i32 @call_preallocated_musttail_cast(i32* preallocated(i32) %a) +; CHECK-LABEL: define i32 @call_preallocated_musttail_cast(ptr preallocated(i32) %a) ; CHECK: call void @__tsan_func_exit() -; CHECK-NEXT: %r = musttail call i32 @preallocated_musttail(i32* preallocated(i32) %a) +; CHECK-NEXT: %r = musttail call i32 @preallocated_musttail(ptr preallocated(i32) %a) ; CHECK-NEXT: %t = bitcast i32 %r to i32 ; CHECK-NEXT: ret i32 %t diff --git a/llvm/test/Instrumentation/ThreadSanitizer/unaligned.ll b/llvm/test/Instrumentation/ThreadSanitizer/unaligned.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/unaligned.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/unaligned.ll @@ -2,142 +2,132 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -define i16 @test_unaligned_read2(i16* %a) sanitize_thread { +define i16 @test_unaligned_read2(ptr %a) sanitize_thread { entry: - %tmp1 = load i16, i16* %a, align 1 + %tmp1 = load i16, ptr %a, align 1 ret i16 %tmp1 } -; CHECK-LABEL: define i16 @test_unaligned_read2(i16* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i16* %a to i8* -; CHECK-NEXT: call void @__tsan_unaligned_read2(i8* %1) -; CHECK-NEXT: %tmp1 = load i16, i16* %a, align 1 +; CHECK-LABEL: define i16 @test_unaligned_read2(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_unaligned_read2(ptr %a) +; CHECK-NEXT: %tmp1 = load i16, ptr %a, align 1 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret i16 -define i32 @test_unaligned_read4(i32* %a) sanitize_thread { +define i32 @test_unaligned_read4(ptr %a) sanitize_thread { entry: - %tmp1 = load i32, i32* %a, align 2 + %tmp1 = load i32, ptr %a, align 2 ret i32 %tmp1 } -; CHECK-LABEL: define i32 @test_unaligned_read4(i32* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i32* %a to i8* -; CHECK-NEXT: call void @__tsan_unaligned_read4(i8* %1) -; CHECK-NEXT: %tmp1 = load i32, i32* %a, align 2 +; CHECK-LABEL: define i32 @test_unaligned_read4(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_unaligned_read4(ptr %a) +; CHECK-NEXT: %tmp1 = load i32, ptr %a, align 2 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret i32 -define i64 @test_unaligned_read8(i64* %a) sanitize_thread { +define i64 @test_unaligned_read8(ptr %a) sanitize_thread { entry: - %tmp1 = load i64, i64* %a, align 4 + %tmp1 = load i64, ptr %a, align 4 ret i64 %tmp1 } -; CHECK-LABEL: define i64 @test_unaligned_read8(i64* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i64* %a to i8* -; CHECK-NEXT: call void @__tsan_unaligned_read8(i8* %1) -; CHECK-NEXT: %tmp1 = load i64, i64* %a, align 4 +; CHECK-LABEL: define i64 @test_unaligned_read8(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_unaligned_read8(ptr %a) +; CHECK-NEXT: %tmp1 = load i64, ptr %a, align 4 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret i64 -define i128 @test_unaligned_read16(i128* %a) sanitize_thread { +define i128 @test_unaligned_read16(ptr %a) sanitize_thread { entry: - %tmp1 = load i128, i128* %a, align 1 + %tmp1 = load i128, ptr %a, align 1 ret i128 %tmp1 } -; CHECK-LABEL: define i128 @test_unaligned_read16(i128* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i128* %a to i8* -; CHECK-NEXT: call void @__tsan_unaligned_read16(i8* %1) -; CHECK-NEXT: %tmp1 = load i128, i128* %a, align 1 +; CHECK-LABEL: define i128 @test_unaligned_read16(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_unaligned_read16(ptr %a) +; CHECK-NEXT: %tmp1 = load i128, ptr %a, align 1 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret i128 -define i128 @test_aligned_read16(i128* %a) sanitize_thread { +define i128 @test_aligned_read16(ptr %a) sanitize_thread { entry: - %tmp1 = load i128, i128* %a, align 8 + %tmp1 = load i128, ptr %a, align 8 ret i128 %tmp1 } -; CHECK-LABEL: define i128 @test_aligned_read16(i128* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i128* %a to i8* -; CHECK-NEXT: call void @__tsan_read16(i8* %1) -; CHECK-NEXT: %tmp1 = load i128, i128* %a, align 8 +; CHECK-LABEL: define i128 @test_aligned_read16(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_read16(ptr %a) +; CHECK-NEXT: %tmp1 = load i128, ptr %a, align 8 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret i128 -define void @test_unaligned_write2(i16* %a) sanitize_thread { +define void @test_unaligned_write2(ptr %a) sanitize_thread { entry: - store i16 1, i16* %a, align 1 + store i16 1, ptr %a, align 1 ret void } -; CHECK-LABEL: define void @test_unaligned_write2(i16* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i16* %a to i8* -; CHECK-NEXT: call void @__tsan_unaligned_write2(i8* %1) -; CHECK-NEXT: store i16 1, i16* %a, align 1 +; CHECK-LABEL: define void @test_unaligned_write2(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_unaligned_write2(ptr %a) +; CHECK-NEXT: store i16 1, ptr %a, align 1 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret void -define void @test_unaligned_write4(i32* %a) sanitize_thread { +define void @test_unaligned_write4(ptr %a) sanitize_thread { entry: - store i32 1, i32* %a, align 1 + store i32 1, ptr %a, align 1 ret void } -; CHECK-LABEL: define void @test_unaligned_write4(i32* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i32* %a to i8* -; CHECK-NEXT: call void @__tsan_unaligned_write4(i8* %1) -; CHECK-NEXT: store i32 1, i32* %a, align 1 +; CHECK-LABEL: define void @test_unaligned_write4(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_unaligned_write4(ptr %a) +; CHECK-NEXT: store i32 1, ptr %a, align 1 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret void -define void @test_unaligned_write8(i64* %a) sanitize_thread { +define void @test_unaligned_write8(ptr %a) sanitize_thread { entry: - store i64 1, i64* %a, align 1 + store i64 1, ptr %a, align 1 ret void } -; CHECK-LABEL: define void @test_unaligned_write8(i64* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i64* %a to i8* -; CHECK-NEXT: call void @__tsan_unaligned_write8(i8* %1) -; CHECK-NEXT: store i64 1, i64* %a, align 1 +; CHECK-LABEL: define void @test_unaligned_write8(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_unaligned_write8(ptr %a) +; CHECK-NEXT: store i64 1, ptr %a, align 1 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret void -define void @test_unaligned_write16(i128* %a) sanitize_thread { +define void @test_unaligned_write16(ptr %a) sanitize_thread { entry: - store i128 1, i128* %a, align 1 + store i128 1, ptr %a, align 1 ret void } -; CHECK-LABEL: define void @test_unaligned_write16(i128* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i128* %a to i8* -; CHECK-NEXT: call void @__tsan_unaligned_write16(i8* %1) -; CHECK-NEXT: store i128 1, i128* %a, align 1 +; CHECK-LABEL: define void @test_unaligned_write16(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_unaligned_write16(ptr %a) +; CHECK-NEXT: store i128 1, ptr %a, align 1 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret void -define void @test_aligned_write16(i128* %a) sanitize_thread { +define void @test_aligned_write16(ptr %a) sanitize_thread { entry: - store i128 1, i128* %a, align 8 + store i128 1, ptr %a, align 8 ret void } -; CHECK-LABEL: define void @test_aligned_write16(i128* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i128* %a to i8* -; CHECK-NEXT: call void @__tsan_write16(i8* %1) -; CHECK-NEXT: store i128 1, i128* %a, align 8 +; CHECK-LABEL: define void @test_aligned_write16(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_write16(ptr %a) +; CHECK-NEXT: store i128 1, ptr %a, align 8 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret void diff --git a/llvm/test/Instrumentation/ThreadSanitizer/volatile.ll b/llvm/test/Instrumentation/ThreadSanitizer/volatile.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/volatile.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/volatile.ll @@ -2,174 +2,162 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -define i16 @test_volatile_read2(i16* %a) sanitize_thread { +define i16 @test_volatile_read2(ptr %a) sanitize_thread { entry: - %tmp1 = load volatile i16, i16* %a, align 2 + %tmp1 = load volatile i16, ptr %a, align 2 ret i16 %tmp1 } -; CHECK-LABEL: define i16 @test_volatile_read2(i16* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i16* %a to i8* -; CHECK-NEXT: call void @__tsan_volatile_read2(i8* %1) -; CHECK-NEXT: %tmp1 = load volatile i16, i16* %a, align 2 +; CHECK-LABEL: define i16 @test_volatile_read2(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_volatile_read2(ptr %a) +; CHECK-NEXT: %tmp1 = load volatile i16, ptr %a, align 2 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret i16 -define i32 @test_volatile_read4(i32* %a) sanitize_thread { +define i32 @test_volatile_read4(ptr %a) sanitize_thread { entry: - %tmp1 = load volatile i32, i32* %a, align 4 + %tmp1 = load volatile i32, ptr %a, align 4 ret i32 %tmp1 } -; CHECK-LABEL: define i32 @test_volatile_read4(i32* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i32* %a to i8* -; CHECK-NEXT: call void @__tsan_volatile_read4(i8* %1) -; CHECK-NEXT: %tmp1 = load volatile i32, i32* %a, align 4 +; CHECK-LABEL: define i32 @test_volatile_read4(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_volatile_read4(ptr %a) +; CHECK-NEXT: %tmp1 = load volatile i32, ptr %a, align 4 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret i32 -define i64 @test_volatile_read8(i64* %a) sanitize_thread { +define i64 @test_volatile_read8(ptr %a) sanitize_thread { entry: - %tmp1 = load volatile i64, i64* %a, align 8 + %tmp1 = load volatile i64, ptr %a, align 8 ret i64 %tmp1 } -; CHECK-LABEL: define i64 @test_volatile_read8(i64* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i64* %a to i8* -; CHECK-NEXT: call void @__tsan_volatile_read8(i8* %1) -; CHECK-NEXT: %tmp1 = load volatile i64, i64* %a, align 8 +; CHECK-LABEL: define i64 @test_volatile_read8(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_volatile_read8(ptr %a) +; CHECK-NEXT: %tmp1 = load volatile i64, ptr %a, align 8 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret i64 -define i128 @test_volatile_read16(i128* %a) sanitize_thread { +define i128 @test_volatile_read16(ptr %a) sanitize_thread { entry: - %tmp1 = load volatile i128, i128* %a, align 16 + %tmp1 = load volatile i128, ptr %a, align 16 ret i128 %tmp1 } -; CHECK-LABEL: define i128 @test_volatile_read16(i128* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i128* %a to i8* -; CHECK-NEXT: call void @__tsan_volatile_read16(i8* %1) -; CHECK-NEXT: %tmp1 = load volatile i128, i128* %a, align 16 +; CHECK-LABEL: define i128 @test_volatile_read16(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_volatile_read16(ptr %a) +; CHECK-NEXT: %tmp1 = load volatile i128, ptr %a, align 16 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret i128 -define void @test_volatile_write2(i16* %a) sanitize_thread { +define void @test_volatile_write2(ptr %a) sanitize_thread { entry: - store volatile i16 1, i16* %a, align 2 + store volatile i16 1, ptr %a, align 2 ret void } -; CHECK-LABEL: define void @test_volatile_write2(i16* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i16* %a to i8* -; CHECK-NEXT: call void @__tsan_volatile_write2(i8* %1) -; CHECK-NEXT: store volatile i16 1, i16* %a, align 2 +; CHECK-LABEL: define void @test_volatile_write2(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_volatile_write2(ptr %a) +; CHECK-NEXT: store volatile i16 1, ptr %a, align 2 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret void -define void @test_volatile_write4(i32* %a) sanitize_thread { +define void @test_volatile_write4(ptr %a) sanitize_thread { entry: - store volatile i32 1, i32* %a, align 4 + store volatile i32 1, ptr %a, align 4 ret void } -; CHECK-LABEL: define void @test_volatile_write4(i32* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i32* %a to i8* -; CHECK-NEXT: call void @__tsan_volatile_write4(i8* %1) -; CHECK-NEXT: store volatile i32 1, i32* %a, align 4 +; CHECK-LABEL: define void @test_volatile_write4(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_volatile_write4(ptr %a) +; CHECK-NEXT: store volatile i32 1, ptr %a, align 4 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret void -define void @test_volatile_write8(i64* %a) sanitize_thread { +define void @test_volatile_write8(ptr %a) sanitize_thread { entry: - store volatile i64 1, i64* %a, align 8 + store volatile i64 1, ptr %a, align 8 ret void } -; CHECK-LABEL: define void @test_volatile_write8(i64* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i64* %a to i8* -; CHECK-NEXT: call void @__tsan_volatile_write8(i8* %1) -; CHECK-NEXT: store volatile i64 1, i64* %a, align 8 +; CHECK-LABEL: define void @test_volatile_write8(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_volatile_write8(ptr %a) +; CHECK-NEXT: store volatile i64 1, ptr %a, align 8 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret void -define void @test_volatile_write16(i128* %a) sanitize_thread { +define void @test_volatile_write16(ptr %a) sanitize_thread { entry: - store volatile i128 1, i128* %a, align 16 + store volatile i128 1, ptr %a, align 16 ret void } -; CHECK-LABEL: define void @test_volatile_write16(i128* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i128* %a to i8* -; CHECK-NEXT: call void @__tsan_volatile_write16(i8* %1) -; CHECK-NEXT: store volatile i128 1, i128* %a, align 16 +; CHECK-LABEL: define void @test_volatile_write16(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_volatile_write16(ptr %a) +; CHECK-NEXT: store volatile i128 1, ptr %a, align 16 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret void ; Check unaligned volatile accesses -define i32 @test_unaligned_read4(i32* %a) sanitize_thread { +define i32 @test_unaligned_read4(ptr %a) sanitize_thread { entry: - %tmp1 = load volatile i32, i32* %a, align 2 + %tmp1 = load volatile i32, ptr %a, align 2 ret i32 %tmp1 } -; CHECK-LABEL: define i32 @test_unaligned_read4(i32* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i32* %a to i8* -; CHECK-NEXT: call void @__tsan_unaligned_volatile_read4(i8* %1) -; CHECK-NEXT: %tmp1 = load volatile i32, i32* %a, align 2 +; CHECK-LABEL: define i32 @test_unaligned_read4(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_unaligned_volatile_read4(ptr %a) +; CHECK-NEXT: %tmp1 = load volatile i32, ptr %a, align 2 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret i32 -define void @test_unaligned_write4(i32* %a) sanitize_thread { +define void @test_unaligned_write4(ptr %a) sanitize_thread { entry: - store volatile i32 1, i32* %a, align 1 + store volatile i32 1, ptr %a, align 1 ret void } -; CHECK-LABEL: define void @test_unaligned_write4(i32* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i32* %a to i8* -; CHECK-NEXT: call void @__tsan_unaligned_volatile_write4(i8* %1) -; CHECK-NEXT: store volatile i32 1, i32* %a, align 1 +; CHECK-LABEL: define void @test_unaligned_write4(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_unaligned_volatile_write4(ptr %a) +; CHECK-NEXT: store volatile i32 1, ptr %a, align 1 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret void ; Check that regular aligned accesses are unaffected -define i32 @test_read4(i32* %a) sanitize_thread { +define i32 @test_read4(ptr %a) sanitize_thread { entry: - %tmp1 = load i32, i32* %a, align 4 + %tmp1 = load i32, ptr %a, align 4 ret i32 %tmp1 } -; CHECK-LABEL: define i32 @test_read4(i32* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i32* %a to i8* -; CHECK-NEXT: call void @__tsan_read4(i8* %1) -; CHECK-NEXT: %tmp1 = load i32, i32* %a, align 4 +; CHECK-LABEL: define i32 @test_read4(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_read4(ptr %a) +; CHECK-NEXT: %tmp1 = load i32, ptr %a, align 4 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret i32 -define void @test_write4(i32* %a) sanitize_thread { +define void @test_write4(ptr %a) sanitize_thread { entry: - store i32 1, i32* %a, align 4 + store i32 1, ptr %a, align 4 ret void } -; CHECK-LABEL: define void @test_write4(i32* %a) -; CHECK: call void @__tsan_func_entry(i8* %0) -; CHECK-NEXT: %1 = bitcast i32* %a to i8* -; CHECK-NEXT: call void @__tsan_write4(i8* %1) -; CHECK-NEXT: store i32 1, i32* %a, align 4 +; CHECK-LABEL: define void @test_write4(ptr %a) +; CHECK: call void @__tsan_func_entry(ptr %0) +; CHECK-NEXT: call void @__tsan_write4(ptr %a) +; CHECK-NEXT: store i32 1, ptr %a, align 4 ; CHECK-NEXT: call void @__tsan_func_exit() ; CHECK: ret void diff --git a/llvm/test/Instrumentation/ThreadSanitizer/vptr_read.ll b/llvm/test/Instrumentation/ThreadSanitizer/vptr_read.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/vptr_read.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/vptr_read.ll @@ -2,10 +2,10 @@ ; Check that vptr reads are treated in a special way. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -define i8 @Foo(i8* %a) nounwind uwtable sanitize_thread { +define i8 @Foo(ptr %a) nounwind uwtable sanitize_thread { entry: ; CHECK: call void @__tsan_vptr_read - %0 = load i8, i8* %a, align 8, !tbaa !0 + %0 = load i8, ptr %a, align 8, !tbaa !0 ret i8 %0 } !0 = !{!2, !2, i64 0} diff --git a/llvm/test/Instrumentation/ThreadSanitizer/vptr_update.ll b/llvm/test/Instrumentation/ThreadSanitizer/vptr_update.ll --- a/llvm/test/Instrumentation/ThreadSanitizer/vptr_update.ll +++ b/llvm/test/Instrumentation/ThreadSanitizer/vptr_update.ll @@ -2,21 +2,21 @@ ; Check that vtable pointer updates are treated in a special way. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -define void @Foo(i8** nocapture %a, i8* %b) nounwind uwtable sanitize_thread { +define void @Foo(ptr nocapture %a, ptr %b) nounwind uwtable sanitize_thread { entry: ; CHECK-LABEL: @Foo ; CHECK: call void @__tsan_vptr_update ; CHECK: ret void - store i8* %b, i8** %a, align 8, !tbaa !0 + store ptr %b, ptr %a, align 8, !tbaa !0 ret void } -define void @FooInt(i64* nocapture %a, i64 %b) nounwind uwtable sanitize_thread { +define void @FooInt(ptr nocapture %a, i64 %b) nounwind uwtable sanitize_thread { entry: ; CHECK-LABEL: @FooInt ; CHECK: call void @__tsan_vptr_update ; CHECK: ret void - store i64 %b, i64* %a, align 8, !tbaa !0 + store i64 %b, ptr %a, align 8, !tbaa !0 ret void } @@ -25,13 +25,13 @@ declare i32 @Func2() ; Test that we properly handle vector stores marked as vtable updates. -define void @VectorVptrUpdate(<2 x i8*>* nocapture %a, i8* %b) nounwind uwtable sanitize_thread { +define void @VectorVptrUpdate(ptr nocapture %a, ptr %b) nounwind uwtable sanitize_thread { entry: ; CHECK-LABEL: @VectorVptrUpdate ; CHECK: call void @__tsan_vptr_update{{.*}}Func1 ; CHECK-NOT: call void @__tsan_vptr_update ; CHECK: ret void - store <2 x i8 *> , <2 x i8 *>* %a, align 8, !tbaa !0 + store <2 x ptr> , ptr %a, align 8, !tbaa !0 ret void } diff --git a/llvm/test/LTO/X86/Inputs/codemodel-3.ll b/llvm/test/LTO/X86/Inputs/codemodel-3.ll --- a/llvm/test/LTO/X86/Inputs/codemodel-3.ll +++ b/llvm/test/LTO/X86/Inputs/codemodel-3.ll @@ -8,9 +8,9 @@ %struct.rtx_def = type { i16, i16 } -define void @bar(%struct.rtx_def* %a, i8 %b, i32 %c) { - call void @llvm.memset.p0struct.rtx_def.i32(%struct.rtx_def* align 4 %a, i8 %b, i32 %c, i1 true) +define void @bar(ptr %a, i8 %b, i32 %c) { + call void @llvm.memset.p0.rtx_def.i32(ptr align 4 %a, i8 %b, i32 %c, i1 true) ret void } -declare void @llvm.memset.p0struct.rtx_def.i32(%struct.rtx_def*, i8, i32, i1) +declare void @llvm.memset.p0.rtx_def.i32(ptr, i8, i32, i1) diff --git a/llvm/test/LTO/X86/Inputs/remangle_intrinsics.ll b/llvm/test/LTO/X86/Inputs/remangle_intrinsics.ll --- a/llvm/test/LTO/X86/Inputs/remangle_intrinsics.ll +++ b/llvm/test/LTO/X86/Inputs/remangle_intrinsics.ll @@ -2,9 +2,9 @@ %struct.rtx_def = type { i16, i16 } -define void @bar(%struct.rtx_def* %a, i8 %b, i32 %c) { - call void @llvm.memset.p0struct.rtx_def.i32(%struct.rtx_def* align 4 %a, i8 %b, i32 %c, i1 true) +define void @bar(ptr %a, i8 %b, i32 %c) { + call void @llvm.memset.p0.rtx_def.i32(ptr align 4 %a, i8 %b, i32 %c, i1 true) ret void } -declare void @llvm.memset.p0struct.rtx_def.i32(%struct.rtx_def*, i8, i32, i1) +declare void @llvm.memset.p0.rtx_def.i32(ptr, i8, i32, i1) diff --git a/llvm/test/LTO/X86/Inputs/type-mapping-bug3.ll b/llvm/test/LTO/X86/Inputs/type-mapping-bug3.ll --- a/llvm/test/LTO/X86/Inputs/type-mapping-bug3.ll +++ b/llvm/test/LTO/X86/Inputs/type-mapping-bug3.ll @@ -3,7 +3,7 @@ ; T2 is the non-opaque struct required to trigger the uniqued T2.0 and T3.0 to ; respectively T2 and T3 in the destination module. -%"T2" = type { %"T3"* } +%"T2" = type { ptr } %"T3" = type opaque ; Use/refer to T2 so it gets added as an IdentifiedStructType. The debug diff --git a/llvm/test/LTO/X86/Inputs/type-mapping-src.ll b/llvm/test/LTO/X86/Inputs/type-mapping-src.ll --- a/llvm/test/LTO/X86/Inputs/type-mapping-src.ll +++ b/llvm/test/LTO/X86/Inputs/type-mapping-src.ll @@ -5,7 +5,7 @@ %CommonStruct = type opaque @x = external global %SrcType -@bar = internal global %CommonStruct* null, !dbg !0 +@bar = internal global ptr null, !dbg !0 !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!8} diff --git a/llvm/test/LTO/X86/cfi_endproc.ll b/llvm/test/LTO/X86/cfi_endproc.ll --- a/llvm/test/LTO/X86/cfi_endproc.ll +++ b/llvm/test/LTO/X86/cfi_endproc.ll @@ -18,7 +18,7 @@ ; Without -exported-symbol, main should be eliminated by LTO. ; With -exported-symbol=main, main should be preserved by LTO. -define i32 @main(i32 %argc, i8** %argv) { +define i32 @main(i32 %argc, ptr %argv) { ; NOEXPORT-NOT: main ; EXPORT: main call void @PR14512() @@ -29,14 +29,14 @@ ; RUN: llvm-nm %t | FileCheck %s -check-prefix=ZED1_AND_ZED2 ; ZED1_AND_ZED2: V zed1 @zed1 = linkonce_odr global i32 42 -define i32* @get_zed1() { - ret i32* @zed1 +define ptr @get_zed1() { + ret ptr @zed1 } ; ZED1_AND_ZED2: r zed2 @zed2 = linkonce_odr unnamed_addr constant i32 42 define i32 @useZed2() { - %x = load i32, i32* @zed2 + %x = load i32, ptr @zed2 ret i32 %x } diff --git a/llvm/test/LTO/X86/cfi_jt_aliases.ll b/llvm/test/LTO/X86/cfi_jt_aliases.ll --- a/llvm/test/LTO/X86/cfi_jt_aliases.ll +++ b/llvm/test/LTO/X86/cfi_jt_aliases.ll @@ -51,7 +51,7 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -@f = internal global [4 x void ()*] [void ()* @a, void ()* @b, void ()* @c, void ()* null], align 16 +@f = internal global [4 x ptr] [ptr @a, ptr @b, ptr @c, ptr null], align 16 define dso_local void @a() !type !5 !type !6 { ret void } define dso_local void @b() !type !5 !type !6 { ret void } @@ -60,25 +60,24 @@ define dso_local void @d() !type !5 !type !6 { entry: %i = alloca i32, align 4 - store i32 0, i32* %i, align 4 + store i32 0, ptr %i, align 4 br label %for.cond for.cond: ; preds = %for.inc, %entry - %0 = load i32, i32* %i, align 4 + %0 = load i32, ptr %i, align 4 %idxprom = sext i32 %0 to i64 - %arrayidx = getelementptr inbounds [4 x void ()*], [4 x void ()*]* @f, i64 0, i64 %idxprom - %1 = load void ()*, void ()** %arrayidx, align 8 - %tobool = icmp ne void ()* %1, null + %arrayidx = getelementptr inbounds [4 x ptr], ptr @f, i64 0, i64 %idxprom + %1 = load ptr, ptr %arrayidx, align 8 + %tobool = icmp ne ptr %1, null br i1 %tobool, label %for.body, label %for.end for.body: ; preds = %for.cond - %2 = load i32, i32* %i, align 4 + %2 = load i32, ptr %i, align 4 %idxprom1 = sext i32 %2 to i64 - %arrayidx2 = getelementptr inbounds [4 x void ()*], [4 x void ()*]* @f, i64 0, i64 %idxprom1 - %3 = load void ()*, void ()** %arrayidx2, align 8 - %4 = bitcast void ()* %3 to i8*, !nosanitize !7 - %5 = call i1 @llvm.type.test(i8* %4, metadata !"_ZTSFvvE"), !nosanitize !7 - br i1 %5, label %cont, label %trap, !nosanitize !7 + %arrayidx2 = getelementptr inbounds [4 x ptr], ptr @f, i64 0, i64 %idxprom1 + %3 = load ptr, ptr %arrayidx2, align 8 + %4 = call i1 @llvm.type.test(ptr %3, metadata !"_ZTSFvvE"), !nosanitize !7 + br i1 %4, label %cont, label %trap, !nosanitize !7 trap: ; preds = %for.body call void @llvm.ubsantrap(i8 2), !nosanitize !7 @@ -89,16 +88,16 @@ br label %for.inc for.inc: ; preds = %cont - %6 = load i32, i32* %i, align 4 - %inc = add nsw i32 %6, 1 - store i32 %inc, i32* %i, align 4 + %5 = load i32, ptr %i, align 4 + %inc = add nsw i32 %5, 1 + store i32 %inc, ptr %i, align 4 br label %for.cond for.end: ; preds = %for.cond ret void } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.ubsantrap(i8 immarg) !llvm.module.flags = !{!0, !1, !2, !3} diff --git a/llvm/test/LTO/X86/codemodel-1.ll b/llvm/test/LTO/X86/codemodel-1.ll --- a/llvm/test/LTO/X86/codemodel-1.ll +++ b/llvm/test/LTO/X86/codemodel-1.ll @@ -12,9 +12,9 @@ @data = internal constant [0 x i32] [] -define i32* @_start() nounwind readonly { +define ptr @_start() nounwind readonly { entry: ; CHECK-SMALL-LABEL: <_start>: ; CHECK-SMALL: leaq (%rip), %rax - ret i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0) + ret ptr @data } diff --git a/llvm/test/LTO/X86/codemodel-2.ll b/llvm/test/LTO/X86/codemodel-2.ll --- a/llvm/test/LTO/X86/codemodel-2.ll +++ b/llvm/test/LTO/X86/codemodel-2.ll @@ -12,9 +12,9 @@ @data = internal constant [0 x i32] [] -define i32* @_start() nounwind readonly { +define ptr @_start() nounwind readonly { entry: ; CHECK-LARGE-LABEL: <_start>: ; CHECK-LARGE: movabsq $0, %rax - ret i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0) + ret ptr @data } diff --git a/llvm/test/LTO/X86/codemodel-3.ll b/llvm/test/LTO/X86/codemodel-3.ll --- a/llvm/test/LTO/X86/codemodel-3.ll +++ b/llvm/test/LTO/X86/codemodel-3.ll @@ -12,9 +12,9 @@ @data = internal constant [0 x i32] [] -define i32* @_start() nounwind readonly { +define ptr @_start() nounwind readonly { entry: - ret i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0) + ret ptr @data } ; CHECK: 'Code Model': IDs have conflicting values diff --git a/llvm/test/LTO/X86/diagnostic-handler-remarks.ll b/llvm/test/LTO/X86/diagnostic-handler-remarks.ll --- a/llvm/test/LTO/X86/diagnostic-handler-remarks.ll +++ b/llvm/test/LTO/X86/diagnostic-handler-remarks.ll @@ -93,39 +93,39 @@ ret i32 %i } -define i32 @func2(i32* %out, i32* %out2, i32* %A, i32* %B, i32* %C, i32* %D, i32* %E, i32* %F) { +define i32 @func2(ptr %out, ptr %out2, ptr %A, ptr %B, ptr %C, ptr %D, ptr %E, ptr %F) { entry: br label %for.body for.body: ; preds = %for.body, %entry %i.037 = phi i64 [ 0, %entry ], [ %inc, %for.body ] - %arrayidx = getelementptr inbounds i32, i32* %A, i64 %i.037 - %0 = load i32, i32* %arrayidx, align 4 - %arrayidx1 = getelementptr inbounds i32, i32* %B, i64 %i.037 - %1 = load i32, i32* %arrayidx1, align 4 + %arrayidx = getelementptr inbounds i32, ptr %A, i64 %i.037 + %0 = load i32, ptr %arrayidx, align 4 + %arrayidx1 = getelementptr inbounds i32, ptr %B, i64 %i.037 + %1 = load i32, ptr %arrayidx1, align 4 %add = add nsw i32 %1, %0 - %arrayidx2 = getelementptr inbounds i32, i32* %C, i64 %i.037 - %2 = load i32, i32* %arrayidx2, align 4 + %arrayidx2 = getelementptr inbounds i32, ptr %C, i64 %i.037 + %2 = load i32, ptr %arrayidx2, align 4 %add3 = add nsw i32 %add, %2 - %arrayidx4 = getelementptr inbounds i32, i32* %E, i64 %i.037 - %3 = load i32, i32* %arrayidx4, align 4 + %arrayidx4 = getelementptr inbounds i32, ptr %E, i64 %i.037 + %3 = load i32, ptr %arrayidx4, align 4 %add5 = add nsw i32 %add3, %3 - %arrayidx6 = getelementptr inbounds i32, i32* %F, i64 %i.037 - %4 = load i32, i32* %arrayidx6, align 4 + %arrayidx6 = getelementptr inbounds i32, ptr %F, i64 %i.037 + %4 = load i32, ptr %arrayidx6, align 4 %add7 = add nsw i32 %add5, %4 - %arrayidx8 = getelementptr inbounds i32, i32* %out, i64 %i.037 - store i32 %add7, i32* %arrayidx8, align 4 - %5 = load i32, i32* %arrayidx, align 4 - %6 = load i32, i32* %arrayidx1, align 4 + %arrayidx8 = getelementptr inbounds i32, ptr %out, i64 %i.037 + store i32 %add7, ptr %arrayidx8, align 4 + %5 = load i32, ptr %arrayidx, align 4 + %6 = load i32, ptr %arrayidx1, align 4 %add11 = add nsw i32 %6, %5 - %7 = load i32, i32* %arrayidx2, align 4 + %7 = load i32, ptr %arrayidx2, align 4 %add13 = add nsw i32 %add11, %7 - %8 = load i32, i32* %arrayidx4, align 4 + %8 = load i32, ptr %arrayidx4, align 4 %add15 = add nsw i32 %add13, %8 - %9 = load i32, i32* %arrayidx6, align 4 + %9 = load i32, ptr %arrayidx6, align 4 %add17 = add nsw i32 %add15, %9 - %arrayidx18 = getelementptr inbounds i32, i32* %out2, i64 %i.037 - store i32 %add17, i32* %arrayidx18, align 4 + %arrayidx18 = getelementptr inbounds i32, ptr %out2, i64 %i.037 + store i32 %add17, ptr %arrayidx18, align 4 %inc = add i64 %i.037, 1 %exitcond = icmp eq i64 %inc, 256 br i1 %exitcond, label %for.end, label %for.body diff --git a/llvm/test/LTO/X86/inline-asm-lto-discard.ll b/llvm/test/LTO/X86/inline-asm-lto-discard.ll --- a/llvm/test/LTO/X86/inline-asm-lto-discard.ll +++ b/llvm/test/LTO/X86/inline-asm-lto-discard.ll @@ -64,7 +64,7 @@ module asm ".weak foo" module asm ".equ foo,bar" -@llvm.compiler.used = appending global [1 x i8*] [i8* bitcast (i32 (i32)* @bar to i8*)], section "llvm.metadata" +@llvm.compiler.used = appending global [1 x ptr] [ptr @bar], section "llvm.metadata" define internal i32 @bar(i32 %0) { %2 = add nsw i32 %0, 1 diff --git a/llvm/test/LTO/X86/keep-used-puts-during-instcombine.ll b/llvm/test/LTO/X86/keep-used-puts-during-instcombine.ll --- a/llvm/test/LTO/X86/keep-used-puts-during-instcombine.ll +++ b/llvm/test/LTO/X86/keep-used-puts-during-instcombine.ll @@ -4,33 +4,32 @@ target triple = "x86_64-apple-darwin11" -@llvm.compiler.used = appending global [1 x i8*] [ - i8* bitcast (i32(i8*)* @puts to i8*) +@llvm.compiler.used = appending global [1 x ptr] [ + ptr @puts ], section "llvm.metadata" -@llvm.used = appending global [1 x i8*] [ - i8* bitcast (i32(i32)* @uses_printf to i8*) +@llvm.used = appending global [1 x ptr] [ + ptr @uses_printf ], section "llvm.metadata" @str = private unnamed_addr constant [13 x i8] c"hello world\0A\00" define i32 @uses_printf(i32 %i) { entry: - %s = getelementptr [13 x i8], [13 x i8]* @str, i64 0, i64 0 - call i32 (i8*, ...) @printf(i8* %s) + call i32 (ptr, ...) @printf(ptr @str) ret i32 0 } -define internal i32 @printf(i8* readonly nocapture %fmt, ...) { +define internal i32 @printf(ptr readonly nocapture %fmt, ...) { entry: - %ret = call i32 @bar(i8* %fmt) + %ret = call i32 @bar(ptr %fmt) ret i32 %ret } ; CHECK: define {{.*}} @puts( -define internal i32 @puts(i8* %s) { +define internal i32 @puts(ptr %s) { entry: - %ret = call i32 @bar(i8* %s) + %ret = call i32 @bar(ptr %s) ret i32 %ret } -declare i32 @bar(i8*) +declare i32 @bar(ptr) diff --git a/llvm/test/LTO/X86/libcall-overridden-via-alias.ll b/llvm/test/LTO/X86/libcall-overridden-via-alias.ll --- a/llvm/test/LTO/X86/libcall-overridden-via-alias.ll +++ b/llvm/test/LTO/X86/libcall-overridden-via-alias.ll @@ -51,13 +51,13 @@ @src = global float 0x40091EB860000000, align 4 @dst = common global float 0.000000e+00, align 4 -@logf = alias float (float), float (float)* @fname +@logf = alias float (float), ptr @fname define i32 @main() local_unnamed_addr { entry: - %0 = load volatile float, float* @src, align 4 + %0 = load volatile float, ptr @src, align 4 %1 = tail call float @llvm.log.f32(float %0) - store volatile float %1, float* @dst, align 4 + store volatile float %1, ptr @dst, align 4 ret i32 0 } diff --git a/llvm/test/LTO/X86/linkonce_odr_func.ll b/llvm/test/LTO/X86/linkonce_odr_func.ll --- a/llvm/test/LTO/X86/linkonce_odr_func.ll +++ b/llvm/test/LTO/X86/linkonce_odr_func.ll @@ -44,11 +44,11 @@ call void @foo1() call void @foo2() call void @foo3() - %x1 = load i32, i32* @v1 - %x2 = load i32, i32* @v2 - %x3 = load i32, i32* @v3 - %x4 = load i32, i32* @v4 - %x5 = load i32, i32* @v5 - %x6 = load i32, i32* @v6 + %x1 = load i32, ptr @v1 + %x2 = load i32, ptr @v2 + %x3 = load i32, ptr @v3 + %x4 = load i32, ptr @v4 + %x5 = load i32, ptr @v5 + %x6 = load i32, ptr @v6 ret void } diff --git a/llvm/test/LTO/X86/no-undefined-puts-when-implemented.ll b/llvm/test/LTO/X86/no-undefined-puts-when-implemented.ll --- a/llvm/test/LTO/X86/no-undefined-puts-when-implemented.ll +++ b/llvm/test/LTO/X86/no-undefined-puts-when-implemented.ll @@ -15,27 +15,26 @@ ; CHECK: T _uses_puts define i32 @uses_puts(i32 %i) { entry: - %s = call i8* @foo(i32 %i) - %ret = call i32 @puts(i8* %s) + %s = call ptr @foo(i32 %i) + %ret = call i32 @puts(ptr %s) ret i32 %ret } define i32 @uses_printf(i32 %i) { entry: - %s = getelementptr [13 x i8], [13 x i8]* @str, i64 0, i64 0 - call i32 (i8*, ...) @printf(i8* %s) + call i32 (ptr, ...) @printf(ptr @str) ret i32 0 } -define hidden i32 @printf(i8* readonly nocapture %fmt, ...) { +define hidden i32 @printf(ptr readonly nocapture %fmt, ...) { entry: - %ret = call i32 @bar(i8* %fmt) + %ret = call i32 @bar(ptr %fmt) ret i32 %ret } -define hidden i32 @puts(i8* %s) { +define hidden i32 @puts(ptr %s) { entry: - %ret = call i32 @bar(i8* %s) + %ret = call i32 @bar(ptr %s) ret i32 %ret } -declare i8* @foo(i32) -declare i32 @bar(i8*) +declare ptr @foo(i32) +declare i32 @bar(ptr) diff --git a/llvm/test/LTO/X86/objc-detection-i386.ll b/llvm/test/LTO/X86/objc-detection-i386.ll --- a/llvm/test/LTO/X86/objc-detection-i386.ll +++ b/llvm/test/LTO/X86/objc-detection-i386.ll @@ -12,36 +12,36 @@ module asm "\09.globl .objc_category_name_A_foo" %0 = type opaque -%struct._objc_method = type { i8*, i8*, i8* } -%struct._objc_category = type { i8*, i8*, %struct._objc_method_list*, %struct._objc_method_list*, %struct._objc_protocol_list*, i32, %struct._prop_list_t*, %struct._prop_list_t* } +%struct._objc_method = type { ptr, ptr, ptr } +%struct._objc_category = type { ptr, ptr, ptr, ptr, ptr, i32, ptr, ptr } %struct._objc_method_list = type opaque -%struct._objc_protocol_list = type { %struct._objc_protocol_list*, i32, [0 x %struct._objc_protocol] } -%struct._objc_protocol = type { %struct._objc_protocol_extension*, i8*, %struct._objc_protocol_list*, %struct._objc_method_description_list*, %struct._objc_method_description_list* } -%struct._objc_protocol_extension = type { i32, %struct._objc_method_description_list*, %struct._objc_method_description_list*, %struct._prop_list_t*, i8**, %struct._prop_list_t* } +%struct._objc_protocol_list = type { ptr, i32, [0 x %struct._objc_protocol] } +%struct._objc_protocol = type { ptr, ptr, ptr, ptr, ptr } +%struct._objc_protocol_extension = type { i32, ptr, ptr, ptr, ptr, ptr } %struct._objc_method_description_list = type { i32, [0 x %struct._objc_method_description] } -%struct._objc_method_description = type { i8*, i8* } +%struct._objc_method_description = type { ptr, ptr } %struct._prop_list_t = type { i32, i32, [0 x %struct._prop_t] } -%struct._prop_t = type { i8*, i8* } -%struct._objc_module = type { i32, i32, i8*, %struct._objc_symtab* } -%struct._objc_symtab = type { i32, i8*, i16, i16, [0 x i8*] } +%struct._prop_t = type { ptr, ptr } +%struct._objc_module = type { i32, i32, ptr, ptr } +%struct._objc_symtab = type { i32, ptr, i16, i16, [0 x ptr] } @OBJC_METH_VAR_NAME_ = private global [12 x i8] c"foo_myStuff\00", section "__TEXT,__cstring,cstring_literals", align 1 @OBJC_METH_VAR_TYPE_ = private global [7 x i8] c"v8@0:4\00", section "__TEXT,__cstring,cstring_literals", align 1 @OBJC_CLASS_NAME_ = private global [4 x i8] c"foo\00", section "__TEXT,__cstring,cstring_literals", align 1 @OBJC_CLASS_NAME_.1 = private global [2 x i8] c"A\00", section "__TEXT,__cstring,cstring_literals", align 1 -@OBJC_CATEGORY_INSTANCE_METHODS_A_foo = private global { i8*, i32, [1 x %struct._objc_method] } { i8* null, i32 1, [1 x %struct._objc_method] [%struct._objc_method { i8* getelementptr inbounds ([12 x i8], [12 x i8]* @OBJC_METH_VAR_NAME_, i32 0, i32 0), i8* getelementptr inbounds ([7 x i8], [7 x i8]* @OBJC_METH_VAR_TYPE_, i32 0, i32 0), i8* bitcast (void (%0*, i8*)* @"\01-[A(foo) foo_myStuff]" to i8*) }] }, section "__OBJC,__cat_inst_meth,regular,no_dead_strip", align 4 -@OBJC_CATEGORY_A_foo = private global %struct._objc_category { i8* getelementptr inbounds ([4 x i8], [4 x i8]* @OBJC_CLASS_NAME_, i32 0, i32 0), i8* getelementptr inbounds ([2 x i8], [2 x i8]* @OBJC_CLASS_NAME_.1, i32 0, i32 0), %struct._objc_method_list* bitcast ({ i8*, i32, [1 x %struct._objc_method] }* @OBJC_CATEGORY_INSTANCE_METHODS_A_foo to %struct._objc_method_list*), %struct._objc_method_list* null, %struct._objc_protocol_list* null, i32 32, %struct._prop_list_t* null, %struct._prop_list_t* null }, section "__OBJC,__category,regular,no_dead_strip", align 4 +@OBJC_CATEGORY_INSTANCE_METHODS_A_foo = private global { ptr, i32, [1 x %struct._objc_method] } { ptr null, i32 1, [1 x %struct._objc_method] [%struct._objc_method { ptr @OBJC_METH_VAR_NAME_, ptr @OBJC_METH_VAR_TYPE_, ptr @"\01-[A(foo) foo_myStuff]" }] }, section "__OBJC,__cat_inst_meth,regular,no_dead_strip", align 4 +@OBJC_CATEGORY_A_foo = private global %struct._objc_category { ptr @OBJC_CLASS_NAME_, ptr @OBJC_CLASS_NAME_.1, ptr @OBJC_CATEGORY_INSTANCE_METHODS_A_foo, ptr null, ptr null, i32 32, ptr null, ptr null }, section "__OBJC,__category,regular,no_dead_strip", align 4 @OBJC_CLASS_NAME_.2 = private global [1 x i8] zeroinitializer, section "__TEXT,__cstring,cstring_literals", align 1 -@OBJC_SYMBOLS = private global { i32, i8*, i16, i16, [1 x i8*] } { i32 0, i8* null, i16 0, i16 1, [1 x i8*] [i8* bitcast (%struct._objc_category* @OBJC_CATEGORY_A_foo to i8*)] }, section "__OBJC,__symbols,regular,no_dead_strip", align 4 -@OBJC_MODULES = private global %struct._objc_module { i32 7, i32 16, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @OBJC_CLASS_NAME_.2, i32 0, i32 0), %struct._objc_symtab* bitcast ({ i32, i8*, i16, i16, [1 x i8*] }* @OBJC_SYMBOLS to %struct._objc_symtab*) }, section "__OBJC,__module_info,regular,no_dead_strip", align 4 -@llvm.compiler.used = appending global [9 x i8*] [i8* getelementptr inbounds ([12 x i8], [12 x i8]* @OBJC_METH_VAR_NAME_, i32 0, i32 0), i8* getelementptr inbounds ([7 x i8], [7 x i8]* @OBJC_METH_VAR_TYPE_, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @OBJC_CLASS_NAME_, i32 0, i32 0), i8* getelementptr inbounds ([2 x i8], [2 x i8]* @OBJC_CLASS_NAME_.1, i32 0, i32 0), i8* bitcast ({ i8*, i32, [1 x %struct._objc_method] }* @OBJC_CATEGORY_INSTANCE_METHODS_A_foo to i8*), i8* bitcast (%struct._objc_category* @OBJC_CATEGORY_A_foo to i8*), i8* getelementptr inbounds ([1 x i8], [1 x i8]* @OBJC_CLASS_NAME_.2, i32 0, i32 0), i8* bitcast ({ i32, i8*, i16, i16, [1 x i8*] }* @OBJC_SYMBOLS to i8*), i8* bitcast (%struct._objc_module* @OBJC_MODULES to i8*)], section "llvm.metadata" +@OBJC_SYMBOLS = private global { i32, ptr, i16, i16, [1 x ptr] } { i32 0, ptr null, i16 0, i16 1, [1 x ptr] [ptr @OBJC_CATEGORY_A_foo] }, section "__OBJC,__symbols,regular,no_dead_strip", align 4 +@OBJC_MODULES = private global %struct._objc_module { i32 7, i32 16, ptr @OBJC_CLASS_NAME_.2, ptr @OBJC_SYMBOLS }, section "__OBJC,__module_info,regular,no_dead_strip", align 4 +@llvm.compiler.used = appending global [9 x ptr] [ptr @OBJC_METH_VAR_NAME_, ptr @OBJC_METH_VAR_TYPE_, ptr @OBJC_CLASS_NAME_, ptr @OBJC_CLASS_NAME_.1, ptr @OBJC_CATEGORY_INSTANCE_METHODS_A_foo, ptr @OBJC_CATEGORY_A_foo, ptr @OBJC_CLASS_NAME_.2, ptr @OBJC_SYMBOLS, ptr @OBJC_MODULES], section "llvm.metadata" ; Function Attrs: nounwind ssp -define internal void @"\01-[A(foo) foo_myStuff]"(%0*, i8*) #0 { - %3 = alloca %0*, align 4 - %4 = alloca i8*, align 4 - store %0* %0, %0** %3, align 4 - store i8* %1, i8** %4, align 4 +define internal void @"\01-[A(foo) foo_myStuff]"(ptr, ptr) #0 { + %3 = alloca ptr, align 4 + %4 = alloca ptr, align 4 + store ptr %0, ptr %3, align 4 + store ptr %1, ptr %4, align 4 ret void } diff --git a/llvm/test/LTO/X86/objc-detection.ll b/llvm/test/LTO/X86/objc-detection.ll --- a/llvm/test/LTO/X86/objc-detection.ll +++ b/llvm/test/LTO/X86/objc-detection.ll @@ -7,34 +7,34 @@ target triple = "x86_64-apple-macosx10.12.0" %0 = type opaque -%struct._class_t = type { %struct._class_t*, %struct._class_t*, %struct._objc_cache*, i8* (i8*, i8*)**, %struct._class_ro_t* } +%struct._class_t = type { ptr, ptr, ptr, ptr, ptr } %struct._objc_cache = type opaque -%struct._class_ro_t = type { i32, i32, i32, i8*, i8*, %struct.__method_list_t*, %struct._objc_protocol_list*, %struct._ivar_list_t*, i8*, %struct._prop_list_t* } +%struct._class_ro_t = type { i32, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr } %struct.__method_list_t = type { i32, i32, [0 x %struct._objc_method] } -%struct._objc_method = type { i8*, i8*, i8* } -%struct._objc_protocol_list = type { i64, [0 x %struct._protocol_t*] } -%struct._protocol_t = type { i8*, i8*, %struct._objc_protocol_list*, %struct.__method_list_t*, %struct.__method_list_t*, %struct.__method_list_t*, %struct.__method_list_t*, %struct._prop_list_t*, i32, i32, i8**, i8*, %struct._prop_list_t* } +%struct._objc_method = type { ptr, ptr, ptr } +%struct._objc_protocol_list = type { i64, [0 x ptr] } +%struct._protocol_t = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, ptr, ptr, ptr } %struct._ivar_list_t = type { i32, i32, [0 x %struct._ivar_t] } -%struct._ivar_t = type { i64*, i8*, i8*, i32, i32 } +%struct._ivar_t = type { ptr, ptr, ptr, i32, i32 } %struct._prop_list_t = type { i32, i32, [0 x %struct._prop_t] } -%struct._prop_t = type { i8*, i8* } -%struct._category_t = type { i8*, %struct._class_t*, %struct.__method_list_t*, %struct.__method_list_t*, %struct._objc_protocol_list*, %struct._prop_list_t*, %struct._prop_list_t*, i32 } +%struct._prop_t = type { ptr, ptr } +%struct._category_t = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32 } @OBJC_CLASS_NAME_ = private global [4 x i8] c"foo\00", section "__TEXT,__objc_classname,cstring_literals", align 1 @"OBJC_CLASS_$_A" = external global %struct._class_t @OBJC_METH_VAR_NAME_ = private global [12 x i8] c"foo_myStuff\00", section "__TEXT,__objc_methname,cstring_literals", align 1 @OBJC_METH_VAR_TYPE_ = private global [8 x i8] c"v16@0:8\00", section "__TEXT,__objc_methtype,cstring_literals", align 1 -@"\01l_OBJC_$_CATEGORY_INSTANCE_METHODS_A_$_foo" = private global { i32, i32, [1 x %struct._objc_method] } { i32 24, i32 1, [1 x %struct._objc_method] [%struct._objc_method { i8* getelementptr inbounds ([12 x i8], [12 x i8]* @OBJC_METH_VAR_NAME_, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8], [8 x i8]* @OBJC_METH_VAR_TYPE_, i32 0, i32 0), i8* bitcast (void (%0*, i8*)* @"\01-[A(foo) foo_myStuff]" to i8*) }] }, section "__DATA, __objc_const", align 8 -@"\01l_OBJC_$_CATEGORY_A_$_foo" = private global %struct._category_t { i8* getelementptr inbounds ([4 x i8], [4 x i8]* @OBJC_CLASS_NAME_, i32 0, i32 0), %struct._class_t* @"OBJC_CLASS_$_A", %struct.__method_list_t* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_CATEGORY_INSTANCE_METHODS_A_$_foo" to %struct.__method_list_t*), %struct.__method_list_t* null, %struct._objc_protocol_list* null, %struct._prop_list_t* null, %struct._prop_list_t* null, i32 64 }, section "__DATA, __objc_const", align 8 -@"OBJC_LABEL_CATEGORY_$" = private global [1 x i8*] [i8* bitcast (%struct._category_t* @"\01l_OBJC_$_CATEGORY_A_$_foo" to i8*)], section "__DATA, __objc_catlist, regular, no_dead_strip", align 8 -@llvm.compiler.used = appending global [6 x i8*] [i8* getelementptr inbounds ([4 x i8], [4 x i8]* @OBJC_CLASS_NAME_, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @OBJC_METH_VAR_NAME_, i32 0, i32 0), i8* getelementptr inbounds ([8 x i8], [8 x i8]* @OBJC_METH_VAR_TYPE_, i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_CATEGORY_INSTANCE_METHODS_A_$_foo" to i8*), i8* bitcast (%struct._category_t* @"\01l_OBJC_$_CATEGORY_A_$_foo" to i8*), i8* bitcast ([1 x i8*]* @"OBJC_LABEL_CATEGORY_$" to i8*)], section "llvm.metadata" +@"\01l_OBJC_$_CATEGORY_INSTANCE_METHODS_A_$_foo" = private global { i32, i32, [1 x %struct._objc_method] } { i32 24, i32 1, [1 x %struct._objc_method] [%struct._objc_method { ptr @OBJC_METH_VAR_NAME_, ptr @OBJC_METH_VAR_TYPE_, ptr @"\01-[A(foo) foo_myStuff]" }] }, section "__DATA, __objc_const", align 8 +@"\01l_OBJC_$_CATEGORY_A_$_foo" = private global %struct._category_t { ptr @OBJC_CLASS_NAME_, ptr @"OBJC_CLASS_$_A", ptr @"\01l_OBJC_$_CATEGORY_INSTANCE_METHODS_A_$_foo", ptr null, ptr null, ptr null, ptr null, i32 64 }, section "__DATA, __objc_const", align 8 +@"OBJC_LABEL_CATEGORY_$" = private global [1 x ptr] [ptr @"\01l_OBJC_$_CATEGORY_A_$_foo"], section "__DATA, __objc_catlist, regular, no_dead_strip", align 8 +@llvm.compiler.used = appending global [6 x ptr] [ptr @OBJC_CLASS_NAME_, ptr @OBJC_METH_VAR_NAME_, ptr @OBJC_METH_VAR_TYPE_, ptr @"\01l_OBJC_$_CATEGORY_INSTANCE_METHODS_A_$_foo", ptr @"\01l_OBJC_$_CATEGORY_A_$_foo", ptr @"OBJC_LABEL_CATEGORY_$"], section "llvm.metadata" ; Function Attrs: ssp uwtable -define internal void @"\01-[A(foo) foo_myStuff]"(%0*, i8*) #0 { - %3 = alloca %0*, align 8 - %4 = alloca i8*, align 8 - store %0* %0, %0** %3, align 8 - store i8* %1, i8** %4, align 8 +define internal void @"\01-[A(foo) foo_myStuff]"(ptr, ptr) #0 { + %3 = alloca ptr, align 8 + %4 = alloca ptr, align 8 + store ptr %0, ptr %3, align 8 + store ptr %1, ptr %4, align 8 ret void } diff --git a/llvm/test/LTO/X86/pr38046.ll b/llvm/test/LTO/X86/pr38046.ll --- a/llvm/test/LTO/X86/pr38046.ll +++ b/llvm/test/LTO/X86/pr38046.ll @@ -11,7 +11,7 @@ target triple = "x86_64-unknown-linux-gnu" define i32 @foo() { - call void @llvm.dbg.value(metadata i32 ()* @get, metadata !7, metadata !DIExpression()), !dbg !DILocation(scope: !6) + call void @llvm.dbg.value(metadata ptr @get, metadata !7, metadata !DIExpression()), !dbg !DILocation(scope: !6) ret i32 0 } diff --git a/llvm/test/LTO/X86/remangle_intrinsics.ll b/llvm/test/LTO/X86/remangle_intrinsics.ll --- a/llvm/test/LTO/X86/remangle_intrinsics.ll +++ b/llvm/test/LTO/X86/remangle_intrinsics.ll @@ -14,9 +14,9 @@ %struct.rtx_def = type { i16 } -define void @foo(%struct.rtx_def* %a, i8 %b, i32 %c) { - call void @llvm.memset.p0struct.rtx_def.i32(%struct.rtx_def* align 4 %a, i8 %b, i32 %c, i1 true) +define void @foo(ptr %a, i8 %b, i32 %c) { + call void @llvm.memset.p0.rtx_def.i32(ptr align 4 %a, i8 %b, i32 %c, i1 true) ret void } -declare void @llvm.memset.p0struct.rtx_def.i32(%struct.rtx_def*, i8, i32, i1) +declare void @llvm.memset.p0.rtx_def.i32(ptr, i8, i32, i1) diff --git a/llvm/test/LTO/X86/set-merged.ll b/llvm/test/LTO/X86/set-merged.ll --- a/llvm/test/LTO/X86/set-merged.ll +++ b/llvm/test/LTO/X86/set-merged.ll @@ -10,9 +10,9 @@ define i32 @_Z3fooi(i32 %a) { entry: %a.addr = alloca i32, align 4 - store i32 %a, i32* %a.addr, align 4 - %0 = load i32, i32* %a.addr, align 4 - %1 = load i32, i32* %a.addr, align 4 + store i32 %a, ptr %a.addr, align 4 + %0 = load i32, ptr %a.addr, align 4 + %1 = load i32, ptr %a.addr, align 4 %call = call i32 @_Z4bar2i(i32 %1) %add = add nsw i32 %0, %call ret i32 %add @@ -21,8 +21,8 @@ define i32 @_Z4bar2i(i32 %a) { entry: %a.addr = alloca i32, align 4 - store i32 %a, i32* %a.addr, align 4 - %0 = load i32, i32* %a.addr, align 4 + store i32 %a, ptr %a.addr, align 4 + %0 = load i32, ptr %a.addr, align 4 %mul = mul nsw i32 2, %0 ret i32 %mul } @@ -30,7 +30,7 @@ define i32 @main() { entry: %retval = alloca i32, align 4 - store i32 0, i32* %retval + store i32 0, ptr %retval %call = call i32 @_Z3fooi(i32 44) ret i32 %call } diff --git a/llvm/test/LTO/X86/stdcall.ll b/llvm/test/LTO/X86/stdcall.ll --- a/llvm/test/LTO/X86/stdcall.ll +++ b/llvm/test/LTO/X86/stdcall.ll @@ -5,6 +5,6 @@ target triple = "i386-pc-windows-msvc19.0.23918" ; CHECK: .globl _DllMain@12 -define x86_stdcallcc i32 @DllMain(i8* %module, i32 %reason, i8* %reserved) { +define x86_stdcallcc i32 @DllMain(ptr %module, i32 %reason, ptr %reserved) { ret i32 1 } diff --git a/llvm/test/LTO/X86/symver-asm.ll b/llvm/test/LTO/X86/symver-asm.ll --- a/llvm/test/LTO/X86/symver-asm.ll +++ b/llvm/test/LTO/X86/symver-asm.ll @@ -17,7 +17,7 @@ ; Local values used in inline assembly must be specified on the ; llvm.compiler.used so they aren't incorrectly DCE'd during module linking. -@llvm.compiler.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @io_cancel_local_0_4 to i8*)], section "llvm.metadata" +@llvm.compiler.used = appending global [1 x ptr] [ptr @io_cancel_local_0_4], section "llvm.metadata" define i32 @io_cancel_0_4() { ; CHECK-DAG: T io_cancel@@LIBAIO_0.4 diff --git a/llvm/test/LTO/X86/tli-nobuiltin.ll b/llvm/test/LTO/X86/tli-nobuiltin.ll --- a/llvm/test/LTO/X86/tli-nobuiltin.ll +++ b/llvm/test/LTO/X86/tli-nobuiltin.ll @@ -31,7 +31,7 @@ target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.11.0" -declare i32 @fprintf(%FILE*, i8*, ...) +declare i32 @fprintf(ptr, ptr, ...) %FILE = type { } @@ -40,9 +40,7 @@ ; Check fprintf(fp, "%s", str) -> fwrite(str, fp) only when builtins are enabled -define void @foo(%FILE* %fp) { - %fmt = getelementptr [3 x i8], [3 x i8]* @percent_s, i32 0, i32 0 - %str = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0 - call i32 (%FILE*, i8*, ...) @fprintf(%FILE* %fp, i8* %fmt, i8* %str) +define void @foo(ptr %fp) { + call i32 (ptr, ptr, ...) @fprintf(ptr %fp, ptr @percent_s, ptr @hello_world) ret void } diff --git a/llvm/test/LTO/X86/triple-init2.ll b/llvm/test/LTO/X86/triple-init2.ll --- a/llvm/test/LTO/X86/triple-init2.ll +++ b/llvm/test/LTO/X86/triple-init2.ll @@ -18,7 +18,7 @@ target datalayout = "e-m:w-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-windows-msvc19.11.0" -define dso_local i32 @main(i32 %argc, i8** nocapture readnone %argv) local_unnamed_addr { +define dso_local i32 @main(i32 %argc, ptr nocapture readnone %argv) local_unnamed_addr { entry: %conv = sitofp i32 %argc to float %exp2 = tail call float @llvm.exp2.f32(float %conv) diff --git a/llvm/test/LTO/X86/type-mapping-bug.ll b/llvm/test/LTO/X86/type-mapping-bug.ll --- a/llvm/test/LTO/X86/type-mapping-bug.ll +++ b/llvm/test/LTO/X86/type-mapping-bug.ll @@ -11,11 +11,11 @@ %CommonStruct = type { i32 } ; The Src module will re-use our DINode for this type. %Tricky = type opaque -%Tricky.1 = type { %DstType* } +%Tricky.1 = type { ptr } @x = global %DstType zeroinitializer @foo = internal global %CommonStruct zeroinitializer, !dbg !0 -; That DINode will refer to this value, casted to %Tricky.1* (!11), +; That DINode will refer to this value, casted to ptr (!11), ; which will then show up in Src's getIdentifiedStructTypes(). @templateValueParam = global i8 0 ; Because of the names, we would try to map %Tricky.1 to %Tricky -- @@ -24,7 +24,7 @@ ; a destination type. Since these types are not in the source module, ; there should be no attempt to create a mapping involving them; ; both types should be left as they are. -@use = global %Tricky* null +@use = global ptr null ; Mark %Tricky used. !llvm.dbg.cu = !{!2} @@ -41,7 +41,7 @@ !8 = !DIDerivedType(tag: DW_TAG_inheritance, scope: !6, baseType: !9) !9 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Template<&x>", file: !3, line: 3, size: 8, elements: !4, templateParams: !10, identifier: ".?AU?$Template@$1?x@@3UX@@A@@") !10 = !{!11} -!11 = !DITemplateValueParameter(type: !12, value: %Tricky.1* bitcast (i8* @templateValueParam to %Tricky.1*)) +!11 = !DITemplateValueParameter(type: !12, value: ptr @templateValueParam) !12 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !13, size: 64) !13 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "X", file: !3, line: 1, size: 8, elements: !4, identifier: ".?AUX@@") !14 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/llvm/test/LTO/X86/type-mapping-bug2.ll b/llvm/test/LTO/X86/type-mapping-bug2.ll --- a/llvm/test/LTO/X86/type-mapping-bug2.ll +++ b/llvm/test/LTO/X86/type-mapping-bug2.ll @@ -16,7 +16,7 @@ unreachable } -define i1 @b(%"T2"*) { +define i1 @b(ptr) { unreachable } @@ -32,7 +32,7 @@ ; The reference to @b and T2 that will be loaded in %t0.o -!7 = !DITemplateValueParameter(value: i1 (%"T2"*)* @b) +!7 = !DITemplateValueParameter(value: ptr @b) !8 = distinct !DISubprogram(unit: !2) ; This DICompositeType is uniqued against !5 in Inputs/type-mapping-bug2.ll, diff --git a/llvm/test/LTO/X86/type-mapping-bug3.ll b/llvm/test/LTO/X86/type-mapping-bug3.ll --- a/llvm/test/LTO/X86/type-mapping-bug3.ll +++ b/llvm/test/LTO/X86/type-mapping-bug3.ll @@ -9,7 +9,7 @@ ; T2 is the non-opaque struct required to trigger the uniqued T2.0 and T3.0 to ; respectively T2 and T3 in the destination module. -%"T2" = type { %"T3"* } +%"T2" = type { ptr } %"T3" = type opaque ; Use/refer to T2 so it gets added as an IdentifiedStructType. @@ -19,14 +19,14 @@ ; The global declaration that causes the assertion when its type is mapped to ; itself incorrectly. -declare void @d(%"T3"*) +declare void @d(ptr) define void @b() { entry: - %f.addr = alloca %"T3"*load %"T3"*, %"T3"** %f.addr + %f.addr = alloca ptr load ptr, ptr %f.addr ; The call with the getCalledOperand() vs getCalledFunction() mismatch. - call void @d(%"T3"* %0) + call void @d(ptr %0) unreachable } @@ -44,4 +44,4 @@ !6 = !{!7} ; The reference to d and T3 that gets loaded into %t0.o -!7 = !DITemplateValueParameter(value: void (%"T3"*)* @d) +!7 = !DITemplateValueParameter(value: ptr @d) diff --git a/llvm/test/LTO/X86/unnamed.ll b/llvm/test/LTO/X86/unnamed.ll --- a/llvm/test/LTO/X86/unnamed.ll +++ b/llvm/test/LTO/X86/unnamed.ll @@ -7,4 +7,4 @@ target triple = "x86_64-unknown-linux-gnu" @0 = private global i32 42 -@foo = constant i32* @0 +@foo = constant ptr @0 diff --git a/llvm/test/MC/AArch64/SME/ld1b.s b/llvm/test/MC/AArch64/SME/ld1b.s --- a/llvm/test/MC/AArch64/SME/ld1b.s +++ b/llvm/test/MC/AArch64/SME/ld1b.s @@ -305,3 +305,18 @@ // CHECK-ENCODING: [0x87,0xa9,0x0b,0xe0] // CHECK-ERROR: instruction requires: sme // CHECK-UNKNOWN: e00ba987 + +// --------------------------------------------------------------------------// +// Test parsing in all-caps + +LD1B {ZA0H.B[W12, 0]}, P0/Z, [X0, X0] +// CHECK-INST: ld1b {za0h.b[w12, 0]}, p0/z, [x0, x0] +// CHECK-ENCODING: [0x00,0x00,0x00,0xe0] +// CHECK-ERROR: instruction requires: sme +// CHECK-UNKNOWN: e0000000 + +LD1B {ZA0V.B[W12, 0]}, P0/Z, [X0, X0] +// CHECK-INST: ld1b {za0v.b[w12, 0]}, p0/z, [x0, x0] +// CHECK-ENCODING: [0x00,0x80,0x00,0xe0] +// CHECK-ERROR: instruction requires: sme +// CHECK-UNKNOWN: e0008000 diff --git a/llvm/test/MC/AArch64/arm64-memory.s b/llvm/test/MC/AArch64/arm64-memory.s --- a/llvm/test/MC/AArch64/arm64-memory.s +++ b/llvm/test/MC/AArch64/arm64-memory.s @@ -498,11 +498,23 @@ stlrb w3, [x6] stlrh w3, [x6] + stlr w3, [x6, #0] + stlr x3, [x6, 0] + stlrb w3, [sp] + stlrb w3, [sp, #0] + stlrb w3, [sp, 0] + ; CHECK: stlr w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x88] ; CHECK: stlr x3, [x6] ; encoding: [0xc3,0xfc,0x9f,0xc8] ; CHECK: stlrb w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x08] ; CHECK: stlrh w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x48] +; CHECK: stlr w3, [x6] ; encoding: [0xc3,0xfc,0x9f,0x88] +; CHECK: stlr x3, [x6] ; encoding: [0xc3,0xfc,0x9f,0xc8] +; CHECK: stlrb w3, [sp] ; encoding: [0xe3,0xff,0x9f,0x08] +; CHECK: stlrb w3, [sp] ; encoding: [0xe3,0xff,0x9f,0x08] +; CHECK: stlrb w3, [sp] ; encoding: [0xe3,0xff,0x9f,0x08] + ;----------------------------------------------------------------------------- ; Load-acquire/Store-release exclusive ;----------------------------------------------------------------------------- diff --git a/llvm/test/MC/AArch64/arm64-system-encoding.s b/llvm/test/MC/AArch64/arm64-system-encoding.s --- a/llvm/test/MC/AArch64/arm64-system-encoding.s +++ b/llvm/test/MC/AArch64/arm64-system-encoding.s @@ -609,6 +609,7 @@ mrs x0, ID_PFR0_EL1 mrs x0, ID_PFR1_EL1 mrs x0, ID_DFR0_EL1 + mrs x0, ID_DFR1_EL1 mrs x0, ID_AFR0_EL1 mrs x0, ID_ISAR0_EL1 mrs x0, ID_ISAR1_EL1 @@ -622,6 +623,7 @@ ; CHECK: mrs x0, ID_PFR0_EL1 ; encoding: [0x00,0x01,0x38,0xd5] ; CHECK: mrs x0, ID_PFR1_EL1 ; encoding: [0x20,0x01,0x38,0xd5] ; CHECK: mrs x0, ID_DFR0_EL1 ; encoding: [0x40,0x01,0x38,0xd5] +; CHECK: mrs x0, ID_DFR1_EL1 ; encoding: [0xa0,0x03,0x38,0xd5] ; CHECK: mrs x0, ID_AFR0_EL1 ; encoding: [0x60,0x01,0x38,0xd5] ; CHECK: mrs x0, ID_ISAR0_EL1 ; encoding: [0x00,0x02,0x38,0xd5] ; CHECK: mrs x0, ID_ISAR1_EL1 ; encoding: [0x20,0x02,0x38,0xd5] diff --git a/llvm/test/MC/AArch64/armv8.6a-amvs.s b/llvm/test/MC/AArch64/armv8.6a-amvs.s --- a/llvm/test/MC/AArch64/armv8.6a-amvs.s +++ b/llvm/test/MC/AArch64/armv8.6a-amvs.s @@ -1,6 +1,7 @@ // RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+amvs -o - %s | FileCheck %s // RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a -o - %s | FileCheck %s -// RUN: not llvm-mc -triple aarch64 -show-encoding -o - %p/armv8.6a-amvs.s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: not llvm-mc -triple aarch64 -show-encoding -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR +mrs x0, AMCG1IDR_EL0 msr AMEVCNTVOFF00_EL2, x0 msr AMEVCNTVOFF01_EL2, x0 msr AMEVCNTVOFF02_EL2, x0 @@ -67,6 +68,7 @@ mrs x0, AMEVCNTVOFF115_EL2 // CHECK: .text +// CHECK-NEXT: mrs x0, AMCG1IDR_EL0 // encoding: [0xc0,0xd2,0x3b,0xd5] // CHECK-NEXT: msr AMEVCNTVOFF00_EL2, x0 // encoding: [0x00,0xd8,0x1c,0xd5] // CHECK-NEXT: msr AMEVCNTVOFF01_EL2, x0 // encoding: [0x20,0xd8,0x1c,0xd5] // CHECK-NEXT: msr AMEVCNTVOFF02_EL2, x0 // encoding: [0x40,0xd8,0x1c,0xd5] diff --git a/llvm/test/MC/AArch64/armv8.6a-fgt.s b/llvm/test/MC/AArch64/armv8.6a-fgt.s --- a/llvm/test/MC/AArch64/armv8.6a-fgt.s +++ b/llvm/test/MC/AArch64/armv8.6a-fgt.s @@ -7,11 +7,14 @@ msr HFGITR_EL2, x10 msr HDFGRTR_EL2, x15 msr HDFGWTR_EL2, x20 +msr HAFGRTR_EL2, x25 // CHECK: msr HFGRTR_EL2, x0 // encoding: [0x80,0x11,0x1c,0xd5] // CHECK: msr HFGWTR_EL2, x5 // encoding: [0xa5,0x11,0x1c,0xd5] // CHECK: msr HFGITR_EL2, x10 // encoding: [0xca,0x11,0x1c,0xd5] // CHECK: msr HDFGRTR_EL2, x15 // encoding: [0x8f,0x31,0x1c,0xd5] // CHECK: msr HDFGWTR_EL2, x20 // encoding: [0xb4,0x31,0x1c,0xd5] +// CHECK: msr HAFGRTR_EL2, x25 // encoding: [0xd9,0x31,0x1c,0xd5] +// NOFGT: error: expected writable system register or pstate // NOFGT: error: expected writable system register or pstate // NOFGT: error: expected writable system register or pstate // NOFGT: error: expected writable system register or pstate @@ -23,13 +26,44 @@ mrs x20, HFGITR_EL2 mrs x15, HDFGRTR_EL2 mrs x10, HDFGWTR_EL2 +mrs x5, HAFGRTR_EL2 // CHECK: mrs x30, HFGRTR_EL2 // encoding: [0x9e,0x11,0x3c,0xd5] // CHECK: mrs x25, HFGWTR_EL2 // encoding: [0xb9,0x11,0x3c,0xd5] // CHECK: mrs x20, HFGITR_EL2 // encoding: [0xd4,0x11,0x3c,0xd5] // CHECK: mrs x15, HDFGRTR_EL2 // encoding: [0x8f,0x31,0x3c,0xd5] // CHECK: mrs x10, HDFGWTR_EL2 // encoding: [0xaa,0x31,0x3c,0xd5] +// CHECK: mrs x5, HAFGRTR_EL2 // encoding: [0xc5,0x31,0x3c,0xd5] +// NOFGT: error: expected readable system register +// NOFGT: error: expected readable system register +// NOFGT: error: expected readable system register +// NOFGT: error: expected readable system register // NOFGT: error: expected readable system register // NOFGT: error: expected readable system register + + +mrs x3, HDFGRTR2_EL2 +mrs x3, HDFGWTR2_EL2 +mrs x3, HFGRTR2_EL2 +mrs x3, HFGWTR2_EL2 +// CHECK: mrs x3, HDFGRTR2_EL2 // encoding: [0x03,0x31,0x3c,0xd5] +// CHECK: mrs x3, HDFGWTR2_EL2 // encoding: [0x23,0x31,0x3c,0xd5] +// CHECK: mrs x3, HFGRTR2_EL2 // encoding: [0x43,0x31,0x3c,0xd5] +// CHECK: mrs x3, HFGWTR2_EL2 // encoding: [0x63,0x31,0x3c,0xd5] +// NOFGT: error: expected readable system register // NOFGT: error: expected readable system register // NOFGT: error: expected readable system register // NOFGT: error: expected readable system register + + +msr HDFGRTR2_EL2, x3 +msr HDFGWTR2_EL2, x3 +msr HFGRTR2_EL2, x3 +msr HFGWTR2_EL2, x3 +// CHECK: msr HDFGRTR2_EL2, x3 // encoding: [0x03,0x31,0x1c,0xd5] +// CHECK: msr HDFGWTR2_EL2, x3 // encoding: [0x23,0x31,0x1c,0xd5] +// CHECK: msr HFGRTR2_EL2, x3 // encoding: [0x43,0x31,0x1c,0xd5] +// CHECK: msr HFGWTR2_EL2, x3 // encoding: [0x63,0x31,0x1c,0xd5] +// NOFGT: error: expected writable system register +// NOFGT: error: expected writable system register +// NOFGT: error: expected writable system register +// NOFGT: error: expected writable system register diff --git a/llvm/test/MC/AArch64/armv8.9a-debug-pmu-error.s b/llvm/test/MC/AArch64/armv8.9a-debug-pmu-error.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/armv8.9a-debug-pmu-error.s @@ -0,0 +1,9 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ite < %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a -mattr=+ite < %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a -mattr=+ite < %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.3a -mattr=+ite < %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a -mattr=+ite < %s 2>&1 | FileCheck %s + +// FEAT_PMUv3p9/FEAT_PMUV3_ICNTR - PMZR_EL0 is write-only + mrs x3, PMZR_EL0 +// CHECK: [[@LINE-1]]:21: error: expected readable system register diff --git a/llvm/test/MC/AArch64/armv8.9a-debug-pmu.s b/llvm/test/MC/AArch64/armv8.9a-debug-pmu.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/armv8.9a-debug-pmu.s @@ -0,0 +1,485 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ite < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a -mattr=+ite < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a -mattr=+ite < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.3a -mattr=+ite < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a -mattr=+ite < %s | FileCheck %s + +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.8a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.3a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-ITE %s + +// FEAT_DEBUGv8p9 + mrs x3, MDSELR_EL1 +// CHECK: mrs x3, MDSELR_EL1 // encoding: [0x43,0x04,0x30,0xd5] + msr MDSELR_EL1, x1 +// CHECK: msr MDSELR_EL1, x1 // encoding: [0x41,0x04,0x10,0xd5] + +// FEAT_PMUv3p9 + mrs x3, PMUACR_EL1 +// CHECK: mrs x3, PMUACR_EL1 // encoding: [0x83,0x9e,0x38,0xd5] + msr PMUACR_EL1, x1 +// CHECK: msr PMUACR_EL1, x1 // encoding: [0x81,0x9e,0x18,0xd5] + +// FEAT_PMUv3_SS + mrs x3, PMCCNTSVR_EL1 +// CHECK: mrs x3, PMCCNTSVR_EL1 // encoding: [0xe3,0xeb,0x30,0xd5] + mrs x3, PMICNTSVR_EL1 +// CHECK: mrs x3, PMICNTSVR_EL1 // encoding: [0x03,0xec,0x30,0xd5] + mrs x3, PMSSCR_EL1 +// CHECK: mrs x3, PMSSCR_EL1 // encoding: [0x63,0x9d,0x38,0xd5] + msr PMSSCR_EL1, x1 +// CHECK: msr PMSSCR_EL1, x1 // encoding: [0x61,0x9d,0x18,0xd5] + mrs x3, PMEVCNTSVR0_EL1 +// CHECK: mrs x3, PMEVCNTSVR0_EL1 // encoding: [0x03,0xe8,0x30,0xd5] + mrs x3, PMEVCNTSVR1_EL1 +// CHECK: mrs x3, PMEVCNTSVR1_EL1 // encoding: [0x23,0xe8,0x30,0xd5] + mrs x3, PMEVCNTSVR2_EL1 +// CHECK: mrs x3, PMEVCNTSVR2_EL1 // encoding: [0x43,0xe8,0x30,0xd5] + mrs x3, PMEVCNTSVR3_EL1 +// CHECK: mrs x3, PMEVCNTSVR3_EL1 // encoding: [0x63,0xe8,0x30,0xd5] + mrs x3, PMEVCNTSVR4_EL1 +// CHECK: mrs x3, PMEVCNTSVR4_EL1 // encoding: [0x83,0xe8,0x30,0xd5] + mrs x3, PMEVCNTSVR5_EL1 +// CHECK: mrs x3, PMEVCNTSVR5_EL1 // encoding: [0xa3,0xe8,0x30,0xd5] + mrs x3, PMEVCNTSVR6_EL1 +// CHECK: mrs x3, PMEVCNTSVR6_EL1 // encoding: [0xc3,0xe8,0x30,0xd5] + mrs x3, PMEVCNTSVR7_EL1 +// CHECK: mrs x3, PMEVCNTSVR7_EL1 // encoding: [0xe3,0xe8,0x30,0xd5] + mrs x3, PMEVCNTSVR8_EL1 +// CHECK: mrs x3, PMEVCNTSVR8_EL1 // encoding: [0x03,0xe9,0x30,0xd5] + mrs x3, PMEVCNTSVR9_EL1 +// CHECK: mrs x3, PMEVCNTSVR9_EL1 // encoding: [0x23,0xe9,0x30,0xd5] + mrs x3, PMEVCNTSVR10_EL1 +// CHECK: mrs x3, PMEVCNTSVR10_EL1 // encoding: [0x43,0xe9,0x30,0xd5] + mrs x3, PMEVCNTSVR11_EL1 +// CHECK: mrs x3, PMEVCNTSVR11_EL1 // encoding: [0x63,0xe9,0x30,0xd5] + mrs x3, PMEVCNTSVR12_EL1 +// CHECK: mrs x3, PMEVCNTSVR12_EL1 // encoding: [0x83,0xe9,0x30,0xd5] + mrs x3, PMEVCNTSVR13_EL1 +// CHECK: mrs x3, PMEVCNTSVR13_EL1 // encoding: [0xa3,0xe9,0x30,0xd5] + mrs x3, PMEVCNTSVR14_EL1 +// CHECK: mrs x3, PMEVCNTSVR14_EL1 // encoding: [0xc3,0xe9,0x30,0xd5] + mrs x3, PMEVCNTSVR15_EL1 +// CHECK: mrs x3, PMEVCNTSVR15_EL1 // encoding: [0xe3,0xe9,0x30,0xd5] + mrs x3, PMEVCNTSVR16_EL1 +// CHECK: mrs x3, PMEVCNTSVR16_EL1 // encoding: [0x03,0xea,0x30,0xd5] + mrs x3, PMEVCNTSVR17_EL1 +// CHECK: mrs x3, PMEVCNTSVR17_EL1 // encoding: [0x23,0xea,0x30,0xd5] + mrs x3, PMEVCNTSVR18_EL1 +// CHECK: mrs x3, PMEVCNTSVR18_EL1 // encoding: [0x43,0xea,0x30,0xd5] + mrs x3, PMEVCNTSVR19_EL1 +// CHECK: mrs x3, PMEVCNTSVR19_EL1 // encoding: [0x63,0xea,0x30,0xd5] + mrs x3, PMEVCNTSVR20_EL1 +// CHECK: mrs x3, PMEVCNTSVR20_EL1 // encoding: [0x83,0xea,0x30,0xd5] + mrs x3, PMEVCNTSVR21_EL1 +// CHECK: mrs x3, PMEVCNTSVR21_EL1 // encoding: [0xa3,0xea,0x30,0xd5] + mrs x3, PMEVCNTSVR22_EL1 +// CHECK: mrs x3, PMEVCNTSVR22_EL1 // encoding: [0xc3,0xea,0x30,0xd5] + mrs x3, PMEVCNTSVR23_EL1 +// CHECK: mrs x3, PMEVCNTSVR23_EL1 // encoding: [0xe3,0xea,0x30,0xd5] + mrs x3, PMEVCNTSVR24_EL1 +// CHECK: mrs x3, PMEVCNTSVR24_EL1 // encoding: [0x03,0xeb,0x30,0xd5] + mrs x3, PMEVCNTSVR25_EL1 +// CHECK: mrs x3, PMEVCNTSVR25_EL1 // encoding: [0x23,0xeb,0x30,0xd5] + mrs x3, PMEVCNTSVR26_EL1 +// CHECK: mrs x3, PMEVCNTSVR26_EL1 // encoding: [0x43,0xeb,0x30,0xd5] + mrs x3, PMEVCNTSVR27_EL1 +// CHECK: mrs x3, PMEVCNTSVR27_EL1 // encoding: [0x63,0xeb,0x30,0xd5] + mrs x3, PMEVCNTSVR28_EL1 +// CHECK: mrs x3, PMEVCNTSVR28_EL1 // encoding: [0x83,0xeb,0x30,0xd5] + mrs x3, PMEVCNTSVR29_EL1 +// CHECK: mrs x3, PMEVCNTSVR29_EL1 // encoding: [0xa3,0xeb,0x30,0xd5] + mrs x3, PMEVCNTSVR30_EL1 +// CHECK: mrs x3, PMEVCNTSVR30_EL1 // encoding: [0xc3,0xeb,0x30,0xd5] + +// FEAT_PMUv3_ICNTR + mrs x3, PMICNTR_EL0 +// CHECK: mrs x3, PMICNTR_EL0 // encoding: [0x03,0x94,0x3b,0xd5] + msr PMICNTR_EL0, x3 +// CHECK: msr PMICNTR_EL0, x3 // encoding: [0x03,0x94,0x1b,0xd5] + mrs x3, PMICFILTR_EL0 +// CHECK: mrs x3, PMICFILTR_EL0 // encoding: [0x03,0x96,0x3b,0xd5] + msr PMICFILTR_EL0, x3 +// CHECK: msr PMICFILTR_EL0, x3 // encoding: [0x03,0x96,0x1b,0xd5] + +// FEAT_PMUv3p9/FEAT_PMUV3_ICNTR + msr PMZR_EL0, x3 +// CHECK: msr PMZR_EL0, x3 // encoding: [0x83,0x9d,0x1b,0xd5] + +// FEAT_SEBEP + mrs x3, PMECR_EL1 +// CHECK: mrs x3, PMECR_EL1 // encoding: [0xa3,0x9e,0x38,0xd5] + msr PMECR_EL1, x1 +// CHECK: msr PMECR_EL1, x1 // encoding: [0xa1,0x9e,0x18,0xd5] + mrs x3, PMIAR_EL1 +// CHECK: mrs x3, PMIAR_EL1 // encoding: [0xe3,0x9e,0x38,0xd5] + msr PMIAR_EL1, x1 +// CHECK: msr PMIAR_EL1, x1 // encoding: [0xe1,0x9e,0x18,0xd5] + +// FEAT_SPMU + mrs x3, SPMACCESSR_EL1 +// CHECK: mrs x3, SPMACCESSR_EL1 // encoding: [0x63,0x9d,0x30,0xd5] + msr SPMACCESSR_EL1, x1 +// CHECK: msr SPMACCESSR_EL1, x1 // encoding: [0x61,0x9d,0x10,0xd5] + mrs x3, SPMACCESSR_EL12 +// CHECK: mrs x3, SPMACCESSR_EL12 // encoding: [0x63,0x9d,0x35,0xd5] + msr SPMACCESSR_EL12, x1 +// CHECK: msr SPMACCESSR_EL12, x1 // encoding: [0x61,0x9d,0x15,0xd5] + mrs x3, SPMACCESSR_EL2 +// CHECK: mrs x3, SPMACCESSR_EL2 // encoding: [0x63,0x9d,0x34,0xd5] + msr SPMACCESSR_EL2, x1 +// CHECK: msr SPMACCESSR_EL2, x1 // encoding: [0x61,0x9d,0x14,0xd5] + mrs x3, SPMACCESSR_EL3 +// CHECK: mrs x3, SPMACCESSR_EL3 // encoding: [0x63,0x9d,0x36,0xd5] + msr SPMACCESSR_EL3, x1 +// CHECK: msr SPMACCESSR_EL3, x1 // encoding: [0x61,0x9d,0x16,0xd5] + mrs x3, SPMCNTENCLR_EL0 +// CHECK: mrs x3, SPMCNTENCLR_EL0 // encoding: [0x43,0x9c,0x33,0xd5] + msr SPMCNTENCLR_EL0, x1 +// CHECK: msr SPMCNTENCLR_EL0, x1 // encoding: [0x41,0x9c,0x13,0xd5] + mrs x3, SPMCNTENSET_EL0 +// CHECK: mrs x3, SPMCNTENSET_EL0 // encoding: [0x23,0x9c,0x33,0xd5] + msr SPMCNTENSET_EL0, x1 +// CHECK: msr SPMCNTENSET_EL0, x1 // encoding: [0x21,0x9c,0x13,0xd5] + mrs x3, SPMCR_EL0 +// CHECK: mrs x3, SPMCR_EL0 // encoding: [0x03,0x9c,0x33,0xd5] + msr SPMCR_EL0, x1 +// CHECK: msr SPMCR_EL0, x1 // encoding: [0x01,0x9c,0x13,0xd5] + mrs x3, SPMDEVAFF_EL1 +// CHECK: mrs x3, SPMDEVAFF_EL1 // encoding: [0xc3,0x9d,0x30,0xd5] + mrs x3, SPMDEVARCH_EL1 +// CHECK: mrs x3, SPMDEVARCH_EL1 // encoding: [0xa3,0x9d,0x30,0xd5] + + mrs x3, SPMEVCNTR0_EL0 +// CHECK: mrs x3, SPMEVCNTR0_EL0 // encoding: [0x03,0xe0,0x33,0xd5] + msr SPMEVCNTR0_EL0, x1 +// CHECK: msr SPMEVCNTR0_EL0, x1 // encoding: [0x01,0xe0,0x13,0xd5] + mrs x3, SPMEVCNTR1_EL0 +// CHECK: mrs x3, SPMEVCNTR1_EL0 // encoding: [0x23,0xe0,0x33,0xd5] + msr SPMEVCNTR1_EL0, x1 +// CHECK: msr SPMEVCNTR1_EL0, x1 // encoding: [0x21,0xe0,0x13,0xd5] + mrs x3, SPMEVCNTR2_EL0 +// CHECK: mrs x3, SPMEVCNTR2_EL0 // encoding: [0x43,0xe0,0x33,0xd5] + msr SPMEVCNTR2_EL0, x1 +// CHECK: msr SPMEVCNTR2_EL0, x1 // encoding: [0x41,0xe0,0x13,0xd5] + mrs x3, SPMEVCNTR3_EL0 +// CHECK: mrs x3, SPMEVCNTR3_EL0 // encoding: [0x63,0xe0,0x33,0xd5] + msr SPMEVCNTR3_EL0, x1 +// CHECK: msr SPMEVCNTR3_EL0, x1 // encoding: [0x61,0xe0,0x13,0xd5] + mrs x3, SPMEVCNTR4_EL0 +// CHECK: mrs x3, SPMEVCNTR4_EL0 // encoding: [0x83,0xe0,0x33,0xd5] + msr SPMEVCNTR4_EL0, x1 +// CHECK: msr SPMEVCNTR4_EL0, x1 // encoding: [0x81,0xe0,0x13,0xd5] + mrs x3, SPMEVCNTR5_EL0 +// CHECK: mrs x3, SPMEVCNTR5_EL0 // encoding: [0xa3,0xe0,0x33,0xd5] + msr SPMEVCNTR5_EL0, x1 +// CHECK: msr SPMEVCNTR5_EL0, x1 // encoding: [0xa1,0xe0,0x13,0xd5] + mrs x3, SPMEVCNTR6_EL0 +// CHECK: mrs x3, SPMEVCNTR6_EL0 // encoding: [0xc3,0xe0,0x33,0xd5] + msr SPMEVCNTR6_EL0, x1 +// CHECK: msr SPMEVCNTR6_EL0, x1 // encoding: [0xc1,0xe0,0x13,0xd5] + mrs x3, SPMEVCNTR7_EL0 +// CHECK: mrs x3, SPMEVCNTR7_EL0 // encoding: [0xe3,0xe0,0x33,0xd5] + msr SPMEVCNTR7_EL0, x1 +// CHECK: msr SPMEVCNTR7_EL0, x1 // encoding: [0xe1,0xe0,0x13,0xd5] + mrs x3, SPMEVCNTR8_EL0 +// CHECK: mrs x3, SPMEVCNTR8_EL0 // encoding: [0x03,0xe1,0x33,0xd5] + msr SPMEVCNTR8_EL0, x1 +// CHECK: msr SPMEVCNTR8_EL0, x1 // encoding: [0x01,0xe1,0x13,0xd5] + mrs x3, SPMEVCNTR9_EL0 +// CHECK: mrs x3, SPMEVCNTR9_EL0 // encoding: [0x23,0xe1,0x33,0xd5] + msr SPMEVCNTR9_EL0, x1 +// CHECK: msr SPMEVCNTR9_EL0, x1 // encoding: [0x21,0xe1,0x13,0xd5] + mrs x3, SPMEVCNTR10_EL0 +// CHECK: mrs x3, SPMEVCNTR10_EL0 // encoding: [0x43,0xe1,0x33,0xd5] + msr SPMEVCNTR10_EL0, x1 +// CHECK: msr SPMEVCNTR10_EL0, x1 // encoding: [0x41,0xe1,0x13,0xd5] + mrs x3, SPMEVCNTR11_EL0 +// CHECK: mrs x3, SPMEVCNTR11_EL0 // encoding: [0x63,0xe1,0x33,0xd5] + msr SPMEVCNTR11_EL0, x1 +// CHECK: msr SPMEVCNTR11_EL0, x1 // encoding: [0x61,0xe1,0x13,0xd5] + mrs x3, SPMEVCNTR12_EL0 +// CHECK: mrs x3, SPMEVCNTR12_EL0 // encoding: [0x83,0xe1,0x33,0xd5] + msr SPMEVCNTR12_EL0, x1 +// CHECK: msr SPMEVCNTR12_EL0, x1 // encoding: [0x81,0xe1,0x13,0xd5] + mrs x3, SPMEVCNTR13_EL0 +// CHECK: mrs x3, SPMEVCNTR13_EL0 // encoding: [0xa3,0xe1,0x33,0xd5] + msr SPMEVCNTR13_EL0, x1 +// CHECK: msr SPMEVCNTR13_EL0, x1 // encoding: [0xa1,0xe1,0x13,0xd5] + mrs x3, SPMEVCNTR14_EL0 +// CHECK: mrs x3, SPMEVCNTR14_EL0 // encoding: [0xc3,0xe1,0x33,0xd5] + msr SPMEVCNTR14_EL0, x1 +// CHECK: msr SPMEVCNTR14_EL0, x1 // encoding: [0xc1,0xe1,0x13,0xd5] + mrs x3, SPMEVCNTR15_EL0 +// CHECK: mrs x3, SPMEVCNTR15_EL0 // encoding: [0xe3,0xe1,0x33,0xd5] + msr SPMEVCNTR15_EL0, x1 +// CHECK: msr SPMEVCNTR15_EL0, x1 // encoding: [0xe1,0xe1,0x13,0xd5] + + mrs x3, SPMEVFILT2R0_EL0 +// CHECK: mrs x3, SPMEVFILT2R0_EL0 // encoding: [0x03,0xe6,0x33,0xd5] + msr SPMEVFILT2R0_EL0, x1 +// CHECK: msr SPMEVFILT2R0_EL0, x1 // encoding: [0x01,0xe6,0x13,0xd5] + mrs x3, SPMEVFILT2R1_EL0 +// CHECK: mrs x3, SPMEVFILT2R1_EL0 // encoding: [0x23,0xe6,0x33,0xd5] + msr SPMEVFILT2R1_EL0, x1 +// CHECK: msr SPMEVFILT2R1_EL0, x1 // encoding: [0x21,0xe6,0x13,0xd5] + mrs x3, SPMEVFILT2R2_EL0 +// CHECK: mrs x3, SPMEVFILT2R2_EL0 // encoding: [0x43,0xe6,0x33,0xd5] + msr SPMEVFILT2R2_EL0, x1 +// CHECK: msr SPMEVFILT2R2_EL0, x1 // encoding: [0x41,0xe6,0x13,0xd5] + mrs x3, SPMEVFILT2R3_EL0 +// CHECK: mrs x3, SPMEVFILT2R3_EL0 // encoding: [0x63,0xe6,0x33,0xd5] + msr SPMEVFILT2R3_EL0, x1 +// CHECK: msr SPMEVFILT2R3_EL0, x1 // encoding: [0x61,0xe6,0x13,0xd5] + mrs x3, SPMEVFILT2R4_EL0 +// CHECK: mrs x3, SPMEVFILT2R4_EL0 // encoding: [0x83,0xe6,0x33,0xd5] + msr SPMEVFILT2R4_EL0, x1 +// CHECK: msr SPMEVFILT2R4_EL0, x1 // encoding: [0x81,0xe6,0x13,0xd5] + mrs x3, SPMEVFILT2R5_EL0 +// CHECK: mrs x3, SPMEVFILT2R5_EL0 // encoding: [0xa3,0xe6,0x33,0xd5] + msr SPMEVFILT2R5_EL0, x1 +// CHECK: msr SPMEVFILT2R5_EL0, x1 // encoding: [0xa1,0xe6,0x13,0xd5] + mrs x3, SPMEVFILT2R6_EL0 +// CHECK: mrs x3, SPMEVFILT2R6_EL0 // encoding: [0xc3,0xe6,0x33,0xd5] + msr SPMEVFILT2R6_EL0, x1 +// CHECK: msr SPMEVFILT2R6_EL0, x1 // encoding: [0xc1,0xe6,0x13,0xd5] + mrs x3, SPMEVFILT2R7_EL0 +// CHECK: mrs x3, SPMEVFILT2R7_EL0 // encoding: [0xe3,0xe6,0x33,0xd5] + msr SPMEVFILT2R7_EL0, x1 +// CHECK: msr SPMEVFILT2R7_EL0, x1 // encoding: [0xe1,0xe6,0x13,0xd5] + mrs x3, SPMEVFILT2R8_EL0 +// CHECK: mrs x3, SPMEVFILT2R8_EL0 // encoding: [0x03,0xe7,0x33,0xd5] + msr SPMEVFILT2R8_EL0, x1 +// CHECK: msr SPMEVFILT2R8_EL0, x1 // encoding: [0x01,0xe7,0x13,0xd5] + mrs x3, SPMEVFILT2R9_EL0 +// CHECK: mrs x3, SPMEVFILT2R9_EL0 // encoding: [0x23,0xe7,0x33,0xd5] + msr SPMEVFILT2R9_EL0, x1 +// CHECK: msr SPMEVFILT2R9_EL0, x1 // encoding: [0x21,0xe7,0x13,0xd5] + mrs x3, SPMEVFILT2R10_EL0 +// CHECK: mrs x3, SPMEVFILT2R10_EL0 // encoding: [0x43,0xe7,0x33,0xd5] + msr SPMEVFILT2R10_EL0, x1 +// CHECK: msr SPMEVFILT2R10_EL0, x1 // encoding: [0x41,0xe7,0x13,0xd5] + mrs x3, SPMEVFILT2R11_EL0 +// CHECK: mrs x3, SPMEVFILT2R11_EL0 // encoding: [0x63,0xe7,0x33,0xd5] + msr SPMEVFILT2R11_EL0, x1 +// CHECK: msr SPMEVFILT2R11_EL0, x1 // encoding: [0x61,0xe7,0x13,0xd5] + mrs x3, SPMEVFILT2R12_EL0 +// CHECK: mrs x3, SPMEVFILT2R12_EL0 // encoding: [0x83,0xe7,0x33,0xd5] + msr SPMEVFILT2R12_EL0, x1 +// CHECK: msr SPMEVFILT2R12_EL0, x1 // encoding: [0x81,0xe7,0x13,0xd5] + mrs x3, SPMEVFILT2R13_EL0 +// CHECK: mrs x3, SPMEVFILT2R13_EL0 // encoding: [0xa3,0xe7,0x33,0xd5] + msr SPMEVFILT2R13_EL0, x1 +// CHECK: msr SPMEVFILT2R13_EL0, x1 // encoding: [0xa1,0xe7,0x13,0xd5] + mrs x3, SPMEVFILT2R14_EL0 +// CHECK: mrs x3, SPMEVFILT2R14_EL0 // encoding: [0xc3,0xe7,0x33,0xd5] + msr SPMEVFILT2R14_EL0, x1 +// CHECK: msr SPMEVFILT2R14_EL0, x1 // encoding: [0xc1,0xe7,0x13,0xd5] + mrs x3, SPMEVFILT2R15_EL0 +// CHECK: mrs x3, SPMEVFILT2R15_EL0 // encoding: [0xe3,0xe7,0x33,0xd5] + msr SPMEVFILT2R15_EL0, x1 +// CHECK: msr SPMEVFILT2R15_EL0, x1 // encoding: [0xe1,0xe7,0x13,0xd5] + + mrs x3, SPMEVFILTR0_EL0 +// CHECK: mrs x3, SPMEVFILTR0_EL0 // encoding: [0x03,0xe4,0x33,0xd5] + msr SPMEVFILTR0_EL0, x1 +// CHECK: msr SPMEVFILTR0_EL0, x1 // encoding: [0x01,0xe4,0x13,0xd5] + mrs x3, SPMEVFILTR1_EL0 +// CHECK: mrs x3, SPMEVFILTR1_EL0 // encoding: [0x23,0xe4,0x33,0xd5] + msr SPMEVFILTR1_EL0, x1 +// CHECK: msr SPMEVFILTR1_EL0, x1 // encoding: [0x21,0xe4,0x13,0xd5] + mrs x3, SPMEVFILTR2_EL0 +// CHECK: mrs x3, SPMEVFILTR2_EL0 // encoding: [0x43,0xe4,0x33,0xd5] + msr SPMEVFILTR2_EL0, x1 +// CHECK: msr SPMEVFILTR2_EL0, x1 // encoding: [0x41,0xe4,0x13,0xd5] + mrs x3, SPMEVFILTR3_EL0 +// CHECK: mrs x3, SPMEVFILTR3_EL0 // encoding: [0x63,0xe4,0x33,0xd5] + msr SPMEVFILTR3_EL0, x1 +// CHECK: msr SPMEVFILTR3_EL0, x1 // encoding: [0x61,0xe4,0x13,0xd5] + mrs x3, SPMEVFILTR4_EL0 +// CHECK: mrs x3, SPMEVFILTR4_EL0 // encoding: [0x83,0xe4,0x33,0xd5] + msr SPMEVFILTR4_EL0, x1 +// CHECK: msr SPMEVFILTR4_EL0, x1 // encoding: [0x81,0xe4,0x13,0xd5] + mrs x3, SPMEVFILTR5_EL0 +// CHECK: mrs x3, SPMEVFILTR5_EL0 // encoding: [0xa3,0xe4,0x33,0xd5] + msr SPMEVFILTR5_EL0, x1 +// CHECK: msr SPMEVFILTR5_EL0, x1 // encoding: [0xa1,0xe4,0x13,0xd5] + mrs x3, SPMEVFILTR6_EL0 +// CHECK: mrs x3, SPMEVFILTR6_EL0 // encoding: [0xc3,0xe4,0x33,0xd5] + msr SPMEVFILTR6_EL0, x1 +// CHECK: msr SPMEVFILTR6_EL0, x1 // encoding: [0xc1,0xe4,0x13,0xd5] + mrs x3, SPMEVFILTR7_EL0 +// CHECK: mrs x3, SPMEVFILTR7_EL0 // encoding: [0xe3,0xe4,0x33,0xd5] + msr SPMEVFILTR7_EL0, x1 +// CHECK: msr SPMEVFILTR7_EL0, x1 // encoding: [0xe1,0xe4,0x13,0xd5] + mrs x3, SPMEVFILTR8_EL0 +// CHECK: mrs x3, SPMEVFILTR8_EL0 // encoding: [0x03,0xe5,0x33,0xd5] + msr SPMEVFILTR8_EL0, x1 +// CHECK: msr SPMEVFILTR8_EL0, x1 // encoding: [0x01,0xe5,0x13,0xd5] + mrs x3, SPMEVFILTR9_EL0 +// CHECK: mrs x3, SPMEVFILTR9_EL0 // encoding: [0x23,0xe5,0x33,0xd5] + msr SPMEVFILTR9_EL0, x1 +// CHECK: msr SPMEVFILTR9_EL0, x1 // encoding: [0x21,0xe5,0x13,0xd5] + mrs x3, SPMEVFILTR10_EL0 +// CHECK: mrs x3, SPMEVFILTR10_EL0 // encoding: [0x43,0xe5,0x33,0xd5] + msr SPMEVFILTR10_EL0, x1 +// CHECK: msr SPMEVFILTR10_EL0, x1 // encoding: [0x41,0xe5,0x13,0xd5] + mrs x3, SPMEVFILTR11_EL0 +// CHECK: mrs x3, SPMEVFILTR11_EL0 // encoding: [0x63,0xe5,0x33,0xd5] + msr SPMEVFILTR11_EL0, x1 +// CHECK: msr SPMEVFILTR11_EL0, x1 // encoding: [0x61,0xe5,0x13,0xd5] + mrs x3, SPMEVFILTR12_EL0 +// CHECK: mrs x3, SPMEVFILTR12_EL0 // encoding: [0x83,0xe5,0x33,0xd5] + msr SPMEVFILTR12_EL0, x1 +// CHECK: msr SPMEVFILTR12_EL0, x1 // encoding: [0x81,0xe5,0x13,0xd5] + mrs x3, SPMEVFILTR13_EL0 +// CHECK: mrs x3, SPMEVFILTR13_EL0 // encoding: [0xa3,0xe5,0x33,0xd5] + msr SPMEVFILTR13_EL0, x1 +// CHECK: msr SPMEVFILTR13_EL0, x1 // encoding: [0xa1,0xe5,0x13,0xd5] + mrs x3, SPMEVFILTR14_EL0 +// CHECK: mrs x3, SPMEVFILTR14_EL0 // encoding: [0xc3,0xe5,0x33,0xd5] + msr SPMEVFILTR14_EL0, x1 +// CHECK: msr SPMEVFILTR14_EL0, x1 // encoding: [0xc1,0xe5,0x13,0xd5] + mrs x3, SPMEVFILTR15_EL0 +// CHECK: mrs x3, SPMEVFILTR15_EL0 // encoding: [0xe3,0xe5,0x33,0xd5] + msr SPMEVFILTR15_EL0, x1 +// CHECK: msr SPMEVFILTR15_EL0, x1 // encoding: [0xe1,0xe5,0x13,0xd5] + + mrs x3, SPMEVTYPER0_EL0 +// CHECK: mrs x3, SPMEVTYPER0_EL0 // encoding: [0x03,0xe2,0x33,0xd5] + msr SPMEVTYPER0_EL0, x1 +// CHECK: msr SPMEVTYPER0_EL0, x1 // encoding: [0x01,0xe2,0x13,0xd5] + mrs x3, SPMEVTYPER1_EL0 +// CHECK: mrs x3, SPMEVTYPER1_EL0 // encoding: [0x23,0xe2,0x33,0xd5] + msr SPMEVTYPER1_EL0, x1 +// CHECK: msr SPMEVTYPER1_EL0, x1 // encoding: [0x21,0xe2,0x13,0xd5] + mrs x3, SPMEVTYPER2_EL0 +// CHECK: mrs x3, SPMEVTYPER2_EL0 // encoding: [0x43,0xe2,0x33,0xd5] + msr SPMEVTYPER2_EL0, x1 +// CHECK: msr SPMEVTYPER2_EL0, x1 // encoding: [0x41,0xe2,0x13,0xd5] + mrs x3, SPMEVTYPER3_EL0 +// CHECK: mrs x3, SPMEVTYPER3_EL0 // encoding: [0x63,0xe2,0x33,0xd5] + msr SPMEVTYPER3_EL0, x1 +// CHECK: msr SPMEVTYPER3_EL0, x1 // encoding: [0x61,0xe2,0x13,0xd5] + mrs x3, SPMEVTYPER4_EL0 +// CHECK: mrs x3, SPMEVTYPER4_EL0 // encoding: [0x83,0xe2,0x33,0xd5] + msr SPMEVTYPER4_EL0, x1 +// CHECK: msr SPMEVTYPER4_EL0, x1 // encoding: [0x81,0xe2,0x13,0xd5] + mrs x3, SPMEVTYPER5_EL0 +// CHECK: mrs x3, SPMEVTYPER5_EL0 // encoding: [0xa3,0xe2,0x33,0xd5] + msr SPMEVTYPER5_EL0, x1 +// CHECK: msr SPMEVTYPER5_EL0, x1 // encoding: [0xa1,0xe2,0x13,0xd5] + mrs x3, SPMEVTYPER6_EL0 +// CHECK: mrs x3, SPMEVTYPER6_EL0 // encoding: [0xc3,0xe2,0x33,0xd5] + msr SPMEVTYPER6_EL0, x1 +// CHECK: msr SPMEVTYPER6_EL0, x1 // encoding: [0xc1,0xe2,0x13,0xd5] + mrs x3, SPMEVTYPER7_EL0 +// CHECK: mrs x3, SPMEVTYPER7_EL0 // encoding: [0xe3,0xe2,0x33,0xd5] + msr SPMEVTYPER7_EL0, x1 +// CHECK: msr SPMEVTYPER7_EL0, x1 // encoding: [0xe1,0xe2,0x13,0xd5] + mrs x3, SPMEVTYPER8_EL0 +// CHECK: mrs x3, SPMEVTYPER8_EL0 // encoding: [0x03,0xe3,0x33,0xd5] + msr SPMEVTYPER8_EL0, x1 +// CHECK: msr SPMEVTYPER8_EL0, x1 // encoding: [0x01,0xe3,0x13,0xd5] + mrs x3, SPMEVTYPER9_EL0 +// CHECK: mrs x3, SPMEVTYPER9_EL0 // encoding: [0x23,0xe3,0x33,0xd5] + msr SPMEVTYPER9_EL0, x1 +// CHECK: msr SPMEVTYPER9_EL0, x1 // encoding: [0x21,0xe3,0x13,0xd5] + mrs x3, SPMEVTYPER10_EL0 +// CHECK: mrs x3, SPMEVTYPER10_EL0 // encoding: [0x43,0xe3,0x33,0xd5] + msr SPMEVTYPER10_EL0, x1 +// CHECK: msr SPMEVTYPER10_EL0, x1 // encoding: [0x41,0xe3,0x13,0xd5] + mrs x3, SPMEVTYPER11_EL0 +// CHECK: mrs x3, SPMEVTYPER11_EL0 // encoding: [0x63,0xe3,0x33,0xd5] + msr SPMEVTYPER11_EL0, x1 +// CHECK: msr SPMEVTYPER11_EL0, x1 // encoding: [0x61,0xe3,0x13,0xd5] + mrs x3, SPMEVTYPER12_EL0 +// CHECK: mrs x3, SPMEVTYPER12_EL0 // encoding: [0x83,0xe3,0x33,0xd5] + msr SPMEVTYPER12_EL0, x1 +// CHECK: msr SPMEVTYPER12_EL0, x1 // encoding: [0x81,0xe3,0x13,0xd5] + mrs x3, SPMEVTYPER13_EL0 +// CHECK: mrs x3, SPMEVTYPER13_EL0 // encoding: [0xa3,0xe3,0x33,0xd5] + msr SPMEVTYPER13_EL0, x1 +// CHECK: msr SPMEVTYPER13_EL0, x1 // encoding: [0xa1,0xe3,0x13,0xd5] + mrs x3, SPMEVTYPER14_EL0 +// CHECK: mrs x3, SPMEVTYPER14_EL0 // encoding: [0xc3,0xe3,0x33,0xd5] + msr SPMEVTYPER14_EL0, x1 +// CHECK: msr SPMEVTYPER14_EL0, x1 // encoding: [0xc1,0xe3,0x13,0xd5] + mrs x3, SPMEVTYPER15_EL0 +// CHECK: mrs x3, SPMEVTYPER15_EL0 // encoding: [0xe3,0xe3,0x33,0xd5] + msr SPMEVTYPER15_EL0, x1 +// CHECK: msr SPMEVTYPER15_EL0, x1 // encoding: [0xe1,0xe3,0x13,0xd5] + + mrs x3, SPMIIDR_EL1 +// CHECK: mrs x3, SPMIIDR_EL1 // encoding: [0x83,0x9d,0x30,0xd5] + mrs x3, SPMINTENCLR_EL1 +// CHECK: mrs x3, SPMINTENCLR_EL1 // encoding: [0x43,0x9e,0x30,0xd5] + msr SPMINTENCLR_EL1, x1 +// CHECK: msr SPMINTENCLR_EL1, x1 // encoding: [0x41,0x9e,0x10,0xd5] + mrs x3, SPMINTENSET_EL1 +// CHECK: mrs x3, SPMINTENSET_EL1 // encoding: [0x23,0x9e,0x30,0xd5] + msr SPMINTENSET_EL1, x1 +// CHECK: msr SPMINTENSET_EL1, x1 // encoding: [0x21,0x9e,0x10,0xd5] + mrs x3, SPMOVSCLR_EL0 +// CHECK: mrs x3, SPMOVSCLR_EL0 // encoding: [0x63,0x9c,0x33,0xd5] + msr SPMOVSCLR_EL0, x1 +// CHECK: msr SPMOVSCLR_EL0, x1 // encoding: [0x61,0x9c,0x13,0xd5] + mrs x3, SPMOVSSET_EL0 +// CHECK: mrs x3, SPMOVSSET_EL0 // encoding: [0x63,0x9e,0x33,0xd5] + msr SPMOVSSET_EL0, x1 +// CHECK: msr SPMOVSSET_EL0, x1 // encoding: [0x61,0x9e,0x13,0xd5] + mrs x3, SPMSELR_EL0 +// CHECK: mrs x3, SPMSELR_EL0 // encoding: [0xa3,0x9c,0x33,0xd5] + msr SPMSELR_EL0, x1 +// CHECK: msr SPMSELR_EL0, x1 // encoding: [0xa1,0x9c,0x13,0xd5] + mrs x3, SPMCGCR0_EL1 +// CHECK: mrs x3, SPMCGCR0_EL1 // encoding: [0x03,0x9d,0x30,0xd5] + mrs x3, SPMCGCR1_EL1 +// CHECK: mrs x3, SPMCGCR1_EL1 // encoding: [0x23,0x9d,0x30,0xd5] + mrs x3, SPMCFGR_EL1 +// CHECK: mrs x3, SPMCFGR_EL1 // encoding: [0xe3,0x9d,0x30,0xd5] + mrs x3, SPMROOTCR_EL3 +// CHECK: mrs x3, SPMROOTCR_EL3 // encoding: [0xe3,0x9e,0x36,0xd5] + msr SPMROOTCR_EL3, x3 +// CHECK: msr SPMROOTCR_EL3, x3 // encoding: [0xe3,0x9e,0x16,0xd5] + mrs x3, SPMSCR_EL1 +// CHECK: mrs x3, SPMSCR_EL1 // encoding: [0xe3,0x9e,0x37,0xd5] + msr SPMSCR_EL1, x3 +// CHECK: msr SPMSCR_EL1, x3 // encoding: [0xe3,0x9e,0x17,0xd5] + +// FEAT_ITE + mrs x3, TRCITEEDCR +// CHECK: mrs x3, TRCITEEDCR // encoding: [0x23,0x02,0x31,0xd5] +// ERROR-NO-ITE: [[@LINE-2]]:21: error: expected readable system register + msr TRCITEEDCR, x3 +// CHECK: msr TRCITEEDCR, x3 // encoding: [0x23,0x02,0x11,0xd5] +// ERROR-NO-ITE: [[@LINE-2]]:17: error: expected writable system register + mrs x3, TRCITECR_EL1 +// CHECK: mrs x3, TRCITECR_EL1 // encoding: [0x63,0x12,0x38,0xd5] +// ERROR-NO-ITE: [[@LINE-2]]:21: error: expected readable system register + msr TRCITECR_EL1, x1 +// CHECK: msr TRCITECR_EL1, x1 // encoding: [0x61,0x12,0x18,0xd5] +// ERROR-NO-ITE: [[@LINE-2]]:17: error: expected writable system register or pstate + mrs x3, TRCITECR_EL12 +// CHECK: mrs x3, TRCITECR_EL12 // encoding: [0x63,0x12,0x3d,0xd5] +// ERROR-NO-ITE: [[@LINE-2]]:21: error: expected readable system register + msr TRCITECR_EL12, x1 +// CHECK: msr TRCITECR_EL12, x1 // encoding: [0x61,0x12,0x1d,0xd5] +// ERROR-NO-ITE: [[@LINE-2]]:17: error: expected writable system register or pstate + mrs x3, TRCITECR_EL2 +// CHECK: mrs x3, TRCITECR_EL2 // encoding: [0x63,0x12,0x3c,0xd5] +// ERROR-NO-ITE: [[@LINE-2]]:21: error: expected readable system register + msr TRCITECR_EL2, x1 +// CHECK: msr TRCITECR_EL2, x1 // encoding: [0x61,0x12,0x1c,0xd5] +// ERROR-NO-ITE: [[@LINE-2]]:17: error: expected writable system register or pstate + trcit x1 +// CHECK: trcit x1 // encoding: [0xe1,0x72,0x0b,0xd5] +// ERROR-NO-ITE: [[@LINE-2]]:13: error: instruction requires: ite + +// FEAT_SPE_FDS + mrs x3, PMSDSFR_EL1 +// CHECK: mrs x3, PMSDSFR_EL1 // encoding: [0x83,0x9a,0x38,0xd5] + msr PMSDSFR_EL1, x3 +// CHECK: msr PMSDSFR_EL1, x3 // encoding: [0x83,0x9a,0x18,0xd5] diff --git a/llvm/test/MC/AArch64/armv8.9a-lrcpc3.s b/llvm/test/MC/AArch64/armv8.9a-lrcpc3.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/armv8.9a-lrcpc3.s @@ -0,0 +1,143 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+rcpc3 < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.9a -mattr=+rcpc3 < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v9.4a -mattr=+rcpc3 < %s | FileCheck %s + +// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s + + stilp w24, w0, [x16, #-8]! +// CHECK: stilp w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stilp w24, w0, [x16, -8]! +// CHECK: stilp w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stilp x25, x1, [x17, -16]! +// CHECK: stilp x25, x1, [x17, #-16]! // encoding: [0x39,0x0a,0x01,0xd9] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stilp x25, x1, [x17, #-16]! +// CHECK: stilp x25, x1, [x17, #-16]! // encoding: [0x39,0x0a,0x01,0xd9] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stilp w26, w2, [x18] +// CHECK: stilp w26, w2, [x18] // encoding: [0x5a,0x1a,0x02,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stilp w26, w2, [x18, #0] +// CHECK: stilp w26, w2, [x18] // encoding: [0x5a,0x1a,0x02,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stilp x27, x3, [sp] +// CHECK: stilp x27, x3, [sp] // encoding: [0xfb,0x1b,0x03,0xd9] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stilp x27, x3, [sp, 0] +// CHECK: stilp x27, x3, [sp] // encoding: [0xfb,0x1b,0x03,0xd9] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldiapp w28, w4, [x20], #8 +// CHECK: ldiapp w28, w4, [x20], #8 // encoding: [0x9c,0x0a,0x44,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldiapp w28, w4, [x20, #0], #8 +// CHECK: ldiapp w28, w4, [x20], #8 // encoding: [0x9c,0x0a,0x44,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldiapp w28, w4, [x20], 8 +// CHECK: ldiapp w28, w4, [x20], #8 // encoding: [0x9c,0x0a,0x44,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldiapp w28, w4, [x20, 0], 8 +// CHECK: ldiapp w28, w4, [x20], #8 // encoding: [0x9c,0x0a,0x44,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldiapp x29, x5, [x21], #16 +// CHECK: ldiapp x29, x5, [x21], #16 // encoding: [0xbd,0x0a,0x45,0xd9] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldiapp x29, x5, [x21], 16 +// CHECK: ldiapp x29, x5, [x21], #16 // encoding: [0xbd,0x0a,0x45,0xd9] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldiapp w30, w6, [sp] +// CHECK: ldiapp w30, w6, [sp] // encoding: [0xfe,0x1b,0x46,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldiapp w30, w6, [sp, #0] +// CHECK: ldiapp w30, w6, [sp] // encoding: [0xfe,0x1b,0x46,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldiapp xzr, x7, [x23] +// CHECK: ldiapp xzr, x7, [x23] // encoding: [0xff,0x1a,0x47,0xd9] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldiapp xzr, x7, [x23, 0] +// CHECK: ldiapp xzr, x7, [x23] // encoding: [0xff,0x1a,0x47,0xd9] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + + stlr w3, [x15, #-4]! +// CHECK: stlr w3, [x15, #-4]! // encoding: [0xe3,0x09,0x80,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stlr w3, [x15, -4]! +// CHECK: stlr w3, [x15, #-4]! // encoding: [0xe3,0x09,0x80,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stlr x3, [x15, #-8]! +// CHECK: stlr x3, [x15, #-8]! // encoding: [0xe3,0x09,0x80,0xd9] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stlr x3, [sp, -8]! +// CHECK: stlr x3, [sp, #-8]! // encoding: [0xe3,0x0b,0x80,0xd9] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldapr w3, [sp], #4 +// CHECK: ldapr w3, [sp], #4 // encoding: [0xe3,0x0b,0xc0,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldapr w3, [x15], 4 +// CHECK: ldapr w3, [x15], #4 // encoding: [0xe3,0x09,0xc0,0x99] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldapr x3, [x15], #8 +// CHECK: ldapr x3, [x15], #8 // encoding: [0xe3,0x09,0xc0,0xd9] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldapr x3, [x15], 8 +// CHECK: ldapr x3, [x15], #8 // encoding: [0xe3,0x09,0xc0,0xd9] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + + stlur b3, [x15, #-1] +// CHECK: stlur b3, [x15, #-1] // encoding: [0xe3,0xf9,0x1f,0x1d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stlur h3, [x15, #2] +// CHECK: stlur h3, [x15, #2] // encoding: [0xe3,0x29,0x00,0x5d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stlur s3, [x15, #-3] +// CHECK: stlur s3, [x15, #-3] // encoding: [0xe3,0xd9,0x1f,0x9d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stlur d3, [sp, #4] +// CHECK: stlur d3, [sp, #4] // encoding: [0xe3,0x4b,0x00,0xdd] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stlur q3, [x15, #-5] +// CHECK: stlur q3, [x15, #-5] // encoding: [0xe3,0xb9,0x9f,0x1d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldapur b3, [x15, #6] +// CHECK: ldapur b3, [x15, #6] // encoding: [0xe3,0x69,0x40,0x1d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldapur h3, [x15, #-7] +// CHECK: ldapur h3, [x15, #-7] // encoding: [0xe3,0x99,0x5f,0x5d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldapur s3, [x15, #8] +// CHECK: ldapur s3, [x15, #8] // encoding: [0xe3,0x89,0x40,0x9d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldapur d3, [x15, #-9] +// CHECK: ldapur d3, [x15, #-9] // encoding: [0xe3,0x79,0x5f,0xdd] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldapur q3, [sp, #10] +// CHECK: ldapur q3, [sp, #10] // encoding: [0xe3,0xab,0xc0,0x1d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + + stl1 { v3.d }[0], [x15] +// CHECK: stl1 { v3.d }[0], [x15] // encoding: [0xe3,0x85,0x01,0x0d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stl1 { v3.d }[0], [x15, #0] +// CHECK: stl1 { v3.d }[0], [x15] // encoding: [0xe3,0x85,0x01,0x0d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stl1 { v3.d }[1], [sp] +// CHECK: stl1 { v3.d }[1], [sp] // encoding: [0xe3,0x87,0x01,0x4d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + stl1 { v3.d }[1], [sp, 0] +// CHECK: stl1 { v3.d }[1], [sp] // encoding: [0xe3,0x87,0x01,0x4d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldap1 { v3.d }[0], [sp] +// CHECK: ldap1 { v3.d }[0], [sp] // encoding: [0xe3,0x87,0x41,0x0d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldap1 { v3.d }[0], [sp, #0] +// CHECK: ldap1 { v3.d }[0], [sp] // encoding: [0xe3,0x87,0x41,0x0d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldap1 { v3.d }[1], [x15] +// CHECK: ldap1 { v3.d }[1], [x15] // encoding: [0xe3,0x85,0x41,0x4d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 + ldap1 { v3.d }[1], [x15, 0] +// CHECK: ldap1 { v3.d }[1], [x15] // encoding: [0xe3,0x85,0x41,0x4d] +// ERROR-NO-RCPC3: [[@LINE-2]]:16: error: instruction requires: rcpc3 diff --git a/llvm/test/MC/AArch64/basic-a64-diagnostics.s b/llvm/test/MC/AArch64/basic-a64-diagnostics.s --- a/llvm/test/MC/AArch64/basic-a64-diagnostics.s +++ b/llvm/test/MC/AArch64/basic-a64-diagnostics.s @@ -3577,6 +3577,7 @@ msr ID_PFR0_EL1, x12 msr ID_PFR1_EL1, x12 msr ID_DFR0_EL1, x12 + msr ID_DFR1_EL1, x12 msr ID_AFR0_EL1, x12 msr ID_MMFR0_EL1, x12 msr ID_MMFR1_EL1, x12 @@ -3666,6 +3667,9 @@ // CHECK-ERROR-NEXT: msr ID_DFR0_EL1, x12 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: expected writable system register or pstate +// CHECK-ERROR-NEXT: msr ID_DFR1_EL1, x12 +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: msr ID_AFR0_EL1, x12 // CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: error: expected writable system register or pstate diff --git a/llvm/test/MC/AArch64/basic-a64-instructions.s b/llvm/test/MC/AArch64/basic-a64-instructions.s --- a/llvm/test/MC/AArch64/basic-a64-instructions.s +++ b/llvm/test/MC/AArch64/basic-a64-instructions.s @@ -4289,6 +4289,7 @@ mrs x9, ID_PFR0_EL1 mrs x9, ID_PFR1_EL1 mrs x9, ID_DFR0_EL1 + mrs x9, ID_DFR1_EL1 mrs x9, ID_AFR0_EL1 mrs x9, ID_MMFR0_EL1 mrs x9, ID_MMFR1_EL1 @@ -4592,6 +4593,7 @@ // CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}} // encoding: [0x09,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} // encoding: [0x29,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} // encoding: [0x49,0x01,0x38,0xd5] +// CHECK: mrs x9, {{id_dfr1_el1|ID_DFR1_EL1}} // encoding: [0xa9,0x03,0x38,0xd5] // CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} // encoding: [0x69,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} // encoding: [0x89,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} // encoding: [0xa9,0x01,0x38,0xd5] diff --git a/llvm/test/MC/AArch64/coff-debug.ll b/llvm/test/MC/AArch64/coff-debug.ll --- a/llvm/test/MC/AArch64/coff-debug.ll +++ b/llvm/test/MC/AArch64/coff-debug.ll @@ -12,7 +12,7 @@ define i32 @main() #0 !dbg !7 { entry: %retval = alloca i32, align 4 - store i32 0, i32* %retval, align 4 + store i32 0, ptr %retval, align 4 ret i32 1, !dbg !11 } diff --git a/llvm/test/MC/AArch64/elf-globaladdress.ll b/llvm/test/MC/AArch64/elf-globaladdress.ll --- a/llvm/test/MC/AArch64/elf-globaladdress.ll +++ b/llvm/test/MC/AArch64/elf-globaladdress.ll @@ -12,25 +12,25 @@ @var64 = dso_local global i64 0 define dso_local void @loadstore() { - %val8 = load i8, i8* @var8 - store volatile i8 %val8, i8* @var8 + %val8 = load i8, ptr @var8 + store volatile i8 %val8, ptr @var8 - %val16 = load i16, i16* @var16 - store volatile i16 %val16, i16* @var16 + %val16 = load i16, ptr @var16 + store volatile i16 %val16, ptr @var16 - %val32 = load i32, i32* @var32 - store volatile i32 %val32, i32* @var32 + %val32 = load i32, ptr @var32 + store volatile i32 %val32, ptr @var32 - %val64 = load i64, i64* @var64 - store volatile i64 %val64, i64* @var64 + %val64 = load i64, ptr @var64 + store volatile i64 %val64, ptr @var64 ret void } -@globaddr = dso_local global i64* null +@globaddr = dso_local global ptr null define dso_local void @address() { - store i64* @var64, i64** @globaddr + store ptr @var64, ptr @globaddr ret void } diff --git a/llvm/test/MC/AArch64/ir-to-imgrel.ll b/llvm/test/MC/AArch64/ir-to-imgrel.ll --- a/llvm/test/MC/AArch64/ir-to-imgrel.ll +++ b/llvm/test/MC/AArch64/ir-to-imgrel.ll @@ -3,9 +3,9 @@ @__ImageBase = external global i8 ; AARCH64: .xword "?x@@3HA"@IMGREL -@"\01?x@@3HA" = global i64 sub nsw (i64 ptrtoint (i64* @"\01?x@@3HA" to i64), i64 ptrtoint (i8* @__ImageBase to i64)), align 8 +@"\01?x@@3HA" = global i64 sub nsw (i64 ptrtoint (ptr @"\01?x@@3HA" to i64), i64 ptrtoint (ptr @__ImageBase to i64)), align 8 declare void @f() ; AARCH64: .xword f@IMGREL -@fp = global i64 sub nsw (i64 ptrtoint (void ()* @f to i64), i64 ptrtoint (i8* @__ImageBase to i64)), align 8 +@fp = global i64 sub nsw (i64 ptrtoint (ptr @f to i64), i64 ptrtoint (ptr @__ImageBase to i64)), align 8 diff --git a/llvm/test/MC/AMDGPU/ds-err.s b/llvm/test/MC/AMDGPU/ds-err.s --- a/llvm/test/MC/AMDGPU/ds-err.s +++ b/llvm/test/MC/AMDGPU/ds-err.s @@ -10,7 +10,7 @@ ds_add_u32 v2, v4 offset:0x10000 // offset0 twice -// CHECK: error: invalid operand for instruction +// CHECK: error: not a valid operand. ds_write2_b32 v2, v4, v6 offset0:4 offset0:8 // offset1 twice diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s --- a/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s +++ b/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s @@ -10342,6 +10342,9 @@ v_fmaak_f32 v5, v1, v2, 0xa1b1c1d1 // GFX10: encoding: [0x01,0x05,0x0a,0x5a,0xd1,0xc1,0xb1,0xa1] +v_fmaak_f32 v5, v1, v2, -1 +// GFX10: encoding: [0x01,0x05,0x0a,0x5a,0xff,0xff,0xff,0xff] + v_cvt_pkrtz_f16_f32_e32 v5, v1, v2 // GFX10: encoding: [0x01,0x05,0x0a,0x5e] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_exp.s b/llvm/test/MC/AMDGPU/gfx11_asm_exp.s --- a/llvm/test/MC/AMDGPU/gfx11_asm_exp.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_exp.s @@ -11,9 +11,9 @@ // GFX11: exp dual_src_blend1 v2, v3, off, off ; encoding: [0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] exp mrtz v4, v3, v2, v1 row_en -// PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // GFX11: exp mrtz v4, v3, v2, v1 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01] exp mrtz v4, v3, off, off done row_en -// PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// PREGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // GFX11: exp mrtz v4, v3, off, off done row_en ; encoding: [0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_mimg_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_mimg_err.s --- a/llvm/test/MC/AMDGPU/gfx11_asm_mimg_err.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_mimg_err.s @@ -1,58 +1,58 @@ // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck --check-prefixes=NOGFX11 --implicit-check-not=error: %s image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1, v0, v20, v21], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1, v5], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_CUBE -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_d v[64:66], [v32, v16, v8, v4, v0, v20, v21], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D_ARRAY -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_d_cl v[64:66], [v32, v16, v8, v4, v2, v1, v0, v20, v21, v48], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_c_d v[64:66], [v32, v16, v0, v2, v1, v4, v8, v12, v16, v17], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_c_d_cl v[64:66], [v32, v16, v0, v2, v1, v4, v8, v12, v16, v17, v18], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_c_b_cl v[64:66], [v32, v16, v0, v2, v1, v5], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_d_o v[64:66], [v32, v16, v0, v2, v4, v5, v6, v7, v8, v9], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_d_cl_o v[64:66], [v32, v16, v0, v2, v4, v5, v6, v7, v8, v9, v10], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_b_cl_o v[64:66], [v32, v16, v0, v2, v1, v4], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_c_cl_o v[64:66], [v32, v16, v0, v2, v1, v4], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_c_d_o v[64:66], [v32, v16, v0, v2, v1, v4, v5, v6, v7, v8, v9], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_c_d_cl_o v[64:66], [v32, v16, v0, v2, v1, v4, v5, v6, v7, v8, v9, v10], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_c_l_o v[64:66], [v32, v16, v0, v2, v1, v4], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_c_b_o v[64:66], [v32, v16, v0, v2, v1, v4], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_sample_c_b_cl_o v[64:66], [v32, v16, v0, v2, v1, v4, v5], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_gather4_c_b_cl v[64:67], [v32, v0, v4, v5, v6, v7], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_3D -// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode +// NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. image_gather4_cl_o v[64:67], [v32, v0, v4, v5, v6], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_3D // NOGFX11: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_wmma.s b/llvm/test/MC/AMDGPU/gfx11_asm_wmma.s --- a/llvm/test/MC/AMDGPU/gfx11_asm_wmma.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_wmma.s @@ -40,12 +40,12 @@ // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], v[16:23] op_sel:[0,0,1] -// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction +// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand. v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], v[16:19] op_sel:[0,0,1] -// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction +// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand. v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], v[16:23] neg_lo:[1,0,0] neg_hi:[1,0,0] // W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], v[16:23] neg_lo:[1,0,0] neg_hi:[1,0,0] ; encoding: [0x10,0x41,0x40,0xcc,0x00,0x11,0x42,0x3c] @@ -116,12 +116,12 @@ // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode v_wmma_f32_16x16x16_bf16 v[16:23], v[0:7], v[8:15], v[16:23] op_sel:[0,0,1] -// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction +// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand. v_wmma_f32_16x16x16_bf16 v[16:19], v[0:7], v[8:15], v[16:19] op_sel:[0,0,1] -// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction +// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand. v_wmma_f32_16x16x16_bf16 v[16:23], v[0:7], v[8:15], v[16:23] neg_lo:[1,0,0] neg_hi:[1,0,0] // W32: v_wmma_f32_16x16x16_bf16 v[16:23], v[0:7], v[8:15], v[16:23] neg_lo:[1,0,0] neg_hi:[1,0,0] ; encoding: [0x10,0x41,0x41,0xcc,0x00,0x11,0x42,0x3c] @@ -344,12 +344,12 @@ // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode v_wmma_i32_16x16x16_iu8 v[16:23], v[0:7], v[8:15], v[16:23] op_sel:[0,0,1] -// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction +// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand. v_wmma_i32_16x16x16_iu8 v[16:19], v[0:7], v[8:15], v[16:19] op_sel:[0,0,1] -// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction +// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand. v_wmma_i32_16x16x16_iu8 v[8:15], v[0:3], v[4:7], v[8:15] neg_lo:[1,0,0] neg_hi:[1,0,0] // W32: v_wmma_i32_16x16x16_iu8 v[8:15], v[0:3], v[4:7], v[8:15] neg_lo:[1,0,0] neg_hi:[1,0,0] ; encoding: [0x08,0x41,0x44,0xcc,0x00,0x09,0x22,0x3c] @@ -420,12 +420,12 @@ // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode v_wmma_i32_16x16x16_iu4 v[16:23], v[0:7], v[8:15], v[16:23] op_sel:[0,0,1] -// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction +// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand. v_wmma_i32_16x16x16_iu4 v[16:19], v[0:7], v[8:15], v[16:19] op_sel:[0,0,1] -// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction +// W32-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: not a valid operand. +// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: not a valid operand. v_wmma_i32_16x16x16_iu4 v[4:11], v[0:1], v[2:3], v[4:11] neg_lo:[1,0,0] neg_hi:[1,0,0] // W32: v_wmma_i32_16x16x16_iu4 v[4:11], v[0:1], v[2:3], v[4:11] neg_lo:[1,0,0] neg_hi:[1,0,0] ; encoding: [0x04,0x41,0x45,0xcc,0x00,0x05,0x12,0x3c] diff --git a/llvm/test/MC/AMDGPU/gfx9-asm-err.s b/llvm/test/MC/AMDGPU/gfx9-asm-err.s --- a/llvm/test/MC/AMDGPU/gfx9-asm-err.s +++ b/llvm/test/MC/AMDGPU/gfx9-asm-err.s @@ -31,7 +31,7 @@ // GFX9ERR: error: literal operands are not supported v_cvt_u32_f64 v5, v[0:1] quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf -// GFX9ERR: error: invalid operand for instruction +// GFX9ERR: error: not a valid operand. global_load_lds_dword v[2:3], off // GFX9ERR: error: instruction not supported on this GPU diff --git a/llvm/test/MC/AMDGPU/gfx90a_asm_features.s b/llvm/test/MC/AMDGPU/gfx90a_asm_features.s --- a/llvm/test/MC/AMDGPU/gfx90a_asm_features.s +++ b/llvm/test/MC/AMDGPU/gfx90a_asm_features.s @@ -958,12 +958,12 @@ // GFX90A: global_atomic_add_f32 v0, v[0:1], v2, off glc ; encoding: [0x00,0x80,0x35,0xdd,0x00,0x02,0x7f,0x00] // GFX1010: error: instruction not supported on this GPU -// GFX908: error: operands are not valid for this GPU or mode +// GFX908: error: invalid operand for instruction global_atomic_add_f32 v0, v[0:1], v2, off glc // GFX90A: global_atomic_pk_add_f16 v0, v[0:1], v2, off glc ; encoding: [0x00,0x80,0x39,0xdd,0x00,0x02,0x7f,0x00] // GFX1010: error: instruction not supported on this GPU -// GFX908: error: operands are not valid for this GPU or mode +// GFX908: error: invalid operand for instruction global_atomic_pk_add_f16 v0, v[0:1], v2, off glc // GFX90A: global_atomic_add_f64 v[0:1], v[0:1], v[2:3], off glc ; encoding: [0x00,0x80,0x3d,0xdd,0x00,0x02,0x7f,0x00] @@ -991,7 +991,7 @@ flat_atomic_min_f64 v[0:1], v[0:1], v[2:3] glc // GFX90A: global_atomic_add_f32 v0, v[0:1], v2, off glc ; encoding: [0x00,0x80,0x35,0xdd,0x00,0x02,0x7f,0x00] -// GFX908: error: operands are not valid for this GPU or mode +// GFX908: error: invalid operand for instruction // GFX1010: error: instruction not supported on this GPU global_atomic_add_f32 v0, v[0:1], v2, off glc @@ -1008,7 +1008,7 @@ // GFX1010: error: instruction not supported on this GPU global_atomic_add_f32 v1, v0, v2, s[0:1] glc ; encoding: [0x00,0x80,0x35,0xdd,0x00,0x02,0x00,0x01] -// GFX908: error: operands are not valid for this GPU or mode +// GFX908: error: invalid operand for instruction // GFX1010: error: instruction not supported on this GPU // GFX90A: global_atomic_pk_add_f16 v0, v[0:1], v2, off glc ; encoding: [0x00,0x80,0x39,0xdd,0x00,0x02,0x7f,0x00] global_atomic_pk_add_f16 v0, v[0:1], v2, off glc diff --git a/llvm/test/MC/AMDGPU/gfx90a_err.s b/llvm/test/MC/AMDGPU/gfx90a_err.s --- a/llvm/test/MC/AMDGPU/gfx90a_err.s +++ b/llvm/test/MC/AMDGPU/gfx90a_err.s @@ -181,7 +181,7 @@ // GFX90A: error: invalid register class: data and dst should be all VGPR or AGPR image_load v[0:4], v2, s[0:7] dmask:0xf unorm tfe -// GFX90A: error: operands are not valid for this GPU or mode +// GFX90A: error: invalid operand for instruction image_sample_lz v[0:3], v[0:1], s[4:11], s[16:19] dmask:0xf // GFX90A: error: instruction not supported on this GPU diff --git a/llvm/test/MC/AMDGPU/gfx940_err.s b/llvm/test/MC/AMDGPU/gfx940_err.s --- a/llvm/test/MC/AMDGPU/gfx940_err.s +++ b/llvm/test/MC/AMDGPU/gfx940_err.s @@ -88,13 +88,13 @@ // GFX940: error: invalid operand for instruction v_cvt_sr_fp8_f32 v1, v2, v3 mul:2 -// GFX940: error: invalid operand for instruction +// GFX940: error: not a valid operand. v_cvt_pk_fp8_f32 v1, v2, v3 clamp // GFX940: error: invalid operand for instruction v_cvt_pk_fp8_f32 v1, v2, v3 mul:2 -// GFX940: error: invalid operand for instruction +// GFX940: error: not a valid operand. s_getreg_b32 s1, hwreg(HW_REG_FLAT_SCR_LO) // GFX940: error: specified hardware register is not supported on this GPU @@ -121,7 +121,7 @@ // GFX940: error: instruction not supported on this GPU global_load_dword v[2:3], off lds -// GFX940: error: operands are not valid for this GPU or mode +// GFX940: error: invalid operand for instruction scratch_load_dword v2, off lds -// GFX940: error: operands are not valid for this GPU or mode +// GFX940: error: invalid operand for instruction diff --git a/llvm/test/MC/AMDGPU/mimg-err.s b/llvm/test/MC/AMDGPU/mimg-err.s --- a/llvm/test/MC/AMDGPU/mimg-err.s +++ b/llvm/test/MC/AMDGPU/mimg-err.s @@ -11,7 +11,7 @@ image_load v[4:6], v[237:240], s[28:35] dmask:0x7 tfe // NOGCN: error: image data size does not match dmask and tfe // NOGFX9: error: image data size does not match dmask, d16 and tfe -// NOGFX90A: error: operands are not valid for this GPU or mode +// NOGFX90A: error: invalid operand for instruction image_load v[4:5], v[237:240], s[28:35] dmask:0x7 // NOGCN: error: image data size does not match dmask and tfe @@ -31,7 +31,7 @@ image_load v4, v[237:240], s[28:35] tfe // NOGCN: error: image data size does not match dmask and tfe // NOGFX9: error: image data size does not match dmask, d16 and tfe -// NOGFX90A: error: operands are not valid for this GPU or mode +// NOGFX90A: error: invalid operand for instruction //===----------------------------------------------------------------------===// // Image Sample @@ -40,7 +40,7 @@ image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 tfe // NOGCN: error: image data size does not match dmask and tfe // NOGFX9: error: image data size does not match dmask, d16 and tfe -// NOGFX90A: error: operands are not valid for this GPU or mode +// NOGFX90A: error: invalid operand for instruction image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x3 // NOGCN: error: image data size does not match dmask and tfe @@ -59,7 +59,7 @@ image_atomic_add v252, v2, s[8:15] dmask:0x1 tfe // NOGCN: error: image data size does not match dmask and tfe // NOGFX9: error: image data size does not match dmask and tfe -// NOGFX90A: error: operands are not valid for this GPU or mode +// NOGFX90A: error: invalid operand for instruction image_atomic_add v[6:7], v255, s[8:15] dmask:0x2 // NOGCN: error: image data size does not match dmask and tfe @@ -74,7 +74,7 @@ image_atomic_cmpswap v[4:7], v[192:195], s[28:35] dmask:0xf tfe // NOGCN: error: image data size does not match dmask and tfe // NOGFX9: error: image data size does not match dmask and tfe -// NOGFX90A: error: operands are not valid for this GPU or mode +// NOGFX90A: error: invalid operand for instruction image_atomic_add v252, v2, s[8:15] // NOGCN: error: invalid atomic image dmask @@ -84,12 +84,12 @@ image_atomic_add v[6:7], v255, s[8:15] dmask:0x2 tfe // NOGCN: error: invalid atomic image dmask // NOGFX9: error: invalid atomic image dmask -// NOGFX90A: error: operands are not valid for this GPU or mode +// NOGFX90A: error: invalid operand for instruction image_atomic_cmpswap v[4:7], v[192:195], s[28:35] dmask:0xe tfe // NOGCN: error: invalid atomic image dmask // NOGFX9: error: invalid atomic image dmask -// NOGFX90A: error: operands are not valid for this GPU or mode +// NOGFX90A: error: invalid operand for instruction //===----------------------------------------------------------------------===// // Image Gather diff --git a/llvm/test/MC/AMDGPU/mtbuf.s b/llvm/test/MC/AMDGPU/mtbuf.s --- a/llvm/test/MC/AMDGPU/mtbuf.s +++ b/llvm/test/MC/AMDGPU/mtbuf.s @@ -277,7 +277,7 @@ // Check addr64 tbuffer_store_format_xyzw v[1:4], v[1:2], ttmp[4:7], s0, format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT] addr64 // SICI: tbuffer_store_format_xyzw v[1:4], v[1:2], ttmp[4:7], s0 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT] addr64 ; encoding: [0x00,0x80,0xa7,0xeb,0x01,0x01,0x1d,0x00] -// VI-ERR: error: operands are not valid for this GPU or mode +// VI-ERR: error: invalid operand for instruction //===----------------------------------------------------------------------===// // Tests for symbolic format errors handling diff --git a/llvm/test/MC/AMDGPU/mubuf.s b/llvm/test/MC/AMDGPU/mubuf.s --- a/llvm/test/MC/AMDGPU/mubuf.s +++ b/llvm/test/MC/AMDGPU/mubuf.s @@ -172,35 +172,35 @@ buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 // SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 ; encoding: [0x00,0x80,0x30,0xe0,0x02,0x01,0x01,0x01] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 // SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 ; encoding: [0x04,0x80,0x30,0xe0,0x02,0x01,0x01,0x01] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc // SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0x01,0x01] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc // SICI: buffer_load_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc ; encoding: [0x04,0x80,0x30,0xe0,0x02,0x01,0x41,0x01] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_load_dword v[1:2], v[2:3], s[4:7], s1 addr64 offset:4 tfe // SICI: buffer_load_dword v[1:2], v[2:3], s[4:7], s1 addr64 offset:4 tfe ; encoding: [0x04,0x80,0x30,0xe0,0x02,0x01,0x81,0x01] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_load_dword v[1:2], v[2:3], s[4:7], s1 addr64 glc tfe // SICI: buffer_load_dword v[1:2], v[2:3], s[4:7], s1 addr64 glc tfe ; encoding: [0x00,0xc0,0x30,0xe0,0x02,0x01,0x81,0x01] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_load_dword v[1:2], v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe // SICI: buffer_load_dword v[1:2], v[2:3], s[4:7], s1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xc1,0x01] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_load_dword v[1:2], v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe // SICI: buffer_load_dword v[1:2], v[2:3], ttmp[4:7], ttmp1 addr64 offset:4 glc slc tfe ; encoding: [0x04,0xc0,0x30,0xe0,0x02,0x01,0xdd,0x71] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction //===----------------------------------------------------------------------===// // store - immediate offset only @@ -288,19 +288,19 @@ buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 ; encoding: [0x00,0x80,0x70,0xe0,0x02,0x01,0x01,0x01] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x01,0x01] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 glc ; encoding: [0x04,0xc0,0x70,0xe0,0x02,0x01,0x01,0x01] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc // SICI: buffer_store_dword v1, v[2:3], s[4:7], s1 addr64 offset:4 slc ; encoding: [0x04,0x80,0x70,0xe0,0x02,0x01,0x41,0x01] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction //===----------------------------------------------------------------------===// // Instructions @@ -441,23 +441,23 @@ //===----------------------------------------------------------------------===// buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 // SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 ; encoding: [0x00,0x80,0xf0,0xe0,0x02,0x01,0x02,0xb8] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_atomic_inc v1, v[2:3], s[8:11], s4 addr64 // SICI: buffer_atomic_inc v1, v[2:3], s[8:11], s4 addr64 ; encoding: [0x00,0x80,0xf0,0xe0,0x02,0x01,0x02,0x04] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 slc // SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 slc ; encoding: [0x00,0x80,0xf0,0xe0,0x02,0x01,0x42,0xb8] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 // SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 ; encoding: [0x04,0x80,0xf0,0xe0,0x02,0x01,0x02,0xb8] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 slc // SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 slc ; encoding: [0x04,0x80,0xf0,0xe0,0x02,0x01,0x42,0xb8] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_atomic_inc v1, off, s[8:11], 56 // SICI: buffer_atomic_inc v1, off, s[8:11], 56 ; encoding: [0x00,0x00,0xf0,0xe0,0x00,0x01,0x02,0xb8] @@ -541,23 +541,23 @@ buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 glc // SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 glc ; encoding: [0x00,0xc0,0xf0,0xe0,0x02,0x01,0x02,0xb8] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_atomic_inc v1, v[2:3], s[8:11], s4 addr64 glc // SICI: buffer_atomic_inc v1, v[2:3], s[8:11], s4 addr64 glc ; encoding: [0x00,0xc0,0xf0,0xe0,0x02,0x01,0x02,0x04] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 glc slc // SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 glc slc ; encoding: [0x00,0xc0,0xf0,0xe0,0x02,0x01,0x42,0xb8] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 glc // SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 glc ; encoding: [0x04,0xc0,0xf0,0xe0,0x02,0x01,0x02,0xb8] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 glc slc // SICI: buffer_atomic_inc v1, v[2:3], s[8:11], 56 addr64 offset:4 glc slc ; encoding: [0x04,0xc0,0xf0,0xe0,0x02,0x01,0x42,0xb8] -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: invalid operand for instruction buffer_atomic_inc v1, off, s[8:11], 56 glc // SICI: buffer_atomic_inc v1, off, s[8:11], 56 glc ; encoding: [0x00,0x40,0xf0,0xe0,0x00,0x01,0x02,0xb8] diff --git a/llvm/test/MC/AMDGPU/smem.s b/llvm/test/MC/AMDGPU/smem.s --- a/llvm/test/MC/AMDGPU/smem.s +++ b/llvm/test/MC/AMDGPU/smem.s @@ -671,8 +671,8 @@ // NOVI: error: expected a 20-bit unsigned offset s_load_dword s1, s[2:3], s0 offset:0x1FFFFF -// NOSICI: error: operands are not valid for this GPU or mode -// NOVI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. +// NOVI: error: not a valid operand. // NOGFX9: error: expected a 21-bit signed offset // NOGFX10: error: expected a 21-bit signed offset @@ -682,8 +682,8 @@ // NOVI: error: expected a 20-bit unsigned offset s_buffer_load_dword s10, s[92:95], s0 offset:-1 -// NOSICI: error: operands are not valid for this GPU or mode -// NOVI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. +// NOVI: error: not a valid operand. // NOGFX9: error: expected a 20-bit unsigned offset // NOGFX10: error: expected a 20-bit unsigned offset diff --git a/llvm/test/MC/AMDGPU/vop3-errs.s b/llvm/test/MC/AMDGPU/vop3-errs.s --- a/llvm/test/MC/AMDGPU/vop3-errs.s +++ b/llvm/test/MC/AMDGPU/vop3-errs.s @@ -13,10 +13,11 @@ // GFX67: error: instruction not supported on this GPU v_cmp_eq_f32_e64 vcc, v0, v1 mul:2 -// GCN: error: invalid operand for instruction +// GFX67: error: not a valid operand. +// GFX89: error: not a valid operand. v_cmp_le_f64_e64 vcc, v0, v1 mul:4 -// GCN: error: invalid operand for instruction +// GCN: error: not a valid operand. // // mul @@ -63,7 +64,7 @@ v_interp_p2_f16 v5, v2, attr1.x, v3 mul:2 // GFX67: error: instruction not supported on this GPU -// GFX89: error: invalid operand for instruction +// GFX89: error: not a valid operand. // // v_div_scale_* diff --git a/llvm/test/MC/AMDGPU/vop3-gfx9.s b/llvm/test/MC/AMDGPU/vop3-gfx9.s --- a/llvm/test/MC/AMDGPU/vop3-gfx9.s +++ b/llvm/test/MC/AMDGPU/vop3-gfx9.s @@ -258,17 +258,17 @@ v_fma_f16 v5, v1, v2, v3 op_sel:[1,0,0,0] // GFX9: v_fma_f16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x06,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_fma_f16 v5, v1, v2, v3 op_sel:[0,1,0,0] // GFX9: v_fma_f16 v5, v1, v2, v3 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0x06,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] // GFX9: v_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x06,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_fma_legacy_f16_e64 v5, v1, v2, v3 // GFX9: v_fma_legacy_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04] @@ -319,17 +319,17 @@ v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,0,0,0] // GFX9: v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x07,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,1,0] // GFX9: v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x07,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,0,1] // GFX9: v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x07,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_div_fixup_legacy_f16_e64 v5, 0.5, v2, v3 // GFX9: v_div_fixup_legacy_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04] @@ -383,32 +383,32 @@ v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,0,0] // GFX9: v_mad_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_mad_f16 v5, v1, v2, v3 op_sel:[1,0,0,0] // GFX9: v_mad_f16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x03,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_mad_f16 v5, v1, v2, v3 op_sel:[0,1,0,0] // GFX9: v_mad_f16 v5, v1, v2, v3 op_sel:[0,1,0,0] ; encoding: [0x05,0x10,0x03,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,1,0] // GFX9: v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,1,0] ; encoding: [0x05,0x20,0x03,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,0,1] // GFX9: v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x03,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_mad_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] // GFX9: v_mad_f16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x03,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_mad_f16 v5, v1, v2, v3 clamp // GFX9: v_mad_f16 v5, v1, v2, v3 clamp ; encoding: [0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04] @@ -438,12 +438,12 @@ v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0,1] // GFX9: v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x05,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_mad_i16 v5, v1, v2, v3 op_sel:[1,1,1,1] // GFX9: v_mad_i16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x05,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_mad_legacy_f16_e64 v5, 0.5, v2, v3 // GFX9: v_mad_legacy_f16 v5, 0.5, v2, v3 ; encoding: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04] @@ -524,17 +524,17 @@ v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0] // GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0] ; encoding: [0x05,0x08,0x04,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1] // GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1] ; encoding: [0x05,0x40,0x04,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1] // GFX9: v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x04,0xd2,0x01,0x05,0x0e,0x04] // NOSICI: error: instruction not supported on this GPU -// NOVI: error: operands are not valid for this GPU or mode +// NOVI: error: not a valid operand. v_interp_p2_f16 v5, v2, attr0.x, v3 // GFX9: v_interp_p2_f16 v5, v2, attr0.x, v3 ; encoding: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04] diff --git a/llvm/test/MC/AMDGPU/vop_dpp.s b/llvm/test/MC/AMDGPU/vop_dpp.s --- a/llvm/test/MC/AMDGPU/vop_dpp.s +++ b/llvm/test/MC/AMDGPU/vop_dpp.s @@ -115,19 +115,19 @@ // Check modifiers //===----------------------------------------------------------------------===// -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_add_f32_dpp v0, -v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x19,0xa1] v_add_f32 v0, -v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_add_f32_dpp v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x89,0xa1] v_add_f32 v0, v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_add_f32_dpp v0, -v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x99,0xa1] v_add_f32 v0, -v0, |v0| row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_add_f32_dpp v0, |v0|, -v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x69,0xa1] v_add_f32 v0, |v0|, -v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 @@ -139,15 +139,15 @@ // GCN: v_nop row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x7e,0x00,0x01,0x09,0xa1] v_nop row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cvt_u32_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x0e,0x00,0x7e,0x00,0x01,0x09,0xa1] v_cvt_u32_f32 v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_fract_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x36,0x00,0x7e,0x00,0x01,0x09,0xa1] v_fract_f32 v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_sin_f32_dpp v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x52,0x00,0x7e,0x00,0x01,0x09,0xa1] v_sin_f32 v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 @@ -155,95 +155,95 @@ // VI9: v_mov_b32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x02,0x7e,0x00,0x01,0x09,0xa1] v_mov_b32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cvt_f32_i32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x0a,0x02,0x7e,0x00,0x01,0x09,0xa1] v_cvt_f32_i32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cvt_f32_u32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x0c,0x02,0x7e,0x00,0x01,0x09,0xa1] v_cvt_f32_u32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cvt_i32_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x10,0x02,0x7e,0x00,0x01,0x09,0xa1] v_cvt_i32_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cvt_f16_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x14,0x02,0x7e,0x00,0x01,0x09,0xa1] v_cvt_f16_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cvt_f32_f16_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x16,0x02,0x7e,0x00,0x01,0x09,0xa1] v_cvt_f32_f16 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cvt_rpi_i32_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x18,0x02,0x7e,0x00,0x01,0x09,0xa1] v_cvt_rpi_i32_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cvt_flr_i32_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x1a,0x02,0x7e,0x00,0x01,0x09,0xa1] v_cvt_flr_i32_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cvt_off_f32_i4_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x1c,0x02,0x7e,0x00,0x01,0x09,0xa1] v_cvt_off_f32_i4 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cvt_f32_ubyte0_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x22,0x02,0x7e,0x00,0x01,0x09,0xa1] v_cvt_f32_ubyte0 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cvt_f32_ubyte1_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x24,0x02,0x7e,0x00,0x01,0x09,0xa1] v_cvt_f32_ubyte1 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cvt_f32_ubyte2_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x26,0x02,0x7e,0x00,0x01,0x09,0xa1] v_cvt_f32_ubyte2 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cvt_f32_ubyte3_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x28,0x02,0x7e,0x00,0x01,0x09,0xa1] v_cvt_f32_ubyte3 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_trunc_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x38,0x02,0x7e,0x00,0x01,0x09,0xa1] v_trunc_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_ceil_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x3a,0x02,0x7e,0x00,0x01,0x09,0xa1] v_ceil_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_rndne_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x3c,0x02,0x7e,0x00,0x01,0x09,0xa1] v_rndne_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_floor_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x3e,0x02,0x7e,0x00,0x01,0x09,0xa1] v_floor_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_exp_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x40,0x02,0x7e,0x00,0x01,0x09,0xa1] v_exp_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_log_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x42,0x02,0x7e,0x00,0x01,0x09,0xa1] v_log_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_rcp_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x44,0x02,0x7e,0x00,0x01,0x09,0xa1] v_rcp_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_rcp_iflag_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x46,0x02,0x7e,0x00,0x01,0x09,0xa1] v_rcp_iflag_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_rsq_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x48,0x02,0x7e,0x00,0x01,0x09,0xa1] v_rsq_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_sqrt_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x4e,0x02,0x7e,0x00,0x01,0x09,0xa1] v_sqrt_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_cos_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x54,0x02,0x7e,0x00,0x01,0x09,0xa1] v_cos_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 @@ -267,22 +267,22 @@ // VI9: v_ffbh_i32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x5e,0x02,0x7e,0x00,0x01,0x09,0xa1] v_ffbh_i32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_frexp_exp_i32_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x66,0x02,0x7e,0x00,0x01,0x09,0xa1] v_frexp_exp_i32_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_frexp_mant_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x68,0x02,0x7e,0x00,0x01,0x09,0xa1] v_frexp_mant_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 // VI9: v_log_legacy_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x98,0x02,0x7e,0x00,0x01,0x09,0xa1] // NOSI: error: instruction not supported on this GPU -// NOCI: error: operands are not valid for this GPU or mode +// NOCI: error: not a valid operand. v_log_legacy_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 // VI9: v_exp_legacy_f32_dpp v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x96,0x02,0x7e,0x00,0x01,0x09,0xa1] // NOSI: error: instruction not supported on this GPU -// NOCI: error: operands are not valid for this GPU or mode +// NOCI: error: not a valid operand. v_exp_legacy_f32 v1, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 // NOSICI: error: instruction not supported on this GPU @@ -382,23 +382,23 @@ //===----------------------------------------------------------------------===// // ToDo: VOP2bInst instructions: v_add_u32, v_sub_u32 ... (vcc and ApplyMnemonic in AsmMatcherEmitter.cpp) -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_mac_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x01,0x01,0xff] v_mac_f32 v0, v0, v0 row_shl:1 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_mac_f32_dpp v0, v0, v0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x1f,0x01,0xff] v_mac_f32 v0, v0, v0 row_shr:0xf -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_mac_f32_dpp v0, v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bank_mask:0xf bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x2c,0x00,0x4d,0x08,0xaf] v_mac_f32 v0, v0, v0 quad_perm:[1,3,0,1] row_mask:0xa bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_add_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x02,0x00,0x01,0x09,0xa1] v_add_f32 v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_min_f32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x14,0x00,0x01,0x09,0xa1] v_min_f32 v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 @@ -406,19 +406,19 @@ // VI9: v_and_b32_dpp v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x00,0x00,0x26,0x00,0x01,0x09,0xa1] v_and_b32 v0, v0, v0 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_mul_i32_i24_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x0c,0x02,0x01,0x09,0xa1] v_mul_i32_i24 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_sub_f32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x04,0x02,0x01,0x09,0xa1] v_sub_f32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_subrev_f32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x06,0x02,0x01,0x09,0xa1] v_subrev_f32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_mul_f32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x0a,0x02,0x01,0x09,0xa1] v_mul_f32 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 @@ -426,7 +426,7 @@ // VI9: v_mul_hi_i32_i24_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x0e,0x02,0x01,0x09,0xa1] v_mul_hi_i32_i24 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_mul_u32_u24_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x10,0x02,0x01,0x09,0xa1] v_mul_u32_u24 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 @@ -434,7 +434,7 @@ // VI9: v_mul_hi_u32_u24_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x12,0x02,0x01,0x09,0xa1] v_mul_hi_u32_u24 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // VI9: v_max_f32_dpp v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x16,0x02,0x01,0x09,0xa1] v_max_f32 v1, v2 v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 @@ -551,46 +551,46 @@ v_ldexp_f16 v1, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 // NOSICI: error: instruction not supported on this GPU -// NOGFX9: error: operands are not valid for this GPU or mode +// NOGFX9: error: not a valid operand. // VI: v_add_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x32,0x02,0x01,0x09,0xa1] v_add_u32 v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 // NOSICI: error: instruction not supported on this GPU -// NOGFX9: error: operands are not valid for this GPU or mode +// NOGFX9: error: not a valid operand. // VI: v_sub_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x34,0x02,0x01,0x09,0xa1] v_sub_u32 v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 // NOSICI: error: instruction not supported on this GPU -// NOGFX9: error: operands are not valid for this GPU or mode +// NOGFX9: error: not a valid operand. // VI: v_subrev_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x36,0x02,0x01,0x09,0xa1] v_subrev_u32 v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // NOGFX9: error: instruction not supported on this GPU // VI: v_addc_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x38,0x02,0x01,0x09,0xa1] v_addc_u32 v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // NOGFX9: error: instruction not supported on this GPU // VI: v_subb_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x3a,0x02,0x01,0x09,0xa1] v_subb_u32 v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // NOGFX9: error: instruction not supported on this GPU // VI: v_subbrev_u32_dpp v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x3c,0x02,0x01,0x09,0xa1] v_subbrev_u32 v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // NOVI: error: instruction not supported on this GPU // GFX9: v_add_co_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x32,0x02,0x01,0x09,0xa1] v_add_co_u32 v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // NOVI: error: instruction not supported on this GPU // GFX9: v_sub_co_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x34,0x02,0x01,0x09,0xa1] v_sub_co_u32 v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: operands are not valid for this GPU or mode +// NOSICI: error: not a valid operand. // NOVI: error: instruction not supported on this GPU // GFX9: v_subrev_co_u32_dpp v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x06,0x02,0x36,0x02,0x01,0x09,0xa1] v_subrev_co_u32 v1, vcc, v2, v3 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 @@ -632,7 +632,7 @@ // NOGFX9: error: invalid operand for instruction v_and_b32 v0, 42, v1 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: invalid operand for instruction +// NOSICI: error: not a valid operand. // NOVI: error: invalid operand for instruction // NOGFX9: error: invalid operand for instruction v_add_f32 v0, v1, 345 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 @@ -647,7 +647,7 @@ // NOGFX9: error: invalid operand for instruction v_and_b32 v0, s42, v1 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 -// NOSICI: error: invalid operand for instruction +// NOSICI: error: not a valid operand. // NOVI: error: invalid operand for instruction // NOGFX9: error: invalid operand for instruction v_add_f32 v0, v1, s45 row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 diff --git a/llvm/test/MC/AMDGPU/vop_sdwa.s b/llvm/test/MC/AMDGPU/vop_sdwa.s --- a/llvm/test/MC/AMDGPU/vop_sdwa.s +++ b/llvm/test/MC/AMDGPU/vop_sdwa.s @@ -11,31 +11,31 @@ // Check SDWA operands //---------------------------------------------------------------------------// -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_mov_b32_sdwa v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x02,0x10,0x06,0x00] v_mov_b32 v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_mov_b32_sdwa v3, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1 ; encoding: [0xf9,0x02,0x06,0x7e,0x04,0x11,0x05,0x00] v_mov_b32 v3, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_mov_b32_sdwa v15, v99 dst_sel:BYTE_2 dst_unused:UNUSED_SEXT src0_sel:WORD_0 ; encoding: [0xf9,0x02,0x1e,0x7e,0x63,0x0a,0x04,0x00] v_mov_b32 v15, v99 dst_sel:BYTE_2 dst_unused:UNUSED_SEXT src0_sel:WORD_0 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_min_u32_sdwa v194, v13, v1 dst_sel:BYTE_3 dst_unused:UNUSED_SEXT src0_sel:BYTE_3 src1_sel:BYTE_2 ; encoding: [0xf9,0x02,0x84,0x1d,0x0d,0x0b,0x03,0x02] v_min_u32 v194, v13, v1 dst_sel:BYTE_3 dst_unused:UNUSED_SEXT src0_sel:BYTE_3 src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_min_u32_sdwa v255, v4, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:WORD_1 ; encoding: [0xf9,0x02,0xfe,0x1d,0x04,0x04,0x02,0x05] v_min_u32 v255, v4, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:WORD_1 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_min_u32_sdwa v200, v200, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; encoding: [0xf9,0x02,0x90,0x1d,0xc8,0x05,0x01,0x06] v_min_u32 v200, v200, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_min_u32_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x1c,0x01,0x06,0x00,0x06] v_min_u32 v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD @@ -43,43 +43,43 @@ // Check optional operands //---------------------------------------------------------------------------// -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_u32_f32_sdwa v0, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x0e,0x00,0x7e,0x00,0x36,0x06,0x00] v_cvt_u32_f32 v0, v0 clamp dst_sel:DWORD -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_fract_f32_sdwa v0, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x36,0x00,0x7e,0x00,0x26,0x06,0x00] v_fract_f32 v0, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PAD -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_sin_f32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x52,0x00,0x7e,0x00,0x06,0x05,0x00] v_sin_f32 v0, v0 dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_mov_b32_sdwa v1, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:WORD_1 ; encoding: [0xf9,0x02,0x02,0x7e,0x00,0x36,0x05,0x00] v_mov_b32 v1, v0 clamp src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_trunc_f32_sdwa v1, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:WORD_1 ; encoding: [0xf9,0x38,0x02,0x7e,0x00,0x36,0x05,0x00] v_trunc_f32 v1, v0 clamp dst_sel:DWORD src0_sel:WORD_1 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // GFX89: v_mov_b32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x00,0x16,0x06,0x00] v_mov_b32_sdwa v1, v0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // GFX89: v_add_f32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x05,0x06] v_add_f32_sdwa v0, v0, v0 dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_min_f32_sdwa v0, v0, v0 clamp dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x14,0x00,0x36,0x06,0x02] v_min_f32 v0, v0, v0 clamp dst_sel:DWORD src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_and_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x26,0x00,0x06,0x06,0x02] v_and_b32 v0, v0, v0 dst_unused:UNUSED_PAD src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // GFX89: v_mul_i32_i24_sdwa v1, v2, v3 clamp dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x06,0x02,0x0c,0x02,0x36,0x06,0x06] v_mul_i32_i24_sdwa v1, v2, v3 clamp @@ -87,31 +87,31 @@ // Check modifiers //===----------------------------------------------------------------------===// -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_fract_f32_sdwa v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x36,0x00,0x7e,0x00,0x06,0x25,0x00] v_fract_f32 v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_sin_f32_sdwa v0, -|v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x52,0x00,0x7e,0x00,0x06,0x35,0x00] v_sin_f32 v0, -abs(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_add_f32_sdwa v0, -|v0|, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x35,0x12] v_add_f32 v0, -|v0|, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_min_f32_sdwa v0, |v0|, -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x14,0x00,0x06,0x25,0x12] v_min_f32 v0, abs(v0), -v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // GFX89: v_mov_b32_sdwa v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x00,0x16,0x0e,0x00] v_mov_b32_sdwa v1, sext(v0) -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_and_b32_sdwa v0, sext(v0), sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x26,0x00,0x06,0x0e,0x0a] v_and_b32 v0, sext(v0), sext(v0) dst_unused:UNUSED_PAD src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmp_class_f32 vcc, -v1, sext(v2) src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x12,0x0c] // GFX9: v_cmp_class_f32_sdwa vcc, -v1, sext(v2) src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x12,0x0c] v_cmp_class_f32_sdwa vcc, -v1, sext(v2) src0_sel:BYTE_2 src1_sel:WORD_0 @@ -120,250 +120,250 @@ // Check VOP1 opcodes //===----------------------------------------------------------------------===// -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // GFX89: v_nop ; encoding: [0xf9,0x00,0x00,0x7e,0x00,0x00,0x00,0x00] v_nop_sdwa -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_u32_f32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x0e,0x00,0x7e,0x00,0x06,0x05,0x00] v_cvt_u32_f32 v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_fract_f32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x36,0x00,0x7e,0x00,0x06,0x05,0x00] v_fract_f32 v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_sin_f32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x52,0x00,0x7e,0x00,0x06,0x05,0x00] v_sin_f32 v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_mov_b32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x02,0x02,0x7e,0x00,0x06,0x05,0x00] v_mov_b32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_f32_i32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x0a,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_f32_i32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_f32_u32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x0c,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_f32_u32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_i32_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x10,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_i32_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_f16_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x14,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_f16_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_f32_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x16,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_f32_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_rpi_i32_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x18,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_rpi_i32_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_flr_i32_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x1a,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_flr_i32_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_off_f32_i4_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x1c,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_off_f32_i4 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_f32_ubyte0_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x22,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_f32_ubyte0 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_f32_ubyte1_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x24,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_f32_ubyte1 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_f32_ubyte2_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x26,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_f32_ubyte2 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cvt_f32_ubyte3_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x28,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_f32_ubyte3 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_trunc_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x38,0x02,0x7e,0x00,0x06,0x05,0x00] v_trunc_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_ceil_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x3a,0x02,0x7e,0x00,0x06,0x05,0x00] v_ceil_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_rndne_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x3c,0x02,0x7e,0x00,0x06,0x05,0x00] v_rndne_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_floor_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x3e,0x02,0x7e,0x00,0x06,0x05,0x00] v_floor_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_exp_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x40,0x02,0x7e,0x00,0x06,0x05,0x00] v_exp_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_log_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x42,0x02,0x7e,0x00,0x06,0x05,0x00] v_log_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_rcp_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x44,0x02,0x7e,0x00,0x06,0x05,0x00] v_rcp_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_rcp_iflag_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x46,0x02,0x7e,0x00,0x06,0x05,0x00] v_rcp_iflag_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_rsq_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x48,0x02,0x7e,0x00,0x06,0x05,0x00] v_rsq_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_sqrt_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x4e,0x02,0x7e,0x00,0x06,0x05,0x00] v_sqrt_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_cos_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x54,0x02,0x7e,0x00,0x06,0x05,0x00] v_cos_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_not_b32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x56,0x02,0x7e,0x00,0x06,0x05,0x00] v_not_b32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_bfrev_b32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x58,0x02,0x7e,0x00,0x06,0x05,0x00] v_bfrev_b32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_ffbh_u32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x5a,0x02,0x7e,0x00,0x06,0x05,0x00] v_ffbh_u32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_ffbl_b32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x5c,0x02,0x7e,0x00,0x06,0x05,0x00] v_ffbl_b32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_ffbh_i32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x5e,0x02,0x7e,0x00,0x06,0x05,0x00] v_ffbh_i32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_frexp_exp_i32_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x66,0x02,0x7e,0x00,0x06,0x05,0x00] v_frexp_exp_i32_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_frexp_mant_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x68,0x02,0x7e,0x00,0x06,0x05,0x00] v_frexp_mant_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 // GFX89: v_log_legacy_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x98,0x02,0x7e,0x00,0x06,0x05,0x00] // NOSI: error: instruction not supported on this GPU -// NOCI: error: invalid operand for instruction +// NOCI: error: not a valid operand. v_log_legacy_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 // GFX89: v_exp_legacy_f32_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x96,0x02,0x7e,0x00,0x06,0x05,0x00] // NOSI: error: instruction not supported on this GPU -// NOCI: error: invalid operand for instruction +// NOCI: error: not a valid operand. v_exp_legacy_f32 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_cvt_f16_u16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x72,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_f16_u16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_cvt_f16_i16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x74,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_f16_i16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_cvt_u16_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x76,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_u16_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_cvt_i16_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x78,0x02,0x7e,0x00,0x06,0x05,0x00] v_cvt_i16_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_rcp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x7a,0x02,0x7e,0x00,0x06,0x05,0x00] v_rcp_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_sqrt_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x7c,0x02,0x7e,0x00,0x06,0x05,0x00] v_sqrt_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_rsq_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x7e,0x02,0x7e,0x00,0x06,0x05,0x00] v_rsq_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_log_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x80,0x02,0x7e,0x00,0x06,0x05,0x00] v_log_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_exp_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x82,0x02,0x7e,0x00,0x06,0x05,0x00] v_exp_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_frexp_mant_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x84,0x02,0x7e,0x00,0x06,0x05,0x00] v_frexp_mant_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_frexp_exp_i16_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x86,0x02,0x7e,0x00,0x06,0x05,0x00] v_frexp_exp_i16_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_floor_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x88,0x02,0x7e,0x00,0x06,0x05,0x00] v_floor_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_ceil_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x8a,0x02,0x7e,0x00,0x06,0x05,0x00] v_ceil_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_trunc_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x8c,0x02,0x7e,0x00,0x06,0x05,0x00] v_trunc_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_rndne_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x8e,0x02,0x7e,0x00,0x06,0x05,0x00] v_rndne_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_fract_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x90,0x02,0x7e,0x00,0x06,0x05,0x00] v_fract_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_sin_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x92,0x02,0x7e,0x00,0x06,0x05,0x00] v_sin_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_cos_f16_sdwa v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x94,0x02,0x7e,0x00,0x06,0x05,0x00] v_cos_f16 v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 // GFX9: v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x16,0x00] -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD // GFX9: v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x26,0x00] -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD // GFX9: v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00] -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD // GFX9: v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x05,0x00] -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 // GFX9: v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00] -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD @@ -371,237 +371,237 @@ // Check VOP2 opcodes //===----------------------------------------------------------------------===// -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_add_f32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x05,0x02] v_add_f32 v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_min_f32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x14,0x00,0x06,0x05,0x02] v_min_f32 v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_and_b32_sdwa v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x26,0x00,0x06,0x05,0x02] v_and_b32 v0, v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_mul_i32_i24_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x0c,0x02,0x06,0x05,0x02] v_mul_i32_i24 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_sub_f32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x04,0x02,0x06,0x05,0x02] v_sub_f32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_subrev_f32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x06,0x02,0x06,0x05,0x02] v_subrev_f32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_mul_f32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x0a,0x02,0x06,0x05,0x02] v_mul_f32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_mul_hi_i32_i24_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x0e,0x02,0x06,0x05,0x02] v_mul_hi_i32_i24 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_mul_u32_u24_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x10,0x02,0x06,0x05,0x02] v_mul_u32_u24 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_mul_hi_u32_u24_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x12,0x02,0x06,0x05,0x02] v_mul_hi_u32_u24 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_max_f32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x16,0x02,0x06,0x05,0x02] v_max_f32 v1, v2 v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_min_i32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x18,0x02,0x06,0x05,0x02] v_min_i32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_max_i32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x1a,0x02,0x06,0x05,0x02] v_max_i32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_min_u32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x1c,0x02,0x06,0x05,0x02] v_min_u32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_max_u32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x1e,0x02,0x06,0x05,0x02] v_max_u32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_lshrrev_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x20,0x02,0x06,0x05,0x02] v_lshrrev_b32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_ashrrev_i32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x22,0x02,0x06,0x05,0x02] v_ashrrev_i32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_lshlrev_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x24,0x02,0x06,0x05,0x02] v_lshlrev_b32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_or_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x28,0x02,0x06,0x05,0x02] v_or_b32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // GFX89: v_xor_b32_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x2a,0x02,0x06,0x05,0x02] v_xor_b32 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_add_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x3e,0x02,0x06,0x05,0x02] v_add_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_sub_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x40,0x02,0x06,0x05,0x02] v_sub_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_subrev_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x42,0x02,0x06,0x05,0x02] v_subrev_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_mul_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x44,0x02,0x06,0x05,0x02] v_mul_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_add_u16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x4c,0x02,0x06,0x05,0x02] v_add_u16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_sub_u16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x4e,0x02,0x06,0x05,0x02] v_sub_u16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_subrev_u16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x50,0x02,0x06,0x05,0x02] v_subrev_u16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_mul_lo_u16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x52,0x02,0x06,0x05,0x02] v_mul_lo_u16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_lshlrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x54,0x02,0x06,0x05,0x02] v_lshlrev_b16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_lshrrev_b16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x56,0x02,0x06,0x05,0x02] v_lshrrev_b16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_ashrrev_i16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x58,0x02,0x06,0x05,0x02] v_ashrrev_i16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_max_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x5a,0x02,0x06,0x05,0x02] v_max_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_min_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x5c,0x02,0x06,0x05,0x02] v_min_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_max_u16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x5e,0x02,0x06,0x05,0x02] v_max_u16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_max_i16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x60,0x02,0x06,0x05,0x02] v_max_i16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_min_u16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x62,0x02,0x06,0x05,0x02] v_min_u16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_min_i16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x64,0x02,0x06,0x05,0x02] v_min_i16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // GFX89: v_ldexp_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x66,0x02,0x06,0x05,0x02] v_ldexp_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOGFX9: error: operands are not valid for this GPU or mode // VI: v_add_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x32,0x02,0x06,0x05,0x02] v_add_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOGFX9: error: operands are not valid for this GPU or mode // VI: v_sub_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x34,0x02,0x06,0x05,0x02] v_sub_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOGFX9: error: operands are not valid for this GPU or mode // VI: v_subrev_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x36,0x02,0x06,0x05,0x02] v_subrev_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOGFX9: error: instruction not supported on this GPU // VI: v_addc_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x38,0x02,0x06,0x05,0x02] v_addc_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOGFX9: error: instruction not supported on this GPU // VI: v_subb_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x3a,0x02,0x06,0x05,0x02] v_subb_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOGFX9: error: instruction not supported on this GPU // VI: v_subbrev_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x3c,0x02,0x06,0x05,0x02] v_subbrev_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: instruction not supported on this GPU // GFX9: v_add_co_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x32,0x02,0x06,0x05,0x02] v_add_co_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: instruction not supported on this GPU // GFX9: v_sub_co_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x34,0x02,0x06,0x05,0x02] v_sub_co_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: instruction not supported on this GPU // GFX9: v_subrev_co_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x36,0x02,0x06,0x05,0x02] v_subrev_co_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU // GFX9: v_addc_co_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x38,0x02,0x06,0x05,0x02] v_addc_co_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU // GFX9: v_subb_co_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x3a,0x02,0x06,0x05,0x02] v_subb_co_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU // GFX9: v_subbrev_co_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x3c,0x02,0x06,0x05,0x02] v_subbrev_co_u32_sdwa v1, vcc, v2, v3, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // GFX89: v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x00,0x06,0x06] v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_cndmask_b32_sdwa v5, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0xc1,0x06,0x86,0x06] v_cndmask_b32_sdwa v5, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // GFX89: v_cndmask_b32_sdwa v5, -v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x16,0x26] v_cndmask_b32_sdwa v5, -v1, |v2|, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // GFX89: v_cndmask_b32_sdwa v5, |v1|, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x26,0x16] v_cndmask_b32_sdwa v5, |v1|, -v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD v_cndmask_b32_sdwa v5, vcc_lo, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE-1]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // NOGFX9: error: invalid operand (violates constant bus restrictions) @@ -609,72 +609,72 @@ // Check VOPC opcodes //===----------------------------------------------------------------------===// -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmp_eq_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x02,0x04] // GFX9: v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x02,0x04] v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmp_nle_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x02,0x04] // GFX9: v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x02,0x04] v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmpx_gt_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x02,0x04] // GFX9: v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x02,0x04] v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmpx_nlt_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x02,0x04] // GFX9: v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x02,0x04] v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmp_lt_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x02,0x04] // GFX9: v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x02,0x04] v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmp_t_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x02,0x04] // GFX9: v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x02,0x04] v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmpx_eq_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x02,0x04] // GFX9: v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x02,0x04] v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmpx_ne_i32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x02,0x04] // GFX9: v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x02,0x04] v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmp_f_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x02,0x04] // GFX9: v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x02,0x04] v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmp_gt_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x02,0x04] // GFX9: v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x02,0x04] v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmpx_le_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x02,0x04] // GFX9: v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x02,0x04] v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmpx_ne_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x02,0x04] // GFX9: v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x02,0x04] v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmp_class_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x02,0x04] // GFX9: v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x02,0x04] v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // VI: v_cmpx_class_f32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x02,0x04] // GFX9: v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 ; encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x02,0x04] v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0 @@ -687,101 +687,101 @@ // v_mac_f16/f32 is prohibited //===----------------------------------------------------------------------===// -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. // VI: v_mac_f32_sdwa v3, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:WORD_1 src1_sel:DWORD ; encoding: [0xf9,0x0a,0x06,0x2c,0x04,0x16,0x05,0x06] -// NOGFX9: error: operands are not valid for this GPU or mode +// NOGFX9: error: not a valid operand. v_mac_f32 v3, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:WORD_1 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. // VI: v_mac_f32_sdwa v15, v99, v194 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:WORD_0 src1_sel:DWORD ; encoding: [0xf9,0x84,0x1f,0x2c,0x63,0x0e,0x04,0x06] -// NOGFX9: error: operands are not valid for this GPU or mode +// NOGFX9: error: not a valid operand. v_mac_f32 v15, v99, v194 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:WORD_0 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. // NOVI: error: invalid operand for instruction -// NOGFX9: error: operands are not valid for this GPU or mode +// NOGFX9: error: not a valid operand. v_mac_f32 v194, v13, v1 dst_sel:BYTE_0 dst_unused:UNUSED_SEXT src0_sel:BYTE_3 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // VI: v_mac_f16_sdwa v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x06,0x02,0x46,0x02,0x06,0x05,0x02] -// NOGFX9: error: operands are not valid for this GPU or mode +// NOGFX9: error: not a valid operand. v_mac_f16 v1, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 //===----------------------------------------------------------------------===// // Scalar registers are allowed //===----------------------------------------------------------------------===// -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. // NOVI: error: invalid operand for instruction // GFX9: v_mov_b32_sdwa v1, s2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x02,0x10,0x86,0x00] v_mov_b32 v1, s2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. // NOVI: error: invalid operand for instruction // GFX9: v_mov_b32_sdwa v1, exec_lo dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x7e,0x10,0x86,0x00] v_mov_b32 v1, exec_lo dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: register not available on this GPU // GFX9: v_mov_b32_sdwa v1, ttmp12 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x78,0x10,0x86,0x00] v_mov_b32_sdwa v1, ttmp12 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x85,0x02] v_add_f32 v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v0, v0, s22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x2c,0x00,0x02,0x00,0x06,0x05,0x82] v_add_f32 v0, v0, s22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. // NOVI: error: invalid operand for instruction // NOGFX9: error: invalid operand for instruction v_add_f32 v0, exec_lo, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. // NOVI: error: invalid operand for instruction // NOGFX9: error: register not available on this GPU v_add_f32 v0, v1, tba_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. // NOVI: error: invalid operand for instruction // NOGFX9: error: register not available on this GPU v_add_f32 v0, v1, tma_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_cmp_eq_f32_sdwa vcc, s1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x85,0x02] v_cmp_eq_f32_sdwa vcc, s1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x2c,0x84,0x7c,0x01,0x00,0x05,0x82] v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: register not available on this GPU // GFX9: v_cmp_eq_f32_sdwa ttmp[12:13], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0xf8,0x05,0x02] v_cmp_eq_f32_sdwa ttmp[12:13], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: operands are not valid for this GPU or mode // NOGFX9: error: register not available on this GPU v_cmp_eq_f32_sdwa tba, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: operands are not valid for this GPU or mode // NOGFX9: error: register not available on this GPU v_cmp_eq_f32_sdwa tma, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: register not available on this GPU // GFX9: v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0xf6,0x84,0x7c,0x01,0x00,0x05,0x82] v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // NOGFX9: error: invalid operand (violates constant bus restrictions) v_cmp_eq_f32_sdwa vcc, exec_lo, vcc_lo src0_sel:WORD_1 src1_sel:BYTE_2 @@ -796,227 +796,227 @@ // Inline constants are allowed (though semantics is not clear yet) //===----------------------------------------------------------------------===// -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_mov_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0x80,0x06,0x86,0x00] v_mov_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_mov_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0xc1,0x06,0x86,0x00] v_mov_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_mov_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0xf0,0x06,0x86,0x00] v_mov_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_mov_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0xf7,0x06,0x86,0x00] v_mov_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_mov_b32_sdwa v5, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0xc1,0x16,0x8e,0x00] v_mov_b32_sdwa v5, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xc1,0x06,0x86,0x06] v_add_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, |-1|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xc1,0x16,0xa6,0x06] v_add_f32_sdwa v5, |-1|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, neg(-1), -|v2| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xc1,0x16,0x96,0x36] v_add_f32_sdwa v5, neg(-1), -|v2| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, -|-1|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xc1,0x16,0xb6,0x06] v_add_f32_sdwa v5, -|-1|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xf0,0x06,0x86,0x06] v_add_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, |-4.0|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xf7,0x16,0xa6,0x06] v_add_f32_sdwa v5, |-4.0|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, neg(-4.0), v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xf7,0x16,0x96,0x06] v_add_f32_sdwa v5, neg(-4.0), v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, -|-4.0|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x02,0xf7,0x16,0xb6,0x06] v_add_f32_sdwa v5, -|-4.0|, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, v2, -4.0 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xee,0x0b,0x02,0x02,0x16,0x06,0x86] v_add_f32_sdwa v5, v2, -4.0 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, v2, |-4.0| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xee,0x0b,0x02,0x02,0x16,0x06,0xa6] v_add_f32_sdwa v5, v2, |-4.0| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, v2, neg(-4.0) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xee,0x0b,0x02,0x02,0x16,0x06,0x96] v_add_f32_sdwa v5, v2, neg(-4.0) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, v2, -|-4.0| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xee,0x0b,0x02,0x02,0x16,0x06,0xb6] v_add_f32_sdwa v5, v2, -|-4.0| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0x86] v_add_f32_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, v2, |-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0xa6] v_add_f32_sdwa v5, v2, |-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, v2, neg(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0x96] v_add_f32_sdwa v5, v2, neg(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_add_f32_sdwa v5, v2, -|-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x02,0x02,0x16,0x06,0xb6] v_add_f32_sdwa v5, v2, -|-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_and_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x26,0xf7,0x16,0x86,0x06] v_and_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_and_b32_sdwa v5, sext(-4.0), v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x26,0xf7,0x16,0x8e,0x06] v_and_b32_sdwa v5, sext(-4.0), v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_and_b32_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x26,0x02,0x16,0x06,0x86] v_and_b32_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_and_b32_sdwa v5, v2, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x26,0x02,0x16,0x06,0x8e] v_and_b32_sdwa v5, v2, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: invalid operand for instruction // GFX9: v_exp_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xc1,0x16,0x86,0x00] v_exp_f16_sdwa v5, -1 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: invalid operand for instruction // GFX9: v_exp_f16_sdwa v5, |-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xc1,0x16,0xa6,0x00] v_exp_f16_sdwa v5, |-1| -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: invalid operand for instruction // GFX9: v_exp_f16_sdwa v5, neg(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xc1,0x16,0x96,0x00] v_exp_f16_sdwa v5, neg(-1) -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: invalid operand for instruction // GFX9: v_exp_f16_sdwa v5, -|-1| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xc1,0x16,0xb6,0x00] v_exp_f16_sdwa v5, -|-1| -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: invalid operand for instruction // GFX9: v_exp_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xf0,0x16,0x86,0x00] v_exp_f16_sdwa v5, 0.5 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: invalid operand for instruction // GFX9: v_exp_f16_sdwa v5, |0.5| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xf0,0x16,0xa6,0x00] v_exp_f16_sdwa v5, |0.5| -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: invalid operand for instruction // GFX9: v_exp_f16_sdwa v5, neg(0.5) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xf0,0x16,0x96,0x00] v_exp_f16_sdwa v5, neg(0.5) -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: invalid operand for instruction // GFX9: v_exp_f16_sdwa v5, -|0.5| dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x82,0x0a,0x7e,0xf0,0x16,0xb6,0x00] v_exp_f16_sdwa v5, -|0.5| -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: invalid operand for instruction // NOGFX9: error: invalid operand for instruction v_max_i16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: invalid operand for instruction // NOGFX9: error: invalid operand for instruction v_max_i16_sdwa v5, sext(-4.0), v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: invalid operand for instruction // GFX9: v_max_i16_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x60,0x02,0x16,0x06,0x86] v_max_i16_sdwa v5, v2, -1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: invalid operand for instruction // GFX9: v_max_i16_sdwa v5, v2, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x0b,0x60,0x02,0x16,0x06,0x8e] v_max_i16_sdwa v5, v2, sext(-1) dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_cmp_eq_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0x86,0x06] v_cmp_eq_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_cmp_eq_f32_sdwa s[6:7], |-4.0|, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0xa6,0x06] v_cmp_eq_f32_sdwa s[6:7], |-4.0|, v2 src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_cmp_eq_f32_sdwa s[6:7], neg(-4.0), v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0x96,0x06] v_cmp_eq_f32_sdwa s[6:7], neg(-4.0), v2 src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_cmp_eq_f32_sdwa s[6:7], -|-4.0|, v2 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0xb6,0x06] v_cmp_eq_f32_sdwa s[6:7], -|-4.0|, v2 src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_cmp_eq_f32_sdwa s[6:7], v2, -1 src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0x86] v_cmp_eq_f32_sdwa s[6:7], v2, -1 src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_cmp_eq_f32_sdwa s[6:7], v2, |-1| src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0xa6] v_cmp_eq_f32_sdwa s[6:7], v2, |-1| src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_cmp_eq_f32_sdwa s[6:7], v2, neg(-1) src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0x96] v_cmp_eq_f32_sdwa s[6:7], v2, neg(-1) src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_cmp_eq_f32_sdwa s[6:7], v2, -|-1| src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x82,0x85,0x7c,0x02,0x86,0x06,0xb6] v_cmp_eq_f32_sdwa s[6:7], v2, -|-1| src0_sel:DWORD src1_sel:DWORD @@ -1025,19 +1025,19 @@ // Literals are not allowed //===----------------------------------------------------------------------===// -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // NOGFX89: error: invalid operand for instruction v_add_f32 v0, v1, 3.45 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // NOGFX89: error: invalid operand for instruction v_cmpx_class_f32 vcc, v1, 200 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: not a valid operand. +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // NOGFX89: error: invalid operand for instruction v_cmpx_class_f32 vcc, 200, v1 src0_sel:BYTE_2 src1_sel:WORD_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOGFX89: error: invalid operand for instruction v_mov_b32_sdwa v5, -17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD @@ -1045,17 +1045,17 @@ // VOPC with arbitrary SGPR destination //===----------------------------------------------------------------------===// -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: operands are not valid for this GPU or mode // GFX9: v_cmp_eq_f32_sdwa s[2:3], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x82,0x05,0x02] v_cmp_eq_f32_sdwa s[2:3], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: operands are not valid for this GPU or mode // GFX9: v_cmp_eq_f32_sdwa exec, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0xfe,0x05,0x02] v_cmp_eq_f32_sdwa exec, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOVI: error: invalid operand for instruction // GFX9: v_cmp_eq_f32_sdwa exec, s2, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x02,0xfe,0x85,0x02] v_cmp_eq_f32_sdwa exec, s2, v2 src0_sel:WORD_1 src1_sel:BYTE_2 @@ -1064,23 +1064,23 @@ // OMod output modifier allowed //===----------------------------------------------------------------------===// -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. // NOVI: error: operands are not valid for this GPU or mode // GFX9: v_trunc_f32_sdwa v1, v2 mul:2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x38,0x02,0x7e,0x02,0x50,0x06,0x00] v_trunc_f32 v1, v2 mul:2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD -// NOSICI: error: invalid operand for instruction -// NOVI: error: operands are not valid for this GPU or mode +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. +// NOVI: error: not a valid operand. // GFX9: v_trunc_f32_sdwa v1, v2 clamp div:2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x38,0x02,0x7e,0x02,0xf0,0x06,0x00] v_trunc_f32 v1, v2 clamp div:2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. // NOVI: error: operands are not valid for this GPU or mode // GFX9: v_add_f32_sdwa v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x46,0x05,0x02] v_add_f32 v0, v0, v0 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction -// NOVI: error: operands are not valid for this GPU or mode +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: not a valid operand. +// NOVI: error: not a valid operand. // GFX9: v_add_f32_sdwa v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0xe6,0x05,0x02] v_add_f32 v0, v0, v0 clamp div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 @@ -1088,16 +1088,16 @@ // Check Instructions //---------------------------------------------------------------------------// -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: instruction not supported on this GPU // GFX9: v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:BYTE_0 ; encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x00,0x00] v_screen_partition_4se_b32_sdwa v5, v1 src0_sel:BYTE_0 -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOGFX89: error: not a valid operand. v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD -// NOSICI: error: sdwa variant of this instruction is not supported +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: sdwa variant of this instruction is not supported // NOGFX89: error: not a valid operand. v_cndmask_b32_sdwa v5, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD @@ -1105,66 +1105,66 @@ // Validate register size checks (bug 37943) //===----------------------------------------------------------------------===// -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // NOGFX89: error: invalid operand for instruction v_add_f32 v0, s[0:1], v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // NOGFX89: error: invalid operand for instruction v_add_f32 v0, s[0:3], v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // NOGFX89: error: invalid operand for instruction v_add_f32 v0, v[0:1], v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // NOGFX89: error: invalid operand for instruction v_add_f32 v0, v[0:2], v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // NOGFX89: error: invalid operand for instruction v_add_f32 v0, v0, s[0:1] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // NOGFX89: error: invalid operand for instruction v_add_f32 v0, s0, v[0:1] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: invalid operand for instruction +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: not a valid operand. // NOGFX89: error: invalid operand for instruction v_add_f32 v0, s0, v[0:3] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOGFX89: error: invalid operand for instruction v_add_f16 v1, v[2:3], v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOGFX89: error: invalid operand for instruction v_add_f16 v1, s[2:3], v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOGFX89: error: invalid operand for instruction v_add_f16 v1, v2, v[2:3] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+2]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOGFX89: error: invalid operand for instruction v_add_f16 v1, v2, s[2:3] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: not a valid operand // NOGFX9: error: invalid operand for instruction v_add_u32 v1, v[2:3], v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: not a valid operand // NOGFX9: error: invalid operand for instruction v_add_u32 v1, s[2:3], v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: not a valid operand // NOGFX9: error: invalid operand for instruction v_add_u32 v1, v3, v[2:3] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 -// NOSICI: error: instruction not supported on this GPU +// NOSICI: [[@LINE+3]]:{{[0-9]+}}: error: instruction not supported on this GPU // NOVI: error: not a valid operand // NOGFX9: error: invalid operand for instruction v_add_u32 v1, v3, s[2:3] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 diff --git a/llvm/test/MC/ARM/cxx-global-constructor.ll b/llvm/test/MC/ARM/cxx-global-constructor.ll --- a/llvm/test/MC/ARM/cxx-global-constructor.ll +++ b/llvm/test/MC/ARM/cxx-global-constructor.ll @@ -2,7 +2,7 @@ ; RUN: -filetype=obj -o - | llvm-readobj -r - | FileCheck %s -@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @f, i8* null }] +@llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @f, ptr null }] define void @f() { ret void diff --git a/llvm/test/MC/ARM/data-in-code.ll b/llvm/test/MC/ARM/data-in-code.ll --- a/llvm/test/MC/ARM/data-in-code.ll +++ b/llvm/test/MC/ARM/data-in-code.ll @@ -9,8 +9,8 @@ ;; Ensure that if a jump table is generated that it has Mapping Symbols ;; marking the data-in-code region. -define void @foo(i32* %ptr, i32 %b) nounwind ssp { - %tmp = load i32, i32* %ptr, align 4 +define void @foo(ptr %ptr, i32 %b) nounwind ssp { + %tmp = load i32, ptr %ptr, align 4 switch i32 %tmp, label %exit [ i32 0, label %bb0 i32 1, label %bb1 @@ -18,16 +18,16 @@ i32 3, label %bb3 ] bb0: - store i32 %b, i32* %ptr, align 4 + store i32 %b, ptr %ptr, align 4 br label %exit bb1: - store i32 1, i32* %ptr, align 4 + store i32 1, ptr %ptr, align 4 br label %exit bb2: - store i32 2, i32* %ptr, align 4 + store i32 2, ptr %ptr, align 4 br label %exit bb3: - store i32 4, i32* %ptr, align 4 + store i32 4, ptr %ptr, align 4 br label %exit exit: ret void diff --git a/llvm/test/MC/AVR/separator.s b/llvm/test/MC/AVR/separator.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AVR/separator.s @@ -0,0 +1,11 @@ +; RUN: llvm-mc -filetype=obj -triple avr < %s | llvm-objdump -d - | FileCheck %s + +foo: + + ; The $ symbol is a separator (like a newline). + mov r0, r1 $ mov r1, r2 $ mov r2, r3 $ mov r3, r4 + +; CHECK: mov r0, r1 +; CHECK: mov r1, r2 +; CHECK: mov r2, r3 +; CHECK: mov r3, r4 diff --git a/llvm/test/MC/AsmParser/pr28805.ll b/llvm/test/MC/AsmParser/pr28805.ll --- a/llvm/test/MC/AsmParser/pr28805.ll +++ b/llvm/test/MC/AsmParser/pr28805.ll @@ -6,11 +6,10 @@ define i32 @_xbegin() { entry: %res = alloca i32, align 4 - %0 = bitcast i32* %res to i8* - store i32 -1, i32* %res, align 4 - call void asm sideeffect inteldialect ".byte 0xC7\0A\09.byte 0xF8\0A\09.byte 2\0A\09.byte 0\0A\09.byte 0\0A\09.byte 0\0A\09jmp .L__MSASMLABEL_.0__L2\0A\09mov dword ptr $0, eax\0A\09.L__MSASMLABEL_.0__L2:", "=*m,~{dirflag},~{fpsr},~{flags}"(i32* elementtype(i32) nonnull %res) - %1 = load i32, i32* %res, align 4 - ret i32 %1 + store i32 -1, ptr %res, align 4 + call void asm sideeffect inteldialect ".byte 0xC7\0A\09.byte 0xF8\0A\09.byte 2\0A\09.byte 0\0A\09.byte 0\0A\09.byte 0\0A\09jmp .L__MSASMLABEL_.0__L2\0A\09mov dword ptr $0, eax\0A\09.L__MSASMLABEL_.0__L2:", "=*m,~{dirflag},~{fpsr},~{flags}"(ptr elementtype(i32) nonnull %res) + %0 = load i32, ptr %res, align 4 + ret i32 %0 } ; CHECK-NOT: Error parsing inline asm diff --git a/llvm/test/MC/COFF/cgprofile.ll b/llvm/test/MC/COFF/cgprofile.ll --- a/llvm/test/MC/COFF/cgprofile.ll +++ b/llvm/test/MC/COFF/cgprofile.ll @@ -23,10 +23,10 @@ !0 = !{i32 5, !"CG Profile", !1} !1 = !{!2, !3, !4, !5} -!2 = !{void ()* @a, void ()* @b, i64 32} -!3 = !{void (i1)* @freq, void ()* @a, i64 11} -!4 = !{void (i1)* @freq, void ()* @b, i64 20} -!5 = !{void (i1)* @freq, null, i64 20} +!2 = !{ptr @a, ptr @b, i64 32} +!3 = !{ptr @freq, ptr @a, i64 11} +!4 = !{ptr @freq, ptr @b, i64 20} +!5 = !{ptr @freq, null, i64 20} ; CHECK: .cg_profile a, b, 32 ; CHECK: .cg_profile freq, a, 11 diff --git a/llvm/test/MC/COFF/const-gv-with-rel-init.ll b/llvm/test/MC/COFF/const-gv-with-rel-init.ll --- a/llvm/test/MC/COFF/const-gv-with-rel-init.ll +++ b/llvm/test/MC/COFF/const-gv-with-rel-init.ll @@ -4,8 +4,8 @@ ret void } -@ptr = constant void ()* @f, section ".CRT$XLB", align 8 +@ptr = constant ptr @f, section ".CRT$XLB", align 8 ; CHECK: .section .CRT$XLB,"dr" -@weak_array = weak_odr unnamed_addr constant [1 x i8*] [i8* bitcast (void ()* @f to i8*)] +@weak_array = weak_odr unnamed_addr constant [1 x ptr] [ptr @f] ; CHECK: .section .rdata,"dr" diff --git a/llvm/test/MC/COFF/cross-section-relative.ll b/llvm/test/MC/COFF/cross-section-relative.ll --- a/llvm/test/MC/COFF/cross-section-relative.ll +++ b/llvm/test/MC/COFF/cross-section-relative.ll @@ -7,26 +7,26 @@ @g2 = constant i32 2; @g3 = constant i32 3; @g4 = constant i32 4; -@__ImageBase = external global i64*; +@__ImageBase = external global ptr; ;;;; cross-section relative relocations ; CHECK: .quad (g3-t1)+4 -@t1 = global i64 add(i64 sub(i64 ptrtoint(i32* @g3 to i64), i64 ptrtoint(i64* @t1 to i64)), i64 4), section ".fix" +@t1 = global i64 add(i64 sub(i64 ptrtoint(ptr @g3 to i64), i64 ptrtoint(ptr @t1 to i64)), i64 4), section ".fix" ; CHECK: .quad g3-t2 -@t2 = global i64 sub(i64 ptrtoint(i32* @g3 to i64), i64 ptrtoint(i64* @t2 to i64)), section ".fix" +@t2 = global i64 sub(i64 ptrtoint(ptr @g3 to i64), i64 ptrtoint(ptr @t2 to i64)), section ".fix" ; CHECK: .quad (g3-t3)-4 -@t3 = global i64 sub(i64 sub(i64 ptrtoint(i32* @g3 to i64), i64 ptrtoint(i64* @t3 to i64)), i64 4), section ".fix" +@t3 = global i64 sub(i64 sub(i64 ptrtoint(ptr @g3 to i64), i64 ptrtoint(ptr @t3 to i64)), i64 4), section ".fix" ; CHECK: .long g3-t4 -@t4 = global i32 trunc(i64 sub(i64 ptrtoint(i32* @g3 to i64), i64 ptrtoint(i32* @t4 to i64)) to i32), section ".fix" +@t4 = global i32 trunc(i64 sub(i64 ptrtoint(ptr @g3 to i64), i64 ptrtoint(ptr @t4 to i64)) to i32), section ".fix" ;;;; image base relocation ; CHECK: .long g3@IMGREL{{$}} -@t5 = global i32 trunc(i64 sub(i64 ptrtoint(i32* @g3 to i64), i64 ptrtoint(i64** @__ImageBase to i64)) to i32), section ".fix" +@t5 = global i32 trunc(i64 sub(i64 ptrtoint(ptr @g3 to i64), i64 ptrtoint(ptr @__ImageBase to i64)) to i32), section ".fix" ; CHECK: .long g3@IMGREL+4{{$}} -@t6 = global i32 trunc(i64 sub(i64 ptrtoint(i32* getelementptr (i32, i32* @g3, i32 1) to i64), i64 ptrtoint(i64** @__ImageBase to i64)) to i32), section ".fix" +@t6 = global i32 trunc(i64 sub(i64 ptrtoint(ptr getelementptr (i32, ptr @g3, i32 1) to i64), i64 ptrtoint(ptr @__ImageBase to i64)) to i32), section ".fix" ;;;; cross-section relative with source offset @@ -36,5 +36,5 @@ @t7 = global %struct.EEType { [2 x i8] c"\01\02", i64 256, - i32 trunc(i64 sub(i64 ptrtoint(i32* @g3 to i64), i64 ptrtoint(i32* getelementptr inbounds (%struct.EEType, %struct.EEType* @t7, i32 0, i32 2) to i64)) to i32 ) + i32 trunc(i64 sub(i64 ptrtoint(ptr @g3 to i64), i64 ptrtoint(ptr getelementptr inbounds (%struct.EEType, ptr @t7, i32 0, i32 2) to i64)) to i32 ) }, section ".fix" diff --git a/llvm/test/MC/COFF/global_ctors_dtors.ll b/llvm/test/MC/COFF/global_ctors_dtors.ll --- a/llvm/test/MC/COFF/global_ctors_dtors.ll +++ b/llvm/test/MC/COFF/global_ctors_dtors.ll @@ -9,19 +9,19 @@ @.str2 = private unnamed_addr constant [12 x i8] c"destructing\00", align 1 @.str3 = private unnamed_addr constant [5 x i8] c"main\00", align 1 -%ini = type { i32, void()*, i8* } +%ini = type { i32, ptr, ptr } @llvm.global_ctors = appending global [3 x %ini ] [ - %ini { i32 65535, void ()* @a_global_ctor, i8* null }, - %ini { i32 65535, void ()* @b_global_ctor, i8* bitcast (i32* @b to i8*) }, - %ini { i32 65535, void ()* @c_global_ctor, i8* bitcast (i32* @c to i8*) } + %ini { i32 65535, ptr @a_global_ctor, ptr null }, + %ini { i32 65535, ptr @b_global_ctor, ptr @b }, + %ini { i32 65535, ptr @c_global_ctor, ptr @c } ] -@llvm.global_dtors = appending global [1 x %ini ] [%ini { i32 65535, void ()* @a_global_dtor, i8* null }] +@llvm.global_dtors = appending global [1 x %ini ] [%ini { i32 65535, ptr @a_global_dtor, ptr null }] -declare i32 @puts(i8*) +declare i32 @puts(ptr) define void @a_global_ctor() nounwind { - %1 = call i32 @puts(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0)) + %1 = call i32 @puts(ptr @.str) ret void } @@ -30,22 +30,22 @@ @c = available_externally dllimport global i32 zeroinitializer define void @b_global_ctor() nounwind { - store i32 42, i32* @b + store i32 42, ptr @b ret void } define void @c_global_ctor() nounwind { - store i32 42, i32* @c + store i32 42, ptr @c ret void } define void @a_global_dtor() nounwind { - %1 = call i32 @puts(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str2, i32 0, i32 0)) + %1 = call i32 @puts(ptr @.str2) ret void } define i32 @main() nounwind { - %1 = call i32 @puts(i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str3, i32 0, i32 0)) + %1 = call i32 @puts(ptr @.str3) ret i32 0 } diff --git a/llvm/test/MC/COFF/ir-to-imgrel.ll b/llvm/test/MC/COFF/ir-to-imgrel.ll --- a/llvm/test/MC/COFF/ir-to-imgrel.ll +++ b/llvm/test/MC/COFF/ir-to-imgrel.ll @@ -3,9 +3,9 @@ @__ImageBase = external global i8 ; X64: .quad "?x@@3HA"@IMGREL -@"\01?x@@3HA" = global i64 sub nsw (i64 ptrtoint (i64* @"\01?x@@3HA" to i64), i64 ptrtoint (i8* @__ImageBase to i64)), align 8 +@"\01?x@@3HA" = global i64 sub nsw (i64 ptrtoint (ptr @"\01?x@@3HA" to i64), i64 ptrtoint (ptr @__ImageBase to i64)), align 8 declare void @f() ; X64: .quad f@IMGREL -@fp = global i64 sub nsw (i64 ptrtoint (void ()* @f to i64), i64 ptrtoint (i8* @__ImageBase to i64)), align 8 +@fp = global i64 sub nsw (i64 ptrtoint (ptr @f to i64), i64 ptrtoint (ptr @__ImageBase to i64)), align 8 diff --git a/llvm/test/MC/COFF/tricky-names.ll b/llvm/test/MC/COFF/tricky-names.ll --- a/llvm/test/MC/COFF/tricky-names.ll +++ b/llvm/test/MC/COFF/tricky-names.ll @@ -13,9 +13,9 @@ @"\01@foo.bar" = global i32 0 define weak i32 @"\01??_B?$num_put@_WV?$back_insert_iterator@V?$basic_string@_WU?$char_traits@_W@std@@V?$allocator@_W@2@@std@@@std@@@std@@51"() section ".text" { - %a = load i32, i32* @"\01??__E_Generic_object@?$_Error_objects@H@std@@YAXXZ" - %b = load i32, i32* @"\01__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4" - %c = load i32, i32* @"\01@foo.bar" + %a = load i32, ptr @"\01??__E_Generic_object@?$_Error_objects@H@std@@YAXXZ" + %b = load i32, ptr @"\01__ZL16ExceptionHandlerP19_EXCEPTION_POINTERS@4" + %c = load i32, ptr @"\01@foo.bar" %x = add i32 %a, %b %y = add i32 %x, %c ret i32 %y diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s b/llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s --- a/llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s +++ b/llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s @@ -1,6 +1,8 @@ // RUN: llvm-mc -triple aarch64 -show-encoding -disassemble -mattr=+amvs %s | FileCheck %s // RUN: llvm-mc -triple aarch64 -show-encoding -disassemble -mattr=+v8.6a -o - %s | FileCheck %s // RUN: llvm-mc -triple aarch64 -show-encoding -disassemble -o - %s | FileCheck --check-prefix=NOAMVS %s +[0xc0,0xd2,0x1b,0xd5] +[0xc0,0xd2,0x3b,0xd5] [0x00,0xd8,0x1c,0xd5] [0x20,0xd8,0x1c,0xd5] [0x40,0xd8,0x1c,0xd5] @@ -66,6 +68,8 @@ [0xc0,0xdb,0x3c,0xd5] [0xe0,0xdb,0x3c,0xd5] // CHECK: .text +// CHECK-NEXT: msr S3_3_C13_C2_6, x0 // encoding: [0xc0,0xd2,0x1b,0xd5] +// CHECK-NEXT: mrs x0, AMCG1IDR_EL0 // encoding: [0xc0,0xd2,0x3b,0xd5] // CHECK-NEXT: msr AMEVCNTVOFF00_EL2, x0 // encoding: [0x00,0xd8,0x1c,0xd5] // CHECK-NEXT: msr AMEVCNTVOFF01_EL2, x0 // encoding: [0x20,0xd8,0x1c,0xd5] // CHECK-NEXT: msr AMEVCNTVOFF02_EL2, x0 // encoding: [0x40,0xd8,0x1c,0xd5] @@ -131,6 +135,8 @@ // CHECK-NEXT: mrs x0, AMEVCNTVOFF114_EL2 // encoding: [0xc0,0xdb,0x3c,0xd5] // CHECK-NEXT: mrs x0, AMEVCNTVOFF115_EL2 // encoding: [0xe0,0xdb,0x3c,0xd5] // NOAMVS: .text +// NOAMVS-NEXT: msr S3_3_C13_C2_6, x0 // encoding: [0xc0,0xd2,0x1b,0xd5] +// NOAMVS-NEXT: mrs x0, S3_3_C13_C2_6 // encoding: [0xc0,0xd2,0x3b,0xd5] // NOAMVS-NEXT: msr S3_4_C13_C8_0, x0 // encoding: [0x00,0xd8,0x1c,0xd5] // NOAMVS-NEXT: msr S3_4_C13_C8_1, x0 // encoding: [0x20,0xd8,0x1c,0xd5] // NOAMVS-NEXT: msr S3_4_C13_C8_2, x0 // encoding: [0x40,0xd8,0x1c,0xd5] diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt b/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt --- a/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt +++ b/llvm/test/MC/Disassembler/AArch64/armv8.6a-fgt.txt @@ -6,31 +6,64 @@ [0xc0,0x11,0x1c,0xd5] [0x80,0x31,0x1c,0xd5] [0xa0,0x31,0x1c,0xd5] +[0xc0,0x31,0x1c,0xd5] # CHECK: msr HFGRTR_EL2, x0 # CHECK: msr HFGWTR_EL2, x0 # CHECK: msr HFGITR_EL2, x0 # CHECK: msr HDFGRTR_EL2, x0 # CHECK: msr HDFGWTR_EL2, x0 +# CHECK: msr HAFGRTR_EL2, x0 # NOFGT: msr S3_4_C1_C1_4, x0 # NOFGT: msr S3_4_C1_C1_5, x0 # NOFGT: msr S3_4_C1_C1_6, x0 # NOFGT: msr S3_4_C3_C1_4, x0 # NOFGT: msr S3_4_C3_C1_5, x0 +# NOFGT: msr S3_4_C3_C1_6, x0 [0x80,0x11,0x3c,0xd5] [0xa0,0x11,0x3c,0xd5] [0xc0,0x11,0x3c,0xd5] [0x80,0x31,0x3c,0xd5] [0xa0,0x31,0x3c,0xd5] +[0xc0,0x31,0x3c,0xd5] # CHECK: mrs x0, HFGRTR_EL2 # CHECK: mrs x0, HFGWTR_EL2 # CHECK: mrs x0, HFGITR_EL2 # CHECK: mrs x0, HDFGRTR_EL2 # CHECK: mrs x0, HDFGWTR_EL2 +# CHECK: mrs x0, HAFGRTR_EL2 # NOFGT: mrs x0, S3_4_C1_C1_4 # NOFGT: mrs x0, S3_4_C1_C1_5 # NOFGT: mrs x0, S3_4_C1_C1_6 # NOFGT: mrs x0, S3_4_C3_C1_4 # NOFGT: mrs x0, S3_4_C3_C1_5 +# NOFGT: mrs x0, S3_4_C3_C1_6 + +[0x03,0x31,0x3c,0xd5] +[0x23,0x31,0x3c,0xd5] +[0x43,0x31,0x3c,0xd5] +[0x63,0x31,0x3c,0xd5] +# CHECK: mrs x3, HDFGRTR2_EL2 +# CHECK: mrs x3, HDFGWTR2_EL2 +# CHECK: mrs x3, HFGRTR2_EL2 +# CHECK: mrs x3, HFGWTR2_EL2 +# NOFGT: mrs x3, S3_4_C3_C1_0 +# NOFGT: mrs x3, S3_4_C3_C1_1 +# NOFGT: mrs x3, S3_4_C3_C1_2 +# NOFGT: mrs x3, S3_4_C3_C1_3 + + +[0x03,0x31,0x1c,0xd5] +[0x23,0x31,0x1c,0xd5] +[0x43,0x31,0x1c,0xd5] +[0x63,0x31,0x1c,0xd5] +# CHECK: msr HDFGRTR2_EL2, x3 +# CHECK: msr HDFGWTR2_EL2, x3 +# CHECK: msr HFGRTR2_EL2, x3 +# CHECK: msr HFGWTR2_EL2, x3 +# NOFGT: msr S3_4_C3_C1_0, x3 +# NOFGT: msr S3_4_C3_C1_1, x3 +# NOFGT: msr S3_4_C3_C1_2, x3 +# NOFGT: msr S3_4_C3_C1_3, x3 diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-debug-pmu.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-debug-pmu.txt new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Disassembler/AArch64/armv8.9a-debug-pmu.txt @@ -0,0 +1,730 @@ +# RUN: llvm-mc -triple=aarch64 -mattr=+ite -disassemble %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+v8.8a -mattr=+ite -disassemble %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+v9.3a -mattr=+ite -disassemble %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+v8.9a -mattr=+ite -disassemble %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+v9.4a -mattr=+ite -disassemble %s | FileCheck %s + +# RUN: llvm-mc -triple=aarch64 -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE +# RUN: llvm-mc -triple=aarch64 -mattr=+v8.8a -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE +# RUN: llvm-mc -triple=aarch64 -mattr=+v9.3a -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE +# RUN: llvm-mc -triple=aarch64 -mattr=+v8.9a -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE +# RUN: llvm-mc -triple=aarch64 -mattr=+v9.4a -disassemble %s | FileCheck %s --check-prefix=ERROR-NO-ITE + +[0x83,0x00,0x30,0xd5] +# CHECK: mrs x3, DBGBVR0_EL1 +[0x81,0x00,0x10,0xd5] +# CHECK: msr DBGBVR0_EL1, x1 +[0x83,0x01,0x30,0xd5] +# CHECK: mrs x3, DBGBVR1_EL1 +[0x81,0x01,0x10,0xd5] +# CHECK: msr DBGBVR1_EL1, x1 +[0x83,0x02,0x30,0xd5] +# CHECK: mrs x3, DBGBVR2_EL1 +[0x81,0x02,0x10,0xd5] +# CHECK: msr DBGBVR2_EL1, x1 +[0x83,0x03,0x30,0xd5] +# CHECK: mrs x3, DBGBVR3_EL1 +[0x81,0x03,0x10,0xd5] +# CHECK: msr DBGBVR3_EL1, x1 +[0x83,0x04,0x30,0xd5] +# CHECK: mrs x3, DBGBVR4_EL1 +[0x81,0x04,0x10,0xd5] +# CHECK: msr DBGBVR4_EL1, x1 +[0x83,0x05,0x30,0xd5] +# CHECK: mrs x3, DBGBVR5_EL1 +[0x81,0x05,0x10,0xd5] +# CHECK: msr DBGBVR5_EL1, x1 +[0x83,0x06,0x30,0xd5] +# CHECK: mrs x3, DBGBVR6_EL1 +[0x81,0x06,0x10,0xd5] +# CHECK: msr DBGBVR6_EL1, x1 +[0x83,0x07,0x30,0xd5] +# CHECK: mrs x3, DBGBVR7_EL1 +[0x81,0x07,0x10,0xd5] +# CHECK: msr DBGBVR7_EL1, x1 +[0x83,0x08,0x30,0xd5] +# CHECK: mrs x3, DBGBVR8_EL1 +[0x81,0x08,0x10,0xd5] +# CHECK: msr DBGBVR8_EL1, x1 +[0x83,0x09,0x30,0xd5] +# CHECK: mrs x3, DBGBVR9_EL1 +[0x81,0x09,0x10,0xd5] +# CHECK: msr DBGBVR9_EL1, x1 +[0x83,0x0a,0x30,0xd5] +# CHECK: mrs x3, DBGBVR10_EL1 +[0x81,0x0a,0x10,0xd5] +# CHECK: msr DBGBVR10_EL1, x1 +[0x83,0x0b,0x30,0xd5] +# CHECK: mrs x3, DBGBVR11_EL1 +[0x81,0x0b,0x10,0xd5] +# CHECK: msr DBGBVR11_EL1, x1 +[0x83,0x0c,0x30,0xd5] +# CHECK: mrs x3, DBGBVR12_EL1 +[0x81,0x0c,0x10,0xd5] +# CHECK: msr DBGBVR12_EL1, x1 +[0x83,0x0d,0x30,0xd5] +# CHECK: mrs x3, DBGBVR13_EL1 +[0x81,0x0d,0x10,0xd5] +# CHECK: msr DBGBVR13_EL1, x1 +[0x83,0x0e,0x30,0xd5] +# CHECK: mrs x3, DBGBVR14_EL1 +[0x81,0x0e,0x10,0xd5] +# CHECK: msr DBGBVR14_EL1, x1 +[0x83,0x0f,0x30,0xd5] +# CHECK: mrs x3, DBGBVR15_EL1 +[0x81,0x0f,0x10,0xd5] +# CHECK: msr DBGBVR15_EL1, x1 + +[0xa3,0x00,0x30,0xd5] +# CHECK: mrs x3, DBGBCR0_EL1 +[0xa1,0x00,0x10,0xd5] +# CHECK: msr DBGBCR0_EL1, x1 +[0xa3,0x01,0x30,0xd5] +# CHECK: mrs x3, DBGBCR1_EL1 +[0xa1,0x01,0x10,0xd5] +# CHECK: msr DBGBCR1_EL1, x1 +[0xa3,0x02,0x30,0xd5] +# CHECK: mrs x3, DBGBCR2_EL1 +[0xa1,0x02,0x10,0xd5] +# CHECK: msr DBGBCR2_EL1, x1 +[0xa3,0x03,0x30,0xd5] +# CHECK: mrs x3, DBGBCR3_EL1 +[0xa1,0x03,0x10,0xd5] +# CHECK: msr DBGBCR3_EL1, x1 +[0xa3,0x04,0x30,0xd5] +# CHECK: mrs x3, DBGBCR4_EL1 +[0xa1,0x04,0x10,0xd5] +# CHECK: msr DBGBCR4_EL1, x1 +[0xa3,0x05,0x30,0xd5] +# CHECK: mrs x3, DBGBCR5_EL1 +[0xa1,0x05,0x10,0xd5] +# CHECK: msr DBGBCR5_EL1, x1 +[0xa3,0x06,0x30,0xd5] +# CHECK: mrs x3, DBGBCR6_EL1 +[0xa1,0x06,0x10,0xd5] +# CHECK: msr DBGBCR6_EL1, x1 +[0xa3,0x07,0x30,0xd5] +# CHECK: mrs x3, DBGBCR7_EL1 +[0xa1,0x07,0x10,0xd5] +# CHECK: msr DBGBCR7_EL1, x1 +[0xa3,0x08,0x30,0xd5] +# CHECK: mrs x3, DBGBCR8_EL1 +[0xa1,0x08,0x10,0xd5] +# CHECK: msr DBGBCR8_EL1, x1 +[0xa3,0x09,0x30,0xd5] +# CHECK: mrs x3, DBGBCR9_EL1 +[0xa1,0x09,0x10,0xd5] +# CHECK: msr DBGBCR9_EL1, x1 +[0xa3,0x0a,0x30,0xd5] +# CHECK: mrs x3, DBGBCR10_EL1 +[0xa1,0x0a,0x10,0xd5] +# CHECK: msr DBGBCR10_EL1, x1 +[0xa3,0x0b,0x30,0xd5] +# CHECK: mrs x3, DBGBCR11_EL1 +[0xa1,0x0b,0x10,0xd5] +# CHECK: msr DBGBCR11_EL1, x1 +[0xa3,0x0c,0x30,0xd5] +# CHECK: mrs x3, DBGBCR12_EL1 +[0xa1,0x0c,0x10,0xd5] +# CHECK: msr DBGBCR12_EL1, x1 +[0xa3,0x0d,0x30,0xd5] +# CHECK: mrs x3, DBGBCR13_EL1 +[0xa1,0x0d,0x10,0xd5] +# CHECK: msr DBGBCR13_EL1, x1 +[0xa3,0x0e,0x30,0xd5] +# CHECK: mrs x3, DBGBCR14_EL1 +[0xa1,0x0e,0x10,0xd5] +# CHECK: msr DBGBCR14_EL1, x1 +[0xa3,0x0f,0x30,0xd5] +# CHECK: mrs x3, DBGBCR15_EL1 +[0xa1,0x0f,0x10,0xd5] +# CHECK: msr DBGBCR15_EL1, x1 + +[0xc3,0x00,0x30,0xd5] +# CHECK: mrs x3, DBGWVR0_EL1 +[0xc1,0x00,0x10,0xd5] +# CHECK: msr DBGWVR0_EL1, x1 +[0xc3,0x01,0x30,0xd5] +# CHECK: mrs x3, DBGWVR1_EL1 +[0xc1,0x01,0x10,0xd5] +# CHECK: msr DBGWVR1_EL1, x1 +[0xc3,0x02,0x30,0xd5] +# CHECK: mrs x3, DBGWVR2_EL1 +[0xc1,0x02,0x10,0xd5] +# CHECK: msr DBGWVR2_EL1, x1 +[0xc3,0x03,0x30,0xd5] +# CHECK: mrs x3, DBGWVR3_EL1 +[0xc1,0x03,0x10,0xd5] +# CHECK: msr DBGWVR3_EL1, x1 +[0xc3,0x04,0x30,0xd5] +# CHECK: mrs x3, DBGWVR4_EL1 +[0xc1,0x04,0x10,0xd5] +# CHECK: msr DBGWVR4_EL1, x1 +[0xc3,0x05,0x30,0xd5] +# CHECK: mrs x3, DBGWVR5_EL1 +[0xc1,0x05,0x10,0xd5] +# CHECK: msr DBGWVR5_EL1, x1 +[0xc3,0x06,0x30,0xd5] +# CHECK: mrs x3, DBGWVR6_EL1 +[0xc1,0x06,0x10,0xd5] +# CHECK: msr DBGWVR6_EL1, x1 +[0xc3,0x07,0x30,0xd5] +# CHECK: mrs x3, DBGWVR7_EL1 +[0xc1,0x07,0x10,0xd5] +# CHECK: msr DBGWVR7_EL1, x1 +[0xc3,0x08,0x30,0xd5] +# CHECK: mrs x3, DBGWVR8_EL1 +[0xc1,0x08,0x10,0xd5] +# CHECK: msr DBGWVR8_EL1, x1 +[0xc3,0x09,0x30,0xd5] +# CHECK: mrs x3, DBGWVR9_EL1 +[0xc1,0x09,0x10,0xd5] +# CHECK: msr DBGWVR9_EL1, x1 +[0xc3,0x0a,0x30,0xd5] +# CHECK: mrs x3, DBGWVR10_EL1 +[0xc1,0x0a,0x10,0xd5] +# CHECK: msr DBGWVR10_EL1, x1 +[0xc3,0x0b,0x30,0xd5] +# CHECK: mrs x3, DBGWVR11_EL1 +[0xc1,0x0b,0x10,0xd5] +# CHECK: msr DBGWVR11_EL1, x1 +[0xc3,0x0c,0x30,0xd5] +# CHECK: mrs x3, DBGWVR12_EL1 +[0xc1,0x0c,0x10,0xd5] +# CHECK: msr DBGWVR12_EL1, x1 +[0xc3,0x0d,0x30,0xd5] +# CHECK: mrs x3, DBGWVR13_EL1 +[0xc1,0x0d,0x10,0xd5] +# CHECK: msr DBGWVR13_EL1, x1 +[0xc3,0x0e,0x30,0xd5] +# CHECK: mrs x3, DBGWVR14_EL1 +[0xc1,0x0e,0x10,0xd5] +# CHECK: msr DBGWVR14_EL1, x1 +[0xc3,0x0f,0x30,0xd5] +# CHECK: mrs x3, DBGWVR15_EL1 +[0xc1,0x0f,0x10,0xd5] +# CHECK: msr DBGWVR15_EL1, x1 + +[0xe3,0x00,0x30,0xd5] +# CHECK: mrs x3, DBGWCR0_EL1 +[0xe1,0x00,0x10,0xd5] +# CHECK: msr DBGWCR0_EL1, x1 +[0xe3,0x01,0x30,0xd5] +# CHECK: mrs x3, DBGWCR1_EL1 +[0xe1,0x01,0x10,0xd5] +# CHECK: msr DBGWCR1_EL1, x1 +[0xe3,0x02,0x30,0xd5] +# CHECK: mrs x3, DBGWCR2_EL1 +[0xe1,0x02,0x10,0xd5] +# CHECK: msr DBGWCR2_EL1, x1 +[0xe3,0x03,0x30,0xd5] +# CHECK: mrs x3, DBGWCR3_EL1 +[0xe1,0x03,0x10,0xd5] +# CHECK: msr DBGWCR3_EL1, x1 +[0xe3,0x04,0x30,0xd5] +# CHECK: mrs x3, DBGWCR4_EL1 +[0xe1,0x04,0x10,0xd5] +# CHECK: msr DBGWCR4_EL1, x1 +[0xe3,0x05,0x30,0xd5] +# CHECK: mrs x3, DBGWCR5_EL1 +[0xe1,0x05,0x10,0xd5] +# CHECK: msr DBGWCR5_EL1, x1 +[0xe3,0x06,0x30,0xd5] +# CHECK: mrs x3, DBGWCR6_EL1 +[0xe1,0x06,0x10,0xd5] +# CHECK: msr DBGWCR6_EL1, x1 +[0xe3,0x07,0x30,0xd5] +# CHECK: mrs x3, DBGWCR7_EL1 +[0xe1,0x07,0x10,0xd5] +# CHECK: msr DBGWCR7_EL1, x1 +[0xe3,0x08,0x30,0xd5] +# CHECK: mrs x3, DBGWCR8_EL1 +[0xe1,0x08,0x10,0xd5] +# CHECK: msr DBGWCR8_EL1, x1 +[0xe3,0x09,0x30,0xd5] +# CHECK: mrs x3, DBGWCR9_EL1 +[0xe1,0x09,0x10,0xd5] +# CHECK: msr DBGWCR9_EL1, x1 +[0xe3,0x0a,0x30,0xd5] +# CHECK: mrs x3, DBGWCR10_EL1 +[0xe1,0x0a,0x10,0xd5] +# CHECK: msr DBGWCR10_EL1, x1 +[0xe3,0x0b,0x30,0xd5] +# CHECK: mrs x3, DBGWCR11_EL1 +[0xe1,0x0b,0x10,0xd5] +# CHECK: msr DBGWCR11_EL1, x1 +[0xe3,0x0c,0x30,0xd5] +# CHECK: mrs x3, DBGWCR12_EL1 +[0xe1,0x0c,0x10,0xd5] +# CHECK: msr DBGWCR12_EL1, x1 +[0xe3,0x0d,0x30,0xd5] +# CHECK: mrs x3, DBGWCR13_EL1 +[0xe1,0x0d,0x10,0xd5] +# CHECK: msr DBGWCR13_EL1, x1 +[0xe3,0x0e,0x30,0xd5] +# CHECK: mrs x3, DBGWCR14_EL1 +[0xe1,0x0e,0x10,0xd5] +# CHECK: msr DBGWCR14_EL1, x1 +[0xe3,0x0f,0x30,0xd5] +# CHECK: mrs x3, DBGWCR15_EL1 +[0xe1,0x0f,0x10,0xd5] +# CHECK: msr DBGWCR15_EL1, x1 + +[0x43,0x04,0x30,0xd5] +# CHECK: mrs x3, MDSELR_EL1 +[0x41,0x04,0x10,0xd5] +# CHECK: msr MDSELR_EL1, x1 + +[0x83,0x9e,0x38,0xd5] +# CHECK: mrs x3, PMUACR_EL1 +[0x81,0x9e,0x18,0xd5] +# CHECK: msr PMUACR_EL1, x1 + +[0xe3,0xeb,0x30,0xd5] +# CHECK: mrs x3, PMCCNTSVR_EL1 +[0x03,0xec,0x30,0xd5] +# CHECK: mrs x3, PMICNTSVR_EL1 +[0x63,0x9d,0x38,0xd5] +# CHECK: mrs x3, PMSSCR_EL1 +[0x61,0x9d,0x18,0xd5] +# CHECK: msr PMSSCR_EL1, x1 +[0x03,0xe8,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR0_EL1 +[0x23,0xe8,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR1_EL1 +[0x43,0xe8,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR2_EL1 +[0x63,0xe8,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR3_EL1 +[0x83,0xe8,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR4_EL1 +[0xa3,0xe8,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR5_EL1 +[0xc3,0xe8,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR6_EL1 +[0xe3,0xe8,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR7_EL1 +[0x03,0xe9,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR8_EL1 +[0x23,0xe9,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR9_EL1 +[0x43,0xe9,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR10_EL1 +[0x63,0xe9,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR11_EL1 +[0x83,0xe9,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR12_EL1 +[0xa3,0xe9,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR13_EL1 +[0xc3,0xe9,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR14_EL1 +[0xe3,0xe9,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR15_EL1 +[0x03,0xea,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR16_EL1 +[0x23,0xea,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR17_EL1 +[0x43,0xea,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR18_EL1 +[0x63,0xea,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR19_EL1 +[0x83,0xea,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR20_EL1 +[0xa3,0xea,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR21_EL1 +[0xc3,0xea,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR22_EL1 +[0xe3,0xea,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR23_EL1 +[0x03,0xeb,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR24_EL1 +[0x23,0xeb,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR25_EL1 +[0x43,0xeb,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR26_EL1 +[0x63,0xeb,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR27_EL1 +[0x83,0xeb,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR28_EL1 +[0xa3,0xeb,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR29_EL1 +[0xc3,0xeb,0x30,0xd5] +# CHECK: mrs x3, PMEVCNTSVR30_EL1 + +[0x03,0x94,0x3b,0xd5] +# CHECK: mrs x3, PMICNTR_EL0 +[0x03,0x94,0x1b,0xd5] +# CHECK: msr PMICNTR_EL0, x3 +[0x03,0x96,0x3b,0xd5] +# CHECK: mrs x3, PMICFILTR_EL0 +[0x03,0x96,0x1b,0xd5] +# CHECK: msr PMICFILTR_EL0, x3 + +[0x83,0x9d,0x1b,0xd5] +# CHECK: msr PMZR_EL0, x3 + +[0xa3,0x9e,0x38,0xd5] +# CHECK: mrs x3, PMECR_EL1 +[0xa1,0x9e,0x18,0xd5] +# CHECK: msr PMECR_EL1, x1 +[0xe3,0x9e,0x38,0xd5] +# CHECK: mrs x3, PMIAR_EL1 +[0xe1,0x9e,0x18,0xd5] +# CHECK: msr PMIAR_EL1, x1 + +[0x63,0x9d,0x30,0xd5] +# CHECK: mrs x3, SPMACCESSR_EL1 +[0x61,0x9d,0x10,0xd5] +# CHECK: msr SPMACCESSR_EL1, x1 +[0x63,0x9d,0x35,0xd5] +# CHECK: mrs x3, SPMACCESSR_EL12 +[0x61,0x9d,0x15,0xd5] +# CHECK: msr SPMACCESSR_EL12, x1 +[0x63,0x9d,0x34,0xd5] +# CHECK: mrs x3, SPMACCESSR_EL2 +[0x61,0x9d,0x14,0xd5] +# CHECK: msr SPMACCESSR_EL2, x1 +[0x63,0x9d,0x36,0xd5] +# CHECK: mrs x3, SPMACCESSR_EL3 +[0x61,0x9d,0x16,0xd5] +# CHECK: msr SPMACCESSR_EL3, x1 +[0x43,0x9c,0x33,0xd5] +# CHECK: mrs x3, SPMCNTENCLR_EL0 +[0x41,0x9c,0x13,0xd5] +# CHECK: msr SPMCNTENCLR_EL0, x1 +[0x23,0x9c,0x33,0xd5] +# CHECK: mrs x3, SPMCNTENSET_EL0 +[0x21,0x9c,0x13,0xd5] +# CHECK: msr SPMCNTENSET_EL0, x1 +[0x03,0x9c,0x33,0xd5] +# CHECK: mrs x3, SPMCR_EL0 +[0x01,0x9c,0x13,0xd5] +# CHECK: msr SPMCR_EL0, x1 +[0xc3,0x9d,0x30,0xd5] +# CHECK: mrs x3, SPMDEVAFF_EL1 +[0xa3,0x9d,0x30,0xd5] +# CHECK: mrs x3, SPMDEVARCH_EL1 + +[0x03,0xe0,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR0_EL0 +[0x01,0xe0,0x13,0xd5] +# CHECK: msr SPMEVCNTR0_EL0, x1 +[0x23,0xe0,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR1_EL0 +[0x21,0xe0,0x13,0xd5] +# CHECK: msr SPMEVCNTR1_EL0, x1 +[0x43,0xe0,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR2_EL0 +[0x41,0xe0,0x13,0xd5] +# CHECK: msr SPMEVCNTR2_EL0, x1 +[0x63,0xe0,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR3_EL0 +[0x61,0xe0,0x13,0xd5] +# CHECK: msr SPMEVCNTR3_EL0, x1 +[0x83,0xe0,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR4_EL0 +[0x81,0xe0,0x13,0xd5] +# CHECK: msr SPMEVCNTR4_EL0, x1 +[0xa3,0xe0,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR5_EL0 +[0xa1,0xe0,0x13,0xd5] +# CHECK: msr SPMEVCNTR5_EL0, x1 +[0xc3,0xe0,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR6_EL0 +[0xc1,0xe0,0x13,0xd5] +# CHECK: msr SPMEVCNTR6_EL0, x1 +[0xe3,0xe0,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR7_EL0 +[0xe1,0xe0,0x13,0xd5] +# CHECK: msr SPMEVCNTR7_EL0, x1 +[0x03,0xe1,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR8_EL0 +[0x01,0xe1,0x13,0xd5] +# CHECK: msr SPMEVCNTR8_EL0, x1 +[0x23,0xe1,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR9_EL0 +[0x21,0xe1,0x13,0xd5] +# CHECK: msr SPMEVCNTR9_EL0, x1 +[0x43,0xe1,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR10_EL0 +[0x41,0xe1,0x13,0xd5] +# CHECK: msr SPMEVCNTR10_EL0, x1 +[0x63,0xe1,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR11_EL0 +[0x61,0xe1,0x13,0xd5] +# CHECK: msr SPMEVCNTR11_EL0, x1 +[0x83,0xe1,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR12_EL0 +[0x81,0xe1,0x13,0xd5] +# CHECK: msr SPMEVCNTR12_EL0, x1 +[0xa3,0xe1,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR13_EL0 +[0xa1,0xe1,0x13,0xd5] +# CHECK: msr SPMEVCNTR13_EL0, x1 +[0xc3,0xe1,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR14_EL0 +[0xc1,0xe1,0x13,0xd5] +# CHECK: msr SPMEVCNTR14_EL0, x1 +[0xe3,0xe1,0x33,0xd5] +# CHECK: mrs x3, SPMEVCNTR15_EL0 +[0xe1,0xe1,0x13,0xd5] +# CHECK: msr SPMEVCNTR15_EL0, x1 + +[0x03,0xe6,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R0_EL0 +[0x01,0xe6,0x13,0xd5] +# CHECK: msr SPMEVFILT2R0_EL0, x1 +[0x23,0xe6,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R1_EL0 +[0x21,0xe6,0x13,0xd5] +# CHECK: msr SPMEVFILT2R1_EL0, x1 +[0x43,0xe6,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R2_EL0 +[0x41,0xe6,0x13,0xd5] +# CHECK: msr SPMEVFILT2R2_EL0, x1 +[0x63,0xe6,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R3_EL0 +[0x61,0xe6,0x13,0xd5] +# CHECK: msr SPMEVFILT2R3_EL0, x1 +[0x83,0xe6,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R4_EL0 +[0x81,0xe6,0x13,0xd5] +# CHECK: msr SPMEVFILT2R4_EL0, x1 +[0xa3,0xe6,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R5_EL0 +[0xa1,0xe6,0x13,0xd5] +# CHECK: msr SPMEVFILT2R5_EL0, x1 +[0xc3,0xe6,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R6_EL0 +[0xc1,0xe6,0x13,0xd5] +# CHECK: msr SPMEVFILT2R6_EL0, x1 +[0xe3,0xe6,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R7_EL0 +[0xe1,0xe6,0x13,0xd5] +# CHECK: msr SPMEVFILT2R7_EL0, x1 +[0x03,0xe7,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R8_EL0 +[0x01,0xe7,0x13,0xd5] +# CHECK: msr SPMEVFILT2R8_EL0, x1 +[0x23,0xe7,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R9_EL0 +[0x21,0xe7,0x13,0xd5] +# CHECK: msr SPMEVFILT2R9_EL0, x1 +[0x43,0xe7,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R10_EL0 +[0x41,0xe7,0x13,0xd5] +# CHECK: msr SPMEVFILT2R10_EL0, x1 +[0x63,0xe7,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R11_EL0 +[0x61,0xe7,0x13,0xd5] +# CHECK: msr SPMEVFILT2R11_EL0, x1 +[0x83,0xe7,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R12_EL0 +[0x81,0xe7,0x13,0xd5] +# CHECK: msr SPMEVFILT2R12_EL0, x1 +[0xa3,0xe7,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R13_EL0 +[0xa1,0xe7,0x13,0xd5] +# CHECK: msr SPMEVFILT2R13_EL0, x1 +[0xc3,0xe7,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R14_EL0 +[0xc1,0xe7,0x13,0xd5] +# CHECK: msr SPMEVFILT2R14_EL0, x1 +[0xe3,0xe7,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILT2R15_EL0 +[0xe1,0xe7,0x13,0xd5] +# CHECK: msr SPMEVFILT2R15_EL0, x1 + +[0x03,0xe4,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR0_EL0 +[0x01,0xe4,0x13,0xd5] +# CHECK: msr SPMEVFILTR0_EL0, x1 +[0x23,0xe4,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR1_EL0 +[0x21,0xe4,0x13,0xd5] +# CHECK: msr SPMEVFILTR1_EL0, x1 +[0x43,0xe4,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR2_EL0 +[0x41,0xe4,0x13,0xd5] +# CHECK: msr SPMEVFILTR2_EL0, x1 +[0x63,0xe4,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR3_EL0 +[0x61,0xe4,0x13,0xd5] +# CHECK: msr SPMEVFILTR3_EL0, x1 +[0x83,0xe4,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR4_EL0 +[0x81,0xe4,0x13,0xd5] +# CHECK: msr SPMEVFILTR4_EL0, x1 +[0xa3,0xe4,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR5_EL0 +[0xa1,0xe4,0x13,0xd5] +# CHECK: msr SPMEVFILTR5_EL0, x1 +[0xc3,0xe4,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR6_EL0 +[0xc1,0xe4,0x13,0xd5] +# CHECK: msr SPMEVFILTR6_EL0, x1 +[0xe3,0xe4,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR7_EL0 +[0xe1,0xe4,0x13,0xd5] +# CHECK: msr SPMEVFILTR7_EL0, x1 +[0x03,0xe5,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR8_EL0 +[0x01,0xe5,0x13,0xd5] +# CHECK: msr SPMEVFILTR8_EL0, x1 +[0x23,0xe5,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR9_EL0 +[0x21,0xe5,0x13,0xd5] +# CHECK: msr SPMEVFILTR9_EL0, x1 +[0x43,0xe5,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR10_EL0 +[0x41,0xe5,0x13,0xd5] +# CHECK: msr SPMEVFILTR10_EL0, x1 +[0x63,0xe5,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR11_EL0 +[0x61,0xe5,0x13,0xd5] +# CHECK: msr SPMEVFILTR11_EL0, x1 +[0x83,0xe5,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR12_EL0 +[0x81,0xe5,0x13,0xd5] +# CHECK: msr SPMEVFILTR12_EL0, x1 +[0xa3,0xe5,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR13_EL0 +[0xa1,0xe5,0x13,0xd5] +# CHECK: msr SPMEVFILTR13_EL0, x1 +[0xc3,0xe5,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR14_EL0 +[0xc1,0xe5,0x13,0xd5] +# CHECK: msr SPMEVFILTR14_EL0, x1 +[0xe3,0xe5,0x33,0xd5] +# CHECK: mrs x3, SPMEVFILTR15_EL0 +[0xe1,0xe5,0x13,0xd5] +# CHECK: msr SPMEVFILTR15_EL0, x1 + +[0x03,0xe2,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER0_EL0 +[0x01,0xe2,0x13,0xd5] +# CHECK: msr SPMEVTYPER0_EL0, x1 +[0x23,0xe2,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER1_EL0 +[0x21,0xe2,0x13,0xd5] +# CHECK: msr SPMEVTYPER1_EL0, x1 +[0x43,0xe2,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER2_EL0 +[0x41,0xe2,0x13,0xd5] +# CHECK: msr SPMEVTYPER2_EL0, x1 +[0x63,0xe2,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER3_EL0 +[0x61,0xe2,0x13,0xd5] +# CHECK: msr SPMEVTYPER3_EL0, x1 +[0x83,0xe2,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER4_EL0 +[0x81,0xe2,0x13,0xd5] +# CHECK: msr SPMEVTYPER4_EL0, x1 +[0xa3,0xe2,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER5_EL0 +[0xa1,0xe2,0x13,0xd5] +# CHECK: msr SPMEVTYPER5_EL0, x1 +[0xc3,0xe2,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER6_EL0 +[0xc1,0xe2,0x13,0xd5] +# CHECK: msr SPMEVTYPER6_EL0, x1 +[0xe3,0xe2,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER7_EL0 +[0xe1,0xe2,0x13,0xd5] +# CHECK: msr SPMEVTYPER7_EL0, x1 +[0x03,0xe3,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER8_EL0 +[0x01,0xe3,0x13,0xd5] +# CHECK: msr SPMEVTYPER8_EL0, x1 +[0x23,0xe3,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER9_EL0 +[0x21,0xe3,0x13,0xd5] +# CHECK: msr SPMEVTYPER9_EL0, x1 +[0x43,0xe3,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER10_EL0 +[0x41,0xe3,0x13,0xd5] +# CHECK: msr SPMEVTYPER10_EL0, x1 +[0x63,0xe3,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER11_EL0 +[0x61,0xe3,0x13,0xd5] +# CHECK: msr SPMEVTYPER11_EL0, x1 +[0x83,0xe3,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER12_EL0 +[0x81,0xe3,0x13,0xd5] +# CHECK: msr SPMEVTYPER12_EL0, x1 +[0xa3,0xe3,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER13_EL0 +[0xa1,0xe3,0x13,0xd5] +# CHECK: msr SPMEVTYPER13_EL0, x1 +[0xc3,0xe3,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER14_EL0 +[0xc1,0xe3,0x13,0xd5] +# CHECK: msr SPMEVTYPER14_EL0, x1 +[0xe3,0xe3,0x33,0xd5] +# CHECK: mrs x3, SPMEVTYPER15_EL0 +[0xe1,0xe3,0x13,0xd5] +# CHECK: msr SPMEVTYPER15_EL0, x1 + +[0x83,0x9d,0x30,0xd5] +# CHECK: mrs x3, SPMIIDR_EL1 +[0x43,0x9e,0x30,0xd5] +# CHECK: mrs x3, SPMINTENCLR_EL1 +[0x41,0x9e,0x10,0xd5] +# CHECK: msr SPMINTENCLR_EL1, x1 +[0x23,0x9e,0x30,0xd5] +# CHECK: mrs x3, SPMINTENSET_EL1 +[0x21,0x9e,0x10,0xd5] +# CHECK: msr SPMINTENSET_EL1, x1 +[0x63,0x9c,0x33,0xd5] +# CHECK: mrs x3, SPMOVSCLR_EL0 +[0x61,0x9c,0x13,0xd5] +# CHECK: msr SPMOVSCLR_EL0, x1 +[0x63,0x9e,0x33,0xd5] +# CHECK: mrs x3, SPMOVSSET_EL0 +[0x61,0x9e,0x13,0xd5] +# CHECK: msr SPMOVSSET_EL0, x1 +[0xa3,0x9c,0x33,0xd5] +# CHECK: mrs x3, SPMSELR_EL0 +[0xa1,0x9c,0x13,0xd5] +# CHECK: msr SPMSELR_EL0, x1 +[0x03,0x9d,0x30,0xd5] +# CHECK: mrs x3, SPMCGCR0_EL1 +[0x23,0x9d,0x30,0xd5] +# CHECK: mrs x3, SPMCGCR1_EL1 +[0xe3,0x9d,0x30,0xd5] +# CHECK: mrs x3, SPMCFGR_EL1 +[0xe3,0x9e,0x36,0xd5] +# CHECK: mrs x3, SPMROOTCR_EL3 +[0xe3,0x9e,0x16,0xd5] +# CHECK: msr SPMROOTCR_EL3, x3 +[0xe3,0x9e,0x37,0xd5] +# CHECK: mrs x3, SPMSCR_EL1 +[0xe3,0x9e,0x17,0xd5] +# CHECK: msr SPMSCR_EL1, x3 + +[0x63,0x12,0x38,0xd5] +# CHECK: mrs x3, TRCITECR_EL1 +# ERROR-NO-ITE: mrs x3, S3_0_C1_C2_3 +[0x61,0x12,0x18,0xd5] +# CHECK: msr TRCITECR_EL1, x1 +# ERROR-NO-ITE: msr S3_0_C1_C2_3, x1 +[0x63,0x12,0x3d,0xd5] +# CHECK: mrs x3, TRCITECR_EL12 +# ERROR-NO-ITE: mrs x3, S3_5_C1_C2_3 +[0x61,0x12,0x1d,0xd5] +# CHECK: msr TRCITECR_EL12, x1 +# ERROR-NO-ITE: msr S3_5_C1_C2_3, x1 +[0x63,0x12,0x3c,0xd5] +# CHECK: mrs x3, TRCITECR_EL2 +# ERROR-NO-ITE: mrs x3, S3_4_C1_C2_3 +[0x61,0x12,0x1c,0xd5] +# CHECK: msr TRCITECR_EL2, x1 +# ERROR-NO-ITE: msr S3_4_C1_C2_3, x1 +[0xe1,0x72,0x0b,0xd5] +# CHECK: trcit x1 +# ERROR-NO-ITE: sys #3, c7, c2, #7, x1 + +[0x83,0x9a,0x38,0xd5] +# CHECK: mrs x3, PMSDSFR_EL1 +[0x83,0x9a,0x18,0xd5] +# CHECK: msr PMSDSFR_EL1, x3 diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt b/llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Disassembler/AArch64/armv8.9a-lrcpc3.txt @@ -0,0 +1,113 @@ +# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding -mattr=+rcpc3 < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding -mattr=+v8.9a -mattr=+rcpc3 < %s | FileCheck %s +# RUN: llvm-mc -triple aarch64-none-linux-gnu -disassemble -show-encoding -mattr=+v9.4a -mattr=+rcpc3 < %s | FileCheck %s + +# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s +# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v8.9a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s +# RUN: not llvm-mc -triple aarch64-none-linux-gnu -disassemble -mattr=+v9.4a < %s 2>&1 | FileCheck --check-prefix=ERROR-NO-RCPC3 %s + +[0x18,0x0a,0x00,0x99] +# CHECK: stilp w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0x18,0x0a,0x00,0x99] +# CHECK: stilp w24, w0, [x16, #-8]! // encoding: [0x18,0x0a,0x00,0x99] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0x39,0x0a,0x01,0xd9] +# CHECK: stilp x25, x1, [x17, #-16]! // encoding: [0x39,0x0a,0x01,0xd9] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0x39,0x0a,0x01,0xd9] +# CHECK: stilp x25, x1, [x17, #-16]! // encoding: [0x39,0x0a,0x01,0xd9] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0x5a,0x1a,0x02,0x99] +# CHECK: stilp w26, w2, [x18] // encoding: [0x5a,0x1a,0x02,0x99] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xfb,0x1b,0x03,0xd9] +# CHECK: stilp x27, x3, [sp] // encoding: [0xfb,0x1b,0x03,0xd9] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0x9c,0x0a,0x44,0x99] +# CHECK: ldiapp w28, w4, [x20], #8 // encoding: [0x9c,0x0a,0x44,0x99] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0x9c,0x0a,0x44,0x99] +# CHECK: ldiapp w28, w4, [x20], #8 // encoding: [0x9c,0x0a,0x44,0x99] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xbd,0x0a,0x45,0xd9] +# CHECK: ldiapp x29, x5, [x21], #16 // encoding: [0xbd,0x0a,0x45,0xd9] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xbd,0x0a,0x45,0xd9] +# CHECK: ldiapp x29, x5, [x21], #16 // encoding: [0xbd,0x0a,0x45,0xd9] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xfe,0x1b,0x46,0x99] +# CHECK: ldiapp w30, w6, [sp] // encoding: [0xfe,0x1b,0x46,0x99] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xff,0x1a,0x47,0xd9] +# CHECK: ldiapp xzr, x7, [x23] // encoding: [0xff,0x1a,0x47,0xd9] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding + +[0xe3,0x09,0x80,0x99] +# CHECK: stlr w3, [x15, #-4]! // encoding: [0xe3,0x09,0x80,0x99] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x09,0x80,0x99] +# CHECK: stlr w3, [x15, #-4]! // encoding: [0xe3,0x09,0x80,0x99] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x09,0x80,0xd9] +# CHECK: stlr x3, [x15, #-8]! // encoding: [0xe3,0x09,0x80,0xd9] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x0b,0x80,0xd9] +# CHECK: stlr x3, [sp, #-8]! // encoding: [0xe3,0x0b,0x80,0xd9] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x0b,0xc0,0x99] +# CHECK: ldapr w3, [sp], #4 // encoding: [0xe3,0x0b,0xc0,0x99] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x09,0xc0,0x99] +# CHECK: ldapr w3, [x15], #4 // encoding: [0xe3,0x09,0xc0,0x99] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x09,0xc0,0xd9] +# CHECK: ldapr x3, [x15], #8 // encoding: [0xe3,0x09,0xc0,0xd9] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x09,0xc0,0xd9] +# CHECK: ldapr x3, [x15], #8 // encoding: [0xe3,0x09,0xc0,0xd9] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding + +[0xe3,0xf9,0x1f,0x1d] +# CHECK: stlur b3, [x15, #-1] // encoding: [0xe3,0xf9,0x1f,0x1d] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x29,0x00,0x5d] +# CHECK: stlur h3, [x15, #2] // encoding: [0xe3,0x29,0x00,0x5d] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0xd9,0x1f,0x9d] +# CHECK: stlur s3, [x15, #-3] // encoding: [0xe3,0xd9,0x1f,0x9d] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x4b,0x00,0xdd] +# CHECK: stlur d3, [sp, #4] // encoding: [0xe3,0x4b,0x00,0xdd] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0xb9,0x9f,0x1d] +# CHECK: stlur q3, [x15, #-5] // encoding: [0xe3,0xb9,0x9f,0x1d] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x69,0x40,0x1d] +# CHECK: ldapur b3, [x15, #6] // encoding: [0xe3,0x69,0x40,0x1d] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x99,0x5f,0x5d] +# CHECK: ldapur h3, [x15, #-7] // encoding: [0xe3,0x99,0x5f,0x5d] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x89,0x40,0x9d] +# CHECK: ldapur s3, [x15, #8] // encoding: [0xe3,0x89,0x40,0x9d] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x79,0x5f,0xdd] +# CHECK: ldapur d3, [x15, #-9] // encoding: [0xe3,0x79,0x5f,0xdd] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0xab,0xc0,0x1d] +# CHECK: ldapur q3, [sp, #10] // encoding: [0xe3,0xab,0xc0,0x1d] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding + +[0xe3,0x85,0x01,0x0d] +# CHECK: stl1 { v3.d }[0], [x15] // encoding: [0xe3,0x85,0x01,0x0d] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x87,0x01,0x4d] +# CHECK: stl1 { v3.d }[1], [sp] // encoding: [0xe3,0x87,0x01,0x4d] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x87,0x41,0x0d] +# CHECK: ldap1 { v3.d }[0], [sp] // encoding: [0xe3,0x87,0x41,0x0d] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding +[0xe3,0x85,0x41,0x4d] +# CHECK: ldap1 { v3.d }[1], [x15] // encoding: [0xe3,0x85,0x41,0x4d] +# ERROR-NO-RCPC3: [[@LINE-2]]:2: warning: invalid instruction encoding diff --git a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt --- a/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -3509,6 +3509,7 @@ # CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}} # CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} # CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} +# CHECK: mrs x9, {{id_dfr1_el1|ID_DFR1_EL1}} # CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} # CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} # CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} @@ -4068,6 +4069,7 @@ 0x9 0x1 0x38 0xd5 0x29 0x1 0x38 0xd5 0x49 0x1 0x38 0xd5 +0xa9 0x3 0x38 0xd5 0x69 0x1 0x38 0xd5 0x89 0x1 0x38 0xd5 0xa9 0x1 0x38 0xd5 diff --git a/llvm/test/MC/ELF/bss.ll b/llvm/test/MC/ELF/bss.ll --- a/llvm/test/MC/ELF/bss.ll +++ b/llvm/test/MC/ELF/bss.ll @@ -4,5 +4,5 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" target triple = "i386-pc-linux-gnu" -@g0 = global i8* null, align 4 ; [#uses=0] +@g0 = global ptr null, align 4 ; [#uses=0] diff --git a/llvm/test/MC/ELF/cfi-version.ll b/llvm/test/MC/ELF/cfi-version.ll --- a/llvm/test/MC/ELF/cfi-version.ll +++ b/llvm/test/MC/ELF/cfi-version.ll @@ -10,7 +10,7 @@ ; Function Attrs: nounwind define i32 @foo() #0 !dbg !4 { entry: - %call = call i32 bitcast (i32 (...)* @bar to i32 ()*)(), !dbg !12 + %call = call i32 @bar(), !dbg !12 %add = add nsw i32 %call, 1, !dbg !12 ret i32 %add, !dbg !12 } diff --git a/llvm/test/MC/ELF/cgprofile.ll b/llvm/test/MC/ELF/cgprofile.ll --- a/llvm/test/MC/ELF/cgprofile.ll +++ b/llvm/test/MC/ELF/cgprofile.ll @@ -23,10 +23,10 @@ !0 = !{i32 5, !"CG Profile", !1} !1 = !{!2, !3, !4, !5} -!2 = !{void ()* @a, void ()* @b, i64 32} -!3 = !{void (i1)* @freq, void ()* @a, i64 11} -!4 = !{void (i1)* @freq, void ()* @b, i64 20} -!5 = !{void (i1)* @freq, null, i64 20} +!2 = !{ptr @a, ptr @b, i64 32} +!3 = !{ptr @freq, ptr @a, i64 11} +!4 = !{ptr @freq, ptr @b, i64 20} +!5 = !{ptr @freq, null, i64 20} ; CHECK: .cg_profile a, b, 32 ; CHECK: .cg_profile freq, a, 11 diff --git a/llvm/test/MC/ELF/entsize.ll b/llvm/test/MC/ELF/entsize.ll --- a/llvm/test/MC/ELF/entsize.ll +++ b/llvm/test/MC/ELF/entsize.ll @@ -8,15 +8,15 @@ @.c8b = private unnamed_addr constant [1 x i64] [i64 42] define i32 @main() nounwind { - %1 = call i32 @puts(i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0)) - %2 = call i32 @puts(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str2, i32 0, i32 0)) - call void @foo(i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.c8a, i32 0, i32 0)) - call void @foo(i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.c8b, i32 0, i32 0)) + %1 = call i32 @puts(ptr @.str1) + %2 = call i32 @puts(ptr @.str2) + call void @foo(ptr @.c8a) + call void @foo(ptr @.c8b) ret i32 0 } -declare i32 @puts(i8* nocapture) nounwind -declare void @foo(i64* nocapture) nounwind +declare i32 @puts(ptr nocapture) nounwind +declare void @foo(ptr nocapture) nounwind ;;;;; diff --git a/llvm/test/MC/ELF/section-relro.ll b/llvm/test/MC/ELF/section-relro.ll --- a/llvm/test/MC/ELF/section-relro.ll +++ b/llvm/test/MC/ELF/section-relro.ll @@ -5,7 +5,7 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux" -@funcs_relro = hidden constant [2 x i32 ()*] [i32 ()* bitcast (i32 (...)* @func1 to i32 ()*), i32 ()* bitcast (i32 (...)* @func2 to i32 ()*)], align 16 #0 +@funcs_relro = hidden constant [2 x ptr] [ptr @func1, ptr @func2], align 16 #0 @var_data = hidden global i32 33, align 4 #0 declare i32 @func1(...) @@ -15,13 +15,13 @@ define hidden i32 @foo(i32 %i) { entry: %i.addr = alloca i32, align 4 - store i32 %i, i32* %i.addr, align 4 - %0 = load i32, i32* %i.addr, align 4 + store i32 %i, ptr %i.addr, align 4 + %0 = load i32, ptr %i.addr, align 4 %idxprom = sext i32 %0 to i64 - %arrayidx = getelementptr inbounds [2 x i32 ()*], [2 x i32 ()*]* @funcs_relro, i64 0, i64 %idxprom - %1 = load i32 ()*, i32 ()** %arrayidx, align 8 + %arrayidx = getelementptr inbounds [2 x ptr], ptr @funcs_relro, i64 0, i64 %idxprom + %1 = load ptr, ptr %arrayidx, align 8 %call = call i32 %1() - %2 = load i32, i32* @var_data, align 4 + %2 = load i32, ptr @var_data, align 4 %add = add nsw i32 %call, %2 ret i32 %add } diff --git a/llvm/test/MC/Hexagon/extended_relocations.ll b/llvm/test/MC/Hexagon/extended_relocations.ll --- a/llvm/test/MC/Hexagon/extended_relocations.ll +++ b/llvm/test/MC/Hexagon/extended_relocations.ll @@ -9,12 +9,12 @@ @.str = private unnamed_addr constant [10 x i8] c"cxfir.log\00", align 1 -declare i32 @printf(i8*, ...) #1 +declare i32 @printf(ptr, ...) #1 ; Function Attrs: nounwind define i32 @main() #0 { entry: - %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([10 x i8], [10 x i8]* @.str, i32 0, i32 0)) + %call = call i32 (ptr, ...) @printf(ptr @.str) ret i32 0 } diff --git a/llvm/test/MC/MachO/AArch64/cstexpr-gotpcrel.ll b/llvm/test/MC/MachO/AArch64/cstexpr-gotpcrel.ll --- a/llvm/test/MC/MachO/AArch64/cstexpr-gotpcrel.ll +++ b/llvm/test/MC/MachO/AArch64/cstexpr-gotpcrel.ll @@ -7,10 +7,10 @@ %struct.anon = type { i32, i32 } @localfoo = global i32 42 -@localgotequiv = private unnamed_addr constant i32* @localfoo +@localgotequiv = private unnamed_addr constant ptr @localfoo @extfoo = external global i32 -@extgotequiv = private unnamed_addr constant i32* @extfoo +@extgotequiv = private unnamed_addr constant ptr @extfoo ; Don't replace GOT equivalent usage within instructions and emit the GOT ; equivalent since it can't be replaced by the GOT entry. @bargotequiv is @@ -19,7 +19,7 @@ ; CHECK: l_bargotequiv: ; CHECK-NEXT: .quad _extbar @extbar = external global i32 -@bargotequiv = private unnamed_addr constant i32* @extbar +@bargotequiv = private unnamed_addr constant ptr @extbar @table = global [4 x %struct.data] [ ; CHECK-LABEL: _table @@ -31,8 +31,8 @@ ; CHECK-NEXT: Ltmp0: ; CHECK-NEXT: .long _localfoo@GOT-Ltmp0 %struct.data { i32 4, %struct.anon { i32 5, - i32 trunc (i64 sub (i64 ptrtoint (i32** @localgotequiv to i64), - i64 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i64 1, i32 1, i32 1) to i64)) + i32 trunc (i64 sub (i64 ptrtoint (ptr @localgotequiv to i64), + i64 ptrtoint (ptr getelementptr inbounds ([4 x %struct.data], ptr @table, i32 0, i64 1, i32 1, i32 1) to i64)) to i32)} }, @@ -41,8 +41,8 @@ ; CHECK-NEXT: Ltmp1: ; CHECK-NEXT: _extfoo@GOT-Ltmp1 %struct.data { i32 4, %struct.anon { i32 5, - i32 trunc (i64 sub (i64 ptrtoint (i32** @extgotequiv to i64), - i64 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i64 2, i32 1, i32 1) to i64)) + i32 trunc (i64 sub (i64 ptrtoint (ptr @extgotequiv to i64), + i64 ptrtoint (ptr getelementptr inbounds ([4 x %struct.data], ptr @table, i32 0, i64 2, i32 1, i32 1) to i64)) to i32)} }, ; Test support for arbitrary constants into the GOTPCREL offset, which is @@ -51,8 +51,8 @@ ; CHECK: .long 5 ; CHECK-NEXT: .long ((l_extgotequiv-_table)-44)+24 %struct.data { i32 4, %struct.anon { i32 5, - i32 add (i32 trunc (i64 sub (i64 ptrtoint (i32** @extgotequiv to i64), - i64 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i64 3, i32 1, i32 1) to i64)) + i32 add (i32 trunc (i64 sub (i64 ptrtoint (ptr @extgotequiv to i64), + i64 ptrtoint (ptr getelementptr inbounds ([4 x %struct.data], ptr @table, i32 0, i64 3, i32 1, i32 1) to i64)) to i32), i32 24)} } ], align 16 @@ -62,19 +62,19 @@ ; CHECK-LABEL: _delta ; CHECK: Ltmp2: ; CHECK-NEXT: .long _extfoo@GOT-Ltmp2 -@delta = global i32 trunc (i64 sub (i64 ptrtoint (i32** @extgotequiv to i64), - i64 ptrtoint (i32* @delta to i64)) +@delta = global i32 trunc (i64 sub (i64 ptrtoint (ptr @extgotequiv to i64), + i64 ptrtoint (ptr @delta to i64)) to i32) ; CHECK-LABEL: _deltaplus: ; CHECK: .long (l_localgotequiv-_deltaplus)+55 -@deltaplus = global i32 add (i32 trunc (i64 sub (i64 ptrtoint (i32** @localgotequiv to i64), - i64 ptrtoint (i32* @deltaplus to i64)) +@deltaplus = global i32 add (i32 trunc (i64 sub (i64 ptrtoint (ptr @localgotequiv to i64), + i64 ptrtoint (ptr @deltaplus to i64)) to i32), i32 55) define i32 @t0(i32 %a) { - %x = add i32 trunc (i64 sub (i64 ptrtoint (i32** @bargotequiv to i64), - i64 ptrtoint (i32 (i32)* @t0 to i64)) + %x = add i32 trunc (i64 sub (i64 ptrtoint (ptr @bargotequiv to i64), + i64 ptrtoint (ptr @t0 to i64)) to i32), %a ret i32 %x } diff --git a/llvm/test/MC/MachO/ARM/cstexpr-gotpcrel.ll b/llvm/test/MC/MachO/ARM/cstexpr-gotpcrel.ll --- a/llvm/test/MC/MachO/ARM/cstexpr-gotpcrel.ll +++ b/llvm/test/MC/MachO/ARM/cstexpr-gotpcrel.ll @@ -12,10 +12,10 @@ ; GOT-EQUIV-NOT: _localgotequiv ; GOT-EQUIV-NOT: _extgotequiv @localfoo = global i32 42 -@localgotequiv = private unnamed_addr constant i32* @localfoo +@localgotequiv = private unnamed_addr constant ptr @localfoo @extfoo = external global i32 -@extgotequiv = private unnamed_addr constant i32* @extfoo +@extgotequiv = private unnamed_addr constant ptr @extfoo ; Don't replace GOT equivalent usage within instructions and emit the GOT ; equivalent since it can't be replaced by the GOT entry. @bargotequiv is @@ -24,7 +24,7 @@ ; CHECK: l_bargotequiv: ; CHECK-NEXT: .long _extbar @extbar = external global i32 -@bargotequiv = private unnamed_addr constant i32* @extbar +@bargotequiv = private unnamed_addr constant ptr @extbar @table = global [4 x %struct.data] [ ; CHECK-LABEL: _table @@ -34,23 +34,23 @@ ; CHECK-NOT: l_localgotequiv-(_table+20) ; CHECK-NEXT: L_localfoo$non_lazy_ptr-(_table+20) %struct.data { i32 4, %struct.anon { i32 5, - i32 sub (i32 ptrtoint (i32** @localgotequiv to i32), - i32 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i32 1, i32 1, i32 1) to i32))} + i32 sub (i32 ptrtoint (ptr @localgotequiv to i32), + i32 ptrtoint (ptr getelementptr inbounds ([4 x %struct.data], ptr @table, i32 0, i32 1, i32 1, i32 1) to i32))} }, ; CHECK: .long 5 ; CHECK-NOT: l_extgotequiv-(_table+32) ; CHECK-NEXT: L_extfoo$non_lazy_ptr-(_table+32) %struct.data { i32 4, %struct.anon { i32 5, - i32 sub (i32 ptrtoint (i32** @extgotequiv to i32), - i32 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i32 2, i32 1, i32 1) to i32))} + i32 sub (i32 ptrtoint (ptr @extgotequiv to i32), + i32 ptrtoint (ptr getelementptr inbounds ([4 x %struct.data], ptr @table, i32 0, i32 2, i32 1, i32 1) to i32))} }, ; Test support for arbitrary constants into the GOTPCREL offset ; CHECK: .long 5 ; CHECK-NOT: (l_extgotequiv-(_table+44))+24 ; CHECK-NEXT: L_extfoo$non_lazy_ptr-(_table+20) %struct.data { i32 4, %struct.anon { i32 5, - i32 add (i32 sub (i32 ptrtoint (i32** @extgotequiv to i32), - i32 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i32 3, i32 1, i32 1) to i32)), + i32 add (i32 sub (i32 ptrtoint (ptr @extgotequiv to i32), + i32 ptrtoint (ptr getelementptr inbounds ([4 x %struct.data], ptr @table, i32 0, i32 3, i32 1, i32 1) to i32)), i32 24)} } ], align 16 @@ -58,17 +58,17 @@ ; Test multiple uses of GOT equivalents. ; CHECK-LABEL: _delta ; CHECK: .long L_extfoo$non_lazy_ptr-_delta -@delta = global i32 sub (i32 ptrtoint (i32** @extgotequiv to i32), - i32 ptrtoint (i32* @delta to i32)) +@delta = global i32 sub (i32 ptrtoint (ptr @extgotequiv to i32), + i32 ptrtoint (ptr @delta to i32)) ; CHECK-LABEL: _deltaplus: ; CHECK: .long L_localfoo$non_lazy_ptr-(_deltaplus-55) -@deltaplus = global i32 add (i32 sub (i32 ptrtoint (i32** @localgotequiv to i32), - i32 ptrtoint (i32* @deltaplus to i32)), +@deltaplus = global i32 add (i32 sub (i32 ptrtoint (ptr @localgotequiv to i32), + i32 ptrtoint (ptr @deltaplus to i32)), i32 55) define i32 @t0(i32 %a) { - %x = add i32 sub (i32 ptrtoint (i32** @bargotequiv to i32), - i32 ptrtoint (i32 (i32)* @t0 to i32)), %a + %x = add i32 sub (i32 ptrtoint (ptr @bargotequiv to i32), + i32 ptrtoint (ptr @t0 to i32)), %a ret i32 %x } diff --git a/llvm/test/MC/MachO/ARM/no-tls-assert.ll b/llvm/test/MC/MachO/ARM/no-tls-assert.ll --- a/llvm/test/MC/MachO/ARM/no-tls-assert.ll +++ b/llvm/test/MC/MachO/ARM/no-tls-assert.ll @@ -5,8 +5,8 @@ target triple = "thumbv7-apple-ios9.0.0" @b = external thread_local global i32 -define i32* @func(i32 %a) !dbg !9 { - ret i32* @b +define ptr @func(i32 %a) !dbg !9 { + ret ptr @b } !llvm.dbg.cu = !{!0} diff --git a/llvm/test/MC/MachO/cgprofile.ll b/llvm/test/MC/MachO/cgprofile.ll --- a/llvm/test/MC/MachO/cgprofile.ll +++ b/llvm/test/MC/MachO/cgprofile.ll @@ -23,10 +23,10 @@ !0 = !{i32 5, !"CG Profile", !1} !1 = !{!2, !3, !4, !5} -!2 = !{void ()* @a, void ()* @b, i64 32} -!3 = !{void (i1)* @freq, void ()* @a, i64 11} -!4 = !{void (i1)* @freq, void ()* @b, i64 20} -!5 = !{void (i1)* @freq, null, i64 20} +!2 = !{ptr @a, ptr @b, i64 32} +!3 = !{ptr @freq, ptr @a, i64 11} +!4 = !{ptr @freq, ptr @b, i64 20} +!5 = !{ptr @freq, null, i64 20} ; CHECK: .cg_profile _a, _b, 32 ; CHECK: .cg_profile _freq, _a, 11 diff --git a/llvm/test/MC/MachO/cstexpr-gotpcrel-32.ll b/llvm/test/MC/MachO/cstexpr-gotpcrel-32.ll --- a/llvm/test/MC/MachO/cstexpr-gotpcrel-32.ll +++ b/llvm/test/MC/MachO/cstexpr-gotpcrel-32.ll @@ -12,10 +12,10 @@ ; GOT-EQUIV-NOT: _localgotequiv ; GOT-EQUIV-NOT: _extgotequiv @localfoo = global i32 42 -@localgotequiv = private unnamed_addr constant i32* @localfoo +@localgotequiv = private unnamed_addr constant ptr @localfoo @extfoo = external global i32 -@extgotequiv = private unnamed_addr constant i32* @extfoo +@extgotequiv = private unnamed_addr constant ptr @extfoo ; Don't replace GOT equivalent usage within instructions and emit the GOT ; equivalent since it can't be replaced by the GOT entry. @bargotequiv is @@ -24,7 +24,7 @@ ; CHECK: l_bargotequiv: ; CHECK-NEXT: .long _extbar @extbar = external global i32 -@bargotequiv = private unnamed_addr constant i32* @extbar +@bargotequiv = private unnamed_addr constant ptr @extbar @table = global [4 x %struct.data] [ ; CHECK-LABEL: _table @@ -34,23 +34,23 @@ ; CHECK-NOT: l_localgotequiv-(_table+20) ; CHECK-NEXT: L_localfoo$non_lazy_ptr-(_table+20) %struct.data { i32 4, %struct.anon { i32 5, - i32 sub (i32 ptrtoint (i32** @localgotequiv to i32), - i32 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i32 1, i32 1, i32 1) to i32))} + i32 sub (i32 ptrtoint (ptr @localgotequiv to i32), + i32 ptrtoint (ptr getelementptr inbounds ([4 x %struct.data], ptr @table, i32 0, i32 1, i32 1, i32 1) to i32))} }, ; CHECK: .long 5 ; CHECK-NOT: l_extgotequiv-(_table+32) ; CHECK-NEXT: L_extfoo$non_lazy_ptr-(_table+32) %struct.data { i32 4, %struct.anon { i32 5, - i32 sub (i32 ptrtoint (i32** @extgotequiv to i32), - i32 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i32 2, i32 1, i32 1) to i32))} + i32 sub (i32 ptrtoint (ptr @extgotequiv to i32), + i32 ptrtoint (ptr getelementptr inbounds ([4 x %struct.data], ptr @table, i32 0, i32 2, i32 1, i32 1) to i32))} }, ; Test support for arbitrary constants into the GOTPCREL offset ; CHECK: .long 5 ; CHECK-NOT: (l_extgotequiv-(_table+44))+24 ; CHECK-NEXT: L_extfoo$non_lazy_ptr-(_table+20) %struct.data { i32 4, %struct.anon { i32 5, - i32 add (i32 sub (i32 ptrtoint (i32** @extgotequiv to i32), - i32 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i32 3, i32 1, i32 1) to i32)), + i32 add (i32 sub (i32 ptrtoint (ptr @extgotequiv to i32), + i32 ptrtoint (ptr getelementptr inbounds ([4 x %struct.data], ptr @table, i32 0, i32 3, i32 1, i32 1) to i32)), i32 24)} } ], align 16 @@ -58,18 +58,18 @@ ; Test multiple uses of GOT equivalents. ; CHECK-LABEL: _delta ; CHECK: .long L_extfoo$non_lazy_ptr-_delta -@delta = global i32 sub (i32 ptrtoint (i32** @extgotequiv to i32), - i32 ptrtoint (i32* @delta to i32)) +@delta = global i32 sub (i32 ptrtoint (ptr @extgotequiv to i32), + i32 ptrtoint (ptr @delta to i32)) ; CHECK-LABEL: _deltaplus: ; CHECK: .long L_localfoo$non_lazy_ptr-(_deltaplus-55) -@deltaplus = global i32 add (i32 sub (i32 ptrtoint (i32** @localgotequiv to i32), - i32 ptrtoint (i32* @deltaplus to i32)), +@deltaplus = global i32 add (i32 sub (i32 ptrtoint (ptr @localgotequiv to i32), + i32 ptrtoint (ptr @deltaplus to i32)), i32 55) define i32 @t0(i32 %a) { - %x = add i32 sub (i32 ptrtoint (i32** @bargotequiv to i32), - i32 ptrtoint (i32 (i32)* @t0 to i32)), %a + %x = add i32 sub (i32 ptrtoint (ptr @bargotequiv to i32), + i32 ptrtoint (ptr @t0 to i32)), %a ret i32 %x } @@ -77,13 +77,13 @@ ; CHECK-LABEL: _localindirect ; CHECK: .long 65603 @localindirect = internal constant i32 65603 -@got.localindirect = private unnamed_addr constant i32* @localindirect +@got.localindirect = private unnamed_addr constant ptr @localindirect ; CHECK-LABEL: _localindirectuser: ; CHECK: .long L_localindirect$non_lazy_ptr-_localindirectuser @localindirectuser = internal constant - i32 sub (i32 ptrtoint (i32** @got.localindirect to i32), - i32 ptrtoint (i32* @localindirectuser to i32)) + i32 sub (i32 ptrtoint (ptr @got.localindirect to i32), + i32 ptrtoint (ptr @localindirectuser to i32)) ; Test internal indirect local symbols where the user doesn't see the ; definition of the other symbols yet. @@ -95,14 +95,14 @@ ; CHECK-LABEL: _undeflocalindirectuser: ; CHECK: .long L_undeflocalindirect$non_lazy_ptr-_undeflocalindirectuser @undeflocalindirectuser = internal constant - i32 sub (i32 ptrtoint (i32** @got.undeflocalindirect to i32), - i32 ptrtoint (i32* @undeflocalindirectuser to i32)), + i32 sub (i32 ptrtoint (ptr @got.undeflocalindirect to i32), + i32 ptrtoint (ptr @undeflocalindirectuser to i32)), section "__TEXT,__const" ; CHECK-LABEL: _undeflocalindirect: ; CHECK: .long 65603 @undeflocalindirect = internal constant i32 65603 -@got.undeflocalindirect = private unnamed_addr constant i32* @undeflocalindirect +@got.undeflocalindirect = private unnamed_addr constant ptr @undeflocalindirect ; CHECK-LABEL: .section __IMPORT,__pointers diff --git a/llvm/test/MC/MachO/cstexpr-gotpcrel-64.ll b/llvm/test/MC/MachO/cstexpr-gotpcrel-64.ll --- a/llvm/test/MC/MachO/cstexpr-gotpcrel-64.ll +++ b/llvm/test/MC/MachO/cstexpr-gotpcrel-64.ll @@ -14,10 +14,10 @@ ; X86-GOT-EQUIV-NOT: L_localgotequiv ; X86-GOT-EQUIV-NOT: l_extgotequiv @localfoo = global i32 42 -@localgotequiv = private unnamed_addr constant i32* @localfoo +@localgotequiv = private unnamed_addr constant ptr @localfoo @extfoo = external global i32 -@extgotequiv = private unnamed_addr constant i32* @extfoo +@extgotequiv = private unnamed_addr constant ptr @extfoo ; Don't replace GOT equivalent usage within instructions and emit the GOT ; equivalent since it can't be replaced by the GOT entry. @bargotequiv is @@ -26,7 +26,7 @@ ; X86: l_bargotequiv: ; X86-NEXT: .quad _extbar @extbar = external global i32 -@bargotequiv = private unnamed_addr constant i32* @extbar +@bargotequiv = private unnamed_addr constant ptr @extbar @table = global [4 x %struct.data] [ %struct.data { i32 1, %struct.anon { i32 2, i32 3 } }, @@ -36,16 +36,16 @@ ; X86-NOT: .long _localgotequiv-(_table+20) ; X86-NEXT: .long _localfoo@GOTPCREL+4 %struct.data { i32 4, %struct.anon { i32 5, - i32 trunc (i64 sub (i64 ptrtoint (i32** @localgotequiv to i64), - i64 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i64 1, i32 1, i32 1) to i64)) + i32 trunc (i64 sub (i64 ptrtoint (ptr @localgotequiv to i64), + i64 ptrtoint (ptr getelementptr inbounds ([4 x %struct.data], ptr @table, i32 0, i64 1, i32 1, i32 1) to i64)) to i32)} }, ; X86: .long 5 ; X86-NOT: _extgotequiv-(_table+32) ; X86-NEXT: .long _extfoo@GOTPCREL+4 %struct.data { i32 4, %struct.anon { i32 5, - i32 trunc (i64 sub (i64 ptrtoint (i32** @extgotequiv to i64), - i64 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i64 2, i32 1, i32 1) to i64)) + i32 trunc (i64 sub (i64 ptrtoint (ptr @extgotequiv to i64), + i64 ptrtoint (ptr getelementptr inbounds ([4 x %struct.data], ptr @table, i32 0, i64 2, i32 1, i32 1) to i64)) to i32)} }, ; Test support for arbitrary constants into the GOTPCREL offset. @@ -54,8 +54,8 @@ ; X86-NOT: _extgotequiv-(_table+44) ; X86-NEXT: .long _extfoo@GOTPCREL+28 %struct.data { i32 4, %struct.anon { i32 5, - i32 add (i32 trunc (i64 sub (i64 ptrtoint (i32** @extgotequiv to i64), - i64 ptrtoint (i32* getelementptr inbounds ([4 x %struct.data], [4 x %struct.data]* @table, i32 0, i64 3, i32 1, i32 1) to i64)) + i32 add (i32 trunc (i64 sub (i64 ptrtoint (ptr @extgotequiv to i64), + i64 ptrtoint (ptr getelementptr inbounds ([4 x %struct.data], ptr @table, i32 0, i64 3, i32 1, i32 1) to i64)) to i32), i32 24)} } ], align 16 @@ -64,38 +64,38 @@ ; X86-LABEL: _delta ; X86: .long _extfoo@GOTPCREL+4 -@delta = global i32 trunc (i64 sub (i64 ptrtoint (i32** @extgotequiv to i64), - i64 ptrtoint (i32* @delta to i64)) +@delta = global i32 trunc (i64 sub (i64 ptrtoint (ptr @extgotequiv to i64), + i64 ptrtoint (ptr @delta to i64)) to i32) ; X86-LABEL: _deltaplus: ; X86: .long _localfoo@GOTPCREL+59 -@deltaplus = global i32 add (i32 trunc (i64 sub (i64 ptrtoint (i32** @localgotequiv to i64), - i64 ptrtoint (i32* @deltaplus to i64)) +@deltaplus = global i32 add (i32 trunc (i64 sub (i64 ptrtoint (ptr @localgotequiv to i64), + i64 ptrtoint (ptr @deltaplus to i64)) to i32), i32 55) define i32 @t0(i32 %a) { - %x = add i32 trunc (i64 sub (i64 ptrtoint (i32** @bargotequiv to i64), - i64 ptrtoint (i32 (i32)* @t0 to i64)) + %x = add i32 trunc (i64 sub (i64 ptrtoint (ptr @bargotequiv to i64), + i64 ptrtoint (ptr @t0 to i64)) to i32), %a ret i32 %x } ; Also test direct instruction uses. -define i32** @t1() { - ret i32** @bargotequiv +define ptr @t1() { + ret ptr @bargotequiv } ; Do not crash when a pattern cannot be matched as a GOT equivalent define void @foo() { ; X86-NOGOT-EQUIV-LABEL: _foo: ; X86-NOGOT-EQUIV: leaq _b(%rip), %rax - store i8** @b, i8*** null + store ptr @b, ptr null ret void } @a = external global i8 -@b = internal unnamed_addr constant i8* @a +@b = internal unnamed_addr constant ptr @a ; X86-NOGOT-EQUIV-LABEL: _c: ; X86-NOGOT-EQUIV: .quad _b -@c = global i8** @b +@c = global ptr @b diff --git a/llvm/test/MC/MachO/tlv-bss.ll b/llvm/test/MC/MachO/tlv-bss.ll --- a/llvm/test/MC/MachO/tlv-bss.ll +++ b/llvm/test/MC/MachO/tlv-bss.ll @@ -15,24 +15,24 @@ ; Generated from this C++ source ; template ; struct Tls { -; static __thread void* val; +; static __thread ptr val; ; }; -; template __thread void* Tls::val; +; template __thread ptr Tls::val; -; void* f(int x) { +; ptr f(int x) { ; return Tls::val; ; } -@_ZN3TlsIlE3valE = weak_odr thread_local global i8* null, align 8 +@_ZN3TlsIlE3valE = weak_odr thread_local global ptr null, align 8 ; Function Attrs: nounwind ssp uwtable -define i8* @_Z1fi(i32 %x) #0 { +define ptr @_Z1fi(i32 %x) #0 { entry: %x.addr = alloca i32, align 4 - store i32 %x, i32* %x.addr, align 4 - %0 = load i8*, i8** @_ZN3TlsIlE3valE, align 8 - ret i8* %0 + store i32 %x, ptr %x.addr, align 4 + %0 = load ptr, ptr @_ZN3TlsIlE3valE, align 8 + ret ptr %0 } attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/MC/Mips/elf-bigendian.ll b/llvm/test/MC/Mips/elf-bigendian.ll --- a/llvm/test/MC/Mips/elf-bigendian.ll +++ b/llvm/test/MC/Mips/elf-bigendian.ll @@ -43,18 +43,18 @@ define i32 @main() nounwind { entry: - %0 = load i32, i32* @x, align 4 + %0 = load i32, ptr @x, align 4 %tobool = icmp eq i32 %0, 0 br i1 %tobool, label %if.end, label %foo if.end: ; preds = %entry - %puts = tail call i32 @puts(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @str, i32 0, i32 0)) + %puts = tail call i32 @puts(ptr @str) br label %foo foo: ; preds = %entry, %if.end - %puts2 = tail call i32 @puts(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @str2, i32 0, i32 0)) + %puts2 = tail call i32 @puts(ptr @str2) ret i32 0 } -declare i32 @puts(i8* nocapture) nounwind +declare i32 @puts(ptr nocapture) nounwind diff --git a/llvm/test/MC/Mips/sym-offset.ll b/llvm/test/MC/Mips/sym-offset.ll --- a/llvm/test/MC/Mips/sym-offset.ll +++ b/llvm/test/MC/Mips/sym-offset.ll @@ -17,10 +17,10 @@ ; CHECK: 0000: 00001C3C 00009C27 21E09903 0000828F ; CHECK-NEXT: 0010: 0E004188 0B004198 - %call = tail call i32 @memcmp(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @string1, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8], [10 x i8]* @string2, i32 0, i32 0), i32 4) nounwind readonly + %call = tail call i32 @memcmp(ptr @string1, ptr @string2, i32 4) nounwind readonly %cmp = icmp eq i32 %call, 0 %conv = zext i1 %cmp to i32 ret i32 %conv } -declare i32 @memcmp(i8* nocapture, i8* nocapture, i32) nounwind readonly +declare i32 @memcmp(ptr nocapture, ptr nocapture, i32) nounwind readonly diff --git a/llvm/test/MC/RISCV/compress-rv32d.s b/llvm/test/MC/RISCV/compress-rv32d.s --- a/llvm/test/MC/RISCV/compress-rv32d.s +++ b/llvm/test/MC/RISCV/compress-rv32d.s @@ -8,6 +8,16 @@ # RUN: llvm-mc -triple riscv32 -mattr=+c,+d -filetype=obj < %s \ # RUN: | llvm-objdump --triple=riscv32 --mattr=+c,+d -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s +# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcd,+d -show-encoding < %s \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-ALIAS %s +# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcd,+d -show-encoding \ +# RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcd,+d -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+experimental-zcd,+d -d - \ +# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s +# RUN: llvm-mc -triple riscv32 -mattr=+experimental-zcd,+d -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv32 --mattr=+experimental-zcd,+d -d -M no-aliases - \ +# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s # RUN: llvm-mc -triple riscv64 -mattr=+c,+d -show-encoding < %s \ # RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s @@ -19,6 +29,16 @@ # RUN: llvm-mc -triple riscv64 -mattr=+c,+d -filetype=obj < %s \ # RUN: | llvm-objdump --triple=riscv64 --mattr=+c,+d -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s +# RUN: llvm-mc -triple riscv64 -mattr=+experimental-zcd,+d -show-encoding < %s \ +# RUN: | FileCheck -check-prefixes=CHECK-ALIAS %s +# RUN: llvm-mc -triple riscv64 -mattr=+experimental-zcd,+d -show-encoding \ +# RUN: -riscv-no-aliases < %s | FileCheck -check-prefixes=CHECK-INST %s +# RUN: llvm-mc -triple riscv64 -mattr=+experimental-zcd,+d -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv64 --mattr=+experimental-zcd,+d -d - \ +# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-ALIAS %s +# RUN: llvm-mc -triple riscv64 -mattr=+experimental-zcd,+d -filetype=obj < %s \ +# RUN: | llvm-objdump --triple=riscv64 --mattr=+experimental-zcd,+d -d -M no-aliases - \ +# RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s # Tests double precision floating point instructions available in rv32 and in rv64. diff --git a/llvm/test/MC/RISCV/rv32dc-valid.s b/llvm/test/MC/RISCV/rv32dc-valid.s --- a/llvm/test/MC/RISCV/rv32dc-valid.s +++ b/llvm/test/MC/RISCV/rv32dc-valid.s @@ -3,31 +3,39 @@ # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c,+d < %s \ # RUN: | llvm-objdump --mattr=+c,+d -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zcd,+d -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zcd,+d < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zcd,+d -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # # RUN: not llvm-mc -triple riscv32 -mattr=+c \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s +# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zcd \ +# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s # RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-DC %s # CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp) # CHECK-ASM: encoding: [0x7e,0x34] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fldsp fs0, 504(sp) # CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp) # CHECK-ASM: encoding: [0xc6,0xbf] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsdsp fa7, 504(sp) # CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5) # CHECK-ASM: encoding: [0xf4,0x3f] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fld fa3, 248(a5) # CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1) # CHECK-ASM: encoding: [0xf0,0xbd] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsd fa2, 248(a1) diff --git a/llvm/test/MC/RISCV/rv64dc-valid.s b/llvm/test/MC/RISCV/rv64dc-valid.s --- a/llvm/test/MC/RISCV/rv64dc-valid.s +++ b/llvm/test/MC/RISCV/rv64dc-valid.s @@ -3,31 +3,39 @@ # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c,+d < %s \ # RUN: | llvm-objdump --mattr=+c,+d -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zcd,+d -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zcd,+d < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zcd,+d -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # # RUN: not llvm-mc -triple riscv64 -mattr=+c \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s +# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zcd \ +# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s # RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-DC %s # CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp) # CHECK-ASM: encoding: [0x7e,0x34] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fldsp fs0, 504(sp) # CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp) # CHECK-ASM: encoding: [0xc6,0xbf] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsdsp fa7, 504(sp) # CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5) # CHECK-ASM: encoding: [0xf4,0x3f] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fld fa3, 248(a5) # CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1) # CHECK-ASM: encoding: [0xf0,0xbd] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsd fa2, 248(a1) diff --git a/llvm/test/MC/WebAssembly/blockaddress.ll b/llvm/test/MC/WebAssembly/blockaddress.ll --- a/llvm/test/MC/WebAssembly/blockaddress.ll +++ b/llvm/test/MC/WebAssembly/blockaddress.ll @@ -4,7 +4,7 @@ target triple = "wasm32-unknown-unknown" -@foo = internal global i8* blockaddress(@bar, %addr), align 4 +@foo = internal global ptr blockaddress(@bar, %addr), align 4 define hidden i32 @bar() #0 { entry: diff --git a/llvm/test/MC/WebAssembly/bss.ll b/llvm/test/MC/WebAssembly/bss.ll --- a/llvm/test/MC/WebAssembly/bss.ll +++ b/llvm/test/MC/WebAssembly/bss.ll @@ -2,7 +2,7 @@ target triple = "wasm32-unknown-unknown" -@g0 = global i8* null, align 4 +@g0 = global ptr null, align 4 @g1 = global i32 0, align 4 %union.u1 = type {} diff --git a/llvm/test/MC/WebAssembly/data-symbol-in-text-section.ll b/llvm/test/MC/WebAssembly/data-symbol-in-text-section.ll --- a/llvm/test/MC/WebAssembly/data-symbol-in-text-section.ll +++ b/llvm/test/MC/WebAssembly/data-symbol-in-text-section.ll @@ -7,6 +7,6 @@ define hidden i32 @main() local_unnamed_addr #0 { entry: - %0 = load i32, i32* getelementptr inbounds ([1024 x i32], [1024 x i32]* @data_symbol, i32 0, i32 10) + %0 = load i32, ptr getelementptr inbounds ([1024 x i32], ptr @data_symbol, i32 0, i32 10) ret i32 %0 } diff --git a/llvm/test/MC/WebAssembly/debug-byval-struct.ll b/llvm/test/MC/WebAssembly/debug-byval-struct.ll --- a/llvm/test/MC/WebAssembly/debug-byval-struct.ll +++ b/llvm/test/MC/WebAssembly/debug-byval-struct.ll @@ -20,26 +20,23 @@ %struct.s = type { i32, float } ; Function Attrs: noinline nounwind optnone -define hidden i32 @some_func(i32 %x, %union.u* byval(%union.u) align 4 %some_union, %struct.s* byval(%struct.s) align 4 %some_struct, i32* %a) #0 !dbg !7 { +define hidden i32 @some_func(i32 %x, ptr byval(%union.u) align 4 %some_union, ptr byval(%struct.s) align 4 %some_struct, ptr %a) #0 !dbg !7 { entry: %x.addr = alloca i32, align 4 - %a.addr = alloca i32*, align 4 - store i32 %x, i32* %x.addr, align 4 - call void @llvm.dbg.declare(metadata i32* %x.addr, metadata !23, metadata !DIExpression()), !dbg !24 - call void @llvm.dbg.declare(metadata %union.u* %some_union, metadata !25, metadata !DIExpression()), !dbg !26 - call void @llvm.dbg.declare(metadata %struct.s* %some_struct, metadata !27, metadata !DIExpression()), !dbg !28 - store i32* %a, i32** %a.addr, align 4 - call void @llvm.dbg.declare(metadata i32** %a.addr, metadata !29, metadata !DIExpression()), !dbg !30 - %0 = load i32, i32* %x.addr, align 4, !dbg !31 - %x1 = bitcast %union.u* %some_union to i32*, !dbg !32 - %1 = load i32, i32* %x1, align 4, !dbg !32 + %a.addr = alloca ptr, align 4 + store i32 %x, ptr %x.addr, align 4 + call void @llvm.dbg.declare(metadata ptr %x.addr, metadata !23, metadata !DIExpression()), !dbg !24 + call void @llvm.dbg.declare(metadata ptr %some_union, metadata !25, metadata !DIExpression()), !dbg !26 + call void @llvm.dbg.declare(metadata ptr %some_struct, metadata !27, metadata !DIExpression()), !dbg !28 + store ptr %a, ptr %a.addr, align 4 + call void @llvm.dbg.declare(metadata ptr %a.addr, metadata !29, metadata !DIExpression()), !dbg !30 + %0 = load i32, ptr %x.addr, align 4, !dbg !31 + %1 = load i32, ptr %some_union, align 4, !dbg !32 %add = add nsw i32 %0, %1, !dbg !33 - %x2 = getelementptr inbounds %struct.s, %struct.s* %some_struct, i32 0, i32 0, !dbg !34 - %2 = load i32, i32* %x2, align 4, !dbg !34 + %2 = load i32, ptr %some_struct, align 4, !dbg !34 %add3 = add nsw i32 %add, %2, !dbg !35 - %3 = load i32*, i32** %a.addr, align 4, !dbg !36 - %arrayidx = getelementptr inbounds i32, i32* %3, i32 0, !dbg !36 - %4 = load i32, i32* %arrayidx, align 4, !dbg !36 + %3 = load ptr, ptr %a.addr, align 4, !dbg !36 + %4 = load i32, ptr %3, align 4, !dbg !36 %add4 = add nsw i32 %add3, %4, !dbg !37 ret i32 %add4, !dbg !38 } diff --git a/llvm/test/MC/WebAssembly/debug-info.ll b/llvm/test/MC/WebAssembly/debug-info.ll --- a/llvm/test/MC/WebAssembly/debug-info.ll +++ b/llvm/test/MC/WebAssembly/debug-info.ll @@ -270,8 +270,8 @@ source_filename = "test.c" @myextern = external global i32, align 4 -@foo = hidden global i32* @myextern, align 4, !dbg !0 -@ptr2 = hidden global void ()* @f2, align 4, !dbg !6 +@foo = hidden global ptr @myextern, align 4, !dbg !0 +@ptr2 = hidden global ptr @f2, align 4, !dbg !6 ; Function Attrs: noinline nounwind optnone define hidden void @f2() #0 !dbg !17 { diff --git a/llvm/test/MC/WebAssembly/debug-info64.ll b/llvm/test/MC/WebAssembly/debug-info64.ll --- a/llvm/test/MC/WebAssembly/debug-info64.ll +++ b/llvm/test/MC/WebAssembly/debug-info64.ll @@ -276,8 +276,8 @@ source_filename = "test.c" @myextern = external global i32, align 4 -@foo = hidden global i32* @myextern, align 4, !dbg !0 -@ptr2 = hidden global void ()* @f2, align 4, !dbg !6 +@foo = hidden global ptr @myextern, align 4, !dbg !0 +@ptr2 = hidden global ptr @f2, align 4, !dbg !6 ; Function Attrs: noinline nounwind optnone define hidden void @f2() #0 !dbg !17 { diff --git a/llvm/test/MC/WebAssembly/debug-localvar.ll b/llvm/test/MC/WebAssembly/debug-localvar.ll --- a/llvm/test/MC/WebAssembly/debug-localvar.ll +++ b/llvm/test/MC/WebAssembly/debug-localvar.ll @@ -9,16 +9,16 @@ %arg.addr = alloca i32, align 4 %a = alloca i32, align 4 %b = alloca i32, align 4 - store i32 %arg, i32* %arg.addr, align 4 - call void @llvm.dbg.declare(metadata i32* %arg.addr, metadata !11, metadata !DIExpression()), !dbg !12 - call void @llvm.dbg.declare(metadata i32* %a, metadata !13, metadata !DIExpression()), !dbg !14 - store i32 1, i32* %a, align 4, !dbg !14 - call void @llvm.dbg.declare(metadata i32* %b, metadata !15, metadata !DIExpression()), !dbg !17 - store i32 2, i32* %b, align 4, !dbg !17 - %0 = load i32, i32* %b, align 4, !dbg !18 - store i32 %0, i32* %arg.addr, align 4, !dbg !19 - %1 = load i32, i32* %arg.addr, align 4, !dbg !20 - %2 = load i32, i32* %a, align 4, !dbg !21 + store i32 %arg, ptr %arg.addr, align 4 + call void @llvm.dbg.declare(metadata ptr %arg.addr, metadata !11, metadata !DIExpression()), !dbg !12 + call void @llvm.dbg.declare(metadata ptr %a, metadata !13, metadata !DIExpression()), !dbg !14 + store i32 1, ptr %a, align 4, !dbg !14 + call void @llvm.dbg.declare(metadata ptr %b, metadata !15, metadata !DIExpression()), !dbg !17 + store i32 2, ptr %b, align 4, !dbg !17 + %0 = load i32, ptr %b, align 4, !dbg !18 + store i32 %0, ptr %arg.addr, align 4, !dbg !19 + %1 = load i32, ptr %arg.addr, align 4, !dbg !20 + %2 = load i32, ptr %a, align 4, !dbg !21 %add = add nsw i32 %1, %2, !dbg !22 ret i32 %add, !dbg !23 } diff --git a/llvm/test/MC/WebAssembly/debug-template-param.ll b/llvm/test/MC/WebAssembly/debug-template-param.ll --- a/llvm/test/MC/WebAssembly/debug-template-param.ll +++ b/llvm/test/MC/WebAssembly/debug-template-param.ll @@ -59,7 +59,7 @@ !13 = !{!14, !16} !14 = !DITemplateTypeParameter(type: !15) !15 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) -!16 = !DITemplateValueParameter(name: "b", type: !17, value: i8 ()* @_Z1av) +!16 = !DITemplateValueParameter(name: "b", type: !17, value: ptr @_Z1av) !17 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !18, size: 32) !18 = !DISubroutineType(types: !19) !19 = !{!15} diff --git a/llvm/test/MC/WebAssembly/dwarfdump.ll b/llvm/test/MC/WebAssembly/dwarfdump.ll --- a/llvm/test/MC/WebAssembly/dwarfdump.ll +++ b/llvm/test/MC/WebAssembly/dwarfdump.ll @@ -116,8 +116,8 @@ source_filename = "test.c" @myextern = external global i32, align 4 -@foo = hidden global i32* @myextern, align 4, !dbg !0 -@ptr2 = hidden global void ()* @f2, align 4, !dbg !6 +@foo = hidden global ptr @myextern, align 4, !dbg !0 +@ptr2 = hidden global ptr @f2, align 4, !dbg !6 ; Function Attrs: noinline nounwind optnone define hidden void @f2() #0 !dbg !17 { diff --git a/llvm/test/MC/WebAssembly/dwarfdump64.ll b/llvm/test/MC/WebAssembly/dwarfdump64.ll --- a/llvm/test/MC/WebAssembly/dwarfdump64.ll +++ b/llvm/test/MC/WebAssembly/dwarfdump64.ll @@ -61,8 +61,8 @@ source_filename = "test.c" @myextern = external global i32, align 4 -@foo = hidden global i32* @myextern, align 4, !dbg !0 -@ptr2 = hidden global void ()* @f2, align 4, !dbg !6 +@foo = hidden global ptr @myextern, align 4, !dbg !0 +@ptr2 = hidden global ptr @f2, align 4, !dbg !6 ; Function Attrs: noinline nounwind optnone define hidden void @f2() #0 !dbg !17 { diff --git a/llvm/test/MC/WebAssembly/extern-functype-intrinsic.ll b/llvm/test/MC/WebAssembly/extern-functype-intrinsic.ll --- a/llvm/test/MC/WebAssembly/extern-functype-intrinsic.ll +++ b/llvm/test/MC/WebAssembly/extern-functype-intrinsic.ll @@ -9,15 +9,15 @@ ; Function Attrs: nounwind define hidden i32 @d() local_unnamed_addr #0 { entry: - %0 = call i32 bitcast (i32 (...)* @g to i32 ()*)() #3 - call void @llvm.memset.p0i8.i32(i8* nonnull align 4 inttoptr (i32 4 to i8*), i8 0, i32 %0, i1 false) ; preds = %for.body.preheader, %entry + %0 = call i32 @g() #3 + call void @llvm.memset.p0.i32(ptr nonnull align 4 inttoptr (i32 4 to ptr), i8 0, i32 %0, i1 false) ; preds = %for.body.preheader, %entry ret i32 undef } declare i32 @g(...) local_unnamed_addr #1 ; Function Attrs: argmemonly nofree nounwind willreturn writeonly -declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i1 immarg) #2 +declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg) #2 attributes #0 = { nounwind "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" } attributes #1 = { "frame-pointer"="none" "no-prototype" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" } diff --git a/llvm/test/MC/WebAssembly/external-data.ll b/llvm/test/MC/WebAssembly/external-data.ll --- a/llvm/test/MC/WebAssembly/external-data.ll +++ b/llvm/test/MC/WebAssembly/external-data.ll @@ -8,7 +8,7 @@ @myimport = external global i32, align 4 @foo = global i64 7, align 4 -@bar = hidden global i32* @myimport, align 4 +@bar = hidden global ptr @myimport, align 4 ; CHECK: - Type: DATA{{$}} ; CHECK-NEXT: Relocations: diff --git a/llvm/test/MC/WebAssembly/external-func-address.ll b/llvm/test/MC/WebAssembly/external-func-address.ll --- a/llvm/test/MC/WebAssembly/external-func-address.ll +++ b/llvm/test/MC/WebAssembly/external-func-address.ll @@ -6,12 +6,12 @@ ; imports and relocations of type R_TABLE_INDEX_I32. declare void @f0(i32) #0 -@ptr_to_f0 = hidden global void (i32)* @f0, align 4 +@ptr_to_f0 = hidden global ptr @f0, align 4 attributes #0 = { "wasm-import-module"="somewhere" "wasm-import-name"="something" } declare void @f1(i32) #1 -@ptr_to_f1 = hidden global void (i32)* @f1, align 4 +@ptr_to_f1 = hidden global ptr @f1, align 4 ; Check that varargs functions have correctly typed imports declare i32 @varargs(i32, i32, ...) diff --git a/llvm/test/MC/WebAssembly/func-address.ll b/llvm/test/MC/WebAssembly/func-address.ll --- a/llvm/test/MC/WebAssembly/func-address.ll +++ b/llvm/test/MC/WebAssembly/func-address.ll @@ -19,8 +19,8 @@ ; function. define hidden void @call_indirect() #0 { entry: - %adr = alloca i32 ()*, align 4 - store i32 ()* @import3, i32 ()** %adr, align 4 + %adr = alloca ptr, align 4 + store ptr @import3, ptr %adr, align 4 ret void } diff --git a/llvm/test/MC/WebAssembly/function-alias.ll b/llvm/test/MC/WebAssembly/function-alias.ll --- a/llvm/test/MC/WebAssembly/function-alias.ll +++ b/llvm/test/MC/WebAssembly/function-alias.ll @@ -3,13 +3,13 @@ target triple = "wasm32-unknown-unknown-wasm" -@foo = alias i8, bitcast (i8* ()* @func to i8*) -@bar = alias i8* (), i8* ()* @func -@bar2 = alias i8* (), i8* ()* @bar +@foo = alias i8, ptr @func +@bar = alias ptr (), ptr @func +@bar2 = alias ptr (), ptr @bar -define i8* @func() { - call i8* @bar2(); - ret i8* @foo; +define ptr @func() { + call ptr @bar2(); + ret ptr @foo; } ; CHECK: Symbols [ diff --git a/llvm/test/MC/WebAssembly/global-ctor-dtor.ll b/llvm/test/MC/WebAssembly/global-ctor-dtor.ll --- a/llvm/test/MC/WebAssembly/global-ctor-dtor.ll +++ b/llvm/test/MC/WebAssembly/global-ctor-dtor.ll @@ -9,14 +9,14 @@ declare void @func2() declare void @func3() -@llvm.global_ctors = appending global [2 x { i32, void ()*, i8* }] [ - { i32, void ()*, i8* } { i32 65535, void ()* @func0, i8* null }, - { i32, void ()*, i8* } { i32 42, void ()* @func1, i8* null } +@llvm.global_ctors = appending global [2 x { i32, ptr, ptr }] [ + { i32, ptr, ptr } { i32 65535, ptr @func0, ptr null }, + { i32, ptr, ptr } { i32 42, ptr @func1, ptr null } ] -@llvm.global_dtors = appending global [2 x { i32, void ()*, i8* }] [ - { i32, void ()*, i8* } { i32 65535, void ()* @func2, i8* null }, - { i32, void ()*, i8* } { i32 42, void ()* @func3, i8* null } +@llvm.global_dtors = appending global [2 x { i32, ptr, ptr }] [ + { i32, ptr, ptr } { i32 65535, ptr @func2, ptr null }, + { i32, ptr, ptr } { i32 42, ptr @func3, ptr null } ] ; CHECK: - Type: IMPORT diff --git a/llvm/test/MC/WebAssembly/libcall.ll b/llvm/test/MC/WebAssembly/libcall.ll --- a/llvm/test/MC/WebAssembly/libcall.ll +++ b/llvm/test/MC/WebAssembly/libcall.ll @@ -2,13 +2,13 @@ target triple = "wasm32-unknown-unknown" -define hidden void @call_memcpy(i8* align 4 %a, i8* align 4 %b) { +define hidden void @call_memcpy(ptr align 4 %a, ptr align 4 %b) { entry: - tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 %a, i8* align 4 %b, i32 512, i1 false) + tail call void @llvm.memcpy.p0.p0.i32(ptr align 4 %a, ptr align 4 %b, i32 512, i1 false) ret void } -declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) +declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1) ; CHECK: --- !WASM ; CHECK-NEXT: FileHeader: diff --git a/llvm/test/MC/WebAssembly/no-dead-strip.ll b/llvm/test/MC/WebAssembly/no-dead-strip.ll --- a/llvm/test/MC/WebAssembly/no-dead-strip.ll +++ b/llvm/test/MC/WebAssembly/no-dead-strip.ll @@ -2,7 +2,7 @@ target triple = "wasm32-unknown-unknown" -@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @foo to i8*)], section "llvm.metadata" +@llvm.used = appending global [1 x ptr] [ptr @foo], section "llvm.metadata" define i32 @foo() { entry: diff --git a/llvm/test/MC/WebAssembly/offset.ll b/llvm/test/MC/WebAssembly/offset.ll --- a/llvm/test/MC/WebAssembly/offset.ll +++ b/llvm/test/MC/WebAssembly/offset.ll @@ -8,7 +8,7 @@ ; CHECK-NEXT: Locals: ; CHECK-NEXT: Body: 41002802FFFFFFFF0F0B define i32 @load_i32_from_negative_address() { - %t = load i32, i32* inttoptr (i32 -1 to i32*) + %t = load i32, ptr inttoptr (i32 -1 to ptr) ret i32 %t } @@ -16,6 +16,6 @@ ; CHECK-NEXT: Locals: ; CHECK-NEXT: Body: 41002802030B define i32 @load_i32_from_wrapped_address() { - %t = load i32, i32* inttoptr (i32 4294967299 to i32*) + %t = load i32, ptr inttoptr (i32 4294967299 to ptr) ret i32 %t } diff --git a/llvm/test/MC/WebAssembly/reloc-data.ll b/llvm/test/MC/WebAssembly/reloc-data.ll --- a/llvm/test/MC/WebAssembly/reloc-data.ll +++ b/llvm/test/MC/WebAssembly/reloc-data.ll @@ -7,9 +7,9 @@ @foo = external global i32, align 4 @bar = global i64 7, align 4 -@a = global i32* getelementptr (i32, i32* @foo, i32 2), align 8 -@b = global i64* getelementptr (i64, i64* @bar, i64 -2), align 8 -@c = global [3 x i32*] [i32* @foo, i32* @foo, i32* @foo], align 16 +@a = global ptr getelementptr (i32, ptr @foo, i32 2), align 8 +@b = global ptr getelementptr (i64, ptr @bar, i64 -2), align 8 +@c = global [3 x ptr] [ptr @foo, ptr @foo, ptr @foo], align 16 ; CHECK: Format: WASM ; CHECK: Relocations [ diff --git a/llvm/test/MC/WebAssembly/reloc-relative.ll b/llvm/test/MC/WebAssembly/reloc-relative.ll --- a/llvm/test/MC/WebAssembly/reloc-relative.ll +++ b/llvm/test/MC/WebAssembly/reloc-relative.ll @@ -30,19 +30,19 @@ ; @foo - @bar @foo = external global i32, align 4 @bar = constant i32 sub ( - i32 ptrtoint (i32* @foo to i32), - i32 ptrtoint (i32* @bar to i32) + i32 ptrtoint (ptr @foo to i32), + i32 ptrtoint (ptr @bar to i32) ), section ".sec1" ; @foo - @addend + 4 @fizz = constant i32 42, align 4, section ".sec2" @addend = constant i32 sub ( - i32 ptrtoint (i32* @foo to i32), - i32 ptrtoint (i32* @fizz to i32) + i32 ptrtoint (ptr @foo to i32), + i32 ptrtoint (ptr @fizz to i32) ), section ".sec2" @x_sec = constant i32 sub ( - i32 ptrtoint (i32* @fizz to i32), - i32 ptrtoint (i32* @x_sec to i32) + i32 ptrtoint (ptr @fizz to i32), + i32 ptrtoint (ptr @x_sec to i32) ), section ".sec1" diff --git a/llvm/test/MC/WebAssembly/tag-section-decoding.ll b/llvm/test/MC/WebAssembly/tag-section-decoding.ll --- a/llvm/test/MC/WebAssembly/tag-section-decoding.ll +++ b/llvm/test/MC/WebAssembly/tag-section-decoding.ll @@ -7,7 +7,7 @@ target triple = "wasm32-unknown-unknown" -declare void @llvm.wasm.throw(i32, i8*) +declare void @llvm.wasm.throw(i32, ptr) define i32 @dummy0() { entry: @@ -329,8 +329,8 @@ ret i32 0 } -define i32 @test_throw(i8* %p) { - call void @llvm.wasm.throw(i32 0, i8* %p) +define i32 @test_throw(ptr %p) { + call void @llvm.wasm.throw(i32 0, ptr %p) ret i32 0 } diff --git a/llvm/test/MC/WebAssembly/tag-section.ll b/llvm/test/MC/WebAssembly/tag-section.ll --- a/llvm/test/MC/WebAssembly/tag-section.ll +++ b/llvm/test/MC/WebAssembly/tag-section.ll @@ -3,15 +3,15 @@ target triple = "wasm32-unknown-unknown" -declare void @llvm.wasm.throw(i32, i8*) +declare void @llvm.wasm.throw(i32, ptr) -define i32 @test_throw0(i8* %p) { - call void @llvm.wasm.throw(i32 0, i8* %p) +define i32 @test_throw0(ptr %p) { + call void @llvm.wasm.throw(i32 0, ptr %p) ret i32 0 } -define i32 @test_throw1(i8* %p) { - call void @llvm.wasm.throw(i32 0, i8* %p) +define i32 @test_throw1(ptr %p) { + call void @llvm.wasm.throw(i32 0, ptr %p) ret i32 1 } diff --git a/llvm/test/MC/WebAssembly/unnamed-data.ll b/llvm/test/MC/WebAssembly/unnamed-data.ll --- a/llvm/test/MC/WebAssembly/unnamed-data.ll +++ b/llvm/test/MC/WebAssembly/unnamed-data.ll @@ -5,8 +5,8 @@ @.str1 = private unnamed_addr constant [6 x i8] c"hello\00", align 1 @.str2 = private unnamed_addr constant [6 x i8] c"world\00", align 1 -@a = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str1, i32 0, i32 0), align 8 -@b = global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @.str2, i32 0, i32 0), align 8 +@a = global ptr @.str1, align 8 +@b = global ptr @.str2, align 8 ; CHECK: - Type: DATA{{$}} diff --git a/llvm/test/MC/X86/intel-syntax-var-offset.ll b/llvm/test/MC/X86/intel-syntax-var-offset.ll --- a/llvm/test/MC/X86/intel-syntax-var-offset.ll +++ b/llvm/test/MC/X86/intel-syntax-var-offset.ll @@ -30,20 +30,20 @@ ; CHECK: mov rdx, offset X ; CHECK: mov qword ptr [PX], rdx -@PZ = common dso_local global i8* null, align 8 +@PZ = common dso_local global ptr null, align 8 @Z = common dso_local global [4 x i8] zeroinitializer, align 1 @X = common dso_local global [4 x i8] zeroinitializer, align 1 -@PX = common dso_local global i8* null, align 8 +@PX = common dso_local global ptr null, align 8 @Y = common dso_local global [4 x i8] zeroinitializer, align 1 -@PY = common dso_local global i8* null, align 8 +@PY = common dso_local global ptr null, align 8 -define dso_local i8* @test057(i64 %x) { +define dso_local ptr @test057(i64 %x) { entry: %x.addr = alloca i64, align 8 - store i64 %x, i64* %x.addr, align 8 - %0 = call i8* asm "movq $1, %rax;movq %rax, $0;pushq $$Y;popq %rcx;movq %rcx, PY;movq $$X, %rdx;movq %rdx, PX;", "=r,im,~{rax},~{rcx},~{rdx},~{dirflag},~{fpsr},~{flags}"(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @Z, i32 0, i32 0)) - store i8* %0, i8** @PZ, align 8 - %1 = load i8*, i8** @PZ, align 8 - ret i8* %1 + store i64 %x, ptr %x.addr, align 8 + %0 = call ptr asm "movq $1, %rax;movq %rax, $0;pushq $$Y;popq %rcx;movq %rcx, PY;movq $$X, %rdx;movq %rdx, PX;", "=r,im,~{rax},~{rcx},~{rdx},~{dirflag},~{fpsr},~{flags}"(ptr @Z) + store ptr %0, ptr @PZ, align 8 + %1 = load ptr, ptr @PZ, align 8 + ret ptr %1 } diff --git a/llvm/test/Other/force-opaque-ptrs.ll b/llvm/test/Other/force-opaque-ptrs.ll --- a/llvm/test/Other/force-opaque-ptrs.ll +++ b/llvm/test/Other/force-opaque-ptrs.ll @@ -20,8 +20,15 @@ ; CHECK: @ga2 = alias i19, ptr @g2 @ga2 = alias i19, i19* bitcast (i18* @g2 to i19*) -; CHECK: @gi = ifunc i20 (), ptr @f -@gi = ifunc i20 (), i20 ()* ()* bitcast (void (i32*)* @f to i20 ()* ()*) +; CHECK: @gi = ifunc i20 (), ptr @resolver +@gi = ifunc i20 (), i20 ()* ()* bitcast (i32* ()* @resolver to i20 ()* ()*) + + +define i32* @resolver() { + %load = load i32, i32* @g.fwd + %ptr = inttoptr i32 %load to i32* + ret i32* %ptr +} define void @f(i32* %p) { ; CHECK-LABEL: define {{[^@]+}}@f diff --git a/llvm/test/ThinLTO/X86/Inputs/alias_import.ll b/llvm/test/ThinLTO/X86/Inputs/alias_import.ll --- a/llvm/test/ThinLTO/X86/Inputs/alias_import.ll +++ b/llvm/test/ThinLTO/X86/Inputs/alias_import.ll @@ -1,60 +1,60 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" -@globalfuncAlias = alias void (...), bitcast (void ()* @globalfunc to void (...)*) -@globalfuncWeakAlias = weak alias void (...), bitcast (void ()* @globalfunc to void (...)*) -@globalfuncLinkonceAlias = linkonce alias void (...), bitcast (void ()* @globalfunc to void (...)*) -@globalfuncWeakODRAlias = weak_odr alias void (...), bitcast (void ()* @globalfunc to void (...)*) -@globalfuncLinkonceODRAlias = linkonce_odr alias void (...), bitcast (void ()* @globalfunc to void (...)*) +@globalfuncAlias = alias void (...), ptr @globalfunc +@globalfuncWeakAlias = weak alias void (...), ptr @globalfunc +@globalfuncLinkonceAlias = linkonce alias void (...), ptr @globalfunc +@globalfuncWeakODRAlias = weak_odr alias void (...), ptr @globalfunc +@globalfuncLinkonceODRAlias = linkonce_odr alias void (...), ptr @globalfunc define hidden void @globalfunc() { entry: ret void } -@internalfuncAlias = alias void (...), bitcast (void ()* @internalfunc to void (...)*) -@internalfuncWeakAlias = weak alias void (...), bitcast (void ()* @internalfunc to void (...)*) -@internalfuncLinkonceAlias = linkonce alias void (...), bitcast (void ()* @internalfunc to void (...)*) -@internalfuncWeakODRAlias = weak_odr alias void (...), bitcast (void ()* @internalfunc to void (...)*) -@internalfuncLinkonceODRAlias = linkonce_odr alias void (...), bitcast (void ()* @internalfunc to void (...)*) +@internalfuncAlias = alias void (...), ptr @internalfunc +@internalfuncWeakAlias = weak alias void (...), ptr @internalfunc +@internalfuncLinkonceAlias = linkonce alias void (...), ptr @internalfunc +@internalfuncWeakODRAlias = weak_odr alias void (...), ptr @internalfunc +@internalfuncLinkonceODRAlias = linkonce_odr alias void (...), ptr @internalfunc define internal void @internalfunc() { entry: ret void } -@linkonceODRfuncAlias = alias void (...), bitcast (void ()* @linkonceODRfunc to void (...)*) -@linkonceODRfuncWeakAlias = weak alias void (...), bitcast (void ()* @linkonceODRfunc to void (...)*) -@linkonceODRfuncLinkonceAlias = linkonce alias void (...), bitcast (void ()* @linkonceODRfunc to void (...)*) -@linkonceODRfuncWeakODRAlias = weak_odr alias void (...), bitcast (void ()* @linkonceODRfunc to void (...)*) -@linkonceODRfuncLinkonceODRAlias = linkonce_odr alias void (...), bitcast (void ()* @linkonceODRfunc to void (...)*) +@linkonceODRfuncAlias = alias void (...), ptr @linkonceODRfunc +@linkonceODRfuncWeakAlias = weak alias void (...), ptr @linkonceODRfunc +@linkonceODRfuncLinkonceAlias = linkonce alias void (...), ptr @linkonceODRfunc +@linkonceODRfuncWeakODRAlias = weak_odr alias void (...), ptr @linkonceODRfunc +@linkonceODRfuncLinkonceODRAlias = linkonce_odr alias void (...), ptr @linkonceODRfunc define linkonce_odr void @linkonceODRfunc() { entry: ret void } -@weakODRfuncAlias = alias void (...), bitcast (void ()* @weakODRfunc to void (...)*) -@weakODRfuncWeakAlias = weak alias void (...), bitcast (void ()* @weakODRfunc to void (...)*) -@weakODRfuncLinkonceAlias = linkonce alias void (...), bitcast (void ()* @weakODRfunc to void (...)*) -@weakODRfuncWeakODRAlias = weak_odr alias void (...), bitcast (void ()* @weakODRfunc to void (...)*) -@weakODRfuncLinkonceODRAlias = linkonce_odr alias void (...), bitcast (void ()* @weakODRfunc to void (...)*) +@weakODRfuncAlias = alias void (...), ptr @weakODRfunc +@weakODRfuncWeakAlias = weak alias void (...), ptr @weakODRfunc +@weakODRfuncLinkonceAlias = linkonce alias void (...), ptr @weakODRfunc +@weakODRfuncWeakODRAlias = weak_odr alias void (...), ptr @weakODRfunc +@weakODRfuncLinkonceODRAlias = linkonce_odr alias void (...), ptr @weakODRfunc define weak_odr void @weakODRfunc() { entry: ret void } -@linkoncefuncAlias = alias void (...), bitcast (void ()* @linkoncefunc to void (...)*) -@linkoncefuncWeakAlias = weak alias void (...), bitcast (void ()* @linkoncefunc to void (...)*) -@linkoncefuncLinkonceAlias = linkonce alias void (...), bitcast (void ()* @linkoncefunc to void (...)*) -@linkoncefuncWeakODRAlias = weak_odr alias void (...), bitcast (void ()* @linkoncefunc to void (...)*) -@linkoncefuncLinkonceODRAlias = linkonce_odr alias void (...), bitcast (void ()* @linkoncefunc to void (...)*) +@linkoncefuncAlias = alias void (...), ptr @linkoncefunc +@linkoncefuncWeakAlias = weak alias void (...), ptr @linkoncefunc +@linkoncefuncLinkonceAlias = linkonce alias void (...), ptr @linkoncefunc +@linkoncefuncWeakODRAlias = weak_odr alias void (...), ptr @linkoncefunc +@linkoncefuncLinkonceODRAlias = linkonce_odr alias void (...), ptr @linkoncefunc define linkonce void @linkoncefunc() { entry: ret void } -@weakfuncAlias = alias void (...), bitcast (void ()* @weakfunc to void (...)*) -@weakfuncWeakAlias = weak alias void (...), bitcast (void ()* @weakfunc to void (...)*) -@weakfuncLinkonceAlias = linkonce alias void (...), bitcast (void ()* @weakfunc to void (...)*) -@weakfuncWeakODRAlias = weak_odr alias void (...), bitcast (void ()* @weakfunc to void (...)*) -@weakfuncLinkonceODRAlias = linkonce_odr alias void (...), bitcast (void ()* @weakfunc to void (...)*) +@weakfuncAlias = alias void (...), ptr @weakfunc +@weakfuncWeakAlias = weak alias void (...), ptr @weakfunc +@weakfuncLinkonceAlias = linkonce alias void (...), ptr @weakfunc +@weakfuncWeakODRAlias = weak_odr alias void (...), ptr @weakfunc +@weakfuncLinkonceODRAlias = linkonce_odr alias void (...), ptr @weakfunc define weak void @weakfunc() { entry: ret void diff --git a/llvm/test/ThinLTO/X86/Inputs/alias_internal.ll b/llvm/test/ThinLTO/X86/Inputs/alias_internal.ll --- a/llvm/test/ThinLTO/X86/Inputs/alias_internal.ll +++ b/llvm/test/ThinLTO/X86/Inputs/alias_internal.ll @@ -1,8 +1,8 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define internal i32 @f(i8*) unnamed_addr { +define internal i32 @f(ptr) unnamed_addr { ret i32 42 } -@a2 = weak alias i32 (i8*), i32 (i8*)* @f +@a2 = weak alias i32 (ptr), ptr @f diff --git a/llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions-import.ll b/llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions-import.ll --- a/llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions-import.ll +++ b/llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions-import.ll @@ -1,15 +1,15 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define i1 @importf1(i8* %p) { - %x = call i1 @f1(i8* %p) +define i1 @importf1(ptr %p) { + %x = call i1 @f1(ptr %p) ret i1 %x } -define i1 @importf2(i8* %p) { - %x = call i1 @f2(i8* %p) +define i1 @importf2(ptr %p) { + %x = call i1 @f2(ptr %p) ret i1 %x } -declare i1 @f1(i8* %p) -declare i1 @f2(i8* %p) +declare i1 @f1(ptr %p) +declare i1 @f2(ptr %p) diff --git a/llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions2.ll b/llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions2.ll --- a/llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions2.ll +++ b/llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions2.ll @@ -1,9 +1,9 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -@vt2 = constant i1 (i8*)* @vf2, !type !0 +@vt2 = constant ptr @vf2, !type !0 -define internal i1 @vf2(i8* %this) { +define internal i1 @vf2(ptr %this) { ret i1 0 } diff --git a/llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions3.ll b/llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions3.ll --- a/llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions3.ll +++ b/llvm/test/ThinLTO/X86/Inputs/cache-typeid-resolutions3.ll @@ -1,14 +1,14 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -@vt2a = constant i1 (i8*)* @vf2a, !type !0 -@vt2b = constant i1 (i8*)* @vf2b, !type !0 +@vt2a = constant ptr @vf2a, !type !0 +@vt2b = constant ptr @vf2b, !type !0 -define internal i1 @vf2a(i8* %this) { +define internal i1 @vf2a(ptr %this) { ret i1 0 } -define internal i1 @vf2b(i8* %this) { +define internal i1 @vf2b(ptr %this) { ret i1 1 } diff --git a/llvm/test/ThinLTO/X86/Inputs/callees-metadata.ll b/llvm/test/ThinLTO/X86/Inputs/callees-metadata.ll --- a/llvm/test/ThinLTO/X86/Inputs/callees-metadata.ll +++ b/llvm/test/ThinLTO/X86/Inputs/callees-metadata.ll @@ -1,11 +1,11 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -@fptr = internal unnamed_addr global i32 (i32)* @f2, align 8 +@fptr = internal unnamed_addr global ptr @f2, align 8 define dso_local i32 @foo(i32 %x) local_unnamed_addr { entry: - %0 = load i32 (i32)*, i32 (i32)** @fptr, align 8 + %0 = load ptr, ptr @fptr, align 8 %call = tail call i32 %0(i32 %x), !callees !0 ret i32 %call } @@ -16,7 +16,7 @@ br i1 %tobool, label %if.end, label %if.then if.then: ; preds = %entry - store i32 (i32)* @f1, i32 (i32)** @fptr, align 8 + store ptr @f1, ptr @fptr, align 8 %sub.i = add nsw i32 %x, -1 br label %if.end @@ -31,4 +31,4 @@ ret i32 %sub } -!0 = !{i32 (i32)* @f1, i32 (i32)* @f2} +!0 = !{ptr @f1, ptr @f2} diff --git a/llvm/test/ThinLTO/X86/Inputs/cfi-distributed.ll b/llvm/test/ThinLTO/X86/Inputs/cfi-distributed.ll --- a/llvm/test/ThinLTO/X86/Inputs/cfi-distributed.ll +++ b/llvm/test/ThinLTO/X86/Inputs/cfi-distributed.ll @@ -2,20 +2,19 @@ target triple = "x86_64-grtev4-linux-gnu" %struct.B2 = type { %struct.A2 } -%struct.A2 = type { i32 (...)** } +%struct.A2 = type { ptr } %struct.B3 = type { %struct.A3 } -%struct.A3 = type { i32 (...)** } +%struct.A3 = type { ptr } -@_ZTV1B2 = constant { [3 x i8*] } { [3 x i8*] [i8* undef, i8* undef, i8* undef] }, !type !0 +@_ZTV1B2 = constant { [3 x ptr] } { [3 x ptr] [ptr undef, ptr undef, ptr undef] }, !type !0 -@_ZTV1B3 = constant { [3 x i8*] } { [3 x i8*] [i8* undef, i8* undef, i8* undef] }, !type !1 +@_ZTV1B3 = constant { [3 x ptr] } { [3 x ptr] [ptr undef, ptr undef, ptr undef] }, !type !1 -define void @test2(i8* %b) { +define void @test2(ptr %b) { entry: - %0 = bitcast i8* %b to i8** - %vtable2 = load i8*, i8** %0 - %1 = tail call i1 @llvm.type.test(i8* %vtable2, metadata !"_ZTS1A2") - br i1 %1, label %cont, label %trap + %vtable2 = load ptr, ptr %b + %0 = tail call i1 @llvm.type.test(ptr %vtable2, metadata !"_ZTS1A2") + br i1 %0, label %cont, label %trap trap: tail call void @llvm.trap() @@ -25,12 +24,11 @@ ret void } -define void @test1(i8* %b) { +define void @test1(ptr %b) { entry: - %0 = bitcast i8* %b to i8** - %vtable2 = load i8*, i8** %0 - %1 = tail call i1 @llvm.type.test(i8* %vtable2, metadata !"_ZTS1A3") - br i1 %1, label %cont, label %trap + %vtable2 = load ptr, ptr %b + %0 = tail call i1 @llvm.type.test(ptr %vtable2, metadata !"_ZTS1A3") + br i1 %0, label %cont, label %trap trap: tail call void @llvm.trap() @@ -40,9 +38,9 @@ ret void } -@test3 = hidden unnamed_addr alias void (i8*), void (i8*)* @test1 +@test3 = hidden unnamed_addr alias void (ptr), ptr @test1 -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.trap() !0 = !{i64 16, !"_ZTS1A2"} diff --git a/llvm/test/ThinLTO/X86/Inputs/cfi-icall-only-bazqux.ll b/llvm/test/ThinLTO/X86/Inputs/cfi-icall-only-bazqux.ll --- a/llvm/test/ThinLTO/X86/Inputs/cfi-icall-only-bazqux.ll +++ b/llvm/test/ThinLTO/X86/Inputs/cfi-icall-only-bazqux.ll @@ -1,23 +1,23 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare !type !0 i8 @bar(i8*) -declare i1 @llvm.type.test(i8* %ptr, metadata %type) nounwind readnone +declare !type !0 i8 @bar(ptr) +declare i1 @llvm.type.test(ptr %ptr, metadata %type) nounwind readnone -define i8 @baz(i8* %p) !type !0 { - %x = call i1 @llvm.type.test(i8* %p, metadata !"t1") +define i8 @baz(ptr %p) !type !0 { + %x = call i1 @llvm.type.test(ptr %p, metadata !"t1") %1 = select i1 %x, i8 0, i8 3 ret i8 %1 } -define i8 @qux(i8* %p) !type !0 { - %x = call i1 @llvm.type.test(i8* %p, metadata !"t1") +define i8 @qux(ptr %p) !type !0 { + %x = call i1 @llvm.type.test(ptr %p, metadata !"t1") ret i8 4 } -define i8 @g(i1 %i, i8* %p) { - %1 = select i1 %i, i8(i8*)* @bar, i8(i8*)* @qux - %2 = call i8 %1(i8* %p) +define i8 @g(i1 %i, ptr %p) { + %1 = select i1 %i, ptr @bar, ptr @qux + %2 = call i8 %1(ptr %p) ret i8 %2 } diff --git a/llvm/test/ThinLTO/X86/Inputs/cfi-unsat.ll b/llvm/test/ThinLTO/X86/Inputs/cfi-unsat.ll --- a/llvm/test/ThinLTO/X86/Inputs/cfi-unsat.ll +++ b/llvm/test/ThinLTO/X86/Inputs/cfi-unsat.ll @@ -1,66 +1,62 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.A = type { i32 (...)** } -%struct.B = type { i32 (...)** } +%struct.A = type { ptr } +%struct.B = type { ptr } -@_ZTV1B = linkonce_odr constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1nEi to i8*)] }, !type !0 +@_ZTV1B = linkonce_odr constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B1fEi, ptr @_ZN1B1nEi] }, !type !0 $test = comdat any $testb = comdat any -define linkonce_odr i32 @test(%struct.A* %obj, i32 %a) comdat { +define linkonce_odr i32 @test(ptr %obj, i32 %a) comdat { entry: - %0 = bitcast %struct.A* %obj to i8** - %vtable5 = load i8*, i8** %0 + %vtable5 = load ptr, ptr %obj - %1 = tail call { i8*, i1 } @llvm.type.checked.load(i8* %vtable5, i32 8, metadata !"_ZTS1A") - %2 = extractvalue { i8*, i1 } %1, 1 - br i1 %2, label %cont, label %trap + %0 = tail call { ptr, i1 } @llvm.type.checked.load(ptr %vtable5, i32 8, metadata !"_ZTS1A") + %1 = extractvalue { ptr, i1 } %0, 1 + br i1 %1, label %cont, label %trap trap: tail call void @llvm.trap() unreachable cont: - %3 = extractvalue { i8*, i1 } %1, 0 - %4 = bitcast i8* %3 to i32 (%struct.A*, i32)* + %2 = extractvalue { ptr, i1 } %0, 0 - %call = tail call i32 %4(%struct.A* nonnull %obj, i32 %a) + %call = tail call i32 %2(ptr nonnull %obj, i32 %a) ret i32 %call } -define linkonce_odr i32 @testb(%struct.A* %obj, i32 %a) comdat { +define linkonce_odr i32 @testb(ptr %obj, i32 %a) comdat { entry: - %0 = bitcast %struct.A* %obj to i8** - %vtable5 = load i8*, i8** %0 + %vtable5 = load ptr, ptr %obj - %1 = tail call { i8*, i1 } @llvm.type.checked.load(i8* %vtable5, i32 0, metadata !"_ZTS1A") - %2 = extractvalue { i8*, i1 } %1, 1 - br i1 %2, label %cont, label %trap + %0 = tail call { ptr, i1 } @llvm.type.checked.load(ptr %vtable5, i32 0, metadata !"_ZTS1A") + %1 = extractvalue { ptr, i1 } %0, 1 + br i1 %1, label %cont, label %trap trap: tail call void @llvm.trap() unreachable cont: - %3 = extractvalue { i8*, i1 } %1, 0 - %4 = bitcast i8* %3 to i32 (%struct.A*, i32)* + %2 = extractvalue { ptr, i1 } %0, 0 - %call = tail call i32 %4(%struct.A* nonnull %obj, i32 %a) + %call = tail call i32 %2(ptr nonnull %obj, i32 %a) ret i32 %call } -declare { i8*, i1 } @llvm.type.checked.load(i8*, i32, metadata) +declare { ptr, i1 } @llvm.type.checked.load(ptr, i32, metadata) declare void @llvm.trap() -define internal i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) { +define internal i32 @_ZN1B1fEi(ptr %this, i32 %a) { entry: ret i32 0 } -define internal i32 @_ZN1B1nEi(%struct.B* %this, i32 %a) { +define internal i32 @_ZN1B1nEi(ptr %this, i32 %a) { entry: ret i32 0 } diff --git a/llvm/test/ThinLTO/X86/Inputs/devirt2.ll b/llvm/test/ThinLTO/X86/Inputs/devirt2.ll --- a/llvm/test/ThinLTO/X86/Inputs/devirt2.ll +++ b/llvm/test/ThinLTO/X86/Inputs/devirt2.ll @@ -1,55 +1,52 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } %struct.B = type { %struct.A } %struct.C = type { %struct.A } -%struct.D = type { i32 (...)** } -%struct.E = type { i32 (...)** } +%struct.D = type { ptr } +%struct.E = type { ptr } -@_ZTV1B = constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !type !1 -@_ZTV1C = constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.C*, i32)* @_ZN1C1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !type !2 -@_ZTV1D = linkonce_odr constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.D*, i32)* @_ZN1D1mEi to i8*)] }, !type !3 -@_ZTV1E = constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.E*, i32)* @_ZN1E1mEi to i8*)] }, !type !4 +@_ZTV1B = constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B1fEi, ptr @_ZN1A1nEi] }, !type !0, !type !1 +@_ZTV1C = constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1C1fEi, ptr @_ZN1A1nEi] }, !type !0, !type !2 +@_ZTV1D = linkonce_odr constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr undef, ptr @_ZN1D1mEi] }, !type !3 +@_ZTV1E = constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr undef, ptr @_ZN1E1mEi] }, !type !4 -define i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) #0 { +define i32 @_ZN1B1fEi(ptr %this, i32 %a) #0 { ret i32 0 } -define internal i32 @_ZN1A1nEi(%struct.A* %this, i32 %a) #0 { +define internal i32 @_ZN1A1nEi(ptr %this, i32 %a) #0 { ret i32 0 } -define i32 @_ZN1C1fEi(%struct.C* %this, i32 %a) #0 { +define i32 @_ZN1C1fEi(ptr %this, i32 %a) #0 { ret i32 0 } -define linkonce_odr i32 @_ZN1D1mEi(%struct.D* %this, i32 %a) #0 { +define linkonce_odr i32 @_ZN1D1mEi(ptr %this, i32 %a) #0 { ret i32 0 } -define internal i32 @_ZN1E1mEi(%struct.E* %this, i32 %a) #0 { +define internal i32 @_ZN1E1mEi(ptr %this, i32 %a) #0 { ret i32 0, !dbg !12 } -define i32 @test2(%struct.E* %obj, i32 %a) { +define i32 @test2(ptr %obj, i32 %a) { entry: - %0 = bitcast %struct.E* %obj to i8***, !dbg !12 - %vtable2 = load i8**, i8*** %0 - %1 = bitcast i8** %vtable2 to i8* - %p2 = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1E") + %vtable2 = load ptr, ptr %obj + %p2 = call i1 @llvm.type.test(ptr %vtable2, metadata !"_ZTS1E") call void @llvm.assume(i1 %p2) - %2 = bitcast i8** %vtable2 to i32 (%struct.E*, i32)** - %fptr33 = load i32 (%struct.E*, i32)*, i32 (%struct.E*, i32)** %2, align 8 + %fptr33 = load ptr, ptr %vtable2, align 8 - %call4 = tail call i32 %fptr33(%struct.E* nonnull %obj, i32 %a) + %call4 = tail call i32 %fptr33(ptr nonnull %obj, i32 %a) ret i32 %call4 } attributes #0 = { noinline optnone } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) !llvm.dbg.cu = !{!5} diff --git a/llvm/test/ThinLTO/X86/Inputs/devirt_after_filtering_unreachable_lib.ll b/llvm/test/ThinLTO/X86/Inputs/devirt_after_filtering_unreachable_lib.ll --- a/llvm/test/ThinLTO/X86/Inputs/devirt_after_filtering_unreachable_lib.ll +++ b/llvm/test/ThinLTO/X86/Inputs/devirt_after_filtering_unreachable_lib.ll @@ -4,33 +4,30 @@ target triple = "x86_64-unknown-linux-gnu" %Derived = type { %Base } -%Base = type { i32 (...)** } +%Base = type { ptr } -@_ZTV7Derived = constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* null, i8* bitcast (void (%Derived*)* @_ZN7DerivedD0Ev to i8*)] }, !type !0, !type !1, !vcall_visibility !2 -@_ZTV4Base = constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* null, i8* bitcast (void (%Base*)* @_ZN4BaseD0Ev to i8*)] }, !type !0, !vcall_visibility !2 +@_ZTV7Derived = constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr null, ptr @_ZN7DerivedD0Ev] }, !type !0, !type !1, !vcall_visibility !2 +@_ZTV4Base = constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr null, ptr @_ZN4BaseD0Ev] }, !type !0, !vcall_visibility !2 -define void @_Z3fooP4Base(%Base* %b) { +define void @_Z3fooP4Base(ptr %b) { entry: - %0 = bitcast %Base* %b to void (%Base*)*** - %vtable = load void (%Base*)**, void (%Base*)*** %0 - %1 = bitcast void (%Base*)** %vtable to i8* - %2 = tail call i1 @llvm.type.test(i8* %1, metadata !"_ZTS4Base") - tail call void @llvm.assume(i1 %2) - %vfn = getelementptr inbounds void (%Base*)*, void (%Base*)** %vtable, i64 0 - %3 = load void (%Base*)*, void (%Base*)** %vfn - tail call void %3(%Base* %b) + %vtable = load ptr, ptr %b + %0 = tail call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS4Base") + tail call void @llvm.assume(i1 %0) + %1 = load ptr, ptr %vtable + tail call void %1(ptr %b) ret void } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) -define void @_ZN7DerivedD0Ev(%Derived* %this) { +define void @_ZN7DerivedD0Ev(ptr %this) { ret void } -define void @_ZN4BaseD0Ev(%Base* %this) { +define void @_ZN4BaseD0Ev(ptr %this) { unreachable } diff --git a/llvm/test/ThinLTO/X86/Inputs/devirt_alias.ll b/llvm/test/ThinLTO/X86/Inputs/devirt_alias.ll --- a/llvm/test/ThinLTO/X86/Inputs/devirt_alias.ll +++ b/llvm/test/ThinLTO/X86/Inputs/devirt_alias.ll @@ -1,12 +1,12 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.D = type { i32 (...)** } +%struct.D = type { ptr } -@some_name = constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.D*, i32)* @_ZN1D1mEi to i8*)] }, !type !3 -@_ZTV1D = alias { [3 x i8*] }, { [3 x i8*] }* @some_name +@some_name = constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr undef, ptr @_ZN1D1mEi] }, !type !3 +@_ZTV1D = alias { [3 x ptr] }, ptr @some_name -define i32 @_ZN1D1mEi(%struct.D* %this, i32 %a) #0 { +define i32 @_ZN1D1mEi(ptr %this, i32 %a) #0 { ret i32 0; } diff --git a/llvm/test/ThinLTO/X86/Inputs/devirt_available_externally.ll b/llvm/test/ThinLTO/X86/Inputs/devirt_available_externally.ll --- a/llvm/test/ThinLTO/X86/Inputs/devirt_available_externally.ll +++ b/llvm/test/ThinLTO/X86/Inputs/devirt_available_externally.ll @@ -1,11 +1,11 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.D = type { i32 (...)** } +%struct.D = type { ptr } -@_ZTV1D = constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.D*, i32)* @_ZN1D1mEi to i8*)] }, !type !3 +@_ZTV1D = constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr undef, ptr @_ZN1D1mEi] }, !type !3 -define i32 @_ZN1D1mEi(%struct.D* %this, i32 %a) #0 { +define i32 @_ZN1D1mEi(ptr %this, i32 %a) #0 { ret i32 0; } diff --git a/llvm/test/ThinLTO/X86/Inputs/devirt_external_comdat_same_guid.ll b/llvm/test/ThinLTO/X86/Inputs/devirt_external_comdat_same_guid.ll --- a/llvm/test/ThinLTO/X86/Inputs/devirt_external_comdat_same_guid.ll +++ b/llvm/test/ThinLTO/X86/Inputs/devirt_external_comdat_same_guid.ll @@ -3,40 +3,37 @@ source_filename = "-" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } %struct.B = type { %struct.A } $_ZTV1B = comdat any -@_ZTV1B = constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, comdat, !type !0, !type !1 +@_ZTV1B = constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B1fEi, ptr @_ZN1A1nEi] }, comdat, !type !0, !type !1 -define i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) #0 comdat($_ZTV1B) { +define i32 @_ZN1B1fEi(ptr %this, i32 %a) #0 comdat($_ZTV1B) { ret i32 0; } -define i32 @_ZN1A1nEi(%struct.A* %this, i32 %a) #0 comdat($_ZTV1B) { +define i32 @_ZN1A1nEi(ptr %this, i32 %a) #0 comdat($_ZTV1B) { ret i32 0; } -define i32 @test2(%struct.B* %obj, i32 %a) { +define i32 @test2(ptr %obj, i32 %a) { entry: - %0 = bitcast %struct.B* %obj to i8*** - %vtable2 = load i8**, i8*** %0 - %1 = bitcast i8** %vtable2 to i8* - %p2 = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1B") + %vtable2 = load ptr, ptr %obj + %p2 = call i1 @llvm.type.test(ptr %vtable2, metadata !"_ZTS1B") call void @llvm.assume(i1 %p2) - %fptrptr = getelementptr i8*, i8** %vtable2, i32 1 - %2 = bitcast i8** %fptrptr to i32 (%struct.B*, i32)** - %fptr33 = load i32 (%struct.B*, i32)*, i32 (%struct.B*, i32)** %2, align 8 + %fptrptr = getelementptr ptr, ptr %vtable2, i32 1 + %fptr33 = load ptr, ptr %fptrptr, align 8 - %call4 = tail call i32 %fptr33(%struct.B* nonnull %obj, i32 %a) + %call4 = tail call i32 %fptr33(ptr nonnull %obj, i32 %a) ret i32 %call4 } attributes #0 = { noinline optnone } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) !0 = !{i64 16, !"_ZTS1A"} diff --git a/llvm/test/ThinLTO/X86/Inputs/devirt_local_same_guid.ll b/llvm/test/ThinLTO/X86/Inputs/devirt_local_same_guid.ll --- a/llvm/test/ThinLTO/X86/Inputs/devirt_local_same_guid.ll +++ b/llvm/test/ThinLTO/X86/Inputs/devirt_local_same_guid.ll @@ -3,38 +3,35 @@ source_filename = "-" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } %struct.B = type { %struct.A } -@_ZTV1B = internal constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !type !1 +@_ZTV1B = internal constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B1fEi, ptr @_ZN1A1nEi] }, !type !0, !type !1 -define internal i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) #0 { +define internal i32 @_ZN1B1fEi(ptr %this, i32 %a) #0 { ret i32 0; } -define internal i32 @_ZN1A1nEi(%struct.A* %this, i32 %a) #0 { +define internal i32 @_ZN1A1nEi(ptr %this, i32 %a) #0 { ret i32 0; } -define i32 @test2(%struct.B* %obj, i32 %a) { +define i32 @test2(ptr %obj, i32 %a) { entry: - %0 = bitcast %struct.B* %obj to i8*** - %vtable2 = load i8**, i8*** %0 - %1 = bitcast i8** %vtable2 to i8* - %p2 = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1B") + %vtable2 = load ptr, ptr %obj + %p2 = call i1 @llvm.type.test(ptr %vtable2, metadata !"_ZTS1B") call void @llvm.assume(i1 %p2) - %fptrptr = getelementptr i8*, i8** %vtable2, i32 1 - %2 = bitcast i8** %fptrptr to i32 (%struct.B*, i32)** - %fptr33 = load i32 (%struct.B*, i32)*, i32 (%struct.B*, i32)** %2, align 8 + %fptrptr = getelementptr ptr, ptr %vtable2, i32 1 + %fptr33 = load ptr, ptr %fptrptr, align 8 - %call4 = tail call i32 %fptr33(%struct.B* nonnull %obj, i32 %a) + %call4 = tail call i32 %fptr33(ptr nonnull %obj, i32 %a) ret i32 %call4 } attributes #0 = { noinline optnone } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) !0 = !{i64 16, !"_ZTS1A"} diff --git a/llvm/test/ThinLTO/X86/Inputs/devirt_promote.ll b/llvm/test/ThinLTO/X86/Inputs/devirt_promote.ll --- a/llvm/test/ThinLTO/X86/Inputs/devirt_promote.ll +++ b/llvm/test/ThinLTO/X86/Inputs/devirt_promote.ll @@ -1,38 +1,35 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } %struct.B = type { %struct.A } -@_ZTV1B = constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !type !1 +@_ZTV1B = constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B1fEi, ptr @_ZN1A1nEi] }, !type !0, !type !1 -define i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) #0 { +define i32 @_ZN1B1fEi(ptr %this, i32 %a) #0 { ret i32 0; } -define internal i32 @_ZN1A1nEi(%struct.A* %this, i32 %a) #0 { +define internal i32 @_ZN1A1nEi(ptr %this, i32 %a) #0 { ret i32 0; } -define i32 @test2(%struct.B* %obj, i32 %a) { +define i32 @test2(ptr %obj, i32 %a) { entry: - %0 = bitcast %struct.B* %obj to i8*** - %vtable2 = load i8**, i8*** %0 - %1 = bitcast i8** %vtable2 to i8* - %p2 = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1B") + %vtable2 = load ptr, ptr %obj + %p2 = call i1 @llvm.type.test(ptr %vtable2, metadata !"_ZTS1B") call void @llvm.assume(i1 %p2) - %fptrptr = getelementptr i8*, i8** %vtable2, i32 1 - %2 = bitcast i8** %fptrptr to i32 (%struct.B*, i32)** - %fptr33 = load i32 (%struct.B*, i32)*, i32 (%struct.B*, i32)** %2, align 8 + %fptrptr = getelementptr ptr, ptr %vtable2, i32 1 + %fptr33 = load ptr, ptr %fptrptr, align 8 - %call4 = tail call i32 %fptr33(%struct.B* nonnull %obj, i32 %a) + %call4 = tail call i32 %fptr33(ptr nonnull %obj, i32 %a) ret i32 %call4 } attributes #0 = { noinline optnone } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) !0 = !{i64 16, !"_ZTS1A"} diff --git a/llvm/test/ThinLTO/X86/Inputs/devirt_single_hybrid_bar.ll b/llvm/test/ThinLTO/X86/Inputs/devirt_single_hybrid_bar.ll --- a/llvm/test/ThinLTO/X86/Inputs/devirt_single_hybrid_bar.ll +++ b/llvm/test/ThinLTO/X86/Inputs/devirt_single_hybrid_bar.ll @@ -3,7 +3,7 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } $_ZNK1A1fEv = comdat any @@ -13,35 +13,33 @@ $_ZTI1A = comdat any -@_ZTV1A = linkonce_odr hidden unnamed_addr constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* bitcast ({ i8*, i8* }* @_ZTI1A to i8*), i8* bitcast (i32 (%struct.A*)* @_ZNK1A1fEv to i8*)] }, comdat, align 8, !type !0, !type !1 -@_ZTVN10__cxxabiv117__class_type_infoE = external dso_local global i8* +@_ZTV1A = linkonce_odr hidden unnamed_addr constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr @_ZTI1A, ptr @_ZNK1A1fEv] }, comdat, align 8, !type !0, !type !1 +@_ZTVN10__cxxabiv117__class_type_infoE = external dso_local global ptr @_ZTS1A = linkonce_odr hidden constant [3 x i8] c"1A\00", comdat, align 1 -@_ZTI1A = linkonce_odr hidden constant { i8*, i8* } { i8* bitcast (i8** getelementptr inbounds (i8*, i8** @_ZTVN10__cxxabiv117__class_type_infoE, i64 2) to i8*), i8* getelementptr inbounds ([3 x i8], [3 x i8]* @_ZTS1A, i32 0, i32 0) }, comdat, align 8 +@_ZTI1A = linkonce_odr hidden constant { ptr, ptr } { ptr getelementptr inbounds (ptr, ptr @_ZTVN10__cxxabiv117__class_type_infoE, i64 2), ptr @_ZTS1A }, comdat, align 8 ; Function Attrs: uwtable define hidden i32 @_Z3barv() local_unnamed_addr #0 { entry: %b = alloca %struct.A, align 8 - %0 = bitcast %struct.A* %b to i8* - call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0) - %1 = getelementptr inbounds %struct.A, %struct.A* %b, i64 0, i32 0 - store i32 (...)** bitcast (i8** getelementptr inbounds ({ [3 x i8*] }, { [3 x i8*] }* @_ZTV1A, i64 0, inrange i32 0, i64 2) to i32 (...)**), i32 (...)*** %1, align 8, !tbaa !4 - %call = call i32 @_Z3fooP1A(%struct.A* nonnull %b) + call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %b) + store ptr getelementptr inbounds ({ [3 x ptr] }, ptr @_ZTV1A, i64 0, inrange i32 0, i64 2), ptr %b, align 8, !tbaa !4 + %call = call i32 @_Z3fooP1A(ptr nonnull %b) %add = add nsw i32 %call, 10 - call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0) #4 + call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %b) #4 ret i32 %add } ; Function Attrs: argmemonly nounwind willreturn -declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) -declare dso_local i32 @_Z3fooP1A(%struct.A*) local_unnamed_addr +declare dso_local i32 @_Z3fooP1A(ptr) local_unnamed_addr ; Function Attrs: argmemonly nounwind willreturn -declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) ; Function Attrs: nounwind uwtable -define linkonce_odr hidden i32 @_ZNK1A1fEv(%struct.A* %this) unnamed_addr comdat align 2 { +define linkonce_odr hidden i32 @_ZNK1A1fEv(ptr %this) unnamed_addr comdat align 2 { entry: ret i32 3 } diff --git a/llvm/test/ThinLTO/X86/Inputs/devirt_single_hybrid_foo.ll b/llvm/test/ThinLTO/X86/Inputs/devirt_single_hybrid_foo.ll --- a/llvm/test/ThinLTO/X86/Inputs/devirt_single_hybrid_foo.ll +++ b/llvm/test/ThinLTO/X86/Inputs/devirt_single_hybrid_foo.ll @@ -3,24 +3,22 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } ; Function Attrs: uwtable -define hidden i32 @_Z3fooP1A(%struct.A* %pA) local_unnamed_addr { +define hidden i32 @_Z3fooP1A(ptr %pA) local_unnamed_addr { entry: - %0 = bitcast %struct.A* %pA to i32 (%struct.A*)*** - %vtable = load i32 (%struct.A*)**, i32 (%struct.A*)*** %0, align 8, !tbaa !2 - %1 = bitcast i32 (%struct.A*)** %vtable to i8* - %2 = tail call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1A") - tail call void @llvm.assume(i1 %2) - %3 = load i32 (%struct.A*)*, i32 (%struct.A*)** %vtable, align 8 - %call = tail call i32 %3(%struct.A* %pA) + %vtable = load ptr, ptr %pA, align 8, !tbaa !2 + %0 = tail call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1A") + tail call void @llvm.assume(i1 %0) + %1 = load ptr, ptr %vtable, align 8 + %call = tail call i32 %1(ptr %pA) %add = add nsw i32 %call, 10 ret i32 %add } ; Function Attrs: nounwind readnone willreturn -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) ; Function Attrs: nounwind willreturn declare void @llvm.assume(i1) diff --git a/llvm/test/ThinLTO/X86/Inputs/dicompositetype-unique-alias.ll b/llvm/test/ThinLTO/X86/Inputs/dicompositetype-unique-alias.ll --- a/llvm/test/ThinLTO/X86/Inputs/dicompositetype-unique-alias.ll +++ b/llvm/test/ThinLTO/X86/Inputs/dicompositetype-unique-alias.ll @@ -5,18 +5,17 @@ %struct.Vec = type { i8 } %struct.S = type { i8 } -@_ZN4CFVSD1Ev = alias void (%struct.CFVS*), void (%struct.CFVS*)* @_ZN4CFVSD2Ev +@_ZN4CFVSD1Ev = alias void (ptr), ptr @_ZN4CFVSD2Ev -define void @_ZN4CFVSD2Ev(%struct.CFVS* %this) unnamed_addr align 2 !dbg !8 { +define void @_ZN4CFVSD2Ev(ptr %this) unnamed_addr align 2 !dbg !8 { entry: - %this.addr = alloca %struct.CFVS*, align 8 - store %struct.CFVS* %this, %struct.CFVS** %this.addr, align 8 - %this1 = load %struct.CFVS*, %struct.CFVS** %this.addr, align 8 - %m_val = getelementptr inbounds %struct.CFVS, %struct.CFVS* %this1, i32 0, i32 0 + %this.addr = alloca ptr, align 8 + store ptr %this, ptr %this.addr, align 8 + %this1 = load ptr, ptr %this.addr, align 8 ret void } -declare dereferenceable(1) %struct.S* @_Z3Getv() +declare dereferenceable(1) ptr @_Z3Getv() !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3, !4, !5, !6} diff --git a/llvm/test/ThinLTO/X86/Inputs/dicompositetype-unique2.ll b/llvm/test/ThinLTO/X86/Inputs/dicompositetype-unique2.ll --- a/llvm/test/ThinLTO/X86/Inputs/dicompositetype-unique2.ll +++ b/llvm/test/ThinLTO/X86/Inputs/dicompositetype-unique2.ll @@ -5,16 +5,15 @@ %struct.Vec = type { i8 } %struct.S = type { i8 } -define void @_ZN4CFVSD2Ev(%struct.CFVS* %this) unnamed_addr align 2 !dbg !8 { +define void @_ZN4CFVSD2Ev(ptr %this) unnamed_addr align 2 !dbg !8 { entry: - %this.addr = alloca %struct.CFVS*, align 8 - store %struct.CFVS* %this, %struct.CFVS** %this.addr, align 8 - %this1 = load %struct.CFVS*, %struct.CFVS** %this.addr, align 8 - %m_val = getelementptr inbounds %struct.CFVS, %struct.CFVS* %this1, i32 0, i32 0 + %this.addr = alloca ptr, align 8 + store ptr %this, ptr %this.addr, align 8 + %this1 = load ptr, ptr %this.addr, align 8 ret void } -declare dereferenceable(1) %struct.S* @_Z3Getv() +declare dereferenceable(1) ptr @_Z3Getv() !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3, !4, !5, !6} @@ -34,7 +33,7 @@ !13 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "Vec<&Get>", file: !10, line: 4, size: 8, elements: !14, templateParams: !19, identifier: "_ZTS3VecIXadL_Z3GetvEEE") !14 = !{!35} !19 = !{!20} -!20 = !DITemplateValueParameter(name: "F", type: !21, value: %struct.S* ()* @_Z3Getv) +!20 = !DITemplateValueParameter(name: "F", type: !21, value: ptr @_Z3Getv) !21 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !22, size: 64) !22 = !DIDerivedType(tag: DW_TAG_typedef, name: "Func", file: !10, line: 2, baseType: !23) !23 = !DISubroutineType(types: !24) diff --git a/llvm/test/ThinLTO/X86/Inputs/dot-dumper.ll b/llvm/test/ThinLTO/X86/Inputs/dot-dumper.ll --- a/llvm/test/ThinLTO/X86/Inputs/dot-dumper.ll +++ b/llvm/test/ThinLTO/X86/Inputs/dot-dumper.ll @@ -6,8 +6,8 @@ ; Function Attrs: norecurse nounwind readonly uwtable define i32 @foo() local_unnamed_addr #0 { - %1 = load i32, i32* @B, align 4 - %2 = load i32, i32* @A, align 4 + %1 = load i32, ptr @B, align 4 + %2 = load i32, ptr @A, align 4 %3 = add nsw i32 %2, %1 ret i32 %3 } diff --git a/llvm/test/ThinLTO/X86/Inputs/drop-debug-info.ll b/llvm/test/ThinLTO/X86/Inputs/drop-debug-info.ll --- a/llvm/test/ThinLTO/X86/Inputs/drop-debug-info.ll +++ b/llvm/test/ThinLTO/X86/Inputs/drop-debug-info.ll @@ -9,7 +9,7 @@ define void @globalfunc() { entry: - %0 = load i8, i8* @argc, align 1 + %0 = load i8, ptr @argc, align 1 tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !19, metadata !29), !dbg !DILocation(scope: !13) ret void } diff --git a/llvm/test/ThinLTO/X86/Inputs/funcimport-tbaa.ll b/llvm/test/ThinLTO/X86/Inputs/funcimport-tbaa.ll --- a/llvm/test/ThinLTO/X86/Inputs/funcimport-tbaa.ll +++ b/llvm/test/ThinLTO/X86/Inputs/funcimport-tbaa.ll @@ -4,8 +4,8 @@ define i32 @main() { entry: - %unused = call float @globalfunc1(i32* null, float*null) + %unused = call float @globalfunc1(ptr null, ptr null) ret i32 0 } -declare float @globalfunc1(i32*, float*) \ No newline at end of file +declare float @globalfunc1(ptr, ptr) \ No newline at end of file diff --git a/llvm/test/ThinLTO/X86/Inputs/globals-import-blockaddr.ll b/llvm/test/ThinLTO/X86/Inputs/globals-import-blockaddr.ll --- a/llvm/test/ThinLTO/X86/Inputs/globals-import-blockaddr.ll +++ b/llvm/test/ThinLTO/X86/Inputs/globals-import-blockaddr.ll @@ -1,17 +1,17 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -@label_addr = internal constant [1 x i8*] [i8* blockaddress(@bar, %lb)], align 8 +@label_addr = internal constant [1 x ptr] [ptr blockaddress(@bar, %lb)], align 8 ; Function Attrs: noinline norecurse nounwind optnone uwtable -define dso_local [1 x i8*]* @foo() { - ret [1 x i8*]* @label_addr +define dso_local ptr @foo() { + ret ptr @label_addr } ; Function Attrs: noinline norecurse nounwind optnone uwtable -define dso_local [1 x i8*]* @bar() { +define dso_local ptr @bar() { br label %lb lb: - ret [1 x i8*]* @label_addr + ret ptr @label_addr } diff --git a/llvm/test/ThinLTO/X86/Inputs/globals-import.ll b/llvm/test/ThinLTO/X86/Inputs/globals-import.ll --- a/llvm/test/ThinLTO/X86/Inputs/globals-import.ll +++ b/llvm/test/ThinLTO/X86/Inputs/globals-import.ll @@ -4,6 +4,6 @@ @baz = internal constant i32 10, align 4 define linkonce_odr i32 @foo() { - %1 = load i32, i32* @baz, align 4 + %1 = load i32, ptr @baz, align 4 ret i32 %1 } diff --git a/llvm/test/ThinLTO/X86/Inputs/guid_collision.ll b/llvm/test/ThinLTO/X86/Inputs/guid_collision.ll --- a/llvm/test/ThinLTO/X86/Inputs/guid_collision.ll +++ b/llvm/test/ThinLTO/X86/Inputs/guid_collision.ll @@ -7,9 +7,9 @@ ret i64 0 } -@llvm.global_ctors = appending global [0 x { i32, void ()*, i8* }] zeroinitializer +@llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer define i64 @G() { - ;%1 = load i32, i32* @dummy2, align 4 + ;%1 = load i32, ptr @dummy2, align 4 ret i64 0 } diff --git a/llvm/test/ThinLTO/X86/Inputs/import-constant.ll b/llvm/test/ThinLTO/X86/Inputs/import-constant.ll --- a/llvm/test/ThinLTO/X86/Inputs/import-constant.ll +++ b/llvm/test/ThinLTO/X86/Inputs/import-constant.ll @@ -1,15 +1,15 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -%struct.S = type { i32, i32, i32* } -%struct.Q = type { %struct.S* } +%struct.S = type { i32, i32, ptr } +%struct.Q = type { ptr } @val = dso_local global i32 42, align 4 -@_ZL3Obj = internal constant %struct.S { i32 4, i32 8, i32* @val }, align 8 -@outer = dso_local local_unnamed_addr global %struct.Q { %struct.S* @_ZL3Obj }, align 8 +@_ZL3Obj = internal constant %struct.S { i32 4, i32 8, ptr @val }, align 8 +@outer = dso_local local_unnamed_addr global %struct.Q { ptr @_ZL3Obj }, align 8 -define dso_local nonnull %struct.S* @_Z6getObjv() local_unnamed_addr { +define dso_local nonnull ptr @_Z6getObjv() local_unnamed_addr { entry: - store %struct.S* null, %struct.S** getelementptr inbounds (%struct.Q, %struct.Q* @outer, i64 1, i32 0), align 8 - ret %struct.S* @_ZL3Obj + store ptr null, ptr getelementptr inbounds (%struct.Q, ptr @outer, i64 1, i32 0), align 8 + ret ptr @_ZL3Obj } diff --git a/llvm/test/ThinLTO/X86/Inputs/import-metadata.ll b/llvm/test/ThinLTO/X86/Inputs/import-metadata.ll --- a/llvm/test/ThinLTO/X86/Inputs/import-metadata.ll +++ b/llvm/test/ThinLTO/X86/Inputs/import-metadata.ll @@ -4,9 +4,9 @@ define i32 @foo(i32 %goo) { entry: %goo.addr = alloca i32, align 4 - store i32 %goo, i32* %goo.addr, align 4 - %0 = load i32, i32* %goo.addr, align 4 - %1 = load i32, i32* %goo.addr, align 4 + store i32 %goo, ptr %goo.addr, align 4 + %0 = load i32, ptr %goo.addr, align 4 + %1 = load i32, ptr %goo.addr, align 4 %mul = mul nsw i32 %0, %1 ret i32 %mul } diff --git a/llvm/test/ThinLTO/X86/Inputs/index-const-prop-alias.ll b/llvm/test/ThinLTO/X86/Inputs/index-const-prop-alias.ll --- a/llvm/test/ThinLTO/X86/Inputs/index-const-prop-alias.ll +++ b/llvm/test/ThinLTO/X86/Inputs/index-const-prop-alias.ll @@ -2,4 +2,4 @@ target triple = "x86_64-unknown-linux-gnu" @g = global i32 42, align 4 -@g.alias = weak alias i32, i32* @g +@g.alias = weak alias i32, ptr @g diff --git a/llvm/test/ThinLTO/X86/Inputs/index-const-prop-cache-foo.ll b/llvm/test/ThinLTO/X86/Inputs/index-const-prop-cache-foo.ll --- a/llvm/test/ThinLTO/X86/Inputs/index-const-prop-cache-foo.ll +++ b/llvm/test/ThinLTO/X86/Inputs/index-const-prop-cache-foo.ll @@ -5,14 +5,14 @@ ; Function Attrs: norecurse nounwind readonly ssp uwtable define i32 @foo() local_unnamed_addr { - %1 = load i32, i32* @gFoo, align 4 + %1 = load i32, ptr @gFoo, align 4 ret i32 %1 } ; Function Attrs: nounwind ssp uwtable define void @bar() local_unnamed_addr { %1 = tail call i32 @rand() - store i32 %1, i32* @gFoo, align 4 + store i32 %1, ptr @gFoo, align 4 ret void } diff --git a/llvm/test/ThinLTO/X86/Inputs/index-const-prop-full-lto.ll b/llvm/test/ThinLTO/X86/Inputs/index-const-prop-full-lto.ll --- a/llvm/test/ThinLTO/X86/Inputs/index-const-prop-full-lto.ll +++ b/llvm/test/ThinLTO/X86/Inputs/index-const-prop-full-lto.ll @@ -4,7 +4,7 @@ @g = external global i32 define i32 @foo() { - %v = load i32, i32* @g + %v = load i32, ptr @g ret i32 %v } diff --git a/llvm/test/ThinLTO/X86/Inputs/index-const-prop-gvref.ll b/llvm/test/ThinLTO/X86/Inputs/index-const-prop-gvref.ll --- a/llvm/test/ThinLTO/X86/Inputs/index-const-prop-gvref.ll +++ b/llvm/test/ThinLTO/X86/Inputs/index-const-prop-gvref.ll @@ -1,5 +1,5 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -@b = dso_local global i32* @a, align 8 +@b = dso_local global ptr @a, align 8 @a = dso_local global i32 42, align 4 diff --git a/llvm/test/ThinLTO/X86/Inputs/index-const-prop-linkage.ll b/llvm/test/ThinLTO/X86/Inputs/index-const-prop-linkage.ll --- a/llvm/test/ThinLTO/X86/Inputs/index-const-prop-linkage.ll +++ b/llvm/test/ThinLTO/X86/Inputs/index-const-prop-linkage.ll @@ -6,9 +6,9 @@ @g3 = available_externally global i32 42, align 4 define i32 @foo() { - %v1 = load i32, i32* @g1 - %v2 = load i32, i32* @g2 - %v3 = load i32, i32* @g3 + %v1 = load i32, ptr @g1 + %v2 = load i32, ptr @g2 + %v3 = load i32, ptr @g3 %s1 = add i32 %v1, %v2 %s2 = add i32 %s1, %v3 ret i32 %s2 diff --git a/llvm/test/ThinLTO/X86/Inputs/index-const-prop.ll b/llvm/test/ThinLTO/X86/Inputs/index-const-prop.ll --- a/llvm/test/ThinLTO/X86/Inputs/index-const-prop.ll +++ b/llvm/test/ThinLTO/X86/Inputs/index-const-prop.ll @@ -6,21 +6,21 @@ ; Function Attrs: norecurse nounwind readonly define i32 @foo() local_unnamed_addr #0 !dbg !14 { - %1 = load i32, i32* @gFoo, align 4, !dbg !17 + %1 = load i32, ptr @gFoo, align 4, !dbg !17 ret i32 %1, !dbg !18 } ; Function Attrs: norecurse nounwind readonly define i32 @bar() local_unnamed_addr #0 !dbg !19 { - %1 = load i32, i32* @gBar, align 4, !dbg !20 + %1 = load i32, ptr @gBar, align 4, !dbg !20 ret i32 %1, !dbg !21 } define void @baz() local_unnamed_addr !dbg !22 { %1 = tail call i32 @rand(), !dbg !25 - store i32 %1, i32* @gFoo, align 4, !dbg !26 + store i32 %1, ptr @gFoo, align 4, !dbg !26 %2 = tail call i32 @rand(), !dbg !27 - store i32 %2, i32* @gBar, align 4, !dbg !28 + store i32 %2, ptr @gBar, align 4, !dbg !28 ret void, !dbg !29 } diff --git a/llvm/test/ThinLTO/X86/Inputs/linkonce_resolution_comdat.ll b/llvm/test/ThinLTO/X86/Inputs/linkonce_resolution_comdat.ll --- a/llvm/test/ThinLTO/X86/Inputs/linkonce_resolution_comdat.ll +++ b/llvm/test/ThinLTO/X86/Inputs/linkonce_resolution_comdat.ll @@ -6,7 +6,7 @@ @g_private = private global i32 41, comdat($g) -define linkonce_odr i32 @f(i8*) unnamed_addr comdat($f) { +define linkonce_odr i32 @f(ptr) unnamed_addr comdat($f) { ret i32 41 } @@ -19,6 +19,6 @@ } define i32 @h() { - %i = call i32 @f(i8* null) + %i = call i32 @f(ptr null) ret i32 %i } diff --git a/llvm/test/ThinLTO/X86/Inputs/local_name_conflict1.ll b/llvm/test/ThinLTO/X86/Inputs/local_name_conflict1.ll --- a/llvm/test/ThinLTO/X86/Inputs/local_name_conflict1.ll +++ b/llvm/test/ThinLTO/X86/Inputs/local_name_conflict1.ll @@ -15,6 +15,6 @@ ; Function Attrs: noinline nounwind uwtable define internal i32 @foo() { entry: - %0 = load i32, i32* @baz, align 4 + %0 = load i32, ptr @baz, align 4 ret i32 %0 } diff --git a/llvm/test/ThinLTO/X86/Inputs/local_name_conflict2.ll b/llvm/test/ThinLTO/X86/Inputs/local_name_conflict2.ll --- a/llvm/test/ThinLTO/X86/Inputs/local_name_conflict2.ll +++ b/llvm/test/ThinLTO/X86/Inputs/local_name_conflict2.ll @@ -15,6 +15,6 @@ ; Function Attrs: noinline nounwind uwtable define internal i32 @foo() { entry: - %0 = load i32, i32* @baz, align 4 + %0 = load i32, ptr @baz, align 4 ret i32 %0 } diff --git a/llvm/test/ThinLTO/X86/Inputs/local_name_conflict_var1.ll b/llvm/test/ThinLTO/X86/Inputs/local_name_conflict_var1.ll --- a/llvm/test/ThinLTO/X86/Inputs/local_name_conflict_var1.ll +++ b/llvm/test/ThinLTO/X86/Inputs/local_name_conflict_var1.ll @@ -8,6 +8,6 @@ ; Function Attrs: noinline nounwind uwtable define i32 @a() { entry: - %0 = load i32, i32* @baz, align 4 + %0 = load i32, ptr @baz, align 4 ret i32 %0 } diff --git a/llvm/test/ThinLTO/X86/Inputs/local_name_conflict_var2.ll b/llvm/test/ThinLTO/X86/Inputs/local_name_conflict_var2.ll --- a/llvm/test/ThinLTO/X86/Inputs/local_name_conflict_var2.ll +++ b/llvm/test/ThinLTO/X86/Inputs/local_name_conflict_var2.ll @@ -8,6 +8,6 @@ ; Function Attrs: noinline nounwind uwtable define i32 @b() { entry: - %0 = load i32, i32* @baz, align 4 + %0 = load i32, ptr @baz, align 4 ret i32 %0 } diff --git a/llvm/test/ThinLTO/X86/Inputs/module_asm2.ll b/llvm/test/ThinLTO/X86/Inputs/module_asm2.ll --- a/llvm/test/ThinLTO/X86/Inputs/module_asm2.ll +++ b/llvm/test/ThinLTO/X86/Inputs/module_asm2.ll @@ -1,7 +1,7 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define i32 @main({ i64, { i64, i8* }* } %unnamed) #0 { +define i32 @main({ i64, ptr } %unnamed) #0 { %1 = call i32 @func1() #1 %2 = call i32 @func2() #1 %3 = call i32 @func3() #1 diff --git a/llvm/test/ThinLTO/X86/Inputs/personality.ll b/llvm/test/ThinLTO/X86/Inputs/personality.ll --- a/llvm/test/ThinLTO/X86/Inputs/personality.ll +++ b/llvm/test/ThinLTO/X86/Inputs/personality.ll @@ -1,18 +1,18 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-linux-gnu" -define void @bar() personality i32 (i32, i32, i64, i8*, i8*)* @personality_routine { +define void @bar() personality ptr @personality_routine { ret void } -define protected i32 @personality_routine(i32, i32, i64, i8*, i8*) { +define protected i32 @personality_routine(i32, i32, i64, ptr, ptr) { ret i32 0 } -define protected i32 @personality_routine2(i32, i32, i64, i8*, i8*) { +define protected i32 @personality_routine2(i32, i32, i64, ptr, ptr) { ret i32 0 } -define protected i32 @personality_routine3(i32, i32, i64, i8*, i8*) { +define protected i32 @personality_routine3(i32, i32, i64, ptr, ptr) { ret i32 0 } diff --git a/llvm/test/ThinLTO/X86/Inputs/promote-local-name-1.ll b/llvm/test/ThinLTO/X86/Inputs/promote-local-name-1.ll --- a/llvm/test/ThinLTO/X86/Inputs/promote-local-name-1.ll +++ b/llvm/test/ThinLTO/X86/Inputs/promote-local-name-1.ll @@ -15,6 +15,6 @@ ; Function Attrs: noinline nounwind uwtable define internal i32 @foo() { entry: - %0 = load i32, i32* @baz, align 4 + %0 = load i32, ptr @baz, align 4 ret i32 %0 } diff --git a/llvm/test/ThinLTO/X86/Inputs/reference_non_importable.ll b/llvm/test/ThinLTO/X86/Inputs/reference_non_importable.ll --- a/llvm/test/ThinLTO/X86/Inputs/reference_non_importable.ll +++ b/llvm/test/ThinLTO/X86/Inputs/reference_non_importable.ll @@ -1,8 +1,8 @@ target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.11.0" -declare i8 **@foo() +declare ptr@foo() define i32 @main() { - call i8 **@foo() + call ptr@foo() ret i32 0 } diff --git a/llvm/test/ThinLTO/X86/Inputs/referenced_by_constant.ll b/llvm/test/ThinLTO/X86/Inputs/referenced_by_constant.ll --- a/llvm/test/ThinLTO/X86/Inputs/referenced_by_constant.ll +++ b/llvm/test/ThinLTO/X86/Inputs/referenced_by_constant.ll @@ -10,13 +10,13 @@ ret void } -@someglobal = internal unnamed_addr constant i8* bitcast (void ()* @referencedbyglobal to i8*) -@someglobal2 = internal unnamed_addr constant i8* bitcast (void ()* @localreferencedbyglobal to i8*) -@ptr = global i8** null -@ptr2 = global i8** null +@someglobal = internal unnamed_addr constant ptr @referencedbyglobal +@someglobal2 = internal unnamed_addr constant ptr @localreferencedbyglobal +@ptr = global ptr null +@ptr2 = global ptr null define void @bar() #0 align 2 { - store i8** getelementptr inbounds (i8*, i8** @someglobal, i64 0) , i8*** @ptr, align 8 - store i8** getelementptr inbounds (i8*, i8** @someglobal2, i64 0) , i8*** @ptr2, align 8 + store ptr @someglobal , ptr @ptr, align 8 + store ptr @someglobal2 , ptr @ptr2, align 8 ret void } diff --git a/llvm/test/ThinLTO/X86/Inputs/section.ll b/llvm/test/ThinLTO/X86/Inputs/section.ll --- a/llvm/test/ThinLTO/X86/Inputs/section.ll +++ b/llvm/test/ThinLTO/X86/Inputs/section.ll @@ -4,7 +4,7 @@ ; @reference_gv_with_section() can't be imported define i32 @reference_gv_with_section() { - %res = load i32, i32* @var_with_section + %res = load i32, ptr @var_with_section ret i32 %res } diff --git a/llvm/test/ThinLTO/X86/Inputs/select_right_alias_definition1.ll b/llvm/test/ThinLTO/X86/Inputs/select_right_alias_definition1.ll --- a/llvm/test/ThinLTO/X86/Inputs/select_right_alias_definition1.ll +++ b/llvm/test/ThinLTO/X86/Inputs/select_right_alias_definition1.ll @@ -1,6 +1,6 @@ -@foo = weak alias i32 (...), bitcast (i32 ()* @foo1 to i32 (...)*) +@foo = weak alias i32 (...), @foo1 define i32 @foo1() { ret i32 42 } \ No newline at end of file diff --git a/llvm/test/ThinLTO/X86/Inputs/select_right_alias_definition2.ll b/llvm/test/ThinLTO/X86/Inputs/select_right_alias_definition2.ll --- a/llvm/test/ThinLTO/X86/Inputs/select_right_alias_definition2.ll +++ b/llvm/test/ThinLTO/X86/Inputs/select_right_alias_definition2.ll @@ -1,7 +1,7 @@ -@foo = alias i32 (...), bitcast (i32 ()* @foo2 to i32 (...)*) +@foo = alias i32 (...), @foo2 define linkonce_odr i32 @foo2() { %ret = add i32 42, 42 ret i32 %ret } \ No newline at end of file diff --git a/llvm/test/ThinLTO/X86/Inputs/weak_resolution.ll b/llvm/test/ThinLTO/X86/Inputs/weak_resolution.ll --- a/llvm/test/ThinLTO/X86/Inputs/weak_resolution.ll +++ b/llvm/test/ThinLTO/X86/Inputs/weak_resolution.ll @@ -2,10 +2,10 @@ target triple = "x86_64-apple-macosx10.11.0" ; Alias are not optimized -@linkonceodralias = linkonce_odr alias void (), void ()* @linkonceodrfuncwithalias +@linkonceodralias = linkonce_odr alias void (), ptr @linkonceodrfuncwithalias ; Alias are not optimized -@linkoncealias = linkonce alias void (), void ()* @linkoncefuncwithalias +@linkoncealias = linkonce alias void (), ptr @linkoncefuncwithalias ; Function with an alias are not optimized define linkonce_odr void @linkonceodrfuncwithalias() #0 { diff --git a/llvm/test/ThinLTO/X86/Inputs/writeonly-with-refs.ll b/llvm/test/ThinLTO/X86/Inputs/writeonly-with-refs.ll --- a/llvm/test/ThinLTO/X86/Inputs/writeonly-with-refs.ll +++ b/llvm/test/ThinLTO/X86/Inputs/writeonly-with-refs.ll @@ -4,14 +4,14 @@ target triple = "x86_64-unknown-linux-gnu" %struct.S = type { i32 } -%struct.Q = type { %struct.S* } +%struct.Q = type { ptr } @_ZL3Obj = internal constant %struct.S { i32 42 }, align 4 -@outer = dso_local local_unnamed_addr global %struct.Q { %struct.S* @_ZL3Obj }, align 8 +@outer = dso_local local_unnamed_addr global %struct.Q { ptr @_ZL3Obj }, align 8 ; Function Attrs: nofree norecurse nounwind uwtable writeonly define dso_local void @_Z3foov() local_unnamed_addr { entry: - store %struct.S* null, %struct.S** getelementptr inbounds (%struct.Q, %struct.Q* @outer, i64 0, i32 0), align 8 + store ptr null, ptr @outer, align 8 ret void } diff --git a/llvm/test/ThinLTO/X86/alias-ifunc.ll b/llvm/test/ThinLTO/X86/alias-ifunc.ll --- a/llvm/test/ThinLTO/X86/alias-ifunc.ll +++ b/llvm/test/ThinLTO/X86/alias-ifunc.ll @@ -22,9 +22,9 @@ @foo = ifunc i32 (i32), ptr @foo_resolver ; CHECK-RESOLVER: (name: "foo_resolver" ; CHECK-RESOLVER-SAME: live: 1 -define internal i32 (i32)* @foo_resolver() { +define internal ptr @foo_resolver() { entry: - ret i32 (i32)* null + ret ptr null } ; CHECK-BAR: (name: "bar" ; CHECK-BAR-NOT: summaries: ( @@ -43,7 +43,7 @@ ; CHECK-QUUX: (name: "quux" ; CHECK-QUUX-SAME: live: 1 -@quux = internal alias i32 (i32)* (), ptr @foo_resolver +@quux = internal alias ptr (), ptr @foo_resolver @quuz = internal ifunc i32 (i32), ptr @quux ; CHECK-CORGE: (name: "corge" diff --git a/llvm/test/ThinLTO/X86/alias_import.ll b/llvm/test/ThinLTO/X86/alias_import.ll --- a/llvm/test/ThinLTO/X86/alias_import.ll +++ b/llvm/test/ThinLTO/X86/alias_import.ll @@ -7,36 +7,36 @@ ; Alias can't point to "available_externally", so they are implemented by ; importing the alias as an available_externally definition copied from the ; aliasee's body. -; PROMOTE-DAG: @globalfuncAlias = alias void (...), bitcast (void ()* @globalfunc to void (...)*) -; PROMOTE-DAG: @globalfuncWeakAlias = weak alias void (...), bitcast (void ()* @globalfunc to void (...)*) -; PROMOTE-DAG: @globalfuncLinkonceAlias = weak alias void (...), bitcast (void ()* @globalfunc to void (...)*) -; PROMOTE-DAG: @globalfuncWeakODRAlias = weak_odr alias void (...), bitcast (void ()* @globalfunc to void (...)*) -; PROMOTE-DAG: @globalfuncLinkonceODRAlias = weak_odr alias void (...), bitcast (void ()* @globalfunc to void (...)*) -; PROMOTE-DAG: @internalfuncAlias = alias void (...), bitcast (void ()* @internalfunc to void (...)*) -; PROMOTE-DAG: @internalfuncWeakAlias = weak alias void (...), bitcast (void ()* @internalfunc to void (...)*) -; PROMOTE-DAG: @internalfuncLinkonceAlias = weak alias void (...), bitcast (void ()* @internalfunc to void (...)*) -; PROMOTE-DAG: @internalfuncWeakODRAlias = weak_odr alias void (...), bitcast (void ()* @internalfunc to void (...)*) -; PROMOTE-DAG: @internalfuncLinkonceODRAlias = weak_odr alias void (...), bitcast (void ()* @internalfunc to void (...)*) -; PROMOTE-DAG: @linkoncefuncAlias = alias void (...), bitcast (void ()* @linkoncefunc to void (...)*) -; PROMOTE-DAG: @linkoncefuncWeakAlias = weak alias void (...), bitcast (void ()* @linkoncefunc to void (...)*) -; PROMOTE-DAG: @linkoncefuncLinkonceAlias = weak alias void (...), bitcast (void ()* @linkoncefunc to void (...)*) -; PROMOTE-DAG: @linkoncefuncWeakODRAlias = weak_odr alias void (...), bitcast (void ()* @linkoncefunc to void (...)*) -; PROMOTE-DAG: @linkoncefuncLinkonceODRAlias = weak_odr alias void (...), bitcast (void ()* @linkoncefunc to void (...)*) -; PROMOTE-DAG: @weakfuncAlias = alias void (...), bitcast (void ()* @weakfunc to void (...)*) -; PROMOTE-DAG: @weakfuncWeakAlias = weak alias void (...), bitcast (void ()* @weakfunc to void (...)*) -; PROMOTE-DAG: @weakfuncLinkonceAlias = weak alias void (...), bitcast (void ()* @weakfunc to void (...)*) -; PROMOTE-DAG: @weakfuncWeakODRAlias = weak_odr alias void (...), bitcast (void ()* @weakfunc to void (...)*) -; PROMOTE-DAG: @weakfuncLinkonceODRAlias = weak_odr alias void (...), bitcast (void ()* @weakfunc to void (...)*) -; PROMOTE-DAG: @weakODRfuncAlias = alias void (...), bitcast (void ()* @weakODRfunc to void (...)*) -; PROMOTE-DAG: @weakODRfuncWeakAlias = weak alias void (...), bitcast (void ()* @weakODRfunc to void (...)*) -; PROMOTE-DAG: @weakODRfuncLinkonceAlias = weak alias void (...), bitcast (void ()* @weakODRfunc to void (...)*) -; PROMOTE-DAG: @weakODRfuncWeakODRAlias = weak_odr alias void (...), bitcast (void ()* @weakODRfunc to void (...)*) -; PROMOTE-DAG: @weakODRfuncLinkonceODRAlias = weak_odr alias void (...), bitcast (void ()* @weakODRfunc to void (...)*) -; PROMOTE-DAG: @linkonceODRfuncAlias = alias void (...), bitcast (void ()* @linkonceODRfunc to void (...)*) -; PROMOTE-DAG: @linkonceODRfuncWeakAlias = weak alias void (...), bitcast (void ()* @linkonceODRfunc to void (...)*) -; PROMOTE-DAG: @linkonceODRfuncWeakODRAlias = weak_odr alias void (...), bitcast (void ()* @linkonceODRfunc to void (...)*) -; PROMOTE-DAG: @linkonceODRfuncLinkonceAlias = weak alias void (...), bitcast (void ()* @linkonceODRfunc to void (...)*) -; PROMOTE-DAG: @linkonceODRfuncLinkonceODRAlias = weak_odr alias void (...), bitcast (void ()* @linkonceODRfunc to void (...)*) +; PROMOTE-DAG: @globalfuncAlias = alias void (...), ptr @globalfunc +; PROMOTE-DAG: @globalfuncWeakAlias = weak alias void (...), ptr @globalfunc +; PROMOTE-DAG: @globalfuncLinkonceAlias = weak alias void (...), ptr @globalfunc +; PROMOTE-DAG: @globalfuncWeakODRAlias = weak_odr alias void (...), ptr @globalfunc +; PROMOTE-DAG: @globalfuncLinkonceODRAlias = weak_odr alias void (...), ptr @globalfunc +; PROMOTE-DAG: @internalfuncAlias = alias void (...), ptr @internalfunc +; PROMOTE-DAG: @internalfuncWeakAlias = weak alias void (...), ptr @internalfunc +; PROMOTE-DAG: @internalfuncLinkonceAlias = weak alias void (...), ptr @internalfunc +; PROMOTE-DAG: @internalfuncWeakODRAlias = weak_odr alias void (...), ptr @internalfunc +; PROMOTE-DAG: @internalfuncLinkonceODRAlias = weak_odr alias void (...), ptr @internalfunc +; PROMOTE-DAG: @linkoncefuncAlias = alias void (...), ptr @linkoncefunc +; PROMOTE-DAG: @linkoncefuncWeakAlias = weak alias void (...), ptr @linkoncefunc +; PROMOTE-DAG: @linkoncefuncLinkonceAlias = weak alias void (...), ptr @linkoncefunc +; PROMOTE-DAG: @linkoncefuncWeakODRAlias = weak_odr alias void (...), ptr @linkoncefunc +; PROMOTE-DAG: @linkoncefuncLinkonceODRAlias = weak_odr alias void (...), ptr @linkoncefunc +; PROMOTE-DAG: @weakfuncAlias = alias void (...), ptr @weakfunc +; PROMOTE-DAG: @weakfuncWeakAlias = weak alias void (...), ptr @weakfunc +; PROMOTE-DAG: @weakfuncLinkonceAlias = weak alias void (...), ptr @weakfunc +; PROMOTE-DAG: @weakfuncWeakODRAlias = weak_odr alias void (...), ptr @weakfunc +; PROMOTE-DAG: @weakfuncLinkonceODRAlias = weak_odr alias void (...), ptr @weakfunc +; PROMOTE-DAG: @weakODRfuncAlias = alias void (...), ptr @weakODRfunc +; PROMOTE-DAG: @weakODRfuncWeakAlias = weak alias void (...), ptr @weakODRfunc +; PROMOTE-DAG: @weakODRfuncLinkonceAlias = weak alias void (...), ptr @weakODRfunc +; PROMOTE-DAG: @weakODRfuncWeakODRAlias = weak_odr alias void (...), ptr @weakODRfunc +; PROMOTE-DAG: @weakODRfuncLinkonceODRAlias = weak_odr alias void (...), ptr @weakODRfunc +; PROMOTE-DAG: @linkonceODRfuncAlias = alias void (...), ptr @linkonceODRfunc +; PROMOTE-DAG: @linkonceODRfuncWeakAlias = weak alias void (...), ptr @linkonceODRfunc +; PROMOTE-DAG: @linkonceODRfuncWeakODRAlias = weak_odr alias void (...), ptr @linkonceODRfunc +; PROMOTE-DAG: @linkonceODRfuncLinkonceAlias = weak alias void (...), ptr @linkonceODRfunc +; PROMOTE-DAG: @linkonceODRfuncLinkonceODRAlias = weak_odr alias void (...), ptr @linkonceODRfunc ; PROMOTE-DAG: define hidden void @globalfunc() ; PROMOTE-DAG: define internal void @internalfunc() diff --git a/llvm/test/ThinLTO/X86/alias_internal.ll b/llvm/test/ThinLTO/X86/alias_internal.ll --- a/llvm/test/ThinLTO/X86/alias_internal.ll +++ b/llvm/test/ThinLTO/X86/alias_internal.ll @@ -14,8 +14,8 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define internal i32 @f(i8*) unnamed_addr { +define internal i32 @f(ptr) unnamed_addr { ret i32 42 } -@a1 = weak alias i32 (i8*), i32 (i8*)* @f +@a1 = weak alias i32 (ptr), ptr @f diff --git a/llvm/test/ThinLTO/X86/asm.ll b/llvm/test/ThinLTO/X86/asm.ll --- a/llvm/test/ThinLTO/X86/asm.ll +++ b/llvm/test/ThinLTO/X86/asm.ll @@ -15,10 +15,10 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define i8* @ref() { +define ptr @ref() { entry: - %0 = tail call i8* asm sideeffect "lea ff_h264_cabac_tables(%rip), $0", "=&r,~{dirflag},~{fpsr},~{flags}"() - ret i8* %0 + %0 = tail call ptr asm sideeffect "lea ff_h264_cabac_tables(%rip), $0", "=&r,~{dirflag},~{fpsr},~{flags}"() + ret ptr %0 } ;--- b.s @@ -31,4 +31,4 @@ ; CHECK: @ff_h264_cabac_tables = dso_local constant [1 x i8] c"\09" @ff_h264_cabac_tables = dso_local constant [1 x i8] c"\09" -@llvm.compiler.used = appending global [1 x i8*] [i8* bitcast ([1 x i8]* @ff_h264_cabac_tables to i8*)], section "llvm.metadata" +@llvm.compiler.used = appending global [1 x ptr] [ptr @ff_h264_cabac_tables], section "llvm.metadata" diff --git a/llvm/test/ThinLTO/X86/cache-typeid-resolutions.ll b/llvm/test/ThinLTO/X86/cache-typeid-resolutions.ll --- a/llvm/test/ThinLTO/X86/cache-typeid-resolutions.ll +++ b/llvm/test/ThinLTO/X86/cache-typeid-resolutions.ll @@ -25,25 +25,21 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -@f1 = alias i1(i8*), i1 (i8*)* @f1_actual +@f1 = alias i1(ptr), ptr @f1_actual -define i1 @f1_actual(i8* %p) { - %x = call i1 @llvm.type.test(i8* %p, metadata !"typeid1") +define i1 @f1_actual(ptr %p) { + %x = call i1 @llvm.type.test(ptr %p, metadata !"typeid1") ret i1 %x } -define i1 @f2(i8* %obj) { - %vtableptr = bitcast i8* %obj to [3 x i8*]** - %vtable = load [3 x i8*]*, [3 x i8*]** %vtableptr - %vtablei8 = bitcast [3 x i8*]* %vtable to i8* - %p = call i1 @llvm.type.test(i8* %vtablei8, metadata !"typeid2") +define i1 @f2(ptr %obj) { + %vtable = load ptr, ptr %obj + %p = call i1 @llvm.type.test(ptr %vtable, metadata !"typeid2") call void @llvm.assume(i1 %p) - %fptrptr = getelementptr [3 x i8*], [3 x i8*]* %vtable, i32 0, i32 0 - %fptr = load i8*, i8** %fptrptr - %fptr_casted = bitcast i8* %fptr to i1 (i8*)* - %result = call i1 %fptr_casted(i8* %obj) + %fptr = load ptr, ptr %vtable + %result = call i1 %fptr(ptr %obj) ret i1 %result } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) diff --git a/llvm/test/ThinLTO/X86/cfi-distributed.ll b/llvm/test/ThinLTO/X86/cfi-distributed.ll --- a/llvm/test/ThinLTO/X86/cfi-distributed.ll +++ b/llvm/test/ThinLTO/X86/cfi-distributed.ll @@ -44,18 +44,17 @@ target triple = "x86_64-grtev4-linux-gnu" %struct.B = type { %struct.A } -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } -@_ZTV1B = constant { [3 x i8*] } { [3 x i8*] [i8* undef, i8* undef, i8* undef] }, !type !0 +@_ZTV1B = constant { [3 x ptr] } { [3 x ptr] [ptr undef, ptr undef, ptr undef] }, !type !0 -define void @test(i8* %b) { +define void @test(ptr %b) { entry: - tail call void @test2(i8* %b) - tail call void @test3(i8* %b) - %0 = bitcast i8* %b to i8** - %vtable2 = load i8*, i8** %0 - %1 = tail call i1 @llvm.type.test(i8* %vtable2, metadata !"_ZTS1A") - br i1 %1, label %cont, label %trap + tail call void @test2(ptr %b) + tail call void @test3(ptr %b) + %vtable2 = load ptr, ptr %b + %0 = tail call i1 @llvm.type.test(ptr %vtable2, metadata !"_ZTS1A") + br i1 %0, label %cont, label %trap trap: tail call void @llvm.trap() @@ -65,9 +64,9 @@ ret void } -declare void @test2(i8*) -declare void @test3(i8*) -declare i1 @llvm.type.test(i8*, metadata) +declare void @test2(ptr) +declare void @test3(ptr) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.trap() !0 = !{i64 16, !"_ZTS1A"} diff --git a/llvm/test/ThinLTO/X86/cfi-icall-only-defuse.ll b/llvm/test/ThinLTO/X86/cfi-icall-only-defuse.ll --- a/llvm/test/ThinLTO/X86/cfi-icall-only-defuse.ll +++ b/llvm/test/ThinLTO/X86/cfi-icall-only-defuse.ll @@ -17,23 +17,23 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare !type !0 i8 @baz(i8*) -declare i1 @llvm.type.test(i8* %ptr, metadata %type) nounwind readnone +declare !type !0 i8 @baz(ptr) +declare i1 @llvm.type.test(ptr %ptr, metadata %type) nounwind readnone -define i8 @foo(i8* %p) !type !0 { - %x = call i1 @llvm.type.test(i8* %p, metadata !"t1") +define i8 @foo(ptr %p) !type !0 { + %x = call i1 @llvm.type.test(ptr %p, metadata !"t1") %1 = select i1 %x, i8 0, i8 1 ret i8 %1 } -define i8 @bar(i8* %p) !type !0 { - %x = call i1 @llvm.type.test(i8* %p, metadata !"t1") +define i8 @bar(ptr %p) !type !0 { + %x = call i1 @llvm.type.test(ptr %p, metadata !"t1") ret i8 2 } -define i8 @f(i1 %i, i8* %p) { - %1 = select i1 %i, i8(i8*)* @foo, i8(i8*)* @baz - %2 = call i8 %1(i8* %p) +define i8 @f(i1 %i, ptr %p) { + %1 = select i1 %i, ptr @foo, ptr @baz + %2 = call i8 %1(ptr %p) ret i8 %2 } diff --git a/llvm/test/ThinLTO/X86/cfi-icall.ll b/llvm/test/ThinLTO/X86/cfi-icall.ll --- a/llvm/test/ThinLTO/X86/cfi-icall.ll +++ b/llvm/test/ThinLTO/X86/cfi-icall.ll @@ -8,21 +8,21 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -define i1 @foo(i8* %p) !type !0 { +define i1 @foo(ptr %p) !type !0 { entry: - %x = call i1 @llvm.type.test(i8* %p, metadata !"typeid1") + %x = call i1 @llvm.type.test(ptr %p, metadata !"typeid1") ret i1 %x } -declare !type !0 i1 @bar(i8*) +declare !type !0 i1 @bar(ptr) ; Functions must be address taken to have jump table entries emitted define void @addrtaken(i1 %i) { - %1 = select i1 %i, i1(i8*)* @foo, i1(i8*)* @bar + %1 = select i1 %i, ptr @foo, ptr @bar ret void } -declare i1 @llvm.type.test(i8* %ptr, metadata %type) nounwind readnone +declare i1 @llvm.type.test(ptr %ptr, metadata %type) nounwind readnone !0 = !{i64 0, !"typeid1"} diff --git a/llvm/test/ThinLTO/X86/cfi-unsat.ll b/llvm/test/ThinLTO/X86/cfi-unsat.ll --- a/llvm/test/ThinLTO/X86/cfi-unsat.ll +++ b/llvm/test/ThinLTO/X86/cfi-unsat.ll @@ -31,28 +31,26 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } $test2 = comdat any -define linkonce_odr i32 @test2(%struct.A* %obj, i32 %a) comdat { +define linkonce_odr i32 @test2(ptr %obj, i32 %a) comdat { entry: - %0 = bitcast %struct.A* %obj to i8** - %vtable5 = load i8*, i8** %0 + %vtable5 = load ptr, ptr %obj - %1 = tail call { i8*, i1 } @llvm.type.checked.load(i8* %vtable5, i32 8, metadata !"_ZTS1A") - %2 = extractvalue { i8*, i1 } %1, 1 - br i1 %2, label %cont, label %trap + %0 = tail call { ptr, i1 } @llvm.type.checked.load(ptr %vtable5, i32 8, metadata !"_ZTS1A") + %1 = extractvalue { ptr, i1 } %0, 1 + br i1 %1, label %cont, label %trap trap: tail call void @llvm.trap() unreachable cont: - %3 = extractvalue { i8*, i1 } %1, 0 - %4 = bitcast i8* %3 to i32 (%struct.A*, i32)* + %2 = extractvalue { ptr, i1 } %0, 0 - %call = tail call i32 %4(%struct.A* nonnull %obj, i32 %a) + %call = tail call i32 %2(ptr nonnull %obj, i32 %a) ret i32 %call } @@ -76,5 +74,5 @@ ; CHECK-IR1-NEXT: unreachable ; CHECK-IR1-NEXT: } -declare { i8*, i1 } @llvm.type.checked.load(i8*, i32, metadata) +declare { ptr, i1 } @llvm.type.checked.load(ptr, i32, metadata) declare void @llvm.trap() diff --git a/llvm/test/ThinLTO/X86/cfi.ll b/llvm/test/ThinLTO/X86/cfi.ll --- a/llvm/test/ThinLTO/X86/cfi.ll +++ b/llvm/test/ThinLTO/X86/cfi.ll @@ -16,20 +16,19 @@ target triple = "x86_64-grtev4-linux-gnu" %struct.B = type { %struct.A } -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } -@_ZTV1B = constant { [3 x i8*] } { [3 x i8*] [i8* undef, i8* undef, i8* undef] }, !type !0 +@_ZTV1B = constant { [3 x ptr] } { [3 x ptr] [ptr undef, ptr undef, ptr undef] }, !type !0 ; CHECK-IR-LABEL: define void @test -define void @test(i8* %b) { +define void @test(ptr %b) { entry: ; Ensure that traps are conditional. Invalid TYPE_ID can cause ; unconditional traps. ; CHECK-IR: br i1 {{.*}}, label %trap - %0 = bitcast i8* %b to i8** - %vtable2 = load i8*, i8** %0 - %1 = tail call i1 @llvm.type.test(i8* %vtable2, metadata !"_ZTS1A") - br i1 %1, label %cont, label %trap + %vtable2 = load ptr, ptr %b + %0 = tail call i1 @llvm.type.test(ptr %vtable2, metadata !"_ZTS1A") + br i1 %0, label %cont, label %trap trap: tail call void @llvm.trap() @@ -41,10 +40,10 @@ } ; CHECK-IR-LABEL: } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.trap() -declare i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) +declare i32 @_ZN1B1fEi(ptr %this, i32 %a) !0 = !{i64 16, !"_ZTS1A"} !1 = !{i64 16, !"_ZTS1B"} diff --git a/llvm/test/ThinLTO/X86/ctor-dtor-alias.ll b/llvm/test/ThinLTO/X86/ctor-dtor-alias.ll --- a/llvm/test/ThinLTO/X86/ctor-dtor-alias.ll +++ b/llvm/test/ThinLTO/X86/ctor-dtor-alias.ll @@ -3,7 +3,7 @@ ;; template ;; struct A { A() {} virtual ~A() {} }; ;; template struct A; -;; void *foo() { return new A; } +;; ptr foo() { return new A; } ;; ;; clang -c -fpic -O1 -flto=thin a.cc && cp a.o b.o && ld.lld -shared a.o b.so diff --git a/llvm/test/ThinLTO/X86/ctor-dtor-alias2.ll b/llvm/test/ThinLTO/X86/ctor-dtor-alias2.ll --- a/llvm/test/ThinLTO/X86/ctor-dtor-alias2.ll +++ b/llvm/test/ThinLTO/X86/ctor-dtor-alias2.ll @@ -8,7 +8,7 @@ ;; template ;; struct A final { virtual ~A() {} }; ;; template struct A; -;; extern "C" void bb(A *a) { delete a; } +;; extern "C" void bb(Aptr a) { delete a; } ;; ;; clang -c -fpic -O0 -flto=thin a.cc && ld.lld -shared a.o b.o ;; diff --git a/llvm/test/ThinLTO/X86/devirt-after-icp.ll b/llvm/test/ThinLTO/X86/devirt-after-icp.ll --- a/llvm/test/ThinLTO/X86/devirt-after-icp.ll +++ b/llvm/test/ThinLTO/X86/devirt-after-icp.ll @@ -70,38 +70,33 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%class.A = type { i32 (...)** } +%class.A = type { ptr } %class.B = type { %class.A } -@_ZTV1A = linkonce_odr hidden unnamed_addr constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%class.A*)* @_ZN1A3fooEv to i8*), i8* bitcast (i32 (%class.A*)* @_ZN1A3barEv to i8*)] }, align 8, !type !0 -@_ZTV1B = hidden unnamed_addr constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%class.B*)* @_ZN1B3fooEv to i8*), i8* bitcast (i32 (%class.B*)* @_ZN1B3barEv to i8*)] }, align 8, !type !0, !type !1 +@_ZTV1A = linkonce_odr hidden unnamed_addr constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1A3fooEv, ptr @_ZN1A3barEv] }, align 8, !type !0 +@_ZTV1B = hidden unnamed_addr constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B3fooEv, ptr @_ZN1B3barEv] }, align 8, !type !0, !type !1 -define hidden i32 @_Z3bazP1A(%class.A* %a) local_unnamed_addr { +define hidden i32 @_Z3bazP1A(ptr %a) local_unnamed_addr { entry: - %0 = bitcast %class.A* %a to i32 (%class.A*)*** - %vtable = load i32 (%class.A*)**, i32 (%class.A*)*** %0, align 8 - %1 = bitcast i32 (%class.A*)** %vtable to i8* - %2 = tail call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1A") - tail call void @llvm.assume(i1 %2) - %3 = load i32 (%class.A*)*, i32 (%class.A*)** %vtable, align 8 + %vtable = load ptr, ptr %a, align 8 + %0 = tail call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1A") + tail call void @llvm.assume(i1 %0) + %1 = load ptr, ptr %vtable, align 8 ; This is the compare instruction inserted by ICP - %4 = icmp eq i32 (%class.A*)* %3, bitcast (i32 (%class.B*)* @_ZN1B3fooEv to i32 (%class.A*)*) - br i1 %4, label %if.true.direct_targ, label %if.false.orig_indirect + %2 = icmp eq ptr %1, @_ZN1B3fooEv + br i1 %2, label %if.true.direct_targ, label %if.false.orig_indirect ; This block contains the promoted and inlined call to B::foo(); ; CHECK-IR: if.true.direct_targ: ; preds = %entry if.true.direct_targ: ; preds = %entry - %5 = bitcast %class.A* %a to %class.B* - %6 = bitcast i32 (%class.A*)** %vtable to i8* - %7 = tail call i1 @llvm.type.test(i8* %6, metadata !"_ZTS1B") - tail call void @llvm.assume(i1 %7) - %vfn.i1 = getelementptr inbounds i32 (%class.A*)*, i32 (%class.A*)** %vtable, i64 1 - %vfn.i = bitcast i32 (%class.A*)** %vfn.i1 to i32 (%class.B*)** - %8 = load i32 (%class.B*)*, i32 (%class.B*)** %vfn.i, align 8 + %3 = tail call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1B") + tail call void @llvm.assume(i1 %3) + %vfn.i1 = getelementptr inbounds ptr, ptr %vtable, i64 1 + %4 = load ptr, ptr %vfn.i1, align 8 ; Call to bar() can be devirtualized to call to B::bar(), since it was ; inlined from B::foo() after ICP introduced the guarded promotion. ; CHECK-IR: %call.i = tail call i32 @_ZN1B3barEv(ptr nonnull %a) - %call.i = tail call i32 %8(%class.B* %5) + %call.i = tail call i32 %4(ptr %a) br label %if.end.icp ; This block contains the fallback indirect call a->foo() @@ -109,22 +104,22 @@ if.false.orig_indirect: ; preds = %entry ; Fallback indirect call to foo() cannot be devirtualized. ; CHECK-IR: %call = tail call i32 % - %call = tail call i32 %3(%class.A* nonnull %a) + %call = tail call i32 %1(ptr nonnull %a) br label %if.end.icp if.end.icp: ; preds = %if.false.orig_indirect, %if.true.direct_targ - %9 = phi i32 [ %call, %if.false.orig_indirect ], [ %call.i, %if.true.direct_targ ] - ret i32 %9 + %5 = phi i32 [ %call, %if.false.orig_indirect ], [ %call.i, %if.true.direct_targ ] + ret i32 %5 } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) -declare dso_local i32 @_ZN1B3fooEv(%class.B* %this) unnamed_addr -declare dso_local i32 @_ZN1B3barEv(%class.B*) unnamed_addr -declare dso_local i32 @_ZN1A3barEv(%class.A* %this) unnamed_addr -declare dso_local i32 @_ZN1A3fooEv(%class.A* %this) unnamed_addr +declare dso_local i32 @_ZN1B3fooEv(ptr %this) unnamed_addr +declare dso_local i32 @_ZN1B3barEv(ptr) unnamed_addr +declare dso_local i32 @_ZN1A3barEv(ptr %this) unnamed_addr +declare dso_local i32 @_ZN1A3fooEv(ptr %this) unnamed_addr !0 = !{i64 16, !"_ZTS1A"} !1 = !{i64 16, !"_ZTS1B"} diff --git a/llvm/test/ThinLTO/X86/devirt.ll b/llvm/test/ThinLTO/X86/devirt.ll --- a/llvm/test/ThinLTO/X86/devirt.ll +++ b/llvm/test/ThinLTO/X86/devirt.ll @@ -90,75 +90,68 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } %struct.B = type { %struct.A } %struct.C = type { %struct.A } -%struct.D = type { i32 (...)** } +%struct.D = type { ptr } -@_ZTV1B = constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !type !1 -@_ZTV1C = constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.C*, i32)* @_ZN1C1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !type !2 -@_ZTV1D = constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.D*, i32)* @_ZN1D1mEi to i8*)] }, !type !3 +@_ZTV1B = constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B1fEi, ptr @_ZN1A1nEi] }, !type !0, !type !1 +@_ZTV1C = constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1C1fEi, ptr @_ZN1A1nEi] }, !type !0, !type !2 +@_ZTV1D = constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr undef, ptr @_ZN1D1mEi] }, !type !3 ; CHECK-IR-LABEL: define i32 @test -define i32 @test(%struct.A* %obj, %struct.D* %obj2, i32 %a) { +define i32 @test(ptr %obj, ptr %obj2, i32 %a) { entry: - %0 = bitcast %struct.A* %obj to i8*** - %vtable = load i8**, i8*** %0 - %1 = bitcast i8** %vtable to i8* - %p = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1A") + %vtable = load ptr, ptr %obj + %p = call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1A") call void @llvm.assume(i1 %p) - %fptrptr = getelementptr i8*, i8** %vtable, i32 1 - %2 = bitcast i8** %fptrptr to i32 (%struct.A*, i32)** - %fptr1 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %2, align 8 + %fptrptr = getelementptr ptr, ptr %vtable, i32 1 + %fptr1 = load ptr, ptr %fptrptr, align 8 ; Check that the call was devirtualized. ; CHECK-IR: %call = tail call i32 @_ZN1A1nEi ; Ensure !prof and !callees metadata for indirect call promotion removed. ; CHECK-IR-NOT: prof ; CHECK-IR-NOT: callees - %call = tail call i32 %fptr1(%struct.A* nonnull %obj, i32 %a), !prof !5, !callees !6 + %call = tail call i32 %fptr1(ptr nonnull %obj, i32 %a), !prof !5, !callees !6 - %3 = bitcast i8** %vtable to i32 (%struct.A*, i32)** - %fptr22 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %3, align 8 + %fptr22 = load ptr, ptr %vtable, align 8 ; We still have to call it as virtual. ; CHECK-IR: %call3 = tail call i32 %fptr22 - %call3 = tail call i32 %fptr22(%struct.A* nonnull %obj, i32 %call) + %call3 = tail call i32 %fptr22(ptr nonnull %obj, i32 %call) - %4 = bitcast %struct.D* %obj2 to i8*** - %vtable2 = load i8**, i8*** %4 - %5 = bitcast i8** %vtable2 to i8* - %p2 = call i1 @llvm.type.test(i8* %5, metadata !4) + %vtable2 = load ptr, ptr %obj2 + %p2 = call i1 @llvm.type.test(ptr %vtable2, metadata !4) call void @llvm.assume(i1 %p2) - %6 = bitcast i8** %vtable2 to i32 (%struct.D*, i32)** - %fptr33 = load i32 (%struct.D*, i32)*, i32 (%struct.D*, i32)** %6, align 8 + %fptr33 = load ptr, ptr %vtable2, align 8 ; Check that the call was devirtualized. ; CHECK-IR: %call4 = tail call i32 @_ZN1D1mEi - %call4 = tail call i32 %fptr33(%struct.D* nonnull %obj2, i32 %call3) + %call4 = tail call i32 %fptr33(ptr nonnull %obj2, i32 %call3) ret i32 %call4 } ; CHECK-IR-LABEL: ret i32 ; CHECK-IR-LABEL: } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) -define i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) #0 { +define i32 @_ZN1B1fEi(ptr %this, i32 %a) #0 { ret i32 0; } -define i32 @_ZN1A1nEi(%struct.A* %this, i32 %a) #0 { +define i32 @_ZN1A1nEi(ptr %this, i32 %a) #0 { ret i32 0; } -define i32 @_ZN1C1fEi(%struct.C* %this, i32 %a) #0 { +define i32 @_ZN1C1fEi(ptr %this, i32 %a) #0 { ret i32 0; } -define i32 @_ZN1D1mEi(%struct.D* %this, i32 %a) #0 { +define i32 @_ZN1D1mEi(ptr %this, i32 %a) #0 { ret i32 0; } @@ -171,4 +164,4 @@ !3 = !{i64 16, !4} !4 = distinct !{} !5 = !{!"VP", i32 0, i64 1, i64 1621563287929432257, i64 1} -!6 = !{i32 (%struct.A*, i32)* @_ZN1A1nEi} +!6 = !{ptr @_ZN1A1nEi} diff --git a/llvm/test/ThinLTO/X86/devirt2.ll b/llvm/test/ThinLTO/X86/devirt2.ll --- a/llvm/test/ThinLTO/X86/devirt2.ll +++ b/llvm/test/ThinLTO/X86/devirt2.ll @@ -150,60 +150,53 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } %struct.B = type { %struct.A } %struct.C = type { %struct.A } -%struct.D = type { i32 (...)** } -%struct.E = type { i32 (...)** } +%struct.D = type { ptr } +%struct.E = type { ptr } -@_ZTV1B = external constant [4 x i8*] -@_ZTV1C = external constant [4 x i8*] -;@_ZTV1D = external constant [3 x i8*] -@_ZTV1D = linkonce_odr constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.D*, i32)* @_ZN1D1mEi to i8*)] }, !type !3 +@_ZTV1B = external constant [4 x ptr] +@_ZTV1C = external constant [4 x ptr] +;@_ZTV1D = external constant [3 x ptr] +@_ZTV1D = linkonce_odr constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr undef, ptr @_ZN1D1mEi] }, !type !3 -define linkonce_odr i32 @_ZN1D1mEi(%struct.D* %this, i32 %a) #0 { +define linkonce_odr i32 @_ZN1D1mEi(ptr %this, i32 %a) #0 { ret i32 0 } ; CHECK-IR1-LABEL: define i32 @test -define i32 @test(%struct.A* %obj, %struct.D* %obj2, %struct.E* %obj3, i32 %a) { +define i32 @test(ptr %obj, ptr %obj2, ptr %obj3, i32 %a) { entry: - %0 = bitcast %struct.A* %obj to i8*** - %vtable = load i8**, i8*** %0 - %1 = bitcast i8** %vtable to i8* - %p = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1A") + %vtable = load ptr, ptr %obj + %p = call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1A") call void @llvm.assume(i1 %p) - %fptrptr = getelementptr i8*, i8** %vtable, i32 1 - %2 = bitcast i8** %fptrptr to i32 (%struct.A*, i32)** - %fptr1 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %2, align 8 + %fptrptr = getelementptr ptr, ptr %vtable, i32 1 + %fptr1 = load ptr, ptr %fptrptr, align 8 ; Check that the call was devirtualized. Ignore extra character before ; symbol name which would happen if it was promoted during module ; splitting for hybrid WPD. ; CHECK-IR1: %call = tail call i32 @_ZN1A1nEi - %call = tail call i32 %fptr1(%struct.A* nonnull %obj, i32 %a) + %call = tail call i32 %fptr1(ptr nonnull %obj, i32 %a) - %3 = bitcast i8** %vtable to i32 (%struct.A*, i32)** - %fptr22 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %3, align 8 + %fptr22 = load ptr, ptr %vtable, align 8 ; We still have to call it as virtual. ; CHECK-IR1: %call3 = tail call i32 %fptr22 - %call3 = tail call i32 %fptr22(%struct.A* nonnull %obj, i32 %call) + %call3 = tail call i32 %fptr22(ptr nonnull %obj, i32 %call) - %4 = bitcast %struct.D* %obj2 to i8*** - %vtable2 = load i8**, i8*** %4 - %5 = bitcast i8** %vtable2 to i8* - %p2 = call i1 @llvm.type.test(i8* %5, metadata !"_ZTS1D") + %vtable2 = load ptr, ptr %obj2 + %p2 = call i1 @llvm.type.test(ptr %vtable2, metadata !"_ZTS1D") call void @llvm.assume(i1 %p2) - %6 = bitcast i8** %vtable2 to i32 (%struct.D*, i32)** - %fptr33 = load i32 (%struct.D*, i32)*, i32 (%struct.D*, i32)** %6, align 8 + %fptr33 = load ptr, ptr %vtable2, align 8 ; Check that the call was devirtualized. ; CHECK-IR1: %call4 = tail call i32 @_ZN1D1mEi - %call4 = tail call i32 %fptr33(%struct.D* nonnull %obj2, i32 %call3) + %call4 = tail call i32 %fptr33(ptr nonnull %obj2, i32 %call3) - %call5 = tail call i32 @test2(%struct.E* nonnull %obj3, i32 %call4) + %call5 = tail call i32 @test2(ptr nonnull %obj3, i32 %call4) ret i32 %call5 } ; CHECK-IR1-LABEL: ret i32 @@ -216,9 +209,9 @@ ; splitting for hybrid WPD. ; CHECK-IR2-NEXT: %call4 = tail call i32 @{{.*}}_ZN1E1mEi -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) -declare i32 @test2(%struct.E* %obj, i32 %a) +declare i32 @test2(ptr %obj, i32 %a) attributes #0 = { noinline optnone } diff --git a/llvm/test/ThinLTO/X86/devirt_after_filtering_unreachable.ll b/llvm/test/ThinLTO/X86/devirt_after_filtering_unreachable.ll --- a/llvm/test/ThinLTO/X86/devirt_after_filtering_unreachable.ll +++ b/llvm/test/ThinLTO/X86/devirt_after_filtering_unreachable.ll @@ -64,21 +64,18 @@ target triple = "x86_64-unknown-linux-gnu" %Derived = type { %Base } -%Base = type { i32 (...)** } +%Base = type { ptr } -@_ZTV7Derived = external constant { [5 x i8*] } +@_ZTV7Derived = external constant { [5 x ptr] } define hidden i32 @main() { entry: - %call = tail call i8* @_Znwm(i64 8) - %0 = bitcast i8* %call to %Derived* - %1 = getelementptr inbounds %Derived, %Derived* %0, i64 0, i32 0, i32 0 - store i32 (...)** bitcast (i8** getelementptr inbounds ({ [5 x i8*] }, { [5 x i8*] }* @_ZTV7Derived, i64 0, inrange i32 0, i64 2) to i32 (...)**), i32 (...)*** %1 - %2 = getelementptr %Derived, %Derived* %0, i64 0, i32 0 - tail call void @_Z3fooP4Base(%Base* nonnull %2) + %call = tail call ptr @_Znwm(i64 8) + store ptr getelementptr inbounds ({ [5 x ptr] }, ptr @_ZTV7Derived, i64 0, inrange i32 0, i64 2), ptr %call + tail call void @_Z3fooP4Base(ptr nonnull %call) ret i32 0 } -declare i8* @_Znwm(i64) +declare ptr @_Znwm(i64) -declare void @_Z3fooP4Base(%Base*) +declare void @_Z3fooP4Base(ptr) diff --git a/llvm/test/ThinLTO/X86/devirt_alias.ll b/llvm/test/ThinLTO/X86/devirt_alias.ll --- a/llvm/test/ThinLTO/X86/devirt_alias.ll +++ b/llvm/test/ThinLTO/X86/devirt_alias.ll @@ -26,33 +26,30 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.D = type { i32 (...)** } +%struct.D = type { ptr } -@_ZTV1D = linkonce_odr constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.D*, i32)* @_ZN1D1mEi to i8*)] }, !type !3 +@_ZTV1D = linkonce_odr constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr undef, ptr @_ZN1D1mEi] }, !type !3 ; CHECK-IR1-LABEL: define i32 @test -define i32 @test(%struct.D* %obj2, i32 %a) { +define i32 @test(ptr %obj2, i32 %a) { entry: - %0 = bitcast %struct.D* %obj2 to i8*** - %vtable2 = load i8**, i8*** %0 - %1 = bitcast i8** %vtable2 to i8* - %p2 = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1D") + %vtable2 = load ptr, ptr %obj2 + %p2 = call i1 @llvm.type.test(ptr %vtable2, metadata !"_ZTS1D") call void @llvm.assume(i1 %p2) - %2 = bitcast i8** %vtable2 to i32 (%struct.D*, i32)** - %fptr33 = load i32 (%struct.D*, i32)*, i32 (%struct.D*, i32)** %2, align 8 + %fptr33 = load ptr, ptr %vtable2, align 8 ; Check that the call was devirtualized. ; CHECK-IR1: %call4 = tail call i32 @_ZN1D1mEi - %call4 = tail call i32 %fptr33(%struct.D* nonnull %obj2, i32 %a) + %call4 = tail call i32 %fptr33(ptr nonnull %obj2, i32 %a) ret i32 %call4 } ; CHECK-IR1-LABEL: ret i32 ; CHECK-IR1-LABEL: } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) -declare i32 @_ZN1D1mEi(%struct.D* %this, i32 %a) +declare i32 @_ZN1D1mEi(ptr %this, i32 %a) attributes #0 = { noinline optnone } diff --git a/llvm/test/ThinLTO/X86/devirt_available_externally.ll b/llvm/test/ThinLTO/X86/devirt_available_externally.ll --- a/llvm/test/ThinLTO/X86/devirt_available_externally.ll +++ b/llvm/test/ThinLTO/X86/devirt_available_externally.ll @@ -42,32 +42,29 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.D = type { i32 (...)** } +%struct.D = type { ptr } -@_ZTV1D = available_externally constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.D*, i32)* @_ZN1D1mEi to i8*)] } +@_ZTV1D = available_externally constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr undef, ptr @_ZN1D1mEi] } ; CHECK-IR1-LABEL: define i32 @test -define i32 @test(%struct.D* %obj2, i32 %a) { +define i32 @test(ptr %obj2, i32 %a) { entry: - %0 = bitcast %struct.D* %obj2 to i8*** - %vtable2 = load i8**, i8*** %0 - %1 = bitcast i8** %vtable2 to i8* - %p2 = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1D") + %vtable2 = load ptr, ptr %obj2 + %p2 = call i1 @llvm.type.test(ptr %vtable2, metadata !"_ZTS1D") call void @llvm.assume(i1 %p2) - %2 = bitcast i8** %vtable2 to i32 (%struct.D*, i32)** - %fptr33 = load i32 (%struct.D*, i32)*, i32 (%struct.D*, i32)** %2, align 8 + %fptr33 = load ptr, ptr %vtable2, align 8 ; Check that the call was devirtualized. ; CHECK-IR1: %call4 = tail call i32 @_ZN1D1mEi - %call4 = tail call i32 %fptr33(%struct.D* nonnull %obj2, i32 %a) + %call4 = tail call i32 %fptr33(ptr nonnull %obj2, i32 %a) ret i32 %call4 } ; CHECK-IR1-LABEL: ret i32 ; CHECK-IR1-LABEL: } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) -declare i32 @_ZN1D1mEi(%struct.D* %this, i32 %a) +declare i32 @_ZN1D1mEi(ptr %this, i32 %a) attributes #0 = { noinline optnone } diff --git a/llvm/test/ThinLTO/X86/devirt_external_comdat_same_guid.ll b/llvm/test/ThinLTO/X86/devirt_external_comdat_same_guid.ll --- a/llvm/test/ThinLTO/X86/devirt_external_comdat_same_guid.ll +++ b/llvm/test/ThinLTO/X86/devirt_external_comdat_same_guid.ll @@ -33,44 +33,40 @@ source_filename = "-" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } %struct.B = type { %struct.A } $_ZTV1B = comdat any -@_ZTV1B = constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1nEi to i8*)] }, comdat, !type !0, !type !1 +@_ZTV1B = constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B1fEi, ptr @_ZN1B1nEi] }, comdat, !type !0, !type !1 -define i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) #0 comdat($_ZTV1B) { +define i32 @_ZN1B1fEi(ptr %this, i32 %a) #0 comdat($_ZTV1B) { ret i32 0; } -define i32 @_ZN1B1nEi(%struct.B* %this, i32 %a) #0 comdat($_ZTV1B) { +define i32 @_ZN1B1nEi(ptr %this, i32 %a) #0 comdat($_ZTV1B) { ret i32 0; } ; Ensures that vtable of B is live so that we will attempt devirt. -define dso_local i32 @use_B(%struct.B* %a) { +define dso_local i32 @use_B(ptr %a) { entry: - %0 = bitcast %struct.B* %a to i32 (...)*** - store i32 (...)** bitcast (i8** getelementptr inbounds ({ [4 x i8*] }, { [4 x i8*] }* @_ZTV1B, i64 0, inrange i32 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 8 + store ptr getelementptr inbounds ({ [4 x ptr] }, ptr @_ZTV1B, i64 0, inrange i32 0, i64 2), ptr %a, align 8 ret i32 0 } ; CHECK-IR1: define i32 @test( -define i32 @test(%struct.A* %obj, i32 %a) { +define i32 @test(ptr %obj, i32 %a) { entry: - %0 = bitcast %struct.A* %obj to i8*** - %vtable = load i8**, i8*** %0 - %1 = bitcast i8** %vtable to i8* - %p = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1A") + %vtable = load ptr, ptr %obj + %p = call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1A") call void @llvm.assume(i1 %p) - %fptrptr = getelementptr i8*, i8** %vtable, i32 1 - %2 = bitcast i8** %fptrptr to i32 (%struct.A*, i32)** - %fptr1 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %2, align 8 + %fptrptr = getelementptr ptr, ptr %vtable, i32 1 + %fptr1 = load ptr, ptr %fptrptr, align 8 ; Check that the call was devirtualized. ; CHECK-IR1: tail call i32 {{.*}}@_ZN1A1nEi - %call = tail call i32 %fptr1(%struct.A* nonnull %obj, i32 %a) + %call = tail call i32 %fptr1(ptr nonnull %obj, i32 %a) ret i32 %call } @@ -79,7 +75,7 @@ ; Check that the call was devirtualized. ; CHECK-IR2: tail call i32 @_ZN1A1nEi -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) attributes #0 = { noinline optnone } diff --git a/llvm/test/ThinLTO/X86/devirt_local_same_guid.ll b/llvm/test/ThinLTO/X86/devirt_local_same_guid.ll --- a/llvm/test/ThinLTO/X86/devirt_local_same_guid.ll +++ b/llvm/test/ThinLTO/X86/devirt_local_same_guid.ll @@ -21,42 +21,38 @@ source_filename = "-" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } %struct.B = type { %struct.A } -@_ZTV1B = internal constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1nEi to i8*)] }, !type !0, !type !1 +@_ZTV1B = internal constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B1fEi, ptr @_ZN1B1nEi] }, !type !0, !type !1 -define internal i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) #0 { +define internal i32 @_ZN1B1fEi(ptr %this, i32 %a) #0 { ret i32 0; } -define internal i32 @_ZN1B1nEi(%struct.B* %this, i32 %a) #0 { +define internal i32 @_ZN1B1nEi(ptr %this, i32 %a) #0 { ret i32 0; } ; Ensures that vtable of B is live so that we will attempt devirt. -define dso_local i32 @use_B(%struct.B* %a) { +define dso_local i32 @use_B(ptr %a) { entry: - %0 = bitcast %struct.B* %a to i32 (...)*** - store i32 (...)** bitcast (i8** getelementptr inbounds ({ [4 x i8*] }, { [4 x i8*] }* @_ZTV1B, i64 0, inrange i32 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 8 + store ptr getelementptr inbounds ({ [4 x ptr] }, ptr @_ZTV1B, i64 0, inrange i32 0, i64 2), ptr %a, align 8 ret i32 0 } ; CHECK-IR1: define i32 @test( -define i32 @test(%struct.A* %obj, i32 %a) { +define i32 @test(ptr %obj, i32 %a) { entry: - %0 = bitcast %struct.A* %obj to i8*** - %vtable = load i8**, i8*** %0 - %1 = bitcast i8** %vtable to i8* - %p = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1A") + %vtable = load ptr, ptr %obj + %p = call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1A") call void @llvm.assume(i1 %p) - %fptrptr = getelementptr i8*, i8** %vtable, i32 1 - %2 = bitcast i8** %fptrptr to i32 (%struct.A*, i32)** - %fptr1 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %2, align 8 + %fptrptr = getelementptr ptr, ptr %vtable, i32 1 + %fptr1 = load ptr, ptr %fptrptr, align 8 ; Check that the call was not devirtualized. ; CHECK-IR1: %call = tail call i32 %fptr1 - %call = tail call i32 %fptr1(%struct.A* nonnull %obj, i32 %a) + %call = tail call i32 %fptr1(ptr nonnull %obj, i32 %a) ret i32 %call } @@ -65,7 +61,7 @@ ; Check that the call was not devirtualized. ; CHECK-IR2: %call4 = tail call i32 %fptr -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) attributes #0 = { noinline optnone } diff --git a/llvm/test/ThinLTO/X86/devirt_multiple_type_test.ll b/llvm/test/ThinLTO/X86/devirt_multiple_type_test.ll --- a/llvm/test/ThinLTO/X86/devirt_multiple_type_test.ll +++ b/llvm/test/ThinLTO/X86/devirt_multiple_type_test.ll @@ -23,41 +23,36 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -%class.A = type { i32 (...)** } +%class.A = type { ptr } %class.B = type { %class.A } -@_ZTV1A = hidden unnamed_addr constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* undef, i8* bitcast (void (%class.A*)* @_ZN1A3fooEv to i8*)] }, align 8, !type !0, !vcall_visibility !2 -@_ZTV1B = hidden unnamed_addr constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* undef, i8* bitcast (void (%class.B*)* @_ZN1B3fooEv to i8*)] }, align 8, !type !0, !type !3, !vcall_visibility !2 +@_ZTV1A = hidden unnamed_addr constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr undef, ptr @_ZN1A3fooEv] }, align 8, !type !0, !vcall_visibility !2 +@_ZTV1B = hidden unnamed_addr constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr undef, ptr @_ZN1B3fooEv] }, align 8, !type !0, !type !3, !vcall_visibility !2 -declare void @_ZN1A3fooEv(%class.A* nocapture %this) +declare void @_ZN1A3fooEv(ptr nocapture %this) -define hidden void @_ZN1B3fooEv(%class.B* nocapture %this) { +define hidden void @_ZN1B3fooEv(ptr nocapture %this) { entry: ret void } ; Function Attrs: nounwind readnone willreturn -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) ; Function Attrs: nounwind willreturn declare void @llvm.assume(i1) ; Function Attrs: uwtable -define hidden void @_Z6callerP1B(%class.B* %b) local_unnamed_addr { +define hidden void @_Z6callerP1B(ptr %b) local_unnamed_addr { entry: - %0 = bitcast %class.B* %b to void (%class.B*)*** - %vtable = load void (%class.B*)**, void (%class.B*)*** %0, align 8, !tbaa !12, !invariant.group !15 - %1 = bitcast void (%class.B*)** %vtable to i8* - %2 = tail call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1B") + %vtable = load ptr, ptr %b, align 8, !tbaa !12, !invariant.group !15 + %0 = tail call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1B") + tail call void @llvm.assume(i1 %0) + %1 = load ptr, ptr %vtable, align 8, !invariant.load !15 + tail call void %1(ptr %b) + %2 = tail call i1 @llvm.type.test(ptr nonnull %vtable, metadata !"_ZTS1A") tail call void @llvm.assume(i1 %2) - %3 = load void (%class.B*)*, void (%class.B*)** %vtable, align 8, !invariant.load !15 - tail call void %3(%class.B* %b) - %4 = getelementptr %class.B, %class.B* %b, i64 0, i32 0 - %5 = bitcast void (%class.B*)** %vtable to i8* - %6 = tail call i1 @llvm.type.test(i8* nonnull %5, metadata !"_ZTS1A") - tail call void @llvm.assume(i1 %6) - %7 = bitcast void (%class.B*)* %3 to void (%class.A*)* - tail call void %7(%class.A* %4) + tail call void %1(ptr %b) ret void } diff --git a/llvm/test/ThinLTO/X86/devirt_promote.ll b/llvm/test/ThinLTO/X86/devirt_promote.ll --- a/llvm/test/ThinLTO/X86/devirt_promote.ll +++ b/llvm/test/ThinLTO/X86/devirt_promote.ll @@ -43,23 +43,20 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } ; CHECK-IR1-LABEL: define i32 @test -define i32 @test(%struct.A* %obj, i32 %a) { +define i32 @test(ptr %obj, i32 %a) { entry: - %0 = bitcast %struct.A* %obj to i8*** - %vtable = load i8**, i8*** %0 - %1 = bitcast i8** %vtable to i8* - %p = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1A") + %vtable = load ptr, ptr %obj + %p = call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1A") call void @llvm.assume(i1 %p) - %fptrptr = getelementptr i8*, i8** %vtable, i32 1 - %2 = bitcast i8** %fptrptr to i32 (%struct.A*, i32)** - %fptr1 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %2, align 8 + %fptrptr = getelementptr ptr, ptr %vtable, i32 1 + %fptr1 = load ptr, ptr %fptrptr, align 8 ; Check that the call was devirtualized. ; CHECK-IR1: %call = tail call i32 @_ZN1A1nEi - %call = tail call i32 %fptr1(%struct.A* nonnull %obj, i32 %a) + %call = tail call i32 %fptr1(ptr nonnull %obj, i32 %a) ret i32 %call } @@ -70,7 +67,7 @@ ; Check that the call was devirtualized. ; CHECK-IR2: %call4 = tail call i32 @_ZN1A1nEi -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) attributes #0 = { noinline optnone } diff --git a/llvm/test/ThinLTO/X86/devirt_pure_virtual_base.ll b/llvm/test/ThinLTO/X86/devirt_pure_virtual_base.ll --- a/llvm/test/ThinLTO/X86/devirt_pure_virtual_base.ll +++ b/llvm/test/ThinLTO/X86/devirt_pure_virtual_base.ll @@ -57,50 +57,47 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } %struct.B = type { %struct.A } -@_ZTV1A = linkonce_odr unnamed_addr constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (void ()* @__cxa_pure_virtual to i8*), i8* bitcast (void ()* @__cxa_pure_virtual to i8*)] }, !type !0, !vcall_visibility !2 -@_ZTV1B = linkonce_odr unnamed_addr constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !type !1, !vcall_visibility !2 +@_ZTV1A = linkonce_odr unnamed_addr constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @__cxa_pure_virtual, ptr @__cxa_pure_virtual] }, !type !0, !vcall_visibility !2 +@_ZTV1B = linkonce_odr unnamed_addr constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B1fEi, ptr @_ZN1A1nEi] }, !type !0, !type !1, !vcall_visibility !2 ;; Prevent the vtables from being dead code eliminated. -@llvm.used = appending global [2 x i8*] [ i8* bitcast ( { [4 x i8*] }* @_ZTV1A to i8*), i8* bitcast ( { [4 x i8*] }* @_ZTV1B to i8*)] +@llvm.used = appending global [2 x ptr] [ ptr @_ZTV1A, ptr @_ZTV1B] ; CHECK-IR-LABEL: define dso_local i32 @_start -define i32 @_start(%struct.A* %obj, i32 %a) { +define i32 @_start(ptr %obj, i32 %a) { entry: - %0 = bitcast %struct.A* %obj to i8*** - %vtable = load i8**, i8*** %0 - %1 = bitcast i8** %vtable to i8* - %p = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1A") + %vtable = load ptr, ptr %obj + %p = call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1A") call void @llvm.assume(i1 %p) - %fptrptr = getelementptr i8*, i8** %vtable, i32 1 - %2 = bitcast i8** %fptrptr to i32 (%struct.A*, i32)** - %fptr1 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %2, align 8 + %fptrptr = getelementptr ptr, ptr %vtable, i32 1 + %fptr1 = load ptr, ptr %fptrptr, align 8 ;; Check that the call was devirtualized. ; CHECK-IR: %call = tail call i32 @_ZN1A1nEi ; CHECK-NODEVIRT-IR: %call = tail call i32 %fptr1 - %call = tail call i32 %fptr1(%struct.A* nonnull %obj, i32 %a) + %call = tail call i32 %fptr1(ptr nonnull %obj, i32 %a) ret i32 %call } ; CHECK-IR-LABEL: ret i32 ; CHECK-IR-NEXT: } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) declare void @__cxa_pure_virtual() unnamed_addr -define linkonce_odr i32 @_ZN1A1fEi(%struct.A* %this, i32 %a) #0 { +define linkonce_odr i32 @_ZN1A1fEi(ptr %this, i32 %a) #0 { ret i32 0 } -define linkonce_odr i32 @_ZN1A1nEi(%struct.A* %this, i32 %a) #0 { +define linkonce_odr i32 @_ZN1A1nEi(ptr %this, i32 %a) #0 { ret i32 0 } -define linkonce_odr i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) #0 { +define linkonce_odr i32 @_ZN1B1fEi(ptr %this, i32 %a) #0 { ret i32 0 } diff --git a/llvm/test/ThinLTO/X86/devirt_vcall_vis_hidden.ll b/llvm/test/ThinLTO/X86/devirt_vcall_vis_hidden.ll --- a/llvm/test/ThinLTO/X86/devirt_vcall_vis_hidden.ll +++ b/llvm/test/ThinLTO/X86/devirt_vcall_vis_hidden.ll @@ -61,72 +61,65 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -%struct.A = type { i32 (...)** } +%struct.A = type { ptr } %struct.B = type { %struct.A } %struct.C = type { %struct.A } -%struct.D = type { i32 (...)** } +%struct.D = type { ptr } -@_ZTV1B = constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.B*, i32)* @_ZN1B1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !type !1, !vcall_visibility !5 -@_ZTV1C = constant { [4 x i8*] } { [4 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.C*, i32)* @_ZN1C1fEi to i8*), i8* bitcast (i32 (%struct.A*, i32)* @_ZN1A1nEi to i8*)] }, !type !0, !type !2, !vcall_visibility !5 -@_ZTV1D = constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.D*, i32)* @_ZN1D1mEi to i8*)] }, !type !3, !vcall_visibility !5 +@_ZTV1B = constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1B1fEi, ptr @_ZN1A1nEi] }, !type !0, !type !1, !vcall_visibility !5 +@_ZTV1C = constant { [4 x ptr] } { [4 x ptr] [ptr null, ptr undef, ptr @_ZN1C1fEi, ptr @_ZN1A1nEi] }, !type !0, !type !2, !vcall_visibility !5 +@_ZTV1D = constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr undef, ptr @_ZN1D1mEi] }, !type !3, !vcall_visibility !5 ; CHECK-IR-LABEL: define i32 @test -define i32 @test(%struct.A* %obj, %struct.D* %obj2, i32 %a) { +define i32 @test(ptr %obj, ptr %obj2, i32 %a) { entry: - %0 = bitcast %struct.A* %obj to i8*** - %vtable = load i8**, i8*** %0 - %1 = bitcast i8** %vtable to i8* - %p = call i1 @llvm.type.test(i8* %1, metadata !"_ZTS1A") + %vtable = load ptr, ptr %obj + %p = call i1 @llvm.type.test(ptr %vtable, metadata !"_ZTS1A") call void @llvm.assume(i1 %p) - %fptrptr = getelementptr i8*, i8** %vtable, i32 1 - %2 = bitcast i8** %fptrptr to i32 (%struct.A*, i32)** - %fptr1 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %2, align 8 + %fptrptr = getelementptr ptr, ptr %vtable, i32 1 + %fptr1 = load ptr, ptr %fptrptr, align 8 ; Check that the call was devirtualized. ; CHECK-IR: %call = tail call i32 @_ZN1A1nEi - %call = tail call i32 %fptr1(%struct.A* nonnull %obj, i32 %a) + %call = tail call i32 %fptr1(ptr nonnull %obj, i32 %a) - %3 = bitcast i8** %vtable to i32 (%struct.A*, i32)** - %fptr22 = load i32 (%struct.A*, i32)*, i32 (%struct.A*, i32)** %3, align 8 + %fptr22 = load ptr, ptr %vtable, align 8 ; We still have to call it as virtual. ; CHECK-IR: %call3 = tail call i32 %fptr22 - %call3 = tail call i32 %fptr22(%struct.A* nonnull %obj, i32 %call) + %call3 = tail call i32 %fptr22(ptr nonnull %obj, i32 %call) - %4 = bitcast %struct.D* %obj2 to i8*** - %vtable2 = load i8**, i8*** %4 - %5 = bitcast i8** %vtable2 to i8* - %p2 = call i1 @llvm.type.test(i8* %5, metadata !4) + %vtable2 = load ptr, ptr %obj2 + %p2 = call i1 @llvm.type.test(ptr %vtable2, metadata !4) call void @llvm.assume(i1 %p2) - %6 = bitcast i8** %vtable2 to i32 (%struct.D*, i32)** - %fptr33 = load i32 (%struct.D*, i32)*, i32 (%struct.D*, i32)** %6, align 8 + %fptr33 = load ptr, ptr %vtable2, align 8 ; Check that the call was devirtualized. ; CHECK-IR: %call4 = tail call i32 @_ZN1D1mEi - %call4 = tail call i32 %fptr33(%struct.D* nonnull %obj2, i32 %call3) + %call4 = tail call i32 %fptr33(ptr nonnull %obj2, i32 %call3) ret i32 %call4 } ; CHECK-IR-LABEL: ret i32 ; CHECK-IR-LABEL: } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) -define i32 @_ZN1B1fEi(%struct.B* %this, i32 %a) #0 { +define i32 @_ZN1B1fEi(ptr %this, i32 %a) #0 { ret i32 0; } -define i32 @_ZN1A1nEi(%struct.A* %this, i32 %a) #0 { +define i32 @_ZN1A1nEi(ptr %this, i32 %a) #0 { ret i32 0; } -define i32 @_ZN1C1fEi(%struct.C* %this, i32 %a) #0 { +define i32 @_ZN1C1fEi(ptr %this, i32 %a) #0 { ret i32 0; } -define i32 @_ZN1D1mEi(%struct.D* %this, i32 %a) #0 { +define i32 @_ZN1D1mEi(ptr %this, i32 %a) #0 { ret i32 0; } diff --git a/llvm/test/ThinLTO/X86/dicompositetype-unique-alias.ll b/llvm/test/ThinLTO/X86/dicompositetype-unique-alias.ll --- a/llvm/test/ThinLTO/X86/dicompositetype-unique-alias.ll +++ b/llvm/test/ThinLTO/X86/dicompositetype-unique-alias.ll @@ -23,26 +23,26 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-scei-ps4" -%class.C = type <{ i32 (...)**, %class.A, %struct.CFVS, [6 x i8] }> +%class.C = type <{ ptr, %class.A, %struct.CFVS, [6 x i8] }> %class.A = type { %struct.Vec } %struct.Vec = type { i8 } %struct.CFVS = type { %struct.Vec } %struct.S = type { i8 } -define void @_ZN1CD2Ev(%class.C* %this) unnamed_addr align 2 { +define void @_ZN1CD2Ev(ptr %this) unnamed_addr align 2 { entry: - %this.addr = alloca %class.C*, align 8 - %this1 = load %class.C*, %class.C** %this.addr, align 8 - %m = getelementptr inbounds %class.C, %class.C* %this1, i32 0, i32 2 - call void @_ZN4CFVSD1Ev(%struct.CFVS* %m), !dbg !50 - call void @_ZN4CFVSD2Ev(%struct.CFVS* %m), !dbg !50 + %this.addr = alloca ptr, align 8 + %this1 = load ptr, ptr %this.addr, align 8 + %m = getelementptr inbounds %class.C, ptr %this1, i32 0, i32 2 + call void @_ZN4CFVSD1Ev(ptr %m), !dbg !50 + call void @_ZN4CFVSD2Ev(ptr %m), !dbg !50 ret void } -declare void @_ZN4CFVSD1Ev(%struct.CFVS*) unnamed_addr -declare void @_ZN4CFVSD2Ev(%struct.CFVS*) unnamed_addr +declare void @_ZN4CFVSD1Ev(ptr) unnamed_addr +declare void @_ZN4CFVSD2Ev(ptr) unnamed_addr -declare dereferenceable(1) %struct.S* @_Z3Getv() +declare dereferenceable(1) ptr @_Z3Getv() !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3, !4, !5, !6} diff --git a/llvm/test/ThinLTO/X86/dicompositetype-unique2.ll b/llvm/test/ThinLTO/X86/dicompositetype-unique2.ll --- a/llvm/test/ThinLTO/X86/dicompositetype-unique2.ll +++ b/llvm/test/ThinLTO/X86/dicompositetype-unique2.ll @@ -16,24 +16,24 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-scei-ps4" -%class.C = type <{ i32 (...)**, %class.A, %struct.CFVS, [6 x i8] }> +%class.C = type <{ ptr, %class.A, %struct.CFVS, [6 x i8] }> %class.A = type { %struct.Vec } %struct.Vec = type { i8 } %struct.CFVS = type { %struct.Vec } %struct.S = type { i8 } -define void @_ZN1CD2Ev(%class.C* %this) unnamed_addr align 2 !dbg !8 { +define void @_ZN1CD2Ev(ptr %this) unnamed_addr align 2 !dbg !8 { entry: - %this.addr = alloca %class.C*, align 8 - %this1 = load %class.C*, %class.C** %this.addr, align 8 - %m = getelementptr inbounds %class.C, %class.C* %this1, i32 0, i32 2 - call void @_ZN4CFVSD2Ev(%struct.CFVS* %m), !dbg !50 + %this.addr = alloca ptr, align 8 + %this1 = load ptr, ptr %this.addr, align 8 + %m = getelementptr inbounds %class.C, ptr %this1, i32 0, i32 2 + call void @_ZN4CFVSD2Ev(ptr %m), !dbg !50 ret void } -declare void @_ZN4CFVSD2Ev(%struct.CFVS*) unnamed_addr +declare void @_ZN4CFVSD2Ev(ptr) unnamed_addr -declare dereferenceable(1) %struct.S* @_Z3Getv() +declare dereferenceable(1) ptr @_Z3Getv() !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3, !4, !5, !6} @@ -52,7 +52,7 @@ !16 = !DIFile(filename: "./bz188598.h", directory: ".") !17 = !{!55} !22 = !{!23} -!23 = !DITemplateValueParameter(name: "F", type: !24, value: %struct.S* ()* @_Z3Getv) +!23 = !DITemplateValueParameter(name: "F", type: !24, value: ptr @_Z3Getv) !24 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !25, size: 64) !25 = !DIDerivedType(tag: DW_TAG_typedef, name: "Func", file: !16, line: 2, baseType: !26) !26 = !DISubroutineType(types: !27) diff --git a/llvm/test/ThinLTO/X86/dot-dumper-full-lto.ll b/llvm/test/ThinLTO/X86/dot-dumper-full-lto.ll --- a/llvm/test/ThinLTO/X86/dot-dumper-full-lto.ll +++ b/llvm/test/ThinLTO/X86/dot-dumper-full-lto.ll @@ -20,7 +20,7 @@ @A = external global i32 define i32 @main() { - %v = load i32, i32* @A + %v = load i32, ptr @A ret i32 %v } diff --git a/llvm/test/ThinLTO/X86/dot-dumper.ll b/llvm/test/ThinLTO/X86/dot-dumper.ll --- a/llvm/test/ThinLTO/X86/dot-dumper.ll +++ b/llvm/test/ThinLTO/X86/dot-dumper.ll @@ -71,9 +71,9 @@ ; Function Attrs: nounwind uwtable define i32 @main() local_unnamed_addr { %1 = tail call i32 (...) @foo() - %2 = load i32, i32* @A, align 4 + %2 = load i32, ptr @A, align 4 %3 = add nsw i32 %2, %1 ret i32 %3 } -@main_alias = weak_odr alias i32 (), i32 ()* @main +@main_alias = weak_odr alias i32 (), ptr @main declare i32 @foo(...) local_unnamed_addr diff --git a/llvm/test/ThinLTO/X86/export.ll b/llvm/test/ThinLTO/X86/export.ll --- a/llvm/test/ThinLTO/X86/export.ll +++ b/llvm/test/ThinLTO/X86/export.ll @@ -21,6 +21,6 @@ define internal void @staticfunc() #0 { entry: - %0 = load i32, i32* @staticvar, align 4 + %0 = load i32, ptr @staticvar, align 4 ret void } diff --git a/llvm/test/ThinLTO/X86/funcattrs-prop-maythrow.ll b/llvm/test/ThinLTO/X86/funcattrs-prop-maythrow.ll --- a/llvm/test/ThinLTO/X86/funcattrs-prop-maythrow.ll +++ b/llvm/test/ThinLTO/X86/funcattrs-prop-maythrow.ll @@ -63,7 +63,7 @@ declare i32 @__gxx_personality_v0(...) -define void @cleanupret() personality i32 (...)* @__gxx_personality_v0 { +define void @cleanupret() personality ptr @__gxx_personality_v0 { entry: invoke void @nonThrowing() to label %exit unwind label %pad @@ -74,7 +74,7 @@ ret void } -define void @catchret() personality i32 (...)* @__gxx_personality_v0 { +define void @catchret() personality ptr @__gxx_personality_v0 { entry: invoke void @nonThrowing() to label %exit unwind label %pad @@ -87,7 +87,7 @@ ret void } -define void @resume() uwtable optsize ssp personality i32 (...)* @__gxx_personality_v0 { +define void @resume() uwtable optsize ssp personality ptr @__gxx_personality_v0 { entry: invoke void @nonThrowing() to label %try.cont unwind label %lpad @@ -96,12 +96,12 @@ ret void lpad: ; preds = %entry - %exn = landingpad {i8*, i32} + %exn = landingpad {ptr, i32} cleanup - resume { i8*, i32 } %exn + resume { ptr, i32 } %exn } -define void @cleanupret_nounwind() #0 personality i32 (...)* @__gxx_personality_v0 { +define void @cleanupret_nounwind() #0 personality ptr @__gxx_personality_v0 { entry: invoke void @nonThrowing() to label %exit unwind label %pad diff --git a/llvm/test/ThinLTO/X86/funcattrs-prop-unknown.ll b/llvm/test/ThinLTO/X86/funcattrs-prop-unknown.ll --- a/llvm/test/ThinLTO/X86/funcattrs-prop-unknown.ll +++ b/llvm/test/ThinLTO/X86/funcattrs-prop-unknown.ll @@ -9,24 +9,24 @@ ; CHECK-NOT: ; Function Attrs: ; CHECK: define i32 @indirect(ptr nocapture %0) { -define i32 @indirect(i32 ()* nocapture) { +define i32 @indirect(ptr nocapture) { %2 = tail call i32 %0() ret i32 %2 } ; CHECK-NOT: ; Function Attrs: ; CHECK: define ptr @inlineasm() { -define i8* @inlineasm() { +define ptr @inlineasm() { entry: - %0 = tail call i8* asm sideeffect "lea ff_h264_cabac_tables(%rip), $0", "=&r,~{dirflag},~{fpsr},~{flags}"() - ret i8* %0 + %0 = tail call ptr asm sideeffect "lea ff_h264_cabac_tables(%rip), $0", "=&r,~{dirflag},~{fpsr},~{flags}"() + ret ptr %0 } ; CHECK-NOT: ; Function Attrs: ; CHECK: define void @selectcallee() { define void @selectcallee() { ; Test calls that aren't handled either as direct or indirect. - call void select (i1 icmp eq (i32* @global, i32* null), void ()* @f, void ()* @g)() + call void select (i1 icmp eq (ptr @global, ptr null), ptr @f, ptr @g)() ret void } diff --git a/llvm/test/ThinLTO/X86/funcimport-tbaa.ll b/llvm/test/ThinLTO/X86/funcimport-tbaa.ll --- a/llvm/test/ThinLTO/X86/funcimport-tbaa.ll +++ b/llvm/test/ThinLTO/X86/funcimport-tbaa.ll @@ -13,19 +13,19 @@ target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.11.0" -define float @globalfunc1(i32*, float*) { - %3 = load i32, i32* %0, align 4, !tbaa !0 +define float @globalfunc1(ptr, ptr) { + %3 = load i32, ptr %0, align 4, !tbaa !0 %4 = sitofp i32 %3 to float - %5 = load float, float* %1, align 4, !tbaa !4 + %5 = load float, ptr %1, align 4, !tbaa !4 %6 = fadd float %4, %5 ret float %6 } ; We need a second function for force the metadata to be emitted in the global block -define float @globalfunc2(i32*, float*) { - %3 = load i32, i32* %0, align 4, !tbaa !0 +define float @globalfunc2(ptr, ptr) { + %3 = load i32, ptr %0, align 4, !tbaa !0 %4 = sitofp i32 %3 to float - %5 = load float, float* %1, align 4, !tbaa !4 + %5 = load float, ptr %1, align 4, !tbaa !4 %6 = fadd float %4, %5 ret float %6 } diff --git a/llvm/test/ThinLTO/X86/globals-import-blockaddr.ll b/llvm/test/ThinLTO/X86/globals-import-blockaddr.ll --- a/llvm/test/ThinLTO/X86/globals-import-blockaddr.ll +++ b/llvm/test/ThinLTO/X86/globals-import-blockaddr.ll @@ -13,14 +13,14 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -declare dso_local [1 x i8*]* @foo(); -declare dso_local [1 x i8*]* @bar(); +declare dso_local ptr @foo(); +declare dso_local ptr @bar(); define dso_local i32 @main() { - %p1 = call [1 x i8*]* @foo() - %p2 = call [1 x i8*]* @bar() - %v1 = ptrtoint [1 x i8*]* %p1 to i32 - %v2 = ptrtoint [1 x i8*]* %p2 to i32 + %p1 = call ptr @foo() + %p2 = call ptr @bar() + %v1 = ptrtoint ptr %p1 to i32 + %v2 = ptrtoint ptr %p2 to i32 %v3 = add i32 %v1, %v2 ret i32 %v3 } diff --git a/llvm/test/ThinLTO/X86/guid_collision.ll b/llvm/test/ThinLTO/X86/guid_collision.ll --- a/llvm/test/ThinLTO/X86/guid_collision.ll +++ b/llvm/test/ThinLTO/X86/guid_collision.ll @@ -27,7 +27,7 @@ ; from, to test handling of a global variable with an entry in the distributed ; index but not with a copy in the source module (since we can't import ; appending linkage globals). -@llvm.global_ctors = appending global [0 x { i32, void ()*, i8* }] zeroinitializer +@llvm.global_ctors = appending global [0 x { i32, ptr, ptr }] zeroinitializer define i64 @H() { call i64 @G() diff --git a/llvm/test/ThinLTO/X86/import-constant.ll b/llvm/test/ThinLTO/X86/import-constant.ll --- a/llvm/test/ThinLTO/X86/import-constant.ll +++ b/llvm/test/ThinLTO/X86/import-constant.ll @@ -45,17 +45,16 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -%struct.S = type { i32, i32, i32* } +%struct.S = type { i32, i32, ptr } define dso_local i32 @main() local_unnamed_addr { entry: - %call = tail call %struct.S* @_Z6getObjv() - %d = getelementptr inbounds %struct.S, %struct.S* %call, i64 0, i32 0 - %0 = load i32, i32* %d, align 8 - %v = getelementptr inbounds %struct.S, %struct.S* %call, i64 0, i32 1 - %1 = load i32, i32* %v, align 4 + %call = tail call ptr @_Z6getObjv() + %0 = load i32, ptr %call, align 8 + %v = getelementptr inbounds %struct.S, ptr %call, i64 0, i32 1 + %1 = load i32, ptr %v, align 4 %add = add nsw i32 %1, %0 ret i32 %add } -declare dso_local %struct.S* @_Z6getObjv() local_unnamed_addr +declare dso_local ptr @_Z6getObjv() local_unnamed_addr diff --git a/llvm/test/ThinLTO/X86/index-const-prop-O0.ll b/llvm/test/ThinLTO/X86/index-const-prop-O0.ll --- a/llvm/test/ThinLTO/X86/index-const-prop-O0.ll +++ b/llvm/test/ThinLTO/X86/index-const-prop-O0.ll @@ -13,6 +13,6 @@ @g = external global i32 define i32 @main() { - %v = load i32, i32* @g + %v = load i32, ptr @g ret i32 %v } diff --git a/llvm/test/ThinLTO/X86/index-const-prop-alias.ll b/llvm/test/ThinLTO/X86/index-const-prop-alias.ll --- a/llvm/test/ThinLTO/X86/index-const-prop-alias.ll +++ b/llvm/test/ThinLTO/X86/index-const-prop-alias.ll @@ -33,10 +33,10 @@ @g = external global i32 define i32 @main() { - %v = load i32, i32* @g + %v = load i32, ptr @g ret i32 %v } -define i32* @ret_ptr() { - ret i32* @g.alias +define ptr @ret_ptr() { + ret ptr @g.alias } diff --git a/llvm/test/ThinLTO/X86/index-const-prop-dead.ll b/llvm/test/ThinLTO/X86/index-const-prop-dead.ll --- a/llvm/test/ThinLTO/X86/index-const-prop-dead.ll +++ b/llvm/test/ThinLTO/X86/index-const-prop-dead.ll @@ -21,6 +21,6 @@ } define i32 @foo() { - %v = load i32, i32* @g + %v = load i32, ptr @g ret i32 %v } diff --git a/llvm/test/ThinLTO/X86/index-const-prop-gvref-pie.ll b/llvm/test/ThinLTO/X86/index-const-prop-gvref-pie.ll --- a/llvm/test/ThinLTO/X86/index-const-prop-gvref-pie.ll +++ b/llvm/test/ThinLTO/X86/index-const-prop-gvref-pie.ll @@ -13,12 +13,12 @@ target triple = "x86_64-unknown-linux-gnu" @a = external global i32 -@b = external global i32* +@b = external global ptr define i32 @main() { - %p = load i32*, i32** @b, align 8 - store i32 33, i32* %p, align 4 - %v = load i32, i32* @a, align 4 + %p = load ptr, ptr @b, align 8 + store i32 33, ptr %p, align 4 + %v = load i32, ptr @a, align 4 ret i32 %v } diff --git a/llvm/test/ThinLTO/X86/index-const-prop-gvref.ll b/llvm/test/ThinLTO/X86/index-const-prop-gvref.ll --- a/llvm/test/ThinLTO/X86/index-const-prop-gvref.ll +++ b/llvm/test/ThinLTO/X86/index-const-prop-gvref.ll @@ -30,22 +30,22 @@ ; RUN: llvm-dis < %t6.0.3.imported.bc | FileCheck %s --check-prefix=OLDAPI_SRC ; RUN: llvm-dis < %t6.1.3.imported.bc | FileCheck %s --check-prefix=OLDAPI_DST_DSO -; OLDAPI_SRC: @b = internal global i32* @a, align 8 +; OLDAPI_SRC: @b = internal global ptr @a, align 8 ; OLDAPI_SRC-NEXT: @a = dso_local global i32 42, align 4 -; OLDAPI_DST: @b = external dso_local global i32* +; OLDAPI_DST: @b = external dso_local global ptr ; OLDAPI_DST-NEXT: @a = available_externally dso_local global i32 42, align 4 -; OLDAPI_DST_DSO: @b = external global i32* +; OLDAPI_DST_DSO: @b = external global ptr ; OLDAPI_DST_DSO-NEXT: @a = available_externally global i32 42, align 4 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @a = external global i32 -@b = external global i32* +@b = external global ptr define i32 @main() { - %p = load i32*, i32** @b, align 8 - store i32 33, i32* %p, align 4 - %v = load i32, i32* @a, align 4 + %p = load ptr, ptr @b, align 8 + store i32 33, ptr %p, align 4 + %v = load i32, ptr @a, align 4 ret i32 %v } diff --git a/llvm/test/ThinLTO/X86/index-const-prop-linkage.ll b/llvm/test/ThinLTO/X86/index-const-prop-linkage.ll --- a/llvm/test/ThinLTO/X86/index-const-prop-linkage.ll +++ b/llvm/test/ThinLTO/X86/index-const-prop-linkage.ll @@ -19,7 +19,7 @@ declare i32 @foo() @g2 = external global i32 -@llvm.used = appending global [1 x i32*] [i32* @g2] +@llvm.used = appending global [1 x ptr] [ptr @g2] define i32 @main() { %v = call i32 @foo() diff --git a/llvm/test/ThinLTO/X86/index-const-prop.ll b/llvm/test/ThinLTO/X86/index-const-prop.ll --- a/llvm/test/ThinLTO/X86/index-const-prop.ll +++ b/llvm/test/ThinLTO/X86/index-const-prop.ll @@ -38,8 +38,8 @@ @gDead = internal unnamed_addr global i32 1, align 4 define i32 @main() local_unnamed_addr { - %call = tail call i32 bitcast (i32 (...)* @foo to i32 ()*)() - %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() + %call = tail call i32 @foo() + %call1 = tail call i32 @bar() %add = add nsw i32 %call1, %call ret i32 %add } diff --git a/llvm/test/ThinLTO/X86/index-const-prop2.ll b/llvm/test/ThinLTO/X86/index-const-prop2.ll --- a/llvm/test/ThinLTO/X86/index-const-prop2.ll +++ b/llvm/test/ThinLTO/X86/index-const-prop2.ll @@ -87,8 +87,8 @@ @gBar = external global i32 define i32 @main() local_unnamed_addr { - %call = tail call i32 bitcast (i32 (...)* @foo to i32 ()*)() - %call1 = tail call i32 bitcast (i32 (...)* @bar to i32 ()*)() + %call = tail call i32 @foo() + %call1 = tail call i32 @bar() %add = add nsw i32 %call1, %call ret i32 %add } diff --git a/llvm/test/ThinLTO/X86/internalize.ll b/llvm/test/ThinLTO/X86/internalize.ll --- a/llvm/test/ThinLTO/X86/internalize.ll +++ b/llvm/test/ThinLTO/X86/internalize.ll @@ -80,7 +80,7 @@ ; Make @weak_func_nonprevailing an aliasee to ensure it is still marked ; live and kept as a definition even when non-prevailing. We want to ensure ; this definition is not internalized. -@alias1 = hidden alias void (), void ()* @weak_func_nonprevailing +@alias1 = hidden alias void (), ptr @weak_func_nonprevailing define weak void @weak_func_nonprevailing() { ret void } diff --git a/llvm/test/ThinLTO/X86/lazyload_metadata.ll b/llvm/test/ThinLTO/X86/lazyload_metadata.ll --- a/llvm/test/ThinLTO/X86/lazyload_metadata.ll +++ b/llvm/test/ThinLTO/X86/lazyload_metadata.ll @@ -23,7 +23,7 @@ target triple = "x86_64-apple-macosx10.11.0" define void @globalfunc1(i32 %arg) { - %x = call i1 @llvm.type.test(i8* undef, metadata !"typeid1") + %x = call i1 @llvm.type.test(ptr undef, metadata !"typeid1") %tmp = add i32 %arg, 0, !metadata !2 ret void } @@ -34,7 +34,7 @@ ; These function are not imported and so we don't want to load their metadata. define void @globalfunc2(i32 %arg) { - %x = call i1 @llvm.type.test(i8* undef, metadata !"typeid1") + %x = call i1 @llvm.type.test(ptr undef, metadata !"typeid1") %tmp = add i32 %arg, 0, !metadata !1 ret void } @@ -44,7 +44,7 @@ ret void } -declare i1 @llvm.type.test(i8* %ptr, metadata %bitset) nounwind readnone +declare i1 @llvm.type.test(ptr %ptr, metadata %bitset) nounwind readnone !1 = !{!2, !3, !4, !5, !6, !7, !8, !9} !2 = !{!"Hello World"} diff --git a/llvm/test/ThinLTO/X86/linkonce_aliasee_ref_import.ll b/llvm/test/ThinLTO/X86/linkonce_aliasee_ref_import.ll --- a/llvm/test/ThinLTO/X86/linkonce_aliasee_ref_import.ll +++ b/llvm/test/ThinLTO/X86/linkonce_aliasee_ref_import.ll @@ -28,7 +28,7 @@ target triple = "x86_64-grtev4-linux-gnu" $baz.clone = comdat any -@baz = weak alias void (), void ()* @baz.clone +@baz = weak alias void (), ptr @baz.clone define void @foo() #5 align 2 { tail call void @baz.clone() diff --git a/llvm/test/ThinLTO/X86/linkonce_resolution_comdat.ll b/llvm/test/ThinLTO/X86/linkonce_resolution_comdat.ll --- a/llvm/test/ThinLTO/X86/linkonce_resolution_comdat.ll +++ b/llvm/test/ThinLTO/X86/linkonce_resolution_comdat.ll @@ -12,12 +12,12 @@ ; from second module is preempted and converted to available_externally and ; removed from comdat. ; IMPORT1: @g_private = private global i32 43, comdat($g) -; IMPORT1: define weak_odr i32 @f(i8* %0) unnamed_addr [[ATTR:#[0-9]+]] comdat { +; IMPORT1: define weak_odr i32 @f(ptr %0) unnamed_addr [[ATTR:#[0-9]+]] comdat { ; IMPORT1: define weak_odr i32 @g() unnamed_addr [[ATTR]] comdat { ; IMPORT1: define internal void @g_internal() unnamed_addr comdat($g) { ; IMPORT2: @g_private = available_externally dso_local global i32 41{{$}} -; IMPORT2: define available_externally i32 @f(i8* %0) unnamed_addr [[ATTR:#[0-9]+]] { +; IMPORT2: define available_externally i32 @f(ptr %0) unnamed_addr [[ATTR:#[0-9]+]] { ; IMPORT2: define available_externally i32 @g() unnamed_addr [[ATTR]] { ; IMPORT2: define available_externally dso_local void @g_internal() unnamed_addr { @@ -41,7 +41,7 @@ @g_private = private global i32 43, comdat($g) -define linkonce_odr i32 @f(i8*) unnamed_addr comdat { +define linkonce_odr i32 @f(ptr) unnamed_addr comdat { ret i32 43 } diff --git a/llvm/test/ThinLTO/X86/llvm.used.ll b/llvm/test/ThinLTO/X86/llvm.used.ll --- a/llvm/test/ThinLTO/X86/llvm.used.ll +++ b/llvm/test/ThinLTO/X86/llvm.used.ll @@ -16,7 +16,7 @@ define internal void @_ZN12_GLOBAL__N_16Module4dumpEv() { ret void } -@llvm.used = appending global [1 x i8*] [i8* bitcast (void ()* @_ZN12_GLOBAL__N_16Module4dumpEv to i8*)], section "llvm.metadata" +@llvm.used = appending global [1 x ptr] [ptr @_ZN12_GLOBAL__N_16Module4dumpEv], section "llvm.metadata" define void @globalfunc() #0 { diff --git a/llvm/test/ThinLTO/X86/load-store-caching.ll b/llvm/test/ThinLTO/X86/load-store-caching.ll --- a/llvm/test/ThinLTO/X86/load-store-caching.ll +++ b/llvm/test/ThinLTO/X86/load-store-caching.ll @@ -8,17 +8,17 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -%struct.S = type { %struct.Derived* } +%struct.S = type { ptr } %struct.Derived = type { i32 } %struct.Base = type { i32 } @obj = dso_local local_unnamed_addr global %struct.S zeroinitializer, align 8 -define dso_local %struct.Base* @foo() local_unnamed_addr { +define dso_local ptr @foo() local_unnamed_addr { entry: - %0 = load %struct.Base*, %struct.Base** bitcast (%struct.S* @obj to %struct.Base**), align 8 - store %struct.Base* null, %struct.Base** bitcast (%struct.S* @obj to %struct.Base**), align 8 - ret %struct.Base* %0 + %0 = load ptr, ptr @obj, align 8 + store ptr null, ptr @obj, align 8 + ret ptr %0 } ; CHECK: ^0 = module: diff --git a/llvm/test/ThinLTO/X86/local_name_conflict.ll b/llvm/test/ThinLTO/X86/local_name_conflict.ll --- a/llvm/test/ThinLTO/X86/local_name_conflict.ll +++ b/llvm/test/ThinLTO/X86/local_name_conflict.ll @@ -35,7 +35,7 @@ define i32 @main() { entry: %retval = alloca i32, align 4 - store i32 0, i32* %retval, align 4 + store i32 0, ptr %retval, align 4 %call = call i32 (...) @b() ret i32 %call } diff --git a/llvm/test/ThinLTO/X86/module_asm2.ll b/llvm/test/ThinLTO/X86/module_asm2.ll --- a/llvm/test/ThinLTO/X86/module_asm2.ll +++ b/llvm/test/ThinLTO/X86/module_asm2.ll @@ -70,8 +70,8 @@ @b = internal global i32 1, align 4 @x = internal global i32 1, align 4 -@llvm.compiler.used = appending global [1 x i8*] [i8* bitcast (i32* @b to i8*)], section "llvm.metadata" -@llvm.used = appending global [1 x i8*] [i8* bitcast (i32* @x to i8*)], section "llvm.metadata" +@llvm.compiler.used = appending global [1 x ptr] [ptr @b], section "llvm.metadata" +@llvm.used = appending global [1 x ptr] [ptr @x], section "llvm.metadata" module asm "\09.text" module asm "\09.type\09foo,@function" @@ -108,12 +108,12 @@ } define i32 @func2() #1 { - %1 = load i32, i32* @b, align 4 + %1 = load i32, ptr @b, align 4 ret i32 %1 } define i32 @func3() #1 { - %1 = load i32, i32* @x, align 4 + %1 = load i32, ptr @x, align 4 ret i32 %1 } diff --git a/llvm/test/ThinLTO/X86/nodevirt-nonpromoted-typeid.ll b/llvm/test/ThinLTO/X86/nodevirt-nonpromoted-typeid.ll --- a/llvm/test/ThinLTO/X86/nodevirt-nonpromoted-typeid.ll +++ b/llvm/test/ThinLTO/X86/nodevirt-nonpromoted-typeid.ll @@ -26,53 +26,49 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-grtev4-linux-gnu" -@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @g, i8* null }] +@llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @g, ptr null }] -%struct.D = type { i32 (...)** } +%struct.D = type { ptr } -@_ZTV1D = internal constant { [3 x i8*] } { [3 x i8*] [i8* null, i8* undef, i8* bitcast (i32 (%struct.D*, i32)* @_ZN1D1mEi to i8*)] }, !type !3 +@_ZTV1D = internal constant { [3 x ptr] } { [3 x ptr] [ptr null, ptr undef, ptr @_ZN1D1mEi] }, !type !3 ; CHECK-IR-LABEL: define weak_odr dso_local i32 @test -define weak_odr i32 @test(%struct.D* %obj2, i32 %a) { +define weak_odr i32 @test(ptr %obj2, i32 %a) { entry: - %0 = bitcast %struct.D* %obj2 to i8*** - %vtable2 = load i8**, i8*** %0 - %1 = bitcast i8** %vtable2 to i8* - %p2 = call i1 @llvm.type.test(i8* %1, metadata !4) + %vtable2 = load ptr, ptr %obj2 + %p2 = call i1 @llvm.type.test(ptr %vtable2, metadata !4) call void @llvm.assume(i1 %p2) - %2 = bitcast i8** %vtable2 to i32 (%struct.D*, i32)** - %fptr33 = load i32 (%struct.D*, i32)*, i32 (%struct.D*, i32)** %2, align 8 + %fptr33 = load ptr, ptr %vtable2, align 8 ; Check that the call was not devirtualized. ; CHECK-IR: %call4 = tail call i32 %fptr33 - %call4 = tail call i32 %fptr33(%struct.D* nonnull %obj2, i32 0) + %call4 = tail call i32 %fptr33(ptr nonnull %obj2, i32 0) ret i32 %call4 } ; CHECK-IR-LABEL: ret i32 ; CHECK-IR-LABEL: } ; Function Attrs: inlinehint nounwind uwtable -define internal void @_ZN1DC2Ev(%struct.D* %this) unnamed_addr align 2 { +define internal void @_ZN1DC2Ev(ptr %this) unnamed_addr align 2 { entry: - %this.addr = alloca %struct.D*, align 8 - store %struct.D* %this, %struct.D** %this.addr, align 8 - %this1 = load %struct.D*, %struct.D** %this.addr - %0 = bitcast %struct.D* %this1 to i32 (...)*** - store i32 (...)** bitcast (i8** getelementptr inbounds ({ [3 x i8*] }, { [3 x i8*] }* @_ZTV1D, i64 0, inrange i32 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 8 + %this.addr = alloca ptr, align 8 + store ptr %this, ptr %this.addr, align 8 + %this1 = load ptr, ptr %this.addr + store ptr getelementptr inbounds ({ [3 x ptr] }, ptr @_ZTV1D, i64 0, inrange i32 0, i64 2), ptr %this1, align 8 ret void } define internal void @g() section ".text.startup" { %d = alloca %struct.D, align 8 - call void @_ZN1DC2Ev(%struct.D* %d) + call void @_ZN1DC2Ev(ptr %d) ret void } -declare i1 @llvm.type.test(i8*, metadata) +declare i1 @llvm.type.test(ptr, metadata) declare void @llvm.assume(i1) -declare i32 @_ZN1D1mEi(%struct.D* %this, i32 %a) +declare i32 @_ZN1D1mEi(ptr %this, i32 %a) !3 = !{i64 16, !4} !4 = distinct !{} diff --git a/llvm/test/ThinLTO/X86/noinline.ll b/llvm/test/ThinLTO/X86/noinline.ll --- a/llvm/test/ThinLTO/X86/noinline.ll +++ b/llvm/test/ThinLTO/X86/noinline.ll @@ -16,7 +16,7 @@ target triple = "x86_64-pc-linux-gnu" ; Function Attrs: nounwind ssp uwtable -define i32 @main(i32, i8** nocapture readnone) local_unnamed_addr #0 { +define i32 @main(i32, ptr nocapture readnone) local_unnamed_addr #0 { %3 = tail call i32 @foo(i32 %0) #0 ret i32 %3 } diff --git a/llvm/test/ThinLTO/X86/personality.ll b/llvm/test/ThinLTO/X86/personality.ll --- a/llvm/test/ThinLTO/X86/personality.ll +++ b/llvm/test/ThinLTO/X86/personality.ll @@ -45,28 +45,28 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-pc-linux-gnu" -declare protected i32 @personality_routine(i32, i32, i64, i8*, i8*) -declare protected i32 @personality_routine2(i32, i32, i64, i8*, i8*) -declare protected i32 @personality_routine3(i32, i32, i64, i8*, i8*) +declare protected i32 @personality_routine(i32, i32, i64, ptr, ptr) +declare protected i32 @personality_routine2(i32, i32, i64, ptr, ptr) +declare protected i32 @personality_routine3(i32, i32, i64, ptr, ptr) declare void @bar() -define void @foo() personality i32 (i32, i32, i64, i8*, i8*)* @personality_routine { +define void @foo() personality ptr @personality_routine { ret void } -define internal void @foo2b() personality i8* bitcast (i32 (i32, i32, i64, i8*, i8*)* @personality_routine2 to i8*) { +define internal void @foo2b() personality ptr @personality_routine2 { ret void } -define internal void @foo2a() prologue void ()* @foo2b { +define internal void @foo2a() prologue ptr @foo2b { ret void } -define void @foo2() prefix void ()* @foo2a { +define void @foo2() prefix ptr @foo2a { ret void } -define void @foo3() personality i8* bitcast (i32 (i32, i32, i64, i8*, i8*)* @personality_routine3 to i8*) { +define void @foo3() personality ptr @personality_routine3 { ret void } diff --git a/llvm/test/ThinLTO/X86/pr35472.ll b/llvm/test/ThinLTO/X86/pr35472.ll --- a/llvm/test/ThinLTO/X86/pr35472.ll +++ b/llvm/test/ThinLTO/X86/pr35472.ll @@ -26,26 +26,24 @@ define void @_Z5Bravov() !dbg !7 { %Hotel = alloca %struct.Delta, align 4 %India = alloca %struct.Echo, align 4 - call void @llvm.dbg.declare(metadata %struct.Delta* %Hotel, metadata !10, metadata !DIExpression()), !dbg !22 - call void @_ZN4EchoD2Ev(%struct.Echo* %India), !dbg !28 + call void @llvm.dbg.declare(metadata ptr %Hotel, metadata !10, metadata !DIExpression()), !dbg !22 + call void @_ZN4EchoD2Ev(ptr %India), !dbg !28 ret void, !dbg !28 } declare void @llvm.dbg.declare(metadata, metadata, metadata) -define linkonce_odr void @_ZN4EchoD2Ev(%struct.Echo* %this) unnamed_addr comdat align 2 { - %this.addr.i = alloca %struct.Charlie*, align 8 - call void @llvm.dbg.declare(metadata %struct.Charlie** %this.addr.i, metadata !29, metadata !DIExpression()), !dbg !32 - %this1.i = load %struct.Charlie*, %struct.Charlie** %this.addr.i, align 8 - %Golf.i = getelementptr inbounds %struct.Charlie, %struct.Charlie* %this1.i, i32 0, i32 0, !dbg !33 +define linkonce_odr void @_ZN4EchoD2Ev(ptr %this) unnamed_addr comdat align 2 { + %this.addr.i = alloca ptr, align 8 + call void @llvm.dbg.declare(metadata ptr %this.addr.i, metadata !29, metadata !DIExpression()), !dbg !32 + %this1.i = load ptr, ptr %this.addr.i, align 8 ret void } -define linkonce_odr void @_ZN5DeltaD2Ev(%struct.Delta* %this) unnamed_addr comdat align 2 !dbg !36 { - %this.addr.i = alloca %struct.Charlie*, align 8 - call void @llvm.dbg.declare(metadata %struct.Charlie** %this.addr.i, metadata !29, metadata !DIExpression()), !dbg !41 - %this1.i = load %struct.Charlie*, %struct.Charlie** %this.addr.i, align 8 - %Golf.i = getelementptr inbounds %struct.Charlie, %struct.Charlie* %this1.i, i32 0, i32 0, !dbg !48 +define linkonce_odr void @_ZN5DeltaD2Ev(ptr %this) unnamed_addr comdat align 2 !dbg !36 { + %this.addr.i = alloca ptr, align 8 + call void @llvm.dbg.declare(metadata ptr %this.addr.i, metadata !29, metadata !DIExpression()), !dbg !41 + %this1.i = load ptr, ptr %this.addr.i, align 8 ret void } diff --git a/llvm/test/ThinLTO/X86/promote-local-name.ll b/llvm/test/ThinLTO/X86/promote-local-name.ll --- a/llvm/test/ThinLTO/X86/promote-local-name.ll +++ b/llvm/test/ThinLTO/X86/promote-local-name.ll @@ -25,7 +25,7 @@ define i32 @main() { entry: %retval = alloca i32, align 4 - store i32 0, i32* %retval, align 4 + store i32 0, ptr %retval, align 4 %call = call i32 (...) @b() ret i32 %call } diff --git a/llvm/test/ThinLTO/X86/reference_non_importable.ll b/llvm/test/ThinLTO/X86/reference_non_importable.ll --- a/llvm/test/ThinLTO/X86/reference_non_importable.ll +++ b/llvm/test/ThinLTO/X86/reference_non_importable.ll @@ -17,12 +17,12 @@ ; RUN: llvm-dis < %t.o.1.2.internalize.bc | FileCheck %s --check-prefix=PROMOTE ; PROMOTE: @a = private global i8 0, section "__TEXT,__cstring,cstring_literals" @a = private global i8 0, section "__TEXT,__cstring,cstring_literals" -@b = global i8 *@a +@b = global ptr@a ; We want foo to be imported in the main module! ; RUN: llvm-dis < %t.o.2.3.import.bc | FileCheck %s --check-prefix=IMPORT ; IMPORT: define available_externally dso_local ptr @foo() -define i8 **@foo() { - ret i8 **@b +define ptr@foo() { + ret ptr@b } diff --git a/llvm/test/ThinLTO/X86/selective-save-temps.ll b/llvm/test/ThinLTO/X86/selective-save-temps.ll --- a/llvm/test/ThinLTO/X86/selective-save-temps.ll +++ b/llvm/test/ThinLTO/X86/selective-save-temps.ll @@ -144,17 +144,16 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" -%struct.S = type { i32, i32, i32* } +%struct.S = type { i32, i32, ptr } define dso_local i32 @main() local_unnamed_addr { entry: - %call = tail call %struct.S* @_Z6getObjv() - %d = getelementptr inbounds %struct.S, %struct.S* %call, i64 0, i32 0 - %0 = load i32, i32* %d, align 8 - %v = getelementptr inbounds %struct.S, %struct.S* %call, i64 0, i32 1 - %1 = load i32, i32* %v, align 4 + %call = tail call ptr @_Z6getObjv() + %0 = load i32, ptr %call, align 8 + %v = getelementptr inbounds %struct.S, ptr %call, i64 0, i32 1 + %1 = load i32, ptr %v, align 4 %add = add nsw i32 %1, %0 ret i32 %add } -declare dso_local %struct.S* @_Z6getObjv() local_unnamed_addr +declare dso_local ptr @_Z6getObjv() local_unnamed_addr diff --git a/llvm/test/ThinLTO/X86/thinlto-internalize-doublepromoted.ll b/llvm/test/ThinLTO/X86/thinlto-internalize-doublepromoted.ll --- a/llvm/test/ThinLTO/X86/thinlto-internalize-doublepromoted.ll +++ b/llvm/test/ThinLTO/X86/thinlto-internalize-doublepromoted.ll @@ -27,7 +27,6 @@ ; CHECK: define hidden void @foo.llvm.123() define hidden void @foo.llvm.123() { - %1 = getelementptr inbounds [10 x i8], [10 x i8]* @switch.table.foo.llvm.123, i64 0, i64 0 - store i8 1, i8* %1, align 8 + store i8 1, ptr @switch.table.foo.llvm.123, align 8 ret void } diff --git a/llvm/test/ThinLTO/X86/thinlto-internalize-used.ll b/llvm/test/ThinLTO/X86/thinlto-internalize-used.ll --- a/llvm/test/ThinLTO/X86/thinlto-internalize-used.ll +++ b/llvm/test/ThinLTO/X86/thinlto-internalize-used.ll @@ -7,7 +7,7 @@ target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.15.0" -@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 ()* @foo to i8*)], section "llvm.metadata" +@llvm.used = appending global [1 x ptr] [ptr @foo], section "llvm.metadata" ; Make sure foo is not internalized. ; CHECK: define i32 @foo() diff --git a/llvm/test/ThinLTO/X86/tli-nobuiltin.ll b/llvm/test/ThinLTO/X86/tli-nobuiltin.ll --- a/llvm/test/ThinLTO/X86/tli-nobuiltin.ll +++ b/llvm/test/ThinLTO/X86/tli-nobuiltin.ll @@ -28,7 +28,7 @@ target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-apple-macosx10.11.0" -declare i32 @fprintf(%FILE*, i8*, ...) +declare i32 @fprintf(ptr, ptr, ...) %FILE = type { } @@ -37,10 +37,8 @@ ; Check fprintf(fp, "%s", str) -> fwrite(str, fp) only when builtins are enabled -define void @foo(%FILE* %fp) { - %fmt = getelementptr [3 x i8], [3 x i8]* @percent_s, i32 0, i32 0 - %str = getelementptr [13 x i8], [13 x i8]* @hello_world, i32 0, i32 0 - call i32 (%FILE*, i8*, ...) @fprintf(%FILE* %fp, i8* %fmt, i8* %str) +define void @foo(ptr %fp) { + call i32 (ptr, ptr, ...) @fprintf(ptr %fp, ptr @percent_s, ptr @hello_world) ret void } diff --git a/llvm/test/ThinLTO/X86/visibility-elf.ll b/llvm/test/ThinLTO/X86/visibility-elf.ll --- a/llvm/test/ThinLTO/X86/visibility-elf.ll +++ b/llvm/test/ThinLTO/X86/visibility-elf.ll @@ -28,7 +28,7 @@ @var1 = weak global i32 1, align 4 @var2 = extern_weak global i32 -declare void @ext(void ()*) +declare void @ext(ptr) ; CHECK: declare hidden i32 @hidden_def_weak_def() ; CHECK: declare protected void @protected_def_weak_def() @@ -53,7 +53,7 @@ define weak i32 @hidden_def_weak_def() { entry: - %0 = load i32, i32* @var2 + %0 = load i32, ptr @var2 ret i32 %0 } @@ -75,13 +75,13 @@ define i32 @main() { entry: - call void @ext(void ()* bitcast (i32 ()* @hidden_def_weak_def to void ()*)) - call void @ext(void ()* @protected_def_weak_def) - call void @ext(void ()* @protected_def_weak_hidden_def) - call void @ext(void ()* @hidden_def_ref) - call void @ext(void ()* @hidden_def_weak_ref) - call void @ext(void ()* @protected_def_hidden_ref) - call void @ext(void ()* @not_imported) + call void @ext(ptr @hidden_def_weak_def) + call void @ext(ptr @protected_def_weak_def) + call void @ext(ptr @protected_def_weak_hidden_def) + call void @ext(ptr @hidden_def_ref) + call void @ext(ptr @hidden_def_weak_ref) + call void @ext(ptr @protected_def_hidden_ref) + call void @ext(ptr @not_imported) ;; Calls ensure the functions are imported. call i32 @hidden_def_weak_def() @@ -102,7 +102,7 @@ define hidden i32 @hidden_def_weak_def() { entry: - %0 = load i32, i32* @var1 + %0 = load i32, ptr @var1 ret i32 %0 } diff --git a/llvm/test/ThinLTO/X86/visibility-macho.ll b/llvm/test/ThinLTO/X86/visibility-macho.ll --- a/llvm/test/ThinLTO/X86/visibility-macho.ll +++ b/llvm/test/ThinLTO/X86/visibility-macho.ll @@ -24,7 +24,7 @@ @var1 = weak global i32 1, align 4 @var2 = extern_weak global i32 -declare void @ext(void ()*) +declare void @ext(ptr) ; CHECK: declare hidden i32 @hidden_def_weak_def() ;; Currently the visibility is not propagated onto an unimported function, @@ -40,7 +40,7 @@ define weak i32 @hidden_def_weak_def() { entry: - %0 = load i32, i32* @var2 + %0 = load i32, ptr @var2 ret i32 %0 } @@ -51,10 +51,10 @@ define i32 @main() { entry: - call void @ext(void ()* bitcast (i32 ()* @hidden_def_weak_def to void ()*)) - call void @ext(void ()* @hidden_def_ref) - call void @ext(void ()* @hidden_def_weak_ref) - call void @ext(void ()* @not_imported) + call void @ext(ptr @hidden_def_weak_def) + call void @ext(ptr @hidden_def_ref) + call void @ext(ptr @hidden_def_weak_ref) + call void @ext(ptr @not_imported) ;; Calls ensure the functions are imported. call i32 @hidden_def_weak_def() @@ -72,7 +72,7 @@ define hidden i32 @hidden_def_weak_def() { entry: - %0 = load i32, i32* @var1 + %0 = load i32, ptr @var1 ret i32 %0 } diff --git a/llvm/test/ThinLTO/X86/weak_externals.ll b/llvm/test/ThinLTO/X86/weak_externals.ll --- a/llvm/test/ThinLTO/X86/weak_externals.ll +++ b/llvm/test/ThinLTO/X86/weak_externals.ll @@ -27,17 +27,16 @@ @_ZZN9SingletonI1SE11getInstanceEvE8instance = linkonce_odr dso_local global %struct.S zeroinitializer, comdat, align 8 -@_ZZN9SingletonI1SE11getInstanceEvE13instance_weak = weak_odr dso_local global %struct.S* null, comdat, align 8 +@_ZZN9SingletonI1SE11getInstanceEvE13instance_weak = weak_odr dso_local global ptr null, comdat, align 8 define dso_local void @_ZL5initSv() { - %1 = call dereferenceable(16) %struct.S* @_ZN9SingletonI1SE11getInstanceEv() - store %struct.S* %1, %struct.S** @_ZZN9SingletonI1SE11getInstanceEvE13instance_weak - %2 = getelementptr inbounds %struct.S, %struct.S* %1, i32 0, i32 0 - store i64 1, i64* %2, align 8 + %1 = call dereferenceable(16) ptr @_ZN9SingletonI1SE11getInstanceEv() + store ptr %1, ptr @_ZZN9SingletonI1SE11getInstanceEvE13instance_weak + store i64 1, ptr %1, align 8 ret void } -define linkonce_odr dso_local dereferenceable(16) %struct.S* @_ZN9SingletonI1SE11getInstanceEv() #0 comdat align 2 { - ret %struct.S* @_ZZN9SingletonI1SE11getInstanceEvE8instance +define linkonce_odr dso_local dereferenceable(16) ptr @_ZN9SingletonI1SE11getInstanceEv() #0 comdat align 2 { + ret ptr @_ZZN9SingletonI1SE11getInstanceEvE8instance } diff --git a/llvm/test/ThinLTO/X86/weak_resolution.ll b/llvm/test/ThinLTO/X86/weak_resolution.ll --- a/llvm/test/ThinLTO/X86/weak_resolution.ll +++ b/llvm/test/ThinLTO/X86/weak_resolution.ll @@ -16,14 +16,14 @@ target triple = "x86_64-apple-macosx10.11.0" ; Alias are resolved, but can't be turned into "available_externally" -; MOD1: @linkonceodralias = weak_odr alias void (), void ()* @linkonceodrfuncwithalias -; MOD2: @linkonceodralias = linkonce_odr alias void (), void ()* @linkonceodrfuncwithalias -@linkonceodralias = linkonce_odr alias void (), void ()* @linkonceodrfuncwithalias +; MOD1: @linkonceodralias = weak_odr alias void (), ptr @linkonceodrfuncwithalias +; MOD2: @linkonceodralias = linkonce_odr alias void (), ptr @linkonceodrfuncwithalias +@linkonceodralias = linkonce_odr alias void (), ptr @linkonceodrfuncwithalias ; Alias are resolved, but can't be turned into "available_externally" -; MOD1: @linkoncealias = weak alias void (), void ()* @linkoncefuncwithalias -; MOD2: @linkoncealias = linkonce alias void (), void ()* @linkoncefuncwithalias -@linkoncealias = linkonce alias void (), void ()* @linkoncefuncwithalias +; MOD1: @linkoncealias = weak alias void (), ptr @linkoncefuncwithalias +; MOD2: @linkoncealias = linkonce alias void (), ptr @linkoncefuncwithalias +@linkoncealias = linkonce alias void (), ptr @linkoncefuncwithalias ; Function with an alias are resolved to weak_odr in prevailing module, but ; not optimized in non-prevailing module (illegal to have an diff --git a/llvm/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll --- a/llvm/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll +++ b/llvm/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll @@ -1,17 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -mtriple=aarch64-linux-gnu -atomic-expand %s | FileCheck %s -define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fadd_f32( -; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -19,21 +18,20 @@ ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fadd float* %ptr, float %value seq_cst + %res = atomicrmw fadd ptr %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fsub_f32( -; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -41,7 +39,7 @@ ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fsub float* %ptr, float %value seq_cst + %res = atomicrmw fsub ptr %ptr, float %value seq_cst ret float %res } diff --git a/llvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll b/llvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll --- a/llvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll +++ b/llvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll @@ -2,16 +2,15 @@ ; RUN: opt -codegen-opt-level=1 -S -mtriple=aarch64-- -atomic-expand %s | FileCheck %s ; RUN: opt -codegen-opt-level=1 -S -mtriple=aarch64-- -mattr=+outline-atomics -atomic-expand %s | FileCheck %s --check-prefix=OUTLINE-ATOMICS -define void @atomic_swap_f16(half* %ptr, half %val) nounwind { +define void @atomic_swap_f16(ptr %ptr, half %val) nounwind { ; CHECK-LABEL: @atomic_swap_f16( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast half* [[PTR:%.*]] to i16* ; CHECK-NEXT: [[TMP2:%.*]] = bitcast half [[VAL:%.*]] to i16 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: -; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i16(i16* elementtype(i16) [[TMP1]]) +; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i16) [[PTR:%.*]]) ; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i16 ; CHECK-NEXT: [[TMP5:%.*]] = zext i16 [[TMP2]] to i64 -; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.aarch64.stxr.p0i16(i64 [[TMP5]], i16* elementtype(i16) [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.aarch64.stxr.p0(i64 [[TMP5]], ptr elementtype(i16) [[PTR]]) ; CHECK-NEXT: [[TRYAGAIN:%.*]] = icmp ne i32 [[TMP6]], 0 ; CHECK-NEXT: br i1 [[TRYAGAIN]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]] ; CHECK: atomicrmw.end: @@ -19,26 +18,24 @@ ; CHECK-NEXT: ret void ; ; OUTLINE-ATOMICS-LABEL: @atomic_swap_f16( -; OUTLINE-ATOMICS-NEXT: [[TMP1:%.*]] = bitcast half* [[PTR:%.*]] to i16* ; OUTLINE-ATOMICS-NEXT: [[TMP2:%.*]] = bitcast half [[VAL:%.*]] to i16 -; OUTLINE-ATOMICS-NEXT: [[TMP3:%.*]] = atomicrmw xchg i16* [[TMP1]], i16 [[TMP2]] acquire, align 2 +; OUTLINE-ATOMICS-NEXT: [[TMP3:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i16 [[TMP2]] acquire, align 2 ; OUTLINE-ATOMICS-NEXT: [[TMP4:%.*]] = bitcast i16 [[TMP3]] to half ; OUTLINE-ATOMICS-NEXT: ret void ; - %t1 = atomicrmw xchg half* %ptr, half %val acquire + %t1 = atomicrmw xchg ptr %ptr, half %val acquire ret void } -define void @atomic_swap_f32(float* %ptr, float %val) nounwind { +define void @atomic_swap_f32(ptr %ptr, float %val) nounwind { ; CHECK-LABEL: @atomic_swap_f32( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[PTR:%.*]] to i32* ; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[VAL:%.*]] to i32 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: -; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i32(i32* elementtype(i32) [[TMP1]]) +; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i32) [[PTR:%.*]]) ; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32 ; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP2]] to i64 -; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.aarch64.stxr.p0i32(i64 [[TMP5]], i32* elementtype(i32) [[TMP1]]) +; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.aarch64.stxr.p0(i64 [[TMP5]], ptr elementtype(i32) [[PTR]]) ; CHECK-NEXT: [[TRYAGAIN:%.*]] = icmp ne i32 [[TMP6]], 0 ; CHECK-NEXT: br i1 [[TRYAGAIN]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]] ; CHECK: atomicrmw.end: @@ -46,24 +43,22 @@ ; CHECK-NEXT: ret void ; ; OUTLINE-ATOMICS-LABEL: @atomic_swap_f32( -; OUTLINE-ATOMICS-NEXT: [[TMP1:%.*]] = bitcast float* [[PTR:%.*]] to i32* ; OUTLINE-ATOMICS-NEXT: [[TMP2:%.*]] = bitcast float [[VAL:%.*]] to i32 -; OUTLINE-ATOMICS-NEXT: [[TMP3:%.*]] = atomicrmw xchg i32* [[TMP1]], i32 [[TMP2]] acquire, align 4 +; OUTLINE-ATOMICS-NEXT: [[TMP3:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i32 [[TMP2]] acquire, align 4 ; OUTLINE-ATOMICS-NEXT: [[TMP4:%.*]] = bitcast i32 [[TMP3]] to float ; OUTLINE-ATOMICS-NEXT: ret void ; - %t1 = atomicrmw xchg float* %ptr, float %val acquire + %t1 = atomicrmw xchg ptr %ptr, float %val acquire ret void } -define void @atomic_swap_f64(double* %ptr, double %val) nounwind { +define void @atomic_swap_f64(ptr %ptr, double %val) nounwind { ; CHECK-LABEL: @atomic_swap_f64( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast double* [[PTR:%.*]] to i64* ; CHECK-NEXT: [[TMP2:%.*]] = bitcast double [[VAL:%.*]] to i64 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: -; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.ldaxr.p0i64(i64* elementtype(i64) [[TMP1]]) -; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.aarch64.stxr.p0i64(i64 [[TMP2]], i64* elementtype(i64) [[TMP1]]) +; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.ldaxr.p0(ptr elementtype(i64) [[PTR:%.*]]) +; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.aarch64.stxr.p0(i64 [[TMP2]], ptr elementtype(i64) [[PTR]]) ; CHECK-NEXT: [[TRYAGAIN:%.*]] = icmp ne i32 [[TMP4]], 0 ; CHECK-NEXT: br i1 [[TRYAGAIN]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]] ; CHECK: atomicrmw.end: @@ -71,12 +66,11 @@ ; CHECK-NEXT: ret void ; ; OUTLINE-ATOMICS-LABEL: @atomic_swap_f64( -; OUTLINE-ATOMICS-NEXT: [[TMP1:%.*]] = bitcast double* [[PTR:%.*]] to i64* ; OUTLINE-ATOMICS-NEXT: [[TMP2:%.*]] = bitcast double [[VAL:%.*]] to i64 -; OUTLINE-ATOMICS-NEXT: [[TMP3:%.*]] = atomicrmw xchg i64* [[TMP1]], i64 [[TMP2]] acquire, align 8 +; OUTLINE-ATOMICS-NEXT: [[TMP3:%.*]] = atomicrmw xchg ptr [[PTR:%.*]], i64 [[TMP2]] acquire, align 8 ; OUTLINE-ATOMICS-NEXT: [[TMP4:%.*]] = bitcast i64 [[TMP3]] to double ; OUTLINE-ATOMICS-NEXT: ret void ; - %t1 = atomicrmw xchg double* %ptr, double %val acquire + %t1 = atomicrmw xchg ptr %ptr, double %val acquire ret void } diff --git a/llvm/test/Transforms/AtomicExpand/AArch64/pcsections.ll b/llvm/test/Transforms/AtomicExpand/AArch64/pcsections.ll --- a/llvm/test/Transforms/AtomicExpand/AArch64/pcsections.ll +++ b/llvm/test/Transforms/AtomicExpand/AArch64/pcsections.ll @@ -1,102 +1,102 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -mtriple=aarch64-linux-gnu -atomic-expand %s | FileCheck %s -define i8 @atomic8_load_unordered(i8* %a) nounwind uwtable { +define i8 @atomic8_load_unordered(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_load_unordered( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, i8* [[A:%.*]] unordered, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, ptr [[A:%.*]] unordered, align 1, !pcsections !0 ; CHECK-NEXT: ret i8 [[TMP0]] ; entry: - %0 = load atomic i8, i8* %a unordered, align 1, !pcsections !0 + %0 = load atomic i8, ptr %a unordered, align 1, !pcsections !0 ret i8 %0 } -define i8 @atomic8_load_monotonic(i8* %a) nounwind uwtable { +define i8 @atomic8_load_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_load_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, i8* [[A:%.*]] monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, ptr [[A:%.*]] monotonic, align 1, !pcsections !0 ; CHECK-NEXT: ret i8 [[TMP0]] ; entry: - %0 = load atomic i8, i8* %a monotonic, align 1, !pcsections !0 + %0 = load atomic i8, ptr %a monotonic, align 1, !pcsections !0 ret i8 %0 } -define i8 @atomic8_load_acquire(i8* %a) nounwind uwtable { +define i8 @atomic8_load_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_load_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, i8* [[A:%.*]] acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, ptr [[A:%.*]] acquire, align 1, !pcsections !0 ; CHECK-NEXT: ret i8 [[TMP0]] ; entry: - %0 = load atomic i8, i8* %a acquire, align 1, !pcsections !0 + %0 = load atomic i8, ptr %a acquire, align 1, !pcsections !0 ret i8 %0 } -define i8 @atomic8_load_seq_cst(i8* %a) nounwind uwtable { +define i8 @atomic8_load_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_load_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, i8* [[A:%.*]] seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8, ptr [[A:%.*]] seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: ret i8 [[TMP0]] ; entry: - %0 = load atomic i8, i8* %a seq_cst, align 1, !pcsections !0 + %0 = load atomic i8, ptr %a seq_cst, align 1, !pcsections !0 ret i8 %0 } -define void @atomic8_store_unordered(i8* %a) nounwind uwtable { +define void @atomic8_store_unordered(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_store_unordered( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i8 0, i8* [[A:%.*]] unordered, align 1, !pcsections !0 +; CHECK-NEXT: store atomic i8 0, ptr [[A:%.*]] unordered, align 1, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i8 0, i8* %a unordered, align 1, !pcsections !0 + store atomic i8 0, ptr %a unordered, align 1, !pcsections !0 ret void } -define void @atomic8_store_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_store_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_store_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i8 0, i8* [[A:%.*]] monotonic, align 1, !pcsections !0 +; CHECK-NEXT: store atomic i8 0, ptr [[A:%.*]] monotonic, align 1, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i8 0, i8* %a monotonic, align 1, !pcsections !0 + store atomic i8 0, ptr %a monotonic, align 1, !pcsections !0 ret void } -define void @atomic8_store_release(i8* %a) nounwind uwtable { +define void @atomic8_store_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_store_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i8 0, i8* [[A:%.*]] release, align 1, !pcsections !0 +; CHECK-NEXT: store atomic i8 0, ptr [[A:%.*]] release, align 1, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i8 0, i8* %a release, align 1, !pcsections !0 + store atomic i8 0, ptr %a release, align 1, !pcsections !0 ret void } -define void @atomic8_store_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_store_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_store_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i8 0, i8* [[A:%.*]] seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: store atomic i8 0, ptr [[A:%.*]] seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i8 0, i8* %a seq_cst, align 1, !pcsections !0 + store atomic i8 0, ptr %a seq_cst, align 1, !pcsections !0 ret void } -define void @atomic8_xchg_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_xchg_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_xchg_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 monotonic monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 monotonic monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -104,18 +104,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i8* %a, i8 0 monotonic, !pcsections !0 + atomicrmw xchg ptr %a, i8 0 monotonic, !pcsections !0 ret void } -define void @atomic8_add_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_add_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_add_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -123,18 +123,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i8* %a, i8 0 monotonic, !pcsections !0 + atomicrmw add ptr %a, i8 0 monotonic, !pcsections !0 ret void } -define void @atomic8_sub_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_sub_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_sub_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -142,18 +142,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i8* %a, i8 0 monotonic, !pcsections !0 + atomicrmw sub ptr %a, i8 0 monotonic, !pcsections !0 ret void } -define void @atomic8_and_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_and_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_and_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 monotonic monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 monotonic monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -161,18 +161,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i8* %a, i8 0 monotonic, !pcsections !0 + atomicrmw and ptr %a, i8 0 monotonic, !pcsections !0 ret void } -define void @atomic8_or_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_or_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_or_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -180,18 +180,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i8* %a, i8 0 monotonic, !pcsections !0 + atomicrmw or ptr %a, i8 0 monotonic, !pcsections !0 ret void } -define void @atomic8_xor_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_xor_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_xor_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] monotonic monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -199,18 +199,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i8* %a, i8 0 monotonic, !pcsections !0 + atomicrmw xor ptr %a, i8 0 monotonic, !pcsections !0 ret void } -define void @atomic8_nand_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_nand_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_nand_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 -1 monotonic monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 -1 monotonic monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -218,18 +218,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i8* %a, i8 0 monotonic, !pcsections !0 + atomicrmw nand ptr %a, i8 0 monotonic, !pcsections !0 ret void } -define void @atomic8_xchg_acquire(i8* %a) nounwind uwtable { +define void @atomic8_xchg_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_xchg_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 acquire acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 acquire acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -237,18 +237,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i8* %a, i8 0 acquire, !pcsections !0 + atomicrmw xchg ptr %a, i8 0 acquire, !pcsections !0 ret void } -define void @atomic8_add_acquire(i8* %a) nounwind uwtable { +define void @atomic8_add_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_add_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -256,18 +256,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i8* %a, i8 0 acquire, !pcsections !0 + atomicrmw add ptr %a, i8 0 acquire, !pcsections !0 ret void } -define void @atomic8_sub_acquire(i8* %a) nounwind uwtable { +define void @atomic8_sub_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_sub_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -275,18 +275,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i8* %a, i8 0 acquire, !pcsections !0 + atomicrmw sub ptr %a, i8 0 acquire, !pcsections !0 ret void } -define void @atomic8_and_acquire(i8* %a) nounwind uwtable { +define void @atomic8_and_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_and_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 acquire acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 acquire acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -294,18 +294,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i8* %a, i8 0 acquire, !pcsections !0 + atomicrmw and ptr %a, i8 0 acquire, !pcsections !0 ret void } -define void @atomic8_or_acquire(i8* %a) nounwind uwtable { +define void @atomic8_or_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_or_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -313,18 +313,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i8* %a, i8 0 acquire, !pcsections !0 + atomicrmw or ptr %a, i8 0 acquire, !pcsections !0 ret void } -define void @atomic8_xor_acquire(i8* %a) nounwind uwtable { +define void @atomic8_xor_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_xor_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acquire acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -332,18 +332,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i8* %a, i8 0 acquire, !pcsections !0 + atomicrmw xor ptr %a, i8 0 acquire, !pcsections !0 ret void } -define void @atomic8_nand_acquire(i8* %a) nounwind uwtable { +define void @atomic8_nand_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_nand_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 -1 acquire acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 -1 acquire acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -351,18 +351,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i8* %a, i8 0 acquire, !pcsections !0 + atomicrmw nand ptr %a, i8 0 acquire, !pcsections !0 ret void } -define void @atomic8_xchg_release(i8* %a) nounwind uwtable { +define void @atomic8_xchg_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_xchg_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 release monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 release monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -370,18 +370,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i8* %a, i8 0 release, !pcsections !0 + atomicrmw xchg ptr %a, i8 0 release, !pcsections !0 ret void } -define void @atomic8_add_release(i8* %a) nounwind uwtable { +define void @atomic8_add_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_add_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -389,18 +389,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i8* %a, i8 0 release, !pcsections !0 + atomicrmw add ptr %a, i8 0 release, !pcsections !0 ret void } -define void @atomic8_sub_release(i8* %a) nounwind uwtable { +define void @atomic8_sub_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_sub_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -408,18 +408,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i8* %a, i8 0 release, !pcsections !0 + atomicrmw sub ptr %a, i8 0 release, !pcsections !0 ret void } -define void @atomic8_and_release(i8* %a) nounwind uwtable { +define void @atomic8_and_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_and_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 release monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 release monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -427,18 +427,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i8* %a, i8 0 release, !pcsections !0 + atomicrmw and ptr %a, i8 0 release, !pcsections !0 ret void } -define void @atomic8_or_release(i8* %a) nounwind uwtable { +define void @atomic8_or_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_or_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -446,18 +446,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i8* %a, i8 0 release, !pcsections !0 + atomicrmw or ptr %a, i8 0 release, !pcsections !0 ret void } -define void @atomic8_xor_release(i8* %a) nounwind uwtable { +define void @atomic8_xor_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_xor_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] release monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -465,18 +465,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i8* %a, i8 0 release, !pcsections !0 + atomicrmw xor ptr %a, i8 0 release, !pcsections !0 ret void } -define void @atomic8_nand_release(i8* %a) nounwind uwtable { +define void @atomic8_nand_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_nand_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 -1 release monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 -1 release monotonic, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -484,18 +484,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i8* %a, i8 0 release, !pcsections !0 + atomicrmw nand ptr %a, i8 0 release, !pcsections !0 ret void } -define void @atomic8_xchg_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_xchg_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_xchg_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 acq_rel acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 acq_rel acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -503,18 +503,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i8* %a, i8 0 acq_rel, !pcsections !0 + atomicrmw xchg ptr %a, i8 0 acq_rel, !pcsections !0 ret void } -define void @atomic8_add_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_add_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_add_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -522,18 +522,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i8* %a, i8 0 acq_rel, !pcsections !0 + atomicrmw add ptr %a, i8 0 acq_rel, !pcsections !0 ret void } -define void @atomic8_sub_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_sub_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_sub_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -541,18 +541,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i8* %a, i8 0 acq_rel, !pcsections !0 + atomicrmw sub ptr %a, i8 0 acq_rel, !pcsections !0 ret void } -define void @atomic8_and_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_and_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_and_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 acq_rel acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 acq_rel acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -560,18 +560,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i8* %a, i8 0 acq_rel, !pcsections !0 + atomicrmw and ptr %a, i8 0 acq_rel, !pcsections !0 ret void } -define void @atomic8_or_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_or_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_or_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -579,18 +579,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i8* %a, i8 0 acq_rel, !pcsections !0 + atomicrmw or ptr %a, i8 0 acq_rel, !pcsections !0 ret void } -define void @atomic8_xor_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_xor_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_xor_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] acq_rel acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -598,18 +598,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i8* %a, i8 0 acq_rel, !pcsections !0 + atomicrmw xor ptr %a, i8 0 acq_rel, !pcsections !0 ret void } -define void @atomic8_nand_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_nand_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_nand_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 -1 acq_rel acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 -1 acq_rel acquire, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -617,18 +617,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i8* %a, i8 0 acq_rel, !pcsections !0 + atomicrmw nand ptr %a, i8 0 acq_rel, !pcsections !0 ret void } -define void @atomic8_xchg_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_xchg_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_xchg_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 seq_cst seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 seq_cst seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -636,18 +636,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i8* %a, i8 0 seq_cst, !pcsections !0 + atomicrmw xchg ptr %a, i8 0 seq_cst, !pcsections !0 ret void } -define void @atomic8_add_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_add_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_add_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -655,18 +655,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i8* %a, i8 0 seq_cst, !pcsections !0 + atomicrmw add ptr %a, i8 0 seq_cst, !pcsections !0 ret void } -define void @atomic8_sub_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_sub_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_sub_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -674,18 +674,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i8* %a, i8 0 seq_cst, !pcsections !0 + atomicrmw sub ptr %a, i8 0 seq_cst, !pcsections !0 ret void } -define void @atomic8_and_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_and_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_and_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 0 seq_cst seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 0 seq_cst seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -693,18 +693,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i8* %a, i8 0 seq_cst, !pcsections !0 + atomicrmw and ptr %a, i8 0 seq_cst, !pcsections !0 ret void } -define void @atomic8_or_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_or_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_or_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -712,18 +712,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i8* %a, i8 0 seq_cst, !pcsections !0 + atomicrmw or ptr %a, i8 0 seq_cst, !pcsections !0 ret void } -define void @atomic8_xor_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_xor_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_xor_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 [[LOADED]] seq_cst seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -731,18 +731,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i8* %a, i8 0 seq_cst, !pcsections !0 + atomicrmw xor ptr %a, i8 0 seq_cst, !pcsections !0 ret void } -define void @atomic8_nand_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_nand_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_nand_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[A:%.*]], align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[A:%.*]], align 1, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i8 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 [[LOADED]], i8 -1 seq_cst seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 [[LOADED]], i8 -1 seq_cst seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i8, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i8, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -750,181 +750,181 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i8* %a, i8 0 seq_cst, !pcsections !0 + atomicrmw nand ptr %a, i8 0 seq_cst, !pcsections !0 ret void } -define void @atomic8_cas_monotonic(i8* %a) nounwind uwtable { +define void @atomic8_cas_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_cas_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i8* [[A:%.*]], i8 0, i8 1 monotonic monotonic, align 1, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 monotonic acquire, align 1, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 monotonic seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i8 0, i8 1 monotonic monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 monotonic acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 monotonic seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i8* %a, i8 0, i8 1 monotonic monotonic, !pcsections !0 - cmpxchg i8* %a, i8 0, i8 1 monotonic acquire, !pcsections !0 - cmpxchg i8* %a, i8 0, i8 1 monotonic seq_cst, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 monotonic monotonic, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 monotonic acquire, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 monotonic seq_cst, !pcsections !0 ret void } -define void @atomic8_cas_acquire(i8* %a) nounwind uwtable { +define void @atomic8_cas_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_cas_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i8* [[A:%.*]], i8 0, i8 1 acquire monotonic, align 1, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 acquire acquire, align 1, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 acquire seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i8 0, i8 1 acquire monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 acquire acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 acquire seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i8* %a, i8 0, i8 1 acquire monotonic, !pcsections !0 - cmpxchg i8* %a, i8 0, i8 1 acquire acquire, !pcsections !0 - cmpxchg i8* %a, i8 0, i8 1 acquire seq_cst, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 acquire monotonic, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 acquire acquire, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 acquire seq_cst, !pcsections !0 ret void } -define void @atomic8_cas_release(i8* %a) nounwind uwtable { +define void @atomic8_cas_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_cas_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i8* [[A:%.*]], i8 0, i8 1 release monotonic, align 1, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 release acquire, align 1, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 release seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i8 0, i8 1 release monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 release acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 release seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i8* %a, i8 0, i8 1 release monotonic, !pcsections !0 - cmpxchg i8* %a, i8 0, i8 1 release acquire, !pcsections !0 - cmpxchg i8* %a, i8 0, i8 1 release seq_cst, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 release monotonic, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 release acquire, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 release seq_cst, !pcsections !0 ret void } -define void @atomic8_cas_acq_rel(i8* %a) nounwind uwtable { +define void @atomic8_cas_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_cas_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i8* [[A:%.*]], i8 0, i8 1 acq_rel monotonic, align 1, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 acq_rel acquire, align 1, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 acq_rel seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i8 0, i8 1 acq_rel monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 acq_rel acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 acq_rel seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i8* %a, i8 0, i8 1 acq_rel monotonic, !pcsections !0 - cmpxchg i8* %a, i8 0, i8 1 acq_rel acquire, !pcsections !0 - cmpxchg i8* %a, i8 0, i8 1 acq_rel seq_cst, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 acq_rel monotonic, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 acq_rel acquire, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 acq_rel seq_cst, !pcsections !0 ret void } -define void @atomic8_cas_seq_cst(i8* %a) nounwind uwtable { +define void @atomic8_cas_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic8_cas_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i8* [[A:%.*]], i8 0, i8 1 seq_cst monotonic, align 1, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 seq_cst acquire, align 1, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i8* [[A]], i8 0, i8 1 seq_cst seq_cst, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i8 0, i8 1 seq_cst monotonic, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 seq_cst acquire, align 1, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i8 0, i8 1 seq_cst seq_cst, align 1, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i8* %a, i8 0, i8 1 seq_cst monotonic, !pcsections !0 - cmpxchg i8* %a, i8 0, i8 1 seq_cst acquire, !pcsections !0 - cmpxchg i8* %a, i8 0, i8 1 seq_cst seq_cst, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 seq_cst monotonic, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 seq_cst acquire, !pcsections !0 + cmpxchg ptr %a, i8 0, i8 1 seq_cst seq_cst, !pcsections !0 ret void } -define i16 @atomic16_load_unordered(i16* %a) nounwind uwtable { +define i16 @atomic16_load_unordered(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_load_unordered( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, i16* [[A:%.*]] unordered, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, ptr [[A:%.*]] unordered, align 2, !pcsections !0 ; CHECK-NEXT: ret i16 [[TMP0]] ; entry: - %0 = load atomic i16, i16* %a unordered, align 2, !pcsections !0 + %0 = load atomic i16, ptr %a unordered, align 2, !pcsections !0 ret i16 %0 } -define i16 @atomic16_load_monotonic(i16* %a) nounwind uwtable { +define i16 @atomic16_load_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_load_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, i16* [[A:%.*]] monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, ptr [[A:%.*]] monotonic, align 2, !pcsections !0 ; CHECK-NEXT: ret i16 [[TMP0]] ; entry: - %0 = load atomic i16, i16* %a monotonic, align 2, !pcsections !0 + %0 = load atomic i16, ptr %a monotonic, align 2, !pcsections !0 ret i16 %0 } -define i16 @atomic16_load_acquire(i16* %a) nounwind uwtable { +define i16 @atomic16_load_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_load_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, i16* [[A:%.*]] acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, ptr [[A:%.*]] acquire, align 2, !pcsections !0 ; CHECK-NEXT: ret i16 [[TMP0]] ; entry: - %0 = load atomic i16, i16* %a acquire, align 2, !pcsections !0 + %0 = load atomic i16, ptr %a acquire, align 2, !pcsections !0 ret i16 %0 } -define i16 @atomic16_load_seq_cst(i16* %a) nounwind uwtable { +define i16 @atomic16_load_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_load_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, i16* [[A:%.*]] seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i16, ptr [[A:%.*]] seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: ret i16 [[TMP0]] ; entry: - %0 = load atomic i16, i16* %a seq_cst, align 2, !pcsections !0 + %0 = load atomic i16, ptr %a seq_cst, align 2, !pcsections !0 ret i16 %0 } -define void @atomic16_store_unordered(i16* %a) nounwind uwtable { +define void @atomic16_store_unordered(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_store_unordered( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i16 0, i16* [[A:%.*]] unordered, align 2, !pcsections !0 +; CHECK-NEXT: store atomic i16 0, ptr [[A:%.*]] unordered, align 2, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i16 0, i16* %a unordered, align 2, !pcsections !0 + store atomic i16 0, ptr %a unordered, align 2, !pcsections !0 ret void } -define void @atomic16_store_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_store_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_store_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i16 0, i16* [[A:%.*]] monotonic, align 2, !pcsections !0 +; CHECK-NEXT: store atomic i16 0, ptr [[A:%.*]] monotonic, align 2, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i16 0, i16* %a monotonic, align 2, !pcsections !0 + store atomic i16 0, ptr %a monotonic, align 2, !pcsections !0 ret void } -define void @atomic16_store_release(i16* %a) nounwind uwtable { +define void @atomic16_store_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_store_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i16 0, i16* [[A:%.*]] release, align 2, !pcsections !0 +; CHECK-NEXT: store atomic i16 0, ptr [[A:%.*]] release, align 2, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i16 0, i16* %a release, align 2, !pcsections !0 + store atomic i16 0, ptr %a release, align 2, !pcsections !0 ret void } -define void @atomic16_store_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_store_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_store_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i16 0, i16* [[A:%.*]] seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: store atomic i16 0, ptr [[A:%.*]] seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i16 0, i16* %a seq_cst, align 2, !pcsections !0 + store atomic i16 0, ptr %a seq_cst, align 2, !pcsections !0 ret void } -define void @atomic16_xchg_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_xchg_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_xchg_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 monotonic monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 monotonic monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -932,18 +932,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i16* %a, i16 0 monotonic, !pcsections !0 + atomicrmw xchg ptr %a, i16 0 monotonic, !pcsections !0 ret void } -define void @atomic16_add_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_add_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_add_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -951,18 +951,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i16* %a, i16 0 monotonic, !pcsections !0 + atomicrmw add ptr %a, i16 0 monotonic, !pcsections !0 ret void } -define void @atomic16_sub_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_sub_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_sub_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -970,18 +970,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i16* %a, i16 0 monotonic, !pcsections !0 + atomicrmw sub ptr %a, i16 0 monotonic, !pcsections !0 ret void } -define void @atomic16_and_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_and_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_and_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 monotonic monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 monotonic monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -989,18 +989,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i16* %a, i16 0 monotonic, !pcsections !0 + atomicrmw and ptr %a, i16 0 monotonic, !pcsections !0 ret void } -define void @atomic16_or_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_or_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_or_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1008,18 +1008,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i16* %a, i16 0 monotonic, !pcsections !0 + atomicrmw or ptr %a, i16 0 monotonic, !pcsections !0 ret void } -define void @atomic16_xor_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_xor_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_xor_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] monotonic monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1027,18 +1027,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i16* %a, i16 0 monotonic, !pcsections !0 + atomicrmw xor ptr %a, i16 0 monotonic, !pcsections !0 ret void } -define void @atomic16_nand_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_nand_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_nand_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 -1 monotonic monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 -1 monotonic monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1046,18 +1046,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i16* %a, i16 0 monotonic, !pcsections !0 + atomicrmw nand ptr %a, i16 0 monotonic, !pcsections !0 ret void } -define void @atomic16_xchg_acquire(i16* %a) nounwind uwtable { +define void @atomic16_xchg_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_xchg_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 acquire acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 acquire acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1065,18 +1065,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i16* %a, i16 0 acquire, !pcsections !0 + atomicrmw xchg ptr %a, i16 0 acquire, !pcsections !0 ret void } -define void @atomic16_add_acquire(i16* %a) nounwind uwtable { +define void @atomic16_add_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_add_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1084,18 +1084,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i16* %a, i16 0 acquire, !pcsections !0 + atomicrmw add ptr %a, i16 0 acquire, !pcsections !0 ret void } -define void @atomic16_sub_acquire(i16* %a) nounwind uwtable { +define void @atomic16_sub_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_sub_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1103,18 +1103,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i16* %a, i16 0 acquire, !pcsections !0 + atomicrmw sub ptr %a, i16 0 acquire, !pcsections !0 ret void } -define void @atomic16_and_acquire(i16* %a) nounwind uwtable { +define void @atomic16_and_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_and_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 acquire acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 acquire acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1122,18 +1122,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i16* %a, i16 0 acquire, !pcsections !0 + atomicrmw and ptr %a, i16 0 acquire, !pcsections !0 ret void } -define void @atomic16_or_acquire(i16* %a) nounwind uwtable { +define void @atomic16_or_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_or_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1141,18 +1141,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i16* %a, i16 0 acquire, !pcsections !0 + atomicrmw or ptr %a, i16 0 acquire, !pcsections !0 ret void } -define void @atomic16_xor_acquire(i16* %a) nounwind uwtable { +define void @atomic16_xor_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_xor_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acquire acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1160,18 +1160,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i16* %a, i16 0 acquire, !pcsections !0 + atomicrmw xor ptr %a, i16 0 acquire, !pcsections !0 ret void } -define void @atomic16_nand_acquire(i16* %a) nounwind uwtable { +define void @atomic16_nand_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_nand_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 -1 acquire acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 -1 acquire acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1179,18 +1179,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i16* %a, i16 0 acquire, !pcsections !0 + atomicrmw nand ptr %a, i16 0 acquire, !pcsections !0 ret void } -define void @atomic16_xchg_release(i16* %a) nounwind uwtable { +define void @atomic16_xchg_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_xchg_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 release monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 release monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1198,18 +1198,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i16* %a, i16 0 release, !pcsections !0 + atomicrmw xchg ptr %a, i16 0 release, !pcsections !0 ret void } -define void @atomic16_add_release(i16* %a) nounwind uwtable { +define void @atomic16_add_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_add_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1217,18 +1217,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i16* %a, i16 0 release, !pcsections !0 + atomicrmw add ptr %a, i16 0 release, !pcsections !0 ret void } -define void @atomic16_sub_release(i16* %a) nounwind uwtable { +define void @atomic16_sub_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_sub_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1236,18 +1236,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i16* %a, i16 0 release, !pcsections !0 + atomicrmw sub ptr %a, i16 0 release, !pcsections !0 ret void } -define void @atomic16_and_release(i16* %a) nounwind uwtable { +define void @atomic16_and_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_and_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 release monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 release monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1255,18 +1255,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i16* %a, i16 0 release, !pcsections !0 + atomicrmw and ptr %a, i16 0 release, !pcsections !0 ret void } -define void @atomic16_or_release(i16* %a) nounwind uwtable { +define void @atomic16_or_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_or_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1274,18 +1274,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i16* %a, i16 0 release, !pcsections !0 + atomicrmw or ptr %a, i16 0 release, !pcsections !0 ret void } -define void @atomic16_xor_release(i16* %a) nounwind uwtable { +define void @atomic16_xor_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_xor_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] release monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1293,18 +1293,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i16* %a, i16 0 release, !pcsections !0 + atomicrmw xor ptr %a, i16 0 release, !pcsections !0 ret void } -define void @atomic16_nand_release(i16* %a) nounwind uwtable { +define void @atomic16_nand_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_nand_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 -1 release monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 -1 release monotonic, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1312,18 +1312,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i16* %a, i16 0 release, !pcsections !0 + atomicrmw nand ptr %a, i16 0 release, !pcsections !0 ret void } -define void @atomic16_xchg_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_xchg_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_xchg_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 acq_rel acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 acq_rel acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1331,18 +1331,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i16* %a, i16 0 acq_rel, !pcsections !0 + atomicrmw xchg ptr %a, i16 0 acq_rel, !pcsections !0 ret void } -define void @atomic16_add_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_add_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_add_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1350,18 +1350,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i16* %a, i16 0 acq_rel, !pcsections !0 + atomicrmw add ptr %a, i16 0 acq_rel, !pcsections !0 ret void } -define void @atomic16_sub_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_sub_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_sub_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1369,18 +1369,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i16* %a, i16 0 acq_rel, !pcsections !0 + atomicrmw sub ptr %a, i16 0 acq_rel, !pcsections !0 ret void } -define void @atomic16_and_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_and_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_and_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 acq_rel acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 acq_rel acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1388,18 +1388,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i16* %a, i16 0 acq_rel, !pcsections !0 + atomicrmw and ptr %a, i16 0 acq_rel, !pcsections !0 ret void } -define void @atomic16_or_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_or_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_or_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1407,18 +1407,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i16* %a, i16 0 acq_rel, !pcsections !0 + atomicrmw or ptr %a, i16 0 acq_rel, !pcsections !0 ret void } -define void @atomic16_xor_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_xor_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_xor_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] acq_rel acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1426,18 +1426,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i16* %a, i16 0 acq_rel, !pcsections !0 + atomicrmw xor ptr %a, i16 0 acq_rel, !pcsections !0 ret void } -define void @atomic16_nand_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_nand_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_nand_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 -1 acq_rel acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 -1 acq_rel acquire, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1445,18 +1445,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i16* %a, i16 0 acq_rel, !pcsections !0 + atomicrmw nand ptr %a, i16 0 acq_rel, !pcsections !0 ret void } -define void @atomic16_xchg_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_xchg_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_xchg_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 seq_cst seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 seq_cst seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1464,18 +1464,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i16* %a, i16 0 seq_cst, !pcsections !0 + atomicrmw xchg ptr %a, i16 0 seq_cst, !pcsections !0 ret void } -define void @atomic16_add_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_add_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_add_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1483,18 +1483,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i16* %a, i16 0 seq_cst, !pcsections !0 + atomicrmw add ptr %a, i16 0 seq_cst, !pcsections !0 ret void } -define void @atomic16_sub_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_sub_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_sub_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1502,18 +1502,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i16* %a, i16 0 seq_cst, !pcsections !0 + atomicrmw sub ptr %a, i16 0 seq_cst, !pcsections !0 ret void } -define void @atomic16_and_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_and_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_and_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 0 seq_cst seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 0 seq_cst seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1521,18 +1521,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i16* %a, i16 0 seq_cst, !pcsections !0 + atomicrmw and ptr %a, i16 0 seq_cst, !pcsections !0 ret void } -define void @atomic16_or_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_or_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_or_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1540,18 +1540,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i16* %a, i16 0 seq_cst, !pcsections !0 + atomicrmw or ptr %a, i16 0 seq_cst, !pcsections !0 ret void } -define void @atomic16_xor_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_xor_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_xor_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 [[LOADED]] seq_cst seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1559,18 +1559,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i16* %a, i16 0 seq_cst, !pcsections !0 + atomicrmw xor ptr %a, i16 0 seq_cst, !pcsections !0 ret void } -define void @atomic16_nand_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_nand_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_nand_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* [[A:%.*]], align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[A:%.*]], align 2, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i16 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 [[LOADED]], i16 -1 seq_cst seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 [[LOADED]], i16 -1 seq_cst seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i16, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i16, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1578,181 +1578,181 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i16* %a, i16 0 seq_cst, !pcsections !0 + atomicrmw nand ptr %a, i16 0 seq_cst, !pcsections !0 ret void } -define void @atomic16_cas_monotonic(i16* %a) nounwind uwtable { +define void @atomic16_cas_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_cas_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i16* [[A:%.*]], i16 0, i16 1 monotonic monotonic, align 2, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 monotonic acquire, align 2, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 monotonic seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i16 0, i16 1 monotonic monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 monotonic acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 monotonic seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i16* %a, i16 0, i16 1 monotonic monotonic, !pcsections !0 - cmpxchg i16* %a, i16 0, i16 1 monotonic acquire, !pcsections !0 - cmpxchg i16* %a, i16 0, i16 1 monotonic seq_cst, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 monotonic monotonic, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 monotonic acquire, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 monotonic seq_cst, !pcsections !0 ret void } -define void @atomic16_cas_acquire(i16* %a) nounwind uwtable { +define void @atomic16_cas_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_cas_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i16* [[A:%.*]], i16 0, i16 1 acquire monotonic, align 2, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 acquire acquire, align 2, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 acquire seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i16 0, i16 1 acquire monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 acquire acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 acquire seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i16* %a, i16 0, i16 1 acquire monotonic, !pcsections !0 - cmpxchg i16* %a, i16 0, i16 1 acquire acquire, !pcsections !0 - cmpxchg i16* %a, i16 0, i16 1 acquire seq_cst, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 acquire monotonic, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 acquire acquire, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 acquire seq_cst, !pcsections !0 ret void } -define void @atomic16_cas_release(i16* %a) nounwind uwtable { +define void @atomic16_cas_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_cas_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i16* [[A:%.*]], i16 0, i16 1 release monotonic, align 2, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 release acquire, align 2, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 release seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i16 0, i16 1 release monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 release acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 release seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i16* %a, i16 0, i16 1 release monotonic, !pcsections !0 - cmpxchg i16* %a, i16 0, i16 1 release acquire, !pcsections !0 - cmpxchg i16* %a, i16 0, i16 1 release seq_cst, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 release monotonic, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 release acquire, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 release seq_cst, !pcsections !0 ret void } -define void @atomic16_cas_acq_rel(i16* %a) nounwind uwtable { +define void @atomic16_cas_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_cas_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i16* [[A:%.*]], i16 0, i16 1 acq_rel monotonic, align 2, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 acq_rel acquire, align 2, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 acq_rel seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i16 0, i16 1 acq_rel monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 acq_rel acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 acq_rel seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i16* %a, i16 0, i16 1 acq_rel monotonic, !pcsections !0 - cmpxchg i16* %a, i16 0, i16 1 acq_rel acquire, !pcsections !0 - cmpxchg i16* %a, i16 0, i16 1 acq_rel seq_cst, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 acq_rel monotonic, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 acq_rel acquire, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 acq_rel seq_cst, !pcsections !0 ret void } -define void @atomic16_cas_seq_cst(i16* %a) nounwind uwtable { +define void @atomic16_cas_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic16_cas_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i16* [[A:%.*]], i16 0, i16 1 seq_cst monotonic, align 2, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 seq_cst acquire, align 2, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i16* [[A]], i16 0, i16 1 seq_cst seq_cst, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i16 0, i16 1 seq_cst monotonic, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 seq_cst acquire, align 2, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i16 0, i16 1 seq_cst seq_cst, align 2, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i16* %a, i16 0, i16 1 seq_cst monotonic, !pcsections !0 - cmpxchg i16* %a, i16 0, i16 1 seq_cst acquire, !pcsections !0 - cmpxchg i16* %a, i16 0, i16 1 seq_cst seq_cst, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 seq_cst monotonic, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 seq_cst acquire, !pcsections !0 + cmpxchg ptr %a, i16 0, i16 1 seq_cst seq_cst, !pcsections !0 ret void } -define i32 @atomic32_load_unordered(i32* %a) nounwind uwtable { +define i32 @atomic32_load_unordered(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_load_unordered( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, i32* [[A:%.*]] unordered, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, ptr [[A:%.*]] unordered, align 4, !pcsections !0 ; CHECK-NEXT: ret i32 [[TMP0]] ; entry: - %0 = load atomic i32, i32* %a unordered, align 4, !pcsections !0 + %0 = load atomic i32, ptr %a unordered, align 4, !pcsections !0 ret i32 %0 } -define i32 @atomic32_load_monotonic(i32* %a) nounwind uwtable { +define i32 @atomic32_load_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_load_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, i32* [[A:%.*]] monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, ptr [[A:%.*]] monotonic, align 4, !pcsections !0 ; CHECK-NEXT: ret i32 [[TMP0]] ; entry: - %0 = load atomic i32, i32* %a monotonic, align 4, !pcsections !0 + %0 = load atomic i32, ptr %a monotonic, align 4, !pcsections !0 ret i32 %0 } -define i32 @atomic32_load_acquire(i32* %a) nounwind uwtable { +define i32 @atomic32_load_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_load_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, i32* [[A:%.*]] acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, ptr [[A:%.*]] acquire, align 4, !pcsections !0 ; CHECK-NEXT: ret i32 [[TMP0]] ; entry: - %0 = load atomic i32, i32* %a acquire, align 4, !pcsections !0 + %0 = load atomic i32, ptr %a acquire, align 4, !pcsections !0 ret i32 %0 } -define i32 @atomic32_load_seq_cst(i32* %a) nounwind uwtable { +define i32 @atomic32_load_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_load_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, i32* [[A:%.*]] seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, ptr [[A:%.*]] seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: ret i32 [[TMP0]] ; entry: - %0 = load atomic i32, i32* %a seq_cst, align 4, !pcsections !0 + %0 = load atomic i32, ptr %a seq_cst, align 4, !pcsections !0 ret i32 %0 } -define void @atomic32_store_unordered(i32* %a) nounwind uwtable { +define void @atomic32_store_unordered(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_store_unordered( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i32 0, i32* [[A:%.*]] unordered, align 4, !pcsections !0 +; CHECK-NEXT: store atomic i32 0, ptr [[A:%.*]] unordered, align 4, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i32 0, i32* %a unordered, align 4, !pcsections !0 + store atomic i32 0, ptr %a unordered, align 4, !pcsections !0 ret void } -define void @atomic32_store_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_store_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_store_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i32 0, i32* [[A:%.*]] monotonic, align 4, !pcsections !0 +; CHECK-NEXT: store atomic i32 0, ptr [[A:%.*]] monotonic, align 4, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i32 0, i32* %a monotonic, align 4, !pcsections !0 + store atomic i32 0, ptr %a monotonic, align 4, !pcsections !0 ret void } -define void @atomic32_store_release(i32* %a) nounwind uwtable { +define void @atomic32_store_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_store_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i32 0, i32* [[A:%.*]] release, align 4, !pcsections !0 +; CHECK-NEXT: store atomic i32 0, ptr [[A:%.*]] release, align 4, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i32 0, i32* %a release, align 4, !pcsections !0 + store atomic i32 0, ptr %a release, align 4, !pcsections !0 ret void } -define void @atomic32_store_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_store_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_store_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i32 0, i32* [[A:%.*]] seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: store atomic i32 0, ptr [[A:%.*]] seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i32 0, i32* %a seq_cst, align 4, !pcsections !0 + store atomic i32 0, ptr %a seq_cst, align 4, !pcsections !0 ret void } -define void @atomic32_xchg_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_xchg_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_xchg_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 monotonic monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 monotonic monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1760,18 +1760,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i32* %a, i32 0 monotonic, !pcsections !0 + atomicrmw xchg ptr %a, i32 0 monotonic, !pcsections !0 ret void } -define void @atomic32_add_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_add_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_add_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1779,18 +1779,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i32* %a, i32 0 monotonic, !pcsections !0 + atomicrmw add ptr %a, i32 0 monotonic, !pcsections !0 ret void } -define void @atomic32_sub_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_sub_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_sub_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1798,18 +1798,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i32* %a, i32 0 monotonic, !pcsections !0 + atomicrmw sub ptr %a, i32 0 monotonic, !pcsections !0 ret void } -define void @atomic32_and_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_and_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_and_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 monotonic monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 monotonic monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1817,18 +1817,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i32* %a, i32 0 monotonic, !pcsections !0 + atomicrmw and ptr %a, i32 0 monotonic, !pcsections !0 ret void } -define void @atomic32_or_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_or_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_or_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1836,18 +1836,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i32* %a, i32 0 monotonic, !pcsections !0 + atomicrmw or ptr %a, i32 0 monotonic, !pcsections !0 ret void } -define void @atomic32_xor_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_xor_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_xor_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] monotonic monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1855,18 +1855,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i32* %a, i32 0 monotonic, !pcsections !0 + atomicrmw xor ptr %a, i32 0 monotonic, !pcsections !0 ret void } -define void @atomic32_nand_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_nand_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_nand_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 -1 monotonic monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 -1 monotonic monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1874,18 +1874,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i32* %a, i32 0 monotonic, !pcsections !0 + atomicrmw nand ptr %a, i32 0 monotonic, !pcsections !0 ret void } -define void @atomic32_xchg_acquire(i32* %a) nounwind uwtable { +define void @atomic32_xchg_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_xchg_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 acquire acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 acquire acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1893,18 +1893,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i32* %a, i32 0 acquire, !pcsections !0 + atomicrmw xchg ptr %a, i32 0 acquire, !pcsections !0 ret void } -define void @atomic32_add_acquire(i32* %a) nounwind uwtable { +define void @atomic32_add_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_add_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1912,18 +1912,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i32* %a, i32 0 acquire, !pcsections !0 + atomicrmw add ptr %a, i32 0 acquire, !pcsections !0 ret void } -define void @atomic32_sub_acquire(i32* %a) nounwind uwtable { +define void @atomic32_sub_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_sub_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1931,18 +1931,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i32* %a, i32 0 acquire, !pcsections !0 + atomicrmw sub ptr %a, i32 0 acquire, !pcsections !0 ret void } -define void @atomic32_and_acquire(i32* %a) nounwind uwtable { +define void @atomic32_and_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_and_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 acquire acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 acquire acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1950,18 +1950,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i32* %a, i32 0 acquire, !pcsections !0 + atomicrmw and ptr %a, i32 0 acquire, !pcsections !0 ret void } -define void @atomic32_or_acquire(i32* %a) nounwind uwtable { +define void @atomic32_or_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_or_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1969,18 +1969,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i32* %a, i32 0 acquire, !pcsections !0 + atomicrmw or ptr %a, i32 0 acquire, !pcsections !0 ret void } -define void @atomic32_xor_acquire(i32* %a) nounwind uwtable { +define void @atomic32_xor_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_xor_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acquire acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -1988,18 +1988,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i32* %a, i32 0 acquire, !pcsections !0 + atomicrmw xor ptr %a, i32 0 acquire, !pcsections !0 ret void } -define void @atomic32_nand_acquire(i32* %a) nounwind uwtable { +define void @atomic32_nand_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_nand_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 -1 acquire acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 -1 acquire acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2007,18 +2007,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i32* %a, i32 0 acquire, !pcsections !0 + atomicrmw nand ptr %a, i32 0 acquire, !pcsections !0 ret void } -define void @atomic32_xchg_release(i32* %a) nounwind uwtable { +define void @atomic32_xchg_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_xchg_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 release monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 release monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2026,18 +2026,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i32* %a, i32 0 release, !pcsections !0 + atomicrmw xchg ptr %a, i32 0 release, !pcsections !0 ret void } -define void @atomic32_add_release(i32* %a) nounwind uwtable { +define void @atomic32_add_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_add_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2045,18 +2045,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i32* %a, i32 0 release, !pcsections !0 + atomicrmw add ptr %a, i32 0 release, !pcsections !0 ret void } -define void @atomic32_sub_release(i32* %a) nounwind uwtable { +define void @atomic32_sub_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_sub_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2064,18 +2064,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i32* %a, i32 0 release, !pcsections !0 + atomicrmw sub ptr %a, i32 0 release, !pcsections !0 ret void } -define void @atomic32_and_release(i32* %a) nounwind uwtable { +define void @atomic32_and_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_and_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 release monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 release monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2083,18 +2083,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i32* %a, i32 0 release, !pcsections !0 + atomicrmw and ptr %a, i32 0 release, !pcsections !0 ret void } -define void @atomic32_or_release(i32* %a) nounwind uwtable { +define void @atomic32_or_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_or_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2102,18 +2102,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i32* %a, i32 0 release, !pcsections !0 + atomicrmw or ptr %a, i32 0 release, !pcsections !0 ret void } -define void @atomic32_xor_release(i32* %a) nounwind uwtable { +define void @atomic32_xor_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_xor_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] release monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2121,18 +2121,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i32* %a, i32 0 release, !pcsections !0 + atomicrmw xor ptr %a, i32 0 release, !pcsections !0 ret void } -define void @atomic32_nand_release(i32* %a) nounwind uwtable { +define void @atomic32_nand_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_nand_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 -1 release monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 -1 release monotonic, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2140,18 +2140,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i32* %a, i32 0 release, !pcsections !0 + atomicrmw nand ptr %a, i32 0 release, !pcsections !0 ret void } -define void @atomic32_xchg_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_xchg_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_xchg_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 acq_rel acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 acq_rel acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2159,18 +2159,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i32* %a, i32 0 acq_rel, !pcsections !0 + atomicrmw xchg ptr %a, i32 0 acq_rel, !pcsections !0 ret void } -define void @atomic32_add_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_add_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_add_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2178,18 +2178,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i32* %a, i32 0 acq_rel, !pcsections !0 + atomicrmw add ptr %a, i32 0 acq_rel, !pcsections !0 ret void } -define void @atomic32_sub_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_sub_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_sub_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2197,18 +2197,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i32* %a, i32 0 acq_rel, !pcsections !0 + atomicrmw sub ptr %a, i32 0 acq_rel, !pcsections !0 ret void } -define void @atomic32_and_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_and_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_and_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 acq_rel acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 acq_rel acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2216,18 +2216,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i32* %a, i32 0 acq_rel, !pcsections !0 + atomicrmw and ptr %a, i32 0 acq_rel, !pcsections !0 ret void } -define void @atomic32_or_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_or_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_or_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2235,18 +2235,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i32* %a, i32 0 acq_rel, !pcsections !0 + atomicrmw or ptr %a, i32 0 acq_rel, !pcsections !0 ret void } -define void @atomic32_xor_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_xor_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_xor_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] acq_rel acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2254,18 +2254,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i32* %a, i32 0 acq_rel, !pcsections !0 + atomicrmw xor ptr %a, i32 0 acq_rel, !pcsections !0 ret void } -define void @atomic32_nand_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_nand_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_nand_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 -1 acq_rel acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 -1 acq_rel acquire, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2273,18 +2273,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i32* %a, i32 0 acq_rel, !pcsections !0 + atomicrmw nand ptr %a, i32 0 acq_rel, !pcsections !0 ret void } -define void @atomic32_xchg_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_xchg_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_xchg_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 seq_cst seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 seq_cst seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2292,18 +2292,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i32* %a, i32 0 seq_cst, !pcsections !0 + atomicrmw xchg ptr %a, i32 0 seq_cst, !pcsections !0 ret void } -define void @atomic32_add_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_add_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_add_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2311,18 +2311,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i32* %a, i32 0 seq_cst, !pcsections !0 + atomicrmw add ptr %a, i32 0 seq_cst, !pcsections !0 ret void } -define void @atomic32_sub_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_sub_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_sub_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2330,18 +2330,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i32* %a, i32 0 seq_cst, !pcsections !0 + atomicrmw sub ptr %a, i32 0 seq_cst, !pcsections !0 ret void } -define void @atomic32_and_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_and_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_and_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 0 seq_cst seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 0 seq_cst seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2349,18 +2349,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i32* %a, i32 0 seq_cst, !pcsections !0 + atomicrmw and ptr %a, i32 0 seq_cst, !pcsections !0 ret void } -define void @atomic32_or_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_or_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_or_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2368,18 +2368,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i32* %a, i32 0 seq_cst, !pcsections !0 + atomicrmw or ptr %a, i32 0 seq_cst, !pcsections !0 ret void } -define void @atomic32_xor_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_xor_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_xor_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 [[LOADED]] seq_cst seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2387,18 +2387,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i32* %a, i32 0 seq_cst, !pcsections !0 + atomicrmw xor ptr %a, i32 0 seq_cst, !pcsections !0 ret void } -define void @atomic32_nand_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_nand_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_nand_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A:%.*]], align 4, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 [[LOADED]], i32 -1 seq_cst seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 [[LOADED]], i32 -1 seq_cst seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2406,203 +2406,203 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i32* %a, i32 0 seq_cst, !pcsections !0 + atomicrmw nand ptr %a, i32 0 seq_cst, !pcsections !0 ret void } -define void @atomic32_cas_monotonic(i32* %a) nounwind uwtable { +define void @atomic32_cas_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_cas_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i32* [[A:%.*]], i32 0, i32 1 monotonic monotonic, align 4, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 monotonic acquire, align 4, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 monotonic seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i32 0, i32 1 monotonic monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 monotonic acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 monotonic seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i32* %a, i32 0, i32 1 monotonic monotonic, !pcsections !0 - cmpxchg i32* %a, i32 0, i32 1 monotonic acquire, !pcsections !0 - cmpxchg i32* %a, i32 0, i32 1 monotonic seq_cst, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 monotonic monotonic, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 monotonic acquire, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 monotonic seq_cst, !pcsections !0 ret void } -define void @atomic32_cas_acquire(i32* %a) nounwind uwtable { +define void @atomic32_cas_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_cas_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i32* [[A:%.*]], i32 0, i32 1 acquire monotonic, align 4, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 acquire acquire, align 4, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 acquire seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i32 0, i32 1 acquire monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 acquire acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 acquire seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i32* %a, i32 0, i32 1 acquire monotonic, !pcsections !0 - cmpxchg i32* %a, i32 0, i32 1 acquire acquire, !pcsections !0 - cmpxchg i32* %a, i32 0, i32 1 acquire seq_cst, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 acquire monotonic, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 acquire acquire, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 acquire seq_cst, !pcsections !0 ret void } -define void @atomic32_cas_release(i32* %a) nounwind uwtable { +define void @atomic32_cas_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_cas_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i32* [[A:%.*]], i32 0, i32 1 release monotonic, align 4, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 release acquire, align 4, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 release seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i32 0, i32 1 release monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 release acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 release seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i32* %a, i32 0, i32 1 release monotonic, !pcsections !0 - cmpxchg i32* %a, i32 0, i32 1 release acquire, !pcsections !0 - cmpxchg i32* %a, i32 0, i32 1 release seq_cst, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 release monotonic, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 release acquire, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 release seq_cst, !pcsections !0 ret void } -define void @atomic32_cas_acq_rel(i32* %a) nounwind uwtable { +define void @atomic32_cas_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_cas_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i32* [[A:%.*]], i32 0, i32 1 acq_rel monotonic, align 4, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 acq_rel acquire, align 4, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 acq_rel seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i32 0, i32 1 acq_rel monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 acq_rel acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 acq_rel seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i32* %a, i32 0, i32 1 acq_rel monotonic, !pcsections !0 - cmpxchg i32* %a, i32 0, i32 1 acq_rel acquire, !pcsections !0 - cmpxchg i32* %a, i32 0, i32 1 acq_rel seq_cst, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 acq_rel monotonic, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 acq_rel acquire, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 acq_rel seq_cst, !pcsections !0 ret void } -define void @atomic32_cas_seq_cst(i32* %a) nounwind uwtable { +define void @atomic32_cas_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic32_cas_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i32* [[A:%.*]], i32 0, i32 1 seq_cst monotonic, align 4, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 seq_cst acquire, align 4, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i32* [[A]], i32 0, i32 1 seq_cst seq_cst, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i32 0, i32 1 seq_cst monotonic, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 seq_cst acquire, align 4, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i32 0, i32 1 seq_cst seq_cst, align 4, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i32* %a, i32 0, i32 1 seq_cst monotonic, !pcsections !0 - cmpxchg i32* %a, i32 0, i32 1 seq_cst acquire, !pcsections !0 - cmpxchg i32* %a, i32 0, i32 1 seq_cst seq_cst, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 seq_cst monotonic, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 seq_cst acquire, !pcsections !0 + cmpxchg ptr %a, i32 0, i32 1 seq_cst seq_cst, !pcsections !0 ret void } -define i64 @atomic64_load_unordered(i64* %a) nounwind uwtable { +define i64 @atomic64_load_unordered(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_load_unordered( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, i64* [[A:%.*]] unordered, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, ptr [[A:%.*]] unordered, align 8, !pcsections !0 ; CHECK-NEXT: ret i64 [[TMP0]] ; entry: - %0 = load atomic i64, i64* %a unordered, align 8, !pcsections !0 + %0 = load atomic i64, ptr %a unordered, align 8, !pcsections !0 ret i64 %0 } -define i64 @atomic64_load_monotonic(i64* %a) nounwind uwtable { +define i64 @atomic64_load_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_load_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, i64* [[A:%.*]] monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, ptr [[A:%.*]] monotonic, align 8, !pcsections !0 ; CHECK-NEXT: ret i64 [[TMP0]] ; entry: - %0 = load atomic i64, i64* %a monotonic, align 8, !pcsections !0 + %0 = load atomic i64, ptr %a monotonic, align 8, !pcsections !0 ret i64 %0 } -define i64 @atomic64_load_acquire(i64* %a) nounwind uwtable { +define i64 @atomic64_load_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_load_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, i64* [[A:%.*]] acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, ptr [[A:%.*]] acquire, align 8, !pcsections !0 ; CHECK-NEXT: ret i64 [[TMP0]] ; entry: - %0 = load atomic i64, i64* %a acquire, align 8, !pcsections !0 + %0 = load atomic i64, ptr %a acquire, align 8, !pcsections !0 ret i64 %0 } -define i64 @atomic64_load_seq_cst(i64* %a) nounwind uwtable { +define i64 @atomic64_load_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_load_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, i64* [[A:%.*]] seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, ptr [[A:%.*]] seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: ret i64 [[TMP0]] ; entry: - %0 = load atomic i64, i64* %a seq_cst, align 8, !pcsections !0 + %0 = load atomic i64, ptr %a seq_cst, align 8, !pcsections !0 ret i64 %0 } -define i8* @atomic64_load_seq_cst_ptr_ty(i8** %a) nounwind uwtable { +define ptr @atomic64_load_seq_cst_ptr_ty(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_load_seq_cst_ptr_ty( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load atomic i8*, i8** [[A:%.*]] seq_cst, align 8, !pcsections !0 -; CHECK-NEXT: ret i8* [[TMP0]] +; CHECK-NEXT: [[TMP0:%.*]] = load atomic ptr, ptr [[A:%.*]] seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: ret ptr [[TMP0]] ; entry: - %0 = load atomic i8*, i8** %a seq_cst, align 8, !pcsections !0 - ret i8* %0 + %0 = load atomic ptr, ptr %a seq_cst, align 8, !pcsections !0 + ret ptr %0 } -define void @atomic64_store_unordered(i64* %a) nounwind uwtable { +define void @atomic64_store_unordered(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_store_unordered( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i64 0, i64* [[A:%.*]] unordered, align 8, !pcsections !0 +; CHECK-NEXT: store atomic i64 0, ptr [[A:%.*]] unordered, align 8, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i64 0, i64* %a unordered, align 8, !pcsections !0 + store atomic i64 0, ptr %a unordered, align 8, !pcsections !0 ret void } -define void @atomic64_store_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_store_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_store_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i64 0, i64* [[A:%.*]] monotonic, align 8, !pcsections !0 +; CHECK-NEXT: store atomic i64 0, ptr [[A:%.*]] monotonic, align 8, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i64 0, i64* %a monotonic, align 8, !pcsections !0 + store atomic i64 0, ptr %a monotonic, align 8, !pcsections !0 ret void } -define void @atomic64_store_release(i64* %a) nounwind uwtable { +define void @atomic64_store_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_store_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i64 0, i64* [[A:%.*]] release, align 8, !pcsections !0 +; CHECK-NEXT: store atomic i64 0, ptr [[A:%.*]] release, align 8, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i64 0, i64* %a release, align 8, !pcsections !0 + store atomic i64 0, ptr %a release, align 8, !pcsections !0 ret void } -define void @atomic64_store_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_store_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_store_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i64 0, i64* [[A:%.*]] seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: store atomic i64 0, ptr [[A:%.*]] seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i64 0, i64* %a seq_cst, align 8, !pcsections !0 + store atomic i64 0, ptr %a seq_cst, align 8, !pcsections !0 ret void } -define void @atomic64_store_seq_cst_ptr_ty(i8** %a, i8* %v) nounwind uwtable { +define void @atomic64_store_seq_cst_ptr_ty(ptr %a, ptr %v) nounwind uwtable { ; CHECK-LABEL: @atomic64_store_seq_cst_ptr_ty( ; CHECK-NEXT: entry: -; CHECK-NEXT: store atomic i8* [[V:%.*]], i8** [[A:%.*]] seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: store atomic ptr [[V:%.*]], ptr [[A:%.*]] seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - store atomic i8* %v, i8** %a seq_cst, align 8, !pcsections !0 + store atomic ptr %v, ptr %a seq_cst, align 8, !pcsections !0 ret void } -define void @atomic64_xchg_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_xchg_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_xchg_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 monotonic monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 monotonic monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2610,18 +2610,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i64* %a, i64 0 monotonic, !pcsections !0 + atomicrmw xchg ptr %a, i64 0 monotonic, !pcsections !0 ret void } -define void @atomic64_add_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_add_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_add_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2629,18 +2629,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i64* %a, i64 0 monotonic, !pcsections !0 + atomicrmw add ptr %a, i64 0 monotonic, !pcsections !0 ret void } -define void @atomic64_sub_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_sub_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_sub_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2648,18 +2648,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i64* %a, i64 0 monotonic, !pcsections !0 + atomicrmw sub ptr %a, i64 0 monotonic, !pcsections !0 ret void } -define void @atomic64_and_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_and_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_and_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 monotonic monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 monotonic monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2667,18 +2667,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i64* %a, i64 0 monotonic, !pcsections !0 + atomicrmw and ptr %a, i64 0 monotonic, !pcsections !0 ret void } -define void @atomic64_or_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_or_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_or_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2686,18 +2686,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i64* %a, i64 0 monotonic, !pcsections !0 + atomicrmw or ptr %a, i64 0 monotonic, !pcsections !0 ret void } -define void @atomic64_xor_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_xor_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_xor_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] monotonic monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2705,18 +2705,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i64* %a, i64 0 monotonic, !pcsections !0 + atomicrmw xor ptr %a, i64 0 monotonic, !pcsections !0 ret void } -define void @atomic64_nand_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_nand_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_nand_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 -1 monotonic monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 -1 monotonic monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2724,18 +2724,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i64* %a, i64 0 monotonic, !pcsections !0 + atomicrmw nand ptr %a, i64 0 monotonic, !pcsections !0 ret void } -define void @atomic64_xchg_acquire(i64* %a) nounwind uwtable { +define void @atomic64_xchg_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_xchg_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 acquire acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 acquire acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2743,18 +2743,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i64* %a, i64 0 acquire, !pcsections !0 + atomicrmw xchg ptr %a, i64 0 acquire, !pcsections !0 ret void } -define void @atomic64_add_acquire(i64* %a) nounwind uwtable { +define void @atomic64_add_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_add_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2762,18 +2762,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i64* %a, i64 0 acquire, !pcsections !0 + atomicrmw add ptr %a, i64 0 acquire, !pcsections !0 ret void } -define void @atomic64_sub_acquire(i64* %a) nounwind uwtable { +define void @atomic64_sub_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_sub_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2781,18 +2781,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i64* %a, i64 0 acquire, !pcsections !0 + atomicrmw sub ptr %a, i64 0 acquire, !pcsections !0 ret void } -define void @atomic64_and_acquire(i64* %a) nounwind uwtable { +define void @atomic64_and_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_and_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 acquire acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 acquire acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2800,18 +2800,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i64* %a, i64 0 acquire, !pcsections !0 + atomicrmw and ptr %a, i64 0 acquire, !pcsections !0 ret void } -define void @atomic64_or_acquire(i64* %a) nounwind uwtable { +define void @atomic64_or_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_or_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2819,18 +2819,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i64* %a, i64 0 acquire, !pcsections !0 + atomicrmw or ptr %a, i64 0 acquire, !pcsections !0 ret void } -define void @atomic64_xor_acquire(i64* %a) nounwind uwtable { +define void @atomic64_xor_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_xor_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acquire acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2838,18 +2838,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i64* %a, i64 0 acquire, !pcsections !0 + atomicrmw xor ptr %a, i64 0 acquire, !pcsections !0 ret void } -define void @atomic64_nand_acquire(i64* %a) nounwind uwtable { +define void @atomic64_nand_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_nand_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 -1 acquire acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 -1 acquire acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2857,18 +2857,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i64* %a, i64 0 acquire, !pcsections !0 + atomicrmw nand ptr %a, i64 0 acquire, !pcsections !0 ret void } -define void @atomic64_xchg_release(i64* %a) nounwind uwtable { +define void @atomic64_xchg_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_xchg_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 release monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 release monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2876,18 +2876,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i64* %a, i64 0 release, !pcsections !0 + atomicrmw xchg ptr %a, i64 0 release, !pcsections !0 ret void } -define void @atomic64_add_release(i64* %a) nounwind uwtable { +define void @atomic64_add_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_add_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2895,18 +2895,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i64* %a, i64 0 release, !pcsections !0 + atomicrmw add ptr %a, i64 0 release, !pcsections !0 ret void } -define void @atomic64_sub_release(i64* %a) nounwind uwtable { +define void @atomic64_sub_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_sub_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2914,18 +2914,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i64* %a, i64 0 release, !pcsections !0 + atomicrmw sub ptr %a, i64 0 release, !pcsections !0 ret void } -define void @atomic64_and_release(i64* %a) nounwind uwtable { +define void @atomic64_and_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_and_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 release monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 release monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2933,18 +2933,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i64* %a, i64 0 release, !pcsections !0 + atomicrmw and ptr %a, i64 0 release, !pcsections !0 ret void } -define void @atomic64_or_release(i64* %a) nounwind uwtable { +define void @atomic64_or_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_or_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2952,18 +2952,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i64* %a, i64 0 release, !pcsections !0 + atomicrmw or ptr %a, i64 0 release, !pcsections !0 ret void } -define void @atomic64_xor_release(i64* %a) nounwind uwtable { +define void @atomic64_xor_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_xor_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] release monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2971,18 +2971,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i64* %a, i64 0 release, !pcsections !0 + atomicrmw xor ptr %a, i64 0 release, !pcsections !0 ret void } -define void @atomic64_nand_release(i64* %a) nounwind uwtable { +define void @atomic64_nand_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_nand_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 -1 release monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 -1 release monotonic, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -2990,18 +2990,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i64* %a, i64 0 release, !pcsections !0 + atomicrmw nand ptr %a, i64 0 release, !pcsections !0 ret void } -define void @atomic64_xchg_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_xchg_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_xchg_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 acq_rel acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 acq_rel acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3009,18 +3009,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i64* %a, i64 0 acq_rel, !pcsections !0 + atomicrmw xchg ptr %a, i64 0 acq_rel, !pcsections !0 ret void } -define void @atomic64_add_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_add_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_add_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3028,18 +3028,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i64* %a, i64 0 acq_rel, !pcsections !0 + atomicrmw add ptr %a, i64 0 acq_rel, !pcsections !0 ret void } -define void @atomic64_sub_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_sub_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_sub_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3047,18 +3047,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i64* %a, i64 0 acq_rel, !pcsections !0 + atomicrmw sub ptr %a, i64 0 acq_rel, !pcsections !0 ret void } -define void @atomic64_and_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_and_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_and_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 acq_rel acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 acq_rel acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3066,18 +3066,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i64* %a, i64 0 acq_rel, !pcsections !0 + atomicrmw and ptr %a, i64 0 acq_rel, !pcsections !0 ret void } -define void @atomic64_or_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_or_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_or_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3085,18 +3085,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i64* %a, i64 0 acq_rel, !pcsections !0 + atomicrmw or ptr %a, i64 0 acq_rel, !pcsections !0 ret void } -define void @atomic64_xor_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_xor_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_xor_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] acq_rel acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3104,18 +3104,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i64* %a, i64 0 acq_rel, !pcsections !0 + atomicrmw xor ptr %a, i64 0 acq_rel, !pcsections !0 ret void } -define void @atomic64_nand_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_nand_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_nand_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 -1 acq_rel acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 -1 acq_rel acquire, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3123,18 +3123,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i64* %a, i64 0 acq_rel, !pcsections !0 + atomicrmw nand ptr %a, i64 0 acq_rel, !pcsections !0 ret void } -define void @atomic64_xchg_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_xchg_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_xchg_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 seq_cst seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 seq_cst seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3142,18 +3142,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i64* %a, i64 0 seq_cst, !pcsections !0 + atomicrmw xchg ptr %a, i64 0 seq_cst, !pcsections !0 ret void } -define void @atomic64_add_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_add_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_add_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3161,18 +3161,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i64* %a, i64 0 seq_cst, !pcsections !0 + atomicrmw add ptr %a, i64 0 seq_cst, !pcsections !0 ret void } -define void @atomic64_sub_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_sub_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_sub_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3180,18 +3180,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i64* %a, i64 0 seq_cst, !pcsections !0 + atomicrmw sub ptr %a, i64 0 seq_cst, !pcsections !0 ret void } -define void @atomic64_and_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_and_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_and_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 0 seq_cst seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 0 seq_cst seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3199,18 +3199,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i64* %a, i64 0 seq_cst, !pcsections !0 + atomicrmw and ptr %a, i64 0 seq_cst, !pcsections !0 ret void } -define void @atomic64_or_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_or_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_or_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3218,18 +3218,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i64* %a, i64 0 seq_cst, !pcsections !0 + atomicrmw or ptr %a, i64 0 seq_cst, !pcsections !0 ret void } -define void @atomic64_xor_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_xor_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_xor_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 [[LOADED]] seq_cst seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3237,18 +3237,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i64* %a, i64 0 seq_cst, !pcsections !0 + atomicrmw xor ptr %a, i64 0 seq_cst, !pcsections !0 ret void } -define void @atomic64_nand_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_nand_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_nand_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[A:%.*]], align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A:%.*]], align 8, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 [[LOADED]], i64 -1 seq_cst seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 [[LOADED]], i64 -1 seq_cst seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3256,160 +3256,159 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i64* %a, i64 0 seq_cst, !pcsections !0 + atomicrmw nand ptr %a, i64 0 seq_cst, !pcsections !0 ret void } -define void @atomic64_cas_monotonic(i64* %a) nounwind uwtable { +define void @atomic64_cas_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_cas_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i64* [[A:%.*]], i64 0, i64 1 monotonic monotonic, align 8, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 monotonic acquire, align 8, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 monotonic seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i64 0, i64 1 monotonic monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 monotonic acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 monotonic seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i64* %a, i64 0, i64 1 monotonic monotonic, !pcsections !0 - cmpxchg i64* %a, i64 0, i64 1 monotonic acquire, !pcsections !0 - cmpxchg i64* %a, i64 0, i64 1 monotonic seq_cst, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 monotonic monotonic, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 monotonic acquire, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 monotonic seq_cst, !pcsections !0 ret void } -define void @atomic64_cas_acquire(i64* %a) nounwind uwtable { +define void @atomic64_cas_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_cas_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i64* [[A:%.*]], i64 0, i64 1 acquire monotonic, align 8, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 acquire acquire, align 8, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 acquire seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i64 0, i64 1 acquire monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 acquire acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 acquire seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i64* %a, i64 0, i64 1 acquire monotonic, !pcsections !0 - cmpxchg i64* %a, i64 0, i64 1 acquire acquire, !pcsections !0 - cmpxchg i64* %a, i64 0, i64 1 acquire seq_cst, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 acquire monotonic, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 acquire acquire, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 acquire seq_cst, !pcsections !0 ret void } -define void @atomic64_cas_release(i64* %a) nounwind uwtable { +define void @atomic64_cas_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_cas_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i64* [[A:%.*]], i64 0, i64 1 release monotonic, align 8, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 release acquire, align 8, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 release seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i64 0, i64 1 release monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 release acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 release seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i64* %a, i64 0, i64 1 release monotonic, !pcsections !0 - cmpxchg i64* %a, i64 0, i64 1 release acquire, !pcsections !0 - cmpxchg i64* %a, i64 0, i64 1 release seq_cst, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 release monotonic, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 release acquire, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 release seq_cst, !pcsections !0 ret void } -define void @atomic64_cas_acq_rel(i64* %a) nounwind uwtable { +define void @atomic64_cas_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_cas_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i64* [[A:%.*]], i64 0, i64 1 acq_rel monotonic, align 8, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 acq_rel acquire, align 8, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 acq_rel seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i64 0, i64 1 acq_rel monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 acq_rel acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 acq_rel seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i64* %a, i64 0, i64 1 acq_rel monotonic, !pcsections !0 - cmpxchg i64* %a, i64 0, i64 1 acq_rel acquire, !pcsections !0 - cmpxchg i64* %a, i64 0, i64 1 acq_rel seq_cst, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 acq_rel monotonic, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 acq_rel acquire, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 acq_rel seq_cst, !pcsections !0 ret void } -define void @atomic64_cas_seq_cst(i64* %a) nounwind uwtable { +define void @atomic64_cas_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic64_cas_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i64* [[A:%.*]], i64 0, i64 1 seq_cst monotonic, align 8, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 seq_cst acquire, align 8, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg i64* [[A]], i64 0, i64 1 seq_cst seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i64 0, i64 1 seq_cst monotonic, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 seq_cst acquire, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = cmpxchg ptr [[A]], i64 0, i64 1 seq_cst seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i64* %a, i64 0, i64 1 seq_cst monotonic, !pcsections !0 - cmpxchg i64* %a, i64 0, i64 1 seq_cst acquire, !pcsections !0 - cmpxchg i64* %a, i64 0, i64 1 seq_cst seq_cst, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 seq_cst monotonic, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 seq_cst acquire, !pcsections !0 + cmpxchg ptr %a, i64 0, i64 1 seq_cst seq_cst, !pcsections !0 ret void } -define void @atomic64_cas_seq_cst_ptr_ty(i8** %a, i8* %v1, i8* %v2) nounwind uwtable { +define void @atomic64_cas_seq_cst_ptr_ty(ptr %a, ptr %v1, ptr %v2) nounwind uwtable { ; CHECK-LABEL: @atomic64_cas_seq_cst_ptr_ty( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = bitcast i8** [[A:%.*]] to i64*, !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8* [[V1:%.*]] to i64, !pcsections !0 -; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint i8* [[V2:%.*]] to i64, !pcsections !0 -; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i64* [[TMP0]], i64 [[TMP1]], i64 [[TMP2]] seq_cst seq_cst, align 8, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[V1:%.*]] to i64, !pcsections !0 +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[V2:%.*]] to i64, !pcsections !0 +; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg ptr [[A:%.*]], i64 [[TMP1]], i64 [[TMP2]] seq_cst seq_cst, align 8, !pcsections !0 ; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP3]], 0, !pcsections !0 ; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i64, i1 } [[TMP3]], 1, !pcsections !0 -; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP4]] to i8*, !pcsections !0 -; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { i8*, i1 } undef, i8* [[TMP6]], 0, !pcsections !0 -; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { i8*, i1 } [[TMP7]], i1 [[TMP5]], 1, !pcsections !0 +; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP4]] to ptr, !pcsections !0 +; CHECK-NEXT: [[TMP7:%.*]] = insertvalue { ptr, i1 } poison, ptr [[TMP6]], 0, !pcsections !0 +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { ptr, i1 } [[TMP7]], i1 [[TMP5]], 1, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i8** %a, i8* %v1, i8* %v2 seq_cst seq_cst, !pcsections !0 + cmpxchg ptr %a, ptr %v1, ptr %v2 seq_cst seq_cst, !pcsections !0 ret void } -define i128 @atomic128_load_unordered(i128* %a) nounwind uwtable { +define i128 @atomic128_load_unordered(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_load_unordered( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 0 monotonic monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 0 monotonic monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[LOADED:%.*]] = extractvalue { i128, i1 } [[TMP0]], 0, !pcsections !0 ; CHECK-NEXT: ret i128 [[LOADED]] ; entry: - %0 = load atomic i128, i128* %a unordered, align 16, !pcsections !0 + %0 = load atomic i128, ptr %a unordered, align 16, !pcsections !0 ret i128 %0 } -define i128 @atomic128_load_monotonic(i128* %a) nounwind uwtable { +define i128 @atomic128_load_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_load_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 0 monotonic monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 0 monotonic monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[LOADED:%.*]] = extractvalue { i128, i1 } [[TMP0]], 0, !pcsections !0 ; CHECK-NEXT: ret i128 [[LOADED]] ; entry: - %0 = load atomic i128, i128* %a monotonic, align 16, !pcsections !0 + %0 = load atomic i128, ptr %a monotonic, align 16, !pcsections !0 ret i128 %0 } -define i128 @atomic128_load_acquire(i128* %a) nounwind uwtable { +define i128 @atomic128_load_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_load_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 0 acquire acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 0 acquire acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[LOADED:%.*]] = extractvalue { i128, i1 } [[TMP0]], 0, !pcsections !0 ; CHECK-NEXT: ret i128 [[LOADED]] ; entry: - %0 = load atomic i128, i128* %a acquire, align 16, !pcsections !0 + %0 = load atomic i128, ptr %a acquire, align 16, !pcsections !0 ret i128 %0 } -define i128 @atomic128_load_seq_cst(i128* %a) nounwind uwtable { +define i128 @atomic128_load_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_load_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 0 seq_cst seq_cst, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 0 seq_cst seq_cst, align 16, !pcsections !0 ; CHECK-NEXT: [[LOADED:%.*]] = extractvalue { i128, i1 } [[TMP0]], 0, !pcsections !0 ; CHECK-NEXT: ret i128 [[LOADED]] ; entry: - %0 = load atomic i128, i128* %a seq_cst, align 16, !pcsections !0 + %0 = load atomic i128, ptr %a seq_cst, align 16, !pcsections !0 ret i128 %0 } -define void @atomic128_store_unordered(i128* %a) nounwind uwtable { +define void @atomic128_store_unordered(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_store_unordered( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3417,18 +3416,18 @@ ; CHECK-NEXT: ret void ; entry: - store atomic i128 0, i128* %a unordered, align 16, !pcsections !0 + store atomic i128 0, ptr %a unordered, align 16, !pcsections !0 ret void } -define void @atomic128_store_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_store_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_store_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3436,18 +3435,18 @@ ; CHECK-NEXT: ret void ; entry: - store atomic i128 0, i128* %a monotonic, align 16, !pcsections !0 + store atomic i128 0, ptr %a monotonic, align 16, !pcsections !0 ret void } -define void @atomic128_store_release(i128* %a) nounwind uwtable { +define void @atomic128_store_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_store_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 release monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 release monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3455,18 +3454,18 @@ ; CHECK-NEXT: ret void ; entry: - store atomic i128 0, i128* %a release, align 16, !pcsections !0 + store atomic i128 0, ptr %a release, align 16, !pcsections !0 ret void } -define void @atomic128_store_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_store_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_store_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 seq_cst seq_cst, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 seq_cst seq_cst, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3474,18 +3473,18 @@ ; CHECK-NEXT: ret void ; entry: - store atomic i128 0, i128* %a seq_cst, align 16, !pcsections !0 + store atomic i128 0, ptr %a seq_cst, align 16, !pcsections !0 ret void } -define void @atomic128_xchg_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_xchg_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_xchg_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3493,18 +3492,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i128* %a, i128 0 monotonic, !pcsections !0 + atomicrmw xchg ptr %a, i128 0 monotonic, !pcsections !0 ret void } -define void @atomic128_add_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_add_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_add_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3512,18 +3511,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i128* %a, i128 0 monotonic, !pcsections !0 + atomicrmw add ptr %a, i128 0 monotonic, !pcsections !0 ret void } -define void @atomic128_sub_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_sub_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_sub_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3531,18 +3530,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i128* %a, i128 0 monotonic, !pcsections !0 + atomicrmw sub ptr %a, i128 0 monotonic, !pcsections !0 ret void } -define void @atomic128_and_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_and_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_and_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 monotonic monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3550,18 +3549,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i128* %a, i128 0 monotonic, !pcsections !0 + atomicrmw and ptr %a, i128 0 monotonic, !pcsections !0 ret void } -define void @atomic128_or_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_or_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_or_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3569,18 +3568,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i128* %a, i128 0 monotonic, !pcsections !0 + atomicrmw or ptr %a, i128 0 monotonic, !pcsections !0 ret void } -define void @atomic128_xor_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_xor_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_xor_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] monotonic monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3588,18 +3587,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i128* %a, i128 0 monotonic, !pcsections !0 + atomicrmw xor ptr %a, i128 0 monotonic, !pcsections !0 ret void } -define void @atomic128_nand_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_nand_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_nand_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 -1 monotonic monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 -1 monotonic monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3607,18 +3606,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i128* %a, i128 0 monotonic, !pcsections !0 + atomicrmw nand ptr %a, i128 0 monotonic, !pcsections !0 ret void } -define void @atomic128_xchg_acquire(i128* %a) nounwind uwtable { +define void @atomic128_xchg_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_xchg_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 acquire acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 acquire acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3626,18 +3625,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i128* %a, i128 0 acquire, !pcsections !0 + atomicrmw xchg ptr %a, i128 0 acquire, !pcsections !0 ret void } -define void @atomic128_add_acquire(i128* %a) nounwind uwtable { +define void @atomic128_add_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_add_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3645,18 +3644,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i128* %a, i128 0 acquire, !pcsections !0 + atomicrmw add ptr %a, i128 0 acquire, !pcsections !0 ret void } -define void @atomic128_sub_acquire(i128* %a) nounwind uwtable { +define void @atomic128_sub_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_sub_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3664,18 +3663,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i128* %a, i128 0 acquire, !pcsections !0 + atomicrmw sub ptr %a, i128 0 acquire, !pcsections !0 ret void } -define void @atomic128_and_acquire(i128* %a) nounwind uwtable { +define void @atomic128_and_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_and_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 acquire acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 acquire acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3683,18 +3682,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i128* %a, i128 0 acquire, !pcsections !0 + atomicrmw and ptr %a, i128 0 acquire, !pcsections !0 ret void } -define void @atomic128_or_acquire(i128* %a) nounwind uwtable { +define void @atomic128_or_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_or_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3702,18 +3701,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i128* %a, i128 0 acquire, !pcsections !0 + atomicrmw or ptr %a, i128 0 acquire, !pcsections !0 ret void } -define void @atomic128_xor_acquire(i128* %a) nounwind uwtable { +define void @atomic128_xor_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_xor_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acquire acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3721,18 +3720,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i128* %a, i128 0 acquire, !pcsections !0 + atomicrmw xor ptr %a, i128 0 acquire, !pcsections !0 ret void } -define void @atomic128_nand_acquire(i128* %a) nounwind uwtable { +define void @atomic128_nand_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_nand_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 -1 acquire acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 -1 acquire acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3740,18 +3739,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i128* %a, i128 0 acquire, !pcsections !0 + atomicrmw nand ptr %a, i128 0 acquire, !pcsections !0 ret void } -define void @atomic128_xchg_release(i128* %a) nounwind uwtable { +define void @atomic128_xchg_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_xchg_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 release monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 release monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3759,18 +3758,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i128* %a, i128 0 release, !pcsections !0 + atomicrmw xchg ptr %a, i128 0 release, !pcsections !0 ret void } -define void @atomic128_add_release(i128* %a) nounwind uwtable { +define void @atomic128_add_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_add_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3778,18 +3777,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i128* %a, i128 0 release, !pcsections !0 + atomicrmw add ptr %a, i128 0 release, !pcsections !0 ret void } -define void @atomic128_sub_release(i128* %a) nounwind uwtable { +define void @atomic128_sub_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_sub_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3797,18 +3796,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i128* %a, i128 0 release, !pcsections !0 + atomicrmw sub ptr %a, i128 0 release, !pcsections !0 ret void } -define void @atomic128_and_release(i128* %a) nounwind uwtable { +define void @atomic128_and_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_and_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 release monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 release monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3816,18 +3815,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i128* %a, i128 0 release, !pcsections !0 + atomicrmw and ptr %a, i128 0 release, !pcsections !0 ret void } -define void @atomic128_or_release(i128* %a) nounwind uwtable { +define void @atomic128_or_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_or_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3835,18 +3834,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i128* %a, i128 0 release, !pcsections !0 + atomicrmw or ptr %a, i128 0 release, !pcsections !0 ret void } -define void @atomic128_xor_release(i128* %a) nounwind uwtable { +define void @atomic128_xor_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_xor_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] release monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3854,18 +3853,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i128* %a, i128 0 release, !pcsections !0 + atomicrmw xor ptr %a, i128 0 release, !pcsections !0 ret void } -define void @atomic128_nand_release(i128* %a) nounwind uwtable { +define void @atomic128_nand_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_nand_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 -1 release monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 -1 release monotonic, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3873,18 +3872,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i128* %a, i128 0 release, !pcsections !0 + atomicrmw nand ptr %a, i128 0 release, !pcsections !0 ret void } -define void @atomic128_xchg_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_xchg_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_xchg_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 acq_rel acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 acq_rel acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3892,18 +3891,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i128* %a, i128 0 acq_rel, !pcsections !0 + atomicrmw xchg ptr %a, i128 0 acq_rel, !pcsections !0 ret void } -define void @atomic128_add_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_add_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_add_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3911,18 +3910,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i128* %a, i128 0 acq_rel, !pcsections !0 + atomicrmw add ptr %a, i128 0 acq_rel, !pcsections !0 ret void } -define void @atomic128_sub_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_sub_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_sub_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3930,18 +3929,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i128* %a, i128 0 acq_rel, !pcsections !0 + atomicrmw sub ptr %a, i128 0 acq_rel, !pcsections !0 ret void } -define void @atomic128_and_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_and_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_and_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 acq_rel acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 acq_rel acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3949,18 +3948,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i128* %a, i128 0 acq_rel, !pcsections !0 + atomicrmw and ptr %a, i128 0 acq_rel, !pcsections !0 ret void } -define void @atomic128_or_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_or_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_or_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3968,18 +3967,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i128* %a, i128 0 acq_rel, !pcsections !0 + atomicrmw or ptr %a, i128 0 acq_rel, !pcsections !0 ret void } -define void @atomic128_xor_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_xor_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_xor_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] acq_rel acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -3987,18 +3986,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i128* %a, i128 0 acq_rel, !pcsections !0 + atomicrmw xor ptr %a, i128 0 acq_rel, !pcsections !0 ret void } -define void @atomic128_nand_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_nand_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_nand_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 -1 acq_rel acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 -1 acq_rel acquire, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -4006,18 +4005,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i128* %a, i128 0 acq_rel, !pcsections !0 + atomicrmw nand ptr %a, i128 0 acq_rel, !pcsections !0 ret void } -define void @atomic128_xchg_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_xchg_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_xchg_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 seq_cst seq_cst, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 seq_cst seq_cst, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -4025,18 +4024,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xchg i128* %a, i128 0 seq_cst, !pcsections !0 + atomicrmw xchg ptr %a, i128 0 seq_cst, !pcsections !0 ret void } -define void @atomic128_add_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_add_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_add_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -4044,18 +4043,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw add i128* %a, i128 0 seq_cst, !pcsections !0 + atomicrmw add ptr %a, i128 0 seq_cst, !pcsections !0 ret void } -define void @atomic128_sub_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_sub_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_sub_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -4063,18 +4062,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw sub i128* %a, i128 0 seq_cst, !pcsections !0 + atomicrmw sub ptr %a, i128 0 seq_cst, !pcsections !0 ret void } -define void @atomic128_and_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_and_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_and_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 0 seq_cst seq_cst, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 0 seq_cst seq_cst, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -4082,18 +4081,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw and i128* %a, i128 0 seq_cst, !pcsections !0 + atomicrmw and ptr %a, i128 0 seq_cst, !pcsections !0 ret void } -define void @atomic128_or_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_or_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_or_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -4101,18 +4100,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw or i128* %a, i128 0 seq_cst, !pcsections !0 + atomicrmw or ptr %a, i128 0 seq_cst, !pcsections !0 ret void } -define void @atomic128_xor_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_xor_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_xor_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 [[LOADED]] seq_cst seq_cst, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -4120,18 +4119,18 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw xor i128* %a, i128 0 seq_cst, !pcsections !0 + atomicrmw xor ptr %a, i128 0 seq_cst, !pcsections !0 ret void } -define void @atomic128_nand_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_nand_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_nand_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = load i128, i128* [[A:%.*]], align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = load i128, ptr [[A:%.*]], align 16, !pcsections !0 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]], !pcsections !0 ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i128 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ], !pcsections !0 -; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg i128* [[A]], i128 [[LOADED]], i128 -1 seq_cst seq_cst, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP1:%.*]] = cmpxchg ptr [[A]], i128 [[LOADED]], i128 -1 seq_cst seq_cst, align 16, !pcsections !0 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i128, i1 } [[TMP1]], 1, !pcsections !0 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i128, i1 } [[TMP1]], 0, !pcsections !0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]], !pcsections !0 @@ -4139,62 +4138,62 @@ ; CHECK-NEXT: ret void ; entry: - atomicrmw nand i128* %a, i128 0 seq_cst, !pcsections !0 + atomicrmw nand ptr %a, i128 0 seq_cst, !pcsections !0 ret void } -define void @atomic128_cas_monotonic(i128* %a) nounwind uwtable { +define void @atomic128_cas_monotonic(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_cas_monotonic( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 1 monotonic monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 1 monotonic monotonic, align 16, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i128* %a, i128 0, i128 1 monotonic monotonic, !pcsections !0 + cmpxchg ptr %a, i128 0, i128 1 monotonic monotonic, !pcsections !0 ret void } -define void @atomic128_cas_acquire(i128* %a) nounwind uwtable { +define void @atomic128_cas_acquire(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_cas_acquire( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 1 acquire acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 1 acquire acquire, align 16, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i128* %a, i128 0, i128 1 acquire acquire, !pcsections !0 + cmpxchg ptr %a, i128 0, i128 1 acquire acquire, !pcsections !0 ret void } -define void @atomic128_cas_release(i128* %a) nounwind uwtable { +define void @atomic128_cas_release(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_cas_release( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 1 release monotonic, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 1 release monotonic, align 16, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i128* %a, i128 0, i128 1 release monotonic, !pcsections !0 + cmpxchg ptr %a, i128 0, i128 1 release monotonic, !pcsections !0 ret void } -define void @atomic128_cas_acq_rel(i128* %a) nounwind uwtable { +define void @atomic128_cas_acq_rel(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_cas_acq_rel( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 1 acq_rel acquire, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 1 acq_rel acquire, align 16, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i128* %a, i128 0, i128 1 acq_rel acquire, !pcsections !0 + cmpxchg ptr %a, i128 0, i128 1 acq_rel acquire, !pcsections !0 ret void } -define void @atomic128_cas_seq_cst(i128* %a) nounwind uwtable { +define void @atomic128_cas_seq_cst(ptr %a) nounwind uwtable { ; CHECK-LABEL: @atomic128_cas_seq_cst( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg i128* [[A:%.*]], i128 0, i128 1 seq_cst seq_cst, align 16, !pcsections !0 +; CHECK-NEXT: [[TMP0:%.*]] = cmpxchg ptr [[A:%.*]], i128 0, i128 1 seq_cst seq_cst, align 16, !pcsections !0 ; CHECK-NEXT: ret void ; entry: - cmpxchg i128* %a, i128 0, i128 1 seq_cst seq_cst, !pcsections !0 + cmpxchg ptr %a, i128 0, i128 1 seq_cst seq_cst, !pcsections !0 ret void } diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll --- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll @@ -4,25 +4,24 @@ target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" -define i16 @test_atomicrmw_xchg_i16_global(i16 addrspace(1)* %ptr, i16 %value) { +define i16 @test_atomicrmw_xchg_i16_global(ptr addrspace(1) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_xchg_i16_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[VALOPERAND_SHIFTED]] -; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP6]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP6]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -31,21 +30,20 @@ ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; - %res = atomicrmw xchg i16 addrspace(1)* %ptr, i16 %value seq_cst + %res = atomicrmw xchg ptr addrspace(1) %ptr, i16 %value seq_cst ret i16 %res } -define i16 @test_atomicrmw_xchg_i16_global_align4(i16 addrspace(1)* %ptr, i16 %value) { +define i16 @test_atomicrmw_xchg_i16_global_align4(ptr addrspace(1) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_xchg_i16_global_align4( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = bitcast i16 addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[VALUE:%.*]] to i32 -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[LOADED]], -65536 ; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP1]] -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP4]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[TMP4]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -53,23 +51,22 @@ ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[NEWLOADED]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; - %res = atomicrmw xchg i16 addrspace(1)* %ptr, i16 %value seq_cst, align 4 + %res = atomicrmw xchg ptr addrspace(1) %ptr, i16 %value seq_cst, align 4 ret i16 %res } -define i16 @test_atomicrmw_add_i16_global(i16 addrspace(1)* %ptr, i16 %value) { +define i16 @test_atomicrmw_add_i16_global(ptr addrspace(1) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_add_i16_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -77,7 +74,7 @@ ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[NEW]], [[MASK]] ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP5]] -; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -86,15 +83,14 @@ ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; - %res = atomicrmw add i16 addrspace(1)* %ptr, i16 %value seq_cst + %res = atomicrmw add ptr addrspace(1) %ptr, i16 %value seq_cst ret i16 %res } -define i16 @test_atomicrmw_add_i16_global_align4(i16 addrspace(1)* %ptr, i16 %value) { +define i16 @test_atomicrmw_add_i16_global_align4(ptr addrspace(1) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_add_i16_global_align4( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = bitcast i16 addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[VALUE:%.*]] to i32 -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -102,7 +98,7 @@ ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[NEW]], 65535 ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[LOADED]], -65536 ; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], [[TMP3]] -; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP5]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[TMP5]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -110,23 +106,22 @@ ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[NEWLOADED]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; - %res = atomicrmw add i16 addrspace(1)* %ptr, i16 %value seq_cst, align 4 + %res = atomicrmw add ptr addrspace(1) %ptr, i16 %value seq_cst, align 4 ret i16 %res } -define i16 @test_atomicrmw_sub_i16_global(i16 addrspace(1)* %ptr, i16 %value) { +define i16 @test_atomicrmw_sub_i16_global(ptr addrspace(1) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_sub_i16_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -134,7 +129,7 @@ ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[NEW]], [[MASK]] ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP5]] -; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -143,45 +138,43 @@ ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; - %res = atomicrmw sub i16 addrspace(1)* %ptr, i16 %value seq_cst + %res = atomicrmw sub ptr addrspace(1) %ptr, i16 %value seq_cst ret i16 %res } -define i16 @test_atomicrmw_and_i16_global(i16 addrspace(1)* %ptr, i16 %value) { +define i16 @test_atomicrmw_and_i16_global(ptr addrspace(1) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_and_i16_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] ; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]] -; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[ANDOPERAND]] seq_cst, align 4 +; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] seq_cst, align 4 ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; - %res = atomicrmw and i16 addrspace(1)* %ptr, i16 %value seq_cst + %res = atomicrmw and ptr addrspace(1) %ptr, i16 %value seq_cst ret i16 %res } -define i16 @test_atomicrmw_nand_i16_global(i16 addrspace(1)* %ptr, i16 %value) { +define i16 @test_atomicrmw_nand_i16_global(ptr addrspace(1) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_nand_i16_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -190,7 +183,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[NEW]], [[MASK]] ; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP6]] -; CHECK-NEXT: [[TMP9:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP8]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP9:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP8]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP9]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP9]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -199,63 +192,60 @@ ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; - %res = atomicrmw nand i16 addrspace(1)* %ptr, i16 %value seq_cst + %res = atomicrmw nand ptr addrspace(1) %ptr, i16 %value seq_cst ret i16 %res } -define i16 @test_atomicrmw_or_i16_global(i16 addrspace(1)* %ptr, i16 %value) { +define i16 @test_atomicrmw_or_i16_global(ptr addrspace(1) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_or_i16_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw or i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4 +; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw or ptr addrspace(1) [[ALIGNEDADDR]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4 ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; - %res = atomicrmw or i16 addrspace(1)* %ptr, i16 %value seq_cst + %res = atomicrmw or ptr addrspace(1) %ptr, i16 %value seq_cst ret i16 %res } -define i16 @test_atomicrmw_xor_i16_global(i16 addrspace(1)* %ptr, i16 %value) { +define i16 @test_atomicrmw_xor_i16_global(ptr addrspace(1) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_xor_i16_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw xor i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4 +; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw xor ptr addrspace(1) [[ALIGNEDADDR]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4 ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; - %res = atomicrmw xor i16 addrspace(1)* %ptr, i16 %value seq_cst + %res = atomicrmw xor ptr addrspace(1) %ptr, i16 %value seq_cst ret i16 %res } -define i16 @test_atomicrmw_max_i16_global(i16 addrspace(1)* %ptr, i16 %value) { +define i16 @test_atomicrmw_max_i16_global(ptr addrspace(1) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_max_i16_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -267,7 +257,7 @@ ; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -276,21 +266,20 @@ ; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED4]] ; - %res = atomicrmw max i16 addrspace(1)* %ptr, i16 %value seq_cst + %res = atomicrmw max ptr addrspace(1) %ptr, i16 %value seq_cst ret i16 %res } -define i16 @test_atomicrmw_min_i16_global(i16 addrspace(1)* %ptr, i16 %value) { +define i16 @test_atomicrmw_min_i16_global(ptr addrspace(1) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_min_i16_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -302,7 +291,7 @@ ; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -311,21 +300,20 @@ ; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED4]] ; - %res = atomicrmw min i16 addrspace(1)* %ptr, i16 %value seq_cst + %res = atomicrmw min ptr addrspace(1) %ptr, i16 %value seq_cst ret i16 %res } -define i16 @test_atomicrmw_umax_i16_global(i16 addrspace(1)* %ptr, i16 %value) { +define i16 @test_atomicrmw_umax_i16_global(ptr addrspace(1) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_umax_i16_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -337,7 +325,7 @@ ; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -346,21 +334,20 @@ ; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED4]] ; - %res = atomicrmw umax i16 addrspace(1)* %ptr, i16 %value seq_cst + %res = atomicrmw umax ptr addrspace(1) %ptr, i16 %value seq_cst ret i16 %res } -define i16 @test_atomicrmw_umin_i16_global(i16 addrspace(1)* %ptr, i16 %value) { +define i16 @test_atomicrmw_umin_i16_global(ptr addrspace(1) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_umin_i16_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -372,7 +359,7 @@ ; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -381,33 +368,32 @@ ; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED4]] ; - %res = atomicrmw umin i16 addrspace(1)* %ptr, i16 %value seq_cst + %res = atomicrmw umin ptr addrspace(1) %ptr, i16 %value seq_cst ret i16 %res } -define i16 @test_cmpxchg_i16_global(i16 addrspace(1)* %out, i16 %in, i16 %old) { +define i16 @test_cmpxchg_i16_global(ptr addrspace(1) %out, i16 %in, i16 %old) { ; CHECK-LABEL: @test_cmpxchg_i16_global( -; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, i16 addrspace(1)* [[OUT:%.*]], i64 4 -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(1)* @llvm.ptrmask.p1i16.i64(i16 addrspace(1)* [[GEP]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(1)* [[GEP]] to i64 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, ptr addrspace(1) [[OUT:%.*]], i64 4 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[GEP]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[GEP]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[IN:%.*]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] ; CHECK-NEXT: [[TMP5:%.*]] = zext i16 [[OLD:%.*]] to i32 ; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP5]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], [[INV_MASK]] ; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]] ; CHECK: partword.cmpxchg.loop: ; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[TMP0:%.*]] ], [ [[TMP15:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ] ; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP4]] ; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP6]] -; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { i32, i1 } [[TMP12]], 0 ; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP12]], 1 ; CHECK-NEXT: br i1 [[TMP14]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]] @@ -418,31 +404,30 @@ ; CHECK: partword.cmpxchg.end: ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP13]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 -; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i16, i1 } undef, i16 [[EXTRACTED]], 0 +; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i16, i1 } poison, i16 [[EXTRACTED]], 0 ; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { i16, i1 } [[TMP17]], i1 [[TMP14]], 1 ; CHECK-NEXT: [[EXTRACT:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0 ; CHECK-NEXT: ret i16 [[EXTRACT]] ; - %gep = getelementptr i16, i16 addrspace(1)* %out, i64 4 - %res = cmpxchg i16 addrspace(1)* %gep, i16 %old, i16 %in seq_cst seq_cst + %gep = getelementptr i16, ptr addrspace(1) %out, i64 4 + %res = cmpxchg ptr addrspace(1) %gep, i16 %old, i16 %in seq_cst seq_cst %extract = extractvalue {i16, i1} %res, 0 ret i16 %extract } -define i16 @test_cmpxchg_i16_global_align4(i16 addrspace(1)* %out, i16 %in, i16 %old) { +define i16 @test_cmpxchg_i16_global_align4(ptr addrspace(1) %out, i16 %in, i16 %old) { ; CHECK-LABEL: @test_cmpxchg_i16_global_align4( -; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, i16 addrspace(1)* [[OUT:%.*]], i64 4 -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = bitcast i16 addrspace(1)* [[GEP]] to i32 addrspace(1)* +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, ptr addrspace(1) [[OUT:%.*]], i64 4 ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[IN:%.*]] to i32 ; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[OLD:%.*]] to i32 -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4 ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], -65536 ; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]] ; CHECK: partword.cmpxchg.loop: ; CHECK-NEXT: [[TMP5:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[TMP11:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ] ; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[TMP1]] ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP5]], [[TMP2]] -; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[TMP7]], i32 [[TMP6]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[GEP]], i32 [[TMP7]], i32 [[TMP6]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[TMP9:%.*]] = extractvalue { i32, i1 } [[TMP8]], 0 ; CHECK-NEXT: [[TMP10:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1 ; CHECK-NEXT: br i1 [[TMP10]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]] @@ -452,35 +437,34 @@ ; CHECK-NEXT: br i1 [[TMP12]], label [[PARTWORD_CMPXCHG_LOOP]], label [[PARTWORD_CMPXCHG_END]] ; CHECK: partword.cmpxchg.end: ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[TMP9]] to i16 -; CHECK-NEXT: [[TMP13:%.*]] = insertvalue { i16, i1 } undef, i16 [[EXTRACTED]], 0 +; CHECK-NEXT: [[TMP13:%.*]] = insertvalue { i16, i1 } poison, i16 [[EXTRACTED]], 0 ; CHECK-NEXT: [[TMP14:%.*]] = insertvalue { i16, i1 } [[TMP13]], i1 [[TMP10]], 1 ; CHECK-NEXT: [[EXTRACT:%.*]] = extractvalue { i16, i1 } [[TMP14]], 0 ; CHECK-NEXT: ret i16 [[EXTRACT]] ; - %gep = getelementptr i16, i16 addrspace(1)* %out, i64 4 - %res = cmpxchg i16 addrspace(1)* %gep, i16 %old, i16 %in seq_cst seq_cst, align 4 + %gep = getelementptr i16, ptr addrspace(1) %out, i64 4 + %res = cmpxchg ptr addrspace(1) %gep, i16 %old, i16 %in seq_cst seq_cst, align 4 %extract = extractvalue {i16, i1} %res, 0 ret i16 %extract } -define i16 @test_atomicrmw_xchg_i16_local(i16 addrspace(3)* %ptr, i16 %value) { +define i16 @test_atomicrmw_xchg_i16_local(ptr addrspace(3) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_xchg_i16_local( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(3)* @llvm.ptrmask.p3i16.i32(i16 addrspace(3)* [[PTR:%.*]], i32 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(3)* [[PTR]] to i32 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i32(ptr addrspace(3) [[PTR:%.*]], i32 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i32 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i32 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[PTRLSB]], 3 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[TMP2]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[TMP2]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[VALOPERAND_SHIFTED]] -; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP6]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP6]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -489,32 +473,31 @@ ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; - %res = atomicrmw xchg i16 addrspace(3)* %ptr, i16 %value seq_cst + %res = atomicrmw xchg ptr addrspace(3) %ptr, i16 %value seq_cst ret i16 %res } -define i16 @test_cmpxchg_i16_local(i16 addrspace(3)* %out, i16 %in, i16 %old) { +define i16 @test_cmpxchg_i16_local(ptr addrspace(3) %out, i16 %in, i16 %old) { ; CHECK-LABEL: @test_cmpxchg_i16_local( -; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, i16 addrspace(3)* [[OUT:%.*]], i64 4 -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16 addrspace(3)* @llvm.ptrmask.p3i16.i32(i16 addrspace(3)* [[GEP]], i32 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i16 addrspace(3)* [[GEP]] to i32 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, ptr addrspace(3) [[OUT:%.*]], i64 4 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i32(ptr addrspace(3) [[GEP]], i32 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[GEP]] to i32 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i32 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[PTRLSB]], 3 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[TMP2]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16 addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[IN:%.*]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[TMP3]], [[TMP2]] ; CHECK-NEXT: [[TMP5:%.*]] = zext i16 [[OLD:%.*]] to i32 ; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP5]], [[TMP2]] -; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], [[INV_MASK]] ; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]] ; CHECK: partword.cmpxchg.loop: ; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[TMP0:%.*]] ], [ [[TMP15:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ] ; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP4]] ; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP6]] -; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { i32, i1 } [[TMP12]], 0 ; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP12]], 1 ; CHECK-NEXT: br i1 [[TMP14]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]] @@ -525,25 +508,24 @@ ; CHECK: partword.cmpxchg.end: ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP13]], [[TMP2]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 -; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i16, i1 } undef, i16 [[EXTRACTED]], 0 +; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i16, i1 } poison, i16 [[EXTRACTED]], 0 ; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { i16, i1 } [[TMP17]], i1 [[TMP14]], 1 ; CHECK-NEXT: [[EXTRACT:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0 ; CHECK-NEXT: ret i16 [[EXTRACT]] ; - %gep = getelementptr i16, i16 addrspace(3)* %out, i64 4 - %res = cmpxchg i16 addrspace(3)* %gep, i16 %old, i16 %in seq_cst seq_cst + %gep = getelementptr i16, ptr addrspace(3) %out, i64 4 + %res = cmpxchg ptr addrspace(3) %gep, i16 %old, i16 %in seq_cst seq_cst %extract = extractvalue {i16, i1} %res, 0 ret i16 %extract } -define i16 @test_atomicrmw_xor_i16_local_align4(i16 addrspace(3)* %ptr, i16 %value) { +define i16 @test_atomicrmw_xor_i16_local_align4(ptr addrspace(3) %ptr, i16 %value) { ; CHECK-LABEL: @test_atomicrmw_xor_i16_local_align4( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = bitcast i16 addrspace(3)* [[PTR:%.*]] to i32 addrspace(3)* ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[VALUE:%.*]] to i32 -; CHECK-NEXT: [[TMP2:%.*]] = atomicrmw xor i32 addrspace(3)* [[ALIGNEDADDR]], i32 [[TMP1]] seq_cst, align 4 +; CHECK-NEXT: [[TMP2:%.*]] = atomicrmw xor ptr addrspace(3) [[PTR:%.*]], i32 [[TMP1]] seq_cst, align 4 ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[TMP2]] to i16 ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; - %res = atomicrmw xor i16 addrspace(3)* %ptr, i16 %value seq_cst, align 4 + %res = atomicrmw xor ptr addrspace(3) %ptr, i16 %value seq_cst, align 4 ret i16 %res } diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll --- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i8.ll @@ -2,25 +2,24 @@ ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -atomic-expand %s | FileCheck %s ; RUN: opt -mtriple=r600-mesa-mesa3d -S -atomic-expand %s | FileCheck %s -define i8 @test_atomicrmw_xchg_i8_global(i8 addrspace(1)* %ptr, i8 %value) { +define i8 @test_atomicrmw_xchg_i8_global(ptr addrspace(1) %ptr, i8 %value) { ; CHECK-LABEL: @test_atomicrmw_xchg_i8_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[VALOPERAND_SHIFTED]] -; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP6]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP6]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -29,23 +28,22 @@ ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8 ; CHECK-NEXT: ret i8 [[EXTRACTED]] ; - %res = atomicrmw xchg i8 addrspace(1)* %ptr, i8 %value seq_cst + %res = atomicrmw xchg ptr addrspace(1) %ptr, i8 %value seq_cst ret i8 %res } -define i8 @test_atomicrmw_add_i8_global(i8 addrspace(1)* %ptr, i8 %value) { +define i8 @test_atomicrmw_add_i8_global(ptr addrspace(1) %ptr, i8 %value) { ; CHECK-LABEL: @test_atomicrmw_add_i8_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -53,7 +51,7 @@ ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[NEW]], [[MASK]] ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP5]] -; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -62,23 +60,22 @@ ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8 ; CHECK-NEXT: ret i8 [[EXTRACTED]] ; - %res = atomicrmw add i8 addrspace(1)* %ptr, i8 %value seq_cst + %res = atomicrmw add ptr addrspace(1) %ptr, i8 %value seq_cst ret i8 %res } -define i8 @test_atomicrmw_add_i8_global_align2(i8 addrspace(1)* %ptr, i8 %value) { +define i8 @test_atomicrmw_add_i8_global_align2(ptr addrspace(1) %ptr, i8 %value) { ; CHECK-LABEL: @test_atomicrmw_add_i8_global_align2( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -86,7 +83,7 @@ ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[NEW]], [[MASK]] ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP5]] -; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -95,15 +92,14 @@ ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8 ; CHECK-NEXT: ret i8 [[EXTRACTED]] ; - %res = atomicrmw add i8 addrspace(1)* %ptr, i8 %value seq_cst, align 2 + %res = atomicrmw add ptr addrspace(1) %ptr, i8 %value seq_cst, align 2 ret i8 %res } -define i8 @test_atomicrmw_add_i8_global_align4(i8 addrspace(1)* %ptr, i8 %value) { +define i8 @test_atomicrmw_add_i8_global_align4(ptr addrspace(1) %ptr, i8 %value) { ; CHECK-LABEL: @test_atomicrmw_add_i8_global_align4( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = bitcast i8 addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[VALUE:%.*]] to i32 -; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -111,7 +107,7 @@ ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[NEW]], 255 ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[LOADED]], -256 ; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], [[TMP3]] -; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP5]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[TMP5]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -119,23 +115,22 @@ ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[NEWLOADED]] to i8 ; CHECK-NEXT: ret i8 [[EXTRACTED]] ; - %res = atomicrmw add i8 addrspace(1)* %ptr, i8 %value seq_cst, align 4 + %res = atomicrmw add ptr addrspace(1) %ptr, i8 %value seq_cst, align 4 ret i8 %res } -define i8 @test_atomicrmw_sub_i8_global(i8 addrspace(1)* %ptr, i8 %value) { +define i8 @test_atomicrmw_sub_i8_global(ptr addrspace(1) %ptr, i8 %value) { ; CHECK-LABEL: @test_atomicrmw_sub_i8_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -143,7 +138,7 @@ ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[NEW]], [[MASK]] ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP5]] -; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -152,45 +147,43 @@ ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8 ; CHECK-NEXT: ret i8 [[EXTRACTED]] ; - %res = atomicrmw sub i8 addrspace(1)* %ptr, i8 %value seq_cst + %res = atomicrmw sub ptr addrspace(1) %ptr, i8 %value seq_cst ret i8 %res } -define i8 @test_atomicrmw_and_i8_global(i8 addrspace(1)* %ptr, i8 %value) { +define i8 @test_atomicrmw_and_i8_global(ptr addrspace(1) %ptr, i8 %value) { ; CHECK-LABEL: @test_atomicrmw_and_i8_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] ; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]] -; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[ANDOPERAND]] seq_cst, align 4 +; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw and ptr addrspace(1) [[ALIGNEDADDR]], i32 [[ANDOPERAND]] seq_cst, align 4 ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8 ; CHECK-NEXT: ret i8 [[EXTRACTED]] ; - %res = atomicrmw and i8 addrspace(1)* %ptr, i8 %value seq_cst + %res = atomicrmw and ptr addrspace(1) %ptr, i8 %value seq_cst ret i8 %res } -define i8 @test_atomicrmw_nand_i8_global(i8 addrspace(1)* %ptr, i8 %value) { +define i8 @test_atomicrmw_nand_i8_global(ptr addrspace(1) %ptr, i8 %value) { ; CHECK-LABEL: @test_atomicrmw_nand_i8_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -199,7 +192,7 @@ ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[NEW]], [[MASK]] ; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP6]] -; CHECK-NEXT: [[TMP9:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP8]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP9:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP8]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP9]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP9]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -208,63 +201,60 @@ ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8 ; CHECK-NEXT: ret i8 [[EXTRACTED]] ; - %res = atomicrmw nand i8 addrspace(1)* %ptr, i8 %value seq_cst + %res = atomicrmw nand ptr addrspace(1) %ptr, i8 %value seq_cst ret i8 %res } -define i8 @test_atomicrmw_or_i8_global(i8 addrspace(1)* %ptr, i8 %value) { +define i8 @test_atomicrmw_or_i8_global(ptr addrspace(1) %ptr, i8 %value) { ; CHECK-LABEL: @test_atomicrmw_or_i8_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw or i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4 +; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw or ptr addrspace(1) [[ALIGNEDADDR]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4 ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8 ; CHECK-NEXT: ret i8 [[EXTRACTED]] ; - %res = atomicrmw or i8 addrspace(1)* %ptr, i8 %value seq_cst + %res = atomicrmw or ptr addrspace(1) %ptr, i8 %value seq_cst ret i8 %res } -define i8 @test_atomicrmw_xor_i8_global(i8 addrspace(1)* %ptr, i8 %value) { +define i8 @test_atomicrmw_xor_i8_global(ptr addrspace(1) %ptr, i8 %value) { ; CHECK-LABEL: @test_atomicrmw_xor_i8_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[VALUE:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw xor i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4 +; CHECK-NEXT: [[TMP4:%.*]] = atomicrmw xor ptr addrspace(1) [[ALIGNEDADDR]], i32 [[VALOPERAND_SHIFTED]] seq_cst, align 4 ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP4]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8 ; CHECK-NEXT: ret i8 [[EXTRACTED]] ; - %res = atomicrmw xor i8 addrspace(1)* %ptr, i8 %value seq_cst + %res = atomicrmw xor ptr addrspace(1) %ptr, i8 %value seq_cst ret i8 %res } -define i8 @test_atomicrmw_max_i8_global(i8 addrspace(1)* %ptr, i8 %value) { +define i8 @test_atomicrmw_max_i8_global(ptr addrspace(1) %ptr, i8 %value) { ; CHECK-LABEL: @test_atomicrmw_max_i8_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -276,7 +266,7 @@ ; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -285,21 +275,20 @@ ; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i8 ; CHECK-NEXT: ret i8 [[EXTRACTED4]] ; - %res = atomicrmw max i8 addrspace(1)* %ptr, i8 %value seq_cst + %res = atomicrmw max ptr addrspace(1) %ptr, i8 %value seq_cst ret i8 %res } -define i8 @test_atomicrmw_min_i8_global(i8 addrspace(1)* %ptr, i8 %value) { +define i8 @test_atomicrmw_min_i8_global(ptr addrspace(1) %ptr, i8 %value) { ; CHECK-LABEL: @test_atomicrmw_min_i8_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -311,7 +300,7 @@ ; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -320,21 +309,20 @@ ; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i8 ; CHECK-NEXT: ret i8 [[EXTRACTED4]] ; - %res = atomicrmw min i8 addrspace(1)* %ptr, i8 %value seq_cst + %res = atomicrmw min ptr addrspace(1) %ptr, i8 %value seq_cst ret i8 %res } -define i8 @test_atomicrmw_umax_i8_global(i8 addrspace(1)* %ptr, i8 %value) { +define i8 @test_atomicrmw_umax_i8_global(ptr addrspace(1) %ptr, i8 %value) { ; CHECK-LABEL: @test_atomicrmw_umax_i8_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -346,7 +334,7 @@ ; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -355,21 +343,20 @@ ; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i8 ; CHECK-NEXT: ret i8 [[EXTRACTED4]] ; - %res = atomicrmw umax i8 addrspace(1)* %ptr, i8 %value seq_cst + %res = atomicrmw umax ptr addrspace(1) %ptr, i8 %value seq_cst ret i8 %res } -define i8 @test_atomicrmw_umin_i8_global(i8 addrspace(1)* %ptr, i8 %value) { +define i8 @test_atomicrmw_umin_i8_global(ptr addrspace(1) %ptr, i8 %value) { ; CHECK-LABEL: @test_atomicrmw_umin_i8_global( -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -381,7 +368,7 @@ ; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -390,33 +377,32 @@ ; CHECK-NEXT: [[EXTRACTED4:%.*]] = trunc i32 [[SHIFTED3]] to i8 ; CHECK-NEXT: ret i8 [[EXTRACTED4]] ; - %res = atomicrmw umin i8 addrspace(1)* %ptr, i8 %value seq_cst + %res = atomicrmw umin ptr addrspace(1) %ptr, i8 %value seq_cst ret i8 %res } -define i8 @test_cmpxchg_i8_global(i8 addrspace(1)* %out, i8 %in, i8 %old) { +define i8 @test_cmpxchg_i8_global(ptr addrspace(1) %out, i8 %in, i8 %old) { ; CHECK-LABEL: @test_cmpxchg_i8_global( -; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, i8 addrspace(1)* [[OUT:%.*]], i64 4 -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(1)* @llvm.ptrmask.p1i8.i64(i8 addrspace(1)* [[GEP]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(1)* [[GEP]] to i64 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr addrspace(1) [[OUT:%.*]], i64 4 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[GEP]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[GEP]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[IN:%.*]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] ; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[OLD:%.*]] to i32 ; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP5]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], [[INV_MASK]] ; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]] ; CHECK: partword.cmpxchg.loop: ; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[TMP0:%.*]] ], [ [[TMP15:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ] ; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP4]] ; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP6]] -; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { i32, i1 } [[TMP12]], 0 ; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP12]], 1 ; CHECK-NEXT: br i1 [[TMP14]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]] @@ -427,40 +413,39 @@ ; CHECK: partword.cmpxchg.end: ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP13]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8 -; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i8, i1 } undef, i8 [[EXTRACTED]], 0 +; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i8, i1 } poison, i8 [[EXTRACTED]], 0 ; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { i8, i1 } [[TMP17]], i1 [[TMP14]], 1 ; CHECK-NEXT: [[EXTRACT:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0 ; CHECK-NEXT: ret i8 [[EXTRACT]] ; - %gep = getelementptr i8, i8 addrspace(1)* %out, i64 4 - %res = cmpxchg i8 addrspace(1)* %gep, i8 %old, i8 %in seq_cst seq_cst + %gep = getelementptr i8, ptr addrspace(1) %out, i64 4 + %res = cmpxchg ptr addrspace(1) %gep, i8 %old, i8 %in seq_cst seq_cst %extract = extractvalue {i8, i1} %res, 0 ret i8 %extract } -define i8 @test_cmpxchg_i8_local_align2(i8 addrspace(3)* %out, i8 %in, i8 %old) { +define i8 @test_cmpxchg_i8_local_align2(ptr addrspace(3) %out, i8 %in, i8 %old) { ; CHECK-LABEL: @test_cmpxchg_i8_local_align2( -; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, i8 addrspace(3)* [[OUT:%.*]], i64 4 -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8 addrspace(3)* @llvm.ptrmask.p3i8.i64(i8 addrspace(3)* [[GEP]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint i8 addrspace(3)* [[GEP]] to i64 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr addrspace(3) [[OUT:%.*]], i64 4 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[GEP]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[GEP]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8 addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)* ; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[IN:%.*]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] ; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[OLD:%.*]] to i32 ; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP5]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], [[INV_MASK]] ; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]] ; CHECK: partword.cmpxchg.loop: ; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[TMP0:%.*]] ], [ [[TMP15:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ] ; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP4]] ; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP6]] -; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[TMP11]], i32 [[TMP10]] seq_cst seq_cst, align 4 ; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { i32, i1 } [[TMP12]], 0 ; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP12]], 1 ; CHECK-NEXT: br i1 [[TMP14]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]] @@ -471,13 +456,13 @@ ; CHECK: partword.cmpxchg.end: ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP13]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8 -; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i8, i1 } undef, i8 [[EXTRACTED]], 0 +; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i8, i1 } poison, i8 [[EXTRACTED]], 0 ; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { i8, i1 } [[TMP17]], i1 [[TMP14]], 1 ; CHECK-NEXT: [[EXTRACT:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0 ; CHECK-NEXT: ret i8 [[EXTRACT]] ; - %gep = getelementptr i8, i8 addrspace(3)* %out, i64 4 - %res = cmpxchg i8 addrspace(3)* %gep, i8 %old, i8 %in seq_cst seq_cst, align 2 + %gep = getelementptr i8, ptr addrspace(3) %out, i64 4 + %res = cmpxchg ptr addrspace(3) %gep, i8 %old, i8 %in seq_cst seq_cst, align 2 %extract = extractvalue {i8, i1} %res, 0 ret i8 %extract } diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization.ll --- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization.ll +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd-flat-specialization.ll @@ -4,17 +4,16 @@ ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 -atomic-expand %s | FileCheck -check-prefix=GFX940 %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -atomic-expand %s | FileCheck -check-prefix=GFX1100 %s -define float @syncscope_system(float* %addr, float %val) #0 { +define float @syncscope_system(ptr %addr, float %val) #0 { ; GFX908-LABEL: @syncscope_system( -; GFX908-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4 +; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -23,15 +22,14 @@ ; GFX908-NEXT: ret float [[TMP6]] ; ; GFX90A-LABEL: @syncscope_system( -; GFX90A-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4 +; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]] -; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32* ; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -40,15 +38,14 @@ ; GFX90A-NEXT: ret float [[TMP6]] ; ; GFX940-LABEL: @syncscope_system( -; GFX940-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4 +; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]] -; GFX940-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32* ; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -57,15 +54,14 @@ ; GFX940-NEXT: ret float [[TMP6]] ; ; GFX1100-LABEL: @syncscope_system( -; GFX1100-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4 +; GFX1100-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4 ; GFX1100-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX1100: atomicrmw.start: ; GFX1100-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX1100-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]] -; GFX1100-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32* ; GFX1100-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX1100-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX1100-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX1100-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX1100-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX1100-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX1100-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -74,36 +70,34 @@ ; GFX1100-NEXT: ret float [[TMP6]] ; ; GFX11-LABEL: @syncscope_system( -; GFX11-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4 +; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float ; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret float [[TMP6]] - %res = atomicrmw fadd float* %addr, float %val seq_cst + %res = atomicrmw fadd ptr %addr, float %val seq_cst ret float %res } -define float @syncscope_workgroup_rtn(float* %addr, float %val) #0 { +define float @syncscope_workgroup_rtn(ptr %addr, float %val) #0 { ; GFX908-LABEL: @syncscope_workgroup_rtn( -; GFX908-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4 +; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -112,27 +106,26 @@ ; GFX908-NEXT: ret float [[TMP6]] ; ; GFX90A-LABEL: @syncscope_workgroup_rtn( -; GFX90A-NEXT: [[TMP1:%.*]] = bitcast float* [[ADDR:%.*]] to i8* ; GFX90A-NEXT: br label [[ATOMICRMW_CHECK_SHARED:%.*]] ; GFX90A: atomicrmw.check.shared: -; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(i8* [[TMP1]]) +; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[ADDR:%.*]]) ; GFX90A-NEXT: br i1 [[IS_SHARED]], label [[ATOMICRMW_SHARED:%.*]], label [[ATOMICRMW_CHECK_PRIVATE:%.*]] ; GFX90A: atomicrmw.shared: -; GFX90A-NEXT: [[TMP2:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(3)* -; GFX90A-NEXT: [[TMP3:%.*]] = atomicrmw fadd float addrspace(3)* [[TMP2]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 +; GFX90A-NEXT: [[TMP2:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(3) +; GFX90A-NEXT: [[TMP3:%.*]] = atomicrmw fadd ptr addrspace(3) [[TMP2]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_PHI:%.*]] ; GFX90A: atomicrmw.check.private: -; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(i8* [[TMP1]]) +; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[ADDR]]) ; GFX90A-NEXT: br i1 [[IS_PRIVATE]], label [[ATOMICRMW_PRIVATE:%.*]], label [[ATOMICRMW_GLOBAL:%.*]] ; GFX90A: atomicrmw.private: -; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(5)* -; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, float addrspace(5)* [[TMP4]], align 4 +; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(5) +; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, ptr addrspace(5) [[TMP4]], align 4 ; GFX90A-NEXT: [[VAL_NEW:%.*]] = fadd float [[LOADED_PRIVATE]], [[VAL]] -; GFX90A-NEXT: store float [[VAL_NEW]], float addrspace(5)* [[TMP4]], align 4 +; GFX90A-NEXT: store float [[VAL_NEW]], ptr addrspace(5) [[TMP4]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_PHI]] ; GFX90A: atomicrmw.global: -; GFX90A-NEXT: [[TMP5:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(1)* -; GFX90A-NEXT: [[TMP6:%.*]] = atomicrmw fadd float addrspace(1)* [[TMP5]], float [[VAL]] syncscope("workgroup") seq_cst, align 4 +; GFX90A-NEXT: [[TMP5:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(1) +; GFX90A-NEXT: [[TMP6:%.*]] = atomicrmw fadd ptr addrspace(1) [[TMP5]], float [[VAL]] syncscope("workgroup") seq_cst, align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_PHI]] ; GFX90A: atomicrmw.phi: ; GFX90A-NEXT: [[LOADED_PHI:%.*]] = phi float [ [[TMP3]], [[ATOMICRMW_SHARED]] ], [ [[LOADED_PRIVATE]], [[ATOMICRMW_PRIVATE]] ], [ [[TMP6]], [[ATOMICRMW_GLOBAL]] ] @@ -141,56 +134,54 @@ ; GFX90A-NEXT: ret float [[LOADED_PHI]] ; ; GFX940-LABEL: @syncscope_workgroup_rtn( -; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd float* [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 +; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 ; GFX940-NEXT: ret float [[RES]] ; ; GFX1100-LABEL: @syncscope_workgroup_rtn( -; GFX1100-NEXT: [[RES:%.*]] = atomicrmw fadd float* [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 +; GFX1100-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 ; GFX1100-NEXT: ret float [[RES]] ; ; GFX11-LABEL: @syncscope_workgroup_rtn( -; GFX11-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4 +; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float ; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret float [[TMP6]] - %res = atomicrmw fadd float* %addr, float %val syncscope("workgroup") seq_cst + %res = atomicrmw fadd ptr %addr, float %val syncscope("workgroup") seq_cst ret float %res } -define void @syncscope_workgroup_nortn(float* %addr, float %val) #0 { +define void @syncscope_workgroup_nortn(ptr %addr, float %val) #0 { ; GFX908-LABEL: @syncscope_workgroup_nortn( -; GFX908-NEXT: [[TMP1:%.*]] = bitcast float* [[ADDR:%.*]] to i8* ; GFX908-NEXT: br label [[ATOMICRMW_CHECK_SHARED:%.*]] ; GFX908: atomicrmw.check.shared: -; GFX908-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(i8* [[TMP1]]) +; GFX908-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[ADDR:%.*]]) ; GFX908-NEXT: br i1 [[IS_SHARED]], label [[ATOMICRMW_SHARED:%.*]], label [[ATOMICRMW_CHECK_PRIVATE:%.*]] ; GFX908: atomicrmw.shared: -; GFX908-NEXT: [[TMP2:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(3)* -; GFX908-NEXT: [[TMP3:%.*]] = atomicrmw fadd float addrspace(3)* [[TMP2]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 +; GFX908-NEXT: [[TMP2:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(3) +; GFX908-NEXT: [[TMP3:%.*]] = atomicrmw fadd ptr addrspace(3) [[TMP2]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 ; GFX908-NEXT: br label [[ATOMICRMW_PHI:%.*]] ; GFX908: atomicrmw.check.private: -; GFX908-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(i8* [[TMP1]]) +; GFX908-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[ADDR]]) ; GFX908-NEXT: br i1 [[IS_PRIVATE]], label [[ATOMICRMW_PRIVATE:%.*]], label [[ATOMICRMW_GLOBAL:%.*]] ; GFX908: atomicrmw.private: -; GFX908-NEXT: [[TMP4:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(5)* -; GFX908-NEXT: [[LOADED_PRIVATE:%.*]] = load float, float addrspace(5)* [[TMP4]], align 4 +; GFX908-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(5) +; GFX908-NEXT: [[LOADED_PRIVATE:%.*]] = load float, ptr addrspace(5) [[TMP4]], align 4 ; GFX908-NEXT: [[VAL_NEW:%.*]] = fadd float [[LOADED_PRIVATE]], [[VAL]] -; GFX908-NEXT: store float [[VAL_NEW]], float addrspace(5)* [[TMP4]], align 4 +; GFX908-NEXT: store float [[VAL_NEW]], ptr addrspace(5) [[TMP4]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_PHI]] ; GFX908: atomicrmw.global: -; GFX908-NEXT: [[TMP5:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(1)* -; GFX908-NEXT: [[TMP6:%.*]] = atomicrmw fadd float addrspace(1)* [[TMP5]], float [[VAL]] syncscope("workgroup") seq_cst, align 4 +; GFX908-NEXT: [[TMP5:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(1) +; GFX908-NEXT: [[TMP6:%.*]] = atomicrmw fadd ptr addrspace(1) [[TMP5]], float [[VAL]] syncscope("workgroup") seq_cst, align 4 ; GFX908-NEXT: br label [[ATOMICRMW_PHI]] ; GFX908: atomicrmw.phi: ; GFX908-NEXT: [[LOADED_PHI:%.*]] = phi float [ [[TMP3]], [[ATOMICRMW_SHARED]] ], [ [[LOADED_PRIVATE]], [[ATOMICRMW_PRIVATE]] ], [ [[TMP6]], [[ATOMICRMW_GLOBAL]] ] @@ -199,27 +190,26 @@ ; GFX908-NEXT: ret void ; ; GFX90A-LABEL: @syncscope_workgroup_nortn( -; GFX90A-NEXT: [[TMP1:%.*]] = bitcast float* [[ADDR:%.*]] to i8* ; GFX90A-NEXT: br label [[ATOMICRMW_CHECK_SHARED:%.*]] ; GFX90A: atomicrmw.check.shared: -; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(i8* [[TMP1]]) +; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[ADDR:%.*]]) ; GFX90A-NEXT: br i1 [[IS_SHARED]], label [[ATOMICRMW_SHARED:%.*]], label [[ATOMICRMW_CHECK_PRIVATE:%.*]] ; GFX90A: atomicrmw.shared: -; GFX90A-NEXT: [[TMP2:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(3)* -; GFX90A-NEXT: [[TMP3:%.*]] = atomicrmw fadd float addrspace(3)* [[TMP2]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 +; GFX90A-NEXT: [[TMP2:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(3) +; GFX90A-NEXT: [[TMP3:%.*]] = atomicrmw fadd ptr addrspace(3) [[TMP2]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_PHI:%.*]] ; GFX90A: atomicrmw.check.private: -; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(i8* [[TMP1]]) +; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[ADDR]]) ; GFX90A-NEXT: br i1 [[IS_PRIVATE]], label [[ATOMICRMW_PRIVATE:%.*]], label [[ATOMICRMW_GLOBAL:%.*]] ; GFX90A: atomicrmw.private: -; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(5)* -; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, float addrspace(5)* [[TMP4]], align 4 +; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(5) +; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, ptr addrspace(5) [[TMP4]], align 4 ; GFX90A-NEXT: [[VAL_NEW:%.*]] = fadd float [[LOADED_PRIVATE]], [[VAL]] -; GFX90A-NEXT: store float [[VAL_NEW]], float addrspace(5)* [[TMP4]], align 4 +; GFX90A-NEXT: store float [[VAL_NEW]], ptr addrspace(5) [[TMP4]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_PHI]] ; GFX90A: atomicrmw.global: -; GFX90A-NEXT: [[TMP5:%.*]] = addrspacecast float* [[ADDR]] to float addrspace(1)* -; GFX90A-NEXT: [[TMP6:%.*]] = atomicrmw fadd float addrspace(1)* [[TMP5]], float [[VAL]] syncscope("workgroup") seq_cst, align 4 +; GFX90A-NEXT: [[TMP5:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(1) +; GFX90A-NEXT: [[TMP6:%.*]] = atomicrmw fadd ptr addrspace(1) [[TMP5]], float [[VAL]] syncscope("workgroup") seq_cst, align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_PHI]] ; GFX90A: atomicrmw.phi: ; GFX90A-NEXT: [[LOADED_PHI:%.*]] = phi float [ [[TMP3]], [[ATOMICRMW_SHARED]] ], [ [[LOADED_PRIVATE]], [[ATOMICRMW_PRIVATE]] ], [ [[TMP6]], [[ATOMICRMW_GLOBAL]] ] @@ -228,44 +218,42 @@ ; GFX90A-NEXT: ret void ; ; GFX940-LABEL: @syncscope_workgroup_nortn( -; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd float* [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 +; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 ; GFX940-NEXT: ret void ; ; GFX1100-LABEL: @syncscope_workgroup_nortn( -; GFX1100-NEXT: [[RES:%.*]] = atomicrmw fadd float* [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 +; GFX1100-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[ADDR:%.*]], float [[VAL:%.*]] syncscope("workgroup") seq_cst, align 4 ; GFX1100-NEXT: ret void ; ; GFX11-LABEL: @syncscope_workgroup_nortn( -; GFX11-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4 +; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float ; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret void - %res = atomicrmw fadd float* %addr, float %val syncscope("workgroup") seq_cst + %res = atomicrmw fadd ptr %addr, float %val syncscope("workgroup") seq_cst ret void } -define float @no_unsafe(float* %addr, float %val) { +define float @no_unsafe(ptr %addr, float %val) { ; GFX908-LABEL: @no_unsafe( -; GFX908-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4 +; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -274,15 +262,14 @@ ; GFX908-NEXT: ret float [[TMP6]] ; ; GFX90A-LABEL: @no_unsafe( -; GFX90A-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4 +; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]] -; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32* ; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 +; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -291,15 +278,14 @@ ; GFX90A-NEXT: ret float [[TMP6]] ; ; GFX940-LABEL: @no_unsafe( -; GFX940-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4 +; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]] -; GFX940-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32* ; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 +; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -308,15 +294,14 @@ ; GFX940-NEXT: ret float [[TMP6]] ; ; GFX1100-LABEL: @no_unsafe( -; GFX1100-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4 +; GFX1100-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4 ; GFX1100-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX1100: atomicrmw.start: ; GFX1100-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX1100-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]] -; GFX1100-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32* ; GFX1100-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX1100-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX1100-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 +; GFX1100-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 ; GFX1100-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX1100-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX1100-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -325,22 +310,21 @@ ; GFX1100-NEXT: ret float [[TMP6]] ; ; GFX11-LABEL: @no_unsafe( -; GFX11-NEXT: [[TMP1:%.*]] = load float, float* [[ADDR:%.*]], align 4 +; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr [[ADDR:%.*]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VAL:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast float* [[ADDR]] to i32* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ADDR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("workgroup") seq_cst seq_cst, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float ; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret float [[TMP6]] - %res = atomicrmw fadd float* %addr, float %val syncscope("workgroup") seq_cst + %res = atomicrmw fadd ptr %addr, float %val syncscope("workgroup") seq_cst ret float %res } diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll --- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fadd.ll @@ -6,17 +6,16 @@ ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 -atomic-expand %s | FileCheck -check-prefix=GFX940 %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -atomic-expand %s | FileCheck -check-prefix=GFX11 %s -define void @test_atomicrmw_fadd_f32_global_no_use_unsafe(float addrspace(1)* %ptr, float %value) #0 { +define void @test_atomicrmw_fadd_f32_global_no_use_unsafe(ptr addrspace(1) %ptr, float %value) #0 { ; CI-LABEL: @test_atomicrmw_fadd_f32_global_no_use_unsafe( -; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -25,15 +24,14 @@ ; CI-NEXT: ret void ; ; GFX9-LABEL: @test_atomicrmw_fadd_f32_global_no_use_unsafe( -; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -42,36 +40,35 @@ ; GFX9-NEXT: ret void ; ; GFX908-LABEL: @test_atomicrmw_fadd_f32_global_no_use_unsafe( -; GFX908-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 +; GFX908-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 ; GFX908-NEXT: ret void ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global_no_use_unsafe( -; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 +; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 ; GFX90A-NEXT: ret void ; ; GFX940-LABEL: @test_atomicrmw_fadd_f32_global_no_use_unsafe( -; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 +; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 ; GFX940-NEXT: ret void ; ; GFX11-LABEL: @test_atomicrmw_fadd_f32_global_no_use_unsafe( -; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 +; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 ; GFX11-NEXT: ret void ; - %res = atomicrmw fadd float addrspace(1)* %ptr, float %value syncscope("wavefront") monotonic + %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value syncscope("wavefront") monotonic ret void } -define float @test_atomicrmw_fadd_f32_global_unsafe(float addrspace(1)* %ptr, float %value) #0 { +define float @test_atomicrmw_fadd_f32_global_unsafe(ptr addrspace(1) %ptr, float %value) #0 { ; CI-LABEL: @test_atomicrmw_fadd_f32_global_unsafe( -; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -80,15 +77,14 @@ ; CI-NEXT: ret float [[TMP6]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f32_global_unsafe( -; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -97,15 +93,14 @@ ; GFX9-NEXT: ret float [[TMP6]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f32_global_unsafe( -; GFX908-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -114,32 +109,31 @@ ; GFX908-NEXT: ret float [[TMP6]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global_unsafe( -; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 +; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 ; GFX90A-NEXT: ret float [[RES]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f32_global_unsafe( -; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 +; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 ; GFX940-NEXT: ret float [[RES]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f32_global_unsafe( -; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(1)* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 +; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 ; GFX11-NEXT: ret float [[RES]] ; - %res = atomicrmw fadd float addrspace(1)* %ptr, float %value syncscope("wavefront") monotonic + %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value syncscope("wavefront") monotonic ret float %res } -define double @test_atomicrmw_fadd_f64_global_unsafe(double addrspace(1)* %ptr, double %value) #0 { +define double @test_atomicrmw_fadd_f64_global_unsafe(ptr addrspace(1) %ptr, double %value) #0 { ; CI-LABEL: @test_atomicrmw_fadd_f64_global_unsafe( -; CI-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8 +; CI-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)* ; CI-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; CI-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -148,15 +142,14 @@ ; CI-NEXT: ret double [[TMP6]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f64_global_unsafe( -; GFX9-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8 +; GFX9-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -165,15 +158,14 @@ ; GFX9-NEXT: ret double [[TMP6]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f64_global_unsafe( -; GFX908-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8 +; GFX908-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -182,23 +174,22 @@ ; GFX908-NEXT: ret double [[TMP6]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f64_global_unsafe( -; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd double addrspace(1)* [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8 +; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8 ; GFX90A-NEXT: ret double [[RES]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f64_global_unsafe( -; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd double addrspace(1)* [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8 +; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8 ; GFX940-NEXT: ret double [[RES]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f64_global_unsafe( -; GFX11-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8 +; GFX11-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -206,21 +197,20 @@ ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret double [[TMP6]] ; - %res = atomicrmw fadd double addrspace(1)* %ptr, double %value syncscope("wavefront") monotonic + %res = atomicrmw fadd ptr addrspace(1) %ptr, double %value syncscope("wavefront") monotonic ret double %res } -define float @test_atomicrmw_fadd_f32_flat_unsafe(float* %ptr, float %value) #0 { +define float @test_atomicrmw_fadd_f32_flat_unsafe(ptr %ptr, float %value) #0 { ; CI-LABEL: @test_atomicrmw_fadd_f32_flat_unsafe( -; CI-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CI-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -229,15 +219,14 @@ ; CI-NEXT: ret float [[TMP6]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f32_flat_unsafe( -; GFX9-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -246,15 +235,14 @@ ; GFX9-NEXT: ret float [[TMP6]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f32_flat_unsafe( -; GFX908-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -263,27 +251,26 @@ ; GFX908-NEXT: ret float [[TMP6]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f32_flat_unsafe( -; GFX90A-NEXT: [[TMP1:%.*]] = bitcast float* [[PTR:%.*]] to i8* ; GFX90A-NEXT: br label [[ATOMICRMW_CHECK_SHARED:%.*]] ; GFX90A: atomicrmw.check.shared: -; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(i8* [[TMP1]]) +; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[PTR:%.*]]) ; GFX90A-NEXT: br i1 [[IS_SHARED]], label [[ATOMICRMW_SHARED:%.*]], label [[ATOMICRMW_CHECK_PRIVATE:%.*]] ; GFX90A: atomicrmw.shared: -; GFX90A-NEXT: [[TMP2:%.*]] = addrspacecast float* [[PTR]] to float addrspace(3)* -; GFX90A-NEXT: [[TMP3:%.*]] = atomicrmw fadd float addrspace(3)* [[TMP2]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 +; GFX90A-NEXT: [[TMP2:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(3) +; GFX90A-NEXT: [[TMP3:%.*]] = atomicrmw fadd ptr addrspace(3) [[TMP2]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_PHI:%.*]] ; GFX90A: atomicrmw.check.private: -; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(i8* [[TMP1]]) +; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[PTR]]) ; GFX90A-NEXT: br i1 [[IS_PRIVATE]], label [[ATOMICRMW_PRIVATE:%.*]], label [[ATOMICRMW_GLOBAL:%.*]] ; GFX90A: atomicrmw.private: -; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast float* [[PTR]] to float addrspace(5)* -; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, float addrspace(5)* [[TMP4]], align 4 +; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(5) +; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, ptr addrspace(5) [[TMP4]], align 4 ; GFX90A-NEXT: [[VAL_NEW:%.*]] = fadd float [[LOADED_PRIVATE]], [[VALUE]] -; GFX90A-NEXT: store float [[VAL_NEW]], float addrspace(5)* [[TMP4]], align 4 +; GFX90A-NEXT: store float [[VAL_NEW]], ptr addrspace(5) [[TMP4]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_PHI]] ; GFX90A: atomicrmw.global: -; GFX90A-NEXT: [[TMP5:%.*]] = addrspacecast float* [[PTR]] to float addrspace(1)* -; GFX90A-NEXT: [[TMP6:%.*]] = atomicrmw fadd float addrspace(1)* [[TMP5]], float [[VALUE]] syncscope("wavefront") monotonic, align 4 +; GFX90A-NEXT: [[TMP5:%.*]] = addrspacecast ptr [[PTR]] to ptr addrspace(1) +; GFX90A-NEXT: [[TMP6:%.*]] = atomicrmw fadd ptr addrspace(1) [[TMP5]], float [[VALUE]] syncscope("wavefront") monotonic, align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_PHI]] ; GFX90A: atomicrmw.phi: ; GFX90A-NEXT: [[LOADED_PHI:%.*]] = phi float [ [[TMP3]], [[ATOMICRMW_SHARED]] ], [ [[LOADED_PRIVATE]], [[ATOMICRMW_PRIVATE]] ], [ [[TMP6]], [[ATOMICRMW_GLOBAL]] ] @@ -292,28 +279,27 @@ ; GFX90A-NEXT: ret float [[LOADED_PHI]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f32_flat_unsafe( -; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd float* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 +; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 ; GFX940-NEXT: ret float [[RES]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f32_flat_unsafe( -; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd float* [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 +; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[PTR:%.*]], float [[VALUE:%.*]] syncscope("wavefront") monotonic, align 4 ; GFX11-NEXT: ret float [[RES]] ; - %res = atomicrmw fadd float* %ptr, float %value syncscope("wavefront") monotonic + %res = atomicrmw fadd ptr %ptr, float %value syncscope("wavefront") monotonic ret float %res } -define double @test_atomicrmw_fadd_f64_flat_unsafe(double* %ptr, double %value) #0 { +define double @test_atomicrmw_fadd_f64_flat_unsafe(ptr %ptr, double %value) #0 { ; CI-LABEL: @test_atomicrmw_fadd_f64_flat_unsafe( -; CI-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; CI-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64* ; CI-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; CI-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -322,15 +308,14 @@ ; CI-NEXT: ret double [[TMP6]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f64_flat_unsafe( -; GFX9-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; GFX9-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -339,15 +324,14 @@ ; GFX9-NEXT: ret double [[TMP6]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f64_flat_unsafe( -; GFX908-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; GFX908-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -356,23 +340,22 @@ ; GFX908-NEXT: ret double [[TMP6]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f64_flat_unsafe( -; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd double* [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8 +; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8 ; GFX90A-NEXT: ret double [[RES]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f64_flat_unsafe( -; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd double* [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8 +; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[PTR:%.*]], double [[VALUE:%.*]] syncscope("wavefront") monotonic, align 8 ; GFX940-NEXT: ret double [[RES]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f64_flat_unsafe( -; GFX11-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; GFX11-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] syncscope("wavefront") monotonic monotonic, align 8 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -380,21 +363,20 @@ ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret double [[TMP6]] ; - %res = atomicrmw fadd double* %ptr, double %value syncscope("wavefront") monotonic + %res = atomicrmw fadd ptr %ptr, double %value syncscope("wavefront") monotonic ret double %res } -define float @test_atomicrmw_fadd_f32_flat(float* %ptr, float %value) { +define float @test_atomicrmw_fadd_f32_flat(ptr %ptr, float %value) { ; CI-LABEL: @test_atomicrmw_fadd_f32_flat( -; CI-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CI-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -403,15 +385,14 @@ ; CI-NEXT: ret float [[TMP6]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f32_flat( -; GFX9-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -420,15 +401,14 @@ ; GFX9-NEXT: ret float [[TMP6]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f32_flat( -; GFX908-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -437,15 +417,14 @@ ; GFX908-NEXT: ret float [[TMP6]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f32_flat( -; GFX90A-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -454,15 +433,14 @@ ; GFX90A-NEXT: ret float [[TMP6]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f32_flat( -; GFX940-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX940-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -471,15 +449,14 @@ ; GFX940-NEXT: ret float [[TMP6]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f32_flat( -; GFX11-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -487,21 +464,20 @@ ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fadd float* %ptr, float %value seq_cst + %res = atomicrmw fadd ptr %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fadd_f32_global(float addrspace(1)* %ptr, float %value) { +define float @test_atomicrmw_fadd_f32_global(ptr addrspace(1) %ptr, float %value) { ; CI-LABEL: @test_atomicrmw_fadd_f32_global( -; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -510,15 +486,14 @@ ; CI-NEXT: ret float [[TMP6]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f32_global( -; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -527,15 +502,14 @@ ; GFX9-NEXT: ret float [[TMP6]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f32_global( -; GFX908-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -544,15 +518,14 @@ ; GFX908-NEXT: ret float [[TMP6]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global( -; GFX90A-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -561,15 +534,14 @@ ; GFX90A-NEXT: ret float [[TMP6]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f32_global( -; GFX940-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX940-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -578,15 +550,14 @@ ; GFX940-NEXT: ret float [[TMP6]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f32_global( -; GFX11-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -594,21 +565,20 @@ ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fadd float addrspace(1)* %ptr, float %value seq_cst + %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value seq_cst ret float %res } -define void @test_atomicrmw_fadd_f32_global_no_use_ieee(float addrspace(1)* %ptr, float %value) { +define void @test_atomicrmw_fadd_f32_global_no_use_ieee(ptr addrspace(1) %ptr, float %value) { ; CI-LABEL: @test_atomicrmw_fadd_f32_global_no_use_ieee( -; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -617,15 +587,14 @@ ; CI-NEXT: ret void ; ; GFX9-LABEL: @test_atomicrmw_fadd_f32_global_no_use_ieee( -; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -634,15 +603,14 @@ ; GFX9-NEXT: ret void ; ; GFX908-LABEL: @test_atomicrmw_fadd_f32_global_no_use_ieee( -; GFX908-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -651,15 +619,14 @@ ; GFX908-NEXT: ret void ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global_no_use_ieee( -; GFX90A-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -668,15 +635,14 @@ ; GFX90A-NEXT: ret void ; ; GFX940-LABEL: @test_atomicrmw_fadd_f32_global_no_use_ieee( -; GFX940-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX940-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -685,15 +651,14 @@ ; GFX940-NEXT: ret void ; ; GFX11-LABEL: @test_atomicrmw_fadd_f32_global_no_use_ieee( -; GFX11-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -701,21 +666,20 @@ ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret void ; - %res = atomicrmw fadd float addrspace(1)* %ptr, float %value seq_cst + %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value seq_cst ret void } -define void @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(float addrspace(1)* %ptr, float %value) #0 { +define void @test_atomicrmw_fadd_f32_global_no_use_denorm_flush(ptr addrspace(1) %ptr, float %value) #0 { ; CI-LABEL: @test_atomicrmw_fadd_f32_global_no_use_denorm_flush( -; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -724,15 +688,14 @@ ; CI-NEXT: ret void ; ; GFX9-LABEL: @test_atomicrmw_fadd_f32_global_no_use_denorm_flush( -; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -741,15 +704,14 @@ ; GFX9-NEXT: ret void ; ; GFX908-LABEL: @test_atomicrmw_fadd_f32_global_no_use_denorm_flush( -; GFX908-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -758,15 +720,14 @@ ; GFX908-NEXT: ret void ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global_no_use_denorm_flush( -; GFX90A-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -775,15 +736,14 @@ ; GFX90A-NEXT: ret void ; ; GFX940-LABEL: @test_atomicrmw_fadd_f32_global_no_use_denorm_flush( -; GFX940-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX940-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -792,15 +752,14 @@ ; GFX940-NEXT: ret void ; ; GFX11-LABEL: @test_atomicrmw_fadd_f32_global_no_use_denorm_flush( -; GFX11-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -808,21 +767,20 @@ ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret void ; - %res = atomicrmw fadd float addrspace(1)* %ptr, float %value seq_cst + %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value seq_cst ret void } -define float @test_atomicrmw_fadd_f32_local(float addrspace(3)* %ptr, float %value) { +define float @test_atomicrmw_fadd_f32_local(ptr addrspace(3) %ptr, float %value) { ; CI-LABEL: @test_atomicrmw_fadd_f32_local( -; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(3)* [[PTR:%.*]], align 4 +; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(3) [[PTR:%.*]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(3)* [[PTR]] to i32 addrspace(3)* ; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(3)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -831,40 +789,39 @@ ; CI-NEXT: ret float [[TMP6]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f32_local( -; GFX9-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(3)* [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4 +; GFX9-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4 ; GFX9-NEXT: ret float [[RES]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f32_local( -; GFX908-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(3)* [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4 +; GFX908-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4 ; GFX908-NEXT: ret float [[RES]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f32_local( -; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(3)* [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4 +; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4 ; GFX90A-NEXT: ret float [[RES]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f32_local( -; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(3)* [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4 +; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4 ; GFX940-NEXT: ret float [[RES]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f32_local( -; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd float addrspace(3)* [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4 +; GFX11-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], float [[VALUE:%.*]] seq_cst, align 4 ; GFX11-NEXT: ret float [[RES]] ; - %res = atomicrmw fadd float addrspace(3)* %ptr, float %value seq_cst + %res = atomicrmw fadd ptr addrspace(3) %ptr, float %value seq_cst ret float %res } -define half @test_atomicrmw_fadd_f16_flat(half* %ptr, half %value) { +define half @test_atomicrmw_fadd_f16_flat(ptr %ptr, half %value) { ; CI-LABEL: @test_atomicrmw_fadd_f16_flat( -; CI-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4) -; CI-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64 +; CI-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4) +; CI-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64 ; CI-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CI-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CI-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CI-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CI-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CI-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32* -; CI-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; CI-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -877,7 +834,7 @@ ; CI-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; CI-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CI-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; CI-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; CI-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; CI-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; CI-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -888,15 +845,14 @@ ; CI-NEXT: ret half [[TMP7]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f16_flat( -; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4) -; GFX9-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64 +; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4) +; GFX9-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64 ; GFX9-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX9-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX9-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX9-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX9-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX9-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32* -; GFX9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; GFX9-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -909,7 +865,7 @@ ; GFX9-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX9-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX9-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX9-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX9-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX9-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX9-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -920,15 +876,14 @@ ; GFX9-NEXT: ret half [[TMP7]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f16_flat( -; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4) -; GFX908-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64 +; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4) +; GFX908-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64 ; GFX908-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX908-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX908-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX908-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX908-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX908-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32* -; GFX908-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; GFX908-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -941,7 +896,7 @@ ; GFX908-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX908-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX908-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX908-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX908-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX908-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX908-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -952,15 +907,14 @@ ; GFX908-NEXT: ret half [[TMP7]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f16_flat( -; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4) -; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64 +; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4) +; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64 ; GFX90A-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX90A-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX90A-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX90A-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX90A-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX90A-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32* -; GFX90A-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; GFX90A-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -973,7 +927,7 @@ ; GFX90A-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX90A-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX90A-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX90A-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX90A-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX90A-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX90A-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -984,15 +938,14 @@ ; GFX90A-NEXT: ret half [[TMP7]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f16_flat( -; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4) -; GFX940-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64 +; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4) +; GFX940-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64 ; GFX940-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX940-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX940-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX940-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX940-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX940-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32* -; GFX940-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; GFX940-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1005,7 +958,7 @@ ; GFX940-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX940-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX940-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX940-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX940-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX940-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX940-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1016,15 +969,14 @@ ; GFX940-NEXT: ret half [[TMP7]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f16_flat( -; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4) -; GFX11-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64 +; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4) +; GFX11-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64 ; GFX11-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX11-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX11-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX11-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX11-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX11-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32* -; GFX11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; GFX11-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1037,7 +989,7 @@ ; GFX11-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX11-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX11-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX11-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX11-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX11-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1047,21 +999,20 @@ ; GFX11-NEXT: [[TMP7:%.*]] = bitcast i16 [[EXTRACTED4]] to half ; GFX11-NEXT: ret half [[TMP7]] ; - %res = atomicrmw fadd half* %ptr, half %value seq_cst + %res = atomicrmw fadd ptr %ptr, half %value seq_cst ret half %res } -define half @test_atomicrmw_fadd_f16_global(half addrspace(1)* %ptr, half %value) { +define half @test_atomicrmw_fadd_f16_global(ptr addrspace(1) %ptr, half %value) { ; CI-LABEL: @test_atomicrmw_fadd_f16_global( -; CI-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4) -; CI-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64 +; CI-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; CI-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; CI-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CI-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CI-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CI-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CI-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CI-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; CI-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; CI-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1074,7 +1025,7 @@ ; CI-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; CI-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CI-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; CI-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; CI-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; CI-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; CI-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1085,15 +1036,14 @@ ; CI-NEXT: ret half [[TMP7]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f16_global( -; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4) -; GFX9-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64 +; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; GFX9-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; GFX9-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX9-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX9-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX9-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX9-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX9-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; GFX9-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; GFX9-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1106,7 +1056,7 @@ ; GFX9-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX9-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX9-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX9-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX9-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX9-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX9-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1117,15 +1067,14 @@ ; GFX9-NEXT: ret half [[TMP7]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f16_global( -; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4) -; GFX908-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64 +; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; GFX908-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; GFX908-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX908-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX908-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX908-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX908-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX908-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; GFX908-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; GFX908-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1138,7 +1087,7 @@ ; GFX908-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX908-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX908-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX908-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX908-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX908-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX908-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1149,15 +1098,14 @@ ; GFX908-NEXT: ret half [[TMP7]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f16_global( -; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4) -; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64 +; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; GFX90A-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX90A-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX90A-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX90A-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX90A-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX90A-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; GFX90A-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; GFX90A-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1170,7 +1118,7 @@ ; GFX90A-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX90A-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX90A-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX90A-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX90A-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX90A-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX90A-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1181,15 +1129,14 @@ ; GFX90A-NEXT: ret half [[TMP7]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f16_global( -; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4) -; GFX940-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64 +; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; GFX940-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; GFX940-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX940-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX940-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX940-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX940-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX940-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; GFX940-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; GFX940-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1202,7 +1149,7 @@ ; GFX940-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX940-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX940-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX940-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX940-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX940-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX940-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1213,15 +1160,14 @@ ; GFX940-NEXT: ret half [[TMP7]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f16_global( -; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4) -; GFX11-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64 +; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; GFX11-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; GFX11-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX11-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX11-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX11-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX11-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX11-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; GFX11-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; GFX11-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1234,7 +1180,7 @@ ; GFX11-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX11-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX11-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX11-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX11-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX11-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1244,14 +1190,13 @@ ; GFX11-NEXT: [[TMP7:%.*]] = bitcast i16 [[EXTRACTED4]] to half ; GFX11-NEXT: ret half [[TMP7]] ; - %res = atomicrmw fadd half addrspace(1)* %ptr, half %value seq_cst + %res = atomicrmw fadd ptr addrspace(1) %ptr, half %value seq_cst ret half %res } -define half @test_atomicrmw_fadd_f16_global_align4(half addrspace(1)* %ptr, half %value) { +define half @test_atomicrmw_fadd_f16_global_align4(ptr addrspace(1) %ptr, half %value) { ; CI-LABEL: @test_atomicrmw_fadd_f16_global_align4( -; CI-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)* -; CI-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4 +; CI-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1262,7 +1207,7 @@ ; CI-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32 ; CI-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536 ; CI-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]] -; CI-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; CI-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1 ; CI-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0 ; CI-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1272,8 +1217,7 @@ ; CI-NEXT: ret half [[TMP5]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f16_global_align4( -; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)* -; GFX9-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4 +; GFX9-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1284,7 +1228,7 @@ ; GFX9-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32 ; GFX9-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536 ; GFX9-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]] -; GFX9-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX9-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1 ; GFX9-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0 ; GFX9-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1294,8 +1238,7 @@ ; GFX9-NEXT: ret half [[TMP5]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f16_global_align4( -; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)* -; GFX908-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4 +; GFX908-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1306,7 +1249,7 @@ ; GFX908-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32 ; GFX908-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536 ; GFX908-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]] -; GFX908-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX908-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1 ; GFX908-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0 ; GFX908-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1316,8 +1259,7 @@ ; GFX908-NEXT: ret half [[TMP5]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f16_global_align4( -; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)* -; GFX90A-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4 +; GFX90A-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1328,7 +1270,7 @@ ; GFX90A-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32 ; GFX90A-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536 ; GFX90A-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]] -; GFX90A-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX90A-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1 ; GFX90A-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0 ; GFX90A-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1338,8 +1280,7 @@ ; GFX90A-NEXT: ret half [[TMP5]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f16_global_align4( -; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)* -; GFX940-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4 +; GFX940-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1350,7 +1291,7 @@ ; GFX940-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32 ; GFX940-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536 ; GFX940-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]] -; GFX940-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX940-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1 ; GFX940-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0 ; GFX940-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1360,8 +1301,7 @@ ; GFX940-NEXT: ret half [[TMP5]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f16_global_align4( -; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)* -; GFX11-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4 +; GFX11-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1372,7 +1312,7 @@ ; GFX11-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32 ; GFX11-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536 ; GFX11-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]] -; GFX11-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX11-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1 ; GFX11-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0 ; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1381,21 +1321,20 @@ ; GFX11-NEXT: [[TMP5:%.*]] = bitcast i16 [[EXTRACTED1]] to half ; GFX11-NEXT: ret half [[TMP5]] ; - %res = atomicrmw fadd half addrspace(1)* %ptr, half %value seq_cst, align 4 + %res = atomicrmw fadd ptr addrspace(1) %ptr, half %value seq_cst, align 4 ret half %res } -define half @test_atomicrmw_fadd_f16_local(half addrspace(3)* %ptr, half %value) { +define half @test_atomicrmw_fadd_f16_local(ptr addrspace(3) %ptr, half %value) { ; CI-LABEL: @test_atomicrmw_fadd_f16_local( -; CI-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4) -; CI-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64 +; CI-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4) +; CI-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64 ; CI-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CI-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; CI-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CI-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CI-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CI-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)* -; CI-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4 +; CI-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1408,7 +1347,7 @@ ; CI-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; CI-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CI-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; CI-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; CI-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; CI-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; CI-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1419,15 +1358,14 @@ ; CI-NEXT: ret half [[TMP7]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f16_local( -; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4) -; GFX9-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64 +; GFX9-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4) +; GFX9-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64 ; GFX9-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX9-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX9-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX9-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX9-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX9-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)* -; GFX9-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4 +; GFX9-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1440,7 +1378,7 @@ ; GFX9-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX9-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX9-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX9-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX9-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX9-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX9-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1451,15 +1389,14 @@ ; GFX9-NEXT: ret half [[TMP7]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f16_local( -; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4) -; GFX908-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64 +; GFX908-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4) +; GFX908-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64 ; GFX908-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX908-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX908-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX908-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX908-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX908-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)* -; GFX908-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4 +; GFX908-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1472,7 +1409,7 @@ ; GFX908-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX908-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX908-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX908-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX908-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX908-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX908-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1483,15 +1420,14 @@ ; GFX908-NEXT: ret half [[TMP7]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f16_local( -; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4) -; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64 +; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4) +; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64 ; GFX90A-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX90A-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX90A-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX90A-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX90A-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX90A-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)* -; GFX90A-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4 +; GFX90A-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1504,7 +1440,7 @@ ; GFX90A-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX90A-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX90A-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX90A-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX90A-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX90A-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX90A-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1515,15 +1451,14 @@ ; GFX90A-NEXT: ret half [[TMP7]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f16_local( -; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4) -; GFX940-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64 +; GFX940-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4) +; GFX940-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64 ; GFX940-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX940-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX940-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX940-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX940-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX940-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)* -; GFX940-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4 +; GFX940-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1536,7 +1471,7 @@ ; GFX940-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX940-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX940-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX940-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX940-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX940-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX940-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1547,15 +1482,14 @@ ; GFX940-NEXT: ret half [[TMP7]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f16_local( -; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4) -; GFX11-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64 +; GFX11-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4) +; GFX11-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64 ; GFX11-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GFX11-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GFX11-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GFX11-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GFX11-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GFX11-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)* -; GFX11-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4 +; GFX11-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -1568,7 +1502,7 @@ ; GFX11-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GFX11-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GFX11-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GFX11-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GFX11-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GFX11-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GFX11-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1578,21 +1512,20 @@ ; GFX11-NEXT: [[TMP7:%.*]] = bitcast i16 [[EXTRACTED4]] to half ; GFX11-NEXT: ret half [[TMP7]] ; - %res = atomicrmw fadd half addrspace(3)* %ptr, half %value seq_cst + %res = atomicrmw fadd ptr addrspace(3) %ptr, half %value seq_cst ret half %res } -define double @test_atomicrmw_fadd_f64_flat(double* %ptr, double %value) { +define double @test_atomicrmw_fadd_f64_flat(ptr %ptr, double %value) { ; CI-LABEL: @test_atomicrmw_fadd_f64_flat( -; CI-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; CI-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64* ; CI-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; CI-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1601,15 +1534,14 @@ ; CI-NEXT: ret double [[TMP6]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f64_flat( -; GFX9-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; GFX9-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1618,15 +1550,14 @@ ; GFX9-NEXT: ret double [[TMP6]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f64_flat( -; GFX908-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; GFX908-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1635,15 +1566,14 @@ ; GFX908-NEXT: ret double [[TMP6]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f64_flat( -; GFX90A-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; GFX90A-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX90A-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX90A-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64* ; GFX90A-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX90A-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX90A-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1652,15 +1582,14 @@ ; GFX90A-NEXT: ret double [[TMP6]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f64_flat( -; GFX940-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; GFX940-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX940-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX940-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64* ; GFX940-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX940-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX940-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1669,15 +1598,14 @@ ; GFX940-NEXT: ret double [[TMP6]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f64_flat( -; GFX11-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; GFX11-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1685,21 +1613,20 @@ ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret double [[TMP6]] ; - %res = atomicrmw fadd double* %ptr, double %value seq_cst + %res = atomicrmw fadd ptr %ptr, double %value seq_cst ret double %res } -define double @test_atomicrmw_fadd_f64_global(double addrspace(1)* %ptr, double %value) { +define double @test_atomicrmw_fadd_f64_global(ptr addrspace(1) %ptr, double %value) { ; CI-LABEL: @test_atomicrmw_fadd_f64_global( -; CI-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8 +; CI-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)* ; CI-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; CI-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1708,15 +1635,14 @@ ; CI-NEXT: ret double [[TMP6]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f64_global( -; GFX9-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8 +; GFX9-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1725,15 +1651,14 @@ ; GFX9-NEXT: ret double [[TMP6]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f64_global( -; GFX908-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8 +; GFX908-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1742,15 +1667,14 @@ ; GFX908-NEXT: ret double [[TMP6]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f64_global( -; GFX90A-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8 +; GFX90A-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX90A-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX90A-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)* ; GFX90A-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX90A-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX90A-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1759,15 +1683,14 @@ ; GFX90A-NEXT: ret double [[TMP6]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f64_global( -; GFX940-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8 +; GFX940-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX940-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX940-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)* ; GFX940-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX940-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX940-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1776,15 +1699,14 @@ ; GFX940-NEXT: ret double [[TMP6]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f64_global( -; GFX11-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8 +; GFX11-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1792,21 +1714,20 @@ ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret double [[TMP6]] ; - %res = atomicrmw fadd double addrspace(1)* %ptr, double %value seq_cst + %res = atomicrmw fadd ptr addrspace(1) %ptr, double %value seq_cst ret double %res } -define double @test_atomicrmw_fadd_f64_local(double addrspace(3)* %ptr, double %value) { +define double @test_atomicrmw_fadd_f64_local(ptr addrspace(3) %ptr, double %value) { ; CI-LABEL: @test_atomicrmw_fadd_f64_local( -; CI-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8 +; CI-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)* ; CI-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; CI-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(3)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1815,15 +1736,14 @@ ; CI-NEXT: ret double [[TMP6]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f64_local( -; GFX9-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8 +; GFX9-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(3)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1832,15 +1752,14 @@ ; GFX9-NEXT: ret double [[TMP6]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f64_local( -; GFX908-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8 +; GFX908-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(3)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1849,23 +1768,22 @@ ; GFX908-NEXT: ret double [[TMP6]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f64_local( -; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd double addrspace(3)* [[PTR:%.*]], double [[VALUE:%.*]] seq_cst, align 8 +; GFX90A-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], double [[VALUE:%.*]] seq_cst, align 8 ; GFX90A-NEXT: ret double [[RES]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f64_local( -; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd double addrspace(3)* [[PTR:%.*]], double [[VALUE:%.*]] seq_cst, align 8 +; GFX940-NEXT: [[RES:%.*]] = atomicrmw fadd ptr addrspace(3) [[PTR:%.*]], double [[VALUE:%.*]] seq_cst, align 8 ; GFX940-NEXT: ret double [[RES]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f64_local( -; GFX11-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8 +; GFX11-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(3)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -1873,21 +1791,20 @@ ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret double [[TMP6]] ; - %res = atomicrmw fadd double addrspace(3)* %ptr, double %value seq_cst + %res = atomicrmw fadd ptr addrspace(3) %ptr, double %value seq_cst ret double %res } -define float @test_atomicrmw_fadd_f32_global_agent(float addrspace(1)* %ptr, float %value) { +define float @test_atomicrmw_fadd_f32_global_agent(ptr addrspace(1) %ptr, float %value) { ; CI-LABEL: @test_atomicrmw_fadd_f32_global_agent( -; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -1896,15 +1813,14 @@ ; CI-NEXT: ret float [[TMP6]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f32_global_agent( -; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -1913,15 +1829,14 @@ ; GFX9-NEXT: ret float [[TMP6]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f32_global_agent( -; GFX908-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -1930,15 +1845,14 @@ ; GFX908-NEXT: ret float [[TMP6]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global_agent( -; GFX90A-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4 +; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -1947,15 +1861,14 @@ ; GFX90A-NEXT: ret float [[TMP6]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f32_global_agent( -; GFX940-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX940-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4 +; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -1964,15 +1877,14 @@ ; GFX940-NEXT: ret float [[TMP6]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f32_global_agent( -; GFX11-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("agent") monotonic monotonic, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -1980,21 +1892,20 @@ ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fadd float addrspace(1)* %ptr, float %value syncscope("agent") monotonic + %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value syncscope("agent") monotonic ret float %res } -define float @test_atomicrmw_fadd_f32_global_one_as(float addrspace(1)* %ptr, float %value) { +define float @test_atomicrmw_fadd_f32_global_one_as(ptr addrspace(1) %ptr, float %value) { ; CI-LABEL: @test_atomicrmw_fadd_f32_global_one_as( -; CI-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; CI-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; CI-NEXT: br label [[ATOMICRMW_START:%.*]] ; CI: atomicrmw.start: ; CI-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CI-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CI-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; CI-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CI-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CI-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4 +; CI-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4 ; CI-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CI-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CI-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -2003,15 +1914,14 @@ ; CI-NEXT: ret float [[TMP6]] ; ; GFX9-LABEL: @test_atomicrmw_fadd_f32_global_one_as( -; GFX9-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX9-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX9-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX9: atomicrmw.start: ; GFX9-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX9-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX9-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX9-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX9-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4 +; GFX9-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4 ; GFX9-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX9-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX9-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -2020,15 +1930,14 @@ ; GFX9-NEXT: ret float [[TMP6]] ; ; GFX908-LABEL: @test_atomicrmw_fadd_f32_global_one_as( -; GFX908-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX908-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX908-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX908: atomicrmw.start: ; GFX908-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX908-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX908-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX908-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX908-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4 +; GFX908-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4 ; GFX908-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX908-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX908-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -2037,15 +1946,14 @@ ; GFX908-NEXT: ret float [[TMP6]] ; ; GFX90A-LABEL: @test_atomicrmw_fadd_f32_global_one_as( -; GFX90A-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX90A-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX90A: atomicrmw.start: ; GFX90A-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX90A-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX90A-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX90A-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX90A-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4 +; GFX90A-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4 ; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX90A-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX90A-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -2054,15 +1962,14 @@ ; GFX90A-NEXT: ret float [[TMP6]] ; ; GFX940-LABEL: @test_atomicrmw_fadd_f32_global_one_as( -; GFX940-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX940-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX940-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX940: atomicrmw.start: ; GFX940-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX940-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX940-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX940-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX940-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4 +; GFX940-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4 ; GFX940-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX940-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX940-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -2071,15 +1978,14 @@ ; GFX940-NEXT: ret float [[TMP6]] ; ; GFX11-LABEL: @test_atomicrmw_fadd_f32_global_one_as( -; GFX11-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GFX11-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GFX11-NEXT: br label [[ATOMICRMW_START:%.*]] ; GFX11: atomicrmw.start: ; GFX11-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GFX11-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; GFX11-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GFX11-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GFX11-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4 +; GFX11-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] syncscope("one-as") monotonic monotonic, align 4 ; GFX11-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GFX11-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GFX11-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -2087,7 +1993,7 @@ ; GFX11: atomicrmw.end: ; GFX11-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fadd float addrspace(1)* %ptr, float %value syncscope("one-as") monotonic + %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value syncscope("one-as") monotonic ret float %res } diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmax.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmax.ll --- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmax.ll +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmax.ll @@ -2,17 +2,16 @@ ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -atomic-expand %s | FileCheck -check-prefix=GCN %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -atomic-expand %s | FileCheck -check-prefix=GCN %s -define float @test_atomicrmw_fmax_f32_flat(float* %ptr, float %value) { +define float @test_atomicrmw_fmax_f32_flat(ptr %ptr, float %value) { ; GCN-LABEL: @test_atomicrmw_fmax_f32_flat( -; GCN-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; GCN-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[TMP2:%.*]] = call float @llvm.maxnum.f32(float [[LOADED]], float [[VALUE:%.*]]) -; GCN-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i32* ; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[TMP2]] to i32 ; GCN-NEXT: [[TMP5:%.*]] = bitcast float [[LOADED]] to i32 -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[TMP3]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GCN-NEXT: [[TMP7]] = bitcast i32 [[NEWLOADED]] to float @@ -20,21 +19,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret float [[TMP7]] ; - %res = atomicrmw fmax float* %ptr, float %value seq_cst + %res = atomicrmw fmax ptr %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fmax_f32_global(float addrspace(1)* %ptr, float %value) { +define float @test_atomicrmw_fmax_f32_global(ptr addrspace(1) %ptr, float %value) { ; GCN-LABEL: @test_atomicrmw_fmax_f32_global( -; GCN-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GCN-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[TMP2:%.*]] = call float @llvm.maxnum.f32(float [[LOADED]], float [[VALUE:%.*]]) -; GCN-NEXT: [[TMP3:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[TMP2]] to i32 ; GCN-NEXT: [[TMP5:%.*]] = bitcast float [[LOADED]] to i32 -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[TMP3]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GCN-NEXT: [[TMP7]] = bitcast i32 [[NEWLOADED]] to float @@ -42,21 +40,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret float [[TMP7]] ; - %res = atomicrmw fmax float addrspace(1)* %ptr, float %value seq_cst + %res = atomicrmw fmax ptr addrspace(1) %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fmax_f32_local(float addrspace(3)* %ptr, float %value) { +define float @test_atomicrmw_fmax_f32_local(ptr addrspace(3) %ptr, float %value) { ; GCN-LABEL: @test_atomicrmw_fmax_f32_local( -; GCN-NEXT: [[TMP1:%.*]] = load float, float addrspace(3)* [[PTR:%.*]], align 4 +; GCN-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(3) [[PTR:%.*]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[TMP2:%.*]] = call float @llvm.maxnum.f32(float [[LOADED]], float [[VALUE:%.*]]) -; GCN-NEXT: [[TMP3:%.*]] = bitcast float addrspace(3)* [[PTR]] to i32 addrspace(3)* ; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[TMP2]] to i32 ; GCN-NEXT: [[TMP5:%.*]] = bitcast float [[LOADED]] to i32 -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[TMP3]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GCN-NEXT: [[TMP7]] = bitcast i32 [[NEWLOADED]] to float @@ -64,21 +61,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret float [[TMP7]] ; - %res = atomicrmw fmax float addrspace(3)* %ptr, float %value seq_cst + %res = atomicrmw fmax ptr addrspace(3) %ptr, float %value seq_cst ret float %res } -define half @test_atomicrmw_fmax_f16_flat(half* %ptr, half %value) { +define half @test_atomicrmw_fmax_f16_flat(ptr %ptr, half %value) { ; GCN-LABEL: @test_atomicrmw_fmax_f16_flat( -; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4) -; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64 +; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4) +; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64 ; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32* -; GCN-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -91,7 +87,7 @@ ; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GCN-NEXT: [[TMP7:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP7:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 ; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 ; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -101,21 +97,20 @@ ; GCN-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half ; GCN-NEXT: ret half [[TMP8]] ; - %res = atomicrmw fmax half* %ptr, half %value seq_cst + %res = atomicrmw fmax ptr %ptr, half %value seq_cst ret half %res } -define half @test_atomicrmw_fmax_f16_global(half addrspace(1)* %ptr, half %value) { +define half @test_atomicrmw_fmax_f16_global(ptr addrspace(1) %ptr, half %value) { ; GCN-LABEL: @test_atomicrmw_fmax_f16_global( -; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4) -; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64 +; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; GCN-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -128,7 +123,7 @@ ; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GCN-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 ; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 ; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -138,14 +133,13 @@ ; GCN-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half ; GCN-NEXT: ret half [[TMP8]] ; - %res = atomicrmw fmax half addrspace(1)* %ptr, half %value seq_cst + %res = atomicrmw fmax ptr addrspace(1) %ptr, half %value seq_cst ret half %res } -define half @test_atomicrmw_fmax_f16_global_align4(half addrspace(1)* %ptr, half %value) { +define half @test_atomicrmw_fmax_f16_global_align4(ptr addrspace(1) %ptr, half %value) { ; GCN-LABEL: @test_atomicrmw_fmax_f16_global_align4( -; GCN-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)* -; GCN-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4 +; GCN-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -156,7 +150,7 @@ ; GCN-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP4]] to i32 ; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536 ; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]] -; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -165,21 +159,20 @@ ; GCN-NEXT: [[TMP6:%.*]] = bitcast i16 [[EXTRACTED1]] to half ; GCN-NEXT: ret half [[TMP6]] ; - %res = atomicrmw fmax half addrspace(1)* %ptr, half %value seq_cst, align 4 + %res = atomicrmw fmax ptr addrspace(1) %ptr, half %value seq_cst, align 4 ret half %res } -define half @test_atomicrmw_fmax_f16_local(half addrspace(3)* %ptr, half %value) { +define half @test_atomicrmw_fmax_f16_local(ptr addrspace(3) %ptr, half %value) { ; GCN-LABEL: @test_atomicrmw_fmax_f16_local( -; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4) -; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64 +; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4) +; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64 ; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)* -; GCN-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4 +; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -192,7 +185,7 @@ ; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GCN-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 ; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 ; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -202,21 +195,20 @@ ; GCN-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half ; GCN-NEXT: ret half [[TMP8]] ; - %res = atomicrmw fmax half addrspace(3)* %ptr, half %value seq_cst + %res = atomicrmw fmax ptr addrspace(3) %ptr, half %value seq_cst ret half %res } -define double @test_atomicrmw_fmax_f64_flat(double* %ptr, double %value) { +define double @test_atomicrmw_fmax_f64_flat(ptr %ptr, double %value) { ; GCN-LABEL: @test_atomicrmw_fmax_f64_flat( -; GCN-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; GCN-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[TMP2:%.*]] = call double @llvm.maxnum.f64(double [[LOADED]], double [[VALUE:%.*]]) -; GCN-NEXT: [[TMP3:%.*]] = bitcast double* [[PTR]] to i64* ; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[TMP2]] to i64 ; GCN-NEXT: [[TMP5:%.*]] = bitcast double [[LOADED]] to i64 -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i64* [[TMP3]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0 ; GCN-NEXT: [[TMP7]] = bitcast i64 [[NEWLOADED]] to double @@ -224,21 +216,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret double [[TMP7]] ; - %res = atomicrmw fmax double* %ptr, double %value seq_cst + %res = atomicrmw fmax ptr %ptr, double %value seq_cst ret double %res } -define double @test_atomicrmw_fmax_f64_global(double addrspace(1)* %ptr, double %value) { +define double @test_atomicrmw_fmax_f64_global(ptr addrspace(1) %ptr, double %value) { ; GCN-LABEL: @test_atomicrmw_fmax_f64_global( -; GCN-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8 +; GCN-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[TMP2:%.*]] = call double @llvm.maxnum.f64(double [[LOADED]], double [[VALUE:%.*]]) -; GCN-NEXT: [[TMP3:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)* ; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[TMP2]] to i64 ; GCN-NEXT: [[TMP5:%.*]] = bitcast double [[LOADED]] to i64 -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i64 addrspace(1)* [[TMP3]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0 ; GCN-NEXT: [[TMP7]] = bitcast i64 [[NEWLOADED]] to double @@ -246,21 +237,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret double [[TMP7]] ; - %res = atomicrmw fmax double addrspace(1)* %ptr, double %value seq_cst + %res = atomicrmw fmax ptr addrspace(1) %ptr, double %value seq_cst ret double %res } -define double @test_atomicrmw_fmax_f64_local(double addrspace(3)* %ptr, double %value) { +define double @test_atomicrmw_fmax_f64_local(ptr addrspace(3) %ptr, double %value) { ; GCN-LABEL: @test_atomicrmw_fmax_f64_local( -; GCN-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8 +; GCN-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[TMP2:%.*]] = call double @llvm.maxnum.f64(double [[LOADED]], double [[VALUE:%.*]]) -; GCN-NEXT: [[TMP3:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)* ; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[TMP2]] to i64 ; GCN-NEXT: [[TMP5:%.*]] = bitcast double [[LOADED]] to i64 -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i64 addrspace(3)* [[TMP3]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0 ; GCN-NEXT: [[TMP7]] = bitcast i64 [[NEWLOADED]] to double @@ -268,6 +258,6 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret double [[TMP7]] ; - %res = atomicrmw fmax double addrspace(3)* %ptr, double %value seq_cst + %res = atomicrmw fmax ptr addrspace(3) %ptr, double %value seq_cst ret double %res } diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmin.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmin.ll --- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmin.ll +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fmin.ll @@ -2,17 +2,16 @@ ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -atomic-expand %s | FileCheck -check-prefix=GCN %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -atomic-expand %s | FileCheck -check-prefix=GCN %s -define float @test_atomicrmw_fmin_f32_flat(float* %ptr, float %value) { +define float @test_atomicrmw_fmin_f32_flat(ptr %ptr, float %value) { ; GCN-LABEL: @test_atomicrmw_fmin_f32_flat( -; GCN-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; GCN-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[TMP2:%.*]] = call float @llvm.minnum.f32(float [[LOADED]], float [[VALUE:%.*]]) -; GCN-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i32* ; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[TMP2]] to i32 ; GCN-NEXT: [[TMP5:%.*]] = bitcast float [[LOADED]] to i32 -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[TMP3]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GCN-NEXT: [[TMP7]] = bitcast i32 [[NEWLOADED]] to float @@ -20,21 +19,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret float [[TMP7]] ; - %res = atomicrmw fmin float* %ptr, float %value seq_cst + %res = atomicrmw fmin ptr %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fmin_f32_global(float addrspace(1)* %ptr, float %value) { +define float @test_atomicrmw_fmin_f32_global(ptr addrspace(1) %ptr, float %value) { ; GCN-LABEL: @test_atomicrmw_fmin_f32_global( -; GCN-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GCN-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[TMP2:%.*]] = call float @llvm.minnum.f32(float [[LOADED]], float [[VALUE:%.*]]) -; GCN-NEXT: [[TMP3:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[TMP2]] to i32 ; GCN-NEXT: [[TMP5:%.*]] = bitcast float [[LOADED]] to i32 -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[TMP3]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GCN-NEXT: [[TMP7]] = bitcast i32 [[NEWLOADED]] to float @@ -42,21 +40,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret float [[TMP7]] ; - %res = atomicrmw fmin float addrspace(1)* %ptr, float %value seq_cst + %res = atomicrmw fmin ptr addrspace(1) %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fmin_f32_local(float addrspace(3)* %ptr, float %value) { +define float @test_atomicrmw_fmin_f32_local(ptr addrspace(3) %ptr, float %value) { ; GCN-LABEL: @test_atomicrmw_fmin_f32_local( -; GCN-NEXT: [[TMP1:%.*]] = load float, float addrspace(3)* [[PTR:%.*]], align 4 +; GCN-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(3) [[PTR:%.*]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[TMP2:%.*]] = call float @llvm.minnum.f32(float [[LOADED]], float [[VALUE:%.*]]) -; GCN-NEXT: [[TMP3:%.*]] = bitcast float addrspace(3)* [[PTR]] to i32 addrspace(3)* ; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[TMP2]] to i32 ; GCN-NEXT: [[TMP5:%.*]] = bitcast float [[LOADED]] to i32 -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[TMP3]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i32 [[TMP5]], i32 [[TMP4]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GCN-NEXT: [[TMP7]] = bitcast i32 [[NEWLOADED]] to float @@ -64,21 +61,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret float [[TMP7]] ; - %res = atomicrmw fmin float addrspace(3)* %ptr, float %value seq_cst + %res = atomicrmw fmin ptr addrspace(3) %ptr, float %value seq_cst ret float %res } -define half @test_atomicrmw_fmin_f16_flat(half* %ptr, half %value) { +define half @test_atomicrmw_fmin_f16_flat(ptr %ptr, half %value) { ; GCN-LABEL: @test_atomicrmw_fmin_f16_flat( -; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4) -; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64 +; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4) +; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64 ; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32* -; GCN-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -91,7 +87,7 @@ ; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GCN-NEXT: [[TMP7:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP7:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 ; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 ; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -101,21 +97,20 @@ ; GCN-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half ; GCN-NEXT: ret half [[TMP8]] ; - %res = atomicrmw fmin half* %ptr, half %value seq_cst + %res = atomicrmw fmin ptr %ptr, half %value seq_cst ret half %res } -define half @test_atomicrmw_fmin_f16_global(half addrspace(1)* %ptr, half %value) { +define half @test_atomicrmw_fmin_f16_global(ptr addrspace(1) %ptr, half %value) { ; GCN-LABEL: @test_atomicrmw_fmin_f16_global( -; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4) -; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64 +; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; GCN-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -128,7 +123,7 @@ ; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GCN-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 ; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 ; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -138,14 +133,13 @@ ; GCN-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half ; GCN-NEXT: ret half [[TMP8]] ; - %res = atomicrmw fmin half addrspace(1)* %ptr, half %value seq_cst + %res = atomicrmw fmin ptr addrspace(1) %ptr, half %value seq_cst ret half %res } -define half @test_atomicrmw_fmin_f16_global_align4(half addrspace(1)* %ptr, half %value) { +define half @test_atomicrmw_fmin_f16_global_align4(ptr addrspace(1) %ptr, half %value) { ; GCN-LABEL: @test_atomicrmw_fmin_f16_global_align4( -; GCN-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)* -; GCN-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4 +; GCN-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -156,7 +150,7 @@ ; GCN-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP4]] to i32 ; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536 ; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]] -; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -165,21 +159,20 @@ ; GCN-NEXT: [[TMP6:%.*]] = bitcast i16 [[EXTRACTED1]] to half ; GCN-NEXT: ret half [[TMP6]] ; - %res = atomicrmw fmin half addrspace(1)* %ptr, half %value seq_cst, align 4 + %res = atomicrmw fmin ptr addrspace(1) %ptr, half %value seq_cst, align 4 ret half %res } -define half @test_atomicrmw_fmin_f16_local(half addrspace(3)* %ptr, half %value) { +define half @test_atomicrmw_fmin_f16_local(ptr addrspace(3) %ptr, half %value) { ; GCN-LABEL: @test_atomicrmw_fmin_f16_local( -; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4) -; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64 +; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4) +; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64 ; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)* -; GCN-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4 +; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -192,7 +185,7 @@ ; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GCN-NEXT: [[TMP7:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 ; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 ; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -202,21 +195,20 @@ ; GCN-NEXT: [[TMP8:%.*]] = bitcast i16 [[EXTRACTED4]] to half ; GCN-NEXT: ret half [[TMP8]] ; - %res = atomicrmw fmin half addrspace(3)* %ptr, half %value seq_cst + %res = atomicrmw fmin ptr addrspace(3) %ptr, half %value seq_cst ret half %res } -define double @test_atomicrmw_fmin_f64_flat(double* %ptr, double %value) { +define double @test_atomicrmw_fmin_f64_flat(ptr %ptr, double %value) { ; GCN-LABEL: @test_atomicrmw_fmin_f64_flat( -; GCN-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; GCN-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[TMP2:%.*]] = call double @llvm.minnum.f64(double [[LOADED]], double [[VALUE:%.*]]) -; GCN-NEXT: [[TMP3:%.*]] = bitcast double* [[PTR]] to i64* ; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[TMP2]] to i64 ; GCN-NEXT: [[TMP5:%.*]] = bitcast double [[LOADED]] to i64 -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i64* [[TMP3]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0 ; GCN-NEXT: [[TMP7]] = bitcast i64 [[NEWLOADED]] to double @@ -224,21 +216,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret double [[TMP7]] ; - %res = atomicrmw fmin double* %ptr, double %value seq_cst + %res = atomicrmw fmin ptr %ptr, double %value seq_cst ret double %res } -define double @test_atomicrmw_fmin_f64_global(double addrspace(1)* %ptr, double %value) { +define double @test_atomicrmw_fmin_f64_global(ptr addrspace(1) %ptr, double %value) { ; GCN-LABEL: @test_atomicrmw_fmin_f64_global( -; GCN-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8 +; GCN-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[TMP2:%.*]] = call double @llvm.minnum.f64(double [[LOADED]], double [[VALUE:%.*]]) -; GCN-NEXT: [[TMP3:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)* ; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[TMP2]] to i64 ; GCN-NEXT: [[TMP5:%.*]] = bitcast double [[LOADED]] to i64 -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i64 addrspace(1)* [[TMP3]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0 ; GCN-NEXT: [[TMP7]] = bitcast i64 [[NEWLOADED]] to double @@ -246,21 +237,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret double [[TMP7]] ; - %res = atomicrmw fmin double addrspace(1)* %ptr, double %value seq_cst + %res = atomicrmw fmin ptr addrspace(1) %ptr, double %value seq_cst ret double %res } -define double @test_atomicrmw_fmin_f64_local(double addrspace(3)* %ptr, double %value) { +define double @test_atomicrmw_fmin_f64_local(ptr addrspace(3) %ptr, double %value) { ; GCN-LABEL: @test_atomicrmw_fmin_f64_local( -; GCN-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8 +; GCN-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP7:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[TMP2:%.*]] = call double @llvm.minnum.f64(double [[LOADED]], double [[VALUE:%.*]]) -; GCN-NEXT: [[TMP3:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)* ; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[TMP2]] to i64 ; GCN-NEXT: [[TMP5:%.*]] = bitcast double [[LOADED]] to i64 -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i64 addrspace(3)* [[TMP3]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP5]], i64 [[TMP4]] seq_cst seq_cst, align 8 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP6]], 0 ; GCN-NEXT: [[TMP7]] = bitcast i64 [[NEWLOADED]] to double @@ -268,6 +258,6 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret double [[TMP7]] ; - %res = atomicrmw fmin double addrspace(3)* %ptr, double %value seq_cst + %res = atomicrmw fmin ptr addrspace(3) %ptr, double %value seq_cst ret double %res } diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fsub.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fsub.ll --- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fsub.ll +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-fsub.ll @@ -2,17 +2,16 @@ ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -atomic-expand %s | FileCheck -check-prefix=GCN %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -atomic-expand %s | FileCheck -check-prefix=GCN %s -define float @test_atomicrmw_fsub_f32_flat(float* %ptr, float %value) { +define float @test_atomicrmw_fsub_f32_flat(ptr %ptr, float %value) { ; GCN-LABEL: @test_atomicrmw_fsub_f32_flat( -; GCN-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; GCN-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]] -; GCN-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; GCN-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GCN-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -20,21 +19,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fsub float* %ptr, float %value seq_cst + %res = atomicrmw fsub ptr %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fsub_f32_global(float addrspace(1)* %ptr, float %value) { +define float @test_atomicrmw_fsub_f32_global(ptr addrspace(1) %ptr, float %value) { ; GCN-LABEL: @test_atomicrmw_fsub_f32_global( -; GCN-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; GCN-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]] -; GCN-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; GCN-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GCN-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -42,21 +40,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fsub float addrspace(1)* %ptr, float %value seq_cst + %res = atomicrmw fsub ptr addrspace(1) %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fsub_f32_local(float addrspace(3)* %ptr, float %value) { +define float @test_atomicrmw_fsub_f32_local(ptr addrspace(3) %ptr, float %value) { ; GCN-LABEL: @test_atomicrmw_fsub_f32_local( -; GCN-NEXT: [[TMP1:%.*]] = load float, float addrspace(3)* [[PTR:%.*]], align 4 +; GCN-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(3) [[PTR:%.*]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]] -; GCN-NEXT: [[TMP2:%.*]] = bitcast float addrspace(3)* [[PTR]] to i32 addrspace(3)* ; GCN-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; GCN-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(3)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; GCN-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -64,21 +61,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fsub float addrspace(3)* %ptr, float %value seq_cst + %res = atomicrmw fsub ptr addrspace(3) %ptr, float %value seq_cst ret float %res } -define half @test_atomicrmw_fsub_f16_flat(half* %ptr, half %value) { +define half @test_atomicrmw_fsub_f16_flat(ptr %ptr, half %value) { ; GCN-LABEL: @test_atomicrmw_fsub_f16_flat( -; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4) -; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64 +; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4) +; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64 ; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32* -; GCN-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -91,7 +87,7 @@ ; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -101,21 +97,20 @@ ; GCN-NEXT: [[TMP7:%.*]] = bitcast i16 [[EXTRACTED4]] to half ; GCN-NEXT: ret half [[TMP7]] ; - %res = atomicrmw fsub half* %ptr, half %value seq_cst + %res = atomicrmw fsub ptr %ptr, half %value seq_cst ret half %res } -define half @test_atomicrmw_fsub_f16_global(half addrspace(1)* %ptr, half %value) { +define half @test_atomicrmw_fsub_f16_global(ptr addrspace(1) %ptr, half %value) { ; GCN-LABEL: @test_atomicrmw_fsub_f16_global( -; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(1)* @llvm.ptrmask.p1f16.i64(half addrspace(1)* [[PTR:%.*]], i64 -4) -; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(1)* [[PTR]] to i64 +; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR:%.*]], i64 -4) +; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 ; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(1)* [[ALIGNEDADDR]] to i32 addrspace(1)* -; GCN-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR1]], align 4 +; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -128,7 +123,7 @@ ; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -138,14 +133,13 @@ ; GCN-NEXT: [[TMP7:%.*]] = bitcast i16 [[EXTRACTED4]] to half ; GCN-NEXT: ret half [[TMP7]] ; - %res = atomicrmw fsub half addrspace(1)* %ptr, half %value seq_cst + %res = atomicrmw fsub ptr addrspace(1) %ptr, half %value seq_cst ret half %res } -define half @test_atomicrmw_fsub_f16_global_align4(half addrspace(1)* %ptr, half %value) { +define half @test_atomicrmw_fsub_f16_global_align4(ptr addrspace(1) %ptr, half %value) { ; GCN-LABEL: @test_atomicrmw_fsub_f16_global_align4( -; GCN-NEXT: [[ALIGNEDADDR:%.*]] = bitcast half addrspace(1)* [[PTR:%.*]] to i32 addrspace(1)* -; GCN-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[ALIGNEDADDR]], align 4 +; GCN-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -156,7 +150,7 @@ ; GCN-NEXT: [[EXTENDED:%.*]] = zext i16 [[TMP3]] to i32 ; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], -65536 ; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[EXTENDED]] -; GCN-NEXT: [[TMP4:%.*]] = cmpxchg i32 addrspace(1)* [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP4:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1 ; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP4]], 0 ; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -165,21 +159,20 @@ ; GCN-NEXT: [[TMP5:%.*]] = bitcast i16 [[EXTRACTED1]] to half ; GCN-NEXT: ret half [[TMP5]] ; - %res = atomicrmw fsub half addrspace(1)* %ptr, half %value seq_cst, align 4 + %res = atomicrmw fsub ptr addrspace(1) %ptr, half %value seq_cst, align 4 ret half %res } -define half @test_atomicrmw_fsub_f16_local(half addrspace(3)* %ptr, half %value) { +define half @test_atomicrmw_fsub_f16_local(ptr addrspace(3) %ptr, half %value) { ; GCN-LABEL: @test_atomicrmw_fsub_f16_local( -; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call half addrspace(3)* @llvm.ptrmask.p3f16.i64(half addrspace(3)* [[PTR:%.*]], i64 -4) -; GCN-NEXT: [[TMP1:%.*]] = ptrtoint half addrspace(3)* [[PTR]] to i64 +; GCN-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(3) @llvm.ptrmask.p3.i64(ptr addrspace(3) [[PTR:%.*]], i64 -4) +; GCN-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(3) [[PTR]] to i64 ; GCN-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; GCN-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 ; GCN-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; GCN-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; GCN-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; GCN-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half addrspace(3)* [[ALIGNEDADDR]] to i32 addrspace(3)* -; GCN-NEXT: [[TMP3:%.*]] = load i32, i32 addrspace(3)* [[ALIGNEDADDR1]], align 4 +; GCN-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) [[ALIGNEDADDR]], align 4 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -192,7 +185,7 @@ ; GCN-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; GCN-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; GCN-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; GCN-NEXT: [[TMP6:%.*]] = cmpxchg i32 addrspace(3)* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 +; GCN-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(3) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] seq_cst seq_cst, align 4 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; GCN-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; GCN-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -202,21 +195,20 @@ ; GCN-NEXT: [[TMP7:%.*]] = bitcast i16 [[EXTRACTED4]] to half ; GCN-NEXT: ret half [[TMP7]] ; - %res = atomicrmw fsub half addrspace(3)* %ptr, half %value seq_cst + %res = atomicrmw fsub ptr addrspace(3) %ptr, half %value seq_cst ret half %res } -define double @test_atomicrmw_fsub_f64_flat(double* %ptr, double %value) { +define double @test_atomicrmw_fsub_f64_flat(ptr %ptr, double %value) { ; GCN-LABEL: @test_atomicrmw_fsub_f64_flat( -; GCN-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; GCN-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[NEW:%.*]] = fsub double [[LOADED]], [[VALUE:%.*]] -; GCN-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64* ; GCN-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GCN-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -224,21 +216,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret double [[TMP6]] ; - %res = atomicrmw fsub double* %ptr, double %value seq_cst + %res = atomicrmw fsub ptr %ptr, double %value seq_cst ret double %res } -define double @test_atomicrmw_fsub_f64_global(double addrspace(1)* %ptr, double %value) { +define double @test_atomicrmw_fsub_f64_global(ptr addrspace(1) %ptr, double %value) { ; GCN-LABEL: @test_atomicrmw_fsub_f64_global( -; GCN-NEXT: [[TMP1:%.*]] = load double, double addrspace(1)* [[PTR:%.*]], align 8 +; GCN-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(1) [[PTR:%.*]], align 8 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[NEW:%.*]] = fsub double [[LOADED]], [[VALUE:%.*]] -; GCN-NEXT: [[TMP2:%.*]] = bitcast double addrspace(1)* [[PTR]] to i64 addrspace(1)* ; GCN-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(1)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GCN-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -246,21 +237,20 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret double [[TMP6]] ; - %res = atomicrmw fsub double addrspace(1)* %ptr, double %value seq_cst + %res = atomicrmw fsub ptr addrspace(1) %ptr, double %value seq_cst ret double %res } -define double @test_atomicrmw_fsub_f64_local(double addrspace(3)* %ptr, double %value) { +define double @test_atomicrmw_fsub_f64_local(ptr addrspace(3) %ptr, double %value) { ; GCN-LABEL: @test_atomicrmw_fsub_f64_local( -; GCN-NEXT: [[TMP1:%.*]] = load double, double addrspace(3)* [[PTR:%.*]], align 8 +; GCN-NEXT: [[TMP1:%.*]] = load double, ptr addrspace(3) [[PTR:%.*]], align 8 ; GCN-NEXT: br label [[ATOMICRMW_START:%.*]] ; GCN: atomicrmw.start: ; GCN-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; GCN-NEXT: [[NEW:%.*]] = fsub double [[LOADED]], [[VALUE:%.*]] -; GCN-NEXT: [[TMP2:%.*]] = bitcast double addrspace(3)* [[PTR]] to i64 addrspace(3)* ; GCN-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; GCN-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; GCN-NEXT: [[TMP5:%.*]] = cmpxchg i64 addrspace(3)* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 +; GCN-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst, align 8 ; GCN-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; GCN-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; GCN-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -268,6 +258,6 @@ ; GCN: atomicrmw.end: ; GCN-NEXT: ret double [[TMP6]] ; - %res = atomicrmw fsub double addrspace(3)* %ptr, double %value seq_cst + %res = atomicrmw fsub ptr addrspace(3) %ptr, double %value seq_cst ret double %res } diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-nand.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-nand.ll --- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-nand.ll +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-rmw-nand.ll @@ -2,59 +2,59 @@ ; RUN: opt -mtriple=amdgcn-amd-amdhsa -S -atomic-expand %s | FileCheck %s ; RUN: opt -mtriple=r600-mesa-mesa3d -S -atomic-expand %s | FileCheck %s -define i32 @test_atomicrmw_nand_i32_flat(i32* %ptr, i32 %value) { +define i32 @test_atomicrmw_nand_i32_flat(ptr %ptr, i32 %value) { ; CHECK-LABEL: @test_atomicrmw_nand_i32_flat( -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[LOADED]], [[VALUE:%.*]] ; CHECK-NEXT: [[NEW:%.*]] = xor i32 [[TMP2]], -1 -; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i32* [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst +; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg ptr [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP3]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP3]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret i32 [[NEWLOADED]] ; - %res = atomicrmw nand i32* %ptr, i32 %value seq_cst + %res = atomicrmw nand ptr %ptr, i32 %value seq_cst ret i32 %res } -define i32 @test_atomicrmw_nand_i32_global(i32 addrspace(1)* %ptr, i32 %value) { +define i32 @test_atomicrmw_nand_i32_global(ptr addrspace(1) %ptr, i32 %value) { ; CHECK-LABEL: @test_atomicrmw_nand_i32_global( -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(1)* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[LOADED]], [[VALUE:%.*]] ; CHECK-NEXT: [[NEW:%.*]] = xor i32 [[TMP2]], -1 -; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i32 addrspace(1)* [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst +; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP3]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP3]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret i32 [[NEWLOADED]] ; - %res = atomicrmw nand i32 addrspace(1)* %ptr, i32 %value seq_cst + %res = atomicrmw nand ptr addrspace(1) %ptr, i32 %value seq_cst ret i32 %res } -define i32 @test_atomicrmw_nand_i32_local(i32 addrspace(3)* %ptr, i32 %value) { +define i32 @test_atomicrmw_nand_i32_local(ptr addrspace(3) %ptr, i32 %value) { ; CHECK-LABEL: @test_atomicrmw_nand_i32_local( -; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32 addrspace(3)* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(3) [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP1]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[LOADED]], [[VALUE:%.*]] ; CHECK-NEXT: [[NEW:%.*]] = xor i32 [[TMP2]], -1 -; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i32 addrspace(3)* [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst +; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg ptr addrspace(3) [[PTR]], i32 [[LOADED]], i32 [[NEW]] seq_cst seq_cst ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP3]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP3]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret i32 [[NEWLOADED]] ; - %res = atomicrmw nand i32 addrspace(3)* %ptr, i32 %value seq_cst + %res = atomicrmw nand ptr addrspace(3) %ptr, i32 %value seq_cst ret i32 %res } diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/unaligned-atomic.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/unaligned-atomic.ll --- a/llvm/test/Transforms/AtomicExpand/AMDGPU/unaligned-atomic.ll +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/unaligned-atomic.ll @@ -2,34 +2,30 @@ ; The AtomicExpand pass cannot handle missing libcalls (yet) so reports a fatal error. ; CHECK: LLVM ERROR: expandAtomicOpToLibcall shouldn't fail for Load -define i32 @atomic_load_global_align1(i32 addrspace(1)* %ptr) { +define i32 @atomic_load_global_align1(ptr addrspace(1) %ptr) { ; GCN-LABEL: @atomic_load_global_align1( -; GCN-NEXT: [[TMP1:%.*]] = bitcast i32 addrspace(1)* [[PTR:%.*]] to i8 addrspace(1)* -; GCN-NEXT: [[TMP2:%.*]] = addrspacecast i8 addrspace(1)* [[TMP1]] to i8* +; GCN-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(1) [[PTR:%.*]] to ptr ; GCN-NEXT: [[TMP3:%.*]] = alloca i32, align 4 -; GCN-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP3]] to i8* -; GCN-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) -; GCN-NEXT: call void @0(i64 4, i8* [[TMP2]], i8* [[TMP4]], i32 5) -; GCN-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP3]], align 4 -; GCN-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP4]]) +; GCN-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP3]]) +; GCN-NEXT: call void @0(i64 4, ptr [[TMP2]], ptr [[TMP3]], i32 5) +; GCN-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP3]], align 4 +; GCN-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP3]]) ; GCN-NEXT: ret i32 [[TMP5]] ; - %val = load atomic i32, i32 addrspace(1)* %ptr seq_cst, align 1 + %val = load atomic i32, ptr addrspace(1) %ptr seq_cst, align 1 ret i32 %val } -define void @atomic_store_global_align1(i32 addrspace(1)* %ptr, i32 %val) { +define void @atomic_store_global_align1(ptr addrspace(1) %ptr, i32 %val) { ; GCN-LABEL: @atomic_store_global_align1( -; GCN-NEXT: [[TMP1:%.*]] = bitcast i32 addrspace(1)* [[PTR:%.*]] to i8 addrspace(1)* -; GCN-NEXT: [[TMP2:%.*]] = addrspacecast i8 addrspace(1)* [[TMP1]] to i8* +; GCN-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(1) [[PTR:%.*]] to ptr ; GCN-NEXT: [[TMP3:%.*]] = alloca i32, align 4 -; GCN-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP3]] to i8* -; GCN-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) -; GCN-NEXT: store i32 [[VAL:%.*]], i32* [[TMP3]], align 4 -; GCN-NEXT: call void @1(i64 4, i8* [[TMP2]], i8* [[TMP4]], i32 0) -; GCN-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP4]]) +; GCN-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP3]]) +; GCN-NEXT: store i32 [[VAL:%.*]], ptr [[TMP3]], align 4 +; GCN-NEXT: call void @1(i64 4, ptr [[TMP2]], ptr [[TMP3]], i32 0) +; GCN-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP3]]) ; GCN-NEXT: ret void ; - store atomic i32 %val, i32 addrspace(1)* %ptr monotonic, align 1 + store atomic i32 %val, ptr addrspace(1) %ptr monotonic, align 1 ret void } diff --git a/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll b/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll --- a/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll +++ b/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v7.ll @@ -1,105 +1,104 @@ ; RUN: opt -S -o - -mtriple=armv7-apple-ios7.0 -atomic-expand -codegen-opt-level=1 %s | FileCheck %s -define i8 @test_atomic_xchg_i8(i8* %ptr, i8 %xchgend) { +define i8 @test_atomic_xchg_i8(ptr %ptr, i8 %xchgend) { ; CHECK-LABEL: @test_atomic_xchg_i8 ; CHECK-NOT: dmb ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[NEWVAL32:%.*]] = zext i8 %xchgend to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK-NOT: dmb ; CHECK: ret i8 [[OLDVAL]] - %res = atomicrmw xchg i8* %ptr, i8 %xchgend monotonic + %res = atomicrmw xchg ptr %ptr, i8 %xchgend monotonic ret i8 %res } -define i16 @test_atomic_add_i16(i16* %ptr, i16 %addend) { +define i16 @test_atomic_add_i16(ptr %ptr, i16 %addend) { ; CHECK-LABEL: @test_atomic_add_i16 ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16 ; CHECK: [[NEWVAL:%.*]] = add i16 [[OLDVAL]], %addend ; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i16) %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: ret i16 [[OLDVAL]] - %res = atomicrmw add i16* %ptr, i16 %addend seq_cst + %res = atomicrmw add ptr %ptr, i16 %addend seq_cst ret i16 %res } -define i32 @test_atomic_sub_i32(i32* %ptr, i32 %subend) { +define i32 @test_atomic_sub_i32(ptr %ptr, i32 %subend) { ; CHECK-LABEL: @test_atomic_sub_i32 ; CHECK-NOT: dmb ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %ptr) +; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %ptr) ; CHECK: [[NEWVAL:%.*]] = sub i32 [[OLDVAL]], %subend -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[NEWVAL]], i32* elementtype(i32) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL]], ptr elementtype(i32) %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: ret i32 [[OLDVAL]] - %res = atomicrmw sub i32* %ptr, i32 %subend acquire + %res = atomicrmw sub ptr %ptr, i32 %subend acquire ret i32 %res } -define i8 @test_atomic_and_i8(i8* %ptr, i8 %andend) { +define i8 @test_atomic_and_i8(ptr %ptr, i8 %andend) { ; CHECK-LABEL: @test_atomic_and_i8 ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[NEWVAL:%.*]] = and i8 [[OLDVAL]], %andend ; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK-NOT: dmb ; CHECK: ret i8 [[OLDVAL]] - %res = atomicrmw and i8* %ptr, i8 %andend release + %res = atomicrmw and ptr %ptr, i8 %andend release ret i8 %res } -define i16 @test_atomic_nand_i16(i16* %ptr, i16 %nandend) { +define i16 @test_atomic_nand_i16(ptr %ptr, i16 %nandend) { ; CHECK-LABEL: @test_atomic_nand_i16 ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16 ; CHECK: [[NEWVAL_TMP:%.*]] = and i16 [[OLDVAL]], %nandend ; CHECK: [[NEWVAL:%.*]] = xor i16 [[NEWVAL_TMP]], -1 ; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i16) %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: ret i16 [[OLDVAL]] - %res = atomicrmw nand i16* %ptr, i16 %nandend seq_cst + %res = atomicrmw nand ptr %ptr, i16 %nandend seq_cst ret i16 %res } -define i64 @test_atomic_or_i64(i64* %ptr, i64 %orend) { +define i64 @test_atomic_or_i64(ptr %ptr, i64 %orend) { ; CHECK-LABEL: @test_atomic_or_i64 ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* -; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]]) +; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(ptr %ptr) ; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 ; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 ; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64 @@ -110,122 +109,121 @@ ; CHECK: [[NEWLO:%.*]] = trunc i64 [[NEWVAL]] to i32 ; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 [[NEWVAL]], 32 ; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32 -; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]]) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], ptr %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: ret i64 [[OLDVAL]] - %res = atomicrmw or i64* %ptr, i64 %orend seq_cst + %res = atomicrmw or ptr %ptr, i64 %orend seq_cst ret i64 %res } -define i8 @test_atomic_xor_i8(i8* %ptr, i8 %xorend) { +define i8 @test_atomic_xor_i8(ptr %ptr, i8 %xorend) { ; CHECK-LABEL: @test_atomic_xor_i8 ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[NEWVAL:%.*]] = xor i8 [[OLDVAL]], %xorend ; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: ret i8 [[OLDVAL]] - %res = atomicrmw xor i8* %ptr, i8 %xorend seq_cst + %res = atomicrmw xor ptr %ptr, i8 %xorend seq_cst ret i8 %res } -define i8 @test_atomic_max_i8(i8* %ptr, i8 %maxend) { +define i8 @test_atomic_max_i8(ptr %ptr, i8 %maxend) { ; CHECK-LABEL: @test_atomic_max_i8 ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[WANT_OLD:%.*]] = icmp sgt i8 [[OLDVAL]], %maxend ; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %maxend ; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: ret i8 [[OLDVAL]] - %res = atomicrmw max i8* %ptr, i8 %maxend seq_cst + %res = atomicrmw max ptr %ptr, i8 %maxend seq_cst ret i8 %res } -define i8 @test_atomic_min_i8(i8* %ptr, i8 %minend) { +define i8 @test_atomic_min_i8(ptr %ptr, i8 %minend) { ; CHECK-LABEL: @test_atomic_min_i8 ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[WANT_OLD:%.*]] = icmp sle i8 [[OLDVAL]], %minend ; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %minend ; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: ret i8 [[OLDVAL]] - %res = atomicrmw min i8* %ptr, i8 %minend seq_cst + %res = atomicrmw min ptr %ptr, i8 %minend seq_cst ret i8 %res } -define i8 @test_atomic_umax_i8(i8* %ptr, i8 %umaxend) { +define i8 @test_atomic_umax_i8(ptr %ptr, i8 %umaxend) { ; CHECK-LABEL: @test_atomic_umax_i8 ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[WANT_OLD:%.*]] = icmp ugt i8 [[OLDVAL]], %umaxend ; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %umaxend ; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: ret i8 [[OLDVAL]] - %res = atomicrmw umax i8* %ptr, i8 %umaxend seq_cst + %res = atomicrmw umax ptr %ptr, i8 %umaxend seq_cst ret i8 %res } -define i8 @test_atomic_umin_i8(i8* %ptr, i8 %uminend) { +define i8 @test_atomic_umin_i8(ptr %ptr, i8 %uminend) { ; CHECK-LABEL: @test_atomic_umin_i8 ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[WANT_OLD:%.*]] = icmp ule i8 [[OLDVAL]], %uminend ; CHECK: [[NEWVAL:%.*]] = select i1 [[WANT_OLD]], i8 [[OLDVAL]], i8 %uminend ; CHECK: [[NEWVAL32:%.*]] = zext i8 [[NEWVAL]] to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: ret i8 [[OLDVAL]] - %res = atomicrmw umin i8* %ptr, i8 %uminend seq_cst + %res = atomicrmw umin ptr %ptr, i8 %uminend seq_cst ret i8 %res } -define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) { +define i8 @test_cmpxchg_i8_seqcst_seqcst(ptr %ptr, i8 %desired, i8 %newval) { ; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst ; CHECK: br label %[[START:.*]] ; CHECK: [[START]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] @@ -237,12 +235,12 @@ ; CHECK: [[LOOP]]: ; CHECK: [[LOADED_LOOP:%.*]] = phi i8 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ] ; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD]] ; CHECK: [[RELEASED_LOAD]]: -; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr) +; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i8 ; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i8 [[OLDVAL_LOOP]], %desired ; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]] @@ -266,17 +264,17 @@ ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i8 [[LOADED]] - %pairold = cmpxchg i8* %ptr, i8 %desired, i8 %newval seq_cst seq_cst + %pairold = cmpxchg ptr %ptr, i8 %desired, i8 %newval seq_cst seq_cst %old = extractvalue { i8, i1 } %pairold, 0 ret i8 %old } -define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newval) { +define i16 @test_cmpxchg_i16_seqcst_monotonic(ptr %ptr, i16 %desired, i16 %newval) { ; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16 ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] @@ -288,12 +286,12 @@ ; CHECK: [[LOOP]]: ; CHECK: [[LOADED_LOOP:%.*]] = phi i16 [ [[OLDVAL]], %[[FENCED_STORE]] ], [ [[OLDVAL_LOOP:%.*]], %[[RELEASED_LOAD:.*]] ] ; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i16) %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[RELEASED_LOAD:.*]] ; CHECK: [[RELEASED_LOAD]]: -; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0i16(i16* elementtype(i16) %ptr) +; CHECK: [[OLDVAL32_LOOP:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i16) %ptr) ; CHECK: [[OLDVAL_LOOP]] = trunc i32 [[OLDVAL32_LOOP]] to i16 ; CHECK: [[SHOULD_STORE_LOOP:%.*]] = icmp eq i16 [[OLDVAL_LOOP]], %desired ; CHECK: br i1 [[SHOULD_STORE_LOOP]], label %[[LOOP]], label %[[NO_STORE_BB]] @@ -317,18 +315,18 @@ ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i16 [[LOADED]] - %pairold = cmpxchg i16* %ptr, i16 %desired, i16 %newval seq_cst monotonic + %pairold = cmpxchg ptr %ptr, i16 %desired, i16 %newval seq_cst monotonic %old = extractvalue { i16, i1 } %pairold, 0 ret i16 %old } -define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newval) { +define i32 @test_cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %desired, i32 %newval) { ; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire ; CHECK-NOT: dmb ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %ptr) +; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %ptr) ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] @@ -337,7 +335,7 @@ ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[OLDVAL]], %[[FENCED_STORE]] ] -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* elementtype(i32) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 %newval, ptr elementtype(i32) %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] @@ -360,19 +358,18 @@ ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i32 [[LOADED_EXIT]] - %pairold = cmpxchg i32* %ptr, i32 %desired, i32 %newval acquire acquire + %pairold = cmpxchg ptr %ptr, i32 %desired, i32 %newval acquire acquire %old = extractvalue { i32, i1 } %pairold, 0 ret i32 %old } -define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %newval) { +define i64 @test_cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %desired, i64 %newval) { ; CHECK-LABEL: @test_cmpxchg_i64_monotonic_monotonic ; CHECK-NOT: dmb ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* -; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]]) +; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(ptr %ptr) ; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 ; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 ; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64 @@ -390,8 +387,7 @@ ; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32 ; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 %newval, 32 ; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32 -; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]]) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], ptr %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] @@ -414,18 +410,18 @@ ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i64 [[LOADED_EXIT]] - %pairold = cmpxchg i64* %ptr, i64 %desired, i64 %newval monotonic monotonic + %pairold = cmpxchg ptr %ptr, i64 %desired, i64 %newval monotonic monotonic %old = extractvalue { i64, i1 } %pairold, 0 ret i64 %old } -define i32 @test_cmpxchg_minsize(i32* %addr, i32 %desired, i32 %new) minsize { +define i32 @test_cmpxchg_minsize(ptr %addr, i32 %desired, i32 %new) minsize { ; CHECK-LABEL: @test_cmpxchg_minsize ; CHECK: call void @llvm.arm.dmb(i32 11) ; CHECK: br label %[[START:.*]] ; CHECK: [[START]]: -; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr) +; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr) ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] @@ -434,7 +430,7 @@ ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ] -; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr) +; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0(i32 %new, ptr elementtype(i32) %addr) ; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 ; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[START]] @@ -457,7 +453,7 @@ ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i32 [[LOADED_EXIT]] - %pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst + %pair = cmpxchg ptr %addr, i32 %desired, i32 %new seq_cst seq_cst %oldval = extractvalue { i32, i1 } %pair, 0 ret i32 %oldval } diff --git a/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll b/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll --- a/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll +++ b/llvm/test/Transforms/AtomicExpand/ARM/atomic-expansion-v8.ll @@ -1,66 +1,65 @@ ; RUN: opt -S -o - -mtriple=armv8-linux-gnueabihf -atomic-expand %s -codegen-opt-level=1 | FileCheck %s -define i8 @test_atomic_xchg_i8(i8* %ptr, i8 %xchgend) { +define i8 @test_atomic_xchg_i8(ptr %ptr, i8 %xchgend) { ; CHECK-LABEL: @test_atomic_xchg_i8 ; CHECK-NOT: fence ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0i8(i8* elementtype(i8) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8 ; CHECK: [[NEWVAL32:%.*]] = zext i8 %xchgend to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK-NOT: fence ; CHECK: ret i8 [[OLDVAL]] - %res = atomicrmw xchg i8* %ptr, i8 %xchgend monotonic + %res = atomicrmw xchg ptr %ptr, i8 %xchgend monotonic ret i8 %res } -define i16 @test_atomic_add_i16(i16* %ptr, i16 %addend) { +define i16 @test_atomic_add_i16(ptr %ptr, i16 %addend) { ; CHECK-LABEL: @test_atomic_add_i16 ; CHECK-NOT: fence ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i16(i16* elementtype(i16) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16 ; CHECK: [[NEWVAL:%.*]] = add i16 [[OLDVAL]], %addend ; CHECK: [[NEWVAL32:%.*]] = zext i16 [[NEWVAL]] to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0(i32 [[NEWVAL32]], ptr elementtype(i16) %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK-NOT: fence ; CHECK: ret i16 [[OLDVAL]] - %res = atomicrmw add i16* %ptr, i16 %addend seq_cst + %res = atomicrmw add ptr %ptr, i16 %addend seq_cst ret i16 %res } -define i32 @test_atomic_sub_i32(i32* %ptr, i32 %subend) { +define i32 @test_atomic_sub_i32(ptr %ptr, i32 %subend) { ; CHECK-LABEL: @test_atomic_sub_i32 ; CHECK-NOT: fence ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32) %ptr) +; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %ptr) ; CHECK: [[NEWVAL:%.*]] = sub i32 [[OLDVAL]], %subend -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 [[NEWVAL]], i32* elementtype(i32) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 [[NEWVAL]], ptr elementtype(i32) %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK-NOT: fence ; CHECK: ret i32 [[OLDVAL]] - %res = atomicrmw sub i32* %ptr, i32 %subend acquire + %res = atomicrmw sub ptr %ptr, i32 %subend acquire ret i32 %res } -define i64 @test_atomic_or_i64(i64* %ptr, i64 %orend) { +define i64 @test_atomic_or_i64(ptr %ptr, i64 %orend) { ; CHECK-LABEL: @test_atomic_or_i64 ; CHECK-NOT: fence ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* -; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldaexd(i8* [[PTR8]]) +; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldaexd(ptr %ptr) ; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 ; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 ; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64 @@ -71,24 +70,23 @@ ; CHECK: [[NEWLO:%.*]] = trunc i64 [[NEWVAL]] to i32 ; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 [[NEWVAL]], 32 ; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32 -; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]]) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlexd(i32 [[NEWLO]], i32 [[NEWHI]], ptr %ptr) ; CHECK: [[TST:%.*]] = icmp ne i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[LOOP]], label %[[END:.*]] ; CHECK: [[END]]: ; CHECK-NOT: fence ; CHECK: ret i64 [[OLDVAL]] - %res = atomicrmw or i64* %ptr, i64 %orend seq_cst + %res = atomicrmw or ptr %ptr, i64 %orend seq_cst ret i64 %res } -define i8 @test_cmpxchg_i8_seqcst_seqcst(i8* %ptr, i8 %desired, i8 %newval) { +define i8 @test_cmpxchg_i8_seqcst_seqcst(ptr %ptr, i8 %desired, i8 %newval) { ; CHECK-LABEL: @test_cmpxchg_i8_seqcst_seqcst ; CHECK-NOT: fence ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i8(i8* elementtype(i8) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i8) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i8 ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i8 [[OLDVAL]], %desired ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] @@ -99,7 +97,7 @@ ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i8 [ [[OLDVAL]], %[[FENCED_STORE]] ] ; CHECK: [[NEWVAL32:%.*]] = zext i8 %newval to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i8(i32 [[NEWVAL32]], i8* elementtype(i8) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0(i32 [[NEWVAL32]], ptr elementtype(i8) %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] @@ -122,18 +120,18 @@ ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i8 [[LOADED_EXIT]] - %pairold = cmpxchg i8* %ptr, i8 %desired, i8 %newval seq_cst seq_cst + %pairold = cmpxchg ptr %ptr, i8 %desired, i8 %newval seq_cst seq_cst %old = extractvalue { i8, i1 } %pairold, 0 ret i8 %old } -define i16 @test_cmpxchg_i16_seqcst_monotonic(i16* %ptr, i16 %desired, i16 %newval) { +define i16 @test_cmpxchg_i16_seqcst_monotonic(ptr %ptr, i16 %desired, i16 %newval) { ; CHECK-LABEL: @test_cmpxchg_i16_seqcst_monotonic ; CHECK-NOT: fence ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0i16(i16* elementtype(i16) %ptr) +; CHECK: [[OLDVAL32:%.*]] = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i16) %ptr) ; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16 ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i16 [[OLDVAL]], %desired ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] @@ -144,7 +142,7 @@ ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i16 [ [[OLDVAL]], %[[FENCED_STORE]] ] ; CHECK: [[NEWVAL32:%.*]] = zext i16 %newval to i32 -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0i16(i32 [[NEWVAL32]], i16* elementtype(i16) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.stlex.p0(i32 [[NEWVAL32]], ptr elementtype(i16) %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] @@ -168,18 +166,18 @@ ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i16 [[LOADED_EXIT]] - %pairold = cmpxchg i16* %ptr, i16 %desired, i16 %newval seq_cst monotonic + %pairold = cmpxchg ptr %ptr, i16 %desired, i16 %newval seq_cst monotonic %old = extractvalue { i16, i1 } %pairold, 0 ret i16 %old } -define i32 @test_cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %desired, i32 %newval) { +define i32 @test_cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %desired, i32 %newval) { ; CHECK-LABEL: @test_cmpxchg_i32_acquire_acquire ; CHECK-NOT: fence ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0i32(i32* elementtype(i32) %ptr) +; CHECK: [[OLDVAL:%.*]] = call i32 @llvm.arm.ldaex.p0(ptr elementtype(i32) %ptr) ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[OLDVAL]], %desired ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] @@ -188,7 +186,7 @@ ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[OLDVAL]], %[[FENCED_STORE]] ] -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %newval, i32* elementtype(i32) %ptr) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strex.p0(i32 %newval, ptr elementtype(i32) %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] @@ -211,19 +209,18 @@ ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i32 [[LOADED_EXIT]] - %pairold = cmpxchg i32* %ptr, i32 %desired, i32 %newval acquire acquire + %pairold = cmpxchg ptr %ptr, i32 %desired, i32 %newval acquire acquire %old = extractvalue { i32, i1 } %pairold, 0 ret i32 %old } -define i64 @test_cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %desired, i64 %newval) { +define i64 @test_cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %desired, i64 %newval) { ; CHECK-LABEL: @test_cmpxchg_i64_monotonic_monotonic ; CHECK-NOT: fence ; CHECK: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: -; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* -; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(i8* [[PTR8]]) +; CHECK: [[LOHI:%.*]] = call { i32, i32 } @llvm.arm.ldrexd(ptr %ptr) ; CHECK: [[LO:%.*]] = extractvalue { i32, i32 } [[LOHI]], 0 ; CHECK: [[HI:%.*]] = extractvalue { i32, i32 } [[LOHI]], 1 ; CHECK: [[LO64:%.*]] = zext i32 [[LO]] to i64 @@ -241,8 +238,7 @@ ; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32 ; CHECK: [[NEWHI_TMP:%.*]] = lshr i64 %newval, 32 ; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32 -; CHECK: [[PTR8:%.*]] = bitcast i64* %ptr to i8* -; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]]) +; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], ptr %ptr) ; CHECK: [[TST:%.*]] = icmp eq i32 [[TRYAGAIN]], 0 ; CHECK: br i1 [[TST]], label %[[SUCCESS_BB:.*]], label %[[LOOP]] @@ -265,7 +261,7 @@ ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i64 [[LOADED_EXIT]] - %pairold = cmpxchg i64* %ptr, i64 %desired, i64 %newval monotonic monotonic + %pairold = cmpxchg ptr %ptr, i64 %desired, i64 %newval monotonic monotonic %old = extractvalue { i64, i1 } %pairold, 0 ret i64 %old } diff --git a/llvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll --- a/llvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll +++ b/llvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll @@ -1,18 +1,17 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -mtriple=armv7-apple-ios7.0 -atomic-expand %s | FileCheck %s -define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fadd_f32( ; CHECK-NEXT: call void @llvm.arm.dmb(i32 11) -; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -21,22 +20,21 @@ ; CHECK-NEXT: call void @llvm.arm.dmb(i32 11) ; CHECK-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fadd float* %ptr, float %value seq_cst + %res = atomicrmw fadd ptr %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fsub_f32( ; CHECK-NEXT: call void @llvm.arm.dmb(i32 11) -; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -45,7 +43,7 @@ ; CHECK-NEXT: call void @llvm.arm.dmb(i32 11) ; CHECK-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fsub float* %ptr, float %value seq_cst + %res = atomicrmw fsub ptr %ptr, float %value seq_cst ret float %res } diff --git a/llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll b/llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll --- a/llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll +++ b/llvm/test/Transforms/AtomicExpand/ARM/cmpxchg-weak.ll @@ -1,12 +1,12 @@ ; RUN: opt -atomic-expand -codegen-opt-level=1 -S -mtriple=thumbv7s-apple-ios7.0 %s | FileCheck %s -define i32 @test_cmpxchg_seq_cst(i32* %addr, i32 %desired, i32 %new) { +define i32 @test_cmpxchg_seq_cst(ptr %addr, i32 %desired, i32 %new) { ; CHECK-LABEL: @test_cmpxchg_seq_cst ; Intrinsic for "dmb ishst" is then expected ; CHECK: br label %[[START:.*]] ; CHECK: [[START]]: -; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr) +; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr) ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] @@ -16,7 +16,7 @@ ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ] -; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr) +; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0(i32 %new, ptr elementtype(i32) %addr) ; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 ; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]] @@ -39,17 +39,17 @@ ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i32 [[LOADED_EXIT]] - %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst seq_cst + %pair = cmpxchg weak ptr %addr, i32 %desired, i32 %new seq_cst seq_cst %oldval = extractvalue { i32, i1 } %pair, 0 ret i32 %oldval } -define i1 @test_cmpxchg_weak_fail(i32* %addr, i32 %desired, i32 %new) { +define i1 @test_cmpxchg_weak_fail(ptr %addr, i32 %desired, i32 %new) { ; CHECK-LABEL: @test_cmpxchg_weak_fail ; CHECK: br label %[[START:.*]] ; CHECK: [[START]]: -; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr) +; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr) ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] @@ -58,7 +58,7 @@ ; CHECK: br label %[[TRY_STORE:.*]] ; CHECK: [[TRY_STORE]]: -; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr) +; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0(i32 %new, ptr elementtype(i32) %addr) ; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 ; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]] @@ -78,18 +78,18 @@ ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i1 [[SUCCESS]] - %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic + %pair = cmpxchg weak ptr %addr, i32 %desired, i32 %new seq_cst monotonic %oldval = extractvalue { i32, i1 } %pair, 1 ret i1 %oldval } -define i32 @test_cmpxchg_monotonic(i32* %addr, i32 %desired, i32 %new) { +define i32 @test_cmpxchg_monotonic(ptr %addr, i32 %desired, i32 %new) { ; CHECK-LABEL: @test_cmpxchg_monotonic ; CHECK-NOT: dmb ; CHECK: br label %[[START:.*]] ; CHECK: [[START]]: -; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr) +; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr) ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] @@ -98,7 +98,7 @@ ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ] -; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr) +; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0(i32 %new, ptr elementtype(i32) %addr) ; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 ; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]] @@ -121,17 +121,17 @@ ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i32 [[LOADED_EXIT]] - %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new monotonic monotonic + %pair = cmpxchg weak ptr %addr, i32 %desired, i32 %new monotonic monotonic %oldval = extractvalue { i32, i1 } %pair, 0 ret i32 %oldval } -define i32 @test_cmpxchg_seq_cst_minsize(i32* %addr, i32 %desired, i32 %new) minsize { +define i32 @test_cmpxchg_seq_cst_minsize(ptr %addr, i32 %desired, i32 %new) minsize { ; CHECK-LABEL: @test_cmpxchg_seq_cst_minsize ; CHECK: br label %[[START:.*]] ; CHECK: [[START]]: -; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0i32(i32* elementtype(i32) %addr) +; CHECK: [[LOADED:%.*]] = call i32 @llvm.arm.ldrex.p0(ptr elementtype(i32) %addr) ; CHECK: [[SHOULD_STORE:%.*]] = icmp eq i32 [[LOADED]], %desired ; CHECK: br i1 [[SHOULD_STORE]], label %[[FENCED_STORE:.*]], label %[[NO_STORE_BB:.*]] @@ -141,7 +141,7 @@ ; CHECK: [[TRY_STORE]]: ; CHECK: [[LOADED_TRYSTORE:%.*]] = phi i32 [ [[LOADED]], %[[FENCED_STORE]] ] -; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0i32(i32 %new, i32* elementtype(i32) %addr) +; CHECK: [[STREX:%.*]] = call i32 @llvm.arm.strex.p0(i32 %new, ptr elementtype(i32) %addr) ; CHECK: [[SUCCESS:%.*]] = icmp eq i32 [[STREX]], 0 ; CHECK: br i1 [[SUCCESS]], label %[[SUCCESS_BB:.*]], label %[[FAILURE_BB:.*]] @@ -164,7 +164,7 @@ ; CHECK: [[SUCCESS:%.*]] = phi i1 [ true, %[[SUCCESS_BB]] ], [ false, %[[FAILURE_BB]] ] ; CHECK: ret i32 [[LOADED_EXIT]] - %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst seq_cst + %pair = cmpxchg weak ptr %addr, i32 %desired, i32 %new seq_cst seq_cst %oldval = extractvalue { i32, i1 } %pair, 0 ret i32 %oldval } diff --git a/llvm/test/Transforms/AtomicExpand/Hexagon/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/Hexagon/atomicrmw-fp.ll --- a/llvm/test/Transforms/AtomicExpand/Hexagon/atomicrmw-fp.ll +++ b/llvm/test/Transforms/AtomicExpand/Hexagon/atomicrmw-fp.ll @@ -1,45 +1,41 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -mtriple=hexagon-- -atomic-expand %s | FileCheck %s -define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fadd_f32( ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: -; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[PTR:%.*]] to i32* -; CHECK-NEXT: [[LARX:%.*]] = call i32 @llvm.hexagon.L2.loadw.locked(i32* [[TMP1]]) +; CHECK-NEXT: [[LARX:%.*]] = call i32 @llvm.hexagon.L2.loadw.locked(ptr [[PTR:%.*]]) ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[LARX]] to float ; CHECK-NEXT: [[NEW:%.*]] = fadd float [[TMP2]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i32* ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[NEW]] to i32 -; CHECK-NEXT: [[STCX:%.*]] = call i32 @llvm.hexagon.S2.storew.locked(i32* [[TMP3]], i32 [[TMP4]]) +; CHECK-NEXT: [[STCX:%.*]] = call i32 @llvm.hexagon.S2.storew.locked(ptr [[PTR]], i32 [[TMP4]]) ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[STCX]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i32 ; CHECK-NEXT: br i1 [[TMP5]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]] ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret float [[TMP2]] ; - %res = atomicrmw fadd float* %ptr, float %value seq_cst + %res = atomicrmw fadd ptr %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fsub_f32( ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: -; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[PTR:%.*]] to i32* -; CHECK-NEXT: [[LARX:%.*]] = call i32 @llvm.hexagon.L2.loadw.locked(i32* [[TMP1]]) +; CHECK-NEXT: [[LARX:%.*]] = call i32 @llvm.hexagon.L2.loadw.locked(ptr [[PTR:%.*]]) ; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[LARX]] to float ; CHECK-NEXT: [[NEW:%.*]] = fsub float [[TMP2]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i32* ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[NEW]] to i32 -; CHECK-NEXT: [[STCX:%.*]] = call i32 @llvm.hexagon.S2.storew.locked(i32* [[TMP3]], i32 [[TMP4]]) +; CHECK-NEXT: [[STCX:%.*]] = call i32 @llvm.hexagon.S2.storew.locked(ptr [[PTR]], i32 [[TMP4]]) ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[STCX]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i32 ; CHECK-NEXT: br i1 [[TMP5]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]] ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret float [[TMP2]] ; - %res = atomicrmw fsub float* %ptr, float %value seq_cst + %res = atomicrmw fsub ptr %ptr, float %value seq_cst ret float %res } diff --git a/llvm/test/Transforms/AtomicExpand/Mips/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/Mips/atomicrmw-fp.ll --- a/llvm/test/Transforms/AtomicExpand/Mips/atomicrmw-fp.ll +++ b/llvm/test/Transforms/AtomicExpand/Mips/atomicrmw-fp.ll @@ -1,18 +1,17 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -mtriple=mips64-mti-linux-gnu -atomic-expand %s | FileCheck %s -define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fadd_f32( ; CHECK-NEXT: fence seq_cst -; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -21,22 +20,21 @@ ; CHECK-NEXT: fence seq_cst ; CHECK-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fadd float* %ptr, float %value seq_cst + %res = atomicrmw fadd ptr %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fsub_f32( ; CHECK-NEXT: fence seq_cst -; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -45,7 +43,7 @@ ; CHECK-NEXT: fence seq_cst ; CHECK-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fsub float* %ptr, float %value seq_cst + %res = atomicrmw fsub ptr %ptr, float %value seq_cst ret float %res } diff --git a/llvm/test/Transforms/AtomicExpand/PowerPC/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/PowerPC/atomicrmw-fp.ll --- a/llvm/test/Transforms/AtomicExpand/PowerPC/atomicrmw-fp.ll +++ b/llvm/test/Transforms/AtomicExpand/PowerPC/atomicrmw-fp.ll @@ -1,18 +1,17 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -mtriple=powerpc64-unknown-unknown -atomic-expand %s | FileCheck %s -define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fadd_f32( ; CHECK-NEXT: call void @llvm.ppc.sync() -; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -21,22 +20,21 @@ ; CHECK-NEXT: call void @llvm.ppc.lwsync() ; CHECK-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fadd float* %ptr, float %value seq_cst + %res = atomicrmw fadd ptr %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fsub_f32( ; CHECK-NEXT: call void @llvm.ppc.sync() -; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -45,7 +43,7 @@ ; CHECK-NEXT: call void @llvm.ppc.lwsync() ; CHECK-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fsub float* %ptr, float %value seq_cst + %res = atomicrmw fsub ptr %ptr, float %value seq_cst ret float %res } diff --git a/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-double.ll b/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-double.ll --- a/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-double.ll +++ b/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-double.ll @@ -4,7 +4,7 @@ ; RUN: opt -S -atomic-expand -mtriple=powerpc64-unknown-unknown \ ; RUN: -opaque-pointers < %s 2>&1 | FileCheck %s -define double @foo(double* %dp) { +define double @foo(ptr %dp) { ; CHECK-LABEL: @foo( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = load atomic i64, ptr [[DP:%.*]] monotonic, align 8 @@ -13,6 +13,6 @@ ; CHECK-NEXT: ret double [[TMP1]] ; entry: - %0 = load atomic double, double* %dp acquire, align 8 + %0 = load atomic double, ptr %dp acquire, align 8 ret double %0 } diff --git a/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-float.ll b/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-float.ll --- a/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-float.ll +++ b/llvm/test/Transforms/AtomicExpand/PowerPC/cfence-float.ll @@ -4,7 +4,7 @@ ; RUN: opt -S -atomic-expand -mtriple=powerpc64-unknown-unknown \ ; RUN: -opaque-pointers < %s 2>&1 | FileCheck %s -define float @bar(float* %fp) { +define float @bar(ptr %fp) { ; CHECK-LABEL: @bar( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = load atomic i32, ptr [[FP:%.*]] monotonic, align 4 @@ -13,6 +13,6 @@ ; CHECK-NEXT: ret float [[TMP1]] ; entry: - %0 = load atomic float, float* %fp acquire, align 4 + %0 = load atomic float, ptr %fp acquire, align 4 ret float %0 } diff --git a/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll b/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll --- a/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll +++ b/llvm/test/Transforms/AtomicExpand/PowerPC/cmpxchg.ll @@ -4,7 +4,7 @@ ; RUN: opt -atomic-expand -S -mtriple=powerpc64-unknown-unknown \ ; RUN: -mcpu=pwr7 %s | FileCheck --check-prefix=PWR7 %s -define i1 @test_cmpxchg_seq_cst(i128* %addr, i128 %desire, i128 %new) { +define i1 @test_cmpxchg_seq_cst(ptr %addr, i128 %desire, i128 %new) { ; CHECK-LABEL: @test_cmpxchg_seq_cst( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[CMP_LO:%.*]] = trunc i128 [[DESIRE:%.*]] to i64 @@ -13,9 +13,8 @@ ; CHECK-NEXT: [[NEW_LO:%.*]] = trunc i128 [[NEW:%.*]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = lshr i128 [[NEW]], 64 ; CHECK-NEXT: [[NEW_HI:%.*]] = trunc i128 [[TMP1]] to i64 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i128* [[ADDR:%.*]] to i8* ; CHECK-NEXT: call void @llvm.ppc.sync() -; CHECK-NEXT: [[TMP3:%.*]] = call { i64, i64 } @llvm.ppc.cmpxchg.i128(i8* [[TMP2]], i64 [[CMP_LO]], i64 [[CMP_HI]], i64 [[NEW_LO]], i64 [[NEW_HI]]) +; CHECK-NEXT: [[TMP3:%.*]] = call { i64, i64 } @llvm.ppc.cmpxchg.i128(ptr [[ADDR:%.*]], i64 [[CMP_LO]], i64 [[CMP_HI]], i64 [[NEW_LO]], i64 [[NEW_HI]]) ; CHECK-NEXT: call void @llvm.ppc.lwsync() ; CHECK-NEXT: [[LO:%.*]] = extractvalue { i64, i64 } [[TMP3]], 0 ; CHECK-NEXT: [[HI:%.*]] = extractvalue { i64, i64 } [[TMP3]], 1 @@ -23,7 +22,7 @@ ; CHECK-NEXT: [[HI64:%.*]] = zext i64 [[HI]] to i128 ; CHECK-NEXT: [[TMP4:%.*]] = shl i128 [[HI64]], 64 ; CHECK-NEXT: [[VAL64:%.*]] = or i128 [[LO64]], [[TMP4]] -; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i128, i1 } undef, i128 [[VAL64]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i128, i1 } poison, i128 [[VAL64]], 0 ; CHECK-NEXT: [[SUCCESS:%.*]] = icmp eq i128 [[DESIRE]], [[VAL64]] ; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i128, i1 } [[TMP5]], i1 [[SUCCESS]], 1 ; CHECK-NEXT: [[SUCC:%.*]] = extractvalue { i128, i1 } [[TMP6]], 1 @@ -31,26 +30,23 @@ ; ; PWR7-LABEL: @test_cmpxchg_seq_cst( ; PWR7-NEXT: entry: -; PWR7-NEXT: [[TMP0:%.*]] = bitcast i128* [[ADDR:%.*]] to i8* ; PWR7-NEXT: [[TMP1:%.*]] = alloca i128, align 8 -; PWR7-NEXT: [[TMP2:%.*]] = bitcast i128* [[TMP1]] to i8* -; PWR7-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP2]]) -; PWR7-NEXT: store i128 [[DESIRE:%.*]], i128* [[TMP1]], align 8 +; PWR7-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[TMP1]]) +; PWR7-NEXT: store i128 [[DESIRE:%.*]], ptr [[TMP1]], align 8 ; PWR7-NEXT: [[TMP3:%.*]] = alloca i128, align 8 -; PWR7-NEXT: [[TMP4:%.*]] = bitcast i128* [[TMP3]] to i8* -; PWR7-NEXT: call void @llvm.lifetime.start.p0i8(i64 16, i8* [[TMP4]]) -; PWR7-NEXT: store i128 [[NEW:%.*]], i128* [[TMP3]], align 8 -; PWR7-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, i8* [[TMP0]], i8* [[TMP2]], i8* [[TMP4]], i32 5, i32 5) -; PWR7-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP4]]) -; PWR7-NEXT: [[TMP6:%.*]] = load i128, i128* [[TMP1]], align 8 -; PWR7-NEXT: call void @llvm.lifetime.end.p0i8(i64 16, i8* [[TMP2]]) -; PWR7-NEXT: [[TMP7:%.*]] = insertvalue { i128, i1 } undef, i128 [[TMP6]], 0 +; PWR7-NEXT: call void @llvm.lifetime.start.p0(i64 16, ptr [[TMP3]]) +; PWR7-NEXT: store i128 [[NEW:%.*]], ptr [[TMP3]], align 8 +; PWR7-NEXT: [[TMP5:%.*]] = call zeroext i1 @__atomic_compare_exchange(i64 16, ptr [[ADDR:%.*]], ptr [[TMP1]], ptr [[TMP3]], i32 5, i32 5) +; PWR7-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[TMP3]]) +; PWR7-NEXT: [[TMP6:%.*]] = load i128, ptr [[TMP1]], align 8 +; PWR7-NEXT: call void @llvm.lifetime.end.p0(i64 16, ptr [[TMP1]]) +; PWR7-NEXT: [[TMP7:%.*]] = insertvalue { i128, i1 } poison, i128 [[TMP6]], 0 ; PWR7-NEXT: [[TMP8:%.*]] = insertvalue { i128, i1 } [[TMP7]], i1 [[TMP5]], 1 ; PWR7-NEXT: [[SUCC:%.*]] = extractvalue { i128, i1 } [[TMP8]], 1 ; PWR7-NEXT: ret i1 [[SUCC]] ; entry: - %pair = cmpxchg weak i128* %addr, i128 %desire, i128 %new seq_cst seq_cst + %pair = cmpxchg weak ptr %addr, i128 %desire, i128 %new seq_cst seq_cst %succ = extractvalue {i128, i1} %pair, 1 ret i1 %succ } diff --git a/llvm/test/Transforms/AtomicExpand/PowerPC/issue55983.ll b/llvm/test/Transforms/AtomicExpand/PowerPC/issue55983.ll --- a/llvm/test/Transforms/AtomicExpand/PowerPC/issue55983.ll +++ b/llvm/test/Transforms/AtomicExpand/PowerPC/issue55983.ll @@ -16,7 +16,7 @@ ret ptr %0 } -define void @foobar({} addrspace(10)* addrspace(11)* %p) { +define void @foobar(ptr addrspace(11) %p) { ; CHECK-LABEL: @foobar( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TMP0:%.*]] = load atomic ptr addrspace(10), ptr addrspace(11) [[P:%.*]] monotonic, align 8 @@ -24,6 +24,6 @@ ; CHECK-NEXT: unreachable ; entry: - %0 = load atomic {} addrspace(10)*, {} addrspace(10)* addrspace(11)* %p acquire, align 8 + %0 = load atomic ptr addrspace(10), ptr addrspace(11) %p acquire, align 8 unreachable } diff --git a/llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-fp.ll --- a/llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-fp.ll +++ b/llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-fp.ll @@ -1,23 +1,21 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -mtriple=riscv32-- -atomic-expand %s | FileCheck %s -define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fadd_f32( ; CHECK-NEXT: [[TMP1:%.*]] = alloca float, align 4 -; CHECK-NEXT: [[TMP2:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i8* -; CHECK-NEXT: [[TMP4:%.*]] = bitcast float* [[TMP1]] to i8* -; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) -; CHECK-NEXT: store float [[LOADED]], float* [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store float [[LOADED]], ptr [[TMP1]], align 4 ; CHECK-NEXT: [[TMP5:%.*]] = bitcast float [[NEW]] to i32 -; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(i8* [[TMP3]], i8* [[TMP4]], i32 [[TMP5]], i32 5, i32 5) -; CHECK-NEXT: [[TMP7:%.*]] = load float, float* [[TMP1]], align 4 -; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP4]]) -; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { float, i1 } undef, float [[TMP7]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[PTR]], ptr [[TMP1]], i32 [[TMP5]], i32 5, i32 5) +; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { float, i1 } poison, float [[TMP7]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { float, i1 } [[TMP8]], i1 [[TMP6]], 1 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { float, i1 } [[TMP9]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { float, i1 } [[TMP9]], 0 @@ -25,27 +23,25 @@ ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret float [[NEWLOADED]] ; - %res = atomicrmw fadd float* %ptr, float %value seq_cst + %res = atomicrmw fadd ptr %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fsub_f32( ; CHECK-NEXT: [[TMP1:%.*]] = alloca float, align 4 -; CHECK-NEXT: [[TMP2:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i8* -; CHECK-NEXT: [[TMP4:%.*]] = bitcast float* [[TMP1]] to i8* -; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* [[TMP4]]) -; CHECK-NEXT: store float [[LOADED]], float* [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: store float [[LOADED]], ptr [[TMP1]], align 4 ; CHECK-NEXT: [[TMP5:%.*]] = bitcast float [[NEW]] to i32 -; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(i8* [[TMP3]], i8* [[TMP4]], i32 [[TMP5]], i32 5, i32 5) -; CHECK-NEXT: [[TMP7:%.*]] = load float, float* [[TMP1]], align 4 -; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[TMP4]]) -; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { float, i1 } undef, float [[TMP7]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = call zeroext i1 @__atomic_compare_exchange_4(ptr [[PTR]], ptr [[TMP1]], i32 [[TMP5]], i32 5, i32 5) +; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[TMP1]], align 4 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 4, ptr [[TMP1]]) +; CHECK-NEXT: [[TMP8:%.*]] = insertvalue { float, i1 } poison, float [[TMP7]], 0 ; CHECK-NEXT: [[TMP9:%.*]] = insertvalue { float, i1 } [[TMP8]], i1 [[TMP6]], 1 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { float, i1 } [[TMP9]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { float, i1 } [[TMP9]], 0 @@ -53,7 +49,7 @@ ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret float [[NEWLOADED]] ; - %res = atomicrmw fsub float* %ptr, float %value seq_cst + %res = atomicrmw fsub ptr %ptr, float %value seq_cst ret float %res } diff --git a/llvm/test/Transforms/AtomicExpand/SPARC/libcalls.ll b/llvm/test/Transforms/AtomicExpand/SPARC/libcalls.ll --- a/llvm/test/Transforms/AtomicExpand/SPARC/libcalls.ll +++ b/llvm/test/Transforms/AtomicExpand/SPARC/libcalls.ll @@ -13,57 +13,51 @@ ;; straightforward. ; CHECK-LABEL: @test_load_i16( -; CHECK: %1 = bitcast i16* %arg to i8* -; CHECK: %2 = call i16 @__atomic_load_2(i8* %1, i32 5) -; CHECK: ret i16 %2 -define i16 @test_load_i16(i16* %arg) { - %ret = load atomic i16, i16* %arg seq_cst, align 4 +; CHECK: %1 = call i16 @__atomic_load_2(ptr %arg, i32 5) +; CHECK: ret i16 %1 +define i16 @test_load_i16(ptr %arg) { + %ret = load atomic i16, ptr %arg seq_cst, align 4 ret i16 %ret } ; CHECK-LABEL: @test_store_i16( -; CHECK: %1 = bitcast i16* %arg to i8* -; CHECK: call void @__atomic_store_2(i8* %1, i16 %val, i32 5) +; CHECK: call void @__atomic_store_2(ptr %arg, i16 %val, i32 5) ; CHECK: ret void -define void @test_store_i16(i16* %arg, i16 %val) { - store atomic i16 %val, i16* %arg seq_cst, align 4 +define void @test_store_i16(ptr %arg, i16 %val) { + store atomic i16 %val, ptr %arg seq_cst, align 4 ret void } ; CHECK-LABEL: @test_exchange_i16( -; CHECK: %1 = bitcast i16* %arg to i8* -; CHECK: %2 = call i16 @__atomic_exchange_2(i8* %1, i16 %val, i32 5) -; CHECK: ret i16 %2 -define i16 @test_exchange_i16(i16* %arg, i16 %val) { - %ret = atomicrmw xchg i16* %arg, i16 %val seq_cst +; CHECK: %1 = call i16 @__atomic_exchange_2(ptr %arg, i16 %val, i32 5) +; CHECK: ret i16 %1 +define i16 @test_exchange_i16(ptr %arg, i16 %val) { + %ret = atomicrmw xchg ptr %arg, i16 %val seq_cst ret i16 %ret } ; CHECK-LABEL: @test_cmpxchg_i16( -; CHECK: %1 = bitcast i16* %arg to i8* -; CHECK: %2 = alloca i16, align 2 -; CHECK: %3 = bitcast i16* %2 to i8* -; CHECK: call void @llvm.lifetime.start.p0i8(i64 2, i8* %3) -; CHECK: store i16 %old, i16* %2, align 2 -; CHECK: %4 = call zeroext i1 @__atomic_compare_exchange_2(i8* %1, i8* %3, i16 %new, i32 5, i32 0) -; CHECK: %5 = load i16, i16* %2, align 2 -; CHECK: call void @llvm.lifetime.end.p0i8(i64 2, i8* %3) -; CHECK: %6 = insertvalue { i16, i1 } undef, i16 %5, 0 -; CHECK: %7 = insertvalue { i16, i1 } %6, i1 %4, 1 -; CHECK: %ret = extractvalue { i16, i1 } %7, 0 +; CHECK: %1 = alloca i16, align 2 +; CHECK: call void @llvm.lifetime.start.p0(i64 2, ptr %1) +; CHECK: store i16 %old, ptr %1, align 2 +; CHECK: %2 = call zeroext i1 @__atomic_compare_exchange_2(ptr %arg, ptr %1, i16 %new, i32 5, i32 0) +; CHECK: %3 = load i16, ptr %1, align 2 +; CHECK: call void @llvm.lifetime.end.p0(i64 2, ptr %1) +; CHECK: %4 = insertvalue { i16, i1 } poison, i16 %3, 0 +; CHECK: %5 = insertvalue { i16, i1 } %4, i1 %2, 1 +; CHECK: %ret = extractvalue { i16, i1 } %5, 0 ; CHECK: ret i16 %ret -define i16 @test_cmpxchg_i16(i16* %arg, i16 %old, i16 %new) { - %ret_succ = cmpxchg i16* %arg, i16 %old, i16 %new seq_cst monotonic +define i16 @test_cmpxchg_i16(ptr %arg, i16 %old, i16 %new) { + %ret_succ = cmpxchg ptr %arg, i16 %old, i16 %new seq_cst monotonic %ret = extractvalue { i16, i1 } %ret_succ, 0 ret i16 %ret } ; CHECK-LABEL: @test_add_i16( -; CHECK: %1 = bitcast i16* %arg to i8* -; CHECK: %2 = call i16 @__atomic_fetch_add_2(i8* %1, i16 %val, i32 5) -; CHECK: ret i16 %2 -define i16 @test_add_i16(i16* %arg, i16 %val) { - %ret = atomicrmw add i16* %arg, i16 %val seq_cst +; CHECK: %1 = call i16 @__atomic_fetch_add_2(ptr %arg, i16 %val, i32 5) +; CHECK: ret i16 %1 +define i16 @test_add_i16(ptr %arg, i16 %val) { + %ret = atomicrmw add ptr %arg, i16 %val seq_cst ret i16 %ret } @@ -73,72 +67,62 @@ ;; 32-bit i386. ; CHECK-LABEL: @test_load_i128( -; CHECK: %1 = bitcast i128* %arg to i8* -; CHECK: %2 = alloca i128, align 8 -; CHECK: %3 = bitcast i128* %2 to i8* -; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %3) -; CHECK: call void @__atomic_load(i32 16, i8* %1, i8* %3, i32 5) -; CHECK: %4 = load i128, i128* %2, align 8 -; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %3) -; CHECK: ret i128 %4 -define i128 @test_load_i128(i128* %arg) { - %ret = load atomic i128, i128* %arg seq_cst, align 16 +; CHECK: %1 = alloca i128, align 8 +; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %1) +; CHECK: call void @__atomic_load(i32 16, ptr %arg, ptr %1, i32 5) +; CHECK: %2 = load i128, ptr %1, align 8 +; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %1) +; CHECK: ret i128 %2 +define i128 @test_load_i128(ptr %arg) { + %ret = load atomic i128, ptr %arg seq_cst, align 16 ret i128 %ret } ; CHECK-LABEL: @test_store_i128( -; CHECK: %1 = bitcast i128* %arg to i8* -; CHECK: %2 = alloca i128, align 8 -; CHECK: %3 = bitcast i128* %2 to i8* -; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %3) -; CHECK: store i128 %val, i128* %2, align 8 -; CHECK: call void @__atomic_store(i32 16, i8* %1, i8* %3, i32 5) -; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %3) +; CHECK: %1 = alloca i128, align 8 +; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %1) +; CHECK: store i128 %val, ptr %1, align 8 +; CHECK: call void @__atomic_store(i32 16, ptr %arg, ptr %1, i32 5) +; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %1) ; CHECK: ret void -define void @test_store_i128(i128* %arg, i128 %val) { - store atomic i128 %val, i128* %arg seq_cst, align 16 +define void @test_store_i128(ptr %arg, i128 %val) { + store atomic i128 %val, ptr %arg seq_cst, align 16 ret void } ; CHECK-LABEL: @test_exchange_i128( -; CHECK: %1 = bitcast i128* %arg to i8* +; CHECK: %1 = alloca i128, align 8 +; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %1) +; CHECK: store i128 %val, ptr %1, align 8 ; CHECK: %2 = alloca i128, align 8 -; CHECK: %3 = bitcast i128* %2 to i8* -; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %3) -; CHECK: store i128 %val, i128* %2, align 8 -; CHECK: %4 = alloca i128, align 8 -; CHECK: %5 = bitcast i128* %4 to i8* -; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %5) -; CHECK: call void @__atomic_exchange(i32 16, i8* %1, i8* %3, i8* %5, i32 5) -; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %3) -; CHECK: %6 = load i128, i128* %4, align 8 -; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %5) -; CHECK: ret i128 %6 -define i128 @test_exchange_i128(i128* %arg, i128 %val) { - %ret = atomicrmw xchg i128* %arg, i128 %val seq_cst +; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %2) +; CHECK: call void @__atomic_exchange(i32 16, ptr %arg, ptr %1, ptr %2, i32 5) +; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %1) +; CHECK: %3 = load i128, ptr %2, align 8 +; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %2) +; CHECK: ret i128 %3 +define i128 @test_exchange_i128(ptr %arg, i128 %val) { + %ret = atomicrmw xchg ptr %arg, i128 %val seq_cst ret i128 %ret } ; CHECK-LABEL: @test_cmpxchg_i128( -; CHECK: %1 = bitcast i128* %arg to i8* +; CHECK: %1 = alloca i128, align 8 +; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %1) +; CHECK: store i128 %old, ptr %1, align 8 ; CHECK: %2 = alloca i128, align 8 -; CHECK: %3 = bitcast i128* %2 to i8* -; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %3) -; CHECK: store i128 %old, i128* %2, align 8 -; CHECK: %4 = alloca i128, align 8 -; CHECK: %5 = bitcast i128* %4 to i8* -; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %5) -; CHECK: store i128 %new, i128* %4, align 8 -; CHECK: %6 = call zeroext i1 @__atomic_compare_exchange(i32 16, i8* %1, i8* %3, i8* %5, i32 5, i32 0) -; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %5) -; CHECK: %7 = load i128, i128* %2, align 8 -; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %3) -; CHECK: %8 = insertvalue { i128, i1 } undef, i128 %7, 0 -; CHECK: %9 = insertvalue { i128, i1 } %8, i1 %6, 1 -; CHECK: %ret = extractvalue { i128, i1 } %9, 0 +; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %2) +; CHECK: store i128 %new, ptr %2, align 8 +; CHECK: %3 = call zeroext i1 @__atomic_compare_exchange(i32 16, ptr %arg, ptr %1, ptr %2, i32 5, i32 0) +; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %2) +; CHECK: %4 = load i128, ptr %1, align 8 +; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %1) +; CHECK: %5 = insertvalue { i128, i1 } poison, i128 %4, 0 +; CHECK: %6 = insertvalue { i128, i1 } %5, i1 %3, 1 +; CHECK: %ret = extractvalue { i128, i1 } %6, 0 ; CHECK: ret i128 %ret -define i128 @test_cmpxchg_i128(i128* %arg, i128 %old, i128 %new) { - %ret_succ = cmpxchg i128* %arg, i128 %old, i128 %new seq_cst monotonic +define i128 @test_cmpxchg_i128(ptr %arg, i128 %old, i128 %new) { + %ret_succ = cmpxchg ptr %arg, i128 %old, i128 %new seq_cst monotonic %ret = extractvalue { i128, i1 } %ret_succ, 0 ret i128 %ret } @@ -150,90 +134,81 @@ ; CHECK-LABEL: @test_add_i128( ; CHECK: %1 = alloca i128, align 8 ; CHECK: %2 = alloca i128, align 8 -; CHECK: %3 = load i128, i128* %arg, align 16 +; CHECK: %3 = load i128, ptr %arg, align 16 ; CHECK: br label %atomicrmw.start ; CHECK:atomicrmw.start: ; CHECK: %loaded = phi i128 [ %3, %0 ], [ %newloaded, %atomicrmw.start ] ; CHECK: %new = add i128 %loaded, %val -; CHECK: %4 = bitcast i128* %arg to i8* -; CHECK: %5 = bitcast i128* %1 to i8* -; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %5) -; CHECK: store i128 %loaded, i128* %1, align 8 -; CHECK: %6 = bitcast i128* %2 to i8* -; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %6) -; CHECK: store i128 %new, i128* %2, align 8 -; CHECK: %7 = call zeroext i1 @__atomic_compare_exchange(i32 16, i8* %4, i8* %5, i8* %6, i32 5, i32 5) -; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %6) -; CHECK: %8 = load i128, i128* %1, align 8 -; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %5) -; CHECK: %9 = insertvalue { i128, i1 } undef, i128 %8, 0 -; CHECK: %10 = insertvalue { i128, i1 } %9, i1 %7, 1 -; CHECK: %success = extractvalue { i128, i1 } %10, 1 -; CHECK: %newloaded = extractvalue { i128, i1 } %10, 0 +; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %1) +; CHECK: store i128 %loaded, ptr %1, align 8 +; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %2) +; CHECK: store i128 %new, ptr %2, align 8 +; CHECK: %4 = call zeroext i1 @__atomic_compare_exchange(i32 16, ptr %arg, ptr %1, ptr %2, i32 5, i32 5) +; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %2) +; CHECK: %5 = load i128, ptr %1, align 8 +; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %1) +; CHECK: %6 = insertvalue { i128, i1 } poison, i128 %5, 0 +; CHECK: %7 = insertvalue { i128, i1 } %6, i1 %4, 1 +; CHECK: %success = extractvalue { i128, i1 } %7, 1 +; CHECK: %newloaded = extractvalue { i128, i1 } %7, 0 ; CHECK: br i1 %success, label %atomicrmw.end, label %atomicrmw.start ; CHECK:atomicrmw.end: ; CHECK: ret i128 %newloaded -define i128 @test_add_i128(i128* %arg, i128 %val) { - %ret = atomicrmw add i128* %arg, i128 %val seq_cst +define i128 @test_add_i128(ptr %arg, i128 %val) { + %ret = atomicrmw add ptr %arg, i128 %val seq_cst ret i128 %ret } ;; Ensure that non-integer types get bitcast correctly on the way in and out of a libcall: ; CHECK-LABEL: @test_load_double( -; CHECK: %1 = bitcast double* %arg to i8* -; CHECK: %2 = call i64 @__atomic_load_8(i8* %1, i32 5) -; CHECK: %3 = bitcast i64 %2 to double -; CHECK: ret double %3 -define double @test_load_double(double* %arg, double %val) { - %1 = load atomic double, double* %arg seq_cst, align 16 +; CHECK: %1 = call i64 @__atomic_load_8(ptr %arg, i32 5) +; CHECK: %2 = bitcast i64 %1 to double +; CHECK: ret double %2 +define double @test_load_double(ptr %arg, double %val) { + %1 = load atomic double, ptr %arg seq_cst, align 16 ret double %1 } ; CHECK-LABEL: @test_store_double( -; CHECK: %1 = bitcast double* %arg to i8* -; CHECK: %2 = bitcast double %val to i64 -; CHECK: call void @__atomic_store_8(i8* %1, i64 %2, i32 5) +; CHECK: %1 = bitcast double %val to i64 +; CHECK: call void @__atomic_store_8(ptr %arg, i64 %1, i32 5) ; CHECK: ret void -define void @test_store_double(double* %arg, double %val) { - store atomic double %val, double* %arg seq_cst, align 16 +define void @test_store_double(ptr %arg, double %val) { + store atomic double %val, ptr %arg seq_cst, align 16 ret void } ; CHECK-LABEL: @test_cmpxchg_ptr( -; CHECK: %1 = bitcast i16** %arg to i8* -; CHECK: %2 = alloca i16*, align 4 -; CHECK: %3 = bitcast i16** %2 to i8* -; CHECK: call void @llvm.lifetime.start.p0i8(i64 4, i8* %3) -; CHECK: store i16* %old, i16** %2, align 4 -; CHECK: %4 = ptrtoint i16* %new to i32 -; CHECK: %5 = call zeroext i1 @__atomic_compare_exchange_4(i8* %1, i8* %3, i32 %4, i32 5, i32 2) -; CHECK: %6 = load i16*, i16** %2, align 4 -; CHECK: call void @llvm.lifetime.end.p0i8(i64 4, i8* %3) -; CHECK: %7 = insertvalue { i16*, i1 } undef, i16* %6, 0 -; CHECK: %8 = insertvalue { i16*, i1 } %7, i1 %5, 1 -; CHECK: %ret = extractvalue { i16*, i1 } %8, 0 -; CHECK: ret i16* %ret +; CHECK: %1 = alloca ptr, align 4 +; CHECK: call void @llvm.lifetime.start.p0(i64 4, ptr %1) +; CHECK: store ptr %old, ptr %1, align 4 +; CHECK: %2 = ptrtoint ptr %new to i32 +; CHECK: %3 = call zeroext i1 @__atomic_compare_exchange_4(ptr %arg, ptr %1, i32 %2, i32 5, i32 2) +; CHECK: %4 = load ptr, ptr %1, align 4 +; CHECK: call void @llvm.lifetime.end.p0(i64 4, ptr %1) +; CHECK: %5 = insertvalue { ptr, i1 } poison, ptr %4, 0 +; CHECK: %6 = insertvalue { ptr, i1 } %5, i1 %3, 1 +; CHECK: %ret = extractvalue { ptr, i1 } %6, 0 +; CHECK: ret ptr %ret ; CHECK: } -define i16* @test_cmpxchg_ptr(i16** %arg, i16* %old, i16* %new) { - %ret_succ = cmpxchg i16** %arg, i16* %old, i16* %new seq_cst acquire - %ret = extractvalue { i16*, i1 } %ret_succ, 0 - ret i16* %ret +define ptr @test_cmpxchg_ptr(ptr %arg, ptr %old, ptr %new) { + %ret_succ = cmpxchg ptr %arg, ptr %old, ptr %new seq_cst acquire + %ret = extractvalue { ptr, i1 } %ret_succ, 0 + ret ptr %ret } ;; ...and for a non-integer type of large size too. ; CHECK-LABEL: @test_store_fp128 -; CHECK: %1 = bitcast fp128* %arg to i8* -; CHECK: %2 = alloca fp128, align 8 -; CHECK: %3 = bitcast fp128* %2 to i8* -; CHECK: call void @llvm.lifetime.start.p0i8(i64 16, i8* %3) -; CHECK: store fp128 %val, fp128* %2, align 8 -; CHECK: call void @__atomic_store(i32 16, i8* %1, i8* %3, i32 5) -; CHECK: call void @llvm.lifetime.end.p0i8(i64 16, i8* %3) +; CHECK: %1 = alloca fp128, align 8 +; CHECK: call void @llvm.lifetime.start.p0(i64 16, ptr %1) +; CHECK: store fp128 %val, ptr %1, align 8 +; CHECK: call void @__atomic_store(i32 16, ptr %arg, ptr %1, i32 5) +; CHECK: call void @llvm.lifetime.end.p0(i64 16, ptr %1) ; CHECK: ret void -define void @test_store_fp128(fp128* %arg, fp128 %val) { - store atomic fp128 %val, fp128* %arg seq_cst, align 16 +define void @test_store_fp128(ptr %arg, fp128 %val) { + store atomic fp128 %val, ptr %arg seq_cst, align 16 ret void } @@ -244,14 +219,14 @@ ; CHECK-LABEL: @test_unaligned_load_i16( ; CHECK: __atomic_load( -define i16 @test_unaligned_load_i16(i16* %arg) { - %ret = load atomic i16, i16* %arg seq_cst, align 1 +define i16 @test_unaligned_load_i16(ptr %arg) { + %ret = load atomic i16, ptr %arg seq_cst, align 1 ret i16 %ret } ; CHECK-LABEL: @test_unaligned_store_i16( ; CHECK: __atomic_store( -define void @test_unaligned_store_i16(i16* %arg, i16 %val) { - store atomic i16 %val, i16* %arg seq_cst, align 1 +define void @test_unaligned_store_i16(ptr %arg, i16 %val) { + store atomic i16 %val, ptr %arg seq_cst, align 1 ret void } diff --git a/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll b/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll --- a/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll +++ b/llvm/test/Transforms/AtomicExpand/SPARC/partword.ll @@ -9,31 +9,30 @@ target datalayout = "E-m:e-i64:64-n32:64-S128" target triple = "sparcv9-unknown-unknown" -define i8 @test_cmpxchg_i8(i8* %arg, i8 %old, i8 %new) { +define i8 @test_cmpxchg_i8(ptr %arg, i8 %old, i8 %new) { ; CHECK-LABEL: @test_cmpxchg_i8( ; CHECK-NEXT: entry: ; CHECK-NEXT: fence seq_cst -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i8* @llvm.ptrmask.p0i8.i64(i8* [[ARG:%.*]], i64 -4) -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i8* [[ARG]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 255, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i8* [[ALIGNEDADDR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[NEW:%.*]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] ; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[OLD:%.*]] to i32 ; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP5]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], [[INV_MASK]] ; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]] ; CHECK: partword.cmpxchg.loop: ; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[ENTRY:%.*]] ], [ [[TMP15:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ] ; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP4]] ; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP6]] -; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[TMP11]], i32 [[TMP10]] monotonic monotonic, align 4 +; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[TMP11]], i32 [[TMP10]] monotonic monotonic, align 4 ; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { i32, i1 } [[TMP12]], 0 ; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP12]], 1 ; CHECK-NEXT: br i1 [[TMP14]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]] @@ -44,43 +43,42 @@ ; CHECK: partword.cmpxchg.end: ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP13]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i8 -; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i8, i1 } undef, i8 [[EXTRACTED]], 0 +; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i8, i1 } poison, i8 [[EXTRACTED]], 0 ; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { i8, i1 } [[TMP17]], i1 [[TMP14]], 1 ; CHECK-NEXT: fence seq_cst ; CHECK-NEXT: [[RET:%.*]] = extractvalue { i8, i1 } [[TMP18]], 0 ; CHECK-NEXT: ret i8 [[RET]] ; entry: - %ret_succ = cmpxchg i8* %arg, i8 %old, i8 %new seq_cst monotonic + %ret_succ = cmpxchg ptr %arg, i8 %old, i8 %new seq_cst monotonic %ret = extractvalue { i8, i1 } %ret_succ, 0 ret i8 %ret } -define i16 @test_cmpxchg_i16(i16* %arg, i16 %old, i16 %new) { +define i16 @test_cmpxchg_i16(ptr %arg, i16 %old, i16 %new) { ; CHECK-LABEL: @test_cmpxchg_i16( ; CHECK-NEXT: entry: ; CHECK-NEXT: fence seq_cst -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16* @llvm.ptrmask.p0i16.i64(i16* [[ARG:%.*]], i64 -4) -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i16* [[ARG]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16* [[ALIGNEDADDR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[NEW:%.*]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] ; CHECK-NEXT: [[TMP5:%.*]] = zext i16 [[OLD:%.*]] to i32 ; CHECK-NEXT: [[TMP6:%.*]] = shl i32 [[TMP5]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], [[INV_MASK]] ; CHECK-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]] ; CHECK: partword.cmpxchg.loop: ; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ [[TMP8]], [[ENTRY:%.*]] ], [ [[TMP15:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ] ; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[TMP9]], [[TMP4]] ; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP6]] -; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[TMP11]], i32 [[TMP10]] monotonic monotonic, align 4 +; CHECK-NEXT: [[TMP12:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[TMP11]], i32 [[TMP10]] monotonic monotonic, align 4 ; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { i32, i1 } [[TMP12]], 0 ; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { i32, i1 } [[TMP12]], 1 ; CHECK-NEXT: br i1 [[TMP14]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]] @@ -91,34 +89,33 @@ ; CHECK: partword.cmpxchg.end: ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[TMP13]], [[SHIFTAMT]] ; CHECK-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 -; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i16, i1 } undef, i16 [[EXTRACTED]], 0 +; CHECK-NEXT: [[TMP17:%.*]] = insertvalue { i16, i1 } poison, i16 [[EXTRACTED]], 0 ; CHECK-NEXT: [[TMP18:%.*]] = insertvalue { i16, i1 } [[TMP17]], i1 [[TMP14]], 1 ; CHECK-NEXT: fence seq_cst ; CHECK-NEXT: [[RET:%.*]] = extractvalue { i16, i1 } [[TMP18]], 0 ; CHECK-NEXT: ret i16 [[RET]] ; entry: - %ret_succ = cmpxchg i16* %arg, i16 %old, i16 %new seq_cst monotonic + %ret_succ = cmpxchg ptr %arg, i16 %old, i16 %new seq_cst monotonic %ret = extractvalue { i16, i1 } %ret_succ, 0 ret i16 %ret } -define i16 @test_add_i16(i16* %arg, i16 %val) { +define i16 @test_add_i16(ptr %arg, i16 %val) { ; CHECK-LABEL: @test_add_i16( ; CHECK-NEXT: entry: ; CHECK-NEXT: fence seq_cst -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16* @llvm.ptrmask.p0i16.i64(i16* [[ARG:%.*]], i64 -4) -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i16* [[ARG]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16* [[ALIGNEDADDR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VAL:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -126,7 +123,7 @@ ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[NEW]], [[MASK]] ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[TMP5]] -; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[TMP7]] monotonic monotonic, align 4 +; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] monotonic monotonic, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -137,31 +134,30 @@ ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; entry: - %ret = atomicrmw add i16* %arg, i16 %val seq_cst + %ret = atomicrmw add ptr %arg, i16 %val seq_cst ret i16 %ret } -define i16 @test_xor_i16(i16* %arg, i16 %val) { +define i16 @test_xor_i16(ptr %arg, i16 %val) { ; CHECK-LABEL: @test_xor_i16( ; CHECK-NEXT: entry: ; CHECK-NEXT: fence seq_cst -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16* @llvm.ptrmask.p0i16.i64(i16* [[ARG:%.*]], i64 -4) -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i16* [[ARG]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16* [[ALIGNEDADDR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VAL:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = xor i32 [[LOADED]], [[VALOPERAND_SHIFTED]] -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[NEW]] monotonic monotonic, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[NEW]] monotonic monotonic, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -172,31 +168,30 @@ ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; entry: - %ret = atomicrmw xor i16* %arg, i16 %val seq_cst + %ret = atomicrmw xor ptr %arg, i16 %val seq_cst ret i16 %ret } -define i16 @test_or_i16(i16* %arg, i16 %val) { +define i16 @test_or_i16(ptr %arg, i16 %val) { ; CHECK-LABEL: @test_or_i16( ; CHECK-NEXT: entry: ; CHECK-NEXT: fence seq_cst -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16* @llvm.ptrmask.p0i16.i64(i16* [[ARG:%.*]], i64 -4) -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i16* [[ARG]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16* [[ALIGNEDADDR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VAL:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = or i32 [[LOADED]], [[VALOPERAND_SHIFTED]] -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[NEW]] monotonic monotonic, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[NEW]] monotonic monotonic, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -207,32 +202,31 @@ ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; entry: - %ret = atomicrmw or i16* %arg, i16 %val seq_cst + %ret = atomicrmw or ptr %arg, i16 %val seq_cst ret i16 %ret } -define i16 @test_and_i16(i16* %arg, i16 %val) { +define i16 @test_and_i16(ptr %arg, i16 %val) { ; CHECK-LABEL: @test_and_i16( ; CHECK-NEXT: entry: ; CHECK-NEXT: fence seq_cst -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16* @llvm.ptrmask.p0i16.i64(i16* [[ARG:%.*]], i64 -4) -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i16* [[ARG]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16* [[ALIGNEDADDR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[VAL:%.*]] to i32 ; CHECK-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] ; CHECK-NEXT: [[ANDOPERAND:%.*]] = or i32 [[INV_MASK]], [[VALOPERAND_SHIFTED]] -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = and i32 [[LOADED]], [[ANDOPERAND]] -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[NEW]] monotonic monotonic, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[NEW]] monotonic monotonic, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -243,24 +237,23 @@ ; CHECK-NEXT: ret i16 [[EXTRACTED]] ; entry: - %ret = atomicrmw and i16* %arg, i16 %val seq_cst + %ret = atomicrmw and ptr %arg, i16 %val seq_cst ret i16 %ret } -define i16 @test_min_i16(i16* %arg, i16 %val) { +define i16 @test_min_i16(ptr %arg, i16 %val) { ; CHECK-LABEL: @test_min_i16( ; CHECK-NEXT: entry: ; CHECK-NEXT: fence seq_cst -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call i16* @llvm.ptrmask.p0i16.i64(i16* [[ARG:%.*]], i64 -4) -; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint i16* [[ARG]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[ARG:%.*]], i64 -4) +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP0]], 3 ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[PTRLSB]], 2 ; CHECK-NEXT: [[TMP2:%.*]] = shl i64 [[TMP1]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast i16* [[ALIGNEDADDR]] to i32* -; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[ENTRY:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -272,7 +265,7 @@ ; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] monotonic monotonic, align 4 +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] monotonic monotonic, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -283,23 +276,22 @@ ; CHECK-NEXT: ret i16 [[EXTRACTED4]] ; entry: - %ret = atomicrmw min i16* %arg, i16 %val seq_cst + %ret = atomicrmw min ptr %arg, i16 %val seq_cst ret i16 %ret } -define half @test_atomicrmw_fadd_f16(half* %ptr, half %value) { +define half @test_atomicrmw_fadd_f16(ptr %ptr, half %value) { ; CHECK-LABEL: @test_atomicrmw_fadd_f16( ; CHECK-NEXT: fence seq_cst -; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call half* @llvm.ptrmask.p0f16.i64(half* [[PTR:%.*]], i64 -4) -; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint half* [[PTR]] to i64 +; CHECK-NEXT: [[ALIGNEDADDR:%.*]] = call ptr @llvm.ptrmask.p0.i64(ptr [[PTR:%.*]], i64 -4) +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[PTR]] to i64 ; CHECK-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[PTRLSB]], 2 ; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[TMP2]], 3 ; CHECK-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP3]] to i32 ; CHECK-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] ; CHECK-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 -; CHECK-NEXT: [[ALIGNEDADDR1:%.*]] = bitcast half* [[ALIGNEDADDR]] to i32* -; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ALIGNEDADDR1]], align 4 +; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[ALIGNEDADDR]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] @@ -312,7 +304,7 @@ ; CHECK-NEXT: [[SHIFTED2:%.*]] = shl nuw i32 [[EXTENDED]], [[SHIFTAMT]] ; CHECK-NEXT: [[UNMASKED:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[INSERTED:%.*]] = or i32 [[UNMASKED]], [[SHIFTED2]] -; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg i32* [[ALIGNEDADDR1]], i32 [[LOADED]], i32 [[INSERTED]] monotonic monotonic, align 4 +; CHECK-NEXT: [[TMP7:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[INSERTED]] monotonic monotonic, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -323,6 +315,6 @@ ; CHECK-NEXT: fence seq_cst ; CHECK-NEXT: ret half [[TMP8]] ; - %res = atomicrmw fadd half* %ptr, half %value seq_cst + %res = atomicrmw fadd ptr %ptr, half %value seq_cst ret half %res } diff --git a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-libcall.ll b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-libcall.ll --- a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-libcall.ll +++ b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-libcall.ll @@ -2,33 +2,29 @@ ; RUN: opt -S -mtriple=i686-linux-gnu -atomic-expand %s | FileCheck %s -define i256 @atomic_load256_libcall(i256* %ptr) nounwind { +define i256 @atomic_load256_libcall(ptr %ptr) nounwind { ; CHECK-LABEL: @atomic_load256_libcall( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast i256* [[PTR:%.*]] to i8* ; CHECK-NEXT: [[TMP2:%.*]] = alloca i256, align 8 -; CHECK-NEXT: [[TMP3:%.*]] = bitcast i256* [[TMP2]] to i8* -; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 32, i8* [[TMP3]]) -; CHECK-NEXT: call void @__atomic_load(i64 32, i8* [[TMP1]], i8* [[TMP3]], i32 0) -; CHECK-NEXT: [[TMP4:%.*]] = load i256, i256* [[TMP2]], align 8 -; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 32, i8* [[TMP3]]) +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 32, ptr [[TMP2]]) +; CHECK-NEXT: call void @__atomic_load(i64 32, ptr [[PTR:%.*]], ptr [[TMP2]], i32 0) +; CHECK-NEXT: [[TMP4:%.*]] = load i256, ptr [[TMP2]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 32, ptr [[TMP2]]) ; CHECK-NEXT: ret i256 [[TMP4]] ; - %result = load atomic i256, i256* %ptr unordered, align 16 + %result = load atomic i256, ptr %ptr unordered, align 16 ret i256 %result } -define i256 @atomic_load256_libcall_as1(i256 addrspace(1)* %ptr) nounwind { +define i256 @atomic_load256_libcall_as1(ptr addrspace(1) %ptr) nounwind { ; CHECK-LABEL: @atomic_load256_libcall_as1( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast i256 addrspace(1)* [[PTR:%.*]] to i8 addrspace(1)* -; CHECK-NEXT: [[TMP2:%.*]] = addrspacecast i8 addrspace(1)* [[TMP1]] to i8* +; CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(1) [[PTR:%.*]] to ptr ; CHECK-NEXT: [[TMP3:%.*]] = alloca i256, align 8 -; CHECK-NEXT: [[TMP4:%.*]] = bitcast i256* [[TMP3]] to i8* -; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 32, i8* [[TMP4]]) -; CHECK-NEXT: call void @__atomic_load(i64 32, i8* [[TMP2]], i8* [[TMP4]], i32 0) -; CHECK-NEXT: [[TMP5:%.*]] = load i256, i256* [[TMP3]], align 8 -; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 32, i8* [[TMP4]]) +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 32, ptr [[TMP3]]) +; CHECK-NEXT: call void @__atomic_load(i64 32, ptr [[TMP2]], ptr [[TMP3]], i32 0) +; CHECK-NEXT: [[TMP5:%.*]] = load i256, ptr [[TMP3]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 32, ptr [[TMP3]]) ; CHECK-NEXT: ret i256 [[TMP5]] ; - %result = load atomic i256, i256 addrspace(1)* %ptr unordered, align 16 + %result = load atomic i256, ptr addrspace(1) %ptr unordered, align 16 ret i256 %result } diff --git a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll --- a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll +++ b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-non-integer.ll @@ -4,164 +4,150 @@ ; `llvm::convertAtomicStoreToIntegerType`. If X86 stops using this ; functionality, please move this test to a target which still is. -define float @float_load_expand(float* %ptr) { +define float @float_load_expand(ptr %ptr) { ; CHECK-LABEL: @float_load_expand -; CHECK: %1 = bitcast float* %ptr to i32* -; CHECK: %2 = load atomic i32, i32* %1 unordered, align 4 -; CHECK: %3 = bitcast i32 %2 to float -; CHECK: ret float %3 - %res = load atomic float, float* %ptr unordered, align 4 +; CHECK: %1 = load atomic i32, ptr %ptr unordered, align 4 +; CHECK: %2 = bitcast i32 %1 to float +; CHECK: ret float %2 + %res = load atomic float, ptr %ptr unordered, align 4 ret float %res } -define float @float_load_expand_seq_cst(float* %ptr) { +define float @float_load_expand_seq_cst(ptr %ptr) { ; CHECK-LABEL: @float_load_expand_seq_cst -; CHECK: %1 = bitcast float* %ptr to i32* -; CHECK: %2 = load atomic i32, i32* %1 seq_cst, align 4 -; CHECK: %3 = bitcast i32 %2 to float -; CHECK: ret float %3 - %res = load atomic float, float* %ptr seq_cst, align 4 +; CHECK: %1 = load atomic i32, ptr %ptr seq_cst, align 4 +; CHECK: %2 = bitcast i32 %1 to float +; CHECK: ret float %2 + %res = load atomic float, ptr %ptr seq_cst, align 4 ret float %res } -define float @float_load_expand_vol(float* %ptr) { +define float @float_load_expand_vol(ptr %ptr) { ; CHECK-LABEL: @float_load_expand_vol -; CHECK: %1 = bitcast float* %ptr to i32* -; CHECK: %2 = load atomic volatile i32, i32* %1 unordered, align 4 -; CHECK: %3 = bitcast i32 %2 to float -; CHECK: ret float %3 - %res = load atomic volatile float, float* %ptr unordered, align 4 +; CHECK: %1 = load atomic volatile i32, ptr %ptr unordered, align 4 +; CHECK: %2 = bitcast i32 %1 to float +; CHECK: ret float %2 + %res = load atomic volatile float, ptr %ptr unordered, align 4 ret float %res } -define float @float_load_expand_addr1(float addrspace(1)* %ptr) { +define float @float_load_expand_addr1(ptr addrspace(1) %ptr) { ; CHECK-LABEL: @float_load_expand_addr1 -; CHECK: %1 = bitcast float addrspace(1)* %ptr to i32 addrspace(1)* -; CHECK: %2 = load atomic i32, i32 addrspace(1)* %1 unordered, align 4 -; CHECK: %3 = bitcast i32 %2 to float -; CHECK: ret float %3 - %res = load atomic float, float addrspace(1)* %ptr unordered, align 4 +; CHECK: %1 = load atomic i32, ptr addrspace(1) %ptr unordered, align 4 +; CHECK: %2 = bitcast i32 %1 to float +; CHECK: ret float %2 + %res = load atomic float, ptr addrspace(1) %ptr unordered, align 4 ret float %res } -define void @float_store_expand(float* %ptr, float %v) { +define void @float_store_expand(ptr %ptr, float %v) { ; CHECK-LABEL: @float_store_expand ; CHECK: %1 = bitcast float %v to i32 -; CHECK: %2 = bitcast float* %ptr to i32* -; CHECK: store atomic i32 %1, i32* %2 unordered, align 4 - store atomic float %v, float* %ptr unordered, align 4 +; CHECK: store atomic i32 %1, ptr %ptr unordered, align 4 + store atomic float %v, ptr %ptr unordered, align 4 ret void } -define void @float_store_expand_seq_cst(float* %ptr, float %v) { +define void @float_store_expand_seq_cst(ptr %ptr, float %v) { ; CHECK-LABEL: @float_store_expand_seq_cst ; CHECK: %1 = bitcast float %v to i32 -; CHECK: %2 = bitcast float* %ptr to i32* -; CHECK: store atomic i32 %1, i32* %2 seq_cst, align 4 - store atomic float %v, float* %ptr seq_cst, align 4 +; CHECK: store atomic i32 %1, ptr %ptr seq_cst, align 4 + store atomic float %v, ptr %ptr seq_cst, align 4 ret void } -define void @float_store_expand_vol(float* %ptr, float %v) { +define void @float_store_expand_vol(ptr %ptr, float %v) { ; CHECK-LABEL: @float_store_expand_vol ; CHECK: %1 = bitcast float %v to i32 -; CHECK: %2 = bitcast float* %ptr to i32* -; CHECK: store atomic volatile i32 %1, i32* %2 unordered, align 4 - store atomic volatile float %v, float* %ptr unordered, align 4 +; CHECK: store atomic volatile i32 %1, ptr %ptr unordered, align 4 + store atomic volatile float %v, ptr %ptr unordered, align 4 ret void } -define void @float_store_expand_addr1(float addrspace(1)* %ptr, float %v) { +define void @float_store_expand_addr1(ptr addrspace(1) %ptr, float %v) { ; CHECK-LABEL: @float_store_expand_addr1 ; CHECK: %1 = bitcast float %v to i32 -; CHECK: %2 = bitcast float addrspace(1)* %ptr to i32 addrspace(1)* -; CHECK: store atomic i32 %1, i32 addrspace(1)* %2 unordered, align 4 - store atomic float %v, float addrspace(1)* %ptr unordered, align 4 +; CHECK: store atomic i32 %1, ptr addrspace(1) %ptr unordered, align 4 + store atomic float %v, ptr addrspace(1) %ptr unordered, align 4 ret void } -define void @pointer_cmpxchg_expand(i8** %ptr, i8* %v) { +define void @pointer_cmpxchg_expand(ptr %ptr, ptr %v) { ; CHECK-LABEL: @pointer_cmpxchg_expand -; CHECK: %1 = bitcast i8** %ptr to i64* -; CHECK: %2 = ptrtoint i8* %v to i64 -; CHECK: %3 = cmpxchg i64* %1, i64 0, i64 %2 seq_cst monotonic -; CHECK: %4 = extractvalue { i64, i1 } %3, 0 -; CHECK: %5 = extractvalue { i64, i1 } %3, 1 -; CHECK: %6 = inttoptr i64 %4 to i8* -; CHECK: %7 = insertvalue { i8*, i1 } undef, i8* %6, 0 -; CHECK: %8 = insertvalue { i8*, i1 } %7, i1 %5, 1 - cmpxchg i8** %ptr, i8* null, i8* %v seq_cst monotonic +; CHECK: %1 = ptrtoint ptr %v to i64 +; CHECK: %2 = cmpxchg ptr %ptr, i64 0, i64 %1 seq_cst monotonic +; CHECK: %3 = extractvalue { i64, i1 } %2, 0 +; CHECK: %4 = extractvalue { i64, i1 } %2, 1 +; CHECK: %5 = inttoptr i64 %3 to ptr +; CHECK: %6 = insertvalue { ptr, i1 } poison, ptr %5, 0 +; CHECK: %7 = insertvalue { ptr, i1 } %6, i1 %4, 1 + cmpxchg ptr %ptr, ptr null, ptr %v seq_cst monotonic ret void } -define void @pointer_cmpxchg_expand2(i8** %ptr, i8* %v) { +define void @pointer_cmpxchg_expand2(ptr %ptr, ptr %v) { ; CHECK-LABEL: @pointer_cmpxchg_expand2 -; CHECK: %1 = bitcast i8** %ptr to i64* -; CHECK: %2 = ptrtoint i8* %v to i64 -; CHECK: %3 = cmpxchg i64* %1, i64 0, i64 %2 release monotonic -; CHECK: %4 = extractvalue { i64, i1 } %3, 0 -; CHECK: %5 = extractvalue { i64, i1 } %3, 1 -; CHECK: %6 = inttoptr i64 %4 to i8* -; CHECK: %7 = insertvalue { i8*, i1 } undef, i8* %6, 0 -; CHECK: %8 = insertvalue { i8*, i1 } %7, i1 %5, 1 - cmpxchg i8** %ptr, i8* null, i8* %v release monotonic +; CHECK: %1 = ptrtoint ptr %v to i64 +; CHECK: %2 = cmpxchg ptr %ptr, i64 0, i64 %1 release monotonic +; CHECK: %3 = extractvalue { i64, i1 } %2, 0 +; CHECK: %4 = extractvalue { i64, i1 } %2, 1 +; CHECK: %5 = inttoptr i64 %3 to ptr +; CHECK: %6 = insertvalue { ptr, i1 } poison, ptr %5, 0 +; CHECK: %7 = insertvalue { ptr, i1 } %6, i1 %4, 1 + cmpxchg ptr %ptr, ptr null, ptr %v release monotonic ret void } -define void @pointer_cmpxchg_expand3(i8** %ptr, i8* %v) { +define void @pointer_cmpxchg_expand3(ptr %ptr, ptr %v) { ; CHECK-LABEL: @pointer_cmpxchg_expand3 -; CHECK: %1 = bitcast i8** %ptr to i64* -; CHECK: %2 = ptrtoint i8* %v to i64 -; CHECK: %3 = cmpxchg i64* %1, i64 0, i64 %2 seq_cst seq_cst -; CHECK: %4 = extractvalue { i64, i1 } %3, 0 -; CHECK: %5 = extractvalue { i64, i1 } %3, 1 -; CHECK: %6 = inttoptr i64 %4 to i8* -; CHECK: %7 = insertvalue { i8*, i1 } undef, i8* %6, 0 -; CHECK: %8 = insertvalue { i8*, i1 } %7, i1 %5, 1 - cmpxchg i8** %ptr, i8* null, i8* %v seq_cst seq_cst +; CHECK: %1 = ptrtoint ptr %v to i64 +; CHECK: %2 = cmpxchg ptr %ptr, i64 0, i64 %1 seq_cst seq_cst +; CHECK: %3 = extractvalue { i64, i1 } %2, 0 +; CHECK: %4 = extractvalue { i64, i1 } %2, 1 +; CHECK: %5 = inttoptr i64 %3 to ptr +; CHECK: %6 = insertvalue { ptr, i1 } poison, ptr %5, 0 +; CHECK: %7 = insertvalue { ptr, i1 } %6, i1 %4, 1 + cmpxchg ptr %ptr, ptr null, ptr %v seq_cst seq_cst ret void } -define void @pointer_cmpxchg_expand4(i8** %ptr, i8* %v) { +define void @pointer_cmpxchg_expand4(ptr %ptr, ptr %v) { ; CHECK-LABEL: @pointer_cmpxchg_expand4 -; CHECK: %1 = bitcast i8** %ptr to i64* -; CHECK: %2 = ptrtoint i8* %v to i64 -; CHECK: %3 = cmpxchg weak i64* %1, i64 0, i64 %2 seq_cst seq_cst -; CHECK: %4 = extractvalue { i64, i1 } %3, 0 -; CHECK: %5 = extractvalue { i64, i1 } %3, 1 -; CHECK: %6 = inttoptr i64 %4 to i8* -; CHECK: %7 = insertvalue { i8*, i1 } undef, i8* %6, 0 -; CHECK: %8 = insertvalue { i8*, i1 } %7, i1 %5, 1 - cmpxchg weak i8** %ptr, i8* null, i8* %v seq_cst seq_cst +; CHECK: %1 = ptrtoint ptr %v to i64 +; CHECK: %2 = cmpxchg weak ptr %ptr, i64 0, i64 %1 seq_cst seq_cst +; CHECK: %3 = extractvalue { i64, i1 } %2, 0 +; CHECK: %4 = extractvalue { i64, i1 } %2, 1 +; CHECK: %5 = inttoptr i64 %3 to ptr +; CHECK: %6 = insertvalue { ptr, i1 } poison, ptr %5, 0 +; CHECK: %7 = insertvalue { ptr, i1 } %6, i1 %4, 1 + cmpxchg weak ptr %ptr, ptr null, ptr %v seq_cst seq_cst ret void } -define void @pointer_cmpxchg_expand5(i8** %ptr, i8* %v) { +define void @pointer_cmpxchg_expand5(ptr %ptr, ptr %v) { ; CHECK-LABEL: @pointer_cmpxchg_expand5 -; CHECK: %1 = bitcast i8** %ptr to i64* -; CHECK: %2 = ptrtoint i8* %v to i64 -; CHECK: %3 = cmpxchg volatile i64* %1, i64 0, i64 %2 seq_cst seq_cst -; CHECK: %4 = extractvalue { i64, i1 } %3, 0 -; CHECK: %5 = extractvalue { i64, i1 } %3, 1 -; CHECK: %6 = inttoptr i64 %4 to i8* -; CHECK: %7 = insertvalue { i8*, i1 } undef, i8* %6, 0 -; CHECK: %8 = insertvalue { i8*, i1 } %7, i1 %5, 1 - cmpxchg volatile i8** %ptr, i8* null, i8* %v seq_cst seq_cst +; CHECK: %1 = ptrtoint ptr %v to i64 +; CHECK: %2 = cmpxchg volatile ptr %ptr, i64 0, i64 %1 seq_cst seq_cst +; CHECK: %3 = extractvalue { i64, i1 } %2, 0 +; CHECK: %4 = extractvalue { i64, i1 } %2, 1 +; CHECK: %5 = inttoptr i64 %3 to ptr +; CHECK: %6 = insertvalue { ptr, i1 } poison, ptr %5, 0 +; CHECK: %7 = insertvalue { ptr, i1 } %6, i1 %4, 1 + cmpxchg volatile ptr %ptr, ptr null, ptr %v seq_cst seq_cst ret void } -define void @pointer_cmpxchg_expand6(i8 addrspace(2)* addrspace(1)* %ptr, - i8 addrspace(2)* %v) { +define void @pointer_cmpxchg_expand6(ptr addrspace(1) %ptr, + ptr addrspace(2) %v) { ; CHECK-LABEL: @pointer_cmpxchg_expand6 -; CHECK: %1 = bitcast i8 addrspace(2)* addrspace(1)* %ptr to i64 addrspace(1)* -; CHECK: %2 = ptrtoint i8 addrspace(2)* %v to i64 -; CHECK: %3 = cmpxchg i64 addrspace(1)* %1, i64 0, i64 %2 seq_cst seq_cst -; CHECK: %4 = extractvalue { i64, i1 } %3, 0 -; CHECK: %5 = extractvalue { i64, i1 } %3, 1 -; CHECK: %6 = inttoptr i64 %4 to i8 addrspace(2)* -; CHECK: %7 = insertvalue { i8 addrspace(2)*, i1 } undef, i8 addrspace(2)* %6, 0 -; CHECK: %8 = insertvalue { i8 addrspace(2)*, i1 } %7, i1 %5, 1 - cmpxchg i8 addrspace(2)* addrspace(1)* %ptr, i8 addrspace(2)* null, i8 addrspace(2)* %v seq_cst seq_cst +; CHECK: %1 = ptrtoint ptr addrspace(2) %v to i64 +; CHECK: %2 = cmpxchg ptr addrspace(1) %ptr, i64 0, i64 %1 seq_cst seq_cst +; CHECK: %3 = extractvalue { i64, i1 } %2, 0 +; CHECK: %4 = extractvalue { i64, i1 } %2, 1 +; CHECK: %5 = inttoptr i64 %3 to ptr addrspace(2) +; CHECK: %6 = insertvalue { ptr addrspace(2), i1 } poison, ptr addrspace(2) %5, 0 +; CHECK: %7 = insertvalue { ptr addrspace(2), i1 } %6, i1 %4, 1 + cmpxchg ptr addrspace(1) %ptr, ptr addrspace(2) null, ptr addrspace(2) %v seq_cst seq_cst ret void } diff --git a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-fp.ll b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-fp.ll --- a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-fp.ll +++ b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-fp.ll @@ -1,17 +1,16 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -mtriple=i686-linux-gnu -atomic-expand %s | FileCheck %s -define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fadd_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fadd_f32( -; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -19,21 +18,20 @@ ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fadd float* %ptr, float %value seq_cst + %res = atomicrmw fadd ptr %ptr, float %value seq_cst ret float %res } -define double @test_atomicrmw_fadd_f64(double* %ptr, double %value) { +define double @test_atomicrmw_fadd_f64(ptr %ptr, double %value) { ; CHECK-LABEL: @test_atomicrmw_fadd_f64( -; CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fadd double [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; CHECK-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -41,21 +39,20 @@ ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret double [[TMP6]] ; - %res = atomicrmw fadd double* %ptr, double %value seq_cst + %res = atomicrmw fadd ptr %ptr, double %value seq_cst ret double %res } -define float @test_atomicrmw_fadd_f32_as1(float addrspace(1)* %ptr, float %value) { +define float @test_atomicrmw_fadd_f32_as1(ptr addrspace(1) %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fadd_f32_as1( -; CHECK-NEXT: [[TMP1:%.*]] = load float, float addrspace(1)* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(1) [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = bitcast float addrspace(1)* [[PTR]] to i32 addrspace(1)* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32 addrspace(1)* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -63,21 +60,20 @@ ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fadd float addrspace(1)* %ptr, float %value seq_cst + %res = atomicrmw fadd ptr addrspace(1) %ptr, float %value seq_cst ret float %res } -define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) { +define float @test_atomicrmw_fsub_f32(ptr %ptr, float %value) { ; CHECK-LABEL: @test_atomicrmw_fsub_f32( -; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0 ; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float @@ -85,21 +81,20 @@ ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret float [[TMP6]] ; - %res = atomicrmw fsub float* %ptr, float %value seq_cst + %res = atomicrmw fsub ptr %ptr, float %value seq_cst ret float %res } -define double @test_atomicrmw_fsub_f64(double* %ptr, double %value) { +define double @test_atomicrmw_fsub_f64(ptr %ptr, double %value) { ; CHECK-LABEL: @test_atomicrmw_fsub_f64( -; CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[PTR:%.*]], align 8 +; CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[PTR:%.*]], align 8 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi double [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[NEW:%.*]] = fsub double [[LOADED]], [[VALUE:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = bitcast double* [[PTR]] to i64* ; CHECK-NEXT: [[TMP3:%.*]] = bitcast double [[NEW]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = bitcast double [[LOADED]] to i64 -; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i64* [[TMP2]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst +; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg ptr [[PTR]], i64 [[TMP4]], i64 [[TMP3]] seq_cst seq_cst ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1 ; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0 ; CHECK-NEXT: [[TMP6]] = bitcast i64 [[NEWLOADED]] to double @@ -107,6 +102,6 @@ ; CHECK: atomicrmw.end: ; CHECK-NEXT: ret double [[TMP6]] ; - %res = atomicrmw fsub double* %ptr, double %value seq_cst + %res = atomicrmw fsub ptr %ptr, double %value seq_cst ret double %res } diff --git a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-initial-load.ll b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-initial-load.ll --- a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-initial-load.ll +++ b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-rmw-initial-load.ll @@ -3,9 +3,9 @@ ; This file tests the function `llvm::expandAtomicRMWToCmpXchg`. ; It isn't technically target specific, but is exposed through a pass that is. -define i8 @test_initial_load(i8* %ptr, i8 %value) { - %res = atomicrmw nand i8* %ptr, i8 %value seq_cst +define i8 @test_initial_load(ptr %ptr, i8 %value) { + %res = atomicrmw nand ptr %ptr, i8 %value seq_cst ret i8 %res } ; CHECK-LABEL: @test_initial_load -; CHECK-NEXT: %1 = load i8, i8* %ptr, align 1 +; CHECK-NEXT: %1 = load i8, ptr %ptr, align 1 diff --git a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-xchg-fp.ll b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-xchg-fp.ll --- a/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-xchg-fp.ll +++ b/llvm/test/Transforms/AtomicExpand/X86/expand-atomic-xchg-fp.ll @@ -1,14 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt -S -mtriple=i686-linux-gnu -atomic-expand %s | FileCheck %s -define double @atomic_xchg_f64(double* %ptr) nounwind { +define double @atomic_xchg_f64(ptr %ptr) nounwind { ; CHECK-LABEL: @atomic_xchg_f64( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast double* [[PTR:%.*]] to i64* -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64* [[TMP1]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[PTR:%.*]], align 8 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] -; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i64* [[TMP1]], i64 [[LOADED]], i64 4616189618054758400 seq_cst seq_cst, align 8 +; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg ptr [[PTR]], i64 [[LOADED]], i64 4616189618054758400 seq_cst seq_cst, align 8 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP3]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP3]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -16,18 +15,17 @@ ; CHECK-NEXT: [[TMP4:%.*]] = bitcast i64 [[NEWLOADED]] to double ; CHECK-NEXT: ret double [[TMP4]] ; - %result = atomicrmw xchg double* %ptr, double 4.0 seq_cst + %result = atomicrmw xchg ptr %ptr, double 4.0 seq_cst ret double %result } -define double @atomic_xchg_f64_as1(double addrspace(1)* %ptr) nounwind { +define double @atomic_xchg_f64_as1(ptr addrspace(1) %ptr) nounwind { ; CHECK-LABEL: @atomic_xchg_f64_as1( -; CHECK-NEXT: [[TMP1:%.*]] = bitcast double addrspace(1)* [[PTR:%.*]] to i64 addrspace(1)* -; CHECK-NEXT: [[TMP2:%.*]] = load i64, i64 addrspace(1)* [[TMP1]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr addrspace(1) [[PTR:%.*]], align 8 ; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]] ; CHECK: atomicrmw.start: ; CHECK-NEXT: [[LOADED:%.*]] = phi i64 [ [[TMP2]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] -; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg i64 addrspace(1)* [[TMP1]], i64 [[LOADED]], i64 4616189618054758400 seq_cst seq_cst, align 8 +; CHECK-NEXT: [[TMP3:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i64 [[LOADED]], i64 4616189618054758400 seq_cst seq_cst, align 8 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i64, i1 } [[TMP3]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i64, i1 } [[TMP3]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -35,6 +33,6 @@ ; CHECK-NEXT: [[TMP4:%.*]] = bitcast i64 [[NEWLOADED]] to double ; CHECK-NEXT: ret double [[TMP4]] ; - %result = atomicrmw xchg double addrspace(1)* %ptr, double 4.0 seq_cst + %result = atomicrmw xchg ptr addrspace(1) %ptr, double 4.0 seq_cst ret double %result } diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/combine-address-mode.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/combine-address-mode.ll --- a/llvm/test/Transforms/CodeGenPrepare/AArch64/combine-address-mode.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/combine-address-mode.ll @@ -5,74 +5,76 @@ define dso_local i32 @f(i1 %a, i8 %b) local_unnamed_addr { ; CHECK-LABEL: @f( -; CHECK-NEXT: br label [[TMP6:%.*]] -; CHECK: 1: -; CHECK-NEXT: br i1 [[A:%.*]], label [[TMP2:%.*]], label [[TMP6]] -; CHECK: 2: -; CHECK-NEXT: [[TMP3:%.*]] = phi i32* [ getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @_MergedGlobals, i32 0, i32 1), [[TMP1:%.*]] ], [ [[TMP16:%.*]], [[TMP14:%.*]] ] -; CHECK-NEXT: [[TMP4:%.*]] = phi i32* [ getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @_MergedGlobals, i32 0, i32 1), [[TMP1]] ], [ [[TMP15:%.*]], [[TMP14]] ] +; CHECK-NEXT: bb: +; CHECK-NEXT: br label [[BB10:%.*]] +; CHECK: bb1: +; CHECK-NEXT: br i1 [[A:%.*]], label [[BB2:%.*]], label [[BB10]] +; CHECK: bb2: +; CHECK-NEXT: [[I:%.*]] = phi ptr [ getelementptr inbounds (<{ i32, i32 }>, ptr @_MergedGlobals, i32 0, i32 1), [[BB1:%.*]] ], [ [[I20:%.*]], [[BB18:%.*]] ] +; CHECK-NEXT: [[I3:%.*]] = phi ptr [ getelementptr inbounds (<{ i32, i32 }>, ptr @_MergedGlobals, i32 0, i32 1), [[BB1]] ], [ [[I19:%.*]], [[BB18]] ] ; CHECK-NEXT: ret i32 0 -; CHECK: 5: -; CHECK-NEXT: br label [[TMP6]] -; CHECK: 6: -; CHECK-NEXT: [[TMP7:%.*]] = phi i32* [ getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @_MergedGlobals, i32 0, i32 0), [[TMP0:%.*]] ], [ [[TMP3]], [[TMP5:%.*]] ], [ getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @_MergedGlobals, i32 0, i32 1), [[TMP1]] ] -; CHECK-NEXT: [[TMP8:%.*]] = phi i32* [ getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @_MergedGlobals, i32 0, i32 0), [[TMP0]] ], [ [[TMP4]], [[TMP5]] ], [ getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @_MergedGlobals, i32 0, i32 1), [[TMP1]] ] -; CHECK-NEXT: br label [[TMP9:%.*]] -; CHECK: 9: -; CHECK-NEXT: [[TMP10:%.*]] = phi i32* [ [[TMP16]], [[TMP14]] ], [ [[TMP7]], [[TMP6]] ] -; CHECK-NEXT: [[TMP11:%.*]] = phi i32* [ [[TMP16]], [[TMP14]] ], [ [[TMP8]], [[TMP6]] ] -; CHECK-NEXT: [[TMP12:%.*]] = phi i32* [ [[TMP15]], [[TMP14]] ], [ [[TMP8]], [[TMP6]] ] -; CHECK-NEXT: br i1 [[A]], label [[TMP14]], label [[TMP13:%.*]] -; CHECK: 13: -; CHECK-NEXT: store i32 5, i32* [[TMP11]], align 4 -; CHECK-NEXT: br label [[TMP14]] -; CHECK: 14: -; CHECK-NEXT: [[TMP15]] = phi i32* [ [[TMP12]], [[TMP13]] ], [ [[TMP10]], [[TMP9]] ] -; CHECK-NEXT: [[TMP16]] = phi i32* [ [[TMP11]], [[TMP13]] ], [ [[TMP10]], [[TMP9]] ] -; CHECK-NEXT: br i1 [[A]], label [[TMP2]], label [[TMP9]] +; CHECK: bb4: +; CHECK-NEXT: br label [[BB10]] +; CHECK: bb10: +; CHECK-NEXT: [[I11:%.*]] = phi ptr [ @_MergedGlobals, [[BB:%.*]] ], [ [[I]], [[BB4:%.*]] ], [ getelementptr inbounds (<{ i32, i32 }>, ptr @_MergedGlobals, i32 0, i32 1), [[BB1]] ] +; CHECK-NEXT: [[I12:%.*]] = phi ptr [ @_MergedGlobals, [[BB]] ], [ [[I3]], [[BB4]] ], [ getelementptr inbounds (<{ i32, i32 }>, ptr @_MergedGlobals, i32 0, i32 1), [[BB1]] ] +; CHECK-NEXT: br label [[BB13:%.*]] +; CHECK: bb13: +; CHECK-NEXT: [[I14:%.*]] = phi ptr [ [[I20]], [[BB18]] ], [ [[I11]], [[BB10]] ] +; CHECK-NEXT: [[I15:%.*]] = phi ptr [ [[I20]], [[BB18]] ], [ [[I12]], [[BB10]] ] +; CHECK-NEXT: [[I16:%.*]] = phi ptr [ [[I19]], [[BB18]] ], [ [[I12]], [[BB10]] ] +; CHECK-NEXT: br i1 [[A]], label [[BB18]], label [[BB17:%.*]] +; CHECK: bb17: +; CHECK-NEXT: store i32 5, ptr [[I15]], align 4 +; CHECK-NEXT: br label [[BB18]] +; CHECK: bb18: +; CHECK-NEXT: [[I19]] = phi ptr [ [[I16]], [[BB17]] ], [ [[I14]], [[BB13]] ] +; CHECK-NEXT: [[I20]] = phi ptr [ [[I15]], [[BB17]] ], [ [[I14]], [[BB13]] ] +; CHECK-NEXT: br i1 [[A]], label [[BB2]], label [[BB13]] ; - br label %11 +bb: + br label %bb10 -1: ; No predecessors! - br i1 %a, label %2, label %10 +bb1: ; No predecessors! + br i1 %a, label %bb2, label %bb9 -2: ; preds = %22, %1 - %3 = phi i32* [ getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @_MergedGlobals, i32 0, i32 1), %1 ], [ %21, %22 ] - %4 = phi i32* [ getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @_MergedGlobals, i32 0, i32 1), %1 ], [ %20, %22 ] +bb2: ; preds = %bb21, %bb1 + %i = phi ptr [ getelementptr inbounds (<{ i32, i32 }>, ptr @_MergedGlobals, i32 0, i32 1), %bb1 ], [ %i20, %bb21 ] + %i3 = phi ptr [ getelementptr inbounds (<{ i32, i32 }>, ptr @_MergedGlobals, i32 0, i32 1), %bb1 ], [ %i19, %bb21 ] ret i32 0 -5: ; No predecessors! - %6 = icmp ugt i8 %b, 50 - br label %7 +bb4: ; No predecessors! + %i5 = icmp ugt i8 %b, 50 + br label %bb6 -7: ; preds = %10, %5 - %8 = phi i32* [ %3, %5 ], [ getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @_MergedGlobals, i32 0, i32 1), %10 ] - %9 = phi i32* [ %4, %5 ], [ getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @_MergedGlobals, i32 0, i32 1), %10 ] - br label %11 +bb6: ; preds = %bb9, %bb4 + %i7 = phi ptr [ %i, %bb4 ], [ getelementptr inbounds (<{ i32, i32 }>, ptr @_MergedGlobals, i32 0, i32 1), %bb9 ] + %i8 = phi ptr [ %i3, %bb4 ], [ getelementptr inbounds (<{ i32, i32 }>, ptr @_MergedGlobals, i32 0, i32 1), %bb9 ] + br label %bb10 -10: ; preds = %1 - br label %7 +bb9: ; preds = %bb1 + br label %bb6 -11: ; preds = %7, %0 - %12 = phi i32* [ getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @_MergedGlobals, i32 0, i32 0), %0 ], [ %8, %7 ] - %13 = phi i32* [ getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @_MergedGlobals, i32 0, i32 0), %0 ], [ %9, %7 ] - br label %14 +bb10: ; preds = %bb6, %bb + %i11 = phi ptr [ getelementptr inbounds (<{ i32, i32 }>, ptr @_MergedGlobals, i32 0, i32 0), %bb ], [ %i7, %bb6 ] + %i12 = phi ptr [ getelementptr inbounds (<{ i32, i32 }>, ptr @_MergedGlobals, i32 0, i32 0), %bb ], [ %i8, %bb6 ] + br label %bb13 -14: ; preds = %19, %11 - %15 = phi i32* [ %21, %19 ], [ %12, %11 ] - %16 = phi i32* [ %21, %19 ], [ %13, %11 ] - %17 = phi i32* [ %20, %19 ], [ %13, %11 ] - br i1 %a, label %19, label %18 +bb13: ; preds = %bb18, %bb10 + %i14 = phi ptr [ %i20, %bb18 ], [ %i11, %bb10 ] + %i15 = phi ptr [ %i20, %bb18 ], [ %i12, %bb10 ] + %i16 = phi ptr [ %i19, %bb18 ], [ %i12, %bb10 ] + br i1 %a, label %bb18, label %bb17 -18: ; preds = %14 - store i32 5, i32* %16, align 4 - br label %19 +bb17: ; preds = %bb13 + store i32 5, ptr %i15, align 4 + br label %bb18 -19: ; preds = %18, %14 - %20 = phi i32* [ %17, %18 ], [ %15, %14 ] - %21 = phi i32* [ %16, %18 ], [ %15, %14 ] - br i1 %a, label %22, label %14 +bb18: ; preds = %bb17, %bb13 + %i19 = phi ptr [ %i16, %bb17 ], [ %i14, %bb13 ] + %i20 = phi ptr [ %i15, %bb17 ], [ %i14, %bb13 ] + br i1 %a, label %bb21, label %bb13 -22: ; preds = %19 - br label %2 +bb21: ; preds = %bb18 + br label %bb2 } diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/free-zext.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/free-zext.ll --- a/llvm/test/Transforms/CodeGenPrepare/AArch64/free-zext.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/free-zext.ll @@ -2,20 +2,20 @@ ; Test for CodeGenPrepare::optimizeLoadExt(): simple case: two loads ; feeding a phi that zext's each loaded value. -define i32 @test_free_zext(i32* %ptr, i32* %ptr2, i32 %c) { +define i32 @test_free_zext(ptr %ptr, ptr %ptr2, i32 %c) { ; CHECK-LABEL: @test_free_zext( bb1: ; CHECK: bb1: ; CHECK: %[[T1:.*]] = load ; CHECK: %[[A1:.*]] = and i32 %[[T1]], 65535 - %load1 = load i32, i32* %ptr, align 4 + %load1 = load i32, ptr %ptr, align 4 %cmp = icmp ne i32 %c, 0 br i1 %cmp, label %bb2, label %bb3 bb2: ; CHECK: bb2: ; CHECK: %[[T2:.*]] = load ; CHECK: %[[A2:.*]] = and i32 %[[T2]], 65535 - %load2 = load i32, i32* %ptr2, align 4 + %load2 = load i32, ptr %ptr2, align 4 br label %bb3 bb3: ; CHECK: bb3: @@ -27,24 +27,24 @@ ; Test for CodeGenPrepare::optimizeLoadExt(): exercise all opcode ; cases of active bit calculation. -define i32 @test_free_zext2(i32* %ptr, i16* %dst16, i32* %dst32, i32 %c) { +define i32 @test_free_zext2(ptr %ptr, ptr %dst16, ptr %dst32, i32 %c) { ; CHECK-LABEL: @test_free_zext2( bb1: ; CHECK: bb1: ; CHECK: %[[T1:.*]] = load ; CHECK: %[[A1:.*]] = and i32 %[[T1]], 65535 - %load1 = load i32, i32* %ptr, align 4 + %load1 = load i32, ptr %ptr, align 4 %cmp = icmp ne i32 %c, 0 br i1 %cmp, label %bb2, label %bb4 bb2: ; CHECK: bb2: %trunc = trunc i32 %load1 to i16 - store i16 %trunc, i16* %dst16, align 2 + store i16 %trunc, ptr %dst16, align 2 br i1 %cmp, label %bb3, label %bb4 bb3: ; CHECK: bb3: %shl = shl i32 %load1, 16 - store i32 %shl, i32* %dst32, align 4 + store i32 %shl, ptr %dst32, align 4 br label %bb4 bb4: ; CHECK: bb4: @@ -56,25 +56,25 @@ ; Test for CodeGenPrepare::optimizeLoadExt(): check case of zext-able ; load feeding a phi in the same block. -define void @test_free_zext3(i32* %ptr, i32* %ptr2, i32* %dst, i64* %c) { +define void @test_free_zext3(ptr %ptr, ptr %ptr2, ptr %dst, ptr %c) { ; CHECK-LABEL: @test_free_zext3( bb1: ; CHECK: bb1: ; CHECK: %[[T1:.*]] = load ; CHECK: %[[A1:.*]] = and i32 %[[T1]], 65535 - %load1 = load i32, i32* %ptr, align 4 + %load1 = load i32, ptr %ptr, align 4 br label %loop loop: ; CHECK: loop: ; CHECK: phi i32 [ %[[A1]], %bb1 ], [ %[[A2:.*]], %loop ] %phi = phi i32 [ %load1, %bb1 ], [ %load2, %loop ] %and = and i32 %phi, 65535 - store i32 %and, i32* %dst, align 4 - %idx = load volatile i64, i64* %c, align 4 - %addr = getelementptr inbounds i32, i32* %ptr2, i64 %idx + store i32 %and, ptr %dst, align 4 + %idx = load volatile i64, ptr %c, align 4 + %addr = getelementptr inbounds i32, ptr %ptr2, i64 %idx ; CHECK: %[[T2:.*]] = load i32 ; CHECK: %[[A2]] = and i32 %[[T2]], 65535 - %load2 = load i32, i32* %addr, align 4 + %load2 = load i32, ptr %addr, align 4 %cmp = icmp ne i64 %idx, 0 br i1 %cmp, label %loop, label %end end: diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll --- a/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll @@ -7,107 +7,107 @@ @c = external dso_local global %struct.a, align 4 @glob_array = internal unnamed_addr constant [16 x i32] [i32 1, i32 1, i32 2, i32 3, i32 5, i32 8, i32 13, i32 21, i32 34, i32 55, i32 89, i32 144, i32 233, i32 377, i32 610, i32 987], align 16 -define @splat_base(i32* %base, %index, %mask) #0 { +define @splat_base(ptr %base, %index, %mask) #0 { ; CHECK-LABEL: @splat_base( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, i32* [[BASE:%.*]], [[INDEX:%.*]] -; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( [[TMP1]], i32 4, [[MASK:%.*]], undef) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[BASE:%.*]], [[INDEX:%.*]] +; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP1]], i32 4, [[MASK:%.*]], undef) ; CHECK-NEXT: ret [[RES]] ; - %broadcast.splatinsert = insertelement poison, i32* %base, i32 0 - %broadcast.splat = shufflevector %broadcast.splatinsert, poison, zeroinitializer - %gep = getelementptr i32, %broadcast.splat, %index - %res = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %gep, i32 4, %mask, undef) + %broadcast.splatinsert = insertelement poison, ptr %base, i32 0 + %broadcast.splat = shufflevector %broadcast.splatinsert, poison, zeroinitializer + %gep = getelementptr i32, %broadcast.splat, %index + %res = call @llvm.masked.gather.nxv4i32.nxv4p0( %gep, i32 4, %mask, undef) ret %res } -define @splat_struct(%struct.a* %base, %mask) #0 { +define @splat_struct(ptr %base, %mask) #0 { ; CHECK-LABEL: @splat_struct( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [[STRUCT_A:%.*]], %struct.a* [[BASE:%.*]], i64 0, i32 1 -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], zeroinitializer -; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( [[TMP2]], i32 4, [[MASK:%.*]], undef) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [[STRUCT_A:%.*]], ptr [[BASE:%.*]], i64 0, i32 1 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[TMP1]], zeroinitializer +; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP2]], i32 4, [[MASK:%.*]], undef) ; CHECK-NEXT: ret [[RES]] ; - %gep = getelementptr %struct.a, %struct.a* %base, zeroinitializer, i32 1 - %res = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %gep, i32 4, %mask, undef) + %gep = getelementptr %struct.a, ptr %base, zeroinitializer, i32 1 + %res = call @llvm.masked.gather.nxv4i32.nxv4p0( %gep, i32 4, %mask, undef) ret %res } -define @scalar_index(i32* %base, i64 %index, %mask) #0 { +define @scalar_index(ptr %base, i64 %index, %mask) #0 { ; CHECK-LABEL: @scalar_index( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i64 [[INDEX:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], zeroinitializer -; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( [[TMP2]], i32 4, [[MASK:%.*]], undef) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[BASE:%.*]], i64 [[INDEX:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[TMP1]], zeroinitializer +; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP2]], i32 4, [[MASK:%.*]], undef) ; CHECK-NEXT: ret [[RES]] ; - %broadcast.splatinsert = insertelement poison, i32* %base, i32 0 - %broadcast.splat = shufflevector %broadcast.splatinsert, poison, zeroinitializer - %gep = getelementptr i32, %broadcast.splat, i64 %index - %res = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %gep, i32 4, %mask, undef) + %broadcast.splatinsert = insertelement poison, ptr %base, i32 0 + %broadcast.splat = shufflevector %broadcast.splatinsert, poison, zeroinitializer + %gep = getelementptr i32, %broadcast.splat, i64 %index + %res = call @llvm.masked.gather.nxv4i32.nxv4p0( %gep, i32 4, %mask, undef) ret %res } -define @splat_index(i32* %base, i64 %index, %mask) #0 { +define @splat_index(ptr %base, i64 %index, %mask) #0 { ; CHECK-LABEL: @splat_index( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i64 [[INDEX:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], zeroinitializer -; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( [[TMP2]], i32 4, [[MASK:%.*]], undef) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[BASE:%.*]], i64 [[INDEX:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[TMP1]], zeroinitializer +; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP2]], i32 4, [[MASK:%.*]], undef) ; CHECK-NEXT: ret [[RES]] ; %broadcast.splatinsert = insertelement poison, i64 %index, i32 0 %broadcast.splat = shufflevector %broadcast.splatinsert, poison, zeroinitializer - %gep = getelementptr i32, i32* %base, %broadcast.splat - %res = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %gep, i32 4, %mask, undef) + %gep = getelementptr i32, ptr %base, %broadcast.splat + %res = call @llvm.masked.gather.nxv4i32.nxv4p0( %gep, i32 4, %mask, undef) ret %res } define @test_global_array( %indxs, %mask) #0 { ; CHECK-LABEL: @test_global_array( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @glob_array, i64 0, i64 0), [[INDXS:%.*]] -; CHECK-NEXT: [[G:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( [[TMP1]], i32 4, [[MASK:%.*]], undef) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr @glob_array, [[INDXS:%.*]] +; CHECK-NEXT: [[G:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP1]], i32 4, [[MASK:%.*]], undef) ; CHECK-NEXT: ret [[G]] ; - %p = getelementptr inbounds [16 x i32], [16 x i32]* @glob_array, i64 0, %indxs - %g = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %p, i32 4, %mask, undef) + %p = getelementptr inbounds [16 x i32], ptr @glob_array, i64 0, %indxs + %g = call @llvm.masked.gather.nxv4i32.nxv4p0( %p, i32 4, %mask, undef) ret %g } define @global_struct_splat( %mask) #0 { ; CHECK-LABEL: @global_struct_splat( -; CHECK-NEXT: [[TMP1:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( shufflevector ( insertelement ( poison, i32* getelementptr inbounds ([[STRUCT_A:%.*]], %struct.a* @c, i64 0, i32 1), i32 0), poison, zeroinitializer), i32 4, [[MASK:%.*]], undef) +; CHECK-NEXT: [[TMP1:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( shufflevector ( insertelement ( poison, ptr getelementptr inbounds ([[STRUCT_A:%.*]], ptr @c, i64 0, i32 1), i32 0), poison, zeroinitializer), i32 4, [[MASK:%.*]], undef) ; CHECK-NEXT: ret [[TMP1]] ; - %1 = insertelement poison, %struct.a* @c, i32 0 - %2 = shufflevector %1, poison, zeroinitializer - %3 = getelementptr %struct.a, %2, zeroinitializer, i32 1 - %4 = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %3, i32 4, %mask, undef) + %1 = insertelement poison, ptr @c, i32 0 + %2 = shufflevector %1, poison, zeroinitializer + %3 = getelementptr %struct.a, %2, zeroinitializer, i32 1 + %4 = call @llvm.masked.gather.nxv4i32.nxv4p0( %3, i32 4, %mask, undef) ret %4 } -define @splat_ptr_gather(i32* %ptr, %mask, %passthru) #0 { +define @splat_ptr_gather(ptr %ptr, %mask, %passthru) #0 { ; CHECK-LABEL: @splat_ptr_gather( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, i32* [[PTR:%.*]], zeroinitializer -; CHECK-NEXT: [[TMP2:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( [[TMP1]], i32 4, [[MASK:%.*]], [[PASSTHRU:%.*]]) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[PTR:%.*]], zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP1]], i32 4, [[MASK:%.*]], [[PASSTHRU:%.*]]) ; CHECK-NEXT: ret [[TMP2]] ; - %1 = insertelement poison, i32* %ptr, i32 0 - %2 = shufflevector %1, poison, zeroinitializer - %3 = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %2, i32 4, %mask, %passthru) + %1 = insertelement poison, ptr %ptr, i32 0 + %2 = shufflevector %1, poison, zeroinitializer + %3 = call @llvm.masked.gather.nxv4i32.nxv4p0( %2, i32 4, %mask, %passthru) ret %3 } -define void @splat_ptr_scatter(i32* %ptr, %mask, %val) #0 { +define void @splat_ptr_scatter(ptr %ptr, %mask, %val) #0 { ; CHECK-LABEL: @splat_ptr_scatter( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, i32* [[PTR:%.*]], zeroinitializer -; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0i32( [[VAL:%.*]], [[TMP1]], i32 4, [[MASK:%.*]]) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[PTR:%.*]], zeroinitializer +; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0( [[VAL:%.*]], [[TMP1]], i32 4, [[MASK:%.*]]) ; CHECK-NEXT: ret void ; - %1 = insertelement poison, i32* %ptr, i32 0 - %2 = shufflevector %1, poison, zeroinitializer - call void @llvm.masked.scatter.nxv4i32.nxv4p0i32( %val, %2, i32 4, %mask) + %1 = insertelement poison, ptr %ptr, i32 0 + %2 = shufflevector %1, poison, zeroinitializer + call void @llvm.masked.scatter.nxv4i32.nxv4p0( %val, %2, i32 4, %mask) ret void } -declare @llvm.masked.gather.nxv4i32.nxv4p0i32(, i32, , ) -declare void @llvm.masked.scatter.nxv4i32.nxv4p0i32(, , i32, ) +declare @llvm.masked.gather.nxv4i32.nxv4p0(, i32, , ) +declare void @llvm.masked.scatter.nxv4i32.nxv4p0(, , i32, ) attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt.ll --- a/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt.ll @@ -7,107 +7,107 @@ @c = external dso_local global %struct.a, align 4 @glob_array = internal unnamed_addr constant [16 x i32] [i32 1, i32 1, i32 2, i32 3, i32 5, i32 8, i32 13, i32 21, i32 34, i32 55, i32 89, i32 144, i32 233, i32 377, i32 610, i32 987], align 16 -define @splat_base(i32* %base, %index, %mask) #0 { +define @splat_base(ptr %base, %index, %mask) #0 { ; CHECK-LABEL: @splat_base( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, i32* [[BASE:%.*]], [[INDEX:%.*]] -; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( [[TMP1]], i32 4, [[MASK:%.*]], undef) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[BASE:%.*]], [[INDEX:%.*]] +; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP1]], i32 4, [[MASK:%.*]], undef) ; CHECK-NEXT: ret [[RES]] ; - %broadcast.splatinsert = insertelement undef, i32* %base, i32 0 - %broadcast.splat = shufflevector %broadcast.splatinsert, undef, zeroinitializer - %gep = getelementptr i32, %broadcast.splat, %index - %res = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %gep, i32 4, %mask, undef) + %broadcast.splatinsert = insertelement undef, ptr %base, i32 0 + %broadcast.splat = shufflevector %broadcast.splatinsert, undef, zeroinitializer + %gep = getelementptr i32, %broadcast.splat, %index + %res = call @llvm.masked.gather.nxv4i32.nxv4p0( %gep, i32 4, %mask, undef) ret %res } -define @splat_struct(%struct.a* %base, %mask) #0 { +define @splat_struct(ptr %base, %mask) #0 { ; CHECK-LABEL: @splat_struct( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [[STRUCT_A:%.*]], %struct.a* [[BASE:%.*]], i64 0, i32 1 -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], zeroinitializer -; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( [[TMP2]], i32 4, [[MASK:%.*]], undef) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr [[STRUCT_A:%.*]], ptr [[BASE:%.*]], i64 0, i32 1 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[TMP1]], zeroinitializer +; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP2]], i32 4, [[MASK:%.*]], undef) ; CHECK-NEXT: ret [[RES]] ; - %gep = getelementptr %struct.a, %struct.a* %base, zeroinitializer, i32 1 - %res = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %gep, i32 4, %mask, undef) + %gep = getelementptr %struct.a, ptr %base, zeroinitializer, i32 1 + %res = call @llvm.masked.gather.nxv4i32.nxv4p0( %gep, i32 4, %mask, undef) ret %res } -define @scalar_index(i32* %base, i64 %index, %mask) #0 { +define @scalar_index(ptr %base, i64 %index, %mask) #0 { ; CHECK-LABEL: @scalar_index( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i64 [[INDEX:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], zeroinitializer -; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( [[TMP2]], i32 4, [[MASK:%.*]], undef) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[BASE:%.*]], i64 [[INDEX:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[TMP1]], zeroinitializer +; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP2]], i32 4, [[MASK:%.*]], undef) ; CHECK-NEXT: ret [[RES]] ; - %broadcast.splatinsert = insertelement undef, i32* %base, i32 0 - %broadcast.splat = shufflevector %broadcast.splatinsert, undef, zeroinitializer - %gep = getelementptr i32, %broadcast.splat, i64 %index - %res = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %gep, i32 4, %mask, undef) + %broadcast.splatinsert = insertelement undef, ptr %base, i32 0 + %broadcast.splat = shufflevector %broadcast.splatinsert, undef, zeroinitializer + %gep = getelementptr i32, %broadcast.splat, i64 %index + %res = call @llvm.masked.gather.nxv4i32.nxv4p0( %gep, i32 4, %mask, undef) ret %res } -define @splat_index(i32* %base, i64 %index, %mask) #0 { +define @splat_index(ptr %base, i64 %index, %mask) #0 { ; CHECK-LABEL: @splat_index( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i64 [[INDEX:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], zeroinitializer -; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( [[TMP2]], i32 4, [[MASK:%.*]], undef) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[BASE:%.*]], i64 [[INDEX:%.*]] +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[TMP1]], zeroinitializer +; CHECK-NEXT: [[RES:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP2]], i32 4, [[MASK:%.*]], undef) ; CHECK-NEXT: ret [[RES]] ; %broadcast.splatinsert = insertelement undef, i64 %index, i32 0 %broadcast.splat = shufflevector %broadcast.splatinsert, undef, zeroinitializer - %gep = getelementptr i32, i32* %base, %broadcast.splat - %res = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %gep, i32 4, %mask, undef) + %gep = getelementptr i32, ptr %base, %broadcast.splat + %res = call @llvm.masked.gather.nxv4i32.nxv4p0( %gep, i32 4, %mask, undef) ret %res } define @test_global_array( %indxs, %mask) #0 { ; CHECK-LABEL: @test_global_array( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @glob_array, i64 0, i64 0), [[INDXS:%.*]] -; CHECK-NEXT: [[G:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( [[TMP1]], i32 4, [[MASK:%.*]], undef) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr @glob_array, [[INDXS:%.*]] +; CHECK-NEXT: [[G:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP1]], i32 4, [[MASK:%.*]], undef) ; CHECK-NEXT: ret [[G]] ; - %p = getelementptr inbounds [16 x i32], [16 x i32]* @glob_array, i64 0, %indxs - %g = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %p, i32 4, %mask, undef) + %p = getelementptr inbounds [16 x i32], ptr @glob_array, i64 0, %indxs + %g = call @llvm.masked.gather.nxv4i32.nxv4p0( %p, i32 4, %mask, undef) ret %g } define @global_struct_splat( %mask) #0 { ; CHECK-LABEL: @global_struct_splat( -; CHECK-NEXT: [[TMP1:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( shufflevector ( insertelement ( poison, i32* getelementptr inbounds ([[STRUCT_A:%.*]], %struct.a* @c, i64 0, i32 1), i32 0), poison, zeroinitializer), i32 4, [[MASK:%.*]], undef) +; CHECK-NEXT: [[TMP1:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( shufflevector ( insertelement ( poison, ptr getelementptr inbounds ([[STRUCT_A:%.*]], ptr @c, i64 0, i32 1), i32 0), poison, zeroinitializer), i32 4, [[MASK:%.*]], undef) ; CHECK-NEXT: ret [[TMP1]] ; - %1 = insertelement undef, %struct.a* @c, i32 0 - %2 = shufflevector %1, undef, zeroinitializer - %3 = getelementptr %struct.a, %2, zeroinitializer, i32 1 - %4 = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %3, i32 4, %mask, undef) + %1 = insertelement undef, ptr @c, i32 0 + %2 = shufflevector %1, undef, zeroinitializer + %3 = getelementptr %struct.a, %2, zeroinitializer, i32 1 + %4 = call @llvm.masked.gather.nxv4i32.nxv4p0( %3, i32 4, %mask, undef) ret %4 } -define @splat_ptr_gather(i32* %ptr, %mask, %passthru) #0 { +define @splat_ptr_gather(ptr %ptr, %mask, %passthru) #0 { ; CHECK-LABEL: @splat_ptr_gather( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, i32* [[PTR:%.*]], zeroinitializer -; CHECK-NEXT: [[TMP2:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0i32( [[TMP1]], i32 4, [[MASK:%.*]], [[PASSTHRU:%.*]]) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[PTR:%.*]], zeroinitializer +; CHECK-NEXT: [[TMP2:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP1]], i32 4, [[MASK:%.*]], [[PASSTHRU:%.*]]) ; CHECK-NEXT: ret [[TMP2]] ; - %1 = insertelement undef, i32* %ptr, i32 0 - %2 = shufflevector %1, undef, zeroinitializer - %3 = call @llvm.masked.gather.nxv4i32.nxv4p0i32( %2, i32 4, %mask, %passthru) + %1 = insertelement undef, ptr %ptr, i32 0 + %2 = shufflevector %1, undef, zeroinitializer + %3 = call @llvm.masked.gather.nxv4i32.nxv4p0( %2, i32 4, %mask, %passthru) ret %3 } -define void @splat_ptr_scatter(i32* %ptr, %mask, %val) #0 { +define void @splat_ptr_scatter(ptr %ptr, %mask, %val) #0 { ; CHECK-LABEL: @splat_ptr_scatter( -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, i32* [[PTR:%.*]], zeroinitializer -; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0i32( [[VAL:%.*]], [[TMP1]], i32 4, [[MASK:%.*]]) +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[PTR:%.*]], zeroinitializer +; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0( [[VAL:%.*]], [[TMP1]], i32 4, [[MASK:%.*]]) ; CHECK-NEXT: ret void ; - %1 = insertelement undef, i32* %ptr, i32 0 - %2 = shufflevector %1, undef, zeroinitializer - call void @llvm.masked.scatter.nxv4i32.nxv4p0i32( %val, %2, i32 4, %mask) + %1 = insertelement undef, ptr %ptr, i32 0 + %2 = shufflevector %1, undef, zeroinitializer + call void @llvm.masked.scatter.nxv4i32.nxv4p0( %val, %2, i32 4, %mask) ret void } -declare @llvm.masked.gather.nxv4i32.nxv4p0i32(, i32, , ) -declare void @llvm.masked.scatter.nxv4i32.nxv4p0i32(, , i32, ) +declare @llvm.masked.gather.nxv4i32.nxv4p0(, i32, , ) +declare void @llvm.masked.scatter.nxv4i32.nxv4p0(, , i32, ) attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/large-offset-gep.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/large-offset-gep.ll --- a/llvm/test/Transforms/CodeGenPrepare/AArch64/large-offset-gep.ll +++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/large-offset-gep.ll @@ -3,7 +3,7 @@ %struct_type = type { [10000 x i32], i32, i32 } -define void @test1(%struct_type** %s, i32 %n) { +define void @test1(ptr %s, i32 %n) { ; CHECK-LABEL: test1: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: ldr x9, [x0] @@ -22,27 +22,27 @@ ; CHECK-NEXT: .LBB0_2: // %while_end ; CHECK-NEXT: ret entry: - %struct = load %struct_type*, %struct_type** %s + %struct = load ptr, ptr %s br label %while_cond while_cond: %phi = phi i32 [ 0, %entry ], [ %i, %while_body ] - %gep0 = getelementptr %struct_type, %struct_type* %struct, i64 0, i32 1 - %gep1 = getelementptr %struct_type, %struct_type* %struct, i64 0, i32 2 + %gep0 = getelementptr %struct_type, ptr %struct, i64 0, i32 1 + %gep1 = getelementptr %struct_type, ptr %struct, i64 0, i32 2 %cmp = icmp slt i32 %phi, %n br i1 %cmp, label %while_body, label %while_end while_body: %i = add i32 %phi, 1 - store i32 %i, i32* %gep0 - store i32 %phi, i32* %gep1 + store i32 %i, ptr %gep0 + store i32 %phi, ptr %gep1 br label %while_cond while_end: ret void } -define void @test2(%struct_type* %struct, i32 %n) { +define void @test2(ptr %struct, i32 %n) { ; CHECK-LABEL: test2: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: cbz x0, .LBB1_3 @@ -62,27 +62,27 @@ ; CHECK-NEXT: .LBB1_3: // %while_end ; CHECK-NEXT: ret entry: - %cmp = icmp eq %struct_type* %struct, null + %cmp = icmp eq ptr %struct, null br i1 %cmp, label %while_end, label %while_cond while_cond: %phi = phi i32 [ 0, %entry ], [ %i, %while_body ] - %gep0 = getelementptr %struct_type, %struct_type* %struct, i64 0, i32 1 - %gep1 = getelementptr %struct_type, %struct_type* %struct, i64 0, i32 2 + %gep0 = getelementptr %struct_type, ptr %struct, i64 0, i32 1 + %gep1 = getelementptr %struct_type, ptr %struct, i64 0, i32 2 %cmp1 = icmp slt i32 %phi, %n br i1 %cmp1, label %while_body, label %while_end while_body: %i = add i32 %phi, 1 - store i32 %i, i32* %gep0 - store i32 %phi, i32* %gep1 + store i32 %i, ptr %gep0 + store i32 %phi, ptr %gep1 br label %while_cond while_end: ret void } -define void @test3(%struct_type* %s1, %struct_type* %s2, i1 %cond, i32 %n) { +define void @test3(ptr %s1, ptr %s2, i1 %cond, i32 %n) { ; CHECK-LABEL: test3: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: tst w2, #0x1 @@ -110,31 +110,31 @@ br label %if_end if_end: - %struct = phi %struct_type* [ %s1, %entry ], [ %s2, %if_true ] - %cmp = icmp eq %struct_type* %struct, null + %struct = phi ptr [ %s1, %entry ], [ %s2, %if_true ] + %cmp = icmp eq ptr %struct, null br i1 %cmp, label %while_end, label %while_cond while_cond: %phi = phi i32 [ 0, %if_end ], [ %i, %while_body ] - %gep0 = getelementptr %struct_type, %struct_type* %struct, i64 0, i32 1 - %gep1 = getelementptr %struct_type, %struct_type* %struct, i64 0, i32 2 + %gep0 = getelementptr %struct_type, ptr %struct, i64 0, i32 1 + %gep1 = getelementptr %struct_type, ptr %struct, i64 0, i32 2 %cmp1 = icmp slt i32 %phi, %n br i1 %cmp1, label %while_body, label %while_end while_body: %i = add i32 %phi, 1 - store i32 %i, i32* %gep0 - store i32 %phi, i32* %gep1 + store i32 %i, ptr %gep0 + store i32 %phi, ptr %gep1 br label %while_cond while_end: ret void } -declare %struct_type* @foo() +declare ptr @foo() declare void @foo2() -define void @test4(i32 %n) uwtable personality i32 (...)* @__FrameHandler { +define void @test4(i32 %n) uwtable personality ptr @__FrameHandler { ; CHECK-LABEL: test4: ; CHECK: .Lfunc_begin0: ; CHECK-NEXT: .cfi_startproc @@ -190,34 +190,34 @@ while_cond: %phi = phi i32 [ 0, %entry ], [ %i, %while_body ] - %struct = invoke %struct_type* @foo() to label %while_cond_x unwind label %cleanup + %struct = invoke ptr @foo() to label %while_cond_x unwind label %cleanup while_cond_x: - %gep0 = getelementptr %struct_type, %struct_type* %struct, i64 0, i32 1 - %gep1 = getelementptr %struct_type, %struct_type* %struct, i64 0, i32 2 - store i32 0, i32* %gep0 + %gep0 = getelementptr %struct_type, ptr %struct, i64 0, i32 1 + %gep1 = getelementptr %struct_type, ptr %struct, i64 0, i32 2 + store i32 0, ptr %gep0 %cmp = icmp slt i32 %phi, %n br i1 %cmp, label %while_body, label %while_end while_body: %i = add i32 %phi, 1 - store i32 %i, i32* %gep0 - store i32 %phi, i32* %gep1 + store i32 %i, ptr %gep0 + store i32 %phi, ptr %gep1 br label %while_cond while_end: ret void cleanup: - %x10 = landingpad { i8*, i32 } + %x10 = landingpad { ptr, i32 } cleanup call void @foo2() - resume { i8*, i32 } %x10 + resume { ptr, i32 } %x10 } declare i32 @__FrameHandler(...) -define void @test5([65536 x i32]** %s, i32 %n) { +define void @test5(ptr %s, i32 %n) { ; CHECK-LABEL: test5: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: ldr x9, [x0] @@ -236,62 +236,61 @@ ; CHECK-NEXT: .LBB4_2: // %while_end ; CHECK-NEXT: ret entry: - %struct = load [65536 x i32]*, [65536 x i32]** %s + %struct = load ptr, ptr %s br label %while_cond while_cond: %phi = phi i32 [ 0, %entry ], [ %i, %while_body ] - %gep0 = getelementptr [65536 x i32], [65536 x i32]* %struct, i64 0, i32 20000 - %gep1 = getelementptr [65536 x i32], [65536 x i32]* %struct, i64 0, i32 20001 + %gep0 = getelementptr [65536 x i32], ptr %struct, i64 0, i32 20000 + %gep1 = getelementptr [65536 x i32], ptr %struct, i64 0, i32 20001 %cmp = icmp slt i32 %phi, %n br i1 %cmp, label %while_body, label %while_end while_body: %i = add i32 %phi, 1 - store i32 %i, i32* %gep0 - store i32 %phi, i32* %gep1 + store i32 %i, ptr %gep0 + store i32 %phi, ptr %gep1 br label %while_cond while_end: ret void } -declare i8* @llvm.strip.invariant.group.p0i8(i8*) +declare ptr @llvm.strip.invariant.group.p0(ptr) -define void @test_invariant_group(i32) { +define void @test_invariant_group(i32 %arg) { ; CHECK-LABEL: test_invariant_group: -; CHECK: // %bb.0: +; CHECK: // %bb.0: // %bb ; CHECK-NEXT: cbz wzr, .LBB5_2 -; CHECK-NEXT: // %bb.1: +; CHECK-NEXT: // %bb.1: // %bb6 ; CHECK-NEXT: cbz w0, .LBB5_3 -; CHECK-NEXT: .LBB5_2: +; CHECK-NEXT: .LBB5_2: // %bb5 ; CHECK-NEXT: ret -; CHECK-NEXT: .LBB5_3: +; CHECK-NEXT: .LBB5_3: // %bb2 ; CHECK-NEXT: cbnz wzr, .LBB5_2 -; CHECK-NEXT: // %bb.4: +; CHECK-NEXT: // %bb.4: // %bb4 ; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: str x8, [x8] ; CHECK-NEXT: ret - br i1 undef, label %8, label %7 +bb: + br i1 undef, label %bb6, label %bb5 -;