diff --git a/llvm/include/llvm/Support/AArch64TargetParser.h b/llvm/include/llvm/Support/AArch64TargetParser.h --- a/llvm/include/llvm/Support/AArch64TargetParser.h +++ b/llvm/include/llvm/Support/AArch64TargetParser.h @@ -79,52 +79,37 @@ }; enum class ArchKind { -#define AARCH64_ARCH(NAME, ID, SUB_ARCH, ARCH_BASE_EXT) ID, +#define AARCH64_ARCH(NAME, ID, ARCH_FEATURE, ARCH_BASE_EXT) ID, #include "AArch64TargetParser.def" }; struct ArchNames { - const char *NameCStr; - size_t NameLength; - const char *SubArchCStr; - size_t SubArchLength; + StringRef Name; + StringRef ArchFeature; uint64_t ArchBaseExtensions; ArchKind ID; - StringRef getName() const { return StringRef(NameCStr, NameLength); } - - // Sub-Arch name. - StringRef getSubArch() const { - return getArchFeature().substr(1, SubArchLength); - } - - // Arch Feature name. - StringRef getArchFeature() const { - return StringRef(SubArchCStr, SubArchLength); - } + // Return ArchFeature without the leading "+". + StringRef getSubArch() const { return ArchFeature.substr(1); } }; const ArchNames AArch64ARCHNames[] = { -#define AARCH64_ARCH(NAME, ID, SUB_ARCH, ARCH_BASE_EXT) \ - {NAME, sizeof(NAME) - 1, "+" SUB_ARCH, sizeof(SUB_ARCH), \ - ARCH_BASE_EXT, AArch64::ArchKind::ID}, +#define AARCH64_ARCH(NAME, ID, ARCH_FEATURE, ARCH_BASE_EXT) \ + {NAME, ARCH_FEATURE, ARCH_BASE_EXT, AArch64::ArchKind::ID}, #include "AArch64TargetParser.def" }; // List of Arch Extension names. struct ExtName { - const char *NameCStr; - size_t NameLength; + StringRef Name; uint64_t ID; - const char *Feature; - const char *NegFeature; - - StringRef getName() const { return StringRef(NameCStr, NameLength); } + StringRef Feature; + StringRef NegFeature; }; const ExtName AArch64ARCHExtNames[] = { #define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) \ - {NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE}, + {NAME, ID, FEATURE, NEGFEATURE}, #include "AArch64TargetParser.def" }; @@ -133,37 +118,28 @@ // When finding the Arch for a CPU, first-found prevails. Sort them accordingly. // When this becomes table-generated, we'd probably need two tables. struct CpuNames { - const char *NameCStr; - size_t NameLength; + StringRef Name; ArchKind ArchID; bool Default; // is $Name the default CPU for $ArchID ? uint64_t DefaultExtensions; - - StringRef getName() const { return StringRef(NameCStr, NameLength); } }; const CpuNames AArch64CPUNames[] = { #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ - {NAME, sizeof(NAME) - 1, AArch64::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT}, + {NAME, AArch64::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT}, #include "AArch64TargetParser.def" }; const struct { - const char *Alias; - size_t AliasLength; - const char *Name; - size_t NameLength; - - StringRef getAlias() const { return StringRef(Alias, AliasLength); } - StringRef getName() const { return StringRef(Name, NameLength); } + StringRef Alias; + StringRef Name; } AArch64CPUAliases[] = { -#define AARCH64_CPU_ALIAS(ALIAS,NAME) \ - {ALIAS, sizeof(ALIAS) - 1, NAME, sizeof(NAME) - 1}, +#define AARCH64_CPU_ALIAS(ALIAS, NAME) {ALIAS, NAME}, #include "AArch64TargetParser.def" }; const ArchKind ArchKinds[] = { -#define AARCH64_ARCH(NAME, ID, SUB_ARCH, ARCH_BASE_EXT) ArchKind::ID, +#define AARCH64_ARCH(NAME, ID, ARCH_FEATURE, ARCH_BASE_EXT) ArchKind::ID, #include "AArch64TargetParser.def" }; diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def b/llvm/include/llvm/Support/AArch64TargetParser.def --- a/llvm/include/llvm/Support/AArch64TargetParser.def +++ b/llvm/include/llvm/Support/AArch64TargetParser.def @@ -13,85 +13,85 @@ // NOTE: NO INCLUDE GUARD DESIRED! #ifndef AARCH64_ARCH -#define AARCH64_ARCH(NAME, ID, SUB_ARCH, ARCH_BASE_EXT) +#define AARCH64_ARCH(NAME, ID, ARCH_FEATURE, ARCH_BASE_EXT) #endif // NOTE: The order and the grouping of the elements matter to make ArchKind iterable. // List is organised as armv8a -> armv8n-a, armv9a -> armv9m-a and armv8-r. -AARCH64_ARCH("invalid", INVALID, "", +AARCH64_ARCH("invalid", INVALID, "+", AArch64::AEK_NONE) -AARCH64_ARCH("armv8-a", ARMV8A, "v8a", +AARCH64_ARCH("armv8-a", ARMV8A, "+v8a", (AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD)) -AARCH64_ARCH("armv8.1-a", ARMV8_1A, "v8.1a", +AARCH64_ARCH("armv8.1-a", ARMV8_1A, "+v8.1a", (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_LSE | AArch64::AEK_RDM)) -AARCH64_ARCH("armv8.2-a", ARMV8_2A, "v8.2a", +AARCH64_ARCH("armv8.2-a", ARMV8_2A, "+v8.2a", (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM)) -AARCH64_ARCH("armv8.3-a", ARMV8_3A, "v8.3a", +AARCH64_ARCH("armv8.3-a", ARMV8_3A, "+v8.3a", (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC)) -AARCH64_ARCH("armv8.4-a", ARMV8_4A, "v8.4a", +AARCH64_ARCH("armv8.4-a", ARMV8_4A, "+v8.4a", (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD)) -AARCH64_ARCH("armv8.5-a", ARMV8_5A, "v8.5a", +AARCH64_ARCH("armv8.5-a", ARMV8_5A, "+v8.5a", (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD)) -AARCH64_ARCH("armv8.6-a", ARMV8_6A, "v8.6a", +AARCH64_ARCH("armv8.6-a", ARMV8_6A, "+v8.6a", (AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 | AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM)) -AARCH64_ARCH("armv8.7-a", ARMV8_7A, "v8.7a", +AARCH64_ARCH("armv8.7-a", ARMV8_7A, "+v8.7a", (AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 | AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM)) -AARCH64_ARCH("armv8.8-a", ARMV8_8A, "v8.8a", +AARCH64_ARCH("armv8.8-a", ARMV8_8A, "+v8.8a", (AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 | AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM)) -AARCH64_ARCH("armv8.9-a", ARMV8_9A, "v8.9a", +AARCH64_ARCH("armv8.9-a", ARMV8_9A, "+v8.9a", (AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 | AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM)) -AARCH64_ARCH("armv9-a", ARMV9A, "v9a", +AARCH64_ARCH("armv9-a", ARMV9A, "+v9a", (AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | AArch64::AEK_SVE2)) -AARCH64_ARCH("armv9.1-a", ARMV9_1A, "v9.1a", +AARCH64_ARCH("armv9.1-a", ARMV9_1A, "+v9.1a", (AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2)) -AARCH64_ARCH("armv9.2-a", ARMV9_2A, "v9.2a", +AARCH64_ARCH("armv9.2-a", ARMV9_2A, "+v9.2a", (AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2)) -AARCH64_ARCH("armv9.3-a", ARMV9_3A, "v9.3a", +AARCH64_ARCH("armv9.3-a", ARMV9_3A, "+v9.3a", (AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2)) -AARCH64_ARCH("armv9.4-a", ARMV9_4A, "v9.4a", +AARCH64_ARCH("armv9.4-a", ARMV9_4A, "+v9.4a", (AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2)) // For v8-R, we do not enable crypto and align with GCC that enables a more // minimal set of optional architecture extensions. -AARCH64_ARCH("armv8-r", ARMV8R, "v8r", +AARCH64_ARCH("armv8-r", ARMV8R, "+v8r", (AArch64::AEK_CRC | AArch64::AEK_RDM | AArch64::AEK_SSBS | AArch64::AEK_DOTPROD | AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_FP16FML | AArch64::AEK_RAS | @@ -102,8 +102,8 @@ #define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) #endif // FIXME: This would be nicer were it tablegen -AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, nullptr, nullptr) -AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, nullptr, nullptr) +AARCH64_ARCH_EXT_NAME("invalid", AArch64::AEK_INVALID, {}, {}) +AARCH64_ARCH_EXT_NAME("none", AArch64::AEK_NONE, {}, {}) AARCH64_ARCH_EXT_NAME("crc", AArch64::AEK_CRC, "+crc", "-crc") AARCH64_ARCH_EXT_NAME("lse", AArch64::AEK_LSE, "+lse", "-lse") AARCH64_ARCH_EXT_NAME("rdm", AArch64::AEK_RDM, "+rdm", "-rdm") diff --git a/llvm/include/llvm/Support/ARMTargetParser.h b/llvm/include/llvm/Support/ARMTargetParser.h --- a/llvm/include/llvm/Support/ARMTargetParser.h +++ b/llvm/include/llvm/Support/ARMTargetParser.h @@ -69,40 +69,34 @@ }; // List of Arch Extension names. -// FIXME: TableGen this. struct ExtName { - const char *NameCStr; - size_t NameLength; + StringRef Name; uint64_t ID; - const char *Feature; - const char *NegFeature; - - StringRef getName() const { return StringRef(NameCStr, NameLength); } + StringRef Feature; + StringRef NegFeature; }; const ExtName ARCHExtNames[] = { #define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) \ - {NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE}, + {NAME, ID, FEATURE, NEGFEATURE}, #include "ARMTargetParser.def" }; // List of HWDiv names (use getHWDivSynonym) and which architectural // features they correspond to (use getHWDivFeatures). -// FIXME: TableGen this. const struct { - const char *NameCStr; - size_t NameLength; + StringRef Name; uint64_t ID; - - StringRef getName() const { return StringRef(NameCStr, NameLength); } } HWDivNames[] = { -#define ARM_HW_DIV_NAME(NAME, ID) {NAME, sizeof(NAME) - 1, ID}, +#define ARM_HW_DIV_NAME(NAME, ID) {NAME, ID}, #include "ARMTargetParser.def" }; // Arch names. enum class ArchKind { -#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID, +#define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU, \ + ARCH_BASE_EXT) \ + ID, #include "ARMTargetParser.def" }; @@ -110,20 +104,16 @@ // The same CPU can have multiple arches and can be default on multiple arches. // When finding the Arch for a CPU, first-found prevails. Sort them accordingly. // When this becomes table-generated, we'd probably need two tables. -// FIXME: TableGen this. struct CpuNames { - const char *NameCStr; - size_t NameLength; + StringRef Name; ArchKind ArchID; bool Default; // is $Name the default CPU for $ArchID ? uint64_t DefaultExtensions; - - StringRef getName() const { return StringRef(NameCStr, NameLength); } }; const CpuNames CPUNames[] = { #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ - {NAME, sizeof(NAME) - 1, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT}, + {NAME, ARM::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT}, #include "ARMTargetParser.def" }; @@ -164,23 +154,19 @@ // List of canonical FPU names (use getFPUSynonym) and which architectural // features they correspond to (use getFPUFeatures). -// FIXME: TableGen this. // The entries must appear in the order listed in ARM::FPUKind for correct // indexing struct FPUName { - const char *NameCStr; - size_t NameLength; + StringRef Name; FPUKind ID; FPUVersion FPUVer; NeonSupportLevel NeonSupport; FPURestriction Restriction; - - StringRef getName() const { return StringRef(NameCStr, NameLength); } }; static const FPUName FPUNames[] = { #define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) \ - {NAME, sizeof(NAME) - 1, KIND, VERSION, NEON_SUPPORT, RESTRICTION}, + {NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION}, #include "llvm/Support/ARMTargetParser.def" }; @@ -191,43 +177,24 @@ // FIXME: SubArch values were simplified to fit into the expectations // of the triples and are not conforming with their official names. // Check to see if the expectation should be changed. -// FIXME: TableGen this. struct ArchNames { - const char *NameCStr; - size_t NameLength; - const char *CPUAttrCStr; - size_t CPUAttrLength; - const char *SubArchCStr; - size_t SubArchLength; + StringRef Name; + StringRef CPUAttr; // CPU class in build attributes. + StringRef ArchFeature; unsigned DefaultFPU; uint64_t ArchBaseExtensions; ArchKind ID; ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes. - StringRef getName() const { return StringRef(NameCStr, NameLength); } - - // CPU class in build attributes. - StringRef getCPUAttr() const { return StringRef(CPUAttrCStr, CPUAttrLength); } - - // Sub-Arch name. - StringRef getSubArch() const { - return getArchFeature().substr(1, SubArchLength); - } - - // Arch Feature name. - StringRef getArchFeature() const { - return StringRef(SubArchCStr, SubArchLength); - } + // Return ArchFeature without the leading "+". + StringRef getSubArch() const { return ArchFeature.substr(1); } }; static const ArchNames ARMArchNames[] = { -#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, \ +#define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU, \ ARCH_BASE_EXT) \ - {NAME, sizeof(NAME) - 1, \ - CPU_ATTR, sizeof(CPU_ATTR) - 1, \ - "+" SUB_ARCH, sizeof(SUB_ARCH), \ - ARCH_FPU, ARCH_BASE_EXT, \ - ArchKind::ID, ARCH_ATTR}, + {NAME, CPU_ATTR, ARCH_FEATURE, ARCH_FPU, \ + ARCH_BASE_EXT, ArchKind::ID, ARCH_ATTR}, #include "llvm/Support/ARMTargetParser.def" }; diff --git a/llvm/include/llvm/Support/ARMTargetParser.def b/llvm/include/llvm/Support/ARMTargetParser.def --- a/llvm/include/llvm/Support/ARMTargetParser.def +++ b/llvm/include/llvm/Support/ARMTargetParser.def @@ -43,165 +43,164 @@ #undef ARM_FPU #ifndef ARM_ARCH -#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) +#define ARM_ARCH(NAME, ID, CPU_ATTR, ARCH_FEATURE, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) #endif -ARM_ARCH("invalid", INVALID, "", "", +ARM_ARCH("invalid", INVALID, "", "+", ARMBuildAttrs::CPUArch::Pre_v4, FK_NONE, ARM::AEK_NONE) -ARM_ARCH("armv4", ARMV4, "4", "v4", ARMBuildAttrs::CPUArch::v4, +ARM_ARCH("armv4", ARMV4, "4", "+v4", ARMBuildAttrs::CPUArch::v4, FK_NONE, ARM::AEK_NONE) -ARM_ARCH("armv4t", ARMV4T, "4T", "v4t", ARMBuildAttrs::CPUArch::v4T, +ARM_ARCH("armv4t", ARMV4T, "4T", "+v4t", ARMBuildAttrs::CPUArch::v4T, FK_NONE, ARM::AEK_NONE) -ARM_ARCH("armv5t", ARMV5T, "5T", "v5", ARMBuildAttrs::CPUArch::v5T, +ARM_ARCH("armv5t", ARMV5T, "5T", "+v5", ARMBuildAttrs::CPUArch::v5T, FK_NONE, ARM::AEK_NONE) -ARM_ARCH("armv5te", ARMV5TE, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE, +ARM_ARCH("armv5te", ARMV5TE, "5TE", "+v5e", ARMBuildAttrs::CPUArch::v5TE, FK_NONE, ARM::AEK_DSP) -ARM_ARCH("armv5tej", ARMV5TEJ, "5TEJ", "v5e", ARMBuildAttrs::CPUArch::v5TEJ, +ARM_ARCH("armv5tej", ARMV5TEJ, "5TEJ", "+v5e", ARMBuildAttrs::CPUArch::v5TEJ, FK_NONE, ARM::AEK_DSP) -ARM_ARCH("armv6", ARMV6, "6", "v6", ARMBuildAttrs::CPUArch::v6, +ARM_ARCH("armv6", ARMV6, "6", "+v6", ARMBuildAttrs::CPUArch::v6, FK_VFPV2, ARM::AEK_DSP) -ARM_ARCH("armv6k", ARMV6K, "6K", "v6k", ARMBuildAttrs::CPUArch::v6K, +ARM_ARCH("armv6k", ARMV6K, "6K", "+v6k", ARMBuildAttrs::CPUArch::v6K, FK_VFPV2, ARM::AEK_DSP) -ARM_ARCH("armv6t2", ARMV6T2, "6T2", "v6t2", ARMBuildAttrs::CPUArch::v6T2, +ARM_ARCH("armv6t2", ARMV6T2, "6T2", "+v6t2", ARMBuildAttrs::CPUArch::v6T2, FK_NONE, ARM::AEK_DSP) -ARM_ARCH("armv6kz", ARMV6KZ, "6KZ", "v6kz", ARMBuildAttrs::CPUArch::v6KZ, +ARM_ARCH("armv6kz", ARMV6KZ, "6KZ", "+v6kz", ARMBuildAttrs::CPUArch::v6KZ, FK_VFPV2, (ARM::AEK_SEC | ARM::AEK_DSP)) -ARM_ARCH("armv6-m", ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M, +ARM_ARCH("armv6-m", ARMV6M, "6-M", "+v6m", ARMBuildAttrs::CPUArch::v6_M, FK_NONE, ARM::AEK_NONE) -ARM_ARCH("armv7-a", ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7, +ARM_ARCH("armv7-a", ARMV7A, "7-A", "+v7", ARMBuildAttrs::CPUArch::v7, FK_NEON, ARM::AEK_DSP) -ARM_ARCH("armv7ve", ARMV7VE, "7VE", "v7ve", ARMBuildAttrs::CPUArch::v7, +ARM_ARCH("armv7ve", ARMV7VE, "7VE", "+v7ve", ARMBuildAttrs::CPUArch::v7, FK_NEON, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP)) -ARM_ARCH("armv7-r", ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7, +ARM_ARCH("armv7-r", ARMV7R, "7-R", "+v7r", ARMBuildAttrs::CPUArch::v7, FK_NONE, (ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP)) -ARM_ARCH("armv7-m", ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7, +ARM_ARCH("armv7-m", ARMV7M, "7-M", "+v7m", ARMBuildAttrs::CPUArch::v7, FK_NONE, ARM::AEK_HWDIVTHUMB) -ARM_ARCH("armv7e-m", ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M, +ARM_ARCH("armv7e-m", ARMV7EM, "7E-M", "+v7em", ARMBuildAttrs::CPUArch::v7E_M, FK_NONE, (ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP)) -ARM_ARCH("armv8-a", ARMV8A, "8-A", "v8a", ARMBuildAttrs::CPUArch::v8_A, +ARM_ARCH("armv8-a", ARMV8A, "8-A", "+v8a", ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC)) -ARM_ARCH("armv8.1-a", ARMV8_1A, "8.1-A", "v8.1a", +ARM_ARCH("armv8.1-a", ARMV8_1A, "8.1-A", "+v8.1a", ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC)) -ARM_ARCH("armv8.2-a", ARMV8_2A, "8.2-A", "v8.2a", +ARM_ARCH("armv8.2-a", ARMV8_2A, "8.2-A", "+v8.2a", ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS)) -ARM_ARCH("armv8.3-a", ARMV8_3A, "8.3-A", "v8.3a", +ARM_ARCH("armv8.3-a", ARMV8_3A, "8.3-A", "+v8.3a", ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS)) -ARM_ARCH("armv8.4-a", ARMV8_4A, "8.4-A", "v8.4a", +ARM_ARCH("armv8.4-a", ARMV8_4A, "8.4-A", "+v8.4a", ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD)) -ARM_ARCH("armv8.5-a", ARMV8_5A, "8.5-A", "v8.5a", +ARM_ARCH("armv8.5-a", ARMV8_5A, "8.5-A", "+v8.5a", ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD)) -ARM_ARCH("armv8.6-a", ARMV8_6A, "8.6-A", "v8.6a", +ARM_ARCH("armv8.6-a", ARMV8_6A, "8.6-A", "+v8.6a", ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM)) -ARM_ARCH("armv8.7-a", ARMV8_7A, "8.7-A", "v8.7a", +ARM_ARCH("armv8.7-a", ARMV8_7A, "8.7-A", "+v8.7a", ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM)) -ARM_ARCH("armv8.8-a", ARMV8_8A, "8.8-A", "v8.8a", +ARM_ARCH("armv8.8-a", ARMV8_8A, "8.8-A", "+v8.8a", ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_SHA2 | ARM::AEK_AES | ARM::AEK_I8MM)) -ARM_ARCH("armv8.9-a", ARMV8_9A, "8.9-A", "v8.9a", +ARM_ARCH("armv8.9-a", ARMV8_9A, "8.9-A", "+v8.9a", ARMBuildAttrs::CPUArch::v8_A, FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_SHA2 | ARM::AEK_AES | ARM::AEK_I8MM)) -ARM_ARCH("armv9-a", ARMV9A, "9-A", "v9a", +ARM_ARCH("armv9-a", ARMV9A, "9-A", "+v9a", ARMBuildAttrs::CPUArch::v9_A, FK_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD)) -ARM_ARCH("armv9.1-a", ARMV9_1A, "9.1-A", "v9.1a", +ARM_ARCH("armv9.1-a", ARMV9_1A, "9.1-A", "+v9.1a", ARMBuildAttrs::CPUArch::v9_A, FK_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM)) -ARM_ARCH("armv9.2-a", ARMV9_2A, "9.2-A", "v9.2a", +ARM_ARCH("armv9.2-a", ARMV9_2A, "9.2-A", "+v9.2a", ARMBuildAttrs::CPUArch::v9_A, FK_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM)) -ARM_ARCH("armv9.3-a", ARMV9_3A, "9.3-A", "v9.3a", +ARM_ARCH("armv9.3-a", ARMV9_3A, "9.3-A", "+v9.3a", ARMBuildAttrs::CPUArch::v9_A, FK_CRYPTO_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM)) -ARM_ARCH("armv9.4-a", ARMV9_4A, "9.4-A", "v9.4a", +ARM_ARCH("armv9.4-a", ARMV9_4A, "9.4-A", "+v9.4a", ARMBuildAttrs::CPUArch::v9_A, FK_NEON_FP_ARMV8, (ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS | ARM::AEK_DOTPROD | ARM::AEK_BF16 | ARM::AEK_I8MM)) -ARM_ARCH("armv8-r", ARMV8R, "8-R", "v8r", ARMBuildAttrs::CPUArch::v8_R, +ARM_ARCH("armv8-r", ARMV8R, "8-R", "+v8r", ARMBuildAttrs::CPUArch::v8_R, FK_NEON_FP_ARMV8, (ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC)) -ARM_ARCH("armv8-m.base", ARMV8MBaseline, "8-M.Baseline", "v8m.base", +ARM_ARCH("armv8-m.base", ARMV8MBaseline, "8-M.Baseline", "+v8m.base", ARMBuildAttrs::CPUArch::v8_M_Base, FK_NONE, ARM::AEK_HWDIVTHUMB) -ARM_ARCH("armv8-m.main", ARMV8MMainline, "8-M.Mainline", "v8m.main", +ARM_ARCH("armv8-m.main", ARMV8MMainline, "8-M.Mainline", "+v8m.main", ARMBuildAttrs::CPUArch::v8_M_Main, FK_FPV5_D16, ARM::AEK_HWDIVTHUMB) -ARM_ARCH("armv8.1-m.main", ARMV8_1MMainline, "8.1-M.Mainline", "v8.1m.main", +ARM_ARCH("armv8.1-m.main", ARMV8_1MMainline, "8.1-M.Mainline", "+v8.1m.main", ARMBuildAttrs::CPUArch::v8_1_M_Main, FK_FP_ARMV8_FULLFP16_SP_D16, ARM::AEK_HWDIVTHUMB | ARM::AEK_RAS | ARM::AEK_LOB) // Non-standard Arch names. -ARM_ARCH("iwmmxt", IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE, +ARM_ARCH("iwmmxt", IWMMXT, "iwmmxt", "+", ARMBuildAttrs::CPUArch::v5TE, FK_NONE, ARM::AEK_NONE) -ARM_ARCH("iwmmxt2", IWMMXT2, "iwmmxt2", "", ARMBuildAttrs::CPUArch::v5TE, +ARM_ARCH("iwmmxt2", IWMMXT2, "iwmmxt2", "+", ARMBuildAttrs::CPUArch::v5TE, FK_NONE, ARM::AEK_NONE) -ARM_ARCH("xscale", XSCALE, "xscale", "v5e", ARMBuildAttrs::CPUArch::v5TE, +ARM_ARCH("xscale", XSCALE, "xscale", "+v5e", ARMBuildAttrs::CPUArch::v5TE, FK_NONE, ARM::AEK_NONE) -ARM_ARCH("armv7s", ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7, +ARM_ARCH("armv7s", ARMV7S, "7-S", "+v7s", ARMBuildAttrs::CPUArch::v7, FK_NEON_VFPV4, ARM::AEK_DSP) -ARM_ARCH("armv7k", ARMV7K, "7-K", "v7k", ARMBuildAttrs::CPUArch::v7, +ARM_ARCH("armv7k", ARMV7K, "7-K", "+v7k", ARMBuildAttrs::CPUArch::v7, FK_NONE, ARM::AEK_DSP) #undef ARM_ARCH #ifndef ARM_ARCH_EXT_NAME #define ARM_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) #endif -// FIXME: This would be nicer were it tablegen -ARM_ARCH_EXT_NAME("invalid", ARM::AEK_INVALID, nullptr, nullptr) -ARM_ARCH_EXT_NAME("none", ARM::AEK_NONE, nullptr, nullptr) +ARM_ARCH_EXT_NAME("invalid", ARM::AEK_INVALID, {}, {}) +ARM_ARCH_EXT_NAME("none", ARM::AEK_NONE, {}, {}) ARM_ARCH_EXT_NAME("crc", ARM::AEK_CRC, "+crc", "-crc") ARM_ARCH_EXT_NAME("crypto", ARM::AEK_CRYPTO, "+crypto","-crypto") ARM_ARCH_EXT_NAME("sha2", ARM::AEK_SHA2, "+sha2", "-sha2") ARM_ARCH_EXT_NAME("aes", ARM::AEK_AES, "+aes", "-aes") ARM_ARCH_EXT_NAME("dotprod", ARM::AEK_DOTPROD, "+dotprod","-dotprod") ARM_ARCH_EXT_NAME("dsp", ARM::AEK_DSP, "+dsp", "-dsp") -ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, nullptr, nullptr) -ARM_ARCH_EXT_NAME("fp.dp", ARM::AEK_FP_DP, nullptr, nullptr) +ARM_ARCH_EXT_NAME("fp", ARM::AEK_FP, {}, {}) +ARM_ARCH_EXT_NAME("fp.dp", ARM::AEK_FP_DP, {}, {}) ARM_ARCH_EXT_NAME("mve", (ARM::AEK_DSP | ARM::AEK_SIMD), "+mve", "-mve") ARM_ARCH_EXT_NAME("mve.fp", (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP), "+mve.fp", "-mve.fp") -ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), nullptr, nullptr) -ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, nullptr, nullptr) -ARM_ARCH_EXT_NAME("simd", ARM::AEK_SIMD, nullptr, nullptr) -ARM_ARCH_EXT_NAME("sec", ARM::AEK_SEC, nullptr, nullptr) -ARM_ARCH_EXT_NAME("virt", ARM::AEK_VIRT, nullptr, nullptr) +ARM_ARCH_EXT_NAME("idiv", (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB), {}, {}) +ARM_ARCH_EXT_NAME("mp", ARM::AEK_MP, {}, {}) +ARM_ARCH_EXT_NAME("simd", ARM::AEK_SIMD, {}, {}) +ARM_ARCH_EXT_NAME("sec", ARM::AEK_SEC, {}, {}) +ARM_ARCH_EXT_NAME("virt", ARM::AEK_VIRT, {}, {}) ARM_ARCH_EXT_NAME("fp16", ARM::AEK_FP16, "+fullfp16", "-fullfp16") ARM_ARCH_EXT_NAME("ras", ARM::AEK_RAS, "+ras", "-ras") -ARM_ARCH_EXT_NAME("os", ARM::AEK_OS, nullptr, nullptr) -ARM_ARCH_EXT_NAME("iwmmxt", ARM::AEK_IWMMXT, nullptr, nullptr) -ARM_ARCH_EXT_NAME("iwmmxt2", ARM::AEK_IWMMXT2, nullptr, nullptr) -ARM_ARCH_EXT_NAME("maverick", ARM::AEK_MAVERICK, nullptr, nullptr) -ARM_ARCH_EXT_NAME("xscale", ARM::AEK_XSCALE, nullptr, nullptr) +ARM_ARCH_EXT_NAME("os", ARM::AEK_OS, {}, {}) +ARM_ARCH_EXT_NAME("iwmmxt", ARM::AEK_IWMMXT, {}, {}) +ARM_ARCH_EXT_NAME("iwmmxt2", ARM::AEK_IWMMXT2, {}, {}) +ARM_ARCH_EXT_NAME("maverick", ARM::AEK_MAVERICK, {}, {}) +ARM_ARCH_EXT_NAME("xscale", ARM::AEK_XSCALE, {}, {}) ARM_ARCH_EXT_NAME("fp16fml", ARM::AEK_FP16FML, "+fp16fml", "-fp16fml") ARM_ARCH_EXT_NAME("bf16", ARM::AEK_BF16, "+bf16", "-bf16") ARM_ARCH_EXT_NAME("sb", ARM::AEK_SB, "+sb", "-sb") diff --git a/llvm/lib/Support/AArch64TargetParser.cpp b/llvm/lib/Support/AArch64TargetParser.cpp --- a/llvm/lib/Support/AArch64TargetParser.cpp +++ b/llvm/lib/Support/AArch64TargetParser.cpp @@ -50,11 +50,10 @@ } AArch64::ArchKind AArch64::getSubArchArchKind(StringRef SubArch) { - return StringSwitch(SubArch) -#define AARCH64_ARCH(NAME, ID, SUB_ARCH, ARCH_BASE_EXT) \ - .Case(SUB_ARCH, ArchKind::ID) -#include "../../include/llvm/Support/AArch64TargetParser.def" - .Default(ArchKind::INVALID); + for (const auto &A : AArch64ARCHNames) + if (A.getSubArch() == SubArch) + return A.ID; + return ArchKind::INVALID; } bool AArch64::getExtensionFeatures(uint64_t Extensions, @@ -86,13 +85,12 @@ std::vector &Features) { if (AK == ArchKind::INVALID) return false; - Features.push_back( - AArch64ARCHNames[static_cast(AK)].getArchFeature()); + Features.push_back(AArch64ARCHNames[static_cast(AK)].ArchFeature); return true; } StringRef AArch64::getArchName(AArch64::ArchKind AK) { - return AArch64ARCHNames[static_cast(AK)].getName(); + return AArch64ARCHNames[static_cast(AK)].Name; } StringRef AArch64::getSubArch(AArch64::ArchKind AK) { @@ -103,14 +101,14 @@ if (ArchExt.startswith("no")) { StringRef ArchExtBase(ArchExt.substr(2)); for (const auto &AE : AArch64ARCHExtNames) { - if (AE.NegFeature && ArchExtBase == AE.getName()) - return StringRef(AE.NegFeature); + if (!AE.NegFeature.empty() && ArchExtBase == AE.Name) + return AE.NegFeature; } } for (const auto &AE : AArch64ARCHExtNames) - if (AE.Feature && ArchExt == AE.getName()) - return StringRef(AE.Feature); + if (!AE.Feature.empty() && ArchExt == AE.Name) + return AE.Feature; return StringRef(); } @@ -130,11 +128,11 @@ void AArch64::fillValidCPUArchList(SmallVectorImpl &Values) { for (const auto &Arch : AArch64CPUNames) { if (Arch.ArchID != ArchKind::INVALID) - Values.push_back(Arch.getName()); + Values.push_back(Arch.Name); } for (const auto &Alias: AArch64CPUAliases) - Values.push_back(Alias.getAlias()); + Values.push_back(Alias.Alias); } bool AArch64::isX18ReservedByDefault(const Triple &TT) { @@ -150,7 +148,7 @@ StringRef Syn = llvm::ARM::getArchSynonym(Arch); for (const auto &A : AArch64ARCHNames) { - if (A.getName().endswith(Syn)) + if (A.Name.endswith(Syn)) return A.ID; } return ArchKind::INVALID; @@ -158,7 +156,7 @@ AArch64::ArchExtKind AArch64::parseArchExt(StringRef ArchExt) { for (const auto &A : AArch64ARCHExtNames) { - if (ArchExt == A.getName()) + if (ArchExt == A.Name) return static_cast(A.ID); } return AArch64::AEK_INVALID; @@ -167,14 +165,14 @@ AArch64::ArchKind AArch64::parseCPUArch(StringRef CPU) { // Resolve aliases first. for (const auto &Alias : AArch64CPUAliases) { - if (CPU == Alias.getAlias()) { - CPU = Alias.getName(); + if (CPU == Alias.Alias) { + CPU = Alias.Name; break; } } // Then find the CPU name. for (const auto &C : AArch64CPUNames) - if (CPU == C.getName()) + if (CPU == C.Name) return C.ArchID; return ArchKind::INVALID; diff --git a/llvm/lib/Support/ARMTargetParser.cpp b/llvm/lib/Support/ARMTargetParser.cpp --- a/llvm/lib/Support/ARMTargetParser.cpp +++ b/llvm/lib/Support/ARMTargetParser.cpp @@ -30,7 +30,7 @@ Arch = getCanonicalArchName(Arch); StringRef Syn = getArchSynonym(Arch); for (const auto &A : ARMArchNames) { - if (A.getName().endswith(Syn)) + if (A.Name.endswith(Syn)) return A.ID; } return ArchKind::INVALID; @@ -214,7 +214,7 @@ unsigned ARM::parseFPU(StringRef FPU) { StringRef Syn = getFPUSynonym(FPU); for (const auto &F : FPUNames) { - if (Syn == F.getName()) + if (Syn == F.Name) return F.ID; } return FK_INVALID; @@ -246,7 +246,7 @@ StringRef ARM::getFPUName(unsigned FPUKind) { if (FPUKind >= FK_LAST) return StringRef(); - return FPUNames[FPUKind].getName(); + return FPUNames[FPUKind].Name; } ARM::FPUVersion ARM::getFPUVersion(unsigned FPUKind) { @@ -311,9 +311,9 @@ return false; for (const auto &AE : ARCHExtNames) { - if ((Extensions & AE.ID) == AE.ID && AE.Feature) + if ((Extensions & AE.ID) == AE.ID && !AE.Feature.empty()) Features.push_back(AE.Feature); - else if (AE.NegFeature) + else if (!AE.NegFeature.empty()) Features.push_back(AE.NegFeature); } @@ -321,11 +321,11 @@ } StringRef ARM::getArchName(ARM::ArchKind AK) { - return ARMArchNames[static_cast(AK)].getName(); + return ARMArchNames[static_cast(AK)].Name; } StringRef ARM::getCPUAttr(ARM::ArchKind AK) { - return ARMArchNames[static_cast(AK)].getCPUAttr(); + return ARMArchNames[static_cast(AK)].CPUAttr; } StringRef ARM::getSubArch(ARM::ArchKind AK) { @@ -339,7 +339,7 @@ StringRef ARM::getArchExtName(uint64_t ArchExtKind) { for (const auto &AE : ARCHExtNames) { if (ArchExtKind == AE.ID) - return AE.getName(); + return AE.Name; } return StringRef(); } @@ -355,7 +355,7 @@ StringRef ARM::getArchExtFeature(StringRef ArchExt) { bool Negated = stripNegationPrefix(ArchExt); for (const auto &AE : ARCHExtNames) { - if (AE.Feature && ArchExt == AE.getName()) + if (!AE.Feature.empty() && ArchExt == AE.Name) return StringRef(Negated ? AE.NegFeature : AE.Feature); } @@ -405,10 +405,10 @@ for (const auto &AE : ARCHExtNames) { if (Negated) { - if ((AE.ID & ID) == ID && AE.NegFeature) + if ((AE.ID & ID) == ID && !AE.NegFeature.empty()) Features.push_back(AE.NegFeature); } else { - if ((AE.ID & ID) == AE.ID && AE.Feature) + if ((AE.ID & ID) == AE.ID && !AE.Feature.empty()) Features.push_back(AE.Feature); } } @@ -454,7 +454,7 @@ // Look for multiple AKs to find the default for pair AK+Name. for (const auto &CPU : CPUNames) { if (CPU.ArchID == AK && CPU.Default) - return CPU.getName(); + return CPU.Name; } // If we can't find a default then target the architecture instead @@ -464,7 +464,7 @@ uint64_t ARM::parseHWDiv(StringRef HWDiv) { StringRef Syn = getHWDivSynonym(HWDiv); for (const auto &D : HWDivNames) { - if (Syn == D.getName()) + if (Syn == D.Name) return D.ID; } return AEK_INVALID; @@ -472,7 +472,7 @@ uint64_t ARM::parseArchExt(StringRef ArchExt) { for (const auto &A : ARCHExtNames) { - if (ArchExt == A.getName()) + if (ArchExt == A.Name) return A.ID; } return AEK_INVALID; @@ -480,7 +480,7 @@ ARM::ArchKind ARM::parseCPUArch(StringRef CPU) { for (const auto &C : CPUNames) { - if (CPU == C.getName()) + if (CPU == C.Name) return C.ArchID; } return ArchKind::INVALID; @@ -489,7 +489,7 @@ void ARM::fillValidCPUArchList(SmallVectorImpl &Values) { for (const auto &Arch : CPUNames) { if (Arch.ArchID != ArchKind::INVALID) - Values.push_back(Arch.getName()); + Values.push_back(Arch.Name); } } diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp --- a/llvm/unittests/Support/TargetParserTest.cpp +++ b/llvm/unittests/Support/TargetParserTest.cpp @@ -683,9 +683,8 @@ std::map> Extensions; for (auto &Ext : ARM::ARCHExtNames) { - if (Ext.Feature && Ext.NegFeature) - Extensions[Ext.ID] = { StringRef(Ext.Feature), - StringRef(Ext.NegFeature) }; + if (!Ext.Feature.empty() && !Ext.NegFeature.empty()) + Extensions[Ext.ID] = {Ext.Feature, Ext.NegFeature}; } Extensions[ARM::AEK_HWDIVARM] = { "+hwdiv-arm", "-hwdiv-arm" };