diff --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp @@ -398,6 +398,16 @@ SQ.getWithInstruction(&EI))) return replaceInstUsesWith(EI, V); + // We don't want to produce a select , c1, c2 + // instruction when constant folding a extractelt + // into a select: + // extractelt (select %c, , ), %const -> + // select %c, [%const], [%const] + if (SelectInst *SI = dyn_cast(EI.getVectorOperand())) + if (SI->getCondition()->getType()->isIntegerTy()) + if (Instruction *R = FoldOpIntoSelect(EI, SI)) + return R; + // If extracting a specified index from the vector, see if we can recursively // find a previously computed scalar that was inserted into the vector. auto *IndexC = dyn_cast(Index); @@ -587,6 +597,7 @@ } } } + return nullptr; } diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -1068,6 +1068,9 @@ return Builder.CreateBinaryIntrinsic(IID, SO, II->getArgOperand(1)); } + if (auto *EI = dyn_cast(&I)) + return Builder.CreateExtractElement(SO, EI->getIndexOperand()); + assert(I.isBinaryOp() && "Unexpected opcode for select folding"); // Figure out if the constant is the left or the right argument. @@ -1154,6 +1157,14 @@ } } + // FIXME: Support multiple select operands during constant folding: + // extractelt (select %c, %, %), (select %c, %c1, %c2) + // This is currently not possible because constant folding will reach + // an unreachable assertion if it doesn't find a constant operand. + if (auto *EI = dyn_cast(&Op)) + if (auto *C = dyn_cast(EI->getIndexOperand()); !C) + return nullptr; + // Make sure that one of the select arms constant folds successfully. Value *NewTV = constantFoldOperationIntoSelectOperand(Op, SI, TV); Value *NewFV = constantFoldOperationIntoSelectOperand(Op, SI, FV); @@ -1165,6 +1176,7 @@ NewTV = foldOperationIntoSelectOperand(Op, TV, Builder); if (!NewFV) NewFV = foldOperationIntoSelectOperand(Op, FV, Builder); + return SelectInst::Create(SI->getCondition(), NewTV, NewFV, "", nullptr, SI); } diff --git a/llvm/test/Transforms/InstCombine/extractelement.ll b/llvm/test/Transforms/InstCombine/extractelement.ll --- a/llvm/test/Transforms/InstCombine/extractelement.ll +++ b/llvm/test/Transforms/InstCombine/extractelement.ll @@ -785,8 +785,7 @@ define i32 @extelt_select_const_operand_vector(i1 %c) { ; ANY-LABEL: @extelt_select_const_operand_vector( -; ANY-NEXT: [[S:%.*]] = select i1 [[C:%.*]], <3 x i32> , <3 x i32> -; ANY-NEXT: [[R:%.*]] = extractelement <3 x i32> [[S]], i64 2 +; ANY-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i32 4, i32 7 ; ANY-NEXT: ret i32 [[R]] ; %s = select i1 %c, <3 x i32> , <3 x i32> @@ -794,13 +793,33 @@ ret i32 %r } +define float @extelt_select_const_operand_vector_float(i1 %c) { +; ANY-LABEL: @extelt_select_const_operand_vector_float( +; ANY-NEXT: [[R:%.*]] = select i1 [[C:%.*]], float 4.000000e+00, float 7.000000e+00 +; ANY-NEXT: ret float [[R]] +; + %s = select i1 %c, <3 x float> , <3 x float> + %r = extractelement <3 x float> %s, i32 2 + ret float %r +} + +define i32 @extelt_vecselect_const_operand_vector(<3 x i1> %c) { +; ANY-LABEL: @extelt_vecselect_const_operand_vector( +; ANY-NEXT: [[S:%.*]] = select <3 x i1> [[C:%.*]], <3 x i32> , <3 x i32> +; ANY-NEXT: [[R:%.*]] = extractelement <3 x i32> [[S]], i64 2 +; ANY-NEXT: ret i32 [[R]] +; + %s = select <3 x i1> %c, <3 x i32> , <3 x i32> + %r = extractelement <3 x i32> %s, i32 2 + ret i32 %r +} + define i32 @extelt_select_const_operand_extractelt_use(i1 %c) { ; ANY-LABEL: @extelt_select_const_operand_extractelt_use( -; ANY-NEXT: [[S:%.*]] = select i1 [[C:%.*]], <3 x i32> , <3 x i32> -; ANY-NEXT: [[E:%.*]] = extractelement <3 x i32> [[S]], i64 2 -; ANY-NEXT: [[M:%.*]] = shl i32 [[E]], 1 -; ANY-NEXT: [[M_2:%.*]] = shl i32 [[E]], 2 -; ANY-NEXT: [[R:%.*]] = mul i32 [[M]], [[M_2]] +; ANY-NEXT: [[E:%.*]] = select i1 [[C:%.*]], i32 4, i32 7 +; ANY-NEXT: [[M:%.*]] = shl nuw nsw i32 [[E]], 1 +; ANY-NEXT: [[M_2:%.*]] = shl nuw nsw i32 [[E]], 2 +; ANY-NEXT: [[R:%.*]] = mul nuw nsw i32 [[M]], [[M_2]] ; ANY-NEXT: ret i32 [[R]] ; %s = select i1 %c, <3 x i32> , <3 x i32> @@ -825,3 +844,77 @@ %r = mul i32 %e, %e.2 ret i32 %r } + +define i32 @extelt_select_const_operand_vector_cond_index(i1 %c) { +; ANY-LABEL: @extelt_select_const_operand_vector_cond_index( +; ANY-NEXT: [[E:%.*]] = select i1 [[C:%.*]], i32 3, i32 4 +; ANY-NEXT: [[S:%.*]] = select i1 [[C]], <3 x i32> , <3 x i32> +; ANY-NEXT: [[R:%.*]] = extractelement <3 x i32> [[S]], i32 [[E]] +; ANY-NEXT: ret i32 [[R]] +; + %e = select i1 %c, i32 3, i32 4 + %s = select i1 %c, <3 x i32> , <3 x i32> + %r = extractelement <3 x i32> %s, i32 %e + ret i32 %r +} + +define i32 @extelt_select_const_operand_vector_var_index(i1 %c, i32 %e) { +; ANY-LABEL: @extelt_select_const_operand_vector_var_index( +; ANY-NEXT: [[S:%.*]] = select i1 [[C:%.*]], <3 x i32> , <3 x i32> +; ANY-NEXT: [[R:%.*]] = extractelement <3 x i32> [[S]], i32 [[E:%.*]] +; ANY-NEXT: ret i32 [[R]] +; + %s = select i1 %c, <3 x i32> , <3 x i32> + %r = extractelement <3 x i32> %s, i32 %e + ret i32 %r +} + +define i32 @extelt_select_var_const_operand_vector(i1 %c, <3 x i32> %v) { +; ANY-LABEL: @extelt_select_var_const_operand_vector( +; ANY-NEXT: [[TMP1:%.*]] = extractelement <3 x i32> [[V:%.*]], i64 1 +; ANY-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i32 [[TMP1]], i32 6 +; ANY-NEXT: ret i32 [[R]] +; + %s = select i1 %c, <3 x i32> %v, <3 x i32> + %r = extractelement <3 x i32> %s, i32 1 + ret i32 %r +} + +define i32 @extelt_select_const_var_operand_vector(i1 %c, <3 x i32> %v) { +; ANY-LABEL: @extelt_select_const_var_operand_vector( +; ANY-NEXT: [[TMP1:%.*]] = extractelement <3 x i32> [[V:%.*]], i64 0 +; ANY-NEXT: [[R:%.*]] = select i1 [[C:%.*]], i32 5, i32 [[TMP1]] +; ANY-NEXT: ret i32 [[R]] +; + %s = select i1 %c, <3 x i32> , <3 x i32> %v + %r = extractelement <3 x i32> %s, i32 0 + ret i32 %r +} + +declare void @use_select(<3 x i32>) + +define i32 @extelt_select_const_var_operands_vector_extra_use(i1 %c, <3 x i32> %x) { +; ANY-LABEL: @extelt_select_const_var_operands_vector_extra_use( +; ANY-NEXT: [[S:%.*]] = select i1 [[C:%.*]], <3 x i32> , <3 x i32> [[X:%.*]] +; ANY-NEXT: call void @use_select(<3 x i32> [[S]]) +; ANY-NEXT: [[R:%.*]] = extractelement <3 x i32> [[S]], i64 0 +; ANY-NEXT: ret i32 [[R]] +; + %s = select i1 %c, <3 x i32> , <3 x i32> %x + call void @use_select(<3 x i32> %s) + %r = extractelement <3 x i32> %s, i64 0 + ret i32 %r +} + +define i32 @extelt_select_const_operands_vector_extra_use_2(i1 %c) { +; ANY-LABEL: @extelt_select_const_operands_vector_extra_use_2( +; ANY-NEXT: [[S:%.*]] = select i1 [[C:%.*]], <3 x i32> , <3 x i32> +; ANY-NEXT: call void @use_select(<3 x i32> [[S]]) +; ANY-NEXT: [[R:%.*]] = extractelement <3 x i32> [[S]], i64 0 +; ANY-NEXT: ret i32 [[R]] +; + %s = select i1 %c, <3 x i32> , <3 x i32> + call void @use_select(<3 x i32> %s) + %r = extractelement <3 x i32> %s, i64 0 + ret i32 %r +} diff --git a/llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll b/llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll --- a/llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll @@ -8,11 +8,8 @@ ; extracting the second element in the vector). define i16 @test_srem_orig(i16 %a, i1 %cmp) { ; CHECK-LABEL: @test_srem_orig( -; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[A:%.*]], i64 0 -; CHECK-NEXT: [[TMP1:%.*]] = srem <2 x i16> [[SPLATINSERT]], -; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> poison, <2 x i32> -; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> , <2 x i16> [[SPLAT_OP]] -; CHECK-NEXT: [[T3:%.*]] = extractelement <2 x i16> [[T2]], i64 1 +; CHECK-NEXT: [[TMP1:%.*]] = srem i16 [[A:%.*]], 2 +; CHECK-NEXT: [[T3:%.*]] = select i1 [[CMP:%.*]], i16 1, i16 [[TMP1]] ; CHECK-NEXT: ret i16 [[T3]] ; %splatinsert = insertelement <2 x i16> poison, i16 %a, i32 0 diff --git a/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll b/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll --- a/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll +++ b/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll @@ -8,11 +8,8 @@ ; extracting the second element in the vector). define i16 @test_srem_orig(i16 %a, i1 %cmp) { ; CHECK-LABEL: @test_srem_orig( -; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> undef, i16 [[A:%.*]], i64 0 -; CHECK-NEXT: [[TMP1:%.*]] = srem <2 x i16> [[SPLATINSERT]], -; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> poison, <2 x i32> -; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> , <2 x i16> [[SPLAT_OP]] -; CHECK-NEXT: [[T3:%.*]] = extractelement <2 x i16> [[T2]], i64 1 +; CHECK-NEXT: [[TMP1:%.*]] = srem i16 [[A:%.*]], 2 +; CHECK-NEXT: [[T3:%.*]] = select i1 [[CMP:%.*]], i16 1, i16 [[TMP1]] ; CHECK-NEXT: ret i16 [[T3]] ; %splatinsert = insertelement <2 x i16> undef, i16 %a, i32 0