Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -12706,7 +12706,7 @@
 }
 
 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
-// is legal, or has an f16 source (which needs to be promoted to f32),
+// is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
 // just return an <SDValue(), SDValue()> pair.
 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
 // to i16, i32 or i64, and we lower it to a legal sequence.
@@ -12723,15 +12723,11 @@
   EVT TheVT = Op.getOperand(0).getValueType();
   auto PtrVT = getPointerTy(DAG.getDataLayout());
 
-  if (TheVT == MVT::f16)
-    // We need to promote the f16 to f32 before using the lowering
-    // in this routine.
+  if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
+    // f16 must be promoted before using the lowering in this routine.
+    // fp128 does not use this lowering.
     return std::make_pair(SDValue(), SDValue());
-
-  assert((TheVT == MVT::f32 ||
-          TheVT == MVT::f64 ||
-          TheVT == MVT::f80) &&
-         "Unexpected FP operand type in FP_TO_INTHelper");
+  }
 
   // If using FIST to compute an unsigned i64, we'll need some fixup
   // to handle values above the maximum signed i64.  A FIST is always
Index: test/CodeGen/X86/scalar-fp-to-i64.ll
===================================================================
--- test/CodeGen/X86/scalar-fp-to-i64.ll
+++ test/CodeGen/X86/scalar-fp-to-i64.ll
@@ -133,3 +133,19 @@
   %r = fptosi x86_fp80 %a to i64
   ret i64 %r
 }
+
+; CHECK-LABEL: t_to_u64
+; CHECK: __fixunstfdi
+; CHECK: ret
+define i64 @t_to_u64(fp128 %a) nounwind {
+  %r = fptoui fp128 %a to i64
+  ret i64 %r
+}
+
+; CHECK-LABEL: t_to_s64
+; CHECK: __fixtfdi
+; CHECK: ret
+define i64 @t_to_s64(fp128 %a) nounwind {
+  %r = fptosi fp128 %a to i64
+  ret i64 %r
+}