diff --git a/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber-vrm4.mir b/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber-vrm4.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber-vrm4.mir @@ -0,0 +1,128 @@ +# RUN: llc %s -mtriple=riscv64 -mattr=+v -riscv-enable-subreg-liveness -run-pass=livestacks -o - | FileCheck %s + +--- | + ; ModuleID = 'test6.ll' + source_filename = "test6.c" + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" + target triple = "riscv64" + + ; Function Attrs: nounwind memory(write) vscale_range(2,1024) + define dso_local signext i32 @main() local_unnamed_addr #0 { + entry: + %dst = alloca [100 x float], align 8 + call void @llvm.lifetime.start.p0(i64 400, ptr nonnull %dst) #4 + %0 = tail call @llvm.riscv.vrgather.vx.nxv8f32.i64( undef, undef, i64 0, i64 0) + call void @llvm.riscv.vse.nxv8f32.i64( %0, ptr nonnull %dst, i64 0) + call void @llvm.lifetime.end.p0(i64 400, ptr nonnull %dst) #4 + ret i32 0 + } + + ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) + declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 + + ; Function Attrs: nounwind memory(none) + declare @llvm.riscv.vrgather.vx.nxv8f32.i64(, , i64, i64) #2 + + ; Function Attrs: nounwind memory(write) + declare void @llvm.riscv.vse.nxv8f32.i64(, ptr nocapture, i64) #3 + + ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) + declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 + + attributes #0 = { nounwind memory(write) vscale_range(2,1024) "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+v,-save-restore,+v" } + attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) "target-features"="+v" } + attributes #2 = { nounwind memory(none) "target-features"="+v" } + attributes #3 = { nounwind memory(write) "target-features"="+v" } + attributes #4 = { nounwind } + + !llvm.module.flags = !{!0, !1, !2} + !llvm.ident = !{!3} + + !0 = !{i32 1, !"wchar_size", i32 4} + !1 = !{i32 1, !"target-abi", !"lp64d"} + !2 = !{i32 1, !"SmallDataLimit", i32 8} + !3 = !{!"clang version 14.9.0 (git@github.com:sifive/riscv-llvm-internal.git 1281f419ffb852a95a13cfce7b956c6a6ae63161)"} + +... +--- +name: main +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: vrm4, preferred-register: '' } + - { id: 1, class: vrm4, preferred-register: '' } + - { id: 2, class: gpr, preferred-register: '' } + - { id: 3, class: gpr, preferred-register: '' } +liveins: [] +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: dst, type: default, offset: 0, size: 400, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0.entry: + ; CHECK-LABEL: bb.0.entry + ; CHECK: %1:vrm4 = IMPLICIT_DEF + ; CHECK-NEXT: %4:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %5:vrm2 = PseudoVLE32_V_M2 killed %4, 0, 5 /* e32 */ + ; CHECK-NEXT: %6:vrm4 = INSERT_SUBREG %1, %5, %subreg.sub_vrm2_0 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: %2:gpr = ADDI %stack.0.dst, 0 + ; CHECK-NEXT: PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: %3:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY %3 + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm4 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %5:vrm2 = PseudoVLE32_V_M2 killed %7:gpr, 0, 5 + %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm2_0 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %2:gpr = ADDI %stack.0.dst, 0 + PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... diff --git a/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber_vrm8.mir b/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber_vrm8.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber_vrm8.mir @@ -0,0 +1,128 @@ +# RUN: llc %s -mtriple=riscv64 -mattr=+v -riscv-enable-subreg-liveness -run-pass=livestacks -o - | FileCheck %s + +--- | + ; ModuleID = 'test6.ll' + source_filename = "test6.c" + target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128" + target triple = "riscv64" + + ; Function Attrs: nounwind memory(write) vscale_range(2,1024) + define dso_local signext i32 @main() local_unnamed_addr #0 { + entry: + %dst = alloca [100 x float], align 8 + call void @llvm.lifetime.start.p0(i64 400, ptr nonnull %dst) #4 + %0 = tail call @llvm.riscv.vrgather.vx.nxv8f32.i64( undef, undef, i64 0, i64 0) + call void @llvm.riscv.vse.nxv8f32.i64( %0, ptr nonnull %dst, i64 0) + call void @llvm.lifetime.end.p0(i64 400, ptr nonnull %dst) #4 + ret i32 0 + } + + ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) + declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1 + + ; Function Attrs: nounwind memory(none) + declare @llvm.riscv.vrgather.vx.nxv8f32.i64(, , i64, i64) #2 + + ; Function Attrs: nounwind memory(write) + declare void @llvm.riscv.vse.nxv8f32.i64(, ptr nocapture, i64) #3 + + ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) + declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1 + + attributes #0 = { nounwind memory(write) vscale_range(2,1024) "frame-pointer"="none" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+m,+relax,+v,-save-restore,+v" } + attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) "target-features"="+v" } + attributes #2 = { nounwind memory(none) "target-features"="+v" } + attributes #3 = { nounwind memory(write) "target-features"="+v" } + attributes #4 = { nounwind } + + !llvm.module.flags = !{!0, !1, !2} + !llvm.ident = !{!3} + + !0 = !{i32 1, !"wchar_size", i32 4} + !1 = !{i32 1, !"target-abi", !"lp64d"} + !2 = !{i32 1, !"SmallDataLimit", i32 8} + !3 = !{!"clang version 14.9.0 (git@github.com:sifive/riscv-llvm-internal.git 1281f419ffb852a95a13cfce7b956c6a6ae63161)"} + +... +--- +name: main +alignment: 2 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: vrm8, preferred-register: '' } + - { id: 1, class: vrm8, preferred-register: '' } + - { id: 2, class: gpr, preferred-register: '' } + - { id: 3, class: gpr, preferred-register: '' } +liveins: [] +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 8 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: + - { id: 0, name: dst, type: default, offset: 0, size: 400, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + varArgsFrameIndex: 0 + varArgsSaveSize: 0 +body: | + bb.0.entry: + ; CHECK-LABEL: bb.0.entry + ; CHECK: %1:vrm8 = IMPLICIT_DEF + ; CHECK-NEXT: %4:gpr = ADDI $x0, 8 + ; CHECK-NEXT: %5:vrm4 = PseudoVLE32_V_M4 killed %4, 0, 5 /* e32 */ + ; CHECK-NEXT: %6:vrm8 = INSERT_SUBREG %1, %5, %subreg.sub_vrm4_0 + ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: %2:gpr = ADDI %stack.0.dst, 0 + ; CHECK-NEXT: PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + ; CHECK-NEXT: %3:gpr = COPY $x0 + ; CHECK-NEXT: $x10 = COPY %3 + ; CHECK-NEXT: PseudoRET implicit $x10 + %1:vrm8 = IMPLICIT_DEF + %7:gpr = ADDI $x0, 8 + %5:vrm4 = PseudoVLE32_V_M4 killed %7:gpr, 0, 5 + %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm4_0 + dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype + early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %2:gpr = ADDI %stack.0.dst, 0 + PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype + %3:gpr = COPY $x0 + $x10 = COPY %3 + PseudoRET implicit $x10 + +... diff --git a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll @@ -0,0 +1,147 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple riscv64 -mattr=+v -riscv-enable-subreg-liveness < %s | FileCheck %s + +define dso_local signext i32 @undef_early_clobber_chain() { +; CHECK-LABEL: undef_early_clobber_chain: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi sp, sp, -400 +; CHECK-NEXT: .cfi_def_cfa_offset 400 +; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma +; CHECK-NEXT: vrgather.vi v8, v8, 0 +; CHECK-NEXT: mv a0, sp +; CHECK-NEXT: vse32.v v8, (a0) +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: addi sp, sp, 400 +; CHECK-NEXT: ret +entry: + %dst = alloca [100 x float], align 8 + call void @llvm.lifetime.start.p0(i64 400, ptr nonnull %dst) #4 + %0 = tail call @llvm.riscv.vrgather.vx.nxv2f32.i64( undef, undef, i64 0, i64 0) + call void @llvm.riscv.vse.nxv2f32.i64( %0, ptr nonnull %dst, i64 0) + call void @llvm.lifetime.end.p0(i64 400, ptr nonnull %dst) #4 + ret i32 0 +} + +define internal void @SubRegLivenessUndefInPhi(i64 %cond) { +; CHECK-LABEL: SubRegLivenessUndefInPhi: +; CHECK: # %bb.0: # %start +; CHECK-NEXT: blez a0, .LBB1_2 +; CHECK-NEXT: # %bb.1: # %Cond1 +; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vadd.vi v10, v8, 1 +; CHECK-NEXT: vadd.vi v12, v8, 3 +; CHECK-NEXT: j .LBB1_3 +; CHECK-NEXT: .LBB1_2: # %Cond2 +; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma +; CHECK-NEXT: vid.v v9 +; CHECK-NEXT: csrr a0, vlenb +; CHECK-NEXT: srli a0, a0, 3 +; CHECK-NEXT: add a1, a0, a0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma +; CHECK-NEXT: vslideup.vx v8, v9, a0 +; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; CHECK-NEXT: vadd.vi v11, v9, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma +; CHECK-NEXT: vslideup.vx v10, v11, a0 +; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma +; CHECK-NEXT: vadd.vi v9, v9, 3 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma +; CHECK-NEXT: vslideup.vx v12, v9, a0 +; CHECK-NEXT: .LBB1_3: # %UseSR +; CHECK-NEXT: vl1r.v v14, (zero) +; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma +; CHECK-NEXT: vrgatherei16.vv v15, v14, v8 +; CHECK-NEXT: vrgatherei16.vv v8, v14, v10 +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: vand.vv v8, v15, v8 +; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma +; CHECK-NEXT: vrgatherei16.vv v9, v14, v12 +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: vs1r.v v8, (zero) +; CHECK-NEXT: ret +start: + %0 = icmp sgt i64 %cond, 0 + br i1 %0, label %Cond1, label %Cond2 + +Cond1: ; preds = %start + %v15 = tail call @llvm.experimental.stepvector.nxv1i16() + %v17 = tail call @llvm.vector.insert.nxv8i16.nxv1i16( poison, %v15, i64 0) + %vs12.i.i.i = add %v15, shufflevector ( insertelement ( poison, i16 1, i32 0), poison, zeroinitializer) + %v18 = tail call @llvm.vector.insert.nxv8i16.nxv1i16( poison, %vs12.i.i.i, i64 0) + %vs16.i.i.i = add %v15, shufflevector ( insertelement ( poison, i16 3, i32 0), poison, zeroinitializer) + %v20 = tail call @llvm.vector.insert.nxv8i16.nxv1i16( poison, %vs16.i.i.i, i64 0) + br label %UseSR + +Cond2: ; preds = %start + %v15.2 = tail call @llvm.experimental.stepvector.nxv1i16() + %v17.2 = tail call @llvm.vector.insert.nxv8i16.nxv1i16( poison, %v15.2, i64 1) + %vs12.i.i.i.2 = add %v15.2, shufflevector ( insertelement ( poison, i16 1, i32 0), poison, zeroinitializer) + %v18.2 = tail call @llvm.vector.insert.nxv8i16.nxv1i16( poison, %vs12.i.i.i.2, i64 1) + %vs16.i.i.i.2 = add %v15.2, shufflevector ( insertelement ( poison, i16 3, i32 0), poison, zeroinitializer) + %v20.2 = tail call @llvm.vector.insert.nxv8i16.nxv1i16( poison, %vs16.i.i.i.2, i64 1) + br label %UseSR + +UseSR: ; preds = %Cond1, Cond2 + %v17.3 = phi [ %v17, %Cond1 ], [ %v17.2, %Cond2 ] + %v18.3 = phi [ %v18, %Cond1 ], [ %v18.2, %Cond2 ] + %v20.3 = phi [ %v20, %Cond1 ], [ %v20.2, %Cond2 ] + %v37 = load , ptr addrspace(1) null, align 8 + %v38 = tail call @llvm.riscv.vrgatherei16.vv.nxv8i8.i64( undef, %v37, %v17.3, i64 4) + %v40 = tail call @llvm.riscv.vrgatherei16.vv.nxv8i8.i64( undef, %v37, %v18.3, i64 4) + %v42 = and %v38, %v40 + %v46 = tail call @llvm.riscv.vrgatherei16.vv.nxv8i8.i64( undef, %v37, %v20.3, i64 4) + %v60 = and %v42, %v46 + store %v60, ptr addrspace(1) null, align 4 + ret void +} + +define internal void @SubRegLivenessUndef() { +; CHECK-LABEL: SubRegLivenessUndef: +; CHECK: # %bb.0: # %loopIR.preheader.i.i +; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: vadd.vi v10, v8, 1 +; CHECK-NEXT: vadd.vi v12, v8, 3 +; CHECK-NEXT: .LBB2_1: # %loopIR3.i.i +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: vl1r.v v9, (zero) +; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma +; CHECK-NEXT: vrgatherei16.vv v11, v9, v8 +; CHECK-NEXT: vrgatherei16.vv v13, v9, v10 +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: vand.vv v11, v11, v13 +; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma +; CHECK-NEXT: vrgatherei16.vv v13, v9, v12 +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma +; CHECK-NEXT: vand.vv v9, v11, v13 +; CHECK-NEXT: vs1r.v v9, (zero) +; CHECK-NEXT: j .LBB2_1 +loopIR.preheader.i.i: + %v15 = tail call @llvm.experimental.stepvector.nxv1i16() + %v17 = tail call @llvm.vector.insert.nxv8i16.nxv1i16( poison, %v15, i64 0) + %vs12.i.i.i = add %v15, shufflevector ( insertelement ( poison, i16 1, i32 0), poison, zeroinitializer) + %v18 = tail call @llvm.vector.insert.nxv8i16.nxv1i16( poison, %vs12.i.i.i, i64 0) + %vs16.i.i.i = add %v15, shufflevector ( insertelement ( poison, i16 3, i32 0), poison, zeroinitializer) + %v20 = tail call @llvm.vector.insert.nxv8i16.nxv1i16( poison, %vs16.i.i.i, i64 0) + br label %loopIR3.i.i + +loopIR3.i.i: ; preds = %loopIR3.i.i, %loopIR.preheader.i.i + %v37 = load , ptr addrspace(1) null, align 8 + %v38 = tail call @llvm.riscv.vrgatherei16.vv.nxv8i8.i64( undef, %v37, %v17, i64 4) + %v40 = tail call @llvm.riscv.vrgatherei16.vv.nxv8i8.i64( undef, %v37, %v18, i64 4) + %v42 = and %v38, %v40 + %v46 = tail call @llvm.riscv.vrgatherei16.vv.nxv8i8.i64( undef, %v37, %v20, i64 4) + %v60 = and %v42, %v46 + store %v60, ptr addrspace(1) null, align 4 + br label %loopIR3.i.i +} + +declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) +declare @llvm.riscv.vrgather.vx.nxv2f32.i64(, , i64, i64) #2 +declare void @llvm.riscv.vse.nxv2f32.i64(, ptr nocapture, i64) +declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) +declare @llvm.experimental.stepvector.nxv1i16() +declare @llvm.vector.insert.nxv8i16.nxv1i16(, , i64 immarg) +declare @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(, , , i64)