Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp =================================================================== --- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp +++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp @@ -104,7 +104,7 @@ m_register_info_count(GetRegisterInfoCount(target_arch)) {} uint32_t RegisterInfoPOSIX_riscv64::GetRegisterCount() const { - return k_num_gpr_registers; + return m_register_info_count; } size_t RegisterInfoPOSIX_riscv64::GetGPRSize() const { @@ -121,7 +121,7 @@ } size_t RegisterInfoPOSIX_riscv64::GetRegisterSetCount() const { - return k_num_register_sets - 1; + return k_num_register_sets; } size_t RegisterInfoPOSIX_riscv64::GetRegisterSetFromRegisterIndex( Index: lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h =================================================================== --- lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h +++ lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h @@ -53,9 +53,13 @@ GPR64_KIND(gpr_##reg, generic_kind), nullptr, nullptr \ } -#define DEFINE_FPR64(reg, generic_kind) \ +#define DEFINE_FPR64(reg, generic_kind) DEFINE_FPR64_ALT(reg, reg, generic_kind) + +#define DEFINE_FPR64_ALT(reg, alt, generic_kind) DEFINE_FPR_ALT(reg, alt, 8, generic_kind) + +#define DEFINE_FPR_ALT(reg, alt, size, generic_kind) \ { \ - #reg, nullptr, 8, FPR_OFFSET(fpr_##reg##_riscv - fpr_first_riscv), \ + #reg, #alt, size, FPR_OFFSET(fpr_##reg##_riscv - fpr_first_riscv), \ lldb::eEncodingUint, lldb::eFormatHex, \ FPR64_KIND(fpr_##reg, generic_kind), nullptr, nullptr \ } @@ -98,38 +102,39 @@ DEFINE_GPR64(x31, LLDB_INVALID_REGNUM), DEFINE_GPR64(x0, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f0, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f1, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f2, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f3, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f4, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f5, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f6, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f7, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f8, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f9, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f10, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f11, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f12, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f13, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f14, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f15, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f16, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f17, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f18, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f19, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f20, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f21, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f22, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f23, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f24, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f25, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f26, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f27, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f28, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f29, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f30, LLDB_INVALID_REGNUM), - DEFINE_FPR64(f31, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(ft0, f0, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(ft1, f1, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(ft2, f2, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(ft3, f3, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(ft4, f4, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(ft5, f5, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(ft6, f6, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(ft7, f7, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fs0, f8, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fs1, f9, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fa0, f10, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fa1, f11, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fa2, f12, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fa3, f13, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fa4, f14, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fa5, f15, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fa6, f16, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fa7, f17, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fs2, f18, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fs3, f19, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fs4, f20, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fs5, f21, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fs6, f22, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fs7, f23, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fs8, f24, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fs9, f25, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fs10, f26, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(fs11, f27, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(ft8, f28, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(ft9, f29, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(ft10, f30, LLDB_INVALID_REGNUM), + DEFINE_FPR64_ALT(ft11, f31, LLDB_INVALID_REGNUM), + DEFINE_FPR_ALT(fcsr, nullptr, 4, LLDB_INVALID_REGNUM), }; #endif // DECLARE_REGISTER_INFOS_RISCV64_STRUCT Index: lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h =================================================================== --- lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h +++ lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h @@ -89,6 +89,38 @@ fpr_f31_riscv, fpr_fcsr_riscv, + fpr_ft0_riscv = fpr_f0_riscv, + fpr_ft1_riscv = fpr_f1_riscv, + fpr_ft2_riscv = fpr_f2_riscv, + fpr_ft3_riscv = fpr_f3_riscv, + fpr_ft4_riscv = fpr_f4_riscv, + fpr_ft5_riscv = fpr_f5_riscv, + fpr_ft6_riscv = fpr_f6_riscv, + fpr_ft7_riscv = fpr_f7_riscv, + fpr_fs0_riscv = fpr_f8_riscv, + fpr_fs1_riscv = fpr_f9_riscv, + fpr_fa0_riscv = fpr_f10_riscv, + fpr_fa1_riscv = fpr_f11_riscv, + fpr_fa2_riscv = fpr_f12_riscv, + fpr_fa3_riscv = fpr_f13_riscv, + fpr_fa4_riscv = fpr_f14_riscv, + fpr_fa5_riscv = fpr_f15_riscv, + fpr_fa6_riscv = fpr_f16_riscv, + fpr_fa7_riscv = fpr_f17_riscv, + fpr_fs2_riscv = fpr_f18_riscv, + fpr_fs3_riscv = fpr_f19_riscv, + fpr_fs4_riscv = fpr_f20_riscv, + fpr_fs5_riscv = fpr_f21_riscv, + fpr_fs6_riscv = fpr_f22_riscv, + fpr_fs7_riscv = fpr_f23_riscv, + fpr_fs8_riscv = fpr_f24_riscv, + fpr_fs9_riscv = fpr_f25_riscv, + fpr_fs10_riscv = fpr_f26_riscv, + fpr_fs11_riscv = fpr_f27_riscv, + fpr_ft8_riscv = fpr_f28_riscv, + fpr_ft9_riscv = fpr_f29_riscv, + fpr_ft10_riscv = fpr_f30_riscv, + fpr_ft11_riscv = fpr_f31_riscv, fpr_last_riscv = fpr_fcsr_riscv, k_num_registers_riscv Index: lldb/source/Utility/RISCV_DWARF_Registers.h =================================================================== --- lldb/source/Utility/RISCV_DWARF_Registers.h +++ lldb/source/Utility/RISCV_DWARF_Registers.h @@ -116,6 +116,7 @@ dwarf_v30, dwarf_v31 = 127, dwarf_first_csr = 4096, + dwarf_fpr_fcsr = dwarf_first_csr + 0x003, dwarf_last_csr = 8191, // register name alias @@ -123,6 +124,39 @@ dwarf_gpr_sp = dwarf_gpr_x2, dwarf_gpr_fp = dwarf_gpr_x8, + dwarf_fpr_ft0 = dwarf_fpr_f0, + dwarf_fpr_ft1 = dwarf_fpr_f1, + dwarf_fpr_ft2 = dwarf_fpr_f2, + dwarf_fpr_ft3 = dwarf_fpr_f3, + dwarf_fpr_ft4 = dwarf_fpr_f4, + dwarf_fpr_ft5 = dwarf_fpr_f5, + dwarf_fpr_ft6 = dwarf_fpr_f6, + dwarf_fpr_ft7 = dwarf_fpr_f7, + dwarf_fpr_fs0 = dwarf_fpr_f8, + dwarf_fpr_fs1 = dwarf_fpr_f9, + dwarf_fpr_fa0 = dwarf_fpr_f10, + dwarf_fpr_fa1 = dwarf_fpr_f11, + dwarf_fpr_fa2 = dwarf_fpr_f12, + dwarf_fpr_fa3 = dwarf_fpr_f13, + dwarf_fpr_fa4 = dwarf_fpr_f14, + dwarf_fpr_fa5 = dwarf_fpr_f15, + dwarf_fpr_fa6 = dwarf_fpr_f16, + dwarf_fpr_fa7 = dwarf_fpr_f17, + dwarf_fpr_fs2 = dwarf_fpr_f18, + dwarf_fpr_fs3 = dwarf_fpr_f19, + dwarf_fpr_fs4 = dwarf_fpr_f20, + dwarf_fpr_fs5 = dwarf_fpr_f21, + dwarf_fpr_fs6 = dwarf_fpr_f22, + dwarf_fpr_fs7 = dwarf_fpr_f23, + dwarf_fpr_fs8 = dwarf_fpr_f24, + dwarf_fpr_fs9 = dwarf_fpr_f25, + dwarf_fpr_fs10 = dwarf_fpr_f26, + dwarf_fpr_fs11 = dwarf_fpr_f27, + dwarf_fpr_ft8 = dwarf_fpr_f28, + dwarf_fpr_ft9 = dwarf_fpr_f29, + dwarf_fpr_ft10 = dwarf_fpr_f30, + dwarf_fpr_ft11 = dwarf_fpr_f31, + // mock pc regnum dwarf_gpr_pc = 11451, };