diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -82,16 +82,16 @@ def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, []>, Requires<[In64BitMode]>; - def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), + def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond), "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, []>, Requires<[In64BitMode]>; - def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), - "bcctr 12, $bi, 0", IIC_BrB, []>, + def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI), + "bcctr 12, $BI, 0", IIC_BrB, []>, Requires<[In64BitMode]>; - def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), - "bcctr 4, $bi, 0", IIC_BrB, []>, + def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI), + "bcctr 4, $BI, 0", IIC_BrB, []>, Requires<[In64BitMode]>; } } @@ -102,10 +102,10 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, hasSideEffects = 0 in { let Defs = [CTR8], Uses = [CTR8] in { - def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), - "bdz $dst">; - def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), - "bdnz $dst">; + def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD), + "bdz $BD">; + def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD), + "bdnz $BD">; } let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { @@ -121,39 +121,39 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8], hasSideEffects = 0 in { // Convenient aliases for call instructions let Uses = [RM] in { - def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), - "bl $func", IIC_BrB, []>; // See Pat patterns below. + def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$LI), + "bl $LI", IIC_BrB, []>; // See Pat patterns below. - def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), - "bl $func", IIC_BrB, []>; + def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$LI), + "bl $LI", IIC_BrB, []>; - def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), - "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>; + def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), + "bla $LI", IIC_BrB, [(PPCcall (i64 imm:$LI))]>; } let Uses = [RM], isCodeGenOnly = 1 in { def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, - (outs), (ins calltarget:$func), - "bl $func\n\tnop", IIC_BrB, []>; + (outs), (ins calltarget:$LI), + "bl $LI\n\tnop", IIC_BrB, []>; def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, - (outs), (ins tlscall:$func), - "bl $func\n\tnop", IIC_BrB, []>; + (outs), (ins tlscall:$LI), + "bl $LI\n\tnop", IIC_BrB, []>; def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, - (outs), (ins abscalltarget:$func), - "bla $func\n\tnop", IIC_BrB, - [(PPCcall_nop (i64 imm:$func))]>; + (outs), (ins abscalltarget:$LI), + "bla $LI\n\tnop", IIC_BrB, + [(PPCcall_nop (i64 imm:$LI))]>; let Predicates = [PCRelativeMemops] in { // BL8_NOTOC means that the caller does not use the TOC pointer and if // it does use R2 then it is just a caller saved register. Therefore it is // safe to emit only the bl and not the nop for this instruction. The // linker will not try to restore R2 after the call. def BL8_NOTOC : IForm<18, 0, 1, (outs), - (ins calltarget:$func), - "bl $func", IIC_BrB, []>; + (ins calltarget:$LI), + "bl $LI", IIC_BrB, []>; def BL8_NOTOC_TLS : IForm<18, 0, 1, (outs), - (ins tlscall:$func), - "bl $func", IIC_BrB, []>; + (ins tlscall:$LI), + "bl $LI", IIC_BrB, []>; } } let Uses = [CTR8, RM] in { @@ -163,16 +163,16 @@ Requires<[In64BitMode]>; let isCodeGenOnly = 1 in { - def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), + def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond), "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, []>, Requires<[In64BitMode]>; - def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), - "bcctrl 12, $bi, 0", IIC_BrB, []>, + def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI), + "bcctrl 12, $BI, 0", IIC_BrB, []>, Requires<[In64BitMode]>; - def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), - "bcctrl 4, $bi, 0", IIC_BrB, []>, + def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI), + "bcctrl 4, $BI, 0", IIC_BrB, []>, Requires<[In64BitMode]>; } } @@ -181,27 +181,27 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8, RM], hasSideEffects = 0, isCodeGenOnly = 1, Uses = [RM] in { // Convenient aliases for call instructions - def BL8_RM : IForm<18, 0, 1, (outs), (ins calltarget:$func), - "bl $func", IIC_BrB, []>; // See Pat patterns below. + def BL8_RM : IForm<18, 0, 1, (outs), (ins calltarget:$LI), + "bl $LI", IIC_BrB, []>; // See Pat patterns below. - def BLA8_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), - "bla $func", IIC_BrB, [(PPCcall_rm (i64 imm:$func))]>; + def BLA8_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), + "bla $LI", IIC_BrB, [(PPCcall_rm (i64 imm:$LI))]>; def BL8_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, - (outs), (ins calltarget:$func), - "bl $func\n\tnop", IIC_BrB, []>; + (outs), (ins calltarget:$LI), + "bl $LI\n\tnop", IIC_BrB, []>; def BLA8_NOP_RM : IForm_and_DForm_4_zero<18, 1, 1, 24, - (outs), (ins abscalltarget:$func), - "bla $func\n\tnop", IIC_BrB, - [(PPCcall_nop_rm (i64 imm:$func))]>; + (outs), (ins abscalltarget:$LI), + "bla $LI\n\tnop", IIC_BrB, + [(PPCcall_nop_rm (i64 imm:$LI))]>; let Predicates = [PCRelativeMemops] in { // BL8_NOTOC means that the caller does not use the TOC pointer and if // it does use R2 then it is just a caller saved register. Therefore it is // safe to emit only the bl and not the nop for this instruction. The // linker will not try to restore R2 after the call. def BL8_NOTOC_RM : IForm<18, 0, 1, (outs), - (ins calltarget:$func), - "bl $func", IIC_BrB, []>; + (ins calltarget:$LI), + "bl $LI", IIC_BrB, []>; } let Uses = [CTR8, RM] in { let isPredicable = 1 in @@ -238,8 +238,8 @@ // conflicts. let Interpretation64Bit = 1, isAsmParserOnly = 1, hasSideEffects = 0 in let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in -def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func), - "bl $func", IIC_BrB, []>; +def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$LI), + "bl $LI", IIC_BrB, []>; // Calls def : Pat<(PPCcall (i64 tglobaladdr:$dst)), @@ -332,38 +332,38 @@ // Instructions to support atomic operations let mayLoad = 1, hasSideEffects = 0 in { -def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), - "ldarx $rD, $ptr", IIC_LdStLDARX, []>; +def LDARX : XForm_1_memOp<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), + "ldarx $RST, $addr", IIC_LdStLDARX, []>; // TODO: Add scheduling info. let hasNoSchedulingInfo = 1 in -def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), - "lqarx $RTp, $ptr", IIC_LdStLQARX, []>, isPPC64; +def LQARX : XForm_1_memOp<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr), + "lqarx $RST, $addr", IIC_LdStLQARX, []>, isPPC64; // Instruction to support lock versions of atomics // (EH=1 - see Power ISA 2.07 Book II 4.4.2) -def LDARXL : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), - "ldarx $rD, $ptr, 1", IIC_LdStLDARX, []>, isRecordForm; +def LDARXL : XForm_1<31, 84, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), + "ldarx $RST, $addr, 1", IIC_LdStLDARX, []>, isRecordForm; // TODO: Add scheduling info. let hasNoSchedulingInfo = 1 in // FIXME: We have to seek a way to remove isRecordForm since // LQARXL is not really altering CR0. -def LQARXL : XForm_1<31, 276, (outs g8prc:$RTp), (ins memrr:$ptr), - "lqarx $RTp, $ptr, 1", IIC_LdStLQARX, []>, +def LQARXL : XForm_1<31, 276, (outs g8prc:$RST), (ins (memrr $RA, $RB):$addr), + "lqarx $RST, $addr, 1", IIC_LdStLQARX, []>, isPPC64, isRecordForm; let hasExtraDefRegAllocReq = 1 in -def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$rD), (ins g8rc:$rA, u5imm:$FC), - "ldat $rD, $rA, $FC", IIC_LdStLoad>, isPPC64, +def LDAT : X_RD5_RS5_IM5<31, 614, (outs g8rc:$RST), (ins g8rc:$RA, u5imm:$RB), + "ldat $RST, $RA, $RB", IIC_LdStLoad>, isPPC64, Requires<[IsISA3_0]>; } let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { -def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), - "stdcx. $rS, $dst", IIC_LdStSTDCX, []>, isRecordForm; +def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), + "stdcx. $RST, $addr", IIC_LdStSTDCX, []>, isRecordForm; // TODO: Add scheduling info. let hasNoSchedulingInfo = 1 in -def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RSp, memrr:$dst), - "stqcx. $RSp, $dst", IIC_LdStSTQCX, []>, +def STQCX : XForm_1_memOp<31, 182, (outs), (ins g8prc:$RST, (memrr $RA, $RB):$addr), + "stqcx. $RST, $addr", IIC_LdStSTQCX, []>, isPPC64, isRecordForm; } @@ -450,8 +450,8 @@ g8rc:$new_hi))>; let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in -def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$rS, g8rc:$rA, u5imm:$FC), - "stdat $rS, $rA, $FC", IIC_LdStStore>, isPPC64, +def STDAT : X_RD5_RS5_IM5<31, 742, (outs), (ins g8rc:$RST, g8rc:$RA, u5imm:$RB), + "stdat $RST, $RA, $RB", IIC_LdStStore>, isPPC64, Requires<[IsISA3_0]>; let Interpretation64Bit = 1, isCodeGenOnly = 1 in { @@ -480,14 +480,14 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in -def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), - "b $dst", IIC_BrB, +def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$LI), + "b $LI", IIC_BrB, []>; let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in -def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), - "ba $dst", IIC_BrB, +def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI), + "ba $LI", IIC_BrB, []>; } } // Interpretation64Bit @@ -509,14 +509,14 @@ // on the cr register selected. Thus, post-ra anti-dep breaking must not // later change that register assignment. let hasExtraDefRegAllocReq = 1 in { -def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), - "mtocrf $FXM, $ST", IIC_BrMCRX>, +def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$RST), + "mtocrf $FXM, $RST", IIC_BrMCRX>, PPC970_DGroup_First, PPC970_Unit_CRU; // Similarly to mtocrf, the mask for mtcrf must be prepared in a way that // is dependent on the cr fields being set. -def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), - "mtcrf $FXM, $rS", IIC_BrMCRX>, +def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$RST), + "mtcrf $FXM, $RST", IIC_BrMCRX>, PPC970_MicroCode, PPC970_Unit_CRU; } // hasExtraDefRegAllocReq = 1 @@ -524,14 +524,14 @@ // on the cr register selected. Thus, post-ra anti-dep breaking must not // later change that register assignment. let hasExtraSrcRegAllocReq = 1 in { -def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), - "mfocrf $rT, $FXM", IIC_SprMFCRF>, +def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$RST), (ins crbitm:$FXM), + "mfocrf $RST, $FXM", IIC_SprMFCRF>, PPC970_DGroup_First, PPC970_Unit_CRU; // Similarly to mfocrf, the mask for mfcrf must be prepared in a way that // is dependent on the cr fields being copied. -def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), - "mfcr $rT", IIC_SprMFCR>, +def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$RT), (ins), + "mfcr $RT", IIC_SprMFCR>, PPC970_MicroCode, PPC970_Unit_CRU; } // hasExtraSrcRegAllocReq = 1 } // hasSideEffects = 0 @@ -554,31 +554,31 @@ Requires<[In64BitMode]>; } -def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR), - "mfspr $RT, $SPR", IIC_SprMFSPR>; -def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT), - "mtspr $SPR, $RT", IIC_SprMTSPR>; +def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RST), (ins i32imm:$SPR), + "mfspr $RST, $SPR", IIC_SprMFSPR>; +def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RST), + "mtspr $SPR, $RST", IIC_SprMTSPR>; //===----------------------------------------------------------------------===// // 64-bit SPR manipulation instrs. let Uses = [CTR8] in { -def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), - "mfctr $rT", IIC_SprMFSPR>, +def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$RST), (ins), + "mfctr $RST", IIC_SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } -let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { -def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), - "mtctr $rS", IIC_SprMTSPR>, +let Pattern = [(PPCmtctr i64:$RST)], Defs = [CTR8] in { +def MTCTR8 : XFXForm_1_ext<31, 467, 9, (outs), (ins g8rc:$RST), + "mtctr $RST", IIC_SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } // MTCTR[8|]loop must be inside a loop-preheader, duplicating // the loop-preheader block will break this assumption. let hasSideEffects = 1, isNotDuplicable = 1, Defs = [CTR8] in { -let Pattern = [(int_set_loop_iterations i64:$rS)] in -def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), - "mtctr $rS", IIC_SprMTSPR>, +let Pattern = [(int_set_loop_iterations i64:$RST)] in +def MTCTR8loop : XFXForm_1_ext<31, 467, 9, (outs), (ins g8rc:$RST), + "mtctr $RST", IIC_SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } @@ -586,9 +586,9 @@ def DecreaseCTR8loop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i64imm:$stride), "#DecreaseCTR8loop", [(set i1:$rT, (int_loop_decrement (i64 imm:$stride)))]>; -let Pattern = [(set i64:$rT, readcyclecounter)] in -def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), - "mfspr $rT, 268", IIC_SprMFTB>, +let Pattern = [(set i64:$RST, readcyclecounter)] in +def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$RST), (ins), + "mfspr $RST, 268", IIC_SprMFTB>, PPC970_DGroup_First, PPC970_Unit_FXU; // Note that encoding mftb using mfspr is now the preferred form, // and has been since at least ISA v2.03. The mftb instruction has @@ -622,13 +622,13 @@ let hasSideEffects = 0 in { let Defs = [LR8] in { -def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), - "mtlr $rS", IIC_SprMTSPR>, +def MTLR8 : XFXForm_1_ext<31, 467, 8, (outs), (ins g8rc:$RST), + "mtlr $RST", IIC_SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } let Uses = [LR8] in { -def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), - "mflr $rT", IIC_SprMFSPR>, +def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$RST), (ins), + "mflr $RST", IIC_SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } } // Interpretation64Bit @@ -644,181 +644,181 @@ let isCodeGenOnly = 1 in { let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { -def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), - "li $rD, $imm", IIC_IntSimple, - [(set i64:$rD, imm64SExt16:$imm)]>, SExt32To64; -def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), - "lis $rD, $imm", IIC_IntSimple, - [(set i64:$rD, imm16ShiftedSExt:$imm)]>, SExt32To64; +def LI8 : DForm_2_r0<14, (outs g8rc:$RST), (ins s16imm64:$D), + "li $RST, $D", IIC_IntSimple, + [(set i64:$RST, imm64SExt16:$D)]>, SExt32To64; +def LIS8 : DForm_2_r0<15, (outs g8rc:$RST), (ins s17imm64:$D), + "lis $RST, $D", IIC_IntSimple, + [(set i64:$RST, imm16ShiftedSExt:$D)]>, SExt32To64; } // Logical ops. let isCommutable = 1 in { -defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "nand", "$rA, $rS, $rB", IIC_IntSimple, - [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; -defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "and", "$rA, $rS, $rB", IIC_IntSimple, - [(set i64:$rA, (and i64:$rS, i64:$rB))]>; +defm NAND8: XForm_6r<31, 476, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "nand", "$RA, $RST, $RB", IIC_IntSimple, + [(set i64:$RA, (not (and i64:$RST, i64:$RB)))]>; +defm AND8 : XForm_6r<31, 28, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "and", "$RA, $RST, $RB", IIC_IntSimple, + [(set i64:$RA, (and i64:$RST, i64:$RB))]>; } // isCommutable -defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "andc", "$rA, $rS, $rB", IIC_IntSimple, - [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; +defm ANDC8: XForm_6r<31, 60, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "andc", "$RA, $RST, $RB", IIC_IntSimple, + [(set i64:$RA, (and i64:$RST, (not i64:$RB)))]>; let isCommutable = 1 in { -defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "or", "$rA, $rS, $rB", IIC_IntSimple, - [(set i64:$rA, (or i64:$rS, i64:$rB))]>; -defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "nor", "$rA, $rS, $rB", IIC_IntSimple, - [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; +defm OR8 : XForm_6r<31, 444, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "or", "$RA, $RST, $RB", IIC_IntSimple, + [(set i64:$RA, (or i64:$RST, i64:$RB))]>; +defm NOR8 : XForm_6r<31, 124, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "nor", "$RA, $RST, $RB", IIC_IntSimple, + [(set i64:$RA, (not (or i64:$RST, i64:$RB)))]>; } // isCommutable -defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "orc", "$rA, $rS, $rB", IIC_IntSimple, - [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; +defm ORC8 : XForm_6r<31, 412, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "orc", "$RA, $RST, $RB", IIC_IntSimple, + [(set i64:$RA, (or i64:$RST, (not i64:$RB)))]>; let isCommutable = 1 in { -defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "eqv", "$rA, $rS, $rB", IIC_IntSimple, - [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; -defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "xor", "$rA, $rS, $rB", IIC_IntSimple, - [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; +defm EQV8 : XForm_6r<31, 284, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "eqv", "$RA, $RST, $RB", IIC_IntSimple, + [(set i64:$RA, (not (xor i64:$RST, i64:$RB)))]>; +defm XOR8 : XForm_6r<31, 316, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "xor", "$RA, $RST, $RB", IIC_IntSimple, + [(set i64:$RA, (xor i64:$RST, i64:$RB))]>; } // let isCommutable = 1 // Logical ops with immediate. let Defs = [CR0] in { -def ANDI8_rec : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), - "andi. $dst, $src1, $src2", IIC_IntGeneral, - [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, +def ANDI8_rec : DForm_4<28, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), + "andi. $RA, $RST, $D", IIC_IntGeneral, + [(set i64:$RA, (and i64:$RST, immZExt16:$D))]>, isRecordForm, SExt32To64, ZExt32To64; -def ANDIS8_rec : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), - "andis. $dst, $src1, $src2", IIC_IntGeneral, - [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, +def ANDIS8_rec : DForm_4<29, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), + "andis. $RA, $RST, $D", IIC_IntGeneral, + [(set i64:$RA, (and i64:$RST, imm16ShiftedZExt:$D))]>, isRecordForm, ZExt32To64; } -def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), - "ori $dst, $src1, $src2", IIC_IntSimple, - [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; -def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), - "oris $dst, $src1, $src2", IIC_IntSimple, - [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; -def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), - "xori $dst, $src1, $src2", IIC_IntSimple, - [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; -def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), - "xoris $dst, $src1, $src2", IIC_IntSimple, - [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; +def ORI8 : DForm_4<24, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), + "ori $RA, $RST, $D", IIC_IntSimple, + [(set i64:$RA, (or i64:$RST, immZExt16:$D))]>; +def ORIS8 : DForm_4<25, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), + "oris $RA, $RST, $D", IIC_IntSimple, + [(set i64:$RA, (or i64:$RST, imm16ShiftedZExt:$D))]>; +def XORI8 : DForm_4<26, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), + "xori $RA, $RST, $D", IIC_IntSimple, + [(set i64:$RA, (xor i64:$RST, immZExt16:$D))]>; +def XORIS8 : DForm_4<27, (outs g8rc:$RA), (ins g8rc:$RST, u16imm64:$D), + "xoris $RA, $RST, $D", IIC_IntSimple, + [(set i64:$RA, (xor i64:$RST, imm16ShiftedZExt:$D))]>; let isCommutable = 1 in -defm ADD8 : XOForm_1rx<31, 266, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "add", "$rT, $rA, $rB", IIC_IntSimple, - [(set i64:$rT, (add i64:$rA, i64:$rB))]>; +defm ADD8 : XOForm_1rx<31, 266, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), + "add", "$RT, $RA, $RB", IIC_IntSimple, + [(set i64:$RT, (add i64:$RA, i64:$RB))]>; // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the // initial-exec thread-local storage model. We need to forbid r0 here - // while it works for add just fine, the linker can relax this to local-exec // addi, which won't work for r0. -def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc_nox0:$rA, tlsreg:$rB), - "add $rT, $rA, $rB", IIC_IntSimple, - [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; +def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc_nox0:$RA, tlsreg:$RB), + "add $RT, $RA, $RB", IIC_IntSimple, + [(set i64:$RT, (add i64:$RA, tglobaltlsaddr:$RB))]>; let mayLoad = 1 in { -def LBZXTLS : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), - "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; -def LHZXTLS : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), - "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; -def LWZXTLS : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), - "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; -def LDXTLS : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), - "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; -def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), - "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; -def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), - "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; -def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), - "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; +def LBZXTLS : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), + "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; +def LHZXTLS : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), + "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; +def LWZXTLS : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), + "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; +def LDXTLS : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), + "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64; +def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), + "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; +def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), + "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; +def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), + "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; } let mayStore = 1 in { -def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), - "stbx $rS, $rA, $rB", IIC_LdStStore, []>, +def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), + "stbx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), - "sthx $rS, $rA, $rB", IIC_LdStStore, []>, +def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), + "sthx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), - "stwx $rS, $rA, $rB", IIC_LdStStore, []>, +def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), + "stwx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), - "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, +def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), + "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64, PPC970_DGroup_Cracked; -def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), - "stbx $rS, $rA, $rB", IIC_LdStStore, []>, +def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), + "stbx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), - "sthx $rS, $rA, $rB", IIC_LdStStore, []>, +def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), + "sthx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), - "stwx $rS, $rA, $rB", IIC_LdStStore, []>, +def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), + "stwx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; } let isCommutable = 1 in -defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "addc", "$rT, $rA, $rB", IIC_IntGeneral, - [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, +defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), + "addc", "$RT, $RA, $RB", IIC_IntGeneral, + [(set i64:$RT, (addc i64:$RA, i64:$RB))]>, PPC970_DGroup_Cracked; let Defs = [CARRY] in -def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), - "addic $rD, $rA, $imm", IIC_IntGeneral, - [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; -def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), - "addi $rD, $rA, $imm", IIC_IntSimple, - [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; -def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), - "addis $rD, $rA, $imm", IIC_IntSimple, - [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; - -def LA8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$sym), - "la $rD, $sym($rA)", IIC_IntGeneral, - [(set i64:$rD, (add i64:$rA, - (PPClo tglobaladdr:$sym, 0)))]>; +def ADDIC8 : DForm_2<12, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D), + "addic $RST, $RA, $D", IIC_IntGeneral, + [(set i64:$RST, (addc i64:$RA, imm64SExt16:$D))]>; +def ADDI8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D), + "addi $RST, $RA, $D", IIC_IntSimple, + [(set i64:$RST, (add i64:$RA, imm64SExt16:$D))]>; +def ADDIS8 : DForm_2<15, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s17imm64:$D), + "addis $RST, $RA, $D", IIC_IntSimple, + [(set i64:$RST, (add i64:$RA, imm16ShiftedSExt:$D))]>; + +def LA8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D), + "la $RST, $D($RA)", IIC_IntGeneral, + [(set i64:$RST, (add i64:$RA, + (PPClo tglobaladdr:$D, 0)))]>; let Defs = [CARRY] in { -def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), - "subfic $rD, $rA, $imm", IIC_IntGeneral, - [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; +def SUBFIC8: DForm_2< 8, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D), + "subfic $RST, $RA, $D", IIC_IntGeneral, + [(set i64:$RST, (subc imm64SExt16:$D, i64:$RA))]>; } -defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "subfc", "$rT, $rA, $rB", IIC_IntGeneral, - [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, +defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), + "subfc", "$RT, $RA, $RB", IIC_IntGeneral, + [(set i64:$RT, (subc i64:$RB, i64:$RA))]>, PPC970_DGroup_Cracked; -defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "subf", "$rT, $rA, $rB", IIC_IntGeneral, - [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; -defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), - "neg", "$rT, $rA", IIC_IntSimple, - [(set i64:$rT, (ineg i64:$rA))]>; +defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), + "subf", "$RT, $RA, $RB", IIC_IntGeneral, + [(set i64:$RT, (sub i64:$RB, i64:$RA))]>; +defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$RT), (ins g8rc:$RA), + "neg", "$RT, $RA", IIC_IntSimple, + [(set i64:$RT, (ineg i64:$RA))]>; let Uses = [CARRY] in { let isCommutable = 1 in -defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "adde", "$rT, $rA, $rB", IIC_IntGeneral, - [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; -defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), - "addme", "$rT, $rA", IIC_IntGeneral, - [(set i64:$rT, (adde i64:$rA, -1))]>; -defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), - "addze", "$rT, $rA", IIC_IntGeneral, - [(set i64:$rT, (adde i64:$rA, 0))]>; -defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "subfe", "$rT, $rA, $rB", IIC_IntGeneral, - [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; -defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), - "subfme", "$rT, $rA", IIC_IntGeneral, - [(set i64:$rT, (sube -1, i64:$rA))]>; -defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), - "subfze", "$rT, $rA", IIC_IntGeneral, - [(set i64:$rT, (sube 0, i64:$rA))]>; +defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), + "adde", "$RT, $RA, $RB", IIC_IntGeneral, + [(set i64:$RT, (adde i64:$RA, i64:$RB))]>; +defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$RT), (ins g8rc:$RA), + "addme", "$RT, $RA", IIC_IntGeneral, + [(set i64:$RT, (adde i64:$RA, -1))]>; +defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$RT), (ins g8rc:$RA), + "addze", "$RT, $RA", IIC_IntGeneral, + [(set i64:$RT, (adde i64:$RA, 0))]>; +defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), + "subfe", "$RT, $RA, $RB", IIC_IntGeneral, + [(set i64:$RT, (sube i64:$RB, i64:$RA))]>; +defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$RT), (ins g8rc:$RA), + "subfme", "$RT, $RA", IIC_IntGeneral, + [(set i64:$RT, (sube -1, i64:$RA))]>; +defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$RT), (ins g8rc:$RA), + "subfze", "$RT, $RA", IIC_IntGeneral, + [(set i64:$RT, (sube 0, i64:$RA))]>; } } // isCodeGenOnly @@ -826,202 +826,202 @@ // previous definition must be marked as CodeGen only to prevent decoding // conflicts. let isAsmParserOnly = 1 in { -def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), - "add $rT, $rA, $rB", IIC_IntSimple, []>; +def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc:$RA, tlsreg:$RB), + "add $RT, $RA, $RB", IIC_IntSimple, []>; let mayLoad = 1 in { -def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), - "lbzx $rD, $rA, $rB", IIC_LdStLoad, []>; -def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), - "lhzx $rD, $rA, $rB", IIC_LdStLoad, []>; -def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), - "lwzx $rD, $rA, $rB", IIC_LdStLoad, []>; -def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$rD), (ins ptr_rc_nor0:$rA, tlsreg:$rB), - "ldx $rD, $rA, $rB", IIC_LdStLD, []>, isPPC64; +def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), + "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; +def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), + "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; +def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), + "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; +def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), + "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64; } let mayStore = 1 in { -def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), - "stbx $rS, $rA, $rB", IIC_LdStStore, []>, +def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), + "stbx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), - "sthx $rS, $rA, $rB", IIC_LdStStore, []>, +def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), + "sthx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), - "stwx $rS, $rA, $rB", IIC_LdStStore, []>, +def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), + "stwx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$rS, ptr_rc_nor0:$rA, tlsreg:$rB), - "stdx $rS, $rA, $rB", IIC_LdStSTD, []>, isPPC64, +def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), + "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64, PPC970_DGroup_Cracked; } } let isCommutable = 1 in { -defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "mulhd", "$rT, $rA, $rB", IIC_IntMulHW, - [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; -defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU, - [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; +defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), + "mulhd", "$RT, $RA, $RB", IIC_IntMulHW, + [(set i64:$RT, (mulhs i64:$RA, i64:$RB))]>; +defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), + "mulhdu", "$RT, $RA, $RB", IIC_IntMulHWU, + [(set i64:$RT, (mulhu i64:$RA, i64:$RB))]>; } // isCommutable } } // Interpretation64Bit let isCompare = 1, hasSideEffects = 0 in { - def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), - "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64; - def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), - "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64; - def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm), - "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64; - def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2), - "cmpldi $dst, $src1, $src2", + def CMPD : XForm_16_ext<31, 0, (outs crrc:$BF), (ins g8rc:$RA, g8rc:$RB), + "cmpd $BF, $RA, $RB", IIC_IntCompare>, isPPC64; + def CMPLD : XForm_16_ext<31, 32, (outs crrc:$BF), (ins g8rc:$RA, g8rc:$RB), + "cmpld $BF, $RA, $RB", IIC_IntCompare>, isPPC64; + def CMPDI : DForm_5_ext<11, (outs crrc:$BF), (ins g8rc:$RA, s16imm64:$D), + "cmpdi $BF, $RA, $D", IIC_IntCompare>, isPPC64; + def CMPLDI : DForm_6_ext<10, (outs crrc:$BF), (ins g8rc:$RA, u16imm64:$D), + "cmpldi $BF, $RA, $D", IIC_IntCompare>, isPPC64; let Interpretation64Bit = 1, isCodeGenOnly = 1 in def CMPRB8 : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), - (ins u1imm:$L, g8rc:$rA, g8rc:$rB), - "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, + (ins u1imm:$L, g8rc:$RA, g8rc:$RB), + "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>, Requires<[IsISA3_0]>; def CMPEQB : X_BF3_RS5_RS5<31, 224, (outs crrc:$BF), - (ins g8rc:$rA, g8rc:$rB), "cmpeqb $BF, $rA, $rB", + (ins g8rc:$RA, g8rc:$RB), "cmpeqb $BF, $RA, $RB", IIC_IntCompare, []>, Requires<[IsISA3_0]>; } let hasSideEffects = 0 in { -defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), - "sld", "$rA, $rS, $rB", IIC_IntRotateD, - [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; -defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), - "srd", "$rA, $rS, $rB", IIC_IntRotateD, - [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; -defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), - "srad", "$rA, $rS, $rB", IIC_IntRotateD, - [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; +defm SLD : XForm_6r<31, 27, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB), + "sld", "$RA, $RST, $RB", IIC_IntRotateD, + [(set i64:$RA, (PPCshl i64:$RST, i32:$RB))]>, isPPC64; +defm SRD : XForm_6r<31, 539, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB), + "srd", "$RA, $RST, $RB", IIC_IntRotateD, + [(set i64:$RA, (PPCsrl i64:$RST, i32:$RB))]>, isPPC64; +defm SRAD : XForm_6rc<31, 794, (outs g8rc:$RA), (ins g8rc:$RST, gprc:$RB), + "srad", "$RA, $RST, $RB", IIC_IntRotateD, + [(set i64:$RA, (PPCsra i64:$RST, i32:$RB))]>, isPPC64; let Interpretation64Bit = 1, isCodeGenOnly = 1 in { -defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$rA), (ins g8rc:$rS), - "cntlzw", "$rA, $rS", IIC_IntGeneral, []>, +defm CNTLZW8 : XForm_11r<31, 26, (outs g8rc:$RA), (ins g8rc:$RST), + "cntlzw", "$RA, $RST", IIC_IntGeneral, []>, ZExt32To64, SExt32To64; -defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$rA), (ins g8rc:$rS), - "cnttzw", "$rA, $rS", IIC_IntGeneral, []>, +defm CNTTZW8 : XForm_11r<31, 538, (outs g8rc:$RA), (ins g8rc:$RST), + "cnttzw", "$RA, $RST", IIC_IntGeneral, []>, Requires<[IsISA3_0]>, ZExt32To64, SExt32To64; -defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), - "extsb", "$rA, $rS", IIC_IntSimple, - [(set i64:$rA, (sext_inreg i64:$rS, i8))]>, SExt32To64; -defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), - "extsh", "$rA, $rS", IIC_IntSimple, - [(set i64:$rA, (sext_inreg i64:$rS, i16))]>, SExt32To64; - -defm SLW8 : XForm_6r<31, 24, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "slw", "$rA, $rS, $rB", IIC_IntGeneral, []>, ZExt32To64; -defm SRW8 : XForm_6r<31, 536, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "srw", "$rA, $rS, $rB", IIC_IntGeneral, []>, ZExt32To64; +defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$RA), (ins g8rc:$RST), + "extsb", "$RA, $RST", IIC_IntSimple, + [(set i64:$RA, (sext_inreg i64:$RST, i8))]>, SExt32To64; +defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$RA), (ins g8rc:$RST), + "extsh", "$RA, $RST", IIC_IntSimple, + [(set i64:$RA, (sext_inreg i64:$RST, i16))]>, SExt32To64; + +defm SLW8 : XForm_6r<31, 24, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "slw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64; +defm SRW8 : XForm_6r<31, 536, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "srw", "$RA, $RST, $RB", IIC_IntGeneral, []>, ZExt32To64; } // Interpretation64Bit // For fast-isel: let isCodeGenOnly = 1 in { -def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), - "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64, +def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$RA), (ins gprc:$RST), + "extsb $RA, $RST", IIC_IntSimple, []>, isPPC64, SExt32To64; -def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), - "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64, +def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$RA), (ins gprc:$RST), + "extsh $RA, $RST", IIC_IntSimple, []>, isPPC64, SExt32To64; } // isCodeGenOnly for fast-isel -defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), - "extsw", "$rA, $rS", IIC_IntSimple, - [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64, +defm EXTSW : XForm_11r<31, 986, (outs g8rc:$RA), (ins g8rc:$RST), + "extsw", "$RA, $RST", IIC_IntSimple, + [(set i64:$RA, (sext_inreg i64:$RST, i32))]>, isPPC64, SExt32To64; let Interpretation64Bit = 1, isCodeGenOnly = 1 in -defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), - "extsw", "$rA, $rS", IIC_IntSimple, - [(set i64:$rA, (sext i32:$rS))]>, isPPC64, +defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$RA), (ins gprc:$RST), + "extsw", "$RA, $RST", IIC_IntSimple, + [(set i64:$RA, (sext i32:$RST))]>, isPPC64, SExt32To64; let isCodeGenOnly = 1 in -def EXTSW_32 : XForm_11<31, 986, (outs gprc:$rA), (ins gprc:$rS), - "extsw $rA, $rS", IIC_IntSimple, +def EXTSW_32 : XForm_11<31, 986, (outs gprc:$RA), (ins gprc:$RST), + "extsw $RA, $RST", IIC_IntSimple, []>, isPPC64; -defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), - "sradi", "$rA, $rS, $SH", IIC_IntRotateDI, - [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; +defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH), + "sradi", "$RA, $RS, $SH", IIC_IntRotateDI, + [(set i64:$RA, (sra i64:$RS, (i32 imm:$SH)))]>, isPPC64; let Interpretation64Bit = 1, isCodeGenOnly = 1 in -defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$rA), - (ins gprc:$rS, u6imm:$SH), - "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, - [(set i64:$rA, - (PPCextswsli i32:$rS, (i32 imm:$SH)))]>, +defm EXTSWSLI_32_64 : XSForm_1r<31, 445, (outs g8rc:$RA), + (ins gprc:$RS, u6imm:$SH), + "extswsli", "$RA, $RS, $SH", IIC_IntRotateDI, + [(set i64:$RA, + (PPCextswsli i32:$RS, (i32 imm:$SH)))]>, isPPC64, Requires<[IsISA3_0]>; -defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), - "extswsli", "$rA, $rS, $SH", IIC_IntRotateDI, +defm EXTSWSLI : XSForm_1rc<31, 445, (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH), + "extswsli", "$RA, $RS, $SH", IIC_IntRotateDI, []>, isPPC64, Requires<[IsISA3_0]>; // For fast-isel: let isCodeGenOnly = 1, Defs = [CARRY] in -def SRADI_32 : XSForm_1<31, 413, (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH), - "sradi $rA, $rS, $SH", IIC_IntRotateDI, []>, isPPC64; +def SRADI_32 : XSForm_1<31, 413, (outs gprc:$RA), (ins gprc:$RS, u6imm:$SH), + "sradi $RA, $RS, $SH", IIC_IntRotateDI, []>, isPPC64; -defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), - "cntlzd", "$rA, $rS", IIC_IntGeneral, - [(set i64:$rA, (ctlz i64:$rS))]>, +defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$RA), (ins g8rc:$RST), + "cntlzd", "$RA, $RST", IIC_IntGeneral, + [(set i64:$RA, (ctlz i64:$RST))]>, ZExt32To64, SExt32To64; -defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$rA), (ins g8rc:$rS), - "cnttzd", "$rA, $rS", IIC_IntGeneral, - [(set i64:$rA, (cttz i64:$rS))]>, Requires<[IsISA3_0]>, +defm CNTTZD : XForm_11r<31, 570, (outs g8rc:$RA), (ins g8rc:$RST), + "cnttzd", "$RA, $RST", IIC_IntGeneral, + [(set i64:$RA, (cttz i64:$RST))]>, Requires<[IsISA3_0]>, ZExt32To64, SExt32To64; -def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), - "popcntd $rA, $rS", IIC_IntGeneral, - [(set i64:$rA, (ctpop i64:$rS))]>, +def POPCNTD : XForm_11<31, 506, (outs g8rc:$RA), (ins g8rc:$RST), + "popcntd $RA, $RST", IIC_IntGeneral, + [(set i64:$RA, (ctpop i64:$RST))]>, ZExt32To64, SExt32To64; -def BPERMD : XForm_6<31, 252, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "bpermd $rA, $rS, $rB", IIC_IntGeneral, - [(set i64:$rA, (int_ppc_bpermd g8rc:$rS, g8rc:$rB))]>, +def BPERMD : XForm_6<31, 252, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "bpermd $RA, $RST, $RB", IIC_IntGeneral, + [(set i64:$RA, (int_ppc_bpermd g8rc:$RST, g8rc:$RB))]>, isPPC64, Requires<[HasBPERMD]>; let isCodeGenOnly = 1, isCommutable = 1 in -def CMPB8 : XForm_6<31, 508, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "cmpb $rA, $rS, $rB", IIC_IntGeneral, - [(set i64:$rA, (PPCcmpb i64:$rS, i64:$rB))]>; +def CMPB8 : XForm_6<31, 508, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "cmpb $RA, $RST, $RB", IIC_IntGeneral, + [(set i64:$RA, (PPCcmpb i64:$RST, i64:$RB))]>; // popcntw also does a population count on the high 32 bits (storing the // results in the high 32-bits of the output). We'll ignore that here (which is // safe because we never separately use the high part of the 64-bit registers). -def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), - "popcntw $rA, $rS", IIC_IntGeneral, - [(set i32:$rA, (ctpop i32:$rS))]>; +def POPCNTW : XForm_11<31, 378, (outs gprc:$RA), (ins gprc:$RST), + "popcntw $RA, $RST", IIC_IntGeneral, + [(set i32:$RA, (ctpop i32:$RST))]>; let isCodeGenOnly = 1 in -def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$rA), (ins g8rc:$rS), - "popcntb $rA, $rS", IIC_IntGeneral, - [(set i64:$rA, (int_ppc_popcntb i64:$rS))]>; - -defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "divd", "$rT, $rA, $rB", IIC_IntDivD, - [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64; -defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "divdu", "$rT, $rA, $rB", IIC_IntDivD, - [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64; -defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "divde", "$rT, $rA, $rB", IIC_IntDivD, - [(set i64:$rT, (int_ppc_divde g8rc:$rA, g8rc:$rB))]>, +def POPCNTB8 : XForm_11<31, 122, (outs g8rc:$RA), (ins g8rc:$RST), + "popcntb $RA, $RST", IIC_IntGeneral, + [(set i64:$RA, (int_ppc_popcntb i64:$RST))]>; + +defm DIVD : XOForm_1rcr<31, 489, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), + "divd", "$RT, $RA, $RB", IIC_IntDivD, + [(set i64:$RT, (sdiv i64:$RA, i64:$RB))]>, isPPC64; +defm DIVDU : XOForm_1rcr<31, 457, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), + "divdu", "$RT, $RA, $RB", IIC_IntDivD, + [(set i64:$RT, (udiv i64:$RA, i64:$RB))]>, isPPC64; +defm DIVDE : XOForm_1rcr<31, 425, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), + "divde", "$RT, $RA, $RB", IIC_IntDivD, + [(set i64:$RT, (int_ppc_divde g8rc:$RA, g8rc:$RB))]>, isPPC64, Requires<[HasExtDiv]>; let Predicates = [IsISA3_0] in { -def MADDHD : VAForm_1a<48, (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), +def MADDHD : VAForm_1a<48, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), "maddhd $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; def MADDHDU : VAForm_1a<49, - (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), + (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), "maddhdu $RT, $RA, $RB, $RC", IIC_IntMulHD, []>, isPPC64; -def MADDLD : VAForm_1a<51, (outs gprc :$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), +def MADDLD : VAForm_1a<51, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB, gprc:$RC), "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, [(set i32:$RT, (add_without_simm16 (mul_without_simm16 i32:$RA, i32:$RB), i32:$RC))]>, isPPC64; let Interpretation64Bit = 1, isCodeGenOnly = 1 in { def MADDLD8 : VAForm_1a<51, - (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), + (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC), "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD, [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>, isPPC64; @@ -1030,26 +1030,26 @@ } def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D), "addpcis $RT, $D", IIC_BrB, []>, isPPC64; -def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "modsd $rT, $rA, $rB", IIC_IntDivW, - [(set i64:$rT, (srem i64:$rA, i64:$rB))]>; -def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "modud $rT, $rA, $rB", IIC_IntDivW, - [(set i64:$rT, (urem i64:$rA, i64:$rB))]>; +def MODSD : XForm_8<31, 777, (outs g8rc:$RST), (ins g8rc:$RA, g8rc:$RB), + "modsd $RST, $RA, $RB", IIC_IntDivW, + [(set i64:$RST, (srem i64:$RA, i64:$RB))]>; +def MODUD : XForm_8<31, 265, (outs g8rc:$RST), (ins g8rc:$RA, g8rc:$RB), + "modud $RST, $RA, $RB", IIC_IntDivW, + [(set i64:$RST, (urem i64:$RA, i64:$RB))]>; } -defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "divdeu", "$rT, $rA, $rB", IIC_IntDivD, - [(set i64:$rT, (int_ppc_divdeu g8rc:$rA, g8rc:$rB))]>, +defm DIVDEU : XOForm_1rcr<31, 393, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), + "divdeu", "$RT, $RA, $RB", IIC_IntDivD, + [(set i64:$RT, (int_ppc_divdeu g8rc:$RA, g8rc:$RB))]>, isPPC64, Requires<[HasExtDiv]>; let isCommutable = 1 in -defm MULLD : XOForm_1rx<31, 233, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), - "mulld", "$rT, $rA, $rB", IIC_IntMulHD, - [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; +defm MULLD : XOForm_1rx<31, 233, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB), + "mulld", "$RT, $RA, $RB", IIC_IntMulHD, + [(set i64:$RT, (mul i64:$RA, i64:$RB))]>, isPPC64; let Interpretation64Bit = 1, isCodeGenOnly = 1 in -def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), - "mulli $rD, $rA, $imm", IIC_IntMulLI, - [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; +def MULLI8 : DForm_2<7, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D), + "mulli $RST, $RA, $D", IIC_IntMulLI, + [(set i64:$RST, (mul i64:$RA, imm64SExt16:$D))]>; } let hasSideEffects = 1 in { @@ -1058,76 +1058,76 @@ } let hasSideEffects = 0 in { -defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), - (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), - "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, - []>, isPPC64, RegConstraint<"$rSi = $rA">, - NoEncode<"$rSi">; +defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$RA), + (ins g8rc:$RAi, g8rc:$RS, u6imm:$SH, u6imm:$MBE), + "rldimi", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, + []>, isPPC64, RegConstraint<"$RAi = $RA">, + NoEncode<"$RAi">; // Rotate instructions. defm RLDCL : MDSForm_1r<30, 8, - (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), - "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, + (outs g8rc:$RA), (ins g8rc:$RS, gprc:$RB, u6imm:$MBE), + "rldcl", "$RA, $RS, $RB, $MBE", IIC_IntRotateD, []>, isPPC64; defm RLDCR : MDSForm_1r<30, 9, - (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), - "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD, + (outs g8rc:$RA), (ins g8rc:$RS, gprc:$RB, u6imm:$MBE), + "rldcr", "$RA, $RS, $RB, $MBE", IIC_IntRotateD, []>, isPPC64; defm RLDICL : MDForm_1r<30, 0, - (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), - "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, + (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE), + "rldicl", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, []>, isPPC64; // For fast-isel: let isCodeGenOnly = 1 in def RLDICL_32_64 : MDForm_1<30, 0, - (outs g8rc:$rA), - (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), - "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI, + (outs g8rc:$RA), + (ins gprc:$RS, u6imm:$SH, u6imm:$MBE), + "rldicl $RA, $RS, $SH, $MBE", IIC_IntRotateDI, []>, isPPC64; // End fast-isel. let Interpretation64Bit = 1, isCodeGenOnly = 1 in defm RLDICL_32 : MDForm_1r<30, 0, - (outs gprc:$rA), - (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), - "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, + (outs gprc:$RA), + (ins gprc:$RS, u6imm:$SH, u6imm:$MBE), + "rldicl", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, []>, isPPC64; defm RLDICR : MDForm_1r<30, 1, - (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), - "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, + (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE), + "rldicr", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, []>, isPPC64; let isCodeGenOnly = 1 in def RLDICR_32 : MDForm_1<30, 1, - (outs gprc:$rA), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE), - "rldicr $rA, $rS, $SH, $MBE", IIC_IntRotateDI, + (outs gprc:$RA), (ins gprc:$RS, u6imm:$SH, u6imm:$MBE), + "rldicr $RA, $RS, $SH, $MBE", IIC_IntRotateDI, []>, isPPC64; defm RLDIC : MDForm_1r<30, 2, - (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), - "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI, + (outs g8rc:$RA), (ins g8rc:$RS, u6imm:$SH, u6imm:$MBE), + "rldic", "$RA, $RS, $SH, $MBE", IIC_IntRotateDI, []>, isPPC64; let Interpretation64Bit = 1, isCodeGenOnly = 1 in { -defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), - (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), - "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, +defm RLWINM8 : MForm_2r<21, (outs g8rc:$RA), + (ins g8rc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), + "rlwinm", "$RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, []>; -defm RLWNM8 : MForm_2r<23, (outs g8rc:$rA), - (ins g8rc:$rS, g8rc:$rB, u5imm:$MB, u5imm:$ME), - "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, +defm RLWNM8 : MForm_1r<23, (outs g8rc:$RA), + (ins g8rc:$RS, g8rc:$RB, u5imm:$MB, u5imm:$ME), + "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral, []>; // RLWIMI can be commuted if the rotate amount is zero. let Interpretation64Bit = 1, isCodeGenOnly = 1 in -defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA), - (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB, - u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", +defm RLWIMI8 : MForm_2r<20, (outs g8rc:$RA), + (ins g8rc:$RAi, g8rc:$RS, u5imm:$SH, u5imm:$MB, + u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME", IIC_IntRotate, []>, PPC970_DGroup_Cracked, - RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; + RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">; let isSelect = 1 in def ISEL8 : AForm_4<31, 15, - (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), - "isel $rT, $rA, $rB, $cond", IIC_IntISEL, + (outs g8rc:$RT), (ins g8rc_nox0:$RA, g8rc:$RB, crbitrc:$COND), + "isel $RT, $RA, $RB, $COND", IIC_IntISEL, []>; } // Interpretation64Bit } // hasSideEffects = 0 @@ -1245,53 +1245,53 @@ // Sign extending loads. let PPC970_Unit = 2 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in -def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), - "lha $rD, $src", IIC_LdStLHA, - [(set i64:$rD, (sextloadi16 DForm:$src))]>, +def LHA8: DForm_1<42, (outs g8rc:$RST), (ins memri:$addr), + "lha $RST, $addr", IIC_LdStLHA, + [(set i64:$RST, (sextloadi16 DForm:$addr))]>, PPC970_DGroup_Cracked, SExt32To64; -def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), - "lwa $rD, $src", IIC_LdStLWA, - [(set i64:$rD, - (sextloadi32 DSForm:$src))]>, isPPC64, +def LWA : DSForm_1<58, 2, (outs g8rc:$RST), (ins memrix:$addr), + "lwa $RST, $addr", IIC_LdStLWA, + [(set i64:$RST, + (sextloadi32 DSForm:$addr))]>, isPPC64, PPC970_DGroup_Cracked, SExt32To64; let Interpretation64Bit = 1, isCodeGenOnly = 1 in -def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$rD), (ins memrr:$src), - "lhax $rD, $src", IIC_LdStLHA, - [(set i64:$rD, (sextloadi16 XForm:$src))]>, +def LHAX8: XForm_1_memOp<31, 343, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), + "lhax $RST, $addr", IIC_LdStLHA, + [(set i64:$RST, (sextloadi16 XForm:$addr))]>, PPC970_DGroup_Cracked, SExt32To64; -def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$rD), (ins memrr:$src), - "lwax $rD, $src", IIC_LdStLHA, - [(set i64:$rD, (sextloadi32 XForm:$src))]>, isPPC64, +def LWAX : XForm_1_memOp<31, 341, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), + "lwax $RST, $addr", IIC_LdStLHA, + [(set i64:$RST, (sextloadi32 XForm:$addr))]>, isPPC64, PPC970_DGroup_Cracked, SExt32To64; // For fast-isel: let isCodeGenOnly = 1, mayLoad = 1, hasSideEffects = 0 in { -def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), - "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64, +def LWA_32 : DSForm_1<58, 2, (outs gprc:$RST), (ins memrix:$addr), + "lwa $RST, $addr", IIC_LdStLWA, []>, isPPC64, PPC970_DGroup_Cracked, SExt32To64; -def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$rD), (ins memrr:$src), - "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64, +def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lwax $RST, $addr", IIC_LdStLHA, []>, isPPC64, PPC970_DGroup_Cracked, SExt32To64; } // end fast-isel isCodeGenOnly // Update forms. let mayLoad = 1, hasSideEffects = 0 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in -def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), +def LHAU8 : DForm_1<43, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr), - "lhau $rD, $addr", IIC_LdStLHAU, + "lhau $RST, $addr", IIC_LdStLHAU, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; // NO LWAU! let Interpretation64Bit = 1, isCodeGenOnly = 1 in -def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), - (ins memrr:$addr), - "lhaux $rD, $addr", IIC_LdStLHAUX, +def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), + (ins (memrr $RA, $RB):$addr), + "lhaux $RST, $addr", IIC_LdStLHAUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, NoEncode<"$ea_result">; -def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), - (ins memrr:$addr), - "lwaux $rD, $addr", IIC_LdStLHAUX, +def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), + (ins (memrr $RA, $RB):$addr), + "lwaux $RST, $addr", IIC_LdStLHAUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, NoEncode<"$ea_result">, isPPC64; } @@ -1300,64 +1300,64 @@ let Interpretation64Bit = 1, isCodeGenOnly = 1 in { // Zero extending loads. let PPC970_Unit = 2 in { -def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), - "lbz $rD, $src", IIC_LdStLoad, - [(set i64:$rD, (zextloadi8 DForm:$src))]>, ZExt32To64, +def LBZ8 : DForm_1<34, (outs g8rc:$RST), (ins memri:$addr), + "lbz $RST, $addr", IIC_LdStLoad, + [(set i64:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64, SExt32To64; -def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), - "lhz $rD, $src", IIC_LdStLoad, - [(set i64:$rD, (zextloadi16 DForm:$src))]>, ZExt32To64, +def LHZ8 : DForm_1<40, (outs g8rc:$RST), (ins memri:$addr), + "lhz $RST, $addr", IIC_LdStLoad, + [(set i64:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64, SExt32To64; -def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), - "lwz $rD, $src", IIC_LdStLoad, - [(set i64:$rD, (zextloadi32 DForm:$src))]>, isPPC64, +def LWZ8 : DForm_1<32, (outs g8rc:$RST), (ins memri:$addr), + "lwz $RST, $addr", IIC_LdStLoad, + [(set i64:$RST, (zextloadi32 DForm:$addr))]>, isPPC64, ZExt32To64; -def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$rD), (ins memrr:$src), - "lbzx $rD, $src", IIC_LdStLoad, - [(set i64:$rD, (zextloadi8 XForm:$src))]>, ZExt32To64, +def LBZX8 : XForm_1_memOp<31, 87, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), + "lbzx $RST, $addr", IIC_LdStLoad, + [(set i64:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64, SExt32To64; -def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$rD), (ins memrr:$src), - "lhzx $rD, $src", IIC_LdStLoad, - [(set i64:$rD, (zextloadi16 XForm:$src))]>, +def LHZX8 : XForm_1_memOp<31, 279, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), + "lhzx $RST, $addr", IIC_LdStLoad, + [(set i64:$RST, (zextloadi16 XForm:$addr))]>, ZExt32To64, SExt32To64; -def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$rD), (ins memrr:$src), - "lwzx $rD, $src", IIC_LdStLoad, - [(set i64:$rD, (zextloadi32 XForm:$src))]>, +def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), + "lwzx $RST, $addr", IIC_LdStLoad, + [(set i64:$RST, (zextloadi32 XForm:$addr))]>, ZExt32To64; // Update forms. let mayLoad = 1, hasSideEffects = 0 in { -def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), +def LBZU8 : DForm_1<35, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr), - "lbzu $rD, $addr", IIC_LdStLoadUpd, + "lbzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), +def LHZU8 : DForm_1<41, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr), - "lhzu $rD, $addr", IIC_LdStLoadUpd, + "lhzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), +def LWZU8 : DForm_1<33, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr), - "lwzu $rD, $addr", IIC_LdStLoadUpd, + "lwzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), - (ins memrr:$addr), - "lbzux $rD, $addr", IIC_LdStLoadUpdX, +def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), + (ins (memrr $RA, $RB):$addr), + "lbzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, NoEncode<"$ea_result">; -def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), - (ins memrr:$addr), - "lhzux $rD, $addr", IIC_LdStLoadUpdX, +def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), + (ins (memrr $RA, $RB):$addr), + "lhzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, NoEncode<"$ea_result">; -def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), - (ins memrr:$addr), - "lwzux $rD, $addr", IIC_LdStLoadUpdX, +def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), + (ins (memrr $RA, $RB):$addr), + "lwzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, NoEncode<"$ea_result">; } @@ -1367,9 +1367,9 @@ // Full 8-byte loads. let PPC970_Unit = 2 in { -def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), - "ld $rD, $src", IIC_LdStLD, - [(set i64:$rD, (load DSForm:$src))]>, isPPC64; +def LD : DSForm_1<58, 0, (outs g8rc:$RST), (ins memrix:$addr), + "ld $RST, $addr", IIC_LdStLD, + [(set i64:$RST, (load DSForm:$addr))]>, isPPC64; // The following four definitions are selected for small code model only. // Otherwise, we need to create two instructions to form a 32-bit offset, // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). @@ -1390,33 +1390,33 @@ [(set i64:$rD, (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64; -def LDX : XForm_1_memOp<31, 21, (outs g8rc:$rD), (ins memrr:$src), - "ldx $rD, $src", IIC_LdStLD, - [(set i64:$rD, (load XForm:$src))]>, isPPC64; +def LDX : XForm_1_memOp<31, 21, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), + "ldx $RST, $addr", IIC_LdStLD, + [(set i64:$RST, (load XForm:$addr))]>, isPPC64; let Predicates = [IsISA2_06] in { -def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$rD), (ins memrr:$src), - "ldbrx $rD, $src", IIC_LdStLoad, - [(set i64:$rD, (PPClbrx ForceXForm:$src, i64))]>, isPPC64; +def LDBRX : XForm_1_memOp<31, 532, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), + "ldbrx $RST, $addr", IIC_LdStLoad, + [(set i64:$RST, (PPClbrx ForceXForm:$addr, i64))]>, isPPC64; } let mayLoad = 1, hasSideEffects = 0, isCodeGenOnly = 1 in { -def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$rD), (ins memrr:$src), - "lhbrx $rD, $src", IIC_LdStLoad, []>, ZExt32To64; -def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$rD), (ins memrr:$src), - "lwbrx $rD, $src", IIC_LdStLoad, []>, ZExt32To64; +def LHBRX8 : XForm_1_memOp<31, 790, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), + "lhbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64; +def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr), + "lwbrx $RST, $addr", IIC_LdStLoad, []>, ZExt32To64; } let mayLoad = 1, hasSideEffects = 0 in { -def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), +def LDU : DSForm_1<58, 1, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins memrix:$addr), - "ldu $rD, $addr", IIC_LdStLDU, + "ldu $RST, $addr", IIC_LdStLDU, []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, NoEncode<"$ea_result">; -def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), - (ins memrr:$addr), - "ldux $rD, $addr", IIC_LdStLDUX, +def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), + (ins (memrr $RA, $RB):$addr), + "ldux $RST, $addr", IIC_LdStLDUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, NoEncode<"$ea_result">, isPPC64; } @@ -1427,8 +1427,8 @@ // TODO: Add scheduling info. def LQ : DQForm_RTp5_RA17_MEM<56, 0, (outs g8prc:$RTp), - (ins memrix16:$src), - "lq $RTp, $src", IIC_LdStLQ, + (ins memrix16:$addr), + "lq $RTp, $addr", IIC_LdStLQ, []>, RegConstraint<"@earlyclobber $RTp">, isPPC64; @@ -1604,50 +1604,50 @@ let PPC970_Unit = 2 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in { // Truncating stores. -def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), - "stb $rS, $src", IIC_LdStStore, - [(truncstorei8 i64:$rS, DForm:$src)]>; -def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), - "sth $rS, $src", IIC_LdStStore, - [(truncstorei16 i64:$rS, DForm:$src)]>; -def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), - "stw $rS, $src", IIC_LdStStore, - [(truncstorei32 i64:$rS, DForm:$src)]>; -def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), - "stbx $rS, $dst", IIC_LdStStore, - [(truncstorei8 i64:$rS, XForm:$dst)]>, +def STB8 : DForm_1<38, (outs), (ins g8rc:$RST, memri:$addr), + "stb $RST, $addr", IIC_LdStStore, + [(truncstorei8 i64:$RST, DForm:$addr)]>; +def STH8 : DForm_1<44, (outs), (ins g8rc:$RST, memri:$addr), + "sth $RST, $addr", IIC_LdStStore, + [(truncstorei16 i64:$RST, DForm:$addr)]>; +def STW8 : DForm_1<36, (outs), (ins g8rc:$RST, memri:$addr), + "stw $RST, $addr", IIC_LdStStore, + [(truncstorei32 i64:$RST, DForm:$addr)]>; +def STBX8 : XForm_8_memOp<31, 215, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), + "stbx $RST, $addr", IIC_LdStStore, + [(truncstorei8 i64:$RST, XForm:$addr)]>, PPC970_DGroup_Cracked; -def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), - "sthx $rS, $dst", IIC_LdStStore, - [(truncstorei16 i64:$rS, XForm:$dst)]>, +def STHX8 : XForm_8_memOp<31, 407, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), + "sthx $RST, $addr", IIC_LdStStore, + [(truncstorei16 i64:$RST, XForm:$addr)]>, PPC970_DGroup_Cracked; -def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), - "stwx $rS, $dst", IIC_LdStStore, - [(truncstorei32 i64:$rS, XForm:$dst)]>, +def STWX8 : XForm_8_memOp<31, 151, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), + "stwx $RST, $addr", IIC_LdStStore, + [(truncstorei32 i64:$RST, XForm:$addr)]>, PPC970_DGroup_Cracked; } // Interpretation64Bit // Normal 8-byte stores. -def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), - "std $rS, $dst", IIC_LdStSTD, - [(store i64:$rS, DSForm:$dst)]>, isPPC64; -def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), - "stdx $rS, $dst", IIC_LdStSTD, - [(store i64:$rS, XForm:$dst)]>, isPPC64, +def STD : DSForm_1<62, 0, (outs), (ins g8rc:$RST, memrix:$addr), + "std $RST, $addr", IIC_LdStSTD, + [(store i64:$RST, DSForm:$addr)]>, isPPC64; +def STDX : XForm_8_memOp<31, 149, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), + "stdx $RST, $addr", IIC_LdStSTD, + [(store i64:$RST, XForm:$addr)]>, isPPC64, PPC970_DGroup_Cracked; let Predicates = [IsISA2_06] in { -def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), - "stdbrx $rS, $dst", IIC_LdStStore, - [(PPCstbrx i64:$rS, ForceXForm:$dst, i64)]>, isPPC64, +def STDBRX: XForm_8_memOp<31, 660, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr), + "stdbrx $RST, $addr", IIC_LdStStore, + [(PPCstbrx i64:$RST, ForceXForm:$addr, i64)]>, isPPC64, PPC970_DGroup_Cracked; } let mayStore = 1, hasNoSchedulingInfo = 1 in { // Normal 16-byte stores. // TODO: Add scheduling info. -def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RSp, memrix:$dst), - "stq $RSp, $dst", IIC_LdStSTQ, +def STQ : DSForm_1<62, 2, (outs), (ins g8prc:$RST, memrix:$addr), + "stq $RST, $addr", IIC_LdStSTQ, []>, isPPC64; def STQX_PSEUDO : PPCCustomInserterPseudo<(outs), @@ -1674,46 +1674,46 @@ // Stores with Update (pre-inc). let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in { -def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), - "stbu $rS, $dst", IIC_LdStSTU, []>, - RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; -def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), - "sthu $rS, $dst", IIC_LdStSTU, []>, - RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; -def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), - "stwu $rS, $dst", IIC_LdStSTU, []>, - RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; +def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, memri:$addr), + "stbu $RST, $addr", IIC_LdStSTU, []>, + RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">; +def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, memri:$addr), + "sthu $RST, $addr", IIC_LdStSTU, []>, + RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">; +def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, memri:$addr), + "stwu $RST, $addr", IIC_LdStSTU, []>, + RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">; def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), - (ins g8rc:$rS, memrr:$dst), - "stbux $rS, $dst", IIC_LdStSTUX, []>, - RegConstraint<"$dst.ptrreg = $ea_res">, + (ins g8rc:$RST, (memrr $RA, $RB):$addr), + "stbux $RST, $addr", IIC_LdStSTUX, []>, + RegConstraint<"$addr.ptrreg = $ea_res">, NoEncode<"$ea_res">, PPC970_DGroup_Cracked; def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), - (ins g8rc:$rS, memrr:$dst), - "sthux $rS, $dst", IIC_LdStSTUX, []>, - RegConstraint<"$dst.ptrreg = $ea_res">, + (ins g8rc:$RST, (memrr $RA, $RB):$addr), + "sthux $RST, $addr", IIC_LdStSTUX, []>, + RegConstraint<"$addr.ptrreg = $ea_res">, NoEncode<"$ea_res">, PPC970_DGroup_Cracked; def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), - (ins g8rc:$rS, memrr:$dst), - "stwux $rS, $dst", IIC_LdStSTUX, []>, - RegConstraint<"$dst.ptrreg = $ea_res">, + (ins g8rc:$RST, (memrr $RA, $RB):$addr), + "stwux $RST, $addr", IIC_LdStSTUX, []>, + RegConstraint<"$addr.ptrreg = $ea_res">, NoEncode<"$ea_res">, PPC970_DGroup_Cracked; } // Interpretation64Bit def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), - (ins g8rc:$rS, memrix:$dst), - "stdu $rS, $dst", IIC_LdStSTU, []>, - RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, + (ins g8rc:$RST, memrix:$addr), + "stdu $RST, $addr", IIC_LdStSTU, []>, + RegConstraint<"$addr.reg = $ea_res">, NoEncode<"$ea_res">, isPPC64; def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), - (ins g8rc:$rS, memrr:$dst), - "stdux $rS, $dst", IIC_LdStSTUX, []>, - RegConstraint<"$dst.ptrreg = $ea_res">, + (ins g8rc:$RST, (memrr $RA, $RB):$addr), + "stdux $RST, $addr", IIC_LdStSTUX, []>, + RegConstraint<"$addr.ptrreg = $ea_res">, NoEncode<"$ea_res">, PPC970_DGroup_Cracked, isPPC64; } @@ -1747,34 +1747,34 @@ let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [RM] in { // FPU Operations. -defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), - "fcfid", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (PPCany_fcfid f64:$frB))]>, isPPC64; -defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), - "fctid", "$frD, $frB", IIC_FPGeneral, +defm FCFID : XForm_26r<63, 846, (outs f8rc:$RST), (ins f8rc:$RB), + "fcfid", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (PPCany_fcfid f64:$RB))]>, isPPC64; +defm FCTID : XForm_26r<63, 814, (outs f8rc:$RST), (ins f8rc:$RB), + "fctid", "$RST, $RB", IIC_FPGeneral, []>, isPPC64; -defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB), - "fctidu", "$frD, $frB", IIC_FPGeneral, +defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$RST), (ins f8rc:$RB), + "fctidu", "$RST, $RB", IIC_FPGeneral, []>, isPPC64; -defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), - "fctidz", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (PPCany_fctidz f64:$frB))]>, isPPC64; - -defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), - "fcfidu", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (PPCany_fcfidu f64:$frB))]>, isPPC64; -defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), - "fcfids", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (PPCany_fcfids f64:$frB))]>, isPPC64; -defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), - "fcfidus", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (PPCany_fcfidus f64:$frB))]>, isPPC64; -defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), - "fctiduz", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (PPCany_fctiduz f64:$frB))]>, isPPC64; -defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), - "fctiwuz", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (PPCany_fctiwuz f64:$frB))]>, isPPC64; +defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$RST), (ins f8rc:$RB), + "fctidz", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (PPCany_fctidz f64:$RB))]>, isPPC64; + +defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$RST), (ins f8rc:$RB), + "fcfidu", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (PPCany_fcfidu f64:$RB))]>, isPPC64; +defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$RST), (ins f8rc:$RB), + "fcfids", "$RST, $RB", IIC_FPGeneral, + [(set f32:$RST, (PPCany_fcfids f64:$RB))]>, isPPC64; +defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$RST), (ins f8rc:$RB), + "fcfidus", "$RST, $RB", IIC_FPGeneral, + [(set f32:$RST, (PPCany_fcfidus f64:$RB))]>, isPPC64; +defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$RST), (ins f8rc:$RB), + "fctiduz", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (PPCany_fctiduz f64:$RB))]>, isPPC64; +defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$RST), (ins f8rc:$RB), + "fctiwuz", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (PPCany_fctiwuz f64:$RB))]>, isPPC64; } // These instructions store a hash computed from the value of the link register @@ -1803,10 +1803,10 @@ } let Interpretation64Bit = 1, isCodeGenOnly = 1, hasSideEffects = 1 in -def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$rT), - (ins g8rc:$rA, g8rc:$rB, u2imm:$CY), - "addex $rT, $rA, $rB, $CY", IIC_IntGeneral, - [(set i64:$rT, (int_ppc_addex i64:$rA, i64:$rB, +def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$RT), + (ins g8rc:$RA, g8rc:$RB, u2imm:$CY), + "addex $RT, $RA, $RB, $CY", IIC_IntGeneral, + [(set i64:$RT, (int_ppc_addex i64:$RA, i64:$RB, timm:$CY))]>; //===----------------------------------------------------------------------===// @@ -1947,15 +1947,15 @@ class X_RA5_RB5 opcode, bits<10> xo, string opc, RegisterOperand ty, InstrItinClass itin, list pattern> - : X_L1_RS5_RS5{ + : X_L1_RS5_RS5{ let L = 1; } class X_L1_RA5_RB5 opcode, bits<10> xo, string opc, RegisterOperand ty, InstrItinClass itin, list pattern> - : X_L1_RS5_RS5; + : X_L1_RS5_RS5; let Interpretation64Bit = 1, isCodeGenOnly = 1 in { def CP_COPY8 : X_RA5_RB5<31, 774, "copy" , g8rc, IIC_LdStCOPY, []>; @@ -1963,8 +1963,8 @@ } // SLB Invalidate Entry Global -def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB), - "slbieg $RS, $RB", IIC_SprSLBIEG, []>; +def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RST, gprc:$RB), + "slbieg $RST, $RB", IIC_SprSLBIEG, []>; // SLB Synchronize def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>; diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -266,72 +266,72 @@ // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. class VA1a_Int_Ty xo, string opc, Intrinsic IntID, ValueType Ty> - : VAForm_1a; + : VAForm_1a; // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the // inputs doesn't match the type of the output. class VA1a_Int_Ty2 xo, string opc, Intrinsic IntID, ValueType OutTy, ValueType InTy> - : VAForm_1a; + : VAForm_1a; // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two // input types and an output type. class VA1a_Int_Ty3 xo, string opc, Intrinsic IntID, ValueType OutTy, ValueType In1Ty, ValueType In2Ty> - : VAForm_1a; + : VAForm_1a; // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. class VX1_Int_Ty xo, string opc, Intrinsic IntID, ValueType Ty> - : VXForm_1; + : VXForm_1; // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the // inputs doesn't match the type of the output. class VX1_Int_Ty2 xo, string opc, Intrinsic IntID, ValueType OutTy, ValueType InTy> - : VXForm_1; + : VXForm_1; // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two // input types and an output type. class VX1_Int_Ty3 xo, string opc, Intrinsic IntID, ValueType OutTy, ValueType In1Ty, ValueType In2Ty> - : VXForm_1; + : VXForm_1; // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. class VX2_Int_SP xo, string opc, Intrinsic IntID> - : VXForm_2; + : VXForm_2; // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the // inputs doesn't match the type of the output. class VX2_Int_Ty2 xo, string opc, Intrinsic IntID, ValueType OutTy, ValueType InTy> - : VXForm_2; + : VXForm_2; class VXBX_Int_Ty xo, string opc, Intrinsic IntID, ValueType Ty> - : VXForm_BX; + : VXForm_BX; class VXCR_Int_Ty xo, string opc, Intrinsic IntID, ValueType Ty> - : VXForm_CR; + : VXForm_CR; //===----------------------------------------------------------------------===// // Instruction Definitions. @@ -342,130 +342,130 @@ def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM), "dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>, Deprecated { - let A = 0; - let B = 0; + let RA = 0; + let RB = 0; } def DSSALL : DSS_Form<1, 822, (outs), (ins), "dssall", IIC_LdStLoad /*FIXME*/, []>, Deprecated { let STRM = 0; - let A = 0; - let B = 0; + let RA = 0; + let RB = 0; } -def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), - "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, - [(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>, +def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$RA, gprc:$RB), + "dst $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dst i32:$RA, i32:$RB, imm:$STRM)]>, Deprecated; -def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), - "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, - [(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>, +def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$RA, gprc:$RB), + "dstt $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dstt i32:$RA, i32:$RB, imm:$STRM)]>, Deprecated; -def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), - "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, - [(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>, +def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$RA, gprc:$RB), + "dstst $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dstst i32:$RA, i32:$RB, imm:$STRM)]>, Deprecated; -def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB), - "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, - [(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>, +def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$RA, gprc:$RB), + "dststt $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dststt i32:$RA, i32:$RB, imm:$STRM)]>, Deprecated; let isCodeGenOnly = 1 in { // The very same instructions as above, but formally matching 64bit registers. - def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), - "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, - [(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>, + def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$RA, gprc:$RB), + "dst $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dst i64:$RA, i32:$RB, imm:$STRM)]>, Deprecated; - def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), - "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, - [(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>, + def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$RA, gprc:$RB), + "dstt $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dstt i64:$RA, i32:$RB, imm:$STRM)]>, Deprecated; - def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), - "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, - [(int_ppc_altivec_dstst i64:$rA, i32:$rB, + def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$RA, gprc:$RB), + "dstst $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dstst i64:$RA, i32:$RB, imm:$STRM)]>, Deprecated; - def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB), - "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, - [(int_ppc_altivec_dststt i64:$rA, i32:$rB, + def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$RA, gprc:$RB), + "dststt $RA, $RB, $STRM", IIC_LdStLoad /*FIXME*/, + [(int_ppc_altivec_dststt i64:$RA, i32:$RB, imm:$STRM)]>, Deprecated; } let hasSideEffects = 1 in { - def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), - "mfvscr $vD", IIC_LdStStore, - [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; - def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), - "mtvscr $vB", IIC_LdStLoad, - [(int_ppc_altivec_mtvscr v4i32:$vB)]>; + def MFVSCR : VXForm_4<1540, (outs vrrc:$VD), (ins), + "mfvscr $VD", IIC_LdStStore, + [(set v8i16:$VD, (int_ppc_altivec_mfvscr))]>; + def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$VB), + "mtvscr $VB", IIC_LdStLoad, + [(int_ppc_altivec_mtvscr v4i32:$VB)]>; } let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { // Loads. -def LVEBX: XForm_1_memOp<31, 7, (outs vrrc:$vD), (ins memrr:$src), - "lvebx $vD, $src", IIC_LdStLoad, - [(set v16i8:$vD, (int_ppc_altivec_lvebx ForceXForm:$src))]>; -def LVEHX: XForm_1_memOp<31, 39, (outs vrrc:$vD), (ins memrr:$src), - "lvehx $vD, $src", IIC_LdStLoad, - [(set v8i16:$vD, (int_ppc_altivec_lvehx ForceXForm:$src))]>; -def LVEWX: XForm_1_memOp<31, 71, (outs vrrc:$vD), (ins memrr:$src), - "lvewx $vD, $src", IIC_LdStLoad, - [(set v4i32:$vD, (int_ppc_altivec_lvewx ForceXForm:$src))]>; -def LVX : XForm_1_memOp<31, 103, (outs vrrc:$vD), (ins memrr:$src), - "lvx $vD, $src", IIC_LdStLoad, - [(set v4i32:$vD, (int_ppc_altivec_lvx ForceXForm:$src))]>; -def LVXL : XForm_1_memOp<31, 359, (outs vrrc:$vD), (ins memrr:$src), - "lvxl $vD, $src", IIC_LdStLoad, - [(set v4i32:$vD, (int_ppc_altivec_lvxl ForceXForm:$src))]>; +def LVEBX: XForm_1_memOp<31, 7, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr), + "lvebx $RST, $addr", IIC_LdStLoad, + [(set v16i8:$RST, (int_ppc_altivec_lvebx ForceXForm:$addr))]>; +def LVEHX: XForm_1_memOp<31, 39, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr), + "lvehx $RST, $addr", IIC_LdStLoad, + [(set v8i16:$RST, (int_ppc_altivec_lvehx ForceXForm:$addr))]>; +def LVEWX: XForm_1_memOp<31, 71, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr), + "lvewx $RST, $addr", IIC_LdStLoad, + [(set v4i32:$RST, (int_ppc_altivec_lvewx ForceXForm:$addr))]>; +def LVX : XForm_1_memOp<31, 103, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr), + "lvx $RST, $addr", IIC_LdStLoad, + [(set v4i32:$RST, (int_ppc_altivec_lvx ForceXForm:$addr))]>; +def LVXL : XForm_1_memOp<31, 359, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr), + "lvxl $RST, $addr", IIC_LdStLoad, + [(set v4i32:$RST, (int_ppc_altivec_lvxl ForceXForm:$addr))]>; } -def LVSL : XForm_1_memOp<31, 6, (outs vrrc:$vD), (ins memrr:$src), - "lvsl $vD, $src", IIC_LdStLoad, - [(set v16i8:$vD, (int_ppc_altivec_lvsl ForceXForm:$src))]>, +def LVSL : XForm_1_memOp<31, 6, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr), + "lvsl $RST, $addr", IIC_LdStLoad, + [(set v16i8:$RST, (int_ppc_altivec_lvsl ForceXForm:$addr))]>, PPC970_Unit_LSU; -def LVSR : XForm_1_memOp<31, 38, (outs vrrc:$vD), (ins memrr:$src), - "lvsr $vD, $src", IIC_LdStLoad, - [(set v16i8:$vD, (int_ppc_altivec_lvsr ForceXForm:$src))]>, +def LVSR : XForm_1_memOp<31, 38, (outs vrrc:$RST), (ins (memrr $RA, $RB):$addr), + "lvsr $RST, $addr", IIC_LdStLoad, + [(set v16i8:$RST, (int_ppc_altivec_lvsr ForceXForm:$addr))]>, PPC970_Unit_LSU; let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { // Stores. -def STVEBX: XForm_8_memOp<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), - "stvebx $rS, $dst", IIC_LdStStore, - [(int_ppc_altivec_stvebx v16i8:$rS, ForceXForm:$dst)]>; -def STVEHX: XForm_8_memOp<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), - "stvehx $rS, $dst", IIC_LdStStore, - [(int_ppc_altivec_stvehx v8i16:$rS, ForceXForm:$dst)]>; -def STVEWX: XForm_8_memOp<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), - "stvewx $rS, $dst", IIC_LdStStore, - [(int_ppc_altivec_stvewx v4i32:$rS, ForceXForm:$dst)]>; -def STVX : XForm_8_memOp<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), - "stvx $rS, $dst", IIC_LdStStore, - [(int_ppc_altivec_stvx v4i32:$rS, ForceXForm:$dst)]>; -def STVXL : XForm_8_memOp<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), - "stvxl $rS, $dst", IIC_LdStStore, - [(int_ppc_altivec_stvxl v4i32:$rS, ForceXForm:$dst)]>; +def STVEBX: XForm_8_memOp<31, 135, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr), + "stvebx $RST, $addr", IIC_LdStStore, + [(int_ppc_altivec_stvebx v16i8:$RST, ForceXForm:$addr)]>; +def STVEHX: XForm_8_memOp<31, 167, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr), + "stvehx $RST, $addr", IIC_LdStStore, + [(int_ppc_altivec_stvehx v8i16:$RST, ForceXForm:$addr)]>; +def STVEWX: XForm_8_memOp<31, 199, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr), + "stvewx $RST, $addr", IIC_LdStStore, + [(int_ppc_altivec_stvewx v4i32:$RST, ForceXForm:$addr)]>; +def STVX : XForm_8_memOp<31, 231, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr), + "stvx $RST, $addr", IIC_LdStStore, + [(int_ppc_altivec_stvx v4i32:$RST, ForceXForm:$addr)]>; +def STVXL : XForm_8_memOp<31, 487, (outs), (ins vrrc:$RST, (memrr $RA, $RB):$addr), + "stvxl $RST, $addr", IIC_LdStStore, + [(int_ppc_altivec_stvxl v4i32:$RST, ForceXForm:$addr)]>; } let PPC970_Unit = 5 in { // VALU Operations. // VA-Form instructions. 3-input AltiVec ops. let isCommutable = 1 in { -def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), - "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP, - [(set v4f32:$vD, - (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; +def VMADDFP : VAForm_1<46, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RC, vrrc:$RB), + "vmaddfp $RT, $RA, $RC, $RB", IIC_VecFP, + [(set v4f32:$RT, + (fma v4f32:$RA, v4f32:$RC, v4f32:$RB))]>; // FIXME: The fma+fneg pattern won't match because fneg is not legal. -def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), - "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP, - [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, - (fneg v4f32:$vB))))]>; +def VNMSUBFP: VAForm_1<47, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RC, vrrc:$RB), + "vnmsubfp $RT, $RA, $RC, $RB", IIC_VecFP, + [(set v4f32:$RT, (fneg (fma v4f32:$RA, v4f32:$RC, + (fneg v4f32:$RB))))]>; let hasSideEffects = 1 in { def VMHADDSHS : VA1a_Int_Ty<32, "vmhaddshs", int_ppc_altivec_vmhaddshs, v8i16>; def VMHRADDSHS : VA1a_Int_Ty<33, "vmhraddshs", int_ppc_altivec_vmhraddshs, @@ -479,26 +479,26 @@ def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>; // Shuffles. -def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u4imm:$SH), - "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP, - [(set v16i8:$vD, - (PPCvecshl v16i8:$vA, v16i8:$vB, imm32SExt16:$SH))]>; +def VSLDOI : VAForm_2<44, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, u4imm:$SH), + "vsldoi $RT, $RA, $RB, $SH", IIC_VecFP, + [(set v16i8:$RT, + (PPCvecshl v16i8:$RA, v16i8:$RB, imm32SExt16:$SH))]>; // VX-Form instructions. AltiVec arithmetic ops. let isCommutable = 1 in { -def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vaddfp $vD, $vA, $vB", IIC_VecFP, - [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; - -def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vaddubm $vD, $vA, $vB", IIC_VecGeneral, - [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; -def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vadduhm $vD, $vA, $vB", IIC_VecGeneral, - [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; -def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vadduwm $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; +def VADDFP : VXForm_1<10, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vaddfp $VD, $VA, $VB", IIC_VecFP, + [(set v4f32:$VD, (fadd v4f32:$VA, v4f32:$VB))]>; + +def VADDUBM : VXForm_1<0, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vaddubm $VD, $VA, $VB", IIC_VecGeneral, + [(set v16i8:$VD, (add v16i8:$VA, v16i8:$VB))]>; +def VADDUHM : VXForm_1<64, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vadduhm $VD, $VA, $VB", IIC_VecGeneral, + [(set v8i16:$VD, (add v8i16:$VA, v8i16:$VB))]>; +def VADDUWM : VXForm_1<128, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vadduwm $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (add v4i32:$VA, v4i32:$VB))]>; def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; def VADDSBS : VX1_Int_Ty<768, "vaddsbs", int_ppc_altivec_vaddsbs, v16i8>; @@ -510,51 +510,51 @@ } // isCommutable let isCommutable = 1 in -def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vand $vD, $vA, $vB", IIC_VecFP, - [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; -def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vandc $vD, $vA, $vB", IIC_VecFP, - [(set v4i32:$vD, (and v4i32:$vA, - (vnot v4i32:$vB)))]>; - -def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), - "vcfsx $vD, $vB, $UIMM", IIC_VecFP, - [(set v4f32:$vD, - (int_ppc_altivec_vcfsx v4i32:$vB, timm:$UIMM))]>; -def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), - "vcfux $vD, $vB, $UIMM", IIC_VecFP, - [(set v4f32:$vD, - (int_ppc_altivec_vcfux v4i32:$vB, timm:$UIMM))]>; -def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), - "vctsxs $vD, $vB, $UIMM", IIC_VecFP, - [(set v4i32:$vD, - (int_ppc_altivec_vctsxs v4f32:$vB, timm:$UIMM))]>; -def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), - "vctuxs $vD, $vB, $UIMM", IIC_VecFP, - [(set v4i32:$vD, - (int_ppc_altivec_vctuxs v4f32:$vB, timm:$UIMM))]>; +def VAND : VXForm_1<1028, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vand $VD, $VA, $VB", IIC_VecFP, + [(set v4i32:$VD, (and v4i32:$VA, v4i32:$VB))]>; +def VANDC : VXForm_1<1092, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vandc $VD, $VA, $VB", IIC_VecFP, + [(set v4i32:$VD, (and v4i32:$VA, + (vnot v4i32:$VB)))]>; + +def VCFSX : VXForm_1<842, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB), + "vcfsx $VD, $VB, $VA", IIC_VecFP, + [(set v4f32:$VD, + (int_ppc_altivec_vcfsx v4i32:$VB, timm:$VA))]>; +def VCFUX : VXForm_1<778, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB), + "vcfux $VD, $VB, $VA", IIC_VecFP, + [(set v4f32:$VD, + (int_ppc_altivec_vcfux v4i32:$VB, timm:$VA))]>; +def VCTSXS : VXForm_1<970, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB), + "vctsxs $VD, $VB, $VA", IIC_VecFP, + [(set v4i32:$VD, + (int_ppc_altivec_vctsxs v4f32:$VB, timm:$VA))]>; +def VCTUXS : VXForm_1<906, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB), + "vctuxs $VD, $VB, $VA", IIC_VecFP, + [(set v4i32:$VD, + (int_ppc_altivec_vctuxs v4f32:$VB, timm:$VA))]>; // Defines with the UIM field set to 0 for floating-point // to integer (fp_to_sint/fp_to_uint) conversions and integer // to floating-point (sint_to_fp/uint_to_fp) conversions. let isCodeGenOnly = 1, VA = 0 in { -def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), - "vcfsx $vD, $vB, 0", IIC_VecFP, - [(set v4f32:$vD, - (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; -def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), - "vctuxs $vD, $vB, 0", IIC_VecFP, - [(set v4i32:$vD, - (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; -def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), - "vcfux $vD, $vB, 0", IIC_VecFP, - [(set v4f32:$vD, - (int_ppc_altivec_vcfux v4i32:$vB, 0))]>; -def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), - "vctsxs $vD, $vB, 0", IIC_VecFP, - [(set v4i32:$vD, - (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; +def VCFSX_0 : VXForm_1<842, (outs vrrc:$VD), (ins vrrc:$VB), + "vcfsx $VD, $VB, 0", IIC_VecFP, + [(set v4f32:$VD, + (int_ppc_altivec_vcfsx v4i32:$VB, 0))]>; +def VCTUXS_0 : VXForm_1<906, (outs vrrc:$VD), (ins vrrc:$VB), + "vctuxs $VD, $VB, 0", IIC_VecFP, + [(set v4i32:$VD, + (int_ppc_altivec_vctuxs v4f32:$VB, 0))]>; +def VCFUX_0 : VXForm_1<778, (outs vrrc:$VD), (ins vrrc:$VB), + "vcfux $VD, $VB, 0", IIC_VecFP, + [(set v4f32:$VD, + (int_ppc_altivec_vcfux v4i32:$VB, 0))]>; +def VCTSXS_0 : VXForm_1<970, (outs vrrc:$VD), (ins vrrc:$VB), + "vctsxs $VD, $VB, 0", IIC_VecFP, + [(set v4i32:$VD, + (int_ppc_altivec_vctsxs v4f32:$VB, 0))]>; } def VEXPTEFP : VX2_Int_SP<394, "vexptefp", int_ppc_altivec_vexptefp>; def VLOGEFP : VX2_Int_SP<458, "vlogefp", int_ppc_altivec_vlogefp>; @@ -583,24 +583,24 @@ def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; } // isCommutable -def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmrghb $vD, $vA, $vB", IIC_VecFP, - [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; -def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmrghh $vD, $vA, $vB", IIC_VecFP, - [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; -def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmrghw $vD, $vA, $vB", IIC_VecFP, - [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; -def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmrglb $vD, $vA, $vB", IIC_VecFP, - [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; -def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmrglh $vD, $vA, $vB", IIC_VecFP, - [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; -def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmrglw $vD, $vA, $vB", IIC_VecFP, - [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; +def VMRGHB : VXForm_1< 12, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmrghb $VD, $VA, $VB", IIC_VecFP, + [(set v16i8:$VD, (vmrghb_shuffle v16i8:$VA, v16i8:$VB))]>; +def VMRGHH : VXForm_1< 76, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmrghh $VD, $VA, $VB", IIC_VecFP, + [(set v16i8:$VD, (vmrghh_shuffle v16i8:$VA, v16i8:$VB))]>; +def VMRGHW : VXForm_1<140, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmrghw $VD, $VA, $VB", IIC_VecFP, + [(set v16i8:$VD, (vmrghw_shuffle v16i8:$VA, v16i8:$VB))]>; +def VMRGLB : VXForm_1<268, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmrglb $VD, $VA, $VB", IIC_VecFP, + [(set v16i8:$VD, (vmrglb_shuffle v16i8:$VA, v16i8:$VB))]>; +def VMRGLH : VXForm_1<332, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmrglh $VD, $VA, $VB", IIC_VecFP, + [(set v16i8:$VD, (vmrglh_shuffle v16i8:$VA, v16i8:$VB))]>; +def VMRGLW : VXForm_1<396, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmrglw $VD, $VA, $VB", IIC_VecFP, + [(set v16i8:$VD, (vmrglw_shuffle v16i8:$VA, v16i8:$VB))]>; def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, v4i32, v16i8, v4i32>; @@ -645,18 +645,18 @@ def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; -def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vsubfp $vD, $vA, $vB", IIC_VecGeneral, - [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; -def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vsububm $vD, $vA, $vB", IIC_VecGeneral, - [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; -def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vsubuhm $vD, $vA, $vB", IIC_VecGeneral, - [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; -def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vsubuwm $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; +def VSUBFP : VXForm_1<74, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vsubfp $VD, $VA, $VB", IIC_VecGeneral, + [(set v4f32:$VD, (fsub v4f32:$VA, v4f32:$VB))]>; +def VSUBUBM : VXForm_1<1024, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vsububm $VD, $VA, $VB", IIC_VecGeneral, + [(set v16i8:$VD, (sub v16i8:$VA, v16i8:$VB))]>; +def VSUBUHM : VXForm_1<1088, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vsubuhm $VD, $VA, $VB", IIC_VecGeneral, + [(set v8i16:$VD, (sub v8i16:$VA, v8i16:$VB))]>; +def VSUBUWM : VXForm_1<1152, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vsubuwm $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (sub v4i32:$VA, v4i32:$VB))]>; def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; def VSUBSHS : VX1_Int_Ty<1856, "vsubshs" , int_ppc_altivec_vsubshs, v8i16>; @@ -677,17 +677,17 @@ v4i32, v16i8, v4i32>; } -def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vnor $vD, $vA, $vB", IIC_VecFP, - [(set v4i32:$vD, (vnot (or v4i32:$vA, - v4i32:$vB)))]>; +def VNOR : VXForm_1<1284, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vnor $VD, $VA, $VB", IIC_VecFP, + [(set v4i32:$VD, (vnot (or v4i32:$VA, + v4i32:$VB)))]>; let isCommutable = 1 in { -def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vor $vD, $vA, $vB", IIC_VecFP, - [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; -def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vxor $vD, $vA, $vB", IIC_VecFP, - [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; +def VOR : VXForm_1<1156, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vor $VD, $VA, $VB", IIC_VecFP, + [(set v4i32:$VD, (or v4i32:$VA, v4i32:$VB))]>; +def VXOR : VXForm_1<1220, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vxor $VD, $VA, $VB", IIC_VecFP, + [(set v4i32:$VD, (xor v4i32:$VA, v4i32:$VB))]>; } // isCommutable def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; @@ -701,23 +701,23 @@ def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>; def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; -def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), - "vspltb $vD, $vB, $UIMM", IIC_VecPerm, - [(set v16i8:$vD, - (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; -def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), - "vsplth $vD, $vB, $UIMM", IIC_VecPerm, - [(set v16i8:$vD, - (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; -def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), - "vspltw $vD, $vB, $UIMM", IIC_VecPerm, - [(set v16i8:$vD, - (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; +def VSPLTB : VXForm_1<524, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB), + "vspltb $VD, $VB, $VA", IIC_VecPerm, + [(set v16i8:$VD, + (vspltb_shuffle:$VA v16i8:$VB, (undef)))]>; +def VSPLTH : VXForm_1<588, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB), + "vsplth $VD, $VB, $VA", IIC_VecPerm, + [(set v16i8:$VD, + (vsplth_shuffle:$VA v16i8:$VB, (undef)))]>; +def VSPLTW : VXForm_1<652, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB), + "vspltw $VD, $VB, $VA", IIC_VecPerm, + [(set v16i8:$VD, + (vspltw_shuffle:$VA v16i8:$VB, (undef)))]>; let isCodeGenOnly = 1, hasSideEffects = 0 in { - def VSPLTBs : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), - "vspltb $vD, $vB, $UIMM", IIC_VecPerm, []>; - def VSPLTHs : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vfrc:$vB), - "vsplth $vD, $vB, $UIMM", IIC_VecPerm, []>; + def VSPLTBs : VXForm_1<524, (outs vrrc:$VD), (ins u5imm:$VA, vfrc:$VB), + "vspltb $VD, $VB, $VA", IIC_VecPerm, []>; + def VSPLTHs : VXForm_1<588, (outs vrrc:$VD), (ins u5imm:$VA, vfrc:$VB), + "vsplth $VD, $VB, $VA", IIC_VecPerm, []>; } def VSR : VX1_Int_Ty< 708, "vsr" , int_ppc_altivec_vsr, v4i32>; @@ -731,15 +731,15 @@ def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>; -def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), - "vspltisb $vD, $SIMM", IIC_VecPerm, - [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; -def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), - "vspltish $vD, $SIMM", IIC_VecPerm, - [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; -def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), - "vspltisw $vD, $SIMM", IIC_VecPerm, - [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; +def VSPLTISB : VXForm_3<780, (outs vrrc:$VD), (ins s5imm:$IMM), + "vspltisb $VD, $IMM", IIC_VecPerm, + [(set v16i8:$VD, (v16i8 vecspltisb:$IMM))]>; +def VSPLTISH : VXForm_3<844, (outs vrrc:$VD), (ins s5imm:$IMM), + "vspltish $VD, $IMM", IIC_VecPerm, + [(set v8i16:$VD, (v8i16 vecspltish:$IMM))]>; +def VSPLTISW : VXForm_3<908, (outs vrrc:$VD), (ins s5imm:$IMM), + "vspltisw $VD, $IMM", IIC_VecPerm, + [(set v4i32:$VD, (v4i32 vecspltisw:$IMM))]>; // Vector Pack. def VPKPX : VX1_Int_Ty2<782, "vpkpx", int_ppc_altivec_vpkpx, @@ -758,14 +758,14 @@ def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, v8i16, v4i32>; } -def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vpkuhum $vD, $vA, $vB", IIC_VecFP, - [(set v16i8:$vD, - (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; -def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vpkuwum $vD, $vA, $vB", IIC_VecFP, - [(set v16i8:$vD, - (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; +def VPKUHUM : VXForm_1<14, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vpkuhum $VD, $VA, $VB", IIC_VecFP, + [(set v16i8:$VD, + (vpkuhum_shuffle v16i8:$VA, v16i8:$VB))]>; +def VPKUWUM : VXForm_1<78, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vpkuwum $VD, $VA, $VB", IIC_VecFP, + [(set v16i8:$VD, + (vpkuwum_shuffle v16i8:$VA, v16i8:$VB))]>; // Vector Unpack. def VUPKHPX : VX2_Int_Ty2<846, "vupkhpx", int_ppc_altivec_vupkhpx, @@ -785,74 +785,74 @@ // Altivec Comparisons. class VCMP xo, string asmstr, ValueType Ty> - : VXRForm_1; + [(set Ty:$VD, (Ty (PPCvcmp Ty:$VA, Ty:$VB, xo)))]>; class VCMP_rec xo, string asmstr, ValueType Ty> - : VXRForm_1 { + [(set Ty:$VD, (Ty (PPCvcmp_rec Ty:$VA, Ty:$VB, xo)))]> { let Defs = [CR6]; let RC = 1; } // f32 element comparisons.0 -def VCMPBFP : VCMP <966, "vcmpbfp $vD, $vA, $vB" , v4f32>; -def VCMPBFP_rec : VCMP_rec<966, "vcmpbfp. $vD, $vA, $vB" , v4f32>; -def VCMPEQFP : VCMP <198, "vcmpeqfp $vD, $vA, $vB" , v4f32>; -def VCMPEQFP_rec : VCMP_rec<198, "vcmpeqfp. $vD, $vA, $vB", v4f32>; -def VCMPGEFP : VCMP <454, "vcmpgefp $vD, $vA, $vB" , v4f32>; -def VCMPGEFP_rec : VCMP_rec<454, "vcmpgefp. $vD, $vA, $vB", v4f32>; -def VCMPGTFP : VCMP <710, "vcmpgtfp $vD, $vA, $vB" , v4f32>; -def VCMPGTFP_rec : VCMP_rec<710, "vcmpgtfp. $vD, $vA, $vB", v4f32>; +def VCMPBFP : VCMP <966, "vcmpbfp $VD, $VA, $VB" , v4f32>; +def VCMPBFP_rec : VCMP_rec<966, "vcmpbfp. $VD, $VA, $VB" , v4f32>; +def VCMPEQFP : VCMP <198, "vcmpeqfp $VD, $VA, $VB" , v4f32>; +def VCMPEQFP_rec : VCMP_rec<198, "vcmpeqfp. $VD, $VA, $VB", v4f32>; +def VCMPGEFP : VCMP <454, "vcmpgefp $VD, $VA, $VB" , v4f32>; +def VCMPGEFP_rec : VCMP_rec<454, "vcmpgefp. $VD, $VA, $VB", v4f32>; +def VCMPGTFP : VCMP <710, "vcmpgtfp $VD, $VA, $VB" , v4f32>; +def VCMPGTFP_rec : VCMP_rec<710, "vcmpgtfp. $VD, $VA, $VB", v4f32>; // i8 element comparisons. -def VCMPEQUB : VCMP < 6, "vcmpequb $vD, $vA, $vB" , v16i8>; -def VCMPEQUB_rec : VCMP_rec< 6, "vcmpequb. $vD, $vA, $vB", v16i8>; -def VCMPGTSB : VCMP <774, "vcmpgtsb $vD, $vA, $vB" , v16i8>; -def VCMPGTSB_rec : VCMP_rec<774, "vcmpgtsb. $vD, $vA, $vB", v16i8>; -def VCMPGTUB : VCMP <518, "vcmpgtub $vD, $vA, $vB" , v16i8>; -def VCMPGTUB_rec : VCMP_rec<518, "vcmpgtub. $vD, $vA, $vB", v16i8>; +def VCMPEQUB : VCMP < 6, "vcmpequb $VD, $VA, $VB" , v16i8>; +def VCMPEQUB_rec : VCMP_rec< 6, "vcmpequb. $VD, $VA, $VB", v16i8>; +def VCMPGTSB : VCMP <774, "vcmpgtsb $VD, $VA, $VB" , v16i8>; +def VCMPGTSB_rec : VCMP_rec<774, "vcmpgtsb. $VD, $VA, $VB", v16i8>; +def VCMPGTUB : VCMP <518, "vcmpgtub $VD, $VA, $VB" , v16i8>; +def VCMPGTUB_rec : VCMP_rec<518, "vcmpgtub. $VD, $VA, $VB", v16i8>; // i16 element comparisons. -def VCMPEQUH : VCMP < 70, "vcmpequh $vD, $vA, $vB" , v8i16>; -def VCMPEQUH_rec : VCMP_rec< 70, "vcmpequh. $vD, $vA, $vB", v8i16>; -def VCMPGTSH : VCMP <838, "vcmpgtsh $vD, $vA, $vB" , v8i16>; -def VCMPGTSH_rec : VCMP_rec<838, "vcmpgtsh. $vD, $vA, $vB", v8i16>; -def VCMPGTUH : VCMP <582, "vcmpgtuh $vD, $vA, $vB" , v8i16>; -def VCMPGTUH_rec : VCMP_rec<582, "vcmpgtuh. $vD, $vA, $vB", v8i16>; +def VCMPEQUH : VCMP < 70, "vcmpequh $VD, $VA, $VB" , v8i16>; +def VCMPEQUH_rec : VCMP_rec< 70, "vcmpequh. $VD, $VA, $VB", v8i16>; +def VCMPGTSH : VCMP <838, "vcmpgtsh $VD, $VA, $VB" , v8i16>; +def VCMPGTSH_rec : VCMP_rec<838, "vcmpgtsh. $VD, $VA, $VB", v8i16>; +def VCMPGTUH : VCMP <582, "vcmpgtuh $VD, $VA, $VB" , v8i16>; +def VCMPGTUH_rec : VCMP_rec<582, "vcmpgtuh. $VD, $VA, $VB", v8i16>; // i32 element comparisons. -def VCMPEQUW : VCMP <134, "vcmpequw $vD, $vA, $vB" , v4i32>; -def VCMPEQUW_rec : VCMP_rec<134, "vcmpequw. $vD, $vA, $vB", v4i32>; -def VCMPGTSW : VCMP <902, "vcmpgtsw $vD, $vA, $vB" , v4i32>; -def VCMPGTSW_rec : VCMP_rec<902, "vcmpgtsw. $vD, $vA, $vB", v4i32>; -def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>; -def VCMPGTUW_rec : VCMP_rec<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>; +def VCMPEQUW : VCMP <134, "vcmpequw $VD, $VA, $VB" , v4i32>; +def VCMPEQUW_rec : VCMP_rec<134, "vcmpequw. $VD, $VA, $VB", v4i32>; +def VCMPGTSW : VCMP <902, "vcmpgtsw $VD, $VA, $VB" , v4i32>; +def VCMPGTSW_rec : VCMP_rec<902, "vcmpgtsw. $VD, $VA, $VB", v4i32>; +def VCMPGTUW : VCMP <646, "vcmpgtuw $VD, $VA, $VB" , v4i32>; +def VCMPGTUW_rec : VCMP_rec<646, "vcmpgtuw. $VD, $VA, $VB", v4i32>; let isCodeGenOnly = 1, isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in { -def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), - "vxor $vD, $vD, $vD", IIC_VecFP, - [(set v16i8:$vD, (v16i8 immAllZerosV))]>; -def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), - "vxor $vD, $vD, $vD", IIC_VecFP, - [(set v8i16:$vD, (v8i16 immAllZerosV))]>; -def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), - "vxor $vD, $vD, $vD", IIC_VecFP, - [(set v4i32:$vD, (v4i32 immAllZerosV))]>; +def V_SET0B : VXForm_setzero<1220, (outs vrrc:$VD), (ins), + "vxor $VD, $VD, $VD", IIC_VecFP, + [(set v16i8:$VD, (v16i8 immAllZerosV))]>; +def V_SET0H : VXForm_setzero<1220, (outs vrrc:$VD), (ins), + "vxor $VD, $VD, $VD", IIC_VecFP, + [(set v8i16:$VD, (v8i16 immAllZerosV))]>; +def V_SET0 : VXForm_setzero<1220, (outs vrrc:$VD), (ins), + "vxor $VD, $VD, $VD", IIC_VecFP, + [(set v4i32:$VD, (v4i32 immAllZerosV))]>; let IMM=-1 in { -def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), - "vspltisw $vD, -1", IIC_VecFP, - [(set v16i8:$vD, (v16i8 immAllOnesV))]>; -def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), - "vspltisw $vD, -1", IIC_VecFP, - [(set v8i16:$vD, (v8i16 immAllOnesV))]>; -def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), - "vspltisw $vD, -1", IIC_VecFP, - [(set v4i32:$vD, (v4i32 immAllOnesV))]>; +def V_SETALLONESB : VXForm_3<908, (outs vrrc:$VD), (ins), + "vspltisw $VD, -1", IIC_VecFP, + [(set v16i8:$VD, (v16i8 immAllOnesV))]>; +def V_SETALLONESH : VXForm_3<908, (outs vrrc:$VD), (ins), + "vspltisw $VD, -1", IIC_VecFP, + [(set v8i16:$VD, (v8i16 immAllOnesV))]>; +def V_SETALLONES : VXForm_3<908, (outs vrrc:$VD), (ins), + "vspltisw $VD, -1", IIC_VecFP, + [(set v4i32:$VD, (v4i32 immAllOnesV))]>; } } } // VALU Operations. @@ -1166,15 +1166,15 @@ // [PO VRT VRA VRB 1 PS XO], "_o" means CR6 is set. class VX_VT5_VA5_VB5_PS1_XO9_o xo, string opc, list pattern> : VX_RD5_RSp5_PS1_XO9 { + (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, u1imm:$PS), + !strconcat(opc, " $VD, $VA, $VB, $PS"), IIC_VecFP, pattern> { let Defs = [CR6]; } // [PO VRT VRA VRB 1 / XO] class VX_VT5_VA5_VB5_XO9_o xo, string opc, list pattern> - : VX_RD5_RSp5_PS1_XO9 { + : VX_RD5_RSp5_PS1_XO9 { let Defs = [CR6]; let PS = 0; } @@ -1192,9 +1192,9 @@ v2i64, v4i32>; def VMULOUW : VX1_Int_Ty2<136, "vmulouw", int_ppc_altivec_vmulouw, v2i64, v4i32>; -def VMULUWM : VXForm_1<137, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmuluwm $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (mul v4i32:$vA, v4i32:$vB))]>; +def VMULUWM : VXForm_1<137, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmuluwm $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (mul v4i32:$VA, v4i32:$VB))]>; def VMAXSD : VX1_Int_Ty<450, "vmaxsd", int_ppc_altivec_vmaxsd, v2i64>; def VMAXUD : VX1_Int_Ty<194, "vmaxud", int_ppc_altivec_vmaxud, v2i64>; def VMINSD : VX1_Int_Ty<962, "vminsd", int_ppc_altivec_vminsd, v2i64>; @@ -1202,14 +1202,14 @@ } // isCommutable // Vector merge -def VMRGEW : VXForm_1<1932, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmrgew $vD, $vA, $vB", IIC_VecFP, - [(set v16i8:$vD, - (v16i8 (vmrgew_shuffle v16i8:$vA, v16i8:$vB)))]>; -def VMRGOW : VXForm_1<1676, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmrgow $vD, $vA, $vB", IIC_VecFP, - [(set v16i8:$vD, - (v16i8 (vmrgow_shuffle v16i8:$vA, v16i8:$vB)))]>; +def VMRGEW : VXForm_1<1932, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmrgew $VD, $VA, $VB", IIC_VecFP, + [(set v16i8:$VD, + (v16i8 (vmrgew_shuffle v16i8:$VA, v16i8:$VB)))]>; +def VMRGOW : VXForm_1<1676, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmrgow $VD, $VA, $VB", IIC_VecFP, + [(set v16i8:$VD, + (v16i8 (vmrgow_shuffle v16i8:$VA, v16i8:$VB)))]>; // Match vmrgew(x,x) and vmrgow(x,x) def:Pat<(vmrgew_unary_shuffle v16i8:$vA, undef), @@ -1232,12 +1232,12 @@ (v2i64 (VRLD v2i64:$vA, v2i64:$vB))>; // Vector shifts -def VSLD : VXForm_1<1476, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vsld $vD, $vA, $vB", IIC_VecGeneral, []>; -def VSRD : VXForm_1<1732, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vsrd $vD, $vA, $vB", IIC_VecGeneral, []>; -def VSRAD : VXForm_1<964, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vsrad $vD, $vA, $vB", IIC_VecGeneral, []>; +def VSLD : VXForm_1<1476, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vsld $VD, $VA, $VB", IIC_VecGeneral, []>; +def VSRD : VXForm_1<1732, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vsrd $VD, $VA, $VB", IIC_VecGeneral, []>; +def VSRAD : VXForm_1<964, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vsrad $VD, $VA, $VB", IIC_VecGeneral, []>; def : Pat<(v2i64 (shl v2i64:$vA, v2i64:$vB)), (v2i64 (VSLD $vA, $vB))>; @@ -1254,12 +1254,12 @@ // Vector Integer Arithmetic Instructions let isCommutable = 1 in { -def VADDUDM : VXForm_1<192, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vaddudm $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (add v2i64:$vA, v2i64:$vB))]>; -def VADDUQM : VXForm_1<256, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vadduqm $vD, $vA, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (add v1i128:$vA, v1i128:$vB))]>; +def VADDUDM : VXForm_1<192, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vaddudm $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (add v2i64:$VA, v2i64:$VB))]>; +def VADDUQM : VXForm_1<256, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vadduqm $VD, $VA, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (add v1i128:$VA, v1i128:$VB))]>; } // isCommutable // Vector Quadword Add @@ -1268,45 +1268,45 @@ def VADDECUQ : VA1a_Int_Ty<61, "vaddecuq", int_ppc_altivec_vaddecuq, v1i128>; // Vector Doubleword Subtract -def VSUBUDM : VXForm_1<1216, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vsubudm $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (sub v2i64:$vA, v2i64:$vB))]>; +def VSUBUDM : VXForm_1<1216, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vsubudm $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (sub v2i64:$VA, v2i64:$VB))]>; // Vector Quadword Subtract -def VSUBUQM : VXForm_1<1280, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vsubuqm $vD, $vA, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (sub v1i128:$vA, v1i128:$vB))]>; +def VSUBUQM : VXForm_1<1280, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vsubuqm $VD, $VA, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (sub v1i128:$VA, v1i128:$VB))]>; def VSUBEUQM : VA1a_Int_Ty<62, "vsubeuqm", int_ppc_altivec_vsubeuqm, v1i128>; def VSUBCUQ : VX1_Int_Ty<1344, "vsubcuq", int_ppc_altivec_vsubcuq, v1i128>; def VSUBECUQ : VA1a_Int_Ty<63, "vsubecuq", int_ppc_altivec_vsubecuq, v1i128>; // Count Leading Zeros -def VCLZB : VXForm_2<1794, (outs vrrc:$vD), (ins vrrc:$vB), - "vclzb $vD, $vB", IIC_VecGeneral, - [(set v16i8:$vD, (ctlz v16i8:$vB))]>; -def VCLZH : VXForm_2<1858, (outs vrrc:$vD), (ins vrrc:$vB), - "vclzh $vD, $vB", IIC_VecGeneral, - [(set v8i16:$vD, (ctlz v8i16:$vB))]>; -def VCLZW : VXForm_2<1922, (outs vrrc:$vD), (ins vrrc:$vB), - "vclzw $vD, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (ctlz v4i32:$vB))]>; -def VCLZD : VXForm_2<1986, (outs vrrc:$vD), (ins vrrc:$vB), - "vclzd $vD, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (ctlz v2i64:$vB))]>; +def VCLZB : VXForm_2<1794, (outs vrrc:$VD), (ins vrrc:$VB), + "vclzb $VD, $VB", IIC_VecGeneral, + [(set v16i8:$VD, (ctlz v16i8:$VB))]>; +def VCLZH : VXForm_2<1858, (outs vrrc:$VD), (ins vrrc:$VB), + "vclzh $VD, $VB", IIC_VecGeneral, + [(set v8i16:$VD, (ctlz v8i16:$VB))]>; +def VCLZW : VXForm_2<1922, (outs vrrc:$VD), (ins vrrc:$VB), + "vclzw $VD, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (ctlz v4i32:$VB))]>; +def VCLZD : VXForm_2<1986, (outs vrrc:$VD), (ins vrrc:$VB), + "vclzd $VD, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (ctlz v2i64:$VB))]>; // Population Count -def VPOPCNTB : VXForm_2<1795, (outs vrrc:$vD), (ins vrrc:$vB), - "vpopcntb $vD, $vB", IIC_VecGeneral, - [(set v16i8:$vD, (ctpop v16i8:$vB))]>; -def VPOPCNTH : VXForm_2<1859, (outs vrrc:$vD), (ins vrrc:$vB), - "vpopcnth $vD, $vB", IIC_VecGeneral, - [(set v8i16:$vD, (ctpop v8i16:$vB))]>; -def VPOPCNTW : VXForm_2<1923, (outs vrrc:$vD), (ins vrrc:$vB), - "vpopcntw $vD, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (ctpop v4i32:$vB))]>; -def VPOPCNTD : VXForm_2<1987, (outs vrrc:$vD), (ins vrrc:$vB), - "vpopcntd $vD, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (ctpop v2i64:$vB))]>; +def VPOPCNTB : VXForm_2<1795, (outs vrrc:$VD), (ins vrrc:$VB), + "vpopcntb $VD, $VB", IIC_VecGeneral, + [(set v16i8:$VD, (ctpop v16i8:$VB))]>; +def VPOPCNTH : VXForm_2<1859, (outs vrrc:$VD), (ins vrrc:$VB), + "vpopcnth $VD, $VB", IIC_VecGeneral, + [(set v8i16:$VD, (ctpop v8i16:$VB))]>; +def VPOPCNTW : VXForm_2<1923, (outs vrrc:$VD), (ins vrrc:$VB), + "vpopcntw $VD, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (ctpop v4i32:$VB))]>; +def VPOPCNTD : VXForm_2<1987, (outs vrrc:$VD), (ins vrrc:$VB), + "vpopcntd $VD, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (ctpop v2i64:$VB))]>; let isCommutable = 1 in { // FIXME: Use AddedComplexity > 400 to ensure these patterns match before the @@ -1319,26 +1319,26 @@ // 2. Employ a more disciplined use of AddedComplexity, which would provide // more fine-grained control than option 1. This would be beneficial // if we find situations where Altivec is really preferred over VSX. -def VEQV : VXForm_1<1668, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "veqv $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (vnot (xor v4i32:$vA, v4i32:$vB)))]>; -def VNAND : VXForm_1<1412, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vnand $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (vnot (and v4i32:$vA, v4i32:$vB)))]>; +def VEQV : VXForm_1<1668, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "veqv $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (vnot (xor v4i32:$VA, v4i32:$VB)))]>; +def VNAND : VXForm_1<1412, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vnand $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (vnot (and v4i32:$VA, v4i32:$VB)))]>; } // isCommutable -def VORC : VXForm_1<1348, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vorc $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (or v4i32:$vA, - (vnot v4i32:$vB)))]>; +def VORC : VXForm_1<1348, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vorc $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (or v4i32:$VA, + (vnot v4i32:$VB)))]>; // i64 element comparisons. -def VCMPEQUD : VCMP <199, "vcmpequd $vD, $vA, $vB" , v2i64>; -def VCMPEQUD_rec : VCMP_rec<199, "vcmpequd. $vD, $vA, $vB", v2i64>; -def VCMPGTSD : VCMP <967, "vcmpgtsd $vD, $vA, $vB" , v2i64>; -def VCMPGTSD_rec : VCMP_rec<967, "vcmpgtsd. $vD, $vA, $vB", v2i64>; -def VCMPGTUD : VCMP <711, "vcmpgtud $vD, $vA, $vB" , v2i64>; -def VCMPGTUD_rec : VCMP_rec<711, "vcmpgtud. $vD, $vA, $vB", v2i64>; +def VCMPEQUD : VCMP <199, "vcmpequd $VD, $VA, $VB" , v2i64>; +def VCMPEQUD_rec : VCMP_rec<199, "vcmpequd. $VD, $VA, $VB", v2i64>; +def VCMPGTSD : VCMP <967, "vcmpgtsd $VD, $VA, $VB" , v2i64>; +def VCMPGTSD_rec : VCMP_rec<967, "vcmpgtsd. $VD, $VA, $VB", v2i64>; +def VCMPGTUD : VCMP <711, "vcmpgtud $VD, $VA, $VB" , v2i64>; +def VCMPGTUD_rec : VCMP_rec<711, "vcmpgtud. $VD, $VA, $VB", v2i64>; // The cryptography instructions that do not require Category:Vector.Crypto def VPMSUMB : VX1_Int_Ty<1032, "vpmsumb", @@ -1349,8 +1349,8 @@ int_ppc_altivec_crypto_vpmsumw, v4i32>; def VPMSUMD : VX1_Int_Ty<1224, "vpmsumd", int_ppc_altivec_crypto_vpmsumd, v2i64>; -def VPERMXOR : VAForm_1<45, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, vrrc:$VC), - "vpermxor $VD, $VA, $VB, $VC", IIC_VecFP, []>; +def VPERMXOR : VAForm_1<45, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC), + "vpermxor $RT, $RA, $RB, $RC", IIC_VecFP, []>; // Vector doubleword integer pack and unpack. let hasSideEffects = 1 in { @@ -1361,10 +1361,10 @@ def VPKUDUS : VX1_Int_Ty2<1230, "vpkudus", int_ppc_altivec_vpkudus, v4i32, v2i64>; } -def VPKUDUM : VXForm_1<1102, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vpkudum $vD, $vA, $vB", IIC_VecFP, - [(set v16i8:$vD, - (vpkudum_shuffle v16i8:$vA, v16i8:$vB))]>; +def VPKUDUM : VXForm_1<1102, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vpkudum $VD, $VA, $VB", IIC_VecFP, + [(set v16i8:$VD, + (vpkudum_shuffle v16i8:$VA, v16i8:$VB))]>; def VUPKHSW : VX2_Int_Ty2<1614, "vupkhsw", int_ppc_altivec_vupkhsw, v2i64, v4i32>; def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw, @@ -1414,33 +1414,33 @@ v1i128, v2i64, v1i128>; // i8 element comparisons. -def VCMPNEB : VCMP < 7, "vcmpneb $vD, $vA, $vB" , v16i8>; -def VCMPNEB_rec : VCMP_rec < 7, "vcmpneb. $vD, $vA, $vB" , v16i8>; -def VCMPNEZB : VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>; -def VCMPNEZB_rec : VCMP_rec<263, "vcmpnezb. $vD, $vA, $vB", v16i8>; +def VCMPNEB : VCMP < 7, "vcmpneb $VD, $VA, $VB" , v16i8>; +def VCMPNEB_rec : VCMP_rec < 7, "vcmpneb. $VD, $VA, $VB" , v16i8>; +def VCMPNEZB : VCMP <263, "vcmpnezb $VD, $VA, $VB" , v16i8>; +def VCMPNEZB_rec : VCMP_rec<263, "vcmpnezb. $VD, $VA, $VB", v16i8>; // i16 element comparisons. -def VCMPNEH : VCMP < 71, "vcmpneh $vD, $vA, $vB" , v8i16>; -def VCMPNEH_rec : VCMP_rec< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>; -def VCMPNEZH : VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>; -def VCMPNEZH_rec : VCMP_rec<327, "vcmpnezh. $vD, $vA, $vB", v8i16>; +def VCMPNEH : VCMP < 71, "vcmpneh $VD, $VA, $VB" , v8i16>; +def VCMPNEH_rec : VCMP_rec< 71, "vcmpneh. $VD, $VA, $VB" , v8i16>; +def VCMPNEZH : VCMP <327, "vcmpnezh $VD, $VA, $VB" , v8i16>; +def VCMPNEZH_rec : VCMP_rec<327, "vcmpnezh. $VD, $VA, $VB", v8i16>; // i32 element comparisons. -def VCMPNEW : VCMP <135, "vcmpnew $vD, $vA, $vB" , v4i32>; -def VCMPNEW_rec : VCMP_rec<135, "vcmpnew. $vD, $vA, $vB" , v4i32>; -def VCMPNEZW : VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>; -def VCMPNEZW_rec : VCMP_rec<391, "vcmpnezw. $vD, $vA, $vB", v4i32>; +def VCMPNEW : VCMP <135, "vcmpnew $VD, $VA, $VB" , v4i32>; +def VCMPNEW_rec : VCMP_rec<135, "vcmpnew. $VD, $VA, $VB" , v4i32>; +def VCMPNEZW : VCMP <391, "vcmpnezw $VD, $VA, $VB" , v4i32>; +def VCMPNEZW_rec : VCMP_rec<391, "vcmpnezw. $VD, $VA, $VB", v4i32>; // VX-Form: [PO VRT / UIM VRB XO]. // We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent // "/ UIM" (1 + 4 bit) class VX1_VT5_UIM5_VB5 xo, string opc, list pattern> - : VXForm_1; + : VXForm_1; class VX1_RT5_RA5_VB5 xo, string opc, list pattern> - : VXForm_1; + : VXForm_1; // Vector Extract Unsigned def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>; @@ -1459,58 +1459,58 @@ } // Vector Insert Element Instructions -def VINSERTB : VXForm_1<781, (outs vrrc:$vD), - (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), - "vinsertb $vD, $vB, $UIM", IIC_VecGeneral, - [(set v16i8:$vD, (PPCvecinsert v16i8:$vDi, v16i8:$vB, - imm32SExt16:$UIM))]>, - RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; -def VINSERTH : VXForm_1<845, (outs vrrc:$vD), - (ins vrrc:$vDi, u4imm:$UIM, vrrc:$vB), - "vinserth $vD, $vB, $UIM", IIC_VecGeneral, - [(set v8i16:$vD, (PPCvecinsert v8i16:$vDi, v8i16:$vB, - imm32SExt16:$UIM))]>, - RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; +def VINSERTB : VXForm_1<781, (outs vrrc:$VD), + (ins vrrc:$VDi, u4imm:$VA, vrrc:$VB), + "vinsertb $VD, $VB, $VA", IIC_VecGeneral, + [(set v16i8:$VD, (PPCvecinsert v16i8:$VDi, v16i8:$VB, + imm32SExt16:$VA))]>, + RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; +def VINSERTH : VXForm_1<845, (outs vrrc:$VD), + (ins vrrc:$VDi, u4imm:$VA, vrrc:$VB), + "vinserth $VD, $VB, $VA", IIC_VecGeneral, + [(set v8i16:$VD, (PPCvecinsert v8i16:$VDi, v8i16:$VB, + imm32SExt16:$VA))]>, + RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>; def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>; class VX_VT5_EO5_VB5 xo, bits<5> eo, string opc, list pattern> - : VXForm_RD5_XO5_RS5; + : VXForm_RD5_XO5_RS5; class VX_VT5_EO5_VB5s xo, bits<5> eo, string opc, list pattern> - : VXForm_RD5_XO5_RS5; - -// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD] -def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$rD), (ins vrrc:$vB), - "vclzlsbb $rD, $vB", IIC_VecGeneral, - [(set i32:$rD, (int_ppc_altivec_vclzlsbb - v16i8:$vB))]>; -def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$rD), (ins vrrc:$vB), - "vctzlsbb $rD, $vB", IIC_VecGeneral, - [(set i32:$rD, (int_ppc_altivec_vctzlsbb - v16i8:$vB))]>; + : VXForm_RD5_XO5_RS5; + +// Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[RD] +def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$VD), (ins vrrc:$VB), + "vclzlsbb $VD, $VB", IIC_VecGeneral, + [(set i32:$VD, (int_ppc_altivec_vclzlsbb + v16i8:$VB))]>; +def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$VD), (ins vrrc:$VB), + "vctzlsbb $VD, $VB", IIC_VecGeneral, + [(set i32:$VD, (int_ppc_altivec_vctzlsbb + v16i8:$VB))]>; // Vector Count Trailing Zeros def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb", - [(set v16i8:$vD, (cttz v16i8:$vB))]>; + [(set v16i8:$VD, (cttz v16i8:$VB))]>; def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh", - [(set v8i16:$vD, (cttz v8i16:$vB))]>; + [(set v8i16:$VD, (cttz v8i16:$VB))]>; def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw", - [(set v4i32:$vD, (cttz v4i32:$vB))]>; + [(set v4i32:$VD, (cttz v4i32:$VB))]>; def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd", - [(set v2i64:$vD, (cttz v2i64:$vB))]>; + [(set v2i64:$VD, (cttz v2i64:$VB))]>; // Vector Extend Sign def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", - [(set v4i32:$vD, (int_ppc_altivec_vextsb2w v16i8:$vB))]>; + [(set v4i32:$VD, (int_ppc_altivec_vextsb2w v16i8:$VB))]>; def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", - [(set v4i32:$vD, (int_ppc_altivec_vextsh2w v8i16:$vB))]>; + [(set v4i32:$VD, (int_ppc_altivec_vextsh2w v8i16:$VB))]>; def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", - [(set v2i64:$vD, (int_ppc_altivec_vextsb2d v16i8:$vB))]>; + [(set v2i64:$VD, (int_ppc_altivec_vextsb2d v16i8:$VB))]>; def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", - [(set v2i64:$vD, (int_ppc_altivec_vextsh2d v8i16:$vB))]>; + [(set v2i64:$VD, (int_ppc_altivec_vextsh2d v8i16:$VB))]>; def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", - [(set v2i64:$vD, (int_ppc_altivec_vextsw2d v4i32:$vB))]>; + [(set v2i64:$VD, (int_ppc_altivec_vextsw2d v4i32:$VB))]>; let isCodeGenOnly = 1 in { def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>; def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>; @@ -1527,64 +1527,64 @@ // Vector Integer Negate def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", - [(set v4i32:$vD, - (sub (v4i32 immAllZerosV), v4i32:$vB))]>; + [(set v4i32:$VD, + (sub (v4i32 immAllZerosV), v4i32:$VB))]>; def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", - [(set v2i64:$vD, - (sub (v2i64 immAllZerosV), v2i64:$vB))]>; + [(set v2i64:$VD, + (sub (v2i64 immAllZerosV), v2i64:$VB))]>; // Vector Parity Byte -def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD, - (int_ppc_altivec_vprtybw v4i32:$vB))]>; -def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$vD, - (int_ppc_altivec_vprtybd v2i64:$vB))]>; -def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$vD, - (int_ppc_altivec_vprtybq v1i128:$vB))]>; +def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$VD, + (int_ppc_altivec_vprtybw v4i32:$VB))]>; +def VPRTYBD : VX_VT5_EO5_VB5<1538, 9, "vprtybd", [(set v2i64:$VD, + (int_ppc_altivec_vprtybd v2i64:$VB))]>; +def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$VD, + (int_ppc_altivec_vprtybq v1i128:$VB))]>; // Vector (Bit) Permute (Right-indexed) def VBPERMD : VX1_Int_Ty3<1484, "vbpermd", int_ppc_altivec_vbpermd, v2i64, v2i64, v16i8>; -def VPERMR : VAForm_1a<59, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), - "vpermr $vD, $vA, $vB, $vC", IIC_VecFP, []>; +def VPERMR : VAForm_1a<59, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC), + "vpermr $RT, $RA, $RB, $RC", IIC_VecFP, []>; class VX1_VT5_VA5_VB5 xo, string opc, list pattern> - : VXForm_1; + : VXForm_1; // Vector Rotate Left Mask/Mask-Insert def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm", - [(set v4i32:$vD, - (int_ppc_altivec_vrlwnm v4i32:$vA, - v4i32:$vB))]>; -def VRLWMI : VXForm_1<133, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), - "vrlwmi $vD, $vA, $vB", IIC_VecFP, - [(set v4i32:$vD, - (int_ppc_altivec_vrlwmi v4i32:$vA, v4i32:$vB, - v4i32:$vDi))]>, - RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; + [(set v4i32:$VD, + (int_ppc_altivec_vrlwnm v4i32:$VA, + v4i32:$VB))]>; +def VRLWMI : VXForm_1<133, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi), + "vrlwmi $VD, $VA, $VB", IIC_VecFP, + [(set v4i32:$VD, + (int_ppc_altivec_vrlwmi v4i32:$VA, v4i32:$VB, + v4i32:$VDi))]>, + RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", - [(set v2i64:$vD, - (int_ppc_altivec_vrldnm v2i64:$vA, - v2i64:$vB))]>; -def VRLDMI : VXForm_1<197, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), - "vrldmi $vD, $vA, $vB", IIC_VecFP, - [(set v2i64:$vD, - (int_ppc_altivec_vrldmi v2i64:$vA, v2i64:$vB, - v2i64:$vDi))]>, - RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; + [(set v2i64:$VD, + (int_ppc_altivec_vrldnm v2i64:$VA, + v2i64:$VB))]>; +def VRLDMI : VXForm_1<197, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi), + "vrldmi $VD, $VA, $VB", IIC_VecFP, + [(set v2i64:$VD, + (int_ppc_altivec_vrldmi v2i64:$VA, v2i64:$VB, + v2i64:$VDi))]>, + RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; // Vector Shift Left/Right def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", - [(set v16i8 : $vD, (int_ppc_altivec_vslv v16i8 : $vA, v16i8 : $vB))]>; + [(set v16i8 : $VD, (int_ppc_altivec_vslv v16i8 : $VA, v16i8 : $VB))]>; def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", - [(set v16i8 : $vD, (int_ppc_altivec_vsrv v16i8 : $vA, v16i8 : $vB))]>; + [(set v16i8 : $VD, (int_ppc_altivec_vsrv v16i8 : $VA, v16i8 : $VB))]>; // Vector Multiply-by-10 (& Write Carry) Unsigned Quadword -def VMUL10UQ : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA), - "vmul10uq $vD, $vA", IIC_VecFP, []>; -def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$vD), (ins vrrc:$vA), - "vmul10cuq $vD, $vA", IIC_VecFP, []>; +def VMUL10UQ : VXForm_BX<513, (outs vrrc:$VD), (ins vrrc:$VA), + "vmul10uq $VD, $VA", IIC_VecFP, []>; +def VMUL10CUQ : VXForm_BX< 1, (outs vrrc:$VD), (ins vrrc:$VA), + "vmul10cuq $VD, $VA", IIC_VecFP, []>; // Vector Multiply-by-10 Extended (& Write Carry) Unsigned Quadword def VMUL10EUQ : VX1_VT5_VA5_VB5<577, "vmul10euq" , []>; @@ -1595,16 +1595,16 @@ // [PO VRT EO VRB 1 PS XO], "_o" means CR6 is set. class VX_VT5_EO5_VB5_PS1_XO9_o eo, bits<9> xo, string opc, list pattern> - : VX_RD5_EO5_RS5_PS1_XO9 { + : VX_RD5_EO5_RS5_PS1_XO9 { let Defs = [CR6]; } // [PO VRT EO VRB 1 / XO] class VX_VT5_EO5_VB5_XO9_o eo, bits<9> xo, string opc, list pattern> - : VX_RD5_EO5_RS5_PS1_XO9 { + : VX_RD5_EO5_RS5_PS1_XO9 { let Defs = [CR6]; let PS = 0; } @@ -1633,14 +1633,14 @@ def BCDUTRUNC_rec : VX_VT5_VA5_VB5_XO9_o <321, "bcdutrunc.", []>; // Absolute Difference -def VABSDUB : VXForm_1<1027, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vabsdub $vD, $vA, $vB", IIC_VecGeneral, - [(set v16i8:$vD, (int_ppc_altivec_vabsdub v16i8:$vA, v16i8:$vB))]>; -def VABSDUH : VXForm_1<1091, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vabsduh $vD, $vA, $vB", IIC_VecGeneral, - [(set v8i16:$vD, (int_ppc_altivec_vabsduh v8i16:$vA, v8i16:$vB))]>; -def VABSDUW : VXForm_1<1155, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vabsduw $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (int_ppc_altivec_vabsduw v4i32:$vA, v4i32:$vB))]>; +def VABSDUB : VXForm_1<1027, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vabsdub $VD, $VA, $VB", IIC_VecGeneral, + [(set v16i8:$VD, (int_ppc_altivec_vabsdub v16i8:$VA, v16i8:$VB))]>; +def VABSDUH : VXForm_1<1091, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vabsduh $VD, $VA, $VB", IIC_VecGeneral, + [(set v8i16:$VD, (int_ppc_altivec_vabsduh v8i16:$VA, v8i16:$VB))]>; +def VABSDUW : VXForm_1<1155, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vabsduw $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (int_ppc_altivec_vabsduw v4i32:$VA, v4i32:$VB))]>; } // end HasP9Altivec diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td --- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td @@ -205,7 +205,8 @@ let Inst{31} = lk; } -class BForm_4 opcode, bits<5> bo, bit aa, bit lk, +class +BForm_4 opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, string asmstr> : I { bits<5> BI; @@ -233,47 +234,33 @@ // 1.7.4 D-Form class DForm_base opcode, dag OOL, dag IOL, string asmstr, - InstrItinClass itin, list pattern> + InstrItinClass itin, list pattern> : I { - bits<5> A; - bits<5> B; - bits<16> C; + bits<5> RST; + bits<5> RA; + bits<16> D; let Pattern = pattern; - - let Inst{6-10} = A; - let Inst{11-15} = B; - let Inst{16-31} = C; + + let Inst{6-10} = RST; + let Inst{11-15} = RA; + let Inst{16-31} = D; } class DForm_1 opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : I { - bits<5> A; - bits<21> Addr; + bits<5> RST; + // FIXME: bogus names, to force positional matching for the moment. + bits<21> addr_foo; let Pattern = pattern; - - let Inst{6-10} = A; - let Inst{11-15} = Addr{20-16}; // Base Reg - let Inst{16-31} = Addr{15-0}; // Displacement -} -class DForm_1a opcode, dag OOL, dag IOL, string asmstr, - InstrItinClass itin, list pattern> - : I { - bits<5> A; - bits<16> C; - bits<5> B; - - let Pattern = pattern; - - let Inst{6-10} = A; - let Inst{11-15} = B; - let Inst{16-31} = C; + let Inst{6-10} = RST; + let Inst{11-15} = addr_foo{20-16}; // Base Reg + let Inst{16-31} = addr_foo{15-0}; // Displacement } - class DForm_2 opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : DForm_base { @@ -286,52 +273,52 @@ class DForm_2_r0 opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : I { - bits<5> A; - bits<16> B; - + bits<5> RST; + bits<16> D; + let Pattern = pattern; - - let Inst{6-10} = A; + + let Inst{6-10} = RST; let Inst{11-15} = 0; - let Inst{16-31} = B; + let Inst{16-31} = D; } class DForm_4 opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : I { - bits<5> B; - bits<5> A; - bits<16> C; - + bits<5> RA; + bits<5> RST; + bits<16> D; + let Pattern = pattern; - - let Inst{6-10} = A; - let Inst{11-15} = B; - let Inst{16-31} = C; + + let Inst{6-10} = RST; + let Inst{11-15} = RA; + let Inst{16-31} = D; } - + class DForm_4_zero opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : DForm_1 { - let A = 0; - let Addr = 0; + let RST = 0; + let addr_foo = 0; } class DForm_4_fixedreg_zero opcode, bits<5> R, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : DForm_4 { - let A = R; - let B = R; - let C = 0; + let RST = R; + let RA = R; + let D = 0; } class IForm_and_DForm_1 opcode1, bit aa, bit lk, bits<6> opcode2, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : I2 { - bits<5> A; - bits<21> Addr; + bits<5> RST; + bits<21> addr; let Pattern = pattern; bits<24> LI; @@ -340,9 +327,9 @@ let Inst{30} = aa; let Inst{31} = lk; - let Inst{38-42} = A; - let Inst{43-47} = Addr{20-16}; // Base Reg - let Inst{48-63} = Addr{15-0}; // Displacement + let Inst{38-42} = RST; + let Inst{43-47} = addr{20-16}; // Base Reg + let Inst{48-63} = addr{15-0}; // Displacement } // This is used to emit BL8+NOP. @@ -351,8 +338,8 @@ InstrItinClass itin, list pattern> : IForm_and_DForm_1 { - let A = 0; - let Addr = 0; + let RST = 0; + let addr = 0; } class DForm_5 opcode, dag OOL, dag IOL, string asmstr, @@ -361,13 +348,13 @@ bits<3> BF; bits<1> L; bits<5> RA; - bits<16> I; + bits<16> D; let Inst{6-8} = BF; let Inst{9} = 0; let Inst{10} = L; let Inst{11-15} = RA; - let Inst{16-31} = I; + let Inst{16-31} = D; } class DForm_5_ext opcode, dag OOL, dag IOL, string asmstr, @@ -392,13 +379,19 @@ InstrItinClass itin, list pattern> : I { bits<5> RST; - bits<19> DS_RA; + // FIXME: bogus names, to force positional matching for the moment.rr + bits<19> addr_foo; + bits<14> DS; + bits<5> RA; + + let DS = addr_foo{13-0}; + let RA = addr_foo{18-14}; let Pattern = pattern; - + let Inst{6-10} = RST; - let Inst{11-15} = DS_RA{18-14}; // Register # - let Inst{16-29} = DS_RA{13-0}; // Displacement. + let Inst{11-15} = RA; + let Inst{16-29} = DS; let Inst{30-31} = xo; } @@ -423,13 +416,17 @@ string asmstr, InstrItinClass itin, list pattern> : I { bits<6> XT; - bits<17> DS_RA; + bits<17> addr; + bits<5> RA; + bits<12> DQ; + let RA = addr{16-12}; + let DQ = addr{11-0}; let Pattern = pattern; let Inst{6-10} = XT{4-0}; - let Inst{11-15} = DS_RA{16-12}; // Register # - let Inst{16-27} = DS_RA{11-0}; // Displacement. + let Inst{11-15} = RA; + let Inst{16-27} = DQ; let Inst{28} = XT{5}; let Inst{29-31} = xo; } @@ -439,12 +436,16 @@ list pattern> : I { bits<5> RTp; - bits<17> DQ_RA; + bits<17> addr; + bits<5> RA; + bits<12> DQ; + let RA = addr{16-12}; + let DQ = addr{11-0}; let Pattern = pattern; let Inst{6-10} = RTp{4-0}; - let Inst{11-15} = DQ_RA{16-12}; // Register # - let Inst{16-27} = DQ_RA{11-0}; // Displacement. + let Inst{11-15} = RA; + let Inst{16-27} = DQ; let Inst{28-31} = xo; } @@ -453,16 +454,16 @@ InstrItinClass itin, list pattern> : I { bits<5> RST; - bits<5> A; - bits<5> B; + bits<5> RA; + bits<5> RB; let Pattern = pattern; bit RC = 0; // set by isRecordForm let Inst{6-10} = RST; - let Inst{11-15} = A; - let Inst{16-20} = B; + let Inst{11-15} = RA; + let Inst{16-20} = RB; let Inst{21-30} = xo; let Inst{31} = RC; } @@ -489,15 +490,15 @@ opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> : I { - bits<5> A; + bits<5> RA; bits<5> RST; - bits<5> B; + bits<5> RB; bit RC = 0; // set by isRecordForm let Inst{6-10} = RST; - let Inst{11-15} = A; - let Inst{16-20} = B; + let Inst{11-15} = RA; + let Inst{16-20} = RB; let Inst{21-30} = xo; let Inst{31} = RC; } @@ -520,21 +521,21 @@ class XForm_rs opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : XForm_base_r3xo { - let A = 0; - let B = 0; + let RA = 0; + let RB = 0; } class XForm_tlbws opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : I { bits<5> RST; - bits<5> A; + bits<5> RA; bits<1> WS; let Pattern = pattern; let Inst{6-10} = RST; - let Inst{11-15} = A; + let Inst{11-15} = RA; let Inst{20} = WS; let Inst{21-30} = xo; let Inst{31} = 0; @@ -563,7 +564,7 @@ class XForm_11 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : XForm_base_r3xo_swapped { - let B = 0; + let RB = 0; let Pattern = pattern; } @@ -571,10 +572,10 @@ InstrItinClass itin> : I { bits<3> BF; - bits<1> L; + bits<1> L; bits<5> RA; bits<5> RB; - + let Inst{6-8} = BF; let Inst{9} = 0; let Inst{10} = L; @@ -651,13 +652,13 @@ InstrItinClass itin> : I { bits<3> BF; - bits<5> FRA; - bits<5> FRB; - + bits<5> RA; + bits<5> RB; + let Inst{6-8} = BF; let Inst{9-10} = 0; - let Inst{11-15} = FRA; - let Inst{16-20} = FRB; + let Inst{11-15} = RA; + let Inst{16-20} = RB; let Inst{21-30} = xo; let Inst{31} = 0; } @@ -665,7 +666,7 @@ class XForm_17a opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : XForm_17 { - let FRA = 0; + let RA = 0; let Pattern = pattern; } @@ -754,7 +755,7 @@ class XForm_26 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : XForm_base_r3xo { - let A = 0; + let RA = 0; } class XForm_28_memOp opcode, bits<10> xo, dag OOL, dag IOL, @@ -889,15 +890,15 @@ InstrItinClass itin, list pattern> : XForm_base_r3xo { let RST = 0; - let A = 0; - let B = 0; + let RA = 0; + let RB = 0; } class XForm_16b opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : XForm_base_r3xo { let RST = 0; - let A = 0; + let RA = 0; } class XForm_htm0 opcode, bits<10> xo, dag OOL, dag IOL, @@ -996,7 +997,7 @@ class X_RD5_XO5_RS5 opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : XForm_base_r3xo { - let A = xo2; + let RA = xo2; } class X_BF3_DCMX7_RS5 opcode, bits<10> xo, dag OOL, dag IOL, @@ -1040,8 +1041,8 @@ class X_BF3 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> : XForm_17 { - let FRA = 0; - let FRB = 0; + let RA = 0; + let RB = 0; } // [PO /// L RA RB XO /] @@ -1060,14 +1061,14 @@ InstrItinClass itin, list pattern> : I { bits<6> XT; - bits<5> A; - bits<5> B; + bits<5> RA; + bits<5> RB; let Pattern = pattern; let Inst{6-10} = XT{4-0}; - let Inst{11-15} = A; - let Inst{16-20} = B; + let Inst{11-15} = RA; + let Inst{16-20} = RB; let Inst{21-30} = xo; let Inst{31} = XT{5}; } @@ -1079,7 +1080,7 @@ class XX1_RS6_RD5_XO opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : XX1Form { - let B = 0; + let RB = 0; } class XX2Form opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, @@ -1347,14 +1348,14 @@ class DCB_Form xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : I<31, OOL, IOL, asmstr, itin> { - bits<5> A; - bits<5> B; + bits<5> RA; + bits<5> RB; let Pattern = pattern; let Inst{6-10} = immfield; - let Inst{11-15} = A; - let Inst{16-20} = B; + let Inst{11-15} = RA; + let Inst{16-20} = RB; let Inst{21-30} = xo; let Inst{31} = 0; } @@ -1363,14 +1364,14 @@ InstrItinClass itin, list pattern> : I<31, OOL, IOL, asmstr, itin> { bits<5> TH; - bits<5> A; - bits<5> B; + bits<5> RA; + bits<5> RB; let Pattern = pattern; let Inst{6-10} = TH; - let Inst{11-15} = A; - let Inst{16-20} = B; + let Inst{11-15} = RA; + let Inst{16-20} = RB; let Inst{21-30} = xo; let Inst{31} = 0; } @@ -1380,16 +1381,16 @@ InstrItinClass itin, list pattern> : I<31, OOL, IOL, asmstr, itin> { bits<2> STRM; - bits<5> A; - bits<5> B; + bits<5> RA; + bits<5> RB; let Pattern = pattern; let Inst{6} = T; let Inst{7-8} = 0; let Inst{9-10} = STRM; - let Inst{11-15} = A; - let Inst{16-20} = B; + let Inst{11-15} = RA; + let Inst{16-20} = RB; let Inst{21-30} = xo; let Inst{31} = 0; } @@ -1588,7 +1589,7 @@ : I2 { bits<5> RST; - bits<21> D_RA; + bits<21> addr; let Pattern = pattern; @@ -1600,18 +1601,18 @@ let Inst{31} = lk; let Inst{38-42} = RST; - let Inst{43-47} = D_RA{20-16}; // Base Register - let Inst{48-63} = D_RA{15-0}; // Displacement + let Inst{43-47} = addr{20-16}; // Base Register + let Inst{48-63} = addr{15-0}; // Displacement } // 1.7.8 XFX-Form class XFXForm_1 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> : I { - bits<5> RT; + bits<5> RST; bits<10> SPR; - let Inst{6-10} = RT; + let Inst{6-10} = RST; let Inst{11} = SPR{4}; let Inst{12} = SPR{3}; let Inst{13} = SPR{2}; @@ -1647,22 +1648,22 @@ InstrItinClass itin, list pattern> : I { bits<5> RT; - bits<10> Entry; + bits<10> imm; let Pattern = pattern; let Inst{6-10} = RT; - let Inst{11-20} = Entry; + let Inst{11-20} = imm; let Inst{21-30} = xo; let Inst{31} = 0; } class XFXForm_5 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, - InstrItinClass itin> + InstrItinClass itin> : I { bits<8> FXM; - bits<5> rS; - - let Inst{6-10} = rS; + bits<5> RST; + + let Inst{6-10} = RST; let Inst{11} = 0; let Inst{12-19} = FXM; let Inst{20} = 0; @@ -1671,12 +1672,12 @@ } class XFXForm_5a opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, - InstrItinClass itin> + InstrItinClass itin> : I { - bits<5> ST; + bits<5> RST; bits<8> FXM; - - let Inst{6-10} = ST; + + let Inst{6-10} = RST; let Inst{11} = 1; let Inst{12-19} = FXM; let Inst{20} = 0; @@ -1684,16 +1685,6 @@ let Inst{31} = 0; } -class XFXForm_7 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, - InstrItinClass itin> - : XFXForm_1; - -class XFXForm_7_ext opcode, bits<10> xo, bits<10> spr, - dag OOL, dag IOL, string asmstr, InstrItinClass itin> - : XFXForm_7 { - let SPR = spr; -} - // XFL-Form - MTFSF // This is probably 1.7.9, but I don't have the reference that uses this // numbering scheme... @@ -1701,7 +1692,7 @@ InstrItinClass itin, listpattern> : I { bits<8> FM; - bits<5> rT; + bits<5> RT; bit RC = 0; // set by isRecordForm let Pattern = pattern; @@ -1709,7 +1700,7 @@ let Inst{6} = 0; let Inst{7-14} = FM; let Inst{15} = 0; - let Inst{16-20} = rT; + let Inst{16-20} = RT; let Inst{21-30} = xo; let Inst{31} = RC; } @@ -1737,7 +1728,7 @@ class XSForm_1 opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : I { - bits<5> A; + bits<5> RA; bits<5> RS; bits<6> SH; @@ -1745,7 +1736,7 @@ let Pattern = pattern; let Inst{6-10} = RS; - let Inst{11-15} = A; + let Inst{11-15} = RA; let Inst{16-20} = SH{4,3,2,1,0}; let Inst{21-29} = xo; let Inst{30} = SH{5}; @@ -1853,7 +1844,23 @@ class MForm_2 opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> - : MForm_1 { + : I { + bits<5> RA; + bits<5> RS; + bits<5> SH; + bits<5> MB; + bits<5> ME; + + let Pattern = pattern; + + bit RC = 0; // set by isRecordForm + + let Inst{6-10} = RS; + let Inst{11-15} = RA; + let Inst{16-20} = SH; + let Inst{21-25} = MB; + let Inst{26-30} = ME; + let Inst{31} = RC; } // 1.7.14 MD-Form @@ -1905,17 +1912,17 @@ class VAForm_1 xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : I<4, OOL, IOL, asmstr, itin> { - bits<5> VD; - bits<5> VA; - bits<5> VC; - bits<5> VB; + bits<5> RT; + bits<5> RA; + bits<5> RC; + bits<5> RB; let Pattern = pattern; - let Inst{6-10} = VD; - let Inst{11-15} = VA; - let Inst{16-20} = VB; - let Inst{21-25} = VC; + let Inst{6-10} = RT; + let Inst{11-15} = RA; + let Inst{16-20} = RB; + let Inst{21-25} = RC; let Inst{26-31} = xo; } @@ -1923,33 +1930,33 @@ class VAForm_1a xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : I<4, OOL, IOL, asmstr, itin> { - bits<5> VD; - bits<5> VA; - bits<5> VB; - bits<5> VC; + bits<5> RT; + bits<5> RA; + bits<5> RB; + bits<5> RC; let Pattern = pattern; - let Inst{6-10} = VD; - let Inst{11-15} = VA; - let Inst{16-20} = VB; - let Inst{21-25} = VC; + let Inst{6-10} = RT; + let Inst{11-15} = RA; + let Inst{16-20} = RB; + let Inst{21-25} = RC; let Inst{26-31} = xo; } class VAForm_2 xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : I<4, OOL, IOL, asmstr, itin> { - bits<5> VD; - bits<5> VA; - bits<5> VB; + bits<5> RT; + bits<5> RA; + bits<5> RB; bits<4> SH; let Pattern = pattern; - let Inst{6-10} = VD; - let Inst{11-15} = VA; - let Inst{16-20} = VB; + let Inst{6-10} = RT; + let Inst{11-15} = RA; + let Inst{16-20} = RB; let Inst{21} = 0; let Inst{22-25} = SH; let Inst{26-31} = xo; @@ -2039,12 +2046,12 @@ class VXForm_RD5_XO5_RS5 xo, bits<5> eo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : I<4, OOL, IOL, asmstr, itin> { - bits<5> RD; + bits<5> VD; bits<5> VB; let Pattern = pattern; - let Inst{6-10} = RD; + let Inst{6-10} = VD; let Inst{11-15} = eo; let Inst{16-20} = VB; let Inst{21-31} = xo; diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -53,36 +53,36 @@ let Predicates = [HasVSX, IsISAFuture] in { let mayLoad = 1 in { - def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB), - "lxvrl $XT, $src, $rB", IIC_LdStLoad, []>; + def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB), + "lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>; - def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB), - "lxvrll $XT, $src, $rB", IIC_LdStLoad, []>; + def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB), + "lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>; def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp), - (ins memr:$src, g8rc:$rB), - "lxvprl $XTp, $src, $rB", IIC_LdStLFD, []>; + (ins memr:$RA, g8rc:$RB), + "lxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>; def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp), - (ins memr:$src, g8rc:$rB), - "lxvprll $XTp, $src, $rB", IIC_LdStLFD, []>; + (ins memr:$RA, g8rc:$RB), + "lxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>; } let mayStore = 1 in { def STXVRL : XX1Form_memOp<31, 653, (outs), - (ins vsrc:$XT, memr:$dst, g8rc:$rB), - "stxvrl $XT, $dst, $rB", IIC_LdStLoad, []>; + (ins vsrc:$XT, memr:$RA, g8rc:$RB), + "stxvrl $XT, $RA, $RB", IIC_LdStLoad, []>; def STXVRLL : XX1Form_memOp<31, 685, (outs), - (ins vsrc:$XT, memr:$dst, g8rc:$rB), - "stxvrll $XT, $dst, $rB", IIC_LdStLoad, []>; + (ins vsrc:$XT, memr:$RA, g8rc:$RB), + "stxvrll $XT, $RA, $RB", IIC_LdStLoad, []>; def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs), - (ins vsrprc:$XTp, memr:$src, g8rc:$rB), - "stxvprl $XTp, $src, $rB", IIC_LdStLFD, []>; + (ins vsrprc:$XTp, memr:$RA, g8rc:$RB), + "stxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>; def STXVPRLL : XForm_XTp5_XAB5<31, 749, (outs), - (ins vsrprc:$XTp, memr:$src, g8rc:$rB), - "stxvprll $XTp, $src, $rB", IIC_LdStLFD, []>; + (ins vsrprc:$XTp, memr:$RA, g8rc:$RB), + "stxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>; } } diff --git a/llvm/lib/Target/PowerPC/PPCInstrHTM.td b/llvm/lib/Target/PowerPC/PPCInstrHTM.td --- a/llvm/lib/Target/PowerPC/PPCInstrHTM.td +++ b/llvm/lib/Target/PowerPC/PPCInstrHTM.td @@ -35,30 +35,30 @@ (outs), (ins u1imm:$A), "tend. $A", IIC_SprMTSPR>; def TABORT : XForm_base_r3xo <31, 910, - (outs), (ins gprc:$A), "tabort. $A", IIC_SprMTSPR, + (outs), (ins gprc:$RA), "tabort. $RA", IIC_SprMTSPR, []>, isRecordForm { let RST = 0; - let B = 0; + let RB = 0; } def TABORTWC : XForm_base_r3xo <31, 782, - (outs), (ins u5imm:$RTS, gprc:$A, gprc:$B), - "tabortwc. $RTS, $A, $B", IIC_SprMTSPR, []>, + (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB), + "tabortwc. $RST, $RA, $RB", IIC_SprMTSPR, []>, isRecordForm; def TABORTWCI : XForm_base_r3xo <31, 846, - (outs), (ins u5imm:$RTS, gprc:$A, u5imm:$B), - "tabortwci. $RTS, $A, $B", IIC_SprMTSPR, []>, + (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB), + "tabortwci. $RST, $RA, $RB", IIC_SprMTSPR, []>, isRecordForm; def TABORTDC : XForm_base_r3xo <31, 814, - (outs), (ins u5imm:$RTS, gprc:$A, gprc:$B), - "tabortdc. $RTS, $A, $B", IIC_SprMTSPR, []>, + (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB), + "tabortdc. $RST, $RA, $RB", IIC_SprMTSPR, []>, isRecordForm; def TABORTDCI : XForm_base_r3xo <31, 878, - (outs), (ins u5imm:$RTS, gprc:$A, u5imm:$B), - "tabortdci. $RTS, $A, $B", IIC_SprMTSPR, []>, + (outs), (ins u5imm:$RST, gprc:$RA, u5imm:$RB), + "tabortdci. $RST, $RA, $RB", IIC_SprMTSPR, []>, isRecordForm; def TSR : XForm_htm2 <31, 750, @@ -66,19 +66,19 @@ isRecordForm; def TRECLAIM : XForm_base_r3xo <31, 942, - (outs), (ins gprc:$A), "treclaim. $A", + (outs), (ins gprc:$RA), "treclaim. $RA", IIC_SprMTSPR, []>, isRecordForm { let RST = 0; - let B = 0; + let RB = 0; } def TRECHKPT : XForm_base_r3xo <31, 1006, (outs), (ins), "trechkpt.", IIC_SprMTSPR, []>, isRecordForm { let RST = 0; - let A = 0; - let B = 0; + let RA = 0; + let RB = 0; } } diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -933,6 +933,20 @@ } } +multiclass MForm_1r opcode, dag OOL, dag IOL, + string asmbase, string asmstr, InstrItinClass itin, + list pattern> { + let BaseName = asmbase in { + def NAME : MForm_1, RecFormRel; + let Defs = [CR0] in + def _rec : MForm_1, isRecordForm, RecFormRel; + } +} + multiclass MForm_2r opcode, dag OOL, dag IOL, string asmbase, string asmstr, InstrItinClass itin, list pattern> { @@ -1195,14 +1209,14 @@ []>; let isCodeGenOnly = 1 in { - def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), + def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond), "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, []>; - def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi), - "bcctr 12, $bi, 0", IIC_BrB, []>; - def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi), - "bcctr 4, $bi, 0", IIC_BrB, []>; + def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI), + "bcctr 12, $BI, 0", IIC_BrB, []>; + def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI), + "bcctr 4, $BI, 0", IIC_BrB, []>; } } } @@ -1230,48 +1244,48 @@ hasSideEffects = 0 in { let isBarrier = 1 in { let isPredicable = 1 in - def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$dst), - "b $dst", IIC_BrB, - [(br bb:$dst)]>; - def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$dst), - "ba $dst", IIC_BrB, []>; + def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$LI), + "b $LI", IIC_BrB, + [(br bb:$LI)]>; + def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$LI), + "ba $LI", IIC_BrB, []>; } // BCC represents an arbitrary conditional branch on a predicate. // FIXME: should be able to write a pattern for PPCcondbranch, but can't use // a two-value operand where a dag node expects two operands. :( let isCodeGenOnly = 1 in { - class BCC_class : BForm<16, 0, 0, (outs), (ins pred:$cond, condbrtarget:$dst), - "b${cond:cc}${cond:pm} ${cond:reg}, $dst" - /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$dst)]*/>; + class BCC_class : BForm<16, 0, 0, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD), + "b${cond:cc}${cond:pm} ${cond:reg}, $BD" + /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$BD)]*/>; def BCC : BCC_class; // The same as BCC, except that it's not a terminator. Used for introducing // control flow dependency without creating new blocks. let isTerminator = 0 in def CTRL_DEP : BCC_class; - def BCCA : BForm<16, 1, 0, (outs), (ins pred:$cond, abscondbrtarget:$dst), - "b${cond:cc}a${cond:pm} ${cond:reg}, $dst">; + def BCCA : BForm<16, 1, 0, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD), + "b${cond:cc}a${cond:pm} ${cond:reg}, $BD">; let isReturn = 1, Uses = [LR, RM] in - def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond), + def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins (pred $BIBO, $CR):$cond), "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; } let isCodeGenOnly = 1 in { - let Pattern = [(brcond i1:$bi, bb:$dst)] in - def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), - "bc 12, $bi, $dst">; + let Pattern = [(brcond i1:$BI, bb:$BD)] in + def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD), + "bc 12, $BI, $BD">; - let Pattern = [(brcond (not i1:$bi), bb:$dst)] in - def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$bi, condbrtarget:$dst), - "bc 4, $bi, $dst">; + let Pattern = [(brcond (not i1:$BI), bb:$BD)] in + def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD), + "bc 4, $BI, $BD">; let isReturn = 1, Uses = [LR, RM] in { - def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$bi), - "bclr 12, $bi, 0", IIC_BrB, []>; - def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$bi), - "bclr 4, $bi, 0", IIC_BrB, []>; + def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$BI), + "bclr 12, $BI, 0", IIC_BrB, []>; + def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$BI), + "bclr 4, $BI, 0", IIC_BrB, []>; } } @@ -1291,30 +1305,30 @@ } let Defs = [CTR], Uses = [CTR] in { - def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), - "bdz $dst">; - def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), - "bdnz $dst">; - def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$dst), - "bdza $dst">; - def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$dst), - "bdnza $dst">; - def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$dst), - "bdz+ $dst">; - def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$dst), - "bdnz+ $dst">; - def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$dst), - "bdza+ $dst">; - def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$dst), - "bdnza+ $dst">; - def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$dst), - "bdz- $dst">; - def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$dst), - "bdnz- $dst">; - def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$dst), - "bdza- $dst">; - def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$dst), - "bdnza- $dst">; + def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD), + "bdz $BD">; + def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD), + "bdnz $BD">; + def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$BD), + "bdza $BD">; + def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$BD), + "bdnza $BD">; + def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$BD), + "bdz+ $BD">; + def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$BD), + "bdnz+ $BD">; + def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$BD), + "bdza+ $BD">; + def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$BD), + "bdnza+ $BD">; + def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$BD), + "bdz- $BD">; + def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$BD), + "bdnz- $BD">; + def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$BD), + "bdza- $BD">; + def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$BD), + "bdnza- $BD">; } } @@ -1322,36 +1336,36 @@ let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7, hasSideEffects = 0 in { let Defs = [LR], Uses = [RM] in { - def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$dst), - "bcl 20, 31, $dst">; + def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$BD), + "bcl 20, 31, $BD">; } } let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { // Convenient aliases for call instructions let Uses = [RM] in { - def BL : IForm<18, 0, 1, (outs), (ins calltarget:$func), - "bl $func", IIC_BrB, []>; // See Pat patterns below. - def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), - "bla $func", IIC_BrB, [(PPCcall (i32 imm:$func))]>; + def BL : IForm<18, 0, 1, (outs), (ins calltarget:$LI), + "bl $LI", IIC_BrB, []>; // See Pat patterns below. + def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), + "bla $LI", IIC_BrB, [(PPCcall (i32 imm:$LI))]>; let isCodeGenOnly = 1 in { - def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$func), - "bl $func", IIC_BrB, []>; - def BCCL : BForm<16, 0, 1, (outs), (ins pred:$cond, condbrtarget:$dst), - "b${cond:cc}l${cond:pm} ${cond:reg}, $dst">; - def BCCLA : BForm<16, 1, 1, (outs), (ins pred:$cond, abscondbrtarget:$dst), - "b${cond:cc}la${cond:pm} ${cond:reg}, $dst">; + def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$LI), + "bl $LI", IIC_BrB, []>; + def BCCL : BForm<16, 0, 1, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD), + "b${cond:cc}l${cond:pm} ${cond:reg}, $BD">; + def BCCLA : BForm<16, 1, 1, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD), + "b${cond:cc}la${cond:pm} ${cond:reg}, $BD">; def BCL : BForm_4<16, 12, 0, 1, (outs), - (ins crbitrc:$bi, condbrtarget:$dst), - "bcl 12, $bi, $dst">; + (ins crbitrc:$BI, condbrtarget:$BD), + "bcl 12, $BI, $BD">; def BCLn : BForm_4<16, 4, 0, 1, (outs), - (ins crbitrc:$bi, condbrtarget:$dst), - "bcl 4, $bi, $dst">; + (ins crbitrc:$BI, condbrtarget:$BD), + "bcl 4, $BI, $BD">; def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, - (outs), (ins calltarget:$func), - "bl $func\n\tnop", IIC_BrB, []>; + (outs), (ins calltarget:$LI), + "bl $LI\n\tnop", IIC_BrB, []>; } } let Uses = [CTR, RM] in { @@ -1361,14 +1375,14 @@ Requires<[In32BitMode]>; let isCodeGenOnly = 1 in { - def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), + def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond), "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, []>; - def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi), - "bcctrl 12, $bi, 0", IIC_BrB, []>; - def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi), - "bcctrl 4, $bi, 0", IIC_BrB, []>; + def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI), + "bcctrl 12, $BI, 0", IIC_BrB, []>; + def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI), + "bcctrl 4, $BI, 0", IIC_BrB, []>; } } let Uses = [LR, RM] in { @@ -1376,41 +1390,41 @@ "blrl", IIC_BrB, []>; let isCodeGenOnly = 1 in { - def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins pred:$cond), + def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins (pred $BIBO, $CR):$cond), "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, []>; - def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$bi), - "bclrl 12, $bi, 0", IIC_BrB, []>; - def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$bi), - "bclrl 4, $bi, 0", IIC_BrB, []>; + def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$BI), + "bclrl 12, $BI, 0", IIC_BrB, []>; + def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$BI), + "bclrl 4, $BI, 0", IIC_BrB, []>; } } let Defs = [CTR], Uses = [CTR, RM] in { - def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$dst), - "bdzl $dst">; - def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$dst), - "bdnzl $dst">; - def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$dst), - "bdzla $dst">; - def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$dst), - "bdnzla $dst">; - def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$dst), - "bdzl+ $dst">; - def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$dst), - "bdnzl+ $dst">; - def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$dst), - "bdzla+ $dst">; - def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$dst), - "bdnzla+ $dst">; - def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$dst), - "bdzl- $dst">; - def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$dst), - "bdnzl- $dst">; - def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$dst), - "bdzla- $dst">; - def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$dst), - "bdnzla- $dst">; + def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$BD), + "bdzl $BD">; + def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$BD), + "bdnzl $BD">; + def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$BD), + "bdzla $BD">; + def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$BD), + "bdnzla $BD">; + def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$BD), + "bdzl+ $BD">; + def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$BD), + "bdnzl+ $BD">; + def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$BD), + "bdzla+ $BD">; + def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$BD), + "bdnzla+ $BD">; + def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$BD), + "bdzl- $BD">; + def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$BD), + "bdnzl- $BD">; + def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$BD), + "bdzla- $BD">; + def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$BD), + "bdnzla- $BD">; } let Defs = [CTR], Uses = [CTR, LR, RM] in { def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), @@ -1431,14 +1445,14 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in { // Convenient aliases for call instructions let Uses = [RM] in { - def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$func), - "bl $func", IIC_BrB, []>; // See Pat patterns below. - def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), - "bla $func", IIC_BrB, [(PPCcall_rm (i32 imm:$func))]>; + def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$LI), + "bl $LI", IIC_BrB, []>; // See Pat patterns below. + def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), + "bla $LI", IIC_BrB, [(PPCcall_rm (i32 imm:$LI))]>; def BL_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, - (outs), (ins calltarget:$func), - "bl $func\n\tnop", IIC_BrB, []>; + (outs), (ins calltarget:$LI), + "bl $LI\n\tnop", IIC_BrB, []>; } let Uses = [CTR, RM] in { let isPredicable = 1 in @@ -1469,8 +1483,8 @@ Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { def BCTRL_LWZinto_toc: XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), - (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, - [(PPCbctrl_load_toc iaddr:$src)]>, Requires<[In32BitMode]>; + (ins memri:$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, + [(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>; } @@ -1478,8 +1492,8 @@ Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in { def BCTRL_LWZinto_toc_RM: XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), - (ins memri:$src), "bctrl\n\tlwz 2, $src", IIC_BrB, - [(PPCbctrl_load_toc_rm iaddr:$src)]>, Requires<[In32BitMode]>; + (ins memri:$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, + [(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>; } @@ -1492,14 +1506,14 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in -def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$dst), - "b $dst", IIC_BrB, +def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$LI), + "b $LI", IIC_BrB, []>; let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in -def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), - "ba $dst", IIC_BrB, +def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI), + "ba $LI", IIC_BrB, []>; } @@ -1532,8 +1546,8 @@ // System call. let PPC970_Unit = 7 in { - def SC : SCForm<17, 1, (outs), (ins i32imm:$lev), - "sc $lev", IIC_BrB, [(PPCsc (i32 imm:$lev))]>; + def SC : SCForm<17, 1, (outs), (ins i32imm:$LEV), + "sc $LEV", IIC_BrB, [(PPCsc (i32 imm:$LEV))]>; } // Branch history rolling buffer. @@ -1543,57 +1557,57 @@ // The $dmy argument used for MFBHRBE is not needed; however, including // it avoids automatic generation of PPCFastISel::fastEmit_i(), which // interferes with necessary special handling (see PPCFastISel.cpp). -def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$rD), +def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$RT), (ins u10imm:$imm, u10imm:$dmy), - "mfbhrbe $rD, $imm", IIC_BrB, - [(set i32:$rD, + "mfbhrbe $RT, $imm", IIC_BrB, + [(set i32:$RT, (PPCmfbhrbe imm:$imm, imm:$dmy))]>, PPC970_DGroup_First; -def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm", - IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>, +def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$S), "rfebb $S", + IIC_BrB, [(PPCrfebb (i32 imm:$S))]>, PPC970_DGroup_Single; def : InstAlias<"rfebb", (RFEBB 1)>; // DCB* instructions. -def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", - IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, +def DCBA : DCB_Form<758, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcba $addr", + IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$addr)]>, PPC970_DGroup_Single; -def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", - IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, +def DCBI : DCB_Form<470, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbi $addr", + IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$addr)]>, PPC970_DGroup_Single; -def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst", - IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>, +def DCBST : DCB_Form<54, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbst $addr", + IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$addr)]>, PPC970_DGroup_Single; -def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst", - IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>, +def DCBZ : DCB_Form<1014, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbz $addr", + IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$addr)]>, PPC970_DGroup_Single; -def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", - IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, +def DCBZL : DCB_Form<1014, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzl $addr", + IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$addr)]>, PPC970_DGroup_Single; -def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, memrr:$dst), - "dcbf $dst, $TH", IIC_LdStDCBF, []>, +def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, (memrr $RA, $RB):$addr), + "dcbf $addr, $TH", IIC_LdStDCBF, []>, PPC970_DGroup_Single; let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { -def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst), - "dcbt $dst, $TH", IIC_LdStDCBF, []>, +def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr), + "dcbt $addr, $TH", IIC_LdStDCBF, []>, PPC970_DGroup_Single; -def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst), - "dcbtst $dst, $TH", IIC_LdStDCBF, []>, +def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr), + "dcbtst $addr, $TH", IIC_LdStDCBF, []>, PPC970_DGroup_Single; } // hasSideEffects = 0 -def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src), - "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>; -def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src), - "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; -def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), - "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; -def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src), - "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; +def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), + "icblc $CT, $addr", IIC_LdStStore>, Requires<[HasICBT]>; +def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), + "icblq. $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; +def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), + "icbt $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; +def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), + "icbtls $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; def : Pat<(int_ppc_dcbt xoaddr:$dst), (DCBT 0, xoaddr:$dst)>; @@ -1742,71 +1756,71 @@ // Instructions to support atomic operations let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { -def LBARX : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), - "lbarx $rD, $src", IIC_LdStLWARX, []>, +def LBARX : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lbarx $RST, $addr", IIC_LdStLWARX, []>, Requires<[HasPartwordAtomics]>; -def LHARX : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), - "lharx $rD, $src", IIC_LdStLWARX, []>, +def LHARX : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lharx $RST, $addr", IIC_LdStLWARX, []>, Requires<[HasPartwordAtomics]>; -def LWARX : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), - "lwarx $rD, $src", IIC_LdStLWARX, []>; +def LWARX : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lwarx $RST, $addr", IIC_LdStLWARX, []>; // Instructions to support lock versions of atomics // (EH=1 - see Power ISA 2.07 Book II 4.4.2) -def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$rD), (ins memrr:$src), - "lbarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, +def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lbarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm, Requires<[HasPartwordAtomics]>; -def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$rD), (ins memrr:$src), - "lharx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm, +def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lharx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm, Requires<[HasPartwordAtomics]>; -def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$rD), (ins memrr:$src), - "lwarx $rD, $src, 1", IIC_LdStLWARX, []>, isRecordForm; +def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lwarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm; // The atomic instructions use the destination register as well as the next one // or two registers in order (modulo 31). let hasExtraSrcRegAllocReq = 1 in -def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$rD), (ins gprc:$rA, u5imm:$FC), - "lwat $rD, $rA, $FC", IIC_LdStLoad>, +def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$RST), (ins gprc:$RA, u5imm:$RB), + "lwat $RST, $RA, $RB", IIC_LdStLoad>, Requires<[IsISA3_0]>; } let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { -def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$rS, memrr:$dst), - "stbcx. $rS, $dst", IIC_LdStSTWCX, []>, +def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), + "stbcx. $RST, $addr", IIC_LdStSTWCX, []>, isRecordForm, Requires<[HasPartwordAtomics]>; -def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$rS, memrr:$dst), - "sthcx. $rS, $dst", IIC_LdStSTWCX, []>, +def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), + "sthcx. $RST, $addr", IIC_LdStSTWCX, []>, isRecordForm, Requires<[HasPartwordAtomics]>; -def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$rS, memrr:$dst), - "stwcx. $rS, $dst", IIC_LdStSTWCX, []>, isRecordForm; +def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), + "stwcx. $RST, $addr", IIC_LdStSTWCX, []>, isRecordForm; } let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in -def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$rS, gprc:$rA, u5imm:$FC), - "stwat $rS, $rA, $FC", IIC_LdStStore>, +def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB), + "stwat $RST, $RA, $RB", IIC_LdStStore>, Requires<[IsISA3_0]>; let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; -def TWI : DForm_base<3, (outs), (ins u5imm:$to, gprc:$rA, s16imm:$imm, variable_ops), - "twi $to, $rA, $imm", IIC_IntTrapW, []>; -def TW : XForm_1<31, 4, (outs), (ins u5imm:$to, gprc:$rA, gprc:$rB, variable_ops), - "tw $to, $rA, $rB", IIC_IntTrapW, []>; -def TDI : DForm_base<2, (outs), (ins u5imm:$to, g8rc:$rA, s16imm:$imm, variable_ops), - "tdi $to, $rA, $imm", IIC_IntTrapD, []>; -def TD : XForm_1<31, 68, (outs), (ins u5imm:$to, g8rc:$rA, g8rc:$rB, variable_ops), - "td $to, $rA, $rB", IIC_IntTrapD, []>; +def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops), + "twi $RST, $RA, $D", IIC_IntTrapW, []>; +def TW : XForm_1<31, 4, (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB, variable_ops), + "tw $RST, $RA, $RB", IIC_IntTrapW, []>; +def TDI : DForm_base<2, (outs), (ins u5imm:$RST, g8rc:$RA, s16imm:$D, variable_ops), + "tdi $RST, $RA, $D", IIC_IntTrapD, []>; +def TD : XForm_1<31, 68, (outs), (ins u5imm:$RST, g8rc:$RA, g8rc:$RB, variable_ops), + "td $RST, $RA, $RB", IIC_IntTrapD, []>; -def POPCNTB : XForm_11<31, 122, (outs gprc:$rA), (ins gprc:$rS), - "popcntb $rA, $rS", IIC_IntGeneral, - [(set i32:$rA, (int_ppc_popcntb i32:$rS))]>; +def POPCNTB : XForm_11<31, 122, (outs gprc:$RA), (ins gprc:$RST), + "popcntb $RA, $RST", IIC_IntGeneral, + [(set i32:$RA, (int_ppc_popcntb i32:$RST))]>; //===----------------------------------------------------------------------===// // PPC32 Load Instructions. @@ -1814,102 +1828,102 @@ // Unindexed (r+i) Loads. let PPC970_Unit = 2 in { -def LBZ : DForm_1<34, (outs gprc:$rD), (ins memri:$src), - "lbz $rD, $src", IIC_LdStLoad, - [(set i32:$rD, (zextloadi8 DForm:$src))]>, ZExt32To64, +def LBZ : DForm_1<34, (outs gprc:$RST), (ins memri:$addr), + "lbz $RST, $addr", IIC_LdStLoad, + [(set i32:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64, SExt32To64; -def LHA : DForm_1<42, (outs gprc:$rD), (ins memri:$src), - "lha $rD, $src", IIC_LdStLHA, - [(set i32:$rD, (sextloadi16 DForm:$src))]>, +def LHA : DForm_1<42, (outs gprc:$RST), (ins memri:$addr), + "lha $RST, $addr", IIC_LdStLHA, + [(set i32:$RST, (sextloadi16 DForm:$addr))]>, PPC970_DGroup_Cracked, SExt32To64; -def LHZ : DForm_1<40, (outs gprc:$rD), (ins memri:$src), - "lhz $rD, $src", IIC_LdStLoad, - [(set i32:$rD, (zextloadi16 DForm:$src))]>, ZExt32To64, +def LHZ : DForm_1<40, (outs gprc:$RST), (ins memri:$addr), + "lhz $RST, $addr", IIC_LdStLoad, + [(set i32:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64, SExt32To64; -def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src), - "lwz $rD, $src", IIC_LdStLoad, - [(set i32:$rD, (load DForm:$src))]>, ZExt32To64; +def LWZ : DForm_1<32, (outs gprc:$RST), (ins memri:$addr), + "lwz $RST, $addr", IIC_LdStLoad, + [(set i32:$RST, (load DForm:$addr))]>, ZExt32To64; let Predicates = [HasFPU] in { -def LFS : DForm_1<48, (outs f4rc:$rD), (ins memri:$src), - "lfs $rD, $src", IIC_LdStLFD, - [(set f32:$rD, (load DForm:$src))]>; -def LFD : DForm_1<50, (outs f8rc:$rD), (ins memri:$src), - "lfd $rD, $src", IIC_LdStLFD, - [(set f64:$rD, (load DForm:$src))]>; +def LFS : DForm_1<48, (outs f4rc:$RST), (ins memri:$addr), + "lfs $RST, $addr", IIC_LdStLFD, + [(set f32:$RST, (load DForm:$addr))]>; +def LFD : DForm_1<50, (outs f8rc:$RST), (ins memri:$addr), + "lfd $RST, $addr", IIC_LdStLFD, + [(set f64:$RST, (load DForm:$addr))]>; } // Unindexed (r+i) Loads with Update (preinc). let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { -def LBZU : DForm_1<35, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), - "lbzu $rD, $addr", IIC_LdStLoadUpd, +def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr), + "lbzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LHAU : DForm_1<43, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), - "lhau $rD, $addr", IIC_LdStLHAU, +def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr), + "lhau $RST, $addr", IIC_LdStLHAU, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LHZU : DForm_1<41, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), - "lhzu $rD, $addr", IIC_LdStLoadUpd, +def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr), + "lhzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LWZU : DForm_1<33, (outs gprc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), - "lwzu $rD, $addr", IIC_LdStLoadUpd, +def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr), + "lwzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; let Predicates = [HasFPU] in { -def LFSU : DForm_1<49, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), - "lfsu $rD, $addr", IIC_LdStLFDU, +def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr), + "lfsu $RST, $addr", IIC_LdStLFDU, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; -def LFDU : DForm_1<51, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), - "lfdu $rD, $addr", IIC_LdStLFDU, +def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins memri:$addr), + "lfdu $RST, $addr", IIC_LdStLFDU, []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; } // Indexed (r+r) Loads with Update (preinc). -def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$rD, ptr_rc_nor0:$ea_result), - (ins memrr:$addr), - "lbzux $rD, $addr", IIC_LdStLoadUpdX, +def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, ptr_rc_nor0:$ea_result), + (ins (memrr $RA, $RB):$addr), + "lbzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, NoEncode<"$ea_result">; -def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$rD, ptr_rc_nor0:$ea_result), - (ins memrr:$addr), - "lhaux $rD, $addr", IIC_LdStLHAUX, +def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, ptr_rc_nor0:$ea_result), + (ins (memrr $RA, $RB):$addr), + "lhaux $RST, $addr", IIC_LdStLHAUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, NoEncode<"$ea_result">; -def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$rD, ptr_rc_nor0:$ea_result), - (ins memrr:$addr), - "lhzux $rD, $addr", IIC_LdStLoadUpdX, +def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, ptr_rc_nor0:$ea_result), + (ins (memrr $RA, $RB):$addr), + "lhzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, NoEncode<"$ea_result">; -def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$rD, ptr_rc_nor0:$ea_result), - (ins memrr:$addr), - "lwzux $rD, $addr", IIC_LdStLoadUpdX, +def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, ptr_rc_nor0:$ea_result), + (ins (memrr $RA, $RB):$addr), + "lwzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, NoEncode<"$ea_result">; let Predicates = [HasFPU] in { -def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$rD, ptr_rc_nor0:$ea_result), - (ins memrr:$addr), - "lfsux $rD, $addr", IIC_LdStLFDUX, +def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), + (ins (memrr $RA, $RB):$addr), + "lfsux $RST, $addr", IIC_LdStLFDUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, NoEncode<"$ea_result">; -def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$rD, ptr_rc_nor0:$ea_result), - (ins memrr:$addr), - "lfdux $rD, $addr", IIC_LdStLFDUX, +def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), + (ins (memrr $RA, $RB):$addr), + "lfdux $RST, $addr", IIC_LdStLFDUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, NoEncode<"$ea_result">; } @@ -1919,49 +1933,49 @@ // Indexed (r+r) Loads. // let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { -def LBZX : XForm_1_memOp<31, 87, (outs gprc:$rD), (ins memrr:$src), - "lbzx $rD, $src", IIC_LdStLoad, - [(set i32:$rD, (zextloadi8 XForm:$src))]>, ZExt32To64, +def LBZX : XForm_1_memOp<31, 87, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lbzx $RST, $addr", IIC_LdStLoad, + [(set i32:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64, SExt32To64; -def LHAX : XForm_1_memOp<31, 343, (outs gprc:$rD), (ins memrr:$src), - "lhax $rD, $src", IIC_LdStLHA, - [(set i32:$rD, (sextloadi16 XForm:$src))]>, +def LHAX : XForm_1_memOp<31, 343, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lhax $RST, $addr", IIC_LdStLHA, + [(set i32:$RST, (sextloadi16 XForm:$addr))]>, PPC970_DGroup_Cracked, SExt32To64; -def LHZX : XForm_1_memOp<31, 279, (outs gprc:$rD), (ins memrr:$src), - "lhzx $rD, $src", IIC_LdStLoad, - [(set i32:$rD, (zextloadi16 XForm:$src))]>, ZExt32To64, +def LHZX : XForm_1_memOp<31, 279, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lhzx $RST, $addr", IIC_LdStLoad, + [(set i32:$RST, (zextloadi16 XForm:$addr))]>, ZExt32To64, SExt32To64; -def LWZX : XForm_1_memOp<31, 23, (outs gprc:$rD), (ins memrr:$src), - "lwzx $rD, $src", IIC_LdStLoad, - [(set i32:$rD, (load XForm:$src))]>, ZExt32To64; -def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$rD), (ins memrr:$src), - "lhbrx $rD, $src", IIC_LdStLoad, - [(set i32:$rD, (PPClbrx ForceXForm:$src, i16))]>, ZExt32To64; -def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$rD), (ins memrr:$src), - "lwbrx $rD, $src", IIC_LdStLoad, - [(set i32:$rD, (PPClbrx ForceXForm:$src, i32))]>, ZExt32To64; +def LWZX : XForm_1_memOp<31, 23, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lwzx $RST, $addr", IIC_LdStLoad, + [(set i32:$RST, (load XForm:$addr))]>, ZExt32To64; +def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lhbrx $RST, $addr", IIC_LdStLoad, + [(set i32:$RST, (PPClbrx ForceXForm:$addr, i16))]>, ZExt32To64; +def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lwbrx $RST, $addr", IIC_LdStLoad, + [(set i32:$RST, (PPClbrx ForceXForm:$addr, i32))]>, ZExt32To64; let Predicates = [HasFPU] in { -def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$frD), (ins memrr:$src), - "lfsx $frD, $src", IIC_LdStLFD, - [(set f32:$frD, (load XForm:$src))]>; -def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$frD), (ins memrr:$src), - "lfdx $frD, $src", IIC_LdStLFD, - [(set f64:$frD, (load XForm:$src))]>; +def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$RST), (ins (memrr $RA, $RB):$addr), + "lfsx $RST, $addr", IIC_LdStLFD, + [(set f32:$RST, (load XForm:$addr))]>; +def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), + "lfdx $RST, $addr", IIC_LdStLFD, + [(set f64:$RST, (load XForm:$addr))]>; -def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$frD), (ins memrr:$src), - "lfiwax $frD, $src", IIC_LdStLFD, - [(set f64:$frD, (PPClfiwax ForceXForm:$src))]>; -def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$frD), (ins memrr:$src), - "lfiwzx $frD, $src", IIC_LdStLFD, - [(set f64:$frD, (PPClfiwzx ForceXForm:$src))]>; +def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), + "lfiwax $RST, $addr", IIC_LdStLFD, + [(set f64:$RST, (PPClfiwax ForceXForm:$addr))]>; +def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), + "lfiwzx $RST, $addr", IIC_LdStLFD, + [(set f64:$RST, (PPClfiwzx ForceXForm:$addr))]>; } } // Load Multiple let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in -def LMW : DForm_1<46, (outs gprc:$rD), (ins memri:$src), - "lmw $rD, $src", IIC_LdStLMW, []>; +def LMW : DForm_1<46, (outs gprc:$RST), (ins memri:$src), + "lmw $RST, $src", IIC_LdStLMW, []>; //===----------------------------------------------------------------------===// // PPC32 Store Instructions. @@ -1969,42 +1983,42 @@ // Unindexed (r+i) Stores. let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { -def STB : DForm_1<38, (outs), (ins gprc:$rS, memri:$dst), - "stb $rS, $dst", IIC_LdStStore, - [(truncstorei8 i32:$rS, DForm:$dst)]>; -def STH : DForm_1<44, (outs), (ins gprc:$rS, memri:$dst), - "sth $rS, $dst", IIC_LdStStore, - [(truncstorei16 i32:$rS, DForm:$dst)]>; -def STW : DForm_1<36, (outs), (ins gprc:$rS, memri:$dst), - "stw $rS, $dst", IIC_LdStStore, - [(store i32:$rS, DForm:$dst)]>; +def STB : DForm_1<38, (outs), (ins gprc:$RST, memri:$dst), + "stb $RST, $dst", IIC_LdStStore, + [(truncstorei8 i32:$RST, DForm:$dst)]>; +def STH : DForm_1<44, (outs), (ins gprc:$RST, memri:$dst), + "sth $RST, $dst", IIC_LdStStore, + [(truncstorei16 i32:$RST, DForm:$dst)]>; +def STW : DForm_1<36, (outs), (ins gprc:$RST, memri:$dst), + "stw $RST, $dst", IIC_LdStStore, + [(store i32:$RST, DForm:$dst)]>; let Predicates = [HasFPU] in { -def STFS : DForm_1<52, (outs), (ins f4rc:$rS, memri:$dst), - "stfs $rS, $dst", IIC_LdStSTFD, - [(store f32:$rS, DForm:$dst)]>; -def STFD : DForm_1<54, (outs), (ins f8rc:$rS, memri:$dst), - "stfd $rS, $dst", IIC_LdStSTFD, - [(store f64:$rS, DForm:$dst)]>; +def STFS : DForm_1<52, (outs), (ins f4rc:$RST, memri:$dst), + "stfs $RST, $dst", IIC_LdStSTFD, + [(store f32:$RST, DForm:$dst)]>; +def STFD : DForm_1<54, (outs), (ins f8rc:$RST, memri:$dst), + "stfd $RST, $dst", IIC_LdStSTFD, + [(store f64:$RST, DForm:$dst)]>; } } // Unindexed (r+i) Stores with Update (preinc). let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { -def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), - "stbu $rS, $dst", IIC_LdStSTU, []>, +def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, memri:$dst), + "stbu $RST, $dst", IIC_LdStSTU, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; -def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), - "sthu $rS, $dst", IIC_LdStSTU, []>, +def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, memri:$dst), + "sthu $RST, $dst", IIC_LdStSTU, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; -def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$rS, memri:$dst), - "stwu $rS, $dst", IIC_LdStSTU, []>, +def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, memri:$dst), + "stwu $RST, $dst", IIC_LdStSTU, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; let Predicates = [HasFPU] in { -def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$rS, memri:$dst), - "stfsu $rS, $dst", IIC_LdStSTFDU, []>, +def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, memri:$dst), + "stfsu $RST, $dst", IIC_LdStSTFDU, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; -def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$rS, memri:$dst), - "stfdu $rS, $dst", IIC_LdStSTFDU, []>, +def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, memri:$dst), + "stfdu $RST, $dst", IIC_LdStSTFDU, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; } } @@ -2025,73 +2039,73 @@ // Indexed (r+r) Stores. let PPC970_Unit = 2 in { -def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$rS, memrr:$dst), - "stbx $rS, $dst", IIC_LdStStore, - [(truncstorei8 i32:$rS, XForm:$dst)]>, +def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), + "stbx $RST, $addr", IIC_LdStStore, + [(truncstorei8 i32:$RST, XForm:$addr)]>, PPC970_DGroup_Cracked; -def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$rS, memrr:$dst), - "sthx $rS, $dst", IIC_LdStStore, - [(truncstorei16 i32:$rS, XForm:$dst)]>, +def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), + "sthx $RST, $addr", IIC_LdStStore, + [(truncstorei16 i32:$RST, XForm:$addr)]>, PPC970_DGroup_Cracked; -def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$rS, memrr:$dst), - "stwx $rS, $dst", IIC_LdStStore, - [(store i32:$rS, XForm:$dst)]>, +def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), + "stwx $RST, $addr", IIC_LdStStore, + [(store i32:$RST, XForm:$addr)]>, PPC970_DGroup_Cracked; -def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$rS, memrr:$dst), - "sthbrx $rS, $dst", IIC_LdStStore, - [(PPCstbrx i32:$rS, ForceXForm:$dst, i16)]>, +def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), + "sthbrx $RST, $addr", IIC_LdStStore, + [(PPCstbrx i32:$RST, ForceXForm:$addr, i16)]>, PPC970_DGroup_Cracked; -def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$rS, memrr:$dst), - "stwbrx $rS, $dst", IIC_LdStStore, - [(PPCstbrx i32:$rS, ForceXForm:$dst, i32)]>, +def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), + "stwbrx $RST, $addr", IIC_LdStStore, + [(PPCstbrx i32:$RST, ForceXForm:$addr, i32)]>, PPC970_DGroup_Cracked; let Predicates = [HasFPU] in { -def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$frS, memrr:$dst), - "stfiwx $frS, $dst", IIC_LdStSTFD, - [(PPCstfiwx f64:$frS, ForceXForm:$dst)]>; +def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), + "stfiwx $RST, $addr", IIC_LdStSTFD, + [(PPCstfiwx f64:$RST, ForceXForm:$addr)]>; -def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$frS, memrr:$dst), - "stfsx $frS, $dst", IIC_LdStSTFD, - [(store f32:$frS, XForm:$dst)]>; -def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$frS, memrr:$dst), - "stfdx $frS, $dst", IIC_LdStSTFD, - [(store f64:$frS, XForm:$dst)]>; +def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$RST, (memrr $RA, $RB):$addr), + "stfsx $RST, $addr", IIC_LdStSTFD, + [(store f32:$RST, XForm:$addr)]>; +def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), + "stfdx $RST, $addr", IIC_LdStSTFD, + [(store f64:$RST, XForm:$addr)]>; } } // Indexed (r+r) Stores with Update (preinc). let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), - (ins gprc:$rS, memrr:$dst), - "stbux $rS, $dst", IIC_LdStSTUX, []>, - RegConstraint<"$dst.ptrreg = $ea_res">, + (ins gprc:$RST, (memrr $RA, $RB):$addr), + "stbux $RST, $addr", IIC_LdStSTUX, []>, + RegConstraint<"$addr.ptrreg = $ea_res">, NoEncode<"$ea_res">, PPC970_DGroup_Cracked; def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), - (ins gprc:$rS, memrr:$dst), - "sthux $rS, $dst", IIC_LdStSTUX, []>, - RegConstraint<"$dst.ptrreg = $ea_res">, + (ins gprc:$RST, (memrr $RA, $RB):$addr), + "sthux $RST, $addr", IIC_LdStSTUX, []>, + RegConstraint<"$addr.ptrreg = $ea_res">, NoEncode<"$ea_res">, PPC970_DGroup_Cracked; def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), - (ins gprc:$rS, memrr:$dst), - "stwux $rS, $dst", IIC_LdStSTUX, []>, - RegConstraint<"$dst.ptrreg = $ea_res">, + (ins gprc:$RST, (memrr $RA, $RB):$addr), + "stwux $RST, $addr", IIC_LdStSTUX, []>, + RegConstraint<"$addr.ptrreg = $ea_res">, NoEncode<"$ea_res">, PPC970_DGroup_Cracked; let Predicates = [HasFPU] in { def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), - (ins f4rc:$rS, memrr:$dst), - "stfsux $rS, $dst", IIC_LdStSTFDU, []>, - RegConstraint<"$dst.ptrreg = $ea_res">, + (ins f4rc:$RST, (memrr $RA, $RB):$addr), + "stfsux $RST, $addr", IIC_LdStSTFDU, []>, + RegConstraint<"$addr.ptrreg = $ea_res">, NoEncode<"$ea_res">, PPC970_DGroup_Cracked; def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), - (ins f8rc:$rS, memrr:$dst), - "stfdux $rS, $dst", IIC_LdStSTFDU, []>, - RegConstraint<"$dst.ptrreg = $ea_res">, + (ins f8rc:$RST, (memrr $RA, $RB):$addr), + "stfdux $RST, $addr", IIC_LdStSTFDU, []>, + RegConstraint<"$addr.ptrreg = $ea_res">, NoEncode<"$ea_res">, PPC970_DGroup_Cracked; } @@ -2115,8 +2129,8 @@ // Store Multiple let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in -def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst), - "stmw $rS, $dst", IIC_LdStLMW, []>; +def STMW : DForm_1<47, (outs), (ins gprc:$RST, memri:$dst), + "stmw $RST, $dst", IIC_LdStLMW, []>; def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L), "sync $L", IIC_LdStSync, []>; @@ -2151,43 +2165,43 @@ // let PPC970_Unit = 1 in { // FXU Operations. -def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm), - "addi $rD, $rA, $imm", IIC_IntSimple, - [(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>; +def ADDI : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D), + "addi $RST, $RA, $D", IIC_IntSimple, + [(set i32:$RST, (add i32:$RA, imm32SExt16:$D))]>; let BaseName = "addic" in { let Defs = [CARRY] in -def ADDIC : DForm_2<12, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), - "addic $rD, $rA, $imm", IIC_IntGeneral, - [(set i32:$rD, (addc i32:$rA, imm32SExt16:$imm))]>, +def ADDIC : DForm_2<12, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), + "addic $RST, $RA, $D", IIC_IntGeneral, + [(set i32:$RST, (addc i32:$RA, imm32SExt16:$D))]>, RecFormRel, PPC970_DGroup_Cracked; let Defs = [CARRY, CR0] in -def ADDIC_rec : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), - "addic. $rD, $rA, $imm", IIC_IntGeneral, +def ADDIC_rec : DForm_2<13, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), + "addic. $RST, $RA, $D", IIC_IntGeneral, []>, isRecordForm, RecFormRel; } -def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s17imm:$imm), - "addis $rD, $rA, $imm", IIC_IntSimple, - [(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>; +def ADDIS : DForm_2<15, (outs gprc:$RST), (ins gprc_nor0:$RA, s17imm:$D), + "addis $RST, $RA, $D", IIC_IntSimple, + [(set i32:$RST, (add i32:$RA, imm16ShiftedSExt:$D))]>; let isCodeGenOnly = 1 in -def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym), - "la $rD, $sym($rA)", IIC_IntGeneral, - [(set i32:$rD, (add i32:$rA, - (PPClo tglobaladdr:$sym, 0)))]>; -def MULLI : DForm_2< 7, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), - "mulli $rD, $rA, $imm", IIC_IntMulLI, - [(set i32:$rD, (mul i32:$rA, imm32SExt16:$imm))]>; +def LA : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D), + "la $RST, $D($RA)", IIC_IntGeneral, + [(set i32:$RST, (add i32:$RA, + (PPClo tglobaladdr:$D, 0)))]>; +def MULLI : DForm_2< 7, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), + "mulli $RST, $RA, $D", IIC_IntMulLI, + [(set i32:$RST, (mul i32:$RA, imm32SExt16:$D))]>; let Defs = [CARRY] in -def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm), - "subfic $rD, $rA, $imm", IIC_IntGeneral, - [(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>; +def SUBFIC : DForm_2< 8, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), + "subfic $RST, $RA, $D", IIC_IntGeneral, + [(set i32:$RST, (subc imm32SExt16:$D, i32:$RA))]>; let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { - def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm), - "li $rD, $imm", IIC_IntSimple, - [(set i32:$rD, imm32SExt16:$imm)]>, SExt32To64; - def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s17imm:$imm), - "lis $rD, $imm", IIC_IntSimple, - [(set i32:$rD, imm16ShiftedSExt:$imm)]>, SExt32To64; + def LI : DForm_2_r0<14, (outs gprc:$RST), (ins s16imm:$D), + "li $RST, $D", IIC_IntSimple, + [(set i32:$RST, imm32SExt16:$D)]>, SExt32To64; + def LIS : DForm_2_r0<15, (outs gprc:$RST), (ins s17imm:$D), + "lis $RST, $D", IIC_IntSimple, + [(set i32:$RST, imm16ShiftedSExt:$D)]>, SExt32To64; } } @@ -2196,27 +2210,27 @@ let PPC970_Unit = 1 in { // FXU Operations. let Defs = [CR0] in { -def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), - "andi. $dst, $src1, $src2", IIC_IntGeneral, - [(set i32:$dst, (and i32:$src1, immZExt16:$src2))]>, +def ANDI_rec : DForm_4<28, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), + "andi. $RA, $RST, $D", IIC_IntGeneral, + [(set i32:$RA, (and i32:$RST, immZExt16:$D))]>, isRecordForm, ZExt32To64, SExt32To64; -def ANDIS_rec : DForm_4<29, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), - "andis. $dst, $src1, $src2", IIC_IntGeneral, - [(set i32:$dst, (and i32:$src1, imm16ShiftedZExt:$src2))]>, +def ANDIS_rec : DForm_4<29, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), + "andis. $RA, $RST, $D", IIC_IntGeneral, + [(set i32:$RA, (and i32:$RST, imm16ShiftedZExt:$D))]>, isRecordForm, ZExt32To64; } -def ORI : DForm_4<24, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), - "ori $dst, $src1, $src2", IIC_IntSimple, - [(set i32:$dst, (or i32:$src1, immZExt16:$src2))]>; -def ORIS : DForm_4<25, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), - "oris $dst, $src1, $src2", IIC_IntSimple, - [(set i32:$dst, (or i32:$src1, imm16ShiftedZExt:$src2))]>; -def XORI : DForm_4<26, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), - "xori $dst, $src1, $src2", IIC_IntSimple, - [(set i32:$dst, (xor i32:$src1, immZExt16:$src2))]>; -def XORIS : DForm_4<27, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2), - "xoris $dst, $src1, $src2", IIC_IntSimple, - [(set i32:$dst, (xor i32:$src1, imm16ShiftedZExt:$src2))]>; +def ORI : DForm_4<24, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), + "ori $RA, $RST, $D", IIC_IntSimple, + [(set i32:$RA, (or i32:$RST, immZExt16:$D))]>; +def ORIS : DForm_4<25, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), + "oris $RA, $RST, $D", IIC_IntSimple, + [(set i32:$RA, (or i32:$RST, imm16ShiftedZExt:$D))]>; +def XORI : DForm_4<26, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), + "xori $RA, $RST, $D", IIC_IntSimple, + [(set i32:$RA, (xor i32:$RST, immZExt16:$D))]>; +def XORIS : DForm_4<27, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), + "xoris $RA, $RST, $D", IIC_IntSimple, + [(set i32:$RA, (xor i32:$RST, imm16ShiftedZExt:$D))]>; def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, []>; @@ -2229,57 +2243,57 @@ } let isCompare = 1, hasSideEffects = 0 in { - def CMPWI : DForm_5_ext<11, (outs crrc:$crD), (ins gprc:$rA, s16imm:$imm), - "cmpwi $crD, $rA, $imm", IIC_IntCompare>; - def CMPLWI : DForm_6_ext<10, (outs crrc:$dst), (ins gprc:$src1, u16imm:$src2), - "cmplwi $dst, $src1, $src2", IIC_IntCompare>; + def CMPWI : DForm_5_ext<11, (outs crrc:$BF), (ins gprc:$RA, s16imm:$D), + "cmpwi $BF, $RA, $D", IIC_IntCompare>; + def CMPLWI : DForm_6_ext<10, (outs crrc:$BF), (ins gprc:$RA, u16imm:$D), + "cmplwi $BF, $RA, $D", IIC_IntCompare>; def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), - (ins u1imm:$L, gprc:$rA, gprc:$rB), - "cmprb $BF, $L, $rA, $rB", IIC_IntCompare, []>, + (ins u1imm:$L, gprc:$RA, gprc:$RB), + "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>, Requires<[IsISA3_0]>; } } let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. let isCommutable = 1 in { -defm NAND : XForm_6r<31, 476, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), - "nand", "$rA, $rS, $rB", IIC_IntSimple, - [(set i32:$rA, (not (and i32:$rS, i32:$rB)))]>; -defm AND : XForm_6r<31, 28, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), - "and", "$rA, $rS, $rB", IIC_IntSimple, - [(set i32:$rA, (and i32:$rS, i32:$rB))]>; +defm NAND : XForm_6r<31, 476, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), + "nand", "$RA, $RST, $RB", IIC_IntSimple, + [(set i32:$RA, (not (and i32:$RST, i32:$RB)))]>; +defm AND : XForm_6r<31, 28, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), + "and", "$RA, $RST, $RB", IIC_IntSimple, + [(set i32:$RA, (and i32:$RST, i32:$RB))]>; } // isCommutable -defm ANDC : XForm_6r<31, 60, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), - "andc", "$rA, $rS, $rB", IIC_IntSimple, - [(set i32:$rA, (and i32:$rS, (not i32:$rB)))]>; +defm ANDC : XForm_6r<31, 60, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), + "andc", "$RA, $RST, $RB", IIC_IntSimple, + [(set i32:$RA, (and i32:$RST, (not i32:$RB)))]>; let isCommutable = 1 in { -defm OR : XForm_6r<31, 444, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), - "or", "$rA, $rS, $rB", IIC_IntSimple, - [(set i32:$rA, (or i32:$rS, i32:$rB))]>; -defm NOR : XForm_6r<31, 124, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), - "nor", "$rA, $rS, $rB", IIC_IntSimple, - [(set i32:$rA, (not (or i32:$rS, i32:$rB)))]>; +defm OR : XForm_6r<31, 444, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), + "or", "$RA, $RST, $RB", IIC_IntSimple, + [(set i32:$RA, (or i32:$RST, i32:$RB))]>; +defm NOR : XForm_6r<31, 124, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), + "nor", "$RA, $RST, $RB", IIC_IntSimple, + [(set i32:$RA, (not (or i32:$RST, i32:$RB)))]>; } // isCommutable -defm ORC : XForm_6r<31, 412, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), - "orc", "$rA, $rS, $rB", IIC_IntSimple, - [(set i32:$rA, (or i32:$rS, (not i32:$rB)))]>; +defm ORC : XForm_6r<31, 412, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), + "orc", "$RA, $RST, $RB", IIC_IntSimple, + [(set i32:$RA, (or i32:$RST, (not i32:$RB)))]>; let isCommutable = 1 in { -defm EQV : XForm_6r<31, 284, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), - "eqv", "$rA, $rS, $rB", IIC_IntSimple, - [(set i32:$rA, (not (xor i32:$rS, i32:$rB)))]>; -defm XOR : XForm_6r<31, 316, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), - "xor", "$rA, $rS, $rB", IIC_IntSimple, - [(set i32:$rA, (xor i32:$rS, i32:$rB))]>; +defm EQV : XForm_6r<31, 284, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), + "eqv", "$RA, $RST, $RB", IIC_IntSimple, + [(set i32:$RA, (not (xor i32:$RST, i32:$RB)))]>; +defm XOR : XForm_6r<31, 316, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), + "xor", "$RA, $RST, $RB", IIC_IntSimple, + [(set i32:$RA, (xor i32:$RST, i32:$RB))]>; } // isCommutable -defm SLW : XForm_6r<31, 24, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), - "slw", "$rA, $rS, $rB", IIC_IntGeneral, - [(set i32:$rA, (PPCshl i32:$rS, i32:$rB))]>, ZExt32To64; -defm SRW : XForm_6r<31, 536, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), - "srw", "$rA, $rS, $rB", IIC_IntGeneral, - [(set i32:$rA, (PPCsrl i32:$rS, i32:$rB))]>, ZExt32To64; -defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), - "sraw", "$rA, $rS, $rB", IIC_IntShift, - [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>, SExt32To64; +defm SLW : XForm_6r<31, 24, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), + "slw", "$RA, $RST, $RB", IIC_IntGeneral, + [(set i32:$RA, (PPCshl i32:$RST, i32:$RB))]>, ZExt32To64; +defm SRW : XForm_6r<31, 536, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), + "srw", "$RA, $RST, $RB", IIC_IntGeneral, + [(set i32:$RA, (PPCsrl i32:$RST, i32:$RB))]>, ZExt32To64; +defm SRAW : XForm_6rc<31, 792, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), + "sraw", "$RA, $RST, $RB", IIC_IntShift, + [(set i32:$RA, (PPCsra i32:$RST, i32:$RB))]>, SExt32To64; } def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>; @@ -2292,109 +2306,109 @@ let PPC970_Unit = 1 in { // FXU Operations. let hasSideEffects = 0 in { -defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH), - "srawi", "$rA, $rS, $SH", IIC_IntShift, - [(set i32:$rA, (sra i32:$rS, (i32 imm:$SH)))]>, +defm SRAWI : XForm_10rc<31, 824, (outs gprc:$RA), (ins gprc:$RST, u5imm:$RB), + "srawi", "$RA, $RST, $RB", IIC_IntShift, + [(set i32:$RA, (sra i32:$RST, (i32 imm:$RB)))]>, SExt32To64; -defm CNTLZW : XForm_11r<31, 26, (outs gprc:$rA), (ins gprc:$rS), - "cntlzw", "$rA, $rS", IIC_IntGeneral, - [(set i32:$rA, (ctlz i32:$rS))]>, ZExt32To64; -defm CNTTZW : XForm_11r<31, 538, (outs gprc:$rA), (ins gprc:$rS), - "cnttzw", "$rA, $rS", IIC_IntGeneral, - [(set i32:$rA, (cttz i32:$rS))]>, Requires<[IsISA3_0]>, +defm CNTLZW : XForm_11r<31, 26, (outs gprc:$RA), (ins gprc:$RST), + "cntlzw", "$RA, $RST", IIC_IntGeneral, + [(set i32:$RA, (ctlz i32:$RST))]>, ZExt32To64; +defm CNTTZW : XForm_11r<31, 538, (outs gprc:$RA), (ins gprc:$RST), + "cnttzw", "$RA, $RST", IIC_IntGeneral, + [(set i32:$RA, (cttz i32:$RST))]>, Requires<[IsISA3_0]>, ZExt32To64; -defm EXTSB : XForm_11r<31, 954, (outs gprc:$rA), (ins gprc:$rS), - "extsb", "$rA, $rS", IIC_IntSimple, - [(set i32:$rA, (sext_inreg i32:$rS, i8))]>, SExt32To64; -defm EXTSH : XForm_11r<31, 922, (outs gprc:$rA), (ins gprc:$rS), - "extsh", "$rA, $rS", IIC_IntSimple, - [(set i32:$rA, (sext_inreg i32:$rS, i16))]>, SExt32To64; +defm EXTSB : XForm_11r<31, 954, (outs gprc:$RA), (ins gprc:$RST), + "extsb", "$RA, $RST", IIC_IntSimple, + [(set i32:$RA, (sext_inreg i32:$RST, i8))]>, SExt32To64; +defm EXTSH : XForm_11r<31, 922, (outs gprc:$RA), (ins gprc:$RST), + "extsh", "$RA, $RST", IIC_IntSimple, + [(set i32:$RA, (sext_inreg i32:$RST, i16))]>, SExt32To64; let isCommutable = 1 in -def CMPB : XForm_6<31, 508, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB), - "cmpb $rA, $rS, $rB", IIC_IntGeneral, - [(set i32:$rA, (PPCcmpb i32:$rS, i32:$rB))]>; +def CMPB : XForm_6<31, 508, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), + "cmpb $RA, $RST, $RB", IIC_IntGeneral, + [(set i32:$RA, (PPCcmpb i32:$RST, i32:$RB))]>; } let isCompare = 1, hasSideEffects = 0 in { - def CMPW : XForm_16_ext<31, 0, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), - "cmpw $crD, $rA, $rB", IIC_IntCompare>; - def CMPLW : XForm_16_ext<31, 32, (outs crrc:$crD), (ins gprc:$rA, gprc:$rB), - "cmplw $crD, $rA, $rB", IIC_IntCompare>; + def CMPW : XForm_16_ext<31, 0, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB), + "cmpw $BF, $RA, $RB", IIC_IntCompare>; + def CMPLW : XForm_16_ext<31, 32, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB), + "cmplw $BF, $RA, $RB", IIC_IntCompare>; } } let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in { - def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), - "fcmpu $crD, $fA, $fB", IIC_FPCompare>; - def FCMPOS : XForm_17<63, 32, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB), - "fcmpo $crD, $fA, $fB", IIC_FPCompare>; + def FCMPUS : XForm_17<63, 0, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB), + "fcmpu $BF, $RA, $RB", IIC_FPCompare>; + def FCMPOS : XForm_17<63, 32, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB), + "fcmpo $BF, $RA, $RB", IIC_FPCompare>; let Interpretation64Bit = 1, isCodeGenOnly = 1 in { - def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), - "fcmpu $crD, $fA, $fB", IIC_FPCompare>; - def FCMPOD : XForm_17<63, 32, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), - "fcmpo $crD, $fA, $fB", IIC_FPCompare>; + def FCMPUD : XForm_17<63, 0, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), + "fcmpu $BF, $RA, $RB", IIC_FPCompare>; + def FCMPOD : XForm_17<63, 32, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), + "fcmpo $BF, $RA, $RB", IIC_FPCompare>; } } -def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), - "ftdiv $crD, $fA, $fB", IIC_FPCompare>; -def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB), - "ftsqrt $crD, $fB", IIC_FPCompare, - [(set i32:$crD, (PPCftsqrt f64:$fB))]>; +def FTDIV: XForm_17<63, 128, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), + "ftdiv $BF, $RA, $RB", IIC_FPCompare>; +def FTSQRT: XForm_17a<63, 160, (outs crrc:$BF), (ins f8rc:$RB), + "ftsqrt $BF, $RB", IIC_FPCompare, + [(set i32:$BF, (PPCftsqrt f64:$RB))]>; let mayRaiseFPException = 1, hasSideEffects = 0 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in - defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), - "frin", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (any_fround f64:$frB))]>; - defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), - "frin", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (any_fround f32:$frB))]>; + defm FRIND : XForm_26r<63, 392, (outs f8rc:$RST), (ins f8rc:$RB), + "frin", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (any_fround f64:$RB))]>; + defm FRINS : XForm_26r<63, 392, (outs f4rc:$RST), (ins f4rc:$RB), + "frin", "$RST, $RB", IIC_FPGeneral, + [(set f32:$RST, (any_fround f32:$RB))]>; let Interpretation64Bit = 1, isCodeGenOnly = 1 in - defm FRIPD : XForm_26r<63, 456, (outs f8rc:$frD), (ins f8rc:$frB), - "frip", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (any_fceil f64:$frB))]>; - defm FRIPS : XForm_26r<63, 456, (outs f4rc:$frD), (ins f4rc:$frB), - "frip", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (any_fceil f32:$frB))]>; + defm FRIPD : XForm_26r<63, 456, (outs f8rc:$RST), (ins f8rc:$RB), + "frip", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (any_fceil f64:$RB))]>; + defm FRIPS : XForm_26r<63, 456, (outs f4rc:$RST), (ins f4rc:$RB), + "frip", "$RST, $RB", IIC_FPGeneral, + [(set f32:$RST, (any_fceil f32:$RB))]>; let Interpretation64Bit = 1, isCodeGenOnly = 1 in - defm FRIZD : XForm_26r<63, 424, (outs f8rc:$frD), (ins f8rc:$frB), - "friz", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (any_ftrunc f64:$frB))]>; - defm FRIZS : XForm_26r<63, 424, (outs f4rc:$frD), (ins f4rc:$frB), - "friz", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (any_ftrunc f32:$frB))]>; + defm FRIZD : XForm_26r<63, 424, (outs f8rc:$RST), (ins f8rc:$RB), + "friz", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (any_ftrunc f64:$RB))]>; + defm FRIZS : XForm_26r<63, 424, (outs f4rc:$RST), (ins f4rc:$RB), + "friz", "$RST, $RB", IIC_FPGeneral, + [(set f32:$RST, (any_ftrunc f32:$RB))]>; let Interpretation64Bit = 1, isCodeGenOnly = 1 in - defm FRIMD : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB), - "frim", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (any_ffloor f64:$frB))]>; - defm FRIMS : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB), - "frim", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (any_ffloor f32:$frB))]>; + defm FRIMD : XForm_26r<63, 488, (outs f8rc:$RST), (ins f8rc:$RB), + "frim", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (any_ffloor f64:$RB))]>; + defm FRIMS : XForm_26r<63, 488, (outs f4rc:$RST), (ins f4rc:$RB), + "frim", "$RST, $RB", IIC_FPGeneral, + [(set f32:$RST, (any_ffloor f32:$RB))]>; } let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in { - defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), - "fctiw", "$frD, $frB", IIC_FPGeneral, + defm FCTIW : XForm_26r<63, 14, (outs f8rc:$RST), (ins f8rc:$RB), + "fctiw", "$RST, $RB", IIC_FPGeneral, []>; - defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB), - "fctiwu", "$frD, $frB", IIC_FPGeneral, + defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$RST), (ins f8rc:$RB), + "fctiwu", "$RST, $RB", IIC_FPGeneral, []>; - defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), - "fctiwz", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (PPCany_fctiwz f64:$frB))]>; + defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$RST), (ins f8rc:$RB), + "fctiwz", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (PPCany_fctiwz f64:$RB))]>; - defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), - "frsp", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (any_fpround f64:$frB))]>; + defm FRSP : XForm_26r<63, 12, (outs f4rc:$RST), (ins f8rc:$RB), + "frsp", "$RST, $RB", IIC_FPGeneral, + [(set f32:$RST, (any_fpround f64:$RB))]>; - defm FSQRT : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB), - "fsqrt", "$frD, $frB", IIC_FPSqrtD, - [(set f64:$frD, (any_fsqrt f64:$frB))]>; - defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB), - "fsqrts", "$frD, $frB", IIC_FPSqrtS, - [(set f32:$frD, (any_fsqrt f32:$frB))]>; + defm FSQRT : XForm_26r<63, 22, (outs f8rc:$RST), (ins f8rc:$RB), + "fsqrt", "$RST, $RB", IIC_FPSqrtD, + [(set f64:$RST, (any_fsqrt f64:$RB))]>; + defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$RST), (ins f4rc:$RB), + "fsqrts", "$RST, $RB", IIC_FPSqrtS, + [(set f32:$RST, (any_fsqrt f32:$RB))]>; } } @@ -2405,57 +2419,57 @@ /// that they will fill slots (which could cause the load of a LSU reject to /// sneak into a d-group with a store). let hasSideEffects = 0, Predicates = [HasFPU] in -defm FMR : XForm_26r<63, 72, (outs f4rc:$frD), (ins f4rc:$frB), - "fmr", "$frD, $frB", IIC_FPGeneral, - []>, // (set f32:$frD, f32:$frB) +defm FMR : XForm_26r<63, 72, (outs f4rc:$RST), (ins f4rc:$RB), + "fmr", "$RST, $RB", IIC_FPGeneral, + []>, // (set f32:$RST, f32:$RB) PPC970_Unit_Pseudo; let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. // These are artificially split into two different forms, for 4/8 byte FP. -defm FABSS : XForm_26r<63, 264, (outs f4rc:$frD), (ins f4rc:$frB), - "fabs", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (fabs f32:$frB))]>; +defm FABSS : XForm_26r<63, 264, (outs f4rc:$RST), (ins f4rc:$RB), + "fabs", "$RST, $RB", IIC_FPGeneral, + [(set f32:$RST, (fabs f32:$RB))]>; let Interpretation64Bit = 1, isCodeGenOnly = 1 in -defm FABSD : XForm_26r<63, 264, (outs f8rc:$frD), (ins f8rc:$frB), - "fabs", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (fabs f64:$frB))]>; -defm FNABSS : XForm_26r<63, 136, (outs f4rc:$frD), (ins f4rc:$frB), - "fnabs", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (fneg (fabs f32:$frB)))]>; +defm FABSD : XForm_26r<63, 264, (outs f8rc:$RST), (ins f8rc:$RB), + "fabs", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (fabs f64:$RB))]>; +defm FNABSS : XForm_26r<63, 136, (outs f4rc:$RST), (ins f4rc:$RB), + "fnabs", "$RST, $RB", IIC_FPGeneral, + [(set f32:$RST, (fneg (fabs f32:$RB)))]>; let Interpretation64Bit = 1, isCodeGenOnly = 1 in -defm FNABSD : XForm_26r<63, 136, (outs f8rc:$frD), (ins f8rc:$frB), - "fnabs", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (fneg (fabs f64:$frB)))]>; -defm FNEGS : XForm_26r<63, 40, (outs f4rc:$frD), (ins f4rc:$frB), - "fneg", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (fneg f32:$frB))]>; +defm FNABSD : XForm_26r<63, 136, (outs f8rc:$RST), (ins f8rc:$RB), + "fnabs", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (fneg (fabs f64:$RB)))]>; +defm FNEGS : XForm_26r<63, 40, (outs f4rc:$RST), (ins f4rc:$RB), + "fneg", "$RST, $RB", IIC_FPGeneral, + [(set f32:$RST, (fneg f32:$RB))]>; let Interpretation64Bit = 1, isCodeGenOnly = 1 in -defm FNEGD : XForm_26r<63, 40, (outs f8rc:$frD), (ins f8rc:$frB), - "fneg", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (fneg f64:$frB))]>; +defm FNEGD : XForm_26r<63, 40, (outs f8rc:$RST), (ins f8rc:$RB), + "fneg", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (fneg f64:$RB))]>; -defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$frD), (ins f4rc:$frA, f4rc:$frB), - "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, - [(set f32:$frD, (fcopysign f32:$frB, f32:$frA))]>; +defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$RST), (ins f4rc:$RA, f4rc:$RB), + "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral, + [(set f32:$RST, (fcopysign f32:$RB, f32:$RA))]>; let Interpretation64Bit = 1, isCodeGenOnly = 1 in -defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$frD), (ins f8rc:$frA, f8rc:$frB), - "fcpsgn", "$frD, $frA, $frB", IIC_FPGeneral, - [(set f64:$frD, (fcopysign f64:$frB, f64:$frA))]>; +defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB), + "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral, + [(set f64:$RST, (fcopysign f64:$RB, f64:$RA))]>; // Reciprocal estimates. let mayRaiseFPException = 1 in { -defm FRE : XForm_26r<63, 24, (outs f8rc:$frD), (ins f8rc:$frB), - "fre", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (PPCfre f64:$frB))]>; -defm FRES : XForm_26r<59, 24, (outs f4rc:$frD), (ins f4rc:$frB), - "fres", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (PPCfre f32:$frB))]>; -defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$frD), (ins f8rc:$frB), - "frsqrte", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (PPCfrsqrte f64:$frB))]>; -defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$frD), (ins f4rc:$frB), - "frsqrtes", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (PPCfrsqrte f32:$frB))]>; +defm FRE : XForm_26r<63, 24, (outs f8rc:$RST), (ins f8rc:$RB), + "fre", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (PPCfre f64:$RB))]>; +defm FRES : XForm_26r<59, 24, (outs f4rc:$RST), (ins f4rc:$RB), + "fres", "$RST, $RB", IIC_FPGeneral, + [(set f32:$RST, (PPCfre f32:$RB))]>; +defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$RST), (ins f8rc:$RB), + "frsqrte", "$RST, $RB", IIC_FPGeneral, + [(set f64:$RST, (PPCfrsqrte f64:$RB))]>; +defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$RST), (ins f4rc:$RB), + "frsqrtes", "$RST, $RB", IIC_FPGeneral, + [(set f32:$RST, (PPCfrsqrte f32:$RB))]>; } } @@ -2523,13 +2537,13 @@ let isCodeGenOnly = 1 in { let isReMaterializable = 1, isAsCheapAsAMove = 1 in { -def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$dst), (ins), - "creqv $dst, $dst, $dst", IIC_BrCR, - [(set i1:$dst, 1)]>; +def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$CRD), (ins), + "creqv $CRD, $CRD, $CRD", IIC_BrCR, + [(set i1:$CRD, 1)]>; -def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$dst), (ins), - "crxor $dst, $dst, $dst", IIC_BrCR, - [(set i1:$dst, 0)]>; +def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$CRD), (ins), + "crxor $CRD, $CRD, $CRD", IIC_BrCR, + [(set i1:$CRD, 0)]>; } let Defs = [CR1EQ], CRD = 6 in { @@ -2546,19 +2560,19 @@ // XFX-Form instructions. Instructions that deal with SPRs. // -def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR), - "mfspr $RT, $SPR", IIC_SprMFSPR>; -def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), - "mtspr $SPR, $RT", IIC_SprMTSPR>; +def MFSPR : XFXForm_1<31, 339, (outs gprc:$RST), (ins i32imm:$SPR), + "mfspr $RST, $SPR", IIC_SprMFSPR>; +def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RST), + "mtspr $SPR, $RST", IIC_SprMTSPR>; -def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), - "mftb $RT, $SPR", IIC_SprMFTB>; +def MFTB : XFXForm_1<31, 371, (outs gprc:$RST), (ins i32imm:$SPR), + "mftb $RST, $SPR", IIC_SprMFTB>; -def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR), - "mfpmr $RT, $SPR", IIC_SprMFPMR>; +def MFPMR : XFXForm_1<31, 334, (outs gprc:$RST), (ins i32imm:$SPR), + "mfpmr $RST, $SPR", IIC_SprMFPMR>; -def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT), - "mtpmr $SPR, $RT", IIC_SprMTPMR>; +def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RST), + "mtpmr $SPR, $RST", IIC_SprMTPMR>; // A pseudo-instruction used to implement the read of the 64-bit cycle counter @@ -2568,19 +2582,19 @@ "#ReadTB", []>; let Uses = [CTR] in { -def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$rT), (ins), - "mfctr $rT", IIC_SprMFSPR>, +def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$RST), (ins), + "mfctr $RST", IIC_SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } -let Defs = [CTR], Pattern = [(PPCmtctr i32:$rS)] in { -def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), - "mtctr $rS", IIC_SprMTSPR>, +let Defs = [CTR], Pattern = [(PPCmtctr i32:$RST)] in { +def MTCTR : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST), + "mtctr $RST", IIC_SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } let hasSideEffects = 1, isCodeGenOnly = 1, isNotDuplicable = 1, Defs = [CTR] in { -let Pattern = [(int_set_loop_iterations i32:$rS)] in -def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), - "mtctr $rS", IIC_SprMTSPR>, +let Pattern = [(int_set_loop_iterations i32:$RST)] in +def MTCTRloop : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST), + "mtctr $RST", IIC_SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } @@ -2590,23 +2604,23 @@ let hasSideEffects = 0 in { let Defs = [LR] in { -def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), - "mtlr $rS", IIC_SprMTSPR>, +def MTLR : XFXForm_1_ext<31, 467, 8, (outs), (ins gprc:$RST), + "mtlr $RST", IIC_SprMTSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } let Uses = [LR] in { -def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), - "mflr $rT", IIC_SprMFSPR>, +def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$RST), (ins), + "mflr $RST", IIC_SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } } let hasSideEffects = 1 in { - def MTUDSCR : XFXForm_7_ext<31, 467, 3, (outs), (ins gprc:$rX), - "mtspr 3, $rX", IIC_SprMTSPR>, + def MTUDSCR : XFXForm_1_ext<31, 467, 3, (outs), (ins gprc:$RST), + "mtspr 3, $RST", IIC_SprMTSPR>, PPC970_DGroup_Single, PPC970_Unit_FXU; - def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$rX), (ins), - "mfspr $rX, 3", IIC_SprMFSPR>, + def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$RST), (ins), + "mfspr $RST, 3", IIC_SprMFSPR>, PPC970_DGroup_First, PPC970_Unit_FXU; } @@ -2621,20 +2635,20 @@ // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed // like a GPR on the PPC970. As such, copies in and out have the same // performance characteristics as an OR instruction. - def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), - "mtspr 256, $rS", IIC_IntGeneral>, + def MTVRSAVE : XFXForm_1_ext<31, 467, 256, (outs), (ins gprc:$RST), + "mtspr 256, $RST", IIC_IntGeneral>, PPC970_DGroup_Single, PPC970_Unit_FXU; - def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), (ins), - "mfspr $rT, 256", IIC_IntGeneral>, + def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), (ins), + "mfspr $RST, 256", IIC_IntGeneral>, PPC970_DGroup_First, PPC970_Unit_FXU; - def MTVRSAVEv : XFXForm_7_ext<31, 467, 256, - (outs VRSAVERC:$reg), (ins gprc:$rS), - "mtspr 256, $rS", IIC_IntGeneral>, + def MTVRSAVEv : XFXForm_1_ext<31, 467, 256, + (outs VRSAVERC:$SPR), (ins gprc:$RST), + "mtspr 256, $RST", IIC_IntGeneral>, PPC970_DGroup_Single, PPC970_Unit_FXU; - def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$rT), - (ins VRSAVERC:$reg), - "mfspr $rT, 256", IIC_IntGeneral>, + def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), + (ins VRSAVERC:$SPR), + "mfspr $RST, 256", IIC_IntGeneral>, PPC970_DGroup_First, PPC970_Unit_FXU; } @@ -2647,14 +2661,14 @@ // on the cr register selected. Thus, post-ra anti-dep breaking must not // later change that register assignment. let hasExtraDefRegAllocReq = 1 in { -def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$ST), - "mtocrf $FXM, $ST", IIC_BrMCRX>, +def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$RST), + "mtocrf $FXM, $RST", IIC_BrMCRX>, PPC970_DGroup_First, PPC970_Unit_CRU; // Similarly to mtocrf, the mask for mtcrf must be prepared in a way that // is dependent on the cr fields being set. -def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS), - "mtcrf $FXM, $rS", IIC_BrMCRX>, +def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$RST), + "mtcrf $FXM, $RST", IIC_BrMCRX>, PPC970_MicroCode, PPC970_Unit_CRU; } // hasExtraDefRegAllocReq = 1 @@ -2662,14 +2676,14 @@ // on the cr register selected. Thus, post-ra anti-dep breaking must not // later change that register assignment. let hasExtraSrcRegAllocReq = 1 in { -def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM), - "mfocrf $rT, $FXM", IIC_SprMFCRF>, +def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$RST), (ins crbitm:$FXM), + "mfocrf $RST, $FXM", IIC_SprMFCRF>, PPC970_DGroup_First, PPC970_Unit_CRU; // Similarly to mfocrf, the mask for mfcrf must be prepared in a way that // is dependent on the cr fields being copied. -def MFCR : XFXForm_3<31, 19, (outs gprc:$rT), (ins), - "mfcr $rT", IIC_SprMFCR>, +def MFCR : XFXForm_3<31, 19, (outs gprc:$RT), (ins), + "mfcr $RT", IIC_SprMFCR>, PPC970_MicroCode, PPC970_Unit_CRU; } // hasExtraSrcRegAllocReq = 1 @@ -2704,136 +2718,136 @@ let Defs = [RM], hasSideEffects = 1 in { let isCodeGenOnly = 1 in - def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$rT), - "mtfsf $FM, $rT", IIC_IntMTFSB0, - [(int_ppc_mtfsf timm:$FM, f64:$rT)]>, + def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$RT), + "mtfsf $FM, $RT", IIC_IntMTFSB0, + [(int_ppc_mtfsf timm:$FM, f64:$RT)]>, PPC970_DGroup_Single, PPC970_Unit_FPU; } let Uses = [RM], hasSideEffects = 1 in { - def MFFS : XForm_42<63, 583, (outs f8rc:$rT), (ins), - "mffs $rT", IIC_IntMFFS, - [(set f64:$rT, (PPCmffs))]>, + def MFFS : XForm_42<63, 583, (outs f8rc:$RST), (ins), + "mffs $RST", IIC_IntMFFS, + [(set f64:$RST, (PPCmffs))]>, PPC970_DGroup_Single, PPC970_Unit_FPU; let Defs = [CR1] in - def MFFS_rec : XForm_42<63, 583, (outs f8rc:$rT), (ins), - "mffs. $rT", IIC_IntMFFS, []>, isRecordForm; + def MFFS_rec : XForm_42<63, 583, (outs f8rc:$RST), (ins), + "mffs. $RST", IIC_IntMFFS, []>, isRecordForm; - def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins), - "mffsce $rT", IIC_IntMFFS, []>, + def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$RST), (ins), + "mffsce $RST", IIC_IntMFFS, []>, PPC970_DGroup_Single, PPC970_Unit_FPU; - def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT), - (ins f8rc:$FRB), "mffscdrn $rT, $FRB", + def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$RST), + (ins f8rc:$FRB), "mffscdrn $RST, $FRB", IIC_IntMFFS, []>, PPC970_DGroup_Single, PPC970_Unit_FPU; - def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT), + def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$RST), (ins u3imm:$DRM), - "mffscdrni $rT, $DRM", + "mffscdrni $RST, $DRM", IIC_IntMFFS, []>, PPC970_DGroup_Single, PPC970_Unit_FPU; - def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT), - (ins f8rc:$FRB), "mffscrn $rT, $FRB", + def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$RST), + (ins f8rc:$FRB), "mffscrn $RST, $FRB", IIC_IntMFFS, []>, PPC970_DGroup_Single, PPC970_Unit_FPU; - def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT), - (ins u2imm:$RM), "mffscrni $rT, $RM", + def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$RST), + (ins u2imm:$RM), "mffscrni $RST, $RM", IIC_IntMFFS, []>, PPC970_DGroup_Single, PPC970_Unit_FPU; - def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins), - "mffsl $rT", IIC_IntMFFS, []>, + def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$RST), (ins), + "mffsl $RST", IIC_IntMFFS, []>, PPC970_DGroup_Single, PPC970_Unit_FPU; } } let Predicates = [IsISA3_0] in { -def MODSW : XForm_8<31, 779, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "modsw $rT, $rA, $rB", IIC_IntDivW, - [(set i32:$rT, (srem i32:$rA, i32:$rB))]>; -def MODUW : XForm_8<31, 267, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "moduw $rT, $rA, $rB", IIC_IntDivW, - [(set i32:$rT, (urem i32:$rA, i32:$rB))]>; +def MODSW : XForm_8<31, 779, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB), + "modsw $RST, $RA, $RB", IIC_IntDivW, + [(set i32:$RST, (srem i32:$RA, i32:$RB))]>; +def MODUW : XForm_8<31, 267, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB), + "moduw $RST, $RA, $RB", IIC_IntDivW, + [(set i32:$RST, (urem i32:$RA, i32:$RB))]>; let hasSideEffects = 1 in -def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$rT), - (ins gprc:$rA, gprc:$rB, u2imm:$CY), - "addex $rT, $rA, $rB, $CY", IIC_IntGeneral, []>; +def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$RT), + (ins gprc:$RA, gprc:$RB, u2imm:$CY), + "addex $RT, $RA, $RB, $CY", IIC_IntGeneral, []>; } let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. // XO-Form instructions. Arithmetic instructions that can set overflow bit let isCommutable = 1 in -defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "add", "$rT, $rA, $rB", IIC_IntSimple, - [(set i32:$rT, (add i32:$rA, i32:$rB))]>; +defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), + "add", "$RT, $RA, $RB", IIC_IntSimple, + [(set i32:$RT, (add i32:$RA, i32:$RB))]>; let isCodeGenOnly = 1 in -def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$rT), (ins gprc:$rA, tlsreg32:$rB), - "add $rT, $rA, $rB", IIC_IntSimple, - [(set i32:$rT, (add i32:$rA, tglobaltlsaddr:$rB))]>; +def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$RT), (ins gprc:$RA, tlsreg32:$RB), + "add $RT, $RA, $RB", IIC_IntSimple, + [(set i32:$RT, (add i32:$RA, tglobaltlsaddr:$RB))]>; let isCommutable = 1 in -defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "addc", "$rT, $rA, $rB", IIC_IntGeneral, - [(set i32:$rT, (addc i32:$rA, i32:$rB))]>, +defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), + "addc", "$RT, $RA, $RB", IIC_IntGeneral, + [(set i32:$RT, (addc i32:$RA, i32:$RB))]>, PPC970_DGroup_Cracked; -defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "divw", "$rT, $rA, $rB", IIC_IntDivW, - [(set i32:$rT, (sdiv i32:$rA, i32:$rB))]>; -defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "divwu", "$rT, $rA, $rB", IIC_IntDivW, - [(set i32:$rT, (udiv i32:$rA, i32:$rB))]>; -defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "divwe", "$rT, $rA, $rB", IIC_IntDivW, - [(set i32:$rT, (int_ppc_divwe gprc:$rA, gprc:$rB))]>, +defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), + "divw", "$RT, $RA, $RB", IIC_IntDivW, + [(set i32:$RT, (sdiv i32:$RA, i32:$RB))]>; +defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), + "divwu", "$RT, $RA, $RB", IIC_IntDivW, + [(set i32:$RT, (udiv i32:$RA, i32:$RB))]>; +defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), + "divwe", "$RT, $RA, $RB", IIC_IntDivW, + [(set i32:$RT, (int_ppc_divwe gprc:$RA, gprc:$RB))]>, Requires<[HasExtDiv]>; -defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "divweu", "$rT, $rA, $rB", IIC_IntDivW, - [(set i32:$rT, (int_ppc_divweu gprc:$rA, gprc:$rB))]>, +defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), + "divweu", "$RT, $RA, $RB", IIC_IntDivW, + [(set i32:$RT, (int_ppc_divweu gprc:$RA, gprc:$RB))]>, Requires<[HasExtDiv]>; let isCommutable = 1 in { -defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "mulhw", "$rT, $rA, $rB", IIC_IntMulHW, - [(set i32:$rT, (mulhs i32:$rA, i32:$rB))]>; -defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "mulhwu", "$rT, $rA, $rB", IIC_IntMulHWU, - [(set i32:$rT, (mulhu i32:$rA, i32:$rB))]>; -defm MULLW : XOForm_1rx<31, 235, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "mullw", "$rT, $rA, $rB", IIC_IntMulHW, - [(set i32:$rT, (mul i32:$rA, i32:$rB))]>; +defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), + "mulhw", "$RT, $RA, $RB", IIC_IntMulHW, + [(set i32:$RT, (mulhs i32:$RA, i32:$RB))]>; +defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), + "mulhwu", "$RT, $RA, $RB", IIC_IntMulHWU, + [(set i32:$RT, (mulhu i32:$RA, i32:$RB))]>; +defm MULLW : XOForm_1rx<31, 235, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), + "mullw", "$RT, $RA, $RB", IIC_IntMulHW, + [(set i32:$RT, (mul i32:$RA, i32:$RB))]>; } // isCommutable -defm SUBF : XOForm_1rx<31, 40, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "subf", "$rT, $rA, $rB", IIC_IntGeneral, - [(set i32:$rT, (sub i32:$rB, i32:$rA))]>; -defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "subfc", "$rT, $rA, $rB", IIC_IntGeneral, - [(set i32:$rT, (subc i32:$rB, i32:$rA))]>, +defm SUBF : XOForm_1rx<31, 40, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), + "subf", "$RT, $RA, $RB", IIC_IntGeneral, + [(set i32:$RT, (sub i32:$RB, i32:$RA))]>; +defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), + "subfc", "$RT, $RA, $RB", IIC_IntGeneral, + [(set i32:$RT, (subc i32:$RB, i32:$RA))]>, PPC970_DGroup_Cracked; -defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$rT), (ins gprc:$rA), - "neg", "$rT, $rA", IIC_IntSimple, - [(set i32:$rT, (ineg i32:$rA))]>; +defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$RT), (ins gprc:$RA), + "neg", "$RT, $RA", IIC_IntSimple, + [(set i32:$RT, (ineg i32:$RA))]>; let Uses = [CARRY] in { let isCommutable = 1 in -defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "adde", "$rT, $rA, $rB", IIC_IntGeneral, - [(set i32:$rT, (adde i32:$rA, i32:$rB))]>; -defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$rT), (ins gprc:$rA), - "addme", "$rT, $rA", IIC_IntGeneral, - [(set i32:$rT, (adde i32:$rA, -1))]>; -defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$rT), (ins gprc:$rA), - "addze", "$rT, $rA", IIC_IntGeneral, - [(set i32:$rT, (adde i32:$rA, 0))]>; -defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$rT), (ins gprc:$rA, gprc:$rB), - "subfe", "$rT, $rA, $rB", IIC_IntGeneral, - [(set i32:$rT, (sube i32:$rB, i32:$rA))]>; -defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$rT), (ins gprc:$rA), - "subfme", "$rT, $rA", IIC_IntGeneral, - [(set i32:$rT, (sube -1, i32:$rA))]>; -defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA), - "subfze", "$rT, $rA", IIC_IntGeneral, - [(set i32:$rT, (sube 0, i32:$rA))]>; +defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), + "adde", "$RT, $RA, $RB", IIC_IntGeneral, + [(set i32:$RT, (adde i32:$RA, i32:$RB))]>; +defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$RT), (ins gprc:$RA), + "addme", "$RT, $RA", IIC_IntGeneral, + [(set i32:$RT, (adde i32:$RA, -1))]>; +defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$RT), (ins gprc:$RA), + "addze", "$RT, $RA", IIC_IntGeneral, + [(set i32:$RT, (adde i32:$RA, 0))]>; +defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), + "subfe", "$RT, $RA, $RB", IIC_IntGeneral, + [(set i32:$RT, (sube i32:$RB, i32:$RA))]>; +defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$RT), (ins gprc:$RA), + "subfme", "$RT, $RA", IIC_IntGeneral, + [(set i32:$RT, (sube -1, i32:$RA))]>; +defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$RT), (ins gprc:$RA), + "subfze", "$RT, $RA", IIC_IntGeneral, + [(set i32:$RT, (sube 0, i32:$RA))]>; } } @@ -2945,8 +2959,8 @@ let PPC970_Unit = 1 in { // FXU Operations. let isSelect = 1 in def ISEL : AForm_4<31, 15, - (outs gprc:$rT), (ins gprc_nor0:$rA, gprc:$rB, crbitrc:$cond), - "isel $rT, $rA, $rB, $cond", IIC_IntISEL, + (outs gprc:$RT), (ins gprc_nor0:$RA, gprc:$RB, crbitrc:$COND), + "isel $RT, $RA, $RB, $COND", IIC_IntISEL, []>; } @@ -2955,26 +2969,26 @@ // let isCommutable = 1 in { // RLWIMI can be commuted if the rotate amount is zero. -defm RLWIMI : MForm_2r<20, (outs gprc:$rA), - (ins gprc:$rSi, gprc:$rS, u5imm:$SH, u5imm:$MB, - u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME", +defm RLWIMI : MForm_2r<20, (outs gprc:$RA), + (ins gprc:$RAi, gprc:$RS, u5imm:$SH, u5imm:$MB, + u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME", IIC_IntRotate, []>, PPC970_DGroup_Cracked, - RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">; + RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">; } let BaseName = "rlwinm" in { def RLWINM : MForm_2<21, - (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), - "rlwinm $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, + (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), + "rlwinm $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, []>, RecFormRel; let Defs = [CR0] in def RLWINM_rec : MForm_2<21, - (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), - "rlwinm. $rA, $rS, $SH, $MB, $ME", IIC_IntGeneral, + (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), + "rlwinm. $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; } -defm RLWNM : MForm_2r<23, (outs gprc:$rA), - (ins gprc:$rS, gprc:$rB, u5imm:$MB, u5imm:$ME), - "rlwnm", "$rA, $rS, $rB, $MB, $ME", IIC_IntGeneral, +defm RLWNM : MForm_1r<23, (outs gprc:$RA), + (ins gprc:$RS, gprc:$RB, u5imm:$MB, u5imm:$ME), + "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral, []>; } } // hasSideEffects = 0 @@ -4043,21 +4057,21 @@ // FIXME: For B=0 or B > 8, the registers following RT are used. // WARNING: Do not add patterns for this instruction without fixing this. -def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RT), - (ins gprc:$A, u5imm:$B), - "lswi $RT, $A, $B", IIC_LdStLoad, []>; +def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RST), + (ins gprc:$RA, u5imm:$RB), + "lswi $RST, $RA, $RB", IIC_LdStLoad, []>; // FIXME: For B=0 or B > 8, the registers following RT are used. // WARNING: Do not add patterns for this instruction without fixing this. def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), - (ins gprc:$RT, gprc:$A, u5imm:$B), - "stswi $RT, $A, $B", IIC_LdStLoad, []>; + (ins gprc:$RST, gprc:$RA, u5imm:$RB), + "stswi $RST, $RA, $RB", IIC_LdStLoad, []>; def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), "isync", IIC_SprISYNC, []>; -def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src), - "icbi $src", IIC_LdStICBI, []>; +def ICBI : XForm_1a<31, 982, (outs), (ins (memrr $RA, $RB):$addr), + "icbi $addr", IIC_LdStICBI, []>; def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L), "wait $L", IIC_LdStLoad, []>; @@ -4093,18 +4107,18 @@ let Inst{21-30} = 163; } -def DCCCI : XForm_tlb<454, (outs), (ins gprc:$A, gprc:$B), - "dccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; -def ICCCI : XForm_tlb<966, (outs), (ins gprc:$A, gprc:$B), - "iccci $A, $B", IIC_LdStLoad>, Requires<[IsPPC4xx]>; +def DCCCI : XForm_tlb<454, (outs), (ins gprc:$RA, gprc:$RB), + "dccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>; +def ICCCI : XForm_tlb<966, (outs), (ins gprc:$RA, gprc:$RB), + "iccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>; def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; -def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins), - "mfmsr $RT", IIC_SprMFMSR, []>; +def MFMSR : XForm_rs<31, 83, (outs gprc:$RST), (ins), + "mfmsr $RST", IIC_SprMFMSR, []>; def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L), "mtmsrd $RS, $L", IIC_SprMTMSRD>; @@ -4144,11 +4158,11 @@ def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), "slbie $RB", IIC_SprSLBIE, []>; -def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), - "slbmte $RS, $RB", IIC_SprSLBMTE, []>; +def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RST, gprc:$RB), + "slbmte $RST, $RB", IIC_SprSLBMTE, []>; -def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), - "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; +def SLBMFEE : XForm_26<31, 915, (outs gprc:$RST), (ins gprc:$RB), + "slbmfee $RST, $RB", IIC_SprSLBMFEE, []>; def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; @@ -4156,8 +4170,8 @@ def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; let Defs = [CR0] in -def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RT), (ins gprc:$RB), - "slbfee. $RT, $RB", IIC_SprSLBFEE, []>, isRecordForm; +def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RST), (ins gprc:$RB), + "slbfee. $RST, $RB", IIC_SprSLBFEE, []>, isRecordForm; def TLBIA : XForm_0<31, 370, (outs), (ins), "tlbia", IIC_SprTLBIA, []>; @@ -4173,13 +4187,13 @@ def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; -def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RS, gprc:$RB), - "tlbie $RB,$RS", IIC_SprTLBIE, []>; +def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RST, gprc:$RB), + "tlbie $RB,$RST", IIC_SprTLBIE, []>; -def TLBSX : XForm_tlb<914, (outs), (ins gprc:$A, gprc:$B), "tlbsx $A, $B", +def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB", IIC_LdStLoad>, Requires<[IsBookE]>; -def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$A, gprc:$B), "tlbivax $A, $B", +def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$RA, gprc:$RB), "tlbivax $RA, $RB", IIC_LdStLoad>, Requires<[IsBookE]>; def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), @@ -4188,18 +4202,18 @@ def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; -def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RS), (ins gprc:$A, i1imm:$WS), - "tlbre $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; +def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RST), (ins gprc:$RA, i1imm:$WS), + "tlbre $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; -def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RS, gprc:$A, i1imm:$WS), - "tlbwe $RS, $A, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; +def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RST, gprc:$RA, i1imm:$WS), + "tlbwe $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; -def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$A, gprc:$B), - "tlbsx $RST, $A, $B", IIC_LdStLoad, []>, +def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$RA, gprc:$RB), + "tlbsx $RST, $RA, $RB", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; def TLBSX2D : XForm_base_r3xo<31, 914, (outs), - (ins gprc:$RST, gprc:$A, gprc:$B), - "tlbsx. $RST, $A, $B", IIC_LdStLoad, []>, + (ins gprc:$RST, gprc:$RA, gprc:$RB), + "tlbsx. $RST, $RA, $RB", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>, isRecordForm; def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; @@ -4214,10 +4228,10 @@ def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, Requires<[IsE500]>; -def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), - "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; -def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), - "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; +def MFDCR : XFXForm_1<31, 323, (outs gprc:$RST), (ins i32imm:$SPR), + "mfdcr $RST, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; +def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RST, i32imm:$SPR), + "mtdcr $SPR, $RST", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; @@ -4225,86 +4239,86 @@ def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), - (ins gprc:$A, gprc:$B), - "lbzcix $RST, $A, $B", IIC_LdStLoad, []>; + (ins gprc:$RA, gprc:$RB), + "lbzcix $RST, $RA, $RB", IIC_LdStLoad, []>; def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), - (ins gprc:$A, gprc:$B), - "lhzcix $RST, $A, $B", IIC_LdStLoad, []>; + (ins gprc:$RA, gprc:$RB), + "lhzcix $RST, $RA, $RB", IIC_LdStLoad, []>; def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), - (ins gprc:$A, gprc:$B), - "lwzcix $RST, $A, $B", IIC_LdStLoad, []>; + (ins gprc:$RA, gprc:$RB), + "lwzcix $RST, $RA, $RB", IIC_LdStLoad, []>; def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), - (ins gprc:$A, gprc:$B), - "ldcix $RST, $A, $B", IIC_LdStLoad, []>; + (ins gprc:$RA, gprc:$RB), + "ldcix $RST, $RA, $RB", IIC_LdStLoad, []>; def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), - (ins gprc:$RST, gprc:$A, gprc:$B), - "stbcix $RST, $A, $B", IIC_LdStLoad, []>; + (ins gprc:$RST, gprc:$RA, gprc:$RB), + "stbcix $RST, $RA, $RB", IIC_LdStLoad, []>; def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), - (ins gprc:$RST, gprc:$A, gprc:$B), - "sthcix $RST, $A, $B", IIC_LdStLoad, []>; + (ins gprc:$RST, gprc:$RA, gprc:$RB), + "sthcix $RST, $RA, $RB", IIC_LdStLoad, []>; def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), - (ins gprc:$RST, gprc:$A, gprc:$B), - "stwcix $RST, $A, $B", IIC_LdStLoad, []>; + (ins gprc:$RST, gprc:$RA, gprc:$RB), + "stwcix $RST, $RA, $RB", IIC_LdStLoad, []>; def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), - (ins gprc:$RST, gprc:$A, gprc:$B), - "stdcix $RST, $A, $B", IIC_LdStLoad, []>; + (ins gprc:$RST, gprc:$RA, gprc:$RB), + "stdcix $RST, $RA, $RB", IIC_LdStLoad, []>; // External PID Load Store Instructions -def LBEPX : XForm_1<31, 95, (outs gprc:$rD), (ins memrr:$src), - "lbepx $rD, $src", IIC_LdStLoad, []>, +def LBEPX : XForm_1<31, 95, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lbepx $RST, $addr", IIC_LdStLoad, []>, Requires<[IsE500]>; -def LFDEPX : XForm_25<31, 607, (outs f8rc:$frD), (ins memrr:$src), - "lfdepx $frD, $src", IIC_LdStLFD, []>, +def LFDEPX : XForm_25<31, 607, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), + "lfdepx $RST, $addr", IIC_LdStLFD, []>, Requires<[IsE500]>; -def LHEPX : XForm_1<31, 287, (outs gprc:$rD), (ins memrr:$src), - "lhepx $rD, $src", IIC_LdStLoad, []>, +def LHEPX : XForm_1<31, 287, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lhepx $RST, $addr", IIC_LdStLoad, []>, Requires<[IsE500]>; -def LWEPX : XForm_1<31, 31, (outs gprc:$rD), (ins memrr:$src), - "lwepx $rD, $src", IIC_LdStLoad, []>, +def LWEPX : XForm_1<31, 31, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), + "lwepx $RST, $addr", IIC_LdStLoad, []>, Requires<[IsE500]>; -def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$rS, memrr:$dst), - "stbepx $rS, $dst", IIC_LdStStore, []>, +def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), + "stbepx $RST, $addr", IIC_LdStStore, []>, Requires<[IsE500]>; -def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$frS, memrr:$dst), - "stfdepx $frS, $dst", IIC_LdStSTFD, []>, +def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), + "stfdepx $RST, $addr", IIC_LdStSTFD, []>, Requires<[IsE500]>; -def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$rS, memrr:$dst), - "sthepx $rS, $dst", IIC_LdStStore, []>, +def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), + "sthepx $RST, $addr", IIC_LdStStore, []>, Requires<[IsE500]>; -def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$rS, memrr:$dst), - "stwepx $rS, $dst", IIC_LdStStore, []>, +def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), + "stwepx $RST, $addr", IIC_LdStStore, []>, Requires<[IsE500]>; -def DCBFEP : DCB_Form<127, 0, (outs), (ins memrr:$dst), "dcbfep $dst", +def DCBFEP : DCB_Form<127, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbfep $addr", IIC_LdStDCBF, []>, Requires<[IsE500]>; -def DCBSTEP : DCB_Form<63, 0, (outs), (ins memrr:$dst), "dcbstep $dst", +def DCBSTEP : DCB_Form<63, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbstep $addr", IIC_LdStDCBF, []>, Requires<[IsE500]>; -def DCBTEP : DCB_Form_hint<319, (outs), (ins memrr:$dst, u5imm:$TH), - "dcbtep $TH, $dst", IIC_LdStDCBF, []>, +def DCBTEP : DCB_Form_hint<319, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH), + "dcbtep $TH, $addr", IIC_LdStDCBF, []>, Requires<[IsE500]>; -def DCBTSTEP : DCB_Form_hint<255, (outs), (ins memrr:$dst, u5imm:$TH), - "dcbtstep $TH, $dst", IIC_LdStDCBF, []>, +def DCBTSTEP : DCB_Form_hint<255, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH), + "dcbtstep $TH, $addr", IIC_LdStDCBF, []>, Requires<[IsE500]>; -def DCBZEP : DCB_Form<1023, 0, (outs), (ins memrr:$dst), "dcbzep $dst", +def DCBZEP : DCB_Form<1023, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbzep $addr", IIC_LdStDCBF, []>, Requires<[IsE500]>; -def DCBZLEP : DCB_Form<1023, 1, (outs), (ins memrr:$dst), "dcbzlep $dst", +def DCBZLEP : DCB_Form<1023, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzlep $addr", IIC_LdStDCBF, []>, Requires<[IsE500]>; -def ICBIEP : XForm_1a<31, 991, (outs), (ins memrr:$src), "icbiep $src", +def ICBIEP : XForm_1a<31, 991, (outs), (ins (memrr $RA, $RB):$addr), "icbiep $addr", IIC_LdStICBI, []>, Requires<[IsE500]>; //===----------------------------------------------------------------------===// @@ -4679,56 +4693,56 @@ let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in { let Defs = [CTR], Uses = [CTR, RM] in { def gBC : BForm_3<16, 0, 0, (outs), - (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), - "bc $bo, $bi, $dst">; + (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD), + "bc $BO, $BI, $BD">; def gBCA : BForm_3<16, 1, 0, (outs), - (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), - "bca $bo, $bi, $dst">; + (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD), + "bca $BO, $BI, $BD">; let isAsmParserOnly = 1 in { def gBCat : BForm_3_at<16, 0, 0, (outs), - (ins u5imm:$bo, atimm:$at, crbitrc:$bi, - condbrtarget:$dst), - "bc$at $bo, $bi, $dst">; + (ins u5imm:$BO, atimm:$at, crbitrc:$BI, + condbrtarget:$BD), + "bc$at $BO, $BI, $BD">; def gBCAat : BForm_3_at<16, 1, 0, (outs), - (ins u5imm:$bo, atimm:$at, crbitrc:$bi, - abscondbrtarget:$dst), - "bca$at $bo, $bi, $dst">; + (ins u5imm:$BO, atimm:$at, crbitrc:$BI, + abscondbrtarget:$BD), + "bca$at $BO, $BI, $BD">; } // isAsmParserOnly = 1 } let Defs = [LR, CTR], Uses = [CTR, RM] in { def gBCL : BForm_3<16, 0, 1, (outs), - (ins u5imm:$bo, crbitrc:$bi, condbrtarget:$dst), - "bcl $bo, $bi, $dst">; + (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD), + "bcl $BO, $BI, $BD">; def gBCLA : BForm_3<16, 1, 1, (outs), - (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), - "bcla $bo, $bi, $dst">; + (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD), + "bcla $BO, $BI, $BD">; let isAsmParserOnly = 1 in { def gBCLat : BForm_3_at<16, 0, 1, (outs), - (ins u5imm:$bo, atimm:$at, crbitrc:$bi, - condbrtarget:$dst), - "bcl$at $bo, $bi, $dst">; + (ins u5imm:$BO, atimm:$at, crbitrc:$BI, + condbrtarget:$BD), + "bcl$at $BO, $BI, $BD">; def gBCLAat : BForm_3_at<16, 1, 1, (outs), - (ins u5imm:$bo, atimm:$at, crbitrc:$bi, - abscondbrtarget:$dst), - "bcla$at $bo, $bi, $dst">; + (ins u5imm:$BO, atimm:$at, crbitrc:$BI, + abscondbrtarget:$BD), + "bcla$at $BO, $BI, $BD">; } // // isAsmParserOnly = 1 } let Defs = [CTR], Uses = [CTR, LR, RM] in def gBCLR : XLForm_2<19, 16, 0, (outs), - (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), - "bclr $bo, $bi, $bh", IIC_BrB, []>; + (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), + "bclr $BO, $BI, $BH", IIC_BrB, []>; let Defs = [LR, CTR], Uses = [CTR, LR, RM] in def gBCLRL : XLForm_2<19, 16, 1, (outs), - (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), - "bclrl $bo, $bi, $bh", IIC_BrB, []>; + (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), + "bclrl $BO, $BI, $BH", IIC_BrB, []>; let Defs = [CTR], Uses = [CTR, LR, RM] in def gBCCTR : XLForm_2<19, 528, 0, (outs), - (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), - "bcctr $bo, $bi, $bh", IIC_BrB, []>; + (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), + "bcctr $BO, $BI, $BH", IIC_BrB, []>; let Defs = [LR, CTR], Uses = [CTR, LR, RM] in def gBCCTRL : XLForm_2<19, 528, 1, (outs), - (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), - "bcctrl $bo, $bi, $bh", IIC_BrB, []>; + (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), + "bcctrl $BO, $BI, $BH", IIC_BrB, []>; } multiclass BranchSimpleMnemonicAT { diff --git a/llvm/lib/Target/PowerPC/PPCInstrMMA.td b/llvm/lib/Target/PowerPC/PPCInstrMMA.td --- a/llvm/lib/Target/PowerPC/PPCInstrMMA.td +++ b/llvm/lib/Target/PowerPC/PPCInstrMMA.td @@ -502,10 +502,10 @@ let Predicates = [MMA, IsNotISAFuture] in { def XXMFACC : - XForm_AT3<31, 0, 177, (outs acc:$ASo), (ins acc:$AS), "xxmfacc $AS", + XForm_AT3<31, 0, 177, (outs acc:$ATo), (ins acc:$AT), "xxmfacc $AT", IIC_VecGeneral, - [(set v512i1:$ASo, (int_ppc_mma_xxmfacc v512i1:$AS))]>, - RegConstraint<"$ASo = $AS">, NoEncode<"$ASo">; + [(set v512i1:$ATo, (int_ppc_mma_xxmfacc v512i1:$AT))]>, + RegConstraint<"$ATo = $AT">, NoEncode<"$ATo">; def XXMTACC : XForm_AT3<31, 1, 177, (outs acc:$AT), (ins acc:$ATi), "xxmtacc $AT", IIC_VecGeneral, @@ -550,9 +550,9 @@ // On top of that Future CPU has a more convenient way to move between vsrs // and wacc registers using xxextfdmr512 and xxinstdmr512. def XXMFACCW : - XForm_AT3<31, 0, 177, (outs wacc:$ASo), (ins wacc:$AS), "xxmfacc $AS", + XForm_AT3<31, 0, 177, (outs wacc:$ATo), (ins wacc:$AT), "xxmfacc $AT", IIC_VecGeneral, []>, - RegConstraint<"$ASo = $AS">, NoEncode<"$ASo">; + RegConstraint<"$ATo = $AT">, NoEncode<"$ATo">; def XXMTACCW : XForm_AT3<31, 1, 177, (outs wacc:$AT), (ins wacc:$ATi), "xxmtacc $AT", IIC_VecGeneral, []>, diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td --- a/llvm/lib/Target/PowerPC/PPCInstrP10.td +++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td @@ -184,7 +184,7 @@ class MLS_DForm_R_SI34_RTA5_MEM opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : PI<1, opcode, OOL, IOL, asmstr, itin> { - bits<5> FRS; + bits<5> RST; bits<39> D_RA; let Pattern = pattern; @@ -197,7 +197,7 @@ let Inst{14-31} = D_RA{33-16}; // d0 // The instruction. - let Inst{38-42} = FRS{4-0}; + let Inst{38-42} = RST{4-0}; let Inst{43-47} = D_RA{38-34}; // RA let Inst{48-63} = D_RA{15-0}; // d1 } @@ -257,7 +257,7 @@ class 8LS_DForm_R_SI34_RTA5_MEM opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : PI<1, opcode, OOL, IOL, asmstr, itin> { - bits<5> RT; + bits<5> RST; bits<39> D_RA; let Pattern = pattern; @@ -269,7 +269,7 @@ let Inst{14-31} = D_RA{33-16}; // d0 // The instruction. - let Inst{38-42} = RT{4-0}; + let Inst{38-42} = RST{4-0}; let Inst{43-47} = D_RA{38-34}; // RA let Inst{48-63} = D_RA{15-0}; // d1 } @@ -280,7 +280,7 @@ string asmstr, InstrItinClass itin, list pattern> : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> { - bits<6> XT; + bits<6> XST; bits<39> D_RA; let Pattern = pattern; @@ -294,8 +294,8 @@ let Inst{14-31} = D_RA{33-16}; // d0 // The instruction. - let Inst{37} = XT{5}; - let Inst{38-42} = XT{4-0}; + let Inst{37} = XST{5}; + let Inst{38-42} = XST{4-0}; let Inst{43-47} = D_RA{38-34}; // RA let Inst{48-63} = D_RA{15-0}; // d1 } @@ -368,16 +368,16 @@ // VX-Form: [PO VRT RA VRB XO]. // Destructive (insert) forms are suffixed with _ins. class VXForm_VTB5_RA5_ins xo, string opc, list pattern> - : VXForm_1, - RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; + : VXForm_1, + RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; // VX-Form: [PO VRT RA RB XO]. // Destructive (insert) forms are suffixed with _ins. class VXForm_VRT5_RAB5_ins xo, string opc, list pattern> - : VXForm_1, - RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; + : VXForm_1, + RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; // VX-Form: [ PO BF // VRA VRB XO ] class VXForm_BF3_VAB5 xo, dag OOL, dag IOL, string asmstr, @@ -566,7 +566,9 @@ class XForm_XT5_BI5 opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list pattern> : XForm_base_r3xo { - let B = 0; + bits<5> BI; + let RA = BI; + let RB = 0; } multiclass MLS_DForm_R_SI34_RTA5_MEM_p opcode, dag OOL, dag IOL, @@ -631,124 +633,124 @@ let mayLoad = 1, mayStore = 0 in { defm PLXV : - 8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XT), (ins memri34:$D_RA), + 8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins memri34:$D_RA), (ins memri34_pcrel:$D_RA), - "plxv $XT, $D_RA", IIC_LdStLFD>; + "plxv $XST, $D_RA", IIC_LdStLFD>; defm PLFS : - MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA), - (ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA", + MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins memri34:$D_RA), + (ins memri34_pcrel:$D_RA), "plfs $RST, $D_RA", IIC_LdStLFD>; defm PLFD : - MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA), - (ins memri34_pcrel:$D_RA), "plfd $FRT, $D_RA", + MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$RST), (ins memri34:$D_RA), + (ins memri34_pcrel:$D_RA), "plfd $RST, $D_RA", IIC_LdStLFD>; defm PLXSSP : - 8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA), + 8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins memri34:$D_RA), (ins memri34_pcrel:$D_RA), - "plxssp $VRT, $D_RA", IIC_LdStLFD>; + "plxssp $RST, $D_RA", IIC_LdStLFD>; defm PLXSD : - 8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA), + 8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$RST), (ins memri34:$D_RA), (ins memri34_pcrel:$D_RA), - "plxsd $VRT, $D_RA", IIC_LdStLFD>; + "plxsd $RST, $D_RA", IIC_LdStLFD>; let Interpretation64Bit = 1, isCodeGenOnly = 1 in { defm PLBZ8 : - MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RT), (ins memri34:$D_RA), - (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA", + MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins memri34:$D_RA), + (ins memri34_pcrel:$D_RA), "plbz $RST, $D_RA", IIC_LdStLFD>; defm PLHZ8 : - MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RT), (ins memri34:$D_RA), - (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA", + MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins memri34:$D_RA), + (ins memri34_pcrel:$D_RA), "plhz $RST, $D_RA", IIC_LdStLFD>; defm PLHA8 : - MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RT), (ins memri34:$D_RA), - (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA", + MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RST), (ins memri34:$D_RA), + (ins memri34_pcrel:$D_RA), "plha $RST, $D_RA", IIC_LdStLFD>; defm PLWA8 : - 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RT), (ins memri34:$D_RA), + 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RST), (ins memri34:$D_RA), (ins memri34_pcrel:$D_RA), - "plwa $RT, $D_RA", IIC_LdStLFD>; + "plwa $RST, $D_RA", IIC_LdStLFD>; defm PLWZ8 : - MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RT), (ins memri34:$D_RA), - (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA", + MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RST), (ins memri34:$D_RA), + (ins memri34_pcrel:$D_RA), "plwz $RST, $D_RA", IIC_LdStLFD>; } defm PLBZ : - MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RT), (ins memri34:$D_RA), - (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA", + MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RST), (ins memri34:$D_RA), + (ins memri34_pcrel:$D_RA), "plbz $RST, $D_RA", IIC_LdStLFD>; defm PLHZ : - MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RT), (ins memri34:$D_RA), - (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA", + MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RST), (ins memri34:$D_RA), + (ins memri34_pcrel:$D_RA), "plhz $RST, $D_RA", IIC_LdStLFD>; defm PLHA : - MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RT), (ins memri34:$D_RA), - (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA", + MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RST), (ins memri34:$D_RA), + (ins memri34_pcrel:$D_RA), "plha $RST, $D_RA", IIC_LdStLFD>; defm PLWZ : - MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RT), (ins memri34:$D_RA), - (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA", + MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RST), (ins memri34:$D_RA), + (ins memri34_pcrel:$D_RA), "plwz $RST, $D_RA", IIC_LdStLFD>; defm PLWA : - 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RT), (ins memri34:$D_RA), - (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA", + 8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RST), (ins memri34:$D_RA), + (ins memri34_pcrel:$D_RA), "plwa $RST, $D_RA", IIC_LdStLFD>; defm PLD : - 8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RT), (ins memri34:$D_RA), - (ins memri34_pcrel:$D_RA), "pld $RT, $D_RA", + 8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RST), (ins memri34:$D_RA), + (ins memri34_pcrel:$D_RA), "pld $RST, $D_RA", IIC_LdStLFD>; } let mayStore = 1, mayLoad = 0 in { defm PSTXV : - 8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA), - (ins vsrc:$XS, memri34_pcrel:$D_RA), - "pstxv $XS, $D_RA", IIC_LdStLFD>; + 8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, memri34:$D_RA), + (ins vsrc:$XST, memri34_pcrel:$D_RA), + "pstxv $XST, $D_RA", IIC_LdStLFD>; defm PSTFS : - MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA), - (ins f4rc:$FRS, memri34_pcrel:$D_RA), - "pstfs $FRS, $D_RA", IIC_LdStLFD>; + MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, memri34:$D_RA), + (ins f4rc:$RST, memri34_pcrel:$D_RA), + "pstfs $RST, $D_RA", IIC_LdStLFD>; defm PSTFD : - MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA), - (ins f8rc:$FRS, memri34_pcrel:$D_RA), - "pstfd $FRS, $D_RA", IIC_LdStLFD>; + MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, memri34:$D_RA), + (ins f8rc:$RST, memri34_pcrel:$D_RA), + "pstfd $RST, $D_RA", IIC_LdStLFD>; defm PSTXSSP : - 8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA), - (ins vfrc:$VRS, memri34_pcrel:$D_RA), - "pstxssp $VRS, $D_RA", IIC_LdStLFD>; + 8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, memri34:$D_RA), + (ins vfrc:$RST, memri34_pcrel:$D_RA), + "pstxssp $RST, $D_RA", IIC_LdStLFD>; defm PSTXSD : - 8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA), - (ins vfrc:$VRS, memri34_pcrel:$D_RA), - "pstxsd $VRS, $D_RA", IIC_LdStLFD>; + 8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, memri34:$D_RA), + (ins vfrc:$RST, memri34_pcrel:$D_RA), + "pstxsd $RST, $D_RA", IIC_LdStLFD>; let Interpretation64Bit = 1, isCodeGenOnly = 1 in { defm PSTB8 : - MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA), - (ins g8rc:$RS, memri34_pcrel:$D_RA), - "pstb $RS, $D_RA", IIC_LdStLFD>; + MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, memri34:$D_RA), + (ins g8rc:$RST, memri34_pcrel:$D_RA), + "pstb $RST, $D_RA", IIC_LdStLFD>; defm PSTH8 : - MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA), - (ins g8rc:$RS, memri34_pcrel:$D_RA), - "psth $RS, $D_RA", IIC_LdStLFD>; + MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RST, memri34:$D_RA), + (ins g8rc:$RST, memri34_pcrel:$D_RA), + "psth $RST, $D_RA", IIC_LdStLFD>; defm PSTW8 : - MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA), - (ins g8rc:$RS, memri34_pcrel:$D_RA), - "pstw $RS, $D_RA", IIC_LdStLFD>; + MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RST, memri34:$D_RA), + (ins g8rc:$RST, memri34_pcrel:$D_RA), + "pstw $RST, $D_RA", IIC_LdStLFD>; } defm PSTB : - MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RS, memri34:$D_RA), - (ins gprc:$RS, memri34_pcrel:$D_RA), - "pstb $RS, $D_RA", IIC_LdStLFD>; + MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RST, memri34:$D_RA), + (ins gprc:$RST, memri34_pcrel:$D_RA), + "pstb $RST, $D_RA", IIC_LdStLFD>; defm PSTH : - MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RS, memri34:$D_RA), - (ins gprc:$RS, memri34_pcrel:$D_RA), - "psth $RS, $D_RA", IIC_LdStLFD>; + MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RST, memri34:$D_RA), + (ins gprc:$RST, memri34_pcrel:$D_RA), + "psth $RST, $D_RA", IIC_LdStLFD>; defm PSTW : - MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RS, memri34:$D_RA), - (ins gprc:$RS, memri34_pcrel:$D_RA), - "pstw $RS, $D_RA", IIC_LdStLFD>; + MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RST, memri34:$D_RA), + (ins gprc:$RST, memri34_pcrel:$D_RA), + "pstw $RST, $D_RA", IIC_LdStLFD>; defm PSTD : - 8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA), - (ins g8rc:$RS, memri34_pcrel:$D_RA), - "pstd $RS, $D_RA", IIC_LdStLFD>; + 8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RST, memri34:$D_RA), + (ins g8rc:$RST, memri34_pcrel:$D_RA), + "pstd $RST, $D_RA", IIC_LdStLFD>; } } @@ -770,14 +772,14 @@ string asmstr, InstrItinClass itin, list pattern> : I, XFormMemOp { bits<5> XTp; - bits<5> A; - bits<5> B; + bits<5> RA; + bits<5> RB; let Pattern = pattern; let Inst{6-9} = XTp{3-0}; let Inst{10} = XTp{4}; - let Inst{11-15} = A; - let Inst{16-20} = B; + let Inst{11-15} = RA; + let Inst{16-20} = RB; let Inst{21-30} = xo; let Inst{31} = 0; } @@ -1054,8 +1056,8 @@ def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp), (ins memrix16:$DQ_RA), "lxvp $XTp, $DQ_RA", IIC_LdStLFD, []>; - def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins memrr:$src), - "lxvpx $XTp, $src", IIC_LdStLFD, + def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins (memrr $RA, $RB):$addr), + "lxvpx $XTp, $addr", IIC_LdStLFD, []>; } @@ -1063,8 +1065,8 @@ def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp, memrix16:$DQ_RA), "stxvp $XTp, $DQ_RA", IIC_LdStLFD, []>; - def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, memrr:$dst), - "stxvpx $XTp, $dst", IIC_LdStLFD, + def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, (memrr $RA, $RB):$addr), + "stxvpx $XTp, $addr", IIC_LdStLFD, []>; } @@ -1280,8 +1282,8 @@ let Predicates = [PrefixInstrs] in { def XXPERMX : 8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, - vsrc:$XC, u3imm:$UIM), - "xxpermx $XT, $XA, $XB, $XC, $UIM", + vsrc:$XC, u3imm:$IMM), + "xxpermx $XT, $XA, $XB, $XC, $IMM", IIC_VecPerm, []>; def XXBLENDVB : 8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, @@ -1324,349 +1326,349 @@ } let Predicates = [IsISA3_1] in { - def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RT), (ins crbitrc:$BI), - "setbc $RT, $BI", IIC_IntCompare, []>, + def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RST), (ins crbitrc:$BI), + "setbc $RST, $BI", IIC_IntCompare, []>, SExt32To64, ZExt32To64; - def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RT), (ins crbitrc:$BI), - "setbcr $RT, $BI", IIC_IntCompare, []>, + def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RST), (ins crbitrc:$BI), + "setbcr $RST, $BI", IIC_IntCompare, []>, SExt32To64, ZExt32To64; - def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RT), (ins crbitrc:$BI), - "setnbc $RT, $BI", IIC_IntCompare, []>, + def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RST), (ins crbitrc:$BI), + "setnbc $RST, $BI", IIC_IntCompare, []>, SExt32To64; - def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RT), (ins crbitrc:$BI), - "setnbcr $RT, $BI", IIC_IntCompare, []>, + def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RST), (ins crbitrc:$BI), + "setnbcr $RST, $BI", IIC_IntCompare, []>, SExt32To64; let Interpretation64Bit = 1, isCodeGenOnly = 1 in { - def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RT), (ins crbitrc:$BI), - "setbc $RT, $BI", IIC_IntCompare, []>, + def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RST), (ins crbitrc:$BI), + "setbc $RST, $BI", IIC_IntCompare, []>, SExt32To64, ZExt32To64; - def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RT), (ins crbitrc:$BI), - "setbcr $RT, $BI", IIC_IntCompare, []>, + def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RST), (ins crbitrc:$BI), + "setbcr $RST, $BI", IIC_IntCompare, []>, SExt32To64, ZExt32To64; - def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RT), (ins crbitrc:$BI), - "setnbc $RT, $BI", IIC_IntCompare, []>, + def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RST), (ins crbitrc:$BI), + "setnbc $RST, $BI", IIC_IntCompare, []>, SExt32To64; - def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RT), (ins crbitrc:$BI), - "setnbcr $RT, $BI", IIC_IntCompare, []>, + def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RST), (ins crbitrc:$BI), + "setnbcr $RST, $BI", IIC_IntCompare, []>, SExt32To64; } def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT), - (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH), - "vsldbi $VRT, $VRA, $VRB, $SH", + (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD), + "vsldbi $VRT, $VRA, $VRB, $SD", IIC_VecGeneral, [(set v16i8:$VRT, (int_ppc_altivec_vsldbi v16i8:$VRA, v16i8:$VRB, - timm:$SH))]>; + timm:$SD))]>; def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT), - (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH), - "vsrdbi $VRT, $VRA, $VRB, $SH", + (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD), + "vsrdbi $VRT, $VRA, $VRB, $SD", IIC_VecGeneral, [(set v16i8:$VRT, (int_ppc_altivec_vsrdbi v16i8:$VRA, v16i8:$VRB, - timm:$SH))]>; - defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$vT), (ins vrrc:$vB), - "vstribr", "$vT, $vB", IIC_VecGeneral, - [(set v16i8:$vT, - (int_ppc_altivec_vstribr v16i8:$vB))]>; - defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$vT), (ins vrrc:$vB), - "vstribl", "$vT, $vB", IIC_VecGeneral, - [(set v16i8:$vT, - (int_ppc_altivec_vstribl v16i8:$vB))]>; - defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$vT), (ins vrrc:$vB), - "vstrihr", "$vT, $vB", IIC_VecGeneral, - [(set v8i16:$vT, - (int_ppc_altivec_vstrihr v8i16:$vB))]>; - defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$vT), (ins vrrc:$vB), - "vstrihl", "$vT, $vB", IIC_VecGeneral, - [(set v8i16:$vT, - (int_ppc_altivec_vstrihl v8i16:$vB))]>; + timm:$SD))]>; + defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$VT), (ins vrrc:$VB), + "vstribr", "$VT, $VB", IIC_VecGeneral, + [(set v16i8:$VT, + (int_ppc_altivec_vstribr v16i8:$VB))]>; + defm VSTRIBL : VXForm_VTB5_RCr<13, 0, (outs vrrc:$VT), (ins vrrc:$VB), + "vstribl", "$VT, $VB", IIC_VecGeneral, + [(set v16i8:$VT, + (int_ppc_altivec_vstribl v16i8:$VB))]>; + defm VSTRIHR : VXForm_VTB5_RCr<13, 3, (outs vrrc:$VT), (ins vrrc:$VB), + "vstrihr", "$VT, $VB", IIC_VecGeneral, + [(set v8i16:$VT, + (int_ppc_altivec_vstrihr v8i16:$VB))]>; + defm VSTRIHL : VXForm_VTB5_RCr<13, 2, (outs vrrc:$VT), (ins vrrc:$VB), + "vstrihl", "$VT, $VB", IIC_VecGeneral, + [(set v8i16:$VT, + (int_ppc_altivec_vstrihl v8i16:$VB))]>; def VINSW : - VXForm_1<207, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, gprc:$rB), - "vinsw $vD, $rB, $UIM", IIC_VecGeneral, - [(set v4i32:$vD, - (int_ppc_altivec_vinsw v4i32:$vDi, i32:$rB, timm:$UIM))]>, - RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; + VXForm_1<207, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, gprc:$VB), + "vinsw $VD, $VB, $VA", IIC_VecGeneral, + [(set v4i32:$VD, + (int_ppc_altivec_vinsw v4i32:$VDi, i32:$VB, timm:$VA))]>, + RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; def VINSD : - VXForm_1<463, (outs vrrc:$vD), (ins vrrc:$vDi, u4imm:$UIM, g8rc:$rB), - "vinsd $vD, $rB, $UIM", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vinsd v2i64:$vDi, i64:$rB, timm:$UIM))]>, - RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; + VXForm_1<463, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, g8rc:$VB), + "vinsd $VD, $VB, $VA", IIC_VecGeneral, + [(set v2i64:$VD, + (int_ppc_altivec_vinsd v2i64:$VDi, i64:$VB, timm:$VA))]>, + RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; def VINSBVLX : VXForm_VTB5_RA5_ins<15, "vinsbvlx", - [(set v16i8:$vD, - (int_ppc_altivec_vinsbvlx v16i8:$vDi, i32:$rA, - v16i8:$vB))]>; + [(set v16i8:$VD, + (int_ppc_altivec_vinsbvlx v16i8:$VDi, i32:$VA, + v16i8:$VB))]>; def VINSBVRX : VXForm_VTB5_RA5_ins<271, "vinsbvrx", - [(set v16i8:$vD, - (int_ppc_altivec_vinsbvrx v16i8:$vDi, i32:$rA, - v16i8:$vB))]>; + [(set v16i8:$VD, + (int_ppc_altivec_vinsbvrx v16i8:$VDi, i32:$VA, + v16i8:$VB))]>; def VINSHVLX : VXForm_VTB5_RA5_ins<79, "vinshvlx", - [(set v8i16:$vD, - (int_ppc_altivec_vinshvlx v8i16:$vDi, i32:$rA, - v8i16:$vB))]>; + [(set v8i16:$VD, + (int_ppc_altivec_vinshvlx v8i16:$VDi, i32:$VA, + v8i16:$VB))]>; def VINSHVRX : VXForm_VTB5_RA5_ins<335, "vinshvrx", - [(set v8i16:$vD, - (int_ppc_altivec_vinshvrx v8i16:$vDi, i32:$rA, - v8i16:$vB))]>; + [(set v8i16:$VD, + (int_ppc_altivec_vinshvrx v8i16:$VDi, i32:$VA, + v8i16:$VB))]>; def VINSWVLX : VXForm_VTB5_RA5_ins<143, "vinswvlx", - [(set v4i32:$vD, - (int_ppc_altivec_vinswvlx v4i32:$vDi, i32:$rA, - v4i32:$vB))]>; + [(set v4i32:$VD, + (int_ppc_altivec_vinswvlx v4i32:$VDi, i32:$VA, + v4i32:$VB))]>; def VINSWVRX : VXForm_VTB5_RA5_ins<399, "vinswvrx", - [(set v4i32:$vD, - (int_ppc_altivec_vinswvrx v4i32:$vDi, i32:$rA, - v4i32:$vB))]>; + [(set v4i32:$VD, + (int_ppc_altivec_vinswvrx v4i32:$VDi, i32:$VA, + v4i32:$VB))]>; def VINSBLX : VXForm_VRT5_RAB5_ins<527, "vinsblx", - [(set v16i8:$vD, - (int_ppc_altivec_vinsblx v16i8:$vDi, i32:$rA, - i32:$rB))]>; + [(set v16i8:$VD, + (int_ppc_altivec_vinsblx v16i8:$VDi, i32:$VA, + i32:$VB))]>; def VINSBRX : VXForm_VRT5_RAB5_ins<783, "vinsbrx", - [(set v16i8:$vD, - (int_ppc_altivec_vinsbrx v16i8:$vDi, i32:$rA, - i32:$rB))]>; + [(set v16i8:$VD, + (int_ppc_altivec_vinsbrx v16i8:$VDi, i32:$VA, + i32:$VB))]>; def VINSHLX : VXForm_VRT5_RAB5_ins<591, "vinshlx", - [(set v8i16:$vD, - (int_ppc_altivec_vinshlx v8i16:$vDi, i32:$rA, - i32:$rB))]>; + [(set v8i16:$VD, + (int_ppc_altivec_vinshlx v8i16:$VDi, i32:$VA, + i32:$VB))]>; def VINSHRX : VXForm_VRT5_RAB5_ins<847, "vinshrx", - [(set v8i16:$vD, - (int_ppc_altivec_vinshrx v8i16:$vDi, i32:$rA, - i32:$rB))]>; + [(set v8i16:$VD, + (int_ppc_altivec_vinshrx v8i16:$VDi, i32:$VA, + i32:$VB))]>; def VINSWLX : VXForm_VRT5_RAB5_ins<655, "vinswlx", - [(set v4i32:$vD, - (int_ppc_altivec_vinswlx v4i32:$vDi, i32:$rA, - i32:$rB))]>; + [(set v4i32:$VD, + (int_ppc_altivec_vinswlx v4i32:$VDi, i32:$VA, + i32:$VB))]>; def VINSWRX : VXForm_VRT5_RAB5_ins<911, "vinswrx", - [(set v4i32:$vD, - (int_ppc_altivec_vinswrx v4i32:$vDi, i32:$rA, - i32:$rB))]>; + [(set v4i32:$VD, + (int_ppc_altivec_vinswrx v4i32:$VDi, i32:$VA, + i32:$VB))]>; def VINSDLX : - VXForm_1<719, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB), - "vinsdlx $vD, $rA, $rB", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vinsdlx v2i64:$vDi, i64:$rA, i64:$rB))]>, - RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; + VXForm_1<719, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB), + "vinsdlx $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, + (int_ppc_altivec_vinsdlx v2i64:$VDi, i64:$VA, i64:$VB))]>, + RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; def VINSDRX : - VXForm_1<975, (outs vrrc:$vD), (ins vrrc:$vDi, g8rc:$rA, g8rc:$rB), - "vinsdrx $vD, $rA, $rB", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vinsdrx v2i64:$vDi, i64:$rA, i64:$rB))]>, - RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; - def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$rD), (ins vrrc:$vB), - "vextractbm $rD, $vB", IIC_VecGeneral, - [(set i32:$rD, - (int_ppc_altivec_vextractbm v16i8:$vB))]>, + VXForm_1<975, (outs vrrc:$VD), (ins vrrc:$VDi, g8rc:$VA, g8rc:$VB), + "vinsdrx $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, + (int_ppc_altivec_vinsdrx v2i64:$VDi, i64:$VA, i64:$VB))]>, + RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; + def VEXTRACTBM : VXForm_RD5_XO5_RS5<1602, 8, (outs gprc:$VD), (ins vrrc:$VB), + "vextractbm $VD, $VB", IIC_VecGeneral, + [(set i32:$VD, + (int_ppc_altivec_vextractbm v16i8:$VB))]>, ZExt32To64; - def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$rD), (ins vrrc:$vB), - "vextracthm $rD, $vB", IIC_VecGeneral, - [(set i32:$rD, - (int_ppc_altivec_vextracthm v8i16:$vB))]>, + def VEXTRACTHM : VXForm_RD5_XO5_RS5<1602, 9, (outs gprc:$VD), (ins vrrc:$VB), + "vextracthm $VD, $VB", IIC_VecGeneral, + [(set i32:$VD, + (int_ppc_altivec_vextracthm v8i16:$VB))]>, ZExt32To64; - def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$rD), (ins vrrc:$vB), - "vextractwm $rD, $vB", IIC_VecGeneral, - [(set i32:$rD, - (int_ppc_altivec_vextractwm v4i32:$vB))]>, + def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$VD), (ins vrrc:$VB), + "vextractwm $VD, $VB", IIC_VecGeneral, + [(set i32:$VD, + (int_ppc_altivec_vextractwm v4i32:$VB))]>, ZExt32To64; - def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$rD), (ins vrrc:$vB), - "vextractdm $rD, $vB", IIC_VecGeneral, - [(set i32:$rD, - (int_ppc_altivec_vextractdm v2i64:$vB))]>, + def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$VD), (ins vrrc:$VB), + "vextractdm $VD, $VB", IIC_VecGeneral, + [(set i32:$VD, + (int_ppc_altivec_vextractdm v2i64:$VB))]>, ZExt32To64; - def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$rD), (ins vrrc:$vB), - "vextractqm $rD, $vB", IIC_VecGeneral, - [(set i32:$rD, - (int_ppc_altivec_vextractqm v1i128:$vB))]>; - def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB), - "vexpandbm $vD, $vB", IIC_VecGeneral, - [(set v16i8:$vD, (int_ppc_altivec_vexpandbm - v16i8:$vB))]>; - def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB), - "vexpandhm $vD, $vB", IIC_VecGeneral, - [(set v8i16:$vD, (int_ppc_altivec_vexpandhm - v8i16:$vB))]>; - def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB), - "vexpandwm $vD, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (int_ppc_altivec_vexpandwm - v4i32:$vB))]>; - def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB), - "vexpanddm $vD, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (int_ppc_altivec_vexpanddm - v2i64:$vB))]>; - def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB), - "vexpandqm $vD, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (int_ppc_altivec_vexpandqm - v1i128:$vB))]>; - def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$vD), (ins g8rc:$rB), - "mtvsrbm $vD, $rB", IIC_VecGeneral, - [(set v16i8:$vD, - (int_ppc_altivec_mtvsrbm i64:$rB))]>; - def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$vD), (ins g8rc:$rB), - "mtvsrhm $vD, $rB", IIC_VecGeneral, - [(set v8i16:$vD, - (int_ppc_altivec_mtvsrhm i64:$rB))]>; - def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$vD), (ins g8rc:$rB), - "mtvsrwm $vD, $rB", IIC_VecGeneral, - [(set v4i32:$vD, - (int_ppc_altivec_mtvsrwm i64:$rB))]>; - def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$vD), (ins g8rc:$rB), - "mtvsrdm $vD, $rB", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_mtvsrdm i64:$rB))]>; - def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$vD), (ins g8rc:$rB), - "mtvsrqm $vD, $rB", IIC_VecGeneral, - [(set v1i128:$vD, - (int_ppc_altivec_mtvsrqm i64:$rB))]>; - def MTVSRBMI : DXForm<4, 10, (outs vrrc:$vD), (ins u16imm64:$D), - "mtvsrbmi $vD, $D", IIC_VecGeneral, - [(set v16i8:$vD, + def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$VD), (ins vrrc:$VB), + "vextractqm $VD, $VB", IIC_VecGeneral, + [(set i32:$VD, + (int_ppc_altivec_vextractqm v1i128:$VB))]>; + def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$VD), (ins vrrc:$VB), + "vexpandbm $VD, $VB", IIC_VecGeneral, + [(set v16i8:$VD, (int_ppc_altivec_vexpandbm + v16i8:$VB))]>; + def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$VD), (ins vrrc:$VB), + "vexpandhm $VD, $VB", IIC_VecGeneral, + [(set v8i16:$VD, (int_ppc_altivec_vexpandhm + v8i16:$VB))]>; + def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$VD), (ins vrrc:$VB), + "vexpandwm $VD, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (int_ppc_altivec_vexpandwm + v4i32:$VB))]>; + def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$VD), (ins vrrc:$VB), + "vexpanddm $VD, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (int_ppc_altivec_vexpanddm + v2i64:$VB))]>; + def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$VD), (ins vrrc:$VB), + "vexpandqm $VD, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (int_ppc_altivec_vexpandqm + v1i128:$VB))]>; + def MTVSRBM : VXForm_RD5_XO5_RS5<1602, 16, (outs vrrc:$VD), (ins g8rc:$VB), + "mtvsrbm $VD, $VB", IIC_VecGeneral, + [(set v16i8:$VD, + (int_ppc_altivec_mtvsrbm i64:$VB))]>; + def MTVSRHM : VXForm_RD5_XO5_RS5<1602, 17, (outs vrrc:$VD), (ins g8rc:$VB), + "mtvsrhm $VD, $VB", IIC_VecGeneral, + [(set v8i16:$VD, + (int_ppc_altivec_mtvsrhm i64:$VB))]>; + def MTVSRWM : VXForm_RD5_XO5_RS5<1602, 18, (outs vrrc:$VD), (ins g8rc:$VB), + "mtvsrwm $VD, $VB", IIC_VecGeneral, + [(set v4i32:$VD, + (int_ppc_altivec_mtvsrwm i64:$VB))]>; + def MTVSRDM : VXForm_RD5_XO5_RS5<1602, 19, (outs vrrc:$VD), (ins g8rc:$VB), + "mtvsrdm $VD, $VB", IIC_VecGeneral, + [(set v2i64:$VD, + (int_ppc_altivec_mtvsrdm i64:$VB))]>; + def MTVSRQM : VXForm_RD5_XO5_RS5<1602, 20, (outs vrrc:$VD), (ins g8rc:$VB), + "mtvsrqm $VD, $VB", IIC_VecGeneral, + [(set v1i128:$VD, + (int_ppc_altivec_mtvsrqm i64:$VB))]>; + def MTVSRBMI : DXForm<4, 10, (outs vrrc:$RT), (ins u16imm64:$D), + "mtvsrbmi $RT, $D", IIC_VecGeneral, + [(set v16i8:$RT, (int_ppc_altivec_mtvsrbm imm:$D))]>; - def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$rD), - (ins vrrc:$vB, u1imm:$MP), - "vcntmbb $rD, $vB, $MP", IIC_VecGeneral, - [(set i64:$rD, (int_ppc_altivec_vcntmbb - v16i8:$vB, timm:$MP))]>; - def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$rD), - (ins vrrc:$vB, u1imm:$MP), - "vcntmbh $rD, $vB, $MP", IIC_VecGeneral, - [(set i64:$rD, (int_ppc_altivec_vcntmbh - v8i16:$vB, timm:$MP))]>; - def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$rD), - (ins vrrc:$vB, u1imm:$MP), - "vcntmbw $rD, $vB, $MP", IIC_VecGeneral, - [(set i64:$rD, (int_ppc_altivec_vcntmbw - v4i32:$vB, timm:$MP))]>; - def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$rD), - (ins vrrc:$vB, u1imm:$MP), - "vcntmbd $rD, $vB, $MP", IIC_VecGeneral, - [(set i64:$rD, (int_ppc_altivec_vcntmbd - v2i64:$vB, timm:$MP))]>; - def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$vD), - (ins vrrc:$vA, vrrc:$vB, gprc:$rC), - "vextdubvlx $vD, $vA, $vB, $rC", + def VCNTMBB : VXForm_RD5_MP_VB5<1602, 12, (outs g8rc:$RD), + (ins vrrc:$VB, u1imm:$MP), + "vcntmbb $RD, $VB, $MP", IIC_VecGeneral, + [(set i64:$RD, (int_ppc_altivec_vcntmbb + v16i8:$VB, timm:$MP))]>; + def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$RD), + (ins vrrc:$VB, u1imm:$MP), + "vcntmbh $RD, $VB, $MP", IIC_VecGeneral, + [(set i64:$RD, (int_ppc_altivec_vcntmbh + v8i16:$VB, timm:$MP))]>; + def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$RD), + (ins vrrc:$VB, u1imm:$MP), + "vcntmbw $RD, $VB, $MP", IIC_VecGeneral, + [(set i64:$RD, (int_ppc_altivec_vcntmbw + v4i32:$VB, timm:$MP))]>; + def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$RD), + (ins vrrc:$VB, u1imm:$MP), + "vcntmbd $RD, $VB, $MP", IIC_VecGeneral, + [(set i64:$RD, (int_ppc_altivec_vcntmbd + v2i64:$VB, timm:$MP))]>; + def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$RT), + (ins vrrc:$RA, vrrc:$RB, gprc:$RC), + "vextdubvlx $RT, $RA, $RB, $RC", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vextdubvlx v16i8:$vA, - v16i8:$vB, - i32:$rC))]>; - def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$vD), - (ins vrrc:$vA, vrrc:$vB, gprc:$rC), - "vextdubvrx $vD, $vA, $vB, $rC", + [(set v2i64:$RT, + (int_ppc_altivec_vextdubvlx v16i8:$RA, + v16i8:$RB, + i32:$RC))]>; + def VEXTDUBVRX : VAForm_1a<25, (outs vrrc:$RT), + (ins vrrc:$RA, vrrc:$RB, gprc:$RC), + "vextdubvrx $RT, $RA, $RB, $RC", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vextdubvrx v16i8:$vA, - v16i8:$vB, - i32:$rC))]>; - def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$vD), - (ins vrrc:$vA, vrrc:$vB, gprc:$rC), - "vextduhvlx $vD, $vA, $vB, $rC", + [(set v2i64:$RT, + (int_ppc_altivec_vextdubvrx v16i8:$RA, + v16i8:$RB, + i32:$RC))]>; + def VEXTDUHVLX : VAForm_1a<26, (outs vrrc:$RT), + (ins vrrc:$RA, vrrc:$RB, gprc:$RC), + "vextduhvlx $RT, $RA, $RB, $RC", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vextduhvlx v8i16:$vA, - v8i16:$vB, - i32:$rC))]>; - def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$vD), - (ins vrrc:$vA, vrrc:$vB, gprc:$rC), - "vextduhvrx $vD, $vA, $vB, $rC", + [(set v2i64:$RT, + (int_ppc_altivec_vextduhvlx v8i16:$RA, + v8i16:$RB, + i32:$RC))]>; + def VEXTDUHVRX : VAForm_1a<27, (outs vrrc:$RT), + (ins vrrc:$RA, vrrc:$RB, gprc:$RC), + "vextduhvrx $RT, $RA, $RB, $RC", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vextduhvrx v8i16:$vA, - v8i16:$vB, - i32:$rC))]>; - def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$vD), - (ins vrrc:$vA, vrrc:$vB, gprc:$rC), - "vextduwvlx $vD, $vA, $vB, $rC", + [(set v2i64:$RT, + (int_ppc_altivec_vextduhvrx v8i16:$RA, + v8i16:$RB, + i32:$RC))]>; + def VEXTDUWVLX : VAForm_1a<28, (outs vrrc:$RT), + (ins vrrc:$RA, vrrc:$RB, gprc:$RC), + "vextduwvlx $RT, $RA, $RB, $RC", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vextduwvlx v4i32:$vA, - v4i32:$vB, - i32:$rC))]>; - def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$vD), - (ins vrrc:$vA, vrrc:$vB, gprc:$rC), - "vextduwvrx $vD, $vA, $vB, $rC", + [(set v2i64:$RT, + (int_ppc_altivec_vextduwvlx v4i32:$RA, + v4i32:$RB, + i32:$RC))]>; + def VEXTDUWVRX : VAForm_1a<29, (outs vrrc:$RT), + (ins vrrc:$RA, vrrc:$RB, gprc:$RC), + "vextduwvrx $RT, $RA, $RB, $RC", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vextduwvrx v4i32:$vA, - v4i32:$vB, - i32:$rC))]>; - def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$vD), - (ins vrrc:$vA, vrrc:$vB, gprc:$rC), - "vextddvlx $vD, $vA, $vB, $rC", + [(set v2i64:$RT, + (int_ppc_altivec_vextduwvrx v4i32:$RA, + v4i32:$RB, + i32:$RC))]>; + def VEXTDDVLX : VAForm_1a<30, (outs vrrc:$RT), + (ins vrrc:$RA, vrrc:$RB, gprc:$RC), + "vextddvlx $RT, $RA, $RB, $RC", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vextddvlx v2i64:$vA, - v2i64:$vB, - i32:$rC))]>; - def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$vD), - (ins vrrc:$vA, vrrc:$vB, gprc:$rC), - "vextddvrx $vD, $vA, $vB, $rC", + [(set v2i64:$RT, + (int_ppc_altivec_vextddvlx v2i64:$RA, + v2i64:$RB, + i32:$RC))]>; + def VEXTDDVRX : VAForm_1a<31, (outs vrrc:$RT), + (ins vrrc:$RA, vrrc:$RB, gprc:$RC), + "vextddvrx $RT, $RA, $RB, $RC", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vextddvrx v2i64:$vA, - v2i64:$vB, - i32:$rC))]>; - def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vpdepd $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>; - def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vpextd $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>; - def PDEPD : XForm_6<31, 156, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "pdepd $rA, $rS, $rB", IIC_IntGeneral, - [(set i64:$rA, (int_ppc_pdepd i64:$rS, i64:$rB))]>; - def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "pextd $rA, $rS, $rB", IIC_IntGeneral, - [(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>; - def VCFUGED : VXForm_1<1357, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vcfuged $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vcfuged v2i64:$vA, v2i64:$vB))]>; - def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$rD), (ins vrrc:$vB, u3imm:$N), - "vgnb $rD, $vB, $N", IIC_VecGeneral, - [(set i64:$rD, - (int_ppc_altivec_vgnb v1i128:$vB, timm:$N))]>; - def CFUGED : XForm_6<31, 220, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "cfuged $rA, $rS, $rB", IIC_IntGeneral, - [(set i64:$rA, (int_ppc_cfuged i64:$rS, i64:$rB))]>; + [(set v2i64:$RT, + (int_ppc_altivec_vextddvrx v2i64:$RA, + v2i64:$RB, + i32:$RC))]>; + def VPDEPD : VXForm_1<1485, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vpdepd $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, + (int_ppc_altivec_vpdepd v2i64:$VA, v2i64:$VB))]>; + def VPEXTD : VXForm_1<1421, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vpextd $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, + (int_ppc_altivec_vpextd v2i64:$VA, v2i64:$VB))]>; + def PDEPD : XForm_6<31, 156, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "pdepd $RA, $RST, $RB", IIC_IntGeneral, + [(set i64:$RA, (int_ppc_pdepd i64:$RST, i64:$RB))]>; + def PEXTD : XForm_6<31, 188, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "pextd $RA, $RST, $RB", IIC_IntGeneral, + [(set i64:$RA, (int_ppc_pextd i64:$RST, i64:$RB))]>; + def VCFUGED : VXForm_1<1357, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vcfuged $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, + (int_ppc_altivec_vcfuged v2i64:$VA, v2i64:$VB))]>; + def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$RD), (ins vrrc:$VB, u3imm:$N), + "vgnb $RD, $VB, $N", IIC_VecGeneral, + [(set i64:$RD, + (int_ppc_altivec_vgnb v1i128:$VB, timm:$N))]>; + def CFUGED : XForm_6<31, 220, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "cfuged $RA, $RST, $RB", IIC_IntGeneral, + [(set i64:$RA, (int_ppc_cfuged i64:$RST, i64:$RB))]>; def XXEVAL : 8RR_XX4Form_IMM8_XTAB6<34, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC, u8imm:$IMM), "xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral, [(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA, v2i64:$XB, v2i64:$XC, timm:$IMM))]>; - def VCLZDM : VXForm_1<1924, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vclzdm $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vclzdm v2i64:$vA, v2i64:$vB))]>; - def VCTZDM : VXForm_1<1988, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vctzdm $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, - (int_ppc_altivec_vctzdm v2i64:$vA, v2i64:$vB))]>; - def CNTLZDM : XForm_6<31, 59, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "cntlzdm $rA, $rS, $rB", IIC_IntGeneral, - [(set i64:$rA, - (int_ppc_cntlzdm i64:$rS, i64:$rB))]>; - def CNTTZDM : XForm_6<31, 571, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), - "cnttzdm $rA, $rS, $rB", IIC_IntGeneral, - [(set i64:$rA, - (int_ppc_cnttzdm i64:$rS, i64:$rB))]>; + def VCLZDM : VXForm_1<1924, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vclzdm $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, + (int_ppc_altivec_vclzdm v2i64:$VA, v2i64:$VB))]>; + def VCTZDM : VXForm_1<1988, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vctzdm $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, + (int_ppc_altivec_vctzdm v2i64:$VA, v2i64:$VB))]>; + def CNTLZDM : XForm_6<31, 59, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "cntlzdm $RA, $RST, $RB", IIC_IntGeneral, + [(set i64:$RA, + (int_ppc_cntlzdm i64:$RST, i64:$RB))]>; + def CNTTZDM : XForm_6<31, 571, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB), + "cnttzdm $RA, $RST, $RB", IIC_IntGeneral, + [(set i64:$RA, + (int_ppc_cnttzdm i64:$RST, i64:$RB))]>; def XXGENPCVBM : XForm_XT6_IMM5_VB5<60, 916, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), "xxgenpcvbm $XT, $VRB, $IMM", IIC_VecGeneral, []>; @@ -1679,85 +1681,85 @@ def XXGENPCVDM : XForm_XT6_IMM5_VB5<60, 949, (outs vsrc:$XT), (ins vrrc:$VRB, s5imm:$IMM), "xxgenpcvdm $XT, $VRB, $IMM", IIC_VecGeneral, []>; - def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB), - "vclrlb $vD, $vA, $rB", IIC_VecGeneral, - [(set v16i8:$vD, - (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>; - def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB), - "vclrrb $vD, $vA, $rB", IIC_VecGeneral, - [(set v16i8:$vD, - (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>; - def VMULLD : VXForm_1<457, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmulld $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (mul v2i64:$vA, v2i64:$vB))]>; - def VMULHSW : VXForm_1<905, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmulhsw $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (mulhs v4i32:$vA, v4i32:$vB))]>; - def VMULHUW : VXForm_1<649, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmulhuw $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (mulhu v4i32:$vA, v4i32:$vB))]>; - def VMULHSD : VXForm_1<969, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmulhsd $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (mulhs v2i64:$vA, v2i64:$vB))]>; - def VMULHUD : VXForm_1<713, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmulhud $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (mulhu v2i64:$vA, v2i64:$vB))]>; - def VMODSW : VXForm_1<1931, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmodsw $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (srem v4i32:$vA, v4i32:$vB))]>; - def VMODUW : VXForm_1<1675, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmoduw $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (urem v4i32:$vA, v4i32:$vB))]>; - def VMODSD : VXForm_1<1995, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmodsd $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (srem v2i64:$vA, v2i64:$vB))]>; - def VMODUD : VXForm_1<1739, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmodud $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (urem v2i64:$vA, v2i64:$vB))]>; - def VDIVSW : VXForm_1<395, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vdivsw $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (sdiv v4i32:$vA, v4i32:$vB))]>; - def VDIVUW : VXForm_1<139, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vdivuw $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (udiv v4i32:$vA, v4i32:$vB))]>; - def VDIVSD : VXForm_1<459, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vdivsd $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (sdiv v2i64:$vA, v2i64:$vB))]>; - def VDIVUD : VXForm_1<203, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vdivud $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (udiv v2i64:$vA, v2i64:$vB))]>; - def VDIVESW : VXForm_1<907, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vdivesw $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (int_ppc_altivec_vdivesw v4i32:$vA, - v4i32:$vB))]>; - def VDIVEUW : VXForm_1<651, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vdiveuw $vD, $vA, $vB", IIC_VecGeneral, - [(set v4i32:$vD, (int_ppc_altivec_vdiveuw v4i32:$vA, - v4i32:$vB))]>; - def VDIVESD : VXForm_1<971, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vdivesd $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (int_ppc_altivec_vdivesd v2i64:$vA, - v2i64:$vB))]>; - def VDIVEUD : VXForm_1<715, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vdiveud $vD, $vA, $vB", IIC_VecGeneral, - [(set v2i64:$vD, (int_ppc_altivec_vdiveud v2i64:$vA, - v2i64:$vB))]>; + def VCLRLB : VXForm_1<397, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB), + "vclrlb $VD, $VA, $VB", IIC_VecGeneral, + [(set v16i8:$VD, + (int_ppc_altivec_vclrlb v16i8:$VA, i32:$VB))]>; + def VCLRRB : VXForm_1<461, (outs vrrc:$VD), (ins vrrc:$VA, gprc:$VB), + "vclrrb $VD, $VA, $VB", IIC_VecGeneral, + [(set v16i8:$VD, + (int_ppc_altivec_vclrrb v16i8:$VA, i32:$VB))]>; + def VMULLD : VXForm_1<457, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmulld $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (mul v2i64:$VA, v2i64:$VB))]>; + def VMULHSW : VXForm_1<905, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmulhsw $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (mulhs v4i32:$VA, v4i32:$VB))]>; + def VMULHUW : VXForm_1<649, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmulhuw $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (mulhu v4i32:$VA, v4i32:$VB))]>; + def VMULHSD : VXForm_1<969, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmulhsd $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (mulhs v2i64:$VA, v2i64:$VB))]>; + def VMULHUD : VXForm_1<713, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmulhud $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (mulhu v2i64:$VA, v2i64:$VB))]>; + def VMODSW : VXForm_1<1931, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmodsw $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (srem v4i32:$VA, v4i32:$VB))]>; + def VMODUW : VXForm_1<1675, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmoduw $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (urem v4i32:$VA, v4i32:$VB))]>; + def VMODSD : VXForm_1<1995, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmodsd $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (srem v2i64:$VA, v2i64:$VB))]>; + def VMODUD : VXForm_1<1739, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmodud $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (urem v2i64:$VA, v2i64:$VB))]>; + def VDIVSW : VXForm_1<395, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vdivsw $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (sdiv v4i32:$VA, v4i32:$VB))]>; + def VDIVUW : VXForm_1<139, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vdivuw $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (udiv v4i32:$VA, v4i32:$VB))]>; + def VDIVSD : VXForm_1<459, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vdivsd $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (sdiv v2i64:$VA, v2i64:$VB))]>; + def VDIVUD : VXForm_1<203, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vdivud $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (udiv v2i64:$VA, v2i64:$VB))]>; + def VDIVESW : VXForm_1<907, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vdivesw $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (int_ppc_altivec_vdivesw v4i32:$VA, + v4i32:$VB))]>; + def VDIVEUW : VXForm_1<651, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vdiveuw $VD, $VA, $VB", IIC_VecGeneral, + [(set v4i32:$VD, (int_ppc_altivec_vdiveuw v4i32:$VA, + v4i32:$VB))]>; + def VDIVESD : VXForm_1<971, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vdivesd $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (int_ppc_altivec_vdivesd v2i64:$VA, + v2i64:$VB))]>; + def VDIVEUD : VXForm_1<715, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vdiveud $VD, $VA, $VB", IIC_VecGeneral, + [(set v2i64:$VD, (int_ppc_altivec_vdiveud v2i64:$VA, + v2i64:$VB))]>; def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB), "xvtlsbb $BF, $XB", IIC_VecGeneral, []>; - def BRH : XForm_11<31, 219, (outs gprc:$RA), (ins gprc:$RS), - "brh $RA, $RS", IIC_IntRotate, []>; - def BRW : XForm_11<31, 155, (outs gprc:$RA), (ins gprc:$RS), - "brw $RA, $RS", IIC_IntRotate, - [(set i32:$RA, (bswap i32:$RS))]>; + def BRH : XForm_11<31, 219, (outs gprc:$RA), (ins gprc:$RST), + "brh $RA, $RST", IIC_IntRotate, []>; + def BRW : XForm_11<31, 155, (outs gprc:$RA), (ins gprc:$RST), + "brw $RA, $RST", IIC_IntRotate, + [(set i32:$RA, (bswap i32:$RST))]>; let isCodeGenOnly = 1 in { - def BRH8 : XForm_11<31, 219, (outs g8rc:$RA), (ins g8rc:$RS), - "brh $RA, $RS", IIC_IntRotate, []>; - def BRW8 : XForm_11<31, 155, (outs g8rc:$RA), (ins g8rc:$RS), - "brw $RA, $RS", IIC_IntRotate, []>; + def BRH8 : XForm_11<31, 219, (outs g8rc:$RA), (ins g8rc:$RST), + "brh $RA, $RST", IIC_IntRotate, []>; + def BRW8 : XForm_11<31, 155, (outs g8rc:$RA), (ins g8rc:$RST), + "brw $RA, $RST", IIC_IntRotate, []>; } - def BRD : XForm_11<31, 187, (outs g8rc:$RA), (ins g8rc:$RS), - "brd $RA, $RS", IIC_IntRotate, - [(set i64:$RA, (bswap i64:$RS))]>; + def BRD : XForm_11<31, 187, (outs g8rc:$RA), (ins g8rc:$RST), + "brd $RA, $RST", IIC_IntRotate, + [(set i64:$RA, (bswap i64:$RST))]>; // The XFormMemOp flag for the following 8 instructions is set on // the instruction format. @@ -1775,70 +1777,70 @@ def STXVRDX : X_XS6_RA5_RB5<31, 237, "stxvrdx", vsrc, []>; } - def VMULESD : VXForm_1<968, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmulesd $vD, $vA, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (int_ppc_altivec_vmulesd v2i64:$vA, - v2i64:$vB))]>; - def VMULEUD : VXForm_1<712, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmuleud $vD, $vA, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (int_ppc_altivec_vmuleud v2i64:$vA, - v2i64:$vB))]>; - def VMULOSD : VXForm_1<456, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmulosd $vD, $vA, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (int_ppc_altivec_vmulosd v2i64:$vA, - v2i64:$vB))]>; - def VMULOUD : VXForm_1<200, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmuloud $vD, $vA, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (int_ppc_altivec_vmuloud v2i64:$vA, - v2i64:$vB))]>; - def VMSUMCUD : VAForm_1a<23, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), - "vmsumcud $vD, $vA, $vB, $vC", IIC_VecGeneral, - [(set v1i128:$vD, (int_ppc_altivec_vmsumcud - v2i64:$vA, v2i64:$vB, v1i128:$vC))]>; - def VDIVSQ : VXForm_1<267, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vdivsq $vD, $vA, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (sdiv v1i128:$vA, v1i128:$vB))]>; - def VDIVUQ : VXForm_1<11, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vdivuq $vD, $vA, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (udiv v1i128:$vA, v1i128:$vB))]>; - def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vdivesq $vD, $vA, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (int_ppc_altivec_vdivesq v1i128:$vA, - v1i128:$vB))]>; - def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vdiveuq $vD, $vA, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (int_ppc_altivec_vdiveuq v1i128:$vA, - v1i128:$vB))]>; - def VCMPEQUQ : VCMP <455, "vcmpequq $vD, $vA, $vB" , v1i128>; - def VCMPGTSQ : VCMP <903, "vcmpgtsq $vD, $vA, $vB" , v1i128>; - def VCMPGTUQ : VCMP <647, "vcmpgtuq $vD, $vA, $vB" , v1i128>; - def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $vD, $vA, $vB" , v1i128>; - def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $vD, $vA, $vB" , v1i128>; - def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $vD, $vA, $vB" , v1i128>; - def VMODSQ : VXForm_1<1803, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmodsq $vD, $vA, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (srem v1i128:$vA, v1i128:$vB))]>; - def VMODUQ : VXForm_1<1547, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), - "vmoduq $vD, $vA, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (urem v1i128:$vA, v1i128:$vB))]>; - def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$vD), (ins vrrc:$vB), - "vextsd2q $vD, $vB", IIC_VecGeneral, - [(set v1i128:$vD, (int_ppc_altivec_vextsd2q v2i64:$vB))]>; - def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB), - "vcmpuq $BF, $vA, $vB", IIC_VecGeneral, []>; - def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB), - "vcmpsq $BF, $vA, $vB", IIC_VecGeneral, []>; + def VMULESD : VXForm_1<968, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmulesd $VD, $VA, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (int_ppc_altivec_vmulesd v2i64:$VA, + v2i64:$VB))]>; + def VMULEUD : VXForm_1<712, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmuleud $VD, $VA, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (int_ppc_altivec_vmuleud v2i64:$VA, + v2i64:$VB))]>; + def VMULOSD : VXForm_1<456, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmulosd $VD, $VA, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (int_ppc_altivec_vmulosd v2i64:$VA, + v2i64:$VB))]>; + def VMULOUD : VXForm_1<200, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmuloud $VD, $VA, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (int_ppc_altivec_vmuloud v2i64:$VA, + v2i64:$VB))]>; + def VMSUMCUD : VAForm_1a<23, (outs vrrc:$RT), (ins vrrc:$RA, vrrc:$RB, vrrc:$RC), + "vmsumcud $RT, $RA, $RB, $RC", IIC_VecGeneral, + [(set v1i128:$RT, (int_ppc_altivec_vmsumcud + v2i64:$RA, v2i64:$RB, v1i128:$RC))]>; + def VDIVSQ : VXForm_1<267, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vdivsq $VD, $VA, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (sdiv v1i128:$VA, v1i128:$VB))]>; + def VDIVUQ : VXForm_1<11, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vdivuq $VD, $VA, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (udiv v1i128:$VA, v1i128:$VB))]>; + def VDIVESQ : VXForm_1<779, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vdivesq $VD, $VA, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (int_ppc_altivec_vdivesq v1i128:$VA, + v1i128:$VB))]>; + def VDIVEUQ : VXForm_1<523, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vdiveuq $VD, $VA, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (int_ppc_altivec_vdiveuq v1i128:$VA, + v1i128:$VB))]>; + def VCMPEQUQ : VCMP <455, "vcmpequq $VD, $VA, $VB" , v1i128>; + def VCMPGTSQ : VCMP <903, "vcmpgtsq $VD, $VA, $VB" , v1i128>; + def VCMPGTUQ : VCMP <647, "vcmpgtuq $VD, $VA, $VB" , v1i128>; + def VCMPEQUQ_rec : VCMP_rec <455, "vcmpequq. $VD, $VA, $VB" , v1i128>; + def VCMPGTSQ_rec : VCMP_rec <903, "vcmpgtsq. $VD, $VA, $VB" , v1i128>; + def VCMPGTUQ_rec : VCMP_rec <647, "vcmpgtuq. $VD, $VA, $VB" , v1i128>; + def VMODSQ : VXForm_1<1803, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmodsq $VD, $VA, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (srem v1i128:$VA, v1i128:$VB))]>; + def VMODUQ : VXForm_1<1547, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB), + "vmoduq $VD, $VA, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (urem v1i128:$VA, v1i128:$VB))]>; + def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$VD), (ins vrrc:$VB), + "vextsd2q $VD, $VB", IIC_VecGeneral, + [(set v1i128:$VD, (int_ppc_altivec_vextsd2q v2i64:$VB))]>; + def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB), + "vcmpuq $BF, $VA, $VB", IIC_VecGeneral, []>; + def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$VA, vrrc:$VB), + "vcmpsq $BF, $VA, $VB", IIC_VecGeneral, []>; def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm", - [(set v1i128:$vD, - (int_ppc_altivec_vrlqnm v1i128:$vA, - v1i128:$vB))]>; - def VRLQMI : VXForm_1<69, (outs vrrc:$vD), - (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), - "vrlqmi $vD, $vA, $vB", IIC_VecFP, - [(set v1i128:$vD, - (int_ppc_altivec_vrlqmi v1i128:$vA, v1i128:$vB, - v1i128:$vDi))]>, - RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; + [(set v1i128:$VD, + (int_ppc_altivec_vrlqnm v1i128:$VA, + v1i128:$VB))]>; + def VRLQMI : VXForm_1<69, (outs vrrc:$VD), + (ins vrrc:$VA, vrrc:$VB, vrrc:$VDi), + "vrlqmi $VD, $VA, $VB", IIC_VecFP, + [(set v1i128:$VD, + (int_ppc_altivec_vrlqmi v1i128:$VA, v1i128:$VB, + v1i128:$VDi))]>, + RegConstraint<"$VDi = $VD">, NoEncode<"$VDi">; def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>; def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>; def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>; @@ -1855,9 +1857,9 @@ def XVCVSPBF16 : XX2_XT6_XO5_XB6<60, 17, 475, "xvcvspbf16", vsrc, []>; def XVCVBF16SPN : XX2_XT6_XO5_XB6<60, 16, 475, "xvcvbf16spn", vsrc, []>; def XSMAXCQP : X_VT5_VA5_VB5<63, 676, "xsmaxcqp", - [(set f128:$vT, (PPCxsmaxc f128:$vA, f128:$vB))]>; + [(set f128:$RST, (PPCxsmaxc f128:$RA, f128:$RB))]>; def XSMINCQP : X_VT5_VA5_VB5<63, 740, "xsmincqp", - [(set f128:$vT, (PPCxsminc f128:$vA, f128:$vB))]>; + [(set f128:$RST, (PPCxsminc f128:$RA, f128:$RB))]>; } // Multiclass defining patterns for Set Boolean Extension Reverse Instructions. diff --git a/llvm/lib/Target/PowerPC/PPCInstrSPE.td b/llvm/lib/Target/PowerPC/PPCInstrSPE.td --- a/llvm/lib/Target/PowerPC/PPCInstrSPE.td +++ b/llvm/lib/Target/PowerPC/PPCInstrSPE.td @@ -116,22 +116,13 @@ InstrItinClass itin, list pattern> : I<4, OOL, IOL, asmstr, itin> { bits<5> RT; - bits<21> D; + // FIXME: bogus names, to force positional matching for the moment. + bits<21> dst_foo; let Pattern = pattern; let Inst{6-10} = RT; - let Inst{20} = D{0}; - let Inst{19} = D{1}; - let Inst{18} = D{2}; - let Inst{17} = D{3}; - let Inst{16} = D{4}; - let Inst{15} = D{5}; - let Inst{14} = D{6}; - let Inst{13} = D{7}; - let Inst{12} = D{8}; - let Inst{11} = D{9}; - let Inst{11-20} = D{0-9}; + let Inst{11-20} = dst_foo{0-9}; let Inst{21-31} = xo; } @@ -463,50 +454,50 @@ def EVLDD : EVXForm_D<769, (outs sperc:$RT), (ins spe8dis:$dst), "evldd $RT, $dst", IIC_LdStLoad, [(set f64:$RT, (load iaddr:$dst))]>; -def EVLDDX : EVXForm_1<768, (outs sperc:$RT), (ins memrr:$src), +def EVLDDX : EVXForm_1<768, (outs sperc:$RT), (ins (memrr $RA, $RB):$src), "evlddx $RT, $src", IIC_LdStLoad, [(set f64:$RT, (load xaddr:$src))]>; def EVLDH : EVXForm_D<773, (outs sperc:$RT), (ins spe8dis:$dst), "evldh $RT, $dst", IIC_LdStLoad, []>; -def EVLDHX : EVXForm_1<772, (outs sperc:$RT), (ins memrr:$src), +def EVLDHX : EVXForm_1<772, (outs sperc:$RT), (ins (memrr $RA, $RB):$src), "evldhx $RT, $src", IIC_LdStLoad, []>; def EVLDW : EVXForm_D<771, (outs sperc:$RT), (ins spe8dis:$dst), "evldw $RT, $dst", IIC_LdStLoad, []>; -def EVLDWX : EVXForm_1<770, (outs sperc:$RT), (ins memrr:$src), +def EVLDWX : EVXForm_1<770, (outs sperc:$RT), (ins (memrr $RA, $RB):$src), "evldwx $RT, $src", IIC_LdStLoad, []>; def EVLHHESPLAT : EVXForm_D<777, (outs sperc:$RT), (ins spe2dis:$dst), "evlhhesplat $RT, $dst", IIC_LdStLoad, []>; -def EVLHHESPLATX : EVXForm_1<776, (outs sperc:$RT), (ins memrr:$src), +def EVLHHESPLATX : EVXForm_1<776, (outs sperc:$RT), (ins (memrr $RA, $RB):$src), "evlhhesplatx $RT, $src", IIC_LdStLoad, []>; def EVLHHOUSPLAT : EVXForm_D<781, (outs sperc:$RT), (ins spe2dis:$dst), "evlhhousplat $RT, $dst", IIC_LdStLoad, []>; -def EVLHHOUSPLATX : EVXForm_1<780, (outs sperc:$RT), (ins memrr:$src), +def EVLHHOUSPLATX : EVXForm_1<780, (outs sperc:$RT), (ins (memrr $RA, $RB):$src), "evlhhousplatx $RT, $src", IIC_LdStLoad, []>; def EVLHHOSSPLAT : EVXForm_D<783, (outs sperc:$RT), (ins spe2dis:$dst), "evlhhossplat $RT, $dst", IIC_LdStLoad, []>; -def EVLHHOSSPLATX : EVXForm_1<782, (outs sperc:$RT), (ins memrr:$src), +def EVLHHOSSPLATX : EVXForm_1<782, (outs sperc:$RT), (ins (memrr $RA, $RB):$src), "evlhhossplatx $RT, $src", IIC_LdStLoad, []>; def EVLWHE : EVXForm_D<785, (outs sperc:$RT), (ins spe4dis:$dst), "evlwhe $RT, $dst", IIC_LdStLoad, []>; -def EVLWHEX : EVXForm_1<784, (outs sperc:$RT), (ins memrr:$src), +def EVLWHEX : EVXForm_1<784, (outs sperc:$RT), (ins (memrr $RA, $RB):$src), "evlwhex $RT, $src", IIC_LdStLoad, []>; def EVLWHOS : EVXForm_D<791, (outs sperc:$RT), (ins spe4dis:$dst), "evlwhos $RT, $dst", IIC_LdStLoad, []>; -def EVLWHOSX : EVXForm_1<790, (outs sperc:$RT), (ins memrr:$src), +def EVLWHOSX : EVXForm_1<790, (outs sperc:$RT), (ins (memrr $RA, $RB):$src), "evlwhosx $RT, $src", IIC_LdStLoad, []>; def EVLWHOU : EVXForm_D<789, (outs sperc:$RT), (ins spe4dis:$dst), "evlwhou $RT, $dst", IIC_LdStLoad, []>; -def EVLWHOUX : EVXForm_1<788, (outs sperc:$RT), (ins memrr:$src), +def EVLWHOUX : EVXForm_1<788, (outs sperc:$RT), (ins (memrr $RA, $RB):$src), "evlwhoux $RT, $src", IIC_LdStLoad, []>; def EVLWHSPLAT : EVXForm_D<797, (outs sperc:$RT), (ins spe4dis:$dst), "evlwhsplat $RT, $dst", IIC_LdStLoad, []>; -def EVLWHSPLATX : EVXForm_1<796, (outs sperc:$RT), (ins memrr:$src), +def EVLWHSPLATX : EVXForm_1<796, (outs sperc:$RT), (ins (memrr $RA, $RB):$src), "evlwhsplatx $RT, $src", IIC_LdStLoad, []>; def EVLWWSPLAT : EVXForm_D<793, (outs sperc:$RT), (ins spe4dis:$dst), "evlwwsplat $RT, $dst", IIC_LdStLoad, []>; -def EVLWWSPLATX : EVXForm_1<792, (outs sperc:$RT), (ins memrr:$src), +def EVLWWSPLATX : EVXForm_1<792, (outs sperc:$RT), (ins (memrr $RA, $RB):$src), "evlwwsplatx $RT, $src", IIC_LdStLoad, []>; def EVMERGEHI : EVXForm_1<556, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB), @@ -754,34 +745,34 @@ def EVSTDD : EVXForm_D<801, (outs), (ins sperc:$RT, spe8dis:$dst), "evstdd $RT, $dst", IIC_LdStStore, [(store f64:$RT, iaddr:$dst)]>; -def EVSTDDX : EVXForm_1<800, (outs), (ins sperc:$RT, memrr:$dst), +def EVSTDDX : EVXForm_1<800, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst), "evstddx $RT, $dst", IIC_LdStStore, [(store f64:$RT, xaddr:$dst)]>; def EVSTDH : EVXForm_D<805, (outs), (ins sperc:$RT, spe8dis:$dst), "evstdh $RT, $dst", IIC_LdStStore, []>; -def EVSTDHX : EVXForm_1<804, (outs), (ins sperc:$RT, memrr:$dst), +def EVSTDHX : EVXForm_1<804, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst), "evstdhx $RT, $dst", IIC_LdStStore, []>; def EVSTDW : EVXForm_D<803, (outs), (ins sperc:$RT, spe8dis:$dst), "evstdw $RT, $dst", IIC_LdStStore, []>; -def EVSTDWX : EVXForm_1<802, (outs), (ins sperc:$RT, memrr:$dst), +def EVSTDWX : EVXForm_1<802, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst), "evstdwx $RT, $dst", IIC_LdStStore, []>; def EVSTWHE : EVXForm_D<817, (outs), (ins sperc:$RT, spe4dis:$dst), "evstwhe $RT, $dst", IIC_LdStStore, []>; -def EVSTWHEX : EVXForm_1<816, (outs), (ins sperc:$RT, memrr:$dst), +def EVSTWHEX : EVXForm_1<816, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst), "evstwhex $RT, $dst", IIC_LdStStore, []>; def EVSTWHO : EVXForm_D<821, (outs), (ins sperc:$RT, spe4dis:$dst), "evstwho $RT, $dst", IIC_LdStStore, []>; -def EVSTWHOX : EVXForm_1<820, (outs), (ins sperc:$RT, memrr:$dst), +def EVSTWHOX : EVXForm_1<820, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst), "evstwhox $RT, $dst", IIC_LdStStore, []>; def EVSTWWE : EVXForm_D<825, (outs), (ins sperc:$RT, spe4dis:$dst), "evstwwe $RT, $dst", IIC_LdStStore, []>; -def EVSTWWEX : EVXForm_1<824, (outs), (ins sperc:$RT, memrr:$dst), +def EVSTWWEX : EVXForm_1<824, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst), "evstwwex $RT, $dst", IIC_LdStStore, []>; def EVSTWWO : EVXForm_D<829, (outs), (ins sperc:$RT, spe4dis:$dst), "evstwwo $RT, $dst", IIC_LdStStore, []>; -def EVSTWWOX : EVXForm_1<828, (outs), (ins sperc:$RT, memrr:$dst), +def EVSTWWOX : EVXForm_1<828, (outs), (ins sperc:$RT, (memrr $RA, $RB):$dst), "evstwwox $RT, $dst", IIC_LdStStore, []>; def EVSUBFSSIAAW : EVXForm_2<1219, (outs sperc:$RT), (ins sperc:$RA), @@ -803,18 +794,18 @@ let isAsmParserOnly = 1 in { // Identical to the integer Load/Stores, but to handle floats -def SPELWZ : DForm_1<32, (outs spe4rc:$rD), (ins memri:$src), - "lwz $rD, $src", IIC_LdStLoad, - [(set f32:$rD, (load iaddr:$src))]>; -def SPELWZX : XForm_1<31, 23, (outs spe4rc:$rD), (ins memrr:$src), - "lwzx $rD, $src", IIC_LdStLoad, - [(set f32:$rD, (load xaddr:$src))]>; -def SPESTW : DForm_1<36, (outs), (ins spe4rc:$rS, memri:$src), - "stw $rS, $src", IIC_LdStStore, - [(store f32:$rS, iaddr:$src)]>; -def SPESTWX : XForm_8<31, 151, (outs), (ins spe4rc:$rS, memrr:$dst), - "stwx $rS, $dst", IIC_LdStStore, - [(store f32:$rS, xaddr:$dst)]>; +def SPELWZ : DForm_1<32, (outs spe4rc:$RST), (ins memri:$addr), + "lwz $RST, $addr", IIC_LdStLoad, + [(set f32:$RST, (load iaddr:$addr))]>; +def SPELWZX : XForm_1<31, 23, (outs spe4rc:$RST), (ins (memrr $RA, $RB):$addr), + "lwzx $RST, $addr", IIC_LdStLoad, + [(set f32:$RST, (load xaddr:$addr))]>; +def SPESTW : DForm_1<36, (outs), (ins spe4rc:$RST, memri:$addr), + "stw $RST, $addr", IIC_LdStStore, + [(store f32:$RST, iaddr:$addr)]>; +def SPESTWX : XForm_8<31, 151, (outs), (ins spe4rc:$RST, (memrr $RA, $RB):$addr), + "stwx $RST, $addr", IIC_LdStStore, + [(store f32:$RST, xaddr:$addr)]>; } } // HasSPE diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -177,8 +177,8 @@ let Predicates = [HasVSX, HasP9Vector] in { class X_VT5_XO5_VB5 opcode, bits<5> xo2, bits<10> xo, string opc, list pattern> - : X_RD5_XO5_RS5; + : X_RD5_XO5_RS5; // [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /] class X_VT5_XO5_VB5_Ro opcode, bits<5> xo2, bits<10> xo, string opc, @@ -189,14 +189,14 @@ // So we use different operand class for VRB class X_VT5_XO5_VB5_TyVB opcode, bits<5> xo2, bits<10> xo, string opc, RegisterOperand vbtype, list pattern> - : X_RD5_XO5_RS5; + : X_RD5_XO5_RS5; // [PO VRT XO VRB XO /] class X_VT5_XO5_VB5_VSFR opcode, bits<5> xo2, bits<10> xo, string opc, list pattern> - : X_RD5_XO5_RS5; + : X_RD5_XO5_RS5; // [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /] class X_VT5_XO5_VB5_VSFR_Ro opcode, bits<5> xo2, bits<10> xo, string opc, @@ -206,8 +206,8 @@ // [PO T XO B XO BX /] class XX2_RT5_XO5_XB6 opcode, bits<5> xo2, bits<9> xo, string opc, list pattern> - : XX2_RD5_XO5_RS6; + : XX2_RD5_XO5_RS6; // [PO T XO B XO BX TX] class XX2_XT6_XO5_XB6 opcode, bits<5> xo2, bits<9> xo, string opc, @@ -225,8 +225,8 @@ // [PO VRT VRA VRB XO /] class X_VT5_VA5_VB5 opcode, bits<10> xo, string opc, list pattern> - : XForm_1; + : XForm_1; // [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /] class X_VT5_VA5_VB5_Ro opcode, bits<10> xo, string opc, @@ -236,9 +236,9 @@ // [PO VRT VRA VRB XO /] class X_VT5_VA5_VB5_FMA opcode, bits<10> xo, string opc, list pattern> - : XForm_1, - RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">; + : XForm_1, + RegConstraint<"$RSTi = $RST">, NoEncode<"$RSTi">; // [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /] class X_VT5_VA5_VB5_FMA_Ro opcode, bits<10> xo, string opc, @@ -248,16 +248,16 @@ class Z23_VT5_R1_VB5_RMC2_EX1 opcode, bits<8> xo, bit ex, string opc, list pattern> : Z23Form_8 { + (outs vrrc:$VRT), (ins u1imm:$R, vrrc:$VRB, u2imm:$idx), + !strconcat(opc, " $R, $VRT, $VRB, $idx"), IIC_VecFP, pattern> { let RC = ex; } // [PO BF // VRA VRB XO /] class X_BF3_VA5_VB5 opcode, bits<10> xo, string opc, list pattern> - : XForm_17 { + : XForm_17 { let Pattern = pattern; } @@ -265,14 +265,14 @@ // "out" and "in" dag class X_XT6_RA5_RB5 opcode, bits<10> xo, string opc, RegisterOperand vtype, list pattern> - : XX1Form_memOp; + : XX1Form_memOp; // [PO S RA RB XO SX] class X_XS6_RA5_RB5 opcode, bits<10> xo, string opc, RegisterOperand vtype, list pattern> - : XX1Form_memOp; + : XX1Form_memOp; } // Predicates = HasP9Vector } // AddedComplexity = 400, hasSideEffects = 0 @@ -292,30 +292,30 @@ let mayLoad = 1, mayStore = 0 in { let CodeSize = 3 in def LXSDX : XX1Form_memOp<31, 588, - (outs vsfrc:$XT), (ins memrr:$src), - "lxsdx $XT, $src", IIC_LdStLFD, + (outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr), + "lxsdx $XT, $addr", IIC_LdStLFD, []>; // Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later let CodeSize = 3 in - def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins memrr:$src), + def XFLOADf64 : PseudoXFormMemOp<(outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr), "#XFLOADf64", - [(set f64:$XT, (load XForm:$src))]>; + [(set f64:$XT, (load XForm:$addr))]>; let Predicates = [HasVSX, HasOnlySwappingMemOps] in def LXVD2X : XX1Form_memOp<31, 844, - (outs vsrc:$XT), (ins memrr:$src), - "lxvd2x $XT, $src", IIC_LdStLFD, + (outs vsrc:$XT), (ins (memrr $RA, $RB):$addr), + "lxvd2x $XT, $addr", IIC_LdStLFD, []>; def LXVDSX : XX1Form_memOp<31, 332, - (outs vsrc:$XT), (ins memrr:$src), - "lxvdsx $XT, $src", IIC_LdStLFD, []>; + (outs vsrc:$XT), (ins (memrr $RA, $RB):$addr), + "lxvdsx $XT, $addr", IIC_LdStLFD, []>; let Predicates = [HasVSX, HasOnlySwappingMemOps] in def LXVW4X : XX1Form_memOp<31, 780, - (outs vsrc:$XT), (ins memrr:$src), - "lxvw4x $XT, $src", IIC_LdStLFD, + (outs vsrc:$XT), (ins (memrr $RA, $RB):$addr), + "lxvw4x $XT, $addr", IIC_LdStLFD, []>; } // mayLoad @@ -323,27 +323,27 @@ let mayStore = 1, mayLoad = 0 in { let CodeSize = 3 in def STXSDX : XX1Form_memOp<31, 716, - (outs), (ins vsfrc:$XT, memrr:$dst), - "stxsdx $XT, $dst", IIC_LdStSTFD, + (outs), (ins vsfrc:$XT, (memrr $RA, $RB):$addr), + "stxsdx $XT, $addr", IIC_LdStSTFD, []>; // Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later let CodeSize = 3 in - def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, memrr:$dst), + def XFSTOREf64 : PseudoXFormMemOp<(outs), (ins vsfrc:$XT, (memrr $RA, $RB):$addr), "#XFSTOREf64", - [(store f64:$XT, XForm:$dst)]>; + [(store f64:$XT, XForm:$addr)]>; let Predicates = [HasVSX, HasOnlySwappingMemOps] in { // The behaviour of this instruction is endianness-specific so we provide no // pattern to match it without considering endianness. def STXVD2X : XX1Form_memOp<31, 972, - (outs), (ins vsrc:$XT, memrr:$dst), - "stxvd2x $XT, $dst", IIC_LdStSTFD, + (outs), (ins vsrc:$XT, (memrr $RA, $RB):$addr), + "stxvd2x $XT, $addr", IIC_LdStSTFD, []>; def STXVW4X : XX1Form_memOp<31, 908, - (outs), (ins vsrc:$XT, memrr:$dst), - "stxvw4x $XT, $dst", IIC_LdStSTFD, + (outs), (ins vsrc:$XT, (memrr $RA, $RB):$addr), + "stxvw4x $XT, $addr", IIC_LdStSTFD, []>; } } // mayStore @@ -611,27 +611,27 @@ let mayRaiseFPException = 0 in { def XSTDIVDP : XX3Form_1<60, 61, - (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), - "xstdivdp $crD, $XA, $XB", IIC_FPCompare, []>; + (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB), + "xstdivdp $CR, $XA, $XB", IIC_FPCompare, []>; def XSTSQRTDP : XX2Form_1<60, 106, - (outs crrc:$crD), (ins vsfrc:$XB), - "xstsqrtdp $crD, $XB", IIC_FPCompare, - [(set i32:$crD, (PPCftsqrt f64:$XB))]>; + (outs crrc:$CR), (ins vsfrc:$XB), + "xstsqrtdp $CR, $XB", IIC_FPCompare, + [(set i32:$CR, (PPCftsqrt f64:$XB))]>; def XVTDIVDP : XX3Form_1<60, 125, - (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB), - "xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>; + (outs crrc:$CR), (ins vsrc:$XA, vsrc:$XB), + "xvtdivdp $CR, $XA, $XB", IIC_FPCompare, []>; def XVTDIVSP : XX3Form_1<60, 93, - (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB), - "xvtdivsp $crD, $XA, $XB", IIC_FPCompare, []>; + (outs crrc:$CR), (ins vsrc:$XA, vsrc:$XB), + "xvtdivsp $CR, $XA, $XB", IIC_FPCompare, []>; def XVTSQRTDP : XX2Form_1<60, 234, - (outs crrc:$crD), (ins vsrc:$XB), - "xvtsqrtdp $crD, $XB", IIC_FPCompare, - [(set i32:$crD, (PPCftsqrt v2f64:$XB))]>; + (outs crrc:$CR), (ins vsrc:$XB), + "xvtsqrtdp $CR, $XB", IIC_FPCompare, + [(set i32:$CR, (PPCftsqrt v2f64:$XB))]>; def XVTSQRTSP : XX2Form_1<60, 170, - (outs crrc:$crD), (ins vsrc:$XB), - "xvtsqrtsp $crD, $XB", IIC_FPCompare, - [(set i32:$crD, (PPCftsqrt v4f32:$XB))]>; + (outs crrc:$CR), (ins vsrc:$XB), + "xvtsqrtsp $CR, $XB", IIC_FPCompare, + [(set i32:$CR, (PPCftsqrt v4f32:$XB))]>; } def XVDIVDP : XX3Form<60, 120, @@ -672,11 +672,11 @@ // Compare Instructions def XSCMPODP : XX3Form_1<60, 43, - (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), - "xscmpodp $crD, $XA, $XB", IIC_FPCompare, []>; + (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB), + "xscmpodp $CR, $XA, $XB", IIC_FPCompare, []>; def XSCMPUDP : XX3Form_1<60, 35, - (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), - "xscmpudp $crD, $XA, $XB", IIC_FPCompare, []>; + (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB), + "xscmpudp $CR, $XA, $XB", IIC_FPCompare, []>; defm XVCMPEQDP : XX3Form_Rcr<60, 99, "xvcmpeqdp", "$XT, $XA, $XB", IIC_VecFPCompare, @@ -1043,10 +1043,10 @@ "xxmrglw $XT, $XA, $XB", IIC_VecPerm, []>; def XXPERMDI : XX3Form_2<60, 10, - (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$DM), - "xxpermdi $XT, $XA, $XB, $DM", IIC_VecPerm, + (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$D), + "xxpermdi $XT, $XA, $XB, $D", IIC_VecPerm, [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB, - imm32SExt16:$DM))]>; + imm32SExt16:$D))]>; let isCodeGenOnly = 1 in // Note that the input register class for `$XA` of XXPERMDIs is `vsfrc` which // is not the same with the input register class(`vsrc`) of XXPERMDI instruction. @@ -1056,32 +1056,32 @@ // 2: With `vsfrc` register class, in the final assembly, float registers // like `f0` are used instead of vector scalar register like `vs0`. This // helps readability. - def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM), - "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>; + def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$D), + "xxpermdi $XT, $XA, $XA, $D", IIC_VecPerm, []>; def XXSEL : XX4Form<60, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC), "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>; def XXSLDWI : XX3Form_2<60, 2, - (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW), - "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm, + (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$D), + "xxsldwi $XT, $XA, $XB, $D", IIC_VecPerm, [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB, - imm32SExt16:$SHW))]>; + imm32SExt16:$D))]>; let isCodeGenOnly = 1 in def XXSLDWIs : XX3Form_2s<60, 2, - (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$SHW), - "xxsldwi $XT, $XA, $XA, $SHW", IIC_VecPerm, []>; + (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$D), + "xxsldwi $XT, $XA, $XA, $D", IIC_VecPerm, []>; def XXSPLTW : XX2Form_2<60, 164, - (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM), - "xxspltw $XT, $XB, $UIM", IIC_VecPerm, + (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$D), + "xxspltw $XT, $XB, $D", IIC_VecPerm, [(set v4i32:$XT, - (PPCxxsplt v4i32:$XB, imm32SExt16:$UIM))]>; + (PPCxxsplt v4i32:$XB, imm32SExt16:$D))]>; let isCodeGenOnly = 1 in def XXSPLTWs : XX2Form_2<60, 164, - (outs vsrc:$XT), (ins vsfrc:$XB, u2imm:$UIM), - "xxspltw $XT, $XB, $UIM", IIC_VecPerm, []>; + (outs vsrc:$XT), (ins vsfrc:$XB, u2imm:$D), + "xxspltw $XT, $XB, $D", IIC_VecPerm, []>; // The following VSX instructions were introduced in Power ISA 2.07 let Predicates = [HasVSX, HasP8Vector] in { @@ -1111,12 +1111,12 @@ // VSX scalar loads introduced in ISA 2.07 let mayLoad = 1, mayStore = 0 in { let CodeSize = 3 in - def LXSSPX : XX1Form_memOp<31, 524, (outs vssrc:$XT), (ins memrr:$src), - "lxsspx $XT, $src", IIC_LdStLFD, []>; - def LXSIWAX : XX1Form_memOp<31, 76, (outs vsfrc:$XT), (ins memrr:$src), - "lxsiwax $XT, $src", IIC_LdStLFD, []>; - def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins memrr:$src), - "lxsiwzx $XT, $src", IIC_LdStLFD, []>; + def LXSSPX : XX1Form_memOp<31, 524, (outs vssrc:$XT), (ins (memrr $RA, $RB):$addr), + "lxsspx $XT, $addr", IIC_LdStLFD, []>; + def LXSIWAX : XX1Form_memOp<31, 76, (outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr), + "lxsiwax $XT, $addr", IIC_LdStLFD, []>; + def LXSIWZX : XX1Form_memOp<31, 12, (outs vsfrc:$XT), (ins (memrr $RA, $RB):$addr), + "lxsiwzx $XT, $addr", IIC_LdStLFD, []>; // Pseudo instruction XFLOADf32 will be expanded to LXSSPX or LFSX later let CodeSize = 3 in @@ -1136,10 +1136,10 @@ // VSX scalar stores introduced in ISA 2.07 let mayStore = 1, mayLoad = 0 in { let CodeSize = 3 in - def STXSSPX : XX1Form_memOp<31, 652, (outs), (ins vssrc:$XT, memrr:$dst), - "stxsspx $XT, $dst", IIC_LdStSTFD, []>; - def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, memrr:$dst), - "stxsiwx $XT, $dst", IIC_LdStSTFD, []>; + def STXSSPX : XX1Form_memOp<31, 652, (outs), (ins vssrc:$XT, (memrr $RA, $RB):$addr), + "stxsspx $XT, $addr", IIC_LdStSTFD, []>; + def STXSIWX : XX1Form_memOp<31, 140, (outs), (ins vsfrc:$XT, (memrr $RA, $RB):$addr), + "stxsiwx $XT, $addr", IIC_LdStSTFD, []>; // Pseudo instruction XFSTOREf32 will be expanded to STXSSPX or STFSX later let CodeSize = 3 in @@ -1292,64 +1292,64 @@ let Predicates = [HasVSX, HasDirectMove] in { // VSX direct move instructions - def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsfrc:$XT), - "mfvsrd $rA, $XT", IIC_VecGeneral, - [(set i64:$rA, (PPCmfvsr f64:$XT))]>, + def MFVSRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$RA), (ins vsfrc:$XT), + "mfvsrd $RA, $XT", IIC_VecGeneral, + [(set i64:$RA, (PPCmfvsr f64:$XT))]>, Requires<[In64BitMode]>; // FIXME: Setting the hasSideEffects flag here to match current behaviour. let isCodeGenOnly = 1, hasSideEffects = 1 in - def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vsrc:$XT), - "mfvsrd $rA, $XT", IIC_VecGeneral, + def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$RA), (ins vsrc:$XT), + "mfvsrd $RA, $XT", IIC_VecGeneral, []>, Requires<[In64BitMode]>; - def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT), - "mfvsrwz $rA, $XT", IIC_VecGeneral, - [(set i32:$rA, (PPCmfvsr f64:$XT))]>, ZExt32To64; + def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$RA), (ins vsfrc:$XT), + "mfvsrwz $RA, $XT", IIC_VecGeneral, + [(set i32:$RA, (PPCmfvsr f64:$XT))]>, ZExt32To64; // FIXME: Setting the hasSideEffects flag here to match current behaviour. let isCodeGenOnly = 1, hasSideEffects = 1 in - def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsrc:$XT), - "mfvsrwz $rA, $XT", IIC_VecGeneral, + def MFVRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$RA), (ins vsrc:$XT), + "mfvsrwz $RA, $XT", IIC_VecGeneral, []>; - def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$rA), - "mtvsrd $XT, $rA", IIC_VecGeneral, - [(set f64:$XT, (PPCmtvsra i64:$rA))]>, + def MTVSRD : XX1_RS6_RD5_XO<31, 179, (outs vsfrc:$XT), (ins g8rc:$RA), + "mtvsrd $XT, $RA", IIC_VecGeneral, + [(set f64:$XT, (PPCmtvsra i64:$RA))]>, Requires<[In64BitMode]>; // FIXME: Setting the hasSideEffects flag here to match current behaviour. let isCodeGenOnly = 1, hasSideEffects = 1 in - def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$rA), - "mtvsrd $XT, $rA", IIC_VecGeneral, + def MTVRD : XX1_RS6_RD5_XO<31, 179, (outs vsrc:$XT), (ins g8rc:$RA), + "mtvsrd $XT, $RA", IIC_VecGeneral, []>, Requires<[In64BitMode]>; - def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$rA), - "mtvsrwa $XT, $rA", IIC_VecGeneral, - [(set f64:$XT, (PPCmtvsra i32:$rA))]>; + def MTVSRWA : XX1_RS6_RD5_XO<31, 211, (outs vsfrc:$XT), (ins gprc:$RA), + "mtvsrwa $XT, $RA", IIC_VecGeneral, + [(set f64:$XT, (PPCmtvsra i32:$RA))]>; // FIXME: Setting the hasSideEffects flag here to match current behaviour. let isCodeGenOnly = 1, hasSideEffects = 1 in - def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$rA), - "mtvsrwa $XT, $rA", IIC_VecGeneral, + def MTVRWA : XX1_RS6_RD5_XO<31, 211, (outs vsrc:$XT), (ins gprc:$RA), + "mtvsrwa $XT, $RA", IIC_VecGeneral, []>; - def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$rA), - "mtvsrwz $XT, $rA", IIC_VecGeneral, - [(set f64:$XT, (PPCmtvsrz i32:$rA))]>; + def MTVSRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsfrc:$XT), (ins gprc:$RA), + "mtvsrwz $XT, $RA", IIC_VecGeneral, + [(set f64:$XT, (PPCmtvsrz i32:$RA))]>; // FIXME: Setting the hasSideEffects flag here to match current behaviour. let isCodeGenOnly = 1, hasSideEffects = 1 in - def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$rA), - "mtvsrwz $XT, $rA", IIC_VecGeneral, + def MTVRWZ : XX1_RS6_RD5_XO<31, 243, (outs vsrc:$XT), (ins gprc:$RA), + "mtvsrwz $XT, $RA", IIC_VecGeneral, []>; } // HasDirectMove } // HasVSX, HasP8Vector let Predicates = [HasVSX, IsISA3_0, HasDirectMove] in { -def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$rA), - "mtvsrws $XT, $rA", IIC_VecGeneral, []>; +def MTVSRWS: XX1_RS6_RD5_XO<31, 403, (outs vsrc:$XT), (ins gprc:$RA), + "mtvsrws $XT, $RA", IIC_VecGeneral, []>; -def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$rA, g8rc:$rB), - "mtvsrdd $XT, $rA, $rB", IIC_VecGeneral, +def MTVSRDD: XX1Form<31, 435, (outs vsrc:$XT), (ins g8rc_nox0:$RA, g8rc:$RB), + "mtvsrdd $XT, $RA, $RB", IIC_VecGeneral, []>, Requires<[In64BitMode]>; -def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$rA), (ins vsrc:$XT), - "mfvsrld $rA, $XT", IIC_VecGeneral, +def MFVSRLD: XX1_RS6_RD5_XO<31, 307, (outs g8rc:$RA), (ins vsrc:$XT), + "mfvsrld $RA, $XT", IIC_VecGeneral, []>, Requires<[In64BitMode]>; } // HasVSX, IsISA3_0, HasDirectMove @@ -1358,16 +1358,16 @@ // Quad-Precision Scalar Move Instructions: // Copy Sign def XSCPSGNQP : X_VT5_VA5_VB5<63, 100, "xscpsgnqp", - [(set f128:$vT, - (fcopysign f128:$vB, f128:$vA))]>; + [(set f128:$RST, + (fcopysign f128:$RB, f128:$RA))]>; // Absolute/Negative-Absolute/Negate def XSABSQP : X_VT5_XO5_VB5<63, 0, 804, "xsabsqp", - [(set f128:$vT, (fabs f128:$vB))]>; + [(set f128:$RST, (fabs f128:$RB))]>; def XSNABSQP : X_VT5_XO5_VB5<63, 8, 804, "xsnabsqp", - [(set f128:$vT, (fneg (fabs f128:$vB)))]>; + [(set f128:$RST, (fneg (fabs f128:$RB)))]>; def XSNEGQP : X_VT5_XO5_VB5<63, 16, 804, "xsnegqp", - [(set f128:$vT, (fneg f128:$vB))]>; + [(set f128:$RST, (fneg f128:$RB))]>; //===--------------------------------------------------------------------===// // Quad-Precision Scalar Floating-Point Arithmetic Instructions: @@ -1376,74 +1376,74 @@ let mayRaiseFPException = 1 in { let isCommutable = 1 in { def XSADDQP : X_VT5_VA5_VB5 <63, 4, "xsaddqp", - [(set f128:$vT, (any_fadd f128:$vA, f128:$vB))]>; + [(set f128:$RST, (any_fadd f128:$RA, f128:$RB))]>; def XSMULQP : X_VT5_VA5_VB5 <63, 36, "xsmulqp", - [(set f128:$vT, (any_fmul f128:$vA, f128:$vB))]>; + [(set f128:$RST, (any_fmul f128:$RA, f128:$RB))]>; } def XSSUBQP : X_VT5_VA5_VB5 <63, 516, "xssubqp" , - [(set f128:$vT, (any_fsub f128:$vA, f128:$vB))]>; + [(set f128:$RST, (any_fsub f128:$RA, f128:$RB))]>; def XSDIVQP : X_VT5_VA5_VB5 <63, 548, "xsdivqp", - [(set f128:$vT, (any_fdiv f128:$vA, f128:$vB))]>; + [(set f128:$RST, (any_fdiv f128:$RA, f128:$RB))]>; // Square-Root def XSSQRTQP : X_VT5_XO5_VB5 <63, 27, 804, "xssqrtqp", - [(set f128:$vT, (any_fsqrt f128:$vB))]>; + [(set f128:$RST, (any_fsqrt f128:$RB))]>; // (Negative) Multiply-{Add/Subtract} def XSMADDQP : X_VT5_VA5_VB5_FMA <63, 388, "xsmaddqp", - [(set f128:$vT, - (any_fma f128:$vA, f128:$vB, f128:$vTi))]>; + [(set f128:$RST, + (any_fma f128:$RA, f128:$RB, f128:$RSTi))]>; def XSMSUBQP : X_VT5_VA5_VB5_FMA <63, 420, "xsmsubqp" , - [(set f128:$vT, - (any_fma f128:$vA, f128:$vB, - (fneg f128:$vTi)))]>; + [(set f128:$RST, + (any_fma f128:$RA, f128:$RB, + (fneg f128:$RSTi)))]>; def XSNMADDQP : X_VT5_VA5_VB5_FMA <63, 452, "xsnmaddqp", - [(set f128:$vT, - (fneg (any_fma f128:$vA, f128:$vB, - f128:$vTi)))]>; + [(set f128:$RST, + (fneg (any_fma f128:$RA, f128:$RB, + f128:$RSTi)))]>; def XSNMSUBQP : X_VT5_VA5_VB5_FMA <63, 484, "xsnmsubqp", - [(set f128:$vT, - (fneg (any_fma f128:$vA, f128:$vB, - (fneg f128:$vTi))))]>; + [(set f128:$RST, + (fneg (any_fma f128:$RA, f128:$RB, + (fneg f128:$RSTi))))]>; let isCommutable = 1 in { def XSADDQPO : X_VT5_VA5_VB5_Ro<63, 4, "xsaddqpo", - [(set f128:$vT, + [(set f128:$RST, (int_ppc_addf128_round_to_odd - f128:$vA, f128:$vB))]>; + f128:$RA, f128:$RB))]>; def XSMULQPO : X_VT5_VA5_VB5_Ro<63, 36, "xsmulqpo", - [(set f128:$vT, + [(set f128:$RST, (int_ppc_mulf128_round_to_odd - f128:$vA, f128:$vB))]>; + f128:$RA, f128:$RB))]>; } def XSSUBQPO : X_VT5_VA5_VB5_Ro<63, 516, "xssubqpo", - [(set f128:$vT, + [(set f128:$RST, (int_ppc_subf128_round_to_odd - f128:$vA, f128:$vB))]>; + f128:$RA, f128:$RB))]>; def XSDIVQPO : X_VT5_VA5_VB5_Ro<63, 548, "xsdivqpo", - [(set f128:$vT, + [(set f128:$RST, (int_ppc_divf128_round_to_odd - f128:$vA, f128:$vB))]>; + f128:$RA, f128:$RB))]>; def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo", - [(set f128:$vT, - (int_ppc_sqrtf128_round_to_odd f128:$vB))]>; + [(set f128:$RST, + (int_ppc_sqrtf128_round_to_odd f128:$RB))]>; def XSMADDQPO : X_VT5_VA5_VB5_FMA_Ro<63, 388, "xsmaddqpo", - [(set f128:$vT, + [(set f128:$RST, (int_ppc_fmaf128_round_to_odd - f128:$vA,f128:$vB,f128:$vTi))]>; + f128:$RA,f128:$RB,f128:$RSTi))]>; def XSMSUBQPO : X_VT5_VA5_VB5_FMA_Ro<63, 420, "xsmsubqpo" , - [(set f128:$vT, + [(set f128:$RST, (int_ppc_fmaf128_round_to_odd - f128:$vA, f128:$vB, (fneg f128:$vTi)))]>; + f128:$RA, f128:$RB, (fneg f128:$RSTi)))]>; def XSNMADDQPO: X_VT5_VA5_VB5_FMA_Ro<63, 452, "xsnmaddqpo", - [(set f128:$vT, + [(set f128:$RST, (fneg (int_ppc_fmaf128_round_to_odd - f128:$vA, f128:$vB, f128:$vTi)))]>; + f128:$RA, f128:$RB, f128:$RSTi)))]>; def XSNMSUBQPO: X_VT5_VA5_VB5_FMA_Ro<63, 484, "xsnmsubqpo", - [(set f128:$vT, + [(set f128:$RST, (fneg (int_ppc_fmaf128_round_to_odd - f128:$vA, f128:$vB, (fneg f128:$vTi))))]>; + f128:$RA, f128:$RB, (fneg f128:$RSTi))))]>; } // mayRaiseFPException // FIXME: Setting the hasSideEffects flag here to match current behaviour. @@ -1451,8 +1451,8 @@ let hasSideEffects = 1 in { // DP/QP Compare Exponents def XSCMPEXPDP : XX3Form_1<60, 59, - (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB), - "xscmpexpdp $crD, $XA, $XB", IIC_FPCompare, []>; + (outs crrc:$CR), (ins vsfrc:$XA, vsfrc:$XB), + "xscmpexpdp $CR, $XA, $XB", IIC_FPCompare, []>; def XSCMPEXPQP : X_BF3_VA5_VB5<63, 164, "xscmpexpqp", []>; let mayRaiseFPException = 1 in { @@ -1477,14 +1477,14 @@ let mayRaiseFPException = 1 in { // Convert DP -> QP def XSCVDPQP : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc, - [(set f128:$vT, (any_fpextend f64:$vB))]>; + [(set f128:$RST, (any_fpextend f64:$RB))]>; // Round & Convert QP -> DP (dword[1] is set to zero) def XSCVQPDP : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>; def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo", - [(set f64:$vT, + [(set f64:$RST, (int_ppc_truncf128_round_to_odd - f128:$vB))]>; + f128:$RB))]>; } // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero) @@ -1533,14 +1533,14 @@ // Insert Exponent DP/QP // XT NOTE: XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU - def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$rA, g8rc:$rB), - "xsiexpdp $XT, $rA, $rB", IIC_VecFP, []>; + def XSIEXPDP : XX1Form <60, 918, (outs vsrc:$XT), (ins g8rc:$RA, g8rc:$RB), + "xsiexpdp $XT, $RA, $RB", IIC_VecFP, []>; // FIXME: Setting the hasSideEffects flag here to match current behaviour. let hasSideEffects = 1 in { // vB NOTE: only vB.dword[0] is used, that's why we don't use // X_VT5_VA5_VB5 form - def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$vT), (ins vrrc:$vA, vsfrc:$vB), - "xsiexpqp $vT, $vA, $vB", IIC_VecFP, []>; + def XSIEXPQP : XForm_18<63, 868, (outs vrrc:$FRT), (ins vrrc:$FRA, vsfrc:$FRB), + "xsiexpqp $FRT, $FRA, $FRB", IIC_VecFP, []>; } // Extract Exponent/Significand DP/QP @@ -1557,18 +1557,18 @@ // XB NOTE: Only XB.dword[1] is used, but we use vsrc on XB. def XXINSERTW : XX2_RD6_UIM5_RS6<60, 181, (outs vsrc:$XT), - (ins vsrc:$XTi, vsrc:$XB, u4imm:$UIM), - "xxinsertw $XT, $XB, $UIM", IIC_VecFP, + (ins vsrc:$XTi, vsrc:$XB, u4imm:$UIM5), + "xxinsertw $XT, $XB, $UIM5", IIC_VecFP, [(set v4i32:$XT, (PPCvecinsert v4i32:$XTi, v4i32:$XB, - imm32SExt16:$UIM))]>, + imm32SExt16:$UIM5))]>, RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">; // Vector Extract Unsigned Word // FIXME: Setting the hasSideEffects flag here to match current behaviour. let hasSideEffects = 1 in def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165, - (outs vsfrc:$XT), (ins vsrc:$XB, u4imm:$UIMM), - "xxextractuw $XT, $XB, $UIMM", IIC_VecFP, []>; + (outs vsfrc:$XT), (ins vsrc:$XB, u4imm:$UIM5), + "xxextractuw $XT, $XB, $UIM5", IIC_VecFP, []>; // Vector Insert Exponent DP/SP def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc, @@ -1600,8 +1600,8 @@ (outs crrc:$BF), (ins u7imm:$DCMX, vsfrc:$XB), "xststdcdp $BF, $XB, $DCMX", IIC_VecFP, []>; def XSTSTDCQP : X_BF3_DCMX7_RS5 <63, 708, - (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$vB), - "xststdcqp $BF, $vB, $DCMX", IIC_VecFP, []>; + (outs crrc:$BF), (ins u7imm:$DCMX, vrrc:$VB), + "xststdcqp $BF, $VB, $DCMX", IIC_VecFP, []>; } // Vector Test Data Class SP/DP @@ -1666,20 +1666,20 @@ // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging. let mayLoad = 1, mayStore = 0 in { // Load Vector - def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$src), - "lxv $XT, $src", IIC_LdStLFD, []>; + def LXV : DQ_RD6_RS5_DQ12<61, 1, (outs vsrc:$XT), (ins memrix16:$addr), + "lxv $XT, $addr", IIC_LdStLFD, []>; // Load DWord - def LXSD : DSForm_1<57, 2, (outs vfrc:$vD), (ins memrix:$src), - "lxsd $vD, $src", IIC_LdStLFD, []>; + def LXSD : DSForm_1<57, 2, (outs vfrc:$RST), (ins memrix:$addr), + "lxsd $RST, $addr", IIC_LdStLFD, []>; // Load SP from src, convert it to DP, and place in dword[0] - def LXSSP : DSForm_1<57, 3, (outs vfrc:$vD), (ins memrix:$src), - "lxssp $vD, $src", IIC_LdStLFD, []>; + def LXSSP : DSForm_1<57, 3, (outs vfrc:$RST), (ins memrix:$addr), + "lxssp $RST, $addr", IIC_LdStLFD, []>; // Load as Integer Byte/Halfword & Zero Indexed def LXSIBZX : X_XT6_RA5_RB5<31, 781, "lxsibzx", vsfrc, - [(set f64:$XT, (PPClxsizx ForceXForm:$src, 1))]>; + [(set f64:$XT, (PPClxsizx ForceXForm:$addr, 1))]>; def LXSIHZX : X_XT6_RA5_RB5<31, 813, "lxsihzx", vsfrc, - [(set f64:$XT, (PPClxsizx ForceXForm:$src, 2))]>; + [(set f64:$XT, (PPClxsizx ForceXForm:$addr, 2))]>; // Load Vector Halfword*8/Byte*16 Indexed def LXVH8X : X_XT6_RA5_RB5<31, 812, "lxvh8x" , vsrc, []>; @@ -1687,14 +1687,14 @@ // Load Vector Indexed def LXVX : X_XT6_RA5_RB5<31, 268, "lxvx" , vsrc, - [(set v2f64:$XT, (load XForm:$src))]>; + [(set v2f64:$XT, (load XForm:$addr))]>; // Load Vector (Left-justified) with Length - def LXVL : XX1Form_memOp<31, 269, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB), - "lxvl $XT, $src, $rB", IIC_LdStLoad, - [(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$src, i64:$rB))]>; - def LXVLL : XX1Form_memOp<31,301, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB), - "lxvll $XT, $src, $rB", IIC_LdStLoad, - [(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$src, i64:$rB))]>; + def LXVL : XX1Form_memOp<31, 269, (outs vsrc:$XT), (ins (memr $RA):$addr, g8rc:$RB), + "lxvl $XT, $addr, $RB", IIC_LdStLoad, + [(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$addr, i64:$RB))]>; + def LXVLL : XX1Form_memOp<31,301, (outs vsrc:$XT), (ins (memr $RA):$addr, g8rc:$RB), + "lxvll $XT, $addr, $RB", IIC_LdStLoad, + [(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$addr, i64:$RB))]>; // Load Vector Word & Splat Indexed def LXVWSX : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>; @@ -1704,20 +1704,20 @@ // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging. let mayStore = 1, mayLoad = 0 in { // Store Vector - def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$dst), - "stxv $XT, $dst", IIC_LdStSTFD, []>; + def STXV : DQ_RD6_RS5_DQ12<61, 5, (outs), (ins vsrc:$XT, memrix16:$addr), + "stxv $XT, $addr", IIC_LdStSTFD, []>; // Store DWord - def STXSD : DSForm_1<61, 2, (outs), (ins vfrc:$vS, memrix:$dst), - "stxsd $vS, $dst", IIC_LdStSTFD, []>; + def STXSD : DSForm_1<61, 2, (outs), (ins vfrc:$RST, memrix:$addr), + "stxsd $RST, $addr", IIC_LdStSTFD, []>; // Convert DP of dword[0] to SP, and Store to dst - def STXSSP : DSForm_1<61, 3, (outs), (ins vfrc:$vS, memrix:$dst), - "stxssp $vS, $dst", IIC_LdStSTFD, []>; + def STXSSP : DSForm_1<61, 3, (outs), (ins vfrc:$RST, memrix:$addr), + "stxssp $RST, $addr", IIC_LdStSTFD, []>; // Store as Integer Byte/Halfword Indexed def STXSIBX : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsfrc, - [(PPCstxsix f64:$XT, ForceXForm:$dst, 1)]>; + [(PPCstxsix f64:$XT, ForceXForm:$addr, 1)]>; def STXSIHX : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsfrc, - [(PPCstxsix f64:$XT, ForceXForm:$dst, 2)]>; + [(PPCstxsix f64:$XT, ForceXForm:$addr, 2)]>; let isCodeGenOnly = 1 in { def STXSIBXv : X_XS6_RA5_RB5<31, 909, "stxsibx" , vsrc, []>; def STXSIHXv : X_XS6_RA5_RB5<31, 941, "stxsihx" , vsrc, []>; @@ -1729,19 +1729,19 @@ // Store Vector Indexed def STXVX : X_XS6_RA5_RB5<31, 396, "stxvx" , vsrc, - [(store v2f64:$XT, XForm:$dst)]>; + [(store v2f64:$XT, XForm:$addr)]>; // Store Vector (Left-justified) with Length def STXVL : XX1Form_memOp<31, 397, (outs), - (ins vsrc:$XT, memr:$dst, g8rc:$rB), - "stxvl $XT, $dst, $rB", IIC_LdStLoad, - [(int_ppc_vsx_stxvl v4i32:$XT, addr:$dst, - i64:$rB)]>; + (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB), + "stxvl $XT, $addr, $RB", IIC_LdStLoad, + [(int_ppc_vsx_stxvl v4i32:$XT, addr:$addr, + i64:$RB)]>; def STXVLL : XX1Form_memOp<31, 429, (outs), - (ins vsrc:$XT, memr:$dst, g8rc:$rB), - "stxvll $XT, $dst, $rB", IIC_LdStLoad, - [(int_ppc_vsx_stxvll v4i32:$XT, addr:$dst, - i64:$rB)]>; + (ins vsrc:$XT, (memr $RA):$addr, g8rc:$RB), + "stxvll $XT, $addr, $RB", IIC_LdStLoad, + [(int_ppc_vsx_stxvll v4i32:$XT, addr:$addr, + i64:$RB)]>; } // mayStore def DFLOADf32 : PPCPostRAExpPseudo<(outs vssrc:$XT), (ins memrix:$src), diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -877,6 +877,10 @@ let ParserMatchClass = PPCDispSPE2Operand; } +// FIXME: Remove the functions like getMemRIEncoding and decodeMemRIOperands, +// and adjust the instruction definitions. There's no need to artificially merge +// the values into a single field anymore, now that sub-operands can be named in +// instruction definitions. def memri : Operand { let PrintMethod = "printMemRegImm"; let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);