diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -316,6 +316,9 @@ "true", "Prefer likely predicted branches over selects">; +def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true", + "MFLR is a fast instruction">; + // Since new processors generally contain a superset of features of those that // came before them, the idea is to make implementations of new processors // less error prone and easier to read. @@ -424,7 +427,7 @@ !listconcat(FusionFeatures, [ DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA, - FeaturePairedVectorMemops]); + FeaturePairedVectorMemops, FeatureFastMFLR]); list P10SpecificFeatures = []; list P10InheritableFeatures = !listconcat(P9InheritableFeatures, P10AdditionalFeatures); diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h --- a/llvm/lib/Target/PowerPC/PPCSubtarget.h +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -168,6 +168,7 @@ bool UsePPCPostRASchedStrategy; bool PairedVectorMemops; bool PredictableSelectIsExpensive; + bool HasFastMFLR; bool HasModernAIXAs; bool IsAIX; @@ -316,6 +317,7 @@ bool hasPartwordAtomics() const { return HasPartwordAtomics; } bool hasQuadwordAtomics() const { return HasQuadwordAtomics; } bool hasDirectMove() const { return HasDirectMove; } + bool hasFastMFLR() const { return HasFastMFLR; } Align getPlatformStackAlignment() const { return Align(16); diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -149,6 +149,7 @@ UsePPCPostRASchedStrategy = false; PairedVectorMemops = false; PredictableSelectIsExpensive = false; + HasFastMFLR = false; HasModernAIXAs = false; IsAIX = false;