Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.td =================================================================== --- llvm/lib/Target/AArch64/AArch64RegisterInfo.td +++ llvm/lib/Target/AArch64/AArch64RegisterInfo.td @@ -1167,6 +1167,10 @@ let ParserMatchClass = ZPRVectorList<64, 2>; } +def ZZ_q : RegisterOperand"> { + let ParserMatchClass = ZPRVectorList<128, 2>; +} + def ZZZ_b : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<8, 3>; } @@ -1183,6 +1187,10 @@ let ParserMatchClass = ZPRVectorList<64, 3>; } +def ZZZ_q : RegisterOperand"> { + let ParserMatchClass = ZPRVectorList<128, 3>; +} + def ZZZZ_b : RegisterOperand"> { let ParserMatchClass = ZPRVectorList<8, 4>; } @@ -1199,6 +1207,10 @@ let ParserMatchClass = ZPRVectorList<64, 4>; } +def ZZZZ_q : RegisterOperand"> { + let ParserMatchClass = ZPRVectorList<128, 4>; +} + // SME2 multiple-of-2 or 4 multi-vector operands def ZPR2Mul2 : RegisterClass<"AArch64", [untyped], 128, (add (decimate ZSeqPairs, 2))> { let Size = 256; Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1011,32 +1011,42 @@ let Predicates = [HasSVEorSME] in { // LD(2|3|4) structured loads with reg+immediate - defm LD2B_IMM : sve_mem_eld_si<0b00, 0b01, ZZ_b, "ld2b", simm4s2>; - defm LD3B_IMM : sve_mem_eld_si<0b00, 0b10, ZZZ_b, "ld3b", simm4s3>; - defm LD4B_IMM : sve_mem_eld_si<0b00, 0b11, ZZZZ_b, "ld4b", simm4s4>; - defm LD2H_IMM : sve_mem_eld_si<0b01, 0b01, ZZ_h, "ld2h", simm4s2>; - defm LD3H_IMM : sve_mem_eld_si<0b01, 0b10, ZZZ_h, "ld3h", simm4s3>; - defm LD4H_IMM : sve_mem_eld_si<0b01, 0b11, ZZZZ_h, "ld4h", simm4s4>; - defm LD2W_IMM : sve_mem_eld_si<0b10, 0b01, ZZ_s, "ld2w", simm4s2>; - defm LD3W_IMM : sve_mem_eld_si<0b10, 0b10, ZZZ_s, "ld3w", simm4s3>; - defm LD4W_IMM : sve_mem_eld_si<0b10, 0b11, ZZZZ_s, "ld4w", simm4s4>; - defm LD2D_IMM : sve_mem_eld_si<0b11, 0b01, ZZ_d, "ld2d", simm4s2>; - defm LD3D_IMM : sve_mem_eld_si<0b11, 0b10, ZZZ_d, "ld3d", simm4s3>; - defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, ZZZZ_d, "ld4d", simm4s4>; + defm LD2B_IMM : sve_mem_eld_si<0b00, 0b01, 0b0, ZZ_b, "ld2b", simm4s2>; + defm LD3B_IMM : sve_mem_eld_si<0b00, 0b10, 0b0, ZZZ_b, "ld3b", simm4s3>; + defm LD4B_IMM : sve_mem_eld_si<0b00, 0b11, 0b0, ZZZZ_b, "ld4b", simm4s4>; + defm LD2H_IMM : sve_mem_eld_si<0b01, 0b01, 0b0, ZZ_h, "ld2h", simm4s2>; + defm LD3H_IMM : sve_mem_eld_si<0b01, 0b10, 0b0, ZZZ_h, "ld3h", simm4s3>; + defm LD4H_IMM : sve_mem_eld_si<0b01, 0b11, 0b0, ZZZZ_h, "ld4h", simm4s4>; + defm LD2W_IMM : sve_mem_eld_si<0b10, 0b01, 0b0, ZZ_s, "ld2w", simm4s2>; + defm LD3W_IMM : sve_mem_eld_si<0b10, 0b10, 0b0, ZZZ_s, "ld3w", simm4s3>; + defm LD4W_IMM : sve_mem_eld_si<0b10, 0b11, 0b0, ZZZZ_s, "ld4w", simm4s4>; + defm LD2D_IMM : sve_mem_eld_si<0b11, 0b01, 0b0, ZZ_d, "ld2d", simm4s2>; + defm LD3D_IMM : sve_mem_eld_si<0b11, 0b10, 0b0, ZZZ_d, "ld3d", simm4s3>; + defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, 0b0, ZZZZ_d, "ld4d", simm4s4>; + let Predicates = [HasSVE2p1_or_HasSME2p1] in { + defm LD2Q_IMM : sve_mem_eld_si<0b00, 0b01, 0b1, ZZ_q, "ld2q", simm4s2>; + defm LD3Q_IMM : sve_mem_eld_si<0b00, 0b10, 0b1, ZZZ_q, "ld3q", simm4s3>; + defm LD4Q_IMM : sve_mem_eld_si<0b00, 0b11, 0b1, ZZZZ_q, "ld4q", simm4s4>; + } // LD(2|3|4) structured loads (register + register) - def LD2B : sve_mem_eld_ss<0b00, 0b01, ZZ_b, "ld2b", GPR64NoXZRshifted8>; - def LD3B : sve_mem_eld_ss<0b00, 0b10, ZZZ_b, "ld3b", GPR64NoXZRshifted8>; - def LD4B : sve_mem_eld_ss<0b00, 0b11, ZZZZ_b, "ld4b", GPR64NoXZRshifted8>; - def LD2H : sve_mem_eld_ss<0b01, 0b01, ZZ_h, "ld2h", GPR64NoXZRshifted16>; - def LD3H : sve_mem_eld_ss<0b01, 0b10, ZZZ_h, "ld3h", GPR64NoXZRshifted16>; - def LD4H : sve_mem_eld_ss<0b01, 0b11, ZZZZ_h, "ld4h", GPR64NoXZRshifted16>; - def LD2W : sve_mem_eld_ss<0b10, 0b01, ZZ_s, "ld2w", GPR64NoXZRshifted32>; - def LD3W : sve_mem_eld_ss<0b10, 0b10, ZZZ_s, "ld3w", GPR64NoXZRshifted32>; - def LD4W : sve_mem_eld_ss<0b10, 0b11, ZZZZ_s, "ld4w", GPR64NoXZRshifted32>; - def LD2D : sve_mem_eld_ss<0b11, 0b01, ZZ_d, "ld2d", GPR64NoXZRshifted64>; - def LD3D : sve_mem_eld_ss<0b11, 0b10, ZZZ_d, "ld3d", GPR64NoXZRshifted64>; - def LD4D : sve_mem_eld_ss<0b11, 0b11, ZZZZ_d, "ld4d", GPR64NoXZRshifted64>; + def LD2B : sve_mem_eld_ss<0b00, 0b01, 0b0, ZZ_b, "ld2b", GPR64NoXZRshifted8>; + def LD3B : sve_mem_eld_ss<0b00, 0b10, 0b0, ZZZ_b, "ld3b", GPR64NoXZRshifted8>; + def LD4B : sve_mem_eld_ss<0b00, 0b11, 0b0, ZZZZ_b, "ld4b", GPR64NoXZRshifted8>; + def LD2H : sve_mem_eld_ss<0b01, 0b01, 0b0, ZZ_h, "ld2h", GPR64NoXZRshifted16>; + def LD3H : sve_mem_eld_ss<0b01, 0b10, 0b0, ZZZ_h, "ld3h", GPR64NoXZRshifted16>; + def LD4H : sve_mem_eld_ss<0b01, 0b11, 0b0, ZZZZ_h, "ld4h", GPR64NoXZRshifted16>; + def LD2W : sve_mem_eld_ss<0b10, 0b01, 0b0, ZZ_s, "ld2w", GPR64NoXZRshifted32>; + def LD3W : sve_mem_eld_ss<0b10, 0b10, 0b0, ZZZ_s, "ld3w", GPR64NoXZRshifted32>; + def LD4W : sve_mem_eld_ss<0b10, 0b11, 0b0, ZZZZ_s, "ld4w", GPR64NoXZRshifted32>; + def LD2D : sve_mem_eld_ss<0b11, 0b01, 0b0, ZZ_d, "ld2d", GPR64NoXZRshifted64>; + def LD3D : sve_mem_eld_ss<0b11, 0b10, 0b0, ZZZ_d, "ld3d", GPR64NoXZRshifted64>; + def LD4D : sve_mem_eld_ss<0b11, 0b11, 0b0, ZZZZ_d, "ld4d", GPR64NoXZRshifted64>; + let Predicates = [HasSVE2p1_or_HasSME2p1] in { + def LD2Q : sve_mem_eld_ss<0b00, 0b01, 0b1, ZZ_q, "ld2q", GPR64NoXZRshifted128>; + def LD3Q : sve_mem_eld_ss<0b00, 0b10, 0b1, ZZZ_q, "ld3q", GPR64NoXZRshifted128>; + def LD4Q : sve_mem_eld_ss<0b00, 0b11, 0b1, ZZZZ_q, "ld4q", GPR64NoXZRshifted128>; + } } // End HasSVEorSME let Predicates = [HasSVE] in { @@ -1424,6 +1434,11 @@ defm ST2D_IMM : sve_mem_est_si<0b11, 0b01, ZZ_d, "st2d", simm4s2>; defm ST3D_IMM : sve_mem_est_si<0b11, 0b10, ZZZ_d, "st3d", simm4s3>; defm ST4D_IMM : sve_mem_est_si<0b11, 0b11, ZZZZ_d, "st4d", simm4s4>; + let Predicates = [HasSVE2p1_or_HasSME2p1] in { + defm ST2Q_IMM : sve_mem_128b_est_si<0b01, ZZ_q, "st2q", simm4s2>; + defm ST3Q_IMM : sve_mem_128b_est_si<0b10, ZZZ_q, "st3q", simm4s3>; + defm ST4Q_IMM : sve_mem_128b_est_si<0b11, ZZZZ_q, "st4q", simm4s4>; + } // ST(2|3|4) structured stores (register + register) def ST2B : sve_mem_est_ss<0b00, 0b01, ZZ_b, "st2b", GPR64NoXZRshifted8>; @@ -1438,7 +1453,11 @@ def ST2D : sve_mem_est_ss<0b11, 0b01, ZZ_d, "st2d", GPR64NoXZRshifted64>; def ST3D : sve_mem_est_ss<0b11, 0b10, ZZZ_d, "st3d", GPR64NoXZRshifted64>; def ST4D : sve_mem_est_ss<0b11, 0b11, ZZZZ_d, "st4d", GPR64NoXZRshifted64>; - + let Predicates = [HasSVE2p1_or_HasSME2p1] in { + def ST2Q : sve_mem_128b_est_ss<0b01, ZZ_q, "st2q", GPR64NoXZRshifted128>; + def ST3Q : sve_mem_128b_est_ss<0b10, ZZZ_q, "st3q", GPR64NoXZRshifted128>; + def ST4Q : sve_mem_128b_est_ss<0b11, ZZZZ_q, "st4q", GPR64NoXZRshifted128>; + } // Non-temporal contiguous stores (register + immediate) defm STNT1B_ZRI : sve_mem_cstnt_si<0b00, "stnt1b", Z_b, ZPR8>; defm STNT1H_ZRI : sve_mem_cstnt_si<0b01, "stnt1h", Z_h, ZPR16>; Index: llvm/lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- llvm/lib/Target/AArch64/SVEInstrFormats.td +++ llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -5810,6 +5810,37 @@ (!cast(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; } + +class sve_mem_128b_est_si nregs, RegisterOperand VecList, + string asm, Operand immtype> + : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4), + asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", + "", []>, Sched<[]> { + bits<5> Zt; + bits<5> Rn; + bits<3> Pg; + bits<4> imm4; + let Inst{31-24} = 0b11100100; + let Inst{23-22} = nregs; + let Inst{21-20} = 0b00; + let Inst{19-16} = imm4; + let Inst{15-13} = 0b000; + let Inst{12-10} = Pg; + let Inst{9-5} = Rn; + let Inst{4-0} = Zt; + + let mayStore = 1; +} + +multiclass sve_mem_128b_est_si nregs, RegisterOperand VecList, + string asm, Operand immtype> { + def NAME : sve_mem_128b_est_si; + + def : InstAlias(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; +} + + class sve_mem_est_ss sz, bits<2> nregs, RegisterOperand VecList, string asm, RegisterOperand gprty> : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), @@ -5832,6 +5863,29 @@ let mayStore = 1; } + +class sve_mem_128b_est_ss nregs, RegisterOperand VecList, + string asm, RegisterOperand gprty> + : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), + asm, "\t$Zt, $Pg, [$Rn, $Rm]", + "", []>, Sched<[]> { + bits<5> Zt; + bits<5> Rn; + bits<3> Pg; + bits<5> Rm; + let Inst{31-24} = 0b11100100; + let Inst{23-22} = nregs; + let Inst{21} = 0b1; + let Inst{20-16} = Rm; + let Inst{15-13} = 0b000; + let Inst{12-10} = Pg; + let Inst{9-5} = Rn; + let Inst{4-0} = Zt; + + let mayStore = 1; +} + + class sve_mem_cst_ss_base dtype, string asm, RegisterOperand listty, RegisterOperand gprty> : I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), @@ -5862,6 +5916,7 @@ (!cast(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; } + class sve_mem_cstnt_si msz, string asm, RegisterOperand VecList> : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]", @@ -7060,8 +7115,8 @@ ZPRRegOp zprty> : sve_mem_cld_si_base; -class sve_mem_eld_si sz, bits<2> nregs, RegisterOperand VecList, - string asm, Operand immtype> +class sve_mem_eld_si sz, bits<2> nregs, bit q, + RegisterOperand VecList, string asm, Operand immtype> : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4), asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", "", @@ -7071,9 +7126,9 @@ bits<5> Rn; bits<4> imm4; let Inst{31-25} = 0b1010010; - let Inst{24-23} = sz; - let Inst{22-21} = nregs; - let Inst{20} = 0; + let Inst{24-23} = !if(q, nregs, sz); + let Inst{22-21} = !if(q, 0b00, nregs); + let Inst{20} = q; let Inst{19-16} = imm4; let Inst{15-13} = 0b111; let Inst{12-10} = Pg; @@ -7083,16 +7138,18 @@ let mayLoad = 1; } -multiclass sve_mem_eld_si sz, bits<2> nregs, RegisterOperand VecList, - string asm, Operand immtype> { - def NAME : sve_mem_eld_si; +multiclass sve_mem_eld_si sz, bits<2> nregs, bit q, + RegisterOperand VecList, string asm, Operand immtype> { + def NAME : sve_mem_eld_si; def : InstAlias(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>; } -class sve_mem_eld_ss sz, bits<2> nregs, RegisterOperand VecList, - string asm, RegisterOperand gprty> + +class sve_mem_eld_ss sz, bits<2> nregs, bit q, + RegisterOperand VecList, string asm, + RegisterOperand gprty> : I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", @@ -7102,10 +7159,12 @@ bits<5> Rn; bits<5> Zt; let Inst{31-25} = 0b1010010; - let Inst{24-23} = sz; - let Inst{22-21} = nregs; + let Inst{24-23} = !if(q, nregs, sz); + let Inst{22-21} = !if(q, 0b01, nregs); let Inst{20-16} = Rm; - let Inst{15-13} = 0b110; + let Inst{15} = 0b1; + let Inst{14} = !if(q, 0b0, 0b1); + let Inst{13} = 0b0; let Inst{12-10} = Pg; let Inst{9-5} = Rn; let Inst{4-0} = Zt; Index: llvm/test/MC/AArch64/SVE2p1/ld2q-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/ld2q-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid predicate register + +ld2q {z0.q, z1.q}, p8/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: ld2q {z0.q, z1.q}, p8/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ld2q {z23.q, z24.q}, p2/m, [x0, x0, lsl #4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ld2q {z23.q, z24.q}, p2/m, [x0, x0, lsl #4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ld2q {z21.q, z22.q}, p2.q, [x10, x21, lsl #4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: ld2q {z21.q, z22.q}, p2.q, [x10, x21, lsl #4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate offset + +ld2q {z23.q, z24.q}, p3/z, [x13, #-17, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14]. +// CHECK-NEXT: ld2q {z23.q, z24.q}, p3/z, [x13, #-17, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ld2q {z23.q, z24.q}, p3/z, [x13, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14]. +// CHECK-NEXT: ld2q {z23.q, z24.q}, p3/z, [x13, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/ld2q.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/ld2q.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +ld2q {z0.q, z1.q}, p0/z, [x0, x0, lsl #4] // 10100100-10100000-10000000-00000000 +// CHECK-INST: ld2q { z0.q, z1.q }, p0/z, [x0, x0, lsl #4] +// CHECK-ENCODING: [0x00,0x80,0xa0,0xa4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a4a08000 + +ld2q {z21.q, z22.q}, p5/z, [x10, x21, lsl #4] // 10100100-10110101-10010101-01010101 +// CHECK-INST: ld2q { z21.q, z22.q }, p5/z, [x10, x21, lsl #4] +// CHECK-ENCODING: [0x55,0x95,0xb5,0xa4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a4b59555 + +ld2q {z23.q, z24.q}, p3/z, [x13, x8, lsl #4] // 10100100-10101000-10001101-10110111 +// CHECK-INST: ld2q { z23.q, z24.q }, p3/z, [x13, x8, lsl #4] +// CHECK-ENCODING: [0xb7,0x8d,0xa8,0xa4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a4a88db7 + +ld2q {z0.q, z1.q}, p0/z, [x0] // 10100100-10010000-11100000-00000000 +// CHECK-INST: ld2q { z0.q, z1.q }, p0/z, [x0] +// CHECK-ENCODING: [0x00,0xe0,0x90,0xa4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a490e000 + +ld2q {z21.q, z22.q}, p5/z, [x10, #10, mul vl] // 10100100-10010101-11110101-01010101 +// CHECK-INST: ld2q { z21.q, z22.q }, p5/z, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0xf5,0x95,0xa4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a495f555 + +ld2q {z23.q, z24.q}, p3/z, [x13, #-16, mul vl] // 10100100-10011000-11101101-10110111 +// CHECK-INST: ld2q { z23.q, z24.q }, p3/z, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0xed,0x98,0xa4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a498edb7 + +ld2q {z31.q, z0.q}, p7/z, [sp, #-2, mul vl] // 10100100-10011111-11111111-11111111 +// CHECK-INST: ld2q { z31.q, z0.q }, p7/z, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0xff,0x9f,0xa4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a49fffff Index: llvm/test/MC/AArch64/SVE2p1/ld3q-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/ld3q-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid predicate register + +ld3q {z0.q, z1.q, z2.q}, p8/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: ld3q {z0.q, z1.q, z2.q}, p8/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ld3q {z23.q, z24.q, z25.q}, p2/m, [x0, x0, lsl #4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ld3q {z23.q, z24.q, z25.q}, p2/m, [x0, x0, lsl #4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ld3q {z21.q, z22.q, z23.q}, p2.q, [x10, x21, lsl #4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: ld3q {z21.q, z22.q, z23.q}, p2.q, [x10, x21, lsl #4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate offset + +ld3q {z23.q, z24.q, z25.q}, p3/z, [x13, #-25, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21]. +// CHECK-NEXT: ld3q {z23.q, z24.q, z25.q}, p3/z, [x13, #-25, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ld3q {z23.q, z24.q, z25.q}, p3/z, [x13, #22, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21]. +// CHECK-NEXT: ld3q {z23.q, z24.q, z25.q}, p3/z, [x13, #22, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/ld3q.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/ld3q.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +ld3q {z0.q, z1.q, z2.q}, p0/z, [x0, x0, lsl #4] // 10100101-00100000-10000000-00000000 +// CHECK-INST: ld3q { z0.q - z2.q }, p0/z, [x0, x0, lsl #4] +// CHECK-ENCODING: [0x00,0x80,0x20,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a5208000 + +ld3q {z21.q, z22.q, z23.q}, p5/z, [x10, x21, lsl #4] // 10100101-00110101-10010101-01010101 +// CHECK-INST: ld3q { z21.q - z23.q }, p5/z, [x10, x21, lsl #4] +// CHECK-ENCODING: [0x55,0x95,0x35,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a5359555 + +ld3q {z23.q, z24.q, z25.q}, p3/z, [x13, x8, lsl #4] // 10100101-00101000-10001101-10110111 +// CHECK-INST: ld3q { z23.q - z25.q }, p3/z, [x13, x8, lsl #4] +// CHECK-ENCODING: [0xb7,0x8d,0x28,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a5288db7 + +ld3q {z0.q, z1.q, z2.q}, p0/z, [x0] // 10100101-00010000-11100000-00000000 +// CHECK-INST: ld3q { z0.q - z2.q }, p0/z, [x0] +// CHECK-ENCODING: [0x00,0xe0,0x10,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a510e000 + +ld3q {z21.q, z22.q, z23.q}, p5/z, [x10, #15, mul vl] // 10100101-00010101-11110101-01010101 +// CHECK-INST: ld3q { z21.q - z23.q }, p5/z, [x10, #15, mul vl] +// CHECK-ENCODING: [0x55,0xf5,0x15,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a515f555 + +ld3q {z23.q, z24.q, z25.q}, p3/z, [x13, #-24, mul vl] // 10100101-00011000-11101101-10110111 +// CHECK-INST: ld3q { z23.q - z25.q }, p3/z, [x13, #-24, mul vl] +// CHECK-ENCODING: [0xb7,0xed,0x18,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a518edb7 + +ld3q {z31.q, z0.q, z1.q}, p7/z, [sp, #-3, mul vl] // 10100101-00011111-11111111-11111111 +// CHECK-INST: ld3q { z31.q, z0.q, z1.q }, p7/z, [sp, #-3, mul vl] +// CHECK-ENCODING: [0xff,0xff,0x1f,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a51fffff Index: llvm/test/MC/AArch64/SVE2p1/ld4q-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/ld4q-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid predicate register + +ld4q {z0.q, z1.q, z2.q, z3.q}, p8/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: ld4q {z0.q, z1.q, z2.q, z3.q}, p8/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ld4q {z23.q, z24.q, z25.q, z26.q}, p2/m, [x0, x0, lsl #4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: ld4q {z23.q, z24.q, z25.q, z26.q}, p2/m, [x0, x0, lsl #4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ld4q {z21.q, z22.q, z23.q, z24.q}, p2.q, [x10, x21, lsl #4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: ld4q {z21.q, z22.q, z23.q, z24.q}, p2.q, [x10, x21, lsl #4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate offset + +ld4q {z23.q, z24.q, z25.q, z26.q}, p3/z, [x13, #-33, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]. +// CHECK-NEXT: ld4q {z23.q, z24.q, z25.q, z26.q}, p3/z, [x13, #-33, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +ld4q {z23.q, z24.q, z25.q, z26.q}, p3/z, [x13, #29, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]. +// CHECK-NEXT: ld4q {z23.q, z24.q, z25.q, z26.q}, p3/z, [x13, #29, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/ld4q.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/ld4q.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +ld4q {z0.q, z1.q, z2.q, z3.q}, p0/z, [x0, x0, lsl #4] // 10100101-10100000-10000000-00000000 +// CHECK-INST: ld4q { z0.q - z3.q }, p0/z, [x0, x0, lsl #4] +// CHECK-ENCODING: [0x00,0x80,0xa0,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a5a08000 + +ld4q {z21.q, z22.q, z23.q, z24.q}, p5/z, [x10, x21, lsl #4] // 10100101-10110101-10010101-01010101 +// CHECK-INST: ld4q { z21.q - z24.q }, p5/z, [x10, x21, lsl #4] +// CHECK-ENCODING: [0x55,0x95,0xb5,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a5b59555 + +ld4q {z23.q, z24.q, z25.q, z26.q}, p3/z, [x13, x8, lsl #4] // 10100101-10101000-10001101-10110111 +// CHECK-INST: ld4q { z23.q - z26.q }, p3/z, [x13, x8, lsl #4] +// CHECK-ENCODING: [0xb7,0x8d,0xa8,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a5a88db7 + +ld4q {z0.q, z1.q, z2.q, z3.q}, p0/z, [x0] // 10100101-10010000-11100000-00000000 +// CHECK-INST: ld4q { z0.q - z3.q }, p0/z, [x0] +// CHECK-ENCODING: [0x00,0xe0,0x90,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a590e000 + +ld4q {z21.q, z22.q, z23.q, z24.q}, p5/z, [x10, #20, mul vl] // 10100101-10010101-11110101-01010101 +// CHECK-INST: ld4q { z21.q - z24.q }, p5/z, [x10, #20, mul vl] +// CHECK-ENCODING: [0x55,0xf5,0x95,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a595f555 + +ld4q {z23.q, z24.q, z25.q, z26.q}, p3/z, [x13, #-32, mul vl] // 10100101-10011000-11101101-10110111 +// CHECK-INST: ld4q { z23.q - z26.q }, p3/z, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb7,0xed,0x98,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a598edb7 + +ld4q {z31.q, z0.q, z1.q, z2.q}, p7/z, [sp, #-4, mul vl] // 10100101-10011111-11111111-11111111 +// CHECK-INST: ld4q { z31.q, z0.q, z1.q, z2.q }, p7/z, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xff,0xff,0x9f,0xa5] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: a59fffff Index: llvm/test/MC/AArch64/SVE2p1/st2q-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st2q-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid predicate register + +st2q {z0.q, z1.q}, p8, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: st2q {z0.q, z1.q}, p8, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2q {z23.q, z24.q}, p2/m, [x0, x0, lsl #4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: st2q {z23.q, z24.q}, p2/m, [x0, x0, lsl #4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2q {z21.q, z22.q}, p2.q, [x10, x21, lsl #4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: st2q {z21.q, z22.q}, p2.q, [x10, x21, lsl #4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate offset + +st2q {z23.q, z24.q}, p3, [x13, #-17, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14]. +// CHECK-NEXT: st2q {z23.q, z24.q}, p3, [x13, #-17, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st2q {z23.q, z24.q}, p3, [x13, #15, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [-16, 14]. +// CHECK-NEXT: st2q {z23.q, z24.q}, p3, [x13, #15, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/st2q.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st2q.s @@ -0,0 +1,57 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +st2q {z0.q, z1.q}, p0, [x0, x0, lsl #4] // 11100100-01100000-00000000-00000000 +// CHECK-INST: st2q { z0.q, z1.q }, p0, [x0, x0, lsl #4] +// CHECK-ENCODING: [0x00,0x00,0x60,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4600000 + +st2q {z21.q, z22.q}, p5, [x10, x21, lsl #4] // 11100100-01110101-00010101-01010101 +// CHECK-INST: st2q { z21.q, z22.q }, p5, [x10, x21, lsl #4] +// CHECK-ENCODING: [0x55,0x15,0x75,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4751555 + +st2q {z23.q, z24.q}, p3, [x13, x8, lsl #4] // 11100100-01101000-00001101-10110111 +// CHECK-INST: st2q { z23.q, z24.q }, p3, [x13, x8, lsl #4] +// CHECK-ENCODING: [0xb7,0x0d,0x68,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4680db7 + +st2q {z0.q, z1.q}, p0, [x0] // 11100100-01000000-00000000-00000000 +// CHECK-INST: st2q { z0.q, z1.q }, p0, [x0] +// CHECK-ENCODING: [0x00,0x00,0x40,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4400000 + +st2q {z21.q, z22.q}, p5, [x10, #10, mul vl] // 11100100-01000101-00010101-01010101 +// CHECK-INST: st2q { z21.q, z22.q }, p5, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x15,0x45,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4451555 + +st2q {z23.q, z24.q}, p3, [x13, #-16, mul vl] // 11100100-01001000-00001101-10110111 +// CHECK-INST: st2q { z23.q, z24.q }, p3, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x0d,0x48,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4480db7 + +st2q {z31.q, z0.q}, p7, [sp, #-2, mul vl] // 11100100-01001111-00011111-11111111 +// CHECK-INST: st2q { z31.q, z0.q }, p7, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0x1f,0x4f,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e44f1fff + Index: llvm/test/MC/AArch64/SVE2p1/st3q-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st3q-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid predicate register + +st3q {z0.q, z1.q, z2.q}, p8/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: st3q {z0.q, z1.q, z2.q}, p8/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3q {z23.q, z24.q, z25.q}, p2/m, [x0, x0, lsl #4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: st3q {z23.q, z24.q, z25.q}, p2/m, [x0, x0, lsl #4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3q {z21.q, z22.q, z23.q}, p2.q, [x10, x21, lsl #4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: st3q {z21.q, z22.q, z23.q}, p2.q, [x10, x21, lsl #4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate offset + +st3q {z23.q, z24.q, z25.q}, p3, [x13, #-25, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21]. +// CHECK-NEXT: st3q {z23.q, z24.q, z25.q}, p3, [x13, #-25, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st3q {z23.q, z24.q, z25.q}, p3, [x13, #22, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 3 in range [-24, 21]. +// CHECK-NEXT: st3q {z23.q, z24.q, z25.q}, p3, [x13, #22, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/st3q.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st3q.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +st3q {z0.q, z1.q, z2.q}, p0, [x0, x0, lsl #4] // 11100100-10100000-00000000-00000000 +// CHECK-INST: st3q { z0.q - z2.q }, p0, [x0, x0, lsl #4] +// CHECK-ENCODING: [0x00,0x00,0xa0,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4a00000 + +st3q {z21.q, z22.q, z23.q}, p5, [x10, x21, lsl #4] // 11100100-10110101-00010101-01010101 +// CHECK-INST: st3q { z21.q - z23.q }, p5, [x10, x21, lsl #4] +// CHECK-ENCODING: [0x55,0x15,0xb5,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4b51555 + +st3q {z23.q, z24.q, z25.q}, p3, [x13, x8, lsl #4] // 11100100-10101000-00001101-10110111 +// CHECK-INST: st3q { z23.q - z25.q }, p3, [x13, x8, lsl #4] +// CHECK-ENCODING: [0xb7,0x0d,0xa8,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4a80db7 + +st3q {z0.q, z1.q, z2.q}, p0, [x0] // 11100100-10000000-00000000-00000000 +// CHECK-INST: st3q { z0.q - z2.q }, p0, [x0] +// CHECK-ENCODING: [0x00,0x00,0x80,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4800000 + +st3q {z21.q, z22.q, z23.q}, p5, [x10, #15, mul vl] // 11100100-10000101-00010101-01010101 +// CHECK-INST: st3q { z21.q - z23.q }, p5, [x10, #15, mul vl] +// CHECK-ENCODING: [0x55,0x15,0x85,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4851555 + +st3q {z23.q, z24.q, z25.q}, p3, [x13, #-24, mul vl] // 11100100-10001000-00001101-10110111 +// CHECK-INST: st3q { z23.q - z25.q }, p3, [x13, #-24, mul vl] +// CHECK-ENCODING: [0xb7,0x0d,0x88,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4880db7 + +st3q {z31.q, z0.q, z1.q}, p7, [sp, #-3, mul vl] // 11100100-10001111-00011111-11111111 +// CHECK-INST: st3q { z31.q, z0.q, z1.q }, p7, [sp, #-3, mul vl] +// CHECK-ENCODING: [0xff,0x1f,0x8f,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e48f1fff Index: llvm/test/MC/AArch64/SVE2p1/st4q-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st4q-diagnostics.s @@ -0,0 +1,32 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid predicate register + +st4q {z0.q, z1.q, z2.q, z3.q}, p8/z, [z0.d, x0] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: st4q {z0.q, z1.q, z2.q, z3.q}, p8/z, [z0.d, x0] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4q {z23.q, z24.q, z25.q, z26.q}, p2/m, [x0, x0, lsl #4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: st4q {z23.q, z24.q, z25.q, z26.q}, p2/m, [x0, x0, lsl #4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4q {z21.q, z22.q, z23.q, z24.q}, p2.q, [x10, x21, lsl #4] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: st4q {z21.q, z22.q, z23.q, z24.q}, p2.q, [x10, x21, lsl #4] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate offset + +st4q {z23.q, z24.q, z25.q, z26.q}, p3, [x13, #-33, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]. +// CHECK-NEXT: st4q {z23.q, z24.q, z25.q, z26.q}, p3, [x13, #-33, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st4q {z23.q, z24.q, z25.q, z26.q}, p3, [x13, #29, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28]. +// CHECK-NEXT: st4q {z23.q, z24.q, z25.q, z26.q}, p3, [x13, #29, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/st4q.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st4q.s @@ -0,0 +1,57 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d --no-print-imm-hex --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +st4q {z0.q, z1.q, z2.q, z3.q}, p0, [x0, x0, lsl #4] // 11100100-11100000-00000000-00000000 +// CHECK-INST: st4q { z0.q - z3.q }, p0, [x0, x0, lsl #4] +// CHECK-ENCODING: [0x00,0x00,0xe0,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4e00000 + +st4q {z21.q, z22.q, z23.q, z24.q}, p5, [x10, x21, lsl #4] // 11100100-11110101-00010101-01010101 +// CHECK-INST: st4q { z21.q - z24.q }, p5, [x10, x21, lsl #4] +// CHECK-ENCODING: [0x55,0x15,0xf5,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4f51555 + +st4q {z23.q, z24.q, z25.q, z26.q}, p3, [x13, x8, lsl #4] // 11100100-11101000-00001101-10110111 +// CHECK-INST: st4q { z23.q - z26.q }, p3, [x13, x8, lsl #4] +// CHECK-ENCODING: [0xb7,0x0d,0xe8,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4e80db7 + +st4q {z0.q, z1.q, z2.q, z3.q}, p0, [x0] // 11100100-11000000-00000000-00000000 +// CHECK-INST: st4q { z0.q - z3.q }, p0, [x0] +// CHECK-ENCODING: [0x00,0x00,0xc0,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4c00000 + +st4q {z21.q, z22.q, z23.q, z24.q}, p5, [x10, #20, mul vl] // 11100100-11000101-00010101-01010101 +// CHECK-INST: st4q { z21.q - z24.q }, p5, [x10, #20, mul vl] +// CHECK-ENCODING: [0x55,0x15,0xc5,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4c51555 + +st4q {z23.q, z24.q, z25.q, z26.q}, p3, [x13, #-32, mul vl] // 11100100-11001000-00001101-10110111 +// CHECK-INST: st4q { z23.q - z26.q }, p3, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb7,0x0d,0xc8,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4c80db7 + +st4q {z31.q, z0.q, z1.q, z2.q}, p7, [sp, #-4, mul vl] // 11100100-11001111-00011111-11111111 +// CHECK-INST: st4q { z31.q, z0.q, z1.q, z2.q }, p7, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xff,0x1f,0xcf,0xe4] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: e4cf1fff +