diff --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -138,6 +138,22 @@
         Worklist.push_back(UserMI);
         break;
 
+      case RISCV::SLL:
+        // Operand 2 is the shift amount which uses 6 bits.
+        if (OpIdx == 2)
+          break;
+        Worklist.push_back(UserMI);
+        break;
+
+      case RISCV::SRA:
+      case RISCV::SRL:
+      case RISCV::ROL:
+      case RISCV::ROR:
+        // Operand 2 is the shift amount which uses 6 bits.
+        if (OpIdx == 2)
+          break;
+        return false;
+
       case RISCV::ADD_UW:
       case RISCV::SH1ADD_UW:
       case RISCV::SH2ADD_UW:
@@ -171,7 +187,6 @@
       case RISCV::AND:
       case RISCV::MUL:
       case RISCV::OR:
-      case RISCV::SLL:
       case RISCV::SUB:
       case RISCV::XOR:
       case RISCV::XORI: