diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1942,12 +1942,7 @@
}
}
-multiclass VPseudoBinaryV_VV<string Constraint = ""> {
- foreach m = MxList in
- defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
-}
-
-multiclass VPseudoBinaryV_VV_LMUL<LMULInfo m, string Constraint = ""> {
+multiclass VPseudoBinaryV_VV<LMULInfo m, string Constraint = ""> {
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
}
@@ -1976,12 +1971,7 @@
}
}
-multiclass VPseudoBinaryV_VX<string Constraint = ""> {
- foreach m = MxList in
- defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>;
-}
-
-multiclass VPseudoBinaryV_VX_LMUL<LMULInfo m, string Constraint = ""> {
+multiclass VPseudoBinaryV_VX<LMULInfo m, string Constraint = ""> {
defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>;
}
@@ -2017,12 +2007,7 @@
}
}
-multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
- foreach m = MxList in
- defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
-}
-
-multiclass VPseudoBinaryV_VI_LMUL<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
+multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
}
@@ -2046,18 +2031,12 @@
// * The destination EEW is greater than the source EEW, the source EMUL is
// at least 1, and the overlap is in the highest-numbered part of the
// destination register group is legal. Otherwise, it is illegal.
-multiclass VPseudoBinaryW_VV<list<LMULInfo> mxlist = MxListW> {
- foreach m = mxlist in
- defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m,
- "@earlyclobber $rd">;
-}
-
-multiclass VPseudoBinaryW_VV_LMUL<LMULInfo m> {
+multiclass VPseudoBinaryW_VV<LMULInfo m> {
defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m,
"@earlyclobber $rd">;
}
-multiclass VPseudoBinaryW_VX_LMUL<LMULInfo m> {
+multiclass VPseudoBinaryW_VX<LMULInfo m> {
defm "_VX" : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m,
"@earlyclobber $rd">;
}
@@ -2068,23 +2047,14 @@
"@earlyclobber $rd">;
}
-multiclass VPseudoBinaryW_WV<list<LMULInfo> mxlist = MxListW> {
- foreach m = mxlist in {
- defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m,
- "@earlyclobber $rd">;
- defm _WV : VPseudoTiedBinary<m.wvrclass, m.vrclass, m,
- "@earlyclobber $rd">;
- }
-}
-
-multiclass VPseudoBinaryW_WV_LMUL<LMULInfo m> {
+multiclass VPseudoBinaryW_WV<LMULInfo m> {
defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m,
"@earlyclobber $rd">;
defm _WV : VPseudoTiedBinary<m.wvrclass, m.vrclass, m,
"@earlyclobber $rd">;
}
-multiclass VPseudoBinaryW_WX_LMUL<LMULInfo m> {
+multiclass VPseudoBinaryW_WX<LMULInfo m> {
defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m>;
}
@@ -2098,35 +2068,17 @@
// exception from the spec.
// "The destination EEW is smaller than the source EEW and the overlap is in the
// lowest-numbered part of the source register group."
-multiclass VPseudoBinaryV_WV {
- foreach m = MxListW in
- defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m,
- !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
-}
-
-multiclass VPseudoBinaryV_WV_LMUL<LMULInfo m> {
+multiclass VPseudoBinaryV_WV<LMULInfo m> {
defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m,
!if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
}
-multiclass VPseudoBinaryV_WX {
- foreach m = MxListW in
- defm _WX : VPseudoBinary<m.vrclass, m.wvrclass, GPR, m,
- !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
-}
-
-multiclass VPseudoBinaryV_WX_LMUL<LMULInfo m> {
+multiclass VPseudoBinaryV_WX<LMULInfo m> {
defm _WX : VPseudoBinary<m.vrclass, m.wvrclass, GPR, m,
!if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
}
-multiclass VPseudoBinaryV_WI {
- foreach m = MxListW in
- defm _WI : VPseudoBinary<m.vrclass, m.wvrclass, uimm5, m,
- !if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
-}
-
-multiclass VPseudoBinaryV_WI_LMUL<LMULInfo m> {
+multiclass VPseudoBinaryV_WI<LMULInfo m> {
defm _WI : VPseudoBinary<m.vrclass, m.wvrclass, uimm5, m,
!if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
}
@@ -2384,13 +2336,7 @@
// lowest-numbered part of the source register group".
// With LMUL<=1 the source and dest occupy a single register so any overlap
// is in the lowest-numbered part.
-multiclass VPseudoBinaryM_VV<list<LMULInfo> mxlist = MxList> {
- foreach m = mxlist in
- defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m,
- !if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
-}
-
-multiclass VPseudoBinaryM_VV_LMUL<LMULInfo m> {
+multiclass VPseudoBinaryM_VV<LMULInfo m> {
defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m,
!if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
}
@@ -2421,11 +2367,11 @@
defvar ReadVGatherV_MX = !cast<SchedRead>("ReadVGatherV_" # mx);
defvar ReadVGatherX_MX = !cast<SchedRead>("ReadVGatherX_" # mx);
- defm "" : VPseudoBinaryV_VV_LMUL<m, Constraint>,
+ defm "" : VPseudoBinaryV_VV<m, Constraint>,
Sched<[WriteVGatherV_MX, ReadVGatherV_MX, ReadVGatherV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX_LMUL<m, Constraint>,
+ defm "" : VPseudoBinaryV_VX<m, Constraint>,
Sched<[WriteVGatherX_MX, ReadVGatherV_MX, ReadVGatherX_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m, Constraint>,
+ defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
Sched<[WriteVGatherI_MX, ReadVGatherV_MX, ReadVMask]>;
}
}
@@ -2439,11 +2385,11 @@
defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
- defm "" : VPseudoBinaryV_VV_LMUL<m, Constraint>,
+ defm "" : VPseudoBinaryV_VV<m, Constraint>,
Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX_LMUL<m, Constraint>,
+ defm "" : VPseudoBinaryV_VX<m, Constraint>,
Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m, Constraint>,
+ defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
Sched<[WriteVSALUI_MX, ReadVSALUV_MX, ReadVMask]>;
}
}
@@ -2458,11 +2404,11 @@
defvar ReadVShiftV_MX = !cast<SchedRead>("ReadVShiftV_" # mx);
defvar ReadVShiftX_MX = !cast<SchedRead>("ReadVShiftX_" # mx);
- defm "" : VPseudoBinaryV_VV_LMUL<m, Constraint>,
+ defm "" : VPseudoBinaryV_VV<m, Constraint>,
Sched<[WriteVShiftV_MX, ReadVShiftV_MX, ReadVShiftV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX_LMUL<m, Constraint>,
+ defm "" : VPseudoBinaryV_VX<m, Constraint>,
Sched<[WriteVShiftX_MX, ReadVShiftV_MX, ReadVShiftX_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m, Constraint>,
+ defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
Sched<[WriteVShiftI_MX, ReadVShiftV_MX, ReadVMask]>;
}
}
@@ -2476,11 +2422,11 @@
defvar ReadVSShiftV_MX = !cast<SchedRead>("ReadVSShiftV_" # mx);
defvar ReadVSShiftX_MX = !cast<SchedRead>("ReadVSShiftX_" # mx);
- defm "" : VPseudoBinaryV_VV_LMUL<m, Constraint>,
+ defm "" : VPseudoBinaryV_VV<m, Constraint>,
Sched<[WriteVSShiftV_MX, ReadVSShiftV_MX, ReadVSShiftV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX_LMUL<m, Constraint>,
+ defm "" : VPseudoBinaryV_VX<m, Constraint>,
Sched<[WriteVSShiftX_MX, ReadVSShiftV_MX, ReadVSShiftX_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m, Constraint>,
+ defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
Sched<[WriteVSShiftI_MX, ReadVSShiftV_MX, ReadVMask]>;
}
}
@@ -2494,11 +2440,11 @@
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
- defm "" : VPseudoBinaryV_VV_LMUL<m, Constraint>,
+ defm "" : VPseudoBinaryV_VV<m, Constraint>,
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX_LMUL<m, Constraint>,
+ defm "" : VPseudoBinaryV_VX<m, Constraint>,
Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m, Constraint>,
+ defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
Sched<[WriteVIALUI_MX, ReadVIALUV_MX, ReadVMask]>;
}
}
@@ -2511,9 +2457,9 @@
defvar ReadVSALUV_MX = !cast<SchedRead>("ReadVSALUV_" # mx);
defvar ReadVSALUX_MX = !cast<SchedRead>("ReadVSALUX_" # mx);
- defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ defm "" : VPseudoBinaryV_VV<m>,
Sched<[WriteVSALUV_MX, ReadVSALUV_MX, ReadVSALUV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ defm "" : VPseudoBinaryV_VX<m>,
Sched<[WriteVSALUX_MX, ReadVSALUV_MX, ReadVSALUX_MX, ReadVMask]>;
}
}
@@ -2526,9 +2472,9 @@
defvar ReadVSMulV_MX = !cast<SchedRead>("ReadVSMulV_" # mx);
defvar ReadVSMulX_MX = !cast<SchedRead>("ReadVSMulX_" # mx);
- defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ defm "" : VPseudoBinaryV_VV<m>,
Sched<[WriteVSMulV_MX, ReadVSMulV_MX, ReadVSMulV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ defm "" : VPseudoBinaryV_VX<m>,
Sched<[WriteVSMulX_MX, ReadVSMulV_MX, ReadVSMulX_MX, ReadVMask]>;
}
}
@@ -2541,9 +2487,9 @@
defvar ReadVAALUV_MX = !cast<SchedRead>("ReadVAALUV_" # mx);
defvar ReadVAALUX_MX = !cast<SchedRead>("ReadVAALUX_" # mx);
- defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ defm "" : VPseudoBinaryV_VV<m>,
Sched<[WriteVAALUV_MX, ReadVAALUV_MX, ReadVAALUV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ defm "" : VPseudoBinaryV_VX<m>,
Sched<[WriteVAALUX_MX, ReadVAALUV_MX, ReadVAALUX_MX, ReadVMask]>;
}
}
@@ -2556,9 +2502,9 @@
defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx);
- defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ defm "" : VPseudoBinaryV_VV<m>,
Sched<[WriteVICmpV_MX, ReadVICmpV_MX, ReadVICmpV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ defm "" : VPseudoBinaryV_VX<m>,
Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>;
}
}
@@ -2571,9 +2517,9 @@
defvar ReadVIMulV_MX = !cast<SchedRead>("ReadVIMulV_" # mx);
defvar ReadVIMulX_MX = !cast<SchedRead>("ReadVIMulX_" # mx);
- defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ defm "" : VPseudoBinaryV_VV<m>,
Sched<[WriteVIMulV_MX, ReadVIMulV_MX, ReadVIMulV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ defm "" : VPseudoBinaryV_VX<m>,
Sched<[WriteVIMulX_MX, ReadVIMulV_MX, ReadVIMulX_MX, ReadVMask]>;
}
}
@@ -2586,9 +2532,9 @@
defvar ReadVIDivV_MX = !cast<SchedRead>("ReadVIDivV_" # mx);
defvar ReadVIDivX_MX = !cast<SchedRead>("ReadVIDivX_" # mx);
- defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ defm "" : VPseudoBinaryV_VV<m>,
Sched<[WriteVIDivV_MX, ReadVIDivV_MX, ReadVIDivV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ defm "" : VPseudoBinaryV_VX<m>,
Sched<[WriteVIDivX_MX, ReadVIDivV_MX, ReadVIDivX_MX, ReadVMask]>;
}
}
@@ -2660,9 +2606,9 @@
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
- defm "" : VPseudoBinaryV_VV_LMUL<m>,
+ defm "" : VPseudoBinaryV_VV<m>,
Sched<[WriteVIALUV_MX, ReadVIALUV_MX, ReadVIALUV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ defm "" : VPseudoBinaryV_VX<m>,
Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
}
}
@@ -2757,9 +2703,9 @@
defvar ReadVIALUV_MX = !cast<SchedRead>("ReadVIALUV_" # mx);
defvar ReadVIALUX_MX = !cast<SchedRead>("ReadVIALUX_" # mx);
- defm "" : VPseudoBinaryV_VX_LMUL<m>,
+ defm "" : VPseudoBinaryV_VX<m>,
Sched<[WriteVIALUX_MX, ReadVIALUV_MX, ReadVIALUX_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_VI_LMUL<ImmType, m>,
+ defm "" : VPseudoBinaryV_VI<ImmType, m>,
Sched<[WriteVIALUI_MX, ReadVIALUV_MX, ReadVMask]>;
}
}
@@ -2772,9 +2718,9 @@
defvar ReadVIWALUV_MX = !cast<SchedRead>("ReadVIWALUV_" # mx);
defvar ReadVIWALUX_MX = !cast<SchedRead>("ReadVIWALUX_" # mx);
- defm "" : VPseudoBinaryW_VV_LMUL<m>,
+ defm "" : VPseudoBinaryW_VV<m>,
Sched<[WriteVIWALUV_MX, ReadVIWALUV_MX, ReadVIWALUV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryW_VX_LMUL<m>,
+ defm "" : VPseudoBinaryW_VX<m>,
Sched<[WriteVIWALUX_MX, ReadVIWALUV_MX, ReadVIWALUX_MX, ReadVMask]>;
}
}
@@ -2787,9 +2733,9 @@
defvar ReadVIWMulV_MX = !cast<SchedRead>("ReadVIWMulV_" # mx);
defvar ReadVIWMulX_MX = !cast<SchedRead>("ReadVIWMulX_" # mx);
- defm "" : VPseudoBinaryW_VV_LMUL<m>,
+ defm "" : VPseudoBinaryW_VV<m>,
Sched<[WriteVIWMulV_MX, ReadVIWMulV_MX, ReadVIWMulV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryW_VX_LMUL<m>,
+ defm "" : VPseudoBinaryW_VX<m>,
Sched<[WriteVIWMulX_MX, ReadVIWMulV_MX, ReadVIWMulX_MX, ReadVMask]>;
}
}
@@ -2800,7 +2746,7 @@
defvar WriteVFWMulV_MX = !cast<SchedWrite>("WriteVFWMulV_" # mx);
defvar ReadVFWMulV_MX = !cast<SchedRead>("ReadVFWMulV_" # mx);
- defm "" : VPseudoBinaryW_VV_LMUL<m>,
+ defm "" : VPseudoBinaryW_VV<m>,
Sched<[WriteVFWMulV_MX, ReadVFWMulV_MX, ReadVFWMulV_MX, ReadVMask]>;
}
@@ -2825,9 +2771,9 @@
defvar ReadVIWALUV_MX = !cast<SchedRead>("ReadVIWALUV_" # mx);
defvar ReadVIWALUX_MX = !cast<SchedRead>("ReadVIWALUX_" # mx);
- defm "" : VPseudoBinaryW_WV_LMUL<m>,
+ defm "" : VPseudoBinaryW_WV<m>,
Sched<[WriteVIWALUV_MX, ReadVIWALUV_MX, ReadVIWALUV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryW_WX_LMUL<m>,
+ defm "" : VPseudoBinaryW_WX<m>,
Sched<[WriteVIWALUX_MX, ReadVIWALUV_MX, ReadVIWALUX_MX, ReadVMask]>;
}
}
@@ -2838,7 +2784,7 @@
defvar WriteVFWALUV_MX = !cast<SchedWrite>("WriteVFWALUV_" # mx);
defvar ReadVFWALUV_MX = !cast<SchedRead>("ReadVFWALUV_" # mx);
- defm "" : VPseudoBinaryW_VV_LMUL<m>,
+ defm "" : VPseudoBinaryW_VV<m>,
Sched<[WriteVFWALUV_MX, ReadVFWALUV_MX, ReadVFWALUV_MX, ReadVMask]>;
}
@@ -2861,7 +2807,7 @@
defvar WriteVFWALUV_MX = !cast<SchedWrite>("WriteVFWALUV_" # mx);
defvar ReadVFWALUV_MX = !cast<SchedRead>("ReadVFWALUV_" # mx);
- defm "" : VPseudoBinaryW_WV_LMUL<m>,
+ defm "" : VPseudoBinaryW_WV<m>,
Sched<[WriteVFWALUV_MX, ReadVFWALUV_MX, ReadVFWALUV_MX, ReadVMask]>;
}
foreach f = FPListW in {
@@ -3022,11 +2968,11 @@
defvar ReadVNClipV_MX = !cast<SchedRead>("ReadVNClipV_" # mx);
defvar ReadVNClipX_MX = !cast<SchedRead>("ReadVNClipX_" # mx);
- defm "" : VPseudoBinaryV_WV_LMUL<m>,
+ defm "" : VPseudoBinaryV_WV<m>,
Sched<[WriteVNClipV_MX, ReadVNClipV_MX, ReadVNClipV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_WX_LMUL<m>,
+ defm "" : VPseudoBinaryV_WX<m>,
Sched<[WriteVNClipX_MX, ReadVNClipV_MX, ReadVNClipX_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_WI_LMUL<m>,
+ defm "" : VPseudoBinaryV_WI<m>,
Sched<[WriteVNClipI_MX, ReadVNClipV_MX, ReadVMask]>;
}
}
@@ -3040,11 +2986,11 @@
defvar ReadVNShiftV_MX = !cast<SchedRead>("ReadVNShiftV_" # mx);
defvar ReadVNShiftX_MX = !cast<SchedRead>("ReadVNShiftX_" # mx);
- defm "" : VPseudoBinaryV_WV_LMUL<m>,
+ defm "" : VPseudoBinaryV_WV<m>,
Sched<[WriteVNShiftV_MX, ReadVNShiftV_MX, ReadVNShiftV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_WX_LMUL<m>,
+ defm "" : VPseudoBinaryV_WX<m>,
Sched<[WriteVNShiftX_MX, ReadVNShiftV_MX, ReadVNShiftX_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_WI_LMUL<m>,
+ defm "" : VPseudoBinaryV_WI<m>,
Sched<[WriteVNShiftI_MX, ReadVNShiftV_MX, ReadVMask]>;
}
}
@@ -3086,15 +3032,7 @@
}
}
-multiclass VPseudoTernaryV_VV_AAXA<string Constraint = "",
- list<LMULInfo> mxlist = MxList> {
- foreach m = mxlist in {
- defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m,
- Constraint, /*Commutable*/1>;
- }
-}
-
-multiclass VPseudoTernaryV_VV_AAXA_LMUL<LMULInfo m, string Constraint = ""> {
+multiclass VPseudoTernaryV_VV_AAXA<LMULInfo m, string Constraint = ""> {
defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m,
Constraint, /*Commutable*/1>;
}
@@ -3114,14 +3052,7 @@
/*Commutable*/1>;
}
-multiclass VPseudoTernaryW_VV<list<LMULInfo> mxlist = MxListW> {
- defvar constraint = "@earlyclobber $rd";
- foreach m = mxlist in
- defm _VV : VPseudoTernaryWithPolicy<m.wvrclass, m.vrclass, m.vrclass, m,
- constraint>;
-}
-
-multiclass VPseudoTernaryW_VV_LMUL<LMULInfo m> {
+multiclass VPseudoTernaryW_VV<LMULInfo m> {
defvar constraint = "@earlyclobber $rd";
defm _VV : VPseudoTernaryWithPolicy<m.wvrclass, m.vrclass, m.vrclass, m,
constraint>;
@@ -3151,7 +3082,7 @@
defvar ReadVIMulAddV_MX = !cast<SchedRead>("ReadVIMulAddV_" # mx);
defvar ReadVIMulAddX_MX = !cast<SchedRead>("ReadVIMulAddX_" # mx);
- defm "" : VPseudoTernaryV_VV_AAXA_LMUL<m, Constraint>,
+ defm "" : VPseudoTernaryV_VV_AAXA<m, Constraint>,
Sched<[WriteVIMulAddV_MX, ReadVIMulAddV_MX, ReadVIMulAddV_MX,
ReadVIMulAddV_MX, ReadVMask]>;
defm "" : VPseudoTernaryV_VX_AAXA<m, Constraint>,
@@ -3166,7 +3097,7 @@
defvar WriteVFMulAddV_MX = !cast<SchedWrite>("WriteVFMulAddV_" # mx);
defvar ReadVFMulAddV_MX = !cast<SchedRead>("ReadVFMulAddV_" # mx);
- defm "" : VPseudoTernaryV_VV_AAXA_LMUL<m, Constraint>,
+ defm "" : VPseudoTernaryV_VV_AAXA<m, Constraint>,
Sched<[WriteVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVMask]>;
}
@@ -3206,7 +3137,7 @@
defvar ReadVIWMulAddV_MX = !cast<SchedRead>("ReadVIWMulAddV_" # mx);
defvar ReadVIWMulAddX_MX = !cast<SchedRead>("ReadVIWMulAddX_" # mx);
- defm "" : VPseudoTernaryW_VV_LMUL<m>,
+ defm "" : VPseudoTernaryW_VV<m>,
Sched<[WriteVIWMulAddV_MX, ReadVIWMulAddV_MX, ReadVIWMulAddV_MX,
ReadVIWMulAddV_MX, ReadVMask]>;
defm "" : VPseudoTernaryW_VX<m>,
@@ -3234,7 +3165,7 @@
defvar WriteVFWMulAddV_MX = !cast<SchedWrite>("WriteVFWMulAddV_" # mx);
defvar ReadVFWMulAddV_MX = !cast<SchedRead>("ReadVFWMulAddV_" # mx);
- defm "" : VPseudoTernaryW_VV_LMUL<m>,
+ defm "" : VPseudoTernaryW_VV<m>,
Sched<[WriteVFWMulAddV_MX, ReadVFWMulAddV_MX,
ReadVFWMulAddV_MX, ReadVFWMulAddV_MX, ReadVMask]>;
}
@@ -3262,7 +3193,7 @@
defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx);
- defm "" : VPseudoBinaryM_VV_LMUL<m>,
+ defm "" : VPseudoBinaryM_VV<m>,
Sched<[WriteVICmpV_MX, ReadVICmpV_MX, ReadVICmpV_MX, ReadVMask]>;
defm "" : VPseudoBinaryM_VX<m>,
Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>;
@@ -3279,7 +3210,7 @@
defvar ReadVICmpV_MX = !cast<SchedRead>("ReadVICmpV_" # mx);
defvar ReadVICmpX_MX = !cast<SchedRead>("ReadVICmpX_" # mx);
- defm "" : VPseudoBinaryM_VV_LMUL<m>,
+ defm "" : VPseudoBinaryM_VV<m>,
Sched<[WriteVICmpV_MX, ReadVICmpV_MX, ReadVICmpV_MX, ReadVMask]>;
defm "" : VPseudoBinaryM_VX<m>,
Sched<[WriteVICmpX_MX, ReadVICmpV_MX, ReadVICmpX_MX, ReadVMask]>;
@@ -3292,7 +3223,7 @@
defvar WriteVFCmpV_MX = !cast<SchedWrite>("WriteVFCmpV_" # mx);
defvar ReadVFCmpV_MX = !cast<SchedRead>("ReadVFCmpV_" # mx);
- defm "" : VPseudoBinaryM_VV_LMUL<m>,
+ defm "" : VPseudoBinaryM_VV<m>,
Sched<[WriteVFCmpV_MX, ReadVFCmpV_MX, ReadVFCmpV_MX, ReadVMask]>;
}