Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -3701,4 +3701,5 @@ defm ORQV : sve2p1_log_reduction_q<0b00, "orqv">; defm EORQV : sve2p1_log_reduction_q<0b01, "eorqv">; defm ANDQV : sve2p1_log_reduction_q<0b10, "andqv">; +defm ADDQV : sve2p1_add_reduction_q<0b01, "addqv">; } Index: llvm/lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- llvm/lib/Target/AArch64/SVEInstrFormats.td +++ llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -9226,3 +9226,30 @@ def _S : sve2p1_log_reduction_q<0b10, opc, mnemonic, ZPR32, "4s">; def _D : sve2p1_log_reduction_q<0b11, opc, mnemonic, ZPR64, "2d">; } + + +// SVE integer add reduction (quadwords) +class sve2p1_add_reduction_q sz, bits<2> opc, string mnemonic, + RegisterOperand zpr_ty, string vec_sfx> + : I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn), + mnemonic, "\t$Vd." # vec_sfx # ", $Pg, $Zn", + "", []>, Sched<[]> { + bits<5> Vd; + bits<5> Zn; + bits<3> Pg; + let Inst{31-24} = 0b00000100; + let Inst{23-22} = sz; + let Inst{21-18} = 0b0001; + let Inst{17-16} = opc; + let Inst{15-13} = 0b001; + let Inst{12-10} = Pg; + let Inst{9-5} = Zn; + let Inst{4-0} = Vd; +} + +multiclass sve2p1_add_reduction_q opc, string mnemonic> { + def _B : sve2p1_add_reduction_q<0b00, opc, mnemonic, ZPR8, "16b">; + def _H : sve2p1_add_reduction_q<0b01, opc, mnemonic, ZPR16, "8h">; + def _S : sve2p1_add_reduction_q<0b10, opc, mnemonic, ZPR32, "4s">; + def _D : sve2p1_add_reduction_q<0b11, opc, mnemonic, ZPR64, "2d">; +} Index: llvm/test/MC/AArch64/SVE2p1/addqv-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/addqv-diagnostics.s @@ -0,0 +1,30 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid predicate register + +addqv v0.2d, p11, z0.d +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) +// CHECK-NEXT: addqv v0.2d, p11, z0.d +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector register + +addqv v0.4h, p1, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: addqv v0.4h, p1, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +addqv z1.s, p1, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: addqv z1.s, p1, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid vector suffix + +addqv v0.8h, p1, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: addqv v0.8h, p1, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/addqv.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/addqv.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +addqv v0.8h, p0, z0.h // 00000100-01000101-00100000-00000000 +// CHECK-INST: addqv v0.8h, p0, z0.h +// CHECK-ENCODING: [0x00,0x20,0x45,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04452000 + +addqv v21.8h, p5, z10.h // 00000100-01000101-00110101-01010101 +// CHECK-INST: addqv v21.8h, p5, z10.h +// CHECK-ENCODING: [0x55,0x35,0x45,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04453555 + +addqv v23.8h, p3, z13.h // 00000100-01000101-00101101-10110111 +// CHECK-INST: addqv v23.8h, p3, z13.h +// CHECK-ENCODING: [0xb7,0x2d,0x45,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04452db7 + +addqv v31.8h, p7, z31.h // 00000100-01000101-00111111-11111111 +// CHECK-INST: addqv v31.8h, p7, z31.h +// CHECK-ENCODING: [0xff,0x3f,0x45,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04453fff + + +addqv v0.4s, p0, z0.s // 00000100-10000101-00100000-00000000 +// CHECK-INST: addqv v0.4s, p0, z0.s +// CHECK-ENCODING: [0x00,0x20,0x85,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04852000 + +addqv v21.4s, p5, z10.s // 00000100-10000101-00110101-01010101 +// CHECK-INST: addqv v21.4s, p5, z10.s +// CHECK-ENCODING: [0x55,0x35,0x85,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04853555 + +addqv v23.4s, p3, z13.s // 00000100-10000101-00101101-10110111 +// CHECK-INST: addqv v23.4s, p3, z13.s +// CHECK-ENCODING: [0xb7,0x2d,0x85,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04852db7 + +addqv v31.4s, p7, z31.s // 00000100-10000101-00111111-11111111 +// CHECK-INST: addqv v31.4s, p7, z31.s +// CHECK-ENCODING: [0xff,0x3f,0x85,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04853fff + + +addqv v0.2d, p0, z0.d // 00000100-11000101-00100000-00000000 +// CHECK-INST: addqv v0.2d, p0, z0.d +// CHECK-ENCODING: [0x00,0x20,0xc5,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04c52000 + +addqv v21.2d, p5, z10.d // 00000100-11000101-00110101-01010101 +// CHECK-INST: addqv v21.2d, p5, z10.d +// CHECK-ENCODING: [0x55,0x35,0xc5,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04c53555 + +addqv v23.2d, p3, z13.d // 00000100-11000101-00101101-10110111 +// CHECK-INST: addqv v23.2d, p3, z13.d +// CHECK-ENCODING: [0xb7,0x2d,0xc5,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04c52db7 + +addqv v31.2d, p7, z31.d // 00000100-11000101-00111111-11111111 +// CHECK-INST: addqv v31.2d, p7, z31.d +// CHECK-ENCODING: [0xff,0x3f,0xc5,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04c53fff + + +addqv v0.16b, p0, z0.b // 00000100-00000101-00100000-00000000 +// CHECK-INST: addqv v0.16b, p0, z0.b +// CHECK-ENCODING: [0x00,0x20,0x05,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04052000 + +addqv v21.16b, p5, z10.b // 00000100-00000101-00110101-01010101 +// CHECK-INST: addqv v21.16b, p5, z10.b +// CHECK-ENCODING: [0x55,0x35,0x05,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04053555 + +addqv v23.16b, p3, z13.b // 00000100-00000101-00101101-10110111 +// CHECK-INST: addqv v23.16b, p3, z13.b +// CHECK-ENCODING: [0xb7,0x2d,0x05,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04052db7 + +addqv v31.16b, p7, z31.b // 00000100-00000101-00111111-11111111 +// CHECK-INST: addqv v31.16b, p7, z31.b +// CHECK-ENCODING: [0xff,0x3f,0x05,0x04] +// CHECK-ERROR: instruction requires: sme2p1 or sve2p1 +// CHECK-UNKNOWN: 04053fff +