diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -719,17 +719,20 @@ multiclass VMALU_MV_Mask funct6, string vm = "v"> { def M : VALUVVNoVm, - Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>; + Sched<[WriteVMALUV_UpperBound, ReadVMALUV_UpperBound, + ReadVMALUV_UpperBound]>; } multiclass VMSFS_MV_V funct6, bits<5> vs1> { def "" : VALUVs2, - Sched<[WriteVMSFSV, ReadVMSFSV, ReadVMask]>; + Sched<[WriteVMSFSV_UpperBound, ReadVMSFSV_UpperBound, + ReadVMask]>; } multiclass VMIOT_MV_V funct6, bits<5> vs1> { def "" : VALUVs2, - Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>; + Sched<[WriteVMIotV_UpperBound, ReadVMIotV_UpperBound, + ReadVMask]>; } multiclass VSHT_IV_V_X_I funct6, Operand optype = simm5, string vw = "v"> { @@ -1519,13 +1522,15 @@ def VCPOP_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd), (ins VR:$vs2, VMaskOp:$vm), "vcpop.m", "$vd, $vs2$vm">, - Sched<[WriteVMPopV, ReadVMPopV, ReadVMask]>; + Sched<[WriteVMPopV_UpperBound, ReadVMPopV_UpperBound, + ReadVMask]>; // vfirst find-first-set mask bit def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd), (ins VR:$vs2, VMaskOp:$vm), "vfirst.m", "$vd, $vs2$vm">, - Sched<[WriteVMFFSV, ReadVMFFSV, ReadVMask]>; + Sched<[WriteVMFFSV_UpperBound, ReadVMFFSV_UpperBound, + ReadVMask]>; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 @@ -1551,7 +1556,7 @@ let vs2 = 0 in def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd), (ins VMaskOp:$vm), "vid.v", "$vd$vm">, - Sched<[WriteVMIdxV, ReadVMask]>; + Sched<[WriteVMIdxV_UpperBound, ReadVMask]>; // Integer Scalar Move Instructions let vm = 1, RVVConstraint = NoConstraint in { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -1770,11 +1770,14 @@ multiclass VPseudoVPOP_M { foreach mti = AllMasks in { + defvar mx = mti.LMul.MX; + defvar WriteVMPopV_MX = !cast("WriteVMPopV_" # mx); + defvar ReadVMPopV_MX = !cast("ReadVMPopV_" # mx); let VLMul = mti.LMul.value in { def "_M_" # mti.BX : VPseudoUnaryNoMask, - Sched<[WriteVMPopV, ReadVMPopV, ReadVMPopV]>; + Sched<[WriteVMPopV_MX, ReadVMPopV_MX, ReadVMPopV_MX]>; def "_M_" # mti.BX # "_MASK" : VPseudoMaskUnarySOutMask, - Sched<[WriteVMPopV, ReadVMPopV, ReadVMPopV]>; + Sched<[WriteVMPopV_MX, ReadVMPopV_MX, ReadVMPopV_MX]>; } } } @@ -1782,11 +1785,14 @@ multiclass VPseudoV1ST_M { foreach mti = AllMasks in { + defvar mx = mti.LMul.MX; + defvar WriteVMFFSV_MX = !cast("WriteVMFFSV_" # mx); + defvar ReadVMFFSV_MX = !cast("ReadVMFFSV_" # mx); let VLMul = mti.LMul.value in { def "_M_" # mti.BX : VPseudoUnaryNoMask, - Sched<[WriteVMFFSV, ReadVMFFSV, ReadVMFFSV]>; + Sched<[WriteVMFFSV_MX, ReadVMFFSV_MX, ReadVMFFSV_MX]>; def "_M_" # mti.BX # "_MASK" : VPseudoMaskUnarySOutMask, - Sched<[WriteVMFFSV, ReadVMFFSV, ReadVMFFSV]>; + Sched<[WriteVMFFSV_MX, ReadVMFFSV_MX, ReadVMFFSV_MX]>; } } } @@ -1795,33 +1801,45 @@ defvar constraint = "@earlyclobber $rd"; foreach mti = AllMasks in { + defvar mx = mti.LMul.MX; + defvar WriteVMSFSV_MX = !cast("WriteVMSFSV_" # mx); + defvar ReadVMSFSV_MX = !cast("ReadVMSFSV_" # mx); let VLMul = mti.LMul.value in { def "_M_" # mti.BX : VPseudoUnaryNoMask, - Sched<[WriteVMSFSV, ReadVMSFSV, ReadVMask]>; + Sched<[WriteVMSFSV_MX, ReadVMSFSV_MX, ReadVMask]>; def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask, - Sched<[WriteVMSFSV, ReadVMSFSV, ReadVMask]>; + Sched<[WriteVMSFSV_MX, ReadVMSFSV_MX, ReadVMask]>; } } } multiclass VPseudoVID_V { foreach m = MxList in { + defvar mx = m.MX; + defvar WriteVMIdxV_MX = !cast("WriteVMIdxV_" # mx); + defvar ReadVMIdxV_MX = !cast("ReadVMIdxV_" # mx); + let VLMul = m.value in { def "_V_" # m.MX : VPseudoNullaryNoMask, - Sched<[WriteVMIdxV, ReadVMask]>; + Sched<[WriteVMIdxV_MX, ReadVMask]>; def "_V_" # m.MX # "_TU": VPseudoNullaryNoMaskTU, - Sched<[WriteVMIdxV, ReadVMask]>; + Sched<[WriteVMIdxV_MX, ReadVMask]>; def "_V_" # m.MX # "_MASK" : VPseudoNullaryMask, RISCVMaskedPseudo, - Sched<[WriteVMIdxV, ReadVMask]>; + Sched<[WriteVMIdxV_MX, ReadVMask]>; } } } multiclass VPseudoNullaryPseudoM { foreach mti = AllMasks in { + defvar mx = mti.LMul.MX; + defvar WriteVMALUV_MX = !cast("WriteVMALUV_" # mx); + defvar ReadVMALUV_MX = !cast("ReadVMALUV_" # mx); + let VLMul = mti.LMul.value in { - def "_M_" # mti.BX : VPseudoNullaryPseudoM; + def "_M_" # mti.BX : VPseudoNullaryPseudoM, + Sched<[WriteVMALUV_MX, ReadVMALUV_MX, ReadVMALUV_MX]>; } } } @@ -1829,14 +1847,17 @@ multiclass VPseudoVIOT_M { defvar constraint = "@earlyclobber $rd"; foreach m = MxList in { + defvar mx = m.MX; + defvar WriteVMIotV_MX = !cast("WriteVMIotV_" # mx); + defvar ReadVMIotV_MX = !cast("ReadVMIotV_" # mx); let VLMul = m.value in { def "_" # m.MX : VPseudoUnaryNoMask, - Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>; + Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>; def "_" # m.MX # "_TU" : VPseudoUnaryNoMaskTU, - Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>; + Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>; def "_" # m.MX # "_MASK" : VPseudoUnaryMaskTA, RISCVMaskedPseudo, - Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>; + Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>; } } } @@ -1977,11 +1998,16 @@ } multiclass VPseudoVALU_MM { - foreach m = MxList in + foreach m = MxList in { + defvar mx = m.MX; + defvar WriteVMALUV_MX = !cast("WriteVMALUV_" # mx); + defvar ReadVMALUV_MX = !cast("ReadVMALUV_" # mx); + let VLMul = m.value in { - def "_MM_" # m.MX : VPseudoBinaryNoMask, - Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>; + def "_MM_" # mx : VPseudoBinaryNoMask, + Sched<[WriteVMALUV_MX, ReadVMALUV_MX, ReadVMALUV_MX]>; } + } } // We use earlyclobber here due to @@ -5566,10 +5592,8 @@ defm PseudoVMXNOR: VPseudoVALU_MM; // Pseudo instructions -defm PseudoVMCLR : VPseudoNullaryPseudoM<"VMXOR">, - Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>; -defm PseudoVMSET : VPseudoNullaryPseudoM<"VMXNOR">, - Sched<[WriteVMALUV, ReadVMALUV, ReadVMALUV]>; +defm PseudoVMCLR : VPseudoNullaryPseudoM<"VMXOR">; +defm PseudoVMSET : VPseudoNullaryPseudoM<"VMXNOR">; //===----------------------------------------------------------------------===// // 16.2. Vector mask population count vcpop diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td --- a/llvm/lib/Target/RISCV/RISCVScheduleV.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td @@ -252,19 +252,19 @@ // 15. Vector Mask Instructions // 15.1. Vector Mask-Register Logical Instructions -def WriteVMALUV : SchedWrite; +defm "" : LMULSchedWrites<"WriteVMALUV">; // 15.2. Vector Mask Population Count -def WriteVMPopV : SchedWrite; +defm "" : LMULSchedWrites<"WriteVMPopV">; // 15.3. Vector Find-First-Set Mask Bit -def WriteVMFFSV : SchedWrite; +defm "" : LMULSchedWrites<"WriteVMFFSV">; // 15.4. Vector Set-Before-First Mask Bit // 15.5. Vector Set-Including-First Mask Bit // 15.6. Vector Set-only-First Mask Bit -def WriteVMSFSV : SchedWrite; +defm "" : LMULSchedWrites<"WriteVMSFSV">; // 15.8. Vector Iota Instruction -def WriteVMIotV : SchedWrite; +defm "" : LMULSchedWrites<"WriteVMIotV">; // 15.9. Vector Element Index Instruction -def WriteVMIdxV : SchedWrite; +defm "" : LMULSchedWrites<"WriteVMIdxV">; // 16. Vector Permutation Instructions // 16.1. Integer Scalar Move Instructions @@ -472,17 +472,17 @@ // 15. Vector Mask Instructions // 15.1. Vector Mask-Register Logical Instructions -def ReadVMALUV : SchedRead; +defm "" : LMULSchedReads<"ReadVMALUV">; // 15.2. Vector Mask Population Count -def ReadVMPopV : SchedRead; +defm "" : LMULSchedReads<"ReadVMPopV">; // 15.3. Vector Find-First-Set Mask Bit -def ReadVMFFSV : SchedRead; +defm "" : LMULSchedReads<"ReadVMFFSV">; // 15.4. Vector Set-Before-First Mask Bit // 15.5. Vector Set-Including-First Mask Bit // 15.6. Vector Set-only-First Mask Bit -def ReadVMSFSV : SchedRead; +defm "" : LMULSchedReads<"ReadVMSFSV">; // 15.8. Vector Iota Instruction -def ReadVMIotV : SchedRead; +defm "" : LMULSchedReads<"ReadVMIotV">; // 16. Vector Permutation Instructions // 16.1. Integer Scalar Move Instructions @@ -666,7 +666,7 @@ defm "" : LMULWriteRes<"WriteVFNCvtFToIV", [], SchedMxListW>; defm "" : LMULWriteRes<"WriteVFNCvtFToFV", [], SchedMxListFW>; -// 15. Vector Reduction Operations +// 14. Vector Reduction Operations def : WriteRes; def : WriteRes; def : WriteRes; @@ -674,13 +674,13 @@ def : WriteRes; def : WriteRes; -// 16. Vector Mask Instructions -def : WriteRes; -def : WriteRes; -def : WriteRes; -def : WriteRes; -def : WriteRes; -def : WriteRes; +// 15. Vector Mask Instructions +defm "" : LMULWriteRes<"WriteVMALUV", []>; +defm "" : LMULWriteRes<"WriteVMPopV", []>; +defm "" : LMULWriteRes<"WriteVMFFSV", []>; +defm "" : LMULWriteRes<"WriteVMSFSV", []>; +defm "" : LMULWriteRes<"WriteVMIotV", []>; +defm "" : LMULWriteRes<"WriteVMIdxV", []>; // 17. Vector Permutation Instructions def : WriteRes; @@ -815,7 +815,7 @@ defm "" : LMULReadAdvance<"ReadVFNCvtFToIV", 0, SchedMxListW>; defm "" : LMULReadAdvance<"ReadVFNCvtFToFV", 0, SchedMxListFW>; -// 15. Vector Reduction Operations +// 14. Vector Reduction Operations def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; @@ -829,12 +829,12 @@ def : ReadAdvance; def : ReadAdvance; -// 16. Vector Mask Instructions -def : ReadAdvance; -def : ReadAdvance; -def : ReadAdvance; -def : ReadAdvance; -def : ReadAdvance; +// 15. Vector Mask Instructions +defm "" : LMULReadAdvance<"ReadVMALUV", 0>; +defm "" : LMULReadAdvance<"ReadVMPopV", 0>; +defm "" : LMULReadAdvance<"ReadVMFFSV", 0>; +defm "" : LMULReadAdvance<"ReadVMSFSV", 0>; +defm "" : LMULReadAdvance<"ReadVMIotV", 0>; // 17. Vector Permutation Instructions def : ReadAdvance;