Index: llvm/lib/CodeGen/MIRVRegNamerUtils.cpp =================================================================== --- llvm/lib/CodeGen/MIRVRegNamerUtils.cpp +++ llvm/lib/CodeGen/MIRVRegNamerUtils.cpp @@ -62,7 +62,8 @@ /* HashConstantPoolIndices */ true, /* HashMemOperands */ true); assert(Hash && "Expected non-zero Hash"); - return std::to_string(Hash).substr(0, 5); + OS << format_hex_no_prefix(Hash, 16, true); + return OS.str(); } // Gets a hashable artifact from a given MachineOperand (ie an unsigned). @@ -132,7 +133,8 @@ } auto HashMI = hash_combine_range(MIOperands.begin(), MIOperands.end()); - return std::to_string(HashMI).substr(0, 5); + OS << format_hex_no_prefix(HashMI, 16, true); + return OS.str(); } unsigned VRegRenamer::createVirtualRegister(unsigned VReg) { Index: llvm/test/CodeGen/MIR/AArch64/mir-canon-constant-pool-hash.mir =================================================================== --- llvm/test/CodeGen/MIR/AArch64/mir-canon-constant-pool-hash.mir +++ llvm/test/CodeGen/MIR/AArch64/mir-canon-constant-pool-hash.mir @@ -14,8 +14,8 @@ body: | bb.0: ; Test that we no longer have hash collisions between two different consts: - ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:gpr64common = ADR - ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:gpr64common = ADR + ;CHECK: %bb{{[0-9a-f]+}}_{{[0-9a-f]+}}__1:gpr64common = ADR + ;CHECK: %bb{{[0-9a-f]+}}_{{[0-9a-f]+}}__1:gpr64common = ADR %vreg0:gpr64common = ADRP target-flags(aarch64-page) %const.0 %vreg1:gpr64common = ADRP target-flags(aarch64-page) %const.1 ... Index: llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir =================================================================== --- llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir +++ llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir @@ -21,10 +21,10 @@ bb.2: bb.3: bb.7: - ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.0 - ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.1 - ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.2 - ;CHECK: %bb{{[0-9]+}}_{{[0-9]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.3 + ;CHECK: %bb{{[0-9a-f]+}}_{{[0-9a-f]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.0 + ;CHECK: %bb{{[0-9a-f]+}}_{{[0-9a-f]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.1 + ;CHECK: %bb{{[0-9a-f]+}}_{{[0-9a-f]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.2 + ;CHECK: %bb{{[0-9a-f]+}}_{{[0-9a-f]+}}__1:_(p0) = G_JUMP_TABLE %jump-table.3 %a:_(p0) = G_JUMP_TABLE %jump-table.0 %b:_(p0) = G_JUMP_TABLE %jump-table.1 %c:_(p0) = G_JUMP_TABLE %jump-table.2 Index: llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir =================================================================== --- llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir +++ llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir @@ -40,7 +40,7 @@ %42:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load (s64)) - ;CHECK: %bb0_{{[0-9]+}}__1:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load (s64)) + ;CHECK: %bb0_{{[0-9a-f]+}}__1:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load (s64)) ;CHECK-NEXT: $w0 = COPY %bb0_ ;CHECK-NEXT: RET_ReallyLR implicit $w0 Index: llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir =================================================================== --- llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir +++ llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir @@ -1,12 +1,12 @@ # RUN: llc -mtriple=arm64-apple-ios11.0.0 -o - -verify-machineinstrs -run-pass mir-canonicalizer %s | FileCheck %s # RUN: llc -mtriple=arm64-apple-ios11.0.0 -o - -mir-vreg-namer-use-stable-hash -verify-machineinstrs -run-pass mir-canonicalizer %s | FileCheck %s # These Idempotent instructions are sorted alphabetically (based on after the '=') -# CHECK: %bb0_{{[0-9]+}}__1:gpr64 = MOVi64imm 4617315517961601024 -# CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 408 -# CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = MOVi32imm 408 -# CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr64all = IMPLICIT_DEF -# CHECK-NEXT: %bb0_{{[0-9]+}}__1:fpr64 = FMOVDi 20 -# CHECK-NEXT: %bb0_{{[0-9]+}}__1:fpr64 = FMOVDi 112 +# CHECK: %bb0_{{[0-9a-f]+}}__1:gpr64 = MOVi64imm 4617315517961601024 +# CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = MOVi32imm 408 +# CHECK-NEXT: %bb0_{{[0-9a-f]+}}__2:gpr32 = MOVi32imm 408 +# CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr64all = IMPLICIT_DEF +# CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fpr64 = FMOVDi 20 +# CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fpr64 = FMOVDi 112 ... --- Index: llvm/test/CodeGen/MIR/AArch64/mirnamer.mir =================================================================== --- llvm/test/CodeGen/MIR/AArch64/mirnamer.mir +++ llvm/test/CodeGen/MIR/AArch64/mirnamer.mir @@ -8,9 +8,9 @@ ;CHECK-LABEL: bb.0 ;CHECK-NEXT: liveins ;CHECK-NEXT: {{ $}} - ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:_(p0) = COPY $d0 - ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:_(<4 x s32>) = COPY $q0 - ;CHECK-NEXT: G_STORE %bb0_{{[0-9]+}}__1(<4 x s32>), %bb0_{{[0-9]+}}__1(p0) :: (store (<4 x s32>)) + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:_(p0) = COPY $d0 + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:_(<4 x s32>) = COPY $q0 + ;CHECK-NEXT: G_STORE %bb0_{{[0-9a-f]+}}__1(<4 x s32>), %bb0_{{[0-9a-f]+}}__1(p0) :: (store (<4 x s32>)) liveins: $q0, $d0 %1:fpr(p0) = COPY $d0 @@ -28,19 +28,19 @@ bb.0: ;CHECK-LABEL: bb.0 - ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = LDRWui - ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 1 - ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = LDRWui - ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 2 - ;CHECK-NEXT: %bb0_{{[0-9]+}}__3:gpr32 = LDRWui - ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 3 - ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = nsw ADDWrr - ;CHECK-NEXT: %bb0_{{[0-9]+}}__4:gpr32 = LDRWui - ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = nsw ADDWrr - ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 4 - ;CHECK-NEXT: %bb0_{{[0-9]+}}__3:gpr32 = nsw ADDWrr - ;CHECK-NEXT: %bb0_{{[0-9]+}}__5:gpr32 = LDRWui - ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = MOVi32imm 5 + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = LDRWui + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = MOVi32imm 1 + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__2:gpr32 = LDRWui + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = MOVi32imm 2 + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__3:gpr32 = LDRWui + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = MOVi32imm 3 + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = nsw ADDWrr + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__4:gpr32 = LDRWui + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__2:gpr32 = nsw ADDWrr + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = MOVi32imm 4 + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__3:gpr32 = nsw ADDWrr + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__5:gpr32 = LDRWui + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = MOVi32imm 5 %0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load (s64)) %1:gpr32 = MOVi32imm 1 @@ -78,11 +78,11 @@ ;CHECK-LABEL: bb.0: ;CHECK-NEXT: liveins ;CHECK-NEXT: {{ $}} - ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = LDRWui %stack.0, 0 - ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = COPY %bb0_{{[0-9]+}}__1 - ;CHECK-NEXT: %bb0_{{[0-9]+}}__1:gpr32 = COPY %bb0_{{[0-9]+}}__1 - ;CHECK-NEXT: %bb0_{{[0-9]+}}__2:gpr32 = COPY %bb0_{{[0-9]+}}__1 - ;CHECK-NEXT: $w0 = COPY %bb0_{{[0-9]+}}__2 + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = LDRWui %stack.0, 0 + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = COPY %bb0_{{[0-9a-f]+}}__1 + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:gpr32 = COPY %bb0_{{[0-9a-f]+}}__1 + ;CHECK-NEXT: %bb0_{{[0-9a-f]+}}__2:gpr32 = COPY %bb0_{{[0-9a-f]+}}__1 + ;CHECK-NEXT: $w0 = COPY %bb0_{{[0-9a-f]+}}__2 %0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load (s64)) %1:gpr32 = COPY %0 Index: llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir =================================================================== --- llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir +++ llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir @@ -8,18 +8,18 @@ body: | bb.0: ; CHECK-LABEL: name: foo - ; CHECK: %bb0_{{[0-9]+}}__1:sreg_32_xm0 = S_MOV_B32 61440 - ; CHECK: %bb0_{{[0-9]+}}__1:sreg_32_xm0 = S_MOV_B32 0 - ; CHECK: %bb0_{{[0-9]+}}__1:vgpr_32 = COPY $vgpr0 - ; CHECK: %bb0_{{[0-9]+}}__1:sgpr_64 = COPY $sgpr0_sgpr1 - ; CHECK: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_{{[0-9]+}}__1, 9, 0 - ; CHECK: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_{{[0-9]+}}__1, 11, 0 - ; CHECK: %bb0_{{[0-9]+}}__1:vgpr_32 = COPY %bb0_{{[0-9]+}}__1 - ; CHECK: %bb0_{{[0-9]+}}__1:vgpr_32 = COPY %bb0_{{[0-9]+}}__1 - ; CHECK: %bb0_{{[0-9]+}}__2:vgpr_32 = COPY %bb0_{{[0-9]+}}__1 - ; CHECK: %bb0_{{[0-9]+}}__1:vreg_64 = REG_SEQUENCE %bb0_{{[0-9]+}}__1, %subreg.sub0, %bb0_{{[0-9]+}}__1, %subreg.sub1 - ; CHECK: %bb0_{{[0-9]+}}__1:sgpr_128 = REG_SEQUENCE %bb0_{{[0-9]+}}__1, %subreg.sub0, %bb0_{{[0-9]+}}__1, %subreg.sub1, %bb0_{{[0-9]+}}__1, %subreg.sub2, %bb0_{{[0-9]+}}__2, %subreg.sub3 - ; CHECK: BUFFER_STORE_DWORD_ADDR64 %bb0_{{[0-9]+}}__1, %bb0_{{[0-9]+}}__1, %bb0_{{[0-9]+}}__1, 0, 0, 0, 0, 0, implicit $exec + ; CHECK: %bb0_{{[0-9a-f]+}}__1:sreg_32_xm0 = S_MOV_B32 61440 + ; CHECK: %bb0_{{[0-9a-f]+}}__1:sreg_32_xm0 = S_MOV_B32 0 + ; CHECK: %bb0_{{[0-9a-f]+}}__1:vgpr_32 = COPY $vgpr0 + ; CHECK: %bb0_{{[0-9a-f]+}}__1:sgpr_64 = COPY $sgpr0_sgpr1 + ; CHECK: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_{{[0-9a-f]+}}__1, 9, 0 + ; CHECK: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %bb0_{{[0-9a-f]+}}__1, 11, 0 + ; CHECK: %bb0_{{[0-9a-f]+}}__1:vgpr_32 = COPY %bb0_{{[0-9a-f]+}}__1 + ; CHECK: %bb0_{{[0-9a-f]+}}__1:vgpr_32 = COPY %bb0_{{[0-9a-f]+}}__1 + ; CHECK: %bb0_{{[0-9a-f]+}}__2:vgpr_32 = COPY %bb0_{{[0-9a-f]+}}__1 + ; CHECK: %bb0_{{[0-9a-f]+}}__1:vreg_64 = REG_SEQUENCE %bb0_{{[0-9a-f]+}}__1, %subreg.sub0, %bb0_{{[0-9a-f]+}}__1, %subreg.sub1 + ; CHECK: %bb0_{{[0-9a-f]+}}__1:sgpr_128 = REG_SEQUENCE %bb0_{{[0-9a-f]+}}__1, %subreg.sub0, %bb0_{{[0-9a-f]+}}__1, %subreg.sub1, %bb0_{{[0-9a-f]+}}__1, %subreg.sub2, %bb0_{{[0-9a-f]+}}__2, %subreg.sub3 + ; CHECK: BUFFER_STORE_DWORD_ADDR64 %bb0_{{[0-9a-f]+}}__1, %bb0_{{[0-9a-f]+}}__1, %bb0_{{[0-9a-f]+}}__1, 0, 0, 0, 0, 0, implicit $exec ; CHECK: S_ENDPGM 0 %10:sreg_32_xm0 = S_MOV_B32 61440 %11:sreg_32_xm0 = S_MOV_B32 0 Index: llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir =================================================================== --- llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir +++ llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir @@ -25,12 +25,12 @@ liveins: $sgpr4_sgpr5 ; CHECK: COPY - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:sreg_64_xexec = S_LOAD_DWORDX2_IMM %0 = COPY $sgpr4_sgpr5 %1 = S_LOAD_DWORDX2_IMM %0, 0, 0 :: (non-temporal dereferenceable invariant load (s64) from `i64 addrspace(4)* undef`) Index: llvm/test/CodeGen/MIR/X86/mir-canon-hash-bb.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/mir-canon-hash-bb.mir +++ llvm/test/CodeGen/MIR/X86/mir-canon-hash-bb.mir @@ -40,7 +40,7 @@ G_BR %bb.2 ; CHECK: bb.1: - ; CHECK: %bb2_{{[0-9]+}}__1:_(s32) = G_CONSTANT + ; CHECK: %bb2_{{[0-9a-f]+}}__1:_(s32) = G_CONSTANT bb.1: %tmp4:_(s32) = G_CONSTANT i32 1 G_STORE %tmp4(s32), %tmp6(p0) :: (store (s32) into %ir.tmp1) @@ -48,13 +48,13 @@ ; CHECK: bb.2: - ; CHECK: %bb1_{{[0-9]+}}__1:_(s32) = G_CONSTANT + ; CHECK: %bb1_{{[0-9a-f]+}}__1:_(s32) = G_CONSTANT bb.2: %tmp3:_(s32) = G_CONSTANT i32 2 G_STORE %tmp3(s32), %tmp6(p0) :: (store (s32) into %ir.tmp1) ; CHECK: bb.3: - ; CHECK: %bb3_{{[0-9]+}}__1:_(s32) = G_LOAD + ; CHECK: %bb3_{{[0-9a-f]+}}__1:_(s32) = G_LOAD bb.3: %tmp9:_(s32) = G_LOAD %tmp6(p0) :: (load (s32) from %ir.tmp1) $eax = COPY %tmp9(s32) Index: llvm/test/CodeGen/MIR/X86/mircanon-flags.mir =================================================================== --- llvm/test/CodeGen/MIR/X86/mircanon-flags.mir +++ llvm/test/CodeGen/MIR/X86/mircanon-flags.mir @@ -12,15 +12,15 @@ bb.0: ; CHECK: COPY - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nnan VMULSSrr - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = ninf VMULSSrr - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nsz VMULSSrr - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = arcp VMULSSrr - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract VMULSSrr - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = afn VMULSSrr - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = reassoc VMULSSrr - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nsz arcp contract afn reassoc VMULSSrr - ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract afn reassoc VMULSSrr + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = nnan VMULSSrr + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = ninf VMULSSrr + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = nsz VMULSSrr + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = arcp VMULSSrr + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = contract VMULSSrr + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = afn VMULSSrr + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = reassoc VMULSSrr + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = nsz arcp contract afn reassoc VMULSSrr + ; CHECK-NEXT: %bb0_{{[0-9a-f]+}}__1:fr32 = contract afn reassoc VMULSSrr %0:fr32 = COPY $xmm0 %1:fr32 = nnan VMULSSrr %0, %0, implicit $mxcsr