diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -145,7 +145,7 @@
 def HasSMEI16I64     : Predicate<"Subtarget->hasSMEI16I64()">,
                                  AssemblerPredicateWithAll<(all_of FeatureSMEI16I64), "sme-i16i64">;
 def HasSME2          : Predicate<"Subtarget->hasSME2()">,
-                                 AssemblerPredicate<(all_of FeatureSME2), "sme2">;
+                                 AssemblerPredicateWithAll<(all_of FeatureSME2), "sme2">;
 // A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
 // they should be enabled if either has been specified.
 def HasSVEorSME
diff --git a/llvm/test/MC/Disassembler/AArch64/mattr-all.txt b/llvm/test/MC/Disassembler/AArch64/mattr-all.txt
--- a/llvm/test/MC/Disassembler/AArch64/mattr-all.txt
+++ b/llvm/test/MC/Disassembler/AArch64/mattr-all.txt
@@ -39,3 +39,19 @@
 ## predres (to make sure sysreg aliases work)
 # CHECK: cfp rctx, x0
 [0x80,0x73,0x0b,0xd5]
+
+## sme
+# CHECK: addha za0.s, p0/m, p0/m, z0.s
+[0x00,0x00,0x90,0xc0]
+
+## smef64
+# CHECK: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
+[0x00,0x00,0xc0,0x80]
+
+## smei64
+# CHECK: addha za0.d, p0/m, p0/m, z0.d
+[0x00,0x00,0xd0,0xc0]
+
+## sme2
+# CHECK: add { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+[0x00,0xa3,0x60,0xc1]
\ No newline at end of file