Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td =================================================================== --- llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -1487,9 +1487,9 @@ Sched<[]>; } -// The cycle counter PMC register is PMCCNTR_EL0. +// The virtual cycle counter register is CNTVCT_EL0. let Predicates = [HasPerfMon] in -def : Pat<(readcyclecounter), (MRS 0xdce8)>; +def : Pat<(readcyclecounter), (MRS 0xdf02)>; // FPCR register def : Pat<(i64 (int_aarch64_get_fpcr)), (MRS 0xda20)>; Index: llvm/test/CodeGen/AArch64/readcyclecounter.ll =================================================================== --- llvm/test/CodeGen/AArch64/readcyclecounter.ll +++ llvm/test/CodeGen/AArch64/readcyclecounter.ll @@ -37,7 +37,7 @@ define i64 @test_readcyclecounter() nounwind { ; CHECK-LABEL: test_readcyclecounter: - ; PERFMON-NEXT: mrs x0, PMCCNTR_EL0 + ; PERFMON-NEXT: mrs x0, CNTVCT_EL0 ; NOPERFMON-NEXT: mov x0, xzr ; CHECK-NEXT: ret %tmp0 = call i64 @llvm.readcyclecounter()