diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll @@ -3,6 +3,7 @@ target triple = "aarch64-unknown-linux-gnu" +; f16 define <2 x half> @select_v2f16(<2 x half> %op1, <2 x half> %op2, i1 %mask) #0 { ; CHECK-LABEL: select_v2f16: ; CHECK: // %bb.0: @@ -88,7 +89,7 @@ ret <8 x half> %sel } -define void @select_v16f16(ptr %a, ptr %b, i1 %mask) #0 { +define void @select_v16f16(<16 x half>* %a, <16 x half>* %b, i1 %mask) #0 { ; CHECK-LABEL: select_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 @@ -120,13 +121,14 @@ ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %op1 = load volatile <16 x half>, ptr %a - %op2 = load volatile <16 x half>, ptr %b + %op1 = load volatile <16 x half>, <16 x half>* %a + %op2 = load volatile <16 x half>, <16 x half>* %b %sel = select i1 %mask, <16 x half> %op1, <16 x half> %op2 - store <16 x half> %sel, ptr %a + store <16 x half> %sel, <16 x half>* %a ret void } +; f32 define <2 x float> @select_v2f32(<2 x float> %op1, <2 x float> %op2, i1 %mask) #0 { ; CHECK-LABEL: select_v2f32: ; CHECK: // %bb.0: @@ -176,7 +178,7 @@ ret <4 x float> %sel } -define void @select_v8f32(ptr %a, ptr %b, i1 %mask) #0 { +define void @select_v8f32(<8 x float>* %a, <8 x float>* %b, i1 %mask) #0 { ; CHECK-LABEL: select_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 @@ -202,45 +204,26 @@ ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %op1 = load volatile <8 x float>, ptr %a - %op2 = load volatile <8 x float>, ptr %b + %op1 = load volatile <8 x float>, <8 x float>* %a + %op2 = load volatile <8 x float>, <8 x float>* %b %sel = select i1 %mask, <8 x float> %op1, <8 x float> %op2 - store <8 x float> %sel, ptr %a + store <8 x float> %sel, <8 x float>* %a ret void } -define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, i1 %mask) #0 { -; CHECK-LABEL: select_v1f64: -; CHECK: // %bb.0: -; CHECK-NEXT: tst w0, #0x1 -; CHECK-NEXT: mov x9, #-1 -; CHECK-NEXT: csetm x8, ne -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: fmov d3, x9 -; CHECK-NEXT: fmov d2, x8 -; CHECK-NEXT: eor z3.d, z2.d, z3.d -; CHECK-NEXT: and z0.d, z0.d, z2.d -; CHECK-NEXT: and z1.d, z1.d, z3.d -; CHECK-NEXT: orr z0.d, z0.d, z1.d -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 -; CHECK-NEXT: ret - %sel = select i1 %mask, <1 x double> %op1, <1 x double> %op2 - ret <1 x double> %sel -} - +; f64 define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, i1 %mask) #0 { ; CHECK-LABEL: select_v2f64: ; CHECK: // %bb.0: ; CHECK-NEXT: tst w0, #0x1 ; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 -; CHECK-NEXT: adrp x9, .LCPI8_0 +; CHECK-NEXT: adrp x9, .LCPI7_0 ; CHECK-NEXT: csetm x8, ne ; CHECK-NEXT: stp x8, x8, [sp, #-16]! ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: ldr q2, [sp] -; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI8_0] +; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI7_0] ; CHECK-NEXT: and z0.d, z0.d, z2.d ; CHECK-NEXT: eor z3.d, z2.d, z3.d ; CHECK-NEXT: and z1.d, z1.d, z3.d @@ -252,7 +235,7 @@ ret <2 x double> %sel } -define void @select_v4f64(ptr %a, ptr %b, i1 %mask) #0 { +define void @select_v4f64(<4 x double>* %a, <4 x double>* %b, i1 %mask) #0 { ; CHECK-LABEL: select_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: tst w2, #0x1 @@ -260,11 +243,11 @@ ; CHECK-NEXT: csetm x8, ne ; CHECK-NEXT: ldr q1, [x0, #16] ; CHECK-NEXT: ldr q2, [x1] -; CHECK-NEXT: adrp x9, .LCPI9_0 +; CHECK-NEXT: adrp x9, .LCPI8_0 ; CHECK-NEXT: ldr q3, [x1, #16] ; CHECK-NEXT: stp x8, x8, [sp, #-16]! ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI9_0] +; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI8_0] ; CHECK-NEXT: ldr q5, [sp] ; CHECK-NEXT: eor z4.d, z5.d, z4.d ; CHECK-NEXT: and z1.d, z1.d, z5.d @@ -276,10 +259,10 @@ ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %op1 = load volatile <4 x double>, ptr %a - %op2 = load volatile <4 x double>, ptr %b + %op1 = load volatile <4 x double>, <4 x double>* %a + %op2 = load volatile <4 x double>, <4 x double>* %b %sel = select i1 %mask, <4 x double> %op1, <4 x double> %op2 - store <4 x double> %sel, ptr %a + store <4 x double> %sel, <4 x double>* %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll @@ -291,7 +291,7 @@ ; CHECK-LABEL: fcvtzu_v4f32_v4i16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 -; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -304,7 +304,7 @@ ; CHECK-LABEL: fcvtzu_v8f32_v8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: fcvtzu z1.s, p0/m, z1.s ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s ; CHECK-NEXT: ptrue p0.h, vl4 @@ -322,7 +322,7 @@ ; CHECK-LABEL: fcvtzu_v16f32_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] -; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p1.h, vl4 ; CHECK-NEXT: fcvtzu z0.s, p0/m, z0.s ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h @@ -478,7 +478,7 @@ ; CHECK-LABEL: fcvtzu_v2f64_v2i16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -493,7 +493,7 @@ ; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d ; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d @@ -522,7 +522,7 @@ ; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: ldp q0, q1, [x0, #32] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: ldp q3, q2, [x0] @@ -565,7 +565,7 @@ ; CHECK-NEXT: sub sp, sp, #32 ; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: ldp q2, q3, [x0, #32] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d ; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s ; CHECK-NEXT: ldp q4, q5, [x0] @@ -644,7 +644,7 @@ ; CHECK-LABEL: fcvtzu_v1f64_v1i32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -657,7 +657,7 @@ ; CHECK-LABEL: fcvtzu_v2f64_v2i32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -670,7 +670,7 @@ ; CHECK-LABEL: fcvtzu_v4f64_v4i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzu z1.d, p0/m, z1.d ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d ; CHECK-NEXT: ptrue p0.s, vl2 @@ -688,7 +688,7 @@ ; CHECK-LABEL: fcvtzu_v8f64_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p1.s, vl2 ; CHECK-NEXT: fcvtzu z0.d, p0/m, z0.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s @@ -1040,7 +1040,7 @@ ; CHECK-LABEL: fcvtzs_v4f32_v4i16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 -; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -1053,7 +1053,7 @@ ; CHECK-LABEL: fcvtzs_v8f32_v8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: fcvtzs z1.s, p0/m, z1.s ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: ptrue p0.h, vl4 @@ -1071,7 +1071,7 @@ ; CHECK-LABEL: fcvtzs_v16f32_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] -; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p1.h, vl4 ; CHECK-NEXT: fcvtzs z0.s, p0/m, z0.s ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h @@ -1229,7 +1229,7 @@ ; CHECK-LABEL: fcvtzs_v2f64_v2i16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -1244,7 +1244,7 @@ ; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d ; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d @@ -1273,7 +1273,7 @@ ; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: ldp q0, q1, [x0, #32] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: ldp q3, q2, [x0] @@ -1316,7 +1316,7 @@ ; CHECK-NEXT: sub sp, sp, #32 ; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: ldp q2, q3, [x0, #32] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z2.d, p0/m, z2.d ; CHECK-NEXT: uzp1 z2.s, z2.s, z2.s ; CHECK-NEXT: ldp q4, q5, [x0] @@ -1395,7 +1395,7 @@ ; CHECK-LABEL: fcvtzs_v1f64_v1i32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -1408,7 +1408,7 @@ ; CHECK-LABEL: fcvtzs_v2f64_v2i32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -1421,7 +1421,7 @@ ; CHECK-LABEL: fcvtzs_v4f64_v4i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: fcvtzs z1.d, p0/m, z1.d ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: ptrue p0.s, vl2 @@ -1439,7 +1439,7 @@ ; CHECK-LABEL: fcvtzs_v8f64_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p1.s, vl2 ; CHECK-NEXT: fcvtzs z0.d, p0/m, z0.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll @@ -82,7 +82,7 @@ ret <8 x half> %sel } -define void @select_v16f16(ptr %a, ptr %b) #0 { +define void @select_v16f16(<16 x half>* %a, <16 x half>* %b) #0 { ; CHECK-LABEL: select_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x1] @@ -104,11 +104,11 @@ ; CHECK-NEXT: orr z1.d, z2.d, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, ptr %a - %op2 = load <16 x half>, ptr %b + %op1 = load <16 x half>, <16 x half>* %a + %op2 = load <16 x half>, <16 x half>* %b %mask = fcmp oeq <16 x half> %op1, %op2 %sel = select <16 x i1> %mask, <16 x half> %op1, <16 x half> %op2 - store <16 x half> %sel, ptr %a + store <16 x half> %sel, <16 x half>* %a ret void } @@ -159,7 +159,7 @@ ret <4 x float> %sel } -define void @select_v8f32(ptr %a, ptr %b) #0 { +define void @select_v8f32(<8 x float>* %a, <8 x float>* %b) #0 { ; CHECK-LABEL: select_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x1] @@ -181,46 +181,26 @@ ; CHECK-NEXT: orr z1.d, z2.d, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, ptr %a - %op2 = load <8 x float>, ptr %b + %op1 = load <8 x float>, <8 x float>* %a + %op2 = load <8 x float>, <8 x float>* %b %mask = fcmp oeq <8 x float> %op1, %op2 %sel = select <8 x i1> %mask, <8 x float> %op1, <8 x float> %op2 - store <8 x float> %sel, ptr %a + store <8 x float> %sel, <8 x float>* %a ret void } -define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x i1> %mask) #0 { -; CHECK-LABEL: select_v1f64: -; CHECK: // %bb.0: -; CHECK-NEXT: tst w0, #0x1 -; CHECK-NEXT: mov x9, #-1 -; CHECK-NEXT: csetm x8, ne -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: fmov d3, x9 -; CHECK-NEXT: fmov d2, x8 -; CHECK-NEXT: eor z3.d, z2.d, z3.d -; CHECK-NEXT: and z0.d, z0.d, z2.d -; CHECK-NEXT: and z1.d, z1.d, z3.d -; CHECK-NEXT: orr z0.d, z0.d, z1.d -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 -; CHECK-NEXT: ret - %sel = select <1 x i1> %mask, <1 x double> %op1, <1 x double> %op2 - ret <1 x double> %sel -} - define <2 x double> @select_v2f64(<2 x double> %op1, <2 x double> %op2, <2 x i1> %mask) #0 { ; CHECK-LABEL: select_v2f64: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI8_0 -; CHECK-NEXT: adrp x9, .LCPI8_1 +; CHECK-NEXT: adrp x8, .LCPI7_0 +; CHECK-NEXT: adrp x9, .LCPI7_1 ; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 ; CHECK-NEXT: ptrue p0.d, vl2 ; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 ; CHECK-NEXT: uunpklo z2.d, z2.s -; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI8_0] -; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI8_1] +; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI7_0] +; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI7_1] ; CHECK-NEXT: lsl z2.d, p0/m, z2.d, z3.d ; CHECK-NEXT: asr z2.d, p0/m, z2.d, z3.d ; CHECK-NEXT: eor z3.d, z2.d, z4.d @@ -233,14 +213,14 @@ ret <2 x double> %sel } -define void @select_v4f64(ptr %a, ptr %b) #0 { +define void @select_v4f64(<4 x double>* %a, <4 x double>* %b) #0 { ; CHECK-LABEL: select_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x1] -; CHECK-NEXT: adrp x8, .LCPI9_0 +; CHECK-NEXT: adrp x8, .LCPI8_0 ; CHECK-NEXT: ptrue p0.d, vl2 ; CHECK-NEXT: ldp q3, q2, [x0] -; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI9_0] +; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI8_0] ; CHECK-NEXT: fcmeq p1.d, p0/z, z2.d, z1.d ; CHECK-NEXT: fcmeq p0.d, p0/z, z3.d, z0.d ; CHECK-NEXT: mov z5.d, p1/z, #-1 // =0xffffffffffffffff @@ -255,11 +235,11 @@ ; CHECK-NEXT: orr z1.d, z2.d, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, ptr %a - %op2 = load <4 x double>, ptr %b + %op1 = load <4 x double>, <4 x double>* %a + %op2 = load <4 x double>, <4 x double>* %b %mask = fcmp oeq <4 x double> %op1, %op2 %sel = select <4 x i1> %mask, <4 x double> %op1, <4 x double> %op2 - store <4 x double> %sel, ptr %a + store <4 x double> %sel, <4 x double>* %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll @@ -7,6 +7,25 @@ ; ICMP EQ ; +define <4 x i8> @icmp_eq_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 { +; CHECK-LABEL: icmp_eq_v4i8: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI0_0 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.h, vl4 +; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_0] +; CHECK-NEXT: and z1.d, z1.d, z2.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h +; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %cmp = icmp eq <4 x i8> %op1, %op2 + %sext = sext <4 x i1> %cmp to <4 x i8> + ret <4 x i8> %sext +} + define <8 x i8> @icmp_eq_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 { ; CHECK-LABEL: icmp_eq_v8i8: ; CHECK: // %bb.0: @@ -37,7 +56,7 @@ ret <16 x i8> %sext } -define void @icmp_eq_v32i8(ptr %a, ptr %b) #0 { +define void @icmp_eq_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 { ; CHECK-LABEL: icmp_eq_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -49,14 +68,33 @@ ; CHECK-NEXT: mov z1.b, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a - %op2 = load <32 x i8>, ptr %b + %op1 = load <32 x i8>, <32 x i8>* %a + %op2 = load <32 x i8>, <32 x i8>* %b %cmp = icmp eq <32 x i8> %op1, %op2 %sext = sext <32 x i1> %cmp to <32 x i8> - store <32 x i8> %sext, ptr %a + store <32 x i8> %sext, <32 x i8>* %a ret void } +define <2 x i16> @icmp_eq_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 { +; CHECK-LABEL: icmp_eq_v2i16: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI4_0 +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI4_0] +; CHECK-NEXT: and z1.d, z1.d, z2.d +; CHECK-NEXT: and z0.d, z0.d, z2.d +; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s +; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: ret + %cmp = icmp eq <2 x i16> %op1, %op2 + %sext = sext <2 x i1> %cmp to <2 x i16> + ret <2 x i16> %sext +} + define <4 x i16> @icmp_eq_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 { ; CHECK-LABEL: icmp_eq_v4i16: ; CHECK: // %bb.0: @@ -87,7 +125,7 @@ ret <8 x i16> %sext } -define void @icmp_eq_v16i16(ptr %a, ptr %b) #0 { +define void @icmp_eq_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { ; CHECK-LABEL: icmp_eq_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -99,11 +137,11 @@ ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a - %op2 = load <16 x i16>, ptr %b + %op1 = load <16 x i16>, <16 x i16>* %a + %op2 = load <16 x i16>, <16 x i16>* %b %cmp = icmp eq <16 x i16> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, ptr %a + store <16 x i16> %sext, <16 x i16>* %a ret void } @@ -137,7 +175,7 @@ ret <4 x i32> %sext } -define void @icmp_eq_v8i32(ptr %a, ptr %b) #0 { +define void @icmp_eq_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { ; CHECK-LABEL: icmp_eq_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -149,11 +187,11 @@ ; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a - %op2 = load <8 x i32>, ptr %b + %op1 = load <8 x i32>, <8 x i32>* %a + %op2 = load <8 x i32>, <8 x i32>* %b %cmp = icmp eq <8 x i32> %op1, %op2 %sext = sext <8 x i1> %cmp to <8 x i32> - store <8 x i32> %sext, ptr %a + store <8 x i32> %sext, <8 x i32>* %a ret void } @@ -187,7 +225,7 @@ ret <2 x i64> %sext } -define void @icmp_eq_v4i64(ptr %a, ptr %b) #0 { +define void @icmp_eq_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 { ; CHECK-LABEL: icmp_eq_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -199,11 +237,11 @@ ; CHECK-NEXT: mov z1.d, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a - %op2 = load <4 x i64>, ptr %b + %op1 = load <4 x i64>, <4 x i64>* %a + %op2 = load <4 x i64>, <4 x i64>* %b %cmp = icmp eq <4 x i64> %op1, %op2 %sext = sext <4 x i1> %cmp to <4 x i64> - store <4 x i64> %sext, ptr %a + store <4 x i64> %sext, <4 x i64>* %a ret void } @@ -211,7 +249,7 @@ ; ICMP NE ; -define void @icmp_ne_v32i8(ptr %a, ptr %b) #0 { +define void @icmp_ne_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 { ; CHECK-LABEL: icmp_ne_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -223,11 +261,11 @@ ; CHECK-NEXT: mov z1.b, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a - %op2 = load <32 x i8>, ptr %b + %op1 = load <32 x i8>, <32 x i8>* %a + %op2 = load <32 x i8>, <32 x i8>* %b %cmp = icmp ne <32 x i8> %op1, %op2 %sext = sext <32 x i1> %cmp to <32 x i8> - store <32 x i8> %sext, ptr %a + store <32 x i8> %sext, <32 x i8>* %a ret void } @@ -235,21 +273,23 @@ ; ICMP SGE ; -define void @icmp_sge_v8i16(ptr %a, ptr %b) #0 { -; CHECK-LABEL: icmp_sge_v8i16: +define void @icmp_sge_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { +; CHECK-LABEL: icmp_sge_v16i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ptrue p0.h, vl8 -; CHECK-NEXT: ldr q1, [x1] -; CHECK-NEXT: cmpge p0.h, p0/z, z0.h, z1.h -; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ldp q2, q3, [x1] +; CHECK-NEXT: cmpge p1.h, p0/z, z0.h, z2.h +; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: cmpge p0.h, p0/z, z1.h, z3.h +; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i16>, ptr %a - %op2 = load <8 x i16>, ptr %b - %cmp = icmp sge <8 x i16> %op1, %op2 - %sext = sext <8 x i1> %cmp to <8 x i16> - store <8 x i16> %sext, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a + %op2 = load <16 x i16>, <16 x i16>* %b + %cmp = icmp sge <16 x i16> %op1, %op2 + %sext = sext <16 x i1> %cmp to <16 x i16> + store <16 x i16> %sext, <16 x i16>* %a ret void } @@ -257,7 +297,7 @@ ; ICMP SGT ; -define void @icmp_sgt_v16i16(ptr %a, ptr %b) #0 { +define void @icmp_sgt_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { ; CHECK-LABEL: icmp_sgt_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -269,11 +309,11 @@ ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a - %op2 = load <16 x i16>, ptr %b + %op1 = load <16 x i16>, <16 x i16>* %a + %op2 = load <16 x i16>, <16 x i16>* %b %cmp = icmp sgt <16 x i16> %op1, %op2 %sext = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %sext, ptr %a + store <16 x i16> %sext, <16 x i16>* %a ret void } @@ -281,21 +321,23 @@ ; ICMP SLE ; -define void @icmp_sle_v4i32(ptr %a, ptr %b) #0 { -; CHECK-LABEL: icmp_sle_v4i32: +define void @icmp_sle_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { +; CHECK-LABEL: icmp_sle_v8i32: ; CHECK: // %bb.0: -; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ptrue p0.s, vl4 -; CHECK-NEXT: ldr q1, [x1] -; CHECK-NEXT: cmpge p0.s, p0/z, z1.s, z0.s -; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ldp q2, q3, [x1] +; CHECK-NEXT: cmpge p1.s, p0/z, z2.s, z0.s +; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: cmpge p0.s, p0/z, z3.s, z1.s +; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i32>, ptr %a - %op2 = load <4 x i32>, ptr %b - %cmp = icmp sle <4 x i32> %op1, %op2 - %sext = sext <4 x i1> %cmp to <4 x i32> - store <4 x i32> %sext, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a + %op2 = load <8 x i32>, <8 x i32>* %b + %cmp = icmp sle <8 x i32> %op1, %op2 + %sext = sext <8 x i1> %cmp to <8 x i32> + store <8 x i32> %sext, <8 x i32>* %a ret void } @@ -303,7 +345,7 @@ ; ICMP SLT ; -define void @icmp_slt_v8i32(ptr %a, ptr %b) #0 { +define void @icmp_slt_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { ; CHECK-LABEL: icmp_slt_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -315,11 +357,11 @@ ; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a - %op2 = load <8 x i32>, ptr %b + %op1 = load <8 x i32>, <8 x i32>* %a + %op2 = load <8 x i32>, <8 x i32>* %b %cmp = icmp slt <8 x i32> %op1, %op2 %sext = sext <8 x i1> %cmp to <8 x i32> - store <8 x i32> %sext, ptr %a + store <8 x i32> %sext, <8 x i32>* %a ret void } @@ -327,21 +369,23 @@ ; ICMP UGE ; -define void @icmp_uge_v2i64(ptr %a, ptr %b) #0 { -; CHECK-LABEL: icmp_uge_v2i64: +define void @icmp_uge_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 { +; CHECK-LABEL: icmp_uge_v4i64: ; CHECK: // %bb.0: -; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ptrue p0.d, vl2 -; CHECK-NEXT: ldr q1, [x1] -; CHECK-NEXT: cmphs p0.d, p0/z, z0.d, z1.d -; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ldp q2, q3, [x1] +; CHECK-NEXT: cmphs p1.d, p0/z, z0.d, z2.d +; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: cmphs p0.d, p0/z, z1.d, z3.d +; CHECK-NEXT: mov z1.d, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <2 x i64>, ptr %a - %op2 = load <2 x i64>, ptr %b - %cmp = icmp uge <2 x i64> %op1, %op2 - %sext = sext <2 x i1> %cmp to <2 x i64> - store <2 x i64> %sext, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a + %op2 = load <4 x i64>, <4 x i64>* %b + %cmp = icmp uge <4 x i64> %op1, %op2 + %sext = sext <4 x i1> %cmp to <4 x i64> + store <4 x i64> %sext, <4 x i64>* %a ret void } @@ -349,21 +393,23 @@ ; ICMP UGT ; -define void @icmp_ugt_v2i64(ptr %a, ptr %b) #0 { -; CHECK-LABEL: icmp_ugt_v2i64: +define void @icmp_ugt_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 { +; CHECK-LABEL: icmp_ugt_v4i64: ; CHECK: // %bb.0: -; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ptrue p0.d, vl2 -; CHECK-NEXT: ldr q1, [x1] -; CHECK-NEXT: cmphi p0.d, p0/z, z0.d, z1.d -; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ldp q2, q3, [x1] +; CHECK-NEXT: cmphi p1.d, p0/z, z0.d, z2.d +; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: cmphi p0.d, p0/z, z1.d, z3.d +; CHECK-NEXT: mov z1.d, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <2 x i64>, ptr %a - %op2 = load <2 x i64>, ptr %b - %cmp = icmp ugt <2 x i64> %op1, %op2 - %sext = sext <2 x i1> %cmp to <2 x i64> - store <2 x i64> %sext, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a + %op2 = load <4 x i64>, <4 x i64>* %b + %cmp = icmp ugt <4 x i64> %op1, %op2 + %sext = sext <4 x i1> %cmp to <4 x i64> + store <4 x i64> %sext, <4 x i64>* %a ret void } @@ -371,21 +417,23 @@ ; ICMP ULE ; -define void @icmp_ule_v2i64(ptr %a, ptr %b) #0 { -; CHECK-LABEL: icmp_ule_v2i64: +define void @icmp_ule_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 { +; CHECK-LABEL: icmp_ule_v4i64: ; CHECK: // %bb.0: -; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ptrue p0.d, vl2 -; CHECK-NEXT: ldr q1, [x1] -; CHECK-NEXT: cmphs p0.d, p0/z, z1.d, z0.d -; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ldp q2, q3, [x1] +; CHECK-NEXT: cmphs p1.d, p0/z, z2.d, z0.d +; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: cmphs p0.d, p0/z, z3.d, z1.d +; CHECK-NEXT: mov z1.d, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <2 x i64>, ptr %a - %op2 = load <2 x i64>, ptr %b - %cmp = icmp ule <2 x i64> %op1, %op2 - %sext = sext <2 x i1> %cmp to <2 x i64> - store <2 x i64> %sext, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a + %op2 = load <4 x i64>, <4 x i64>* %b + %cmp = icmp ule <4 x i64> %op1, %op2 + %sext = sext <4 x i1> %cmp to <4 x i64> + store <4 x i64> %sext, <4 x i64>* %a ret void } @@ -393,21 +441,23 @@ ; ICMP ULT ; -define void @icmp_ult_v2i64(ptr %a, ptr %b) #0 { -; CHECK-LABEL: icmp_ult_v2i64: +define void @icmp_ult_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 { +; CHECK-LABEL: icmp_ult_v4i64: ; CHECK: // %bb.0: -; CHECK-NEXT: ldr q0, [x0] +; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ptrue p0.d, vl2 -; CHECK-NEXT: ldr q1, [x1] -; CHECK-NEXT: cmphi p0.d, p0/z, z1.d, z0.d -; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff -; CHECK-NEXT: str q0, [x0] +; CHECK-NEXT: ldp q2, q3, [x1] +; CHECK-NEXT: cmphi p1.d, p0/z, z2.d, z0.d +; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: cmphi p0.d, p0/z, z3.d, z1.d +; CHECK-NEXT: mov z1.d, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <2 x i64>, ptr %a - %op2 = load <2 x i64>, ptr %b - %cmp = icmp ult <2 x i64> %op1, %op2 - %sext = sext <2 x i1> %cmp to <2 x i64> - store <2 x i64> %sext, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a + %op2 = load <4 x i64>, <4 x i64>* %b + %cmp = icmp ult <4 x i64> %op1, %op2 + %sext = sext <4 x i1> %cmp to <4 x i64> + store <4 x i64> %sext, <4 x i64>* %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll @@ -7,13 +7,11 @@ ; these tests protects against the possibility that scalable nodes, resulting ; from lowering fixed length vector operations, trigger different isel patterns. -; FIXME: These instructions should have the immediate form - ; ; ADD ; -define void @add_v32i8(ptr %a) #0 { +define void @add_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: add_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI0_0 @@ -23,15 +21,15 @@ ; CHECK-NEXT: add z0.b, z2.b, z0.b ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i32 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %res = add <32 x i8> %op1, %op2 - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @add_v16i16(ptr %a) #0 { +define void @add_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: add_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI1_0 @@ -41,15 +39,15 @@ ; CHECK-NEXT: add z0.h, z2.h, z0.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %res = add <16 x i16> %op1, %op2 - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @add_v8i32(ptr %a) #0 { +define void @add_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: add_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI2_0 @@ -59,15 +57,15 @@ ; CHECK-NEXT: add z0.s, z2.s, z0.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %res = add <8 x i32> %op1, %op2 - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @add_v4i64(ptr %a) #0 { +define void @add_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: add_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI3_0 @@ -77,11 +75,11 @@ ; CHECK-NEXT: add z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %res = add <4 x i64> %op1, %op2 - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } @@ -89,7 +87,7 @@ ; AND ; -define void @and_v32i8(ptr %a) #0 { +define void @and_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: and_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI4_0 @@ -99,15 +97,15 @@ ; CHECK-NEXT: and z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i32 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %res = and <32 x i8> %op1, %op2 - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @and_v16i16(ptr %a) #0 { +define void @and_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: and_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI5_0 @@ -117,15 +115,15 @@ ; CHECK-NEXT: and z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %res = and <16 x i16> %op1, %op2 - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @and_v8i32(ptr %a) #0 { +define void @and_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: and_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI6_0 @@ -135,15 +133,15 @@ ; CHECK-NEXT: and z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %res = and <8 x i32> %op1, %op2 - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @and_v4i64(ptr %a) #0 { +define void @and_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: and_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI7_0 @@ -153,11 +151,11 @@ ; CHECK-NEXT: and z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %res = and <4 x i64> %op1, %op2 - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } @@ -165,7 +163,7 @@ ; ASHR ; -define void @ashr_v32i8(ptr %a) #0 { +define void @ashr_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: ashr_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI8_0 @@ -176,15 +174,15 @@ ; CHECK-NEXT: asrr z0.b, p0/m, z0.b, z2.b ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i32 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %res = ashr <32 x i8> %op1, %op2 - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @ashr_v16i16(ptr %a) #0 { +define void @ashr_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: ashr_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI9_0 @@ -195,15 +193,15 @@ ; CHECK-NEXT: asrr z0.h, p0/m, z0.h, z2.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %res = ashr <16 x i16> %op1, %op2 - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @ashr_v8i32(ptr %a) #0 { +define void @ashr_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: ashr_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI10_0 @@ -214,15 +212,15 @@ ; CHECK-NEXT: asrr z0.s, p0/m, z0.s, z2.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %res = ashr <8 x i32> %op1, %op2 - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @ashr_v4i64(ptr %a) #0 { +define void @ashr_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: ashr_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI11_0 @@ -233,11 +231,11 @@ ; CHECK-NEXT: asrr z0.d, p0/m, z0.d, z2.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %res = ashr <4 x i64> %op1, %op2 - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } @@ -245,7 +243,7 @@ ; ICMP ; -define void @icmp_eq_v32i8(ptr %a) #0 { +define void @icmp_eq_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: icmp_eq_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI12_0 @@ -258,16 +256,16 @@ ; CHECK-NEXT: mov z1.b, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %cmp = icmp eq <32 x i8> %op1, %op2 %res = sext <32 x i1> %cmp to <32 x i8> - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @icmp_sge_v16i16(ptr %a) #0 { +define void @icmp_sge_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: icmp_sge_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI13_0 @@ -280,16 +278,16 @@ ; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %cmp = icmp sge <16 x i16> %op1, %op2 %res = sext <16 x i1> %cmp to <16 x i16> - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @icmp_sgt_v8i32(ptr %a) #0 { +define void @icmp_sgt_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: icmp_sgt_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI14_0 @@ -302,16 +300,16 @@ ; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 -8, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %cmp = icmp sgt <8 x i32> %op1, %op2 %res = sext <8 x i1> %cmp to <8 x i32> - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @icmp_ult_v4i64(ptr %a) #0 { +define void @icmp_ult_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: icmp_ult_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI15_0 @@ -324,12 +322,12 @@ ; CHECK-NEXT: mov z1.d, p0/z, #-1 // =0xffffffffffffffff ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %cmp = icmp ult <4 x i64> %op1, %op2 %res = sext <4 x i1> %cmp to <4 x i64> - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } @@ -337,7 +335,7 @@ ; LSHR ; -define void @lshr_v32i8(ptr %a) #0 { +define void @lshr_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: lshr_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI16_0 @@ -348,15 +346,15 @@ ; CHECK-NEXT: lsrr z0.b, p0/m, z0.b, z2.b ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %res = lshr <32 x i8> %op1, %op2 - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @lshr_v16i16(ptr %a) #0 { +define void @lshr_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: lshr_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI17_0 @@ -367,15 +365,15 @@ ; CHECK-NEXT: lsrr z0.h, p0/m, z0.h, z2.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %res = lshr <16 x i16> %op1, %op2 - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @lshr_v8i32(ptr %a) #0 { +define void @lshr_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: lshr_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI18_0 @@ -386,15 +384,15 @@ ; CHECK-NEXT: lsrr z0.s, p0/m, z0.s, z2.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %res = lshr <8 x i32> %op1, %op2 - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @lshr_v4i64(ptr %a) #0 { +define void @lshr_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: lshr_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI19_0 @@ -405,11 +403,11 @@ ; CHECK-NEXT: lsrr z0.d, p0/m, z0.d, z2.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %res = lshr <4 x i64> %op1, %op2 - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } @@ -417,7 +415,7 @@ ; MUL ; -define void @mul_v32i8(ptr %a) #0 { +define void @mul_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: mul_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI20_0 @@ -428,15 +426,15 @@ ; CHECK-NEXT: mul z0.b, p0/m, z0.b, z2.b ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %res = mul <32 x i8> %op1, %op2 - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @mul_v16i16(ptr %a) #0 { +define void @mul_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: mul_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI21_0 @@ -447,15 +445,15 @@ ; CHECK-NEXT: mul z0.h, p0/m, z0.h, z2.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %res = mul <16 x i16> %op1, %op2 - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @mul_v8i32(ptr %a) #0 { +define void @mul_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: mul_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI22_0 @@ -466,15 +464,15 @@ ; CHECK-NEXT: mul z0.s, p0/m, z0.s, z2.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %res = mul <8 x i32> %op1, %op2 - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @mul_v4i64(ptr %a) #0 { +define void @mul_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: mul_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI23_0 @@ -485,11 +483,11 @@ ; CHECK-NEXT: mul z0.d, p0/m, z0.d, z2.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %res = mul <4 x i64> %op1, %op2 - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } @@ -497,7 +495,7 @@ ; OR ; -define void @or_v32i8(ptr %a) #0 { +define void @or_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: or_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI24_0 @@ -507,15 +505,15 @@ ; CHECK-NEXT: orr z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %res = or <32 x i8> %op1, %op2 - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @or_v16i16(ptr %a) #0 { +define void @or_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: or_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI25_0 @@ -525,15 +523,15 @@ ; CHECK-NEXT: orr z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %res = or <16 x i16> %op1, %op2 - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @or_v8i32(ptr %a) #0 { +define void @or_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: or_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI26_0 @@ -543,15 +541,15 @@ ; CHECK-NEXT: orr z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %res = or <8 x i32> %op1, %op2 - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @or_v4i64(ptr %a) #0 { +define void @or_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: or_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI27_0 @@ -561,11 +559,11 @@ ; CHECK-NEXT: orr z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %res = or <4 x i64> %op1, %op2 - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } @@ -573,7 +571,7 @@ ; SHL ; -define void @shl_v32i8(ptr %a) #0 { +define void @shl_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: shl_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI28_0 @@ -584,15 +582,15 @@ ; CHECK-NEXT: lslr z0.b, p0/m, z0.b, z2.b ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %res = shl <32 x i8> %op1, %op2 - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @shl_v16i16(ptr %a) #0 { +define void @shl_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: shl_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI29_0 @@ -603,15 +601,15 @@ ; CHECK-NEXT: lslr z0.h, p0/m, z0.h, z2.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %res = shl <16 x i16> %op1, %op2 - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @shl_v8i32(ptr %a) #0 { +define void @shl_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: shl_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI30_0 @@ -622,15 +620,15 @@ ; CHECK-NEXT: lslr z0.s, p0/m, z0.s, z2.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %res = shl <8 x i32> %op1, %op2 - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @shl_v4i64(ptr %a) #0 { +define void @shl_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: shl_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI31_0 @@ -641,11 +639,11 @@ ; CHECK-NEXT: lslr z0.d, p0/m, z0.d, z2.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %res = shl <4 x i64> %op1, %op2 - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } @@ -653,7 +651,7 @@ ; SMAX ; -define void @smax_v32i8(ptr %a) #0 { +define void @smax_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: smax_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI32_0 @@ -664,15 +662,15 @@ ; CHECK-NEXT: smax z0.b, p0/m, z0.b, z2.b ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %res = call <32 x i8> @llvm.smax.v32i8(<32 x i8> %op1, <32 x i8> %op2) - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @smax_v16i16(ptr %a) #0 { +define void @smax_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: smax_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI33_0 @@ -683,15 +681,15 @@ ; CHECK-NEXT: smax z0.h, p0/m, z0.h, z2.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %res = call <16 x i16> @llvm.smax.v16i16(<16 x i16> %op1, <16 x i16> %op2) - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @smax_v8i32(ptr %a) #0 { +define void @smax_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: smax_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI34_0 @@ -702,15 +700,15 @@ ; CHECK-NEXT: smax z0.s, p0/m, z0.s, z2.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %res = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %op1, <8 x i32> %op2) - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @smax_v4i64(ptr %a) #0 { +define void @smax_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: smax_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI35_0 @@ -721,11 +719,11 @@ ; CHECK-NEXT: smax z0.d, p0/m, z0.d, z2.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %res = call <4 x i64> @llvm.smax.v4i64(<4 x i64> %op1, <4 x i64> %op2) - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } @@ -733,7 +731,7 @@ ; SMIN ; -define void @smin_v32i8(ptr %a) #0 { +define void @smin_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: smin_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI36_0 @@ -744,15 +742,15 @@ ; CHECK-NEXT: smin z0.b, p0/m, z0.b, z2.b ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %res = call <32 x i8> @llvm.smin.v32i8(<32 x i8> %op1, <32 x i8> %op2) - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @smin_v16i16(ptr %a) #0 { +define void @smin_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: smin_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI37_0 @@ -763,15 +761,15 @@ ; CHECK-NEXT: smin z0.h, p0/m, z0.h, z2.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %res = call <16 x i16> @llvm.smin.v16i16(<16 x i16> %op1, <16 x i16> %op2) - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @smin_v8i32(ptr %a) #0 { +define void @smin_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: smin_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI38_0 @@ -782,15 +780,15 @@ ; CHECK-NEXT: smin z0.s, p0/m, z0.s, z2.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %res = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %op1, <8 x i32> %op2) - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @smin_v4i64(ptr %a) #0 { +define void @smin_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: smin_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI39_0 @@ -801,11 +799,11 @@ ; CHECK-NEXT: smin z0.d, p0/m, z0.d, z2.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %res = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %op1, <4 x i64> %op2) - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } @@ -813,7 +811,7 @@ ; SUB ; -define void @sub_v32i8(ptr %a) #0 { +define void @sub_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: sub_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI40_0 @@ -823,15 +821,15 @@ ; CHECK-NEXT: sub z0.b, z2.b, z0.b ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %res = sub <32 x i8> %op1, %op2 - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @sub_v16i16(ptr %a) #0 { +define void @sub_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: sub_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI41_0 @@ -841,15 +839,15 @@ ; CHECK-NEXT: sub z0.h, z2.h, z0.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %res = sub <16 x i16> %op1, %op2 - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @sub_v8i32(ptr %a) #0 { +define void @sub_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: sub_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI42_0 @@ -859,15 +857,15 @@ ; CHECK-NEXT: sub z0.s, z2.s, z0.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %res = sub <8 x i32> %op1, %op2 - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @sub_v4i64(ptr %a) #0 { +define void @sub_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: sub_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI43_0 @@ -877,11 +875,11 @@ ; CHECK-NEXT: sub z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %res = sub <4 x i64> %op1, %op2 - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } @@ -889,7 +887,7 @@ ; UMAX ; -define void @umax_v32i8(ptr %a) #0 { +define void @umax_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: umax_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI44_0 @@ -900,15 +898,15 @@ ; CHECK-NEXT: umax z0.b, p0/m, z0.b, z2.b ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %res = call <32 x i8> @llvm.umax.v32i8(<32 x i8> %op1, <32 x i8> %op2) - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @umax_v16i16(ptr %a) #0 { +define void @umax_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: umax_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI45_0 @@ -919,15 +917,15 @@ ; CHECK-NEXT: umax z0.h, p0/m, z0.h, z2.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %res = call <16 x i16> @llvm.umax.v16i16(<16 x i16> %op1, <16 x i16> %op2) - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @umax_v8i32(ptr %a) #0 { +define void @umax_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: umax_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI46_0 @@ -938,15 +936,15 @@ ; CHECK-NEXT: umax z0.s, p0/m, z0.s, z2.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %res = call <8 x i32> @llvm.umax.v8i32(<8 x i32> %op1, <8 x i32> %op2) - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @umax_v4i64(ptr %a) #0 { +define void @umax_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: umax_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI47_0 @@ -957,11 +955,11 @@ ; CHECK-NEXT: umax z0.d, p0/m, z0.d, z2.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %res = call <4 x i64> @llvm.umax.v4i64(<4 x i64> %op1, <4 x i64> %op2) - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } @@ -969,7 +967,7 @@ ; UMIN ; -define void @umin_v32i8(ptr %a) #0 { +define void @umin_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: umin_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI48_0 @@ -980,15 +978,15 @@ ; CHECK-NEXT: umin z0.b, p0/m, z0.b, z2.b ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %res = call <32 x i8> @llvm.umin.v32i8(<32 x i8> %op1, <32 x i8> %op2) - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @umin_v16i16(ptr %a) #0 { +define void @umin_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: umin_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI49_0 @@ -999,15 +997,15 @@ ; CHECK-NEXT: umin z0.h, p0/m, z0.h, z2.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %res = call <16 x i16> @llvm.umin.v16i16(<16 x i16> %op1, <16 x i16> %op2) - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @umin_v8i32(ptr %a) #0 { +define void @umin_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: umin_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI50_0 @@ -1018,15 +1016,15 @@ ; CHECK-NEXT: umin z0.s, p0/m, z0.s, z2.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %res = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %op1, <8 x i32> %op2) - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @umin_v4i64(ptr %a) #0 { +define void @umin_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: umin_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI51_0 @@ -1037,11 +1035,11 @@ ; CHECK-NEXT: umin z0.d, p0/m, z0.d, z2.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %res = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %op1, <4 x i64> %op2) - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } @@ -1049,7 +1047,7 @@ ; XOR ; -define void @xor_v32i8(ptr %a) #0 { +define void @xor_v32i8(<32 x i8>* %a) #0 { ; CHECK-LABEL: xor_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI52_0 @@ -1059,15 +1057,15 @@ ; CHECK-NEXT: eor z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a + %op1 = load <32 x i8>, <32 x i8>* %a %ins = insertelement <32 x i8> undef, i8 7, i64 0 %op2 = shufflevector <32 x i8> %ins, <32 x i8> undef, <32 x i32> zeroinitializer %res = xor <32 x i8> %op1, %op2 - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @xor_v16i16(ptr %a) #0 { +define void @xor_v16i16(<16 x i16>* %a) #0 { ; CHECK-LABEL: xor_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI53_0 @@ -1077,15 +1075,15 @@ ; CHECK-NEXT: eor z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a + %op1 = load <16 x i16>, <16 x i16>* %a %ins = insertelement <16 x i16> undef, i16 15, i64 0 %op2 = shufflevector <16 x i16> %ins, <16 x i16> undef, <16 x i32> zeroinitializer %res = xor <16 x i16> %op1, %op2 - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @xor_v8i32(ptr %a) #0 { +define void @xor_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: xor_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI54_0 @@ -1095,15 +1093,15 @@ ; CHECK-NEXT: eor z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %ins = insertelement <8 x i32> undef, i32 31, i64 0 %op2 = shufflevector <8 x i32> %ins, <8 x i32> undef, <8 x i32> zeroinitializer %res = xor <8 x i32> %op1, %op2 - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @xor_v4i64(ptr %a) #0 { +define void @xor_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: xor_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI55_0 @@ -1113,11 +1111,11 @@ ; CHECK-NEXT: eor z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %ins = insertelement <4 x i64> undef, i64 63, i64 0 %op2 = shufflevector <4 x i64> %ins, <4 x i64> undef, <4 x i32> zeroinitializer %res = xor <4 x i64> %op1, %op2 - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll @@ -350,38 +350,18 @@ ret void } -define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) #0 { -; CHECK-LABEL: select_v1i64: -; CHECK: // %bb.0: -; CHECK-NEXT: tst w0, #0x1 -; CHECK-NEXT: mov x9, #-1 -; CHECK-NEXT: csetm x8, ne -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: fmov d3, x9 -; CHECK-NEXT: fmov d2, x8 -; CHECK-NEXT: eor z3.d, z2.d, z3.d -; CHECK-NEXT: and z0.d, z0.d, z2.d -; CHECK-NEXT: and z1.d, z1.d, z3.d -; CHECK-NEXT: orr z0.d, z0.d, z1.d -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 -; CHECK-NEXT: ret - %sel = select i1 %mask, <1 x i64> %op1, <1 x i64> %op2 - ret <1 x i64> %sel -} - define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) #0 { ; CHECK-LABEL: select_v2i64: ; CHECK: // %bb.0: ; CHECK-NEXT: tst w0, #0x1 ; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 -; CHECK-NEXT: adrp x9, .LCPI12_0 +; CHECK-NEXT: adrp x9, .LCPI11_0 ; CHECK-NEXT: csetm x8, ne ; CHECK-NEXT: stp x8, x8, [sp, #-16]! ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: ldr q2, [sp] -; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI12_0] +; CHECK-NEXT: ldr q3, [x9, :lo12:.LCPI11_0] ; CHECK-NEXT: and z0.d, z0.d, z2.d ; CHECK-NEXT: eor z3.d, z2.d, z3.d ; CHECK-NEXT: and z1.d, z1.d, z3.d @@ -401,11 +381,11 @@ ; CHECK-NEXT: csetm x8, ne ; CHECK-NEXT: ldr q1, [x0, #16] ; CHECK-NEXT: ldr q2, [x1] -; CHECK-NEXT: adrp x9, .LCPI13_0 +; CHECK-NEXT: adrp x9, .LCPI12_0 ; CHECK-NEXT: ldr q3, [x1, #16] ; CHECK-NEXT: stp x8, x8, [sp, #-16]! ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI13_0] +; CHECK-NEXT: ldr q4, [x9, :lo12:.LCPI12_0] ; CHECK-NEXT: ldr q5, [sp] ; CHECK-NEXT: eor z4.d, z5.d, z4.d ; CHECK-NEXT: and z1.d, z1.d, z5.d diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll @@ -256,7 +256,7 @@ ; CHECK-LABEL: ucvtf_v2i32_v2f16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -269,7 +269,7 @@ ; CHECK-LABEL: ucvtf_v4i32_v4f16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 -; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -282,7 +282,7 @@ ; CHECK-LABEL: ucvtf_v8i32_v8f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ucvtf z1.h, p0/m, z1.s ; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s ; CHECK-NEXT: ptrue p0.h, vl4 @@ -300,7 +300,7 @@ ; CHECK-LABEL: ucvtf_v16i32_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] -; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: ptrue p1.h, vl4 ; CHECK-NEXT: ucvtf z0.h, p0/m, z0.s ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h @@ -452,7 +452,7 @@ ; CHECK-LABEL: ucvtf_v4i64_v4f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ucvtf z1.s, p0/m, z1.d ; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d @@ -474,7 +474,7 @@ ; CHECK-LABEL: ucvtf_v8i64_v8f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0, #32] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p1.s, vl2 ; CHECK-NEXT: ptrue p2.s ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d @@ -510,7 +510,7 @@ ; CHECK-LABEL: ucvtf_v2i64_v2f32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -523,7 +523,7 @@ ; CHECK-LABEL: ucvtf_v4i64_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ucvtf z1.s, p0/m, z1.d ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d ; CHECK-NEXT: ptrue p0.s, vl2 @@ -541,7 +541,7 @@ ; CHECK-LABEL: ucvtf_v8i64_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: ptrue p1.s, vl2 ; CHECK-NEXT: ucvtf z0.s, p0/m, z0.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s @@ -836,7 +836,7 @@ ; CHECK-LABEL: scvtf_v2i32_v2f16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: scvtf z0.h, p0/m, z0.s ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -849,7 +849,7 @@ ; CHECK-LABEL: scvtf_v4i32_v4f16: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 -; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: scvtf z0.h, p0/m, z0.s ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -862,7 +862,7 @@ ; CHECK-LABEL: scvtf_v8i32_v8f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ptrue p0.s ; CHECK-NEXT: scvtf z1.h, p0/m, z1.s ; CHECK-NEXT: scvtf z0.h, p0/m, z0.s ; CHECK-NEXT: ptrue p0.h, vl4 @@ -1049,7 +1049,7 @@ ; CHECK-LABEL: scvtf_v4i64_v4f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: scvtf z1.s, p0/m, z1.d ; CHECK-NEXT: uzp1 z1.s, z1.s, z1.s ; CHECK-NEXT: scvtf z0.s, p0/m, z0.d @@ -1075,7 +1075,7 @@ ; CHECK-LABEL: scvtf_v2i64_v2f32: ; CHECK: // %bb.0: ; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: scvtf z0.s, p0/m, z0.d ; CHECK-NEXT: uzp1 z0.s, z0.s, z0.s ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -1088,7 +1088,7 @@ ; CHECK-LABEL: scvtf_v4i64_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] -; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: scvtf z1.s, p0/m, z1.d ; CHECK-NEXT: scvtf z0.s, p0/m, z0.d ; CHECK-NEXT: ptrue p0.s, vl2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll @@ -72,7 +72,7 @@ ret <16 x i8> %sel } -define void @select_v32i8(ptr %a, ptr %b) #0 { +define void @select_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 { ; CHECK-LABEL: select_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x1] @@ -94,11 +94,11 @@ ; CHECK-NEXT: orr z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a - %op2 = load <32 x i8>, ptr %b + %op1 = load <32 x i8>, <32 x i8>* %a + %op2 = load <32 x i8>, <32 x i8>* %b %mask = icmp eq <32 x i8> %op1, %op2 %sel = select <32 x i1> %mask, <32 x i8> %op1, <32 x i8> %op2 - store <32 x i8> %sel, ptr %a + store <32 x i8> %sel, <32 x i8>* %a ret void } @@ -172,7 +172,7 @@ ret <8 x i16> %sel } -define void @select_v16i16(ptr %a, ptr %b) #0 { +define void @select_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { ; CHECK-LABEL: select_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x1] @@ -194,11 +194,11 @@ ; CHECK-NEXT: orr z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a - %op2 = load <16 x i16>, ptr %b + %op1 = load <16 x i16>, <16 x i16>* %a + %op2 = load <16 x i16>, <16 x i16>* %b %mask = icmp eq <16 x i16> %op1, %op2 %sel = select <16 x i1> %mask, <16 x i16> %op1, <16 x i16> %op2 - store <16 x i16> %sel, ptr %a + store <16 x i16> %sel, <16 x i16>* %a ret void } @@ -249,7 +249,7 @@ ret <4 x i32> %sel } -define void @select_v8i32(ptr %a, ptr %b) #0 { +define void @select_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { ; CHECK-LABEL: select_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x1] @@ -271,11 +271,11 @@ ; CHECK-NEXT: orr z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a - %op2 = load <8 x i32>, ptr %b + %op1 = load <8 x i32>, <8 x i32>* %a + %op2 = load <8 x i32>, <8 x i32>* %b %mask = icmp eq <8 x i32> %op1, %op2 %sel = select <8 x i1> %mask, <8 x i32> %op1, <8 x i32> %op2 - store <8 x i32> %sel, ptr %a + store <8 x i32> %sel, <8 x i32>* %a ret void } @@ -323,7 +323,7 @@ ret <2 x i64> %sel } -define void @select_v4i64(ptr %a, ptr %b) #0 { +define void @select_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 { ; CHECK-LABEL: select_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x1] @@ -345,11 +345,11 @@ ; CHECK-NEXT: orr z0.d, z2.d, z0.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a - %op2 = load <4 x i64>, ptr %b + %op1 = load <4 x i64>, <4 x i64>* %a + %op2 = load <4 x i64>, <4 x i64>* %b %mask = icmp eq <4 x i64> %op1, %op2 %sel = select <4 x i1> %mask, <4 x i64> %op1, <4 x i64> %op2 - store <4 x i64> %sel, ptr %a + store <4 x i64> %sel, <4 x i64>* %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll @@ -5,131 +5,19 @@ declare void @def(ptr) -define void @alloc_v4i8(ptr %st_ptr) #0 { -; CHECK-LABEL: alloc_v4i8: -; CHECK: // %bb.0: -; CHECK-NEXT: sub sp, sp, #32 -; CHECK-NEXT: stp x30, x19, [sp, #16] // 16-byte Folded Spill -; CHECK-NEXT: mov x19, x0 -; CHECK-NEXT: add x0, sp, #12 -; CHECK-NEXT: bl def -; CHECK-NEXT: add x8, sp, #12 -; CHECK-NEXT: ptrue p0.b, vl2 -; CHECK-NEXT: ld2b { z0.b, z1.b }, p0/z, [x8] -; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: mov z2.b, z0.b[1] -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov w9, s2 -; CHECK-NEXT: stp w8, w9, [sp] -; CHECK-NEXT: ldr d0, [sp] -; CHECK-NEXT: st1b { z0.s }, p0, [x19] -; CHECK-NEXT: ldp x30, x19, [sp, #16] // 16-byte Folded Reload -; CHECK-NEXT: add sp, sp, #32 -; CHECK-NEXT: ret - %alloc = alloca [4 x i8] - call void @def(ptr %alloc) - %load = load <4 x i8>, ptr %alloc - %strided.vec = shufflevector <4 x i8> %load, <4 x i8> poison, <2 x i32> - store <2 x i8> %strided.vec, ptr %st_ptr - ret void -} - -define void @alloc_v6i8(ptr %st_ptr) #0 { -; CHECK-LABEL: alloc_v6i8: -; CHECK: // %bb.0: -; CHECK-NEXT: sub sp, sp, #48 -; CHECK-NEXT: stp x30, x19, [sp, #32] // 16-byte Folded Spill -; CHECK-NEXT: mov x19, x0 -; CHECK-NEXT: add x0, sp, #24 -; CHECK-NEXT: bl def -; CHECK-NEXT: add x8, sp, #24 -; CHECK-NEXT: ptrue p0.b, vl3 -; CHECK-NEXT: ld2b { z0.b, z1.b }, p0/z, [x8] -; CHECK-NEXT: ptrue p0.h, vl4 -; CHECK-NEXT: fmov w8, s1 -; CHECK-NEXT: mov z2.b, z1.b[3] -; CHECK-NEXT: mov z3.b, z1.b[2] -; CHECK-NEXT: mov z0.b, z1.b[1] -; CHECK-NEXT: fmov w9, s2 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: strh w8, [sp, #8] -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: strh w9, [sp, #14] -; CHECK-NEXT: strh w10, [sp, #12] -; CHECK-NEXT: strh w8, [sp, #10] -; CHECK-NEXT: add x8, sp, #20 -; CHECK-NEXT: ldr d0, [sp, #8] -; CHECK-NEXT: st1b { z0.h }, p0, [x8] -; CHECK-NEXT: ldrh w8, [sp, #20] -; CHECK-NEXT: strb w10, [x19, #2] -; CHECK-NEXT: strh w8, [x19] -; CHECK-NEXT: ldp x30, x19, [sp, #32] // 16-byte Folded Reload -; CHECK-NEXT: add sp, sp, #48 -; CHECK-NEXT: ret - %alloc = alloca [6 x i8] - call void @def(ptr %alloc) - %load = load <6 x i8>, ptr %alloc - %strided.vec = shufflevector <6 x i8> %load, <6 x i8> poison, <3 x i32> - store <3 x i8> %strided.vec, ptr %st_ptr - ret void -} - -define void @alloc_v32i8(ptr %st_ptr) #0 { -; CHECK-LABEL: alloc_v32i8: -; CHECK: // %bb.0: -; CHECK-NEXT: sub sp, sp, #64 -; CHECK-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill -; CHECK-NEXT: mov x19, x0 -; CHECK-NEXT: add x0, sp, #16 -; CHECK-NEXT: bl def -; CHECK-NEXT: ldp q0, q1, [sp, #16] -; CHECK-NEXT: mov z2.b, z0.b[14] -; CHECK-NEXT: mov z3.b, z0.b[12] -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: fmov w9, s2 -; CHECK-NEXT: fmov w10, s3 -; CHECK-NEXT: mov z4.b, z0.b[10] -; CHECK-NEXT: mov z5.b, z0.b[8] -; CHECK-NEXT: mov z6.b, z0.b[6] -; CHECK-NEXT: strb w8, [sp] -; CHECK-NEXT: fmov w8, s4 -; CHECK-NEXT: strb w9, [sp, #7] -; CHECK-NEXT: fmov w9, s5 -; CHECK-NEXT: strb w10, [sp, #6] -; CHECK-NEXT: fmov w10, s6 -; CHECK-NEXT: mov z7.b, z0.b[4] -; CHECK-NEXT: mov z0.b, z0.b[2] -; CHECK-NEXT: strb w8, [sp, #5] -; CHECK-NEXT: fmov w8, s7 -; CHECK-NEXT: strb w9, [sp, #4] -; CHECK-NEXT: fmov w9, s0 -; CHECK-NEXT: strb w10, [sp, #3] -; CHECK-NEXT: fmov w10, s1 -; CHECK-NEXT: strb w8, [sp, #2] -; CHECK-NEXT: strb w9, [sp, #1] -; CHECK-NEXT: strb w10, [x19, #8] -; CHECK-NEXT: ldr q0, [sp] -; CHECK-NEXT: fmov x8, d0 -; CHECK-NEXT: str x8, [x19] -; CHECK-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload -; CHECK-NEXT: add sp, sp, #64 -; CHECK-NEXT: ret - %alloc = alloca [32 x i8] - call void @def(ptr %alloc) - %load = load <32 x i8>, ptr %alloc - %strided.vec = shufflevector <32 x i8> %load, <32 x i8> poison, <9 x i32> - store <9 x i8> %strided.vec, ptr %st_ptr - ret void -} - - -define void @alloc_v8f64(ptr %st_ptr) #0 { -; CHECK-LABEL: alloc_v8f64: +define void @st1d_fixed(ptr %st_ptr) #0 { +; CHECK-LABEL: st1d_fixed: ; CHECK: // %bb.0: ; CHECK-NEXT: str x29, [sp, #-32]! // 8-byte Folded Spill +; CHECK-NEXT: .cfi_def_cfa_offset 32 ; CHECK-NEXT: stp x30, x19, [sp, #16] // 16-byte Folded Spill +; CHECK-NEXT: .cfi_offset w19, -8 +; CHECK-NEXT: .cfi_offset w30, -16 +; CHECK-NEXT: .cfi_offset w29, -32 ; CHECK-NEXT: addvl sp, sp, #-1 -; CHECK-NEXT: sub sp, sp, #64 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x20, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 32 + 8 * VG +; CHECK-NEXT: sub sp, sp, #128 +; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0xa0, 0x01, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 160 + 8 * VG ; CHECK-NEXT: mov x19, x0 ; CHECK-NEXT: mov x0, sp ; CHECK-NEXT: bl def @@ -140,19 +28,19 @@ ; CHECK-NEXT: mov w9, #2 ; CHECK-NEXT: cmp x8, #2 ; CHECK-NEXT: csel x8, x8, x9, lo -; CHECK-NEXT: add x10, sp, #64 +; CHECK-NEXT: add x10, sp, #128 ; CHECK-NEXT: lsl x8, x8, #3 ; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: add x9, sp, #64 +; CHECK-NEXT: add x9, sp, #128 ; CHECK-NEXT: st1d { z0.d }, p0, [x10] ; CHECK-NEXT: ldr q2, [x9, x8] ; CHECK-NEXT: stp q0, q2, [x19] ; CHECK-NEXT: addvl sp, sp, #1 -; CHECK-NEXT: add sp, sp, #64 +; CHECK-NEXT: add sp, sp, #128 ; CHECK-NEXT: ldp x30, x19, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldr x29, [sp], #32 // 8-byte Folded Reload ; CHECK-NEXT: ret - %alloc = alloca [8 x double] + %alloc = alloca [16 x double] call void @def(ptr %alloc) %load = load <8 x double>, ptr %alloc %strided.vec = shufflevector <8 x double> %load, <8 x double> poison, <4 x i32> @@ -160,4 +48,4 @@ ret void } -attributes #0 = { "target-features"="+sve" nounwind} +attributes #0 = { "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll @@ -3,7 +3,7 @@ target triple = "aarch64-unknown-linux-gnu" -define <4 x i32> @test(ptr %arg1, ptr %arg2) { +define <4 x i32> @test(<16 x i32>* %arg1, <16 x i32>* %arg2) { ; CHECK-LABEL: test: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: ldp q2, q1, [x0, #32] @@ -18,15 +18,15 @@ ; CHECK-NEXT: stp q2, q1, [x0] ; CHECK-NEXT: ret entry: - %0 = load <16 x i32>, ptr %arg1, align 256 - %1 = load <16 x i32>, ptr %arg2, align 256 + %0 = load <16 x i32>, <16 x i32>* %arg1, align 256 + %1 = load <16 x i32>, <16 x i32>* %arg2, align 256 %shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <4 x i32> %2 = add <16 x i32> %0, %0 - store <16 x i32> %2, ptr %arg1, align 256 + store <16 x i32> %2, <16 x i32>* %arg1, align 256 ret <4 x i32> %shvec } -define <2 x i32> @test2(ptr %arg1, ptr %arg2) { +define <2 x i32> @test2(<16 x i32>* %arg1, <16 x i32>* %arg2) { ; CHECK-LABEL: test2: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: ldp q2, q0, [x0, #32] @@ -43,10 +43,10 @@ ; CHECK-NEXT: stp q1, q2, [x0] ; CHECK-NEXT: ret entry: - %0 = load <16 x i32>, ptr %arg1, align 256 - %1 = load <16 x i32>, ptr %arg2, align 256 + %0 = load <16 x i32>, <16 x i32>* %arg1, align 256 + %1 = load <16 x i32>, <16 x i32>* %arg2, align 256 %shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <2 x i32> %2 = add <16 x i32> %0, %0 - store <16 x i32> %2, ptr %arg1, align 256 + store <16 x i32> %2, <16 x i32>* %arg1, align 256 ret <2 x i32> %shvec } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll @@ -3,7 +3,7 @@ target triple = "aarch64-unknown-linux-gnu" -define void @add_v4i8(ptr %a, ptr %b) #0 { +define void @add_v4i8(<4 x i8>* %a, <4 x i8>* %b) #0 { ; CHECK-LABEL: add_v4i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr s0, [x0] @@ -14,14 +14,14 @@ ; CHECK-NEXT: add z0.h, z0.h, z1.h ; CHECK-NEXT: st1b { z0.h }, p0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i8>, ptr %a - %op2 = load <4 x i8>, ptr %b + %op1 = load <4 x i8>, <4 x i8>* %a + %op2 = load <4 x i8>, <4 x i8>* %b %res = add <4 x i8> %op1, %op2 - store <4 x i8> %res, ptr %a + store <4 x i8> %res, <4 x i8>* %a ret void } -define void @add_v8i8(ptr %a, ptr %b) #0 { +define void @add_v8i8(<8 x i8>* %a, <8 x i8>* %b) #0 { ; CHECK-LABEL: add_v8i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -29,14 +29,14 @@ ; CHECK-NEXT: add z0.b, z0.b, z1.b ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i8>, ptr %a - %op2 = load <8 x i8>, ptr %b + %op1 = load <8 x i8>, <8 x i8>* %a + %op2 = load <8 x i8>, <8 x i8>* %b %res = add <8 x i8> %op1, %op2 - store <8 x i8> %res, ptr %a + store <8 x i8> %res, <8 x i8>* %a ret void } -define void @add_v16i8(ptr %a, ptr %b) #0 { +define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b) #0 { ; CHECK-LABEL: add_v16i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -44,14 +44,14 @@ ; CHECK-NEXT: add z0.b, z0.b, z1.b ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i8>, ptr %a - %op2 = load <16 x i8>, ptr %b + %op1 = load <16 x i8>, <16 x i8>* %a + %op2 = load <16 x i8>, <16 x i8>* %b %res = add <16 x i8> %op1, %op2 - store <16 x i8> %res, ptr %a + store <16 x i8> %res, <16 x i8>* %a ret void } -define void @add_v32i8(ptr %a, ptr %b) #0 { +define void @add_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 { ; CHECK-LABEL: add_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -60,14 +60,14 @@ ; CHECK-NEXT: add z1.b, z1.b, z3.b ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a - %op2 = load <32 x i8>, ptr %b + %op1 = load <32 x i8>, <32 x i8>* %a + %op2 = load <32 x i8>, <32 x i8>* %b %res = add <32 x i8> %op1, %op2 - store <32 x i8> %res, ptr %a + store <32 x i8> %res, <32 x i8>* %a ret void } -define void @add_v2i16(ptr %a, ptr %b, ptr %c) #0 { +define void @add_v2i16(<2 x i16>* %a, <2 x i16>* %b, <2 x i16>* %c) #0 { ; CHECK-LABEL: add_v2i16: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 @@ -86,14 +86,14 @@ ; CHECK-NEXT: st1h { z0.s }, p0, [x0] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %op1 = load <2 x i16>, ptr %a - %op2 = load <2 x i16>, ptr %b + %op1 = load <2 x i16>, <2 x i16>* %a + %op2 = load <2 x i16>, <2 x i16>* %b %res = add <2 x i16> %op1, %op2 - store <2 x i16> %res, ptr %a + store <2 x i16> %res, <2 x i16>* %a ret void } -define void @add_v4i16(ptr %a, ptr %b, ptr %c) #0 { +define void @add_v4i16(<4 x i16>* %a, <4 x i16>* %b, <4 x i16>* %c) #0 { ; CHECK-LABEL: add_v4i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -101,14 +101,14 @@ ; CHECK-NEXT: add z0.h, z0.h, z1.h ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i16>, ptr %a - %op2 = load <4 x i16>, ptr %b + %op1 = load <4 x i16>, <4 x i16>* %a + %op2 = load <4 x i16>, <4 x i16>* %b %res = add <4 x i16> %op1, %op2 - store <4 x i16> %res, ptr %a + store <4 x i16> %res, <4 x i16>* %a ret void } -define void @add_v8i16(ptr %a, ptr %b, ptr %c) #0 { +define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) #0 { ; CHECK-LABEL: add_v8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -116,14 +116,14 @@ ; CHECK-NEXT: add z0.h, z0.h, z1.h ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i16>, ptr %a - %op2 = load <8 x i16>, ptr %b + %op1 = load <8 x i16>, <8 x i16>* %a + %op2 = load <8 x i16>, <8 x i16>* %b %res = add <8 x i16> %op1, %op2 - store <8 x i16> %res, ptr %a + store <8 x i16> %res, <8 x i16>* %a ret void } -define void @add_v16i16(ptr %a, ptr %b, ptr %c) #0 { +define void @add_v16i16(<16 x i16>* %a, <16 x i16>* %b, <16 x i16>* %c) #0 { ; CHECK-LABEL: add_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -132,14 +132,14 @@ ; CHECK-NEXT: add z1.h, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a - %op2 = load <16 x i16>, ptr %b + %op1 = load <16 x i16>, <16 x i16>* %a + %op2 = load <16 x i16>, <16 x i16>* %b %res = add <16 x i16> %op1, %op2 - store <16 x i16> %res, ptr %a + store <16 x i16> %res, <16 x i16>* %a ret void } -define void @abs_v2i32(ptr %a) #0 { +define void @abs_v2i32(<2 x i32>* %a) #0 { ; CHECK-LABEL: abs_v2i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -147,13 +147,13 @@ ; CHECK-NEXT: abs z0.s, p0/m, z0.s ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret - %op1 = load <2 x i32>, ptr %a + %op1 = load <2 x i32>, <2 x i32>* %a %res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %op1, i1 false) - store <2 x i32> %res, ptr %a + store <2 x i32> %res, <2 x i32>* %a ret void } -define void @abs_v4i32(ptr %a) #0 { +define void @abs_v4i32(<4 x i32>* %a) #0 { ; CHECK-LABEL: abs_v4i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -161,13 +161,13 @@ ; CHECK-NEXT: abs z0.s, p0/m, z0.s ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i32>, ptr %a + %op1 = load <4 x i32>, <4 x i32>* %a %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %op1, i1 false) - store <4 x i32> %res, ptr %a + store <4 x i32> %res, <4 x i32>* %a ret void } -define void @abs_v8i32(ptr %a) #0 { +define void @abs_v8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: abs_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -176,13 +176,13 @@ ; CHECK-NEXT: abs z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a + %op1 = load <8 x i32>, <8 x i32>* %a %res = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %op1, i1 false) - store <8 x i32> %res, ptr %a + store <8 x i32> %res, <8 x i32>* %a ret void } -define void @abs_v2i64(ptr %a) #0 { +define void @abs_v2i64(<2 x i64>* %a) #0 { ; CHECK-LABEL: abs_v2i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -190,13 +190,13 @@ ; CHECK-NEXT: abs z0.d, p0/m, z0.d ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %op1 = load <2 x i64>, ptr %a + %op1 = load <2 x i64>, <2 x i64>* %a %res = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %op1, i1 false) - store <2 x i64> %res, ptr %a + store <2 x i64> %res, <2 x i64>* %a ret void } -define void @abs_v4i64(ptr %a) #0 { +define void @abs_v4i64(<4 x i64>* %a) #0 { ; CHECK-LABEL: abs_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -205,13 +205,13 @@ ; CHECK-NEXT: abs z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a + %op1 = load <4 x i64>, <4 x i64>* %a %res = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %op1, i1 false) - store <4 x i64> %res, ptr %a + store <4 x i64> %res, <4 x i64>* %a ret void } -define void @fadd_v2f16(ptr %a, ptr %b) #0 { +define void @fadd_v2f16(<2 x half>* %a, <2 x half>* %b) #0 { ; CHECK-LABEL: fadd_v2f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr s0, [x0] @@ -221,14 +221,14 @@ ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: str w8, [x0] ; CHECK-NEXT: ret - %op1 = load <2 x half>, ptr %a - %op2 = load <2 x half>, ptr %b + %op1 = load <2 x half>, <2 x half>* %a + %op2 = load <2 x half>, <2 x half>* %b %res = fadd <2 x half> %op1, %op2 - store <2 x half> %res, ptr %a + store <2 x half> %res, <2 x half>* %a ret void } -define void @fadd_v4f16(ptr %a, ptr %b) #0 { +define void @fadd_v4f16(<4 x half>* %a, <4 x half>* %b) #0 { ; CHECK-LABEL: fadd_v4f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -237,14 +237,14 @@ ; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x half>, ptr %a - %op2 = load <4 x half>, ptr %b + %op1 = load <4 x half>, <4 x half>* %a + %op2 = load <4 x half>, <4 x half>* %b %res = fadd <4 x half> %op1, %op2 - store <4 x half> %res, ptr %a + store <4 x half> %res, <4 x half>* %a ret void } -define void @fadd_v8f16(ptr %a, ptr %b) #0 { +define void @fadd_v8f16(<8 x half>* %a, <8 x half>* %b) #0 { ; CHECK-LABEL: fadd_v8f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -253,14 +253,14 @@ ; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x half>, ptr %a - %op2 = load <8 x half>, ptr %b + %op1 = load <8 x half>, <8 x half>* %a + %op2 = load <8 x half>, <8 x half>* %b %res = fadd <8 x half> %op1, %op2 - store <8 x half> %res, ptr %a + store <8 x half> %res, <8 x half>* %a ret void } -define void @fadd_v16f16(ptr %a, ptr %b) #0 { +define void @fadd_v16f16(<16 x half>* %a, <16 x half>* %b) #0 { ; CHECK-LABEL: fadd_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -270,14 +270,14 @@ ; CHECK-NEXT: fadd z1.h, p0/m, z1.h, z3.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, ptr %a - %op2 = load <16 x half>, ptr %b + %op1 = load <16 x half>, <16 x half>* %a + %op2 = load <16 x half>, <16 x half>* %b %res = fadd <16 x half> %op1, %op2 - store <16 x half> %res, ptr %a + store <16 x half> %res, <16 x half>* %a ret void } -define void @fadd_v2f32(ptr %a, ptr %b) #0 { +define void @fadd_v2f32(<2 x float>* %a, <2 x float>* %b) #0 { ; CHECK-LABEL: fadd_v2f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr d0, [x0] @@ -286,14 +286,14 @@ ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: str d0, [x0] ; CHECK-NEXT: ret - %op1 = load <2 x float>, ptr %a - %op2 = load <2 x float>, ptr %b + %op1 = load <2 x float>, <2 x float>* %a + %op2 = load <2 x float>, <2 x float>* %b %res = fadd <2 x float> %op1, %op2 - store <2 x float> %res, ptr %a + store <2 x float> %res, <2 x float>* %a ret void } -define void @fadd_v4f32(ptr %a, ptr %b) #0 { +define void @fadd_v4f32(<4 x float>* %a, <4 x float>* %b) #0 { ; CHECK-LABEL: fadd_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -302,14 +302,14 @@ ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x float>, ptr %a - %op2 = load <4 x float>, ptr %b + %op1 = load <4 x float>, <4 x float>* %a + %op2 = load <4 x float>, <4 x float>* %b %res = fadd <4 x float> %op1, %op2 - store <4 x float> %res, ptr %a + store <4 x float> %res, <4 x float>* %a ret void } -define void @fadd_v8f32(ptr %a, ptr %b) #0 { +define void @fadd_v8f32(<8 x float>* %a, <8 x float>* %b) #0 { ; CHECK-LABEL: fadd_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -319,14 +319,14 @@ ; CHECK-NEXT: fadd z1.s, p0/m, z1.s, z3.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, ptr %a - %op2 = load <8 x float>, ptr %b + %op1 = load <8 x float>, <8 x float>* %a + %op2 = load <8 x float>, <8 x float>* %b %res = fadd <8 x float> %op1, %op2 - store <8 x float> %res, ptr %a + store <8 x float> %res, <8 x float>* %a ret void } -define void @fadd_v2f64(ptr %a, ptr %b) #0 { +define void @fadd_v2f64(<2 x double>* %a, <2 x double>* %b) #0 { ; CHECK-LABEL: fadd_v2f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -335,14 +335,14 @@ ; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %op1 = load <2 x double>, ptr %a - %op2 = load <2 x double>, ptr %b + %op1 = load <2 x double>, <2 x double>* %a + %op2 = load <2 x double>, <2 x double>* %b %res = fadd <2 x double> %op1, %op2 - store <2 x double> %res, ptr %a + store <2 x double> %res, <2 x double>* %a ret void } -define void @fadd_v4f64(ptr %a, ptr %b) #0 { +define void @fadd_v4f64(<4 x double>* %a, <4 x double>* %b) #0 { ; CHECK-LABEL: fadd_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -352,10 +352,10 @@ ; CHECK-NEXT: fadd z1.d, p0/m, z1.d, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, ptr %a - %op2 = load <4 x double>, ptr %b + %op1 = load <4 x double>, <4 x double>* %a + %op2 = load <4 x double>, <4 x double>* %b %res = fadd <4 x double> %op1, %op2 - store <4 x double> %res, ptr %a + store <4 x double> %res, <4 x double>* %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll @@ -4,7 +4,7 @@ target triple = "aarch64-unknown-linux-gnu" ; REVB pattern for shuffle v32i8 -> v16i16 -define void @test_revbv16i16(ptr %a) #0 { +define void @test_revbv16i16(<32 x i8>* %a) #0 { ; CHECK-LABEL: test_revbv16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -13,14 +13,14 @@ ; CHECK-NEXT: revb z1.h, p0/m, z1.h ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %tmp1 = load <32 x i8>, ptr %a + %tmp1 = load <32 x i8>, <32 x i8>* %a %tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> - store <32 x i8> %tmp2, ptr %a + store <32 x i8> %tmp2, <32 x i8>* %a ret void } ; REVB pattern for shuffle v32i8 -> v8i32 -define void @test_revbv8i32(ptr %a) #0 { +define void @test_revbv8i32(<32 x i8>* %a) #0 { ; CHECK-LABEL: test_revbv8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -29,14 +29,14 @@ ; CHECK-NEXT: revb z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %tmp1 = load <32 x i8>, ptr %a + %tmp1 = load <32 x i8>, <32 x i8>* %a %tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> - store <32 x i8> %tmp2, ptr %a + store <32 x i8> %tmp2, <32 x i8>* %a ret void } ; REVB pattern for shuffle v32i8 -> v4i64 -define void @test_revbv4i64(ptr %a) #0 { +define void @test_revbv4i64(<32 x i8>* %a) #0 { ; CHECK-LABEL: test_revbv4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -45,14 +45,14 @@ ; CHECK-NEXT: revb z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %tmp1 = load <32 x i8>, ptr %a + %tmp1 = load <32 x i8>, <32 x i8>* %a %tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> - store <32 x i8> %tmp2, ptr %a + store <32 x i8> %tmp2, <32 x i8>* %a ret void } ; REVH pattern for shuffle v16i16 -> v8i32 -define void @test_revhv8i32(ptr %a) #0 { +define void @test_revhv8i32(<16 x i16>* %a) #0 { ; CHECK-LABEL: test_revhv8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -61,14 +61,14 @@ ; CHECK-NEXT: revh z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %tmp1 = load <16 x i16>, ptr %a + %tmp1 = load <16 x i16>, <16 x i16>* %a %tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> - store <16 x i16> %tmp2, ptr %a + store <16 x i16> %tmp2, <16 x i16>* %a ret void } ; REVH pattern for shuffle v16f16 -> v8f32 -define void @test_revhv8f32(ptr %a) #0 { +define void @test_revhv8f32(<16 x half>* %a) #0 { ; CHECK-LABEL: test_revhv8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -77,14 +77,14 @@ ; CHECK-NEXT: revh z1.s, p0/m, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %tmp1 = load <16 x half>, ptr %a + %tmp1 = load <16 x half>, <16 x half>* %a %tmp2 = shufflevector <16 x half> %tmp1, <16 x half> undef, <16 x i32> - store <16 x half> %tmp2, ptr %a + store <16 x half> %tmp2, <16 x half>* %a ret void } ; REVH pattern for shuffle v16i16 -> v4i64 -define void @test_revhv4i64(ptr %a) #0 { +define void @test_revhv4i64(<16 x i16>* %a) #0 { ; CHECK-LABEL: test_revhv4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -93,14 +93,14 @@ ; CHECK-NEXT: revh z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %tmp1 = load <16 x i16>, ptr %a + %tmp1 = load <16 x i16>, <16 x i16>* %a %tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> - store <16 x i16> %tmp2, ptr %a + store <16 x i16> %tmp2, <16 x i16>* %a ret void } ; REVW pattern for shuffle v8i32 -> v4i64 -define void @test_revwv4i64(ptr %a) #0 { +define void @test_revwv4i64(<8 x i32>* %a) #0 { ; CHECK-LABEL: test_revwv4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -109,14 +109,14 @@ ; CHECK-NEXT: revw z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x i32>, ptr %a + %tmp1 = load <8 x i32>, <8 x i32>* %a %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> - store <8 x i32> %tmp2, ptr %a + store <8 x i32> %tmp2, <8 x i32>* %a ret void } ; REVW pattern for shuffle v8f32 -> v4f64 -define void @test_revwv4f64(ptr %a) #0 { +define void @test_revwv4f64(<8 x float>* %a) #0 { ; CHECK-LABEL: test_revwv4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -125,13 +125,14 @@ ; CHECK-NEXT: revw z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x float>, ptr %a + %tmp1 = load <8 x float>, <8 x float>* %a %tmp2 = shufflevector <8 x float> %tmp1, <8 x float> undef, <8 x i32> - store <8 x float> %tmp2, ptr %a + store <8 x float> %tmp2, <8 x float>* %a ret void } -define <16 x i8> @test_revv16i8(ptr %a) #0 { +; Don't use SVE for 128-bit vectors +define <16 x i8> @test_revv16i8(<16 x i8>* %a) #0 { ; CHECK-LABEL: test_revv16i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -139,13 +140,13 @@ ; CHECK-NEXT: revb z0.d, p0/m, z0.d ; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret - %tmp1 = load <16 x i8>, ptr %a + %tmp1 = load <16 x i8>, <16 x i8>* %a %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> ret <16 x i8> %tmp2 } ; REVW pattern for shuffle two v8i32 inputs with the second input available. -define void @test_revwv8i32v8i32(ptr %a, ptr %b) #0 { +define void @test_revwv8i32v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { ; CHECK-LABEL: test_revwv8i32v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x1] @@ -154,14 +155,15 @@ ; CHECK-NEXT: revw z1.d, p0/m, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x i32>, ptr %a - %tmp2 = load <8 x i32>, ptr %b + %tmp1 = load <8 x i32>, <8 x i32>* %a + %tmp2 = load <8 x i32>, <8 x i32>* %b %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> - store <8 x i32> %tmp3, ptr %a + store <8 x i32> %tmp3, <8 x i32>* %a ret void } -define void @test_revhv32i16(ptr %a) #0 { +; REVH pattern for shuffle v32i16 with 256 bits and 512 bits SVE. +define void @test_revhv32i16(<32 x i16>* %a) #0 { ; CHECK-LABEL: test_revhv32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0, #32] @@ -174,13 +176,14 @@ ; CHECK-NEXT: revh z1.d, p0/m, z3.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %tmp1 = load <32 x i16>, ptr %a + %tmp1 = load <32 x i16>, <32 x i16>* %a %tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <32 x i32> - store <32 x i16> %tmp2, ptr %a + store <32 x i16> %tmp2, <32 x i16>* %a ret void } -define void @test_rev_elts_fail(ptr %a) #0 { +; Only support to reverse bytes / halfwords / words within elements +define void @test_rev_elts_fail(<4 x i64>* %a) #0 { ; CHECK-LABEL: test_rev_elts_fail: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] @@ -197,13 +200,17 @@ ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret - %tmp1 = load <4 x i64>, ptr %a + %tmp1 = load <4 x i64>, <4 x i64>* %a %tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> - store <4 x i64> %tmp2, ptr %a + store <4 x i64> %tmp2, <4 x i64>* %a ret void } -define void @test_revv8i32(ptr %a) #0 { +; REV instruction will reverse the order of all elements in the vector. +; When the vector length and the target register size are inconsistent, +; the correctness of generated REV instruction for shuffle pattern cannot be guaranteed. + +define void @test_revv8i32(<8 x i32>* %a) #0 { ; CHECK-LABEL: test_revv8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #32 @@ -231,9 +238,339 @@ ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret - %tmp1 = load <8 x i32>, ptr %a + %tmp1 = load <8 x i32>, <8 x i32>* %a %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> - store <8 x i32> %tmp2, ptr %a + store <8 x i32> %tmp2, <8 x i32>* %a + ret void +} + +define void @test_revv32i8_vl256(<32 x i8>* %a) #0 { +; CHECK-LABEL: test_revv32i8_vl256: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: mov z2.b, z1.b[1] +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: mov z3.b, z1.b[2] +; CHECK-NEXT: mov z4.b, z1.b[3] +; CHECK-NEXT: mov z5.b, z1.b[4] +; CHECK-NEXT: fmov w10, s3 +; CHECK-NEXT: strb w8, [sp, #31] +; CHECK-NEXT: fmov w8, s4 +; CHECK-NEXT: strb w9, [sp, #30] +; CHECK-NEXT: fmov w9, s5 +; CHECK-NEXT: mov z6.b, z1.b[5] +; CHECK-NEXT: mov z7.b, z1.b[6] +; CHECK-NEXT: mov z16.b, z1.b[7] +; CHECK-NEXT: strb w10, [sp, #29] +; CHECK-NEXT: fmov w10, s6 +; CHECK-NEXT: strb w8, [sp, #28] +; CHECK-NEXT: fmov w8, s7 +; CHECK-NEXT: strb w9, [sp, #27] +; CHECK-NEXT: fmov w9, s16 +; CHECK-NEXT: mov z17.b, z1.b[8] +; CHECK-NEXT: mov z18.b, z1.b[9] +; CHECK-NEXT: mov z19.b, z1.b[10] +; CHECK-NEXT: strb w10, [sp, #26] +; CHECK-NEXT: fmov w10, s17 +; CHECK-NEXT: strb w8, [sp, #25] +; CHECK-NEXT: fmov w8, s18 +; CHECK-NEXT: strb w9, [sp, #24] +; CHECK-NEXT: fmov w9, s19 +; CHECK-NEXT: mov z20.b, z1.b[11] +; CHECK-NEXT: mov z21.b, z1.b[12] +; CHECK-NEXT: mov z2.b, z1.b[13] +; CHECK-NEXT: strb w10, [sp, #23] +; CHECK-NEXT: fmov w10, s20 +; CHECK-NEXT: strb w8, [sp, #22] +; CHECK-NEXT: fmov w8, s21 +; CHECK-NEXT: strb w9, [sp, #21] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: mov z2.b, z1.b[14] +; CHECK-NEXT: mov z1.b, z1.b[15] +; CHECK-NEXT: strb w10, [sp, #20] +; CHECK-NEXT: fmov w10, s0 +; CHECK-NEXT: strb w8, [sp, #19] +; CHECK-NEXT: fmov w8, s2 +; CHECK-NEXT: strb w9, [sp, #18] +; CHECK-NEXT: fmov w9, s1 +; CHECK-NEXT: mov z1.b, z0.b[1] +; CHECK-NEXT: mov z2.b, z0.b[2] +; CHECK-NEXT: mov z3.b, z0.b[3] +; CHECK-NEXT: strb w8, [sp, #17] +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: strb w9, [sp, #16] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: strb w10, [sp, #15] +; CHECK-NEXT: fmov w10, s3 +; CHECK-NEXT: mov z4.b, z0.b[4] +; CHECK-NEXT: mov z5.b, z0.b[5] +; CHECK-NEXT: mov z6.b, z0.b[6] +; CHECK-NEXT: strb w8, [sp, #14] +; CHECK-NEXT: fmov w8, s4 +; CHECK-NEXT: strb w9, [sp, #13] +; CHECK-NEXT: fmov w9, s5 +; CHECK-NEXT: strb w10, [sp, #12] +; CHECK-NEXT: fmov w10, s6 +; CHECK-NEXT: mov z7.b, z0.b[7] +; CHECK-NEXT: mov z16.b, z0.b[8] +; CHECK-NEXT: mov z17.b, z0.b[9] +; CHECK-NEXT: strb w8, [sp, #11] +; CHECK-NEXT: fmov w8, s7 +; CHECK-NEXT: strb w9, [sp, #10] +; CHECK-NEXT: fmov w9, s16 +; CHECK-NEXT: strb w10, [sp, #9] +; CHECK-NEXT: fmov w10, s17 +; CHECK-NEXT: mov z18.b, z0.b[10] +; CHECK-NEXT: mov z19.b, z0.b[11] +; CHECK-NEXT: mov z20.b, z0.b[12] +; CHECK-NEXT: strb w8, [sp, #8] +; CHECK-NEXT: fmov w8, s18 +; CHECK-NEXT: strb w9, [sp, #7] +; CHECK-NEXT: fmov w9, s19 +; CHECK-NEXT: strb w10, [sp, #6] +; CHECK-NEXT: fmov w10, s20 +; CHECK-NEXT: mov z21.b, z0.b[13] +; CHECK-NEXT: mov z22.b, z0.b[14] +; CHECK-NEXT: mov z23.b, z0.b[15] +; CHECK-NEXT: strb w8, [sp, #5] +; CHECK-NEXT: fmov w8, s21 +; CHECK-NEXT: strb w9, [sp, #4] +; CHECK-NEXT: fmov w9, s22 +; CHECK-NEXT: strb w10, [sp, #3] +; CHECK-NEXT: fmov w10, s23 +; CHECK-NEXT: strb w8, [sp, #2] +; CHECK-NEXT: strb w9, [sp, #1] +; CHECK-NEXT: strb w10, [sp] +; CHECK-NEXT: ldp q0, q1, [sp] +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: ret + %tmp1 = load <32 x i8>, <32 x i8>* %a + %tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> + store <32 x i8> %tmp2, <32 x i8>* %a + ret void +} + +define void @test_revv16i16_vl256(<16 x i16>* %a) #0 { +; CHECK-LABEL: test_revv16i16_vl256: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: mov z2.h, z0.h[1] +; CHECK-NEXT: mov z3.h, z0.h[2] +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: fmov w10, s3 +; CHECK-NEXT: mov z4.h, z0.h[3] +; CHECK-NEXT: mov z5.h, z0.h[4] +; CHECK-NEXT: mov z2.h, z0.h[5] +; CHECK-NEXT: strh w8, [sp, #30] +; CHECK-NEXT: fmov w8, s4 +; CHECK-NEXT: strh w9, [sp, #28] +; CHECK-NEXT: fmov w9, s5 +; CHECK-NEXT: strh w10, [sp, #26] +; CHECK-NEXT: fmov w10, s2 +; CHECK-NEXT: mov z2.h, z0.h[6] +; CHECK-NEXT: mov z0.h, z0.h[7] +; CHECK-NEXT: strh w8, [sp, #24] +; CHECK-NEXT: fmov w8, s2 +; CHECK-NEXT: strh w9, [sp, #22] +; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: strh w10, [sp, #20] +; CHECK-NEXT: fmov w10, s1 +; CHECK-NEXT: mov z0.h, z1.h[1] +; CHECK-NEXT: mov z2.h, z1.h[2] +; CHECK-NEXT: mov z3.h, z1.h[3] +; CHECK-NEXT: strh w8, [sp, #18] +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: strh w9, [sp, #16] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: strh w10, [sp, #14] +; CHECK-NEXT: fmov w10, s3 +; CHECK-NEXT: mov z4.h, z1.h[4] +; CHECK-NEXT: mov z5.h, z1.h[5] +; CHECK-NEXT: mov z6.h, z1.h[6] +; CHECK-NEXT: strh w8, [sp, #12] +; CHECK-NEXT: fmov w8, s4 +; CHECK-NEXT: strh w9, [sp, #10] +; CHECK-NEXT: fmov w9, s5 +; CHECK-NEXT: strh w10, [sp, #8] +; CHECK-NEXT: fmov w10, s6 +; CHECK-NEXT: strh w8, [sp, #6] +; CHECK-NEXT: strh w9, [sp, #4] +; CHECK-NEXT: strh w10, [sp, #2] +; CHECK-NEXT: ldp q0, q1, [sp] +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: ret + %tmp1 = load <16 x i16>, <16 x i16>* %a + %tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> + store <16 x i16> %tmp2, <16 x i16>* %a + ret void +} + +define void @test_revv8f32_vl256(<8 x float>* %a) #0 { +; CHECK-LABEL: test_revv8f32_vl256: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: mov z2.s, z0.s[1] +; CHECK-NEXT: stp s2, s0, [sp, #24] +; CHECK-NEXT: mov z2.s, z0.s[2] +; CHECK-NEXT: mov z0.s, z0.s[3] +; CHECK-NEXT: stp s0, s2, [sp, #16] +; CHECK-NEXT: mov z0.s, z1.s[1] +; CHECK-NEXT: stp s0, s1, [sp, #8] +; CHECK-NEXT: mov z2.s, z1.s[2] +; CHECK-NEXT: mov z0.s, z1.s[3] +; CHECK-NEXT: stp s0, s2, [sp] +; CHECK-NEXT: ldp q0, q1, [sp] +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: ret + %tmp1 = load <8 x float>, <8 x float>* %a + %tmp2 = shufflevector <8 x float> %tmp1, <8 x float> undef, <8 x i32> + store <8 x float> %tmp2, <8 x float>* %a + ret void +} + +define void @test_revv4f64_vl256(<4 x double>* %a) #0 { +; CHECK-LABEL: test_revv4f64_vl256: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: ldp q0, q1, [x0] +; CHECK-NEXT: mov z2.d, z0.d[1] +; CHECK-NEXT: stp d2, d0, [sp, #16] +; CHECK-NEXT: mov z0.d, z1.d[1] +; CHECK-NEXT: stp d0, d1, [sp] +; CHECK-NEXT: ldp q0, q1, [sp] +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: ret + %tmp1 = load <4 x double>, <4 x double>* %a + %tmp2 = shufflevector <4 x double> %tmp1, <4 x double> undef, <4 x i32> + store <4 x double> %tmp2, <4 x double>* %a + ret void +} + +define void @test_revv8i32v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { +; CHECK-LABEL: test_revv8i32v8i32: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: ldp q0, q1, [x1] +; CHECK-NEXT: mov z2.s, z0.s[1] +; CHECK-NEXT: mov z3.s, z0.s[2] +; CHECK-NEXT: mov z4.s, z0.s[3] +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: fmov w10, s3 +; CHECK-NEXT: fmov w11, s4 +; CHECK-NEXT: mov z0.s, z1.s[1] +; CHECK-NEXT: mov z2.s, z1.s[2] +; CHECK-NEXT: mov z3.s, z1.s[3] +; CHECK-NEXT: stp w9, w8, [sp, #24] +; CHECK-NEXT: fmov w8, s1 +; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: stp w11, w10, [sp, #16] +; CHECK-NEXT: fmov w10, s2 +; CHECK-NEXT: fmov w11, s3 +; CHECK-NEXT: stp w9, w8, [sp, #8] +; CHECK-NEXT: stp w11, w10, [sp] +; CHECK-NEXT: ldp q0, q1, [sp] +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: ret + %tmp1 = load <8 x i32>, <8 x i32>* %a + %tmp2 = load <8 x i32>, <8 x i32>* %b + %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> + store <8 x i32> %tmp3, <8 x i32>* %a + ret void +} + +; Illegal REV pattern. +define void @test_rev_fail(<16 x i16>* %a) #0 { +; CHECK-LABEL: test_rev_fail: +; CHECK: // %bb.0: +; CHECK-NEXT: sub sp, sp, #32 +; CHECK-NEXT: .cfi_def_cfa_offset 32 +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: mov z6.h, z1.h[6] +; CHECK-NEXT: mov z7.h, z1.h[7] +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: mov z2.h, z0.h[1] +; CHECK-NEXT: mov z3.h, z0.h[2] +; CHECK-NEXT: mov z4.h, z0.h[3] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: fmov w10, s3 +; CHECK-NEXT: strh w8, [sp, #14] +; CHECK-NEXT: fmov w8, s4 +; CHECK-NEXT: mov z5.h, z0.h[4] +; CHECK-NEXT: mov z2.h, z0.h[5] +; CHECK-NEXT: strh w9, [sp, #12] +; CHECK-NEXT: fmov w9, s5 +; CHECK-NEXT: strh w10, [sp, #10] +; CHECK-NEXT: fmov w10, s2 +; CHECK-NEXT: mov z2.h, z0.h[6] +; CHECK-NEXT: strh w8, [sp, #8] +; CHECK-NEXT: fmov w8, s2 +; CHECK-NEXT: mov z0.h, z0.h[7] +; CHECK-NEXT: strh w9, [sp, #6] +; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: mov z0.h, z1.h[1] +; CHECK-NEXT: strh w10, [sp, #4] +; CHECK-NEXT: fmov w10, s1 +; CHECK-NEXT: strh w8, [sp, #2] +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: mov z2.h, z1.h[2] +; CHECK-NEXT: mov z3.h, z1.h[3] +; CHECK-NEXT: mov z4.h, z1.h[4] +; CHECK-NEXT: strh w9, [sp] +; CHECK-NEXT: fmov w9, s2 +; CHECK-NEXT: strh w10, [sp, #30] +; CHECK-NEXT: fmov w10, s3 +; CHECK-NEXT: strh w8, [sp, #28] +; CHECK-NEXT: fmov w8, s4 +; CHECK-NEXT: mov z5.h, z1.h[5] +; CHECK-NEXT: strh w9, [sp, #26] +; CHECK-NEXT: fmov w9, s5 +; CHECK-NEXT: strh w10, [sp, #24] +; CHECK-NEXT: fmov w10, s6 +; CHECK-NEXT: strh w8, [sp, #22] +; CHECK-NEXT: fmov w8, s7 +; CHECK-NEXT: strh w9, [sp, #20] +; CHECK-NEXT: strh w10, [sp, #18] +; CHECK-NEXT: strh w8, [sp, #16] +; CHECK-NEXT: ldp q1, q0, [sp] +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: ret + %tmp1 = load <16 x i16>, <16 x i16>* %a + %tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> + store <16 x i16> %tmp2, <16 x i16>* %a + ret void +} + +define void @test_revv8i16v8i16(<8 x i16>* %a, <8 x i16>* %b, <16 x i16>* %c) #0 { +; CHECK-LABEL: test_revv8i16v8i16: +; CHECK: // %bb.0: +; CHECK-NEXT: ldr q0, [x1] +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: ldr q1, [x0] +; CHECK-NEXT: revh z0.d, p0/m, z0.d +; CHECK-NEXT: revh z1.d, p0/m, z1.d +; CHECK-NEXT: stp q1, q0, [x2] +; CHECK-NEXT: ret + %tmp1 = load <8 x i16>, <8 x i16>* %a + %tmp2 = load <8 x i16>, <8 x i16>* %b + %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> + store <16 x i16> %tmp3, <16 x i16>* %c ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll @@ -3,7 +3,7 @@ target triple = "aarch64-unknown-linux-gnu" -define void @zip1_v32i8(ptr %a, ptr %b) #0 { +define void @zip1_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 { ; CHECK-LABEL: zip1_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 @@ -66,14 +66,14 @@ ; CHECK-NEXT: str q2, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %tmp1 = load volatile <32 x i8>, ptr %a - %tmp2 = load volatile <32 x i8>, ptr %b + %tmp1 = load volatile <32 x i8>, <32 x i8>* %a + %tmp2 = load volatile <32 x i8>, <32 x i8>* %b %tmp3 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> - store volatile <32 x i8> %tmp3, ptr %a + store volatile <32 x i8> %tmp3, <32 x i8>* %a ret void } -define void @zip_v32i16(ptr %a, ptr %b) #0 { +define void @zip_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { ; CHECK-LABEL: zip_v32i16: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #64 @@ -194,16 +194,16 @@ ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: add sp, sp, #64 ; CHECK-NEXT: ret - %tmp1 = load <32 x i16>, ptr %a - %tmp2 = load <32 x i16>, ptr %b + %tmp1 = load <32 x i16>, <32 x i16>* %a + %tmp2 = load <32 x i16>, <32 x i16>* %b %tmp3 = shufflevector <32 x i16> %tmp1, <32 x i16> %tmp2, <32 x i32> %tmp4 = shufflevector <32 x i16> %tmp1, <32 x i16> %tmp2, <32 x i32> %tmp5 = add <32 x i16> %tmp3, %tmp4 - store <32 x i16> %tmp5, ptr %a + store <32 x i16> %tmp5, <32 x i16>* %a ret void } -define void @zip1_v16i16(ptr %a, ptr %b) #0 { +define void @zip1_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { ; CHECK-LABEL: zip1_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 @@ -242,14 +242,14 @@ ; CHECK-NEXT: str q2, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %tmp1 = load volatile <16 x i16>, ptr %a - %tmp2 = load volatile <16 x i16>, ptr %b + %tmp1 = load volatile <16 x i16>, <16 x i16>* %a + %tmp2 = load volatile <16 x i16>, <16 x i16>* %b %tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> - store volatile <16 x i16> %tmp3, ptr %a + store volatile <16 x i16> %tmp3, <16 x i16>* %a ret void } -define void @zip1_v8i32(ptr %a, ptr %b) #0 { +define void @zip1_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { ; CHECK-LABEL: zip1_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 @@ -274,14 +274,14 @@ ; CHECK-NEXT: str q2, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %tmp1 = load volatile <8 x i32>, ptr %a - %tmp2 = load volatile <8 x i32>, ptr %b + %tmp1 = load volatile <8 x i32>, <8 x i32>* %a + %tmp2 = load volatile <8 x i32>, <8 x i32>* %b %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> - store volatile <8 x i32> %tmp3, ptr %a + store volatile <8 x i32> %tmp3, <8 x i32>* %a ret void } -define void @zip_v4f64(ptr %a, ptr %b) #0 { +define void @zip_v4f64(<4 x double>* %a, <4 x double>* %b) #0 { ; CHECK-LABEL: zip_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] @@ -295,16 +295,16 @@ ; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <4 x double>, ptr %a - %tmp2 = load <4 x double>, ptr %b + %tmp1 = load <4 x double>, <4 x double>* %a + %tmp2 = load <4 x double>, <4 x double>* %b %tmp3 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> %tmp4 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> %tmp5 = fadd <4 x double> %tmp3, %tmp4 - store <4 x double> %tmp5, ptr %a + store <4 x double> %tmp5, <4 x double>* %a ret void } -define void @zip_v4i32(ptr %a, ptr %b) #0 { +define void @zip_v4i32(<4 x i32>* %a, <4 x i32>* %b) #0 { ; CHECK-LABEL: zip_v4i32: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 @@ -327,16 +327,16 @@ ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %tmp1 = load <4 x i32>, ptr %a - %tmp2 = load <4 x i32>, ptr %b + %tmp1 = load <4 x i32>, <4 x i32>* %a + %tmp2 = load <4 x i32>, <4 x i32>* %b %tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> %tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> %tmp5 = add <4 x i32> %tmp3, %tmp4 - store <4 x i32> %tmp5, ptr %a + store <4 x i32> %tmp5, <4 x i32>* %a ret void } -define void @zip1_v8i32_undef(ptr %a) #0 { +define void @zip1_v8i32_undef(<8 x i32>* %a) #0 { ; CHECK-LABEL: zip1_v8i32_undef: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 @@ -355,13 +355,13 @@ ; CHECK-NEXT: str q1, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %tmp1 = load volatile <8 x i32>, ptr %a + %tmp1 = load volatile <8 x i32>, <8 x i32>* %a %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> - store volatile <8 x i32> %tmp2, ptr %a + store volatile <8 x i32> %tmp2, <8 x i32>* %a ret void } -define void @trn_v32i8(ptr %a, ptr %b) #0 { +define void @trn_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 { ; CHECK-LABEL: trn_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] @@ -374,64 +374,47 @@ ; CHECK-NEXT: add z0.b, z5.b, z0.b ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <32 x i8>, ptr %a - %tmp2 = load <32 x i8>, ptr %b + %tmp1 = load <32 x i8>, <32 x i8>* %a + %tmp2 = load <32 x i8>, <32 x i8>* %b %tmp3 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> %tmp4 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> %tmp5 = add <32 x i8> %tmp3, %tmp4 - store <32 x i8> %tmp5, ptr %a + store <32 x i8> %tmp5, <32 x i8>* %a ret void } -define void @trn_v8i16(ptr %a, ptr %b) #0 { -; CHECK-LABEL: trn_v8i16: +define void @trn_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0 { +; CHECK-LABEL: trn_v32i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ldr q0, [x0] -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: mov z1.h, z0.h[3] -; CHECK-NEXT: mov z2.h, z0.h[1] -; CHECK-NEXT: mov z6.h, z0.h[2] -; CHECK-NEXT: mov z3.h, z0.h[5] -; CHECK-NEXT: mov z4.h, z0.h[4] -; CHECK-NEXT: mov z5.h, z0.h[6] -; CHECK-NEXT: fmov w9, s1 -; CHECK-NEXT: mov z0.h, z0.h[7] -; CHECK-NEXT: fmov w10, s2 -; CHECK-NEXT: fmov w11, s6 -; CHECK-NEXT: strh w8, [sp, #-32]! -; CHECK-NEXT: .cfi_def_cfa_offset 32 -; CHECK-NEXT: fmov w8, s3 -; CHECK-NEXT: fmov w12, s4 -; CHECK-NEXT: fmov w13, s5 -; CHECK-NEXT: strh w11, [sp, #4] -; CHECK-NEXT: fmov w11, s0 -; CHECK-NEXT: strh w9, [sp, #14] -; CHECK-NEXT: strh w10, [sp, #12] -; CHECK-NEXT: strh w8, [sp, #10] -; CHECK-NEXT: strh w12, [sp, #8] -; CHECK-NEXT: strh w13, [sp, #6] -; CHECK-NEXT: strh w11, [sp, #2] -; CHECK-NEXT: strh w11, [sp, #28] -; CHECK-NEXT: strh w12, [sp, #26] -; CHECK-NEXT: strh w8, [sp, #22] -; CHECK-NEXT: strh w9, [sp, #20] -; CHECK-NEXT: strh w13, [sp, #18] -; CHECK-NEXT: strh w10, [sp, #16] -; CHECK-NEXT: ldp q0, q1, [sp] -; CHECK-NEXT: add z0.h, z0.h, z1.h -; CHECK-NEXT: str q0, [x0] -; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: ldp q1, q0, [x0] +; CHECK-NEXT: ldp q3, q2, [x0, #32] +; CHECK-NEXT: ldp q5, q4, [x1, #32] +; CHECK-NEXT: trn1 z16.h, z3.h, z5.h +; CHECK-NEXT: trn2 z3.h, z3.h, z5.h +; CHECK-NEXT: add z3.h, z16.h, z3.h +; CHECK-NEXT: ldp q6, q7, [x1] +; CHECK-NEXT: trn1 z17.h, z2.h, z4.h +; CHECK-NEXT: trn2 z2.h, z2.h, z4.h +; CHECK-NEXT: add z2.h, z17.h, z2.h +; CHECK-NEXT: stp q3, q2, [x0, #32] +; CHECK-NEXT: trn1 z18.h, z1.h, z6.h +; CHECK-NEXT: trn2 z1.h, z1.h, z6.h +; CHECK-NEXT: add z1.h, z18.h, z1.h +; CHECK-NEXT: trn1 z19.h, z0.h, z7.h +; CHECK-NEXT: trn2 z0.h, z0.h, z7.h +; CHECK-NEXT: add z0.h, z19.h, z0.h +; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x i16>, ptr %a - %tmp2 = load <8 x i16>, ptr %b - %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> - %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> - %tmp5 = add <8 x i16> %tmp3, %tmp4 - store <8 x i16> %tmp5, ptr %a + %tmp1 = load <32 x i16>, <32 x i16>* %a + %tmp2 = load <32 x i16>, <32 x i16>* %b + %tmp3 = shufflevector <32 x i16> %tmp1, <32 x i16> %tmp2, <32 x i32> + %tmp4 = shufflevector <32 x i16> %tmp1, <32 x i16> %tmp2, <32 x i32> + %tmp5 = add <32 x i16> %tmp3, %tmp4 + store <32 x i16> %tmp5, <32 x i16>* %a ret void } -define void @trn_v16i16(ptr %a, ptr %b) #0 { +define void @trn_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { ; CHECK-LABEL: trn_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] @@ -444,16 +427,16 @@ ; CHECK-NEXT: add z0.h, z5.h, z0.h ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <16 x i16>, ptr %a - %tmp2 = load <16 x i16>, ptr %b + %tmp1 = load <16 x i16>, <16 x i16>* %a + %tmp2 = load <16 x i16>, <16 x i16>* %b %tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> %tmp4 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> %tmp5 = add <16 x i16> %tmp3, %tmp4 - store <16 x i16> %tmp5, ptr %a + store <16 x i16> %tmp5, <16 x i16>* %a ret void } -define void @trn_v8i32(ptr %a, ptr %b) #0 { +define void @trn_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { ; CHECK-LABEL: trn_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] @@ -466,16 +449,16 @@ ; CHECK-NEXT: add z0.s, z5.s, z0.s ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x i32>, ptr %a - %tmp2 = load <8 x i32>, ptr %b + %tmp1 = load <8 x i32>, <8 x i32>* %a + %tmp2 = load <8 x i32>, <8 x i32>* %b %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> %tmp4 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> %tmp5 = add <8 x i32> %tmp3, %tmp4 - store <8 x i32> %tmp5, ptr %a + store <8 x i32> %tmp5, <8 x i32>* %a ret void } -define void @trn_v4f64(ptr %a, ptr %b) #0 { +define void @trn_v4f64(<4 x double>* %a, <4 x double>* %b) #0 { ; CHECK-LABEL: trn_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] @@ -489,16 +472,16 @@ ; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z5.d ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <4 x double>, ptr %a - %tmp2 = load <4 x double>, ptr %b + %tmp1 = load <4 x double>, <4 x double>* %a + %tmp2 = load <4 x double>, <4 x double>* %b %tmp3 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> %tmp4 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> %tmp5 = fadd <4 x double> %tmp3, %tmp4 - store <4 x double> %tmp5, ptr %a + store <4 x double> %tmp5, <4 x double>* %a ret void } -define void @trn_v4f32(ptr %a, ptr %b) #0 { +define void @trn_v4f32(<4 x float>* %a, <4 x float>* %b) #0 { ; CHECK-LABEL: trn_v4f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0] @@ -509,16 +492,16 @@ ; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z2.s ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <4 x float>, ptr %a - %tmp2 = load <4 x float>, ptr %b + %tmp1 = load <4 x float>, <4 x float>* %a + %tmp2 = load <4 x float>, <4 x float>* %b %tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> %tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> %tmp5 = fadd <4 x float> %tmp3, %tmp4 - store <4 x float> %tmp5, ptr %a + store <4 x float> %tmp5, <4 x float>* %a ret void } -define void @trn_v8i32_undef(ptr %a) #0 { +define void @trn_v8i32_undef(<8 x i32>* %a) #0 { ; CHECK-LABEL: trn_v8i32_undef: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q0, q1, [x0] @@ -530,15 +513,15 @@ ; CHECK-NEXT: add z1.s, z3.s, z1.s ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %tmp1 = load <8 x i32>, ptr %a + %tmp1 = load <8 x i32>, <8 x i32>* %a %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> %tmp4 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> %tmp5 = add <8 x i32> %tmp3, %tmp4 - store <8 x i32> %tmp5, ptr %a + store <8 x i32> %tmp5, <8 x i32>* %a ret void } -define void @zip2_v32i8(ptr %a, ptr %b) #0{ +define void @zip2_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0{ ; CHECK-LABEL: zip2_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 @@ -601,14 +584,14 @@ ; CHECK-NEXT: str q2, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %tmp1 = load volatile <32 x i8>, ptr %a - %tmp2 = load volatile <32 x i8>, ptr %b + %tmp1 = load volatile <32 x i8>, <32 x i8>* %a + %tmp2 = load volatile <32 x i8>, <32 x i8>* %b %tmp3 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> - store volatile <32 x i8> %tmp3, ptr %a + store volatile <32 x i8> %tmp3, <32 x i8>* %a ret void } -define void @zip2_v16i16(ptr %a, ptr %b) #0{ +define void @zip2_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0{ ; CHECK-LABEL: zip2_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 @@ -647,14 +630,14 @@ ; CHECK-NEXT: str q2, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %tmp1 = load volatile <16 x i16>, ptr %a - %tmp2 = load volatile <16 x i16>, ptr %b + %tmp1 = load volatile <16 x i16>, <16 x i16>* %a + %tmp2 = load volatile <16 x i16>, <16 x i16>* %b %tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> - store volatile <16 x i16> %tmp3, ptr %a + store volatile <16 x i16> %tmp3, <16 x i16>* %a ret void } -define void @zip2_v8i32(ptr %a, ptr %b) #0{ +define void @zip2_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0{ ; CHECK-LABEL: zip2_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 @@ -679,14 +662,14 @@ ; CHECK-NEXT: str q2, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %tmp1 = load volatile <8 x i32>, ptr %a - %tmp2 = load volatile <8 x i32>, ptr %b + %tmp1 = load volatile <8 x i32>, <8 x i32>* %a + %tmp2 = load volatile <8 x i32>, <8 x i32>* %b %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> - store volatile <8 x i32> %tmp3, ptr %a + store volatile <8 x i32> %tmp3, <8 x i32>* %a ret void } -define void @zip2_v8i32_undef(ptr %a) #0{ +define void @zip2_v8i32_undef(<8 x i32>* %a) #0{ ; CHECK-LABEL: zip2_v8i32_undef: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 @@ -705,13 +688,13 @@ ; CHECK-NEXT: str q1, [x0, #16] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %tmp1 = load volatile <8 x i32>, ptr %a + %tmp1 = load volatile <8 x i32>, <8 x i32>* %a %tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> - store volatile <8 x i32> %tmp2, ptr %a + store volatile <8 x i32> %tmp2, <8 x i32>* %a ret void } -define void @uzp_v32i8(ptr %a, ptr %b) #0{ +define void @uzp_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0{ ; CHECK-LABEL: uzp_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #128 @@ -922,49 +905,241 @@ ; CHECK-NEXT: ldp d15, d14, [sp, #64] // 16-byte Folded Reload ; CHECK-NEXT: add sp, sp, #128 ; CHECK-NEXT: ret - %tmp1 = load <32 x i8>, ptr %a - %tmp2 = load <32 x i8>, ptr %b + %tmp1 = load <32 x i8>, <32 x i8>* %a + %tmp2 = load <32 x i8>, <32 x i8>* %b %tmp3 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> %tmp4 = shufflevector <32 x i8> %tmp1, <32 x i8> %tmp2, <32 x i32> %tmp5 = add <32 x i8> %tmp3, %tmp4 - store <32 x i8> %tmp5, ptr %a + store <32 x i8> %tmp5, <32 x i8>* %a ret void } -define void @uzp_v4i16(ptr %a, ptr %b) #0{ -; CHECK-LABEL: uzp_v4i16: +define void @uzp_v32i16(<32 x i16>* %a, <32 x i16>* %b) #0{ +; CHECK-LABEL: uzp_v32i16: ; CHECK: // %bb.0: -; CHECK-NEXT: ldr d0, [x0] -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: mov z1.h, z0.h[1] -; CHECK-NEXT: mov z2.h, z0.h[2] -; CHECK-NEXT: mov z0.h, z0.h[3] -; CHECK-NEXT: fmov w9, s1 -; CHECK-NEXT: fmov w10, s2 -; CHECK-NEXT: fmov w11, s0 -; CHECK-NEXT: strh w8, [sp, #-16]! -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: strh w9, [sp, #6] -; CHECK-NEXT: strh w10, [sp, #4] -; CHECK-NEXT: strh w11, [sp, #2] -; CHECK-NEXT: strh w8, [sp, #10] -; CHECK-NEXT: strh w10, [sp, #12] +; CHECK-NEXT: sub sp, sp, #192 +; CHECK-NEXT: .cfi_def_cfa_offset 192 +; CHECK-NEXT: stp d15, d14, [sp, #128] // 16-byte Folded Spill +; CHECK-NEXT: stp d13, d12, [sp, #144] // 16-byte Folded Spill +; CHECK-NEXT: stp d11, d10, [sp, #160] // 16-byte Folded Spill +; CHECK-NEXT: stp d9, d8, [sp, #176] // 16-byte Folded Spill +; CHECK-NEXT: .cfi_offset b8, -8 +; CHECK-NEXT: .cfi_offset b9, -16 +; CHECK-NEXT: .cfi_offset b10, -24 +; CHECK-NEXT: .cfi_offset b11, -32 +; CHECK-NEXT: .cfi_offset b12, -40 +; CHECK-NEXT: .cfi_offset b13, -48 +; CHECK-NEXT: .cfi_offset b14, -56 +; CHECK-NEXT: .cfi_offset b15, -64 +; CHECK-NEXT: ldp q4, q5, [x1] +; CHECK-NEXT: fmov w9, s4 +; CHECK-NEXT: mov z22.h, z4.h[4] +; CHECK-NEXT: mov z23.h, z4.h[2] +; CHECK-NEXT: mov z21.h, z4.h[6] +; CHECK-NEXT: fmov w8, s5 +; CHECK-NEXT: mov z7.h, z5.h[4] +; CHECK-NEXT: ldp q0, q1, [x0, #32] +; CHECK-NEXT: mov z16.h, z5.h[2] +; CHECK-NEXT: mov z6.h, z5.h[6] +; CHECK-NEXT: fmov w10, s6 +; CHECK-NEXT: mov z17.h, z5.h[7] +; CHECK-NEXT: mov z18.h, z5.h[5] +; CHECK-NEXT: mov z19.h, z5.h[3] +; CHECK-NEXT: mov z14.h, z0.h[4] +; CHECK-NEXT: mov z15.h, z0.h[2] +; CHECK-NEXT: mov z13.h, z0.h[6] +; CHECK-NEXT: mov z20.h, z5.h[1] +; CHECK-NEXT: ldp q2, q3, [x0] +; CHECK-NEXT: mov z5.h, z4.h[7] +; CHECK-NEXT: mov z6.h, z4.h[5] +; CHECK-NEXT: mov z12.h, z1.h[5] +; CHECK-NEXT: mov z10.h, z2.h[4] +; CHECK-NEXT: mov z11.h, z2.h[2] +; CHECK-NEXT: ldp q25, q24, [x1, #32] +; CHECK-NEXT: strh w8, [sp, #40] +; CHECK-NEXT: fmov w8, s7 +; CHECK-NEXT: strh w9, [sp, #32] +; CHECK-NEXT: fmov w9, s16 +; CHECK-NEXT: strh w10, [sp, #46] +; CHECK-NEXT: fmov w10, s21 +; CHECK-NEXT: strh w8, [sp, #44] +; CHECK-NEXT: fmov w8, s22 +; CHECK-NEXT: strh w9, [sp, #42] +; CHECK-NEXT: mov z29.h, z25.h[6] +; CHECK-NEXT: fmov w9, s24 +; CHECK-NEXT: mov z26.h, z24.h[6] +; CHECK-NEXT: strh w8, [sp, #36] +; CHECK-NEXT: fmov w8, s23 +; CHECK-NEXT: mov z27.h, z24.h[4] +; CHECK-NEXT: mov z30.h, z25.h[4] ; CHECK-NEXT: strh w9, [sp, #8] -; CHECK-NEXT: ldp d0, d1, [sp] -; CHECK-NEXT: add z0.h, z0.h, z1.h -; CHECK-NEXT: str d0, [x0] -; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: fmov w9, s27 +; CHECK-NEXT: strh w8, [sp, #34] +; CHECK-NEXT: fmov w8, s26 +; CHECK-NEXT: strh w10, [sp, #38] +; CHECK-NEXT: mov z31.h, z25.h[2] +; CHECK-NEXT: strh w9, [sp, #12] +; CHECK-NEXT: fmov w9, s30 +; CHECK-NEXT: strh w8, [sp, #14] +; CHECK-NEXT: fmov w8, s29 +; CHECK-NEXT: fmov w10, s25 +; CHECK-NEXT: mov z28.h, z24.h[2] +; CHECK-NEXT: strh w9, [sp, #4] +; CHECK-NEXT: fmov w9, s3 +; CHECK-NEXT: strh w8, [sp, #6] +; CHECK-NEXT: fmov w8, s31 +; CHECK-NEXT: strh w10, [sp] +; CHECK-NEXT: fmov w10, s28 +; CHECK-NEXT: mov z28.h, z3.h[6] +; CHECK-NEXT: mov z29.h, z3.h[4] +; CHECK-NEXT: strh w8, [sp, #2] +; CHECK-NEXT: fmov w8, s28 +; CHECK-NEXT: strh w9, [sp, #104] +; CHECK-NEXT: fmov w9, s29 +; CHECK-NEXT: mov z30.h, z3.h[2] +; CHECK-NEXT: mov z31.h, z3.h[5] +; CHECK-NEXT: mov z8.h, z3.h[3] +; CHECK-NEXT: mov z9.h, z3.h[1] +; CHECK-NEXT: mov z3.h, z2.h[6] +; CHECK-NEXT: strh w8, [sp, #110] +; CHECK-NEXT: fmov w8, s3 +; CHECK-NEXT: strh w9, [sp, #108] +; CHECK-NEXT: fmov w9, s10 +; CHECK-NEXT: strh w10, [sp, #10] +; CHECK-NEXT: fmov w10, s2 +; CHECK-NEXT: mov z10.h, z1.h[2] +; CHECK-NEXT: strh w8, [sp, #102] +; CHECK-NEXT: fmov w8, s11 +; CHECK-NEXT: strh w9, [sp, #100] +; CHECK-NEXT: fmov w9, s1 +; CHECK-NEXT: strh w10, [sp, #96] +; CHECK-NEXT: fmov w10, s30 +; CHECK-NEXT: mov z30.h, z1.h[4] +; CHECK-NEXT: strh w8, [sp, #98] +; CHECK-NEXT: strh w9, [sp, #72] +; CHECK-NEXT: fmov w8, s30 +; CHECK-NEXT: fmov w9, s10 +; CHECK-NEXT: strh w10, [sp, #106] +; CHECK-NEXT: fmov w10, s0 +; CHECK-NEXT: mov z7.h, z4.h[3] +; CHECK-NEXT: strh w8, [sp, #76] +; CHECK-NEXT: fmov w8, s14 +; CHECK-NEXT: strh w9, [sp, #74] +; CHECK-NEXT: fmov w9, s15 +; CHECK-NEXT: strh w10, [sp, #64] +; CHECK-NEXT: fmov w10, s13 +; CHECK-NEXT: strh w8, [sp, #68] +; CHECK-NEXT: fmov w8, s17 +; CHECK-NEXT: strh w9, [sp, #66] +; CHECK-NEXT: fmov w9, s18 +; CHECK-NEXT: strh w10, [sp, #70] +; CHECK-NEXT: fmov w10, s19 +; CHECK-NEXT: strh w8, [sp, #62] +; CHECK-NEXT: fmov w8, s20 +; CHECK-NEXT: strh w9, [sp, #60] +; CHECK-NEXT: fmov w9, s5 +; CHECK-NEXT: mov z4.h, z4.h[1] +; CHECK-NEXT: strh w10, [sp, #58] +; CHECK-NEXT: fmov w10, s6 +; CHECK-NEXT: strh w8, [sp, #56] +; CHECK-NEXT: fmov w8, s7 +; CHECK-NEXT: strh w9, [sp, #54] +; CHECK-NEXT: fmov w9, s4 +; CHECK-NEXT: mov z16.h, z24.h[7] +; CHECK-NEXT: mov z21.h, z24.h[5] +; CHECK-NEXT: mov z22.h, z24.h[3] +; CHECK-NEXT: strh w10, [sp, #52] +; CHECK-NEXT: fmov w10, s16 +; CHECK-NEXT: strh w8, [sp, #50] +; CHECK-NEXT: fmov w8, s21 +; CHECK-NEXT: strh w9, [sp, #48] +; CHECK-NEXT: fmov w9, s22 +; CHECK-NEXT: mov z23.h, z24.h[1] +; CHECK-NEXT: mov z24.h, z25.h[7] +; CHECK-NEXT: mov z26.h, z25.h[5] +; CHECK-NEXT: strh w10, [sp, #30] +; CHECK-NEXT: fmov w10, s23 +; CHECK-NEXT: strh w8, [sp, #28] +; CHECK-NEXT: fmov w8, s24 +; CHECK-NEXT: strh w9, [sp, #26] +; CHECK-NEXT: fmov w9, s26 +; CHECK-NEXT: mov z27.h, z25.h[3] +; CHECK-NEXT: mov z25.h, z25.h[1] +; CHECK-NEXT: strh w10, [sp, #24] +; CHECK-NEXT: fmov w10, s27 +; CHECK-NEXT: strh w8, [sp, #22] +; CHECK-NEXT: fmov w8, s25 +; CHECK-NEXT: strh w9, [sp, #20] +; CHECK-NEXT: fmov w9, s31 +; CHECK-NEXT: mov z3.h, z2.h[5] +; CHECK-NEXT: strh w10, [sp, #18] +; CHECK-NEXT: fmov w10, s8 +; CHECK-NEXT: strh w8, [sp, #16] +; CHECK-NEXT: fmov w8, s9 +; CHECK-NEXT: strh w9, [sp, #124] +; CHECK-NEXT: fmov w9, s3 +; CHECK-NEXT: mov z28.h, z2.h[3] +; CHECK-NEXT: mov z2.h, z2.h[1] +; CHECK-NEXT: mov z11.h, z1.h[7] +; CHECK-NEXT: strh w10, [sp, #122] +; CHECK-NEXT: fmov w10, s28 +; CHECK-NEXT: strh w8, [sp, #120] +; CHECK-NEXT: fmov w8, s2 +; CHECK-NEXT: strh w9, [sp, #116] +; CHECK-NEXT: fmov w9, s11 +; CHECK-NEXT: mov z29.h, z1.h[6] +; CHECK-NEXT: fmov w11, s29 +; CHECK-NEXT: mov z29.h, z1.h[3] +; CHECK-NEXT: mov z1.h, z1.h[1] +; CHECK-NEXT: strh w10, [sp, #114] +; CHECK-NEXT: fmov w10, s12 +; CHECK-NEXT: strh w8, [sp, #112] +; CHECK-NEXT: fmov w8, s29 +; CHECK-NEXT: strh w9, [sp, #94] +; CHECK-NEXT: fmov w9, s1 +; CHECK-NEXT: mov z30.h, z0.h[7] +; CHECK-NEXT: mov z10.h, z0.h[5] +; CHECK-NEXT: mov z0.h, z0.h[3] +; CHECK-NEXT: strh w10, [sp, #92] +; CHECK-NEXT: fmov w10, s30 +; CHECK-NEXT: strh w8, [sp, #90] +; CHECK-NEXT: fmov w8, s10 +; CHECK-NEXT: strh w9, [sp, #88] +; CHECK-NEXT: fmov w9, s0 +; CHECK-NEXT: ldr q13, [sp, #32] +; CHECK-NEXT: strh w11, [sp, #78] +; CHECK-NEXT: ldr q0, [sp, #48] +; CHECK-NEXT: strh w10, [sp, #86] +; CHECK-NEXT: ldr q17, [sp] +; CHECK-NEXT: strh w8, [sp, #84] +; CHECK-NEXT: strh w9, [sp, #82] +; CHECK-NEXT: ldr q1, [sp, #16] +; CHECK-NEXT: ldr q18, [sp, #96] +; CHECK-NEXT: add z0.h, z13.h, z0.h +; CHECK-NEXT: ldr q19, [sp, #64] +; CHECK-NEXT: ldr q2, [sp, #112] +; CHECK-NEXT: add z1.h, z17.h, z1.h +; CHECK-NEXT: ldr q3, [sp, #80] +; CHECK-NEXT: stp q0, q1, [x0, #32] +; CHECK-NEXT: ldp d9, d8, [sp, #176] // 16-byte Folded Reload +; CHECK-NEXT: add z0.h, z18.h, z2.h +; CHECK-NEXT: ldp d11, d10, [sp, #160] // 16-byte Folded Reload +; CHECK-NEXT: add z1.h, z19.h, z3.h +; CHECK-NEXT: ldp d13, d12, [sp, #144] // 16-byte Folded Reload +; CHECK-NEXT: stp q0, q1, [x0] +; CHECK-NEXT: ldp d15, d14, [sp, #128] // 16-byte Folded Reload +; CHECK-NEXT: add sp, sp, #192 ; CHECK-NEXT: ret - %tmp1 = load <4 x i16>, ptr %a - %tmp2 = load <4 x i16>, ptr %b - %tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> - %tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> - %tmp5 = add <4 x i16> %tmp3, %tmp4 - store <4 x i16> %tmp5, ptr %a + %tmp1 = load <32 x i16>, <32 x i16>* %a + %tmp2 = load <32 x i16>, <32 x i16>* %b + %tmp3 = shufflevector <32 x i16> %tmp1, <32 x i16> %tmp2, <32 x i32> + %tmp4 = shufflevector <32 x i16> %tmp1, <32 x i16> %tmp2, <32 x i32> + %tmp5 = add <32 x i16> %tmp3, %tmp4 + store <32 x i16> %tmp5, <32 x i16>* %a ret void } -define void @uzp_v16i16(ptr %a, ptr %b) #0{ +define void @uzp_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0{ ; CHECK-LABEL: uzp_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #64 @@ -1072,16 +1247,16 @@ ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: add sp, sp, #64 ; CHECK-NEXT: ret - %tmp1 = load <16 x i16>, ptr %a - %tmp2 = load <16 x i16>, ptr %b + %tmp1 = load <16 x i16>, <16 x i16>* %a + %tmp2 = load <16 x i16>, <16 x i16>* %b %tmp3 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> %tmp4 = shufflevector <16 x i16> %tmp1, <16 x i16> %tmp2, <16 x i32> %tmp5 = add <16 x i16> %tmp3, %tmp4 - store <16 x i16> %tmp5, ptr %a + store <16 x i16> %tmp5, <16 x i16>* %a ret void } -define void @uzp_v8f32(ptr %a, ptr %b) #0{ +define void @uzp_v8f32(<8 x float>* %a, <8 x float>* %b) #0{ ; CHECK-LABEL: uzp_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #64 @@ -1110,16 +1285,16 @@ ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: add sp, sp, #64 ; CHECK-NEXT: ret - %tmp1 = load <8 x float>, ptr %a - %tmp2 = load <8 x float>, ptr %b + %tmp1 = load <8 x float>, <8 x float>* %a + %tmp2 = load <8 x float>, <8 x float>* %b %tmp3 = shufflevector <8 x float> %tmp1, <8 x float> %tmp2, <8 x i32> %tmp4 = shufflevector <8 x float> %tmp1, <8 x float> %tmp2, <8 x i32> %tmp5 = fadd <8 x float> %tmp3, %tmp4 - store <8 x float> %tmp5, ptr %a + store <8 x float> %tmp5, <8 x float>* %a ret void } -define void @uzp_v4i64(ptr %a, ptr %b) #0{ +define void @uzp_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0{ ; CHECK-LABEL: uzp_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] @@ -1132,16 +1307,16 @@ ; CHECK-NEXT: add z1.d, z5.d, z1.d ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %tmp1 = load <4 x i64>, ptr %a - %tmp2 = load <4 x i64>, ptr %b + %tmp1 = load <4 x i64>, <4 x i64>* %a + %tmp2 = load <4 x i64>, <4 x i64>* %b %tmp3 = shufflevector <4 x i64> %tmp1, <4 x i64> %tmp2, <4 x i32> %tmp4 = shufflevector <4 x i64> %tmp1, <4 x i64> %tmp2, <4 x i32> %tmp5 = add <4 x i64> %tmp3, %tmp4 - store <4 x i64> %tmp5, ptr %a + store <4 x i64> %tmp5, <4 x i64>* %a ret void } -define void @uzp_v8i16(ptr %a, ptr %b) #0{ +define void @uzp_v8i16(<8 x i16>* %a, <8 x i16>* %b) #0{ ; CHECK-LABEL: uzp_v8i16: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #32 @@ -1199,16 +1374,16 @@ ; CHECK-NEXT: str q0, [x0] ; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret - %tmp1 = load <8 x i16>, ptr %a - %tmp2 = load <8 x i16>, ptr %b + %tmp1 = load <8 x i16>, <8 x i16>* %a + %tmp2 = load <8 x i16>, <8 x i16>* %b %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> %tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> %tmp5 = add <8 x i16> %tmp3, %tmp4 - store <8 x i16> %tmp5, ptr %a + store <8 x i16> %tmp5, <8 x i16>* %a ret void } -define void @uzp_v8i32_undef(ptr %a) #0{ +define void @uzp_v8i32_undef(<8 x i32>* %a) #0{ ; CHECK-LABEL: uzp_v8i32_undef: ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #32 @@ -1237,15 +1412,15 @@ ; CHECK-NEXT: stp q0, q0, [x0] ; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret - %tmp1 = load <8 x i32>, ptr %a + %tmp1 = load <8 x i32>, <8 x i32>* %a %tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> %tmp4 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> %tmp5 = add <8 x i32> %tmp3, %tmp4 - store <8 x i32> %tmp5, ptr %a + store <8 x i32> %tmp5, <8 x i32>* %a ret void } -define void @zip_vscale2_4(ptr %a, ptr %b) #0 { +define void @zip_vscale2_4(<4 x double>* %a, <4 x double>* %b) #0 { ; CHECK-LABEL: zip_vscale2_4: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q0, [x0] @@ -1259,12 +1434,12 @@ ; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: stp q2, q0, [x0] ; CHECK-NEXT: ret - %tmp1 = load <4 x double>, ptr %a - %tmp2 = load <4 x double>, ptr %b + %tmp1 = load <4 x double>, <4 x double>* %a + %tmp2 = load <4 x double>, <4 x double>* %b %tmp3 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> %tmp4 = shufflevector <4 x double> %tmp1, <4 x double> %tmp2, <4 x i32> %tmp5 = fadd <4 x double> %tmp3, %tmp4 - store <4 x double> %tmp5, ptr %a + store <4 x double> %tmp5, <4 x double>* %a ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll @@ -3,8 +3,8 @@ target triple = "aarch64-unknown-linux-gnu" -define i1 @ptest_v16i1(ptr %a, ptr %b) #0 { -; CHECK-LABEL: ptest_v16i1: +define i1 @ptest_v16i1_256bit_min_sve(float* %a, float * %b) #0 { +; CHECK-LABEL: ptest_v16i1_256bit_min_sve: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI0_0 ; CHECK-NEXT: ptrue p0.s, vl4 @@ -35,21 +35,99 @@ ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret - %v0 = bitcast ptr %a to <16 x float>* + %v0 = bitcast float* %a to <16 x float>* %v1 = load <16 x float>, <16 x float>* %v0, align 4 %v2 = fcmp une <16 x float> %v1, zeroinitializer %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2) ret i1 %v3 } -define i1 @ptest_or_v16i1(ptr %a, ptr %b) #0 { -; CHECK-LABEL: ptest_or_v16i1: +define i1 @ptest_v16i1_512bit_min_sve(float* %a, float * %b) #0 { +; CHECK-LABEL: ptest_v16i1_512bit_min_sve: ; CHECK: // %bb.0: ; CHECK-NEXT: adrp x8, .LCPI1_0 ; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldp q1, q2, [x0, #32] +; CHECK-NEXT: ptrue p1.h, vl4 +; CHECK-NEXT: ldp q3, q4, [x0] +; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI1_0] +; CHECK-NEXT: fcmne p2.s, p0/z, z2.s, z0.s +; CHECK-NEXT: mov z2.s, p2/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p2.s, p0/z, z1.s, z0.s +; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p2.s, p0/z, z4.s, z0.s +; CHECK-NEXT: fcmne p0.s, p0/z, z3.s, z0.s +; CHECK-NEXT: mov z0.s, p2/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h +; CHECK-NEXT: mov z3.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: splice z1.h, p1, z1.h, z2.h +; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z2.h, z3.h, z3.h +; CHECK-NEXT: splice z2.h, p1, z2.h, z0.h +; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z0.b, z2.b, z2.b +; CHECK-NEXT: ptrue p0.b, vl8 +; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: orv b0, p0, z0.b +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: and w0, w8, #0x1 +; CHECK-NEXT: ret + %v0 = bitcast float* %a to <16 x float>* + %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v2 = fcmp une <16 x float> %v1, zeroinitializer + %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2) + ret i1 %v3 +} + +define i1 @ptest_v16i1_512bit_sve(float* %a, float * %b) #0 { +; CHECK-LABEL: ptest_v16i1_512bit_sve: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI2_0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldp q1, q2, [x0, #32] +; CHECK-NEXT: ptrue p1.h, vl4 +; CHECK-NEXT: ldp q3, q4, [x0] +; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI2_0] +; CHECK-NEXT: fcmne p2.s, p0/z, z2.s, z0.s +; CHECK-NEXT: mov z2.s, p2/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p2.s, p0/z, z1.s, z0.s +; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p2.s, p0/z, z4.s, z0.s +; CHECK-NEXT: fcmne p0.s, p0/z, z3.s, z0.s +; CHECK-NEXT: mov z0.s, p2/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h +; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h +; CHECK-NEXT: mov z3.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: splice z1.h, p1, z1.h, z2.h +; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z2.h, z3.h, z3.h +; CHECK-NEXT: splice z2.h, p1, z2.h, z0.h +; CHECK-NEXT: uzp1 z1.b, z1.b, z1.b +; CHECK-NEXT: uzp1 z0.b, z2.b, z2.b +; CHECK-NEXT: ptrue p0.b, vl8 +; CHECK-NEXT: splice z0.b, p0, z0.b, z1.b +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: orv b0, p0, z0.b +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: and w0, w8, #0x1 +; CHECK-NEXT: ret + %v0 = bitcast float* %a to <16 x float>* + %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v2 = fcmp une <16 x float> %v1, zeroinitializer + %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2) + ret i1 %v3 +} + +define i1 @ptest_or_v16i1_512bit_min_sve(float* %a, float * %b) #0 { +; CHECK-LABEL: ptest_or_v16i1_512bit_min_sve: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI3_0 +; CHECK-NEXT: ptrue p0.s, vl4 ; CHECK-NEXT: ldp q0, q2, [x0, #32] ; CHECK-NEXT: ptrue p1.h, vl4 -; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0] +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0] ; CHECK-NEXT: ldp q3, q4, [x0] ; CHECK-NEXT: fcmne p2.s, p0/z, z2.s, z1.s ; CHECK-NEXT: fcmne p3.s, p0/z, z0.s, z1.s @@ -94,7 +172,7 @@ ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret - %v0 = bitcast ptr %a to <16 x float>* + %v0 = bitcast float* %a to <16 x float>* %v1 = load <16 x float>, <16 x float>* %v0, align 4 %v2 = fcmp une <16 x float> %v1, zeroinitializer %v3 = bitcast float* %b to <16 x float>* @@ -111,14 +189,77 @@ ; AND reduction. ; -define i1 @ptest_and_v16i1(ptr %a, ptr %b) #0 { -; CHECK-LABEL: ptest_and_v16i1: +define i1 @ptest_and_v16i1_512bit_sve(float* %a, float * %b) #0 { +; CHECK-LABEL: ptest_and_v16i1_512bit_sve: ; CHECK: // %bb.0: -; CHECK-NEXT: adrp x8, .LCPI2_0 +; CHECK-NEXT: adrp x8, .LCPI4_0 +; CHECK-NEXT: ptrue p0.s, vl4 +; CHECK-NEXT: ldp q0, q2, [x0, #32] +; CHECK-NEXT: ptrue p1.h, vl4 +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0] +; CHECK-NEXT: ldp q3, q4, [x0] +; CHECK-NEXT: fcmne p2.s, p0/z, z2.s, z1.s +; CHECK-NEXT: fcmne p3.s, p0/z, z0.s, z1.s +; CHECK-NEXT: mov z0.s, p2/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z2.s, p3/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h +; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h +; CHECK-NEXT: splice z2.h, p1, z2.h, z0.h +; CHECK-NEXT: ldp q0, q5, [x1, #32] +; CHECK-NEXT: fcmne p2.s, p0/z, z4.s, z1.s +; CHECK-NEXT: uzp1 z2.b, z2.b, z2.b +; CHECK-NEXT: mov z4.s, p2/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmne p2.s, p0/z, z3.s, z1.s +; CHECK-NEXT: mov z3.s, p2/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h +; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h +; CHECK-NEXT: fcmne p3.s, p0/z, z0.s, z1.s +; CHECK-NEXT: splice z3.h, p1, z3.h, z4.h +; CHECK-NEXT: fcmne p2.s, p0/z, z5.s, z1.s +; CHECK-NEXT: uzp1 z3.b, z3.b, z3.b +; CHECK-NEXT: ldp q4, q5, [x1] +; CHECK-NEXT: mov z0.s, p2/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h +; CHECK-NEXT: fcmne p2.s, p0/z, z5.s, z1.s +; CHECK-NEXT: fcmne p0.s, p0/z, z4.s, z1.s +; CHECK-NEXT: mov z5.s, p3/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: mov z4.s, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h +; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h +; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h +; CHECK-NEXT: splice z5.h, p1, z5.h, z0.h +; CHECK-NEXT: splice z4.h, p1, z4.h, z1.h +; CHECK-NEXT: ptrue p3.b, vl8 +; CHECK-NEXT: uzp1 z0.b, z5.b, z5.b +; CHECK-NEXT: uzp1 z1.b, z4.b, z4.b +; CHECK-NEXT: splice z3.b, p3, z3.b, z2.b +; CHECK-NEXT: splice z1.b, p3, z1.b, z0.b +; CHECK-NEXT: ptrue p0.b, vl16 +; CHECK-NEXT: and z0.d, z3.d, z1.d +; CHECK-NEXT: andv b0, p0, z0.b +; CHECK-NEXT: fmov w8, s0 +; CHECK-NEXT: and w0, w8, #0x1 +; CHECK-NEXT: ret + %v0 = bitcast float* %a to <16 x float>* + %v1 = load <16 x float>, <16 x float>* %v0, align 4 + %v2 = fcmp une <16 x float> %v1, zeroinitializer + %v3 = bitcast float* %b to <16 x float>* + %v4 = load <16 x float>, <16 x float>* %v3, align 4 + %v5 = fcmp une <16 x float> %v4, zeroinitializer + %v6 = and <16 x i1> %v2, %v5 + %v7 = call i1 @llvm.vector.reduce.and.i1.v16i1 (<16 x i1> %v6) + ret i1 %v7 +} + +define i1 @ptest_and_v16i1_512bit_min_sve(float* %a, float * %b) #0 { +; CHECK-LABEL: ptest_and_v16i1_512bit_min_sve: +; CHECK: // %bb.0: +; CHECK-NEXT: adrp x8, .LCPI5_0 ; CHECK-NEXT: ptrue p0.s, vl4 ; CHECK-NEXT: ldp q0, q2, [x0, #32] ; CHECK-NEXT: ptrue p1.h, vl4 -; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0] +; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0] ; CHECK-NEXT: ldp q3, q4, [x0] ; CHECK-NEXT: fcmne p2.s, p0/z, z2.s, z1.s ; CHECK-NEXT: fcmne p3.s, p0/z, z0.s, z1.s @@ -163,7 +304,7 @@ ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: and w0, w8, #0x1 ; CHECK-NEXT: ret - %v0 = bitcast ptr %a to <16 x float>* + %v0 = bitcast float* %a to <16 x float>* %v1 = load <16 x float>, <16 x float>* %v0, align 4 %v2 = fcmp une <16 x float> %v1, zeroinitializer %v3 = bitcast float* %b to <16 x float>* diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll @@ -1,20 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s -; Test we can code generater patterns of the form: -; fixed_length_vector = ISD::EXTRACT_SUBVECTOR scalable_vector, 0 -; scalable_vector = ISD::INSERT_SUBVECTOR scalable_vector, fixed_length_vector, 0 -; -; NOTE: Currently shufflevector does not support scalable vectors so it cannot -; be used to model the above operations. Instead these tests rely on knowing -; how fixed length operation are lowered to scalable ones, with multiple blocks -; ensuring insert/extract sequences are not folded away. - -target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target triple = "aarch64-unknown-linux-gnu" ; i8 -define void @subvector_v4i8(ptr %in, ptr %out) #0 { +define void @subvector_v4i8(<4 x i8> *%in, <4 x i8>* %out) #0 { ; CHECK-LABEL: subvector_v4i8: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr s0, [x0] @@ -22,58 +12,58 @@ ; CHECK-NEXT: uunpklo z0.h, z0.b ; CHECK-NEXT: st1b { z0.h }, p0, [x1] ; CHECK-NEXT: ret - %a = load <4 x i8>, ptr %in + %a = load <4 x i8>, <4 x i8>* %in br label %bb1 bb1: - store <4 x i8> %a, ptr %out + store <4 x i8> %a, <4 x i8>* %out ret void } -define void @subvector_v8i8(ptr %in, ptr %out) #0 { +define void @subvector_v8i8(<8 x i8> *%in, <8 x i8>* %out) #0 { ; CHECK-LABEL: subvector_v8i8: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret - %a = load <8 x i8>, ptr %in + %a = load <8 x i8>, <8 x i8>* %in br label %bb1 bb1: - store <8 x i8> %a, ptr %out + store <8 x i8> %a, <8 x i8>* %out ret void } -define void @subvector_v16i8(ptr %in, ptr %out) #0 { +define void @subvector_v16i8(<16 x i8> *%in, <16 x i8>* %out) #0 { ; CHECK-LABEL: subvector_v16i8: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %a = load <16 x i8>, ptr %in + %a = load <16 x i8>, <16 x i8>* %in br label %bb1 bb1: - store <16 x i8> %a, ptr %out + store <16 x i8> %a, <16 x i8>* %out ret void } -define void @subvector_v32i8(ptr %in, ptr %out) #0 { +define void @subvector_v32i8(<32 x i8> *%in, <32 x i8>* %out) #0 { ; CHECK-LABEL: subvector_v32i8: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret - %a = load <32 x i8>, ptr %in + %a = load <32 x i8>, <32 x i8>* %in br label %bb1 bb1: - store <32 x i8> %a, ptr %out + store <32 x i8> %a, <32 x i8>* %out ret void } ; i16 -define void @subvector_v2i16(ptr %in, ptr %out) #0 { +define void @subvector_v2i16(<2 x i16> *%in, <2 x i16>* %out) #0 { ; CHECK-LABEL: subvector_v2i16: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: sub sp, sp, #16 @@ -87,254 +77,254 @@ ; CHECK-NEXT: st1h { z0.s }, p0, [x1] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret - %a = load <2 x i16>, ptr %in + %a = load <2 x i16>, <2 x i16>* %in br label %bb1 bb1: - store <2 x i16> %a, ptr %out + store <2 x i16> %a, <2 x i16>* %out ret void } -define void @subvector_v4i16(ptr %in, ptr %out) #0 { +define void @subvector_v4i16(<4 x i16> *%in, <4 x i16>* %out) #0 { ; CHECK-LABEL: subvector_v4i16: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret - %a = load <4 x i16>, ptr %in + %a = load <4 x i16>, <4 x i16>* %in br label %bb1 bb1: - store <4 x i16> %a, ptr %out + store <4 x i16> %a, <4 x i16>* %out ret void } -define void @subvector_v8i16(ptr %in, ptr %out) #0 { +define void @subvector_v8i16(<8 x i16> *%in, <8 x i16>* %out) #0 { ; CHECK-LABEL: subvector_v8i16: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %a = load <8 x i16>, ptr %in + %a = load <8 x i16>, <8 x i16>* %in br label %bb1 bb1: - store <8 x i16> %a, ptr %out + store <8 x i16> %a, <8 x i16>* %out ret void } -define void @subvector_v16i16(ptr %in, ptr %out) #0 { +define void @subvector_v16i16(<16 x i16> *%in, <16 x i16>* %out) #0 { ; CHECK-LABEL: subvector_v16i16: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret - %a = load <16 x i16>, ptr %in + %a = load <16 x i16>, <16 x i16>* %in br label %bb1 bb1: - store <16 x i16> %a, ptr %out + store <16 x i16> %a, <16 x i16>* %out ret void } ; i32 -define void @subvector_v2i32(ptr %in, ptr %out) #0 { +define void @subvector_v2i32(<2 x i32> *%in, <2 x i32>* %out) #0 { ; CHECK-LABEL: subvector_v2i32: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret - %a = load <2 x i32>, ptr %in + %a = load <2 x i32>, <2 x i32>* %in br label %bb1 bb1: - store <2 x i32> %a, ptr %out + store <2 x i32> %a, <2 x i32>* %out ret void } -define void @subvector_v4i32(ptr %in, ptr %out) #0 { +define void @subvector_v4i32(<4 x i32> *%in, <4 x i32>* %out) #0 { ; CHECK-LABEL: subvector_v4i32: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %a = load <4 x i32>, ptr %in + %a = load <4 x i32>, <4 x i32>* %in br label %bb1 bb1: - store <4 x i32> %a, ptr %out + store <4 x i32> %a, <4 x i32>* %out ret void } -define void @subvector_v8i32(ptr %in, ptr %out) #0 { +define void @subvector_v8i32(<8 x i32> *%in, <8 x i32>* %out) #0 { ; CHECK-LABEL: subvector_v8i32: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret - %a = load <8 x i32>, ptr %in + %a = load <8 x i32>, <8 x i32>* %in br label %bb1 bb1: - store <8 x i32> %a, ptr %out + store <8 x i32> %a, <8 x i32>* %out ret void } ; i64 -define void @subvector_v2i64(ptr %in, ptr %out) #0 { +define void @subvector_v2i64(<2 x i64> *%in, <2 x i64>* %out) #0 { ; CHECK-LABEL: subvector_v2i64: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %a = load <2 x i64>, ptr %in + %a = load <2 x i64>, <2 x i64>* %in br label %bb1 bb1: - store <2 x i64> %a, ptr %out + store <2 x i64> %a, <2 x i64>* %out ret void } -define void @subvector_v4i64(ptr %in, ptr %out) #0 { +define void @subvector_v4i64(<4 x i64> *%in, <4 x i64>* %out) #0 { ; CHECK-LABEL: subvector_v4i64: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret - %a = load <4 x i64>, ptr %in + %a = load <4 x i64>, <4 x i64>* %in br label %bb1 bb1: - store <4 x i64> %a, ptr %out + store <4 x i64> %a, <4 x i64>* %out ret void } ; f16 -define void @subvector_v2f16(ptr %in, ptr %out) #0 { +define void @subvector_v2f16(<2 x half> *%in, <2 x half>* %out) #0 { ; CHECK-LABEL: subvector_v2f16: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr w8, [x0] ; CHECK-NEXT: str w8, [x1] ; CHECK-NEXT: ret - %a = load <2 x half>, ptr %in + %a = load <2 x half>, <2 x half>* %in br label %bb1 bb1: - store <2 x half> %a, ptr %out + store <2 x half> %a, <2 x half>* %out ret void } -define void @subvector_v4f16(ptr %in, ptr %out) #0 { +define void @subvector_v4f16(<4 x half> *%in, <4 x half>* %out) #0 { ; CHECK-LABEL: subvector_v4f16: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret - %a = load <4 x half>, ptr %in + %a = load <4 x half>, <4 x half>* %in br label %bb1 bb1: - store <4 x half> %a, ptr %out + store <4 x half> %a, <4 x half>* %out ret void } -define void @subvector_v8f16(ptr %in, ptr %out) #0 { +define void @subvector_v8f16(<8 x half> *%in, <8 x half>* %out) #0 { ; CHECK-LABEL: subvector_v8f16: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %a = load <8 x half>, ptr %in + %a = load <8 x half>, <8 x half>* %in br label %bb1 bb1: - store <8 x half> %a, ptr %out + store <8 x half> %a, <8 x half>* %out ret void } -define void @subvector_v16f16(ptr %in, ptr %out) #0 { +define void @subvector_v16f16(<16 x half> *%in, <16 x half>* %out) #0 { ; CHECK-LABEL: subvector_v16f16: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret - %a = load <16 x half>, ptr %in + %a = load <16 x half>, <16 x half>* %in br label %bb1 bb1: - store <16 x half> %a, ptr %out + store <16 x half> %a, <16 x half>* %out ret void } ; f32 -define void @subvector_v2f32(ptr %in, ptr %out) #0 { +define void @subvector_v2f32(<2 x float> *%in, <2 x float>* %out) #0 { ; CHECK-LABEL: subvector_v2f32: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: str d0, [x1] ; CHECK-NEXT: ret - %a = load <2 x float>, ptr %in + %a = load <2 x float>, <2 x float>* %in br label %bb1 bb1: - store <2 x float> %a, ptr %out + store <2 x float> %a, <2 x float>* %out ret void } -define void @subvector_v4f32(ptr %in, ptr %out) #0 { +define void @subvector_v4f32(<4 x float> *%in, <4 x float>* %out) #0 { ; CHECK-LABEL: subvector_v4f32: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %a = load <4 x float>, ptr %in + %a = load <4 x float>, <4 x float>* %in br label %bb1 bb1: - store <4 x float> %a, ptr %out + store <4 x float> %a, <4 x float>* %out ret void } -define void @subvector_v8f32(ptr %in, ptr %out) #0 { +define void @subvector_v8f32(<8 x float> *%in, <8 x float>* %out) #0 { ; CHECK-LABEL: subvector_v8f32: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret - %a = load <8 x float>,ptr %in + %a = load <8 x float>, <8 x float>* %in br label %bb1 bb1: - store <8 x float> %a, ptr %out + store <8 x float> %a, <8 x float>* %out ret void } ; f64 -define void @subvector_v2f64(ptr %in, ptr %out) #0 { +define void @subvector_v2f64(<2 x double> *%in, <2 x double>* %out) #0 { ; CHECK-LABEL: subvector_v2f64: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: str q0, [x1] ; CHECK-NEXT: ret - %a = load <2 x double>, ptr %in + %a = load <2 x double>, <2 x double>* %in br label %bb1 bb1: - store <2 x double> %a, ptr %out + store <2 x double> %a, <2 x double>* %out ret void } -define void @subvector_v4f64(ptr %in, ptr %out) #0 { +define void @subvector_v4f64(<4 x double> *%in, <4 x double>* %out) #0 { ; CHECK-LABEL: subvector_v4f64: ; CHECK: // %bb.0: // %bb1 ; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: stp q0, q1, [x1] ; CHECK-NEXT: ret - %a = load <4 x double>, ptr %in + %a = load <4 x double>, <4 x double>* %in br label %bb1 bb1: - store <4 x double> %a, ptr %out + store <4 x double> %a, <4 x double>* %out ret void } diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll @@ -3,29 +3,10 @@ target triple = "aarch64-unknown-linux-gnu" -define <4 x i8> @shuffle_ext_byone_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 { -; CHECK-LABEL: shuffle_ext_byone_v4i8: -; CHECK: // %bb.0: -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: mov z1.h, z0.h[1] -; CHECK-NEXT: fmov w8, s0 -; CHECK-NEXT: mov z2.h, z0.h[2] -; CHECK-NEXT: mov z0.h, z0.h[3] -; CHECK-NEXT: fmov w9, s1 -; CHECK-NEXT: fmov w10, s2 -; CHECK-NEXT: fmov w11, s0 -; CHECK-NEXT: strh w8, [sp, #8] -; CHECK-NEXT: strh w9, [sp, #14] -; CHECK-NEXT: strh w10, [sp, #12] -; CHECK-NEXT: strh w11, [sp, #10] -; CHECK-NEXT: ldr d0, [sp, #8] -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret - %ret = shufflevector <4 x i8> %op1, <4 x i8> %op2, <4 x i32> - ret <4 x i8> %ret -} +; define <4 x i8> @shuffle_ext_byone_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 { +; %ret = shufflevector <4 x i8> %op1, <4 x i8> %op2, <4 x i32> +; ret <4 x i8> %ret +; } define <8 x i8> @shuffle_ext_byone_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 { ; CHECK-LABEL: shuffle_ext_byone_v8i8: @@ -56,7 +37,7 @@ ret <16 x i8> %ret } -define void @shuffle_ext_byone_v32i8(ptr %a, ptr %b) #0 { +define void @shuffle_ext_byone_v32i8(<32 x i8>* %a, <32 x i8>* %b) #0 { ; CHECK-LABEL: shuffle_ext_byone_v32i8: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0, #16] @@ -70,27 +51,20 @@ ; CHECK-NEXT: insr z0.b, w9 ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <32 x i8>, ptr %a - %op2 = load <32 x i8>, ptr %b + %op1 = load <32 x i8>, <32 x i8>* %a + %op2 = load <32 x i8>, <32 x i8>* %b %ret = shufflevector <32 x i8> %op1, <32 x i8> %op2, <32 x i32> - store <32 x i8> %ret, ptr %a + store <32 x i8> %ret, <32 x i8>* %a ret void } -define <2 x i16> @shuffle_ext_byone_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 { -; CHECK-LABEL: shuffle_ext_byone_v2i16: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: revw z0.d, p0/m, z0.d -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 -; CHECK-NEXT: ret - %ret = shufflevector <2 x i16> %op1, <2 x i16> %op2, <2 x i32> - ret <2 x i16> %ret -} +; define <2 x i16> @shuffle_ext_byone_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 { +; %ret = shufflevector <2 x i16> %op1, <2 x i16> %op2, <2 x i32> +; ret <2 x i16> %ret +; } define <4 x i16> @shuffle_ext_byone_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 { ; CHECK-LABEL: shuffle_ext_byone_v4i16: @@ -120,7 +94,7 @@ ret <8 x i16> %ret } -define void @shuffle_ext_byone_v16i16(ptr %a, ptr %b) #0 { +define void @shuffle_ext_byone_v16i16(<16 x i16>* %a, <16 x i16>* %b) #0 { ; CHECK-LABEL: shuffle_ext_byone_v16i16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0, #16] @@ -134,11 +108,11 @@ ; CHECK-NEXT: insr z0.h, w9 ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x i16>, ptr %a - %op2 = load <16 x i16>, ptr %b + %op1 = load <16 x i16>, <16 x i16>* %a + %op2 = load <16 x i16>, <16 x i16>* %b %ret = shufflevector <16 x i16> %op1, <16 x i16> %op2, <16 x i32> - store <16 x i16> %ret, ptr %a + store <16 x i16> %ret, <16 x i16>* %a ret void } @@ -170,7 +144,7 @@ ret <4 x i32> %ret } -define void @shuffle_ext_byone_v8i32(ptr %a, ptr %b) #0 { +define void @shuffle_ext_byone_v8i32(<8 x i32>* %a, <8 x i32>* %b) #0 { ; CHECK-LABEL: shuffle_ext_byone_v8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0, #16] @@ -184,10 +158,10 @@ ; CHECK-NEXT: insr z0.s, w9 ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x i32>, ptr %a - %op2 = load <8 x i32>, ptr %b + %op1 = load <8 x i32>, <8 x i32>* %a + %op2 = load <8 x i32>, <8 x i32>* %b %ret = shufflevector <8 x i32> %op1, <8 x i32> %op2, <8 x i32> - store <8 x i32> %ret, ptr %a + store <8 x i32> %ret, <8 x i32>* %a ret void } @@ -205,7 +179,7 @@ ret <2 x i64> %ret } -define void @shuffle_ext_byone_v4i64(ptr %a, ptr %b) #0 { +define void @shuffle_ext_byone_v4i64(<4 x i64>* %a, <4 x i64>* %b) #0 { ; CHECK-LABEL: shuffle_ext_byone_v4i64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0, #16] @@ -219,10 +193,10 @@ ; CHECK-NEXT: insr z0.d, x9 ; CHECK-NEXT: stp q1, q0, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x i64>, ptr %a - %op2 = load <4 x i64>, ptr %b + %op1 = load <4 x i64>, <4 x i64>* %a + %op2 = load <4 x i64>, <4 x i64>* %b %ret = shufflevector <4 x i64> %op1, <4 x i64> %op2, <4 x i32> - store <4 x i64> %ret, ptr %a + store <4 x i64> %ret, <4 x i64>* %a ret void } @@ -253,7 +227,7 @@ ret <8 x half> %ret } -define void @shuffle_ext_byone_v16f16(ptr %a, ptr %b) #0 { +define void @shuffle_ext_byone_v16f16(<16 x half>* %a, <16 x half>* %b) #0 { ; CHECK-LABEL: shuffle_ext_byone_v16f16: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q2, [x1] @@ -264,11 +238,11 @@ ; CHECK-NEXT: insr z1.h, h0 ; CHECK-NEXT: stp q1, q2, [x0] ; CHECK-NEXT: ret - %op1 = load <16 x half>, ptr %a - %op2 = load <16 x half>, ptr %b + %op1 = load <16 x half>, <16 x half>* %a + %op2 = load <16 x half>, <16 x half>* %b %ret = shufflevector <16 x half> %op1, <16 x half> %op2, <16 x i32> - store <16 x half> %ret, ptr %a + store <16 x half> %ret, <16 x half>* %a ret void } @@ -298,7 +272,7 @@ ret <4 x float> %ret } -define void @shuffle_ext_byone_v8f32(ptr %a, ptr %b) #0 { +define void @shuffle_ext_byone_v8f32(<8 x float>* %a, <8 x float>* %b) #0 { ; CHECK-LABEL: shuffle_ext_byone_v8f32: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q2, [x1] @@ -309,10 +283,10 @@ ; CHECK-NEXT: insr z1.s, s0 ; CHECK-NEXT: stp q1, q2, [x0] ; CHECK-NEXT: ret - %op1 = load <8 x float>, ptr %a - %op2 = load <8 x float>, ptr %b + %op1 = load <8 x float>, <8 x float>* %a + %op2 = load <8 x float>, <8 x float>* %b %ret = shufflevector <8 x float> %op1, <8 x float> %op2, <8 x i32> - store <8 x float> %ret, ptr %a + store <8 x float> %ret, <8 x float>* %a ret void } @@ -329,7 +303,7 @@ ret <2 x double> %ret } -define void @shuffle_ext_byone_v4f64(ptr %a, ptr %b) #0 { +define void @shuffle_ext_byone_v4f64(<4 x double>* %a, <4 x double>* %b) #0 { ; CHECK-LABEL: shuffle_ext_byone_v4f64: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q2, [x1] @@ -340,14 +314,14 @@ ; CHECK-NEXT: insr z1.d, d0 ; CHECK-NEXT: stp q1, q2, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, ptr %a - %op2 = load <4 x double>, ptr %b + %op1 = load <4 x double>, <4 x double>* %a + %op2 = load <4 x double>, <4 x double>* %b %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> - store <4 x double> %ret, ptr %a + store <4 x double> %ret, <4 x double>* %a ret void } -define void @shuffle_ext_byone_reverse(ptr %a, ptr %b) #0 { +define void @shuffle_ext_byone_reverse(<4 x double>* %a, <4 x double>* %b) #0 { ; CHECK-LABEL: shuffle_ext_byone_reverse: ; CHECK: // %bb.0: ; CHECK-NEXT: ldp q1, q2, [x0] @@ -358,24 +332,24 @@ ; CHECK-NEXT: insr z1.d, d0 ; CHECK-NEXT: stp q1, q2, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, ptr %a - %op2 = load <4 x double>, ptr %b + %op1 = load <4 x double>, <4 x double>* %a + %op2 = load <4 x double>, <4 x double>* %b %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> - store <4 x double> %ret, ptr %a + store <4 x double> %ret, <4 x double>* %a ret void } -define void @shuffle_ext_invalid(ptr %a, ptr %b) #0 { +define void @shuffle_ext_invalid(<4 x double>* %a, <4 x double>* %b) #0 { ; CHECK-LABEL: shuffle_ext_invalid: ; CHECK: // %bb.0: ; CHECK-NEXT: ldr q0, [x0, #16] ; CHECK-NEXT: ldr q1, [x1] ; CHECK-NEXT: stp q0, q1, [x0] ; CHECK-NEXT: ret - %op1 = load <4 x double>, ptr %a - %op2 = load <4 x double>, ptr %b + %op1 = load <4 x double>, <4 x double>* %a + %op2 = load <4 x double>, <4 x double>* %b %ret = shufflevector <4 x double> %op1, <4 x double> %op2, <4 x i32> - store <4 x double> %ret, ptr %a + store <4 x double> %ret, <4 x double>* %a ret void }