Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9718,7 +9718,7 @@
       if (!VT.isScalableVector() || VT.getVectorElementType() != MVT::i1)
         return std::make_pair(0U, nullptr);
       bool restricted = (PC == PredicateConstraint::Upl);
-      return restricted ? std::make_pair(0U, &AArch64::PPR_3bRegClass)
+      return restricted ? std::make_pair(0U, &AArch64::PPR_p0to7RegClass)
                         : std::make_pair(0U, &AArch64::PPRRegClass);
     }
   }
Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -879,7 +879,7 @@
 }
 
 def PPR    : PPRClass<15>;
-def PPR_3b : PPRClass<7>; // Restricted 3 bit SVE predicate register class.
+def PPR_p0to7 : PPRClass<7>; // Restricted 3 bit SVE predicate register class.
 
 class PPRAsmOperand <string name, string RegClass, int Width>: AsmOperandClass {
   let Name = "SVE" # name # "Reg";
@@ -902,9 +902,9 @@
 def PPR32  : PPRRegOp<"s", PPRAsmOp32,  ElementSizeS,  PPR>;
 def PPR64  : PPRRegOp<"d", PPRAsmOp64,  ElementSizeD,  PPR>;
 
-def PPRAsmOp3bAny : PPRAsmOperand<"Predicate3bAny", "PPR_3b",  0>;
+def PPRAsmOpAny_p0to7 : PPRAsmOperand<"PredicateAny_p0to7", "PPR_p0to7",  0>;
 
-def PPR3bAny : PPRRegOp<"",  PPRAsmOp3bAny, ElementSizeNone, PPR_3b>;
+def PPRAny_p0to7 : PPRRegOp<"", PPRAsmOpAny_p0to7, ElementSizeNone, PPR_p0to7>;
 
 //******************************************************************************
 
Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1466,19 +1466,19 @@
   multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instruction RegImmInst, Instruction RegRegInst, ComplexPattern AddrCP> {
     // reg + imm
     let AddedComplexity = 2 in {
-      def _reg_imm : Pat<(prefetch (PredTy PPR_3b:$gp), (am_sve_indexed_s6 GPR64sp:$base, simm6s1:$offset), (i32 sve_prfop:$prfop)),
-                         (RegImmInst sve_prfop:$prfop, PPR_3b:$gp, GPR64:$base, simm6s1:$offset)>;
+      def _reg_imm : Pat<(prefetch (PredTy PPR_p0to7:$gp), (am_sve_indexed_s6 GPR64sp:$base, simm6s1:$offset), (i32 sve_prfop:$prfop)),
+                         (RegImmInst sve_prfop:$prfop, PPR_p0to7:$gp, GPR64:$base, simm6s1:$offset)>;
     }
 
     // reg + reg
     let AddedComplexity = 1 in {
-      def _reg_reg : Pat<(prefetch (PredTy PPR_3b:$gp), (AddrCP GPR64sp:$base, GPR64:$index), (i32 sve_prfop:$prfop)),
-                         (RegRegInst sve_prfop:$prfop, PPR_3b:$gp, GPR64:$base, GPR64:$index)>;
+      def _reg_reg : Pat<(prefetch (PredTy PPR_p0to7:$gp), (AddrCP GPR64sp:$base, GPR64:$index), (i32 sve_prfop:$prfop)),
+                         (RegRegInst sve_prfop:$prfop, PPR_p0to7:$gp, GPR64:$base, GPR64:$index)>;
     }
 
     // default fallback
-    def _default : Pat<(prefetch  (PredTy PPR_3b:$gp), GPR64:$base, (i32 sve_prfop:$prfop)),
-                       (RegImmInst sve_prfop:$prfop, PPR_3b:$gp, GPR64:$base, (i64 0))>;
+    def _default : Pat<(prefetch  (PredTy PPR_p0to7:$gp), GPR64:$base, (i32 sve_prfop:$prfop)),
+                       (RegImmInst sve_prfop:$prfop, PPR_p0to7:$gp, GPR64:$base, (i64 0))>;
   }
 
   defm : sve_prefetch<int_aarch64_sve_prf, nxv16i1, PRFB_PRI, PRFB_PRR, am_sve_regreg_lsl0>;
@@ -2149,68 +2149,68 @@
                   (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>;
 
   def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGE_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
+                  (CMPGE_PPzZZ_B PPR8:$Zd, PPRAny_p0to7:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
   def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (CMPGE_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (CMPGE_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (CMPGE_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHI_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
+                  (CMPHI_PPzZZ_B PPR8:$Zd, PPRAny_p0to7:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
   def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHI_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (CMPHI_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHI_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (CMPHI_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHI_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (CMPHI_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHS_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
+                  (CMPHS_PPzZZ_B PPR8:$Zd, PPRAny_p0to7:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
   def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHS_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (CMPHS_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHS_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (CMPHS_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPHS_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (CMPHS_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGT_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
+                  (CMPGT_PPzZZ_B PPR8:$Zd, PPRAny_p0to7:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
   def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (CMPGT_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (CMPGT_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
-                  (CMPGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (CMPGT_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
-                  (FACGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (FACGE_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
-                  (FACGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (FACGE_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
-                  (FACGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (FACGE_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
-                  (FACGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (FACGT_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
-                  (FACGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (FACGT_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
-                  (FACGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (FACGT_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
-                  (FCMGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (FCMGE_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
-                  (FCMGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (FCMGE_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
-                  (FCMGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (FCMGE_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
-                  (FCMGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
+                  (FCMGT_PPzZZ_H PPR16:$Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
   def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
-                  (FCMGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
+                  (FCMGT_PPzZZ_S PPR32:$Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
   def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
-                  (FCMGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
+                  (FCMGT_PPzZZ_D PPR64:$Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
   // Pseudo instructions representing unpredicated LDR and STR for ZPR2,3,4.
   // These get expanded to individual LDR_ZXI/STR_ZXI instructions in
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1207,7 +1207,7 @@
       RK = RegKind::SVEDataVector;
       break;
     case AArch64::PPRRegClassID:
-    case AArch64::PPR_3bRegClassID:
+    case AArch64::PPR_p0to7RegClassID:
       RK = RegKind::SVEPredicateVector;
       break;
     default:
@@ -5571,7 +5571,7 @@
   case Match_InvalidSVEPredicateSReg:
   case Match_InvalidSVEPredicateDReg:
     return Error(Loc, "invalid predicate register.");
-  case Match_InvalidSVEPredicate3bAnyReg:
+  case Match_InvalidSVEPredicateAny_p0to7Reg:
     return Error(Loc, "invalid restricted predicate register, expected p0..p7 (without element suffix)");
   case Match_InvalidSVEExactFPImmOperandHalfOne:
     return Error(Loc, "Invalid floating point constant, expected 0.5 or 1.0.");
@@ -6144,7 +6144,7 @@
   case Match_InvalidSVEPredicateHReg:
   case Match_InvalidSVEPredicateSReg:
   case Match_InvalidSVEPredicateDReg:
-  case Match_InvalidSVEPredicate3bAnyReg:
+  case Match_InvalidSVEPredicateAny_p0to7Reg:
   case Match_InvalidSVEExactFPImmOperandHalfOne:
   case Match_InvalidSVEExactFPImmOperandHalfTwo:
   case Match_InvalidSVEExactFPImmOperandZeroOne:
Index: llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
===================================================================
--- llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -134,9 +134,9 @@
 static DecodeStatus DecodePPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                            uint64_t Address,
                                            const MCDisassembler *Decoder);
-static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
-                                              uint64_t Address,
-                                              const MCDisassembler *Decoder);
+static DecodeStatus DecodePPR_p0to7RegisterClass(MCInst &Inst, unsigned RegNo,
+                                                 uint64_t Address,
+                                                 const MCDisassembler *Decoder);
 
 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
                                                uint64_t Address,
@@ -699,9 +699,9 @@
   return Success;
 }
 
-static DecodeStatus DecodePPR_3bRegisterClass(MCInst &Inst, unsigned RegNo,
-                                              uint64_t Addr,
-                                              const MCDisassembler *Decoder) {
+static DecodeStatus
+DecodePPR_p0to7RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
+                             const MCDisassembler *Decoder) {
   if (RegNo > 7)
     return Fail;
 
Index: llvm/lib/Target/AArch64/SMEInstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -29,7 +29,7 @@
 //===----------------------------------------------------------------------===//
 
 class sme_outer_product_pseudo<ZPRRegOp zpr_ty>
-    : Pseudo<(outs), (ins i64imm:$tile, PPR3bAny:$pn, PPR3bAny:$pm,
+    : Pseudo<(outs), (ins i64imm:$tile, PPRAny_p0to7:$pn, PPRAny_p0to7:$pm,
                           zpr_ty:$zn, zpr_ty:$zm), []>,
       Sched<[]> {
   // Translated to the actual instructions in AArch64ISelLowering.cpp
@@ -39,7 +39,7 @@
 class sme_fp_outer_product_inst<bit S, bit sz, MatrixTileOperand za_ty,
                                 ZPRRegOp zpr_ty, string mnemonic>
     : I<(outs za_ty:$ZAda),
-      (ins za_ty:$_ZAda, PPR3bAny:$Pn, PPR3bAny:$Pm, zpr_ty:$Zn, zpr_ty:$Zm),
+      (ins za_ty:$_ZAda, PPRAny_p0to7:$Pn, PPRAny_p0to7:$Pm, zpr_ty:$Zn, zpr_ty:$Zm),
         mnemonic, "\t$ZAda, $Pn/m, $Pm/m, $Zn, $Zm",
         "", []>,
       Sched<[]> {
@@ -69,7 +69,7 @@
 
   def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR32>;
 
-  def : Pat<(op imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm),
+  def : Pat<(op imm0_3:$tile, (nxv4i1 PPRAny_p0to7:$pn), (nxv4i1 PPRAny_p0to7:$pm),
                 (nxv4f32 ZPR32:$zn), (nxv4f32 ZPR32:$zm)),
             (!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
 }
@@ -82,7 +82,7 @@
 
   def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR64>;
 
-  def : Pat<(op imm0_7:$tile, (nxv2i1 PPR3bAny:$pn), (nxv2i1 PPR3bAny:$pm),
+  def : Pat<(op imm0_7:$tile, (nxv2i1 PPRAny_p0to7:$pn), (nxv2i1 PPRAny_p0to7:$pm),
                 (nxv2f64 ZPR64:$zn), (nxv2f64 ZPR64:$zm)),
             (!cast<Instruction>(NAME # _PSEUDO) imm0_7:$tile, $pn, $pm, $zn, $zm)>;
 }
@@ -91,7 +91,7 @@
                                  MatrixTileOperand za_ty, ZPRRegOp zpr_ty,
                                  string mnemonic>
     : I<(outs za_ty:$ZAda),
-        (ins za_ty:$_ZAda, PPR3bAny:$Pn, PPR3bAny:$Pm, zpr_ty:$Zn, zpr_ty:$Zm),
+        (ins za_ty:$_ZAda, PPRAny_p0to7:$Pn, PPRAny_p0to7:$Pm, zpr_ty:$Zn, zpr_ty:$Zm),
         mnemonic, "\t$ZAda, $Pn/m, $Pm/m, $Zn, $Zm",
         "", []>,
       Sched<[]> {
@@ -125,7 +125,7 @@
 
   def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR8>;
 
-  def : Pat<(op imm0_3:$tile, (nxv16i1 PPR3bAny:$pn), (nxv16i1 PPR3bAny:$pm),
+  def : Pat<(op imm0_3:$tile, (nxv16i1 PPRAny_p0to7:$pn), (nxv16i1 PPRAny_p0to7:$pm),
                 (nxv16i8 ZPR8:$zn), (nxv16i8 ZPR8:$zm)),
             (!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
 }
@@ -140,14 +140,14 @@
 
   def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR16>;
 
-  def : Pat<(op imm0_7:$tile, (nxv8i1 PPR3bAny:$pn), (nxv8i1 PPR3bAny:$pm),
+  def : Pat<(op imm0_7:$tile, (nxv8i1 PPRAny_p0to7:$pn), (nxv8i1 PPRAny_p0to7:$pm),
                 (nxv8i16 ZPR16:$zn), (nxv8i16 ZPR16:$zm)),
             (!cast<Instruction>(NAME # _PSEUDO) imm0_7:$tile, $pn, $pm, $zn, $zm)>;
 }
 
 class sme_outer_product_widening_inst<bit op, bit S, string mnemonic>
     : I<(outs TileOp32:$ZAda),
-        (ins  TileOp32:$_ZAda, PPR3bAny:$Pn, PPR3bAny:$Pm, ZPR16:$Zn, ZPR16:$Zm),
+        (ins  TileOp32:$_ZAda, PPRAny_p0to7:$Pn, PPRAny_p0to7:$Pm, ZPR16:$Zn, ZPR16:$Zm),
         mnemonic, "\t$ZAda, $Pn/m, $Pm/m, $Zn, $Zm",
         "", []>,
       Sched<[]> {
@@ -174,7 +174,7 @@
 
   def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR16>;
 
-  def : Pat<(op imm0_3:$tile, (nxv8i1 PPR3bAny:$pn), (nxv8i1 PPR3bAny:$pm),
+  def : Pat<(op imm0_3:$tile, (nxv8i1 PPRAny_p0to7:$pn), (nxv8i1 PPRAny_p0to7:$pm),
                 (nxv8bf16 ZPR16:$zn), (nxv8bf16 ZPR16:$zm)),
             (!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
 }
@@ -184,7 +184,7 @@
 
   def NAME # _PSEUDO : sme_outer_product_pseudo<ZPR16>;
 
-  def : Pat<(op imm0_3:$tile, (nxv8i1 PPR3bAny:$pn), (nxv8i1 PPR3bAny:$pm),
+  def : Pat<(op imm0_3:$tile, (nxv8i1 PPRAny_p0to7:$pn), (nxv8i1 PPRAny_p0to7:$pm),
                 (nxv8f16 ZPR16:$zn), (nxv8f16 ZPR16:$zm)),
             (!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
 }
@@ -196,7 +196,7 @@
 class sme_add_vector_to_tile_inst<bit op, bit V, MatrixTileOperand tile_ty,
                                   ZPRRegOp zpr_ty, string mnemonic>
     : I<(outs tile_ty:$ZAda),
-        (ins tile_ty:$_ZAda, PPR3bAny:$Pn, PPR3bAny:$Pm, zpr_ty:$Zn),
+        (ins tile_ty:$_ZAda, PPRAny_p0to7:$Pn, PPRAny_p0to7:$Pm, zpr_ty:$Zn),
         mnemonic, "\t$ZAda, $Pn/m, $Pm/m, $Zn",
         "", []>, Sched<[]> {
   bits<3> Pm;
@@ -229,7 +229,7 @@
 
 class sme_add_vector_to_tile_pseudo<ZPRRegOp zpr_ty>
     : Pseudo<(outs),
-             (ins i64imm:$tile, PPR3bAny:$Pn, PPR3bAny:$Pm, zpr_ty:$Zn), []>,
+             (ins i64imm:$tile, PPRAny_p0to7:$Pn, PPRAny_p0to7:$Pm, zpr_ty:$Zn), []>,
       Sched<[]> {
   // Translated to the actual instructions in AArch64ISelLowering.cpp
   let usesCustomInserter = 1;
@@ -239,11 +239,11 @@
 def ADDVA_MPPZ_PSEUDO_S : sme_add_vector_to_tile_pseudo<ZPR32>;
 
 def : Pat<(int_aarch64_sme_addha
-            imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm),
+            imm0_3:$tile, (nxv4i1 PPRAny_p0to7:$pn), (nxv4i1 PPRAny_p0to7:$pm),
             (nxv4i32 ZPR32:$zn)),
           (ADDHA_MPPZ_PSEUDO_S imm0_3:$tile, $pn, $pm, $zn)>;
 def : Pat<(int_aarch64_sme_addva
-            imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm),
+            imm0_3:$tile, (nxv4i1 PPRAny_p0to7:$pn), (nxv4i1 PPRAny_p0to7:$pm),
             (nxv4i32 ZPR32:$zn)),
           (ADDVA_MPPZ_PSEUDO_S imm0_3:$tile, $pn, $pm, $zn)>;
 
@@ -252,11 +252,11 @@
 def ADDVA_MPPZ_PSEUDO_D : sme_add_vector_to_tile_pseudo<ZPR64>;
 
 def : Pat<(int_aarch64_sme_addha
-            imm0_7:$tile, (nxv2i1 PPR3bAny:$pn), (nxv2i1 PPR3bAny:$pm),
+            imm0_7:$tile, (nxv2i1 PPRAny_p0to7:$pn), (nxv2i1 PPRAny_p0to7:$pm),
             (nxv2i64 ZPR64:$zn)),
           (ADDHA_MPPZ_PSEUDO_D imm0_7:$tile, $pn, $pm, $zn)>;
 def : Pat<(int_aarch64_sme_addva
-            imm0_7:$tile, (nxv2i1 PPR3bAny:$pn), (nxv2i1 PPR3bAny:$pm),
+            imm0_7:$tile, (nxv2i1 PPRAny_p0to7:$pn), (nxv2i1 PPRAny_p0to7:$pm),
             (nxv2i64 ZPR64:$zn)),
           (ADDVA_MPPZ_PSEUDO_D imm0_7:$tile, $pn, $pm, $zn)>;
 }
@@ -291,7 +291,7 @@
                          Operand imm_ty, RegisterOperand gpr_ty>
     : sme_mem_ld_ss_base<
         Q, is_col, msz, (outs tile_ty:$ZAt),
-        (ins MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn,
+        (ins MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg, GPR64sp:$Rn,
              gpr_ty:$Rm),
         mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg/z, [$Rn, $Rm]">;
 
@@ -300,12 +300,12 @@
                                    Operand imm_ty, RegisterOperand gpr_ty,
                                    string pg_suffix=""> {
   def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn, $Rm]",
-                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, gpr_ty:$Rm), 0>;
+                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gpr_ty:$Rm), 0>;
   // Default XZR offset aliases
   def : InstAlias<mnemonic # "\t\\{$ZAt[$Rv, $imm]\\}, $Pg" # pg_suffix # ", [$Rn]",
-                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>;
+                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg, GPR64sp:$Rn, XZR), 1>;
   def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn]",
-                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>;
+                  (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg, GPR64sp:$Rn, XZR), 0>;
 }
 
 multiclass sme_mem_ss_aliases<string mnemonic, string inst, bit is_col,
@@ -336,13 +336,13 @@
                                   ComplexPattern addr,
                                   ComplexPattern tileslice> {
   // base, tileslice
-  def : Pat<(Load PPR3bAny:$pg, GPR64sp:$base, tile_ty:$tile,
+  def : Pat<(Load PPRAny_p0to7:$pg, GPR64sp:$base, tile_ty:$tile,
                   (i32 (tileslice MatrixIndexGPR32Op12_15:$idx, offset_ty:$imm))),
             (Inst tile_ty:$tile, $idx, $imm, $pg, $base, XZR)>;
 
   // reg + reg, tileslice
   let AddedComplexity = 1 in {
-    def : Pat<(Load PPR3bAny:$pg, (addr GPR64sp:$base, GPR64:$offset),
+    def : Pat<(Load PPRAny_p0to7:$pg, (addr GPR64sp:$base, GPR64:$offset),
                     tile_ty:$tile, (i32 (tileslice MatrixIndexGPR32Op12_15:$idx,
                                               offset_ty:$imm))),
               (Inst tile_ty:$tile, $idx, $imm, $pg, $base, $offset)>;
@@ -351,7 +351,7 @@
 
 class sme_load_pseudo
     : Pseudo<(outs), (ins i64imm:$tile, MatrixIndexGPR32Op12_15:$idx,
-                          i64imm:$imm, PPR3bAny:$pg, GPR64sp:$base, GPR64:$offset), []>,
+                          i64imm:$imm, PPRAny_p0to7:$pg, GPR64sp:$base, GPR64:$offset), []>,
       Sched<[]> {
   // Translated to the actual instructions in AArch64ISelLowering.cpp
   let usesCustomInserter = 1;
@@ -469,7 +469,7 @@
                          Operand imm_ty, RegisterOperand gpr_ty>
     : sme_mem_st_ss_base<
         Q, is_col, msz,
-        (ins tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg,
+        (ins tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg,
              GPR64sp:$Rn, gpr_ty:$Rm),
         mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg, [$Rn, $Rm]">;
 
@@ -483,13 +483,13 @@
                                   ComplexPattern addr,
                                   ComplexPattern tileslice> {
   // base, tileslice
-  def : Pat<(Store PPR3bAny:$pg, GPR64sp:$base, (imm2tile untyped:$tile),
+  def : Pat<(Store PPRAny_p0to7:$pg, GPR64sp:$base, (imm2tile untyped:$tile),
                    (i32 (tileslice MatrixIndexGPR32Op12_15:$idx, offset_ty:$imm))),
             (Inst $tile, $idx, $imm, $pg, $base, XZR)>;
 
   // reg + reg, tileslice
   let AddedComplexity = 1 in {
-    def : Pat<(Store PPR3bAny:$pg, (addr GPR64sp:$base, GPR64:$offset),
+    def : Pat<(Store PPRAny_p0to7:$pg, (addr GPR64sp:$base, GPR64:$offset),
                      (imm2tile untyped:$tile),
                      (i32 (tileslice MatrixIndexGPR32Op12_15:$idx, offset_ty:$imm))),
               (Inst $tile, $idx, $imm, $pg, $base, $offset)>;
@@ -669,7 +669,7 @@
                               bit is_col, Operand imm_ty, ZPRRegOp zpr_ty,
                               string mnemonic>
     : sme_vector_to_tile_base<Q, is_col, sz, (outs tile_ty:$ZAd),
-        (ins tile_ty:$_ZAd, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, zpr_ty:$Zn),
+        (ins tile_ty:$_ZAd, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg, zpr_ty:$Zn),
         mnemonic, "\t$ZAd[$Rv, $imm], $Pg/m, $Zn">{
 
   let Constraints = "$ZAd = $_ZAd";
@@ -680,7 +680,7 @@
                                       MatrixTileVectorOperand tile_ty,
                                       ZPRRegOp zpr_ty, Operand imm_ty> {
   def : InstAlias<"mov\t$ZAd[$Rv, $imm], $Pg/m, $Zn",
-                  (inst tile_ty:$ZAd, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, zpr_ty:$Zn), 1>;
+                  (inst tile_ty:$ZAd, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPRAny_p0to7:$Pg, zpr_ty:$Zn), 1>;
 }
 
 multiclass sme_vector_to_tile_patterns<Instruction inst, ValueType zpr_vt,
@@ -689,19 +689,19 @@
                                        SDPatternOperator op,
                                        ComplexPattern tileslice> {
   def : Pat<(op imm_ty:$tile, MatrixIndexGPR32Op12_15:$idx,
-                (ppr_vt PPR3bAny:$pg), (zpr_vt ZPRAny:$zn)),
+                (ppr_vt PPRAny_p0to7:$pg), (zpr_vt ZPRAny:$zn)),
             (inst imm_ty:$tile, $idx, 0, $pg, $zn)>;
   let AddedComplexity = 1 in {
     def : Pat<(op imm_ty:$tile, (i32 (tileslice MatrixIndexGPR32Op12_15:$idx,
                                                 offset_ty:$imm)),
-                  (ppr_vt PPR3bAny:$pg), (zpr_vt ZPRAny:$zn)),
+                  (ppr_vt PPRAny_p0to7:$pg), (zpr_vt ZPRAny:$zn)),
               (inst imm_ty:$tile, $idx, $imm, $pg, $zn)>;
   }
 }
 
 class sme_mova_insert_pseudo
     : Pseudo<(outs), (ins i64imm:$tile, MatrixIndexGPR32Op12_15:$idx,
-                          i64imm:$imm, PPR3bAny:$pg, ZPRAny:$zn), []>,
+                          i64imm:$imm, PPRAny_p0to7:$pg, ZPRAny:$zn), []>,
       Sched<[]> {
   // Translated to the actual instructions in AArch64ISelLowering.cpp
   let usesCustomInserter = 1;
@@ -858,7 +858,7 @@
                               MatrixTileVectorOperand tile_ty,
                               bit is_col, Operand imm_ty, string mnemonic>
     : sme_tile_to_vector_base<Q, is_col, sz, (outs zpr_ty:$Zd),
-        (ins zpr_ty:$_Zd, PPR3bAny:$Pg, tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm),
+        (ins zpr_ty:$_Zd, PPRAny_p0to7:$Pg, tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm),
         mnemonic, "\t$Zd, $Pg/m, $ZAn[$Rv, $imm]"> {
 
   let Constraints = "$Zd = $_Zd";
@@ -868,7 +868,7 @@
                                       MatrixTileVectorOperand tile_ty,
                                       Operand imm_ty > {
   def : InstAlias<"mov\t$Zd, $Pg/m, $ZAn[$Rv, $imm]",
-                  (inst zpr_ty:$Zd, PPR3bAny:$Pg, tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm), 1>;
+                  (inst zpr_ty:$Zd, PPRAny_p0to7:$Pg, tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm), 1>;
 }
 
 multiclass sme_tile_to_vector_patterns<Instruction inst, ValueType zpr_vt,
@@ -876,11 +876,11 @@
                                        ComplexPattern imm2tile,
                                        ComplexPattern tileslice,
                                        SDPatternOperator op> {
-  def : Pat<(zpr_vt (op (zpr_vt ZPRAny:$passthru), (ppr_vt PPR3bAny:$pg),
+  def : Pat<(zpr_vt (op (zpr_vt ZPRAny:$passthru), (ppr_vt PPRAny_p0to7:$pg),
                         (imm2tile untyped:$tile), MatrixIndexGPR32Op12_15:$idx)),
             (inst $passthru, $pg, $tile, $idx, 0)>;
   let AddedComplexity = 1 in {
-    def : Pat<(zpr_vt (op (zpr_vt ZPRAny:$passthru), (ppr_vt PPR3bAny:$pg),
+    def : Pat<(zpr_vt (op (zpr_vt ZPRAny:$passthru), (ppr_vt PPRAny_p0to7:$pg),
                           (imm2tile untyped:$tile),
                           (i32 (tileslice MatrixIndexGPR32Op12_15:$idx,
                                           offset_ty:$imm)))),
@@ -1053,7 +1053,7 @@
 //===----------------------------------------------------------------------===//
 
 class sve2_int_perm_revd<string asm>
-    : I<(outs ZPR128:$Zd), (ins ZPR128:$_Zd, PPR3bAny:$Pg, ZPR128:$Zn),
+    : I<(outs ZPR128:$Zd), (ins ZPR128:$_Zd, PPRAny_p0to7:$Pg, ZPR128:$Zn),
         asm, "\t$Zd, $Pg/m, $Zn", "", []>,
       Sched<[]> {
   bits<5> Zd;
Index: llvm/lib/Target/AArch64/SVEInstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -509,7 +509,7 @@
                           ValueType pt, ValueType it,
                           FPImmLeaf immL, int imm,
                           Instruction inst>
-: Pat<(vt (op (pt PPR_3b:$Pg), (vt ZPR:$Zs1), (vt (splat_vector (it immL))))),
+: Pat<(vt (op (pt PPR_p0to7:$Pg), (vt ZPR:$Zs1), (vt (splat_vector (it immL))))),
       (inst $Pg, $Zs1, imm)>;
 
 class SVE_2_Op_Fp_Imm_Pat_Zero<ValueType vt, SDPatternOperator op,
@@ -590,21 +590,21 @@
   class PredTwoOpPseudo<string name, ZPRRegOp zprty,
                         FalseLanesEnum flags = FalseLanesNone>
   : SVEPseudo2Instr<name, 0>,
-    Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2), []> {
+    Pseudo<(outs zprty:$Zd), (ins PPRAny_p0to7:$Pg, zprty:$Zs1, zprty:$Zs2), []> {
     let FalseLanes = flags;
   }
 
   class PredTwoOpImmPseudo<string name, ZPRRegOp zprty, Operand immty,
                            FalseLanesEnum flags = FalseLanesNone>
   : SVEPseudo2Instr<name, 0>,
-    Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, immty:$imm), []> {
+    Pseudo<(outs zprty:$Zd), (ins PPRAny_p0to7:$Pg, zprty:$Zs1, immty:$imm), []> {
     let FalseLanes = flags;
   }
 
   class PredThreeOpPseudo<string name, ZPRRegOp zprty,
                           FalseLanesEnum flags = FalseLanesNone>
   : SVEPseudo2Instr<name, 0>,
-    Pseudo<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zs1, zprty:$Zs2, zprty:$Zs3), []> {
+    Pseudo<(outs zprty:$Zd), (ins PPRAny_p0to7:$Pg, zprty:$Zs1, zprty:$Zs2, zprty:$Zs3), []> {
     let FalseLanes = flags;
   }
 }
@@ -615,7 +615,7 @@
 let hasNoSchedulingInfo = 1 in {
   class PredOneOpPassthruPseudo<string name, ZPRRegOp zprty>
   : SVEPseudo2Instr<name, 0>,
-    Pseudo<(outs zprty:$Zd), (ins zprty:$Passthru, PPR3bAny:$Pg, zprty:$Zs), []>;
+    Pseudo<(outs zprty:$Zd), (ins zprty:$Passthru, PPRAny_p0to7:$Pg, zprty:$Zs), []>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -1851,7 +1851,7 @@
 class sve_fp_2op_i_p_zds<bits<2> sz, bits<3> opc, string asm,
                          ZPRRegOp zprty,
                          Operand imm_ty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, imm_ty:$i1),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, imm_ty:$i1),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $i1",
   "",
   []>, Sched<[]> {
@@ -1890,7 +1890,7 @@
 
 class sve_fp_2op_p_zds<bits<2> sz, bits<4> opc, string asm,
                        ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
   "",
   []>, Sched<[]> {
@@ -2069,7 +2069,7 @@
 //===----------------------------------------------------------------------===//
 
 class sve_fp_3op_p_zds_a<bits<2> sz, bits<2> opc, string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
+: I<(outs zprty:$Zda), (ins PPRAny_p0to7:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
   asm, "\t$Zda, $Pg/m, $Zn, $Zm",
   "",
   []>, Sched<[]> {
@@ -2110,7 +2110,7 @@
 
 class sve_fp_3op_p_zds_b<bits<2> sz, bits<2> opc, string asm,
                          ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
   asm, "\t$Zdn, $Pg/m, $Zm, $Za",
   "",
   []>, Sched<[]> {
@@ -2260,7 +2260,7 @@
 //===----------------------------------------------------------------------===//
 
 class sve_fp_fcmla<bits<2> sz, string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm,
+: I<(outs zprty:$Zda), (ins PPRAny_p0to7:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm,
                         complexrotateop:$imm),
   asm, "\t$Zda, $Pg/m, $Zn, $Zm, $imm",
   "", []>, Sched<[]> {
@@ -2349,7 +2349,7 @@
 //===----------------------------------------------------------------------===//
 
 class sve_fp_fcadd<bits<2> sz, string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm,
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm,
                         complexrotateopodd:$imm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm, $imm",
   "",
@@ -2391,7 +2391,7 @@
 
 class sve2_fp_convert_precision<bits<4> opc, string asm,
                                 ZPRRegOp zprty1, ZPRRegOp zprty2>
-: I<(outs zprty1:$Zd), (ins zprty1:$_Zd, PPR3bAny:$Pg, zprty2:$Zn),
+: I<(outs zprty1:$Zd), (ins zprty1:$_Zd, PPRAny_p0to7:$Pg, zprty2:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn",
   "",
   []>, Sched<[]> {
@@ -2438,7 +2438,7 @@
 
 class sve2_fp_pairwise_pred<bits<2> sz, bits<3> opc, string asm,
                             ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
   "",
   []>, Sched<[]> {
@@ -2629,7 +2629,7 @@
 
 class sve_fp_2op_p_zd<bits<7> opc, string asm, RegisterOperand i_zprtype,
                       RegisterOperand o_zprtype, ElementSizeEnum Sz>
-: I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPR3bAny:$Pg, i_zprtype:$Zn),
+: I<(outs o_zprtype:$Zd), (ins i_zprtype:$_Zd, PPRAny_p0to7:$Pg, i_zprtype:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn",
   "",
   []>, Sched<[]> {
@@ -2780,7 +2780,7 @@
 
 class sve_int_bin_pred_arit_log<bits<2> sz8_64, bits<2> fmt, bits<3> opc,
                                 string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zdn;
@@ -2903,7 +2903,7 @@
 
 class sve_int_mladdsub_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm,
                                 ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm, zprty:$Za),
   asm, "\t$Zdn, $Pg/m, $Zm, $Za",
   "",
   []>, Sched<[]> {
@@ -2940,7 +2940,7 @@
 
 class sve_int_mlas_vvv_pred<bits<2> sz8_64, bits<1> opc, string asm,
                             ZPRRegOp zprty>
-: I<(outs zprty:$Zda), (ins PPR3bAny:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
+: I<(outs zprty:$Zda), (ins PPRAny_p0to7:$Pg, zprty:$_Zda, zprty:$Zn, zprty:$Zm),
   asm, "\t$Zda, $Pg/m, $Zn, $Zm",
   "",
   []>, Sched<[]> {
@@ -3425,7 +3425,7 @@
 
 class sve2_int_arith_pred<bits<2> sz, bits<6> opc, string asm,
                           ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm", "", []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zm;
@@ -3468,7 +3468,7 @@
 
 class sve2_int_sadd_long_accum_pairwise<bits<2> sz, bit U, string asm,
                                         ZPRRegOp zprty1, ZPRRegOp zprty2>
-: I<(outs zprty1:$Zda), (ins PPR3bAny:$Pg, zprty1:$_Zda, zprty2:$Zn),
+: I<(outs zprty1:$Zda), (ins PPRAny_p0to7:$Pg, zprty1:$_Zda, zprty2:$Zn),
   asm, "\t$Zda, $Pg/m, $Zn", "", []>, Sched<[]> {
   bits<3> Pg;
   bits<5> Zn;
@@ -3499,7 +3499,7 @@
 
 class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc,
                             string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn",
   "",
   []>, Sched<[]> {
@@ -4146,7 +4146,7 @@
 
 class sve_int_un_pred_arit<bits<2> sz8_64, bits<4> opc,
                              string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn",
   "",
   []>, Sched<[]> {
@@ -4729,7 +4729,7 @@
 
 class sve_int_cmp<bit cmp_1, bits<2> sz8_64, bits<3> opc, string asm,
                   PPRRegOp pprty, ZPRRegOp zprty1, ZPRRegOp zprty2>
-: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty1:$Zn, zprty2:$Zm),
+: I<(outs pprty:$Pd), (ins PPRAny_p0to7:$Pg, zprty1:$Zn, zprty2:$Zm),
   asm, "\t$Pd, $Pg/z, $Zn, $Zm",
   "",
   []>, Sched<[]> {
@@ -4818,7 +4818,7 @@
 class sve_int_scmp_vi<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
                       ZPRRegOp zprty,
                       Operand immtype>
-: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm5),
+: I<(outs pprty:$Pd), (ins PPRAny_p0to7:$Pg, zprty:$Zn, immtype:$imm5),
   asm, "\t$Pd, $Pg/z, $Zn, $imm5",
   "",
   []>, Sched<[]> {
@@ -4846,12 +4846,12 @@
 multiclass SVE_SETCC_Imm_Pat<CondCode cc, CondCode commuted_cc,
                              ValueType predvt, ValueType intvt,
                              Operand immtype, Instruction cmp> {
-  def : Pat<(predvt (AArch64setcc_z (predvt PPR_3b:$Pg),
+  def : Pat<(predvt (AArch64setcc_z (predvt PPR_p0to7:$Pg),
                                     (intvt ZPR:$Zs1),
                                     (intvt (splat_vector (immtype:$imm))),
                                     cc)),
             (cmp $Pg, $Zs1, immtype:$imm)>;
-  def : Pat<(predvt (AArch64setcc_z (predvt PPR_3b:$Pg),
+  def : Pat<(predvt (AArch64setcc_z (predvt PPR_p0to7:$Pg),
                                     (intvt (splat_vector (immtype:$imm))),
                                     (intvt ZPR:$Zs1),
                                     commuted_cc)),
@@ -4893,7 +4893,7 @@
 
 class sve_int_ucmp_vi<bits<2> sz8_64, bits<2> opc, string asm, PPRRegOp pprty,
                       ZPRRegOp zprty, Operand immtype>
-: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, immtype:$imm7),
+: I<(outs pprty:$Pd), (ins PPRAny_p0to7:$Pg, zprty:$Zn, immtype:$imm7),
   asm, "\t$Pd, $Pg/z, $Zn, $imm7",
   "",
   []>, Sched<[]> {
@@ -5044,7 +5044,7 @@
 
 class sve_fp_fast_red<bits<2> sz, bits<3> opc, string asm,
                       ZPRRegOp zprty, FPRasZPROperand dstOpType>
-: I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs dstOpType:$Vd), (ins PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Vd, $Pg, $Zn",
   "",
   []>, Sched<[]> {
@@ -5080,7 +5080,7 @@
 
 class sve_fp_2op_p_vd<bits<2> sz, bits<3> opc, string asm,
                       ZPRRegOp zprty, FPRasZPROperand dstOpType>
-: I<(outs dstOpType:$Vdn), (ins PPR3bAny:$Pg, dstOpType:$_Vdn, zprty:$Zm),
+: I<(outs dstOpType:$Vdn), (ins PPRAny_p0to7:$Pg, dstOpType:$_Vdn, zprty:$Zm),
   asm, "\t$Vdn, $Pg, $_Vdn, $Zm",
   "",
   []>,
@@ -5119,7 +5119,7 @@
 
 class sve_fp_3op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty,
                       ZPRRegOp zprty>
-: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
+: I<(outs pprty:$Pd), (ins PPRAny_p0to7:$Pg, zprty:$Zn, zprty:$Zm),
   asm, "\t$Pd, $Pg/z, $Zn, $Zm",
   "",
   []>, Sched<[]> {
@@ -5178,7 +5178,7 @@
 
 class sve_fp_2op_p_pd<bits<2> sz, bits<3> opc, string asm, PPRRegOp pprty,
                       ZPRRegOp zprty>
-: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs pprty:$Pd), (ins PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Pd, $Pg/z, $Zn, #0.0",
   "",
   []>, Sched<[]> {
@@ -5429,7 +5429,7 @@
 
 class sve_int_bin_pred_shift_imm<bits<4> tsz8_64, bits<4> opc, string asm,
                                  ZPRRegOp zprty, Operand immtype>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, immtype:$imm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, immtype:$imm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $imm",
   "",
   []>, Sched<[]> {
@@ -5545,7 +5545,7 @@
 
 class sve_int_bin_pred_shift<bits<2> sz8_64, bit wide, bits<3> opc,
                              string asm, ZPRRegOp zprty, ZPRRegOp zprty2>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty2:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty2:$Zm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
   "",
   []>, Sched<[]> {
@@ -5707,7 +5707,7 @@
 
 class sve_mem_cst_si<bits<2> msz, bits<2> esz, string asm,
                      RegisterOperand VecList>
-: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
+: I<(outs), (ins VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
   asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
   "",
   []>, Sched<[]> {
@@ -5734,16 +5734,16 @@
   def NAME : sve_mem_cst_si<msz, esz, asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
-                 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
+                 (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
-                  (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_est_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                      string asm, Operand immtype>
-: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),
+: I<(outs), (ins VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, immtype:$imm4),
   asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
   "",
   []>, Sched<[]> {
@@ -5769,12 +5769,12 @@
   def NAME : sve_mem_est_si<sz, nregs, VecList, asm, immtype>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
-                  (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_est_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                      string asm, RegisterOperand gprty>
-: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs), (ins VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
@@ -5796,7 +5796,7 @@
 
 class sve_mem_cst_ss_base<bits<4> dtype, string asm,
                           RegisterOperand listty, RegisterOperand gprty>
-: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs), (ins listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
@@ -5821,11 +5821,11 @@
   def NAME : sve_mem_cst_ss_base<dtype, asm, listty, gprty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 }
 
 class sve_mem_cstnt_si<bits<2> msz, string asm, RegisterOperand VecList>
-: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
+: I<(outs), (ins VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
   asm, "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
   "",
   []>, Sched<[]> {
@@ -5850,16 +5850,16 @@
   def NAME : sve_mem_cstnt_si<msz, asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $imm4, mul vl]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn]",
-                  (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_cstnt_ss_base<bits<2> msz, string asm, RegisterOperand listty,
                             RegisterOperand gprty>
-: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs), (ins listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
@@ -5884,12 +5884,12 @@
   def NAME : sve_mem_cstnt_ss_base<msz, asm, listty, gprty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
-                 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                 (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 }
 
 class sve2_mem_sstnt_vs_base<bits<3> opc, string asm,
                              RegisterOperand listty, ZPRRegOp zprty>
-: I<(outs), (ins listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm),
+: I<(outs), (ins listty:$Zt, PPRAny_p0to7:$Pg, zprty:$Zn, GPR64:$Rm),
   asm, "\t$Zt, $Pg, [$Zn, $Rm]",
   "",
   []>, Sched<[]> {
@@ -5915,14 +5915,14 @@
   def _REAL : sve2_mem_sstnt_vs_base<opc, asm, Z_s, ZPR32>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $Rm]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, GPR64:$Rm), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, GPR64:$Rm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, XZR), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR), 1>;
+                 (!cast<Instruction>(NAME # _REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, XZR), 1>;
 
-  def : Pat <(op (nxv4i32 ZPR32:$Zt), (nxv4i1 PPR3bAny:$Pg), (nxv4i32 ZPR32:$Zn), (i64 GPR64:$Rm), vt),
-             (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, GPR64:$Rm)>;
+  def : Pat <(op (nxv4i32 ZPR32:$Zt), (nxv4i1 PPRAny_p0to7:$Pg), (nxv4i32 ZPR32:$Zn), (i64 GPR64:$Rm), vt),
+             (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, GPR64:$Rm)>;
 }
 
 multiclass sve2_mem_sstnt_vs_64_ptrs<bits<3> opc, string asm,
@@ -5931,19 +5931,19 @@
   def _REAL : sve2_mem_sstnt_vs_base<opc, asm, Z_d, ZPR64>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $Rm]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, GPR64:$Rm), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, GPR64:$Rm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, XZR), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR), 1>;
+                 (!cast<Instruction>(NAME # _REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, XZR), 1>;
 
-  def : Pat <(op (nxv2i64 ZPR64:$Zt), (nxv2i1 PPR3bAny:$Pg), (nxv2i64 ZPR64:$Zn), (i64 GPR64:$Rm), vt),
-             (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, GPR64:$Rm)>;
+  def : Pat <(op (nxv2i64 ZPR64:$Zt), (nxv2i1 PPRAny_p0to7:$Pg), (nxv2i64 ZPR64:$Zn), (i64 GPR64:$Rm), vt),
+             (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, GPR64:$Rm)>;
 }
 
 class sve_mem_sst_sv<bits<3> opc, bit xs, bit scaled, string asm,
                      RegisterOperand VecList, RegisterOperand zprext>
-: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+: I<(outs), (ins VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm),
   asm, "\t$Zt, $Pg, [$Rn, $Zm]",
   "",
   []>, Sched<[]> {
@@ -5975,9 +5975,9 @@
   def _SXTW_SCALED : sve_mem_sst_sv<opc, 1, 1, asm, Z_s, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   def : Pat<(uxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
@@ -5995,9 +5995,9 @@
   def _SXTW_SCALED : sve_mem_sst_sv<opc, 1, 1, asm, Z_d, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _SXTW_SCALED) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   def : Pat<(uxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
@@ -6015,9 +6015,9 @@
   def _SXTW : sve_mem_sst_sv<opc, 1, 0, asm, Z_d, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _UXTW) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _UXTW) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _SXTW) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _SXTW) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   def : Pat<(uxtw_op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME # _UXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
@@ -6035,9 +6035,9 @@
   def _SXTW : sve_mem_sst_sv<opc, 1, 0, asm, Z_s, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _UXTW) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _UXTW) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _SXTW) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _SXTW) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   def : Pat<(uxtw_op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME # _UXTW) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
@@ -6047,7 +6047,7 @@
 
 class sve_mem_sst_sv2<bits<2> msz, bit scaled, string asm,
                       RegisterOperand zprext>
-: I<(outs), (ins Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+: I<(outs), (ins Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm),
   asm, "\t$Zt, $Pg, [$Rn, $Zm]",
   "",
   []>, Sched<[]> {
@@ -6075,7 +6075,7 @@
   def _SCALED : sve_mem_sst_sv2<msz, 1, asm, zprext>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME # _SCALED) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
+                 (!cast<Instruction>(NAME # _SCALED) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
 
   def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$indices), vt),
             (!cast<Instruction>(NAME # _SCALED) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$indices)>;
@@ -6087,7 +6087,7 @@
   def NAME : sve_mem_sst_sv2<msz, 0, asm, ZPR64ExtLSL8>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Zm]",
-                 (!cast<Instruction>(NAME) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
+                 (!cast<Instruction>(NAME) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
 
   def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt),
             (!cast<Instruction>(NAME) ZPR:$data, PPR:$gp, GPR64sp:$base, ZPR:$offsets)>;
@@ -6095,7 +6095,7 @@
 
 class sve_mem_sst_vi<bits<3> opc, string asm, ZPRRegOp zprty,
                      RegisterOperand VecList, Operand imm_ty>
-: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, zprty:$Zn, imm_ty:$imm5),
+: I<(outs), (ins VecList:$Zt, PPRAny_p0to7:$Pg, zprty:$Zn, imm_ty:$imm5),
   asm, "\t$Zt, $Pg, [$Zn, $imm5]",
   "",
   []>, Sched<[]> {
@@ -6123,11 +6123,11 @@
   def _IMM : sve_mem_sst_vi<opc, asm, ZPR32, Z_s, imm_ty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 0>;
+                  (!cast<Instruction>(NAME # _IMM) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]",
-                  (!cast<Instruction>(NAME # _IMM) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
+                  (!cast<Instruction>(NAME # _IMM) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
+                  (!cast<Instruction>(NAME # _IMM) Z_s:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, 0), 1>;
 
   def : Pat<(op (nxv4i32 ZPR:$data), (nxv4i1 PPR:$gp), (nxv4i32 ZPR:$ptrs), imm_ty:$index, vt),
             (!cast<Instruction>(NAME # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
@@ -6140,11 +6140,11 @@
   def _IMM : sve_mem_sst_vi<opc, asm, ZPR64, Z_d, imm_ty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
+                  (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]",
-                  (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
+                  (!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
+                  (!cast<Instruction>(NAME # _IMM) Z_d:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, 0), 1>;
 
   def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt),
             (!cast<Instruction>(NAME # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;
@@ -6344,7 +6344,7 @@
 
 class sve_int_perm_clast_rz<bits<2> sz8_64, bit ab, string asm,
                             ZPRRegOp zprty, RegisterClass rt>
-: I<(outs rt:$Rdn), (ins PPR3bAny:$Pg, rt:$_Rdn, zprty:$Zm),
+: I<(outs rt:$Rdn), (ins PPRAny_p0to7:$Pg, rt:$_Rdn, zprty:$Zm),
   asm, "\t$Rdn, $Pg, $_Rdn, $Zm",
   "",
   []>, Sched<[]> {
@@ -6377,7 +6377,7 @@
 
 class sve_int_perm_clast_vz<bits<2> sz8_64, bit ab, string asm,
                             ZPRRegOp zprty, RegisterClass rt>
-: I<(outs rt:$Vdn), (ins PPR3bAny:$Pg, rt:$_Vdn, zprty:$Zm),
+: I<(outs rt:$Vdn), (ins PPRAny_p0to7:$Pg, rt:$_Vdn, zprty:$Zm),
   asm, "\t$Vdn, $Pg, $_Vdn, $Zm",
   "",
   []>, Sched<[]> {
@@ -6411,7 +6411,7 @@
 
 class sve_int_perm_clast_zz<bits<2> sz8_64, bit ab, string asm,
                             ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm),
   asm, "\t$Zdn, $Pg, $_Zdn, $Zm",
   "",
   []>, Sched<[]> {
@@ -6452,7 +6452,7 @@
 
 class sve_int_perm_last_r<bits<2> sz8_64, bit ab, string asm,
                           ZPRRegOp zprty, RegisterClass resultRegType>
-: I<(outs resultRegType:$Rd), (ins PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs resultRegType:$Rd), (ins PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Rd, $Pg, $Zn",
   "",
   []>, Sched<[]> {
@@ -6483,7 +6483,7 @@
 
 class sve_int_perm_last_v<bits<2> sz8_64, bit ab, string asm,
                           ZPRRegOp zprty, RegisterClass dstRegtype>
-: I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs dstRegtype:$Vd), (ins PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Vd, $Pg, $Zn",
   "",
   []>, Sched<[]> {
@@ -6515,7 +6515,7 @@
 }
 
 class sve_int_perm_splice<bits<2> sz8_64, string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+: I<(outs zprty:$Zdn), (ins PPRAny_p0to7:$Pg, zprty:$_Zdn, zprty:$Zm),
   asm, "\t$Zdn, $Pg, $_Zdn, $Zm",
   "",
   []>, Sched<[]> {
@@ -6554,7 +6554,7 @@
 
 class sve2_int_perm_splice_cons<bits<2> sz8_64, string asm,
                                ZPRRegOp zprty, RegisterOperand VecList>
-: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, VecList:$Zn),
+: I<(outs zprty:$Zd), (ins PPRAny_p0to7:$Pg, VecList:$Zn),
   asm, "\t$Zd, $Pg, $Zn",
   "",
   []>, Sched<[]> {
@@ -6578,7 +6578,7 @@
 
 class sve_int_perm_rev<bits<2> sz8_64, bits<2> opc, string asm,
                        ZPRRegOp zprty>
-: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn",
   "",
   []>, Sched<[]> {
@@ -6637,7 +6637,7 @@
 
 class sve_int_perm_cpy_r<bits<2> sz8_64, string asm, ZPRRegOp zprty,
                          RegisterClass srcRegType>
-: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegType:$Rn),
+: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny_p0to7:$Pg, srcRegType:$Rn),
   asm, "\t$Zd, $Pg/m, $Rn",
   "",
   []>, Sched<[]> {
@@ -6663,13 +6663,13 @@
   def _D : sve_int_perm_cpy_r<0b11, asm, ZPR64, GPR64sp>;
 
   def : InstAlias<"mov $Zd, $Pg/m, $Rn",
-                  (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
+                  (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny_p0to7:$Pg, GPR32sp:$Rn), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Rn",
-                  (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
+                  (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny_p0to7:$Pg, GPR32sp:$Rn), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Rn",
-                  (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn), 1>;
+                  (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny_p0to7:$Pg, GPR32sp:$Rn), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Rn",
-                  (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn), 1>;
+                  (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny_p0to7:$Pg, GPR64sp:$Rn), 1>;
 
   def : Pat<(nxv16i8 (op nxv16i1:$pg, i32:$splat, nxv16i8:$passthru)),
             (!cast<Instruction>(NAME # _B) $passthru, $pg, $splat)>;
@@ -6683,7 +6683,7 @@
 
 class sve_int_perm_cpy_v<bits<2> sz8_64, string asm, ZPRRegOp zprty,
                          RegisterClass srcRegtype>
-: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, srcRegtype:$Vn),
+: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPRAny_p0to7:$Pg, srcRegtype:$Vn),
   asm, "\t$Zd, $Pg/m, $Vn",
   "",
   []>, Sched<[]> {
@@ -6709,13 +6709,13 @@
   def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>;
 
   def : InstAlias<"mov $Zd, $Pg/m, $Vn",
-                  (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>;
+                  (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPRAny_p0to7:$Pg, FPR8:$Vn), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Vn",
-                  (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn), 1>;
+                  (!cast<Instruction>(NAME # _H) ZPR16:$Zd, PPRAny_p0to7:$Pg, FPR16:$Vn), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Vn",
-                  (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn), 1>;
+                  (!cast<Instruction>(NAME # _S) ZPR32:$Zd, PPRAny_p0to7:$Pg, FPR32:$Vn), 1>;
   def : InstAlias<"mov $Zd, $Pg/m, $Vn",
-                  (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn), 1>;
+                  (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPRAny_p0to7:$Pg, FPR64:$Vn), 1>;
 
   def : Pat<(nxv8f16 (op nxv8i1:$pg, f16:$splat, nxv8f16:$passthru)),
             (!cast<Instruction>(NAME # _H) $passthru, $pg, $splat)>;
@@ -6731,7 +6731,7 @@
 }
 
 class sve_int_perm_compact<bit sz, string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs zprty:$Zd), (ins PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Zd, $Pg, $Zn",
   "",
   []>, Sched<[]> {
@@ -6762,7 +6762,7 @@
 
 class sve_mem_cld_si_base<bits<4> dtype, bit nf, string asm,
                           RegisterOperand VecList>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
   "",
   []>, Sched<[]> {
@@ -6789,17 +6789,17 @@
   def _REAL : sve_mem_cld_si_base<dtype, nf, asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
-                  (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
+                  (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1, mayLoad = 1 in {
-  def "" : Pseudo<(outs listty:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), []>,
-           PseudoInstExpansion<(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4)>;
+  def "" : Pseudo<(outs listty:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4), []>,
+           PseudoInstExpansion<(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4)>;
   }
 }
 
@@ -6808,7 +6808,7 @@
 : sve_mem_cld_si_base<dtype, 0, asm, listty, zprty>;
 
 class sve_mem_cldnt_si_base<bits<2> msz, string asm, RegisterOperand VecList>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
   "",
   []>, Sched<[]> {
@@ -6833,16 +6833,16 @@
   def NAME : sve_mem_cldnt_si_base<msz, asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s1:$imm4), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_cldnt_ss_base<bits<2> msz, string asm, RegisterOperand VecList,
                             RegisterOperand gprty>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
@@ -6867,11 +6867,11 @@
   def NAME : sve_mem_cldnt_ss_base<msz, asm, listty, gprty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
-                 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                 (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 }
 
 class sve_mem_ldqr_si<bits<2> sz, string asm, RegisterOperand VecList>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s16:$imm4),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm4]", "", []>, Sched<[]> {
   bits<5> Zt;
   bits<5> Rn;
@@ -6893,16 +6893,16 @@
                            ZPRRegOp zprty> {
   def NAME : sve_mem_ldqr_si<sz, asm, listty>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s16:$imm4), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s16:$imm4), 0>;
 }
 
 class sve_mem_ldqr_ss<bits<2> sz, string asm, RegisterOperand VecList,
                       RegisterOperand gprty>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", []>, Sched<[]> {
   bits<5> Zt;
   bits<3> Pg;
@@ -6925,12 +6925,12 @@
   def NAME : sve_mem_ldqr_ss<sz, asm, listty, gprty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 }
 
 class sve_mem_ld_dup<bits<2> dtypeh, bits<2> dtypel, string asm,
                      RegisterOperand VecList, Operand immtype>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, immtype:$imm6),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm6]",
   "",
   []>, Sched<[]> {
@@ -6956,11 +6956,11 @@
   def NAME : sve_mem_ld_dup<dtypeh, dtypel, asm, zlistty, immtype>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm6]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm6), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, immtype:$imm6), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) zlistty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) zlistty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_cld_ss_base<bits<4> dtype, bit ff, dag iops, string asm,
@@ -6989,32 +6989,32 @@
 
 multiclass sve_mem_cld_ss<bits<4> dtype, string asm, RegisterOperand listty,
                           ZPRRegOp zprty, RegisterOperand gprty> {
-  def "" : sve_mem_cld_ss_base<dtype, 0, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+  def "" : sve_mem_cld_ss_base<dtype, 0, (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
                                asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
-                 (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                 (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 }
 
 multiclass sve_mem_cldff_ss<bits<4> dtype, string asm, RegisterOperand listty,
                             ZPRRegOp zprty, RegisterOperand gprty> {
-  def _REAL : sve_mem_cld_ss_base<dtype, 1, (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+  def _REAL : sve_mem_cld_ss_base<dtype, 1, (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
                                   asm, listty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
-                 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>;
+                 (!cast<Instruction>(NAME # _REAL) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, XZR), 1>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>;
+                 (!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, XZR), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def "" : Pseudo<(outs listty:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), []>,
-           PseudoInstExpansion<(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm)>;
+  def "" : Pseudo<(outs listty:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), []>,
+           PseudoInstExpansion<(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm)>;
   }
 }
 
@@ -7024,7 +7024,7 @@
 
 class sve_mem_eld_si<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                      string asm, Operand immtype>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, immtype:$imm4),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, immtype:$imm4),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
   "",
   []>, Sched<[]> {
@@ -7050,12 +7050,12 @@
   def NAME : sve_mem_eld_si<sz, nregs, VecList, asm, immtype>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) VecList:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_eld_ss<bits<2> sz, bits<2> nregs, RegisterOperand VecList,
                      string asm, RegisterOperand gprty>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
@@ -7083,7 +7083,7 @@
 // bit scaled  is '1' if the offsets are scaled
 class sve_mem_32b_gld_sv<bits<4> opc, bit xs, bit scaled, string asm,
                          RegisterOperand zprext>
-: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+: I<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
   "",
   []>, Sched<[]> {
@@ -7117,17 +7117,17 @@
   def _SXTW_SCALED_REAL : sve_mem_32b_gld_sv<opc, 1, 1, asm, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _UXTW_SCALED : Pseudo<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
-                     PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_SCALED_REAL) Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
-  def _SXTW_SCALED : Pseudo<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
-                     PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_SCALED_REAL) Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
+  def _UXTW_SCALED : Pseudo<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
+                     PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_SCALED_REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+  def _SXTW_SCALED : Pseudo<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
+                     PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_SCALED_REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
   }
 
   def : Pat<(nxv4i32 (uxtw_op (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$indices), vt)),
@@ -7146,17 +7146,17 @@
   def _SXTW_REAL : sve_mem_32b_gld_sv<opc, 1, 0, asm, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _UXTW_REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _SXTW_REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _UXTW : Pseudo<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
-              PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_REAL) Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
-  def _SXTW : Pseudo<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
-              PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_REAL) Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
+  def _UXTW : Pseudo<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
+              PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+  def _SXTW : Pseudo<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
+              PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
   }
 
   def : Pat<(nxv4i32 (uxtw_op (nxv4i1 PPR:$gp), GPR64sp:$base, (nxv4i32 ZPR:$offsets), vt)),
@@ -7167,7 +7167,7 @@
 
 
 class sve_mem_32b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
-: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5),
+: I<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm5),
   asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
   "",
   []>, Sched<[]> {
@@ -7195,17 +7195,17 @@
   def _IMM_REAL : sve_mem_32b_gld_vi<opc, asm, imm_ty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 0>;
+                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
-                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
+                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
+                  (!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, 0), 1>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _IMM : Pseudo<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), []>,
-             PseudoInstExpansion<(!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5)>;
+  def _IMM : Pseudo<(outs Z_s:$Zt), (ins PPRAny_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm5), []>,
+             PseudoInstExpansion<(!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm5)>;
   }
 
   def : Pat<(nxv4i32 (op (nxv4i1 PPR:$gp), (nxv4i32 ZPR:$ptrs), imm_ty:$index, vt)),
@@ -7213,7 +7213,7 @@
 }
 
 class sve_mem_prfm_si<bits<2> msz, string asm>
-: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, simm6s1:$imm6),
+: I<(outs), (ins sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm6s1:$imm6),
   asm, "\t$prfop, $Pg, [$Rn, $imm6, mul vl]",
   "",
   []>, Sched<[]> {
@@ -7237,11 +7237,11 @@
   def NAME : sve_mem_prfm_si<msz, asm>;
 
   def : InstAlias<asm # "\t$prfop, $Pg, [$Rn]",
-                  (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
 }
 
 class sve_mem_prfm_ss<bits<3> opc, string asm, RegisterOperand gprty>
-: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs), (ins sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$prfop, $Pg, [$Rn, $Rm]",
   "",
   []>, Sched<[]> {
@@ -7266,7 +7266,7 @@
 
 class sve_mem_32b_prfm_sv<bits<2> msz, bit xs, string asm,
                           RegisterOperand zprext>
-: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+: I<(outs), (ins sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm),
   asm, "\t$prfop, $Pg, [$Rn, $Zm]",
   "",
   []>, Sched<[]> {
@@ -7296,15 +7296,15 @@
   def _UXTW_SCALED : sve_mem_32b_prfm_sv<msz, 0, asm, uxtw_opnd>;
   def _SXTW_SCALED : sve_mem_32b_prfm_sv<msz, 1, asm, sxtw_opnd>;
 
-  def : Pat<(op_uxtw (nxv4i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv4i32 uxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME # _UXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+  def : Pat<(op_uxtw (nxv4i1 PPRAny_p0to7:$Pg), (i64 GPR64sp:$Rn), (nxv4i32 uxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME # _UXTW_SCALED) sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
 
-  def : Pat<(op_sxtw (nxv4i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv4i32 sxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME # _SXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
+  def : Pat<(op_sxtw (nxv4i1 PPRAny_p0to7:$Pg), (i64 GPR64sp:$Rn), (nxv4i32 sxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME # _SXTW_SCALED) sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
 }
 
 class sve_mem_32b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
-: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5),
+: I<(outs), (ins sve_prfop:$prfop, PPRAny_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm5),
   asm, "\t$prfop, $Pg, [$Zn, $imm5]",
   "",
   []>, Sched<[]> {
@@ -7327,10 +7327,10 @@
   def NAME : sve_mem_32b_prfm_vi<msz, asm, imm_ty>;
 
   def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
-                  (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
+                  (!cast<Instruction>(NAME) sve_prfop:$prfop, PPRAny_p0to7:$Pg, ZPR32:$Zn, 0), 1>;
 
-  def : Pat<(op (nxv4i1 PPR_3b:$Pg), (nxv4i32 ZPR32:$Zn), (i64 imm_ty:$imm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR_3b:$Pg, ZPR32:$Zn, imm_ty:$imm)>;
+  def : Pat<(op (nxv4i1 PPR_p0to7:$Pg), (nxv4i32 ZPR32:$Zn), (i64 imm_ty:$imm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm)>;
 }
 
 class sve_mem_z_fill<string asm>
@@ -7412,35 +7412,35 @@
 multiclass sve2_mem_gldnt_vs_32_ptrs<bits<5> opc, string asm,
                                   SDPatternOperator op,
                                   ValueType vt> {
-  def _REAL : sve2_mem_gldnt_vs_base<opc, (ins PPR3bAny:$Pg, ZPR32:$Zn, GPR64:$Rm),
+  def _REAL : sve2_mem_gldnt_vs_base<opc, (ins PPRAny_p0to7:$Pg, ZPR32:$Zn, GPR64:$Rm),
                                      asm, Z_s>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $Rm]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, GPR64:$Rm), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, GPR64:$Rm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR32:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, XZR), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, XZR), 1>;
+                 (!cast<Instruction>(NAME # _REAL) Z_s:$Zt, PPRAny_p0to7:$Pg, ZPR32:$Zn, XZR), 1>;
 
-  def : Pat <(nxv4i32 (op (nxv4i1 PPR3bAny:$Pg), (nxv4i32 ZPR32:$Zd), (i64 GPR64:$Rm), vt)),
-             (!cast<Instruction>(NAME # _REAL) PPR3bAny:$Pg, ZPR32:$Zd, GPR64:$Rm)>;
+  def : Pat <(nxv4i32 (op (nxv4i1 PPRAny_p0to7:$Pg), (nxv4i32 ZPR32:$Zd), (i64 GPR64:$Rm), vt)),
+             (!cast<Instruction>(NAME # _REAL) PPRAny_p0to7:$Pg, ZPR32:$Zd, GPR64:$Rm)>;
 }
 
 multiclass sve2_mem_gldnt_vs_64_ptrs<bits<5> opc, string asm,
                                    SDPatternOperator op,
                                    ValueType vt> {
-  def _REAL : sve2_mem_gldnt_vs_base<opc, (ins PPR3bAny:$Pg, ZPR64:$Zn, GPR64:$Rm),
+  def _REAL : sve2_mem_gldnt_vs_base<opc, (ins PPRAny_p0to7:$Pg, ZPR64:$Zn, GPR64:$Rm),
                                      asm, Z_d>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $Rm]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, GPR64:$Rm), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, GPR64:$Rm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR), 0>;
+                 (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, XZR), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                 (!cast<Instruction>(NAME # _REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR), 1>;
+                 (!cast<Instruction>(NAME # _REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, XZR), 1>;
 
-  def : Pat <(nxv2i64 (op (nxv2i1 PPR3bAny:$Pg), (nxv2i64 ZPR64:$Zd), (i64 GPR64:$Rm), vt)),
-             (!cast<Instruction>(NAME # _REAL) PPR3bAny:$Pg, ZPR64:$Zd, GPR64:$Rm)>;
+  def : Pat <(nxv2i64 (op (nxv2i1 PPRAny_p0to7:$Pg), (nxv2i64 ZPR64:$Zd), (i64 GPR64:$Rm), vt)),
+             (!cast<Instruction>(NAME # _REAL) PPRAny_p0to7:$Pg, ZPR64:$Zd, GPR64:$Rm)>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -7452,7 +7452,7 @@
 // bit lsl     is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
 class sve_mem_64b_gld_sv<bits<4> opc, bit xs, bit scaled, bit lsl, string asm,
                          RegisterOperand zprext>
-: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+: I<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Zm]",
   "",
   []>, Sched<[]> {
@@ -7486,17 +7486,17 @@
   def _SXTW_SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 0, asm, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _UXTW_SCALED_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _SXTW_SCALED_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _UXTW_SCALED : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
-                     PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_SCALED_REAL) Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
-  def _SXTW_SCALED : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
-                     PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_SCALED_REAL) Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
+  def _UXTW_SCALED : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
+                     PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_SCALED_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+  def _SXTW_SCALED : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
+                     PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_SCALED_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
   }
 
   def : Pat<(nxv2i64 (uxtw_op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$indices), vt)),
@@ -7515,17 +7515,17 @@
   def _SXTW_REAL : sve_mem_64b_gld_sv<opc, 1, 0, 0, asm, sxtw_opnd>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _UXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _UXTW_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _SXTW_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _SXTW_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _UXTW : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
-              PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_REAL) Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
-  def _SXTW : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
-              PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_REAL) Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
+  def _UXTW : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm), []>,
+              PseudoInstExpansion<(!cast<Instruction>(NAME # _UXTW_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+  def _SXTW : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm), []>,
+              PseudoInstExpansion<(!cast<Instruction>(NAME # _SXTW_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
   }
 
   def : Pat<(nxv2i64 (uxtw_op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt)),
@@ -7540,13 +7540,13 @@
   def _SCALED_REAL : sve_mem_64b_gld_sv<opc, 1, 1, 1, asm, zprext>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _SCALED_REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _SCALED_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _SCALED : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), []>,
-                PseudoInstExpansion<(!cast<Instruction>(NAME # _SCALED_REAL) Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm)>;
+  def _SCALED : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm), []>,
+                PseudoInstExpansion<(!cast<Instruction>(NAME # _SCALED_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm)>;
   }
 
   def : Pat<(nxv2i64 (op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$indices), vt)),
@@ -7558,13 +7558,13 @@
   def _REAL : sve_mem_64b_gld_sv<opc, 1, 0, 1, asm, ZPR64ExtLSL8>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
-                  (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
+                  (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def "" : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), []>,
-           PseudoInstExpansion<(!cast<Instruction>(NAME # _REAL) Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm)>;
+  def "" : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), []>,
+           PseudoInstExpansion<(!cast<Instruction>(NAME # _REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm)>;
   }
 
   def : Pat<(nxv2i64 (op (nxv2i1 PPR:$gp), GPR64sp:$base, (nxv2i64 ZPR:$offsets), vt)),
@@ -7572,7 +7572,7 @@
 }
 
 class sve_mem_64b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
-: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5),
+: I<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, ZPR64:$Zn, imm_ty:$imm5),
   asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
   "",
   []>, Sched<[]> {
@@ -7600,17 +7600,17 @@
   def _IMM_REAL : sve_mem_64b_gld_vi<opc, asm, imm_ty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
+                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
-                 (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
+                 (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
-                  (!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
+                  (!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, 0), 1>;
 
   // We need a layer of indirection because early machine code passes balk at
   // physical register (i.e. FFR) uses that have no previous definition.
   let hasSideEffects = 1, hasNoSchedulingInfo = 1 in {
-  def _IMM : Pseudo<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), []>,
-                  PseudoInstExpansion<(!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5)>;
+  def _IMM : Pseudo<(outs Z_d:$Zt), (ins PPRAny_p0to7:$Pg, ZPR64:$Zn, imm_ty:$imm5), []>,
+                  PseudoInstExpansion<(!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPRAny_p0to7:$Pg, ZPR64:$Zn, imm_ty:$imm5)>;
   }
 
   def : Pat<(nxv2i64 (op (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt)),
@@ -7620,7 +7620,7 @@
 // bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
 class sve_mem_64b_prfm_sv<bits<2> msz, bit xs, bit lsl, string asm,
                           RegisterOperand zprext>
-: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
+: I<(outs), (ins sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm),
   asm, "\t$prfop, $Pg, [$Rn, $Zm]",
   "",
   []>, Sched<[]> {
@@ -7650,11 +7650,11 @@
   def _UXTW_SCALED : sve_mem_64b_prfm_sv<msz, 0, 0, asm, uxtw_opnd>;
   def _SXTW_SCALED : sve_mem_64b_prfm_sv<msz, 1, 0, asm, sxtw_opnd>;
 
-  def : Pat<(op_uxtw (nxv2i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 uxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME # _UXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
+  def : Pat<(op_uxtw (nxv2i1 PPRAny_p0to7:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 uxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME # _UXTW_SCALED) sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, uxtw_opnd:$Zm)>;
 
-  def : Pat<(op_sxtw (nxv2i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 sxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME # _SXTW_SCALED) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
+  def : Pat<(op_sxtw (nxv2i1 PPRAny_p0to7:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 sxtw_opnd:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME # _SXTW_SCALED) sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, sxtw_opnd:$Zm)>;
 
 }
 
@@ -7662,13 +7662,13 @@
                                           RegisterOperand zprext, SDPatternOperator frag> {
   def NAME : sve_mem_64b_prfm_sv<msz, 1, 1, asm, zprext>;
 
-  def : Pat<(frag (nxv2i1 PPR3bAny:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 zprext:$Zm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm)>;
+  def : Pat<(frag (nxv2i1 PPRAny_p0to7:$Pg), (i64 GPR64sp:$Rn), (nxv2i64 zprext:$Zm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPRAny_p0to7:$Pg, GPR64sp:$Rn, zprext:$Zm)>;
 
 }
 
 class sve_mem_64b_prfm_vi<bits<2> msz, string asm, Operand imm_ty>
-: I<(outs), (ins sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5),
+: I<(outs), (ins sve_prfop:$prfop, PPRAny_p0to7:$Pg, ZPR64:$Zn, imm_ty:$imm5),
   asm, "\t$prfop, $Pg, [$Zn, $imm5]",
   "",
   []>, Sched<[]> {
@@ -7693,10 +7693,10 @@
   def NAME : sve_mem_64b_prfm_vi<msz, asm, imm_ty>;
 
   def : InstAlias<asm # "\t$prfop, $Pg, [$Zn]",
-                  (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
+                  (!cast<Instruction>(NAME) sve_prfop:$prfop, PPRAny_p0to7:$Pg, ZPR64:$Zn, 0), 1>;
 
-  def : Pat<(op (nxv2i1 PPR_3b:$Pg), (nxv2i64 ZPR32:$Zn), (i64 imm_ty:$imm), (i32 sve_prfop:$prfop)),
-            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR_3b:$Pg, ZPR32:$Zn, imm_ty:$imm)>;
+  def : Pat<(op (nxv2i1 PPR_p0to7:$Pg), (nxv2i64 ZPR32:$Zn), (i64 imm_ty:$imm), (i32 sve_prfop:$prfop)),
+            (!cast<Instruction>(NAME) sve_prfop:$prfop, PPR_p0to7:$Pg, ZPR32:$Zn, imm_ty:$imm)>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -7814,7 +7814,7 @@
 
 class sve_int_reduce<bits<2> sz8_32, bits<2> fmt, bits<3> opc, string asm,
                      ZPRRegOp zprty, FPRasZPROperand dstOpType>
-: I<(outs dstOpType:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
+: I<(outs dstOpType:$Vd), (ins PPRAny_p0to7:$Pg, zprty:$Zn),
   asm, "\t$Vd, $Pg, $Zn",
   "",
   []>, Sched<[]> {
@@ -7906,25 +7906,25 @@
 multiclass sve_int_movprfx_pred_merge<bits<3> opc, string asm> {
 let Constraints = "$Zd = $_Zd" in {
   def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/m",
-                                (ins ZPR8:$_Zd, PPR3bAny:$Pg, ZPR8:$Zn)>;
+                                (ins ZPR8:$_Zd, PPRAny_p0to7:$Pg, ZPR8:$Zn)>;
   def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/m",
-                                (ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR16:$Zn)>;
+                                (ins ZPR16:$_Zd, PPRAny_p0to7:$Pg, ZPR16:$Zn)>;
   def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/m",
-                                (ins ZPR32:$_Zd, PPR3bAny:$Pg, ZPR32:$Zn)>;
+                                (ins ZPR32:$_Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn)>;
   def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/m",
-                                (ins ZPR64:$_Zd, PPR3bAny:$Pg, ZPR64:$Zn)>;
+                                (ins ZPR64:$_Zd, PPRAny_p0to7:$Pg, ZPR64:$Zn)>;
 }
 }
 
 multiclass sve_int_movprfx_pred_zero<bits<3> opc, string asm> {
   def _B : sve_int_movprfx_pred<0b00, opc, asm, ZPR8, "/z",
-                                (ins PPR3bAny:$Pg, ZPR8:$Zn)>;
+                                (ins PPRAny_p0to7:$Pg, ZPR8:$Zn)>;
   def _H : sve_int_movprfx_pred<0b01, opc, asm, ZPR16, "/z",
-                                (ins PPR3bAny:$Pg, ZPR16:$Zn)>;
+                                (ins PPRAny_p0to7:$Pg, ZPR16:$Zn)>;
   def _S : sve_int_movprfx_pred<0b10, opc, asm, ZPR32, "/z",
-                                (ins PPR3bAny:$Pg, ZPR32:$Zn)>;
+                                (ins PPRAny_p0to7:$Pg, ZPR32:$Zn)>;
   def _D : sve_int_movprfx_pred<0b11, opc, asm, ZPR64, "/z",
-                                (ins PPR3bAny:$Pg, ZPR64:$Zn)>;
+                                (ins PPRAny_p0to7:$Pg, ZPR64:$Zn)>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -8034,7 +8034,7 @@
 
 class sve2_char_match<bit sz, bit opc, string asm,
                       PPRRegOp pprty, ZPRRegOp zprty>
-: I<(outs pprty:$Pd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
+: I<(outs pprty:$Pd), (ins PPRAny_p0to7:$Pg, zprty:$Zn, zprty:$Zm),
   asm, "\t$Pd, $Pg/z, $Zn, $Zm",
   "",
   []>, Sched<[]> {
@@ -8089,7 +8089,7 @@
 //===----------------------------------------------------------------------===//
 
 class sve2_hist_gen_vector<bit sz, string asm, ZPRRegOp zprty>
-: I<(outs zprty:$Zd), (ins PPR3bAny:$Pg, zprty:$Zn, zprty:$Zm),
+: I<(outs zprty:$Zd), (ins PPRAny_p0to7:$Pg, zprty:$Zn, zprty:$Zm),
   asm, "\t$Zd, $Pg/z, $Zn, $Zm",
   "",
   []>, Sched<[]> {
@@ -8304,7 +8304,7 @@
 }
 
 class sve_bfloat_convert<bit N, string asm>
-: I<(outs ZPR16:$Zd), (ins ZPR16:$_Zd, PPR3bAny:$Pg, ZPR32:$Zn),
+: I<(outs ZPR16:$Zd), (ins ZPR16:$_Zd, PPRAny_p0to7:$Pg, ZPR32:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn", "", []>, Sched<[]> {
   bits<5> Zd;
   bits<3> Pg;
@@ -8447,7 +8447,7 @@
 //===----------------------------------------------------------------------===//
 
 class sve_mem_ldor_si<bits<2> sz, string asm, RegisterOperand VecList>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s32:$imm4),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s32:$imm4),
   asm, "\t$Zt, $Pg/z, [$Rn, $imm4]", "", []>, Sched<[]> {
   bits<5> Zt;
   bits<5> Rn;
@@ -8469,25 +8469,25 @@
                            ZPRRegOp zprty, ValueType Ty, ValueType PredTy, SDNode Ld1ro> {
   def NAME : sve_mem_ldor_si<sz, asm, listty>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) listty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 1>;
+                  (!cast<Instruction>(NAME) listty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 1>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, 0), 0>;
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $imm4]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, simm4s32:$imm4), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, simm4s32:$imm4), 0>;
 
   // Base addressing mode
-  def : Pat<(Ty (Ld1ro (PredTy PPR3bAny:$Pg), GPR64sp:$base)),
-            (!cast<Instruction>(NAME) PPR3bAny:$Pg, GPR64sp:$base, (i64 0))>;
+  def : Pat<(Ty (Ld1ro (PredTy PPRAny_p0to7:$Pg), GPR64sp:$base)),
+            (!cast<Instruction>(NAME) PPRAny_p0to7:$Pg, GPR64sp:$base, (i64 0))>;
   let AddedComplexity = 2 in {
     // Reg + Imm addressing mode
-    def : Pat<(Ty (Ld1ro (PredTy PPR3bAny:$Pg), (add GPR64:$base, (i64 simm4s32:$imm)))),
+    def : Pat<(Ty (Ld1ro (PredTy PPRAny_p0to7:$Pg), (add GPR64:$base, (i64 simm4s32:$imm)))),
               (!cast<Instruction>(NAME) $Pg, $base, simm4s32:$imm)>;
   }
 }
 
 class sve_mem_ldor_ss<bits<2> sz, string asm, RegisterOperand VecList,
                       RegisterOperand gprty>
-: I<(outs VecList:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm),
+: I<(outs VecList:$Zt), (ins PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm),
   asm, "\t$Zt, $Pg/z, [$Rn, $Rm]", "", []>, Sched<[]> {
   bits<5> Zt;
   bits<3> Pg;
@@ -8511,10 +8511,10 @@
   def NAME : sve_mem_ldor_ss<sz, asm, listty, gprty>;
 
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Rm]",
-                  (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
+                  (!cast<Instruction>(NAME) zprty:$Zt, PPRAny_p0to7:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
 
-  def : Pat<(Ty (Ld1ro (PredTy PPR3bAny:$gp), (AddrCP GPR64sp:$base, gprty:$offset))),
-            (!cast<Instruction>(NAME) PPR3bAny:$gp, GPR64sp:$base, gprty:$offset)>;
+  def : Pat<(Ty (Ld1ro (PredTy PPRAny_p0to7:$gp), (AddrCP GPR64sp:$base, gprty:$offset))),
+            (!cast<Instruction>(NAME) PPRAny_p0to7:$gp, GPR64sp:$base, gprty:$offset)>;
 }
 
 //===----------------------------------------------------------------------===//
Index: llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
===================================================================
--- llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
+++ llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll
@@ -51,7 +51,7 @@
 ; CHECK: [[ARG1:%[0-9]+]]:zpr = COPY $z1
 ; CHECK: [[ARG2:%[0-9]+]]:zpr = COPY $z0
 ; CHECK: [[ARG3:%[0-9]+]]:ppr = COPY $p0
-; CHECK: [[ARG4:%[0-9]+]]:ppr_3b = COPY [[ARG3]]
+; CHECK: [[ARG4:%[0-9]+]]:ppr_p0to7 = COPY [[ARG3]]
 ; CHECK: INLINEASM {{.*}} [[ARG4]]
 define <vscale x 8 x half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) {
   %1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
Index: llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
+++ llvm/test/CodeGen/AArch64/sve-calling-convention-byref.ll
@@ -9,7 +9,7 @@
 define aarch64_sve_vector_pcs <vscale x 4 x i32> @callee_with_many_sve_arg(<vscale x 4 x i32> %z0, <vscale x 4 x i32> %z1, <vscale x 4 x i32> %z2, <vscale x 4 x i32> %z3, <vscale x 4 x i32> %z4, <vscale x 4 x i32> %z5, <vscale x 4 x i32> %z6, <vscale x 4 x i32> %z7, <vscale x 4 x i32> %z8, <vscale x 4 x i32> %z9) {
 ; CHECK: name: callee_with_many_sve_arg
 ; CHECK-DAG: [[BASE:%[0-9]+]]:gpr64common = COPY $x1
-; CHECK-DAG: [[PTRUE:%[0-9]+]]:ppr_3b = PTRUE_S 31
+; CHECK-DAG: [[PTRUE:%[0-9]+]]:ppr_p0to7 = PTRUE_S 31
 ; CHECK-DAG: [[RES:%[0-9]+]]:zpr = LD1W_IMM killed [[PTRUE]], [[BASE]]
 ; CHECK-DAG: $z0 = COPY [[RES]]
 ; CHECK:     RET_ReallyLR implicit $z0
@@ -24,7 +24,7 @@
 ; CHECK-NEXT:     stack-id: scalable-vector
 ; CHECK:      - { id: 1, name: '', type: default, offset: 0, size: 16, alignment: 16,
 ; CHECK-NEXT:     stack-id: scalable-vector
-; CHECK-DAG:  [[PTRUE:%[0-9]+]]:ppr_3b = PTRUE_S 31
+; CHECK-DAG:  [[PTRUE:%[0-9]+]]:ppr_p0to7 = PTRUE_S 31
 ; CHECK-DAG:  ST1W_IMM %{{[0-9]+}}, [[PTRUE]], %stack.1, 0
 ; CHECK-DAG:  ST1W_IMM %{{[0-9]+}}, [[PTRUE]], %stack.0, 0
 ; CHECK-DAG:  [[BASE2:%[0-9]+]]:gpr64sp = ADDXri %stack.1, 0
@@ -87,7 +87,7 @@
 ; CHECK: fixedStack:
 ; CHECK:      - { id: 0, type: default, offset: 8, size: 8, alignment: 8, stack-id: default,
 ; CHECK-DAG: [[BASE:%[0-9]+]]:gpr64common = LDRXui %fixed-stack.0, 0
-; CHECK-DAG: [[PTRUE:%[0-9]+]]:ppr_3b = PTRUE_S 31
+; CHECK-DAG: [[PTRUE:%[0-9]+]]:ppr_p0to7 = PTRUE_S 31
 ; CHECK-DAG: [[RES:%[0-9]+]]:zpr = LD1W_IMM killed [[PTRUE]], killed [[BASE]]
 ; CHECK-DAG: $z0 = COPY [[RES]]
 ; CHECK: RET_ReallyLR implicit $z0
@@ -102,8 +102,8 @@
 ; CHECK-NEXT:     stack-id: scalable-vector
 ; CHECK:      - { id: 1, name: '', type: default, offset: 0, size: 16, alignment: 16,
 ; CHECK-NEXT:     stack-id: scalable-vector
-; CHECK-DAG: [[PTRUE_S:%[0-9]+]]:ppr_3b = PTRUE_S 31
-; CHECK-DAG: [[PTRUE_D:%[0-9]+]]:ppr_3b = PTRUE_D 31
+; CHECK-DAG: [[PTRUE_S:%[0-9]+]]:ppr_p0to7 = PTRUE_S 31
+; CHECK-DAG: [[PTRUE_D:%[0-9]+]]:ppr_p0to7 = PTRUE_D 31
 ; CHECK-DAG: ST1D_IMM %{{[0-9]+}}, killed [[PTRUE_D]], %stack.0, 0
 ; CHECK-DAG: ST1W_IMM %{{[0-9]+}}, killed [[PTRUE_S]], %stack.1, 0
 ; CHECK-DAG: [[BASE1:%[0-9]+]]:gpr64common = ADDXri %stack.0, 0
Index: llvm/test/CodeGen/AArch64/sve-localstackalloc.mir
===================================================================
--- llvm/test/CodeGen/AArch64/sve-localstackalloc.mir
+++ llvm/test/CodeGen/AArch64/sve-localstackalloc.mir
@@ -23,7 +23,7 @@
   - { id: 1, class: zpr, preferred-register: '' }
   - { id: 2, class: gpr32, preferred-register: '' }
   - { id: 3, class: gpr64, preferred-register: '' }
-  - { id: 5, class: ppr_3b, preferred-register: '' }
+  - { id: 5, class: ppr_p0to7, preferred-register: '' }
   - { id: 6, class: gpr64sp, preferred-register: '' }
   - { id: 7, class: zpr, preferred-register: '' }
   - { id: 8, class: zpr, preferred-register: '' }
@@ -48,7 +48,7 @@
     %2:gpr32 = COPY $w0
     %1:zpr = COPY $z1
     %0:zpr = COPY $z0
-    %5:ppr_3b = PTRUE_B 31
+    %5:ppr_p0to7 = PTRUE_B 31
     %6:gpr64sp = ADDXri %stack.0, 0, 0
     ST1B_IMM %1, %5, %6, 1 :: (store unknown-size, align 16)
     ST1B_IMM %0, %5, %stack.0, 0 :: (store unknown-size into %stack.0, align 16)
Index: llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpeq.mir
===================================================================
--- llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpeq.mir
+++ llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpeq.mir
@@ -7,7 +7,7 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
   - { id: 3, class: ppr }
@@ -32,7 +32,7 @@
     ; CHECK-NEXT: %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %3:ppr = CMPEQ_PPzZZ_B %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, killed %3, implicit-def $nzcv
     %4:gpr32 = COPY $wzr
@@ -46,10 +46,10 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
-  - { id: 3, class: ppr_3b }
+  - { id: 3, class: ppr_p0to7 }
   - { id: 4, class: ppr }
   - { id: 5, class: ppr }
   - { id: 6, class: gpr32 }
@@ -68,7 +68,7 @@
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %4:ppr = CMPEQ_PPzZZ_H %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, %4, implicit-def $nzcv
     %6:gpr32 = COPY $wzr
@@ -82,10 +82,10 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
-  - { id: 3, class: ppr_3b }
+  - { id: 3, class: ppr_p0to7 }
   - { id: 4, class: ppr }
   - { id: 5, class: ppr }
   - { id: 6, class: gpr32 }
@@ -104,7 +104,7 @@
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %4:ppr = CMPEQ_PPzZZ_S %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, %4, implicit-def $nzcv
     %6:gpr32 = COPY $wzr
@@ -118,10 +118,10 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
-  - { id: 3, class: ppr_3b }
+  - { id: 3, class: ppr_p0to7 }
   - { id: 4, class: ppr }
   - { id: 5, class: ppr }
   - { id: 6, class: gpr32 }
@@ -140,7 +140,7 @@
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %4:ppr = CMPEQ_PPzZZ_D %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, %4, implicit-def $nzcv
     %6:gpr32 = COPY $wzr
@@ -154,7 +154,7 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
@@ -172,7 +172,7 @@
     ; CHECK-LABEL: name: cmpeq_imm_nxv16i8
     ; CHECK-NOT: PTEST
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
     %3:ppr = PTRUE_B 31
     PTEST_PP killed %3, killed %2, implicit-def $nzcv
@@ -187,7 +187,7 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
@@ -206,7 +206,7 @@
     ; CHECK-LABEL: name: cmpeq_imm_nxv8i16
     ; CHECK-NOT: PTEST
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_H %0, %1, 0, implicit-def dead $nzcv
     PTEST_PP %0, %2, implicit-def $nzcv
     %5:gpr32 = COPY $wzr
@@ -220,7 +220,7 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
@@ -239,7 +239,7 @@
     ; CHECK-LABEL: name: cmpeq_imm_nxv4i32
     ; CHECK-NOT: PTEST
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_S %0, %1, 0, implicit-def dead $nzcv
     PTEST_PP %0, %2, implicit-def $nzcv
     %5:gpr32 = COPY $wzr
@@ -253,7 +253,7 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
@@ -272,7 +272,7 @@
     ; CHECK-LABEL: name: cmpeq_imm_nxv2i64
     ; CHECK-NOT: PTEST
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_D %0, %1, 0, implicit-def dead $nzcv
     PTEST_PP %0, %2, implicit-def $nzcv
     %5:gpr32 = COPY $wzr
@@ -286,7 +286,7 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
   - { id: 3, class: ppr }
@@ -306,7 +306,7 @@
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %3:ppr = CMPEQ_WIDE_PPzZZ_B %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, killed %3, implicit-def $nzcv
     %4:gpr32 = COPY $wzr
@@ -320,10 +320,10 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
-  - { id: 3, class: ppr_3b }
+  - { id: 3, class: ppr_p0to7 }
   - { id: 4, class: ppr }
   - { id: 5, class: ppr }
   - { id: 6, class: gpr32 }
@@ -342,7 +342,7 @@
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %4:ppr = CMPEQ_WIDE_PPzZZ_H %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, %4, implicit-def $nzcv
     %6:gpr32 = COPY $wzr
@@ -356,10 +356,10 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
-  - { id: 3, class: ppr_3b }
+  - { id: 3, class: ppr_p0to7 }
   - { id: 4, class: ppr }
   - { id: 5, class: ppr }
   - { id: 6, class: gpr32 }
@@ -378,7 +378,7 @@
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %4:ppr = CMPEQ_WIDE_PPzZZ_S %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %0, %4, implicit-def $nzcv
     %6:gpr32 = COPY $wzr
@@ -392,7 +392,7 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
@@ -414,7 +414,7 @@
     ; CHECK-NEXT: %4:gpr32 = COPY $wzr
     ; CHECK-NEXT: %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
     %3:ppr = PTRUE_B 0
     PTEST_PP killed %3, killed %2, implicit-def $nzcv
@@ -429,7 +429,7 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
@@ -451,7 +451,7 @@
     ; CHECK-NEXT: %4:gpr32 = COPY $wzr
     ; CHECK-NEXT: %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
     %3:ppr = PTRUE_H 31
     PTEST_PP killed %3, killed %2, implicit-def $nzcv
@@ -466,7 +466,7 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: ppr }
   - { id: 3, class: ppr }
@@ -489,7 +489,7 @@
     ; CHECK-NEXT: %4:gpr32 = COPY $wzr
     ; CHECK-NEXT: %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
     %3:ppr = COPY $p1
     PTEST_PP killed %3, killed %2, implicit-def $nzcv
@@ -504,7 +504,7 @@
 alignment:       2
 tracksRegLiveness: true
 registers:
-  - { id: 0, class: ppr_3b }
+  - { id: 0, class: ppr_p0to7 }
   - { id: 1, class: zpr }
   - { id: 2, class: zpr }
   - { id: 3, class: ppr }
@@ -524,7 +524,7 @@
     ; CHECK-NOT: PTEST
     %2:zpr = COPY $z1
     %1:zpr = COPY $z0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
     %3:ppr = CMPEQ_PPzZZ_B %0, %1, %2, implicit-def dead $nzcv
     PTEST_PP %3, killed %3, implicit-def $nzcv
     %4:gpr32 = COPY $wzr
Index: llvm/test/CodeGen/AArch64/sve-ptest-removal-rdffr.mir
===================================================================
--- llvm/test/CodeGen/AArch64/sve-ptest-removal-rdffr.mir
+++ llvm/test/CodeGen/AArch64/sve-ptest-removal-rdffr.mir
@@ -7,12 +7,12 @@
 body: |
   bb.0:
     liveins: $ffr, $p0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
 
     ; CHECK: RDFFRS_PPz
     ; CHECK-NOT: PTEST
-    %1:ppr_3b = RDFFR_PPz %0:ppr_3b
-    PTEST_PP killed %0:ppr_3b, killed %1:ppr_3b, implicit-def $nzcv
+    %1:ppr_p0to7 = RDFFR_PPz %0:ppr_p0to7
+    PTEST_PP killed %0:ppr_p0to7, killed %1:ppr_p0to7, implicit-def $nzcv
 
     ; Consume nzcv
     %2:gpr32 = COPY $wzr
@@ -27,13 +27,13 @@
 body: |
   bb.0:
     liveins: $ffr, $p0, $p1
-    %0:ppr_3b = COPY $p0
-    %1:ppr_3b = COPY $p1
+    %0:ppr_p0to7 = COPY $p0
+    %1:ppr_p0to7 = COPY $p1
 
     ; CHECK: RDFFR_PPz
     ; CHECK: PTEST
-    %2:ppr_3b = RDFFR_PPz %0:ppr_3b
-    PTEST_PP killed %1:ppr_3b, killed %2:ppr_3b, implicit-def $nzcv
+    %2:ppr_p0to7 = RDFFR_PPz %0:ppr_p0to7
+    PTEST_PP killed %1:ppr_p0to7, killed %2:ppr_p0to7, implicit-def $nzcv
 
     ; Consume nzcv
     %3:gpr32 = COPY $wzr
@@ -48,15 +48,15 @@
 body: |
   bb.0:
     liveins: $ffr, $p0, $x0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
 
     ; CHECK: RDFFR_PPz
     ; CHECK-NEXT: ADDSXrr
     ; CHECK-NEXT: PTEST_PP
-    %1:ppr_3b = RDFFR_PPz %0:ppr_3b
+    %1:ppr_p0to7 = RDFFR_PPz %0:ppr_p0to7
     ; Clobber nzcv
     $x0 = ADDSXrr $x0, $x0, implicit-def $nzcv
-    PTEST_PP killed %0:ppr_3b, killed %1:ppr_3b, implicit-def $nzcv
+    PTEST_PP killed %0:ppr_p0to7, killed %1:ppr_p0to7, implicit-def $nzcv
 
     ; Consume nzcv
     %2:gpr32 = COPY $wzr
@@ -71,17 +71,17 @@
 body: |
   bb.0:
     liveins: $ffr, $p0, $x0
-    %0:ppr_3b = COPY $p0
+    %0:ppr_p0to7 = COPY $p0
 
     $wzr = SUBSWri $w0, 0, 0, implicit-def $nzcv
 
     ; CHECK: RDFFR_PPz
     ; CHECK-NEXT: CSINCWr
     ; CHECK-NEXT: PTEST_PP
-    %1:ppr_3b = RDFFR_PPz %0:ppr_3b
+    %1:ppr_p0to7 = RDFFR_PPz %0:ppr_p0to7
     ; Consume nzcv
     %2:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
-    PTEST_PP killed %0:ppr_3b, killed %1:ppr_3b, implicit-def $nzcv
+    PTEST_PP killed %0:ppr_p0to7, killed %1:ppr_p0to7, implicit-def $nzcv
 
     ; Consume nzcv
     %3:gpr32 = COPY $wzr