diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -41,6 +41,7 @@ // CHECK-NOT: __riscv_zicboz // CHECK-NOT: __riscv_svnapot // CHECK-NOT: __riscv_svinval +// CHECK-NOT: __riscv_h // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-M-EXT %s @@ -432,3 +433,9 @@ // RUN: %clang -target riscv64 -march=rv64isvinval -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SVINVAL-EXT %s // CHECK-SVINVAL-EXT: __riscv_svinval 1000000{{$}} + +// RUN: %clang -target riscv32 -march=rv32ih -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-H-EXT %s +// RUN: %clang -target riscv64 -march=rv64ih -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-H-EXT %s +// CHECK-H-EXT: __riscv_h 1000000{{$}} diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -51,6 +51,7 @@ ``C`` Supported ``D`` Supported ``F`` Supported + ``H`` Supported ``M`` Supported ``Svinval`` Assembly Support ``V`` Supported diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -37,7 +37,7 @@ } // end anonymous namespace -static constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvn"; +static constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvnh"; static const RISCVSupportedExtension SupportedExtensions[] = { {"i", RISCVExtensionVersion{2, 0}}, @@ -48,6 +48,8 @@ {"d", RISCVExtensionVersion{2, 0}}, {"c", RISCVExtensionVersion{2, 0}}, + {"h", RISCVExtensionVersion{1, 0}}, + {"zihintpause", RISCVExtensionVersion{2, 0}}, {"zfhmin", RISCVExtensionVersion{1, 0}}, @@ -275,17 +277,14 @@ case 's': HighOrder = 0; break; - case 'h': - HighOrder = 1; - break; case 'z': - HighOrder = 2; + HighOrder = 1; // `z` extension must be sorted by canonical order of second letter. // e.g. zmx has higher rank than zax. LowOrder = singleLetterExtensionRank(ExtName[1]); break; case 'x': - HighOrder = 3; + HighOrder = 2; break; default: llvm_unreachable("Unknown prefix for multi-char extension"); @@ -602,8 +601,8 @@ // The order is OK, then push it into features. // TODO: Use version number when setting target features - // Currently LLVM supports only "mafdcv". - StringRef SupportedStandardExtension = "mafdcv"; + // Currently LLVM supports only "mafdcvh". + StringRef SupportedStandardExtension = "mafdcvh"; if (!SupportedStandardExtension.contains(C)) return createStringError(errc::invalid_argument, "unsupported standard user-level extension '%c'", diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -51,6 +51,10 @@ AssemblerPredicate<(all_of FeatureStdExtD), "'D' (Double-Precision Floating-Point)">; +def FeatureStdExtH + : SubtargetFeature<"h", "HasStdExtH", "true", + "'H' (Hypervisor)">; + def FeatureStdExtZihintpause : SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true", "'zihintpause' (Pause Hint)">; diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -57,6 +57,7 @@ bool HasStdExtZbs = false; bool HasStdExtZca = false; bool HasStdExtV = false; + bool HasStdExtH = false; bool HasStdExtZve32x = false; bool HasStdExtZve32f = false; bool HasStdExtZve64x = false; @@ -157,6 +158,7 @@ bool hasStdExtD() const { return HasStdExtD; } bool hasStdExtC() const { return HasStdExtC; } bool hasStdExtV() const { return HasStdExtV; } + bool hasStdExtH() const { return HasStdExtH; } bool hasStdExtZihintpause() const { return HasStdExtZihintpause; } bool hasStdExtZihintntl() const { return HasStdExtZihintntl; } bool hasStdExtZba() const { return HasStdExtZba; } diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -16,6 +16,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zbc %s -o - | FileCheck --check-prefix=RV32ZBC %s ; RUN: llc -mtriple=riscv32 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s ; RUN: llc -mtriple=riscv32 -mattr=+v %s -o - | FileCheck --check-prefix=RV32V %s +; RUN: llc -mtriple=riscv32 -mattr=+h %s -o - | FileCheck --check-prefix=RV32H %s ; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+v,+f %s -o - | FileCheck --check-prefix=RV32COMBINED %s ; RUN: llc -mtriple=riscv32 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV32ZBKB %s ; RUN: llc -mtriple=riscv32 -mattr=+zbkc %s -o - | FileCheck --check-prefix=RV32ZBKC %s @@ -54,6 +55,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zbc %s -o - | FileCheck --check-prefix=RV64ZBC %s ; RUN: llc -mtriple=riscv64 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s ; RUN: llc -mtriple=riscv64 -mattr=+v %s -o - | FileCheck --check-prefix=RV64V %s +; RUN: llc -mtriple=riscv64 -mattr=+h %s -o - | FileCheck --check-prefix=RV64H %s ; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+v,+f %s -o - | FileCheck --check-prefix=RV64COMBINED %s ; RUN: llc -mtriple=riscv64 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV64ZBKB %s ; RUN: llc -mtriple=riscv64 -mattr=+zbkc %s -o - | FileCheck --check-prefix=RV64ZBKC %s @@ -95,6 +97,7 @@ ; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0" ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0" ; RV32V: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +; RV32H: .attribute 5, "rv32i2p0_h1p0" ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" ; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0" ; RV32ZBKC: .attribute 5, "rv32i2p0_zbkc1p0" @@ -134,6 +137,7 @@ ; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0" ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0" ; RV64V: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +; RV64H: .attribute 5, "rv64i2p0_h1p0" ; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" ; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0" ; RV64ZBKC: .attribute 5, "rv64i2p0_zbkc1p0"