Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -3625,4 +3625,40 @@ defm LDNT1H_4ZCXI : sve2p1_mem_cld_si_4z<"ldnt1h", 0b01, 0b1, ZZZZ_h_mul_r>; defm LDNT1W_4ZCXI : sve2p1_mem_cld_si_4z<"ldnt1w", 0b10, 0b1, ZZZZ_s_mul_r>; defm LDNT1D_4ZCXI : sve2p1_mem_cld_si_4z<"ldnt1d", 0b11, 0b1, ZZZZ_d_mul_r>; + +// Stores of two registers +def ST1B_2ZCXX : sve2p1_mem_cst_ss_2z<"st1b", 0b00, 0b0, ZZ_b_mul_r, GPR64shifted8>; +def ST1H_2ZCXX : sve2p1_mem_cst_ss_2z<"st1h", 0b01, 0b0, ZZ_h_mul_r, GPR64shifted16>; +def ST1W_2ZCXX : sve2p1_mem_cst_ss_2z<"st1w", 0b10, 0b0, ZZ_s_mul_r, GPR64shifted32>; +def ST1D_2ZCXX : sve2p1_mem_cst_ss_2z<"st1d", 0b11, 0b0, ZZ_d_mul_r, GPR64shifted64>; +defm ST1B_2ZCXI : sve2p1_mem_cst_si_2z<"st1b", 0b00, 0b0, ZZ_b_mul_r>; +defm ST1H_2ZCXI : sve2p1_mem_cst_si_2z<"st1h", 0b01, 0b0, ZZ_h_mul_r>; +defm ST1W_2ZCXI : sve2p1_mem_cst_si_2z<"st1w", 0b10, 0b0, ZZ_s_mul_r>; +defm ST1D_2ZCXI : sve2p1_mem_cst_si_2z<"st1d", 0b11, 0b0, ZZ_d_mul_r>; +def STNT1B_2ZCXX : sve2p1_mem_cst_ss_2z<"stnt1b", 0b00, 0b1, ZZ_b_mul_r, GPR64shifted8>; +def STNT1H_2ZCXX : sve2p1_mem_cst_ss_2z<"stnt1h", 0b01, 0b1, ZZ_h_mul_r, GPR64shifted16>; +def STNT1W_2ZCXX : sve2p1_mem_cst_ss_2z<"stnt1w", 0b10, 0b1, ZZ_s_mul_r, GPR64shifted32>; +def STNT1D_2ZCXX : sve2p1_mem_cst_ss_2z<"stnt1d", 0b11, 0b1, ZZ_d_mul_r, GPR64shifted64>; +defm STNT1B_2ZCXI : sve2p1_mem_cst_si_2z<"stnt1b", 0b00, 0b1, ZZ_b_mul_r>; +defm STNT1H_2ZCXI : sve2p1_mem_cst_si_2z<"stnt1h", 0b01, 0b1, ZZ_h_mul_r>; +defm STNT1W_2ZCXI : sve2p1_mem_cst_si_2z<"stnt1w", 0b10, 0b1, ZZ_s_mul_r>; +defm STNT1D_2ZCXI : sve2p1_mem_cst_si_2z<"stnt1d", 0b11, 0b1, ZZ_d_mul_r>; + +// Stores of four registers +def ST1B_4ZCXX : sve2p1_mem_cst_ss_4z<"st1b", 0b00, 0b0, ZZZZ_b_mul_r, GPR64shifted8>; +def ST1H_4ZCXX : sve2p1_mem_cst_ss_4z<"st1h", 0b01, 0b0, ZZZZ_h_mul_r, GPR64shifted16>; +def ST1W_4ZCXX : sve2p1_mem_cst_ss_4z<"st1w", 0b10, 0b0, ZZZZ_s_mul_r, GPR64shifted32>; +def ST1D_4ZCXX : sve2p1_mem_cst_ss_4z<"st1d", 0b11, 0b0, ZZZZ_d_mul_r, GPR64shifted64>; +defm ST1B_4ZCXI : sve2p1_mem_cst_si_4z<"st1b", 0b00, 0b0, ZZZZ_b_mul_r>; +defm ST1H_4ZCXI : sve2p1_mem_cst_si_4z<"st1h", 0b01, 0b0, ZZZZ_h_mul_r>; +defm ST1W_4ZCXI : sve2p1_mem_cst_si_4z<"st1w", 0b10, 0b0, ZZZZ_s_mul_r>; +defm ST1D_4ZCXI : sve2p1_mem_cst_si_4z<"st1d", 0b11, 0b0, ZZZZ_d_mul_r>; +def STNT1B_4ZCXX : sve2p1_mem_cst_ss_4z<"stnt1b", 0b00, 0b1, ZZZZ_b_mul_r, GPR64shifted8>; +def STNT1H_4ZCXX : sve2p1_mem_cst_ss_4z<"stnt1h", 0b01, 0b1, ZZZZ_h_mul_r, GPR64shifted16>; +def STNT1W_4ZCXX : sve2p1_mem_cst_ss_4z<"stnt1w", 0b10, 0b1, ZZZZ_s_mul_r, GPR64shifted32>; +def STNT1D_4ZCXX : sve2p1_mem_cst_ss_4z<"stnt1d", 0b11, 0b1, ZZZZ_d_mul_r, GPR64shifted64>; +defm STNT1B_4ZCXI : sve2p1_mem_cst_si_4z<"stnt1b", 0b00, 0b1, ZZZZ_b_mul_r>; +defm STNT1H_4ZCXI : sve2p1_mem_cst_si_4z<"stnt1h", 0b01, 0b1, ZZZZ_h_mul_r>; +defm STNT1W_4ZCXI : sve2p1_mem_cst_si_4z<"stnt1w", 0b10, 0b1, ZZZZ_s_mul_r>; +defm STNT1D_4ZCXI : sve2p1_mem_cst_si_4z<"stnt1d", 0b11, 0b1, ZZZZ_d_mul_r>; } // End HasSVE2p1_or_HasSME2 Index: llvm/lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- llvm/lib/Target/AArch64/SVEInstrFormats.td +++ llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -8850,3 +8850,119 @@ def : InstAlias(NAME) vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, 0), 1>; } + + +// SME2 multi-vec contiguous store (scalar plus scalar, two registers) +class sve2p1_mem_cst_ss_2z msz, bit n, + RegisterOperand vector_ty, RegisterOperand gpr_ty> + : I<(outs ), + (ins vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, gpr_ty:$Rm), + mnemonic, "\t$Zt, $PNg, [$Rn, $Rm]", + "", []>, Sched<[]> { + bits<4> Zt; + bits<5> Rm; + bits<5> Rn; + bits<3> PNg; + let Inst{31-21} = 0b10100000001; + let Inst{20-16} = Rm; + let Inst{15} = 0b0; + let Inst{14-13} = msz; + let Inst{12-10} = PNg; + let Inst{9-5} = Rn; + let Inst{4-1} = Zt; + let Inst{0} = n; + + let mayStore = 1; +} + + +// SME2 multi-vec contiguous store (scalar plus immediate, two registers) +class sve2p1_mem_cst_si_2z msz, bit n, + RegisterOperand vector_ty> + : I<(outs ), + (ins vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, simm4s2:$imm4), + mnemonic, "\t$Zt, $PNg, [$Rn, $imm4, mul vl]", + "", []>, Sched<[]> { + bits<4> Zt; + bits<5> Rn; + bits<3> PNg; + bits<4> imm4; + let Inst{31-20} = 0b101000000110; + let Inst{19-16} = imm4; + let Inst{15} = 0b0; + let Inst{14-13} = msz; + let Inst{12-10} = PNg; + let Inst{9-5} = Rn; + let Inst{4-1} = Zt; + let Inst{0} = n; + + let mayStore = 1; +} + + +multiclass sve2p1_mem_cst_si_2z msz, bit n, + RegisterOperand vector_ty> { + def NAME : sve2p1_mem_cst_si_2z; + + def : InstAlias(NAME) vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, 0), 1>; +} + + +// SME2 multi-vec contiguous store (scalar plus scalar, four registers) +class sve2p1_mem_cst_ss_4z msz, bit n, + RegisterOperand vector_ty, RegisterOperand gpr_ty> + : I<(outs ), + (ins vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, gpr_ty:$Rm), + mnemonic, "\t$Zt, $PNg, [$Rn, $Rm]", + "", []>, Sched<[]> { + bits<3> Zt; + bits<5> Rm; + bits<5> Rn; + bits<3> PNg; + let Inst{31-21} = 0b10100000001; + let Inst{20-16} = Rm; + let Inst{15} = 0b1; + let Inst{14-13} = msz; + let Inst{12-10} = PNg; + let Inst{9-5} = Rn; + let Inst{4-2} = Zt; + let Inst{1} = 0b0; + let Inst{0} = n; + + let mayStore = 1; +} + + +// SME2 multi-vec contiguous store (scalar plus immediate, four registers) +class sve2p1_mem_cst_si_4z msz, bit n, + RegisterOperand vector_ty> + : I<(outs ), + (ins vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, simm4s4:$imm4), + mnemonic, "\t$Zt, $PNg, [$Rn, $imm4, mul vl]", + "", []>, Sched<[]> { + bits<3> Zt; + bits<5> Rn; + bits<3> PNg; + bits<4> imm4; + let Inst{31-20} = 0b101000000110; + let Inst{19-16} = imm4; + let Inst{15} = 0b1; + let Inst{14-13} = msz; + let Inst{12-10} = PNg; + let Inst{9-5} = Rn; + let Inst{4-2} = Zt; + let Inst{1} = 0b0; + let Inst{0} = n; + + let mayStore = 1; +} + + +multiclass sve2p1_mem_cst_si_4z msz, bit n, + RegisterOperand vector_ty> { + def NAME : sve2p1_mem_cst_si_4z; + + def : InstAlias(NAME) vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn,0), 1>; +} Index: llvm/test/MC/AArch64/SVE2p1/st1b-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st1b-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +st1b {z0.b-z2.b}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: st1b {z0.b-z2.b}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b {z1.b-z4.b}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: st1b {z1.b-z4.b}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b {z7.b-z8.b}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: st1b {z7.b-z8.b}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid predicate-as-counter register + +st1b {z0.b-z1.b}, pn7, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: st1b {z0.b-z1.b}, pn7, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b {z0.b-z1.b}, pn8.b, [x13, #-8, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: st1b {z0.b-z1.b}, pn8.b, [x13, #-8, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate range + +st1b {z0.b-z3.b}, pn8, [x0, #-9, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: st1b {z0.b-z3.b}, pn8, [x0, #-9, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b {z0.b-z3.b}, pn8, [x0, #-36, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: st1b {z0.b-z3.b}, pn8, [x0, #-36, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1b {z0.b-z3.b}, pn8, [x0, #32, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: st1b {z0.b-z3.b}, pn8, [x0, #32, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/st1b.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st1b.s @@ -0,0 +1,110 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +st1b {z0.b-z1.b}, pn8, [x0, x0] // 10100000-00100000-00000000-00000000 +// CHECK-INST: st1b { z0.b, z1.b }, pn8, [x0, x0] +// CHECK-ENCODING: [0x00,0x00,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0200000 + +st1b {z20.b-z21.b}, pn13, [x10, x21] // 10100000-00110101-00010101-01010100 +// CHECK-INST: st1b { z20.b, z21.b }, pn13, [x10, x21] +// CHECK-ENCODING: [0x54,0x15,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0351554 + +st1b {z22.b-z23.b}, pn11, [x13, x8] // 10100000-00101000-00001101-10110110 +// CHECK-INST: st1b { z22.b, z23.b }, pn11, [x13, x8] +// CHECK-ENCODING: [0xb6,0x0d,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0280db6 + +st1b {z30.b-z31.b}, pn15, [sp, xzr] // 10100000-00111111-00011111-11111110 +// CHECK-INST: st1b { z30.b, z31.b }, pn15, [sp, xzr] +// CHECK-ENCODING: [0xfe,0x1f,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03f1ffe + +st1b {z0.b-z1.b}, pn8, [x0] // 10100000-01100000-00000000-00000000 +// CHECK-INST: st1b { z0.b, z1.b }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x00,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0600000 + +st1b {z20.b-z21.b}, pn13, [x10, #10, mul vl] // 10100000-01100101-00010101-01010100 +// CHECK-INST: st1b { z20.b, z21.b }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x54,0x15,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0651554 + +st1b {z22.b-z23.b}, pn11, [x13, #-16, mul vl] // 10100000-01101000-00001101-10110110 +// CHECK-INST: st1b { z22.b, z23.b }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb6,0x0d,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0680db6 + +st1b {z30.b-z31.b}, pn15, [sp, #-2, mul vl] // 10100000-01101111-00011111-11111110 +// CHECK-INST: st1b { z30.b, z31.b }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xfe,0x1f,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06f1ffe + +st1b {z0.b-z3.b}, pn8, [x0, x0] // 10100000-00100000-10000000-00000000 +// CHECK-INST: st1b { z0.b - z3.b }, pn8, [x0, x0] +// CHECK-ENCODING: [0x00,0x80,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0208000 + +st1b {z20.b-z23.b}, pn13, [x10, x21] // 10100000-00110101-10010101-01010100 +// CHECK-INST: st1b { z20.b - z23.b }, pn13, [x10, x21] +// CHECK-ENCODING: [0x54,0x95,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0359554 + +st1b {z20.b-z23.b}, pn11, [x13, x8] // 10100000-00101000-10001101-10110100 +// CHECK-INST: st1b { z20.b - z23.b }, pn11, [x13, x8] +// CHECK-ENCODING: [0xb4,0x8d,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0288db4 + +st1b {z28.b-z31.b}, pn15, [sp, xzr] // 10100000-00111111-10011111-11111100 +// CHECK-INST: st1b { z28.b - z31.b }, pn15, [sp, xzr] +// CHECK-ENCODING: [0xfc,0x9f,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03f9ffc + +st1b {z0.b-z3.b}, pn8, [x0] // 10100000-01100000-10000000-00000000 +// CHECK-INST: st1b { z0.b - z3.b }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x80,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0608000 + +st1b {z20.b-z23.b}, pn13, [x10, #20, mul vl] // 10100000-01100101-10010101-01010100 +// CHECK-INST: st1b { z20.b - z23.b }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x54,0x95,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0659554 + +st1b {z20.b-z23.b}, pn11, [x13, #-32, mul vl] // 10100000-01101000-10001101-10110100 +// CHECK-INST: st1b { z20.b - z23.b }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb4,0x8d,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0688db4 + +st1b {z28.b-z31.b}, pn15, [sp, #-4, mul vl] // 10100000-01101111-10011111-11111100 +// CHECK-INST: st1b { z28.b - z31.b }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfc,0x9f,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06f9ffc Index: llvm/test/MC/AArch64/SVE2p1/st1d-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st1d-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +st1d {z0.d-z2.d}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: st1d {z0.d-z2.d}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d {z1.d-z4.d}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: st1d {z1.d-z4.d}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d {z7.d-z8.d}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: st1d {z7.d-z8.d}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid predicate-as-counter register + +st1d {z0.d-z1.d}, pn7, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: st1d {z0.d-z1.d}, pn7, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d {z0.d-z1.d}, pn8.d, [x13, #-8, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: st1d {z0.d-z1.d}, pn8.d, [x13, #-8, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate range + +st1d {z0.d-z3.d}, pn8, [x0, #-9, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: st1d {z0.d-z3.d}, pn8, [x0, #-9, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d {z0.d-z3.d}, pn8, [x0, #-36, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: st1d {z0.d-z3.d}, pn8, [x0, #-36, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1d {z0.d-z3.d}, pn8, [x0, #32, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: st1d {z0.d-z3.d}, pn8, [x0, #32, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/st1d.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st1d.s @@ -0,0 +1,110 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +st1d {z0.d-z1.d}, pn8, [x0, x0, lsl #3] // 10100000-00100000-01100000-00000000 +// CHECK-INST: st1d { z0.d, z1.d }, pn8, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x00,0x60,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0206000 + +st1d {z20.d-z21.d}, pn13, [x10, x21, lsl #3] // 10100000-00110101-01110101-01010100 +// CHECK-INST: st1d { z20.d, z21.d }, pn13, [x10, x21, lsl #3] +// CHECK-ENCODING: [0x54,0x75,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0357554 + +st1d {z22.d-z23.d}, pn11, [x13, x8, lsl #3] // 10100000-00101000-01101101-10110110 +// CHECK-INST: st1d { z22.d, z23.d }, pn11, [x13, x8, lsl #3] +// CHECK-ENCODING: [0xb6,0x6d,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0286db6 + +st1d {z30.d-z31.d}, pn15, [sp, xzr, lsl #3] // 10100000-00111111-01111111-11111110 +// CHECK-INST: st1d { z30.d, z31.d }, pn15, [sp, xzr, lsl #3] +// CHECK-ENCODING: [0xfe,0x7f,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03f7ffe + +st1d {z0.d-z1.d}, pn8, [x0] // 10100000-01100000-01100000-00000000 +// CHECK-INST: st1d { z0.d, z1.d }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x60,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0606000 + +st1d {z20.d-z21.d}, pn13, [x10, #10, mul vl] // 10100000-01100101-01110101-01010100 +// CHECK-INST: st1d { z20.d, z21.d }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x54,0x75,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0657554 + +st1d {z22.d-z23.d}, pn11, [x13, #-16, mul vl] // 10100000-01101000-01101101-10110110 +// CHECK-INST: st1d { z22.d, z23.d }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb6,0x6d,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0686db6 + +st1d {z30.d-z31.d}, pn15, [sp, #-2, mul vl] // 10100000-01101111-01111111-11111110 +// CHECK-INST: st1d { z30.d, z31.d }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xfe,0x7f,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06f7ffe + +st1d {z0.d-z3.d}, pn8, [x0, x0, lsl #3] // 10100000-00100000-11100000-00000000 +// CHECK-INST: st1d { z0.d - z3.d }, pn8, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x00,0xe0,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a020e000 + +st1d {z20.d-z23.d}, pn13, [x10, x21, lsl #3] // 10100000-00110101-11110101-01010100 +// CHECK-INST: st1d { z20.d - z23.d }, pn13, [x10, x21, lsl #3] +// CHECK-ENCODING: [0x54,0xf5,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a035f554 + +st1d {z20.d-z23.d}, pn11, [x13, x8, lsl #3] // 10100000-00101000-11101101-10110100 +// CHECK-INST: st1d { z20.d - z23.d }, pn11, [x13, x8, lsl #3] +// CHECK-ENCODING: [0xb4,0xed,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a028edb4 + +st1d {z28.d-z31.d}, pn15, [sp, xzr, lsl #3] // 10100000-00111111-11111111-11111100 +// CHECK-INST: st1d { z28.d - z31.d }, pn15, [sp, xzr, lsl #3] +// CHECK-ENCODING: [0xfc,0xff,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03ffffc + +st1d {z0.d-z3.d}, pn8, [x0] // 10100000-01100000-11100000-00000000 +// CHECK-INST: st1d { z0.d - z3.d }, pn8, [x0] +// CHECK-ENCODING: [0x00,0xe0,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a060e000 + +st1d {z20.d-z23.d}, pn13, [x10, #20, mul vl] // 10100000-01100101-11110101-01010100 +// CHECK-INST: st1d { z20.d - z23.d }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x54,0xf5,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a065f554 + +st1d {z20.d-z23.d}, pn11, [x13, #-32, mul vl] // 10100000-01101000-11101101-10110100 +// CHECK-INST: st1d { z20.d - z23.d }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb4,0xed,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a068edb4 + +st1d {z28.d-z31.d}, pn15, [sp, #-4, mul vl] // 10100000-01101111-11111111-11111100 +// CHECK-INST: st1d { z28.d - z31.d }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfc,0xff,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06ffffc Index: llvm/test/MC/AArch64/SVE2p1/st1h-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st1h-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +st1h {z0.h-z2.h}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: st1h {z0.h-z2.h}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h {z1.h-z4.h}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: st1h {z1.h-z4.h}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h {z7.h-z8.h}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: st1h {z7.h-z8.h}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid predicate-as-counter register + +st1h {z0.h-z1.h}, pn7, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: st1h {z0.h-z1.h}, pn7, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h {z0.h-z1.h}, pn8.h, [x13, #-8, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: st1h {z0.h-z1.h}, pn8.h, [x13, #-8, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate range + +st1h {z0.h-z3.h}, pn8, [x0, #-9, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: st1h {z0.h-z3.h}, pn8, [x0, #-9, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h {z0.h-z3.h}, pn8, [x0, #-36, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: st1h {z0.h-z3.h}, pn8, [x0, #-36, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1h {z0.h-z3.h}, pn8, [x0, #32, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: st1h {z0.h-z3.h}, pn8, [x0, #32, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/st1h.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st1h.s @@ -0,0 +1,110 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +st1h {z0.h-z1.h}, pn8, [x0, x0, lsl #1] // 10100000-00100000-00100000-00000000 +// CHECK-INST: st1h { z0.h, z1.h }, pn8, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0x20,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0202000 + +st1h {z20.h-z21.h}, pn13, [x10, x21, lsl #1] // 10100000-00110101-00110101-01010100 +// CHECK-INST: st1h { z20.h, z21.h }, pn13, [x10, x21, lsl #1] +// CHECK-ENCODING: [0x54,0x35,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0353554 + +st1h {z22.h-z23.h}, pn11, [x13, x8, lsl #1] // 10100000-00101000-00101101-10110110 +// CHECK-INST: st1h { z22.h, z23.h }, pn11, [x13, x8, lsl #1] +// CHECK-ENCODING: [0xb6,0x2d,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0282db6 + +st1h {z30.h-z31.h}, pn15, [sp, xzr, lsl #1] // 10100000-00111111-00111111-11111110 +// CHECK-INST: st1h { z30.h, z31.h }, pn15, [sp, xzr, lsl #1] +// CHECK-ENCODING: [0xfe,0x3f,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03f3ffe + +st1h {z0.h-z1.h}, pn8, [x0] // 10100000-01100000-00100000-00000000 +// CHECK-INST: st1h { z0.h, z1.h }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x20,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0602000 + +st1h {z20.h-z21.h}, pn13, [x10, #10, mul vl] // 10100000-01100101-00110101-01010100 +// CHECK-INST: st1h { z20.h, z21.h }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x54,0x35,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0653554 + +st1h {z22.h-z23.h}, pn11, [x13, #-16, mul vl] // 10100000-01101000-00101101-10110110 +// CHECK-INST: st1h { z22.h, z23.h }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb6,0x2d,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0682db6 + +st1h {z30.h-z31.h}, pn15, [sp, #-2, mul vl] // 10100000-01101111-00111111-11111110 +// CHECK-INST: st1h { z30.h, z31.h }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xfe,0x3f,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06f3ffe + +st1h {z0.h-z3.h}, pn8, [x0, x0, lsl #1] // 10100000-00100000-10100000-00000000 +// CHECK-INST: st1h { z0.h - z3.h }, pn8, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0xa0,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a020a000 + +st1h {z20.h-z23.h}, pn13, [x10, x21, lsl #1] // 10100000-00110101-10110101-01010100 +// CHECK-INST: st1h { z20.h - z23.h }, pn13, [x10, x21, lsl #1] +// CHECK-ENCODING: [0x54,0xb5,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a035b554 + +st1h {z20.h-z23.h}, pn11, [x13, x8, lsl #1] // 10100000-00101000-10101101-10110100 +// CHECK-INST: st1h { z20.h - z23.h }, pn11, [x13, x8, lsl #1] +// CHECK-ENCODING: [0xb4,0xad,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a028adb4 + +st1h {z28.h-z31.h}, pn15, [sp, xzr, lsl #1] // 10100000-00111111-10111111-11111100 +// CHECK-INST: st1h { z28.h - z31.h }, pn15, [sp, xzr, lsl #1] +// CHECK-ENCODING: [0xfc,0xbf,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03fbffc + +st1h {z0.h-z3.h}, pn8, [x0] // 10100000-01100000-10100000-00000000 +// CHECK-INST: st1h { z0.h - z3.h }, pn8, [x0] +// CHECK-ENCODING: [0x00,0xa0,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a060a000 + +st1h {z20.h-z23.h}, pn13, [x10, #20, mul vl] // 10100000-01100101-10110101-01010100 +// CHECK-INST: st1h { z20.h - z23.h }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x54,0xb5,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a065b554 + +st1h {z20.h-z23.h}, pn11, [x13, #-32, mul vl] // 10100000-01101000-10101101-10110100 +// CHECK-INST: st1h { z20.h - z23.h }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb4,0xad,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a068adb4 + +st1h {z28.h-z31.h}, pn15, [sp, #-4, mul vl] // 10100000-01101111-10111111-11111100 +// CHECK-INST: st1h { z28.h - z31.h }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfc,0xbf,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06fbffc Index: llvm/test/MC/AArch64/SVE2p1/st1w-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st1w-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +st1w {z0.s-z2.s}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: st1w {z0.s-z2.s}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w {z1.s-z4.s}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: st1w {z1.s-z4.s}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w {z7.s-z8.s}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: st1w {z7.s-z8.s}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid predicate-as-counter register + +st1w {z0.s-z1.s}, pn7, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: st1w {z0.s-z1.s}, pn7, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w {z0.s-z1.s}, pn8.s, [x13, #-8, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: st1w {z0.s-z1.s}, pn8.s, [x13, #-8, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate range + +st1w {z0.s-z3.s}, pn8, [x0, #-9, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: st1w {z0.s-z3.s}, pn8, [x0, #-9, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w {z0.s-z3.s}, pn8, [x0, #-36, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: st1w {z0.s-z3.s}, pn8, [x0, #-36, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +st1w {z0.s-z3.s}, pn8, [x0, #32, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: st1w {z0.s-z3.s}, pn8, [x0, #32, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/st1w.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/st1w.s @@ -0,0 +1,110 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +st1w {z0.s-z1.s}, pn8, [x0, x0, lsl #2] // 10100000-00100000-01000000-00000000 +// CHECK-INST: st1w { z0.s, z1.s }, pn8, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x00,0x40,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0204000 + +st1w {z20.s-z21.s}, pn13, [x10, x21, lsl #2] // 10100000-00110101-01010101-01010100 +// CHECK-INST: st1w { z20.s, z21.s }, pn13, [x10, x21, lsl #2] +// CHECK-ENCODING: [0x54,0x55,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0355554 + +st1w {z22.s-z23.s}, pn11, [x13, x8, lsl #2] // 10100000-00101000-01001101-10110110 +// CHECK-INST: st1w { z22.s, z23.s }, pn11, [x13, x8, lsl #2] +// CHECK-ENCODING: [0xb6,0x4d,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0284db6 + +st1w {z30.s-z31.s}, pn15, [sp, xzr, lsl #2] // 10100000-00111111-01011111-11111110 +// CHECK-INST: st1w { z30.s, z31.s }, pn15, [sp, xzr, lsl #2] +// CHECK-ENCODING: [0xfe,0x5f,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03f5ffe + +st1w {z0.s-z1.s}, pn8, [x0] // 10100000-01100000-01000000-00000000 +// CHECK-INST: st1w { z0.s, z1.s }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x40,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0604000 + +st1w {z20.s-z21.s}, pn13, [x10, #10, mul vl] // 10100000-01100101-01010101-01010100 +// CHECK-INST: st1w { z20.s, z21.s }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x54,0x55,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0655554 + +st1w {z22.s-z23.s}, pn11, [x13, #-16, mul vl] // 10100000-01101000-01001101-10110110 +// CHECK-INST: st1w { z22.s, z23.s }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb6,0x4d,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0684db6 + +st1w {z30.s-z31.s}, pn15, [sp, #-2, mul vl] // 10100000-01101111-01011111-11111110 +// CHECK-INST: st1w { z30.s, z31.s }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xfe,0x5f,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06f5ffe + +st1w {z0.s-z3.s}, pn8, [x0, x0, lsl #2] // 10100000-00100000-11000000-00000000 +// CHECK-INST: st1w { z0.s - z3.s }, pn8, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x00,0xc0,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a020c000 + +st1w {z20.s-z23.s}, pn13, [x10, x21, lsl #2] // 10100000-00110101-11010101-01010100 +// CHECK-INST: st1w { z20.s - z23.s }, pn13, [x10, x21, lsl #2] +// CHECK-ENCODING: [0x54,0xd5,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a035d554 + +st1w {z20.s-z23.s}, pn11, [x13, x8, lsl #2] // 10100000-00101000-11001101-10110100 +// CHECK-INST: st1w { z20.s - z23.s }, pn11, [x13, x8, lsl #2] +// CHECK-ENCODING: [0xb4,0xcd,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a028cdb4 + +st1w {z28.s-z31.s}, pn15, [sp, xzr, lsl #2] // 10100000-00111111-11011111-11111100 +// CHECK-INST: st1w { z28.s - z31.s }, pn15, [sp, xzr, lsl #2] +// CHECK-ENCODING: [0xfc,0xdf,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03fdffc + +st1w {z0.s-z3.s}, pn8, [x0] // 10100000-01100000-11000000-00000000 +// CHECK-INST: st1w { z0.s - z3.s }, pn8, [x0] +// CHECK-ENCODING: [0x00,0xc0,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a060c000 + +st1w {z20.s-z23.s}, pn13, [x10, #20, mul vl] // 10100000-01100101-11010101-01010100 +// CHECK-INST: st1w { z20.s - z23.s }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x54,0xd5,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a065d554 + +st1w {z20.s-z23.s}, pn11, [x13, #-32, mul vl] // 10100000-01101000-11001101-10110100 +// CHECK-INST: st1w { z20.s - z23.s }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb4,0xcd,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a068cdb4 + +st1w {z28.s-z31.s}, pn15, [sp, #-4, mul vl] // 10100000-01101111-11011111-11111100 +// CHECK-INST: st1w { z28.s - z31.s }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfc,0xdf,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06fdffc Index: llvm/test/MC/AArch64/SVE2p1/stnt1b-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/stnt1b-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +stnt1b {z0.b-z2.b}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1b {z0.b-z2.b}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1b {z1.b-z4.b}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: stnt1b {z1.b-z4.b}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1b {z7.b-z8.b}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: stnt1b {z7.b-z8.b}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid predicate-as-counter register + +stnt1b {z0.b-z1.b}, pn7, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: stnt1b {z0.b-z1.b}, pn7, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1b {z0.b-z1.b}, pn8.b, [x13, #-8, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: stnt1b {z0.b-z1.b}, pn8.b, [x13, #-8, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate range + +stnt1b {z0.b-z3.b}, pn8, [x0, #-9, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: stnt1b {z0.b-z3.b}, pn8, [x0, #-9, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1b {z0.b-z3.b}, pn8, [x0, #-36, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: stnt1b {z0.b-z3.b}, pn8, [x0, #-36, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1b {z0.b-z3.b}, pn8, [x0, #32, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: stnt1b {z0.b-z3.b}, pn8, [x0, #32, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/stnt1b.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/stnt1b.s @@ -0,0 +1,110 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +stnt1b {z0.b-z1.b}, pn8, [x0, x0] // 10100000-00100000-00000000-00000001 +// CHECK-INST: stnt1b { z0.b, z1.b }, pn8, [x0, x0] +// CHECK-ENCODING: [0x01,0x00,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0200001 + +stnt1b {z20.b-z21.b}, pn13, [x10, x21] // 10100000-00110101-00010101-01010101 +// CHECK-INST: stnt1b { z20.b, z21.b }, pn13, [x10, x21] +// CHECK-ENCODING: [0x55,0x15,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0351555 + +stnt1b {z22.b-z23.b}, pn11, [x13, x8] // 10100000-00101000-00001101-10110111 +// CHECK-INST: stnt1b { z22.b, z23.b }, pn11, [x13, x8] +// CHECK-ENCODING: [0xb7,0x0d,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0280db7 + +stnt1b {z30.b-z31.b}, pn15, [sp, xzr] // 10100000-00111111-00011111-11111111 +// CHECK-INST: stnt1b { z30.b, z31.b }, pn15, [sp, xzr] +// CHECK-ENCODING: [0xff,0x1f,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03f1fff + +stnt1b {z0.b-z1.b}, pn8, [x0] // 10100000-01100000-00000000-00000001 +// CHECK-INST: stnt1b { z0.b, z1.b }, pn8, [x0] +// CHECK-ENCODING: [0x01,0x00,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0600001 + +stnt1b {z20.b-z21.b}, pn13, [x10, #10, mul vl] // 10100000-01100101-00010101-01010101 +// CHECK-INST: stnt1b { z20.b, z21.b }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x15,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0651555 + +stnt1b {z22.b-z23.b}, pn11, [x13, #-16, mul vl] // 10100000-01101000-00001101-10110111 +// CHECK-INST: stnt1b { z22.b, z23.b }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x0d,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0680db7 + +stnt1b {z30.b-z31.b}, pn15, [sp, #-2, mul vl] // 10100000-01101111-00011111-11111111 +// CHECK-INST: stnt1b { z30.b, z31.b }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0x1f,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06f1fff + +stnt1b {z0.b-z3.b}, pn8, [x0, x0] // 10100000-00100000-10000000-00000001 +// CHECK-INST: stnt1b { z0.b - z3.b }, pn8, [x0, x0] +// CHECK-ENCODING: [0x01,0x80,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0208001 + +stnt1b {z20.b-z23.b}, pn13, [x10, x21] // 10100000-00110101-10010101-01010101 +// CHECK-INST: stnt1b { z20.b - z23.b }, pn13, [x10, x21] +// CHECK-ENCODING: [0x55,0x95,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0359555 + +stnt1b {z20.b-z23.b}, pn11, [x13, x8] // 10100000-00101000-10001101-10110101 +// CHECK-INST: stnt1b { z20.b - z23.b }, pn11, [x13, x8] +// CHECK-ENCODING: [0xb5,0x8d,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0288db5 + +stnt1b {z28.b-z31.b}, pn15, [sp, xzr] // 10100000-00111111-10011111-11111101 +// CHECK-INST: stnt1b { z28.b - z31.b }, pn15, [sp, xzr] +// CHECK-ENCODING: [0xfd,0x9f,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03f9ffd + +stnt1b {z0.b-z3.b}, pn8, [x0] // 10100000-01100000-10000000-00000001 +// CHECK-INST: stnt1b { z0.b - z3.b }, pn8, [x0] +// CHECK-ENCODING: [0x01,0x80,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0608001 + +stnt1b {z20.b-z23.b}, pn13, [x10, #20, mul vl] // 10100000-01100101-10010101-01010101 +// CHECK-INST: stnt1b { z20.b - z23.b }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x55,0x95,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0659555 + +stnt1b {z20.b-z23.b}, pn11, [x13, #-32, mul vl] // 10100000-01101000-10001101-10110101 +// CHECK-INST: stnt1b { z20.b - z23.b }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb5,0x8d,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0688db5 + +stnt1b {z28.b-z31.b}, pn15, [sp, #-4, mul vl] // 10100000-01101111-10011111-11111101 +// CHECK-INST: stnt1b { z28.b - z31.b }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfd,0x9f,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06f9ffd Index: llvm/test/MC/AArch64/SVE2p1/stnt1d-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/stnt1d-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +stnt1d {z0.d-z2.d}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1d {z0.d-z2.d}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1d {z1.d-z4.d}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: stnt1d {z1.d-z4.d}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1d {z7.d-z8.d}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: stnt1d {z7.d-z8.d}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid predicate-as-counter register + +stnt1d {z0.d-z1.d}, pn7, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: stnt1d {z0.d-z1.d}, pn7, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1d {z0.d-z1.d}, pn8.d, [x13, #-8, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: stnt1d {z0.d-z1.d}, pn8.d, [x13, #-8, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate range + +stnt1d {z0.d-z3.d}, pn8, [x0, #-9, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: stnt1d {z0.d-z3.d}, pn8, [x0, #-9, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1d {z0.d-z3.d}, pn8, [x0, #-36, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: stnt1d {z0.d-z3.d}, pn8, [x0, #-36, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1d {z0.d-z3.d}, pn8, [x0, #32, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: stnt1d {z0.d-z3.d}, pn8, [x0, #32, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/stnt1d.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/stnt1d.s @@ -0,0 +1,110 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +stnt1d {z0.d-z1.d}, pn8, [x0, x0, lsl #3] // 10100000-00100000-01100000-00000001 +// CHECK-INST: stnt1d { z0.d, z1.d }, pn8, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x01,0x60,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0206001 + +stnt1d {z20.d-z21.d}, pn13, [x10, x21, lsl #3] // 10100000-00110101-01110101-01010101 +// CHECK-INST: stnt1d { z20.d, z21.d }, pn13, [x10, x21, lsl #3] +// CHECK-ENCODING: [0x55,0x75,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0357555 + +stnt1d {z22.d-z23.d}, pn11, [x13, x8, lsl #3] // 10100000-00101000-01101101-10110111 +// CHECK-INST: stnt1d { z22.d, z23.d }, pn11, [x13, x8, lsl #3] +// CHECK-ENCODING: [0xb7,0x6d,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0286db7 + +stnt1d {z30.d-z31.d}, pn15, [sp, xzr, lsl #3] // 10100000-00111111-01111111-11111111 +// CHECK-INST: stnt1d { z30.d, z31.d }, pn15, [sp, xzr, lsl #3] +// CHECK-ENCODING: [0xff,0x7f,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03f7fff + +stnt1d {z0.d-z1.d}, pn8, [x0] // 10100000-01100000-01100000-00000001 +// CHECK-INST: stnt1d { z0.d, z1.d }, pn8, [x0] +// CHECK-ENCODING: [0x01,0x60,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0606001 + +stnt1d {z20.d-z21.d}, pn13, [x10, #10, mul vl] // 10100000-01100101-01110101-01010101 +// CHECK-INST: stnt1d { z20.d, z21.d }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x75,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0657555 + +stnt1d {z22.d-z23.d}, pn11, [x13, #-16, mul vl] // 10100000-01101000-01101101-10110111 +// CHECK-INST: stnt1d { z22.d, z23.d }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x6d,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0686db7 + +stnt1d {z30.d-z31.d}, pn15, [sp, #-2, mul vl] // 10100000-01101111-01111111-11111111 +// CHECK-INST: stnt1d { z30.d, z31.d }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0x7f,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06f7fff + +stnt1d {z0.d-z3.d}, pn8, [x0, x0, lsl #3] // 10100000-00100000-11100000-00000001 +// CHECK-INST: stnt1d { z0.d - z3.d }, pn8, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x01,0xe0,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a020e001 + +stnt1d {z20.d-z23.d}, pn13, [x10, x21, lsl #3] // 10100000-00110101-11110101-01010101 +// CHECK-INST: stnt1d { z20.d - z23.d }, pn13, [x10, x21, lsl #3] +// CHECK-ENCODING: [0x55,0xf5,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a035f555 + +stnt1d {z20.d-z23.d}, pn11, [x13, x8, lsl #3] // 10100000-00101000-11101101-10110101 +// CHECK-INST: stnt1d { z20.d - z23.d }, pn11, [x13, x8, lsl #3] +// CHECK-ENCODING: [0xb5,0xed,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a028edb5 + +stnt1d {z28.d-z31.d}, pn15, [sp, xzr, lsl #3] // 10100000-00111111-11111111-11111101 +// CHECK-INST: stnt1d { z28.d - z31.d }, pn15, [sp, xzr, lsl #3] +// CHECK-ENCODING: [0xfd,0xff,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03ffffd + +stnt1d {z0.d-z3.d}, pn8, [x0] // 10100000-01100000-11100000-00000001 +// CHECK-INST: stnt1d { z0.d - z3.d }, pn8, [x0] +// CHECK-ENCODING: [0x01,0xe0,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a060e001 + +stnt1d {z20.d-z23.d}, pn13, [x10, #20, mul vl] // 10100000-01100101-11110101-01010101 +// CHECK-INST: stnt1d { z20.d - z23.d }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x55,0xf5,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a065f555 + +stnt1d {z20.d-z23.d}, pn11, [x13, #-32, mul vl] // 10100000-01101000-11101101-10110101 +// CHECK-INST: stnt1d { z20.d - z23.d }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb5,0xed,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a068edb5 + +stnt1d {z28.d-z31.d}, pn15, [sp, #-4, mul vl] // 10100000-01101111-11111111-11111101 +// CHECK-INST: stnt1d { z28.d - z31.d }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfd,0xff,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06ffffd Index: llvm/test/MC/AArch64/SVE2p1/stnt1h-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/stnt1h-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +stnt1h {z0.h-z2.h}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1h {z0.h-z2.h}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1h {z1.h-z4.h}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: stnt1h {z1.h-z4.h}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1h {z7.h-z8.h}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: stnt1h {z7.h-z8.h}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid predicate-as-counter register + +stnt1h {z0.h-z1.h}, pn7, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: stnt1h {z0.h-z1.h}, pn7, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1h {z0.h-z1.h}, pn8.h, [x13, #-8, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: stnt1h {z0.h-z1.h}, pn8.h, [x13, #-8, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate range + +stnt1h {z0.h-z3.h}, pn8, [x0, #-9, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: stnt1h {z0.h-z3.h}, pn8, [x0, #-9, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1h {z0.h-z3.h}, pn8, [x0, #-36, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: stnt1h {z0.h-z3.h}, pn8, [x0, #-36, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1h {z0.h-z3.h}, pn8, [x0, #32, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: stnt1h {z0.h-z3.h}, pn8, [x0, #32, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/stnt1h.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/stnt1h.s @@ -0,0 +1,110 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +stnt1h {z0.h-z1.h}, pn8, [x0, x0, lsl #1] // 10100000-00100000-00100000-00000001 +// CHECK-INST: stnt1h { z0.h, z1.h }, pn8, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x01,0x20,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0202001 + +stnt1h {z20.h-z21.h}, pn13, [x10, x21, lsl #1] // 10100000-00110101-00110101-01010101 +// CHECK-INST: stnt1h { z20.h, z21.h }, pn13, [x10, x21, lsl #1] +// CHECK-ENCODING: [0x55,0x35,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0353555 + +stnt1h {z22.h-z23.h}, pn11, [x13, x8, lsl #1] // 10100000-00101000-00101101-10110111 +// CHECK-INST: stnt1h { z22.h, z23.h }, pn11, [x13, x8, lsl #1] +// CHECK-ENCODING: [0xb7,0x2d,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0282db7 + +stnt1h {z30.h-z31.h}, pn15, [sp, xzr, lsl #1] // 10100000-00111111-00111111-11111111 +// CHECK-INST: stnt1h { z30.h, z31.h }, pn15, [sp, xzr, lsl #1] +// CHECK-ENCODING: [0xff,0x3f,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03f3fff + +stnt1h {z0.h-z1.h}, pn8, [x0] // 10100000-01100000-00100000-00000001 +// CHECK-INST: stnt1h { z0.h, z1.h }, pn8, [x0] +// CHECK-ENCODING: [0x01,0x20,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0602001 + +stnt1h {z20.h-z21.h}, pn13, [x10, #10, mul vl] // 10100000-01100101-00110101-01010101 +// CHECK-INST: stnt1h { z20.h, z21.h }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x35,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0653555 + +stnt1h {z22.h-z23.h}, pn11, [x13, #-16, mul vl] // 10100000-01101000-00101101-10110111 +// CHECK-INST: stnt1h { z22.h, z23.h }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x2d,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0682db7 + +stnt1h {z30.h-z31.h}, pn15, [sp, #-2, mul vl] // 10100000-01101111-00111111-11111111 +// CHECK-INST: stnt1h { z30.h, z31.h }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0x3f,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06f3fff + +stnt1h {z0.h-z3.h}, pn8, [x0, x0, lsl #1] // 10100000-00100000-10100000-00000001 +// CHECK-INST: stnt1h { z0.h - z3.h }, pn8, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x01,0xa0,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a020a001 + +stnt1h {z20.h-z23.h}, pn13, [x10, x21, lsl #1] // 10100000-00110101-10110101-01010101 +// CHECK-INST: stnt1h { z20.h - z23.h }, pn13, [x10, x21, lsl #1] +// CHECK-ENCODING: [0x55,0xb5,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a035b555 + +stnt1h {z20.h-z23.h}, pn11, [x13, x8, lsl #1] // 10100000-00101000-10101101-10110101 +// CHECK-INST: stnt1h { z20.h - z23.h }, pn11, [x13, x8, lsl #1] +// CHECK-ENCODING: [0xb5,0xad,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a028adb5 + +stnt1h {z28.h-z31.h}, pn15, [sp, xzr, lsl #1] // 10100000-00111111-10111111-11111101 +// CHECK-INST: stnt1h { z28.h - z31.h }, pn15, [sp, xzr, lsl #1] +// CHECK-ENCODING: [0xfd,0xbf,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03fbffd + +stnt1h {z0.h-z3.h}, pn8, [x0] // 10100000-01100000-10100000-00000001 +// CHECK-INST: stnt1h { z0.h - z3.h }, pn8, [x0] +// CHECK-ENCODING: [0x01,0xa0,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a060a001 + +stnt1h {z20.h-z23.h}, pn13, [x10, #20, mul vl] // 10100000-01100101-10110101-01010101 +// CHECK-INST: stnt1h { z20.h - z23.h }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x55,0xb5,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a065b555 + +stnt1h {z20.h-z23.h}, pn11, [x13, #-32, mul vl] // 10100000-01101000-10101101-10110101 +// CHECK-INST: stnt1h { z20.h - z23.h }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb5,0xad,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a068adb5 + +stnt1h {z28.h-z31.h}, pn15, [sp, #-4, mul vl] // 10100000-01101111-10111111-11111101 +// CHECK-INST: stnt1h { z28.h - z31.h }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfd,0xbf,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06fbffd Index: llvm/test/MC/AArch64/SVE2p1/stnt1w-diagnostics.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/stnt1w-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +stnt1w {z0.s-z2.s}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: stnt1w {z0.s-z2.s}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1w {z1.s-z4.s}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: stnt1w {z1.s-z4.s}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1w {z7.s-z8.s}, pn8, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: stnt1w {z7.s-z8.s}, pn8, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid predicate-as-counter register + +stnt1w {z0.s-z1.s}, pn7, [x0, x0, lsl #3] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: stnt1w {z0.s-z1.s}, pn7, [x0, x0, lsl #3] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1w {z0.s-z1.s}, pn8.s, [x13, #-8, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate-as-counter register expected pn8..pn15 +// CHECK-NEXT: stnt1w {z0.s-z1.s}, pn8.s, [x13, #-8, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate range + +stnt1w {z0.s-z3.s}, pn8, [x0, #-9, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: stnt1w {z0.s-z3.s}, pn8, [x0, #-9, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1w {z0.s-z3.s}, pn8, [x0, #-36, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: stnt1w {z0.s-z3.s}, pn8, [x0, #-36, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +stnt1w {z0.s-z3.s}, pn8, [x0, #32, mul vl] +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [-32, 28] +// CHECK-NEXT: stnt1w {z0.s-z3.s}, pn8, [x0, #32, mul vl] +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE2p1/stnt1w.s =================================================================== --- /dev/null +++ llvm/test/MC/AArch64/SVE2p1/stnt1w.s @@ -0,0 +1,110 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + +stnt1w {z0.s-z1.s}, pn8, [x0, x0, lsl #2] // 10100000-00100000-01000000-00000001 +// CHECK-INST: stnt1w { z0.s, z1.s }, pn8, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x01,0x40,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0204001 + +stnt1w {z20.s-z21.s}, pn13, [x10, x21, lsl #2] // 10100000-00110101-01010101-01010101 +// CHECK-INST: stnt1w { z20.s, z21.s }, pn13, [x10, x21, lsl #2] +// CHECK-ENCODING: [0x55,0x55,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0355555 + +stnt1w {z22.s-z23.s}, pn11, [x13, x8, lsl #2] // 10100000-00101000-01001101-10110111 +// CHECK-INST: stnt1w { z22.s, z23.s }, pn11, [x13, x8, lsl #2] +// CHECK-ENCODING: [0xb7,0x4d,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0284db7 + +stnt1w {z30.s-z31.s}, pn15, [sp, xzr, lsl #2] // 10100000-00111111-01011111-11111111 +// CHECK-INST: stnt1w { z30.s, z31.s }, pn15, [sp, xzr, lsl #2] +// CHECK-ENCODING: [0xff,0x5f,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03f5fff + +stnt1w {z0.s-z1.s}, pn8, [x0] // 10100000-01100000-01000000-00000001 +// CHECK-INST: stnt1w { z0.s, z1.s }, pn8, [x0] +// CHECK-ENCODING: [0x01,0x40,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0604001 + +stnt1w {z20.s-z21.s}, pn13, [x10, #10, mul vl] // 10100000-01100101-01010101-01010101 +// CHECK-INST: stnt1w { z20.s, z21.s }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x55,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0655555 + +stnt1w {z22.s-z23.s}, pn11, [x13, #-16, mul vl] // 10100000-01101000-01001101-10110111 +// CHECK-INST: stnt1w { z22.s, z23.s }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x4d,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0684db7 + +stnt1w {z30.s-z31.s}, pn15, [sp, #-2, mul vl] // 10100000-01101111-01011111-11111111 +// CHECK-INST: stnt1w { z30.s, z31.s }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0x5f,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06f5fff + +stnt1w {z0.s-z3.s}, pn8, [x0, x0, lsl #2] // 10100000-00100000-11000000-00000001 +// CHECK-INST: stnt1w { z0.s - z3.s }, pn8, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x01,0xc0,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a020c001 + +stnt1w {z20.s-z23.s}, pn13, [x10, x21, lsl #2] // 10100000-00110101-11010101-01010101 +// CHECK-INST: stnt1w { z20.s - z23.s }, pn13, [x10, x21, lsl #2] +// CHECK-ENCODING: [0x55,0xd5,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a035d555 + +stnt1w {z20.s-z23.s}, pn11, [x13, x8, lsl #2] // 10100000-00101000-11001101-10110101 +// CHECK-INST: stnt1w { z20.s - z23.s }, pn11, [x13, x8, lsl #2] +// CHECK-ENCODING: [0xb5,0xcd,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a028cdb5 + +stnt1w {z28.s-z31.s}, pn15, [sp, xzr, lsl #2] // 10100000-00111111-11011111-11111101 +// CHECK-INST: stnt1w { z28.s - z31.s }, pn15, [sp, xzr, lsl #2] +// CHECK-ENCODING: [0xfd,0xdf,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03fdffd + +stnt1w {z0.s-z3.s}, pn8, [x0] // 10100000-01100000-11000000-00000001 +// CHECK-INST: stnt1w { z0.s - z3.s }, pn8, [x0] +// CHECK-ENCODING: [0x01,0xc0,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a060c001 + +stnt1w {z20.s-z23.s}, pn13, [x10, #20, mul vl] // 10100000-01100101-11010101-01010101 +// CHECK-INST: stnt1w { z20.s - z23.s }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x55,0xd5,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a065d555 + +stnt1w {z20.s-z23.s}, pn11, [x13, #-32, mul vl] // 10100000-01101000-11001101-10110101 +// CHECK-INST: stnt1w { z20.s - z23.s }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb5,0xcd,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a068cdb5 + +stnt1w {z28.s-z31.s}, pn15, [sp, #-4, mul vl] // 10100000-01101111-11011111-11111101 +// CHECK-INST: stnt1w { z28.s - z31.s }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfd,0xdf,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06fdffd