diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -109,7 +109,7 @@ bool selectInterpP1F16(MachineInstr &MI) const; bool selectWritelane(MachineInstr &MI) const; bool selectDivScale(MachineInstr &MI) const; - bool selectIntrinsicIcmp(MachineInstr &MI) const; + bool selectIntrinsicCmp(MachineInstr &MI) const; bool selectBallot(MachineInstr &I) const; bool selectRelocConstant(MachineInstr &I) const; bool selectGroupStaticSize(MachineInstr &I) const; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -1093,9 +1093,10 @@ case Intrinsic::amdgcn_div_scale: return selectDivScale(I); case Intrinsic::amdgcn_icmp: + case Intrinsic::amdgcn_fcmp: if (selectImpl(I, *CoverageInfo)) return true; - return selectIntrinsicIcmp(I); + return selectIntrinsicCmp(I); case Intrinsic::amdgcn_ballot: return selectBallot(I); case Intrinsic::amdgcn_reloc_constant: @@ -1174,6 +1175,55 @@ case CmpInst::ICMP_ULE: return Select(AMDGPU::V_CMP_LE_U16_e64, AMDGPU::V_CMP_LE_U16_t16_e64, AMDGPU::V_CMP_LE_U32_e64, AMDGPU::V_CMP_LE_U64_e64); + + case CmpInst::FCMP_OEQ: + return Select(AMDGPU::V_CMP_EQ_F16_e64, AMDGPU::V_CMP_EQ_F16_t16_e64, + AMDGPU::V_CMP_EQ_F32_e64, AMDGPU::V_CMP_EQ_F64_e64); + case CmpInst::FCMP_OGT: + return Select(AMDGPU::V_CMP_GT_F16_e64, AMDGPU::V_CMP_GT_F16_t16_e64, + AMDGPU::V_CMP_GT_F32_e64, AMDGPU::V_CMP_GT_F64_e64); + case CmpInst::FCMP_OGE: + return Select(AMDGPU::V_CMP_GE_F16_e64, AMDGPU::V_CMP_GE_F16_t16_e64, + AMDGPU::V_CMP_GE_F32_e64, AMDGPU::V_CMP_GE_F64_e64); + case CmpInst::FCMP_OLT: + return Select(AMDGPU::V_CMP_LT_F16_e64, AMDGPU::V_CMP_LT_F16_t16_e64, + AMDGPU::V_CMP_LT_F32_e64, AMDGPU::V_CMP_LT_F64_e64); + case CmpInst::FCMP_OLE: + return Select(AMDGPU::V_CMP_LE_F16_e64, AMDGPU::V_CMP_LE_F16_t16_e64, + AMDGPU::V_CMP_LE_F32_e64, AMDGPU::V_CMP_LE_F64_e64); + case CmpInst::FCMP_ONE: + return Select(AMDGPU::V_CMP_NEQ_F16_e64, AMDGPU::V_CMP_NEQ_F16_t16_e64, + AMDGPU::V_CMP_NEQ_F32_e64, AMDGPU::V_CMP_NEQ_F64_e64); + case CmpInst::FCMP_ORD: + return Select(AMDGPU::V_CMP_O_F16_e64, AMDGPU::V_CMP_O_F16_t16_e64, + AMDGPU::V_CMP_O_F32_e64, AMDGPU::V_CMP_O_F64_e64); + case CmpInst::FCMP_UNO: + return Select(AMDGPU::V_CMP_U_F16_e64, AMDGPU::V_CMP_U_F16_t16_e64, + AMDGPU::V_CMP_U_F32_e64, AMDGPU::V_CMP_U_F64_e64); + case CmpInst::FCMP_UEQ: + return Select(AMDGPU::V_CMP_NLG_F16_e64, AMDGPU::V_CMP_NLG_F16_t16_e64, + AMDGPU::V_CMP_NLG_F32_e64, AMDGPU::V_CMP_NLG_F64_e64); + case CmpInst::FCMP_UGT: + return Select(AMDGPU::V_CMP_NLE_F16_e64, AMDGPU::V_CMP_NLE_F16_t16_e64, + AMDGPU::V_CMP_NLE_F32_e64, AMDGPU::V_CMP_NLE_F64_e64); + case CmpInst::FCMP_UGE: + return Select(AMDGPU::V_CMP_NLT_F16_e64, AMDGPU::V_CMP_NLT_F16_t16_e64, + AMDGPU::V_CMP_NLT_F32_e64, AMDGPU::V_CMP_NLT_F64_e64); + case CmpInst::FCMP_ULT: + return Select(AMDGPU::V_CMP_NGE_F16_e64, AMDGPU::V_CMP_NGE_F16_t16_e64, + AMDGPU::V_CMP_NGE_F32_e64, AMDGPU::V_CMP_NGE_F64_e64); + case CmpInst::FCMP_ULE: + return Select(AMDGPU::V_CMP_NGT_F16_e64, AMDGPU::V_CMP_NGT_F16_t16_e64, + AMDGPU::V_CMP_NGT_F32_e64, AMDGPU::V_CMP_NGT_F64_e64); + case CmpInst::FCMP_UNE: + return Select(AMDGPU::V_CMP_NEQ_F16_e64, AMDGPU::V_CMP_NEQ_F16_t16_e64, + AMDGPU::V_CMP_NEQ_F32_e64, AMDGPU::V_CMP_NEQ_F64_e64); + case CmpInst::FCMP_TRUE: + return Select(AMDGPU::V_CMP_TRU_F16_e64, AMDGPU::V_CMP_TRU_F16_t16_e64, + AMDGPU::V_CMP_TRU_F32_e64, AMDGPU::V_CMP_TRU_F64_e64); + case CmpInst::FCMP_FALSE: + return Select(AMDGPU::V_CMP_F_F16_e64, AMDGPU::V_CMP_F_F16_t16_e64, + AMDGPU::V_CMP_F_F32_e64, AMDGPU::V_CMP_F_F64_e64); } } @@ -1263,12 +1313,13 @@ return Ret; } -bool AMDGPUInstructionSelector::selectIntrinsicIcmp(MachineInstr &I) const { +bool AMDGPUInstructionSelector::selectIntrinsicCmp(MachineInstr &I) const { Register Dst = I.getOperand(0).getReg(); if (isVCC(Dst, *MRI)) return false; - if (MRI->getType(Dst).getSizeInBits() != STI.getWavefrontSize()) + LLT DstTy = MRI->getType(Dst); + if (DstTy.getSizeInBits() != STI.getWavefrontSize()) return false; MachineBasicBlock *BB = I.getParent(); @@ -1281,22 +1332,44 @@ return false; auto Pred = static_cast(I.getOperand(4).getImm()); - if (!CmpInst::isIntPredicate(Pred)) { + if (!CmpInst::isIntPredicate(Pred) && !CmpInst::isFPPredicate(Pred)) { BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Dst); I.eraseFromParent(); return RBI.constrainGenericRegister(Dst, *TRI.getBoolRC(), *MRI); } - int Opcode = getV_CMPOpcode(Pred, Size, *Subtarget); + const int Opcode = getV_CMPOpcode(Pred, Size, *Subtarget); if (Opcode == -1) return false; - MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode), Dst) - .add(I.getOperand(2)) - .add(I.getOperand(3)); + MachineInstr *SelectedMI; + if (CmpInst::isFPPredicate(Pred)) { + MachineOperand &LHS = I.getOperand(2); + MachineOperand &RHS = I.getOperand(3); + auto [Src0, Src0Mods] = selectVOP3ModsImpl(LHS); + auto [Src1, Src1Mods] = selectVOP3ModsImpl(RHS); + Register Src0Reg = + copyToVGPRIfSrcFolded(Src0, Src0Mods, LHS, &I, /*ForceVGPR*/ true); + Register Src1Reg = + copyToVGPRIfSrcFolded(Src1, Src1Mods, RHS, &I, /*ForceVGPR*/ true); + SelectedMI = BuildMI(*BB, &I, DL, TII.get(Opcode), Dst) + .addImm(Src0Mods) + .addReg(Src0Reg) + .addImm(Src1Mods) + .addReg(Src1Reg) + .addImm(0); // clamp + } else { + SelectedMI = BuildMI(*BB, &I, DL, TII.get(Opcode), Dst) + .add(I.getOperand(2)) + .add(I.getOperand(3)); + } + RBI.constrainGenericRegister(Dst, *TRI.getBoolRC(), *MRI); + if (!constrainSelectedInstRegOperands(*SelectedMI, TII, TRI, RBI)) + return false; + I.eraseFromParent(); - return constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI); + return true; } bool AMDGPUInstructionSelector::selectBallot(MachineInstr &I) const { diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir @@ -0,0 +1,150 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize32" -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s + +--- +name: fcmp_false_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; CHECK-LABEL: name: fcmp_false_f16 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_CVT_F16_F32_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CVT_F16_F32_t16_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CMP_F_F16_t16_e64_:%[0-9]+]]:sreg_32 = V_CMP_F_F16_t16_e64 0, [[V_CVT_F16_F32_t16_e64_]], 0, [[V_CVT_F16_F32_t16_e64_1]], 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F16_t16_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr1 + %2:vgpr(s16) = G_FPTRUNC %0 + %3:vgpr(s16) = G_FPTRUNC %1 + %4:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fcmp), %2, %3, 0 + S_ENDPGM 0, implicit %4 +... + +--- +name: fcmp_true_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; CHECK-LABEL: name: fcmp_true_f16 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_CVT_F16_F32_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CVT_F16_F32_t16_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CMP_TRU_F16_t16_e64_:%[0-9]+]]:sreg_32 = V_CMP_TRU_F16_t16_e64 0, [[V_CVT_F16_F32_t16_e64_]], 0, [[V_CVT_F16_F32_t16_e64_1]], 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F16_t16_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr1 + %2:vgpr(s16) = G_FPTRUNC %0 + %3:vgpr(s16) = G_FPTRUNC %1 + %4:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fcmp), %2, %3, 15 + S_ENDPGM 0, implicit %4 +... + +--- +name: fcmp_false_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; CHECK-LABEL: name: fcmp_false_f32 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_CMP_F_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_F_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F32_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr1 + %4:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fcmp), %0, %1, 0 + S_ENDPGM 0, implicit %4 +... + +--- +name: fcmp_true_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; CHECK-LABEL: name: fcmp_true_f32 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_CMP_TRU_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_TRU_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F32_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr1 + %4:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fcmp), %0, %1, 15 + S_ENDPGM 0, implicit %4 +... + +--- +name: fcmp_false_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; CHECK-LABEL: name: fcmp_false_f64 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_CVT_F64_F32_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CVT_F64_F32_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CMP_F_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_F_F64_e64 0, [[V_CVT_F64_F32_e64_]], 0, [[V_CVT_F64_F32_e64_1]], 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F64_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr1 + %2:vgpr(s64) = G_FPEXT %0 + %3:vgpr(s64) = G_FPEXT %1 + %4:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fcmp), %2, %3, 0 + S_ENDPGM 0, implicit %4 +... + +--- +name: fcmp_true_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; CHECK-LABEL: name: fcmp_true_f64 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_CVT_F64_F32_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CVT_F64_F32_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CMP_TRU_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_TRU_F64_e64 0, [[V_CVT_F64_F32_e64_]], 0, [[V_CVT_F64_F32_e64_1]], 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F64_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr1 + %2:vgpr(s64) = G_FPEXT %0 + %3:vgpr(s64) = G_FPEXT %1 + %4:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fcmp), %2, %3, 15 + S_ENDPGM 0, implicit %4 +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir @@ -0,0 +1,150 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize64" -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s + +--- +name: fcmp_false_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; CHECK-LABEL: name: fcmp_false_f16 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_CVT_F16_F32_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CVT_F16_F32_t16_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CMP_F_F16_t16_e64_:%[0-9]+]]:sreg_64 = V_CMP_F_F16_t16_e64 0, [[V_CVT_F16_F32_t16_e64_]], 0, [[V_CVT_F16_F32_t16_e64_1]], 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F16_t16_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr1 + %2:vgpr(s16) = G_FPTRUNC %0 + %3:vgpr(s16) = G_FPTRUNC %1 + %4:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fcmp), %2, %3, 0 + S_ENDPGM 0, implicit %4 +... + +--- +name: fcmp_true_f16 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; CHECK-LABEL: name: fcmp_true_f16 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_CVT_F16_F32_t16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CVT_F16_F32_t16_e64_1:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CMP_TRU_F16_t16_e64_:%[0-9]+]]:sreg_64 = V_CMP_TRU_F16_t16_e64 0, [[V_CVT_F16_F32_t16_e64_]], 0, [[V_CVT_F16_F32_t16_e64_1]], 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F16_t16_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr1 + %2:vgpr(s16) = G_FPTRUNC %0 + %3:vgpr(s16) = G_FPTRUNC %1 + %4:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fcmp), %2, %3, 15 + S_ENDPGM 0, implicit %4 +... + +--- +name: fcmp_false_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; CHECK-LABEL: name: fcmp_false_f32 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_CMP_F_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_F_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F32_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr1 + %4:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fcmp), %0, %1, 0 + S_ENDPGM 0, implicit %4 +... + +--- +name: fcmp_true_f32 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; CHECK-LABEL: name: fcmp_true_f32 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_CMP_TRU_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_TRU_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F32_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr1 + %4:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fcmp), %0, %1, 15 + S_ENDPGM 0, implicit %4 +... + +--- +name: fcmp_false_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; CHECK-LABEL: name: fcmp_false_f64 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_CVT_F64_F32_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CVT_F64_F32_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CMP_F_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_F_F64_e64 0, [[V_CVT_F64_F32_e64_]], 0, [[V_CVT_F64_F32_e64_1]], 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_F_F64_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr1 + %2:vgpr(s64) = G_FPEXT %0 + %3:vgpr(s64) = G_FPEXT %1 + %4:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fcmp), %2, %3, 0 + S_ENDPGM 0, implicit %4 +... + +--- +name: fcmp_true_f64 +legalized: true +regBankSelected: true +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + ; CHECK-LABEL: name: fcmp_true_f64 + ; CHECK: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[V_CVT_F64_F32_e64_:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CVT_F64_F32_e64_1:%[0-9]+]]:vreg_64 = nofpexcept V_CVT_F64_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec + ; CHECK-NEXT: [[V_CMP_TRU_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_TRU_F64_e64 0, [[V_CVT_F64_F32_e64_]], 0, [[V_CVT_F64_F32_e64_1]], 0, implicit $mode, implicit $exec + ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CMP_TRU_F64_e64_]] + %0:vgpr(s32) = COPY $vgpr0 + %1:vgpr(s32) = COPY $vgpr1 + %2:vgpr(s64) = G_FPEXT %0 + %3:vgpr(s64) = G_FPEXT %1 + %4:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fcmp), %2, %3, 15 + S_ENDPGM 0, implicit %4 +... diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll deleted file mode 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll +++ /dev/null @@ -1,1920 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize64" -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11 %s -; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s -; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s - -declare i64 @llvm.amdgcn.fcmp.f32(float, float, i32) #0 -declare i64 @llvm.amdgcn.fcmp.f64(double, double, i32) #0 -declare float @llvm.fabs.f32(float) #0 - -declare i64 @llvm.amdgcn.fcmp.f16(half, half, i32) #0 -declare half @llvm.fabs.f16(half) #0 - -define amdgpu_kernel void @v_fcmp_f32_oeq_with_fabs(i64 addrspace(1)* %out, float %src, float %a) { -; GFX11-LABEL: v_fcmp_f32_oeq_with_fabs: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, |s3| -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_oeq_with_fabs: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s3 -; VI-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, |v0| -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_oeq_with_fabs: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s3 -; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, |v0| -; GFX9-NEXT: v_mov_b32_e32 v0, s2 -; GFX9-NEXT: v_mov_b32_e32 v1, s3 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] -; GFX9-NEXT: s_endpgm - %temp = call float @llvm.fabs.f32(float %a) - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float %temp, i32 1) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f32_oeq_both_operands_with_fabs(i64 addrspace(1)* %out, float %src, float %a) { -; GFX11-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_f32_e64 s[2:3], |s2|, |s3| -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_mov_b32_e32 v0, s3 -; VI-NEXT: v_cmp_eq_f32_e64 s[2:3], |s2|, |v0| -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s3 -; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], |s2|, |v0| -; GFX9-NEXT: v_mov_b32_e32 v0, s2 -; GFX9-NEXT: v_mov_b32_e32 v1, s3 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] -; GFX9-NEXT: s_endpgm - %temp = call float @llvm.fabs.f32(float %a) - %src_input = call float @llvm.fabs.f32(float %src) - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src_input, float %temp, i32 1) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f32(i64 addrspace(1)* %out, float %src) { -; GCN-LABEL: v_fcmp_f32: -; GCN: ; %bb.0: -; GCN-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 -1) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f32_oeq(i64 addrspace(1)* %out, float %src) { -; GFX11-LABEL: v_fcmp_f32_oeq: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_f32_e64 s[2:3], 0x42c80000, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_oeq: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_oeq: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_eq_f32_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 1) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f32_one(i64 addrspace(1)* %out, float %src) { -; GFX11-LABEL: v_fcmp_f32_one: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_neq_f32_e64 s[2:3], 0x42c80000, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_one: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_one: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_neq_f32_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 6) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f32_ogt(i64 addrspace(1)* %out, float %src) { -; GFX11-LABEL: v_fcmp_f32_ogt: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_lt_f32_e64 s[2:3], 0x42c80000, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_ogt: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_gt_f32_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_ogt: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_gt_f32_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 2) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f32_oge(i64 addrspace(1)* %out, float %src) { -; GFX11-LABEL: v_fcmp_f32_oge: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_le_f32_e64 s[2:3], 0x42c80000, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_oge: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_ge_f32_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_oge: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 3) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f32_olt(i64 addrspace(1)* %out, float %src) { -; GFX11-LABEL: v_fcmp_f32_olt: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_gt_f32_e64 s[2:3], 0x42c80000, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_olt: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_lt_f32_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_olt: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_lt_f32_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 4) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f32_ole(i64 addrspace(1)* %out, float %src) { -; GFX11-LABEL: v_fcmp_f32_ole: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_ge_f32_e64 s[2:3], 0x42c80000, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_ole: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_le_f32_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_ole: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_le_f32_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 5) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f32_ueq(i64 addrspace(1)* %out, float %src) { -; GFX11-LABEL: v_fcmp_f32_ueq: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_nlg_f32_e64 s[2:3], 0x42c80000, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_ueq: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_nlg_f32_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_ueq: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_nlg_f32_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 9) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f32_une(i64 addrspace(1)* %out, float %src) { -; GFX11-LABEL: v_fcmp_f32_une: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_neq_f32_e64 s[2:3], 0x42c80000, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_une: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_une: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_neq_f32_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 14) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f32_ugt(i64 addrspace(1)* %out, float %src) { -; GFX11-LABEL: v_fcmp_f32_ugt: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_nge_f32_e64 s[2:3], 0x42c80000, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_ugt: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_nle_f32_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_ugt: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_nle_f32_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 10) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f32_uge(i64 addrspace(1)* %out, float %src) { -; GFX11-LABEL: v_fcmp_f32_uge: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_ngt_f32_e64 s[2:3], 0x42c80000, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_uge: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_nlt_f32_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_uge: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_nlt_f32_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 11) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f32_ult(i64 addrspace(1)* %out, float %src) { -; GFX11-LABEL: v_fcmp_f32_ult: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_nle_f32_e64 s[2:3], 0x42c80000, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_ult: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_nge_f32_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_ult: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_nge_f32_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 12) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f32_ule(i64 addrspace(1)* %out, float %src) { -; GFX11-LABEL: v_fcmp_f32_ule: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_nlt_f32_e64 s[2:3], 0x42c80000, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f32_ule: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f32_ule: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_ngt_f32_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 13) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f64_oeq(i64 addrspace(1)* %out, double %src) { -; GFX11-LABEL: v_fcmp_f64_oeq: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: s_mov_b32 s4, 0 -; GFX11-NEXT: s_mov_b32 s5, 0x40590000 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_f64_e64 s[2:3], s[2:3], s[4:5] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f64_oeq: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0 -; VI-NEXT: v_mov_b32_e32 v1, 0x40590000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1] -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f64_oeq: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v1, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s3 -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 1) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f64_one(i64 addrspace(1)* %out, double %src) { -; GFX11-LABEL: v_fcmp_f64_one: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: s_mov_b32 s4, 0 -; GFX11-NEXT: s_mov_b32 s5, 0x40590000 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], s[4:5] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f64_one: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0 -; VI-NEXT: v_mov_b32_e32 v1, 0x40590000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1] -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f64_one: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v1, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s3 -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 6) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f64_ogt(i64 addrspace(1)* %out, double %src) { -; GFX11-LABEL: v_fcmp_f64_ogt: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: s_mov_b32 s4, 0 -; GFX11-NEXT: s_mov_b32 s5, 0x40590000 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_gt_f64_e64 s[2:3], s[2:3], s[4:5] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f64_ogt: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0 -; VI-NEXT: v_mov_b32_e32 v1, 0x40590000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1] -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f64_ogt: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v1, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s3 -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 2) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f64_oge(i64 addrspace(1)* %out, double %src) { -; GFX11-LABEL: v_fcmp_f64_oge: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: s_mov_b32 s4, 0 -; GFX11-NEXT: s_mov_b32 s5, 0x40590000 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_ge_f64_e64 s[2:3], s[2:3], s[4:5] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f64_oge: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0 -; VI-NEXT: v_mov_b32_e32 v1, 0x40590000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1] -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f64_oge: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v1, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s3 -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 3) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f64_olt(i64 addrspace(1)* %out, double %src) { -; GFX11-LABEL: v_fcmp_f64_olt: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: s_mov_b32 s4, 0 -; GFX11-NEXT: s_mov_b32 s5, 0x40590000 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_lt_f64_e64 s[2:3], s[2:3], s[4:5] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f64_olt: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0 -; VI-NEXT: v_mov_b32_e32 v1, 0x40590000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1] -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f64_olt: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v1, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s3 -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 4) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f64_ole(i64 addrspace(1)* %out, double %src) { -; GFX11-LABEL: v_fcmp_f64_ole: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: s_mov_b32 s4, 0 -; GFX11-NEXT: s_mov_b32 s5, 0x40590000 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_le_f64_e64 s[2:3], s[2:3], s[4:5] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f64_ole: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0 -; VI-NEXT: v_mov_b32_e32 v1, 0x40590000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1] -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f64_ole: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v1, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s3 -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 5) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f64_ueq(i64 addrspace(1)* %out, double %src) { -; GFX11-LABEL: v_fcmp_f64_ueq: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: s_mov_b32 s4, 0 -; GFX11-NEXT: s_mov_b32 s5, 0x40590000 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[2:3], s[4:5] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f64_ueq: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0 -; VI-NEXT: v_mov_b32_e32 v1, 0x40590000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1] -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f64_ueq: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v1, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s3 -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 9) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f64_une(i64 addrspace(1)* %out, double %src) { -; GFX11-LABEL: v_fcmp_f64_une: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: s_mov_b32 s4, 0 -; GFX11-NEXT: s_mov_b32 s5, 0x40590000 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], s[4:5] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f64_une: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0 -; VI-NEXT: v_mov_b32_e32 v1, 0x40590000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1] -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f64_une: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v1, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s3 -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 14) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f64_ugt(i64 addrspace(1)* %out, double %src) { -; GFX11-LABEL: v_fcmp_f64_ugt: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: s_mov_b32 s4, 0 -; GFX11-NEXT: s_mov_b32 s5, 0x40590000 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_nle_f64_e64 s[2:3], s[2:3], s[4:5] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f64_ugt: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0 -; VI-NEXT: v_mov_b32_e32 v1, 0x40590000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1] -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f64_ugt: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v1, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s3 -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 10) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f64_uge(i64 addrspace(1)* %out, double %src) { -; GFX11-LABEL: v_fcmp_f64_uge: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: s_mov_b32 s4, 0 -; GFX11-NEXT: s_mov_b32 s5, 0x40590000 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], s[4:5] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f64_uge: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0 -; VI-NEXT: v_mov_b32_e32 v1, 0x40590000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1] -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f64_uge: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v1, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s3 -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 11) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f64_ult(i64 addrspace(1)* %out, double %src) { -; GFX11-LABEL: v_fcmp_f64_ult: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: s_mov_b32 s4, 0 -; GFX11-NEXT: s_mov_b32 s5, 0x40590000 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_nge_f64_e64 s[2:3], s[2:3], s[4:5] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f64_ult: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0 -; VI-NEXT: v_mov_b32_e32 v1, 0x40590000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1] -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f64_ult: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v1, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s3 -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 12) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f64_ule(i64 addrspace(1)* %out, double %src) { -; GFX11-LABEL: v_fcmp_f64_ule: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 -; GFX11-NEXT: s_mov_b32 s4, 0 -; GFX11-NEXT: s_mov_b32 s5, 0x40590000 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_ngt_f64_e64 s[2:3], s[2:3], s[4:5] -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f64_ule: -; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0 -; VI-NEXT: v_mov_b32_e32 v1, 0x40590000 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1] -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f64_ule: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1] -; GFX9-NEXT: v_mov_b32_e32 v1, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s3 -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 13) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_oeq_with_fabs(i64 addrspace(1)* %out, half %src, half %a) { -; GFX11-LABEL: v_fcmp_f16_oeq_with_fabs: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s3, s2, 16 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, |s3| -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_oeq_with_fabs: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: s_lshr_b32 s3, s2, 16 -; VI-NEXT: v_mov_b32_e32 v0, s3 -; VI-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, |v0| -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_oeq_with_fabs: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: s_lshr_b32 s0, s4, 16 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_cmp_eq_f16_e64 s[0:1], s4, |v0| -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %temp = call half @llvm.fabs.f16(half %a) - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half %temp, i32 1) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_oeq_both_operands_with_fabs(i64 addrspace(1)* %out, half %src, half %a) { -; GFX11-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_lshr_b32 s3, s2, 16 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cmp_eq_f16_e64 s[2:3], |s2|, |s3| -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: s_lshr_b32 s3, s2, 16 -; VI-NEXT: v_mov_b32_e32 v0, s3 -; VI-NEXT: v_cmp_eq_f16_e64 s[2:3], |s2|, |v0| -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: s_lshr_b32 s0, s4, 16 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_cmp_eq_f16_e64 s[0:1], |s4|, |v0| -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %temp = call half @llvm.fabs.f16(half %a) - %src_input = call half @llvm.fabs.f16(half %src) - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src_input, half %temp, i32 1) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -define amdgpu_kernel void @v_fcmp_f16(i64 addrspace(1)* %out, half %src) { -; GCN-LABEL: v_fcmp_f16: -; GCN: ; %bb.0: -; GCN-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 -1) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_oeq(i64 addrspace(1)* %out, half %src) { -; GFX11-LABEL: v_fcmp_f16_oeq: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_eq_f16_e64 s[2:3], 0x5640, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_oeq: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x5640 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_oeq: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_eq_f16_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 1) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_one(i64 addrspace(1)* %out, half %src) { -; GFX11-LABEL: v_fcmp_f16_one: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_neq_f16_e64 s[2:3], 0x5640, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_one: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x5640 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_one: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_neq_f16_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 6) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_ogt(i64 addrspace(1)* %out, half %src) { -; GFX11-LABEL: v_fcmp_f16_ogt: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_lt_f16_e64 s[2:3], 0x5640, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_ogt: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x5640 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_gt_f16_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_ogt: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_gt_f16_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 2) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_oge(i64 addrspace(1)* %out, half %src) { -; GFX11-LABEL: v_fcmp_f16_oge: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_le_f16_e64 s[2:3], 0x5640, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_oge: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x5640 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_ge_f16_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_oge: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_ge_f16_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 3) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_olt(i64 addrspace(1)* %out, half %src) { -; GFX11-LABEL: v_fcmp_f16_olt: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_gt_f16_e64 s[2:3], 0x5640, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_olt: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x5640 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_lt_f16_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_olt: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_lt_f16_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 4) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_ole(i64 addrspace(1)* %out, half %src) { -; GFX11-LABEL: v_fcmp_f16_ole: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_ge_f16_e64 s[2:3], 0x5640, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_ole: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x5640 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_le_f16_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_ole: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_le_f16_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 5) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_ueq(i64 addrspace(1)* %out, half %src) { -; GFX11-LABEL: v_fcmp_f16_ueq: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_nlg_f16_e64 s[2:3], 0x5640, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_ueq: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x5640 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_nlg_f16_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_ueq: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_nlg_f16_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 9) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_une(i64 addrspace(1)* %out, half %src) { -; GFX11-LABEL: v_fcmp_f16_une: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_neq_f16_e64 s[2:3], 0x5640, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_une: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x5640 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_une: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_neq_f16_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 14) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_ugt(i64 addrspace(1)* %out, half %src) { -; GFX11-LABEL: v_fcmp_f16_ugt: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_nge_f16_e64 s[2:3], 0x5640, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_ugt: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x5640 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_nle_f16_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_ugt: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_nle_f16_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 10) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_uge(i64 addrspace(1)* %out, half %src) { -; GFX11-LABEL: v_fcmp_f16_uge: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_ngt_f16_e64 s[2:3], 0x5640, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_uge: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x5640 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_nlt_f16_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_uge: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_nlt_f16_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 11) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_ult(i64 addrspace(1)* %out, half %src) { -; GFX11-LABEL: v_fcmp_f16_ult: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_nle_f16_e64 s[2:3], 0x5640, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_ult: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x5640 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_nge_f16_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_ult: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_nge_f16_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 12) - store i64 %result, i64 addrspace(1)* %out - ret void -} - - -define amdgpu_kernel void @v_fcmp_f16_ule(i64 addrspace(1)* %out, half %src) { -; GFX11-LABEL: v_fcmp_f16_ule: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_cmp_nlt_f16_e64 s[2:3], 0x5640, s2 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_mov_b32_e32 v0, s2 -; GFX11-NEXT: v_mov_b32_e32 v1, s3 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm -; -; VI-LABEL: v_fcmp_f16_ule: -; VI: ; %bb.0: -; VI-NEXT: s_load_dword s2, s[0:1], 0x2c -; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; VI-NEXT: v_mov_b32_e32 v0, 0x5640 -; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: v_cmp_ngt_f16_e64 s[2:3], s2, v0 -; VI-NEXT: v_mov_b32_e32 v0, s0 -; VI-NEXT: v_mov_b32_e32 v2, s2 -; VI-NEXT: v_mov_b32_e32 v1, s1 -; VI-NEXT: v_mov_b32_e32 v3, s3 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] -; VI-NEXT: s_endpgm -; -; GFX9-LABEL: v_fcmp_f16_ule: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 -; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_cmp_ngt_f16_e64 s[0:1], s4, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] -; GFX9-NEXT: s_endpgm - %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 13) - store i64 %result, i64 addrspace(1)* %out - ret void -} - -attributes #0 = { nounwind readnone convergent } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll @@ -0,0 +1,2332 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize32" -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11,SDAG-GFX11 %s +; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr="+wavefrontsize32" -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,SDAG-GFX10 %s + +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize32" -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11,GISEL-GFX11 %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -mattr="+wavefrontsize32" -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GISEL-GFX10 %s + +declare i32 @llvm.amdgcn.fcmp.f32(float, float, i32) #0 +declare i32 @llvm.amdgcn.fcmp.f64(double, double, i32) #0 +declare float @llvm.fabs.f32(float) #0 + +declare i32 @llvm.amdgcn.fcmp.f16(half, half, i32) #0 +declare half @llvm.fabs.f16(half) #0 + +define amdgpu_kernel void @v_fcmp_f32_oeq_with_fabs(i32 addrspace(1)* %out, float %src, float %a) { +; SDAG-GFX11-LABEL: v_fcmp_f32_oeq_with_fabs: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_eq_f32_e64 s2, s2, |s3| +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_oeq_with_fabs: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_eq_f32_e64 s2, s2, |s3| +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_oeq_with_fabs: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_eq_f32_e64 s2, s2, |s3| +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_oeq_with_fabs: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_eq_f32_e64 s2, s2, |s3| +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %temp = call float @llvm.fabs.f32(float %a) + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float %temp, i32 1) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_oeq_both_operands_with_fabs(i32 addrspace(1)* %out, float %src, float %a) { +; SDAG-GFX11-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_eq_f32_e64 s2, |s2|, |s3| +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_eq_f32_e64 s2, |s2|, |s3| +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_eq_f32_e64 s2, |s2|, |s3| +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_eq_f32_e64 s2, |s2|, |s3| +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %temp = call float @llvm.fabs.f32(float %a) + %src_input = call float @llvm.fabs.f32(float %src) + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src_input, float %temp, i32 1) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32(i32 addrspace(1)* %out, float %src) { +; SDAG-GFX11-LABEL: v_fcmp_f32: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: global_store_b32 v0, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: global_store_dword v0, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 -1) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_oeq(i32 addrspace(1)* %out, float %src) { +; SDAG-GFX11-LABEL: v_fcmp_f32_oeq: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_eq_f32_e64 s2, 0x42c80000, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_oeq: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_eq_f32_e64 s0, 0x42c80000, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_oeq: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_eq_f32_e64 s2, 0x42c80000, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_oeq: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_eq_f32_e64 s0, 0x42c80000, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 1) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_one(i32 addrspace(1)* %out, float %src) { +; SDAG-GFX11-LABEL: v_fcmp_f32_one: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_neq_f32_e64 s2, 0x42c80000, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_one: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_neq_f32_e64 s0, 0x42c80000, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_one: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_neq_f32_e64 s2, 0x42c80000, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_one: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_neq_f32_e64 s0, 0x42c80000, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 6) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_ogt(i32 addrspace(1)* %out, float %src) { +; SDAG-GFX11-LABEL: v_fcmp_f32_ogt: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_lt_f32_e64 s2, 0x42c80000, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_ogt: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_lt_f32_e64 s0, 0x42c80000, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_ogt: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_lt_f32_e64 s2, 0x42c80000, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_ogt: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_lt_f32_e64 s0, 0x42c80000, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 2) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_oge(i32 addrspace(1)* %out, float %src) { +; SDAG-GFX11-LABEL: v_fcmp_f32_oge: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_le_f32_e64 s2, 0x42c80000, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_oge: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_le_f32_e64 s0, 0x42c80000, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_oge: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_le_f32_e64 s2, 0x42c80000, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_oge: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_le_f32_e64 s0, 0x42c80000, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 3) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_olt(i32 addrspace(1)* %out, float %src) { +; SDAG-GFX11-LABEL: v_fcmp_f32_olt: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x42c80000, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_olt: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_gt_f32_e64 s0, 0x42c80000, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_olt: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_gt_f32_e64 s2, 0x42c80000, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_olt: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_gt_f32_e64 s0, 0x42c80000, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 4) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_ole(i32 addrspace(1)* %out, float %src) { +; SDAG-GFX11-LABEL: v_fcmp_f32_ole: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_ge_f32_e64 s2, 0x42c80000, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_ole: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_ge_f32_e64 s0, 0x42c80000, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_ole: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_ge_f32_e64 s2, 0x42c80000, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_ole: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_ge_f32_e64 s0, 0x42c80000, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 5) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f32_ueq(i32 addrspace(1)* %out, float %src) { +; SDAG-GFX11-LABEL: v_fcmp_f32_ueq: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_nlg_f32_e64 s2, 0x42c80000, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_ueq: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_nlg_f32_e64 s0, 0x42c80000, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_ueq: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_nlg_f32_e64 s2, 0x42c80000, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_ueq: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_nlg_f32_e64 s0, 0x42c80000, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 9) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_une(i32 addrspace(1)* %out, float %src) { +; SDAG-GFX11-LABEL: v_fcmp_f32_une: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_neq_f32_e64 s2, 0x42c80000, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_une: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_neq_f32_e64 s0, 0x42c80000, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_une: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_neq_f32_e64 s2, 0x42c80000, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_une: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_neq_f32_e64 s0, 0x42c80000, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 14) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_ugt(i32 addrspace(1)* %out, float %src) { +; SDAG-GFX11-LABEL: v_fcmp_f32_ugt: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_nge_f32_e64 s2, 0x42c80000, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_ugt: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_nge_f32_e64 s0, 0x42c80000, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_ugt: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_nge_f32_e64 s2, 0x42c80000, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_ugt: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_nge_f32_e64 s0, 0x42c80000, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 10) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_uge(i32 addrspace(1)* %out, float %src) { +; SDAG-GFX11-LABEL: v_fcmp_f32_uge: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_ngt_f32_e64 s2, 0x42c80000, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_uge: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_ngt_f32_e64 s0, 0x42c80000, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_uge: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_ngt_f32_e64 s2, 0x42c80000, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_uge: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_ngt_f32_e64 s0, 0x42c80000, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 11) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_ult(i32 addrspace(1)* %out, float %src) { +; SDAG-GFX11-LABEL: v_fcmp_f32_ult: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0x42c80000, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_ult: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_nle_f32_e64 s0, 0x42c80000, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_ult: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_nle_f32_e64 s2, 0x42c80000, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_ult: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_nle_f32_e64 s0, 0x42c80000, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 12) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_ule(i32 addrspace(1)* %out, float %src) { +; SDAG-GFX11-LABEL: v_fcmp_f32_ule: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_nlt_f32_e64 s2, 0x42c80000, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f32_ule: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_nlt_f32_e64 s0, 0x42c80000, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32_ule: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_nlt_f32_e64 s2, 0x42c80000, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f32_ule: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_nlt_f32_e64 s0, 0x42c80000, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 13) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_oeq(i32 addrspace(1)* %out, double %src) { +; SDAG-GFX11-LABEL: v_fcmp_f64_oeq: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_eq_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f64_oeq: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_eq_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f64_oeq: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_eq_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f64_oeq: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_eq_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 1) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_one(i32 addrspace(1)* %out, double %src) { +; SDAG-GFX11-LABEL: v_fcmp_f64_one: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_neq_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f64_one: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_neq_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f64_one: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_neq_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f64_one: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_neq_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 6) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_ogt(i32 addrspace(1)* %out, double %src) { +; SDAG-GFX11-LABEL: v_fcmp_f64_ogt: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_gt_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f64_ogt: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_gt_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f64_ogt: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_gt_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f64_ogt: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_gt_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 2) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_oge(i32 addrspace(1)* %out, double %src) { +; SDAG-GFX11-LABEL: v_fcmp_f64_oge: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_ge_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f64_oge: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_ge_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f64_oge: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_ge_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f64_oge: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_ge_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 3) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_olt(i32 addrspace(1)* %out, double %src) { +; SDAG-GFX11-LABEL: v_fcmp_f64_olt: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_lt_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f64_olt: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_lt_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f64_olt: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_lt_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f64_olt: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_lt_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 4) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_ole(i32 addrspace(1)* %out, double %src) { +; SDAG-GFX11-LABEL: v_fcmp_f64_ole: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_le_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f64_ole: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_le_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f64_ole: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_le_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f64_ole: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_le_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 5) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_ueq(i32 addrspace(1)* %out, double %src) { +; SDAG-GFX11-LABEL: v_fcmp_f64_ueq: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_nlg_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f64_ueq: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_nlg_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f64_ueq: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_nlg_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f64_ueq: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_nlg_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 9) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_une(i32 addrspace(1)* %out, double %src) { +; SDAG-GFX11-LABEL: v_fcmp_f64_une: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_neq_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f64_une: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_neq_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f64_une: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_neq_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f64_une: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_neq_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 14) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_ugt(i32 addrspace(1)* %out, double %src) { +; SDAG-GFX11-LABEL: v_fcmp_f64_ugt: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_nle_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f64_ugt: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_nle_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f64_ugt: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_nle_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f64_ugt: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_nle_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 10) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_uge(i32 addrspace(1)* %out, double %src) { +; SDAG-GFX11-LABEL: v_fcmp_f64_uge: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_nlt_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f64_uge: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_nlt_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f64_uge: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_nlt_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f64_uge: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_nlt_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 11) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_ult(i32 addrspace(1)* %out, double %src) { +; SDAG-GFX11-LABEL: v_fcmp_f64_ult: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_nge_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f64_ult: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_nge_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f64_ult: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_nge_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f64_ult: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_nge_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 12) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_ule(i32 addrspace(1)* %out, double %src) { +; SDAG-GFX11-LABEL: v_fcmp_f64_ule: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_ngt_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f64_ule: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: s_mov_b32 s4, 0 +; SDAG-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_ngt_f64_e64 s2, s[2:3], s[4:5] +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f64_ule: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GISEL-GFX11-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_ngt_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f64_ule: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX10-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_ngt_f64_e64 s2, s[2:3], s[4:5] +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 13) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_oeq_with_fabs(i32 addrspace(1)* %out, half %src, half %a) { +; SDAG-GFX11-LABEL: v_fcmp_f16_oeq_with_fabs: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: s_lshr_b32 s3, s2, 16 +; SDAG-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_cmp_eq_f16_e64 s2, s2, |s3| +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_oeq_with_fabs: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: s_lshr_b32 s0, s4, 16 +; SDAG-GFX10-NEXT: v_cmp_eq_f16_e64 s0, s4, |s0| +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_oeq_with_fabs: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: s_lshr_b32 s3, s2, 16 +; GISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_cmp_eq_f16_e64 s2, s2, |s3| +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_oeq_with_fabs: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: s_lshr_b32 s0, s4, 16 +; GISEL-GFX10-NEXT: v_cmp_eq_f16_e64 s0, s4, |s0| +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %temp = call half @llvm.fabs.f16(half %a) + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half %temp, i32 1) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_oeq_both_operands_with_fabs(i32 addrspace(1)* %out, half %src, half %a) { +; SDAG-GFX11-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: s_lshr_b32 s3, s2, 16 +; SDAG-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_cmp_eq_f16_e64 s2, |s2|, |s3| +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: s_lshr_b32 s0, s4, 16 +; SDAG-GFX10-NEXT: v_cmp_eq_f16_e64 s0, |s4|, |s0| +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: s_lshr_b32 s3, s2, 16 +; GISEL-GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_cmp_eq_f16_e64 s2, |s2|, |s3| +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: s_lshr_b32 s0, s4, 16 +; GISEL-GFX10-NEXT: v_cmp_eq_f16_e64 s0, |s4|, |s0| +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %temp = call half @llvm.fabs.f16(half %a) + %src_input = call half @llvm.fabs.f16(half %src) + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src_input, half %temp, i32 1) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f16(i32 addrspace(1)* %out, half %src) { +; SDAG-GFX11-LABEL: v_fcmp_f16: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: global_store_b32 v0, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: global_store_dword v0, v0, s[0:1] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 -1) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_oeq(i32 addrspace(1)* %out, half %src) { +; SDAG-GFX11-LABEL: v_fcmp_f16_oeq: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_eq_f16_e64 s2, 0x5640, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_oeq: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_eq_f16_e64 s0, 0x5640, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_oeq: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_eq_f16_e64 s2, 0x5640, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_oeq: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_eq_f16_e64 s0, 0x5640, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 1) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_one(i32 addrspace(1)* %out, half %src) { +; SDAG-GFX11-LABEL: v_fcmp_f16_one: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_neq_f16_e64 s2, 0x5640, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_one: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_neq_f16_e64 s0, 0x5640, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_one: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_neq_f16_e64 s2, 0x5640, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_one: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_neq_f16_e64 s0, 0x5640, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 6) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_ogt(i32 addrspace(1)* %out, half %src) { +; SDAG-GFX11-LABEL: v_fcmp_f16_ogt: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_lt_f16_e64 s2, 0x5640, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_ogt: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_lt_f16_e64 s0, 0x5640, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_ogt: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_lt_f16_e64 s2, 0x5640, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_ogt: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_lt_f16_e64 s0, 0x5640, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 2) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_oge(i32 addrspace(1)* %out, half %src) { +; SDAG-GFX11-LABEL: v_fcmp_f16_oge: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_le_f16_e64 s2, 0x5640, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_oge: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_le_f16_e64 s0, 0x5640, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_oge: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_le_f16_e64 s2, 0x5640, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_oge: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_le_f16_e64 s0, 0x5640, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 3) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_olt(i32 addrspace(1)* %out, half %src) { +; SDAG-GFX11-LABEL: v_fcmp_f16_olt: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_gt_f16_e64 s2, 0x5640, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_olt: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_gt_f16_e64 s0, 0x5640, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_olt: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_gt_f16_e64 s2, 0x5640, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_olt: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_gt_f16_e64 s0, 0x5640, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 4) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_ole(i32 addrspace(1)* %out, half %src) { +; SDAG-GFX11-LABEL: v_fcmp_f16_ole: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_ge_f16_e64 s2, 0x5640, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_ole: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_ge_f16_e64 s0, 0x5640, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_ole: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_ge_f16_e64 s2, 0x5640, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_ole: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_ge_f16_e64 s0, 0x5640, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 5) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_ueq(i32 addrspace(1)* %out, half %src) { +; SDAG-GFX11-LABEL: v_fcmp_f16_ueq: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_nlg_f16_e64 s2, 0x5640, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_ueq: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_nlg_f16_e64 s0, 0x5640, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_ueq: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_nlg_f16_e64 s2, 0x5640, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_ueq: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_nlg_f16_e64 s0, 0x5640, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 9) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_une(i32 addrspace(1)* %out, half %src) { +; SDAG-GFX11-LABEL: v_fcmp_f16_une: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_neq_f16_e64 s2, 0x5640, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_une: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_neq_f16_e64 s0, 0x5640, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_une: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_neq_f16_e64 s2, 0x5640, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_une: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_neq_f16_e64 s0, 0x5640, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 14) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_ugt(i32 addrspace(1)* %out, half %src) { +; SDAG-GFX11-LABEL: v_fcmp_f16_ugt: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_nge_f16_e64 s2, 0x5640, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_ugt: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_nge_f16_e64 s0, 0x5640, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_ugt: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_nge_f16_e64 s2, 0x5640, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_ugt: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_nge_f16_e64 s0, 0x5640, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 10) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_uge(i32 addrspace(1)* %out, half %src) { +; SDAG-GFX11-LABEL: v_fcmp_f16_uge: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_ngt_f16_e64 s2, 0x5640, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_uge: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_ngt_f16_e64 s0, 0x5640, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_uge: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_ngt_f16_e64 s2, 0x5640, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_uge: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_ngt_f16_e64 s0, 0x5640, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 11) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_ult(i32 addrspace(1)* %out, half %src) { +; SDAG-GFX11-LABEL: v_fcmp_f16_ult: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_nle_f16_e64 s2, 0x5640, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_ult: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_nle_f16_e64 s0, 0x5640, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_ult: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_nle_f16_e64 s2, 0x5640, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_ult: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_nle_f16_e64 s0, 0x5640, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 12) + store i32 %result, i32 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_ule(i32 addrspace(1)* %out, half %src) { +; SDAG-GFX11-LABEL: v_fcmp_f16_ule: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_clause 0x1 +; SDAG-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; SDAG-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; SDAG-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX11-NEXT: v_cmp_nlt_f16_e64 s2, 0x5640, s2 +; SDAG-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; SDAG-GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 +; SDAG-GFX11-NEXT: global_store_b32 v0, v1, s[0:1] +; SDAG-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-GFX10-LABEL: v_fcmp_f16_ule: +; SDAG-GFX10: ; %bb.0: +; SDAG-GFX10-NEXT: s_clause 0x1 +; SDAG-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; SDAG-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX10-NEXT: v_cmp_nlt_f16_e64 s0, 0x5640, s4 +; SDAG-GFX10-NEXT: v_mov_b32_e32 v1, s0 +; SDAG-GFX10-NEXT: global_store_dword v0, v1, s[2:3] +; SDAG-GFX10-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16_ule: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_clause 0x1 +; GISEL-GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: v_cmp_nlt_f16_e64 s2, 0x5640, s2 +; GISEL-GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX11-NEXT: global_store_b32 v1, v0, s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-GFX10-LABEL: v_fcmp_f16_ule: +; GISEL-GFX10: ; %bb.0: +; GISEL-GFX10-NEXT: s_clause 0x1 +; GISEL-GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c +; GISEL-GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GISEL-GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX10-NEXT: v_cmp_nlt_f16_e64 s0, 0x5640, s4 +; GISEL-GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-GFX10-NEXT: global_store_dword v1, v0, s[2:3] +; GISEL-GFX10-NEXT: s_endpgm + %result = call i32 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 13) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone convergent } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GCN: {{.*}} +; GFX10: {{.*}} +; GFX11: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll @@ -0,0 +1,2729 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize64" -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11 %s +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s + +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -mattr="+wavefrontsize64" -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11,GISEL-GFX11 %s +; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,GISEL-VI %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,GISEL-GFX9 %s + +declare i64 @llvm.amdgcn.fcmp.f32(float, float, i32) #0 +declare i64 @llvm.amdgcn.fcmp.f64(double, double, i32) #0 +declare float @llvm.fabs.f32(float) #0 + +declare i64 @llvm.amdgcn.fcmp.f16(half, half, i32) #0 +declare half @llvm.fabs.f16(half) #0 + +define amdgpu_kernel void @v_fcmp_f32_oeq_with_fabs(i64 addrspace(1)* %out, float %src, float %a) { +; GFX11-LABEL: v_fcmp_f32_oeq_with_fabs: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, |s3| +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_oeq_with_fabs: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, |v0| +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_oeq_with_fabs: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s3 +; GISEL-VI-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, |v0| +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_oeq_with_fabs: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s3 +; SDAG-VI-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, |v0| +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %temp = call float @llvm.fabs.f32(float %a) + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float %temp, i32 1) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_oeq_both_operands_with_fabs(i64 addrspace(1)* %out, float %src, float %a) { +; GFX11-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_f32_e64 s[2:3], |s2|, |s3| +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mov_b32_e32 v0, s3 +; GFX9-NEXT: v_cmp_eq_f32_e64 s[2:3], |s2|, |v0| +; GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s3 +; GISEL-VI-NEXT: v_cmp_eq_f32_e64 s[2:3], |s2|, |v0| +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s3 +; SDAG-VI-NEXT: v_cmp_eq_f32_e64 s[2:3], |s2|, |v0| +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %temp = call float @llvm.fabs.f32(float %a) + %src_input = call float @llvm.fabs.f32(float %src) + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src_input, float %temp, i32 1) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32(i64 addrspace(1)* %out, float %src) { +; SDAG-GFX-LABEL: v_fcmp_f32: +; SDAG-GFX: ; %bb.0: +; SDAG-GFX-NEXT: s_endpgm +; +; SDAG-GFX11-LABEL: v_fcmp_f32: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-VI-LABEL: v_fcmp_f32: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_endpgm +; +; SDAG-GFX9-LABEL: v_fcmp_f32: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f32: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: global_store_b64 v0, v[0:1], s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s1 +; GISEL-VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f32: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; GISEL-GFX-LABEL: v_fcmp_f32: +; GISEL-GFX: ; %bb.0: +; GISEL-GFX-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-GFX-NEXT: v_mov_b32_e32 v0, 0 +; GISEL-GFX-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1] +; GISEL-GFX-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 -1) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_oeq(i64 addrspace(1)* %out, float %src) { +; GFX11-LABEL: v_fcmp_f32_oeq: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_f32_e64 s[2:3], 0x42c80000, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_oeq: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_f32_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_oeq: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_oeq: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_eq_f32_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 1) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_one(i64 addrspace(1)* %out, float %src) { +; GFX11-LABEL: v_fcmp_f32_one: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_neq_f32_e64 s[2:3], 0x42c80000, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_one: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_neq_f32_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_one: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_one: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 6) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_ogt(i64 addrspace(1)* %out, float %src) { +; GFX11-LABEL: v_fcmp_f32_ogt: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_lt_f32_e64 s[2:3], 0x42c80000, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_ogt: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_gt_f32_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_ogt: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_gt_f32_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_ogt: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_gt_f32_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 2) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_oge(i64 addrspace(1)* %out, float %src) { +; GFX11-LABEL: v_fcmp_f32_oge: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_le_f32_e64 s[2:3], 0x42c80000, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_oge: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_oge: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_ge_f32_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_oge: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_ge_f32_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 3) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_olt(i64 addrspace(1)* %out, float %src) { +; GFX11-LABEL: v_fcmp_f32_olt: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_gt_f32_e64 s[2:3], 0x42c80000, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_olt: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_lt_f32_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_olt: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_lt_f32_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_olt: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_lt_f32_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 4) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_ole(i64 addrspace(1)* %out, float %src) { +; GFX11-LABEL: v_fcmp_f32_ole: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_ge_f32_e64 s[2:3], 0x42c80000, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_ole: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_le_f32_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_ole: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_le_f32_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_ole: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_le_f32_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 5) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f32_ueq(i64 addrspace(1)* %out, float %src) { +; GFX11-LABEL: v_fcmp_f32_ueq: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_nlg_f32_e64 s[2:3], 0x42c80000, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_ueq: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_nlg_f32_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_ueq: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_nlg_f32_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_ueq: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_nlg_f32_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 9) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_une(i64 addrspace(1)* %out, float %src) { +; GFX11-LABEL: v_fcmp_f32_une: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_neq_f32_e64 s[2:3], 0x42c80000, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_une: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_neq_f32_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_une: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_une: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_neq_f32_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 14) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_ugt(i64 addrspace(1)* %out, float %src) { +; GFX11-LABEL: v_fcmp_f32_ugt: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_nge_f32_e64 s[2:3], 0x42c80000, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_ugt: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_nle_f32_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_ugt: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_nle_f32_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_ugt: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_nle_f32_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 10) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_uge(i64 addrspace(1)* %out, float %src) { +; GFX11-LABEL: v_fcmp_f32_uge: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_ngt_f32_e64 s[2:3], 0x42c80000, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_uge: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_nlt_f32_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_uge: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_nlt_f32_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_uge: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_nlt_f32_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 11) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_ult(i64 addrspace(1)* %out, float %src) { +; GFX11-LABEL: v_fcmp_f32_ult: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_nle_f32_e64 s[2:3], 0x42c80000, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_ult: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_nge_f32_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_ult: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_nge_f32_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_ult: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_nge_f32_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 12) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f32_ule(i64 addrspace(1)* %out, float %src) { +; GFX11-LABEL: v_fcmp_f32_ule: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_nlt_f32_e64 s[2:3], 0x42c80000, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f32_ule: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_ngt_f32_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f32_ule: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f32_ule: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x42c80000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_ngt_f32_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 13) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_oeq(i64 addrspace(1)* %out, double %src) { +; GFX11-LABEL: v_fcmp_f64_oeq: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_f64_e64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f64_oeq: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_mov_b32 s4, 0 +; GISEL-VI-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f64_oeq: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX9-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX9-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f64_oeq: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm +; SDAG-GFX9-LABEL: v_fcmp_f64_oeq: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX9-NEXT: v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s3 +; SDAG-GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] +; SDAG-GFX9-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 1) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_one(i64 addrspace(1)* %out, double %src) { +; GFX11-LABEL: v_fcmp_f64_one: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f64_one: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_mov_b32 s4, 0 +; GISEL-VI-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f64_one: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX9-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX9-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f64_one: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm +; SDAG-GFX9-LABEL: v_fcmp_f64_one: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX9-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s3 +; SDAG-GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] +; SDAG-GFX9-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 6) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_ogt(i64 addrspace(1)* %out, double %src) { +; GFX11-LABEL: v_fcmp_f64_ogt: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_gt_f64_e64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f64_ogt: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_mov_b32 s4, 0 +; GISEL-VI-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f64_ogt: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX9-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX9-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f64_ogt: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm +; SDAG-GFX9-LABEL: v_fcmp_f64_ogt: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX9-NEXT: v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s3 +; SDAG-GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] +; SDAG-GFX9-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 2) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_oge(i64 addrspace(1)* %out, double %src) { +; GFX11-LABEL: v_fcmp_f64_oge: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_ge_f64_e64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f64_oge: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_mov_b32 s4, 0 +; GISEL-VI-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f64_oge: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX9-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX9-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f64_oge: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm +; SDAG-GFX9-LABEL: v_fcmp_f64_oge: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX9-NEXT: v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s3 +; SDAG-GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] +; SDAG-GFX9-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 3) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_olt(i64 addrspace(1)* %out, double %src) { +; GFX11-LABEL: v_fcmp_f64_olt: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_lt_f64_e64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f64_olt: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_mov_b32 s4, 0 +; GISEL-VI-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f64_olt: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX9-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX9-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f64_olt: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm +; SDAG-GFX9-LABEL: v_fcmp_f64_olt: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX9-NEXT: v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s3 +; SDAG-GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] +; SDAG-GFX9-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 4) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_ole(i64 addrspace(1)* %out, double %src) { +; GFX11-LABEL: v_fcmp_f64_ole: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_le_f64_e64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f64_ole: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_mov_b32 s4, 0 +; GISEL-VI-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f64_ole: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX9-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX9-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f64_ole: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm +; SDAG-GFX9-LABEL: v_fcmp_f64_ole: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX9-NEXT: v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s3 +; SDAG-GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] +; SDAG-GFX9-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 5) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_ueq(i64 addrspace(1)* %out, double %src) { +; GFX11-LABEL: v_fcmp_f64_ueq: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f64_ueq: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_mov_b32 s4, 0 +; GISEL-VI-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f64_ueq: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX9-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX9-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f64_ueq: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm +; SDAG-GFX9-LABEL: v_fcmp_f64_ueq: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX9-NEXT: v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s3 +; SDAG-GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] +; SDAG-GFX9-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 9) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_une(i64 addrspace(1)* %out, double %src) { +; GFX11-LABEL: v_fcmp_f64_une: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f64_une: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_mov_b32 s4, 0 +; GISEL-VI-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f64_une: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX9-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX9-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f64_une: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm +; SDAG-GFX9-LABEL: v_fcmp_f64_une: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX9-NEXT: v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s3 +; SDAG-GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] +; SDAG-GFX9-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 14) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_ugt(i64 addrspace(1)* %out, double %src) { +; GFX11-LABEL: v_fcmp_f64_ugt: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_nle_f64_e64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f64_ugt: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_mov_b32 s4, 0 +; GISEL-VI-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f64_ugt: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX9-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX9-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f64_ugt: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm +; SDAG-GFX9-LABEL: v_fcmp_f64_ugt: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX9-NEXT: v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s3 +; SDAG-GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] +; SDAG-GFX9-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 10) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_uge(i64 addrspace(1)* %out, double %src) { +; GFX11-LABEL: v_fcmp_f64_uge: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f64_uge: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_mov_b32 s4, 0 +; GISEL-VI-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f64_uge: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX9-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX9-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f64_uge: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm +; SDAG-GFX9-LABEL: v_fcmp_f64_uge: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX9-NEXT: v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s3 +; SDAG-GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] +; SDAG-GFX9-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 11) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_ult(i64 addrspace(1)* %out, double %src) { +; GFX11-LABEL: v_fcmp_f64_ult: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_nge_f64_e64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f64_ult: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_mov_b32 s4, 0 +; GISEL-VI-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f64_ult: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX9-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX9-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f64_ult: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm +; SDAG-GFX9-LABEL: v_fcmp_f64_ult: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX9-NEXT: v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s3 +; SDAG-GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] +; SDAG-GFX9-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 12) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f64_ule(i64 addrspace(1)* %out, double %src) { +; GFX11-LABEL: v_fcmp_f64_ule: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 +; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_mov_b32 s5, 0x40590000 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_ngt_f64_e64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f64_ule: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-VI-NEXT: s_mov_b32 s4, 0 +; GISEL-VI-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f64_ule: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GISEL-GFX9-NEXT: s_mov_b32 s4, 0 +; GISEL-GFX9-NEXT: s_mov_b32 s5, 0x40590000 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s4 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s5 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1] +; GISEL-GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f64_ule: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm +; SDAG-GFX9-LABEL: v_fcmp_f64_ule: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, 0x40590000 +; SDAG-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-GFX9-NEXT: v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1] +; SDAG-GFX9-NEXT: v_mov_b32_e32 v1, s2 +; SDAG-GFX9-NEXT: v_mov_b32_e32 v2, s3 +; SDAG-GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] +; SDAG-GFX9-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 13) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_oeq_with_fabs(i64 addrspace(1)* %out, half %src, half %a) { +; GFX11-LABEL: v_fcmp_f16_oeq_with_fabs: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_lshr_b32 s3, s2, 16 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, |s3| +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_oeq_with_fabs: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_lshr_b32 s0, s4, 16 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_cmp_eq_f16_e64 s[0:1], s4, |v0| +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_oeq_with_fabs: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: s_lshr_b32 s3, s2, 16 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s3 +; GISEL-VI-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, |v0| +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_oeq_with_fabs: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: s_lshr_b32 s3, s2, 16 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s3 +; SDAG-VI-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, |v0| +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %temp = call half @llvm.fabs.f16(half %a) + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half %temp, i32 1) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_oeq_both_operands_with_fabs(i64 addrspace(1)* %out, half %src, half %a) { +; GFX11-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: s_lshr_b32 s3, s2, 16 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cmp_eq_f16_e64 s[2:3], |s2|, |s3| +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_lshr_b32 s0, s4, 16 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_cmp_eq_f16_e64 s[0:1], |s4|, |v0| +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: s_lshr_b32 s3, s2, 16 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s3 +; GISEL-VI-NEXT: v_cmp_eq_f16_e64 s[2:3], |s2|, |v0| +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: s_lshr_b32 s3, s2, 16 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s3 +; SDAG-VI-NEXT: v_cmp_eq_f16_e64 s[2:3], |s2|, |v0| +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %temp = call half @llvm.fabs.f16(half %a) + %src_input = call half @llvm.fabs.f16(half %src) + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src_input, half %temp, i32 1) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +define amdgpu_kernel void @v_fcmp_f16(i64 addrspace(1)* %out, half %src) { +; SDAG-GFX-LABEL: v_fcmp_f16: +; SDAG-GFX: ; %bb.0: +; SDAG-GFX-NEXT: s_endpgm +; +; SDAG-GFX11-LABEL: v_fcmp_f16: +; SDAG-GFX11: ; %bb.0: +; SDAG-GFX11-NEXT: s_endpgm +; +; SDAG-VI-LABEL: v_fcmp_f16: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_endpgm +; +; SDAG-GFX9-LABEL: v_fcmp_f16: +; SDAG-GFX9: ; %bb.0: +; SDAG-GFX9-NEXT: s_endpgm +; +; GISEL-GFX11-LABEL: v_fcmp_f16: +; GISEL-GFX11: ; %bb.0: +; GISEL-GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GISEL-GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GISEL-GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX11-NEXT: global_store_b64 v0, v[0:1], s[0:1] +; GISEL-GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GISEL-GFX11-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s0 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s1 +; GISEL-VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; +; GISEL-GFX9-LABEL: v_fcmp_f16: +; GISEL-GFX9: ; %bb.0: +; GISEL-GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GISEL-GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX9-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1] +; GISEL-GFX9-NEXT: s_endpgm +; GISEL-GFX-LABEL: v_fcmp_f16: +; GISEL-GFX: ; %bb.0: +; GISEL-GFX-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-GFX-NEXT: v_mov_b32_e32 v0, 0 +; GISEL-GFX-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-GFX-NEXT: global_store_dwordx2 v0, v[0:1], s[0:1] +; GISEL-GFX-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 -1) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_oeq(i64 addrspace(1)* %out, half %src) { +; GFX11-LABEL: v_fcmp_f16_oeq: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_eq_f16_e64 s[2:3], 0x5640, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_oeq: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_eq_f16_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_oeq: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_oeq: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_eq_f16_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 1) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_one(i64 addrspace(1)* %out, half %src) { +; GFX11-LABEL: v_fcmp_f16_one: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_neq_f16_e64 s[2:3], 0x5640, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_one: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_neq_f16_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_one: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_one: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 6) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_ogt(i64 addrspace(1)* %out, half %src) { +; GFX11-LABEL: v_fcmp_f16_ogt: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_lt_f16_e64 s[2:3], 0x5640, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_ogt: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_gt_f16_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_ogt: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_gt_f16_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_ogt: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_gt_f16_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 2) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_oge(i64 addrspace(1)* %out, half %src) { +; GFX11-LABEL: v_fcmp_f16_oge: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_le_f16_e64 s[2:3], 0x5640, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_oge: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_ge_f16_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_oge: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_ge_f16_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_oge: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_ge_f16_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 3) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_olt(i64 addrspace(1)* %out, half %src) { +; GFX11-LABEL: v_fcmp_f16_olt: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_gt_f16_e64 s[2:3], 0x5640, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_olt: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_lt_f16_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_olt: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_lt_f16_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_olt: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_lt_f16_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 4) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_ole(i64 addrspace(1)* %out, half %src) { +; GFX11-LABEL: v_fcmp_f16_ole: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_ge_f16_e64 s[2:3], 0x5640, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_ole: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_le_f16_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_ole: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_le_f16_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_ole: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_le_f16_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 5) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_ueq(i64 addrspace(1)* %out, half %src) { +; GFX11-LABEL: v_fcmp_f16_ueq: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_nlg_f16_e64 s[2:3], 0x5640, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_ueq: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_nlg_f16_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_ueq: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_nlg_f16_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_ueq: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_nlg_f16_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 9) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_une(i64 addrspace(1)* %out, half %src) { +; GFX11-LABEL: v_fcmp_f16_une: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_neq_f16_e64 s[2:3], 0x5640, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_une: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_neq_f16_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_une: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_une: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_neq_f16_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 14) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_ugt(i64 addrspace(1)* %out, half %src) { +; GFX11-LABEL: v_fcmp_f16_ugt: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_nge_f16_e64 s[2:3], 0x5640, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_ugt: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_nle_f16_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_ugt: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_nle_f16_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_ugt: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_nle_f16_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 10) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_uge(i64 addrspace(1)* %out, half %src) { +; GFX11-LABEL: v_fcmp_f16_uge: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_ngt_f16_e64 s[2:3], 0x5640, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_uge: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_nlt_f16_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_uge: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_nlt_f16_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_uge: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_nlt_f16_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 11) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_ult(i64 addrspace(1)* %out, half %src) { +; GFX11-LABEL: v_fcmp_f16_ult: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_nle_f16_e64 s[2:3], 0x5640, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_ult: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_nge_f16_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_ult: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_nge_f16_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_ult: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_nge_f16_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 12) + store i64 %result, i64 addrspace(1)* %out + ret void +} + + +define amdgpu_kernel void @v_fcmp_f16_ule(i64 addrspace(1)* %out, half %src) { +; GFX11-LABEL: v_fcmp_f16_ule: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_clause 0x1 +; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_cmp_nlt_f16_e64 s[2:3], 0x5640, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_mov_b32_e32 v1, s3 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] +; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-NEXT: s_endpgm +; +; GFX9-LABEL: v_fcmp_f16_ule: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dword s4, s[0:1], 0x2c +; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v0, 0x5640 +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_cmp_ngt_f16_e64 s[0:1], s4, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] +; GFX9-NEXT: s_endpgm +; +; GISEL-VI-LABEL: v_fcmp_f16_ule: +; GISEL-VI: ; %bb.0: +; GISEL-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; GISEL-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; GISEL-VI-NEXT: s_waitcnt lgkmcnt(0) +; GISEL-VI-NEXT: v_cmp_ngt_f16_e64 s[2:3], s2, v0 +; GISEL-VI-NEXT: v_mov_b32_e32 v0, s2 +; GISEL-VI-NEXT: v_mov_b32_e32 v3, s1 +; GISEL-VI-NEXT: v_mov_b32_e32 v1, s3 +; GISEL-VI-NEXT: v_mov_b32_e32 v2, s0 +; GISEL-VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; GISEL-VI-NEXT: s_endpgm +; SDAG-VI-LABEL: v_fcmp_f16_ule: +; SDAG-VI: ; %bb.0: +; SDAG-VI-NEXT: s_load_dword s2, s[0:1], 0x2c +; SDAG-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, 0x5640 +; SDAG-VI-NEXT: s_waitcnt lgkmcnt(0) +; SDAG-VI-NEXT: v_cmp_ngt_f16_e64 s[2:3], s2, v0 +; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0 +; SDAG-VI-NEXT: v_mov_b32_e32 v2, s2 +; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1 +; SDAG-VI-NEXT: v_mov_b32_e32 v3, s3 +; SDAG-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3] +; SDAG-VI-NEXT: s_endpgm + %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 13) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone convergent } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GCN: {{.*}} +; VI: {{.*}}