diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
@@ -108,7 +108,7 @@
   bool selectInterpP1F16(MachineInstr &MI) const;
   bool selectWritelane(MachineInstr &MI) const;
   bool selectDivScale(MachineInstr &MI) const;
-  bool selectIntrinsicIcmp(MachineInstr &MI) const;
+  bool selectIntrinsicCmp(MachineInstr &MI) const;
   bool selectBallot(MachineInstr &I) const;
   bool selectRelocConstant(MachineInstr &I) const;
   bool selectGroupStaticSize(MachineInstr &I) const;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1039,9 +1039,10 @@
   case Intrinsic::amdgcn_div_scale:
     return selectDivScale(I);
   case Intrinsic::amdgcn_icmp:
+  case Intrinsic::amdgcn_fcmp:
     if (selectImpl(I, *CoverageInfo))
       return true;
-    return selectIntrinsicIcmp(I);
+    return selectIntrinsicCmp(I);
   case Intrinsic::amdgcn_ballot:
     return selectBallot(I);
   case Intrinsic::amdgcn_reloc_constant:
@@ -1120,6 +1121,50 @@
   case CmpInst::ICMP_ULE:
     return Select(AMDGPU::V_CMP_LE_U16_e64, AMDGPU::V_CMP_LE_U16_t16_e64,
                   AMDGPU::V_CMP_LE_U32_e64, AMDGPU::V_CMP_LE_U64_e64);
+
+  case CmpInst::FCMP_OEQ:
+    return Select(AMDGPU::V_CMP_EQ_F16_e64, AMDGPU::V_CMP_EQ_F16_t16_e64,
+                  AMDGPU::V_CMP_EQ_F32_e64, AMDGPU::V_CMP_EQ_F64_e64);
+  case CmpInst::FCMP_OGT:
+    return Select(AMDGPU::V_CMP_GT_F16_e64, AMDGPU::V_CMP_GT_F16_t16_e64,
+                  AMDGPU::V_CMP_GT_F32_e64, AMDGPU::V_CMP_GT_F64_e64);
+  case CmpInst::FCMP_OGE:
+    return Select(AMDGPU::V_CMP_GE_F16_e64, AMDGPU::V_CMP_GE_F16_t16_e64,
+                  AMDGPU::V_CMP_GE_F32_e64, AMDGPU::V_CMP_GE_F64_e64);
+  case CmpInst::FCMP_OLT:
+    return Select(AMDGPU::V_CMP_LT_F16_e64, AMDGPU::V_CMP_LT_F16_t16_e64,
+                  AMDGPU::V_CMP_LT_F32_e64, AMDGPU::V_CMP_LT_F64_e64);
+  case CmpInst::FCMP_OLE:
+    return Select(AMDGPU::V_CMP_LE_F16_e64, AMDGPU::V_CMP_LE_F16_t16_e64,
+                  AMDGPU::V_CMP_LE_F32_e64, AMDGPU::V_CMP_LE_F64_e64);
+  case CmpInst::FCMP_ONE:
+    return Select(AMDGPU::V_CMP_NEQ_F16_e64, AMDGPU::V_CMP_NEQ_F16_t16_e64,
+                  AMDGPU::V_CMP_NEQ_F32_e64, AMDGPU::V_CMP_NEQ_F64_e64);
+  case CmpInst::FCMP_ORD:
+    return Select(AMDGPU::V_CMP_O_F16_e64, AMDGPU::V_CMP_O_F16_t16_e64,
+                  AMDGPU::V_CMP_O_F32_e64, AMDGPU::V_CMP_O_F64_e64);
+  case CmpInst::FCMP_UNO:
+    return Select(AMDGPU::V_CMP_U_F16_e64, AMDGPU::V_CMP_U_F16_t16_e64,
+                  AMDGPU::V_CMP_U_F32_e64, AMDGPU::V_CMP_U_F64_e64);
+  case CmpInst::FCMP_UEQ:
+    return Select(AMDGPU::V_CMP_NLG_F16_e64, AMDGPU::V_CMP_NLG_F16_t16_e64,
+                  AMDGPU::V_CMP_NLG_F32_e64, AMDGPU::V_CMP_NLG_F64_e64);
+  case CmpInst::FCMP_UGT:
+    return Select(AMDGPU::V_CMP_NLE_F16_e64, AMDGPU::V_CMP_NLE_F16_t16_e64,
+                  AMDGPU::V_CMP_NLE_F32_e64, AMDGPU::V_CMP_NLE_F64_e64);
+  case CmpInst::FCMP_UGE:
+    return Select(AMDGPU::V_CMP_NLT_F16_e64, AMDGPU::V_CMP_NLT_F16_t16_e64,
+                  AMDGPU::V_CMP_NLT_F32_e64, AMDGPU::V_CMP_NLT_F64_e64);
+  case CmpInst::FCMP_ULT:
+    return Select(AMDGPU::V_CMP_NGE_F16_e64, AMDGPU::V_CMP_NGE_F16_t16_e64,
+                  AMDGPU::V_CMP_NGE_F32_e64, AMDGPU::V_CMP_NGE_F64_e64);
+  case CmpInst::FCMP_ULE:
+    return Select(AMDGPU::V_CMP_NGT_F16_e64, AMDGPU::V_CMP_NGT_F16_t16_e64,
+                  AMDGPU::V_CMP_NGT_F32_e64, AMDGPU::V_CMP_NGT_F64_e64);
+  case CmpInst::FCMP_UNE:
+    return Select(AMDGPU::V_CMP_NEQ_F16_e64, AMDGPU::V_CMP_NEQ_F16_t16_e64,
+                  AMDGPU::V_CMP_NEQ_F32_e64, AMDGPU::V_CMP_NEQ_F64_e64);
+    return -1;
   }
 }
 
@@ -1209,7 +1254,7 @@
   return Ret;
 }
 
-bool AMDGPUInstructionSelector::selectIntrinsicIcmp(MachineInstr &I) const {
+bool AMDGPUInstructionSelector::selectIntrinsicCmp(MachineInstr &I) const {
   Register Dst = I.getOperand(0).getReg();
   if (isVCC(Dst, *MRI))
     return false;
@@ -1223,7 +1268,9 @@
   unsigned Size = RBI.getSizeInBits(SrcReg, *MRI, TRI);
 
   auto Pred = static_cast<CmpInst::Predicate>(I.getOperand(4).getImm());
-  if (!ICmpInst::isIntPredicate(static_cast<ICmpInst::Predicate>(Pred))) {
+
+  // Invalid predicates -> undef
+  if (!CmpInst::isFPPredicate(Pred) && !CmpInst::isIntPredicate(Pred)) {
     MachineInstr *ICmp =
         BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Dst);
 
@@ -1238,12 +1285,25 @@
   if (Opcode == -1)
     return false;
 
-  MachineInstr *ICmp = BuildMI(*BB, &I, DL, TII.get(Opcode), Dst)
-                           .add(I.getOperand(2))
-                           .add(I.getOperand(3));
-  RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(), *TRI.getBoolRC(),
-                               *MRI);
-  bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI);
+  MachineInstr *SelectedMI;
+  if (CmpInst::isFPPredicate(Pred)) {
+    auto [Src0, Src0Mods] = selectVOP3ModsImpl(I.getOperand(2));
+    auto [Src1, Src1Mods] = selectVOP3ModsImpl(I.getOperand(3));
+    SelectedMI = BuildMI(*BB, &I, DL, TII.get(Opcode), Dst)
+                     .addImm(Src0Mods)
+                     .addReg(Src0)
+                     .addImm(Src1Mods)
+                     .addReg(Src1)
+                     .addImm(0); // omod
+  } else
+    SelectedMI = BuildMI(*BB, &I, DL, TII.get(Opcode), Dst)
+                     .add(I.getOperand(2))
+                     .add(I.getOperand(3));
+
+  RBI.constrainGenericRegister(SelectedMI->getOperand(0).getReg(),
+                               *TRI.getBoolRC(), *MRI);
+
+  bool Ret = constrainSelectedInstRegOperands(*SelectedMI, TII, TRI, RBI);
   I.eraseFromParent();
   return Ret;
 }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll
@@ -1,6 +1,9 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX %s
-; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX,SDAG-GFX %s
+; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,SDAG-VI %s
+
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX,GISEL-GFX %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,GISEL-VI %s
 
 declare i64 @llvm.amdgcn.fcmp.f32(float, float, i32) #0
 declare i64 @llvm.amdgcn.fcmp.f64(double, double, i32) #0
@@ -10,33 +13,58 @@
 declare half @llvm.fabs.f16(half) #0
 
 define amdgpu_kernel void @v_fcmp_f32_oeq_with_fabs(i64 addrspace(1)* %out, float %src, float %a) {
-; GFX-LABEL: v_fcmp_f32_oeq_with_fabs:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_mov_b32_e32 v0, s3
-; GFX-NEXT:    v_cmp_eq_f32_e64 s[2:3], s2, |v0|
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_oeq_with_fabs:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s3
-; VI-NEXT:    v_cmp_eq_f32_e64 s[2:3], s2, |v0|
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_oeq_with_fabs:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s3
+; SDAG-GFX-NEXT:    v_cmp_eq_f32_e64 s[2:3], s2, |v0|
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_oeq_with_fabs:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s3
+; SDAG-VI-NEXT:    v_cmp_eq_f32_e64 s[2:3], s2, |v0|
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_oeq_with_fabs:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s3
+; GISEL-GFX-NEXT:    v_cmp_eq_f32_e64 s[2:3], s2, |v0|
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_oeq_with_fabs:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s3
+; GISEL-VI-NEXT:    v_cmp_eq_f32_e64 s[2:3], s2, |v0|
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %temp = call float @llvm.fabs.f32(float %a)
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float %temp, i32 1)
   store i64 %result, i64 addrspace(1)* %out
@@ -44,33 +72,58 @@
 }
 
 define amdgpu_kernel void @v_fcmp_f32_oeq_both_operands_with_fabs(i64 addrspace(1)* %out, float %src, float %a) {
-; GFX-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_mov_b32_e32 v0, s3
-; GFX-NEXT:    v_cmp_eq_f32_e64 s[2:3], |s2|, |v0|
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v0, s3
-; VI-NEXT:    v_cmp_eq_f32_e64 s[2:3], |s2|, |v0|
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s3
+; SDAG-GFX-NEXT:    v_cmp_eq_f32_e64 s[2:3], |s2|, |v0|
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s3
+; SDAG-VI-NEXT:    v_cmp_eq_f32_e64 s[2:3], |s2|, |v0|
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s3
+; GISEL-GFX-NEXT:    v_cmp_eq_f32_e64 s[2:3], |s2|, |v0|
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_oeq_both_operands_with_fabs:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s3
+; GISEL-VI-NEXT:    v_cmp_eq_f32_e64 s[2:3], |s2|, |v0|
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %temp = call float @llvm.fabs.f32(float %a)
   %src_input = call float @llvm.fabs.f32(float %src)
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src_input, float %temp, i32 1)
@@ -79,207 +132,390 @@
 }
 
 define amdgpu_kernel void @v_fcmp_f32(i64 addrspace(1)* %out, float %src) {
-; GCN-LABEL: v_fcmp_f32:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    global_store_dwordx2 v0, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[0:1], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 -1)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f32_oeq(i64 addrspace(1)* %out, float %src) {
-; GFX-LABEL: v_fcmp_f32_oeq:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_eq_f32_e64 s[4:5], s2, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_oeq:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_eq_f32_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_oeq:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_eq_f32_e64 s[4:5], s2, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_oeq:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_eq_f32_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_oeq:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_eq_f32_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_oeq:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_eq_f32_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 1)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f32_one(i64 addrspace(1)* %out, float %src) {
-; GFX-LABEL: v_fcmp_f32_one:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_neq_f32_e64 s[4:5], s2, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_one:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_neq_f32_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_one:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_neq_f32_e64 s[4:5], s2, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_one:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_neq_f32_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_one:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_neq_f32_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_one:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_neq_f32_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 6)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f32_ogt(i64 addrspace(1)* %out, float %src) {
-; GFX-LABEL: v_fcmp_f32_ogt:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_gt_f32_e64 s[4:5], s2, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_ogt:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_gt_f32_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_ogt:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_gt_f32_e64 s[4:5], s2, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_ogt:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_gt_f32_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_ogt:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_gt_f32_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_ogt:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_gt_f32_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 2)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f32_oge(i64 addrspace(1)* %out, float %src) {
-; GFX-LABEL: v_fcmp_f32_oge:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_ge_f32_e64 s[4:5], s2, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_oge:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_ge_f32_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_oge:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_ge_f32_e64 s[4:5], s2, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_oge:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_ge_f32_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_oge:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_ge_f32_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_oge:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_ge_f32_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 3)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f32_olt(i64 addrspace(1)* %out, float %src) {
-; GFX-LABEL: v_fcmp_f32_olt:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_lt_f32_e64 s[4:5], s2, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_olt:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_lt_f32_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_olt:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_lt_f32_e64 s[4:5], s2, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_olt:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_lt_f32_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_olt:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_lt_f32_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_olt:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_lt_f32_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 4)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f32_ole(i64 addrspace(1)* %out, float %src) {
-; GFX-LABEL: v_fcmp_f32_ole:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_le_f32_e64 s[4:5], s2, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_ole:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_le_f32_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_ole:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_le_f32_e64 s[4:5], s2, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_ole:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_le_f32_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_ole:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_le_f32_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_ole:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_le_f32_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 5)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -287,618 +523,1152 @@
 
 
 define amdgpu_kernel void @v_fcmp_f32_ueq(i64 addrspace(1)* %out, float %src) {
-; GFX-LABEL: v_fcmp_f32_ueq:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_nlg_f32_e64 s[4:5], s2, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_ueq:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_nlg_f32_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_ueq:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_nlg_f32_e64 s[4:5], s2, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_ueq:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_nlg_f32_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_ueq:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_nlg_f32_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_ueq:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_nlg_f32_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 9)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f32_une(i64 addrspace(1)* %out, float %src) {
-; GFX-LABEL: v_fcmp_f32_une:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_neq_f32_e64 s[4:5], s2, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_une:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_neq_f32_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_une:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_neq_f32_e64 s[4:5], s2, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_une:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_neq_f32_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_une:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_neq_f32_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_une:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_neq_f32_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 14)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f32_ugt(i64 addrspace(1)* %out, float %src) {
-; GFX-LABEL: v_fcmp_f32_ugt:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_nle_f32_e64 s[4:5], s2, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_ugt:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_nle_f32_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_ugt:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_nle_f32_e64 s[4:5], s2, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_ugt:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_nle_f32_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_ugt:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_nle_f32_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_ugt:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_nle_f32_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 10)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f32_uge(i64 addrspace(1)* %out, float %src) {
-; GFX-LABEL: v_fcmp_f32_uge:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_nlt_f32_e64 s[4:5], s2, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_uge:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_nlt_f32_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_uge:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_nlt_f32_e64 s[4:5], s2, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_uge:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_nlt_f32_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_uge:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_nlt_f32_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_uge:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_nlt_f32_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 11)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f32_ult(i64 addrspace(1)* %out, float %src) {
-; GFX-LABEL: v_fcmp_f32_ult:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_nge_f32_e64 s[4:5], s2, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_ult:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_nge_f32_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_ult:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_nge_f32_e64 s[4:5], s2, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_ult:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_nge_f32_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_ult:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_nge_f32_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_ult:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_nge_f32_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 12)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f32_ule(i64 addrspace(1)* %out, float %src) {
-; GFX-LABEL: v_fcmp_f32_ule:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_ngt_f32_e64 s[4:5], s2, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f32_ule:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f32_ule:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_ngt_f32_e64 s[4:5], s2, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f32_ule:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f32_ule:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_ngt_f32_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f32_ule:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x42c80000
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_ngt_f32_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f32(float %src, float 100.00, i32 13)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f64_oeq(i64 addrspace(1)* %out, double %src) {
-; GFX-LABEL: v_fcmp_f64_oeq:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0
-; GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f64_oeq:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0
-; VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f64_oeq:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f64_oeq:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f64_oeq:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    s_mov_b32 s4, 0
+; GISEL-GFX-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f64_oeq:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_mov_b32 s4, 0
+; GISEL-VI-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_eq_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 1)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f64_one(i64 addrspace(1)* %out, double %src) {
-; GFX-LABEL: v_fcmp_f64_one:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0
-; GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f64_one:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0
-; VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f64_one:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f64_one:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f64_one:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    s_mov_b32 s4, 0
+; GISEL-GFX-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f64_one:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_mov_b32 s4, 0
+; GISEL-VI-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 6)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f64_ogt(i64 addrspace(1)* %out, double %src) {
-; GFX-LABEL: v_fcmp_f64_ogt:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0
-; GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f64_ogt:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0
-; VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f64_ogt:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f64_ogt:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f64_ogt:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    s_mov_b32 s4, 0
+; GISEL-GFX-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f64_ogt:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_mov_b32 s4, 0
+; GISEL-VI-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_gt_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 2)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f64_oge(i64 addrspace(1)* %out, double %src) {
-; GFX-LABEL: v_fcmp_f64_oge:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0
-; GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f64_oge:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0
-; VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f64_oge:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f64_oge:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f64_oge:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    s_mov_b32 s4, 0
+; GISEL-GFX-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f64_oge:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_mov_b32 s4, 0
+; GISEL-VI-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_ge_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 3)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f64_olt(i64 addrspace(1)* %out, double %src) {
-; GFX-LABEL: v_fcmp_f64_olt:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0
-; GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f64_olt:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0
-; VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f64_olt:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f64_olt:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f64_olt:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    s_mov_b32 s4, 0
+; GISEL-GFX-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f64_olt:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_mov_b32 s4, 0
+; GISEL-VI-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_lt_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 4)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f64_ole(i64 addrspace(1)* %out, double %src) {
-; GFX-LABEL: v_fcmp_f64_ole:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0
-; GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f64_ole:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0
-; VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f64_ole:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f64_ole:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f64_ole:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    s_mov_b32 s4, 0
+; GISEL-GFX-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f64_ole:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_mov_b32 s4, 0
+; GISEL-VI-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_le_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 5)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f64_ueq(i64 addrspace(1)* %out, double %src) {
-; GFX-LABEL: v_fcmp_f64_ueq:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0
-; GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f64_ueq:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0
-; VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f64_ueq:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f64_ueq:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f64_ueq:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    s_mov_b32 s4, 0
+; GISEL-GFX-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f64_ueq:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_mov_b32 s4, 0
+; GISEL-VI-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_nlg_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 9)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f64_une(i64 addrspace(1)* %out, double %src) {
-; GFX-LABEL: v_fcmp_f64_une:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0
-; GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f64_une:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0
-; VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f64_une:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f64_une:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f64_une:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    s_mov_b32 s4, 0
+; GISEL-GFX-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f64_une:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_mov_b32 s4, 0
+; GISEL-VI-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_neq_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 14)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f64_ugt(i64 addrspace(1)* %out, double %src) {
-; GFX-LABEL: v_fcmp_f64_ugt:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0
-; GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f64_ugt:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0
-; VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f64_ugt:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f64_ugt:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f64_ugt:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    s_mov_b32 s4, 0
+; GISEL-GFX-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f64_ugt:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_mov_b32 s4, 0
+; GISEL-VI-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_nle_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 10)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f64_uge(i64 addrspace(1)* %out, double %src) {
-; GFX-LABEL: v_fcmp_f64_uge:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0
-; GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f64_uge:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0
-; VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f64_uge:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f64_uge:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f64_uge:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    s_mov_b32 s4, 0
+; GISEL-GFX-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f64_uge:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_mov_b32 s4, 0
+; GISEL-VI-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_nlt_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 11)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f64_ult(i64 addrspace(1)* %out, double %src) {
-; GFX-LABEL: v_fcmp_f64_ult:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0
-; GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f64_ult:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0
-; VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f64_ult:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f64_ult:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f64_ult:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    s_mov_b32 s4, 0
+; GISEL-GFX-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f64_ult:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_mov_b32 s4, 0
+; GISEL-VI-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_nge_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 12)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @v_fcmp_f64_ule(i64 addrspace(1)* %out, double %src) {
-; GFX-LABEL: v_fcmp_f64_ule:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s7, 0xf000
-; GFX-NEXT:    v_mov_b32_e32 v0, 0
-; GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1]
-; GFX-NEXT:    s_mov_b32 s6, -1
-; GFX-NEXT:    s_mov_b32 s4, s0
-; GFX-NEXT:    s_mov_b32 s5, s1
-; GFX-NEXT:    v_mov_b32_e32 v0, s2
-; GFX-NEXT:    v_mov_b32_e32 v1, s3
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f64_ule:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0
-; VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1]
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f64_ule:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s7, 0xf000
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-GFX-NEXT:    s_mov_b32 s6, -1
+; SDAG-GFX-NEXT:    s_mov_b32 s4, s0
+; SDAG-GFX-NEXT:    s_mov_b32 s5, s1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f64_ule:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, 0x40590000
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1]
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f64_ule:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    s_mov_b32 s4, 0
+; GISEL-GFX-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f64_ule:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_mov_b32 s4, 0
+; GISEL-VI-NEXT:    s_mov_b32 s5, 0x40590000
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s4
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s5
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_ngt_f64_e64 s[2:3], s[2:3], v[0:1]
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f64(double %src, double 100.00, i32 13)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -906,36 +1676,65 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_oeq_with_fabs(i64 addrspace(1)* %out, half %src, half %a) {
-; GFX-LABEL: v_fcmp_f16_oeq_with_fabs:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
-; GFX-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX-NEXT:    v_cvt_f32_f16_e64 v1, |s2|
-; GFX-NEXT:    v_cmp_eq_f32_e64 s[4:5], v0, v1
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_oeq_with_fabs:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    s_lshr_b32 s3, s2, 16
-; VI-NEXT:    v_mov_b32_e32 v0, s3
-; VI-NEXT:    v_cmp_eq_f16_e64 s[2:3], s2, |v0|
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_oeq_with_fabs:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; SDAG-GFX-NEXT:    s_lshr_b32 s2, s2, 16
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e64 v1, |s2|
+; SDAG-GFX-NEXT:    v_cmp_eq_f32_e64 s[4:5], v0, v1
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_oeq_with_fabs:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    s_lshr_b32 s3, s2, 16
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s3
+; SDAG-VI-NEXT:    v_cmp_eq_f16_e64 s[2:3], s2, |v0|
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_oeq_with_fabs:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    s_lshr_b32 s0, s4, 16
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_cmp_eq_f16_e64 s[0:1], s4, |v0|
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_oeq_with_fabs:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    s_lshr_b32 s3, s2, 16
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s3
+; GISEL-VI-NEXT:    v_cmp_eq_f16_e64 s[2:3], s2, |v0|
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %temp = call half @llvm.fabs.f16(half %a)
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half %temp, i32 1)
   store i64 %result, i64 addrspace(1)* %out
@@ -944,36 +1743,65 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_oeq_both_operands_with_fabs(i64 addrspace(1)* %out, half %src, half %a) {
-; GFX-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e64 v0, |s2|
-; GFX-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX-NEXT:    v_cvt_f32_f16_e64 v1, |s2|
-; GFX-NEXT:    v_cmp_eq_f32_e64 s[4:5], v0, v1
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    s_lshr_b32 s3, s2, 16
-; VI-NEXT:    v_mov_b32_e32 v0, s3
-; VI-NEXT:    v_cmp_eq_f16_e64 s[2:3], |s2|, |v0|
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e64 v0, |s2|
+; SDAG-GFX-NEXT:    s_lshr_b32 s2, s2, 16
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e64 v1, |s2|
+; SDAG-GFX-NEXT:    v_cmp_eq_f32_e64 s[4:5], v0, v1
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    s_lshr_b32 s3, s2, 16
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s3
+; SDAG-VI-NEXT:    v_cmp_eq_f16_e64 s[2:3], |s2|, |v0|
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    s_lshr_b32 s0, s4, 16
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_cmp_eq_f16_e64 s[0:1], |s4|, |v0|
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_oeq_both_operands_with_fabs:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    s_lshr_b32 s3, s2, 16
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s3
+; GISEL-VI-NEXT:    v_cmp_eq_f16_e64 s[2:3], |s2|, |v0|
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %temp = call half @llvm.fabs.f16(half %a)
   %src_input = call half @llvm.fabs.f16(half %src)
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src_input, half %temp, i32 1)
@@ -982,9 +1810,30 @@
 }
 
 define amdgpu_kernel void @v_fcmp_f16(i64 addrspace(1)* %out, half %src) {
-; GCN-LABEL: v_fcmp_f16:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    global_store_dwordx2 v0, v[0:1], s[0:1]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[0:1], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 -1)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -992,34 +1841,61 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_oeq(i64 addrspace(1)* %out, half %src) {
-; GFX-LABEL: v_fcmp_f16_oeq:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_mov_b32 s4, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
-; GFX-NEXT:    v_cmp_eq_f32_e64 s[4:5], s4, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_oeq:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x5640
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_eq_f16_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_oeq:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_mov_b32 s4, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; SDAG-GFX-NEXT:    v_cmp_eq_f32_e64 s[4:5], s4, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_oeq:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_eq_f16_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_oeq:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_eq_f16_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_oeq:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_eq_f16_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 1)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -1027,34 +1903,61 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_one(i64 addrspace(1)* %out, half %src) {
-; GFX-LABEL: v_fcmp_f16_one:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_mov_b32 s4, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
-; GFX-NEXT:    v_cmp_neq_f32_e64 s[4:5], s4, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_one:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x5640
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_neq_f16_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_one:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_mov_b32 s4, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; SDAG-GFX-NEXT:    v_cmp_neq_f32_e64 s[4:5], s4, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_one:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_neq_f16_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_one:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_neq_f16_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_one:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_neq_f16_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 6)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -1062,34 +1965,61 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_ogt(i64 addrspace(1)* %out, half %src) {
-; GFX-LABEL: v_fcmp_f16_ogt:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_mov_b32 s4, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
-; GFX-NEXT:    v_cmp_lt_f32_e64 s[4:5], s4, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_ogt:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x5640
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_gt_f16_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_ogt:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_mov_b32 s4, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; SDAG-GFX-NEXT:    v_cmp_lt_f32_e64 s[4:5], s4, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_ogt:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_gt_f16_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_ogt:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_gt_f16_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_ogt:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_gt_f16_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 2)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -1097,34 +2027,61 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_oge(i64 addrspace(1)* %out, half %src) {
-; GFX-LABEL: v_fcmp_f16_oge:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_mov_b32 s4, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
-; GFX-NEXT:    v_cmp_le_f32_e64 s[4:5], s4, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_oge:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x5640
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_ge_f16_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_oge:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_mov_b32 s4, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; SDAG-GFX-NEXT:    v_cmp_le_f32_e64 s[4:5], s4, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_oge:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_ge_f16_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_oge:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_ge_f16_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_oge:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_ge_f16_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 3)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -1132,34 +2089,61 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_olt(i64 addrspace(1)* %out, half %src) {
-; GFX-LABEL: v_fcmp_f16_olt:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_mov_b32 s4, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
-; GFX-NEXT:    v_cmp_gt_f32_e64 s[4:5], s4, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_olt:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x5640
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_lt_f16_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_olt:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_mov_b32 s4, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; SDAG-GFX-NEXT:    v_cmp_gt_f32_e64 s[4:5], s4, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_olt:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_lt_f16_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_olt:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_lt_f16_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_olt:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_lt_f16_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 4)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -1167,34 +2151,61 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_ole(i64 addrspace(1)* %out, half %src) {
-; GFX-LABEL: v_fcmp_f16_ole:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_mov_b32 s4, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
-; GFX-NEXT:    v_cmp_ge_f32_e64 s[4:5], s4, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_ole:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x5640
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_le_f16_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_ole:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_mov_b32 s4, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; SDAG-GFX-NEXT:    v_cmp_ge_f32_e64 s[4:5], s4, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_ole:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_le_f16_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_ole:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_le_f16_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_ole:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_le_f16_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 5)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -1202,34 +2213,61 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_ueq(i64 addrspace(1)* %out, half %src) {
-; GFX-LABEL: v_fcmp_f16_ueq:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_mov_b32 s4, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
-; GFX-NEXT:    v_cmp_nlg_f32_e64 s[4:5], s4, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_ueq:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x5640
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_nlg_f16_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_ueq:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_mov_b32 s4, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; SDAG-GFX-NEXT:    v_cmp_nlg_f32_e64 s[4:5], s4, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_ueq:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_nlg_f16_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_ueq:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_nlg_f16_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_ueq:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_nlg_f16_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 9)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -1237,34 +2275,61 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_une(i64 addrspace(1)* %out, half %src) {
-; GFX-LABEL: v_fcmp_f16_une:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_mov_b32 s4, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
-; GFX-NEXT:    v_cmp_neq_f32_e64 s[4:5], s4, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_une:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x5640
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_neq_f16_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_une:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_mov_b32 s4, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; SDAG-GFX-NEXT:    v_cmp_neq_f32_e64 s[4:5], s4, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_une:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_neq_f16_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_une:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_neq_f16_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_une:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_neq_f16_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 14)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -1272,34 +2337,61 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_ugt(i64 addrspace(1)* %out, half %src) {
-; GFX-LABEL: v_fcmp_f16_ugt:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_mov_b32 s4, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
-; GFX-NEXT:    v_cmp_nge_f32_e64 s[4:5], s4, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_ugt:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x5640
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_nle_f16_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_ugt:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_mov_b32 s4, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; SDAG-GFX-NEXT:    v_cmp_nge_f32_e64 s[4:5], s4, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_ugt:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_nle_f16_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_ugt:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_nle_f16_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_ugt:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_nle_f16_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 10)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -1307,34 +2399,61 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_uge(i64 addrspace(1)* %out, half %src) {
-; GFX-LABEL: v_fcmp_f16_uge:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_mov_b32 s4, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
-; GFX-NEXT:    v_cmp_ngt_f32_e64 s[4:5], s4, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_uge:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x5640
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_nlt_f16_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_uge:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_mov_b32 s4, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; SDAG-GFX-NEXT:    v_cmp_ngt_f32_e64 s[4:5], s4, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_uge:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_nlt_f16_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_uge:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_nlt_f16_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_uge:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_nlt_f16_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 11)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -1342,34 +2461,61 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_ult(i64 addrspace(1)* %out, half %src) {
-; GFX-LABEL: v_fcmp_f16_ult:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_mov_b32 s4, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
-; GFX-NEXT:    v_cmp_nle_f32_e64 s[4:5], s4, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_ult:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x5640
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_nge_f16_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_ult:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_mov_b32 s4, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; SDAG-GFX-NEXT:    v_cmp_nle_f32_e64 s[4:5], s4, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_ult:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_nge_f16_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_ult:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_nge_f16_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_ult:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_nge_f16_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 12)
   store i64 %result, i64 addrspace(1)* %out
   ret void
@@ -1377,37 +2523,68 @@
 
 
 define amdgpu_kernel void @v_fcmp_f16_ule(i64 addrspace(1)* %out, half %src) {
-; GFX-LABEL: v_fcmp_f16_ule:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
-; GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX-NEXT:    s_mov_b32 s3, 0xf000
-; GFX-NEXT:    s_mov_b32 s4, 0x42c80000
-; GFX-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
-; GFX-NEXT:    v_cmp_nlt_f32_e64 s[4:5], s4, v0
-; GFX-NEXT:    s_mov_b32 s2, -1
-; GFX-NEXT:    v_mov_b32_e32 v0, s4
-; GFX-NEXT:    v_mov_b32_e32 v1, s5
-; GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
-; GFX-NEXT:    s_endpgm
-;
-; VI-LABEL: v_fcmp_f16_ule:
-; VI:       ; %bb.0:
-; VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; VI-NEXT:    v_mov_b32_e32 v0, 0x5640
-; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_cmp_ngt_f16_e64 s[2:3], s2, v0
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v2, s2
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_mov_b32_e32 v3, s3
-; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
-; VI-NEXT:    s_endpgm
+; SDAG-GFX-LABEL: v_fcmp_f16_ule:
+; SDAG-GFX:       ; %bb.0:
+; SDAG-GFX-NEXT:    s_load_dword s2, s[0:1], 0xb
+; SDAG-GFX-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SDAG-GFX-NEXT:    s_mov_b32 s3, 0xf000
+; SDAG-GFX-NEXT:    s_mov_b32 s4, 0x42c80000
+; SDAG-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-GFX-NEXT:    v_cvt_f32_f16_e32 v0, s2
+; SDAG-GFX-NEXT:    v_cmp_nlt_f32_e64 s[4:5], s4, v0
+; SDAG-GFX-NEXT:    s_mov_b32 s2, -1
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v0, s4
+; SDAG-GFX-NEXT:    v_mov_b32_e32 v1, s5
+; SDAG-GFX-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SDAG-GFX-NEXT:    s_endpgm
+;
+; SDAG-VI-LABEL: v_fcmp_f16_ule:
+; SDAG-VI:       ; %bb.0:
+; SDAG-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; SDAG-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; SDAG-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; SDAG-VI-NEXT:    v_cmp_ngt_f16_e64 s[2:3], s2, v0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v0, s0
+; SDAG-VI-NEXT:    v_mov_b32_e32 v2, s2
+; SDAG-VI-NEXT:    v_mov_b32_e32 v1, s1
+; SDAG-VI-NEXT:    v_mov_b32_e32 v3, s3
+; SDAG-VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; SDAG-VI-NEXT:    s_endpgm
+;
+; GISEL-GFX-LABEL: v_fcmp_f16_ule:
+; GISEL-GFX:       ; %bb.0:
+; GISEL-GFX-NEXT:    s_load_dword s4, s[0:1], 0x2c
+; GISEL-GFX-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v2, 0
+; GISEL-GFX-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-GFX-NEXT:    v_cmp_ngt_f16_e64 s[0:1], s4, v0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v0, s0
+; GISEL-GFX-NEXT:    v_mov_b32_e32 v1, s1
+; GISEL-GFX-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
+; GISEL-GFX-NEXT:    s_endpgm
+;
+; GISEL-VI-LABEL: v_fcmp_f16_ule:
+; GISEL-VI:       ; %bb.0:
+; GISEL-VI-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GISEL-VI-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, 0x5640
+; GISEL-VI-NEXT:    s_waitcnt lgkmcnt(0)
+; GISEL-VI-NEXT:    v_cmp_ngt_f16_e64 s[2:3], s2, v0
+; GISEL-VI-NEXT:    v_mov_b32_e32 v0, s2
+; GISEL-VI-NEXT:    v_mov_b32_e32 v3, s1
+; GISEL-VI-NEXT:    v_mov_b32_e32 v1, s3
+; GISEL-VI-NEXT:    v_mov_b32_e32 v2, s0
+; GISEL-VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GISEL-VI-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.fcmp.f16(half %src, half 100.00, i32 13)
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 attributes #0 = { nounwind readnone convergent }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GCN: {{.*}}
+; GFX: {{.*}}
+; VI: {{.*}}