Index: llvm/include/llvm/CodeGen/TargetLowering.h =================================================================== --- llvm/include/llvm/CodeGen/TargetLowering.h +++ llvm/include/llvm/CodeGen/TargetLowering.h @@ -1943,7 +1943,7 @@ /// the backend. Atomic operations greater than this size (as well /// as ones that are not naturally aligned), will be expanded by /// AtomicExpandPass into an __atomic_* library call. - unsigned getMaxAtomicSizeInBitsSupported() const { + virtual unsigned getMaxAtomicSizeInBitsSupported(Instruction *) const { return MaxAtomicSizeInBitsSupported; } Index: llvm/lib/CodeGen/AtomicExpandPass.cpp =================================================================== --- llvm/lib/CodeGen/AtomicExpandPass.cpp +++ llvm/lib/CodeGen/AtomicExpandPass.cpp @@ -173,7 +173,7 @@ unsigned Size = getAtomicOpSize(I); Align Alignment = I->getAlign(); return Alignment >= Size && - Size <= TLI->getMaxAtomicSizeInBitsSupported() / 8; + Size <= TLI->getMaxAtomicSizeInBitsSupported(I) / 8; } bool AtomicExpand::runOnFunction(Function &F) { Index: llvm/lib/Target/M68k/M68kISelLowering.h =================================================================== --- llvm/lib/Target/M68k/M68kISelLowering.h +++ llvm/lib/Target/M68k/M68kISelLowering.h @@ -174,6 +174,8 @@ CCAssignFn *getCCAssignFn(CallingConv::ID CC, bool Return, bool IsVarArg) const; + unsigned getMaxAtomicSizeInBitsSupported(Instruction *I) const override; + private: unsigned GetAlignedArgumentStackSize(unsigned StackSize, SelectionDAG &DAG) const; Index: llvm/lib/Target/M68k/M68kISelLowering.cpp =================================================================== --- llvm/lib/Target/M68k/M68kISelLowering.cpp +++ llvm/lib/Target/M68k/M68kISelLowering.cpp @@ -31,6 +31,7 @@ #include "llvm/IR/CallingConv.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/GlobalVariable.h" +#include "llvm/IR/Instructions.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -162,6 +163,14 @@ setMinFunctionAlignment(Align::Constant<2>()); } +unsigned +M68kTargetLowering::getMaxAtomicSizeInBitsSupported(Instruction *I) const { + if (isa(I) || + (isa(I) && Subtarget.atLeastM68020())) + return 32; + return 0; +} + EVT M68kTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const { // M68k SETcc producess either 0x00 or 0xFF Index: llvm/lib/Target/M68k/M68kInstrAtomics.td =================================================================== --- /dev/null +++ llvm/lib/Target/M68k/M68kInstrAtomics.td @@ -0,0 +1,43 @@ +//===-- M68kInstrAtomics.td - Atomics Instructions ---------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// FIXME: This is only supported on MC68020 and later. +class MxCASOp size_encoding, MxType type> + : MxInst<(outs type.ROp:$out), + (ins type.ROp:$dc, type.ROp:$du, !cast("MxARI"#type.Size):$mem), + "cas."#type.Prefix#" $dc, $du, $mem"> { + let Inst = (ascend + (descend 0b00001, size_encoding, 0b011, MxEncAddrMode_j<"mem">.EA), + (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3)) + ); + let Constraints = "$out = $dc"; + let mayLoad = 1; + let mayStore = 1; +} + +def CAS8 : MxCASOp<0x1, MxType8d>; +def CAS16 : MxCASOp<0x2, MxType16d>; +def CAS32 : MxCASOp<0x3, MxType32d>; + + +foreach size = [8, 16, 32] in { + def : Pat<(!cast("atomic_load_"#size) MxCP_ARI:$ptr), + (!cast("MOV"#size#"dj") !cast("MxARI"#size):$ptr)>; + + def : Pat<(!cast("atomic_store_"#size) MxCP_ARI:$ptr, + !cast("MxDRD"#size):$val), + (!cast("MOV"#size#"jd") !cast("MxARI"#size):$ptr, + !cast("MxDRD"#size):$val)>; + + def : Pat<(!cast("atomic_cmp_swap_"#size) MxCP_ARI:$ptr, + !cast("MxDRD"#size):$cmp, + !cast("MxDRD"#size):$new), + (!cast("CAS"#size) !cast("MxDRD"#size):$cmp, + !cast("MxDRD"#size):$new, + !cast("MxARI"#size):$ptr)>; +} Index: llvm/lib/Target/M68k/M68kInstrInfo.td =================================================================== --- llvm/lib/Target/M68k/M68kInstrInfo.td +++ llvm/lib/Target/M68k/M68kInstrInfo.td @@ -781,5 +781,6 @@ include "M68kInstrBits.td" include "M68kInstrArithmetic.td" include "M68kInstrControl.td" +include "M68kInstrAtomics.td" include "M68kInstrCompiler.td" Index: llvm/lib/Target/M68k/M68kTargetMachine.cpp =================================================================== --- llvm/lib/Target/M68k/M68kTargetMachine.cpp +++ llvm/lib/Target/M68k/M68kTargetMachine.cpp @@ -143,6 +143,7 @@ const M68kSubtarget &getM68kSubtarget() const { return *getM68kTargetMachine().getSubtargetImpl(); } + void addIRPasses() override; bool addIRTranslator() override; bool addLegalizeMachineIR() override; bool addRegBankSelect() override; @@ -157,6 +158,8 @@ return new M68kPassConfig(*this, PM); } +void M68kPassConfig::addIRPasses() { addPass(createAtomicExpandPass()); } + bool M68kPassConfig::addInstSelector() { // Install an instruction selector. addPass(createM68kISelDag(getM68kTargetMachine())); Index: llvm/test/CodeGen/M68k/Atomics/cmpxchg.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/M68k/Atomics/cmpxchg.ll @@ -0,0 +1,100 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc %s -o - -mtriple=m68k -mcpu=M68000 | FileCheck %s --check-prefix=NO-ATOMIC +; RUN: llc %s -o - -mtriple=m68k -mcpu=M68010 | FileCheck %s --check-prefix=NO-ATOMIC +; RUN: llc %s -o - -mtriple=m68k -mcpu=M68020 | FileCheck %s --check-prefix=ATOMIC +; RUN: llc %s -o - -mtriple=m68k -mcpu=M68030 | FileCheck %s --check-prefix=ATOMIC +; RUN: llc %s -o - -mtriple=m68k -mcpu=M68040 | FileCheck %s --check-prefix=ATOMIC + +define i1 @cmpxchg_i8_monotonic_monotonic(i8 %cmp, i8 %new, ptr %mem) nounwind { +; NO-ATOMIC-LABEL: cmpxchg_i8_monotonic_monotonic: +; NO-ATOMIC: ; %bb.0: +; NO-ATOMIC-NEXT: suba.l #28, %sp +; NO-ATOMIC-NEXT: move.b (35,%sp), (27,%sp) +; NO-ATOMIC-NEXT: move.b (39,%sp), %d0 +; NO-ATOMIC-NEXT: and.l #255, %d0 +; NO-ATOMIC-NEXT: move.l %d0, (8,%sp) +; NO-ATOMIC-NEXT: lea (27,%sp), %a0 +; NO-ATOMIC-NEXT: move.l %a0, (4,%sp) +; NO-ATOMIC-NEXT: move.l #0, (16,%sp) +; NO-ATOMIC-NEXT: move.l #0, (12,%sp) +; NO-ATOMIC-NEXT: move.l (40,%sp), (%sp) +; NO-ATOMIC-NEXT: jsr __atomic_compare_exchange_1@PLT +; NO-ATOMIC-NEXT: adda.l #28, %sp +; NO-ATOMIC-NEXT: rts +; +; ATOMIC-LABEL: cmpxchg_i8_monotonic_monotonic: +; ATOMIC: ; %bb.0: +; ATOMIC-NEXT: suba.l #4, %sp +; ATOMIC-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill +; ATOMIC-NEXT: move.l (16,%sp), %a0 +; ATOMIC-NEXT: move.b (15,%sp), %d0 +; ATOMIC-NEXT: move.b (11,%sp), %d1 +; ATOMIC-NEXT: move.b %d1, %d2 +; ATOMIC-NEXT: cas.b %d2, %d0, (%a0) +; ATOMIC-NEXT: sub.b %d1, %d2 +; ATOMIC-NEXT: seq %d0 +; ATOMIC-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload +; ATOMIC-NEXT: adda.l #4, %sp +; ATOMIC-NEXT: rts + %res = cmpxchg ptr %mem, i8 %cmp, i8 %new monotonic monotonic + %val = extractvalue {i8, i1} %res, 1 + ret i1 %val +} + +define i16 @cmpxchg_i16_release_monotonic(i16 %cmp, i16 %new, ptr %mem) nounwind { +; NO-ATOMIC-LABEL: cmpxchg_i16_release_monotonic: +; NO-ATOMIC: ; %bb.0: +; NO-ATOMIC-NEXT: suba.l #28, %sp +; NO-ATOMIC-NEXT: move.w (34,%sp), (26,%sp) +; NO-ATOMIC-NEXT: move.w (38,%sp), %d0 +; NO-ATOMIC-NEXT: and.l #65535, %d0 +; NO-ATOMIC-NEXT: move.l %d0, (8,%sp) +; NO-ATOMIC-NEXT: lea (26,%sp), %a0 +; NO-ATOMIC-NEXT: move.l %a0, (4,%sp) +; NO-ATOMIC-NEXT: move.l #0, (16,%sp) +; NO-ATOMIC-NEXT: move.l #3, (12,%sp) +; NO-ATOMIC-NEXT: move.l (40,%sp), (%sp) +; NO-ATOMIC-NEXT: jsr __atomic_compare_exchange_2@PLT +; NO-ATOMIC-NEXT: move.w (26,%sp), %d0 +; NO-ATOMIC-NEXT: adda.l #28, %sp +; NO-ATOMIC-NEXT: rts +; +; ATOMIC-LABEL: cmpxchg_i16_release_monotonic: +; ATOMIC: ; %bb.0: +; ATOMIC-NEXT: move.l (12,%sp), %a0 +; ATOMIC-NEXT: move.w (10,%sp), %d1 +; ATOMIC-NEXT: move.w (6,%sp), %d0 +; ATOMIC-NEXT: cas.w %d0, %d1, (%a0) +; ATOMIC-NEXT: rts + %res = cmpxchg ptr %mem, i16 %cmp, i16 %new release monotonic + %val = extractvalue {i16, i1} %res, 0 + ret i16 %val +} + +define i32 @cmpxchg_i32_release_acquire(i32 %cmp, i32 %new, ptr %mem) nounwind { +; NO-ATOMIC-LABEL: cmpxchg_i32_release_acquire: +; NO-ATOMIC: ; %bb.0: +; NO-ATOMIC-NEXT: suba.l #28, %sp +; NO-ATOMIC-NEXT: move.l (32,%sp), (24,%sp) +; NO-ATOMIC-NEXT: lea (24,%sp), %a0 +; NO-ATOMIC-NEXT: move.l %a0, (4,%sp) +; NO-ATOMIC-NEXT: move.l #2, (16,%sp) +; NO-ATOMIC-NEXT: move.l #3, (12,%sp) +; NO-ATOMIC-NEXT: move.l (36,%sp), (8,%sp) +; NO-ATOMIC-NEXT: move.l (40,%sp), (%sp) +; NO-ATOMIC-NEXT: jsr __atomic_compare_exchange_4@PLT +; NO-ATOMIC-NEXT: move.l (24,%sp), %d0 +; NO-ATOMIC-NEXT: adda.l #28, %sp +; NO-ATOMIC-NEXT: rts +; +; ATOMIC-LABEL: cmpxchg_i32_release_acquire: +; ATOMIC: ; %bb.0: +; ATOMIC-NEXT: move.l (12,%sp), %a0 +; ATOMIC-NEXT: move.l (8,%sp), %d1 +; ATOMIC-NEXT: move.l (4,%sp), %d0 +; ATOMIC-NEXT: cas.l %d0, %d1, (%a0) +; ATOMIC-NEXT: rts + %res = cmpxchg ptr %mem, i32 %cmp, i32 %new release acquire + %val = extractvalue {i32, i1} %res, 0 + ret i32 %val +} Index: llvm/test/CodeGen/M68k/Atomics/load-store.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/M68k/Atomics/load-store.ll @@ -0,0 +1,366 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=m68k -o - %s | FileCheck %s + +define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { +; CHECK-LABEL: atomic_load_i8_unordered: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.b (%a0), %d0 +; CHECK-NEXT: rts + %1 = load atomic i8, i8* %a unordered, align 1 + ret i8 %1 +} + +define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind { +; CHECK-LABEL: atomic_load_i8_monotonic: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.b (%a0), %d0 +; CHECK-NEXT: rts + %1 = load atomic i8, i8* %a monotonic, align 1 + ret i8 %1 +} + +define i8 @atomic_load_i8_acquire(i8 *%a) nounwind { +; CHECK-LABEL: atomic_load_i8_acquire: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.b (%a0), %d0 +; CHECK-NEXT: rts + %1 = load atomic i8, i8* %a acquire, align 1 + ret i8 %1 +} + +define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind { +; CHECK-LABEL: atomic_load_i8_seq_cst: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.b (%a0), %d0 +; CHECK-NEXT: rts + %1 = load atomic i8, i8* %a seq_cst, align 1 + ret i8 %1 +} + +define i16 @atomic_load_i16_unordered(i16 *%a) nounwind { +; CHECK-LABEL: atomic_load_i16_unordered: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.w (%a0), %d0 +; CHECK-NEXT: rts + %1 = load atomic i16, i16* %a unordered, align 2 + ret i16 %1 +} + +define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind { +; CHECK-LABEL: atomic_load_i16_monotonic: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.w (%a0), %d0 +; CHECK-NEXT: rts + %1 = load atomic i16, i16* %a monotonic, align 2 + ret i16 %1 +} + +define i16 @atomic_load_i16_acquire(i16 *%a) nounwind { +; CHECK-LABEL: atomic_load_i16_acquire: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.w (%a0), %d0 +; CHECK-NEXT: rts + %1 = load atomic i16, i16* %a acquire, align 2 + ret i16 %1 +} + +define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind { +; CHECK-LABEL: atomic_load_i16_seq_cst: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.w (%a0), %d0 +; CHECK-NEXT: rts + %1 = load atomic i16, i16* %a seq_cst, align 2 + ret i16 %1 +} + +define i32 @atomic_load_i32_unordered(i32 *%a) nounwind { +; CHECK-LABEL: atomic_load_i32_unordered: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.l (%a0), %d0 +; CHECK-NEXT: rts + %1 = load atomic i32, i32* %a unordered, align 4 + ret i32 %1 +} + +define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind { +; CHECK-LABEL: atomic_load_i32_monotonic: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.l (%a0), %d0 +; CHECK-NEXT: rts + %1 = load atomic i32, i32* %a monotonic, align 4 + ret i32 %1 +} + +define i32 @atomic_load_i32_acquire(i32 *%a) nounwind { +; CHECK-LABEL: atomic_load_i32_acquire: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.l (%a0), %d0 +; CHECK-NEXT: rts + %1 = load atomic i32, i32* %a acquire, align 4 + ret i32 %1 +} + +define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind { +; CHECK-LABEL: atomic_load_i32_seq_cst: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.l (%a0), %d0 +; CHECK-NEXT: rts + %1 = load atomic i32, i32* %a seq_cst, align 4 + ret i32 %1 +} + +define i64 @atomic_load_i64_unordered(i64 *%a) nounwind { +; CHECK-LABEL: atomic_load_i64_unordered: +; CHECK: ; %bb.0: +; CHECK-NEXT: suba.l #12, %sp +; CHECK-NEXT: move.l #0, (4,%sp) +; CHECK-NEXT: move.l (16,%sp), (%sp) +; CHECK-NEXT: jsr __atomic_load_8@PLT +; CHECK-NEXT: adda.l #12, %sp +; CHECK-NEXT: rts + %1 = load atomic i64, i64* %a unordered, align 8 + ret i64 %1 +} + +define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind { +; CHECK-LABEL: atomic_load_i64_monotonic: +; CHECK: ; %bb.0: +; CHECK-NEXT: suba.l #12, %sp +; CHECK-NEXT: move.l #0, (4,%sp) +; CHECK-NEXT: move.l (16,%sp), (%sp) +; CHECK-NEXT: jsr __atomic_load_8@PLT +; CHECK-NEXT: adda.l #12, %sp +; CHECK-NEXT: rts + %1 = load atomic i64, i64* %a monotonic, align 8 + ret i64 %1 +} + +define i64 @atomic_load_i64_acquire(i64 *%a) nounwind { +; CHECK-LABEL: atomic_load_i64_acquire: +; CHECK: ; %bb.0: +; CHECK-NEXT: suba.l #12, %sp +; CHECK-NEXT: move.l #2, (4,%sp) +; CHECK-NEXT: move.l (16,%sp), (%sp) +; CHECK-NEXT: jsr __atomic_load_8@PLT +; CHECK-NEXT: adda.l #12, %sp +; CHECK-NEXT: rts + %1 = load atomic i64, i64* %a acquire, align 8 + ret i64 %1 +} + +define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind { +; CHECK-LABEL: atomic_load_i64_seq_cst: +; CHECK: ; %bb.0: +; CHECK-NEXT: suba.l #12, %sp +; CHECK-NEXT: move.l #5, (4,%sp) +; CHECK-NEXT: move.l (16,%sp), (%sp) +; CHECK-NEXT: jsr __atomic_load_8@PLT +; CHECK-NEXT: adda.l #12, %sp +; CHECK-NEXT: rts + %1 = load atomic i64, i64* %a seq_cst, align 8 + ret i64 %1 +} + +define void @atomic_store_i8_unordered(i8 *%a, i8 %val) nounwind { +; CHECK-LABEL: atomic_store_i8_unordered: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.b (11,%sp), %d0 +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.b %d0, (%a0) +; CHECK-NEXT: rts + store atomic i8 %val, i8* %a unordered, align 1 + ret void +} + +define void @atomic_store_i8_monotonic(i8 *%a, i8 %val) nounwind { +; CHECK-LABEL: atomic_store_i8_monotonic: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.b (11,%sp), %d0 +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.b %d0, (%a0) +; CHECK-NEXT: rts + store atomic i8 %val, i8* %a monotonic, align 1 + ret void +} + +define void @atomic_store_i8_release(i8 *%a, i8 %val) nounwind { +; CHECK-LABEL: atomic_store_i8_release: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.b (11,%sp), %d0 +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.b %d0, (%a0) +; CHECK-NEXT: rts + store atomic i8 %val, i8* %a release, align 1 + ret void +} + +define void @atomic_store_i8_seq_cst(i8 *%a, i8 %val) nounwind { +; CHECK-LABEL: atomic_store_i8_seq_cst: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.b (11,%sp), %d0 +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.b %d0, (%a0) +; CHECK-NEXT: rts + store atomic i8 %val, i8* %a seq_cst, align 1 + ret void +} + +define void @atomic_store_i16_unordered(i16 *%a, i16 %val) nounwind { +; CHECK-LABEL: atomic_store_i16_unordered: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.w (10,%sp), %d0 +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.w %d0, (%a0) +; CHECK-NEXT: rts + store atomic i16 %val, i16* %a unordered, align 2 + ret void +} + +define void @atomic_store_i16_monotonic(i16 *%a, i16 %val) nounwind { +; CHECK-LABEL: atomic_store_i16_monotonic: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.w (10,%sp), %d0 +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.w %d0, (%a0) +; CHECK-NEXT: rts + store atomic i16 %val, i16* %a monotonic, align 2 + ret void +} + +define void @atomic_store_i16_release(i16 *%a, i16 %val) nounwind { +; CHECK-LABEL: atomic_store_i16_release: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.w (10,%sp), %d0 +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.w %d0, (%a0) +; CHECK-NEXT: rts + store atomic i16 %val, i16* %a release, align 2 + ret void +} + +define void @atomic_store_i16_seq_cst(i16 *%a, i16 %val) nounwind { +; CHECK-LABEL: atomic_store_i16_seq_cst: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.w (10,%sp), %d0 +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.w %d0, (%a0) +; CHECK-NEXT: rts + store atomic i16 %val, i16* %a seq_cst, align 2 + ret void +} + +define void @atomic_store_i32_unordered(i32 *%a, i32 %val) nounwind { +; CHECK-LABEL: atomic_store_i32_unordered: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (8,%sp), %d0 +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.l %d0, (%a0) +; CHECK-NEXT: rts + store atomic i32 %val, i32* %a unordered, align 4 + ret void +} + +define void @atomic_store_i32_monotonic(i32 *%a, i32 %val) nounwind { +; CHECK-LABEL: atomic_store_i32_monotonic: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (8,%sp), %d0 +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.l %d0, (%a0) +; CHECK-NEXT: rts + store atomic i32 %val, i32* %a monotonic, align 4 + ret void +} + +define void @atomic_store_i32_release(i32 *%a, i32 %val) nounwind { +; CHECK-LABEL: atomic_store_i32_release: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (8,%sp), %d0 +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.l %d0, (%a0) +; CHECK-NEXT: rts + store atomic i32 %val, i32* %a release, align 4 + ret void +} + +define void @atomic_store_i32_seq_cst(i32 *%a, i32 %val) nounwind { +; CHECK-LABEL: atomic_store_i32_seq_cst: +; CHECK: ; %bb.0: +; CHECK-NEXT: move.l (8,%sp), %d0 +; CHECK-NEXT: move.l (4,%sp), %a0 +; CHECK-NEXT: move.l %d0, (%a0) +; CHECK-NEXT: rts + store atomic i32 %val, i32* %a seq_cst, align 4 + ret void +} + +define void @atomic_store_i64_unordered(i64 *%a, i64 %val) nounwind { +; CHECK-LABEL: atomic_store_i64_unordered: +; CHECK: ; %bb.0: +; CHECK-NEXT: suba.l #20, %sp +; CHECK-NEXT: move.l #0, (12,%sp) +; CHECK-NEXT: move.l (32,%sp), (8,%sp) +; CHECK-NEXT: move.l (28,%sp), (4,%sp) +; CHECK-NEXT: move.l (24,%sp), (%sp) +; CHECK-NEXT: jsr __atomic_store_8@PLT +; CHECK-NEXT: adda.l #20, %sp +; CHECK-NEXT: rts + store atomic i64 %val, i64* %a unordered, align 8 + ret void +} + +define void @atomic_store_i64_monotonic(i64 *%a, i64 %val) nounwind { +; CHECK-LABEL: atomic_store_i64_monotonic: +; CHECK: ; %bb.0: +; CHECK-NEXT: suba.l #20, %sp +; CHECK-NEXT: move.l #0, (12,%sp) +; CHECK-NEXT: move.l (32,%sp), (8,%sp) +; CHECK-NEXT: move.l (28,%sp), (4,%sp) +; CHECK-NEXT: move.l (24,%sp), (%sp) +; CHECK-NEXT: jsr __atomic_store_8@PLT +; CHECK-NEXT: adda.l #20, %sp +; CHECK-NEXT: rts + store atomic i64 %val, i64* %a monotonic, align 8 + ret void +} + +define void @atomic_store_i64_release(i64 *%a, i64 %val) nounwind { +; CHECK-LABEL: atomic_store_i64_release: +; CHECK: ; %bb.0: +; CHECK-NEXT: suba.l #20, %sp +; CHECK-NEXT: move.l #3, (12,%sp) +; CHECK-NEXT: move.l (32,%sp), (8,%sp) +; CHECK-NEXT: move.l (28,%sp), (4,%sp) +; CHECK-NEXT: move.l (24,%sp), (%sp) +; CHECK-NEXT: jsr __atomic_store_8@PLT +; CHECK-NEXT: adda.l #20, %sp +; CHECK-NEXT: rts + store atomic i64 %val, i64* %a release, align 8 + ret void +} + +define void @atomic_store_i64_seq_cst(i64 *%a, i64 %val) nounwind { +; CHECK-LABEL: atomic_store_i64_seq_cst: +; CHECK: ; %bb.0: +; CHECK-NEXT: suba.l #20, %sp +; CHECK-NEXT: move.l #5, (12,%sp) +; CHECK-NEXT: move.l (32,%sp), (8,%sp) +; CHECK-NEXT: move.l (28,%sp), (4,%sp) +; CHECK-NEXT: move.l (24,%sp), (%sp) +; CHECK-NEXT: jsr __atomic_store_8@PLT +; CHECK-NEXT: adda.l #20, %sp +; CHECK-NEXT: rts + store atomic i64 %val, i64* %a seq_cst, align 8 + ret void +} Index: llvm/test/CodeGen/M68k/Atomics/rmw.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/M68k/Atomics/rmw.ll @@ -0,0 +1,54 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc %s -o - -mtriple=m68k | FileCheck %s + +define i8 @atomicrmw_i8(i8 %val, ptr %ptr) { +; CHECK-LABEL: atomicrmw_i8: +; CHECK: .cfi_startproc +; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: suba.l #12, %sp +; CHECK-NEXT: .cfi_def_cfa_offset -16 +; CHECK-NEXT: move.b (19,%sp), %d0 +; CHECK-NEXT: and.l #255, %d0 +; CHECK-NEXT: move.l %d0, (4,%sp) +; CHECK-NEXT: move.l #0, (8,%sp) +; CHECK-NEXT: move.l (20,%sp), (%sp) +; CHECK-NEXT: jsr __atomic_fetch_add_1@PLT +; CHECK-NEXT: adda.l #12, %sp +; CHECK-NEXT: rts + %old = atomicrmw add ptr %ptr, i8 %val monotonic + ret i8 %old +} + +define i16 @atomicrmw_i16(i16 %val, ptr %ptr) { +; CHECK-LABEL: atomicrmw_i16: +; CHECK: .cfi_startproc +; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: suba.l #12, %sp +; CHECK-NEXT: .cfi_def_cfa_offset -16 +; CHECK-NEXT: move.w (18,%sp), %d0 +; CHECK-NEXT: and.l #65535, %d0 +; CHECK-NEXT: move.l %d0, (4,%sp) +; CHECK-NEXT: move.l #2, (8,%sp) +; CHECK-NEXT: move.l (20,%sp), (%sp) +; CHECK-NEXT: jsr __atomic_fetch_sub_2@PLT +; CHECK-NEXT: adda.l #12, %sp +; CHECK-NEXT: rts + %old = atomicrmw sub ptr %ptr, i16 %val acquire + ret i16 %old +} + +define i32 @atomicrmw_i32(i32 %val, ptr %ptr) { +; CHECK-LABEL: atomicrmw_i32: +; CHECK: .cfi_startproc +; CHECK-NEXT: ; %bb.0: +; CHECK-NEXT: suba.l #12, %sp +; CHECK-NEXT: .cfi_def_cfa_offset -16 +; CHECK-NEXT: move.l #5, (8,%sp) +; CHECK-NEXT: move.l (16,%sp), (4,%sp) +; CHECK-NEXT: move.l (20,%sp), (%sp) +; CHECK-NEXT: jsr __atomic_fetch_xor_4@PLT +; CHECK-NEXT: adda.l #12, %sp +; CHECK-NEXT: rts + %old = atomicrmw xor ptr %ptr, i32 %val seq_cst + ret i32 %old +} Index: llvm/test/CodeGen/M68k/pipeline.ll =================================================================== --- llvm/test/CodeGen/M68k/pipeline.ll +++ llvm/test/CodeGen/M68k/pipeline.ll @@ -3,39 +3,9 @@ ; CHECK-NEXT: Pre-ISel Intrinsic Lowering ; CHECK-NEXT: FunctionPass Manager ; CHECK-NEXT: Expand large div/rem -; CHECK-NEXT: Module Verifier +; CHECK-NEXT: Expand Atomic instructions ; CHECK-NEXT: Dominator Tree Construction -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) -; CHECK-NEXT: Natural Loop Information -; CHECK-NEXT: Canonicalize natural loops -; CHECK-NEXT: Scalar Evolution Analysis -; CHECK-NEXT: Loop Pass Manager -; CHECK-NEXT: Canonicalize Freeze Instructions in Loops -; CHECK-NEXT: Induction Variable Users -; CHECK-NEXT: Loop Strength Reduction -; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) -; CHECK-NEXT: Function Alias Analysis Results -; CHECK-NEXT: Merge contiguous icmps into a memcmp -; CHECK-NEXT: Natural Loop Information -; CHECK-NEXT: Lazy Branch Probability Analysis -; CHECK-NEXT: Lazy Block Frequency Analysis -; CHECK-NEXT: Expand memcmp() to load/stores -; CHECK-NEXT: Lower Garbage Collection Instructions -; CHECK-NEXT: Shadow Stack GC Lowering -; CHECK-NEXT: Lower constant intrinsics -; CHECK-NEXT: Remove unreachable blocks from the CFG -; CHECK-NEXT: Natural Loop Information -; CHECK-NEXT: Post-Dominator Tree Construction -; CHECK-NEXT: Branch Probability Analysis -; CHECK-NEXT: Block Frequency Analysis -; CHECK-NEXT: Constant Hoisting -; CHECK-NEXT: Replace intrinsics with calls to vector library -; CHECK-NEXT: Partially inline calls to library functions -; CHECK-NEXT: Expand vector predication intrinsics -; CHECK-NEXT: Scalarize Masked Memory Intrinsics -; CHECK-NEXT: Expand reduction intrinsics ; CHECK-NEXT: Natural Loop Information -; CHECK-NEXT: TLS Variable Hoist ; CHECK-NEXT: CodeGen Prepare ; CHECK-NEXT: Dominator Tree Construction ; CHECK-NEXT: Exception handling preparation @@ -131,4 +101,4 @@ ; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: M68k Assembly Printer -; CHECK-NEXT: Free MachineFunction \ No newline at end of file +; CHECK-NEXT: Free MachineFunction Index: llvm/test/MC/Disassembler/M68k/atomics.txt =================================================================== --- /dev/null +++ llvm/test/MC/Disassembler/M68k/atomics.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc -disassemble %s -triple=m68k | FileCheck %s + +# CHECK: cas.b %d3, %d2, (%a2) +0x0a 0xd2 0x00 0x83 + +# CHECK: cas.w %d4, %d5, (%a3) +0x0c 0xd3 0x01 0x44 + +# CHECK: cas.l %d6, %d7, (%a4) +0x0e 0xd4 0x01 0xc6 \ No newline at end of file Index: llvm/test/MC/M68k/Atomics/cas.s =================================================================== --- /dev/null +++ llvm/test/MC/M68k/Atomics/cas.s @@ -0,0 +1,13 @@ +; RUN: llvm-mc -show-encoding -triple=m68k %s | FileCheck %s + +; CHECK: cas.b %d3, %d2, (%a2) +; CHECK-SAME: ; encoding: [0x0a,0xd2,0x00,0x83] +cas.b %d3, %d2, (%a2) + +; CHECK: cas.w %d4, %d5, (%a3) +; CHECK-SAME: ; encoding: [0x0c,0xd3,0x01,0x44] +cas.w %d4, %d5, (%a3) + +; CHECK: cas.l %d6, %d7, (%a4) +; CHECK-SAME: ; encoding: [0x0e,0xd4,0x01,0xc6] +cas.l %d6, %d7, (%a4)