Index: lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- lib/Target/Mips/MipsISelLowering.cpp
+++ lib/Target/Mips/MipsISelLowering.cpp
@@ -1409,8 +1409,13 @@
       "Unsupported size for EmitAtomicCmpSwapPartial.");
 
   MachineFunction *MF = BB->getParent();
+  bool ArePtrs64bit = ABI.IsN64();
+  bool AreInts64bit = ABI.IsN64() || ABI.IsN32();
   MachineRegisterInfo &RegInfo = MF->getRegInfo();
-  const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
+  llvm::MVT PointerSize = ArePtrs64bit ? MVT::i64 : MVT::i32;
+  llvm::MVT IntValSize = AreInts64bit ? MVT::i64 : MVT::i32;
+  const TargetRegisterClass *RC = getRegClassFor(PointerSize);
+  const TargetRegisterClass *RCi = getRegClassFor(IntValSize);
   const TargetInstrInfo *TII = Subtarget.getInstrInfo();
   DebugLoc DL = MI->getDebugLoc();
 
@@ -1420,19 +1425,19 @@
   unsigned NewVal  = MI->getOperand(3).getReg();
 
   unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
-  unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
-  unsigned Mask = RegInfo.createVirtualRegister(RC);
-  unsigned Mask2 = RegInfo.createVirtualRegister(RC);
-  unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
-  unsigned OldVal = RegInfo.createVirtualRegister(RC);
-  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
-  unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
-  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
+  unsigned ShiftAmt = RegInfo.createVirtualRegister(RCi);
+  unsigned Mask = RegInfo.createVirtualRegister(RCi);
+  unsigned Mask2 = RegInfo.createVirtualRegister(RCi);
+  unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RCi);
+  unsigned OldVal = RegInfo.createVirtualRegister(RCi);
+  unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RCi);
+  unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RCi);
+  unsigned MaskLSB2 = RegInfo.createVirtualRegister(RCi);
   unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
-  unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
-  unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
-  unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
-  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
+  unsigned MaskUpper = RegInfo.createVirtualRegister(RCi);
+  unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RCi);
+  unsigned MaskedNewVal = RegInfo.createVirtualRegister(RCi);
+  unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RCi);
   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
   unsigned SrlRes = RegInfo.createVirtualRegister(RC);
   unsigned Success = RegInfo.createVirtualRegister(RC);
@@ -1475,32 +1480,36 @@
   //    andi    maskednewval,newval,255
   //    sll     shiftednewval,maskednewval,shiftamt
   int64_t MaskImm = (Size == 1) ? 255 : 65535;
-  BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
-    .addReg(Mips::ZERO).addImm(-4);
-  BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
+    .addReg(ABI.GetZeroReg()).addImm(-4);
+  BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
     .addReg(Ptr).addReg(MaskLSB2);
-  BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
+  BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::ANDi64 : Mips::ANDi), PtrLSB2)
+    .addReg(Ptr).addImm(3);
   if (Subtarget.isLittle()) {
-    BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
+    BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DSLL : Mips::SLL), ShiftAmt)
+            .addReg(PtrLSB2).addImm(3);
   } else {
-    unsigned Off = RegInfo.createVirtualRegister(RC);
-    BuildMI(BB, DL, TII->get(Mips::XORi), Off)
+    unsigned Off = RegInfo.createVirtualRegister(RCi);
+    BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::XORi64 : Mips::XORi), Off)
       .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
-    BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
+    BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::DSLL : Mips::SLL), ShiftAmt)
+            .addReg(Off).addImm(3);
   }
-  BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
-    .addReg(Mips::ZERO).addImm(MaskImm);
-  BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::ORi64 : Mips::ORi), MaskUpper)
+    .addReg(ABI.GetZeroReg()).addImm(MaskImm);
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::DSLLV : Mips::SLLV), Mask)
     .addReg(MaskUpper).addReg(ShiftAmt);
-  BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
-  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
-    .addReg(CmpVal).addImm(MaskImm);
-  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
-    .addReg(MaskedCmpVal).addReg(ShiftAmt);
-  BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
-    .addReg(NewVal).addImm(MaskImm);
-  BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
-    .addReg(MaskedNewVal).addReg(ShiftAmt);
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::NOR64 : Mips::NOR), Mask2)
+    .addReg(ABI.GetZeroReg()).addReg(Mask);
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::ANDi64 : Mips::ANDi),
+    MaskedCmpVal).addReg(CmpVal).addImm(MaskImm);
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::DSLLV : Mips::SLLV), 
+    ShiftedCmpVal).addReg(MaskedCmpVal).addReg(ShiftAmt);
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::ANDi64 : Mips::ANDi),
+    MaskedNewVal).addReg(NewVal).addImm(MaskImm);
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::DSLLV : Mips::SLLV), 
+    ShiftedNewVal).addReg(MaskedNewVal).addReg(ShiftAmt);
 
   //  loop1MBB:
   //    ll      oldval,0(alginedaddr)
@@ -1509,9 +1518,9 @@
   BB = loop1MBB;
   unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
   BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
-  BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
-    .addReg(OldVal).addReg(Mask);
-  BuildMI(BB, DL, TII->get(Mips::BNE))
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::AND64 : Mips::AND),
+          MaskedOldVal0).addReg(OldVal).addReg(Mask);
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::BNE64 : Mips::BNE))
     .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
 
   //  loop2MBB:
@@ -1520,22 +1529,22 @@
   //    sc      success,storeval,0(alignedaddr)
   //    beq     success,$0,loop1MBB
   BB = loop2MBB;
-  BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
-    .addReg(OldVal).addReg(Mask2);
-  BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::AND64 : Mips::AND),
+          MaskedOldVal1).addReg(OldVal).addReg(Mask2);
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::OR64 : Mips::OR), StoreVal)
     .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
   unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
   BuildMI(BB, DL, TII->get(SC), Success)
       .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
-  BuildMI(BB, DL, TII->get(Mips::BEQ))
-      .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::BEQ64 : Mips::BEQ))
+      .addReg(Success).addReg(ABI.GetZeroReg()).addMBB(loop1MBB);
 
   //  sinkMBB:
   //    srl     srlres,maskedoldval0,shiftamt
   //    sign_extend dest,srlres
   BB = sinkMBB;
 
-  BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
+  BuildMI(BB, DL, TII->get(AreInts64bit ? Mips::DSRLV : Mips::SRLV), SrlRes)
       .addReg(MaskedOldVal0).addReg(ShiftAmt);
   BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
 
Index: test/CodeGen/Mips/atomicCmpSwapPW.ll
===================================================================
--- test/CodeGen/Mips/atomicCmpSwapPW.ll
+++ test/CodeGen/Mips/atomicCmpSwapPW.ll
@@ -0,0 +1,18 @@
+; RUN: llc  -O0 -march=mips64el -mcpu=mips64r2 < %s -filetype=asm -o - \
+; RUN:   | FileCheck %s -implicit-check-not=lw
+
+@_ZZ14InitializeOncevE5array = global [1 x i32*] zeroinitializer, align 8
+@_ZGVZ14InitializeOncevE5array = global i64 0, align 8
+
+define void @_Z14InitializeOncev()
+#0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
+entry:
+  %exn.slot = alloca i8*
+  %ehselector.slot = alloca i32
+  %0 = load atomic i8,
+     i8* bitcast (i64* @_ZGVZ14InitializeOncevE5array to i8*) acquire, align 8
+  ret void
+}
+
+
+declare i32 @__gxx_personality_v0(...)
\ No newline at end of file