Index: lib/Target/Mips/MipsISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsISelLowering.cpp +++ lib/Target/Mips/MipsISelLowering.cpp @@ -1407,7 +1412,7 @@ MachineFunction *MF = BB->getParent(); MachineRegisterInfo &RegInfo = MF->getRegInfo(); - const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + const TargetRegisterClass *RC = Subtarget.isABI_N64() ? getRegClassFor(MVT::i64) : getRegClassFor(MVT::i32); const TargetInstrInfo *TII = Subtarget.getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); Index: test/CodeGen/Mips/at1.ll =================================================================== --- test/CodeGen/Mips/at1.ll +++ test/CodeGen/Mips/at1.ll @@ -0,0 +1,16 @@ +; RUN: llc %s -march=mips64el -mcpu=mips64r2 < %s -filetype=obj -o - \ +; RUN: | llvm-objdump -mattr=+mips64r2 -d - | FileCheck %s -implicit-check-not=sw + +@_ZZ14InitializeOncevE5array = global [1 x i32*] zeroinitializer, align 8 +@_ZGVZ14InitializeOncevE5array = global i64 0, align 8 + +define void @_Z14InitializeOncev() #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +entry: + %exn.slot = alloca i8* + %ehselector.slot = alloca i32 + %0 = load atomic i8, i8* bitcast (i64* @_ZGVZ14InitializeOncevE5array to i8*) acquire, align 8 + ret void +} + + +declare i32 @__gxx_personality_v0(...)