diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td @@ -1274,6 +1274,108 @@ } } // end let EncoderMethod/DecoderMethod +// SME2 strided multi-vector operands + +// ZStridedPairs +// +// A group of two Z vectors with strided numbering consisting of: +// Zn+0.T and Zn+8.T +// where n is in the range 0 to 7 and 16 to 23 inclusive, and T is one of B, H, +// S, or D. + +// Z0_Z8, Z1_Z9, Z2_Z10, Z3_Z11, Z4_Z12, Z5_Z13, Z6_Z14, Z7_Z15 +def ZStridedPairsLo : RegisterTuples<[zsub0, zsub1], [ + (trunc (rotl ZPR, 0), 8), (trunc (rotl ZPR, 8), 8) +]>; + +// Z16_Z24, Z17_Z25, Z18_Z26, Z19_Z27, Z20_Z28, Z21_Z29, Z22_Z30, Z23_Z31 +def ZStridedPairsHi : RegisterTuples<[zsub0, zsub1], [ + (trunc (rotl ZPR, 16), 8), (trunc (rotl ZPR, 24), 8) +]>; + +// ZStridedQuads +// +// A group of four Z vectors with strided numbering consisting of: +// Zn+0.T, Zn+4.T, Zn+8.T and Zn+12.T +// where n is in the range 0 to 3 and 16 to 19 inclusive, and T is one of B, H, +// S, or D. + +// Z0_Z4_Z8_Z12, Z1_Z5_Z9_Z13, Z2_Z6_Z10_Z14, Z3_Z7_Z11_Z15 +def ZStridedQuadsLo : RegisterTuples<[zsub0, zsub1, zsub2, zsub3], [ + (trunc (rotl ZPR, 0), 4), (trunc (rotl ZPR, 4), 4), + (trunc (rotl ZPR, 8), 4), (trunc (rotl ZPR, 12), 4) +]>; +// Z16_Z20_Z24_Z28, Z17_Z21_Z25_Z29, Z18_Z22_Z26_Z30, Z19_Z23_Z27_Z31 +def ZStridedQuadsHi : RegisterTuples<[zsub0, zsub1, zsub2, zsub3], [ + (trunc (rotl ZPR, 16), 4), (trunc (rotl ZPR, 20), 4), + (trunc (rotl ZPR, 24), 4), (trunc (rotl ZPR, 28), 4) +]>; + +def ZPR2Strided : RegisterClass<"AArch64", [untyped], 256, + (add ZStridedPairsLo, ZStridedPairsHi)> { + let Size = 256; +} +def ZPR4Strided : RegisterClass<"AArch64", [untyped], 512, + (add ZStridedQuadsLo, ZStridedQuadsHi)> { + let Size = 512; +} + + +class ZPRVectorListStrided + : ZPRVectorList { + let Name = "SVEVectorListStrided" # NumRegs # "x" # ElementWidth; + let DiagnosticType = "Invalid" # Name; + let PredicateMethod = "isTypedVectorListStrided"; + let RenderMethod = "addStridedVectorListOperands<" # NumRegs # ">"; +} + +let EncoderMethod = "EncodeZPR2StridedRegisterClass", + DecoderMethod = "DecodeZPR2StridedRegisterClass" in { + def ZZ_b_strided + : RegisterOperand"> { + let ParserMatchClass = ZPRVectorListStrided<8, 2, 8>; + } + + def ZZ_h_strided + : RegisterOperand"> { + let ParserMatchClass = ZPRVectorListStrided<16, 2, 8>; + } + + def ZZ_s_strided + : RegisterOperand"> { + let ParserMatchClass = ZPRVectorListStrided<32, 2, 8>; + } + + def ZZ_d_strided + : RegisterOperand"> { + let ParserMatchClass = ZPRVectorListStrided<64, 2, 8>; + } +} + +let EncoderMethod = "EncodeZPR4StridedRegisterClass", + DecoderMethod = "DecodeZPR4StridedRegisterClass" in { + def ZZZZ_b_strided + : RegisterOperand"> { + let ParserMatchClass = ZPRVectorListStrided<8, 4, 4>; + } + + def ZZZZ_h_strided + : RegisterOperand"> { + let ParserMatchClass = ZPRVectorListStrided<16, 4, 4>; + } + + def ZZZZ_s_strided + : RegisterOperand"> { + let ParserMatchClass = ZPRVectorListStrided<32, 4, 4>; + } + + def ZZZZ_d_strided + : RegisterOperand"> { + let ParserMatchClass = ZPRVectorListStrided<64, 4, 4>; + } +} + class ZPRExtendAsmOperand : AsmOperandClass { let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -619,6 +619,77 @@ defm SQRSHRN_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshrn", 0b100>; defm UQRSHRN_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"uqrshrn", 0b101>; defm SQRSHRUN_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshrun", 0b110>; + +defm SEL_VG2_2ZP2Z2Z: sme2_sel_vector_vg2<"sel">; +defm SEL_VG4_4ZP4Z4Z: sme2_sel_vector_vg4<"sel">; + +def LD1B_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b00, 0b0, ZZ_b_strided, GPR64shifted8, "ld1b">; +def LD1B_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b00, 0b0, ZZZZ_b_strided, GPR64shifted8, "ld1b">; +defm LD1B_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b00, 0b0, ZZ_b_strided, simm4s2, "ld1b">; +defm LD1B_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b00, 0b0, ZZZZ_b_strided, simm4s4, "ld1b">; +def LD1H_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b01, 0b0, ZZ_h_strided, GPR64shifted16, "ld1h">; +def LD1H_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b01, 0b0, ZZZZ_h_strided, GPR64shifted16, "ld1h">; +defm LD1H_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b01, 0b0, ZZ_h_strided, simm4s2, "ld1h">; +defm LD1H_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b01, 0b0, ZZZZ_h_strided, simm4s4, "ld1h">; +def LD1W_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b10, 0b0, ZZ_s_strided, GPR64shifted32, "ld1w">; +def LD1W_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b10, 0b0, ZZZZ_s_strided, GPR64shifted32, "ld1w">; +defm LD1W_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b10, 0b0, ZZ_s_strided, simm4s2, "ld1w">; +defm LD1W_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b10, 0b0, ZZZZ_s_strided, simm4s4, "ld1w">; +def LD1D_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b11, 0b0, ZZ_d_strided, GPR64shifted64, "ld1d">; +def LD1D_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b11, 0b0, ZZZZ_d_strided, GPR64shifted64, "ld1d">; +defm LD1D_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b11, 0b0, ZZ_d_strided, simm4s2, "ld1d">; +defm LD1D_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b11, 0b0, ZZZZ_d_strided, simm4s4, "ld1d">; + +def LDNT1B_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b00, 0b1, ZZ_b_strided, GPR64shifted8, "ldnt1b">; +def LDNT1B_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b00, 0b1, ZZZZ_b_strided, GPR64shifted8, "ldnt1b">; +defm LDNT1B_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b00, 0b1, ZZ_b_strided, simm4s2, "ldnt1b">; +defm LDNT1B_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b00, 0b1, ZZZZ_b_strided, simm4s4, "ldnt1b">; +def LDNT1H_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b01, 0b1, ZZ_h_strided, GPR64shifted16, "ldnt1h">; +def LDNT1H_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b01, 0b1, ZZZZ_h_strided, GPR64shifted16, "ldnt1h">; +defm LDNT1H_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b01, 0b1, ZZ_h_strided, simm4s2, "ldnt1h">; +defm LDNT1H_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b01, 0b1, ZZZZ_h_strided, simm4s4, "ldnt1h">; +def LDNT1W_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b10, 0b1, ZZ_s_strided, GPR64shifted32, "ldnt1w">; +def LDNT1W_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b10, 0b1, ZZZZ_s_strided, GPR64shifted32, "ldnt1w">; +defm LDNT1W_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b10, 0b1, ZZ_s_strided, simm4s2, "ldnt1w">; +defm LDNT1W_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b10, 0b1, ZZZZ_s_strided, simm4s4, "ldnt1w">; +def LDNT1D_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b11, 0b1, ZZ_d_strided, GPR64shifted64, "ldnt1d">; +def LDNT1D_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b11, 0b1, ZZZZ_d_strided, GPR64shifted64, "ldnt1d">; +defm LDNT1D_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b11, 0b1, ZZ_d_strided, simm4s2, "ldnt1d">; +defm LDNT1D_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b11, 0b1, ZZZZ_d_strided, simm4s4, "ldnt1d">; + +def ST1B_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b00, 0b0, ZZ_b_strided, GPR64shifted8, "st1b">; +def ST1B_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b00, 0b0, ZZZZ_b_strided, GPR64shifted8, "st1b">; +defm ST1B_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b00, 0b0, ZZ_b_strided, simm4s2, "st1b">; +defm ST1B_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b00, 0b0, ZZZZ_b_strided, simm4s4, "st1b">; +def ST1H_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b01, 0b0, ZZ_h_strided, GPR64shifted16, "st1h">; +def ST1H_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b01, 0b0, ZZZZ_h_strided, GPR64shifted16, "st1h">; +defm ST1H_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b01, 0b0, ZZ_h_strided, simm4s2, "st1h">; +defm ST1H_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b01, 0b0, ZZZZ_h_strided, simm4s4, "st1h">; +def ST1W_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b10, 0b0, ZZ_s_strided, GPR64shifted32, "st1w">; +def ST1W_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b10, 0b0, ZZZZ_s_strided, GPR64shifted32, "st1w">; +defm ST1W_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b10, 0b0, ZZ_s_strided, simm4s2, "st1w">; +defm ST1W_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b10, 0b0, ZZZZ_s_strided, simm4s4, "st1w">; +def ST1D_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b11, 0b0, ZZ_d_strided, GPR64shifted64, "st1d">; +def ST1D_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b11, 0b0, ZZZZ_d_strided, GPR64shifted64, "st1d">; +defm ST1D_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b11, 0b0, ZZ_d_strided, simm4s2, "st1d">; +defm ST1D_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b11, 0b0, ZZZZ_d_strided, simm4s4, "st1d">; + +def STNT1B_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b00, 0b1, ZZ_b_strided, GPR64shifted8, "stnt1b">; +def STNT1B_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b00, 0b1, ZZZZ_b_strided, GPR64shifted8, "stnt1b">; +defm STNT1B_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b00, 0b1, ZZ_b_strided, simm4s2, "stnt1b">; +defm STNT1B_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b00, 0b1, ZZZZ_b_strided, simm4s4, "stnt1b">; +def STNT1H_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b01, 0b1, ZZ_h_strided, GPR64shifted16, "stnt1h">; +def STNT1H_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b01, 0b1, ZZZZ_h_strided, GPR64shifted16, "stnt1h">; +defm STNT1H_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b01, 0b1, ZZ_h_strided, simm4s2, "stnt1h">; +defm STNT1H_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b01, 0b1, ZZZZ_h_strided, simm4s4, "stnt1h">; +def STNT1W_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b10, 0b1, ZZ_s_strided, GPR64shifted32, "stnt1w">; +def STNT1W_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b10, 0b1, ZZZZ_s_strided, GPR64shifted32, "stnt1w">; +defm STNT1W_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b10, 0b1, ZZ_s_strided, simm4s2, "stnt1w">; +defm STNT1W_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b10, 0b1, ZZZZ_s_strided, simm4s4, "stnt1w">; +def STNT1D_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b11, 0b1, ZZ_d_strided, GPR64shifted64, "stnt1d">; +def STNT1D_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b11, 0b1, ZZZZ_d_strided, GPR64shifted64, "stnt1d">; +defm STNT1D_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b11, 0b1, ZZ_d_strided, simm4s2, "stnt1d">; +defm STNT1D_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b11, 0b1, ZZZZ_d_strided, simm4s4, "stnt1d">; } let Predicates = [HasSME2, HasSMEI16I64] in { diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -407,6 +407,7 @@ struct VectorListOp { unsigned RegNum; unsigned Count; + unsigned Stride; unsigned NumElements; unsigned ElementWidth; RegKind RegisterKind; @@ -686,6 +687,11 @@ return VectorList.Count; } + unsigned getVectorListStride() const { + assert(Kind == k_VectorList && "Invalid access!"); + return VectorList.Stride; + } + int getVectorIndex() const { assert(Kind == k_VectorIndex && "Invalid access!"); return VectorIndex.Val; @@ -1380,7 +1386,7 @@ } template + unsigned ElementWidth, unsigned Stride = 1> bool isTypedVectorList() const { if (Kind != k_VectorList) return false; @@ -1390,6 +1396,8 @@ return false; if (VectorList.ElementWidth != ElementWidth) return false; + if (VectorList.Stride != Stride) + return false; return VectorList.NumElements == NumElements; } @@ -1405,6 +1413,20 @@ return DiagnosticPredicateTy::Match; } + template + DiagnosticPredicate isTypedVectorListStrided() const { + bool Res = isTypedVectorList(); + if (!Res) + return DiagnosticPredicateTy::NoMatch; + if ((VectorList.RegNum < (AArch64::Z0 + Stride)) || + ((VectorList.RegNum >= AArch64::Z16) && + (VectorList.RegNum < (AArch64::Z16 + Stride)))) + return DiagnosticPredicateTy::Match; + return DiagnosticPredicateTy::NoMatch; + } + template DiagnosticPredicate isVectorIndex() const { if (Kind != k_VectorIndex) @@ -1760,6 +1782,43 @@ FirstRegs[(unsigned)RegTy][0])); } + template + void addStridedVectorListOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + assert((NumRegs == 2 || NumRegs == 4) && " NumRegs must be 2 or 4"); + + switch (NumRegs) { + case 2: + if (getVectorListStart() < AArch64::Z16) { + assert((getVectorListStart() < AArch64::Z8) && + (getVectorListStart() >= AArch64::Z0) && "Invalid Register"); + Inst.addOperand(MCOperand::createReg( + AArch64::Z0_Z8 + getVectorListStart() - AArch64::Z0)); + } else { + assert((getVectorListStart() < AArch64::Z24) && + (getVectorListStart() >= AArch64::Z16) && "Invalid Register"); + Inst.addOperand(MCOperand::createReg( + AArch64::Z16_Z24 + getVectorListStart() - AArch64::Z16)); + } + break; + case 4: + if (getVectorListStart() < AArch64::Z16) { + assert((getVectorListStart() < AArch64::Z4) && + (getVectorListStart() >= AArch64::Z0) && "Invalid Register"); + Inst.addOperand(MCOperand::createReg( + AArch64::Z0_Z4_Z8_Z12 + getVectorListStart() - AArch64::Z0)); + } else { + assert((getVectorListStart() < AArch64::Z20) && + (getVectorListStart() >= AArch64::Z16) && "Invalid Register"); + Inst.addOperand(MCOperand::createReg( + AArch64::Z16_Z20_Z24_Z28 + getVectorListStart() - AArch64::Z16)); + } + break; + default: + llvm_unreachable("Unsupported number of registers for strided vec list"); + } + } + void addMatrixTileListOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); unsigned RegMask = getMatrixTileListRegMask(); @@ -2120,12 +2179,13 @@ } static std::unique_ptr - CreateVectorList(unsigned RegNum, unsigned Count, unsigned NumElements, - unsigned ElementWidth, RegKind RegisterKind, SMLoc S, SMLoc E, - MCContext &Ctx) { + CreateVectorList(unsigned RegNum, unsigned Count, unsigned Stride, + unsigned NumElements, unsigned ElementWidth, + RegKind RegisterKind, SMLoc S, SMLoc E, MCContext &Ctx) { auto Op = std::make_unique(k_VectorList, Ctx); Op->VectorList.RegNum = RegNum; Op->VectorList.Count = Count; + Op->VectorList.Stride = Stride; Op->VectorList.NumElements = NumElements; Op->VectorList.ElementWidth = ElementWidth; Op->VectorList.RegisterKind = RegisterKind; @@ -2389,7 +2449,7 @@ OS << ""; break; } @@ -4235,6 +4295,7 @@ int64_t PrevReg = FirstReg; unsigned Count = 1; + int Stride = 1; if (parseOptionalToken(AsmToken::Minus)) { SMLoc Loc = getLoc(); StringRef NextKind; @@ -4261,6 +4322,7 @@ Count += Space; } else { + bool HasCalculatedStride = false; while (parseOptionalToken(AsmToken::Comma)) { SMLoc Loc = getLoc(); StringRef NextKind; @@ -4275,11 +4337,18 @@ return MatchOperand_ParseFail; } - // Registers must be incremental (with wraparound at 31) - if (getContext().getRegisterInfo()->getEncodingValue(Reg) != - (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % - NumRegs) { - Error(Loc, "registers must be sequential"); + unsigned RegVal = getContext().getRegisterInfo()->getEncodingValue(Reg); + unsigned PrevRegVal = + getContext().getRegisterInfo()->getEncodingValue(PrevReg); + if (!HasCalculatedStride) { + Stride = (PrevRegVal < RegVal) ? (RegVal - PrevRegVal) + : (RegVal + NumRegs - PrevRegVal); + HasCalculatedStride = true; + } + + // Register must be incremental (with a wraparound at last register). + if (Stride == 0 || RegVal != ((PrevRegVal + Stride) % NumRegs)) { + Error(Loc, "registers must have the same sequential stride"); return MatchOperand_ParseFail; } @@ -4304,8 +4373,8 @@ } Operands.push_back(AArch64Operand::CreateVectorList( - FirstReg, Count, NumElements, ElementWidth, VectorKind, S, getLoc(), - getContext())); + FirstReg, Count, Stride, NumElements, ElementWidth, VectorKind, S, + getLoc(), getContext())); return MatchOperand_Success; } @@ -4765,7 +4834,8 @@ if (AOp1.isVectorList() && AOp2.isVectorList()) return AOp1.getVectorListCount() == AOp2.getVectorListCount() && - AOp1.getVectorListStart() == AOp2.getVectorListStart(); + AOp1.getVectorListStart() == AOp2.getVectorListStart() && + AOp1.getVectorListStride() == AOp2.getVectorListStride(); if (!AOp1.isReg() || !AOp2.isReg()) return false; @@ -5840,6 +5910,24 @@ "and with matching element types"); case Match_InvalidLookupTable: return Error(Loc, "Invalid lookup table, expected zt0"); + case Match_InvalidSVEVectorListStrided2x8: + case Match_InvalidSVEVectorListStrided2x16: + case Match_InvalidSVEVectorListStrided2x32: + case Match_InvalidSVEVectorListStrided2x64: + return Error( + Loc, + "Invalid vector list, expected list with each SVE vector in the list " + "8 registers apart, and the first register in the range [z0, z7] or " + "[z16, z23] and with correct element type"); + case Match_InvalidSVEVectorListStrided4x8: + case Match_InvalidSVEVectorListStrided4x16: + case Match_InvalidSVEVectorListStrided4x32: + case Match_InvalidSVEVectorListStrided4x64: + return Error( + Loc, + "Invalid vector list, expected list with each SVE vector in the list " + "4 registers apart, and the first register in the range [z0, z3] or " + "[z16, z19] and with correct element type"); default: llvm_unreachable("unexpected error code!"); } @@ -6411,6 +6499,14 @@ case Match_InvalidSVEVectorListMul4x16: case Match_InvalidSVEVectorListMul4x32: case Match_InvalidSVEVectorListMul4x64: + case Match_InvalidSVEVectorListStrided2x8: + case Match_InvalidSVEVectorListStrided2x16: + case Match_InvalidSVEVectorListStrided2x32: + case Match_InvalidSVEVectorListStrided2x64: + case Match_InvalidSVEVectorListStrided4x8: + case Match_InvalidSVEVectorListStrided4x16: + case Match_InvalidSVEVectorListStrided4x32: + case Match_InvalidSVEVectorListStrided4x64: case Match_MSR: case Match_MRS: { if (ErrorInfo >= Operands.size()) diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -123,6 +123,12 @@ static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); +static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder); template static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -650,6 +656,30 @@ return Success; } +static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 15) + return Fail; + unsigned Register = + AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister( + RegNo); + Inst.addOperand(MCOperand::createReg(Register)); + return Success; +} + +static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 7) + return Fail; + unsigned Register = + AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister( + RegNo); + Inst.addOperand(MCOperand::createReg(Register)); + return Success; +} + static DecodeStatus DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask, uint64_t Address, diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp @@ -1495,7 +1495,8 @@ if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) || MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) || - MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg)) + MRI.getRegClass(AArch64::PPR2RegClassID).contains(Reg) || + MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg)) NumRegs = 2; else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) || @@ -1503,9 +1504,16 @@ NumRegs = 3; else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) || - MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg)) + MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg) || + MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg)) NumRegs = 4; + unsigned Stride = 1; + if (MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg)) + Stride = 8; + else if (MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg)) + Stride = 4; + // Now forget about the list and find out what the first register is. if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) Reg = FirstReg; @@ -1526,7 +1534,7 @@ if ((MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) || MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) && - NumRegs > 1 && + NumRegs > 1 && Stride == 1 && // Do not print the range when the last register is lower than the first. // Because it is a wrap-around register. Reg < getNextVectorRegister(Reg, NumRegs - 1)) { @@ -1540,7 +1548,8 @@ O << LayoutSuffix; } } else { - for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) { + for (unsigned i = 0; i < NumRegs; + ++i, Reg = getNextVectorRegister(Reg, Stride)) { // wrap-around sve register if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) || MRI.getRegClass(AArch64::PPRRegClassID).contains(Reg)) diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp @@ -193,6 +193,13 @@ SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + uint32_t EncodeZPR2StridedRegisterClass(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + uint32_t EncodeZPR4StridedRegisterClass(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + uint32_t EncodeMatrixTileListRegisterClass(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; @@ -544,6 +551,26 @@ return RegOpnd - AArch64::P8; } +uint32_t AArch64MCCodeEmitter::EncodeZPR2StridedRegisterClass( + const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + auto RegOpnd = MI.getOperand(OpIdx).getReg(); + unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); + unsigned T = (RegVal & 0x10) >> 1; + unsigned Zt = RegVal & 0x7; + return T | Zt; +} + +uint32_t AArch64MCCodeEmitter::EncodeZPR4StridedRegisterClass( + const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + auto RegOpnd = MI.getOperand(OpIdx).getReg(); + unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); + unsigned T = (RegVal & 0x10) >> 2; + unsigned Zt = RegVal & 0x3; + return T | Zt; +} + uint32_t AArch64MCCodeEmitter::EncodeMatrixTileListRegisterClass( const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -3624,3 +3624,276 @@ let Inst{20-16} = imm{4-0}; } } + +//===----------------------------------------------------------------------===// +// SME2 Multi-vector - SVE Select +class sme2_sel_vector_vg24 sz, bits<4> op, RegisterOperand vector_ty, + string mnemonic> + : I<(outs vector_ty:$Zd), + (ins PNRAny_p8to15:$PNg, vector_ty:$Zn, vector_ty:$Zm), + mnemonic, "\t$Zd, $PNg, $Zn, $Zm", + "", []>, Sched<[]> { + bits<3> PNg; + let Inst{31-24} = 0b11000001; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{17-16} = op{3-2}; + let Inst{15-13} = 0b100; + let Inst{12-10} = PNg; + let Inst{6} = op{1}; + let Inst{5} = 0b0; + let Inst{1} = op{0}; + let Inst{0} = 0b0; +} + +class sme2_sel_vector_vg2 sz, RegisterOperand vector_ty, + string mnemonic> + : sme2_sel_vector_vg24 { + bits<4> Zm; + bits<4> Zn; + bits<4> Zd; + let Inst{20-17} = Zm; + let Inst{9-6} = Zn; + let Inst{4-1} = Zd; +} + +multiclass sme2_sel_vector_vg2{ + def _B : sme2_sel_vector_vg2<0b00, ZZ_b_mul_r, mnemonic>; + def _H : sme2_sel_vector_vg2<0b01, ZZ_h_mul_r, mnemonic>; + def _S : sme2_sel_vector_vg2<0b10, ZZ_s_mul_r, mnemonic>; + def _D : sme2_sel_vector_vg2<0b11, ZZ_d_mul_r, mnemonic>; +} +class sme2_sel_vector_vg4 sz, RegisterOperand vector_ty, + string mnemonic> + : sme2_sel_vector_vg24 { + bits<3> Zm; + bits<3> Zn; + bits<3> Zd; + let Inst{20-18} = Zm; + let Inst{9-7} = Zn; + let Inst{4-2} = Zd; +} +multiclass sme2_sel_vector_vg4 { + def _B : sme2_sel_vector_vg4<0b00, ZZZZ_b_mul_r, mnemonic>; + def _H : sme2_sel_vector_vg4<0b01, ZZZZ_h_mul_r, mnemonic>; + def _S : sme2_sel_vector_vg4<0b10, ZZZZ_s_mul_r, mnemonic>; + def _D : sme2_sel_vector_vg4<0b11, ZZZZ_d_mul_r, mnemonic>; +} + +//===----------------------------------------------------------------------===// +// Non contiguous Load and Store + +class sme2_ld_vector_vg2_multi_scalar_scalar msz, bit n, + RegisterOperand multi_vector_ty, + RegisterOperand gpr_ty, + string mnemonic> + : I<(outs multi_vector_ty:$Zt), + (ins PNRAny_p8to15:$PNg, GPR64sp:$Rn, gpr_ty:$Rm), + mnemonic, "\t$Zt, $PNg/z, [$Rn, $Rm]", + "", []>, Sched<[]> { + bits<5> Rm; + bits<3> PNg; + bits<5> Rn; + bits<4> Zt; + let Inst{31-21} = 0b10100001000; + let Inst{20-16} = Rm; + let Inst{15} = 0b0; + let Inst{14-13} = msz; + let Inst{12-10} = PNg; + let Inst{9-5} = Rn; + let Inst{4} = Zt{3}; + let Inst{3} = n; + let Inst{2-0} = Zt{2-0}; + + let mayLoad = 1; +} + +class sme2_ld_vector_vg4_multi_scalar_scalar msz, bit n, + RegisterOperand multi_vector_ty, + RegisterOperand gpr_ty, + string mnemonic> + : I<(outs multi_vector_ty:$Zt), + (ins PNRAny_p8to15:$PNg, GPR64sp:$Rn, gpr_ty:$Rm), + mnemonic, "\t$Zt, $PNg/z, [$Rn, $Rm]", + "", []>, Sched<[]> { + bits<5> Rm; + bits<3> PNg; + bits<5> Rn; + bits<3> Zt; + let Inst{31-21} = 0b10100001000; + let Inst{20-16} = Rm; + let Inst{15} = 0b1; + let Inst{14-13} = msz; + let Inst{12-10} = PNg; + let Inst{9-5} = Rn; + let Inst{4} = Zt{2}; + let Inst{3} = n; + let Inst{2} = 0b0; + let Inst{1-0} = Zt{1-0}; + + let mayLoad = 1; +} + +class sme2_ld_vector_vg24_multi_scalar_immediate msz, bit n, bits<2> op, + RegisterOperand multi_vector_ty, + Operand index_ty, + string mnemonic> + : I<(outs multi_vector_ty:$Zt), + (ins PNRAny_p8to15:$PNg, GPR64sp:$Rn, index_ty:$imm4), + mnemonic, "\t$Zt, $PNg/z, [$Rn, $imm4, mul vl]", + "", []>, Sched<[]> { + bits<4> imm4; + bits<3> PNg; + bits<5> Rn; + let Inst{31-20} = 0b101000010100; + let Inst{19-16} = imm4; + let Inst{15} = op{1}; + let Inst{14-13} = msz; + let Inst{12-10} = PNg; + let Inst{9-5} = Rn; + let Inst{3} = n; + let Inst{2} = op{0}; + + let mayLoad = 1; +} + +multiclass sme2_ld_vector_vg2_multi_scalar_immediate msz, bit n, + RegisterOperand multi_vector_ty, + Operand index_ty, + string mnemonic>{ + def NAME : sme2_ld_vector_vg24_multi_scalar_immediate { + bits<4> Zt; + let Inst{4} = Zt{3}; + let Inst{2-0} = Zt{2-0}; + } + + def : InstAlias(NAME) multi_vector_ty:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0), 1>; +} + +multiclass sme2_ld_vector_vg4_multi_scalar_immediate msz, bit n, + RegisterOperand multi_vector_ty, + Operand index_ty, + string mnemonic> { + def NAME : sme2_ld_vector_vg24_multi_scalar_immediate { + bits<3> Zt; + let Inst{4} = Zt{2}; + let Inst{1-0} = Zt{1-0}; + } + + def : InstAlias(NAME) multi_vector_ty:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, 0), 1>; +} + +//===----------------------------------------------------------------------===// +// SME2 Non-Contiguous Store +class sme2_st_vector_vg2_multi_scalar_scalar msz, bit n, + RegisterOperand multi_vector_ty, + RegisterOperand gpr_ty, + string mnemonic> + : I<(outs ), + (ins multi_vector_ty:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, gpr_ty:$Rm), + mnemonic, "\t$Zt, $PNg, [$Rn, $Rm]", + "", []>, Sched<[]> { + bits<5> Rm; + bits<3> PNg; + bits<5> Rn; + bits<4> Zt; + let Inst{31-21} = 0b10100001001; + let Inst{20-16} = Rm; + let Inst{15} = 0b0; + let Inst{14-13} = msz; + let Inst{12-10} = PNg; + let Inst{9-5} = Rn; + let Inst{4} = Zt{3}; + let Inst{3} = n; + let Inst{2-0} = Zt{2-0}; + + let mayStore = 1; +} + +class sme2_st_vector_vg4_multi_scalar_scalar msz, bit n, + RegisterOperand multi_vector_ty, + RegisterOperand gpr_ty, + string mnemonic> + : I<(outs ), + (ins multi_vector_ty:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, gpr_ty:$Rm), + mnemonic, "\t$Zt, $PNg, [$Rn, $Rm]", + "", []>, Sched<[]> { + bits<5> Rm; + bits<3> PNg; + bits<5> Rn; + bits<3> Zt; + let Inst{31-21} = 0b10100001001; + let Inst{20-16} = Rm; + let Inst{15} = 0b1; + let Inst{14-13} = msz; + let Inst{12-10} = PNg; + let Inst{9-5} = Rn; + let Inst{4} = Zt{2}; + let Inst{3} = n; + let Inst{2} = 0b0; + let Inst{1-0} = Zt{1-0}; + + let mayStore = 1; +} + +class sme2_st_vector_vg24_multi_scalar_immediate msz, bit n, bits<2> op, + RegisterOperand multi_vector_ty, + Operand index_ty, + string mnemonic> + : I<(outs ), + (ins multi_vector_ty:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn, index_ty:$imm4), + mnemonic, "\t$Zt, $PNg, [$Rn, $imm4, mul vl]", + "", []>, Sched<[]> { + bits<4> imm4; + bits<3> PNg; + bits<5> Rn; + let Inst{31-20} = 0b101000010110; + let Inst{19-16} = imm4; + let Inst{15} = op{1}; + let Inst{14-13} = msz; + let Inst{12-10} = PNg; + let Inst{9-5} = Rn; + let Inst{3} = n; + let Inst{2} = op{0}; + + let mayStore = 1; +} + + +multiclass sme2_st_vector_vg2_multi_scalar_immediate msz, bit n, + RegisterOperand multi_vector_ty, + Operand index_ty, + string mnemonic> { + def NAME: sme2_st_vector_vg24_multi_scalar_immediate { + bits<4> Zt; + let Inst{4} = Zt{3}; + let Inst{2-0} = Zt{2-0}; + } + + def : InstAlias(NAME) multi_vector_ty:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn,0), 1>; +} + +multiclass sme2_st_vector_vg4_multi_scalar_immediate msz, bit n, + RegisterOperand multi_vector_ty, + Operand index_ty, + string mnemonic> { + def NAME : sme2_st_vector_vg24_multi_scalar_immediate { + bits<3> Zt; + let Inst{4} = Zt{2}; + let Inst{1-0} = Zt{1-0}; + } + + def : InstAlias(NAME) multi_vector_ty:$Zt, PNRAny_p8to15:$PNg, GPR64sp:$Rn,0), 1>; +} diff --git a/llvm/test/MC/AArch64/SME2/add-diagnostics.s b/llvm/test/MC/AArch64/SME2/add-diagnostics.s --- a/llvm/test/MC/AArch64/SME2/add-diagnostics.s +++ b/llvm/test/MC/AArch64/SME2/add-diagnostics.s @@ -82,7 +82,7 @@ // Invalid vector list. add za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d} -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: add za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d} // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: @@ -120,7 +120,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: add {z0.s,z1.s}, {z0.s,z2.s}, z15.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: add {z0.s,z1.s}, {z0.s,z2.s}, z15.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/fmla-diagnostics.s b/llvm/test/MC/AArch64/SME2/fmla-diagnostics.s --- a/llvm/test/MC/AArch64/SME2/fmla-diagnostics.s +++ b/llvm/test/MC/AArch64/SME2/fmla-diagnostics.s @@ -66,7 +66,7 @@ // Invalid vector list. fmla za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d} -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fmla za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d} // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/fmls-diagnostics.s b/llvm/test/MC/AArch64/SME2/fmls-diagnostics.s --- a/llvm/test/MC/AArch64/SME2/fmls-diagnostics.s +++ b/llvm/test/MC/AArch64/SME2/fmls-diagnostics.s @@ -52,7 +52,7 @@ // Invalid vector list. fmls za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d} -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: fmls za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d} // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/ld1b.s b/llvm/test/MC/AArch64/SME2/ld1b.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/ld1b.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +ld1b {z0.b, z8.b}, pn8/z, [x0, x0] // 10100001-00000000-00000000-00000000 +// CHECK-INST: ld1b { z0.b, z8.b }, pn8/z, [x0, x0] +// CHECK-ENCODING: [0x00,0x00,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1000000 + +ld1b {z21.b, z29.b}, pn13/z, [x10, x21] // 10100001-00010101-00010101-01010101 +// CHECK-INST: ld1b { z21.b, z29.b }, pn13/z, [x10, x21] +// CHECK-ENCODING: [0x55,0x15,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1151555 + +ld1b {z23.b, z31.b}, pn11/z, [x13, x8] // 10100001-00001000-00001101-10110111 +// CHECK-INST: ld1b { z23.b, z31.b }, pn11/z, [x13, x8] +// CHECK-ENCODING: [0xb7,0x0d,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1080db7 + +ld1b {z23.b, z31.b}, pn15/z, [sp, xzr] // 10100001-00011111-00011111-11110111 +// CHECK-INST: ld1b { z23.b, z31.b }, pn15/z, [sp, xzr] +// CHECK-ENCODING: [0xf7,0x1f,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11f1ff7 + + +ld1b {z0.b, z8.b}, pn8/z, [x0] // 10100001-01000000-00000000-00000000 +// CHECK-INST: ld1b { z0.b, z8.b }, pn8/z, [x0] +// CHECK-ENCODING: [0x00,0x00,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1400000 + +ld1b {z21.b, z29.b}, pn13/z, [x10, #10, mul vl] // 10100001-01000101-00010101-01010101 +// CHECK-INST: ld1b { z21.b, z29.b }, pn13/z, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x15,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1451555 + +ld1b {z23.b, z31.b}, pn11/z, [x13, #-16, mul vl] // 10100001-01001000-00001101-10110111 +// CHECK-INST: ld1b { z23.b, z31.b }, pn11/z, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x0d,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1480db7 + +ld1b {z23.b, z31.b}, pn15/z, [sp, #-2, mul vl] // 10100001-01001111-00011111-11110111 +// CHECK-INST: ld1b { z23.b, z31.b }, pn15/z, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xf7,0x1f,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14f1ff7 + + +ld1b {z0.b, z4.b, z8.b, z12.b}, pn8/z, [x0, x0] // 10100001-00000000-10000000-00000000 +// CHECK-INST: ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x0] +// CHECK-ENCODING: [0x00,0x80,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1008000 + +ld1b {z17.b, z21.b, z25.b, z29.b}, pn13/z, [x10, x21] // 10100001-00010101-10010101-01010001 +// CHECK-INST: ld1b { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, x21] +// CHECK-ENCODING: [0x51,0x95,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1159551 + +ld1b {z19.b, z23.b, z27.b, z31.b}, pn11/z, [x13, x8] // 10100001-00001000-10001101-10110011 +// CHECK-INST: ld1b { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, x8] +// CHECK-ENCODING: [0xb3,0x8d,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1088db3 + +ld1b {z19.b, z23.b, z27.b, z31.b}, pn15/z, [sp, xzr] // 10100001-00011111-10011111-11110011 +// CHECK-INST: ld1b { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, xzr] +// CHECK-ENCODING: [0xf3,0x9f,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11f9ff3 + + +ld1b {z0.b, z4.b, z8.b, z12.b}, pn8/z, [x0] // 10100001-01000000-10000000-00000000 +// CHECK-INST: ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0] +// CHECK-ENCODING: [0x00,0x80,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1408000 + +ld1b {z17.b, z21.b, z25.b, z29.b}, pn13/z, [x10, #20, mul vl] // 10100001-01000101-10010101-01010001 +// CHECK-INST: ld1b { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, #20, mul vl] +// CHECK-ENCODING: [0x51,0x95,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1459551 + +ld1b {z19.b, z23.b, z27.b, z31.b}, pn11/z, [x13, #-32, mul vl] // 10100001-01001000-10001101-10110011 +// CHECK-INST: ld1b { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb3,0x8d,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1488db3 + +ld1b {z19.b, z23.b, z27.b, z31.b}, pn15/z, [sp, #-4, mul vl] // 10100001-01001111-10011111-11110011 +// CHECK-INST: ld1b { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xf3,0x9f,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14f9ff3 + diff --git a/llvm/test/MC/AArch64/SME2/ld1d.s b/llvm/test/MC/AArch64/SME2/ld1d.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/ld1d.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex -\ +// RUN: | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +ld1d {z0.d, z8.d}, pn8/z, [x0, x0, lsl #3] // 10100001-00000000-01100000-00000000 +// CHECK-INST: ld1d { z0.d, z8.d }, pn8/z, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x00,0x60,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1006000 + +ld1d {z21.d, z29.d}, pn13/z, [x10, x21, lsl #3] // 10100001-00010101-01110101-01010101 +// CHECK-INST: ld1d { z21.d, z29.d }, pn13/z, [x10, x21, lsl #3] +// CHECK-ENCODING: [0x55,0x75,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1157555 + +ld1d {z23.d, z31.d}, pn11/z, [x13, x8, lsl #3] // 10100001-00001000-01101101-10110111 +// CHECK-INST: ld1d { z23.d, z31.d }, pn11/z, [x13, x8, lsl #3] +// CHECK-ENCODING: [0xb7,0x6d,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1086db7 + +ld1d {z23.d, z31.d}, pn15/z, [sp, xzr, lsl #3] // 10100001-00011111-01111111-11110111 +// CHECK-INST: ld1d { z23.d, z31.d }, pn15/z, [sp, xzr, lsl #3] +// CHECK-ENCODING: [0xf7,0x7f,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11f7ff7 + + +ld1d {z0.d, z8.d}, pn8/z, [x0] // 10100001-01000000-01100000-00000000 +// CHECK-INST: ld1d { z0.d, z8.d }, pn8/z, [x0] +// CHECK-ENCODING: [0x00,0x60,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1406000 + +ld1d {z21.d, z29.d}, pn13/z, [x10, #10, mul vl] // 10100001-01000101-01110101-01010101 +// CHECK-INST: ld1d { z21.d, z29.d }, pn13/z, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x75,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1457555 + +ld1d {z23.d, z31.d}, pn11/z, [x13, #-16, mul vl] // 10100001-01001000-01101101-10110111 +// CHECK-INST: ld1d { z23.d, z31.d }, pn11/z, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x6d,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1486db7 + +ld1d {z23.d, z31.d}, pn15/z, [sp, #-2, mul vl] // 10100001-01001111-01111111-11110111 +// CHECK-INST: ld1d { z23.d, z31.d }, pn15/z, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xf7,0x7f,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14f7ff7 + + +ld1d {z0.d, z4.d, z8.d, z12.d}, pn8/z, [x0, x0, lsl #3] // 10100001-00000000-11100000-00000000 +// CHECK-INST: ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x00,0xe0,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a100e000 + +ld1d {z17.d, z21.d, z25.d, z29.d}, pn13/z, [x10, x21, lsl #3] // 10100001-00010101-11110101-01010001 +// CHECK-INST: ld1d { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, x21, lsl #3] +// CHECK-ENCODING: [0x51,0xf5,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a115f551 + +ld1d {z19.d, z23.d, z27.d, z31.d}, pn11/z, [x13, x8, lsl #3] // 10100001-00001000-11101101-10110011 +// CHECK-INST: ld1d { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, x8, lsl #3] +// CHECK-ENCODING: [0xb3,0xed,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a108edb3 + +ld1d {z19.d, z23.d, z27.d, z31.d}, pn15/z, [sp, xzr, lsl #3] // 10100001-00011111-11111111-11110011 +// CHECK-INST: ld1d { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, xzr, lsl #3] +// CHECK-ENCODING: [0xf3,0xff,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11ffff3 + + +ld1d {z0.d, z4.d, z8.d, z12.d}, pn8/z, [x0] // 10100001-01000000-11100000-00000000 +// CHECK-INST: ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0] +// CHECK-ENCODING: [0x00,0xe0,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a140e000 + +ld1d {z17.d, z21.d, z25.d, z29.d}, pn13/z, [x10, #20, mul vl] // 10100001-01000101-11110101-01010001 +// CHECK-INST: ld1d { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, #20, mul vl] +// CHECK-ENCODING: [0x51,0xf5,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a145f551 + +ld1d {z19.d, z23.d, z27.d, z31.d}, pn11/z, [x13, #-32, mul vl] // 10100001-01001000-11101101-10110011 +// CHECK-INST: ld1d { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb3,0xed,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a148edb3 + +ld1d {z19.d, z23.d, z27.d, z31.d}, pn15/z, [sp, #-4, mul vl] // 10100001-01001111-11111111-11110011 +// CHECK-INST: ld1d { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xf3,0xff,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14ffff3 + diff --git a/llvm/test/MC/AArch64/SME2/ld1h.s b/llvm/test/MC/AArch64/SME2/ld1h.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/ld1h.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +ld1h {z0.h, z8.h}, pn8/z, [x0, x0, lsl #1] // 10100001-00000000-00100000-00000000 +// CHECK-INST: ld1h { z0.h, z8.h }, pn8/z, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0x20,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1002000 + +ld1h {z21.h, z29.h}, pn13/z, [x10, x21, lsl #1] // 10100001-00010101-00110101-01010101 +// CHECK-INST: ld1h { z21.h, z29.h }, pn13/z, [x10, x21, lsl #1] +// CHECK-ENCODING: [0x55,0x35,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1153555 + +ld1h {z23.h, z31.h}, pn11/z, [x13, x8, lsl #1] // 10100001-00001000-00101101-10110111 +// CHECK-INST: ld1h { z23.h, z31.h }, pn11/z, [x13, x8, lsl #1] +// CHECK-ENCODING: [0xb7,0x2d,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1082db7 + +ld1h {z23.h, z31.h}, pn15/z, [sp, xzr, lsl #1] // 10100001-00011111-00111111-11110111 +// CHECK-INST: ld1h { z23.h, z31.h }, pn15/z, [sp, xzr, lsl #1] +// CHECK-ENCODING: [0xf7,0x3f,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11f3ff7 + + +ld1h {z0.h, z8.h}, pn8/z, [x0] // 10100001-01000000-00100000-00000000 +// CHECK-INST: ld1h { z0.h, z8.h }, pn8/z, [x0] +// CHECK-ENCODING: [0x00,0x20,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1402000 + +ld1h {z21.h, z29.h}, pn13/z, [x10, #10, mul vl] // 10100001-01000101-00110101-01010101 +// CHECK-INST: ld1h { z21.h, z29.h }, pn13/z, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x35,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1453555 + +ld1h {z23.h, z31.h}, pn11/z, [x13, #-16, mul vl] // 10100001-01001000-00101101-10110111 +// CHECK-INST: ld1h { z23.h, z31.h }, pn11/z, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x2d,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1482db7 + +ld1h {z23.h, z31.h}, pn15/z, [sp, #-2, mul vl] // 10100001-01001111-00111111-11110111 +// CHECK-INST: ld1h { z23.h, z31.h }, pn15/z, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xf7,0x3f,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14f3ff7 + + +ld1h {z0.h, z4.h, z8.h, z12.h}, pn8/z, [x0, x0, lsl #1] // 10100001-00000000-10100000-00000000 +// CHECK-INST: ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0xa0,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a100a000 + +ld1h {z17.h, z21.h, z25.h, z29.h}, pn13/z, [x10, x21, lsl #1] // 10100001-00010101-10110101-01010001 +// CHECK-INST: ld1h { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, x21, lsl #1] +// CHECK-ENCODING: [0x51,0xb5,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a115b551 + +ld1h {z19.h, z23.h, z27.h, z31.h}, pn11/z, [x13, x8, lsl #1] // 10100001-00001000-10101101-10110011 +// CHECK-INST: ld1h { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, x8, lsl #1] +// CHECK-ENCODING: [0xb3,0xad,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a108adb3 + +ld1h {z19.h, z23.h, z27.h, z31.h}, pn15/z, [sp, xzr, lsl #1] // 10100001-00011111-10111111-11110011 +// CHECK-INST: ld1h { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, xzr, lsl #1] +// CHECK-ENCODING: [0xf3,0xbf,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11fbff3 + + +ld1h {z0.h, z4.h, z8.h, z12.h}, pn8/z, [x0] // 10100001-01000000-10100000-00000000 +// CHECK-INST: ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0] +// CHECK-ENCODING: [0x00,0xa0,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a140a000 + +ld1h {z17.h, z21.h, z25.h, z29.h}, pn13/z, [x10, #20, mul vl] // 10100001-01000101-10110101-01010001 +// CHECK-INST: ld1h { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, #20, mul vl] +// CHECK-ENCODING: [0x51,0xb5,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a145b551 + +ld1h {z19.h, z23.h, z27.h, z31.h}, pn11/z, [x13, #-32, mul vl] // 10100001-01001000-10101101-10110011 +// CHECK-INST: ld1h { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb3,0xad,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a148adb3 + +ld1h {z19.h, z23.h, z27.h, z31.h}, pn15/z, [sp, #-4, mul vl] // 10100001-01001111-10111111-11110011 +// CHECK-INST: ld1h { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xf3,0xbf,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14fbff3 + diff --git a/llvm/test/MC/AArch64/SME2/ld1w.s b/llvm/test/MC/AArch64/SME2/ld1w.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/ld1w.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +ld1w {z0.s, z8.s}, pn8/z, [x0, x0, lsl #2] // 10100001-00000000-01000000-00000000 +// CHECK-INST: ld1w { z0.s, z8.s }, pn8/z, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x00,0x40,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1004000 + +ld1w {z21.s, z29.s}, pn13/z, [x10, x21, lsl #2] // 10100001-00010101-01010101-01010101 +// CHECK-INST: ld1w { z21.s, z29.s }, pn13/z, [x10, x21, lsl #2] +// CHECK-ENCODING: [0x55,0x55,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1155555 + +ld1w {z23.s, z31.s}, pn11/z, [x13, x8, lsl #2] // 10100001-00001000-01001101-10110111 +// CHECK-INST: ld1w { z23.s, z31.s }, pn11/z, [x13, x8, lsl #2] +// CHECK-ENCODING: [0xb7,0x4d,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1084db7 + +ld1w {z23.s, z31.s}, pn15/z, [sp, xzr, lsl #2] // 10100001-00011111-01011111-11110111 +// CHECK-INST: ld1w { z23.s, z31.s }, pn15/z, [sp, xzr, lsl #2] +// CHECK-ENCODING: [0xf7,0x5f,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11f5ff7 + + +ld1w {z0.s, z8.s}, pn8/z, [x0] // 10100001-01000000-01000000-00000000 +// CHECK-INST: ld1w { z0.s, z8.s }, pn8/z, [x0] +// CHECK-ENCODING: [0x00,0x40,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1404000 + +ld1w {z21.s, z29.s}, pn13/z, [x10, #10, mul vl] // 10100001-01000101-01010101-01010101 +// CHECK-INST: ld1w { z21.s, z29.s }, pn13/z, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x55,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1455555 + +ld1w {z23.s, z31.s}, pn11/z, [x13, #-16, mul vl] // 10100001-01001000-01001101-10110111 +// CHECK-INST: ld1w { z23.s, z31.s }, pn11/z, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x4d,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1484db7 + +ld1w {z23.s, z31.s}, pn15/z, [sp, #-2, mul vl] // 10100001-01001111-01011111-11110111 +// CHECK-INST: ld1w { z23.s, z31.s }, pn15/z, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xf7,0x5f,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14f5ff7 + + +ld1w {z0.s, z4.s, z8.s, z12.s}, pn8/z, [x0, x0, lsl #2] // 10100001-00000000-11000000-00000000 +// CHECK-INST: ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x00,0xc0,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a100c000 + +ld1w {z17.s, z21.s, z25.s, z29.s}, pn13/z, [x10, x21, lsl #2] // 10100001-00010101-11010101-01010001 +// CHECK-INST: ld1w { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, x21, lsl #2] +// CHECK-ENCODING: [0x51,0xd5,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a115d551 + +ld1w {z19.s, z23.s, z27.s, z31.s}, pn11/z, [x13, x8, lsl #2] // 10100001-00001000-11001101-10110011 +// CHECK-INST: ld1w { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, x8, lsl #2] +// CHECK-ENCODING: [0xb3,0xcd,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a108cdb3 + +ld1w {z19.s, z23.s, z27.s, z31.s}, pn15/z, [sp, xzr, lsl #2] // 10100001-00011111-11011111-11110011 +// CHECK-INST: ld1w { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, xzr, lsl #2] +// CHECK-ENCODING: [0xf3,0xdf,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11fdff3 + + +ld1w {z0.s, z4.s, z8.s, z12.s}, pn8/z, [x0] // 10100001-01000000-11000000-00000000 +// CHECK-INST: ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0] +// CHECK-ENCODING: [0x00,0xc0,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a140c000 + +ld1w {z17.s, z21.s, z25.s, z29.s}, pn13/z, [x10, #20, mul vl] // 10100001-01000101-11010101-01010001 +// CHECK-INST: ld1w { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, #20, mul vl] +// CHECK-ENCODING: [0x51,0xd5,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a145d551 + +ld1w {z19.s, z23.s, z27.s, z31.s}, pn11/z, [x13, #-32, mul vl] // 10100001-01001000-11001101-10110011 +// CHECK-INST: ld1w { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb3,0xcd,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a148cdb3 + +ld1w {z19.s, z23.s, z27.s, z31.s}, pn15/z, [sp, #-4, mul vl] // 10100001-01001111-11011111-11110011 +// CHECK-INST: ld1w { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xf3,0xdf,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14fdff3 + diff --git a/llvm/test/MC/AArch64/SME2/ldnt1b.s b/llvm/test/MC/AArch64/SME2/ldnt1b.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/ldnt1b.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +ldnt1b {z0.b, z8.b}, pn8/z, [x0, x0] // 10100001-00000000-00000000-00001000 +// CHECK-INST: ldnt1b { z0.b, z8.b }, pn8/z, [x0, x0] +// CHECK-ENCODING: [0x08,0x00,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1000008 + +ldnt1b {z21.b, z29.b}, pn13/z, [x10, x21] // 10100001-00010101-00010101-01011101 +// CHECK-INST: ldnt1b { z21.b, z29.b }, pn13/z, [x10, x21] +// CHECK-ENCODING: [0x5d,0x15,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a115155d + +ldnt1b {z23.b, z31.b}, pn11/z, [x13, x8] // 10100001-00001000-00001101-10111111 +// CHECK-INST: ldnt1b { z23.b, z31.b }, pn11/z, [x13, x8] +// CHECK-ENCODING: [0xbf,0x0d,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1080dbf + +ldnt1b {z23.b, z31.b}, pn15/z, [sp, xzr] // 10100001-00011111-00011111-11111111 +// CHECK-INST: ldnt1b { z23.b, z31.b }, pn15/z, [sp, xzr] +// CHECK-ENCODING: [0xff,0x1f,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11f1fff + + +ldnt1b {z0.b, z8.b}, pn8/z, [x0] // 10100001-01000000-00000000-00001000 +// CHECK-INST: ldnt1b { z0.b, z8.b }, pn8/z, [x0] +// CHECK-ENCODING: [0x08,0x00,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1400008 + +ldnt1b {z21.b, z29.b}, pn13/z, [x10, #10, mul vl] // 10100001-01000101-00010101-01011101 +// CHECK-INST: ldnt1b { z21.b, z29.b }, pn13/z, [x10, #10, mul vl] +// CHECK-ENCODING: [0x5d,0x15,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a145155d + +ldnt1b {z23.b, z31.b}, pn11/z, [x13, #-16, mul vl] // 10100001-01001000-00001101-10111111 +// CHECK-INST: ldnt1b { z23.b, z31.b }, pn11/z, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xbf,0x0d,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1480dbf + +ldnt1b {z23.b, z31.b}, pn15/z, [sp, #-2, mul vl] // 10100001-01001111-00011111-11111111 +// CHECK-INST: ldnt1b { z23.b, z31.b }, pn15/z, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0x1f,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14f1fff + + +ldnt1b {z0.b, z4.b, z8.b, z12.b}, pn8/z, [x0, x0] // 10100001-00000000-10000000-00001000 +// CHECK-INST: ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x0] +// CHECK-ENCODING: [0x08,0x80,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1008008 + +ldnt1b {z17.b, z21.b, z25.b, z29.b}, pn13/z, [x10, x21] // 10100001-00010101-10010101-01011001 +// CHECK-INST: ldnt1b { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, x21] +// CHECK-ENCODING: [0x59,0x95,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1159559 + +ldnt1b {z19.b, z23.b, z27.b, z31.b}, pn11/z, [x13, x8] // 10100001-00001000-10001101-10111011 +// CHECK-INST: ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, x8] +// CHECK-ENCODING: [0xbb,0x8d,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1088dbb + +ldnt1b {z19.b, z23.b, z27.b, z31.b}, pn15/z, [sp, xzr] // 10100001-00011111-10011111-11111011 +// CHECK-INST: ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, xzr] +// CHECK-ENCODING: [0xfb,0x9f,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11f9ffb + + +ldnt1b {z0.b, z4.b, z8.b, z12.b}, pn8/z, [x0] // 10100001-01000000-10000000-00001000 +// CHECK-INST: ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0] +// CHECK-ENCODING: [0x08,0x80,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1408008 + +ldnt1b {z17.b, z21.b, z25.b, z29.b}, pn13/z, [x10, #20, mul vl] // 10100001-01000101-10010101-01011001 +// CHECK-INST: ldnt1b { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, #20, mul vl] +// CHECK-ENCODING: [0x59,0x95,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1459559 + +ldnt1b {z19.b, z23.b, z27.b, z31.b}, pn11/z, [x13, #-32, mul vl] // 10100001-01001000-10001101-10111011 +// CHECK-INST: ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xbb,0x8d,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1488dbb + +ldnt1b {z19.b, z23.b, z27.b, z31.b}, pn15/z, [sp, #-4, mul vl] // 10100001-01001111-10011111-11111011 +// CHECK-INST: ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfb,0x9f,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14f9ffb + diff --git a/llvm/test/MC/AArch64/SME2/ldnt1d.s b/llvm/test/MC/AArch64/SME2/ldnt1d.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/ldnt1d.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +ldnt1d {z0.d, z8.d}, pn8/z, [x0, x0, lsl #3] // 10100001-00000000-01100000-00001000 +// CHECK-INST: ldnt1d { z0.d, z8.d }, pn8/z, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x08,0x60,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1006008 + +ldnt1d {z21.d, z29.d}, pn13/z, [x10, x21, lsl #3] // 10100001-00010101-01110101-01011101 +// CHECK-INST: ldnt1d { z21.d, z29.d }, pn13/z, [x10, x21, lsl #3] +// CHECK-ENCODING: [0x5d,0x75,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a115755d + +ldnt1d {z23.d, z31.d}, pn11/z, [x13, x8, lsl #3] // 10100001-00001000-01101101-10111111 +// CHECK-INST: ldnt1d { z23.d, z31.d }, pn11/z, [x13, x8, lsl #3] +// CHECK-ENCODING: [0xbf,0x6d,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1086dbf + +ldnt1d {z23.d, z31.d}, pn15/z, [sp, xzr, lsl #3] // 10100001-00011111-01111111-11111111 +// CHECK-INST: ldnt1d { z23.d, z31.d }, pn15/z, [sp, xzr, lsl #3] +// CHECK-ENCODING: [0xff,0x7f,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11f7fff + + +ldnt1d {z0.d, z8.d}, pn8/z, [x0] // 10100001-01000000-01100000-00001000 +// CHECK-INST: ldnt1d { z0.d, z8.d }, pn8/z, [x0] +// CHECK-ENCODING: [0x08,0x60,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1406008 + +ldnt1d {z21.d, z29.d}, pn13/z, [x10, #10, mul vl] // 10100001-01000101-01110101-01011101 +// CHECK-INST: ldnt1d { z21.d, z29.d }, pn13/z, [x10, #10, mul vl] +// CHECK-ENCODING: [0x5d,0x75,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a145755d + +ldnt1d {z23.d, z31.d}, pn11/z, [x13, #-16, mul vl] // 10100001-01001000-01101101-10111111 +// CHECK-INST: ldnt1d { z23.d, z31.d }, pn11/z, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xbf,0x6d,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1486dbf + +ldnt1d {z23.d, z31.d}, pn15/z, [sp, #-2, mul vl] // 10100001-01001111-01111111-11111111 +// CHECK-INST: ldnt1d { z23.d, z31.d }, pn15/z, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0x7f,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14f7fff + + +ldnt1d {z0.d, z4.d, z8.d, z12.d}, pn8/z, [x0, x0, lsl #3] // 10100001-00000000-11100000-00001000 +// CHECK-INST: ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x08,0xe0,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a100e008 + +ldnt1d {z17.d, z21.d, z25.d, z29.d}, pn13/z, [x10, x21, lsl #3] // 10100001-00010101-11110101-01011001 +// CHECK-INST: ldnt1d { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, x21, lsl #3] +// CHECK-ENCODING: [0x59,0xf5,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a115f559 + +ldnt1d {z19.d, z23.d, z27.d, z31.d}, pn11/z, [x13, x8, lsl #3] // 10100001-00001000-11101101-10111011 +// CHECK-INST: ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, x8, lsl #3] +// CHECK-ENCODING: [0xbb,0xed,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a108edbb + +ldnt1d {z19.d, z23.d, z27.d, z31.d}, pn15/z, [sp, xzr, lsl #3] // 10100001-00011111-11111111-11111011 +// CHECK-INST: ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, xzr, lsl #3] +// CHECK-ENCODING: [0xfb,0xff,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11ffffb + + +ldnt1d {z0.d, z4.d, z8.d, z12.d}, pn8/z, [x0] // 10100001-01000000-11100000-00001000 +// CHECK-INST: ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0] +// CHECK-ENCODING: [0x08,0xe0,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a140e008 + +ldnt1d {z17.d, z21.d, z25.d, z29.d}, pn13/z, [x10, #20, mul vl] // 10100001-01000101-11110101-01011001 +// CHECK-INST: ldnt1d { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, #20, mul vl] +// CHECK-ENCODING: [0x59,0xf5,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a145f559 + +ldnt1d {z19.d, z23.d, z27.d, z31.d}, pn11/z, [x13, #-32, mul vl] // 10100001-01001000-11101101-10111011 +// CHECK-INST: ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xbb,0xed,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a148edbb + +ldnt1d {z19.d, z23.d, z27.d, z31.d}, pn15/z, [sp, #-4, mul vl] // 10100001-01001111-11111111-11111011 +// CHECK-INST: ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfb,0xff,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14ffffb + diff --git a/llvm/test/MC/AArch64/SME2/ldnt1h.s b/llvm/test/MC/AArch64/SME2/ldnt1h.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/ldnt1h.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +ldnt1h {z0.h, z8.h}, pn8/z, [x0, x0, lsl #1] // 10100001-00000000-00100000-00001000 +// CHECK-INST: ldnt1h { z0.h, z8.h }, pn8/z, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x08,0x20,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1002008 + +ldnt1h {z21.h, z29.h}, pn13/z, [x10, x21, lsl #1] // 10100001-00010101-00110101-01011101 +// CHECK-INST: ldnt1h { z21.h, z29.h }, pn13/z, [x10, x21, lsl #1] +// CHECK-ENCODING: [0x5d,0x35,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a115355d + +ldnt1h {z23.h, z31.h}, pn11/z, [x13, x8, lsl #1] // 10100001-00001000-00101101-10111111 +// CHECK-INST: ldnt1h { z23.h, z31.h }, pn11/z, [x13, x8, lsl #1] +// CHECK-ENCODING: [0xbf,0x2d,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1082dbf + +ldnt1h {z23.h, z31.h}, pn15/z, [sp, xzr, lsl #1] // 10100001-00011111-00111111-11111111 +// CHECK-INST: ldnt1h { z23.h, z31.h }, pn15/z, [sp, xzr, lsl #1] +// CHECK-ENCODING: [0xff,0x3f,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11f3fff + + +ldnt1h {z0.h, z8.h}, pn8/z, [x0] // 10100001-01000000-00100000-00001000 +// CHECK-INST: ldnt1h { z0.h, z8.h }, pn8/z, [x0] +// CHECK-ENCODING: [0x08,0x20,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1402008 + +ldnt1h {z21.h, z29.h}, pn13/z, [x10, #10, mul vl] // 10100001-01000101-00110101-01011101 +// CHECK-INST: ldnt1h { z21.h, z29.h }, pn13/z, [x10, #10, mul vl] +// CHECK-ENCODING: [0x5d,0x35,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a145355d + +ldnt1h {z23.h, z31.h}, pn11/z, [x13, #-16, mul vl] // 10100001-01001000-00101101-10111111 +// CHECK-INST: ldnt1h { z23.h, z31.h }, pn11/z, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xbf,0x2d,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1482dbf + +ldnt1h {z23.h, z31.h}, pn15/z, [sp, #-2, mul vl] // 10100001-01001111-00111111-11111111 +// CHECK-INST: ldnt1h { z23.h, z31.h }, pn15/z, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0x3f,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14f3fff + + +ldnt1h {z0.h, z4.h, z8.h, z12.h}, pn8/z, [x0, x0, lsl #1] // 10100001-00000000-10100000-00001000 +// CHECK-INST: ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x08,0xa0,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a100a008 + +ldnt1h {z17.h, z21.h, z25.h, z29.h}, pn13/z, [x10, x21, lsl #1] // 10100001-00010101-10110101-01011001 +// CHECK-INST: ldnt1h { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, x21, lsl #1] +// CHECK-ENCODING: [0x59,0xb5,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a115b559 + +ldnt1h {z19.h, z23.h, z27.h, z31.h}, pn11/z, [x13, x8, lsl #1] // 10100001-00001000-10101101-10111011 +// CHECK-INST: ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, x8, lsl #1] +// CHECK-ENCODING: [0xbb,0xad,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a108adbb + +ldnt1h {z19.h, z23.h, z27.h, z31.h}, pn15/z, [sp, xzr, lsl #1] // 10100001-00011111-10111111-11111011 +// CHECK-INST: ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, xzr, lsl #1] +// CHECK-ENCODING: [0xfb,0xbf,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11fbffb + + +ldnt1h {z0.h, z4.h, z8.h, z12.h}, pn8/z, [x0] // 10100001-01000000-10100000-00001000 +// CHECK-INST: ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0] +// CHECK-ENCODING: [0x08,0xa0,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a140a008 + +ldnt1h {z17.h, z21.h, z25.h, z29.h}, pn13/z, [x10, #20, mul vl] // 10100001-01000101-10110101-01011001 +// CHECK-INST: ldnt1h { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, #20, mul vl] +// CHECK-ENCODING: [0x59,0xb5,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a145b559 + +ldnt1h {z19.h, z23.h, z27.h, z31.h}, pn11/z, [x13, #-32, mul vl] // 10100001-01001000-10101101-10111011 +// CHECK-INST: ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xbb,0xad,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a148adbb + +ldnt1h {z19.h, z23.h, z27.h, z31.h}, pn15/z, [sp, #-4, mul vl] // 10100001-01001111-10111111-11111011 +// CHECK-INST: ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfb,0xbf,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14fbffb + diff --git a/llvm/test/MC/AArch64/SME2/ldnt1w.s b/llvm/test/MC/AArch64/SME2/ldnt1w.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/ldnt1w.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +ldnt1w {z0.s, z8.s}, pn8/z, [x0, x0, lsl #2] // 10100001-00000000-01000000-00001000 +// CHECK-INST: ldnt1w { z0.s, z8.s }, pn8/z, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x08,0x40,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1004008 + +ldnt1w {z21.s, z29.s}, pn13/z, [x10, x21, lsl #2] // 10100001-00010101-01010101-01011101 +// CHECK-INST: ldnt1w { z21.s, z29.s }, pn13/z, [x10, x21, lsl #2] +// CHECK-ENCODING: [0x5d,0x55,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a115555d + +ldnt1w {z23.s, z31.s}, pn11/z, [x13, x8, lsl #2] // 10100001-00001000-01001101-10111111 +// CHECK-INST: ldnt1w { z23.s, z31.s }, pn11/z, [x13, x8, lsl #2] +// CHECK-ENCODING: [0xbf,0x4d,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1084dbf + +ldnt1w {z23.s, z31.s}, pn15/z, [sp, xzr, lsl #2] // 10100001-00011111-01011111-11111111 +// CHECK-INST: ldnt1w { z23.s, z31.s }, pn15/z, [sp, xzr, lsl #2] +// CHECK-ENCODING: [0xff,0x5f,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11f5fff + + +ldnt1w {z0.s, z8.s}, pn8/z, [x0] // 10100001-01000000-01000000-00001000 +// CHECK-INST: ldnt1w { z0.s, z8.s }, pn8/z, [x0] +// CHECK-ENCODING: [0x08,0x40,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1404008 + +ldnt1w {z21.s, z29.s}, pn13/z, [x10, #10, mul vl] // 10100001-01000101-01010101-01011101 +// CHECK-INST: ldnt1w { z21.s, z29.s }, pn13/z, [x10, #10, mul vl] +// CHECK-ENCODING: [0x5d,0x55,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a145555d + +ldnt1w {z23.s, z31.s}, pn11/z, [x13, #-16, mul vl] // 10100001-01001000-01001101-10111111 +// CHECK-INST: ldnt1w { z23.s, z31.s }, pn11/z, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xbf,0x4d,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1484dbf + +ldnt1w {z23.s, z31.s}, pn15/z, [sp, #-2, mul vl] // 10100001-01001111-01011111-11111111 +// CHECK-INST: ldnt1w { z23.s, z31.s }, pn15/z, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0x5f,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14f5fff + + +ldnt1w {z0.s, z4.s, z8.s, z12.s}, pn8/z, [x0, x0, lsl #2] // 10100001-00000000-11000000-00001000 +// CHECK-INST: ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x08,0xc0,0x00,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a100c008 + +ldnt1w {z17.s, z21.s, z25.s, z29.s}, pn13/z, [x10, x21, lsl #2] // 10100001-00010101-11010101-01011001 +// CHECK-INST: ldnt1w { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, x21, lsl #2] +// CHECK-ENCODING: [0x59,0xd5,0x15,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a115d559 + +ldnt1w {z19.s, z23.s, z27.s, z31.s}, pn11/z, [x13, x8, lsl #2] // 10100001-00001000-11001101-10111011 +// CHECK-INST: ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, x8, lsl #2] +// CHECK-ENCODING: [0xbb,0xcd,0x08,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a108cdbb + +ldnt1w {z19.s, z23.s, z27.s, z31.s}, pn15/z, [sp, xzr, lsl #2] // 10100001-00011111-11011111-11111011 +// CHECK-INST: ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, xzr, lsl #2] +// CHECK-ENCODING: [0xfb,0xdf,0x1f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a11fdffb + + +ldnt1w {z0.s, z4.s, z8.s, z12.s}, pn8/z, [x0] // 10100001-01000000-11000000-00001000 +// CHECK-INST: ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0] +// CHECK-ENCODING: [0x08,0xc0,0x40,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a140c008 + +ldnt1w {z17.s, z21.s, z25.s, z29.s}, pn13/z, [x10, #20, mul vl] // 10100001-01000101-11010101-01011001 +// CHECK-INST: ldnt1w { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, #20, mul vl] +// CHECK-ENCODING: [0x59,0xd5,0x45,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a145d559 + +ldnt1w {z19.s, z23.s, z27.s, z31.s}, pn11/z, [x13, #-32, mul vl] // 10100001-01001000-11001101-10111011 +// CHECK-INST: ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xbb,0xcd,0x48,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a148cdbb + +ldnt1w {z19.s, z23.s, z27.s, z31.s}, pn15/z, [sp, #-4, mul vl] // 10100001-01001111-11011111-11111011 +// CHECK-INST: ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfb,0xdf,0x4f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a14fdffb + diff --git a/llvm/test/MC/AArch64/SME2/sel-diagnostics.s b/llvm/test/MC/AArch64/SME2/sel-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/sel-diagnostics.s @@ -0,0 +1,37 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +sel {z0.h-z2.h}, pn8, {z0.h-z1.h}, {z0.h-z1.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sel {z0.h-z2.h}, pn8, {z0.h-z1.h}, {z0.h-z1.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sel {z28.s-z31.s}, pn15, {z26.s-z31.s}, {z28.s-z31.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: sel {z28.s-z31.s}, pn15, {z26.s-z31.s}, {z28.s-z31.s} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sel {z28.d-z31.d}, pn15, {z28.d-z31.d}, {z26.d-z31.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: sel {z28.d-z31.d}, pn15, {z28.d-z31.d}, {z26.d-z31.d} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sel {z1.b-z4.b}, pn8, {z0.b-z3.b}, {z0.b-z3.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: sel {z1.b-z4.b}, pn8, {z0.b-z3.b}, {z0.b-z3.b} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sel {z22.s-z23.s}, pn11, {z13.s-z14.s}, {z8.s-z9.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sel {z22.s-z23.s}, pn11, {z13.s-z14.s}, {z8.s-z9.s} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +sel {z0.h-z1.h}, pn8, {z0.h-z1.h}, {z0.s-z1.s} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sel {z0.h-z1.h}, pn8, {z0.h-z1.h}, {z0.s-z1.s} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/sel.s b/llvm/test/MC/AArch64/SME2/sel.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/sel.s @@ -0,0 +1,213 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +sel {z0.h, z1.h}, pn8, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10000000-00000000 +// CHECK-INST: sel { z0.h, z1.h }, pn8, { z0.h, z1.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x00,0x80,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1608000 + +sel {z20.h, z21.h}, pn13, {z10.h, z11.h}, {z20.h, z21.h} // 11000001-01110100-10010101-01010100 +// CHECK-INST: sel { z20.h, z21.h }, pn13, { z10.h, z11.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x54,0x95,0x74,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1749554 + +sel {z22.h, z23.h}, pn11, {z12.h, z13.h}, {z8.h, z9.h} // 11000001-01101000-10001101-10010110 +// CHECK-INST: sel { z22.h, z23.h }, pn11, { z12.h, z13.h }, { z8.h, z9.h } +// CHECK-ENCODING: [0x96,0x8d,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1688d96 + +sel {z30.h, z31.h}, pn15, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10011111-11011110 +// CHECK-INST: sel { z30.h, z31.h }, pn15, { z30.h, z31.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0xde,0x9f,0x7e,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17e9fde + + +sel {z0.s, z1.s}, pn8, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10000000-00000000 +// CHECK-INST: sel { z0.s, z1.s }, pn8, { z0.s, z1.s }, { z0.s, z1.s } +// CHECK-ENCODING: [0x00,0x80,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a08000 + +sel {z20.s, z21.s}, pn13, {z10.s, z11.s}, {z20.s, z21.s} // 11000001-10110100-10010101-01010100 +// CHECK-INST: sel { z20.s, z21.s }, pn13, { z10.s, z11.s }, { z20.s, z21.s } +// CHECK-ENCODING: [0x54,0x95,0xb4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1b49554 + +sel {z22.s, z23.s}, pn11, {z12.s, z13.s}, {z8.s, z9.s} // 11000001-10101000-10001101-10010110 +// CHECK-INST: sel { z22.s, z23.s }, pn11, { z12.s, z13.s }, { z8.s, z9.s } +// CHECK-ENCODING: [0x96,0x8d,0xa8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a88d96 + +sel {z30.s, z31.s}, pn15, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10011111-11011110 +// CHECK-INST: sel { z30.s, z31.s }, pn15, { z30.s, z31.s }, { z30.s, z31.s } +// CHECK-ENCODING: [0xde,0x9f,0xbe,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1be9fde + + +sel {z0.d, z1.d}, pn8, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10000000-00000000 +// CHECK-INST: sel { z0.d, z1.d }, pn8, { z0.d, z1.d }, { z0.d, z1.d } +// CHECK-ENCODING: [0x00,0x80,0xe0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e08000 + +sel {z20.d, z21.d}, pn13, {z10.d, z11.d}, {z20.d, z21.d} // 11000001-11110100-10010101-01010100 +// CHECK-INST: sel { z20.d, z21.d }, pn13, { z10.d, z11.d }, { z20.d, z21.d } +// CHECK-ENCODING: [0x54,0x95,0xf4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f49554 + +sel {z22.d, z23.d}, pn11, {z12.d, z13.d}, {z8.d, z9.d} // 11000001-11101000-10001101-10010110 +// CHECK-INST: sel { z22.d, z23.d }, pn11, { z12.d, z13.d }, { z8.d, z9.d } +// CHECK-ENCODING: [0x96,0x8d,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e88d96 + +sel {z30.d, z31.d}, pn15, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10011111-11011110 +// CHECK-INST: sel { z30.d, z31.d }, pn15, { z30.d, z31.d }, { z30.d, z31.d } +// CHECK-ENCODING: [0xde,0x9f,0xfe,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1fe9fde + + +sel {z0.b, z1.b}, pn8, {z0.b, z1.b}, {z0.b, z1.b} // 11000001-00100000-10000000-00000000 +// CHECK-INST: sel { z0.b, z1.b }, pn8, { z0.b, z1.b }, { z0.b, z1.b } +// CHECK-ENCODING: [0x00,0x80,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1208000 + +sel {z20.b, z21.b}, pn13, {z10.b, z11.b}, {z20.b, z21.b} // 11000001-00110100-10010101-01010100 +// CHECK-INST: sel { z20.b, z21.b }, pn13, { z10.b, z11.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x54,0x95,0x34,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1349554 + +sel {z22.b, z23.b}, pn11, {z12.b, z13.b}, {z8.b, z9.b} // 11000001-00101000-10001101-10010110 +// CHECK-INST: sel { z22.b, z23.b }, pn11, { z12.b, z13.b }, { z8.b, z9.b } +// CHECK-ENCODING: [0x96,0x8d,0x28,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1288d96 + +sel {z30.b, z31.b}, pn15, {z30.b, z31.b}, {z30.b, z31.b} // 11000001-00111110-10011111-11011110 +// CHECK-INST: sel { z30.b, z31.b }, pn15, { z30.b, z31.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0xde,0x9f,0x3e,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c13e9fde + + +sel {z0.h - z3.h}, pn8, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100001-10000000-00000000 +// CHECK-INST: sel { z0.h - z3.h }, pn8, { z0.h - z3.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x00,0x80,0x61,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1618000 + +sel {z20.h - z23.h}, pn13, {z8.h - z11.h}, {z20.h - z23.h} // 11000001-01110101-10010101-00010100 +// CHECK-INST: sel { z20.h - z23.h }, pn13, { z8.h - z11.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x14,0x95,0x75,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1759514 + +sel {z20.h - z23.h}, pn11, {z12.h - z15.h}, {z8.h - z11.h} // 11000001-01101001-10001101-10010100 +// CHECK-INST: sel { z20.h - z23.h }, pn11, { z12.h - z15.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x94,0x8d,0x69,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1698d94 + +sel {z28.h - z31.h}, pn15, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111101-10011111-10011100 +// CHECK-INST: sel { z28.h - z31.h }, pn15, { z28.h - z31.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x9c,0x9f,0x7d,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17d9f9c + + +sel {z0.s - z3.s}, pn8, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100001-10000000-00000000 +// CHECK-INST: sel { z0.s - z3.s }, pn8, { z0.s - z3.s }, { z0.s - z3.s } +// CHECK-ENCODING: [0x00,0x80,0xa1,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a18000 + +sel {z20.s - z23.s}, pn13, {z8.s - z11.s}, {z20.s - z23.s} // 11000001-10110101-10010101-00010100 +// CHECK-INST: sel { z20.s - z23.s }, pn13, { z8.s - z11.s }, { z20.s - z23.s } +// CHECK-ENCODING: [0x14,0x95,0xb5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1b59514 + +sel {z20.s - z23.s}, pn11, {z12.s - z15.s}, {z8.s - z11.s} // 11000001-10101001-10001101-10010100 +// CHECK-INST: sel { z20.s - z23.s }, pn11, { z12.s - z15.s }, { z8.s - z11.s } +// CHECK-ENCODING: [0x94,0x8d,0xa9,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a98d94 + +sel {z28.s - z31.s}, pn15, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111101-10011111-10011100 +// CHECK-INST: sel { z28.s - z31.s }, pn15, { z28.s - z31.s }, { z28.s - z31.s } +// CHECK-ENCODING: [0x9c,0x9f,0xbd,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1bd9f9c + + +sel {z0.d - z3.d}, pn8, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100001-10000000-00000000 +// CHECK-INST: sel { z0.d - z3.d }, pn8, { z0.d - z3.d }, { z0.d - z3.d } +// CHECK-ENCODING: [0x00,0x80,0xe1,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e18000 + +sel {z20.d - z23.d}, pn13, {z8.d - z11.d}, {z20.d - z23.d} // 11000001-11110101-10010101-00010100 +// CHECK-INST: sel { z20.d - z23.d }, pn13, { z8.d - z11.d }, { z20.d - z23.d } +// CHECK-ENCODING: [0x14,0x95,0xf5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f59514 + +sel {z20.d - z23.d}, pn11, {z12.d - z15.d}, {z8.d - z11.d} // 11000001-11101001-10001101-10010100 +// CHECK-INST: sel { z20.d - z23.d }, pn11, { z12.d - z15.d }, { z8.d - z11.d } +// CHECK-ENCODING: [0x94,0x8d,0xe9,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e98d94 + +sel {z28.d - z31.d}, pn15, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111101-10011111-10011100 +// CHECK-INST: sel { z28.d - z31.d }, pn15, { z28.d - z31.d }, { z28.d - z31.d } +// CHECK-ENCODING: [0x9c,0x9f,0xfd,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1fd9f9c + + +sel {z0.b - z3.b}, pn8, {z0.b - z3.b}, {z0.b - z3.b} // 11000001-00100001-10000000-00000000 +// CHECK-INST: sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b } +// CHECK-ENCODING: [0x00,0x80,0x21,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1218000 + +sel {z20.b - z23.b}, pn13, {z8.b - z11.b}, {z20.b - z23.b} // 11000001-00110101-10010101-00010100 +// CHECK-INST: sel { z20.b - z23.b }, pn13, { z8.b - z11.b }, { z20.b - z23.b } +// CHECK-ENCODING: [0x14,0x95,0x35,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1359514 + +sel {z20.b - z23.b}, pn11, {z12.b - z15.b}, {z8.b - z11.b} // 11000001-00101001-10001101-10010100 +// CHECK-INST: sel { z20.b - z23.b }, pn11, { z12.b - z15.b }, { z8.b - z11.b } +// CHECK-ENCODING: [0x94,0x8d,0x29,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1298d94 + +sel {z28.b - z31.b}, pn15, {z28.b - z31.b}, {z28.b - z31.b} // 11000001-00111101-10011111-10011100 +// CHECK-INST: sel { z28.b - z31.b }, pn15, { z28.b - z31.b }, { z28.b - z31.b } +// CHECK-ENCODING: [0x9c,0x9f,0x3d,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c13d9f9c + diff --git a/llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s b/llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s --- a/llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s +++ b/llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s @@ -73,7 +73,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: sqdmulh {z0.s,z1.s}, {z0.s,z2.s}, z15.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.s,z2.s}, z15.s // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/st1b b/llvm/test/MC/AArch64/SME2/st1b new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/st1b @@ -0,0 +1,213 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +st1b {z0.b, z1.b}, pn8, [x0, x0] // 10100000, 00100000, 00000000, 00000000 +// CHECK, INST: st1b { z0.b, z1.b }, pn8, [x0, x0] +// CHECK-ENCODING: [0x00,0x00,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0200000 + +st1b {z20.b, z21.b}, pn13, [x10, x21] // 10100000, 00110101, 00010101, 01010100 +// CHECK, INST: st1b { z20.b, z21.b }, pn13, [x10, x21] +// CHECK-ENCODING: [0x54,0x15,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0351554 + +st1b {z22.b, z23.b}, pn11, [x13, x8] // 10100000, 00101000, 00001101, 10110110 +// CHECK, INST: st1b { z22.b, z23.b }, pn11, [x13, x8] +// CHECK-ENCODING: [0xb6,0x0d,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0280db6 + +st1b {z30.b, z31.b}, pn15, [sp, xzr] // 10100000, 00111111, 00011111, 11111110 +// CHECK, INST: st1b { z30.b, z31.b }, pn15, [sp, xzr] +// CHECK-ENCODING: [0xfe,0x1f,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03f1ffe + + +st1b {z0.b, z1.b}, pn8, [x0] // 10100000, 01100000, 00000000, 00000000 +// CHECK, INST: st1b { z0.b, z1.b }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x00,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0600000 + +st1b {z20.b, z21.b}, pn13, [x10, #10, mul vl] // 10100000, 01100101, 00010101, 01010100 +// CHECK, INST: st1b { z20.b, z21.b }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x54,0x15,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0651554 + +st1b {z22.b, z23.b}, pn11, [x13, #, 16, mul vl] // 10100000, 01101000, 00001101, 10110110 +// CHECK, INST: st1b { z22.b, z23.b }, pn11, [x13, #, 16, mul vl] +// CHECK-ENCODING: [0xb6,0x0d,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0680db6 + +st1b {z30.b, z31.b}, pn15, [sp, #, 2, mul vl] // 10100000, 01101111, 00011111, 11111110 +// CHECK, INST: st1b { z30.b, z31.b }, pn15, [sp, #, 2, mul vl] +// CHECK-ENCODING: [0xfe,0x1f,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06f1ffe + + +st1b {z0.b, z8.b}, pn8, [x0, x0] // 10100001-00100000-00000000-00000000 +// CHECK-INST: st1b { z0.b, z8.b }, pn8, [x0, x0] +// CHECK-ENCODING: [0x00,0x00,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1200000 + +st1b {z21.b, z29.b}, pn13, [x10, x21] // 10100001-00110101-00010101-01010101 +// CHECK-INST: st1b { z21.b, z29.b }, pn13, [x10, x21] +// CHECK-ENCODING: [0x55,0x15,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1351555 + +st1b {z23.b, z31.b}, pn11, [x13, x8] // 10100001-00101000-00001101-10110111 +// CHECK-INST: st1b { z23.b, z31.b }, pn11, [x13, x8] +// CHECK-ENCODING: [0xb7,0x0d,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1280db7 + +st1b {z23.b, z31.b}, pn15, [sp, xzr] // 10100001-00111111-00011111-11110111 +// CHECK-INST: st1b { z23.b, z31.b }, pn15, [sp, xzr] +// CHECK-ENCODING: [0xf7,0x1f,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13f1ff7 + + +st1b {z0.b, z8.b}, pn8, [x0] // 10100001-01100000-00000000-00000000 +// CHECK-INST: st1b { z0.b, z8.b }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x00,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1600000 + +st1b {z21.b, z29.b}, pn13, [x10, #10, mul vl] // 10100001-01100101-00010101-01010101 +// CHECK-INST: st1b { z21.b, z29.b }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x15,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1651555 + +st1b {z23.b, z31.b}, pn11, [x13, #-16, mul vl] // 10100001-01101000-00001101-10110111 +// CHECK-INST: st1b { z23.b, z31.b }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x0d,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1680db7 + +st1b {z23.b, z31.b}, pn15, [sp, #-2, mul vl] // 10100001-01101111-00011111-11110111 +// CHECK-INST: st1b { z23.b, z31.b }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xf7,0x1f,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16f1ff7 + + +st1b {z0.b-z3.b}, pn8, [x0, x0] // 10100000-00100000-10000000-00000000 +// CHECK-INST: st1b { z0.b-z3.b }, pn8, [x0, x0] +// CHECK-ENCODING: [0x00,0x80,0x20,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0208000 + +st1b {z20.b-z23.b}, pn13, [x10, x21] // 10100000-00110101-10010101-01010100 +// CHECK-INST: st1b { z20.b-z23.b }, pn13, [x10, x21] +// CHECK-ENCODING: [0x54,0x95,0x35,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0359554 + +st1b {z20.b-z23.b}, pn11, [x13, x8] // 10100000-00101000-10001101-10110100 +// CHECK-INST: st1b { z20.b-z23.b }, pn11, [x13, x8] +// CHECK-ENCODING: [0xb4,0x8d,0x28,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0288db4 + +st1b {z28.b-z31.b}, pn15, [sp, xzr] // 10100000-00111111-10011111-11111100 +// CHECK-INST: st1b { z28.b-z31.b }, pn15, [sp, xzr] +// CHECK-ENCODING: [0xfc,0x9f,0x3f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a03f9ffc + + +st1b {z0.b-z3.b}, pn8, [x0] // 10100000-01100000-10000000-00000000 +// CHECK-INST: st1b { z0.b-z3.b }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x80,0x60,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0608000 + +st1b {z20.b-z23.b}, pn13, [x10, #20, mul vl] // 10100000-01100101-10010101-01010100 +// CHECK-INST: st1b { z20.b-z23.b }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x54,0x95,0x65,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0659554 + +st1b {z20.b-z23.b}, pn11, [x13, #-32, mul vl] // 10100000-01101000-10001101-10110100 +// CHECK-INST: st1b { z20.b-z23.b }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb4,0x8d,0x68,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a0688db4 + +st1b {z28.b-z31.b}, pn15, [sp, #-4, mul vl] // 10100000-01101111-10011111-11111100 +// CHECK-INST: st1b { z28.b-z31.b }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfc,0x9f,0x6f,0xa0] +// CHECK-ERROR: instruction requires: sme2 or sve2p1 +// CHECK-UNKNOWN: a06f9ffc + + +st1b {z0.b, z4.b, z8.b, z12.b}, pn8, [x0, x0] // 10100001-00100000-10000000-00000000 +// CHECK-INST: st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x0] +// CHECK-ENCODING: [0x00,0x80,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1208000 + +st1b {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, x21] // 10100001-00110101-10010101-01010001 +// CHECK-INST: st1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, x21] +// CHECK-ENCODING: [0x51,0x95,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1359551 + +st1b {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, x8] // 10100001-00101000-10001101-10110011 +// CHECK-INST: st1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, x8] +// CHECK-ENCODING: [0xb3,0x8d,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1288db3 + +st1b {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, xzr] // 10100001-00111111-10011111-11110011 +// CHECK-INST: st1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, xzr] +// CHECK-ENCODING: [0xf3,0x9f,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13f9ff3 + + +st1b {z0.b, z4.b, z8.b, z12.b}, pn8, [x0] // 10100001-01100000-10000000-00000000 +// CHECK-INST: st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x80,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1608000 + +st1b {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, #20, mul vl] // 10100001-01100101-10010101-01010001 +// CHECK-INST: st1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x51,0x95,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1659551 + +st1b {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, #-32, mul vl] // 10100001-01101000-10001101-10110011 +// CHECK-INST: st1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb3,0x8d,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1688db3 + +st1b {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, #-4, mul vl] // 10100001-01101111-10011111-11110011 +// CHECK-INST: st1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xf3,0x9f,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16f9ff3 + diff --git a/llvm/test/MC/AArch64/SME2/st1b.s b/llvm/test/MC/AArch64/SME2/st1b.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/st1b.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +st1b {z0.b, z8.b}, pn8, [x0, x0] // 10100001-00100000-00000000-00000000 +// CHECK-INST: st1b { z0.b, z8.b }, pn8, [x0, x0] +// CHECK-ENCODING: [0x00,0x00,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1200000 + +st1b {z21.b, z29.b}, pn13, [x10, x21] // 10100001-00110101-00010101-01010101 +// CHECK-INST: st1b { z21.b, z29.b }, pn13, [x10, x21] +// CHECK-ENCODING: [0x55,0x15,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1351555 + +st1b {z23.b, z31.b}, pn11, [x13, x8] // 10100001-00101000-00001101-10110111 +// CHECK-INST: st1b { z23.b, z31.b }, pn11, [x13, x8] +// CHECK-ENCODING: [0xb7,0x0d,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1280db7 + +st1b {z23.b, z31.b}, pn15, [sp, xzr] // 10100001-00111111-00011111-11110111 +// CHECK-INST: st1b { z23.b, z31.b }, pn15, [sp, xzr] +// CHECK-ENCODING: [0xf7,0x1f,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13f1ff7 + + +st1b {z0.b, z8.b}, pn8, [x0] // 10100001-01100000-00000000-00000000 +// CHECK-INST: st1b { z0.b, z8.b }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x00,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1600000 + +st1b {z21.b, z29.b}, pn13, [x10, #10, mul vl] // 10100001-01100101-00010101-01010101 +// CHECK-INST: st1b { z21.b, z29.b }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x15,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1651555 + +st1b {z23.b, z31.b}, pn11, [x13, #-16, mul vl] // 10100001-01101000-00001101-10110111 +// CHECK-INST: st1b { z23.b, z31.b }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x0d,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1680db7 + +st1b {z23.b, z31.b}, pn15, [sp, #-2, mul vl] // 10100001-01101111-00011111-11110111 +// CHECK-INST: st1b { z23.b, z31.b }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xf7,0x1f,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16f1ff7 + + +st1b {z0.b, z4.b, z8.b, z12.b}, pn8, [x0, x0] // 10100001-00100000-10000000-00000000 +// CHECK-INST: st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x0] +// CHECK-ENCODING: [0x00,0x80,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1208000 + +st1b {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, x21] // 10100001-00110101-10010101-01010001 +// CHECK-INST: st1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, x21] +// CHECK-ENCODING: [0x51,0x95,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1359551 + +st1b {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, x8] // 10100001-00101000-10001101-10110011 +// CHECK-INST: st1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, x8] +// CHECK-ENCODING: [0xb3,0x8d,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1288db3 + +st1b {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, xzr] // 10100001-00111111-10011111-11110011 +// CHECK-INST: st1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, xzr] +// CHECK-ENCODING: [0xf3,0x9f,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13f9ff3 + + +st1b {z0.b, z4.b, z8.b, z12.b}, pn8, [x0] // 10100001-01100000-10000000-00000000 +// CHECK-INST: st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x80,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1608000 + +st1b {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, #20, mul vl] // 10100001-01100101-10010101-01010001 +// CHECK-INST: st1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x51,0x95,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1659551 + +st1b {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, #-32, mul vl] // 10100001-01101000-10001101-10110011 +// CHECK-INST: st1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb3,0x8d,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1688db3 + +st1b {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, #-4, mul vl] // 10100001-01101111-10011111-11110011 +// CHECK-INST: st1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xf3,0x9f,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16f9ff3 + diff --git a/llvm/test/MC/AArch64/SME2/st1d.s b/llvm/test/MC/AArch64/SME2/st1d.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/st1d.s @@ -0,0 +1,113 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +st1d {z0.d, z8.d}, pn8, [x0, x0, lsl #3] // 10100001-00100000-01100000-00000000 +// CHECK-INST: st1d { z0.d, z8.d }, pn8, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x00,0x60,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1206000 + +st1d {z21.d, z29.d}, pn13, [x10, x21, lsl #3] // 10100001-00110101-01110101-01010101 +// CHECK-INST: st1d { z21.d, z29.d }, pn13, [x10, x21, lsl #3] +// CHECK-ENCODING: [0x55,0x75,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1357555 + +st1d {z23.d, z31.d}, pn11, [x13, x8, lsl #3] // 10100001-00101000-01101101-10110111 +// CHECK-INST: st1d { z23.d, z31.d }, pn11, [x13, x8, lsl #3] +// CHECK-ENCODING: [0xb7,0x6d,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1286db7 + +st1d {z23.d, z31.d}, pn15, [sp, xzr, lsl #3] // 10100001-00111111-01111111-11110111 +// CHECK-INST: st1d { z23.d, z31.d }, pn15, [sp, xzr, lsl #3] +// CHECK-ENCODING: [0xf7,0x7f,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13f7ff7 + + +st1d {z0.d, z8.d}, pn8, [x0] // 10100001-01100000-01100000-00000000 +// CHECK-INST: st1d { z0.d, z8.d }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x60,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1606000 + +st1d {z21.d, z29.d}, pn13, [x10, #10, mul vl] // 10100001-01100101-01110101-01010101 +// CHECK-INST: st1d { z21.d, z29.d }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x75,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1657555 + +st1d {z23.d, z31.d}, pn11, [x13, #-16, mul vl] // 10100001-01101000-01101101-10110111 +// CHECK-INST: st1d { z23.d, z31.d }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x6d,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1686db7 + +st1d {z23.d, z31.d}, pn15, [sp, #-2, mul vl] // 10100001-01101111-01111111-11110111 +// CHECK-INST: st1d { z23.d, z31.d }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xf7,0x7f,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16f7ff7 + + +st1d {z0.d, z4.d, z8.d, z12.d}, pn8, [x0, x0, lsl #3] // 10100001-00100000-11100000-00000000 +// CHECK-INST: st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x00,0xe0,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a120e000 + +st1d {z17.d, z21.d, z25.d, z29.d}, pn13, [x10, x21, lsl #3] // 10100001-00110101-11110101-01010001 +// CHECK-INST: st1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, x21, lsl #3] +// CHECK-ENCODING: [0x51,0xf5,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a135f551 + +st1d {z19.d, z23.d, z27.d, z31.d}, pn11, [x13, x8, lsl #3] // 10100001-00101000-11101101-10110011 +// CHECK-INST: st1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, x8, lsl #3] +// CHECK-ENCODING: [0xb3,0xed,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a128edb3 + +st1d {z19.d, z23.d, z27.d, z31.d}, pn15, [sp, xzr, lsl #3] // 10100001-00111111-11111111-11110011 +// CHECK-INST: st1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, xzr, lsl #3] +// CHECK-ENCODING: [0xf3,0xff,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13ffff3 + + +st1d {z0.d, z4.d, z8.d, z12.d}, pn8, [x0] // 10100001-01100000-11100000-00000000 +// CHECK-INST: st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0] +// CHECK-ENCODING: [0x00,0xe0,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a160e000 + +st1d {z17.d, z21.d, z25.d, z29.d}, pn13, [x10, #20, mul vl] // 10100001-01100101-11110101-01010001 +// CHECK-INST: st1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x51,0xf5,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a165f551 + +st1d {z19.d, z23.d, z27.d, z31.d}, pn11, [x13, #-32, mul vl] // 10100001-01101000-11101101-10110011 +// CHECK-INST: st1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb3,0xed,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a168edb3 + +st1d {z19.d, z23.d, z27.d, z31.d}, pn15, [sp, #-4, mul vl] // 10100001-01101111-11111111-11110011 +// CHECK-INST: st1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xf3,0xff,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16ffff3 + diff --git a/llvm/test/MC/AArch64/SME2/st1h.s b/llvm/test/MC/AArch64/SME2/st1h.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/st1h.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \ +// RUN: |FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +st1h {z0.h, z8.h}, pn8, [x0, x0, lsl #1] // 10100001-00100000-00100000-00000000 +// CHECK-INST: st1h { z0.h, z8.h }, pn8, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0x20,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1202000 + +st1h {z21.h, z29.h}, pn13, [x10, x21, lsl #1] // 10100001-00110101-00110101-01010101 +// CHECK-INST: st1h { z21.h, z29.h }, pn13, [x10, x21, lsl #1] +// CHECK-ENCODING: [0x55,0x35,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1353555 + +st1h {z23.h, z31.h}, pn11, [x13, x8, lsl #1] // 10100001-00101000-00101101-10110111 +// CHECK-INST: st1h { z23.h, z31.h }, pn11, [x13, x8, lsl #1] +// CHECK-ENCODING: [0xb7,0x2d,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1282db7 + +st1h {z23.h, z31.h}, pn15, [sp, xzr, lsl #1] // 10100001-00111111-00111111-11110111 +// CHECK-INST: st1h { z23.h, z31.h }, pn15, [sp, xzr, lsl #1] +// CHECK-ENCODING: [0xf7,0x3f,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13f3ff7 + + +st1h {z0.h, z8.h}, pn8, [x0] // 10100001-01100000-00100000-00000000 +// CHECK-INST: st1h { z0.h, z8.h }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x20,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1602000 + +st1h {z21.h, z29.h}, pn13, [x10, #10, mul vl] // 10100001-01100101-00110101-01010101 +// CHECK-INST: st1h { z21.h, z29.h }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x35,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1653555 + +st1h {z23.h, z31.h}, pn11, [x13, #-16, mul vl] // 10100001-01101000-00101101-10110111 +// CHECK-INST: st1h { z23.h, z31.h }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x2d,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1682db7 + +st1h {z23.h, z31.h}, pn15, [sp, #-2, mul vl] // 10100001-01101111-00111111-11110111 +// CHECK-INST: st1h { z23.h, z31.h }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xf7,0x3f,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16f3ff7 + + +st1h {z0.h, z4.h, z8.h, z12.h}, pn8, [x0, x0, lsl #1] // 10100001-00100000-10100000-00000000 +// CHECK-INST: st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x00,0xa0,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a120a000 + +st1h {z17.h, z21.h, z25.h, z29.h}, pn13, [x10, x21, lsl #1] // 10100001-00110101-10110101-01010001 +// CHECK-INST: st1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, x21, lsl #1] +// CHECK-ENCODING: [0x51,0xb5,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a135b551 + +st1h {z19.h, z23.h, z27.h, z31.h}, pn11, [x13, x8, lsl #1] // 10100001-00101000-10101101-10110011 +// CHECK-INST: st1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, x8, lsl #1] +// CHECK-ENCODING: [0xb3,0xad,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a128adb3 + +st1h {z19.h, z23.h, z27.h, z31.h}, pn15, [sp, xzr, lsl #1] // 10100001-00111111-10111111-11110011 +// CHECK-INST: st1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, xzr, lsl #1] +// CHECK-ENCODING: [0xf3,0xbf,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13fbff3 + + +st1h {z0.h, z4.h, z8.h, z12.h}, pn8, [x0] // 10100001-01100000-10100000-00000000 +// CHECK-INST: st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0] +// CHECK-ENCODING: [0x00,0xa0,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a160a000 + +st1h {z17.h, z21.h, z25.h, z29.h}, pn13, [x10, #20, mul vl] // 10100001-01100101-10110101-01010001 +// CHECK-INST: st1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x51,0xb5,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a165b551 + +st1h {z19.h, z23.h, z27.h, z31.h}, pn11, [x13, #-32, mul vl] // 10100001-01101000-10101101-10110011 +// CHECK-INST: st1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb3,0xad,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a168adb3 + +st1h {z19.h, z23.h, z27.h, z31.h}, pn15, [sp, #-4, mul vl] // 10100001-01101111-10111111-11110011 +// CHECK-INST: st1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xf3,0xbf,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16fbff3 + diff --git a/llvm/test/MC/AArch64/SME2/st1w.s b/llvm/test/MC/AArch64/SME2/st1w.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/st1w.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +st1w {z0.s, z8.s}, pn8, [x0, x0, lsl #2] // 10100001-00100000-01000000-00000000 +// CHECK-INST: st1w { z0.s, z8.s }, pn8, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x00,0x40,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1204000 + +st1w {z21.s, z29.s}, pn13, [x10, x21, lsl #2] // 10100001-00110101-01010101-01010101 +// CHECK-INST: st1w { z21.s, z29.s }, pn13, [x10, x21, lsl #2] +// CHECK-ENCODING: [0x55,0x55,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1355555 + +st1w {z23.s, z31.s}, pn11, [x13, x8, lsl #2] // 10100001-00101000-01001101-10110111 +// CHECK-INST: st1w { z23.s, z31.s }, pn11, [x13, x8, lsl #2] +// CHECK-ENCODING: [0xb7,0x4d,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1284db7 + +st1w {z23.s, z31.s}, pn15, [sp, xzr, lsl #2] // 10100001-00111111-01011111-11110111 +// CHECK-INST: st1w { z23.s, z31.s }, pn15, [sp, xzr, lsl #2] +// CHECK-ENCODING: [0xf7,0x5f,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13f5ff7 + + +st1w {z0.s, z8.s}, pn8, [x0] // 10100001-01100000-01000000-00000000 +// CHECK-INST: st1w { z0.s, z8.s }, pn8, [x0] +// CHECK-ENCODING: [0x00,0x40,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1604000 + +st1w {z21.s, z29.s}, pn13, [x10, #10, mul vl] // 10100001-01100101-01010101-01010101 +// CHECK-INST: st1w { z21.s, z29.s }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x55,0x55,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1655555 + +st1w {z23.s, z31.s}, pn11, [x13, #-16, mul vl] // 10100001-01101000-01001101-10110111 +// CHECK-INST: st1w { z23.s, z31.s }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xb7,0x4d,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1684db7 + +st1w {z23.s, z31.s}, pn15, [sp, #-2, mul vl] // 10100001-01101111-01011111-11110111 +// CHECK-INST: st1w { z23.s, z31.s }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xf7,0x5f,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16f5ff7 + + +st1w {z0.s, z4.s, z8.s, z12.s}, pn8, [x0, x0, lsl #2] // 10100001-00100000-11000000-00000000 +// CHECK-INST: st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x00,0xc0,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a120c000 + +st1w {z17.s, z21.s, z25.s, z29.s}, pn13, [x10, x21, lsl #2] // 10100001-00110101-11010101-01010001 +// CHECK-INST: st1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, x21, lsl #2] +// CHECK-ENCODING: [0x51,0xd5,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a135d551 + +st1w {z19.s, z23.s, z27.s, z31.s}, pn11, [x13, x8, lsl #2] // 10100001-00101000-11001101-10110011 +// CHECK-INST: st1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, x8, lsl #2] +// CHECK-ENCODING: [0xb3,0xcd,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a128cdb3 + +st1w {z19.s, z23.s, z27.s, z31.s}, pn15, [sp, xzr, lsl #2] // 10100001-00111111-11011111-11110011 +// CHECK-INST: st1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, xzr, lsl #2] +// CHECK-ENCODING: [0xf3,0xdf,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13fdff3 + + +st1w {z0.s, z4.s, z8.s, z12.s}, pn8, [x0] // 10100001-01100000-11000000-00000000 +// CHECK-INST: st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0] +// CHECK-ENCODING: [0x00,0xc0,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a160c000 + +st1w {z17.s, z21.s, z25.s, z29.s}, pn13, [x10, #20, mul vl] // 10100001-01100101-11010101-01010001 +// CHECK-INST: st1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x51,0xd5,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a165d551 + +st1w {z19.s, z23.s, z27.s, z31.s}, pn11, [x13, #-32, mul vl] // 10100001-01101000-11001101-10110011 +// CHECK-INST: st1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xb3,0xcd,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a168cdb3 + +st1w {z19.s, z23.s, z27.s, z31.s}, pn15, [sp, #-4, mul vl] // 10100001-01101111-11011111-11110011 +// CHECK-INST: st1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xf3,0xdf,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16fdff3 + diff --git a/llvm/test/MC/AArch64/SME2/stnt1b.s b/llvm/test/MC/AArch64/SME2/stnt1b.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/stnt1b.s @@ -0,0 +1,113 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +stnt1b {z0.b, z8.b}, pn8, [x0, x0] // 10100001-00100000-00000000-00001000 +// CHECK-INST: stnt1b { z0.b, z8.b }, pn8, [x0, x0] +// CHECK-ENCODING: [0x08,0x00,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1200008 + +stnt1b {z21.b, z29.b}, pn13, [x10, x21] // 10100001-00110101-00010101-01011101 +// CHECK-INST: stnt1b { z21.b, z29.b }, pn13, [x10, x21] +// CHECK-ENCODING: [0x5d,0x15,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a135155d + +stnt1b {z23.b, z31.b}, pn11, [x13, x8] // 10100001-00101000-00001101-10111111 +// CHECK-INST: stnt1b { z23.b, z31.b }, pn11, [x13, x8] +// CHECK-ENCODING: [0xbf,0x0d,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1280dbf + +stnt1b {z23.b, z31.b}, pn15, [sp, xzr] // 10100001-00111111-00011111-11111111 +// CHECK-INST: stnt1b { z23.b, z31.b }, pn15, [sp, xzr] +// CHECK-ENCODING: [0xff,0x1f,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13f1fff + + +stnt1b {z0.b, z8.b}, pn8, [x0] // 10100001-01100000-00000000-00001000 +// CHECK-INST: stnt1b { z0.b, z8.b }, pn8, [x0] +// CHECK-ENCODING: [0x08,0x00,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1600008 + +stnt1b {z21.b, z29.b}, pn13, [x10, #10, mul vl] // 10100001-01100101-00010101-01011101 +// CHECK-INST: stnt1b { z21.b, z29.b }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x5d,0x15,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a165155d + +stnt1b {z23.b, z31.b}, pn11, [x13, #-16, mul vl] // 10100001-01101000-00001101-10111111 +// CHECK-INST: stnt1b { z23.b, z31.b }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xbf,0x0d,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1680dbf + +stnt1b {z23.b, z31.b}, pn15, [sp, #-2, mul vl] // 10100001-01101111-00011111-11111111 +// CHECK-INST: stnt1b { z23.b, z31.b }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0x1f,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16f1fff + + +stnt1b {z0.b, z4.b, z8.b, z12.b}, pn8, [x0, x0] // 10100001-00100000-10000000-00001000 +// CHECK-INST: stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x0] +// CHECK-ENCODING: [0x08,0x80,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1208008 + +stnt1b {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, x21] // 10100001-00110101-10010101-01011001 +// CHECK-INST: stnt1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, x21] +// CHECK-ENCODING: [0x59,0x95,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1359559 + +stnt1b {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, x8] // 10100001-00101000-10001101-10111011 +// CHECK-INST: stnt1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, x8] +// CHECK-ENCODING: [0xbb,0x8d,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1288dbb + +stnt1b {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, xzr] // 10100001-00111111-10011111-11111011 +// CHECK-INST: stnt1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, xzr] +// CHECK-ENCODING: [0xfb,0x9f,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13f9ffb + + +stnt1b {z0.b, z4.b, z8.b, z12.b}, pn8, [x0] // 10100001-01100000-10000000-00001000 +// CHECK-INST: stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0] +// CHECK-ENCODING: [0x08,0x80,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1608008 + +stnt1b {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, #20, mul vl] // 10100001-01100101-10010101-01011001 +// CHECK-INST: stnt1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x59,0x95,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1659559 + +stnt1b {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, #-32, mul vl] // 10100001-01101000-10001101-10111011 +// CHECK-INST: stnt1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xbb,0x8d,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1688dbb + +stnt1b {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, #-4, mul vl] // 10100001-01101111-10011111-11111011 +// CHECK-INST: stnt1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfb,0x9f,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16f9ffb + diff --git a/llvm/test/MC/AArch64/SME2/stnt1d.s b/llvm/test/MC/AArch64/SME2/stnt1d.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/stnt1d.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +stnt1d {z0.d, z8.d}, pn8, [x0, x0, lsl #3] // 10100001-00100000-01100000-00001000 +// CHECK-INST: stnt1d { z0.d, z8.d }, pn8, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x08,0x60,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1206008 + +stnt1d {z21.d, z29.d}, pn13, [x10, x21, lsl #3] // 10100001-00110101-01110101-01011101 +// CHECK-INST: stnt1d { z21.d, z29.d }, pn13, [x10, x21, lsl #3] +// CHECK-ENCODING: [0x5d,0x75,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a135755d + +stnt1d {z23.d, z31.d}, pn11, [x13, x8, lsl #3] // 10100001-00101000-01101101-10111111 +// CHECK-INST: stnt1d { z23.d, z31.d }, pn11, [x13, x8, lsl #3] +// CHECK-ENCODING: [0xbf,0x6d,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1286dbf + +stnt1d {z23.d, z31.d}, pn15, [sp, xzr, lsl #3] // 10100001-00111111-01111111-11111111 +// CHECK-INST: stnt1d { z23.d, z31.d }, pn15, [sp, xzr, lsl #3] +// CHECK-ENCODING: [0xff,0x7f,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13f7fff + + +stnt1d {z0.d, z8.d}, pn8, [x0] // 10100001-01100000-01100000-00001000 +// CHECK-INST: stnt1d { z0.d, z8.d }, pn8, [x0] +// CHECK-ENCODING: [0x08,0x60,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1606008 + +stnt1d {z21.d, z29.d}, pn13, [x10, #10, mul vl] // 10100001-01100101-01110101-01011101 +// CHECK-INST: stnt1d { z21.d, z29.d }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x5d,0x75,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a165755d + +stnt1d {z23.d, z31.d}, pn11, [x13, #-16, mul vl] // 10100001-01101000-01101101-10111111 +// CHECK-INST: stnt1d { z23.d, z31.d }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xbf,0x6d,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1686dbf + +stnt1d {z23.d, z31.d}, pn15, [sp, #-2, mul vl] // 10100001-01101111-01111111-11111111 +// CHECK-INST: stnt1d { z23.d, z31.d }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0x7f,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16f7fff + + +stnt1d {z0.d, z4.d, z8.d, z12.d}, pn8, [x0, x0, lsl #3] // 10100001-00100000-11100000-00001000 +// CHECK-INST: stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x0, lsl #3] +// CHECK-ENCODING: [0x08,0xe0,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a120e008 + +stnt1d {z17.d, z21.d, z25.d, z29.d}, pn13, [x10, x21, lsl #3] // 10100001-00110101-11110101-01011001 +// CHECK-INST: stnt1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, x21, lsl #3] +// CHECK-ENCODING: [0x59,0xf5,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a135f559 + +stnt1d {z19.d, z23.d, z27.d, z31.d}, pn11, [x13, x8, lsl #3] // 10100001-00101000-11101101-10111011 +// CHECK-INST: stnt1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, x8, lsl #3] +// CHECK-ENCODING: [0xbb,0xed,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a128edbb + +stnt1d {z19.d, z23.d, z27.d, z31.d}, pn15, [sp, xzr, lsl #3] // 10100001-00111111-11111111-11111011 +// CHECK-INST: stnt1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, xzr, lsl #3] +// CHECK-ENCODING: [0xfb,0xff,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13ffffb + + +stnt1d {z0.d, z4.d, z8.d, z12.d}, pn8, [x0] // 10100001-01100000-11100000-00001000 +// CHECK-INST: stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0] +// CHECK-ENCODING: [0x08,0xe0,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a160e008 + +stnt1d {z17.d, z21.d, z25.d, z29.d}, pn13, [x10, #20, mul vl] // 10100001-01100101-11110101-01011001 +// CHECK-INST: stnt1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x59,0xf5,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a165f559 + +stnt1d {z19.d, z23.d, z27.d, z31.d}, pn11, [x13, #-32, mul vl] // 10100001-01101000-11101101-10111011 +// CHECK-INST: stnt1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xbb,0xed,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a168edbb + +stnt1d {z19.d, z23.d, z27.d, z31.d}, pn15, [sp, #-4, mul vl] // 10100001-01101111-11111111-11111011 +// CHECK-INST: stnt1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfb,0xff,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16ffffb + diff --git a/llvm/test/MC/AArch64/SME2/stnt1h.s b/llvm/test/MC/AArch64/SME2/stnt1h.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/stnt1h.s @@ -0,0 +1,113 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +stnt1h {z0.h, z8.h}, pn8, [x0, x0, lsl #1] // 10100001-00100000-00100000-00001000 +// CHECK-INST: stnt1h { z0.h, z8.h }, pn8, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x08,0x20,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1202008 + +stnt1h {z21.h, z29.h}, pn13, [x10, x21, lsl #1] // 10100001-00110101-00110101-01011101 +// CHECK-INST: stnt1h { z21.h, z29.h }, pn13, [x10, x21, lsl #1] +// CHECK-ENCODING: [0x5d,0x35,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a135355d + +stnt1h {z23.h, z31.h}, pn11, [x13, x8, lsl #1] // 10100001-00101000-00101101-10111111 +// CHECK-INST: stnt1h { z23.h, z31.h }, pn11, [x13, x8, lsl #1] +// CHECK-ENCODING: [0xbf,0x2d,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1282dbf + +stnt1h {z23.h, z31.h}, pn15, [sp, xzr, lsl #1] // 10100001-00111111-00111111-11111111 +// CHECK-INST: stnt1h { z23.h, z31.h }, pn15, [sp, xzr, lsl #1] +// CHECK-ENCODING: [0xff,0x3f,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13f3fff + + +stnt1h {z0.h, z8.h}, pn8, [x0] // 10100001-01100000-00100000-00001000 +// CHECK-INST: stnt1h { z0.h, z8.h }, pn8, [x0] +// CHECK-ENCODING: [0x08,0x20,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1602008 + +stnt1h {z21.h, z29.h}, pn13, [x10, #10, mul vl] // 10100001-01100101-00110101-01011101 +// CHECK-INST: stnt1h { z21.h, z29.h }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x5d,0x35,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a165355d + +stnt1h {z23.h, z31.h}, pn11, [x13, #-16, mul vl] // 10100001-01101000-00101101-10111111 +// CHECK-INST: stnt1h { z23.h, z31.h }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xbf,0x2d,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1682dbf + +stnt1h {z23.h, z31.h}, pn15, [sp, #-2, mul vl] // 10100001-01101111-00111111-11111111 +// CHECK-INST: stnt1h { z23.h, z31.h }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0x3f,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16f3fff + + +stnt1h {z0.h, z4.h, z8.h, z12.h}, pn8, [x0, x0, lsl #1] // 10100001-00100000-10100000-00001000 +// CHECK-INST: stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x0, lsl #1] +// CHECK-ENCODING: [0x08,0xa0,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a120a008 + +stnt1h {z17.h, z21.h, z25.h, z29.h}, pn13, [x10, x21, lsl #1] // 10100001-00110101-10110101-01011001 +// CHECK-INST: stnt1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, x21, lsl #1] +// CHECK-ENCODING: [0x59,0xb5,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a135b559 + +stnt1h {z19.h, z23.h, z27.h, z31.h}, pn11, [x13, x8, lsl #1] // 10100001-00101000-10101101-10111011 +// CHECK-INST: stnt1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, x8, lsl #1] +// CHECK-ENCODING: [0xbb,0xad,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a128adbb + +stnt1h {z19.h, z23.h, z27.h, z31.h}, pn15, [sp, xzr, lsl #1] // 10100001-00111111-10111111-11111011 +// CHECK-INST: stnt1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, xzr, lsl #1] +// CHECK-ENCODING: [0xfb,0xbf,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13fbffb + + +stnt1h {z0.h, z4.h, z8.h, z12.h}, pn8, [x0] // 10100001-01100000-10100000-00001000 +// CHECK-INST: stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0] +// CHECK-ENCODING: [0x08,0xa0,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a160a008 + +stnt1h {z17.h, z21.h, z25.h, z29.h}, pn13, [x10, #20, mul vl] // 10100001-01100101-10110101-01011001 +// CHECK-INST: stnt1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x59,0xb5,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a165b559 + +stnt1h {z19.h, z23.h, z27.h, z31.h}, pn11, [x13, #-32, mul vl] // 10100001-01101000-10101101-10111011 +// CHECK-INST: stnt1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xbb,0xad,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a168adbb + +stnt1h {z19.h, z23.h, z27.h, z31.h}, pn15, [sp, #-4, mul vl] // 10100001-01101111-10111111-11111011 +// CHECK-INST: stnt1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfb,0xbf,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16fbffb + diff --git a/llvm/test/MC/AArch64/SME2/stnt1w.s b/llvm/test/MC/AArch64/SME2/stnt1w.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/stnt1w.s @@ -0,0 +1,115 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=-sme2 --no-print-imm-hex - \ +// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +stnt1w {z0.s, z8.s}, pn8, [x0, x0, lsl #2] // 10100001-00100000-01000000-00001000 +// CHECK-INST: stnt1w { z0.s, z8.s }, pn8, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x08,0x40,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1204008 + +stnt1w {z21.s, z29.s}, pn13, [x10, x21, lsl #2] // 10100001-00110101-01010101-01011101 +// CHECK-INST: stnt1w { z21.s, z29.s }, pn13, [x10, x21, lsl #2] +// CHECK-ENCODING: [0x5d,0x55,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a135555d + +stnt1w {z23.s, z31.s}, pn11, [x13, x8, lsl #2] // 10100001-00101000-01001101-10111111 +// CHECK-INST: stnt1w { z23.s, z31.s }, pn11, [x13, x8, lsl #2] +// CHECK-ENCODING: [0xbf,0x4d,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1284dbf + +stnt1w {z23.s, z31.s}, pn15, [sp, xzr, lsl #2] // 10100001-00111111-01011111-11111111 +// CHECK-INST: stnt1w { z23.s, z31.s }, pn15, [sp, xzr, lsl #2] +// CHECK-ENCODING: [0xff,0x5f,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13f5fff + + +stnt1w {z0.s, z8.s}, pn8, [x0] // 10100001-01100000-01000000-00001000 +// CHECK-INST: stnt1w { z0.s, z8.s }, pn8, [x0] +// CHECK-ENCODING: [0x08,0x40,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1604008 + +stnt1w {z21.s, z29.s}, pn13, [x10, #10, mul vl] // 10100001-01100101-01010101-01011101 +// CHECK-INST: stnt1w { z21.s, z29.s }, pn13, [x10, #10, mul vl] +// CHECK-ENCODING: [0x5d,0x55,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a165555d + +stnt1w {z23.s, z31.s}, pn11, [x13, #-16, mul vl] // 10100001-01101000-01001101-10111111 +// CHECK-INST: stnt1w { z23.s, z31.s }, pn11, [x13, #-16, mul vl] +// CHECK-ENCODING: [0xbf,0x4d,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a1684dbf + +stnt1w {z23.s, z31.s}, pn15, [sp, #-2, mul vl] // 10100001-01101111-01011111-11111111 +// CHECK-INST: stnt1w { z23.s, z31.s }, pn15, [sp, #-2, mul vl] +// CHECK-ENCODING: [0xff,0x5f,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16f5fff + + +stnt1w {z0.s, z4.s, z8.s, z12.s}, pn8, [x0, x0, lsl #2] // 10100001-00100000-11000000-00001000 +// CHECK-INST: stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x0, lsl #2] +// CHECK-ENCODING: [0x08,0xc0,0x20,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a120c008 + +stnt1w {z17.s, z21.s, z25.s, z29.s}, pn13, [x10, x21, lsl #2] // 10100001-00110101-11010101-01011001 +// CHECK-INST: stnt1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, x21, lsl #2] +// CHECK-ENCODING: [0x59,0xd5,0x35,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a135d559 + +stnt1w {z19.s, z23.s, z27.s, z31.s}, pn11, [x13, x8, lsl #2] // 10100001-00101000-11001101-10111011 +// CHECK-INST: stnt1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, x8, lsl #2] +// CHECK-ENCODING: [0xbb,0xcd,0x28,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a128cdbb + +stnt1w {z19.s, z23.s, z27.s, z31.s}, pn15, [sp, xzr, lsl #2] // 10100001-00111111-11011111-11111011 +// CHECK-INST: stnt1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, xzr, lsl #2] +// CHECK-ENCODING: [0xfb,0xdf,0x3f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a13fdffb + + +stnt1w {z0.s, z4.s, z8.s, z12.s}, pn8, [x0] // 10100001-01100000-11000000-00001000 +// CHECK-INST: stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0] +// CHECK-ENCODING: [0x08,0xc0,0x60,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a160c008 + +stnt1w {z17.s, z21.s, z25.s, z29.s}, pn13, [x10, #20, mul vl] // 10100001-01100101-11010101-01011001 +// CHECK-INST: stnt1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, #20, mul vl] +// CHECK-ENCODING: [0x59,0xd5,0x65,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a165d559 + +stnt1w {z19.s, z23.s, z27.s, z31.s}, pn11, [x13, #-32, mul vl] // 10100001-01101000-11001101-10111011 +// CHECK-INST: stnt1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, #-32, mul vl] +// CHECK-ENCODING: [0xbb,0xcd,0x68,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a168cdbb + +stnt1w {z19.s, z23.s, z27.s, z31.s}, pn15, [sp, #-4, mul vl] // 10100001-01101111-11011111-11111011 +// CHECK-INST: stnt1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, #-4, mul vl] +// CHECK-ENCODING: [0xfb,0xdf,0x6f,0xa1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: a16fdffb + diff --git a/llvm/test/MC/AArch64/SME2/sub-diagnostics.s b/llvm/test/MC/AArch64/SME2/sub-diagnostics.s --- a/llvm/test/MC/AArch64/SME2/sub-diagnostics.s +++ b/llvm/test/MC/AArch64/SME2/sub-diagnostics.s @@ -66,7 +66,7 @@ // Invalid vector list. sub za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d} -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: sub za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d} // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld2b-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld2b-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/ld2b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld2b-diagnostics.s @@ -81,7 +81,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld2b { z0.b, z2.b }, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: ld2b { z0.b, z2.b }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld2d-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld2d-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/ld2d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld2d-diagnostics.s @@ -86,7 +86,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld2d { z0.d, z2.d }, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: ld2d { z0.d, z2.d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld2h-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld2h-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/ld2h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld2h-diagnostics.s @@ -86,7 +86,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld2h { z0.h, z2.h }, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: ld2h { z0.h, z2.h }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld2w-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld2w-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/ld2w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld2w-diagnostics.s @@ -86,7 +86,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld2w { z0.s, z2.s }, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: ld2w { z0.s, z2.s }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld3b-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld3b-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/ld3b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld3b-diagnostics.s @@ -81,7 +81,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3b { z0.b, z1.b, z3.b }, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: ld3b { z0.b, z1.b, z3.b }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld3d-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld3d-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/ld3d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld3d-diagnostics.s @@ -86,7 +86,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3d { z0.d, z1.d, z3.d }, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: ld3d { z0.d, z1.d, z3.d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld3h-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld3h-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/ld3h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld3h-diagnostics.s @@ -86,7 +86,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3h { z0.h, z1.h, z3.h }, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: ld3h { z0.h, z1.h, z3.h }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld3w-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld3w-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/ld3w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld3w-diagnostics.s @@ -86,7 +86,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld3w { z0.s, z1.s, z3.s }, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: ld3w { z0.s, z1.s, z3.s }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld4b-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld4b-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/ld4b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld4b-diagnostics.s @@ -81,7 +81,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld4b { z0.b, z1.b, z3.b, z5.b }, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: ld4b { z0.b, z1.b, z3.b, z5.b }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld4d-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld4d-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/ld4d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld4d-diagnostics.s @@ -86,7 +86,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld4d { z0.d, z1.d, z3.d, z5.d }, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: ld4d { z0.d, z1.d, z3.d, z5.d }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld4h-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld4h-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/ld4h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld4h-diagnostics.s @@ -86,7 +86,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld4h { z0.h, z1.h, z3.h, z5.h }, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: ld4h { z0.h, z1.h, z3.h, z5.h }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/ld4w-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld4w-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/ld4w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/ld4w-diagnostics.s @@ -86,7 +86,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld4w { z0.s, z1.s, z3.s, z5.s }, p0/z, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: ld4w { z0.s, z1.s, z3.s, z5.s }, p0/z, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st2b-diagnostics.s b/llvm/test/MC/AArch64/SVE/st2b-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/st2b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st2b-diagnostics.s @@ -91,7 +91,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st2b { z0.b, z2.b }, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: st2b { z0.b, z2.b }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st2d-diagnostics.s b/llvm/test/MC/AArch64/SVE/st2d-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/st2d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st2d-diagnostics.s @@ -96,7 +96,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st2d { z0.d, z2.d }, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: st2d { z0.d, z2.d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st2h-diagnostics.s b/llvm/test/MC/AArch64/SVE/st2h-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/st2h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st2h-diagnostics.s @@ -96,7 +96,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st2h { z0.h, z2.h }, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: st2h { z0.h, z2.h }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st2w-diagnostics.s b/llvm/test/MC/AArch64/SVE/st2w-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/st2w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st2w-diagnostics.s @@ -96,7 +96,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st2w { z0.s, z2.s }, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: st2w { z0.s, z2.s }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st3b-diagnostics.s b/llvm/test/MC/AArch64/SVE/st3b-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/st3b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st3b-diagnostics.s @@ -91,7 +91,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st3b { z0.b, z1.b, z3.b }, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: st3b { z0.b, z1.b, z3.b }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st3d-diagnostics.s b/llvm/test/MC/AArch64/SVE/st3d-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/st3d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st3d-diagnostics.s @@ -96,7 +96,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st3d { z0.d, z1.d, z3.d }, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: st3d { z0.d, z1.d, z3.d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st3h-diagnostics.s b/llvm/test/MC/AArch64/SVE/st3h-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/st3h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st3h-diagnostics.s @@ -96,7 +96,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st3h { z0.h, z1.h, z3.h }, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: st3h { z0.h, z1.h, z3.h }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st3w-diagnostics.s b/llvm/test/MC/AArch64/SVE/st3w-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/st3w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st3w-diagnostics.s @@ -96,7 +96,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st3w { z0.s, z1.s, z3.s }, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: st3w { z0.s, z1.s, z3.s }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st4b-diagnostics.s b/llvm/test/MC/AArch64/SVE/st4b-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/st4b-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st4b-diagnostics.s @@ -91,7 +91,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st4b { z0.b, z1.b, z3.b, z5.b }, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: st4b { z0.b, z1.b, z3.b, z5.b }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st4d-diagnostics.s b/llvm/test/MC/AArch64/SVE/st4d-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/st4d-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st4d-diagnostics.s @@ -96,7 +96,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st4d { z0.d, z1.d, z3.d, z5.d }, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: st4d { z0.d, z1.d, z3.d, z5.d }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st4h-diagnostics.s b/llvm/test/MC/AArch64/SVE/st4h-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/st4h-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st4h-diagnostics.s @@ -96,7 +96,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE/st4w-diagnostics.s b/llvm/test/MC/AArch64/SVE/st4w-diagnostics.s --- a/llvm/test/MC/AArch64/SVE/st4w-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE/st4w-diagnostics.s @@ -96,7 +96,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride // CHECK-NEXT: st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/ext-diagnostics.s b/llvm/test/MC/AArch64/SVE2/ext-diagnostics.s --- a/llvm/test/MC/AArch64/SVE2/ext-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2/ext-diagnostics.s @@ -58,7 +58,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ext z0.b, { z1.b, z31.b }, #0 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: ext z0.b, { z1.b, z31.b }, #0 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/splice-diagnostics.s b/llvm/test/MC/AArch64/SVE2/splice-diagnostics.s --- a/llvm/test/MC/AArch64/SVE2/splice-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2/splice-diagnostics.s @@ -34,7 +34,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: splice z0.b, p0, { z1.b, z31.b } -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: splice z0.b, p0, { z1.b, z31.b } // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2/tbl-diagnostics.s b/llvm/test/MC/AArch64/SVE2/tbl-diagnostics.s --- a/llvm/test/MC/AArch64/SVE2/tbl-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2/tbl-diagnostics.s @@ -25,7 +25,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: tbl z0.d, { z1.d, z21.d }, z3.d -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: tbl z0.d, { z1.d, z21.d }, z3.d // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p1/pext-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/pext-diagnostics.s --- a/llvm/test/MC/AArch64/SVE2p1/pext-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2p1/pext-diagnostics.s @@ -4,12 +4,12 @@ // Invalid vector lists pext {p0.h, p2.h}, pn8[0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: pext {p0.h, p2.h}, pn8[0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: pext {p15.h, p1.h}, pn8[0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: pext {p15.h, p1.h}, pn8[0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s --- a/llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2p1/whilege-diagnostics.s @@ -30,7 +30,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: whilege { p0.b, p2.b }, x13, x8 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: whilege { p0.b, p2.b }, x13, x8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p1/whilegt-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilegt-diagnostics.s --- a/llvm/test/MC/AArch64/SVE2p1/whilegt-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2p1/whilegt-diagnostics.s @@ -30,7 +30,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: whilegt { p0.b, p2.b }, x13, x8 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: whilegt { p0.b, p2.b }, x13, x8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p1/whilehi-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilehi-diagnostics.s --- a/llvm/test/MC/AArch64/SVE2p1/whilehi-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2p1/whilehi-diagnostics.s @@ -30,7 +30,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: whilehi { p0.b, p2.b }, x13, x8 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: whilehi { p0.b, p2.b }, x13, x8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p1/whilehs-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilehs-diagnostics.s --- a/llvm/test/MC/AArch64/SVE2p1/whilehs-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2p1/whilehs-diagnostics.s @@ -30,7 +30,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: whilehs { p0.b, p2.b }, x13, x8 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: whilehs { p0.b, p2.b }, x13, x8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p1/whilele-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilele-diagnostics.s --- a/llvm/test/MC/AArch64/SVE2p1/whilele-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2p1/whilele-diagnostics.s @@ -30,7 +30,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: whilele { p0.b, p2.b }, x13, x8 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: whilele { p0.b, p2.b }, x13, x8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p1/whilelo-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilelo-diagnostics.s --- a/llvm/test/MC/AArch64/SVE2p1/whilelo-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2p1/whilelo-diagnostics.s @@ -30,7 +30,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: whilelo { p0.b, p2.b }, x13, x8 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: whilelo { p0.b, p2.b }, x13, x8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p1/whilels-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilels-diagnostics.s --- a/llvm/test/MC/AArch64/SVE2p1/whilels-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2p1/whilels-diagnostics.s @@ -30,7 +30,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: whilels { p0.b, p2.b }, x13, x8 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: whilels { p0.b, p2.b }, x13, x8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SVE2p1/whilelt-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/whilelt-diagnostics.s --- a/llvm/test/MC/AArch64/SVE2p1/whilelt-diagnostics.s +++ b/llvm/test/MC/AArch64/SVE2p1/whilelt-diagnostics.s @@ -30,7 +30,7 @@ // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: whilelt { p0.b, p2.b }, x13, x8 -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction // CHECK-NEXT: whilelt { p0.b, p2.b }, x13, x8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/neon-diagnostics.s b/llvm/test/MC/AArch64/neon-diagnostics.s --- a/llvm/test/MC/AArch64/neon-diagnostics.s +++ b/llvm/test/MC/AArch64/neon-diagnostics.s @@ -3877,7 +3877,7 @@ ld1 {v1.8h-v1.8h}, [x0] ld1 {v15.8h-v17.4h}, [x15] ld1 {v0.8b-v2.8b, [x0] -// CHECK-ERROR: error: registers must be sequential +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld1 {v0.16b, v2.16b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors @@ -3907,7 +3907,7 @@ // CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld2 {v15.8h, v16.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: registers must be sequential +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: ld2 {v0.8b, v2.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: ld2 {v15.4h, v16.4h, v17.4h}, [x32] @@ -3930,7 +3930,7 @@ // CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: registers must be sequential +// CHECK-ERROR: error: registers must have the same sequential stride // CHECK-ERROR: ld3 {v0.8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: mismatched register size suffix @@ -3948,7 +3948,7 @@ // CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: ld4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: registers must be sequential +// CHECK-ERROR: error: registers must have the same sequential stride // CHECK-ERROR: ld4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors @@ -3985,7 +3985,7 @@ st1 {v1.8h-v1.8h}, [x0] st1 {v15.8h-v17.4h}, [x15] st1 {v0.8b-v2.8b, [x0] -// CHECK-ERROR: error: registers must be sequential +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st1 {v0.16b, v2.16b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors @@ -4015,7 +4015,7 @@ // CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st2 {v15.8h, v16.4h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: registers must be sequential +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR: st2 {v0.8b, v2.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid operand for instruction @@ -4039,7 +4039,7 @@ // CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ -// CHECK-ERROR: error: registers must be sequential +// CHECK-ERROR: error: registers must have the same sequential stride // CHECK-ERROR: st3 {v0.8b, v2.8b, v3.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: mismatched register size suffix @@ -4057,7 +4057,7 @@ // CHECK-ERROR: error: mismatched register size suffix // CHECK-ERROR: st4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15] // CHECK-ERROR: ^ -// CHECK-ERROR: error: registers must be sequential +// CHECK-ERROR: error: registers must have the same sequential stride // CHECK-ERROR: st4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0] // CHECK-ERROR: ^ // CHECK-ERROR: error: invalid number of vectors