diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36981,6 +36981,15 @@
     MI.eraseFromParent(); // The pseudo is gone now.
     return BB;
   }
+  case X86::PREFETCHIT0:
+  case X86::PREFETCHIT1:
+    // PREFETCHIT0/1 apply when in 64-bit mode with RIP-relative addressing.
+    // They stay NOPs otherwise, so optimize them to PREFETCHT0/1.
+    if (MI.getOperand(0).getReg() != X86::RIP)
+      MI.setDesc(TII->get(MI.getOpcode() == X86::PREFETCHIT0
+                              ? X86::PREFETCHT0
+                              : X86::PREFETCHT1));
+    return BB;
   }
 }
 
diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -3002,7 +3002,8 @@
 //===----------------------------------------------------------------------===//
 // PREFETCHIT0 and PREFETCHIT1 Instructions
 // prefetch ADDR, RW, Locality, Data
-let Predicates = [HasPREFETCHI, In64BitMode], SchedRW = [WriteLoad] in {
+let Predicates = [HasPREFETCHI, In64BitMode], SchedRW = [WriteLoad],
+    usesCustomInserter = 1 in {
   def PREFETCHIT0 : I<0x18, MRM7m, (outs), (ins i8mem:$src),
     "prefetchit0\t$src", [(prefetch addr:$src, (i32 0), (i32 3), (i32 0))]>, TB;
   def PREFETCHIT1 : I<0x18, MRM6m, (outs), (ins i8mem:$src),
diff --git a/llvm/test/CodeGen/X86/prefetchi.ll b/llvm/test/CodeGen/X86/prefetchi.ll
--- a/llvm/test/CodeGen/X86/prefetchi.ll
+++ b/llvm/test/CodeGen/X86/prefetchi.ll
@@ -4,8 +4,8 @@
 define dso_local void @t(ptr %ptr) nounwind  {
 ; CHECK-LABEL: t:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    prefetchit1 (%rdi)
-; CHECK-NEXT:    prefetchit0 (%rdi)
+; CHECK-NEXT:    prefetcht1 (%rdi)
+; CHECK-NEXT:    prefetcht0 (%rdi)
 ; CHECK-NEXT:    prefetchit1 t(%rip)
 ; CHECK-NEXT:    prefetchit0 ext(%rip)
 ; CHECK-NEXT:    retq