diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -272,6 +272,8 @@ defm SQDMULH_2ZZ : sme2_sqdmulh_add_vector_vg2_single<"sqdmulh", 0b100000>; defm SQDMULH_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"sqdmulh", 0b100000>; +defm SQDMULH_2Z2Z : sme2_sqdmulh_vector_vg2_multi<"sqdmulh">; +defm SQDMULH_4Z4Z : sme2_sqdmulh_vector_vg4_multi<"sqdmulh">; defm FMLAL_MZZI : sme2_mla_long_array_index<"fmlal", 0b10, 0b00>; defm FMLAL_VG2_M2ZZI : sme2_fp_mla_long_array_vg2_index<"fmlal", 0b00>; @@ -441,6 +443,29 @@ defm EXTRACT_VG2_2ZMI : sme2_mova_array_to_vec_vg2_multi<"mova">; defm EXTRACT_VG4_4ZMI : sme2_mova_array_to_vec_vg4_multi<"mova">; +def SQRSHR_Z2ZI : sme2_sat_shift_vector_vg2<"sqrshr", 0b0, 0b0>; +defm SQRSHR_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshr", 0b000>; + +def UQRSHR_Z2ZI : sme2_sat_shift_vector_vg2<"uqrshr", 0b0, 0b1>; +defm UQRSHR_Z4ZI : sme2_sat_shift_vector_vg4<"uqrshr", 0b001>; + +def SQRSHRU_Z2ZI : sme2_sat_shift_vector_vg2<"sqrshru", 0b1, 0b0>; +defm SQRSHRU_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshru", 0b010>; + +defm SQRSHRN_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshrn", 0b100>; +defm UQRSHRN_Z4ZI : sme2_sat_shift_vector_vg4<"uqrshrn", 0b101>; +defm SQRSHRUN_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshrun", 0b110>; + +defm SRSHL_2ZZ: sme2_shift_vector_vg2_single<"srshl", 0b0010>; +defm SRSHL_4ZZ: sme2_shift_vector_vg4_single<"srshl", 0b0010>; +defm SRSHL_2Z4Z: sme2_shift_vector_vg2_multi<"srshl", 0b0010>; +defm SRSHL_4Z4Z: sme2_shift_vector_vg4_multi<"srshl", 0b0010>; + +defm URSHL_2ZZ: sme2_shift_vector_vg2_single<"urshl", 0b0011>; +defm URSHL_4ZZ: sme2_shift_vector_vg4_single<"urshl", 0b0011>; +defm URSHL_2Z4Z: sme2_shift_vector_vg2_multi<"urshl", 0b0011>; +defm URSHL_4Z4Z: sme2_shift_vector_vg4_multi<"urshl", 0b0011>; + } diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -3195,3 +3195,270 @@ MatrixIndexGPR32Op8_11, sme_elm_idx0_7, "mov", "vgx4">; } + +//===----------------------------------------------------------------------===// +// SME2 multi-vec saturating shift right narrow +class sme2_sat_shift_vector_vg2 + : I<(outs ZPR16:$Zd), (ins ZZ_s_mul_r:$Zn, vecshiftR16:$imm4), + mnemonic, "\t$Zd, $Zn, $imm4", + "", []>, Sched<[]> { + bits<4> imm4; + bits<4> Zn; + bits<5> Zd; + let Inst{31-21} = 0b11000001111; + let Inst{20} = op; + let Inst{19-16} = imm4; + let Inst{15-10} = 0b110101; + let Inst{9-6} = Zn; + let Inst{5} = u; + let Inst{4-0} = Zd; +} + +class sme2_sat_shift_vector_vg4 op, + ZPRRegOp zpr_ty, RegisterOperand vector_ty, + Operand imm_ty, string mnemonic> + : I<(outs zpr_ty:$Zd), (ins vector_ty:$Zn, imm_ty:$imm), + mnemonic, "\t$Zd, $Zn, $imm", + "", []>, Sched<[]> { + bits<3> Zn; + bits<5> Zd; + let Inst{31-24} = 0b11000001; + let Inst{21} = 0b1; + let Inst{15-11} = 0b11011; + let Inst{10} = n; + let Inst{9-7} = Zn; + let Inst{6-5} = op; + let Inst{4-0} = Zd; +} + +multiclass sme2_sat_shift_vector_vg4 op> { + def _B : sme2_sat_shift_vector_vg4{ + bits<5> imm; + let Inst{23-22} = 0b01; + let Inst{20-16} = imm; + } + def _H : sme2_sat_shift_vector_vg4 { + bits<6> imm; + let Inst{23} = 0b1; + let Inst{22} = imm{5}; + let Inst{20-16} = imm{4-0}; + } +} +//===----------------------------------------------------------------------===// +// SME2 shift registers +class sme2_shift_vector_vg2_single sz, bits<3>opc, bit u, + RegisterOperand vector_ty, ZPRRegOp zpr_ty, + string mnemonic> + : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, zpr_ty:$Zm), + mnemonic, "\t$Zdn, $_Zdn, $Zm", + "", []>, Sched<[]> { + bits<4> Zm; + bits<4> Zdn; + let Inst{31-24} = 0b11000001; + let Inst{23-22} = sz; + let Inst{21-20} = 0b10; + let Inst{19-16} = Zm; + let Inst{15-8} = 0b10100010; + let Inst{7-5} = opc; + let Inst{4-1} = Zdn; + let Inst{0} = u; + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sme2_shift_vector_vg2_single opc> { + def _B : sme2_shift_vector_vg2_single<0b00, opc{3-1}, opc{0}, + ZZ_b_mul_r, ZPR4b8, mnemonic>; + def _H : sme2_shift_vector_vg2_single<0b01, opc{3-1}, opc{0}, + ZZ_h_mul_r, ZPR4b16, mnemonic>; + def _S : sme2_shift_vector_vg2_single<0b10, opc{3-1}, opc{0}, + ZZ_s_mul_r, ZPR4b32, mnemonic>; + def _D : sme2_shift_vector_vg2_single<0b11, opc{3-1}, opc{0}, + ZZ_d_mul_r, ZPR4b64, mnemonic>; +} +class sme2_shift_vector_vg4_single sz, bits<3>opc, bit u, + RegisterOperand vector_ty, ZPRRegOp zpr_ty, + string mnemonic> + : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, zpr_ty:$Zm), + mnemonic, "\t$Zdn, $_Zdn, $Zm", + "", []>, Sched<[]> { + bits<4> Zm; + bits<3> Zdn; + let Inst{31-24} = 0b11000001; + let Inst{23-22} = sz; + let Inst{21-20} = 0b10; + let Inst{19-16} = Zm; + let Inst{15-8} = 0b10101010; + let Inst{7-5} = opc; + let Inst{4-2} = Zdn; + let Inst{1} = 0b0; + let Inst{0} = u; + let Constraints = "$Zdn = $_Zdn"; +} +multiclass sme2_shift_vector_vg4_single opc> { + def _B : sme2_shift_vector_vg4_single<0b00, opc{3-1}, opc{0}, + ZZZZ_b_mul_r, ZPR4b8, mnemonic>; + def _H : sme2_shift_vector_vg4_single<0b01, opc{3-1}, opc{0}, + ZZZZ_h_mul_r, ZPR4b16, mnemonic>; + def _S : sme2_shift_vector_vg4_single<0b10, opc{3-1}, opc{0}, + ZZZZ_s_mul_r, ZPR4b32, mnemonic>; + def _D : sme2_shift_vector_vg4_single<0b11, opc{3-1}, opc{0}, + ZZZZ_d_mul_r, ZPR4b64, mnemonic>; +} +class sme2_shift_vector_vg2_multi sz, bits<3>opc, bit u, + RegisterOperand vector_ty, + string mnemonic> + : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, vector_ty:$Zm), + mnemonic, "\t$Zdn, $_Zdn, $Zm", + "", []>, Sched<[]> { + bits<4> Zm; + bits<4> Zdn; + let Inst{31-24} = 0b11000001; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{20-17} = Zm; + let Inst{16-8} = 0b010110010; + let Inst{7-5} = opc; + let Inst{4-1} = Zdn; + let Inst{0} = u; + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sme2_shift_vector_vg2_multi opc> { + def _B : sme2_shift_vector_vg2_multi<0b00, opc{3-1}, opc{0}, ZZ_b_mul_r, + mnemonic>; + def _H : sme2_shift_vector_vg2_multi<0b01, opc{3-1}, opc{0}, ZZ_h_mul_r, + mnemonic>; + def _S : sme2_shift_vector_vg2_multi<0b10, opc{3-1}, opc{0}, ZZ_s_mul_r, + mnemonic>; + def _D : sme2_shift_vector_vg2_multi<0b11, opc{3-1}, opc{0}, ZZ_d_mul_r, + mnemonic>; +} + +class sme2_shift_vector_vg4_multi sz, bits<3>opc, bit u, + RegisterOperand vector_ty, + string mnemonic> + : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, vector_ty:$Zm), + mnemonic, "\t$Zdn, $_Zdn, $Zm", + "", []>, Sched<[]> { + bits<3> Zm; + bits<3> Zdn; + let Inst{31-24} = 0b11000001; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{20-18} = Zm; + let Inst{17-8} = 0b0010111010; + let Inst{7-5} = opc; + let Inst{4-2} = Zdn; + let Inst{1} = 0b0; + let Inst{0} = u; + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sme2_shift_vector_vg4_multi opc> { + def _B : sme2_shift_vector_vg4_multi<0b00, opc{3-1}, opc{0}, ZZZZ_b_mul_r, + mnemonic>; + def _H : sme2_shift_vector_vg4_multi<0b01, opc{3-1}, opc{0}, ZZZZ_h_mul_r, + mnemonic>; + def _S : sme2_shift_vector_vg4_multi<0b10, opc{3-1}, opc{0}, ZZZZ_s_mul_r, + mnemonic>; + def _D : sme2_shift_vector_vg4_multi<0b11, opc{3-1}, opc{0}, ZZZZ_d_mul_r, + mnemonic>; +} + +//===----------------------------------------------------------------------===// +// SME2 signed saturating doubling multiply high +class sme2_sqdmulh_vector_vg2_single sz, RegisterOperand vector_ty, + ZPRRegOp zpr_ty, string mnemonic> + : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, zpr_ty:$Zm), + mnemonic, "\t$Zdn, $_Zdn, $Zm", + "", []>, Sched<[]> { + bits<4> Zm; + bits<4> Zdn; + let Inst{31-24} = 0b11000001; + let Inst{23-22} = sz; + let Inst{21-20} = 0b10; + let Inst{19-16} = Zm; + let Inst{15-5} = 0b10100100000; + let Inst{4-1} = Zdn; + let Inst{0} = 0b0; + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sme2_sqdmulh_vector_vg2_single { + def _B : sme2_sqdmulh_vector_vg2_single<0b00, ZZ_b_mul_r, ZPR4b8, mnemonic>; + def _H : sme2_sqdmulh_vector_vg2_single<0b01, ZZ_h_mul_r, ZPR4b16, mnemonic>; + def _S : sme2_sqdmulh_vector_vg2_single<0b10, ZZ_s_mul_r, ZPR4b32, mnemonic>; + def _D : sme2_sqdmulh_vector_vg2_single<0b11, ZZ_d_mul_r, ZPR4b64, mnemonic>; +} +class sme2_sqdmulh_vector_vg4_single sz, RegisterOperand vector_ty, + ZPRRegOp zpr_ty, string mnemonic> + : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, zpr_ty:$Zm), + mnemonic, "\t$Zdn, $_Zdn, $Zm", + "", []>, Sched<[]> { + bits<4> Zm; + bits<3> Zdn; + let Inst{31-24} = 0b11000001; + let Inst{23-22} = sz; + let Inst{21-20} = 0b10; + let Inst{19-16} = Zm; + let Inst{15-5} = 0b10101100000; + let Inst{4-2} = Zdn; + let Inst{1-0} = 0b00; + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sme2_sqdmulh_vector_vg4_single { + def _B : sme2_sqdmulh_vector_vg4_single<0b00, ZZZZ_b_mul_r, ZPR4b8, mnemonic>; + def _H : sme2_sqdmulh_vector_vg4_single<0b01, ZZZZ_h_mul_r, ZPR4b16, mnemonic>; + def _S : sme2_sqdmulh_vector_vg4_single<0b10, ZZZZ_s_mul_r, ZPR4b32, mnemonic>; + def _D : sme2_sqdmulh_vector_vg4_single<0b11, ZZZZ_d_mul_r, ZPR4b64, mnemonic>; +} + +class sme2_sqdmulh_vector_vg2_multi sz, RegisterOperand vector_ty, + string mnemonic> + : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, vector_ty:$Zm), + mnemonic, "\t$Zdn, $_Zdn, $Zm", + "", []>, Sched<[]> { + bits<4> Zm; + bits<4> Zdn; + let Inst{31-24} = 0b11000001; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{20-17} = Zm; + let Inst{16-5} = 0b010110100000; + let Inst{4-1} = Zdn; + let Inst{0} = 0b0; + let Constraints = "$Zdn = $_Zdn"; +} +multiclass sme2_sqdmulh_vector_vg2_multi { + def _B : sme2_sqdmulh_vector_vg2_multi<0b00, ZZ_b_mul_r, mnemonic>; + def _H : sme2_sqdmulh_vector_vg2_multi<0b01, ZZ_h_mul_r, mnemonic>; + def _S : sme2_sqdmulh_vector_vg2_multi<0b10, ZZ_s_mul_r, mnemonic>; + def _D : sme2_sqdmulh_vector_vg2_multi<0b11, ZZ_d_mul_r, mnemonic>; +} + +class sme2_sqdmulh_vector_vg4_multi sz, RegisterOperand vector_ty, + string mnemonic> + : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, vector_ty:$Zm), + mnemonic, "\t$Zdn, $_Zdn, $Zm", + "", []>, Sched<[]> { + bits<3> Zm; + bits<3> Zdn; + let Inst{31-24} = 0b11000001; + let Inst{23-22} = sz; + let Inst{21} = 0b1; + let Inst{20-18} = Zm; + let Inst{17-5} = 0b0010111100000; + let Inst{4-2} = Zdn; + let Inst{1-0} = 0b00; + let Constraints = "$Zdn = $_Zdn"; +} + +multiclass sme2_sqdmulh_vector_vg4_multi { + def _B : sme2_sqdmulh_vector_vg4_multi<0b00, ZZZZ_b_mul_r, mnemonic>; + def _H : sme2_sqdmulh_vector_vg4_multi<0b01, ZZZZ_h_mul_r, mnemonic>; + def _S : sme2_sqdmulh_vector_vg4_multi<0b10, ZZZZ_s_mul_r, mnemonic>; + def _D : sme2_sqdmulh_vector_vg4_multi<0b11, ZZZZ_d_mul_r, mnemonic>; +} diff --git a/llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s b/llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s --- a/llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s +++ b/llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i64 2>&1 < %s | FileCheck %s +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s // --------------------------------------------------------------------------// // Invalid vector list @@ -23,11 +23,6 @@ // CHECK-NEXT: sqdmulh {z28.b-z29.b}, {z1.b-z2.b}, z15.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: -sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types -// CHECK-NEXT: sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - // --------------------------------------------------------------------------// // Invalid single vector register @@ -48,32 +43,3 @@ // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix // CHECK-NEXT: sqdmulh {z0.d-z3.h}, {z0.d-z3.d}, z0.b // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -// --------------------------------------------------------------------------// -// The tied operands must match, even for vector groups. - -sqdmulh {z0.s-z1.s}, {z2.s-z3.s}, z15.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list -// CHECK-NEXT: sqdmulh {z0.s-z1.s}, {z2.s-z3.s}, z15.s -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -sqdmulh {z0.s,z1.s}, {z2.s,z3.s}, z15.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list -// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z2.s,z3.s}, z15.s -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -sqdmulh {z0.s,z1.s}, {z0.s,z2.s}, z15.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential -// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.s,z2.s}, z15.s -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -sqdmulh {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - -sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction -// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - diff --git a/llvm/test/MC/AArch64/SME2/sqdmulh.s b/llvm/test/MC/AArch64/SME2/sqdmulh.s --- a/llvm/test/MC/AArch64/SME2/sqdmulh.s +++ b/llvm/test/MC/AArch64/SME2/sqdmulh.s @@ -37,6 +37,31 @@ // CHECK-UNKNOWN: c16fa41e +sqdmulh {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110100-00000000 +// CHECK-INST: sqdmulh { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x00,0xb4,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160b400 + +sqdmulh {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110100-00010100 +// CHECK-INST: sqdmulh { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x14,0xb4,0x74,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c174b414 + +sqdmulh {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110100-00010110 +// CHECK-INST: sqdmulh { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h } +// CHECK-ENCODING: [0x16,0xb4,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168b416 + +sqdmulh {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110100-00011110 +// CHECK-INST: sqdmulh { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0x1e,0xb4,0x7e,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17eb41e + + sqdmulh {z0.s - z1.s}, {z0.s - z1.s}, z0.s // 11000001-10100000-10100100-00000000 // CHECK-INST: sqdmulh { z0.s, z1.s }, { z0.s, z1.s }, z0.s // CHECK-ENCODING: [0x00,0xa4,0xa0,0xc1] @@ -62,6 +87,31 @@ // CHECK-UNKNOWN: c1afa41e +sqdmulh {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110100-00000000 +// CHECK-INST: sqdmulh { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s } +// CHECK-ENCODING: [0x00,0xb4,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0b400 + +sqdmulh {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110100-00010100 +// CHECK-INST: sqdmulh { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s } +// CHECK-ENCODING: [0x14,0xb4,0xb4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1b4b414 + +sqdmulh {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110100-00010110 +// CHECK-INST: sqdmulh { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s } +// CHECK-ENCODING: [0x16,0xb4,0xa8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a8b416 + +sqdmulh {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110100-00011110 +// CHECK-INST: sqdmulh { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s } +// CHECK-ENCODING: [0x1e,0xb4,0xbe,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1beb41e + + sqdmulh {z0.d - z1.d}, {z0.d - z1.d}, z0.d // 11000001-11100000-10100100-00000000 // CHECK-INST: sqdmulh { z0.d, z1.d }, { z0.d, z1.d }, z0.d // CHECK-ENCODING: [0x00,0xa4,0xe0,0xc1] @@ -87,6 +137,31 @@ // CHECK-UNKNOWN: c1efa41e +sqdmulh {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110100-00000000 +// CHECK-INST: sqdmulh { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d } +// CHECK-ENCODING: [0x00,0xb4,0xe0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e0b400 + +sqdmulh {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110100-00010100 +// CHECK-INST: sqdmulh { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d } +// CHECK-ENCODING: [0x14,0xb4,0xf4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f4b414 + +sqdmulh {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110100-00010110 +// CHECK-INST: sqdmulh { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d } +// CHECK-ENCODING: [0x16,0xb4,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8b416 + +sqdmulh {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110100-00011110 +// CHECK-INST: sqdmulh { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d } +// CHECK-ENCODING: [0x1e,0xb4,0xfe,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1feb41e + + sqdmulh {z0.b - z1.b}, {z0.b - z1.b}, z0.b // 11000001-00100000-10100100-00000000 // CHECK-INST: sqdmulh { z0.b, z1.b }, { z0.b, z1.b }, z0.b // CHECK-ENCODING: [0x00,0xa4,0x20,0xc1] @@ -111,6 +186,30 @@ // CHECK-ERROR: instruction requires: sme2 // CHECK-UNKNOWN: c12fa41e +sqdmulh {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b} // 11000001-00100000-10110100-00000000 +// CHECK-INST: sqdmulh { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b } +// CHECK-ENCODING: [0x00,0xb4,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c120b400 + +sqdmulh {z20.b - z21.b}, {z20.b - z21.b}, {z20.b - z21.b} // 11000001-00110100-10110100-00010100 +// CHECK-INST: sqdmulh { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x14,0xb4,0x34,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c134b414 + +sqdmulh {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b} // 11000001-00101000-10110100-00010110 +// CHECK-INST: sqdmulh { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b } +// CHECK-ENCODING: [0x16,0xb4,0x28,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c128b416 + +sqdmulh {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b} // 11000001-00111110-10110100-00011110 +// CHECK-INST: sqdmulh { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0x1e,0xb4,0x3e,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c13eb41e + sqdmulh {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101100-00000000 // CHECK-INST: sqdmulh { z0.h - z3.h }, { z0.h - z3.h }, z0.h @@ -137,6 +236,31 @@ // CHECK-UNKNOWN: c16fac1c +sqdmulh {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111100-00000000 +// CHECK-INST: sqdmulh { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x00,0xbc,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160bc00 + +sqdmulh {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111100-00010100 +// CHECK-INST: sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x14,0xbc,0x74,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c174bc14 + +sqdmulh {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111100-00010100 +// CHECK-INST: sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x14,0xbc,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168bc14 + +sqdmulh {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111100-00011100 +// CHECK-INST: sqdmulh { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x1c,0xbc,0x7c,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17cbc1c + + sqdmulh {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101100-00000000 // CHECK-INST: sqdmulh { z0.s - z3.s }, { z0.s - z3.s }, z0.s // CHECK-ENCODING: [0x00,0xac,0xa0,0xc1] @@ -161,6 +285,30 @@ // CHECK-ERROR: instruction requires: sme2 // CHECK-UNKNOWN: c1afac1c +sqdmulh {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111100-00000000 +// CHECK-INST: sqdmulh { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s } +// CHECK-ENCODING: [0x00,0xbc,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0bc00 + +sqdmulh {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111100-00010100 +// CHECK-INST: sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s } +// CHECK-ENCODING: [0x14,0xbc,0xb4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1b4bc14 + +sqdmulh {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111100-00010100 +// CHECK-INST: sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s } +// CHECK-ENCODING: [0x14,0xbc,0xa8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a8bc14 + +sqdmulh {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111100-00011100 +// CHECK-INST: sqdmulh { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s } +// CHECK-ENCODING: [0x1c,0xbc,0xbc,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1bcbc1c + sqdmulh {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101100-00000000 // CHECK-INST: sqdmulh { z0.d - z3.d }, { z0.d - z3.d }, z0.d @@ -187,6 +335,29 @@ // CHECK-UNKNOWN: c1efac1c +sqdmulh {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111100-00000000 +// CHECK-INST: sqdmulh { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d } +// CHECK-ENCODING: [0x00,0xbc,0xe0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e0bc00 + +sqdmulh {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111100-00010100 +// CHECK-INST: sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d } +// CHECK-ENCODING: [0x14,0xbc,0xf4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f4bc14 + +sqdmulh {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111100-00010100 +// CHECK-INST: sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d } +// CHECK-ENCODING: [0x14,0xbc,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8bc14 + +sqdmulh {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111100-00011100 +// CHECK-INST: sqdmulh { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d } +// CHECK-ENCODING: [0x1c,0xbc,0xfc,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1fcbc1c sqdmulh {z0.b - z3.b}, {z0.b - z3.b}, z0.b // 11000001-00100000-10101100-00000000 // CHECK-INST: sqdmulh { z0.b - z3.b }, { z0.b - z3.b }, z0.b // CHECK-ENCODING: [0x00,0xac,0x20,0xc1] @@ -210,3 +381,27 @@ // CHECK-ENCODING: [0x1c,0xac,0x2f,0xc1] // CHECK-ERROR: instruction requires: sme2 // CHECK-UNKNOWN: c12fac1c + +sqdmulh {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b} // 11000001-00100000-10111100-00000000 +// CHECK-INST: sqdmulh { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b } +// CHECK-ENCODING: [0x00,0xbc,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c120bc00 + +sqdmulh {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b} // 11000001-00110100-10111100-00010100 +// CHECK-INST: sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b } +// CHECK-ENCODING: [0x14,0xbc,0x34,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c134bc14 + +sqdmulh {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b} // 11000001-00101000-10111100-00010100 +// CHECK-INST: sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b } +// CHECK-ENCODING: [0x14,0xbc,0x28,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c128bc14 + +sqdmulh {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b} // 11000001-00111100-10111100-00011100 +// CHECK-INST: sqdmulh { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b } +// CHECK-ENCODING: [0x1c,0xbc,0x3c,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c13cbc1c diff --git a/llvm/test/MC/AArch64/SME2/sqrshr-diagnostics.s b/llvm/test/MC/AArch64/SME2/sqrshr-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/sqrshr-diagnostics.s @@ -0,0 +1,55 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +sqrshr z0.b, {z0.s-z4.s}, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: sqrshr z0.b, {z0.s-z4.s}, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshr z0.h, {z10.s-z12.s}, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrshr z0.h, {z10.s-z12.s}, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshr z0.h, {z1.d-z4.d}, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: sqrshr z0.h, {z1.d-z4.d}, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshr z0.h, {z1.s-z2.s}, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: sqrshr z0.h, {z1.s-z2.s}, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate + +sqrshr z31.h, {z28.d-z31.d}, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]. +// CHECK-NEXT: sqrshr z31.h, {z28.d-z31.d}, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshr z31.h, {z28.s-z29.s}, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: sqrshr z31.h, {z28.s-z29.s}, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshr z31.b, {z28.s-z31.s}, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]. +// CHECK-NEXT: sqrshr z31.b, {z28.s-z31.s}, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +sqrshr z23.s, {z12.s-z15.s}, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshr z23.s, {z12.s-z15.s}, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshr z23.b, {z12.d-z15.d}, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: sqrshr z23.b, {z12.d-z15.d}, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/sqrshr.s b/llvm/test/MC/AArch64/SME2/sqrshr.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/sqrshr.s @@ -0,0 +1,88 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +sqrshr z0.h, {z0.s - z1.s}, #16 // 11000001-11100000-11010100-00000000 +// CHECK-INST: sqrshr z0.h, { z0.s, z1.s }, #16 +// CHECK-ENCODING: [0x00,0xd4,0xe0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e0d400 + +sqrshr z21.h, {z10.s - z11.s}, #11 // 11000001-11100101-11010101-01010101 +// CHECK-INST: sqrshr z21.h, { z10.s, z11.s }, #11 +// CHECK-ENCODING: [0x55,0xd5,0xe5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e5d555 + +sqrshr z23.h, {z12.s - z13.s}, #8 // 11000001-11101000-11010101-10010111 +// CHECK-INST: sqrshr z23.h, { z12.s, z13.s }, #8 +// CHECK-ENCODING: [0x97,0xd5,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8d597 + +sqrshr z31.h, {z30.s - z31.s}, #1 // 11000001-11101111-11010111-11011111 +// CHECK-INST: sqrshr z31.h, { z30.s, z31.s }, #1 +// CHECK-ENCODING: [0xdf,0xd7,0xef,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1efd7df + + +sqrshr z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011000-00000000 +// CHECK-INST: sqrshr z0.b, { z0.s - z3.s }, #32 +// CHECK-ENCODING: [0x00,0xd8,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160d800 + +sqrshr z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011001-00010101 +// CHECK-INST: sqrshr z21.b, { z8.s - z11.s }, #11 +// CHECK-ENCODING: [0x15,0xd9,0x75,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c175d915 + +sqrshr z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011001-10010111 +// CHECK-INST: sqrshr z23.b, { z12.s - z15.s }, #24 +// CHECK-ENCODING: [0x97,0xd9,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168d997 + +sqrshr z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011011-10011111 +// CHECK-INST: sqrshr z31.b, { z28.s - z31.s }, #1 +// CHECK-ENCODING: [0x9f,0xdb,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17fdb9f + + +sqrshr z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011000-00000000 +// CHECK-INST: sqrshr z0.h, { z0.d - z3.d }, #64 +// CHECK-ENCODING: [0x00,0xd8,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0d800 + +sqrshr z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011001-00010101 +// CHECK-INST: sqrshr z21.h, { z8.d - z11.d }, #11 +// CHECK-ENCODING: [0x15,0xd9,0xf5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f5d915 + +sqrshr z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011001-10010111 +// CHECK-INST: sqrshr z23.h, { z12.d - z15.d }, #24 +// CHECK-ENCODING: [0x97,0xd9,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8d997 + +sqrshr z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011011-10011111 +// CHECK-INST: sqrshr z31.h, { z28.d - z31.d }, #1 +// CHECK-ENCODING: [0x9f,0xdb,0xff,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1ffdb9f + diff --git a/llvm/test/MC/AArch64/SME2/sqrshrn-diagnostics.s b/llvm/test/MC/AArch64/SME2/sqrshrn-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/sqrshrn-diagnostics.s @@ -0,0 +1,30 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +sqrshrn z0.b, {z0.s-z4.s}, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: sqrshrn z0.b, {z0.s-z4.s}, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrn z0.h, {z1.d-z4.d}, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: sqrshrn z0.h, {z1.d-z4.d}, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate + +sqrshrn z31.h, {z28.d-z31.d}, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]. +// CHECK-NEXT: sqrshrn z31.h, {z28.d-z31.d}, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +sqrshrn z23.s, {z12.s-z15.s}, #24 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrn z23.s, {z12.s-z15.s}, #24 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/sqrshrn.s b/llvm/test/MC/AArch64/SME2/sqrshrn.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/sqrshrn.s @@ -0,0 +1,63 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +sqrshrn z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011100-00000000 +// CHECK-INST: sqrshrn z0.b, { z0.s - z3.s }, #32 +// CHECK-ENCODING: [0x00,0xdc,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160dc00 + +sqrshrn z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011101-00010101 +// CHECK-INST: sqrshrn z21.b, { z8.s - z11.s }, #11 +// CHECK-ENCODING: [0x15,0xdd,0x75,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c175dd15 + +sqrshrn z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011101-10010111 +// CHECK-INST: sqrshrn z23.b, { z12.s - z15.s }, #24 +// CHECK-ENCODING: [0x97,0xdd,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168dd97 + +sqrshrn z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011111-10011111 +// CHECK-INST: sqrshrn z31.b, { z28.s - z31.s }, #1 +// CHECK-ENCODING: [0x9f,0xdf,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17fdf9f + + +sqrshrn z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011100-00000000 +// CHECK-INST: sqrshrn z0.h, { z0.d - z3.d }, #64 +// CHECK-ENCODING: [0x00,0xdc,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0dc00 + +sqrshrn z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011101-00010101 +// CHECK-INST: sqrshrn z21.h, { z8.d - z11.d }, #11 +// CHECK-ENCODING: [0x15,0xdd,0xf5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f5dd15 + +sqrshrn z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011101-10010111 +// CHECK-INST: sqrshrn z23.h, { z12.d - z15.d }, #24 +// CHECK-ENCODING: [0x97,0xdd,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8dd97 + +sqrshrn z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011111-10011111 +// CHECK-INST: sqrshrn z31.h, { z28.d - z31.d }, #1 +// CHECK-ENCODING: [0x9f,0xdf,0xff,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1ffdf9f + diff --git a/llvm/test/MC/AArch64/SME2/sqrshru-diagnostics.s b/llvm/test/MC/AArch64/SME2/sqrshru-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/sqrshru-diagnostics.s @@ -0,0 +1,35 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +sqrshru z0.b, {z0.s-z4.s}, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: sqrshru z0.b, {z0.s-z4.s}, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshru z0.h, {z1.d-z4.d}, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: sqrshru z0.h, {z1.d-z4.d}, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate + +sqrshru z31.h, {z28.d-z31.d}, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]. +// CHECK-NEXT: sqrshru z31.h, {z28.d-z31.d}, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshru z31.h, {z28.d-z31.d}, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]. +// CHECK-NEXT: sqrshru z31.h, {z28.d-z31.d}, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +sqrshru z23.s, {z12.s-z15.s}, #24 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshru z23.s, {z12.s-z15.s}, #24 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/sqrshru.s b/llvm/test/MC/AArch64/SME2/sqrshru.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/sqrshru.s @@ -0,0 +1,87 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +sqrshru z0.h, {z0.s - z1.s}, #16 // 11000001-11110000-11010100-00000000 +// CHECK-INST: sqrshru z0.h, { z0.s, z1.s }, #16 +// CHECK-ENCODING: [0x00,0xd4,0xf0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f0d400 + +sqrshru z21.h, {z10.s - z11.s}, #11 // 11000001-11110101-11010101-01010101 +// CHECK-INST: sqrshru z21.h, { z10.s, z11.s }, #11 +// CHECK-ENCODING: [0x55,0xd5,0xf5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f5d555 + +sqrshru z23.h, {z12.s - z13.s}, #8 // 11000001-11111000-11010101-10010111 +// CHECK-INST: sqrshru z23.h, { z12.s, z13.s }, #8 +// CHECK-ENCODING: [0x97,0xd5,0xf8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f8d597 + +sqrshru z31.h, {z30.s - z31.s}, #1 // 11000001-11111111-11010111-11011111 +// CHECK-INST: sqrshru z31.h, { z30.s, z31.s }, #1 +// CHECK-ENCODING: [0xdf,0xd7,0xff,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1ffd7df + + +sqrshru z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011000-01000000 +// CHECK-INST: sqrshru z0.b, { z0.s - z3.s }, #32 +// CHECK-ENCODING: [0x40,0xd8,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160d840 + +sqrshru z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011001-01010101 +// CHECK-INST: sqrshru z21.b, { z8.s - z11.s }, #11 +// CHECK-ENCODING: [0x55,0xd9,0x75,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c175d955 + +sqrshru z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011001-11010111 +// CHECK-INST: sqrshru z23.b, { z12.s - z15.s }, #24 +// CHECK-ENCODING: [0xd7,0xd9,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168d9d7 + +sqrshru z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011011-11011111 +// CHECK-INST: sqrshru z31.b, { z28.s - z31.s }, #1 +// CHECK-ENCODING: [0xdf,0xdb,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17fdbdf + + +sqrshru z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011000-01000000 +// CHECK-INST: sqrshru z0.h, { z0.d - z3.d }, #64 +// CHECK-ENCODING: [0x40,0xd8,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0d840 + +sqrshru z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011001-01010101 +// CHECK-INST: sqrshru z21.h, { z8.d - z11.d }, #11 +// CHECK-ENCODING: [0x55,0xd9,0xf5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f5d955 + +sqrshru z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011001-11010111 +// CHECK-INST: sqrshru z23.h, { z12.d - z15.d }, #24 +// CHECK-ENCODING: [0xd7,0xd9,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8d9d7 + +sqrshru z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011011-11011111 +// CHECK-INST: sqrshru z31.h, { z28.d - z31.d }, #1 +// CHECK-ENCODING: [0xdf,0xdb,0xff,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1ffdbdf diff --git a/llvm/test/MC/AArch64/SME2/sqrshrun-diagnostics.s b/llvm/test/MC/AArch64/SME2/sqrshrun-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/sqrshrun-diagnostics.s @@ -0,0 +1,30 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +sqrshrun z0.b, {z0.s-z4.s}, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: sqrshrun z0.b, {z0.s-z4.s}, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +sqrshrun z0.h, {z1.d-z4.d}, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: sqrshrun z0.h, {z1.d-z4.d}, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate + +sqrshrun z31.h, {z28.d-z31.d}, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]. +// CHECK-NEXT: sqrshrun z31.h, {z28.d-z31.d}, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +sqrshrun z23.s, {z12.s-z15.s}, #24 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: sqrshrun z23.s, {z12.s-z15.s}, #24 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/sqrshrun.s b/llvm/test/MC/AArch64/SME2/sqrshrun.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/sqrshrun.s @@ -0,0 +1,63 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +sqrshrun z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011100-01000000 +// CHECK-INST: sqrshrun z0.b, { z0.s - z3.s }, #32 +// CHECK-ENCODING: [0x40,0xdc,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160dc40 + +sqrshrun z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011101-01010101 +// CHECK-INST: sqrshrun z21.b, { z8.s - z11.s }, #11 +// CHECK-ENCODING: [0x55,0xdd,0x75,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c175dd55 + +sqrshrun z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011101-11010111 +// CHECK-INST: sqrshrun z23.b, { z12.s - z15.s }, #24 +// CHECK-ENCODING: [0xd7,0xdd,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168ddd7 + +sqrshrun z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011111-11011111 +// CHECK-INST: sqrshrun z31.b, { z28.s - z31.s }, #1 +// CHECK-ENCODING: [0xdf,0xdf,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17fdfdf + + +sqrshrun z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011100-01000000 +// CHECK-INST: sqrshrun z0.h, { z0.d - z3.d }, #64 +// CHECK-ENCODING: [0x40,0xdc,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0dc40 + +sqrshrun z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011101-01010101 +// CHECK-INST: sqrshrun z21.h, { z8.d - z11.d }, #11 +// CHECK-ENCODING: [0x55,0xdd,0xf5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f5dd55 + +sqrshrun z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011101-11010111 +// CHECK-INST: sqrshrun z23.h, { z12.d - z15.d }, #24 +// CHECK-ENCODING: [0xd7,0xdd,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8ddd7 + +sqrshrun z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011111-11011111 +// CHECK-INST: sqrshrun z31.h, { z28.d - z31.d }, #1 +// CHECK-ENCODING: [0xdf,0xdf,0xff,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1ffdfdf + diff --git a/llvm/test/MC/AArch64/SME2/srshl-diagnostics.s b/llvm/test/MC/AArch64/SME2/srshl-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/srshl-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +srshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: srshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: srshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: srshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: srshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: srshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +srshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: srshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Single Register + +srshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: srshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +srshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d +// CHECK-NEXT: srshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/srshl.s b/llvm/test/MC/AArch64/SME2/srshl.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/srshl.s @@ -0,0 +1,413 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +srshl {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100010-00100000 +// CHECK-INST: srshl { z0.h, z1.h }, { z0.h, z1.h }, z0.h +// CHECK-ENCODING: [0x20,0xa2,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160a220 + +srshl {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100010-00110100 +// CHECK-INST: srshl { z20.h, z21.h }, { z20.h, z21.h }, z5.h +// CHECK-ENCODING: [0x34,0xa2,0x65,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c165a234 + +srshl {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100010-00110110 +// CHECK-INST: srshl { z22.h, z23.h }, { z22.h, z23.h }, z8.h +// CHECK-ENCODING: [0x36,0xa2,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168a236 + +srshl {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100010-00111110 +// CHECK-INST: srshl { z30.h, z31.h }, { z30.h, z31.h }, z15.h +// CHECK-ENCODING: [0x3e,0xa2,0x6f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c16fa23e + + +srshl {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110010-00100000 +// CHECK-INST: srshl { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x20,0xb2,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160b220 + +srshl {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110010-00110100 +// CHECK-INST: srshl { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x34,0xb2,0x74,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c174b234 + +srshl {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110010-00110110 +// CHECK-INST: srshl { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h } +// CHECK-ENCODING: [0x36,0xb2,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168b236 + +srshl {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110010-00111110 +// CHECK-INST: srshl { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0x3e,0xb2,0x7e,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17eb23e + + +srshl {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100010-00100000 +// CHECK-INST: srshl { z0.s, z1.s }, { z0.s, z1.s }, z0.s +// CHECK-ENCODING: [0x20,0xa2,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0a220 + +srshl {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100010-00110100 +// CHECK-INST: srshl { z20.s, z21.s }, { z20.s, z21.s }, z5.s +// CHECK-ENCODING: [0x34,0xa2,0xa5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a5a234 + +srshl {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100010-00110110 +// CHECK-INST: srshl { z22.s, z23.s }, { z22.s, z23.s }, z8.s +// CHECK-ENCODING: [0x36,0xa2,0xa8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a8a236 + +srshl {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100010-00111110 +// CHECK-INST: srshl { z30.s, z31.s }, { z30.s, z31.s }, z15.s +// CHECK-ENCODING: [0x3e,0xa2,0xaf,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1afa23e + + +srshl {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110010-00100000 +// CHECK-INST: srshl { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s } +// CHECK-ENCODING: [0x20,0xb2,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0b220 + +srshl {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110010-00110100 +// CHECK-INST: srshl { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s } +// CHECK-ENCODING: [0x34,0xb2,0xb4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1b4b234 + +srshl {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110010-00110110 +// CHECK-INST: srshl { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s } +// CHECK-ENCODING: [0x36,0xb2,0xa8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a8b236 + +srshl {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110010-00111110 +// CHECK-INST: srshl { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s } +// CHECK-ENCODING: [0x3e,0xb2,0xbe,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1beb23e + + +srshl {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100010-00100000 +// CHECK-INST: srshl { z0.d, z1.d }, { z0.d, z1.d }, z0.d +// CHECK-ENCODING: [0x20,0xa2,0xe0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e0a220 + +srshl {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100010-00110100 +// CHECK-INST: srshl { z20.d, z21.d }, { z20.d, z21.d }, z5.d +// CHECK-ENCODING: [0x34,0xa2,0xe5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e5a234 + +srshl {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100010-00110110 +// CHECK-INST: srshl { z22.d, z23.d }, { z22.d, z23.d }, z8.d +// CHECK-ENCODING: [0x36,0xa2,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8a236 + +srshl {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100010-00111110 +// CHECK-INST: srshl { z30.d, z31.d }, { z30.d, z31.d }, z15.d +// CHECK-ENCODING: [0x3e,0xa2,0xef,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1efa23e + + +srshl {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110010-00100000 +// CHECK-INST: srshl { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d } +// CHECK-ENCODING: [0x20,0xb2,0xe0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e0b220 + +srshl {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110010-00110100 +// CHECK-INST: srshl { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d } +// CHECK-ENCODING: [0x34,0xb2,0xf4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f4b234 + +srshl {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110010-00110110 +// CHECK-INST: srshl { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d } +// CHECK-ENCODING: [0x36,0xb2,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8b236 + +srshl {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110010-00111110 +// CHECK-INST: srshl { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d } +// CHECK-ENCODING: [0x3e,0xb2,0xfe,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1feb23e + + +srshl {z0.b, z1.b}, {z0.b, z1.b}, z0.b // 11000001-00100000-10100010-00100000 +// CHECK-INST: srshl { z0.b, z1.b }, { z0.b, z1.b }, z0.b +// CHECK-ENCODING: [0x20,0xa2,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c120a220 + +srshl {z20.b, z21.b}, {z20.b, z21.b}, z5.b // 11000001-00100101-10100010-00110100 +// CHECK-INST: srshl { z20.b, z21.b }, { z20.b, z21.b }, z5.b +// CHECK-ENCODING: [0x34,0xa2,0x25,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c125a234 + +srshl {z22.b, z23.b}, {z22.b, z23.b}, z8.b // 11000001-00101000-10100010-00110110 +// CHECK-INST: srshl { z22.b, z23.b }, { z22.b, z23.b }, z8.b +// CHECK-ENCODING: [0x36,0xa2,0x28,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c128a236 + +srshl {z30.b, z31.b}, {z30.b, z31.b}, z15.b // 11000001-00101111-10100010-00111110 +// CHECK-INST: srshl { z30.b, z31.b }, { z30.b, z31.b }, z15.b +// CHECK-ENCODING: [0x3e,0xa2,0x2f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c12fa23e + + +srshl {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b} // 11000001-00100000-10110010-00100000 +// CHECK-INST: srshl { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b } +// CHECK-ENCODING: [0x20,0xb2,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c120b220 + +srshl {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b} // 11000001-00110100-10110010-00110100 +// CHECK-INST: srshl { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x34,0xb2,0x34,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c134b234 + +srshl {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b} // 11000001-00101000-10110010-00110110 +// CHECK-INST: srshl { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b } +// CHECK-ENCODING: [0x36,0xb2,0x28,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c128b236 + +srshl {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b} // 11000001-00111110-10110010-00111110 +// CHECK-INST: srshl { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0x3e,0xb2,0x3e,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c13eb23e + + +srshl {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101010-00100000 +// CHECK-INST: srshl { z0.h - z3.h }, { z0.h - z3.h }, z0.h +// CHECK-ENCODING: [0x20,0xaa,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160aa20 + +srshl {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101010-00110100 +// CHECK-INST: srshl { z20.h - z23.h }, { z20.h - z23.h }, z5.h +// CHECK-ENCODING: [0x34,0xaa,0x65,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c165aa34 + +srshl {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101010-00110100 +// CHECK-INST: srshl { z20.h - z23.h }, { z20.h - z23.h }, z8.h +// CHECK-ENCODING: [0x34,0xaa,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168aa34 + +srshl {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101010-00111100 +// CHECK-INST: srshl { z28.h - z31.h }, { z28.h - z31.h }, z15.h +// CHECK-ENCODING: [0x3c,0xaa,0x6f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c16faa3c + + +srshl {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111010-00100000 +// CHECK-INST: srshl { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x20,0xba,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160ba20 + +srshl {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111010-00110100 +// CHECK-INST: srshl { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x34,0xba,0x74,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c174ba34 + +srshl {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111010-00110100 +// CHECK-INST: srshl { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x34,0xba,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168ba34 + +srshl {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111010-00111100 +// CHECK-INST: srshl { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x3c,0xba,0x7c,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17cba3c + + +srshl {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101010-00100000 +// CHECK-INST: srshl { z0.s - z3.s }, { z0.s - z3.s }, z0.s +// CHECK-ENCODING: [0x20,0xaa,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0aa20 + +srshl {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101010-00110100 +// CHECK-INST: srshl { z20.s - z23.s }, { z20.s - z23.s }, z5.s +// CHECK-ENCODING: [0x34,0xaa,0xa5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a5aa34 + +srshl {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101010-00110100 +// CHECK-INST: srshl { z20.s - z23.s }, { z20.s - z23.s }, z8.s +// CHECK-ENCODING: [0x34,0xaa,0xa8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a8aa34 + +srshl {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101010-00111100 +// CHECK-INST: srshl { z28.s - z31.s }, { z28.s - z31.s }, z15.s +// CHECK-ENCODING: [0x3c,0xaa,0xaf,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1afaa3c + + +srshl {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111010-00100000 +// CHECK-INST: srshl { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s } +// CHECK-ENCODING: [0x20,0xba,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0ba20 + +srshl {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111010-00110100 +// CHECK-INST: srshl { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s } +// CHECK-ENCODING: [0x34,0xba,0xb4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1b4ba34 + +srshl {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111010-00110100 +// CHECK-INST: srshl { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s } +// CHECK-ENCODING: [0x34,0xba,0xa8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a8ba34 + +srshl {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111010-00111100 +// CHECK-INST: srshl { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s } +// CHECK-ENCODING: [0x3c,0xba,0xbc,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1bcba3c + + +srshl {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101010-00100000 +// CHECK-INST: srshl { z0.d - z3.d }, { z0.d - z3.d }, z0.d +// CHECK-ENCODING: [0x20,0xaa,0xe0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e0aa20 + +srshl {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101010-00110100 +// CHECK-INST: srshl { z20.d - z23.d }, { z20.d - z23.d }, z5.d +// CHECK-ENCODING: [0x34,0xaa,0xe5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e5aa34 + +srshl {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101010-00110100 +// CHECK-INST: srshl { z20.d - z23.d }, { z20.d - z23.d }, z8.d +// CHECK-ENCODING: [0x34,0xaa,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8aa34 + +srshl {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101010-00111100 +// CHECK-INST: srshl { z28.d - z31.d }, { z28.d - z31.d }, z15.d +// CHECK-ENCODING: [0x3c,0xaa,0xef,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1efaa3c + + +srshl {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111010-00100000 +// CHECK-INST: srshl { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d } +// CHECK-ENCODING: [0x20,0xba,0xe0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e0ba20 + +srshl {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111010-00110100 +// CHECK-INST: srshl { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d } +// CHECK-ENCODING: [0x34,0xba,0xf4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f4ba34 + +srshl {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111010-00110100 +// CHECK-INST: srshl { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d } +// CHECK-ENCODING: [0x34,0xba,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8ba34 + +srshl {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111010-00111100 +// CHECK-INST: srshl { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d } +// CHECK-ENCODING: [0x3c,0xba,0xfc,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1fcba3c + + +srshl {z0.b - z3.b}, {z0.b - z3.b}, z0.b // 11000001-00100000-10101010-00100000 +// CHECK-INST: srshl { z0.b - z3.b }, { z0.b - z3.b }, z0.b +// CHECK-ENCODING: [0x20,0xaa,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c120aa20 + +srshl {z20.b - z23.b}, {z20.b - z23.b}, z5.b // 11000001-00100101-10101010-00110100 +// CHECK-INST: srshl { z20.b - z23.b }, { z20.b - z23.b }, z5.b +// CHECK-ENCODING: [0x34,0xaa,0x25,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c125aa34 + +srshl {z20.b - z23.b}, {z20.b - z23.b}, z8.b // 11000001-00101000-10101010-00110100 +// CHECK-INST: srshl { z20.b - z23.b }, { z20.b - z23.b }, z8.b +// CHECK-ENCODING: [0x34,0xaa,0x28,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c128aa34 + +srshl {z28.b - z31.b}, {z28.b - z31.b}, z15.b // 11000001-00101111-10101010-00111100 +// CHECK-INST: srshl { z28.b - z31.b }, { z28.b - z31.b }, z15.b +// CHECK-ENCODING: [0x3c,0xaa,0x2f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c12faa3c + + +srshl {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b} // 11000001-00100000-10111010-00100000 +// CHECK-INST: srshl { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b } +// CHECK-ENCODING: [0x20,0xba,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c120ba20 + +srshl {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b} // 11000001-00110100-10111010-00110100 +// CHECK-INST: srshl { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b } +// CHECK-ENCODING: [0x34,0xba,0x34,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c134ba34 + +srshl {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b} // 11000001-00101000-10111010-00110100 +// CHECK-INST: srshl { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b } +// CHECK-ENCODING: [0x34,0xba,0x28,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c128ba34 + +srshl {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b} // 11000001-00111100-10111010-00111100 +// CHECK-INST: srshl { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b } +// CHECK-ENCODING: [0x3c,0xba,0x3c,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c13cba3c + diff --git a/llvm/test/MC/AArch64/SME2/uqrshr-diagnostics.s b/llvm/test/MC/AArch64/SME2/uqrshr-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/uqrshr-diagnostics.s @@ -0,0 +1,55 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +uqrshr z0.b, {z0.s-z4.s}, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: uqrshr z0.b, {z0.s-z4.s}, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshr z0.h, {z10.s-z12.s}, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uqrshr z0.h, {z10.s-z12.s}, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshr z0.h, {z1.d-z4.d}, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: uqrshr z0.h, {z1.d-z4.d}, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshr z0.h, {z1.s-z2.s}, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: uqrshr z0.h, {z1.s-z2.s}, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate + +uqrshr z31.h, {z28.d-z31.d}, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]. +// CHECK-NEXT: uqrshr z31.h, {z28.d-z31.d}, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshr z31.h, {z28.s-z29.s}, #0 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]. +// CHECK-NEXT: uqrshr z31.h, {z28.s-z29.s}, #0 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshr z31.b, {z28.s-z31.s}, #33 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]. +// CHECK-NEXT: uqrshr z31.b, {z28.s-z31.s}, #33 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +uqrshr z23.s, {z12.s-z15.s}, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshr z23.s, {z12.s-z15.s}, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshr z23.b, {z12.d-z15.d}, #15 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: uqrshr z23.b, {z12.d-z15.d}, #15 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/uqrshr.s b/llvm/test/MC/AArch64/SME2/uqrshr.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/uqrshr.s @@ -0,0 +1,88 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +uqrshr z0.h, {z0.s - z1.s}, #16 // 11000001-11100000-11010100-00100000 +// CHECK-INST: uqrshr z0.h, { z0.s, z1.s }, #16 +// CHECK-ENCODING: [0x20,0xd4,0xe0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e0d420 + +uqrshr z21.h, {z10.s - z11.s}, #11 // 11000001-11100101-11010101-01110101 +// CHECK-INST: uqrshr z21.h, { z10.s, z11.s }, #11 +// CHECK-ENCODING: [0x75,0xd5,0xe5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e5d575 + +uqrshr z23.h, {z12.s - z13.s}, #8 // 11000001-11101000-11010101-10110111 +// CHECK-INST: uqrshr z23.h, { z12.s, z13.s }, #8 +// CHECK-ENCODING: [0xb7,0xd5,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8d5b7 + +uqrshr z31.h, {z30.s - z31.s}, #1 // 11000001-11101111-11010111-11111111 +// CHECK-INST: uqrshr z31.h, { z30.s, z31.s }, #1 +// CHECK-ENCODING: [0xff,0xd7,0xef,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1efd7ff + + +uqrshr z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011000-00100000 +// CHECK-INST: uqrshr z0.b, { z0.s - z3.s }, #32 +// CHECK-ENCODING: [0x20,0xd8,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160d820 + +uqrshr z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011001-00110101 +// CHECK-INST: uqrshr z21.b, { z8.s - z11.s }, #11 +// CHECK-ENCODING: [0x35,0xd9,0x75,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c175d935 + +uqrshr z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011001-10110111 +// CHECK-INST: uqrshr z23.b, { z12.s - z15.s }, #24 +// CHECK-ENCODING: [0xb7,0xd9,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168d9b7 + +uqrshr z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011011-10111111 +// CHECK-INST: uqrshr z31.b, { z28.s - z31.s }, #1 +// CHECK-ENCODING: [0xbf,0xdb,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17fdbbf + + +uqrshr z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011000-00100000 +// CHECK-INST: uqrshr z0.h, { z0.d - z3.d }, #64 +// CHECK-ENCODING: [0x20,0xd8,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0d820 + +uqrshr z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011001-00110101 +// CHECK-INST: uqrshr z21.h, { z8.d - z11.d }, #11 +// CHECK-ENCODING: [0x35,0xd9,0xf5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f5d935 + +uqrshr z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011001-10110111 +// CHECK-INST: uqrshr z23.h, { z12.d - z15.d }, #24 +// CHECK-ENCODING: [0xb7,0xd9,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8d9b7 + +uqrshr z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011011-10111111 +// CHECK-INST: uqrshr z31.h, { z28.d - z31.d }, #1 +// CHECK-ENCODING: [0xbf,0xdb,0xff,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1ffdbbf + diff --git a/llvm/test/MC/AArch64/SME2/uqrshrn-diagnostics.s b/llvm/test/MC/AArch64/SME2/uqrshrn-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/uqrshrn-diagnostics.s @@ -0,0 +1,30 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +uqrshrn z0.b, {z0.s-z4.s}, #32 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: uqrshrn z0.b, {z0.s-z4.s}, #32 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +uqrshrn z0.h, {z1.d-z4.d}, #1 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: uqrshrn z0.h, {z1.d-z4.d}, #1 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid immediate + +uqrshrn z31.h, {z28.d-z31.d}, #65 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]. +// CHECK-NEXT: uqrshrn z31.h, {z28.d-z31.d}, #65 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +uqrshrn z23.s, {z12.s-z15.s}, #24 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width +// CHECK-NEXT: uqrshrn z23.s, {z12.s-z15.s}, #24 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/uqrshrn.s b/llvm/test/MC/AArch64/SME2/uqrshrn.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/uqrshrn.s @@ -0,0 +1,63 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +uqrshrn z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011100-00100000 +// CHECK-INST: uqrshrn z0.b, { z0.s - z3.s }, #32 +// CHECK-ENCODING: [0x20,0xdc,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160dc20 + +uqrshrn z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011101-00110101 +// CHECK-INST: uqrshrn z21.b, { z8.s - z11.s }, #11 +// CHECK-ENCODING: [0x35,0xdd,0x75,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c175dd35 + +uqrshrn z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011101-10110111 +// CHECK-INST: uqrshrn z23.b, { z12.s - z15.s }, #24 +// CHECK-ENCODING: [0xb7,0xdd,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168ddb7 + +uqrshrn z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011111-10111111 +// CHECK-INST: uqrshrn z31.b, { z28.s - z31.s }, #1 +// CHECK-ENCODING: [0xbf,0xdf,0x7f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17fdfbf + + +uqrshrn z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011100-00100000 +// CHECK-INST: uqrshrn z0.h, { z0.d - z3.d }, #64 +// CHECK-ENCODING: [0x20,0xdc,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0dc20 + +uqrshrn z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011101-00110101 +// CHECK-INST: uqrshrn z21.h, { z8.d - z11.d }, #11 +// CHECK-ENCODING: [0x35,0xdd,0xf5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f5dd35 + +uqrshrn z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011101-10110111 +// CHECK-INST: uqrshrn z23.h, { z12.d - z15.d }, #24 +// CHECK-ENCODING: [0xb7,0xdd,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8ddb7 + +uqrshrn z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011111-10111111 +// CHECK-INST: uqrshrn z31.h, { z28.d - z31.d }, #1 +// CHECK-ENCODING: [0xbf,0xdf,0xff,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1ffdfbf + diff --git a/llvm/test/MC/AArch64/SME2/urshl-diagnostics.s b/llvm/test/MC/AArch64/SME2/urshl-diagnostics.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/urshl-diagnostics.s @@ -0,0 +1,50 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s + +// --------------------------------------------------------------------------// +// Invalid vector list + +urshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: urshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK-NEXT: urshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors +// CHECK-NEXT: urshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types +// CHECK-NEXT: urshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: urshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +urshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b} +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types +// CHECK-NEXT: urshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b} +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Single Register + +urshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h +// CHECK-NEXT: urshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Invalid Register Suffix + +urshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d +// CHECK-NEXT: urshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: diff --git a/llvm/test/MC/AArch64/SME2/urshl.s b/llvm/test/MC/AArch64/SME2/urshl.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/AArch64/SME2/urshl.s @@ -0,0 +1,413 @@ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \ +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \ +// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST + + +urshl {z0.h, z1.h}, {z0.h, z1.h}, z0.h // 11000001-01100000-10100010-00100001 +// CHECK-INST: urshl { z0.h, z1.h }, { z0.h, z1.h }, z0.h +// CHECK-ENCODING: [0x21,0xa2,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160a221 + +urshl {z20.h, z21.h}, {z20.h, z21.h}, z5.h // 11000001-01100101-10100010-00110101 +// CHECK-INST: urshl { z20.h, z21.h }, { z20.h, z21.h }, z5.h +// CHECK-ENCODING: [0x35,0xa2,0x65,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c165a235 + +urshl {z22.h, z23.h}, {z22.h, z23.h}, z8.h // 11000001-01101000-10100010-00110111 +// CHECK-INST: urshl { z22.h, z23.h }, { z22.h, z23.h }, z8.h +// CHECK-ENCODING: [0x37,0xa2,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168a237 + +urshl {z30.h, z31.h}, {z30.h, z31.h}, z15.h // 11000001-01101111-10100010-00111111 +// CHECK-INST: urshl { z30.h, z31.h }, { z30.h, z31.h }, z15.h +// CHECK-ENCODING: [0x3f,0xa2,0x6f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c16fa23f + + +urshl {z0.h, z1.h}, {z0.h, z1.h}, {z0.h, z1.h} // 11000001-01100000-10110010-00100001 +// CHECK-INST: urshl { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h } +// CHECK-ENCODING: [0x21,0xb2,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160b221 + +urshl {z20.h, z21.h}, {z20.h, z21.h}, {z20.h, z21.h} // 11000001-01110100-10110010-00110101 +// CHECK-INST: urshl { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h } +// CHECK-ENCODING: [0x35,0xb2,0x74,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c174b235 + +urshl {z22.h, z23.h}, {z22.h, z23.h}, {z8.h, z9.h} // 11000001-01101000-10110010-00110111 +// CHECK-INST: urshl { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h } +// CHECK-ENCODING: [0x37,0xb2,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168b237 + +urshl {z30.h, z31.h}, {z30.h, z31.h}, {z30.h, z31.h} // 11000001-01111110-10110010-00111111 +// CHECK-INST: urshl { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h } +// CHECK-ENCODING: [0x3f,0xb2,0x7e,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17eb23f + + +urshl {z0.s, z1.s}, {z0.s, z1.s}, z0.s // 11000001-10100000-10100010-00100001 +// CHECK-INST: urshl { z0.s, z1.s }, { z0.s, z1.s }, z0.s +// CHECK-ENCODING: [0x21,0xa2,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0a221 + +urshl {z20.s, z21.s}, {z20.s, z21.s}, z5.s // 11000001-10100101-10100010-00110101 +// CHECK-INST: urshl { z20.s, z21.s }, { z20.s, z21.s }, z5.s +// CHECK-ENCODING: [0x35,0xa2,0xa5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a5a235 + +urshl {z22.s, z23.s}, {z22.s, z23.s}, z8.s // 11000001-10101000-10100010-00110111 +// CHECK-INST: urshl { z22.s, z23.s }, { z22.s, z23.s }, z8.s +// CHECK-ENCODING: [0x37,0xa2,0xa8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a8a237 + +urshl {z30.s, z31.s}, {z30.s, z31.s}, z15.s // 11000001-10101111-10100010-00111111 +// CHECK-INST: urshl { z30.s, z31.s }, { z30.s, z31.s }, z15.s +// CHECK-ENCODING: [0x3f,0xa2,0xaf,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1afa23f + + +urshl {z0.s, z1.s}, {z0.s, z1.s}, {z0.s, z1.s} // 11000001-10100000-10110010-00100001 +// CHECK-INST: urshl { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s } +// CHECK-ENCODING: [0x21,0xb2,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0b221 + +urshl {z20.s, z21.s}, {z20.s, z21.s}, {z20.s, z21.s} // 11000001-10110100-10110010-00110101 +// CHECK-INST: urshl { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s } +// CHECK-ENCODING: [0x35,0xb2,0xb4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1b4b235 + +urshl {z22.s, z23.s}, {z22.s, z23.s}, {z8.s, z9.s} // 11000001-10101000-10110010-00110111 +// CHECK-INST: urshl { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s } +// CHECK-ENCODING: [0x37,0xb2,0xa8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a8b237 + +urshl {z30.s, z31.s}, {z30.s, z31.s}, {z30.s, z31.s} // 11000001-10111110-10110010-00111111 +// CHECK-INST: urshl { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s } +// CHECK-ENCODING: [0x3f,0xb2,0xbe,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1beb23f + + +urshl {z0.d, z1.d}, {z0.d, z1.d}, z0.d // 11000001-11100000-10100010-00100001 +// CHECK-INST: urshl { z0.d, z1.d }, { z0.d, z1.d }, z0.d +// CHECK-ENCODING: [0x21,0xa2,0xe0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e0a221 + +urshl {z20.d, z21.d}, {z20.d, z21.d}, z5.d // 11000001-11100101-10100010-00110101 +// CHECK-INST: urshl { z20.d, z21.d }, { z20.d, z21.d }, z5.d +// CHECK-ENCODING: [0x35,0xa2,0xe5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e5a235 + +urshl {z22.d, z23.d}, {z22.d, z23.d}, z8.d // 11000001-11101000-10100010-00110111 +// CHECK-INST: urshl { z22.d, z23.d }, { z22.d, z23.d }, z8.d +// CHECK-ENCODING: [0x37,0xa2,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8a237 + +urshl {z30.d, z31.d}, {z30.d, z31.d}, z15.d // 11000001-11101111-10100010-00111111 +// CHECK-INST: urshl { z30.d, z31.d }, { z30.d, z31.d }, z15.d +// CHECK-ENCODING: [0x3f,0xa2,0xef,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1efa23f + + +urshl {z0.d, z1.d}, {z0.d, z1.d}, {z0.d, z1.d} // 11000001-11100000-10110010-00100001 +// CHECK-INST: urshl { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d } +// CHECK-ENCODING: [0x21,0xb2,0xe0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e0b221 + +urshl {z20.d, z21.d}, {z20.d, z21.d}, {z20.d, z21.d} // 11000001-11110100-10110010-00110101 +// CHECK-INST: urshl { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d } +// CHECK-ENCODING: [0x35,0xb2,0xf4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f4b235 + +urshl {z22.d, z23.d}, {z22.d, z23.d}, {z8.d, z9.d} // 11000001-11101000-10110010-00110111 +// CHECK-INST: urshl { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d } +// CHECK-ENCODING: [0x37,0xb2,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8b237 + +urshl {z30.d, z31.d}, {z30.d, z31.d}, {z30.d, z31.d} // 11000001-11111110-10110010-00111111 +// CHECK-INST: urshl { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d } +// CHECK-ENCODING: [0x3f,0xb2,0xfe,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1feb23f + + +urshl {z0.b, z1.b}, {z0.b, z1.b}, z0.b // 11000001-00100000-10100010-00100001 +// CHECK-INST: urshl { z0.b, z1.b }, { z0.b, z1.b }, z0.b +// CHECK-ENCODING: [0x21,0xa2,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c120a221 + +urshl {z20.b, z21.b}, {z20.b, z21.b}, z5.b // 11000001-00100101-10100010-00110101 +// CHECK-INST: urshl { z20.b, z21.b }, { z20.b, z21.b }, z5.b +// CHECK-ENCODING: [0x35,0xa2,0x25,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c125a235 + +urshl {z22.b, z23.b}, {z22.b, z23.b}, z8.b // 11000001-00101000-10100010-00110111 +// CHECK-INST: urshl { z22.b, z23.b }, { z22.b, z23.b }, z8.b +// CHECK-ENCODING: [0x37,0xa2,0x28,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c128a237 + +urshl {z30.b, z31.b}, {z30.b, z31.b}, z15.b // 11000001-00101111-10100010-00111111 +// CHECK-INST: urshl { z30.b, z31.b }, { z30.b, z31.b }, z15.b +// CHECK-ENCODING: [0x3f,0xa2,0x2f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c12fa23f + + +urshl {z0.b, z1.b}, {z0.b, z1.b}, {z0.b, z1.b} // 11000001-00100000-10110010-00100001 +// CHECK-INST: urshl { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b } +// CHECK-ENCODING: [0x21,0xb2,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c120b221 + +urshl {z20.b, z21.b}, {z20.b, z21.b}, {z20.b, z21.b} // 11000001-00110100-10110010-00110101 +// CHECK-INST: urshl { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b } +// CHECK-ENCODING: [0x35,0xb2,0x34,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c134b235 + +urshl {z22.b, z23.b}, {z22.b, z23.b}, {z8.b, z9.b} // 11000001-00101000-10110010-00110111 +// CHECK-INST: urshl { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b } +// CHECK-ENCODING: [0x37,0xb2,0x28,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c128b237 + +urshl {z30.b, z31.b}, {z30.b, z31.b}, {z30.b, z31.b} // 11000001-00111110-10110010-00111111 +// CHECK-INST: urshl { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b } +// CHECK-ENCODING: [0x3f,0xb2,0x3e,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c13eb23f + + +urshl {z0.h - z3.h}, {z0.h - z3.h}, z0.h // 11000001-01100000-10101010-00100001 +// CHECK-INST: urshl { z0.h - z3.h }, { z0.h - z3.h }, z0.h +// CHECK-ENCODING: [0x21,0xaa,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160aa21 + +urshl {z20.h - z23.h}, {z20.h - z23.h}, z5.h // 11000001-01100101-10101010-00110101 +// CHECK-INST: urshl { z20.h - z23.h }, { z20.h - z23.h }, z5.h +// CHECK-ENCODING: [0x35,0xaa,0x65,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c165aa35 + +urshl {z20.h - z23.h}, {z20.h - z23.h}, z8.h // 11000001-01101000-10101010-00110101 +// CHECK-INST: urshl { z20.h - z23.h }, { z20.h - z23.h }, z8.h +// CHECK-ENCODING: [0x35,0xaa,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168aa35 + +urshl {z28.h - z31.h}, {z28.h - z31.h}, z15.h // 11000001-01101111-10101010-00111101 +// CHECK-INST: urshl { z28.h - z31.h }, { z28.h - z31.h }, z15.h +// CHECK-ENCODING: [0x3d,0xaa,0x6f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c16faa3d + + +urshl {z0.h - z3.h}, {z0.h - z3.h}, {z0.h - z3.h} // 11000001-01100000-10111010-00100001 +// CHECK-INST: urshl { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h } +// CHECK-ENCODING: [0x21,0xba,0x60,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c160ba21 + +urshl {z20.h - z23.h}, {z20.h - z23.h}, {z20.h - z23.h} // 11000001-01110100-10111010-00110101 +// CHECK-INST: urshl { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h } +// CHECK-ENCODING: [0x35,0xba,0x74,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c174ba35 + +urshl {z20.h - z23.h}, {z20.h - z23.h}, {z8.h - z11.h} // 11000001-01101000-10111010-00110101 +// CHECK-INST: urshl { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h } +// CHECK-ENCODING: [0x35,0xba,0x68,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c168ba35 + +urshl {z28.h - z31.h}, {z28.h - z31.h}, {z28.h - z31.h} // 11000001-01111100-10111010-00111101 +// CHECK-INST: urshl { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h } +// CHECK-ENCODING: [0x3d,0xba,0x7c,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c17cba3d + + +urshl {z0.s - z3.s}, {z0.s - z3.s}, z0.s // 11000001-10100000-10101010-00100001 +// CHECK-INST: urshl { z0.s - z3.s }, { z0.s - z3.s }, z0.s +// CHECK-ENCODING: [0x21,0xaa,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0aa21 + +urshl {z20.s - z23.s}, {z20.s - z23.s}, z5.s // 11000001-10100101-10101010-00110101 +// CHECK-INST: urshl { z20.s - z23.s }, { z20.s - z23.s }, z5.s +// CHECK-ENCODING: [0x35,0xaa,0xa5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a5aa35 + +urshl {z20.s - z23.s}, {z20.s - z23.s}, z8.s // 11000001-10101000-10101010-00110101 +// CHECK-INST: urshl { z20.s - z23.s }, { z20.s - z23.s }, z8.s +// CHECK-ENCODING: [0x35,0xaa,0xa8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a8aa35 + +urshl {z28.s - z31.s}, {z28.s - z31.s}, z15.s // 11000001-10101111-10101010-00111101 +// CHECK-INST: urshl { z28.s - z31.s }, { z28.s - z31.s }, z15.s +// CHECK-ENCODING: [0x3d,0xaa,0xaf,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1afaa3d + + +urshl {z0.s - z3.s}, {z0.s - z3.s}, {z0.s - z3.s} // 11000001-10100000-10111010-00100001 +// CHECK-INST: urshl { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s } +// CHECK-ENCODING: [0x21,0xba,0xa0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a0ba21 + +urshl {z20.s - z23.s}, {z20.s - z23.s}, {z20.s - z23.s} // 11000001-10110100-10111010-00110101 +// CHECK-INST: urshl { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s } +// CHECK-ENCODING: [0x35,0xba,0xb4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1b4ba35 + +urshl {z20.s - z23.s}, {z20.s - z23.s}, {z8.s - z11.s} // 11000001-10101000-10111010-00110101 +// CHECK-INST: urshl { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s } +// CHECK-ENCODING: [0x35,0xba,0xa8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1a8ba35 + +urshl {z28.s - z31.s}, {z28.s - z31.s}, {z28.s - z31.s} // 11000001-10111100-10111010-00111101 +// CHECK-INST: urshl { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s } +// CHECK-ENCODING: [0x3d,0xba,0xbc,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1bcba3d + + +urshl {z0.d - z3.d}, {z0.d - z3.d}, z0.d // 11000001-11100000-10101010-00100001 +// CHECK-INST: urshl { z0.d - z3.d }, { z0.d - z3.d }, z0.d +// CHECK-ENCODING: [0x21,0xaa,0xe0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e0aa21 + +urshl {z20.d - z23.d}, {z20.d - z23.d}, z5.d // 11000001-11100101-10101010-00110101 +// CHECK-INST: urshl { z20.d - z23.d }, { z20.d - z23.d }, z5.d +// CHECK-ENCODING: [0x35,0xaa,0xe5,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e5aa35 + +urshl {z20.d - z23.d}, {z20.d - z23.d}, z8.d // 11000001-11101000-10101010-00110101 +// CHECK-INST: urshl { z20.d - z23.d }, { z20.d - z23.d }, z8.d +// CHECK-ENCODING: [0x35,0xaa,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8aa35 + +urshl {z28.d - z31.d}, {z28.d - z31.d}, z15.d // 11000001-11101111-10101010-00111101 +// CHECK-INST: urshl { z28.d - z31.d }, { z28.d - z31.d }, z15.d +// CHECK-ENCODING: [0x3d,0xaa,0xef,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1efaa3d + + +urshl {z0.d - z3.d}, {z0.d - z3.d}, {z0.d - z3.d} // 11000001-11100000-10111010-00100001 +// CHECK-INST: urshl { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d } +// CHECK-ENCODING: [0x21,0xba,0xe0,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e0ba21 + +urshl {z20.d - z23.d}, {z20.d - z23.d}, {z20.d - z23.d} // 11000001-11110100-10111010-00110101 +// CHECK-INST: urshl { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d } +// CHECK-ENCODING: [0x35,0xba,0xf4,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1f4ba35 + +urshl {z20.d - z23.d}, {z20.d - z23.d}, {z8.d - z11.d} // 11000001-11101000-10111010-00110101 +// CHECK-INST: urshl { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d } +// CHECK-ENCODING: [0x35,0xba,0xe8,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1e8ba35 + +urshl {z28.d - z31.d}, {z28.d - z31.d}, {z28.d - z31.d} // 11000001-11111100-10111010-00111101 +// CHECK-INST: urshl { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d } +// CHECK-ENCODING: [0x3d,0xba,0xfc,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c1fcba3d + + +urshl {z0.b - z3.b}, {z0.b - z3.b}, z0.b // 11000001-00100000-10101010-00100001 +// CHECK-INST: urshl { z0.b - z3.b }, { z0.b - z3.b }, z0.b +// CHECK-ENCODING: [0x21,0xaa,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c120aa21 + +urshl {z20.b - z23.b}, {z20.b - z23.b}, z5.b // 11000001-00100101-10101010-00110101 +// CHECK-INST: urshl { z20.b - z23.b }, { z20.b - z23.b }, z5.b +// CHECK-ENCODING: [0x35,0xaa,0x25,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c125aa35 + +urshl {z20.b - z23.b}, {z20.b - z23.b}, z8.b // 11000001-00101000-10101010-00110101 +// CHECK-INST: urshl { z20.b - z23.b }, { z20.b - z23.b }, z8.b +// CHECK-ENCODING: [0x35,0xaa,0x28,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c128aa35 + +urshl {z28.b - z31.b}, {z28.b - z31.b}, z15.b // 11000001-00101111-10101010-00111101 +// CHECK-INST: urshl { z28.b - z31.b }, { z28.b - z31.b }, z15.b +// CHECK-ENCODING: [0x3d,0xaa,0x2f,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c12faa3d + + +urshl {z0.b - z3.b}, {z0.b - z3.b}, {z0.b - z3.b} // 11000001-00100000-10111010-00100001 +// CHECK-INST: urshl { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b } +// CHECK-ENCODING: [0x21,0xba,0x20,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c120ba21 + +urshl {z20.b - z23.b}, {z20.b - z23.b}, {z20.b - z23.b} // 11000001-00110100-10111010-00110101 +// CHECK-INST: urshl { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b } +// CHECK-ENCODING: [0x35,0xba,0x34,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c134ba35 + +urshl {z20.b - z23.b}, {z20.b - z23.b}, {z8.b - z11.b} // 11000001-00101000-10111010-00110101 +// CHECK-INST: urshl { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b } +// CHECK-ENCODING: [0x35,0xba,0x28,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c128ba35 + +urshl {z28.b - z31.b}, {z28.b - z31.b}, {z28.b - z31.b} // 11000001-00111100-10111010-00111101 +// CHECK-INST: urshl { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b } +// CHECK-ENCODING: [0x3d,0xba,0x3c,0xc1] +// CHECK-ERROR: instruction requires: sme2 +// CHECK-UNKNOWN: c13cba3d +