diff --git a/llvm/test/CodeGen/PowerPC/add-int128-madd.ll b/llvm/test/CodeGen/PowerPC/add-int128-madd.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/add-int128-madd.ll @@ -0,0 +1,350 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P9 +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-P8 + +define i128 @add_int64_sext(i64 noundef %a, i64 noundef %b, i64 noundef %c) { +; CHECK-P9-LABEL: add_int64_sext: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: mulld 6, 4, 3 +; CHECK-P9-NEXT: mulhd 4, 4, 3 +; CHECK-P9-NEXT: sradi 7, 5, 63 +; CHECK-P9-NEXT: addc 3, 6, 5 +; CHECK-P9-NEXT: adde 4, 4, 7 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: add_int64_sext: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mulld 6, 4, 3 +; CHECK-P8-NEXT: mulhd 4, 4, 3 +; CHECK-P8-NEXT: sradi 7, 5, 63 +; CHECK-P8-NEXT: addc 3, 6, 5 +; CHECK-P8-NEXT: adde 4, 4, 7 +; CHECK-P8-NEXT: blr +entry: + %conv = sext i64 %a to i128 + %conv1 = sext i64 %b to i128 + %mul = mul nsw i128 %conv1, %conv + %conv2 = sext i64 %c to i128 + %add = add nsw i128 %mul, %conv2 + ret i128 %add +} + +define i128 @add_int64_zext(i64 noundef %a, i64 noundef %b, i64 noundef %c) { +; CHECK-P9-LABEL: add_int64_zext: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: mulld 6, 4, 3 +; CHECK-P9-NEXT: mulhdu 4, 4, 3 +; CHECK-P9-NEXT: addc 3, 6, 5 +; CHECK-P9-NEXT: addze 4, 4 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: add_int64_zext: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mulld 6, 4, 3 +; CHECK-P8-NEXT: mulhdu 4, 4, 3 +; CHECK-P8-NEXT: addc 3, 6, 5 +; CHECK-P8-NEXT: addze 4, 4 +; CHECK-P8-NEXT: blr +entry: + %conv = zext i64 %a to i128 + %conv1 = zext i64 %b to i128 + %mul = mul nsw i128 %conv1, %conv + %conv2 = zext i64 %c to i128 + %add = add nsw i128 %mul, %conv2 + ret i128 %add +} + +define i128 @add_int64_hybrid_ext(i64 noundef %a, i64 noundef %b, i64 noundef %c) { +; CHECK-P9-LABEL: add_int64_hybrid_ext: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: mulhdu 7, 4, 3 +; CHECK-P9-NEXT: sradi 6, 3, 63 +; CHECK-P9-NEXT: mulld 3, 4, 3 +; CHECK-P9-NEXT: maddld 6, 4, 6, 7 +; CHECK-P9-NEXT: sradi 4, 5, 63 +; CHECK-P9-NEXT: addc 3, 3, 5 +; CHECK-P9-NEXT: adde 4, 6, 4 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: add_int64_hybrid_ext: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: sradi 6, 3, 63 +; CHECK-P8-NEXT: mulhdu 7, 4, 3 +; CHECK-P8-NEXT: mulld 6, 4, 6 +; CHECK-P8-NEXT: mulld 3, 4, 3 +; CHECK-P8-NEXT: sradi 4, 5, 63 +; CHECK-P8-NEXT: add 6, 7, 6 +; CHECK-P8-NEXT: addc 3, 3, 5 +; CHECK-P8-NEXT: adde 4, 6, 4 +; CHECK-P8-NEXT: blr +entry: + %conv = sext i64 %a to i128 + %conv1 = zext i64 %b to i128 + %mul = mul nsw i128 %conv1, %conv + %conv2 = sext i64 %c to i128 + %add = add nsw i128 %mul, %conv2 + ret i128 %add +} + +define i128 @add_int64_swap(i64 noundef %a, i64 noundef %b, i64 noundef %c) { +; CHECK-P9-LABEL: add_int64_swap: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: mulld 6, 4, 3 +; CHECK-P9-NEXT: mulhd 4, 4, 3 +; CHECK-P9-NEXT: sradi 7, 5, 63 +; CHECK-P9-NEXT: addc 3, 5, 6 +; CHECK-P9-NEXT: adde 4, 7, 4 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: add_int64_swap: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: mulld 6, 4, 3 +; CHECK-P8-NEXT: mulhd 4, 4, 3 +; CHECK-P8-NEXT: sradi 7, 5, 63 +; CHECK-P8-NEXT: addc 3, 5, 6 +; CHECK-P8-NEXT: adde 4, 7, 4 +; CHECK-P8-NEXT: blr +entry: + %conv = sext i64 %a to i128 + %conv1 = sext i64 %b to i128 + %mul = mul nsw i128 %conv1, %conv + %conv2 = sext i64 %c to i128 + %add = add nsw i128 %conv2, %mul + ret i128 %add +} + +define i128 @add_mix_zext(i63 noundef %a, i63 noundef %b, i64 noundef %c) { +; CHECK-P9-LABEL: add_mix_zext: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: clrldi 3, 3, 1 +; CHECK-P9-NEXT: clrldi 4, 4, 1 +; CHECK-P9-NEXT: mulld 6, 4, 3 +; CHECK-P9-NEXT: mulhdu 4, 4, 3 +; CHECK-P9-NEXT: addc 3, 6, 5 +; CHECK-P9-NEXT: addze 4, 4 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: add_mix_zext: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: clrldi 3, 3, 1 +; CHECK-P8-NEXT: clrldi 4, 4, 1 +; CHECK-P8-NEXT: mulld 6, 4, 3 +; CHECK-P8-NEXT: mulhdu 4, 4, 3 +; CHECK-P8-NEXT: addc 3, 6, 5 +; CHECK-P8-NEXT: addze 4, 4 +; CHECK-P8-NEXT: blr +entry: + %conv = zext i63 %a to i128 + %conv1 = zext i63 %b to i128 + %mul = mul nsw i128 %conv1, %conv + %conv2 = zext i64 %c to i128 + %add = add nsw i128 %mul, %conv2 + ret i128 %add +} + +define i128 @add_int63_sext(i63 noundef %a, i63 noundef %b, i63 noundef %c) { +; CHECK-P9-LABEL: add_int63_sext: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: sldi 3, 3, 1 +; CHECK-P9-NEXT: sldi 4, 4, 1 +; CHECK-P9-NEXT: sradi 3, 3, 1 +; CHECK-P9-NEXT: sradi 4, 4, 1 +; CHECK-P9-NEXT: mulld 6, 4, 3 +; CHECK-P9-NEXT: mulhd 4, 4, 3 +; CHECK-P9-NEXT: sldi 3, 5, 1 +; CHECK-P9-NEXT: sradi 5, 3, 1 +; CHECK-P9-NEXT: sradi 7, 3, 63 +; CHECK-P9-NEXT: addc 3, 6, 5 +; CHECK-P9-NEXT: adde 4, 4, 7 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: add_int63_sext: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: sldi 3, 3, 1 +; CHECK-P8-NEXT: sldi 4, 4, 1 +; CHECK-P8-NEXT: sradi 3, 3, 1 +; CHECK-P8-NEXT: sradi 4, 4, 1 +; CHECK-P8-NEXT: mulld 6, 4, 3 +; CHECK-P8-NEXT: mulhd 4, 4, 3 +; CHECK-P8-NEXT: sldi 3, 5, 1 +; CHECK-P8-NEXT: sradi 5, 3, 1 +; CHECK-P8-NEXT: sradi 7, 3, 63 +; CHECK-P8-NEXT: addc 3, 6, 5 +; CHECK-P8-NEXT: adde 4, 4, 7 +; CHECK-P8-NEXT: blr +entry: + %conv = sext i63 %a to i128 + %conv1 = sext i63 %b to i128 + %mul = mul nsw i128 %conv1, %conv + %conv2 = sext i63 %c to i128 + %add = add nsw i128 %mul, %conv2 + ret i128 %add +} + +define i128 @add_int63_zext(i63 noundef %a, i63 noundef %b, i63 noundef %c) { +; CHECK-P9-LABEL: add_int63_zext: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: clrldi 3, 3, 1 +; CHECK-P9-NEXT: clrldi 4, 4, 1 +; CHECK-P9-NEXT: mulld 6, 4, 3 +; CHECK-P9-NEXT: mulhdu 4, 4, 3 +; CHECK-P9-NEXT: clrldi 3, 5, 1 +; CHECK-P9-NEXT: addc 3, 6, 3 +; CHECK-P9-NEXT: addze 4, 4 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: add_int63_zext: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: clrldi 3, 3, 1 +; CHECK-P8-NEXT: clrldi 4, 4, 1 +; CHECK-P8-NEXT: mulld 6, 4, 3 +; CHECK-P8-NEXT: mulhdu 4, 4, 3 +; CHECK-P8-NEXT: clrldi 3, 5, 1 +; CHECK-P8-NEXT: addc 3, 6, 3 +; CHECK-P8-NEXT: addze 4, 4 +; CHECK-P8-NEXT: blr +entry: + %conv = zext i63 %a to i128 + %conv1 = zext i63 %b to i128 + %mul = mul nsw i128 %conv1, %conv + %conv2 = zext i63 %c to i128 + %add = add nsw i128 %mul, %conv2 + ret i128 %add +} + +define i128 @add_int63_hybrid_ext(i63 noundef %a, i63 noundef %b, i63 noundef %c) { +; CHECK-P9-LABEL: add_int63_hybrid_ext: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: sldi 3, 3, 1 +; CHECK-P9-NEXT: clrldi 4, 4, 1 +; CHECK-P9-NEXT: sradi 3, 3, 1 +; CHECK-P9-NEXT: mulld 6, 4, 3 +; CHECK-P9-NEXT: mulhd 4, 4, 3 +; CHECK-P9-NEXT: sldi 3, 5, 1 +; CHECK-P9-NEXT: sradi 5, 3, 1 +; CHECK-P9-NEXT: sradi 7, 3, 63 +; CHECK-P9-NEXT: addc 3, 6, 5 +; CHECK-P9-NEXT: adde 4, 4, 7 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: add_int63_hybrid_ext: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: sldi 3, 3, 1 +; CHECK-P8-NEXT: clrldi 4, 4, 1 +; CHECK-P8-NEXT: sradi 3, 3, 1 +; CHECK-P8-NEXT: mulld 6, 4, 3 +; CHECK-P8-NEXT: mulhd 4, 4, 3 +; CHECK-P8-NEXT: sldi 3, 5, 1 +; CHECK-P8-NEXT: sradi 5, 3, 1 +; CHECK-P8-NEXT: sradi 7, 3, 63 +; CHECK-P8-NEXT: addc 3, 6, 5 +; CHECK-P8-NEXT: adde 4, 4, 7 +; CHECK-P8-NEXT: blr +entry: + %conv = sext i63 %a to i128 + %conv1 = zext i63 %b to i128 + %mul = mul nsw i128 %conv1, %conv + %conv2 = sext i63 %c to i128 + %add = add nsw i128 %mul, %conv2 + ret i128 %add +} + +define i128 @add_invalid1(i65 noundef %a, i64 noundef %b, i64 noundef %c) { +; CHECK-P9-LABEL: add_invalid1: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: mulhdu 8, 5, 3 +; CHECK-P9-NEXT: clrldi 4, 4, 63 +; CHECK-P9-NEXT: sradi 7, 5, 63 +; CHECK-P9-NEXT: neg 4, 4 +; CHECK-P9-NEXT: maddld 4, 5, 4, 8 +; CHECK-P9-NEXT: maddld 4, 7, 3, 4 +; CHECK-P9-NEXT: mulld 3, 5, 3 +; CHECK-P9-NEXT: sradi 5, 6, 63 +; CHECK-P9-NEXT: addc 3, 3, 6 +; CHECK-P9-NEXT: adde 4, 4, 5 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: add_invalid1: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: clrldi 4, 4, 63 +; CHECK-P8-NEXT: sradi 7, 5, 63 +; CHECK-P8-NEXT: neg 4, 4 +; CHECK-P8-NEXT: mulhdu 8, 5, 3 +; CHECK-P8-NEXT: mulld 4, 5, 4 +; CHECK-P8-NEXT: mulld 7, 7, 3 +; CHECK-P8-NEXT: mulld 3, 5, 3 +; CHECK-P8-NEXT: sradi 5, 6, 63 +; CHECK-P8-NEXT: add 4, 8, 4 +; CHECK-P8-NEXT: add 4, 4, 7 +; CHECK-P8-NEXT: addc 3, 3, 6 +; CHECK-P8-NEXT: adde 4, 4, 5 +; CHECK-P8-NEXT: blr +entry: + %conv = sext i65 %a to i128 + %conv1 = sext i64 %b to i128 + %mul = mul nsw i128 %conv1, %conv + %conv2 = sext i64 %c to i128 + %add = add nsw i128 %mul, %conv2 + ret i128 %add +} + +define i128 @add_highDWZero(i32 noundef %a, i31 noundef %b, i63 noundef %c) { +; CHECK-P9-LABEL: add_highDWZero: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: clrldi 3, 3, 32 +; CHECK-P9-NEXT: clrldi 4, 4, 33 +; CHECK-P9-NEXT: clrldi 5, 5, 1 +; CHECK-P9-NEXT: maddld 3, 4, 3, 5 +; CHECK-P9-NEXT: li 4, 0 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: add_highDWZero: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: clrldi 3, 3, 32 +; CHECK-P8-NEXT: clrldi 4, 4, 33 +; CHECK-P8-NEXT: mulld 3, 4, 3 +; CHECK-P8-NEXT: clrldi 4, 5, 1 +; CHECK-P8-NEXT: add 3, 3, 4 +; CHECK-P8-NEXT: li 4, 0 +; CHECK-P8-NEXT: blr +entry: + %conv = zext i32 %a to i128 + %conv1 = zext i31 %b to i128 + %mul = mul nsw i128 %conv1, %conv + %conv2 = zext i63 %c to i128 + %add = add nsw i128 %mul, %conv2 + ret i128 %add +} + +define i128 @add_sext_highDWNonZero(i16 noundef %a, i16 noundef %b, i16 noundef %c) { +; CHECK-P9-LABEL: add_sext_highDWNonZero: +; CHECK-P9: # %bb.0: # %entry +; CHECK-P9-NEXT: extsh 3, 3 +; CHECK-P9-NEXT: extsh 4, 4 +; CHECK-P9-NEXT: mulld 6, 4, 3 +; CHECK-P9-NEXT: mulhd 4, 4, 3 +; CHECK-P9-NEXT: extsh 3, 5 +; CHECK-P9-NEXT: sradi 5, 3, 63 +; CHECK-P9-NEXT: addc 3, 6, 3 +; CHECK-P9-NEXT: adde 4, 4, 5 +; CHECK-P9-NEXT: blr +; +; CHECK-P8-LABEL: add_sext_highDWNonZero: +; CHECK-P8: # %bb.0: # %entry +; CHECK-P8-NEXT: extsh 3, 3 +; CHECK-P8-NEXT: extsh 4, 4 +; CHECK-P8-NEXT: mulld 6, 4, 3 +; CHECK-P8-NEXT: mulhd 4, 4, 3 +; CHECK-P8-NEXT: extsh 3, 5 +; CHECK-P8-NEXT: sradi 5, 3, 63 +; CHECK-P8-NEXT: addc 3, 6, 3 +; CHECK-P8-NEXT: adde 4, 4, 5 +; CHECK-P8-NEXT: blr +entry: + %conv = sext i16 %a to i128 + %conv1 = sext i16 %b to i128 + %mul = mul nsw i128 %conv1, %conv + %conv2 = sext i16 %c to i128 + %add = add nsw i128 %mul, %conv2 + ret i128 %add +}