diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
--- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
@@ -408,6 +408,12 @@
       for (MachineInstr *MI : InstrsToErase)
         MI->eraseFromParent();
       NumRemovedInPreEmit += InstrsToErase.size();
+      // Fixup liveins to make verifier happy.
+      if (!InstrsToErase.empty()) {
+        LivePhysRegs LPR;
+        MBB.clearLiveIns();
+        computeAndAddLiveIns(LPR, MBB);
+      }
       return !InstrsToErase.empty();
     }
 
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
--- a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
@@ -2,6 +2,10 @@
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
 ; RUN:    | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
+; RUN:     -ppc-track-subreg-liveness < %s | FileCheck --check-prefix=SUBREG %s
+
 
 define void @copy_novsrp() local_unnamed_addr {
 ; CHECK-LABEL: copy_novsrp:
@@ -10,6 +14,12 @@
 ; CHECK-NEXT:    xxlxor vs0, vs0, vs0
 ; CHECK-NEXT:    xxlor vs3, v2, v2
 ; CHECK-NEXT:    stxv vs1, 0(0)
+;
+; SUBREG-LABEL: copy_novsrp:
+; SUBREG:       # %bb.0: # %dmblvi_entry
+; SUBREG-NEXT:    xxlxor vs3, vs3, vs3
+; SUBREG-NEXT:    xxlxor vs0, vs0, vs0
+; SUBREG-NEXT:    stxv vs1, 0(0)
 dmblvi_entry:
   %0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> zeroinitializer, <16 x i8> undef, <16 x i8> undef, <16 x i8> zeroinitializer)
   %1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)