diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -1112,6 +1112,10 @@
   def ZZ_d_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'d'>"> {
     let ParserMatchClass = ZPRVectorListMul<64, 2>;
   }
+
+  def ZZ_q_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'q'>"> {
+    let ParserMatchClass = ZPRVectorListMul<128, 2>;
+  }
 } // end let EncoderMethod/DecoderMethod
 
 let EncoderMethod = "EncodeRegAsMultipleOf<4>",
@@ -1131,6 +1135,10 @@
   def ZZZZ_d_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'d'>"> {
     let ParserMatchClass = ZPRVectorListMul<64, 4>;
   }
+
+  def ZZZZ_q_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'q'>"> {
+    let ParserMatchClass = ZPRVectorListMul<128, 4>;
+  }
 } // end let EncoderMethod/DecoderMethod
 
 class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,
diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
--- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
@@ -367,13 +367,13 @@
 defm UQCVTN_Z4Z     : sme2_int_cvt_vg4_single<"uqcvtn", 0b011>;
 
 def FCVTZS_2Z2Z_StoS : sme2_fp_cvt_vg2_multi<"fcvtzs", 0b010>;
-def FCVTZS_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"fcvtzs", 0b010>;
+defm FCVTZS_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"fcvtzs", 0b010>;
 def FCVTZU_2Z2Z_StoS : sme2_fp_cvt_vg2_multi<"fcvtzu", 0b011>;
-def FCVTZU_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"fcvtzu", 0b011>;
+defm FCVTZU_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"fcvtzu", 0b011>;
 def SCVTF_2Z2Z_StoS  : sme2_fp_cvt_vg2_multi<"scvtf", 0b100>;
-def SCVTF_4Z4Z_StoS  : sme2_fp_cvt_vg4_multi<"scvtf", 0b100>;
+defm SCVTF_4Z4Z_StoS  : sme2_fp_cvt_vg4_multi<"scvtf", 0b100>;
 def UCVTF_2Z2Z_StoS  : sme2_fp_cvt_vg2_multi<"ucvtf", 0b101>;
-def UCVTF_4Z4Z_StoS  : sme2_fp_cvt_vg4_multi<"ucvtf", 0b101>;
+defm UCVTF_4Z4Z_StoS  : sme2_fp_cvt_vg4_multi<"ucvtf", 0b101>;
 
 defm SMAX_VG2_2ZZ  : sme2_int_sve_destructive_vector_vg2_single<"smax", 0b0000000>;
 defm SMAX_VG4_4ZZ  : sme2_int_sve_destructive_vector_vg4_single<"smax", 0b0000000>;
@@ -575,6 +575,16 @@
 defm LUTI4_ZTZI  : sme2_luti4_vector_index<"luti4">;
 defm LUTI4_2ZTZI : sme2_luti4_vector_vg2_index<"luti4">;
 defm LUTI4_4ZTZI : sme2_luti4_vector_vg4_index<"luti4">;
+
+defm SUNPK_VG2_2ZZ  : sme2_unpk_vector_vg2<"sunpk", 0b0>;
+defm SUNPK_VG4_4Z2Z : sme2_unpk_vector_vg4<"sunpk", 0b0>;
+defm UUNPK_VG2_2ZZ  : sme2_unpk_vector_vg2<"uunpk", 0b1>;
+defm UUNPK_VG4_4Z2Z : sme2_unpk_vector_vg4<"uunpk", 0b1>;
+
+defm ZIP_VG2_2ZZZ : sme2_zip_vector_vg2<"zip", 0b0>;
+defm UZP_VG2_2ZZZ : sme2_zip_vector_vg2<"uzp", 0b1>;
+defm ZIP_VG4_4Z4Z : sme2_zip_vector_vg4<"zip", 0b0>;
+defm UZP_VG4_4Z4Z : sme2_zip_vector_vg4<"uzp", 0b1>;
 }
 
 let Predicates = [HasSME2, HasSMEI16I64] in {
diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td
--- a/llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -1820,27 +1820,44 @@
 }
 
 
-class sme2_fp_cvt_vg4_multi<string mnemonic, bits<3> op>
-    : I<(outs ZZZZ_s_mul_r:$Zd), (ins ZZZZ_s_mul_r:$Zn),
+class sme2_zip_cvt_vg4_multi<bits<4> op1, bits<3> op2,
+                             bit op3, RegisterOperand first_vector_ty,
+                              RegisterOperand second_vector_ty,string  mnemonic>
+    : I<(outs first_vector_ty:$Zd), (ins second_vector_ty:$Zn),
          mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
   bits<3> Zn;
   bits<3> Zd;
-  let Inst{31-18} = 0b11000001001100;
-  let Inst{17-16} = op{2-1};
+  let Inst{31-24} = 0b11000001;
+  let Inst{23-22} = op1{3-2};  //sz
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = op1{1-0};
+  let Inst{17-16} = op2{2-1};
   let Inst{15-10} = 0b111000;
   let Inst{9-7}   = Zn;
   let Inst{6}     = 0b0;
-  let Inst{5}     = op{0};
+  let Inst{5}     = op2{0};
   let Inst{4-2}   = Zd;
-  let Inst{1-0}   = 0b00;
+  let Inst{1}     = op3;
+  let Inst{0}     = 0b0;
 }
 
+multiclass sme2_fp_cvt_vg4_multi<string mnemonic, bits<3> op> {
+  def _S : sme2_zip_cvt_vg4_multi<0b0000, op, 0b0,  ZZZZ_s_mul_r, ZZZZ_s_mul_r, mnemonic>;
+}
+
+multiclass sme2_zip_vector_vg4<string mnemonic, bit op> {
+  def _B : sme2_zip_cvt_vg4_multi<0b0001, 0b100, op, ZZZZ_b_mul_r, ZZZZ_b_mul_r, mnemonic>;
+  def _H : sme2_zip_cvt_vg4_multi<0b0101, 0b100, op, ZZZZ_h_mul_r, ZZZZ_h_mul_r, mnemonic>;
+  def _S : sme2_zip_cvt_vg4_multi<0b1001, 0b100, op, ZZZZ_s_mul_r, ZZZZ_s_mul_r, mnemonic>;
+  def _D : sme2_zip_cvt_vg4_multi<0b1101, 0b100, op, ZZZZ_d_mul_r, ZZZZ_d_mul_r, mnemonic>;
+  def _Q : sme2_zip_cvt_vg4_multi<0b0001, 0b110, op, ZZZZ_q_mul_r, ZZZZ_q_mul_r, mnemonic>;
+}
 //===----------------------------------------------------------------------===//
 // SME2 multi-vec CLAMP registers
 
-class sme2_clamp_vector_vg24_multi<bits<2> sz, bits<2> op1, bit u,
-                                   RegisterOperand multi_vector_ty,
-                                   ZPRRegOp vector_ty, string mnemonic>
+class sme2_zip_clamp_vector_vg24_multi<bits<2> sz, bits<3> op1, bit u,
+                                       RegisterOperand multi_vector_ty,
+                                       ZPRRegOp vector_ty, string mnemonic>
     : I<(outs multi_vector_ty:$Zd),
         (ins  multi_vector_ty:$_Zd, vector_ty:$Zn, vector_ty:$Zm),
         mnemonic, "\t$Zd, $Zn, $Zm",
@@ -1851,40 +1868,48 @@
   let Inst{23-22} = sz;
   let Inst{21}    = 0b1;
   let Inst{20-16} = Zm;
-  let Inst{15-12} = 0b1100;
-  let Inst{11-10} = op1;
+  let Inst{15-13} = 0b110;
+  let Inst{12-10} = op1;
   let Inst{9-5}   = Zn;
   let Inst{0}     = u;
 
   let Constraints = "$Zd = $_Zd";
 }
 
-class sme2_clamp_vector_vg2_multi<bits<2> sz, bits<2> op1, bit u,
-                                  RegisterOperand multi_vector_ty,
-                                  ZPRRegOp vector_ty, string mnemonic>
-    : sme2_clamp_vector_vg24_multi<sz, op1, u, multi_vector_ty, vector_ty,
+class sme2_zip_clamp_vector_vg2_multi<bits<2> sz, bits<3> op1, bit u,
+                                      RegisterOperand multi_vector_ty,
+                                      ZPRRegOp vector_ty, string mnemonic>
+    : sme2_zip_clamp_vector_vg24_multi<sz, op1, u, multi_vector_ty, vector_ty,
                                    mnemonic>{
   bits<4> Zd;
   let Inst{4-1} = Zd;
 }
 
 multiclass sme2_fp_clamp_vector_vg2_multi<string mnemonic>{
-  def _H : sme2_clamp_vector_vg2_multi<0b01, 0b00, 0b0, ZZ_h_mul_r, ZPR16, mnemonic>;
-  def _S : sme2_clamp_vector_vg2_multi<0b10, 0b00, 0b0, ZZ_s_mul_r, ZPR32, mnemonic>;
-  def _D : sme2_clamp_vector_vg2_multi<0b11, 0b00, 0b0, ZZ_d_mul_r, ZPR64, mnemonic>;
+  def _H : sme2_zip_clamp_vector_vg2_multi<0b01, 0b000, 0b0, ZZ_h_mul_r, ZPR16, mnemonic>;
+  def _S : sme2_zip_clamp_vector_vg2_multi<0b10, 0b000, 0b0, ZZ_s_mul_r, ZPR32, mnemonic>;
+  def _D : sme2_zip_clamp_vector_vg2_multi<0b11, 0b000, 0b0, ZZ_d_mul_r, ZPR64, mnemonic>;
 }
 
 multiclass sme2_int_clamp_vector_vg2_multi<string mnemonic, bit u>{
-  def _B : sme2_clamp_vector_vg2_multi<0b00, 0b01, u, ZZ_b_mul_r, ZPR8, mnemonic>;
-  def _H : sme2_clamp_vector_vg2_multi<0b01, 0b01, u, ZZ_h_mul_r, ZPR16, mnemonic>;
-  def _S : sme2_clamp_vector_vg2_multi<0b10, 0b01, u, ZZ_s_mul_r, ZPR32, mnemonic>;
-  def _D : sme2_clamp_vector_vg2_multi<0b11, 0b01, u, ZZ_d_mul_r, ZPR64, mnemonic>;
+  def _B : sme2_zip_clamp_vector_vg2_multi<0b00, 0b001, u, ZZ_b_mul_r, ZPR8, mnemonic>;
+  def _H : sme2_zip_clamp_vector_vg2_multi<0b01, 0b001, u, ZZ_h_mul_r, ZPR16, mnemonic>;
+  def _S : sme2_zip_clamp_vector_vg2_multi<0b10, 0b001, u, ZZ_s_mul_r, ZPR32, mnemonic>;
+  def _D : sme2_zip_clamp_vector_vg2_multi<0b11, 0b001, u, ZZ_d_mul_r, ZPR64, mnemonic>;
 }
 
-class sme2_clamp_vector_vg4_multi<bits<2> sz, bits<2> op1, bit u,
+multiclass sme2_zip_vector_vg2<string mnemonic, bit op> {
+  def _B : sme2_zip_clamp_vector_vg2_multi<0b00, 0b100, op, ZZ_b_mul_r, ZPR8, mnemonic>;
+  def _H : sme2_zip_clamp_vector_vg2_multi<0b01, 0b100, op, ZZ_h_mul_r, ZPR16, mnemonic>;
+  def _S : sme2_zip_clamp_vector_vg2_multi<0b10, 0b100, op, ZZ_s_mul_r, ZPR32, mnemonic>;
+  def _D : sme2_zip_clamp_vector_vg2_multi<0b11, 0b100, op, ZZ_d_mul_r, ZPR64, mnemonic>;
+  def _Q : sme2_zip_clamp_vector_vg2_multi<0b00, 0b101, op, ZZ_q_mul_r, ZPR128, mnemonic>;
+}
+
+class sme2_clamp_vector_vg4_multi<bits<2> sz, bits<3> op1, bit u,
                                   RegisterOperand multi_vector_ty,
                                   ZPRRegOp vector_ty, string mnemonic>
-    : sme2_clamp_vector_vg24_multi<sz, op1, u,  multi_vector_ty, vector_ty,
+    : sme2_zip_clamp_vector_vg24_multi<sz, op1, u,  multi_vector_ty, vector_ty,
                                    mnemonic>{
   bits<3> Zd;
   let Inst{4-2} = Zd;
@@ -1892,16 +1917,16 @@
 }
 
 multiclass sme2_fp_clamp_vector_vg4_multi<string mnemonic>{
-  def _H : sme2_clamp_vector_vg4_multi<0b01, 0b10, 0b0, ZZZZ_h_mul_r, ZPR16, mnemonic>;
-  def _S : sme2_clamp_vector_vg4_multi<0b10, 0b10, 0b0, ZZZZ_s_mul_r, ZPR32, mnemonic>;
-  def _D : sme2_clamp_vector_vg4_multi<0b11, 0b10, 0b0, ZZZZ_d_mul_r, ZPR64, mnemonic>;
+  def _H : sme2_clamp_vector_vg4_multi<0b01, 0b010, 0b0, ZZZZ_h_mul_r, ZPR16, mnemonic>;
+  def _S : sme2_clamp_vector_vg4_multi<0b10, 0b010, 0b0, ZZZZ_s_mul_r, ZPR32, mnemonic>;
+  def _D : sme2_clamp_vector_vg4_multi<0b11, 0b010, 0b0, ZZZZ_d_mul_r, ZPR64, mnemonic>;
 }
 
 multiclass sme2_int_clamp_vector_vg4_multi<string mnemonic, bit u>{
-  def _B : sme2_clamp_vector_vg4_multi<0b00, 0b11, u, ZZZZ_b_mul_r, ZPR8, mnemonic>;
-  def _H : sme2_clamp_vector_vg4_multi<0b01, 0b11, u, ZZZZ_h_mul_r, ZPR16, mnemonic>;
-  def _S : sme2_clamp_vector_vg4_multi<0b10, 0b11, u, ZZZZ_s_mul_r, ZPR32, mnemonic>;
-  def _D : sme2_clamp_vector_vg4_multi<0b11, 0b11, u, ZZZZ_d_mul_r, ZPR64, mnemonic>;
+  def _B : sme2_clamp_vector_vg4_multi<0b00, 0b011, u, ZZZZ_b_mul_r, ZPR8, mnemonic>;
+  def _H : sme2_clamp_vector_vg4_multi<0b01, 0b011, u, ZZZZ_h_mul_r, ZPR16, mnemonic>;
+  def _S : sme2_clamp_vector_vg4_multi<0b10, 0b011, u, ZZZZ_s_mul_r, ZPR32, mnemonic>;
+  def _D : sme2_clamp_vector_vg4_multi<0b11, 0b011, u, ZZZZ_d_mul_r, ZPR64, mnemonic>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -2565,3 +2590,53 @@
   def _H : sme2_luti4_vector_vg4_index<0b01, ZZZZ_h_mul_r, mnemonic>;
   def _S : sme2_luti4_vector_vg4_index<0b10, ZZZZ_s_mul_r, mnemonic>;
 }
+
+//===----------------------------------------------------------------------===//
+// SME2 multi-vec unpack two registers
+//===----------------------------------------------------------------------===//
+
+class sme2_unpk_vector_vg2<bits<2> sz, bit u, RegisterOperand vector_ty,
+                        ZPRRegOp zpr_ty, string mnemonic>
+    : I<(outs vector_ty:$Zd), (ins zpr_ty:$Zn),
+        mnemonic, "\t$Zd, $Zn",
+        "", []>, Sched<[]> {
+  bits<5> Zn;
+  bits<4> Zd;
+  let Inst{31-24} = 0b11000001;
+  let Inst{23-22} = sz;
+  let Inst{21-10} = 0b100101111000;
+  let Inst{9-5}   = Zn;
+  let Inst{4-1}   = Zd;
+  let Inst{0}     = u;
+}
+
+multiclass sme2_unpk_vector_vg2<string mnemonic, bit u> {
+  def _H : sme2_unpk_vector_vg2<0b01, u, ZZ_h_mul_r, ZPR8, mnemonic>;
+  def _S : sme2_unpk_vector_vg2<0b10, u, ZZ_s_mul_r, ZPR16, mnemonic>;
+  def _D : sme2_unpk_vector_vg2<0b11, u, ZZ_d_mul_r, ZPR32, mnemonic>;
+}
+
+
+class sme2_unpk_vector_vg4<bits<2> sz, bit u, RegisterOperand first_vector_ty,
+                            RegisterOperand second_vector_ty, string mnemonic>
+    : I<(outs first_vector_ty:$Zd), (ins second_vector_ty:$Zn),
+        mnemonic, "\t$Zd, $Zn",
+        "", []>, Sched<[]> {
+  bits<4> Zn;
+  bits<3> Zd;
+  let Inst{31-24} = 0b11000001;
+  let Inst{23-22} = sz;
+  let Inst{21-10} = 0b110101111000;
+  let Inst{9-6}   = Zn;
+  let Inst{5}     = 0b0;
+  let Inst{4-2}   = Zd;
+  let Inst{1}     = 0b0;
+  let Inst{0}     = u;
+}
+
+multiclass sme2_unpk_vector_vg4<string mnemonic, bit u> {
+  def _H : sme2_unpk_vector_vg4<0b01, u, ZZZZ_h_mul_r, ZZ_b_mul_r, mnemonic>;
+  def _S : sme2_unpk_vector_vg4<0b10, u, ZZZZ_s_mul_r, ZZ_h_mul_r, mnemonic>;
+  def _D : sme2_unpk_vector_vg4<0b11, u, ZZZZ_d_mul_r, ZZ_s_mul_r, mnemonic>;
+}
+
diff --git a/llvm/test/MC/AArch64/SME2/sunpk-diagnostics.s b/llvm/test/MC/AArch64/SME2/sunpk-diagnostics.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sunpk-diagnostics.s
@@ -0,0 +1,32 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+sunpk {z0.h-z2.h}, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sunpk {z0.h-z2.h}, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sunpk {z1.s-z2.s}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: sunpk {z1.s-z2.s}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sunpk {z0.d-z5.d}, {z8.s-z9.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: sunpk {z0.d-z5.d}, {z8.s-z9.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sunpk {z0.s-z3.s}, {z9.h-z11.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sunpk {z0.s-z3.s}, {z9.h-z11.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+sunpk {z0.s-z3.s}, {z8.s-z9.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sunpk {z0.s-z3.s}, {z8.s-z9.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/sunpk.s b/llvm/test/MC/AArch64/SME2/sunpk.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/sunpk.s
@@ -0,0 +1,163 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+sunpk   {z0.h - z1.h}, z0.b  // 11000001-01100101-11100000-00000000
+// CHECK-INST: sunpk   { z0.h, z1.h }, z0.b
+// CHECK-ENCODING: [0x00,0xe0,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e000 <unknown>
+
+sunpk   {z20.h - z21.h}, z10.b  // 11000001-01100101-11100001-01010100
+// CHECK-INST: sunpk   { z20.h, z21.h }, z10.b
+// CHECK-ENCODING: [0x54,0xe1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e154 <unknown>
+
+sunpk   {z22.h - z23.h}, z13.b  // 11000001-01100101-11100001-10110110
+// CHECK-INST: sunpk   { z22.h, z23.h }, z13.b
+// CHECK-ENCODING: [0xb6,0xe1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e1b6 <unknown>
+
+sunpk   {z30.h - z31.h}, z31.b  // 11000001-01100101-11100011-11111110
+// CHECK-INST: sunpk   { z30.h, z31.h }, z31.b
+// CHECK-ENCODING: [0xfe,0xe3,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e3fe <unknown>
+
+
+sunpk   {z0.s - z1.s}, z0.h  // 11000001-10100101-11100000-00000000
+// CHECK-INST: sunpk   { z0.s, z1.s }, z0.h
+// CHECK-ENCODING: [0x00,0xe0,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e000 <unknown>
+
+sunpk   {z20.s - z21.s}, z10.h  // 11000001-10100101-11100001-01010100
+// CHECK-INST: sunpk   { z20.s, z21.s }, z10.h
+// CHECK-ENCODING: [0x54,0xe1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e154 <unknown>
+
+sunpk   {z22.s - z23.s}, z13.h  // 11000001-10100101-11100001-10110110
+// CHECK-INST: sunpk   { z22.s, z23.s }, z13.h
+// CHECK-ENCODING: [0xb6,0xe1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e1b6 <unknown>
+
+sunpk   {z30.s - z31.s}, z31.h  // 11000001-10100101-11100011-11111110
+// CHECK-INST: sunpk   { z30.s, z31.s }, z31.h
+// CHECK-ENCODING: [0xfe,0xe3,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e3fe <unknown>
+
+
+sunpk   {z0.d - z1.d}, z0.s  // 11000001-11100101-11100000-00000000
+// CHECK-INST: sunpk   { z0.d, z1.d }, z0.s
+// CHECK-ENCODING: [0x00,0xe0,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e000 <unknown>
+
+sunpk   {z20.d - z21.d}, z10.s  // 11000001-11100101-11100001-01010100
+// CHECK-INST: sunpk   { z20.d, z21.d }, z10.s
+// CHECK-ENCODING: [0x54,0xe1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e154 <unknown>
+
+sunpk   {z22.d - z23.d}, z13.s  // 11000001-11100101-11100001-10110110
+// CHECK-INST: sunpk   { z22.d, z23.d }, z13.s
+// CHECK-ENCODING: [0xb6,0xe1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e1b6 <unknown>
+
+sunpk   {z30.d - z31.d}, z31.s  // 11000001-11100101-11100011-11111110
+// CHECK-INST: sunpk   { z30.d, z31.d }, z31.s
+// CHECK-ENCODING: [0xfe,0xe3,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e3fe <unknown>
+
+
+sunpk   {z0.h - z3.h}, {z0.b - z1.b}  // 11000001-01110101-11100000-00000000
+// CHECK-INST: sunpk   { z0.h - z3.h }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x00,0xe0,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e000 <unknown>
+
+sunpk   {z20.h - z23.h}, {z10.b - z11.b}  // 11000001-01110101-11100001-01010100
+// CHECK-INST: sunpk   { z20.h - z23.h }, { z10.b, z11.b }
+// CHECK-ENCODING: [0x54,0xe1,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e154 <unknown>
+
+sunpk   {z20.h - z23.h}, {z12.b - z13.b}  // 11000001-01110101-11100001-10010100
+// CHECK-INST: sunpk   { z20.h - z23.h }, { z12.b, z13.b }
+// CHECK-ENCODING: [0x94,0xe1,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e194 <unknown>
+
+sunpk   {z28.h - z31.h}, {z30.b - z31.b}  // 11000001-01110101-11100011-11011100
+// CHECK-INST: sunpk   { z28.h - z31.h }, { z30.b, z31.b }
+// CHECK-ENCODING: [0xdc,0xe3,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e3dc <unknown>
+
+
+sunpk   {z0.s - z3.s}, {z0.h - z1.h}  // 11000001-10110101-11100000-00000000
+// CHECK-INST: sunpk   { z0.s - z3.s }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x00,0xe0,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e000 <unknown>
+
+sunpk   {z20.s - z23.s}, {z10.h - z11.h}  // 11000001-10110101-11100001-01010100
+// CHECK-INST: sunpk   { z20.s - z23.s }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x54,0xe1,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e154 <unknown>
+
+sunpk   {z20.s - z23.s}, {z12.h - z13.h}  // 11000001-10110101-11100001-10010100
+// CHECK-INST: sunpk   { z20.s - z23.s }, { z12.h, z13.h }
+// CHECK-ENCODING: [0x94,0xe1,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e194 <unknown>
+
+sunpk   {z28.s - z31.s}, {z30.h - z31.h}  // 11000001-10110101-11100011-11011100
+// CHECK-INST: sunpk   { z28.s - z31.s }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xdc,0xe3,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e3dc <unknown>
+
+
+sunpk   {z0.d - z3.d}, {z0.s - z1.s}  // 11000001-11110101-11100000-00000000
+// CHECK-INST: sunpk   { z0.d - z3.d }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0xe0,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e000 <unknown>
+
+sunpk   {z20.d - z23.d}, {z10.s - z11.s}  // 11000001-11110101-11100001-01010100
+// CHECK-INST: sunpk   { z20.d - z23.d }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x54,0xe1,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e154 <unknown>
+
+sunpk   {z20.d - z23.d}, {z12.s - z13.s}  // 11000001-11110101-11100001-10010100
+// CHECK-INST: sunpk   { z20.d - z23.d }, { z12.s, z13.s }
+// CHECK-ENCODING: [0x94,0xe1,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e194 <unknown>
+
+sunpk   {z28.d - z31.d}, {z30.s - z31.s}  // 11000001-11110101-11100011-11011100
+// CHECK-INST: sunpk   { z28.d - z31.d }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xdc,0xe3,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e3dc <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/uunpk-diagnostics.s b/llvm/test/MC/AArch64/SME2/uunpk-diagnostics.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/uunpk-diagnostics.s
@@ -0,0 +1,32 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+uunpk {z0.h-z2.h}, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uunpk {z0.h-z2.h}, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uunpk {z1.s-z2.s}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: uunpk {z1.s-z2.s}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uunpk {z0.d-z5.d}, {z8.s-z9.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: uunpk {z0.d-z5.d}, {z8.s-z9.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uunpk {z0.s-z3.s}, {z9.h-z11.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uunpk {z0.s-z3.s}, {z9.h-z11.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+uunpk {z0.s-z3.s}, {z8.s-z9.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uunpk {z0.s-z3.s}, {z8.s-z9.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2/uunpk.s b/llvm/test/MC/AArch64/SME2/uunpk.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/uunpk.s
@@ -0,0 +1,163 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+uunpk   {z0.h - z1.h}, z0.b  // 11000001-01100101-11100000-00000001
+// CHECK-INST: uunpk   { z0.h, z1.h }, z0.b
+// CHECK-ENCODING: [0x01,0xe0,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e001 <unknown>
+
+uunpk   {z20.h - z21.h}, z10.b  // 11000001-01100101-11100001-01010101
+// CHECK-INST: uunpk   { z20.h, z21.h }, z10.b
+// CHECK-ENCODING: [0x55,0xe1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e155 <unknown>
+
+uunpk   {z22.h - z23.h}, z13.b  // 11000001-01100101-11100001-10110111
+// CHECK-INST: uunpk   { z22.h, z23.h }, z13.b
+// CHECK-ENCODING: [0xb7,0xe1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e1b7 <unknown>
+
+uunpk   {z30.h - z31.h}, z31.b  // 11000001-01100101-11100011-11111111
+// CHECK-INST: uunpk   { z30.h, z31.h }, z31.b
+// CHECK-ENCODING: [0xff,0xe3,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e3ff <unknown>
+
+
+uunpk   {z0.s - z1.s}, z0.h  // 11000001-10100101-11100000-00000001
+// CHECK-INST: uunpk   { z0.s, z1.s }, z0.h
+// CHECK-ENCODING: [0x01,0xe0,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e001 <unknown>
+
+uunpk   {z20.s - z21.s}, z10.h  // 11000001-10100101-11100001-01010101
+// CHECK-INST: uunpk   { z20.s, z21.s }, z10.h
+// CHECK-ENCODING: [0x55,0xe1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e155 <unknown>
+
+uunpk   {z22.s - z23.s}, z13.h  // 11000001-10100101-11100001-10110111
+// CHECK-INST: uunpk   { z22.s, z23.s }, z13.h
+// CHECK-ENCODING: [0xb7,0xe1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e1b7 <unknown>
+
+uunpk   {z30.s - z31.s}, z31.h  // 11000001-10100101-11100011-11111111
+// CHECK-INST: uunpk   { z30.s, z31.s }, z31.h
+// CHECK-ENCODING: [0xff,0xe3,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e3ff <unknown>
+
+
+uunpk   {z0.d - z1.d}, z0.s  // 11000001-11100101-11100000-00000001
+// CHECK-INST: uunpk   { z0.d, z1.d }, z0.s
+// CHECK-ENCODING: [0x01,0xe0,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e001 <unknown>
+
+uunpk   {z20.d - z21.d}, z10.s  // 11000001-11100101-11100001-01010101
+// CHECK-INST: uunpk   { z20.d, z21.d }, z10.s
+// CHECK-ENCODING: [0x55,0xe1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e155 <unknown>
+
+uunpk   {z22.d - z23.d}, z13.s  // 11000001-11100101-11100001-10110111
+// CHECK-INST: uunpk   { z22.d, z23.d }, z13.s
+// CHECK-ENCODING: [0xb7,0xe1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e1b7 <unknown>
+
+uunpk   {z30.d - z31.d}, z31.s  // 11000001-11100101-11100011-11111111
+// CHECK-INST: uunpk   { z30.d, z31.d }, z31.s
+// CHECK-ENCODING: [0xff,0xe3,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e3ff <unknown>
+
+
+uunpk   {z0.h - z3.h}, {z0.b - z1.b}  // 11000001-01110101-11100000-00000001
+// CHECK-INST: uunpk   { z0.h - z3.h }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x01,0xe0,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e001 <unknown>
+
+uunpk   {z20.h - z23.h}, {z10.b - z11.b}  // 11000001-01110101-11100001-01010101
+// CHECK-INST: uunpk   { z20.h - z23.h }, { z10.b, z11.b }
+// CHECK-ENCODING: [0x55,0xe1,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e155 <unknown>
+
+uunpk   {z20.h - z23.h}, {z12.b - z13.b}  // 11000001-01110101-11100001-10010101
+// CHECK-INST: uunpk   { z20.h - z23.h }, { z12.b, z13.b }
+// CHECK-ENCODING: [0x95,0xe1,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e195 <unknown>
+
+uunpk   {z28.h - z31.h}, {z30.b - z31.b}  // 11000001-01110101-11100011-11011101
+// CHECK-INST: uunpk   { z28.h - z31.h }, { z30.b, z31.b }
+// CHECK-ENCODING: [0xdd,0xe3,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e3dd <unknown>
+
+
+uunpk   {z0.s - z3.s}, {z0.h - z1.h}  // 11000001-10110101-11100000-00000001
+// CHECK-INST: uunpk   { z0.s - z3.s }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x01,0xe0,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e001 <unknown>
+
+uunpk   {z20.s - z23.s}, {z10.h - z11.h}  // 11000001-10110101-11100001-01010101
+// CHECK-INST: uunpk   { z20.s - z23.s }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x55,0xe1,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e155 <unknown>
+
+uunpk   {z20.s - z23.s}, {z12.h - z13.h}  // 11000001-10110101-11100001-10010101
+// CHECK-INST: uunpk   { z20.s - z23.s }, { z12.h, z13.h }
+// CHECK-ENCODING: [0x95,0xe1,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e195 <unknown>
+
+uunpk   {z28.s - z31.s}, {z30.h - z31.h}  // 11000001-10110101-11100011-11011101
+// CHECK-INST: uunpk   { z28.s - z31.s }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xdd,0xe3,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e3dd <unknown>
+
+
+uunpk   {z0.d - z3.d}, {z0.s - z1.s}  // 11000001-11110101-11100000-00000001
+// CHECK-INST: uunpk   { z0.d - z3.d }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x01,0xe0,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e001 <unknown>
+
+uunpk   {z20.d - z23.d}, {z10.s - z11.s}  // 11000001-11110101-11100001-01010101
+// CHECK-INST: uunpk   { z20.d - z23.d }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x55,0xe1,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e155 <unknown>
+
+uunpk   {z20.d - z23.d}, {z12.s - z13.s}  // 11000001-11110101-11100001-10010101
+// CHECK-INST: uunpk   { z20.d - z23.d }, { z12.s, z13.s }
+// CHECK-ENCODING: [0x95,0xe1,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e195 <unknown>
+
+uunpk   {z28.d - z31.d}, {z30.s - z31.s}  // 11000001-11110101-11100011-11011101
+// CHECK-INST: uunpk   { z28.d - z31.d }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xdd,0xe3,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e3dd <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/uzp-diagnostics.s b/llvm/test/MC/AArch64/SME2/uzp-diagnostics.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/uzp-diagnostics.s
@@ -0,0 +1,25 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+uzp {z0.q-z2.q}, z0.q, z0.q
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uzp {z0.q-z2.q}, z0.q, z0.q
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uzp {z21.h-z22.h}, z10.h, z21.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: uzp {z21.h-z22.h}, z10.h, z21.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uzp {z0.s-z4.s}, {z0.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: uzp {z0.s-z4.s}, {z0.s-z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uzp {z20.b-z23.b}, {z9.b-z12.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: uzp {z20.b-z23.b}, {z9.b-z12.b}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
diff --git a/llvm/test/MC/AArch64/SME2/uzp.s b/llvm/test/MC/AArch64/SME2/uzp.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/uzp.s
@@ -0,0 +1,263 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+uzp     {z0.q - z1.q}, z0.q, z0.q  // 11000001-00100000-11010100-00000001
+// CHECK-INST: uzp     { z0.q, z1.q }, z0.q, z0.q
+// CHECK-ENCODING: [0x01,0xd4,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120d401 <unknown>
+
+uzp     {z20.q - z21.q}, z10.q, z21.q  // 11000001-00110101-11010101-01010101
+// CHECK-INST: uzp     { z20.q, z21.q }, z10.q, z21.q
+// CHECK-ENCODING: [0x55,0xd5,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c135d555 <unknown>
+
+uzp     {z22.q - z23.q}, z13.q, z8.q  // 11000001-00101000-11010101-10110111
+// CHECK-INST: uzp     { z22.q, z23.q }, z13.q, z8.q
+// CHECK-ENCODING: [0xb7,0xd5,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128d5b7 <unknown>
+
+uzp     {z30.q - z31.q}, z31.q, z31.q  // 11000001-00111111-11010111-11111111
+// CHECK-INST: uzp     { z30.q, z31.q }, z31.q, z31.q
+// CHECK-ENCODING: [0xff,0xd7,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13fd7ff <unknown>
+
+
+uzp     {z0.h - z1.h}, z0.h, z0.h  // 11000001-01100000-11010000-00000001
+// CHECK-INST: uzp     { z0.h, z1.h }, z0.h, z0.h
+// CHECK-ENCODING: [0x01,0xd0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160d001 <unknown>
+
+uzp     {z20.h - z21.h}, z10.h, z21.h  // 11000001-01110101-11010001-01010101
+// CHECK-INST: uzp     { z20.h, z21.h }, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0xd1,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175d155 <unknown>
+
+uzp     {z22.h - z23.h}, z13.h, z8.h  // 11000001-01101000-11010001-10110111
+// CHECK-INST: uzp     { z22.h, z23.h }, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0xd1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168d1b7 <unknown>
+
+uzp     {z30.h - z31.h}, z31.h, z31.h  // 11000001-01111111-11010011-11111111
+// CHECK-INST: uzp     { z30.h, z31.h }, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0xd3,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fd3ff <unknown>
+
+
+uzp     {z0.s - z1.s}, z0.s, z0.s  // 11000001-10100000-11010000-00000001
+// CHECK-INST: uzp     { z0.s, z1.s }, z0.s, z0.s
+// CHECK-ENCODING: [0x01,0xd0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0d001 <unknown>
+
+uzp     {z20.s - z21.s}, z10.s, z21.s  // 11000001-10110101-11010001-01010101
+// CHECK-INST: uzp     { z20.s, z21.s }, z10.s, z21.s
+// CHECK-ENCODING: [0x55,0xd1,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5d155 <unknown>
+
+uzp     {z22.s - z23.s}, z13.s, z8.s  // 11000001-10101000-11010001-10110111
+// CHECK-INST: uzp     { z22.s, z23.s }, z13.s, z8.s
+// CHECK-ENCODING: [0xb7,0xd1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8d1b7 <unknown>
+
+uzp     {z30.s - z31.s}, z31.s, z31.s  // 11000001-10111111-11010011-11111111
+// CHECK-INST: uzp     { z30.s, z31.s }, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0xd3,0xbf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bfd3ff <unknown>
+
+
+uzp     {z0.d - z1.d}, z0.d, z0.d  // 11000001-11100000-11010000-00000001
+// CHECK-INST: uzp     { z0.d, z1.d }, z0.d, z0.d
+// CHECK-ENCODING: [0x01,0xd0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0d001 <unknown>
+
+uzp     {z20.d - z21.d}, z10.d, z21.d  // 11000001-11110101-11010001-01010101
+// CHECK-INST: uzp     { z20.d, z21.d }, z10.d, z21.d
+// CHECK-ENCODING: [0x55,0xd1,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5d155 <unknown>
+
+uzp     {z22.d - z23.d}, z13.d, z8.d  // 11000001-11101000-11010001-10110111
+// CHECK-INST: uzp     { z22.d, z23.d }, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0xd1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8d1b7 <unknown>
+
+uzp     {z30.d - z31.d}, z31.d, z31.d  // 11000001-11111111-11010011-11111111
+// CHECK-INST: uzp     { z30.d, z31.d }, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0xd3,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffd3ff <unknown>
+
+
+uzp     {z0.b - z1.b}, z0.b, z0.b  // 11000001-00100000-11010000-00000001
+// CHECK-INST: uzp     { z0.b, z1.b }, z0.b, z0.b
+// CHECK-ENCODING: [0x01,0xd0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120d001 <unknown>
+
+uzp     {z20.b - z21.b}, z10.b, z21.b  // 11000001-00110101-11010001-01010101
+// CHECK-INST: uzp     { z20.b, z21.b }, z10.b, z21.b
+// CHECK-ENCODING: [0x55,0xd1,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c135d155 <unknown>
+
+uzp     {z22.b - z23.b}, z13.b, z8.b  // 11000001-00101000-11010001-10110111
+// CHECK-INST: uzp     { z22.b, z23.b }, z13.b, z8.b
+// CHECK-ENCODING: [0xb7,0xd1,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128d1b7 <unknown>
+
+uzp     {z30.b - z31.b}, z31.b, z31.b  // 11000001-00111111-11010011-11111111
+// CHECK-INST: uzp     { z30.b, z31.b }, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0xd3,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13fd3ff <unknown>
+
+
+uzp     {z0.q - z3.q}, {z0.q - z3.q}  // 11000001-00110111-11100000-00000010
+// CHECK-INST: uzp     { z0.q - z3.q }, { z0.q - z3.q }
+// CHECK-ENCODING: [0x02,0xe0,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e002 <unknown>
+
+uzp     {z20.q - z23.q}, {z8.q - z11.q}  // 11000001-00110111-11100001-00010110
+// CHECK-INST: uzp     { z20.q - z23.q }, { z8.q - z11.q }
+// CHECK-ENCODING: [0x16,0xe1,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e116 <unknown>
+
+uzp     {z20.q - z23.q}, {z12.q - z15.q}  // 11000001-00110111-11100001-10010110
+// CHECK-INST: uzp     { z20.q - z23.q }, { z12.q - z15.q }
+// CHECK-ENCODING: [0x96,0xe1,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e196 <unknown>
+
+uzp     {z28.q - z31.q}, {z28.q - z31.q}  // 11000001-00110111-11100011-10011110
+// CHECK-INST: uzp     { z28.q - z31.q }, { z28.q - z31.q }
+// CHECK-ENCODING: [0x9e,0xe3,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e39e <unknown>
+
+
+uzp     {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01110110-11100000-00000010
+// CHECK-INST: uzp     { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x02,0xe0,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e002 <unknown>
+
+uzp     {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01110110-11100001-00010110
+// CHECK-INST: uzp     { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x16,0xe1,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e116 <unknown>
+
+uzp     {z20.h - z23.h}, {z12.h - z15.h}  // 11000001-01110110-11100001-10010110
+// CHECK-INST: uzp     { z20.h - z23.h }, { z12.h - z15.h }
+// CHECK-ENCODING: [0x96,0xe1,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e196 <unknown>
+
+uzp     {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01110110-11100011-10011110
+// CHECK-INST: uzp     { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x9e,0xe3,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e39e <unknown>
+
+
+uzp     {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10110110-11100000-00000010
+// CHECK-INST: uzp     { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x02,0xe0,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e002 <unknown>
+
+uzp     {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10110110-11100001-00010110
+// CHECK-INST: uzp     { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x16,0xe1,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e116 <unknown>
+
+uzp     {z20.s - z23.s}, {z12.s - z15.s}  // 11000001-10110110-11100001-10010110
+// CHECK-INST: uzp     { z20.s - z23.s }, { z12.s - z15.s }
+// CHECK-ENCODING: [0x96,0xe1,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e196 <unknown>
+
+uzp     {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10110110-11100011-10011110
+// CHECK-INST: uzp     { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x9e,0xe3,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e39e <unknown>
+
+
+uzp     {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11110110-11100000-00000010
+// CHECK-INST: uzp     { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x02,0xe0,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e002 <unknown>
+
+uzp     {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11110110-11100001-00010110
+// CHECK-INST: uzp     { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x16,0xe1,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e116 <unknown>
+
+uzp     {z20.d - z23.d}, {z12.d - z15.d}  // 11000001-11110110-11100001-10010110
+// CHECK-INST: uzp     { z20.d - z23.d }, { z12.d - z15.d }
+// CHECK-ENCODING: [0x96,0xe1,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e196 <unknown>
+
+uzp     {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11110110-11100011-10011110
+// CHECK-INST: uzp     { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x9e,0xe3,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e39e <unknown>
+
+
+uzp     {z0.b - z3.b}, {z0.b - z3.b}  // 11000001-00110110-11100000-00000010
+// CHECK-INST: uzp     { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x02,0xe0,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e002 <unknown>
+
+uzp     {z20.b - z23.b}, {z8.b - z11.b}  // 11000001-00110110-11100001-00010110
+// CHECK-INST: uzp     { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x16,0xe1,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e116 <unknown>
+
+uzp     {z20.b - z23.b}, {z12.b - z15.b}  // 11000001-00110110-11100001-10010110
+// CHECK-INST: uzp     { z20.b - z23.b }, { z12.b - z15.b }
+// CHECK-ENCODING: [0x96,0xe1,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e196 <unknown>
+
+uzp     {z28.b - z31.b}, {z28.b - z31.b}  // 11000001-00110110-11100011-10011110
+// CHECK-INST: uzp     { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x9e,0xe3,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e39e <unknown>
+
diff --git a/llvm/test/MC/AArch64/SME2/zip-diagnostics.s b/llvm/test/MC/AArch64/SME2/zip-diagnostics.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/zip-diagnostics.s
@@ -0,0 +1,25 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+zip {z0.q-z2.q}, z0.q, z0.q
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: zip {z0.q-z2.q}, z0.q, z0.q
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+zip {z21.h-z22.h}, z10.h, z21.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: zip {z21.h-z22.h}, z10.h, z21.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+zip {z0.s-z4.s}, {z0.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: zip {z0.s-z4.s}, {z0.s-z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+zip {z20.b-z23.b}, {z9.b-z12.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: zip {z20.b-z23.b}, {z9.b-z12.b}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
diff --git a/llvm/test/MC/AArch64/SME2/zip.s b/llvm/test/MC/AArch64/SME2/zip.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/zip.s
@@ -0,0 +1,263 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+zip     {z0.q - z1.q}, z0.q, z0.q  // 11000001-00100000-11010100-00000000
+// CHECK-INST: zip     { z0.q, z1.q }, z0.q, z0.q
+// CHECK-ENCODING: [0x00,0xd4,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120d400 <unknown>
+
+zip     {z20.q - z21.q}, z10.q, z21.q  // 11000001-00110101-11010101-01010100
+// CHECK-INST: zip     { z20.q, z21.q }, z10.q, z21.q
+// CHECK-ENCODING: [0x54,0xd5,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c135d554 <unknown>
+
+zip     {z22.q - z23.q}, z13.q, z8.q  // 11000001-00101000-11010101-10110110
+// CHECK-INST: zip     { z22.q, z23.q }, z13.q, z8.q
+// CHECK-ENCODING: [0xb6,0xd5,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128d5b6 <unknown>
+
+zip     {z30.q - z31.q}, z31.q, z31.q  // 11000001-00111111-11010111-11111110
+// CHECK-INST: zip     { z30.q, z31.q }, z31.q, z31.q
+// CHECK-ENCODING: [0xfe,0xd7,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13fd7fe <unknown>
+
+
+zip     {z0.h - z1.h}, z0.h, z0.h  // 11000001-01100000-11010000-00000000
+// CHECK-INST: zip     { z0.h, z1.h }, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0xd0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160d000 <unknown>
+
+zip     {z20.h - z21.h}, z10.h, z21.h  // 11000001-01110101-11010001-01010100
+// CHECK-INST: zip     { z20.h, z21.h }, z10.h, z21.h
+// CHECK-ENCODING: [0x54,0xd1,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175d154 <unknown>
+
+zip     {z22.h - z23.h}, z13.h, z8.h  // 11000001-01101000-11010001-10110110
+// CHECK-INST: zip     { z22.h, z23.h }, z13.h, z8.h
+// CHECK-ENCODING: [0xb6,0xd1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168d1b6 <unknown>
+
+zip     {z30.h - z31.h}, z31.h, z31.h  // 11000001-01111111-11010011-11111110
+// CHECK-INST: zip     { z30.h, z31.h }, z31.h, z31.h
+// CHECK-ENCODING: [0xfe,0xd3,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fd3fe <unknown>
+
+
+zip     {z0.s - z1.s}, z0.s, z0.s  // 11000001-10100000-11010000-00000000
+// CHECK-INST: zip     { z0.s, z1.s }, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0xd0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0d000 <unknown>
+
+zip     {z20.s - z21.s}, z10.s, z21.s  // 11000001-10110101-11010001-01010100
+// CHECK-INST: zip     { z20.s, z21.s }, z10.s, z21.s
+// CHECK-ENCODING: [0x54,0xd1,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5d154 <unknown>
+
+zip     {z22.s - z23.s}, z13.s, z8.s  // 11000001-10101000-11010001-10110110
+// CHECK-INST: zip     { z22.s, z23.s }, z13.s, z8.s
+// CHECK-ENCODING: [0xb6,0xd1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8d1b6 <unknown>
+
+zip     {z30.s - z31.s}, z31.s, z31.s  // 11000001-10111111-11010011-11111110
+// CHECK-INST: zip     { z30.s, z31.s }, z31.s, z31.s
+// CHECK-ENCODING: [0xfe,0xd3,0xbf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bfd3fe <unknown>
+
+
+zip     {z0.d - z1.d}, z0.d, z0.d  // 11000001-11100000-11010000-00000000
+// CHECK-INST: zip     { z0.d, z1.d }, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0xd0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0d000 <unknown>
+
+zip     {z20.d - z21.d}, z10.d, z21.d  // 11000001-11110101-11010001-01010100
+// CHECK-INST: zip     { z20.d, z21.d }, z10.d, z21.d
+// CHECK-ENCODING: [0x54,0xd1,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5d154 <unknown>
+
+zip     {z22.d - z23.d}, z13.d, z8.d  // 11000001-11101000-11010001-10110110
+// CHECK-INST: zip     { z22.d, z23.d }, z13.d, z8.d
+// CHECK-ENCODING: [0xb6,0xd1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8d1b6 <unknown>
+
+zip     {z30.d - z31.d}, z31.d, z31.d  // 11000001-11111111-11010011-11111110
+// CHECK-INST: zip     { z30.d, z31.d }, z31.d, z31.d
+// CHECK-ENCODING: [0xfe,0xd3,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffd3fe <unknown>
+
+
+zip     {z0.b - z1.b}, z0.b, z0.b  // 11000001-00100000-11010000-00000000
+// CHECK-INST: zip     { z0.b, z1.b }, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0xd0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120d000 <unknown>
+
+zip     {z20.b, z21.b}, z10.b, z21.b  // 11000001-00110101-11010001-01010100
+// CHECK-INST: zip     { z20.b, z21.b }, z10.b, z21.b
+// CHECK-ENCODING: [0x54,0xd1,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c135d154 <unknown>
+
+zip     {z22.b - z23.b}, z13.b, z8.b  // 11000001-00101000-11010001-10110110
+// CHECK-INST: zip     { z22.b, z23.b }, z13.b, z8.b
+// CHECK-ENCODING: [0xb6,0xd1,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128d1b6 <unknown>
+
+zip     {z30.b - z31.b}, z31.b, z31.b  // 11000001-00111111-11010011-11111110
+// CHECK-INST: zip     { z30.b, z31.b }, z31.b, z31.b
+// CHECK-ENCODING: [0xfe,0xd3,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13fd3fe <unknown>
+
+
+zip     {z0.q - z3.q}, {z0.q - z3.q}  // 11000001-00110111-11100000-00000000
+// CHECK-INST: zip     { z0.q - z3.q }, { z0.q - z3.q }
+// CHECK-ENCODING: [0x00,0xe0,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e000 <unknown>
+
+zip     {z20.q - z23.q}, {z8.q - z11.q}  // 11000001-00110111-11100001-00010100
+// CHECK-INST: zip     { z20.q - z23.q }, { z8.q - z11.q }
+// CHECK-ENCODING: [0x14,0xe1,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e114 <unknown>
+
+zip     {z20.q - z23.q}, {z12.q - z15.q}  // 11000001-00110111-11100001-10010100
+// CHECK-INST: zip     { z20.q - z23.q }, { z12.q - z15.q }
+// CHECK-ENCODING: [0x94,0xe1,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e194 <unknown>
+
+zip     {z28.q - z31.q}, {z28.q - z31.q}  // 11000001-00110111-11100011-10011100
+// CHECK-INST: zip     { z28.q - z31.q }, { z28.q - z31.q }
+// CHECK-ENCODING: [0x9c,0xe3,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e39c <unknown>
+
+
+zip     {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01110110-11100000-00000000
+// CHECK-INST: zip     { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x00,0xe0,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e000 <unknown>
+
+zip     {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01110110-11100001-00010100
+// CHECK-INST: zip     { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x14,0xe1,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e114 <unknown>
+
+zip     {z20.h - z23.h}, {z12.h - z15.h}  // 11000001-01110110-11100001-10010100
+// CHECK-INST: zip     { z20.h - z23.h }, { z12.h - z15.h }
+// CHECK-ENCODING: [0x94,0xe1,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e194 <unknown>
+
+zip     {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01110110-11100011-10011100
+// CHECK-INST: zip     { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x9c,0xe3,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e39c <unknown>
+
+
+zip     {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10110110-11100000-00000000
+// CHECK-INST: zip     { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0xe0,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e000 <unknown>
+
+zip     {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10110110-11100001-00010100
+// CHECK-INST: zip     { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x14,0xe1,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e114 <unknown>
+
+zip     {z20.s - z23.s}, {z12.s - z15.s}  // 11000001-10110110-11100001-10010100
+// CHECK-INST: zip     { z20.s - z23.s }, { z12.s - z15.s }
+// CHECK-ENCODING: [0x94,0xe1,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e194 <unknown>
+
+zip     {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10110110-11100011-10011100
+// CHECK-INST: zip     { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x9c,0xe3,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e39c <unknown>
+
+
+zip     {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11110110-11100000-00000000
+// CHECK-INST: zip     { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x00,0xe0,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e000 <unknown>
+
+zip     {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11110110-11100001-00010100
+// CHECK-INST: zip     { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x14,0xe1,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e114 <unknown>
+
+zip     {z20.d - z23.d}, {z12.d - z15.d}  // 11000001-11110110-11100001-10010100
+// CHECK-INST: zip     { z20.d - z23.d }, { z12.d - z15.d }
+// CHECK-ENCODING: [0x94,0xe1,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e194 <unknown>
+
+zip     {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11110110-11100011-10011100
+// CHECK-INST: zip     { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x9c,0xe3,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e39c <unknown>
+
+
+zip     {z0.b - z3.b}, {z0.b - z3.b}  // 11000001-00110110-11100000-00000000
+// CHECK-INST: zip     { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x00,0xe0,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e000 <unknown>
+
+zip     {z20.b - z23.b}, {z8.b - z11.b}  // 11000001-00110110-11100001-00010100
+// CHECK-INST: zip     { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x14,0xe1,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e114 <unknown>
+
+zip     {z20.b - z23.b}, {z12.b - z15.b}  // 11000001-00110110-11100001-10010100
+// CHECK-INST: zip     { z20.b - z23.b }, { z12.b - z15.b }
+// CHECK-ENCODING: [0x94,0xe1,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e194 <unknown>
+
+zip     {z28.b - z31.b}, {z28.b - z31.b}  // 11000001-00110110-11100011-10011100
+// CHECK-INST: zip     { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x9c,0xe3,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e39c <unknown>
+