diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -550,6 +550,7 @@ -------------------- - Support ``-mindirect-branch-cs-prefix`` for call and jmp to indirect thunk. - Fix 32-bit ``__fastcall`` and ``__vectorcall`` ABI mismatch with MSVC. +- Add support for ``RAO-INT`` instructions. DWARF Support in Clang ---------------------- diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def --- a/clang/include/clang/Basic/BuiltinsX86.def +++ b/clang/include/clang/Basic/BuiltinsX86.def @@ -2061,6 +2061,12 @@ TARGET_BUILTIN(__builtin_ia32_xsusldtrk, "v", "n", "tsxldtrk") TARGET_BUILTIN(__builtin_ia32_xresldtrk, "v", "n", "tsxldtrk") +// RAO-INT +TARGET_BUILTIN(__builtin_ia32_aadd32, "vv*Si", "n", "raoint") +TARGET_BUILTIN(__builtin_ia32_aand32, "vv*Si", "n", "raoint") +TARGET_BUILTIN(__builtin_ia32_aor32, "vv*Si", "n", "raoint") +TARGET_BUILTIN(__builtin_ia32_axor32, "vv*Si", "n", "raoint") + // MSVC TARGET_HEADER_BUILTIN(_BitScanForward, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") TARGET_HEADER_BUILTIN(_BitScanReverse, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "") diff --git a/clang/include/clang/Basic/BuiltinsX86_64.def b/clang/include/clang/Basic/BuiltinsX86_64.def --- a/clang/include/clang/Basic/BuiltinsX86_64.def +++ b/clang/include/clang/Basic/BuiltinsX86_64.def @@ -133,6 +133,12 @@ TARGET_BUILTIN(__builtin_ia32_tdpbf16ps, "vIUcIUcIUc", "n", "amx-bf16") TARGET_BUILTIN(__builtin_ia32_ptwrite64, "vUOi", "n", "ptwrite") +// RAO-INT +TARGET_BUILTIN(__builtin_ia32_aadd64, "vv*SOi", "n", "raoint") +TARGET_BUILTIN(__builtin_ia32_aand64, "vv*SOi", "n", "raoint") +TARGET_BUILTIN(__builtin_ia32_aor64, "vv*SOi", "n", "raoint") +TARGET_BUILTIN(__builtin_ia32_axor64, "vv*SOi", "n", "raoint") + #undef BUILTIN #undef TARGET_BUILTIN #undef TARGET_HEADER_BUILTIN diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -4654,6 +4654,8 @@ def mno_prfchw : Flag<["-"], "mno-prfchw">, Group; def mptwrite : Flag<["-"], "mptwrite">, Group; def mno_ptwrite : Flag<["-"], "mno-ptwrite">, Group; +def mraoint : Flag<["-"], "mraoint">, Group; +def mno_raoint : Flag<["-"], "mno-raoint">, Group; def mrdpid : Flag<["-"], "mrdpid">, Group; def mno_rdpid : Flag<["-"], "mno-rdpid">, Group; def mrdpru : Flag<["-"], "mrdpru">, Group; diff --git a/clang/lib/Basic/Targets/X86.h b/clang/lib/Basic/Targets/X86.h --- a/clang/lib/Basic/Targets/X86.h +++ b/clang/lib/Basic/Targets/X86.h @@ -135,6 +135,7 @@ bool HasPTWRITE = false; bool HasINVPCID = false; bool HasENQCMD = false; + bool HasRAOINT = false; bool HasKL = false; // For key locker bool HasWIDEKL = false; // For wide key locker bool HasHRESET = false; diff --git a/clang/lib/Basic/Targets/X86.cpp b/clang/lib/Basic/Targets/X86.cpp --- a/clang/lib/Basic/Targets/X86.cpp +++ b/clang/lib/Basic/Targets/X86.cpp @@ -330,6 +330,8 @@ HasAMXINT8 = true; } else if (Feature == "+amx-tile") { HasAMXTILE = true; + } else if (Feature == "+raoint") { + HasRAOINT = true; } else if (Feature == "+avxvnni") { HasAVXVNNI = true; } else if (Feature == "+serialize") { @@ -774,6 +776,8 @@ Builder.defineMacro("__AMXINT8__"); if (HasAMXBF16) Builder.defineMacro("__AMXBF16__"); + if (HasRAOINT) + Builder.defineMacro("__RAOINT__"); if (HasAVXVNNI) Builder.defineMacro("__AVXVNNI__"); if (HasSERIALIZE) @@ -932,6 +936,7 @@ .Case("prefetchwt1", true) .Case("prfchw", true) .Case("ptwrite", true) + .Case("raoint", true) .Case("rdpid", true) .Case("rdpru", true) .Case("rdrnd", true) @@ -1028,6 +1033,7 @@ .Case("prefetchwt1", HasPREFETCHWT1) .Case("prfchw", HasPRFCHW) .Case("ptwrite", HasPTWRITE) + .Case("raoint", HasRAOINT) .Case("rdpid", HasRDPID) .Case("rdpru", HasRDPRU) .Case("rdrnd", HasRDRND) diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt --- a/clang/lib/Headers/CMakeLists.txt +++ b/clang/lib/Headers/CMakeLists.txt @@ -176,6 +176,7 @@ popcntintrin.h prfchwintrin.h ptwriteintrin.h + raointintrin.h rdpruintrin.h rdseedintrin.h rtmintrin.h diff --git a/clang/lib/Headers/cpuid.h b/clang/lib/Headers/cpuid.h --- a/clang/lib/Headers/cpuid.h +++ b/clang/lib/Headers/cpuid.h @@ -200,6 +200,7 @@ #define bit_AMXINT8 0x02000000 /* Features in %eax for leaf 7 sub-leaf 1 */ +#define bit_RAOINT 0x00000008 #define bit_AVXVNNI 0x00000010 #define bit_AVX512BF16 0x00000020 #define bit_HRESET 0x00400000 diff --git a/clang/lib/Headers/raointintrin.h b/clang/lib/Headers/raointintrin.h new file mode 100644 --- /dev/null +++ b/clang/lib/Headers/raointintrin.h @@ -0,0 +1,203 @@ +/*===----------------------- raointintrin.h - RAOINT ------------------------=== + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + * + *===-----------------------------------------------------------------------=== + */ + +#ifndef __X86GPRINTRIN_H +#error "Never use directly; include instead." +#endif // __X86GPRINTRIN_H + +#ifndef __RAOINTINTRIN_H +#define __RAOINTINTRIN_H + +#define __DEFAULT_FN_ATTRS \ + __attribute__((__always_inline__, __nodebug__, __target__("raoint"))) + +/// Atomically add a 32-bit value at memory operand \a __A and a 32-bit \a __B, +/// and store the result to the same memory location. +/// +/// This intrinsic should be used for contention or weak ordering. It may +/// result in bad performance for hot data used by single thread only. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c AADD instruction. +/// +/// \param __A +/// A pointer to a 32-bit memory location. +/// \param __B +/// A 32-bit integer value. +/// +/// \code{.operation} +/// MEM[__A+31:__A] := MEM[__A+31:__A] + __B[31:0] +/// \endcode +static __inline__ void __DEFAULT_FN_ATTRS _aadd_si32(int *__A, int __B) { + __builtin_ia32_aadd32((int *)__A, __B); +} + +/// Atomically and a 32-bit value at memory operand \a __A and a 32-bit \a __B, +/// and store the result to the same memory location. +/// +/// This intrinsic should be used for contention or weak ordering. It may +/// result in bad performance for hot data used by single thread only. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c AAND instruction. +/// +/// \param __A +/// A pointer to a 32-bit memory location. +/// \param __B +/// A 32-bit integer value. +/// +/// \code{.operation} +/// MEM[__A+31:__A] := MEM[__A+31:__A] AND __B[31:0] +/// \endcode +static __inline__ void __DEFAULT_FN_ATTRS _aand_si32(int *__A, int __B) { + __builtin_ia32_aand32((int *)__A, __B); +} + +/// Atomically or a 32-bit value at memory operand \a __A and a 32-bit \a __B, +/// and store the result to the same memory location. +/// +/// This intrinsic should be used for contention or weak ordering. It may +/// result in bad performance for hot data used by single thread only. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c AOR instruction. +/// +/// \param __A +/// A pointer to a 32-bit memory location. +/// \param __B +/// A 32-bit integer value. +/// +/// \code{.operation} +/// MEM[__A+31:__A] := MEM[__A+31:__A] OR __B[31:0] +/// \endcode +static __inline__ void __DEFAULT_FN_ATTRS _aor_si32(int *__A, int __B) { + __builtin_ia32_aor32((int *)__A, __B); +} + +/// Atomically xor a 32-bit value at memory operand \a __A and a 32-bit \a __B, +/// and store the result to the same memory location. +/// +/// This intrinsic should be used for contention or weak ordering. It may +/// result in bad performance for hot data used by single thread only. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c AXOR instruction. +/// +/// \param __A +/// A pointer to a 32-bit memory location. +/// \param __B +/// A 32-bit integer value. +/// +/// \code{.operation} +/// MEM[__A+31:__A] := MEM[__A+31:__A] XOR __B[31:0] +/// \endcode +static __inline__ void __DEFAULT_FN_ATTRS _axor_si32(int *__A, int __B) { + __builtin_ia32_axor32((int *)__A, __B); +} + +#ifdef __x86_64__ +/// Atomically add a 64-bit value at memory operand \a __A and a 64-bit \a __B, +/// and store the result to the same memory location. +/// +/// This intrinsic should be used for contention or weak ordering. It may +/// result in bad performance for hot data used by single thread only. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c AADD instruction. +/// +/// \param __A +/// A pointer to a 64-bit memory location. +/// \param __B +/// A 64-bit integer value. +/// +/// \code{.operation} +/// MEM[__A+63:__A] := MEM[__A+63:__A] + __B[63:0] +/// \endcode +static __inline__ void __DEFAULT_FN_ATTRS _aadd_si64(long long *__A, + long long __B) { + __builtin_ia32_aadd64((long long *)__A, __B); +} + +/// Atomically and a 64-bit value at memory operand \a __A and a 64-bit \a __B, +/// and store the result to the same memory location. +/// +/// This intrinsic should be used for contention or weak ordering. It may +/// result in bad performance for hot data used by single thread only. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c AAND instruction. +/// +/// \param __A +/// A pointer to a 64-bit memory location. +/// \param __B +/// A 64-bit integer value. +/// +/// \code{.operation} +/// MEM[__A+63:__A] := MEM[__A+63:__A] AND __B[63:0] +/// \endcode +static __inline__ void __DEFAULT_FN_ATTRS _aand_si64(long long *__A, + long long __B) { + __builtin_ia32_aand64((long long *)__A, __B); +} + +/// Atomically or a 64-bit value at memory operand \a __A and a 64-bit \a __B, +/// and store the result to the same memory location. +/// +/// This intrinsic should be used for contention or weak ordering. It may +/// result in bad performance for hot data used by single thread only. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c AOR instruction. +/// +/// \param __A +/// A pointer to a 64-bit memory location. +/// \param __B +/// A 64-bit integer value. +/// +/// \code{.operation} +/// MEM[__A+63:__A] := MEM[__A+63:__A] OR __B[63:0] +/// \endcode +static __inline__ void __DEFAULT_FN_ATTRS _aor_si64(long long *__A, + long long __B) { + __builtin_ia32_aor64((long long *)__A, __B); +} + +/// Atomically xor a 64-bit value at memory operand \a __A and a 64-bit \a __B, +/// and store the result to the same memory location. +/// +/// This intrinsic should be used for contention or weak ordering. It may +/// result in bad performance for hot data used by single thread only. +/// +/// \headerfile +/// +/// This intrinsic corresponds to the \c AXOR instruction. +/// +/// \param __A +/// A pointer to a 64-bit memory location. +/// \param __B +/// A 64-bit integer value. +/// +/// \code{.operation} +/// MEM[__A+63:__A] := MEM[__A+63:__A] AOR __B[63:0] +/// \endcode +static __inline__ void __DEFAULT_FN_ATTRS _axor_si64(long long *__A, + long long __B) { + __builtin_ia32_axor64((long long *)__A, __B); +} +#endif // __x86_64__ + +#undef __DEFAULT_FN_ATTRS +#endif // __RAOINTINTRIN_H diff --git a/clang/lib/Headers/x86gprintrin.h b/clang/lib/Headers/x86gprintrin.h --- a/clang/lib/Headers/x86gprintrin.h +++ b/clang/lib/Headers/x86gprintrin.h @@ -25,6 +25,11 @@ #include #endif +#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \ + defined(__RAOINT__) +#include +#endif + #if defined(__i386__) #define __SAVE_GPRBX "mov {%%ebx, %%eax |eax, ebx};" #define __RESTORE_GPRBX "mov {%%eax, %%ebx |ebx, eax};" diff --git a/clang/test/CodeGen/X86/raoint-builtins.c b/clang/test/CodeGen/X86/raoint-builtins.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/X86/raoint-builtins.c @@ -0,0 +1,53 @@ +// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +raoint \ +// RUN: -emit-llvm -o - -Wall -Werror -pedantic -Wno-gnu-statement-expression | FileCheck %s + +#include +#include + +void test_aadd_si32(int *__A, int __B) { + // CHECK-LABEL: @test_aadd_si32( + // CHECK: call void @llvm.x86.aadd32(ptr %{{.*}}, i32 %{{.*}}) + _aadd_si32(__A, __B); +} + +void test_aand_si32(int *__A, int __B) { + // CHECK-LABEL: @test_aand_si32( + // CHECK: call void @llvm.x86.aand32(ptr %{{.*}}, i32 %{{.*}}) + _aand_si32(__A, __B); +} + +void test_aor_si32(int *__A, int __B) { + // CHECK-LABEL: @test_aor_si32( + // CHECK: call void @llvm.x86.aor32(ptr %{{.*}}, i32 %{{.*}}) + _aor_si32(__A, __B); +} + +void test_axor_si32(int *__A, int __B) { + // CHECK-LABEL: @test_axor_si32( + // CHECK: call void @llvm.x86.axor32(ptr %{{.*}}, i32 %{{.*}}) + _axor_si32(__A, __B); +} + +void test_aadd_si64(long long *__A, long long __B) { + // CHECK-LABEL: @test_aadd_si64( + // CHECK: call void @llvm.x86.aadd64(ptr %{{.*}}, i64 %{{.*}}) + _aadd_si64(__A, __B); +} + +void test_aand_si64(long long *__A, long long __B) { + // CHECK-LABEL: @test_aand_si64( + // CHECK: call void @llvm.x86.aand64(ptr %{{.*}}, i64 %{{.*}}) + _aand_si64(__A, __B); +} + +void test_aor_si64(long long *__A, long long __B) { + // CHECK-LABEL: @test_aor_si64( + // CHECK: call void @llvm.x86.aor64(ptr %{{.*}}, i64 %{{.*}}) + _aor_si64(__A, __B); +} + +void test_axor_si64(long long *__A, long long __B) { + // CHECK-LABEL: @test_axor_si64( + // CHECK: call void @llvm.x86.axor64(ptr %{{.*}}, i64 %{{.*}}) + _axor_si64(__A, __B); +} diff --git a/clang/test/Driver/x86-target-features.c b/clang/test/Driver/x86-target-features.c --- a/clang/test/Driver/x86-target-features.c +++ b/clang/test/Driver/x86-target-features.c @@ -305,6 +305,11 @@ // AVX512FP16: "-target-feature" "+avx512fp16" // NO-AVX512FP16: "-target-feature" "-avx512fp16" +// RUN: %clang --target=i386 -march=i386 -mraoint %s -### 2>&1 | FileCheck -check-prefix=RAOINT %s +// RUN: %clang --target=i386 -march=i386 -mno-raoint %s -### 2>&1 | FileCheck -check-prefix=NO-RAOINT %s +// RAOINT: "-target-feature" "+raoint" +// NO-RAOINT: "-target-feature" "-raoint" + // RUN: %clang --target=i386 -march=i386 -mcrc32 %s -### 2>&1 | FileCheck -check-prefix=CRC32 %s // RUN: %clang --target=i386 -march=i386 -mno-crc32 %s -### 2>&1 | FileCheck -check-prefix=NO-CRC32 %s // CRC32: "-target-feature" "+crc32" diff --git a/clang/test/Preprocessor/x86_target_features.c b/clang/test/Preprocessor/x86_target_features.c --- a/clang/test/Preprocessor/x86_target_features.c +++ b/clang/test/Preprocessor/x86_target_features.c @@ -581,6 +581,14 @@ // AVX512FP16NOAVX512DQ-NOT: #define __AVX512DQ__ 1 // AVX512FP16NOAVX512DQ-NOT: #define __AVX512FP16__ 1 +// RUN: %clang -target i386-unknown-linux-gnu -march=atom -mraoint -x c -E -dM -o - %s | FileCheck -check-prefix=RAOINT %s + +// RAOINT: #define __RAOINT__ 1 + +// RUN: %clang -target i386-unknown-linux-gnu -march=atom -mno-raoint -x c -E -dM -o - %s | FileCheck -check-prefix=NO-RAOINT %s + +// NO-RAOINT-NOT: #define __RAOINT__ 1 + // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mcrc32 -x c -E -dM -o - %s | FileCheck -check-prefix=CRC32 %s // CRC32: #define __CRC32__ 1 diff --git a/llvm/include/llvm/IR/IntrinsicsX86.td b/llvm/include/llvm/IR/IntrinsicsX86.td --- a/llvm/include/llvm/IR/IntrinsicsX86.td +++ b/llvm/include/llvm/IR/IntrinsicsX86.td @@ -5115,6 +5115,27 @@ Intrinsic<[llvm_anyvector_ty], [llvm_x86amx_ty], [IntrNoMem]>; } +//===----------------------------------------------------------------------===// +// RAO-INT intrinsics +let TargetPrefix = "x86" in { + def int_x86_aadd32 : ClangBuiltin<"__builtin_ia32_aadd32">, + Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], []>; + def int_x86_aadd64 : ClangBuiltin<"__builtin_ia32_aadd64">, + Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], []>; + def int_x86_aand32 : ClangBuiltin<"__builtin_ia32_aand32">, + Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], []>; + def int_x86_aand64 : ClangBuiltin<"__builtin_ia32_aand64">, + Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], []>; + def int_x86_aor32 : ClangBuiltin<"__builtin_ia32_aor32">, + Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], []>; + def int_x86_aor64 : ClangBuiltin<"__builtin_ia32_aor64">, + Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], []>; + def int_x86_axor32 : ClangBuiltin<"__builtin_ia32_axor32">, + Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], []>; + def int_x86_axor64 : ClangBuiltin<"__builtin_ia32_axor64">, + Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], []>; +} + //===----------------------------------------------------------------------===// // UINTR - User Level Interrupt diff --git a/llvm/include/llvm/Support/X86TargetParser.def b/llvm/include/llvm/Support/X86TargetParser.def --- a/llvm/include/llvm/Support/X86TargetParser.def +++ b/llvm/include/llvm/Support/X86TargetParser.def @@ -200,6 +200,7 @@ X86_FEATURE (XSAVEOPT, "xsaveopt") X86_FEATURE (XSAVES, "xsaves") X86_FEATURE (HRESET, "hreset") +X86_FEATURE (RAOINT, "raoint") X86_FEATURE (AVX512FP16, "avx512fp16") X86_FEATURE (AVXVNNI, "avxvnni") // These features aren't really CPU features, but the frontend can set them. diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp --- a/llvm/lib/Support/Host.cpp +++ b/llvm/lib/Support/Host.cpp @@ -1805,6 +1805,7 @@ Features["amx-int8"] = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave; bool HasLeaf7Subleaf1 = MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX); + Features["raoint"] = HasLeaf7Subleaf1 && ((EAX >> 3) & 1); Features["avxvnni"] = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave; Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save; Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1); diff --git a/llvm/lib/Support/X86TargetParser.cpp b/llvm/lib/Support/X86TargetParser.cpp --- a/llvm/lib/Support/X86TargetParser.cpp +++ b/llvm/lib/Support/X86TargetParser.cpp @@ -581,6 +581,7 @@ constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE; constexpr FeatureBitset ImpliedFeaturesHRESET = {}; +static constexpr FeatureBitset ImpliedFeaturesRAOINT = {}; static constexpr FeatureBitset ImpliedFeaturesAVX512FP16 = FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL; // Key Locker Features diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -254,6 +254,9 @@ def FeatureAMXBF16 : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true", "Support AMX-BF16 instructions", [FeatureAMXTILE]>; +def FeatureRAOINT : SubtargetFeature<"raoint", "HasRAOINT", "true", + "Support RAO-INT instructions", + []>; def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true", "Invalidate Process-Context Identifier">; def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -793,6 +793,13 @@ LBTC, LBTR, + /// RAO arithmetic instructions. + /// OUTCHAIN = AADD(INCHAIN, PTR, RHS) + AADD, + AOR, + AXOR, + AAND, + // Load, scalar_to_vector, and zero extend. VZEXT_LOAD, diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -5621,6 +5621,23 @@ MachineMemOperand::MOVolatile; return true; } + case Intrinsic::x86_aadd32: + case Intrinsic::x86_aadd64: + case Intrinsic::x86_aand32: + case Intrinsic::x86_aand64: + case Intrinsic::x86_aor32: + case Intrinsic::x86_aor64: + case Intrinsic::x86_axor32: + case Intrinsic::x86_axor64: { + Info.opc = ISD::INTRINSIC_W_CHAIN; + Info.ptrVal = I.getArgOperand(0); + unsigned Size = I.getArgOperand(1)->getType()->getScalarSizeInBits(); + Info.memVT = EVT::getIntegerVT(I.getType()->getContext(), Size); + Info.align = Align(Size); + Info.flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore | + MachineMemOperand::MOVolatile; + return true; + } } return false; } @@ -28085,6 +28102,44 @@ DAG.getShiftAmountConstant(Imm, VT, DL)); return DAG.getNode(ISD::MERGE_VALUES, DL, Op->getVTList(), Res, Chain); } + case Intrinsic::x86_aadd32: + case Intrinsic::x86_aadd64: + case Intrinsic::x86_aand32: + case Intrinsic::x86_aand64: + case Intrinsic::x86_aor32: + case Intrinsic::x86_aor64: + case Intrinsic::x86_axor32: + case Intrinsic::x86_axor64: { + SDLoc DL(Op); + SDValue Chain = Op.getOperand(0); + SDValue Op1 = Op.getOperand(2); + SDValue Op2 = Op.getOperand(3); + MVT VT = Op2.getSimpleValueType(); + unsigned Opc = 0; + switch (IntNo) { + default: + llvm_unreachable("Unknown Intrinsic"); + case Intrinsic::x86_aadd32: + case Intrinsic::x86_aadd64: + Opc = X86ISD::AADD; + break; + case Intrinsic::x86_aand32: + case Intrinsic::x86_aand64: + Opc = X86ISD::AAND; + break; + case Intrinsic::x86_aor32: + case Intrinsic::x86_aor64: + Opc = X86ISD::AOR; + break; + case Intrinsic::x86_axor32: + case Intrinsic::x86_axor64: + Opc = X86ISD::AXOR; + break; + } + MachineMemOperand *MMO = cast(Op)->getMemOperand(); + return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), + {Chain, Op1, Op2}, VT, MMO); + } } return SDValue(); } @@ -33709,6 +33764,10 @@ NODE_NAME_CASE(LBTS) NODE_NAME_CASE(LBTC) NODE_NAME_CASE(LBTR) + NODE_NAME_CASE(AADD) + NODE_NAME_CASE(AOR) + NODE_NAME_CASE(AXOR) + NODE_NAME_CASE(AAND) NODE_NAME_CASE(VZEXT_MOVL) NODE_NAME_CASE(VZEXT_LOAD) NODE_NAME_CASE(VEXTRACT_STORE) diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -980,6 +980,7 @@ def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">; def HasENQCMD : Predicate<"Subtarget->hasENQCMD()">; def HasKL : Predicate<"Subtarget->hasKL()">; +def HasRAOINT : Predicate<"Subtarget->hasRAOINT()">; def HasWIDEKL : Predicate<"Subtarget->hasWIDEKL()">; def HasHRESET : Predicate<"Subtarget->hasHRESET()">; def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">; @@ -3167,6 +3168,9 @@ // AMX instructions include "X86InstrAMX.td" +// RAO-INT instructions +include "X86InstrRAOINT.td" + // System instructions. include "X86InstrSystem.td" diff --git a/llvm/lib/Target/X86/X86InstrRAOINT.td b/llvm/lib/Target/X86/X86InstrRAOINT.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/X86/X86InstrRAOINT.td @@ -0,0 +1,45 @@ +//===---- X86InstrRAOINT.td -------------------------------*- tablegen -*--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the instructions that make up the Intel AMX instruction +// set. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// RAO-INT instructions + +def SDTRAOBinaryArith : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>; + +def X86rao_add : SDNode<"X86ISD::AADD", SDTRAOBinaryArith, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def X86rao_or : SDNode<"X86ISD::AOR", SDTRAOBinaryArith, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def X86rao_xor : SDNode<"X86ISD::AXOR", SDTRAOBinaryArith, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def X86rao_and : SDNode<"X86ISD::AAND", SDTRAOBinaryArith, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +multiclass RAOINT_BASE { + let Predicates = [HasRAOINT] in + def 32mr : I<0xfc, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), + !strconcat("a", OpcodeStr, "{l}\t{$src, $dst|$dst, $src}"), + [(!cast("X86rao_" # OpcodeStr) addr:$dst, GR32:$src)]>, + Sched<[WriteALURMW]>; + + let Predicates = [HasRAOINT, In64BitMode] in + def 64mr : I<0xfc, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), + !strconcat("a", OpcodeStr, "{q}\t{$src, $dst|$dst, $src}"), + [(!cast("X86rao_" # OpcodeStr) addr:$dst, GR64:$src)]>, + Sched<[WriteALURMW]>, REX_W; +} + +defm AADD : RAOINT_BASE<"add">, T8PS; +defm AAND : RAOINT_BASE<"and">, T8PD; +defm AOR : RAOINT_BASE<"or" >, T8XD; +defm AXOR : RAOINT_BASE<"xor">, T8XS; diff --git a/llvm/test/CodeGen/X86/raoint-intrinsics-32.ll b/llvm/test/CodeGen/X86/raoint-intrinsics-32.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/X86/raoint-intrinsics-32.ll @@ -0,0 +1,71 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+raoint | FileCheck %s --check-prefixes=X64 +; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+raoint | FileCheck %s --check-prefixes=X86 + +define void @test_int_x86_aadd32(i8* %A, i32 %B) { +; X64-LABEL: test_int_x86_aadd32: +; X64: # %bb.0: +; X64-NEXT: aaddl %esi, (%rdi) # encoding: [0x0f,0x38,0xfc,0x37] +; X64-NEXT: retq # encoding: [0xc3] +; +; X86-LABEL: test_int_x86_aadd32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08] +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04] +; X86-NEXT: aaddl %eax, (%ecx) # encoding: [0x0f,0x38,0xfc,0x01] +; X86-NEXT: retl # encoding: [0xc3] + call void @llvm.x86.aadd32(i8* %A, i32 %B) + ret void +} +declare void @llvm.x86.aadd32(i8* %A, i32 %B) + +define void @test_int_x86_aand32(i8* %A, i32 %B) { +; X64-LABEL: test_int_x86_aand32: +; X64: # %bb.0: +; X64-NEXT: aandl %esi, (%rdi) # encoding: [0x66,0x0f,0x38,0xfc,0x37] +; X64-NEXT: retq # encoding: [0xc3] +; +; X86-LABEL: test_int_x86_aand32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08] +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04] +; X86-NEXT: aandl %eax, (%ecx) # encoding: [0x66,0x0f,0x38,0xfc,0x01] +; X86-NEXT: retl # encoding: [0xc3] + call void @llvm.x86.aand32(i8* %A, i32 %B) + ret void +} +declare void @llvm.x86.aand32(i8* %A, i32 %B) + +define void @test_int_x86_aor32(i8* %A, i32 %B) { +; X64-LABEL: test_int_x86_aor32: +; X64: # %bb.0: +; X64-NEXT: aorl %esi, (%rdi) # encoding: [0xf2,0x0f,0x38,0xfc,0x37] +; X64-NEXT: retq # encoding: [0xc3] +; +; X86-LABEL: test_int_x86_aor32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08] +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04] +; X86-NEXT: aorl %eax, (%ecx) # encoding: [0xf2,0x0f,0x38,0xfc,0x01] +; X86-NEXT: retl # encoding: [0xc3] + call void @llvm.x86.aor32(i8* %A, i32 %B) + ret void +} +declare void @llvm.x86.aor32(i8* %A, i32 %B) + +define void @test_int_x86_axor32(i8* %A, i32 %B) { +; X64-LABEL: test_int_x86_axor32: +; X64: # %bb.0: +; X64-NEXT: axorl %esi, (%rdi) # encoding: [0xf3,0x0f,0x38,0xfc,0x37] +; X64-NEXT: retq # encoding: [0xc3] +; +; X86-LABEL: test_int_x86_axor32: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x08] +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx # encoding: [0x8b,0x4c,0x24,0x04] +; X86-NEXT: axorl %eax, (%ecx) # encoding: [0xf3,0x0f,0x38,0xfc,0x01] +; X86-NEXT: retl # encoding: [0xc3] + call void @llvm.x86.axor32(i8* %A, i32 %B) + ret void +} +declare void @llvm.x86.axor32(i8* %A, i32 %B) diff --git a/llvm/test/CodeGen/X86/raoint-intrinsics-64.ll b/llvm/test/CodeGen/X86/raoint-intrinsics-64.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/X86/raoint-intrinsics-64.ll @@ -0,0 +1,42 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+raoint | FileCheck %s --check-prefixes=X64 + +define void @test_int_x86_aadd64(i8* %A, i64 %B) { +; X64-LABEL: test_int_x86_aadd64: +; X64: # %bb.0: +; X64-NEXT: aaddq %rsi, (%rdi) # encoding: [0x48,0x0f,0x38,0xfc,0x37] +; X64-NEXT: retq # encoding: [0xc3] + call void @llvm.x86.aadd64(i8* %A, i64 %B) + ret void +} +declare void @llvm.x86.aadd64(i8* %A, i64 %B) + +define void @test_int_x86_aand64(i8* %A, i64 %B) { +; X64-LABEL: test_int_x86_aand64: +; X64: # %bb.0: +; X64-NEXT: aandq %rsi, (%rdi) # encoding: [0x66,0x48,0x0f,0x38,0xfc,0x37] +; X64-NEXT: retq # encoding: [0xc3] + call void @llvm.x86.aand64(i8* %A, i64 %B) + ret void +} +declare void @llvm.x86.aand64(i8* %A, i64 %B) + +define void @test_int_x86_aor64(i8* %A, i64 %B) { +; X64-LABEL: test_int_x86_aor64: +; X64: # %bb.0: +; X64-NEXT: aorq %rsi, (%rdi) # encoding: [0xf2,0x48,0x0f,0x38,0xfc,0x37] +; X64-NEXT: retq # encoding: [0xc3] + call void @llvm.x86.aor64(i8* %A, i64 %B) + ret void +} +declare void @llvm.x86.aor64(i8* %A, i64 %B) + +define void @test_int_x86_axor64(i8* %A, i64 %B) { +; X64-LABEL: test_int_x86_axor64: +; X64: # %bb.0: +; X64-NEXT: axorq %rsi, (%rdi) # encoding: [0xf3,0x48,0x0f,0x38,0xfc,0x37] +; X64-NEXT: retq # encoding: [0xc3] + call void @llvm.x86.axor64(i8* %A, i64 %B) + ret void +} +declare void @llvm.x86.axor64(i8* %A, i64 %B) diff --git a/llvm/test/MC/Disassembler/X86/rao-int.txt b/llvm/test/MC/Disassembler/X86/rao-int.txt new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/rao-int.txt @@ -0,0 +1,98 @@ +# RUN: llvm-mc --disassemble %s -triple=i686 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=i686 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: aaddl %ebx, 268435456(%esp,%esi,8) +# INTEL: aadd dword ptr [esp + 8*esi + 268435456], ebx +0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10 + +# ATT: aaddl %ebx, 291(%edi,%eax,4) +# INTEL: aadd dword ptr [edi + 4*eax + 291], ebx +0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00 + +# ATT: aaddl %ebx, (%eax) +# INTEL: aadd dword ptr [eax], ebx +0x0f,0x38,0xfc,0x18 + +# ATT: aaddl %ebx, -512(,%ebp,2) +# INTEL: aadd dword ptr [2*ebp - 512], ebx +0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff + +# ATT: aaddl %ebx, 2032(%ecx) +# INTEL: aadd dword ptr [ecx + 2032], ebx +0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00 + +# ATT: aaddl %ebx, -2048(%edx) +# INTEL: aadd dword ptr [edx - 2048], ebx +0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff + +# ATT: aandl %ebx, 268435456(%esp,%esi,8) +# INTEL: aand dword ptr [esp + 8*esi + 268435456], ebx +0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10 + +# ATT: aandl %ebx, 291(%edi,%eax,4) +# INTEL: aand dword ptr [edi + 4*eax + 291], ebx +0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00 + +# ATT: aandl %ebx, (%eax) +# INTEL: aand dword ptr [eax], ebx +0x66,0x0f,0x38,0xfc,0x18 + +# ATT: aandl %ebx, -512(,%ebp,2) +# INTEL: aand dword ptr [2*ebp - 512], ebx +0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff + +# ATT: aandl %ebx, 2032(%ecx) +# INTEL: aand dword ptr [ecx + 2032], ebx +0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00 + +# ATT: aandl %ebx, -2048(%edx) +# INTEL: aand dword ptr [edx - 2048], ebx +0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff + +# ATT: aorl %ebx, 268435456(%esp,%esi,8) +# INTEL: aor dword ptr [esp + 8*esi + 268435456], ebx +0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10 + +# ATT: aorl %ebx, 291(%edi,%eax,4) +# INTEL: aor dword ptr [edi + 4*eax + 291], ebx +0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00 + +# ATT: aorl %ebx, (%eax) +# INTEL: aor dword ptr [eax], ebx +0xf2,0x0f,0x38,0xfc,0x18 + +# ATT: aorl %ebx, -512(,%ebp,2) +# INTEL: aor dword ptr [2*ebp - 512], ebx +0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff + +# ATT: aorl %ebx, 2032(%ecx) +# INTEL: aor dword ptr [ecx + 2032], ebx +0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00 + +# ATT: aorl %ebx, -2048(%edx) +# INTEL: aor dword ptr [edx - 2048], ebx +0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff + +# ATT: axorl %ebx, 268435456(%esp,%esi,8) +# INTEL: axor dword ptr [esp + 8*esi + 268435456], ebx +0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10 + +# ATT: axorl %ebx, 291(%edi,%eax,4) +# INTEL: axor dword ptr [edi + 4*eax + 291], ebx +0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00 + +# ATT: axorl %ebx, (%eax) +# INTEL: axor dword ptr [eax], ebx +0xf3,0x0f,0x38,0xfc,0x18 + +# ATT: axorl %ebx, -512(,%ebp,2) +# INTEL: axor dword ptr [2*ebp - 512], ebx +0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff + +# ATT: axorl %ebx, 2032(%ecx) +# INTEL: axor dword ptr [ecx + 2032], ebx +0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00 + +# ATT: axorl %ebx, -2048(%edx) +# INTEL: axor dword ptr [edx - 2048], ebx +0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff diff --git a/llvm/test/MC/Disassembler/X86/x86-64-rao-int.txt b/llvm/test/MC/Disassembler/X86/x86-64-rao-int.txt new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/x86-64-rao-int.txt @@ -0,0 +1,194 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT +# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL + +# ATT: aaddq %r9, 268435456(%rbp,%r14,8) +# INTEL: aadd qword ptr [rbp + 8*r14 + 268435456], r9 +0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10 + +# ATT: aaddq %r9, 291(%r8,%rax,4) +# INTEL: aadd qword ptr [r8 + 4*rax + 291], r9 +0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00 + +# ATT: aaddq %r9, (%rip) +# INTEL: aadd qword ptr [rip], r9 +0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00 + +# ATT: aaddq %r9, -512(,%rbp,2) +# INTEL: aadd qword ptr [2*rbp - 512], r9 +0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff + +# ATT: aaddq %r9, 2032(%rcx) +# INTEL: aadd qword ptr [rcx + 2032], r9 +0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00 + +# ATT: aaddq %r9, -2048(%rdx) +# INTEL: aadd qword ptr [rdx - 2048], r9 +0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff + +# ATT: aaddl %ebx, 268435456(%esp,%esi,8) +# INTEL: aadd dword ptr [esp + 8*esi + 268435456], ebx +0x67,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10 + +# ATT: aaddl %ebx, 291(%edi,%eax,4) +# INTEL: aadd dword ptr [edi + 4*eax + 291], ebx +0x67,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00 + +# ATT: aaddl %ebx, (%eax) +# INTEL: aadd dword ptr [eax], ebx +0x67,0x0f,0x38,0xfc,0x18 + +# ATT: aaddl %ebx, -512(,%ebp,2) +# INTEL: aadd dword ptr [2*ebp - 512], ebx +0x67,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff + +# ATT: aaddl %ebx, 2032(%ecx) +# INTEL: aadd dword ptr [ecx + 2032], ebx +0x67,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00 + +# ATT: aaddl %ebx, -2048(%edx) +# INTEL: aadd dword ptr [edx - 2048], ebx +0x67,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff + +# ATT: aandq %r9, 268435456(%rbp,%r14,8) +# INTEL: aand qword ptr [rbp + 8*r14 + 268435456], r9 +0x66,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10 + +# ATT: aandq %r9, 291(%r8,%rax,4) +# INTEL: aand qword ptr [r8 + 4*rax + 291], r9 +0x66,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00 + +# ATT: aandq %r9, (%rip) +# INTEL: aand qword ptr [rip], r9 +0x66,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00 + +# ATT: aandq %r9, -512(,%rbp,2) +# INTEL: aand qword ptr [2*rbp - 512], r9 +0x66,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff + +# ATT: aandq %r9, 2032(%rcx) +# INTEL: aand qword ptr [rcx + 2032], r9 +0x66,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00 + +# ATT: aandq %r9, -2048(%rdx) +# INTEL: aand qword ptr [rdx - 2048], r9 +0x66,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff + +# ATT: aandl %ebx, 268435456(%esp,%esi,8) +# INTEL: aand dword ptr [esp + 8*esi + 268435456], ebx +0x67,0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10 + +# ATT: aandl %ebx, 291(%edi,%eax,4) +# INTEL: aand dword ptr [edi + 4*eax + 291], ebx +0x67,0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00 + +# ATT: aandl %ebx, (%eax) +# INTEL: aand dword ptr [eax], ebx +0x67,0x66,0x0f,0x38,0xfc,0x18 + +# ATT: aandl %ebx, -512(,%ebp,2) +# INTEL: aand dword ptr [2*ebp - 512], ebx +0x67,0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff + +# ATT: aandl %ebx, 2032(%ecx) +# INTEL: aand dword ptr [ecx + 2032], ebx +0x67,0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00 + +# ATT: aandl %ebx, -2048(%edx) +# INTEL: aand dword ptr [edx - 2048], ebx +0x67,0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff + +# ATT: aorq %r9, 268435456(%rbp,%r14,8) +# INTEL: aor qword ptr [rbp + 8*r14 + 268435456], r9 +0xf2,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10 + +# ATT: aorq %r9, 291(%r8,%rax,4) +# INTEL: aor qword ptr [r8 + 4*rax + 291], r9 +0xf2,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00 + +# ATT: aorq %r9, (%rip) +# INTEL: aor qword ptr [rip], r9 +0xf2,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00 + +# ATT: aorq %r9, -512(,%rbp,2) +# INTEL: aor qword ptr [2*rbp - 512], r9 +0xf2,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff + +# ATT: aorq %r9, 2032(%rcx) +# INTEL: aor qword ptr [rcx + 2032], r9 +0xf2,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00 + +# ATT: aorq %r9, -2048(%rdx) +# INTEL: aor qword ptr [rdx - 2048], r9 +0xf2,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff + +# ATT: aorl %ebx, 268435456(%esp,%esi,8) +# INTEL: aor dword ptr [esp + 8*esi + 268435456], ebx +0x67,0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10 + +# ATT: aorl %ebx, 291(%edi,%eax,4) +# INTEL: aor dword ptr [edi + 4*eax + 291], ebx +0x67,0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00 + +# ATT: aorl %ebx, (%eax) +# INTEL: aor dword ptr [eax], ebx +0x67,0xf2,0x0f,0x38,0xfc,0x18 + +# ATT: aorl %ebx, -512(,%ebp,2) +# INTEL: aor dword ptr [2*ebp - 512], ebx +0x67,0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff + +# ATT: aorl %ebx, 2032(%ecx) +# INTEL: aor dword ptr [ecx + 2032], ebx +0x67,0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00 + +# ATT: aorl %ebx, -2048(%edx) +# INTEL: aor dword ptr [edx - 2048], ebx +0x67,0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff + +# ATT: axorq %r9, 268435456(%rbp,%r14,8) +# INTEL: axor qword ptr [rbp + 8*r14 + 268435456], r9 +0xf3,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10 + +# ATT: axorq %r9, 291(%r8,%rax,4) +# INTEL: axor qword ptr [r8 + 4*rax + 291], r9 +0xf3,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00 + +# ATT: axorq %r9, (%rip) +# INTEL: axor qword ptr [rip], r9 +0xf3,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00 + +# ATT: axorq %r9, -512(,%rbp,2) +# INTEL: axor qword ptr [2*rbp - 512], r9 +0xf3,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff + +# ATT: axorq %r9, 2032(%rcx) +# INTEL: axor qword ptr [rcx + 2032], r9 +0xf3,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00 + +# ATT: axorq %r9, -2048(%rdx) +# INTEL: axor qword ptr [rdx - 2048], r9 +0xf3,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff + +# ATT: axorl %ebx, 268435456(%esp,%esi,8) +# INTEL: axor dword ptr [esp + 8*esi + 268435456], ebx +0x67,0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10 + +# ATT: axorl %ebx, 291(%edi,%eax,4) +# INTEL: axor dword ptr [edi + 4*eax + 291], ebx +0x67,0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00 + +# ATT: axorl %ebx, (%eax) +# INTEL: axor dword ptr [eax], ebx +0x67,0xf3,0x0f,0x38,0xfc,0x18 + +# ATT: axorl %ebx, -512(,%ebp,2) +# INTEL: axor dword ptr [2*ebp - 512], ebx +0x67,0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff + +# ATT: axorl %ebx, 2032(%ecx) +# INTEL: axor dword ptr [ecx + 2032], ebx +0x67,0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00 + +# ATT: axorl %ebx, -2048(%edx) +# INTEL: axor dword ptr [edx - 2048], ebx +0x67,0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff diff --git a/llvm/test/MC/X86/rao-int-att.s b/llvm/test/MC/X86/rao-int-att.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/X86/rao-int-att.s @@ -0,0 +1,97 @@ +// RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s + +// CHECK: aaddl %ebx, 268435456(%esp,%esi,8) +// CHECK: encoding: [0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + aaddl %ebx, 268435456(%esp,%esi,8) + +// CHECK: aaddl %ebx, 291(%edi,%eax,4) +// CHECK: encoding: [0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + aaddl %ebx, 291(%edi,%eax,4) + +// CHECK: aaddl %ebx, (%eax) +// CHECK: encoding: [0x0f,0x38,0xfc,0x18] + aaddl %ebx, (%eax) + +// CHECK: aaddl %ebx, -512(,%ebp,2) +// CHECK: encoding: [0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + aaddl %ebx, -512(,%ebp,2) + +// CHECK: aaddl %ebx, 2032(%ecx) +// CHECK: encoding: [0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + aaddl %ebx, 2032(%ecx) + +// CHECK: aaddl %ebx, -2048(%edx) +// CHECK: encoding: [0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + aaddl %ebx, -2048(%edx) + +// CHECK: aandl %ebx, 268435456(%esp,%esi,8) +// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + aandl %ebx, 268435456(%esp,%esi,8) + +// CHECK: aandl %ebx, 291(%edi,%eax,4) +// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + aandl %ebx, 291(%edi,%eax,4) + +// CHECK: aandl %ebx, (%eax) +// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x18] + aandl %ebx, (%eax) + +// CHECK: aandl %ebx, -512(,%ebp,2) +// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + aandl %ebx, -512(,%ebp,2) + +// CHECK: aandl %ebx, 2032(%ecx) +// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + aandl %ebx, 2032(%ecx) + +// CHECK: aandl %ebx, -2048(%edx) +// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + aandl %ebx, -2048(%edx) + +// CHECK: aorl %ebx, 268435456(%esp,%esi,8) +// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + aorl %ebx, 268435456(%esp,%esi,8) + +// CHECK: aorl %ebx, 291(%edi,%eax,4) +// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + aorl %ebx, 291(%edi,%eax,4) + +// CHECK: aorl %ebx, (%eax) +// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x18] + aorl %ebx, (%eax) + +// CHECK: aorl %ebx, -512(,%ebp,2) +// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + aorl %ebx, -512(,%ebp,2) + +// CHECK: aorl %ebx, 2032(%ecx) +// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + aorl %ebx, 2032(%ecx) + +// CHECK: aorl %ebx, -2048(%edx) +// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + aorl %ebx, -2048(%edx) + +// CHECK: axorl %ebx, 268435456(%esp,%esi,8) +// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + axorl %ebx, 268435456(%esp,%esi,8) + +// CHECK: axorl %ebx, 291(%edi,%eax,4) +// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + axorl %ebx, 291(%edi,%eax,4) + +// CHECK: axorl %ebx, (%eax) +// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x18] + axorl %ebx, (%eax) + +// CHECK: axorl %ebx, -512(,%ebp,2) +// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + axorl %ebx, -512(,%ebp,2) + +// CHECK: axorl %ebx, 2032(%ecx) +// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + axorl %ebx, 2032(%ecx) + +// CHECK: axorl %ebx, -2048(%edx) +// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + axorl %ebx, -2048(%edx) diff --git a/llvm/test/MC/X86/rao-int-intel.s b/llvm/test/MC/X86/rao-int-intel.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/X86/rao-int-intel.s @@ -0,0 +1,97 @@ +// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: aadd dword ptr [esp + 8*esi + 268435456], ebx +// CHECK: encoding: [0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + aadd dword ptr [esp + 8*esi + 268435456], ebx + +// CHECK: aadd dword ptr [edi + 4*eax + 291], ebx +// CHECK: encoding: [0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + aadd dword ptr [edi + 4*eax + 291], ebx + +// CHECK: aadd dword ptr [eax], ebx +// CHECK: encoding: [0x0f,0x38,0xfc,0x18] + aadd dword ptr [eax], ebx + +// CHECK: aadd dword ptr [2*ebp - 512], ebx +// CHECK: encoding: [0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + aadd dword ptr [2*ebp - 512], ebx + +// CHECK: aadd dword ptr [ecx + 2032], ebx +// CHECK: encoding: [0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + aadd dword ptr [ecx + 2032], ebx + +// CHECK: aadd dword ptr [edx - 2048], ebx +// CHECK: encoding: [0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + aadd dword ptr [edx - 2048], ebx + +// CHECK: aand dword ptr [esp + 8*esi + 268435456], ebx +// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + aand dword ptr [esp + 8*esi + 268435456], ebx + +// CHECK: aand dword ptr [edi + 4*eax + 291], ebx +// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + aand dword ptr [edi + 4*eax + 291], ebx + +// CHECK: aand dword ptr [eax], ebx +// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x18] + aand dword ptr [eax], ebx + +// CHECK: aand dword ptr [2*ebp - 512], ebx +// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + aand dword ptr [2*ebp - 512], ebx + +// CHECK: aand dword ptr [ecx + 2032], ebx +// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + aand dword ptr [ecx + 2032], ebx + +// CHECK: aand dword ptr [edx - 2048], ebx +// CHECK: encoding: [0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + aand dword ptr [edx - 2048], ebx + +// CHECK: aor dword ptr [esp + 8*esi + 268435456], ebx +// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + aor dword ptr [esp + 8*esi + 268435456], ebx + +// CHECK: aor dword ptr [edi + 4*eax + 291], ebx +// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + aor dword ptr [edi + 4*eax + 291], ebx + +// CHECK: aor dword ptr [eax], ebx +// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x18] + aor dword ptr [eax], ebx + +// CHECK: aor dword ptr [2*ebp - 512], ebx +// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + aor dword ptr [2*ebp - 512], ebx + +// CHECK: aor dword ptr [ecx + 2032], ebx +// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + aor dword ptr [ecx + 2032], ebx + +// CHECK: aor dword ptr [edx - 2048], ebx +// CHECK: encoding: [0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + aor dword ptr [edx - 2048], ebx + +// CHECK: axor dword ptr [esp + 8*esi + 268435456], ebx +// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + axor dword ptr [esp + 8*esi + 268435456], ebx + +// CHECK: axor dword ptr [edi + 4*eax + 291], ebx +// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + axor dword ptr [edi + 4*eax + 291], ebx + +// CHECK: axor dword ptr [eax], ebx +// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x18] + axor dword ptr [eax], ebx + +// CHECK: axor dword ptr [2*ebp - 512], ebx +// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + axor dword ptr [2*ebp - 512], ebx + +// CHECK: axor dword ptr [ecx + 2032], ebx +// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + axor dword ptr [ecx + 2032], ebx + +// CHECK: axor dword ptr [edx - 2048], ebx +// CHECK: encoding: [0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + axor dword ptr [edx - 2048], ebx diff --git a/llvm/test/MC/X86/x86-64-rao-int-att.s b/llvm/test/MC/X86/x86-64-rao-int-att.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/X86/x86-64-rao-int-att.s @@ -0,0 +1,193 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s + +// CHECK: aaddq %r9, 268435456(%rbp,%r14,8) +// CHECK: encoding: [0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10] + aaddq %r9, 268435456(%rbp,%r14,8) + +// CHECK: aaddq %r9, 291(%r8,%rax,4) +// CHECK: encoding: [0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00] + aaddq %r9, 291(%r8,%rax,4) + +// CHECK: aaddq %r9, (%rip) +// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00] + aaddq %r9, (%rip) + +// CHECK: aaddq %r9, -512(,%rbp,2) +// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff] + aaddq %r9, -512(,%rbp,2) + +// CHECK: aaddq %r9, 2032(%rcx) +// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00] + aaddq %r9, 2032(%rcx) + +// CHECK: aaddq %r9, -2048(%rdx) +// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff] + aaddq %r9, -2048(%rdx) + +// CHECK: aaddl %ebx, 268435456(%esp,%esi,8) +// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + aaddl %ebx, 268435456(%esp,%esi,8) + +// CHECK: aaddl %ebx, 291(%edi,%eax,4) +// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + aaddl %ebx, 291(%edi,%eax,4) + +// CHECK: aaddl %ebx, (%eax) +// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x18] + aaddl %ebx, (%eax) + +// CHECK: aaddl %ebx, -512(,%ebp,2) +// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + aaddl %ebx, -512(,%ebp,2) + +// CHECK: aaddl %ebx, 2032(%ecx) +// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + aaddl %ebx, 2032(%ecx) + +// CHECK: aaddl %ebx, -2048(%edx) +// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + aaddl %ebx, -2048(%edx) + +// CHECK: aandq %r9, 268435456(%rbp,%r14,8) +// CHECK: encoding: [0x66,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10] + aandq %r9, 268435456(%rbp,%r14,8) + +// CHECK: aandq %r9, 291(%r8,%rax,4) +// CHECK: encoding: [0x66,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00] + aandq %r9, 291(%r8,%rax,4) + +// CHECK: aandq %r9, (%rip) +// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00] + aandq %r9, (%rip) + +// CHECK: aandq %r9, -512(,%rbp,2) +// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff] + aandq %r9, -512(,%rbp,2) + +// CHECK: aandq %r9, 2032(%rcx) +// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00] + aandq %r9, 2032(%rcx) + +// CHECK: aandq %r9, -2048(%rdx) +// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff] + aandq %r9, -2048(%rdx) + +// CHECK: aandl %ebx, 268435456(%esp,%esi,8) +// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + aandl %ebx, 268435456(%esp,%esi,8) + +// CHECK: aandl %ebx, 291(%edi,%eax,4) +// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + aandl %ebx, 291(%edi,%eax,4) + +// CHECK: aandl %ebx, (%eax) +// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x18] + aandl %ebx, (%eax) + +// CHECK: aandl %ebx, -512(,%ebp,2) +// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + aandl %ebx, -512(,%ebp,2) + +// CHECK: aandl %ebx, 2032(%ecx) +// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + aandl %ebx, 2032(%ecx) + +// CHECK: aandl %ebx, -2048(%edx) +// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + aandl %ebx, -2048(%edx) + +// CHECK: aorq %r9, 268435456(%rbp,%r14,8) +// CHECK: encoding: [0xf2,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10] + aorq %r9, 268435456(%rbp,%r14,8) + +// CHECK: aorq %r9, 291(%r8,%rax,4) +// CHECK: encoding: [0xf2,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00] + aorq %r9, 291(%r8,%rax,4) + +// CHECK: aorq %r9, (%rip) +// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00] + aorq %r9, (%rip) + +// CHECK: aorq %r9, -512(,%rbp,2) +// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff] + aorq %r9, -512(,%rbp,2) + +// CHECK: aorq %r9, 2032(%rcx) +// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00] + aorq %r9, 2032(%rcx) + +// CHECK: aorq %r9, -2048(%rdx) +// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff] + aorq %r9, -2048(%rdx) + +// CHECK: aorl %ebx, 268435456(%esp,%esi,8) +// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + aorl %ebx, 268435456(%esp,%esi,8) + +// CHECK: aorl %ebx, 291(%edi,%eax,4) +// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + aorl %ebx, 291(%edi,%eax,4) + +// CHECK: aorl %ebx, (%eax) +// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x18] + aorl %ebx, (%eax) + +// CHECK: aorl %ebx, -512(,%ebp,2) +// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + aorl %ebx, -512(,%ebp,2) + +// CHECK: aorl %ebx, 2032(%ecx) +// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + aorl %ebx, 2032(%ecx) + +// CHECK: aorl %ebx, -2048(%edx) +// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + aorl %ebx, -2048(%edx) + +// CHECK: axorq %r9, 268435456(%rbp,%r14,8) +// CHECK: encoding: [0xf3,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10] + axorq %r9, 268435456(%rbp,%r14,8) + +// CHECK: axorq %r9, 291(%r8,%rax,4) +// CHECK: encoding: [0xf3,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00] + axorq %r9, 291(%r8,%rax,4) + +// CHECK: axorq %r9, (%rip) +// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00] + axorq %r9, (%rip) + +// CHECK: axorq %r9, -512(,%rbp,2) +// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff] + axorq %r9, -512(,%rbp,2) + +// CHECK: axorq %r9, 2032(%rcx) +// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00] + axorq %r9, 2032(%rcx) + +// CHECK: axorq %r9, -2048(%rdx) +// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff] + axorq %r9, -2048(%rdx) + +// CHECK: axorl %ebx, 268435456(%esp,%esi,8) +// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + axorl %ebx, 268435456(%esp,%esi,8) + +// CHECK: axorl %ebx, 291(%edi,%eax,4) +// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + axorl %ebx, 291(%edi,%eax,4) + +// CHECK: axorl %ebx, (%eax) +// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x18] + axorl %ebx, (%eax) + +// CHECK: axorl %ebx, -512(,%ebp,2) +// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + axorl %ebx, -512(,%ebp,2) + +// CHECK: axorl %ebx, 2032(%ecx) +// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + axorl %ebx, 2032(%ecx) + +// CHECK: axorl %ebx, -2048(%edx) +// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + axorl %ebx, -2048(%edx) diff --git a/llvm/test/MC/X86/x86-64-rao-int-intel.s b/llvm/test/MC/X86/x86-64-rao-int-intel.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/X86/x86-64-rao-int-intel.s @@ -0,0 +1,193 @@ +// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s + +// CHECK: aadd qword ptr [rbp + 8*r14 + 268435456], r9 +// CHECK: encoding: [0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10] + aadd qword ptr [rbp + 8*r14 + 268435456], r9 + +// CHECK: aadd qword ptr [r8 + 4*rax + 291], r9 +// CHECK: encoding: [0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00] + aadd qword ptr [r8 + 4*rax + 291], r9 + +// CHECK: aadd qword ptr [rip], r9 +// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00] + aadd qword ptr [rip], r9 + +// CHECK: aadd qword ptr [2*rbp - 512], r9 +// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff] + aadd qword ptr [2*rbp - 512], r9 + +// CHECK: aadd qword ptr [rcx + 2032], r9 +// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00] + aadd qword ptr [rcx + 2032], r9 + +// CHECK: aadd qword ptr [rdx - 2048], r9 +// CHECK: encoding: [0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff] + aadd qword ptr [rdx - 2048], r9 + +// CHECK: aadd dword ptr [esp + 8*esi + 268435456], ebx +// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + aadd dword ptr [esp + 8*esi + 268435456], ebx + +// CHECK: aadd dword ptr [edi + 4*eax + 291], ebx +// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + aadd dword ptr [edi + 4*eax + 291], ebx + +// CHECK: aadd dword ptr [eax], ebx +// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x18] + aadd dword ptr [eax], ebx + +// CHECK: aadd dword ptr [2*ebp - 512], ebx +// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + aadd dword ptr [2*ebp - 512], ebx + +// CHECK: aadd dword ptr [ecx + 2032], ebx +// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + aadd dword ptr [ecx + 2032], ebx + +// CHECK: aadd dword ptr [edx - 2048], ebx +// CHECK: encoding: [0x67,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + aadd dword ptr [edx - 2048], ebx + +// CHECK: aand qword ptr [rbp + 8*r14 + 268435456], r9 +// CHECK: encoding: [0x66,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10] + aand qword ptr [rbp + 8*r14 + 268435456], r9 + +// CHECK: aand qword ptr [r8 + 4*rax + 291], r9 +// CHECK: encoding: [0x66,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00] + aand qword ptr [r8 + 4*rax + 291], r9 + +// CHECK: aand qword ptr [rip], r9 +// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00] + aand qword ptr [rip], r9 + +// CHECK: aand qword ptr [2*rbp - 512], r9 +// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff] + aand qword ptr [2*rbp - 512], r9 + +// CHECK: aand qword ptr [rcx + 2032], r9 +// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00] + aand qword ptr [rcx + 2032], r9 + +// CHECK: aand qword ptr [rdx - 2048], r9 +// CHECK: encoding: [0x66,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff] + aand qword ptr [rdx - 2048], r9 + +// CHECK: aand dword ptr [esp + 8*esi + 268435456], ebx +// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + aand dword ptr [esp + 8*esi + 268435456], ebx + +// CHECK: aand dword ptr [edi + 4*eax + 291], ebx +// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + aand dword ptr [edi + 4*eax + 291], ebx + +// CHECK: aand dword ptr [eax], ebx +// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x18] + aand dword ptr [eax], ebx + +// CHECK: aand dword ptr [2*ebp - 512], ebx +// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + aand dword ptr [2*ebp - 512], ebx + +// CHECK: aand dword ptr [ecx + 2032], ebx +// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + aand dword ptr [ecx + 2032], ebx + +// CHECK: aand dword ptr [edx - 2048], ebx +// CHECK: encoding: [0x67,0x66,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + aand dword ptr [edx - 2048], ebx + +// CHECK: aor qword ptr [rbp + 8*r14 + 268435456], r9 +// CHECK: encoding: [0xf2,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10] + aor qword ptr [rbp + 8*r14 + 268435456], r9 + +// CHECK: aor qword ptr [r8 + 4*rax + 291], r9 +// CHECK: encoding: [0xf2,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00] + aor qword ptr [r8 + 4*rax + 291], r9 + +// CHECK: aor qword ptr [rip], r9 +// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00] + aor qword ptr [rip], r9 + +// CHECK: aor qword ptr [2*rbp - 512], r9 +// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff] + aor qword ptr [2*rbp - 512], r9 + +// CHECK: aor qword ptr [rcx + 2032], r9 +// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00] + aor qword ptr [rcx + 2032], r9 + +// CHECK: aor qword ptr [rdx - 2048], r9 +// CHECK: encoding: [0xf2,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff] + aor qword ptr [rdx - 2048], r9 + +// CHECK: aor dword ptr [esp + 8*esi + 268435456], ebx +// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + aor dword ptr [esp + 8*esi + 268435456], ebx + +// CHECK: aor dword ptr [edi + 4*eax + 291], ebx +// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + aor dword ptr [edi + 4*eax + 291], ebx + +// CHECK: aor dword ptr [eax], ebx +// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x18] + aor dword ptr [eax], ebx + +// CHECK: aor dword ptr [2*ebp - 512], ebx +// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + aor dword ptr [2*ebp - 512], ebx + +// CHECK: aor dword ptr [ecx + 2032], ebx +// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + aor dword ptr [ecx + 2032], ebx + +// CHECK: aor dword ptr [edx - 2048], ebx +// CHECK: encoding: [0x67,0xf2,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + aor dword ptr [edx - 2048], ebx + +// CHECK: axor qword ptr [rbp + 8*r14 + 268435456], r9 +// CHECK: encoding: [0xf3,0x4e,0x0f,0x38,0xfc,0x8c,0xf5,0x00,0x00,0x00,0x10] + axor qword ptr [rbp + 8*r14 + 268435456], r9 + +// CHECK: axor qword ptr [r8 + 4*rax + 291], r9 +// CHECK: encoding: [0xf3,0x4d,0x0f,0x38,0xfc,0x8c,0x80,0x23,0x01,0x00,0x00] + axor qword ptr [r8 + 4*rax + 291], r9 + +// CHECK: axor qword ptr [rip], r9 +// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x0d,0x00,0x00,0x00,0x00] + axor qword ptr [rip], r9 + +// CHECK: axor qword ptr [2*rbp - 512], r9 +// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x0c,0x6d,0x00,0xfe,0xff,0xff] + axor qword ptr [2*rbp - 512], r9 + +// CHECK: axor qword ptr [rcx + 2032], r9 +// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x89,0xf0,0x07,0x00,0x00] + axor qword ptr [rcx + 2032], r9 + +// CHECK: axor qword ptr [rdx - 2048], r9 +// CHECK: encoding: [0xf3,0x4c,0x0f,0x38,0xfc,0x8a,0x00,0xf8,0xff,0xff] + axor qword ptr [rdx - 2048], r9 + +// CHECK: axor dword ptr [esp + 8*esi + 268435456], ebx +// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9c,0xf4,0x00,0x00,0x00,0x10] + axor dword ptr [esp + 8*esi + 268435456], ebx + +// CHECK: axor dword ptr [edi + 4*eax + 291], ebx +// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9c,0x87,0x23,0x01,0x00,0x00] + axor dword ptr [edi + 4*eax + 291], ebx + +// CHECK: axor dword ptr [eax], ebx +// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x18] + axor dword ptr [eax], ebx + +// CHECK: axor dword ptr [2*ebp - 512], ebx +// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x1c,0x6d,0x00,0xfe,0xff,0xff] + axor dword ptr [2*ebp - 512], ebx + +// CHECK: axor dword ptr [ecx + 2032], ebx +// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x99,0xf0,0x07,0x00,0x00] + axor dword ptr [ecx + 2032], ebx + +// CHECK: axor dword ptr [edx - 2048], ebx +// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xfc,0x9a,0x00,0xf8,0xff,0xff] + axor dword ptr [edx - 2048], ebx