diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -2556,9 +2556,6 @@
   if (!isOpcWithIntImmediate(N, ISD::SHL, ShlImm))
     return false;
 
-  if (!BiggerPattern && !Op.hasOneUse())
-    return false;
-
   EVT VT = N->getValueType(0);
   assert((VT == MVT::i32 || VT == MVT::i64) &&
          "Caller guarantees that type is i32 or i64");
diff --git a/llvm/test/CodeGen/AArch64/bitfield-insert.ll b/llvm/test/CodeGen/AArch64/bitfield-insert.ll
--- a/llvm/test/CodeGen/AArch64/bitfield-insert.ll
+++ b/llvm/test/CodeGen/AArch64/bitfield-insert.ll
@@ -266,10 +266,9 @@
 ; CHECK-LABEL: test_nouseful_bits:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    and w8, w0, #0xff
+; CHECK-NEXT:    bfi w0, w8, #8, #8
 ; CHECK-NEXT:    lsl w8, w8, #8
-; CHECK-NEXT:    mov w9, w8
-; CHECK-NEXT:    bfxil w9, w0, #0, #8
-; CHECK-NEXT:    bfi w8, w9, #16, #16
+; CHECK-NEXT:    bfi w8, w0, #16, #16
 ; CHECK-NEXT:    mov w0, w8
 ; CHECK-NEXT:    ret
   %conv = zext i8 %a to i32     ;   0  0  0  A