diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -1024,6 +1024,20 @@
 defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>;
 defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>;
 
+let OtherPredicates = [HasTrue16BitInsts] in {
+defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U16_t16_e64, i16>;
+defm : ICMP_Pattern <COND_NE, V_CMP_NE_U16_t16_e64, i16>;
+defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U16_t16_e64, i16>;
+defm : ICMP_Pattern <COND_UGE, V_CMP_GE_U16_t16_e64, i16>;
+defm : ICMP_Pattern <COND_ULT, V_CMP_LT_U16_t16_e64, i16>;
+defm : ICMP_Pattern <COND_ULE, V_CMP_LE_U16_t16_e64, i16>;
+defm : ICMP_Pattern <COND_SGT, V_CMP_GT_I16_t16_e64, i16>;
+defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I16_t16_e64, i16>;
+defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I16_t16_e64, i16>;
+defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_t16_e64, i16>;
+} // End OtherPredicates = [HasTrue16BitInsts]
+
+let OtherPredicates = [NotHasTrue16BitInsts] in {
 defm : ICMP_Pattern <COND_EQ, V_CMP_EQ_U16_e64, i16>;
 defm : ICMP_Pattern <COND_NE, V_CMP_NE_U16_e64, i16>;
 defm : ICMP_Pattern <COND_UGT, V_CMP_GT_U16_e64, i16>;
@@ -1034,6 +1048,7 @@
 defm : ICMP_Pattern <COND_SGE, V_CMP_GE_I16_e64, i16>;
 defm : ICMP_Pattern <COND_SLT, V_CMP_LT_I16_e64, i16>;
 defm : ICMP_Pattern <COND_SLE, V_CMP_LE_I16_e64, i16>;
+} // End OtherPredicates = [NotHasTrue16BitInsts]
 
 multiclass FCMP_Pattern <PatFrags cond, Instruction inst, ValueType vt> {
   let WaveSizePredicate = isWave64 in
@@ -1067,14 +1082,6 @@
 defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>;
 defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>;
 
-defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_e64, f16>;
-defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_e64, f16>;
-defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F16_e64, f16>;
-defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F16_e64, f16>;
-defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F16_e64, f16>;
-defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F16_e64, f16>;
-
-
 defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>;
 defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>;
 defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>;
@@ -1089,12 +1096,37 @@
 defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>;
 defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>;
 
+let OtherPredicates = [HasTrue16BitInsts] in {
+defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_t16_e64, f16>;
+defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_t16_e64, f16>;
+defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F16_t16_e64, f16>;
+defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F16_t16_e64, f16>;
+defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F16_t16_e64, f16>;
+defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F16_t16_e64, f16>;
+
+defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F16_t16_e64, f16>;
+defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F16_t16_e64, f16>;
+defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F16_t16_e64, f16>;
+defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F16_t16_e64, f16>;
+defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F16_t16_e64, f16>;
+defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_t16_e64, f16>;
+} // End OtherPredicates = [HasTrue16BitInsts]
+
+let OtherPredicates = [NotHasTrue16BitInsts] in {
+defm : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F16_e64, f16>;
+defm : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F16_e64, f16>;
+defm : FCMP_Pattern <COND_OGT, V_CMP_GT_F16_e64, f16>;
+defm : FCMP_Pattern <COND_OGE, V_CMP_GE_F16_e64, f16>;
+defm : FCMP_Pattern <COND_OLT, V_CMP_LT_F16_e64, f16>;
+defm : FCMP_Pattern <COND_OLE, V_CMP_LE_F16_e64, f16>;
+
 defm : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F16_e64, f16>;
 defm : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F16_e64, f16>;
 defm : FCMP_Pattern <COND_UGT, V_CMP_NLE_F16_e64, f16>;
 defm : FCMP_Pattern <COND_UGE, V_CMP_NLT_F16_e64, f16>;
 defm : FCMP_Pattern <COND_ULT, V_CMP_NGE_F16_e64, f16>;
 defm : FCMP_Pattern <COND_ULE, V_CMP_NGT_F16_e64, f16>;
+} // End OtherPredicates = [NotHasTrue16BitInsts]
 
 //===----------------------------------------------------------------------===//
 // DPP Encodings
diff --git a/llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll b/llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/v_cmp_gfx11.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK %s
+
+define amdgpu_kernel void @test() {
+; CHECK-LABEL: test:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    v_cmp_eq_u16_e64 s0, 0, 0
+; CHECK-NEXT:    v_mov_b32_e32 v1, 0
+; CHECK-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; CHECK-NEXT:    s_cmp_eq_u32 s0, 0
+; CHECK-NEXT:    s_cselect_b32 s0, -1, 0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
+; CHECK-NEXT:    ds_store_b32 v1, v0
+; CHECK-NEXT:    s_endpgm
+entry:
+  %0 = tail call i64 @llvm.amdgcn.icmp.i64.i16(i16 0, i16 0, i32 32)
+  %cmp0 = icmp eq i64 %0, 0
+  %add0 = zext i1 %cmp0 to i32
+  store i32 %add0, ptr addrspace(3) null, align 2147483648
+  ret void
+}
+
+; Function Attrs: convergent nounwind readnone willreturn
+declare i64 @llvm.amdgcn.icmp.i64.i16(i16, i16, i32 immarg) #0
+
+attributes #0 = { convergent nounwind readnone willreturn }