diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -824,6 +824,8 @@
   // TODO: s16 support.
   getActionDefinitionsBuilder(G_FCOPYSIGN).customFor({{s32, s32}, {s64, s64}});
 
+  getActionDefinitionsBuilder(G_FMAD).lower();
+
   getLegacyLegalizerInfo().computeTables();
   verify(*ST.getInstrInfo());
 }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmad.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmad.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmad.mir
@@ -0,0 +1,148 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -verify-machineinstrs -mtriple=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
+
+...
+---
+name:            s16
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $h0, $h1, $h2
+    ; CHECK-LABEL: name: s16
+    ; CHECK: liveins: $h0, $h1, $h2
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %op0:_(s16) = COPY $h0
+    ; CHECK-NEXT: %op1:_(s16) = COPY $h1
+    ; CHECK-NEXT: %op2:_(s16) = COPY $h2
+    ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %op0(s16)
+    ; CHECK-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %op1(s16)
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[FPEXT1]]
+    ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMUL]](s32)
+    ; CHECK-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FPTRUNC]](s16)
+    ; CHECK-NEXT: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT %op2(s16)
+    ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT2]], [[FPEXT3]]
+    ; CHECK-NEXT: %fmad:_(s16) = G_FPTRUNC [[FADD]](s32)
+    ; CHECK-NEXT: $h0 = COPY %fmad(s16)
+    ; CHECK-NEXT: RET_ReallyLR implicit $h0
+    %op0:_(s16) = COPY $h0
+    %op1:_(s16) = COPY $h1
+    %op2:_(s16) = COPY $h2
+    %fmad:_(s16) = G_FMAD %op0, %op1, %op2
+    $h0 = COPY %fmad
+    RET_ReallyLR implicit $h0
+...
+---
+name:            s32
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $s0, $s1, $s2
+    ; CHECK-LABEL: name: s32
+    ; CHECK: liveins: $s0, $s1, $s2
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %op0:_(s32) = COPY $s0
+    ; CHECK-NEXT: %op1:_(s32) = COPY $s1
+    ; CHECK-NEXT: %op2:_(s32) = COPY $s2
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL %op0, %op1
+    ; CHECK-NEXT: %fmad:_(s32) = G_FADD [[FMUL]], %op2
+    ; CHECK-NEXT: $s0 = COPY %fmad(s32)
+    ; CHECK-NEXT: RET_ReallyLR implicit $s0
+    %op0:_(s32) = COPY $s0
+    %op1:_(s32) = COPY $s1
+    %op2:_(s32) = COPY $s2
+    %fmad:_(s32) = G_FMAD %op0, %op1, %op2
+    $s0 = COPY %fmad
+    RET_ReallyLR implicit $s0
+...
+---
+name:            s64
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $d0, $d1, $d2
+    ; CHECK-LABEL: name: s64
+    ; CHECK: liveins: $d0, $d1, $d2
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %op0:_(s64) = COPY $d0
+    ; CHECK-NEXT: %op1:_(s64) = COPY $d1
+    ; CHECK-NEXT: %op2:_(s64) = COPY $d2
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL %op0, %op1
+    ; CHECK-NEXT: %fmad:_(s64) = G_FADD [[FMUL]], %op2
+    ; CHECK-NEXT: $d0 = COPY %fmad(s64)
+    ; CHECK-NEXT: RET_ReallyLR implicit $d0
+    %op0:_(s64) = COPY $d0
+    %op1:_(s64) = COPY $d1
+    %op2:_(s64) = COPY $d2
+    %fmad:_(s64) = G_FMAD %op0, %op1, %op2
+    $d0 = COPY %fmad
+    RET_ReallyLR implicit $d0
+...
+---
+name:            v2s32
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $d0, $d1, $d2
+    ; CHECK-LABEL: name: v2s32
+    ; CHECK: liveins: $d0, $d1, $d2
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %op0:_(<2 x s32>) = COPY $d0
+    ; CHECK-NEXT: %op1:_(<2 x s32>) = COPY $d1
+    ; CHECK-NEXT: %op2:_(<2 x s32>) = COPY $d2
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(<2 x s32>) = G_FMUL %op0, %op1
+    ; CHECK-NEXT: %fmad:_(<2 x s32>) = G_FADD [[FMUL]], %op2
+    ; CHECK-NEXT: $d0 = COPY %fmad(<2 x s32>)
+    ; CHECK-NEXT: RET_ReallyLR implicit $d0
+    %op0:_(<2 x s32>) = COPY $d0
+    %op1:_(<2 x s32>) = COPY $d1
+    %op2:_(<2 x s32>) = COPY $d2
+    %fmad:_(<2 x s32>) = G_FMAD %op0, %op1, %op2
+    $d0 = COPY %fmad
+    RET_ReallyLR implicit $d0
+...
+---
+name:            v4s32
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $q0, $q1, $q2
+    ; CHECK-LABEL: name: v4s32
+    ; CHECK: liveins: $q0, $q1, $q2
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %op0:_(<4 x s32>) = COPY $q0
+    ; CHECK-NEXT: %op1:_(<4 x s32>) = COPY $q1
+    ; CHECK-NEXT: %op2:_(<4 x s32>) = COPY $q2
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(<4 x s32>) = G_FMUL %op0, %op1
+    ; CHECK-NEXT: %fmad:_(<4 x s32>) = G_FADD [[FMUL]], %op2
+    ; CHECK-NEXT: $q0 = COPY %fmad(<4 x s32>)
+    ; CHECK-NEXT: RET_ReallyLR implicit $q0
+    %op0:_(<4 x s32>) = COPY $q0
+    %op1:_(<4 x s32>) = COPY $q1
+    %op2:_(<4 x s32>) = COPY $q2
+    %fmad:_(<4 x s32>) = G_FMAD %op0, %op1, %op2
+    $q0 = COPY %fmad
+    RET_ReallyLR implicit $q0
+...
+---
+name:            v2s64
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $q0, $q1, $q2
+    ; CHECK-LABEL: name: v2s64
+    ; CHECK: liveins: $q0, $q1, $q2
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: %op0:_(<2 x s64>) = COPY $q0
+    ; CHECK-NEXT: %op1:_(<2 x s64>) = COPY $q1
+    ; CHECK-NEXT: %op2:_(<2 x s64>) = COPY $q2
+    ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(<2 x s64>) = G_FMUL %op0, %op1
+    ; CHECK-NEXT: %fmad:_(<2 x s64>) = G_FADD [[FMUL]], %op2
+    ; CHECK-NEXT: $q0 = COPY %fmad(<2 x s64>)
+    ; CHECK-NEXT: RET_ReallyLR implicit $q0
+    %op0:_(<2 x s64>) = COPY $q0
+    %op1:_(<2 x s64>) = COPY $q1
+    %op2:_(<2 x s64>) = COPY $q2
+    %fmad:_(<2 x s64>) = G_FMAD %op0, %op1, %op2
+    $q0 = COPY %fmad
+    RET_ReallyLR implicit $q0
+...