diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -10188,6 +10188,21 @@ return false; switch (Opcode) { + case AMDGPU::G_FADD: + case AMDGPU::G_FSUB: + case AMDGPU::G_FMUL: + case AMDGPU::G_FMA: + case AMDGPU::G_FMAD: + case AMDGPU::G_FDIV: + case AMDGPU::G_FREM: + case AMDGPU::G_FPOW: + case AMDGPU::G_FPEXT: + case AMDGPU::G_FPTRUNC: + return true; + case AMDGPU::G_FNEG: + case AMDGPU::G_FABS: + case AMDGPU::G_FCOPYSIGN: + return isCanonicalized(MI->getOperand(1).getReg(), MF, MaxDepth - 1); case AMDGPU::G_FMINNUM_IEEE: case AMDGPU::G_FMAXNUM_IEEE: { if (Subtarget->supportsMinMaxDenormModes() || diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll @@ -473,8 +473,8 @@ ; GFX9-DENORM-NEXT: v_sub_f16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX9-DENORM-NEXT: v_sub_f16_e32 v3, v1, v5 ; GFX9-DENORM-NEXT: v_sub_f16_sdwa v1, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX9-DENORM-NEXT: v_lshl_or_b32 v0, v0, 16, v2 -; GFX9-DENORM-NEXT: v_lshl_or_b32 v1, v1, 16, v3 +; GFX9-DENORM-NEXT: v_pack_b32_f16 v0, v2, v0 +; GFX9-DENORM-NEXT: v_pack_b32_f16 v1, v3, v1 ; GFX9-DENORM-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_v4f16_sub_mul: @@ -506,13 +506,11 @@ ; GFX10-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3 ; GFX10-DENORM-NEXT: v_sub_f16_e32 v2, v0, v4 -; GFX10-DENORM-NEXT: v_sub_f16_e32 v3, v1, v5 ; GFX10-DENORM-NEXT: v_sub_f16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-DENORM-NEXT: v_sub_f16_e32 v3, v1, v5 ; GFX10-DENORM-NEXT: v_sub_f16_sdwa v1, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX10-DENORM-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX10-DENORM-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX10-DENORM-NEXT: v_lshl_or_b32 v0, v0, 16, v2 -; GFX10-DENORM-NEXT: v_lshl_or_b32 v1, v1, 16, v3 +; GFX10-DENORM-NEXT: v_pack_b32_f16 v0, v2, v0 +; GFX10-DENORM-NEXT: v_pack_b32_f16 v1, v3, v1 ; GFX10-DENORM-NEXT: s_setpc_b64 s[30:31] .entry: %a = fmul <4 x half> %x, %y @@ -550,8 +548,8 @@ ; GFX9-DENORM-NEXT: v_sub_f16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX9-DENORM-NEXT: v_sub_f16_e32 v3, v5, v1 ; GFX9-DENORM-NEXT: v_sub_f16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX9-DENORM-NEXT: v_lshl_or_b32 v0, v0, 16, v2 -; GFX9-DENORM-NEXT: v_lshl_or_b32 v1, v1, 16, v3 +; GFX9-DENORM-NEXT: v_pack_b32_f16 v0, v2, v0 +; GFX9-DENORM-NEXT: v_pack_b32_f16 v1, v3, v1 ; GFX9-DENORM-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_v4f16_sub_mul_rhs: @@ -583,13 +581,11 @@ ; GFX10-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2 ; GFX10-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3 ; GFX10-DENORM-NEXT: v_sub_f16_e32 v2, v4, v0 -; GFX10-DENORM-NEXT: v_sub_f16_e32 v3, v5, v1 ; GFX10-DENORM-NEXT: v_sub_f16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-DENORM-NEXT: v_sub_f16_e32 v3, v5, v1 ; GFX10-DENORM-NEXT: v_sub_f16_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX10-DENORM-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX10-DENORM-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX10-DENORM-NEXT: v_lshl_or_b32 v0, v0, 16, v2 -; GFX10-DENORM-NEXT: v_lshl_or_b32 v1, v1, 16, v3 +; GFX10-DENORM-NEXT: v_pack_b32_f16 v0, v2, v0 +; GFX10-DENORM-NEXT: v_pack_b32_f16 v1, v3, v1 ; GFX10-DENORM-NEXT: s_setpc_b64 s[30:31] .entry: %a = fmul <4 x half> %x, %y diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll @@ -261,8 +261,8 @@ ; GFX9-DENORM-NEXT: v_sub_f16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; GFX9-DENORM-NEXT: v_sub_f16_e32 v3, v1, v5 ; GFX9-DENORM-NEXT: v_sub_f16_sdwa v1, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX9-DENORM-NEXT: v_lshl_or_b32 v0, v0, 16, v2 -; GFX9-DENORM-NEXT: v_lshl_or_b32 v1, v1, 16, v3 +; GFX9-DENORM-NEXT: v_pack_b32_f16 v0, v2, v0 +; GFX9-DENORM-NEXT: v_pack_b32_f16 v1, v3, v1 ; GFX9-DENORM-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: test_v4f16_sub_ext_neg_mul: @@ -294,13 +294,11 @@ ; GFX10-DENORM-NEXT: v_pk_mul_f16 v0, v0, v2 neg_lo:[0,1] neg_hi:[0,1] ; GFX10-DENORM-NEXT: v_pk_mul_f16 v1, v1, v3 neg_lo:[0,1] neg_hi:[0,1] ; GFX10-DENORM-NEXT: v_sub_f16_e32 v2, v0, v4 -; GFX10-DENORM-NEXT: v_sub_f16_e32 v3, v1, v5 ; GFX10-DENORM-NEXT: v_sub_f16_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 +; GFX10-DENORM-NEXT: v_sub_f16_e32 v3, v1, v5 ; GFX10-DENORM-NEXT: v_sub_f16_sdwa v1, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 -; GFX10-DENORM-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX10-DENORM-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX10-DENORM-NEXT: v_lshl_or_b32 v0, v0, 16, v2 -; GFX10-DENORM-NEXT: v_lshl_or_b32 v1, v1, 16, v3 +; GFX10-DENORM-NEXT: v_pack_b32_f16 v0, v2, v0 +; GFX10-DENORM-NEXT: v_pack_b32_f16 v1, v3, v1 ; GFX10-DENORM-NEXT: s_setpc_b64 s[30:31] entry: %a = fmul <4 x half> %x, %y diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s -# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK +# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK --- name: test_fminnum diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll @@ -6,14 +6,14 @@ ; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX8 %s ; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX8 %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9,GFX9-IEEE %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9,GFX9-FLUSH %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9 %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX89,GFX9 %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10,GFX10-IEEE %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10,GFX10-FLUSH %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-IEEE %s -; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FLUSH %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s define half @v_fdiv_f16(half %a, half %b) { ; GFX6-IEEE-LABEL: v_fdiv_f16: @@ -771,77 +771,40 @@ ; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; -; GFX9-IEEE-LABEL: v_fdiv_v2f16_afn: -; GFX9-IEEE: ; %bb.0: -; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-IEEE-NEXT: v_rcp_f16_e32 v2, v1 -; GFX9-IEEE-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-IEEE-NEXT: v_mul_f16_e32 v2, v0, v2 -; GFX9-IEEE-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v2, v0 -; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-FLUSH-LABEL: v_fdiv_v2f16_afn: -; GFX9-FLUSH: ; %bb.0: -; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-FLUSH-NEXT: v_rcp_f16_e32 v2, v1 -; GFX9-FLUSH-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-FLUSH-NEXT: v_mul_f16_e32 v2, v0, v2 -; GFX9-FLUSH-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX9-FLUSH-NEXT: v_lshl_or_b32 v0, v0, 16, v2 -; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-IEEE-LABEL: v_fdiv_v2f16_afn: -; GFX10-IEEE: ; %bb.0: -; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-IEEE-NEXT: v_rcp_f16_e32 v2, v1 -; GFX10-IEEE-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-IEEE-NEXT: v_mul_f16_e32 v2, v0, v2 -; GFX10-IEEE-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v2, v0 -; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-FLUSH-LABEL: v_fdiv_v2f16_afn: -; GFX10-FLUSH: ; %bb.0: -; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-FLUSH-NEXT: v_rcp_f16_e32 v2, v1 -; GFX10-FLUSH-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-FLUSH-NEXT: v_mul_f16_e32 v2, v0, v2 -; GFX10-FLUSH-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX10-FLUSH-NEXT: v_and_b32_e32 v1, 0xffff, v2 -; GFX10-FLUSH-NEXT: v_lshl_or_b32 v0, v0, 16, v1 -; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-IEEE-LABEL: v_fdiv_v2f16_afn: -; GFX11-IEEE: ; %bb.0: -; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 -; GFX11-IEEE-NEXT: v_rcp_f16_e32 v1, v1 -; GFX11-IEEE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX11-IEEE-NEXT: v_rcp_f16_e32 v2, v2 -; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff -; GFX11-IEEE-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX11-IEEE-NEXT: v_mul_f16_e32 v1, v3, v2 -; GFX11-IEEE-NEXT: v_pack_b32_f16 v0, v0, v1 -; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-FLUSH-LABEL: v_fdiv_v2f16_afn: -; GFX11-FLUSH: ; %bb.0: -; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v1 -; GFX11-FLUSH-NEXT: v_rcp_f16_e32 v1, v1 -; GFX11-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX11-FLUSH-NEXT: v_rcp_f16_e32 v2, v2 -; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff -; GFX11-FLUSH-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX11-FLUSH-NEXT: v_mul_f16_e32 v1, v3, v2 -; GFX11-FLUSH-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31] +; GFX9-LABEL: v_fdiv_v2f16_afn: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_rcp_f16_e32 v2, v1 +; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-NEXT: v_pack_b32_f16 v0, v2, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-LABEL: v_fdiv_v2f16_afn: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: v_rcp_f16_e32 v2, v1 +; GFX10-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX10-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX10-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX10-NEXT: v_pack_b32_f16 v0, v2, v0 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_fdiv_v2f16_afn: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GFX11-NEXT: v_rcp_f16_e32 v1, v1 +; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; GFX11-NEXT: v_rcp_f16_e32 v2, v2 +; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX11-NEXT: v_mul_f16_e32 v1, v3, v2 +; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %fdiv = fdiv afn <2 x half> %a, %b ret <2 x half> %fdiv } @@ -1514,77 +1477,40 @@ ; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; -; GFX9-IEEE-LABEL: v_fdiv_v2f16_afn_ulp25: -; GFX9-IEEE: ; %bb.0: -; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-IEEE-NEXT: v_rcp_f16_e32 v2, v1 -; GFX9-IEEE-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-IEEE-NEXT: v_mul_f16_e32 v2, v0, v2 -; GFX9-IEEE-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v2, v0 -; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-FLUSH-LABEL: v_fdiv_v2f16_afn_ulp25: -; GFX9-FLUSH: ; %bb.0: -; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-FLUSH-NEXT: v_rcp_f16_e32 v2, v1 -; GFX9-FLUSH-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-FLUSH-NEXT: v_mul_f16_e32 v2, v0, v2 -; GFX9-FLUSH-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX9-FLUSH-NEXT: v_lshl_or_b32 v0, v0, 16, v2 -; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-IEEE-LABEL: v_fdiv_v2f16_afn_ulp25: -; GFX10-IEEE: ; %bb.0: -; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-IEEE-NEXT: v_rcp_f16_e32 v2, v1 -; GFX10-IEEE-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-IEEE-NEXT: v_mul_f16_e32 v2, v0, v2 -; GFX10-IEEE-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v2, v0 -; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-FLUSH-LABEL: v_fdiv_v2f16_afn_ulp25: -; GFX10-FLUSH: ; %bb.0: -; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-FLUSH-NEXT: v_rcp_f16_e32 v2, v1 -; GFX10-FLUSH-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-FLUSH-NEXT: v_mul_f16_e32 v2, v0, v2 -; GFX10-FLUSH-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX10-FLUSH-NEXT: v_and_b32_e32 v1, 0xffff, v2 -; GFX10-FLUSH-NEXT: v_lshl_or_b32 v0, v0, 16, v1 -; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-IEEE-LABEL: v_fdiv_v2f16_afn_ulp25: -; GFX11-IEEE: ; %bb.0: -; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 -; GFX11-IEEE-NEXT: v_rcp_f16_e32 v1, v1 -; GFX11-IEEE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX11-IEEE-NEXT: v_rcp_f16_e32 v2, v2 -; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff -; GFX11-IEEE-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX11-IEEE-NEXT: v_mul_f16_e32 v1, v3, v2 -; GFX11-IEEE-NEXT: v_pack_b32_f16 v0, v0, v1 -; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-FLUSH-LABEL: v_fdiv_v2f16_afn_ulp25: -; GFX11-FLUSH: ; %bb.0: -; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v1 -; GFX11-FLUSH-NEXT: v_rcp_f16_e32 v1, v1 -; GFX11-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX11-FLUSH-NEXT: v_rcp_f16_e32 v2, v2 -; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff -; GFX11-FLUSH-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX11-FLUSH-NEXT: v_mul_f16_e32 v1, v3, v2 -; GFX11-FLUSH-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31] +; GFX9-LABEL: v_fdiv_v2f16_afn_ulp25: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_rcp_f16_e32 v2, v1 +; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-NEXT: v_pack_b32_f16 v0, v2, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-LABEL: v_fdiv_v2f16_afn_ulp25: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: v_rcp_f16_e32 v2, v1 +; GFX10-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX10-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX10-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX10-NEXT: v_pack_b32_f16 v0, v2, v0 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_fdiv_v2f16_afn_ulp25: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GFX11-NEXT: v_rcp_f16_e32 v1, v1 +; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; GFX11-NEXT: v_rcp_f16_e32 v2, v2 +; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX11-NEXT: v_mul_f16_e32 v1, v3, v2 +; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %fdiv = fdiv afn <2 x half> %a, %b, !fpmath !0 ret <2 x half> %fdiv } @@ -1779,77 +1705,40 @@ ; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-NEXT: s_setpc_b64 s[30:31] ; -; GFX9-IEEE-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: -; GFX9-IEEE: ; %bb.0: -; GFX9-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-IEEE-NEXT: v_rcp_f16_e32 v2, v1 -; GFX9-IEEE-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-IEEE-NEXT: v_mul_f16_e32 v2, v0, v2 -; GFX9-IEEE-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX9-IEEE-NEXT: v_pack_b32_f16 v0, v2, v0 -; GFX9-IEEE-NEXT: s_setpc_b64 s[30:31] -; -; GFX9-FLUSH-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: -; GFX9-FLUSH: ; %bb.0: -; GFX9-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-FLUSH-NEXT: v_rcp_f16_e32 v2, v1 -; GFX9-FLUSH-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX9-FLUSH-NEXT: v_mul_f16_e32 v2, v0, v2 -; GFX9-FLUSH-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX9-FLUSH-NEXT: v_lshl_or_b32 v0, v0, 16, v2 -; GFX9-FLUSH-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-IEEE-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: -; GFX10-IEEE: ; %bb.0: -; GFX10-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-IEEE-NEXT: v_rcp_f16_e32 v2, v1 -; GFX10-IEEE-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-IEEE-NEXT: v_mul_f16_e32 v2, v0, v2 -; GFX10-IEEE-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX10-IEEE-NEXT: v_pack_b32_f16 v0, v2, v0 -; GFX10-IEEE-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-FLUSH-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: -; GFX10-FLUSH: ; %bb.0: -; GFX10-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-FLUSH-NEXT: v_rcp_f16_e32 v2, v1 -; GFX10-FLUSH-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -; GFX10-FLUSH-NEXT: v_mul_f16_e32 v2, v0, v2 -; GFX10-FLUSH-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD -; GFX10-FLUSH-NEXT: v_and_b32_e32 v1, 0xffff, v2 -; GFX10-FLUSH-NEXT: v_lshl_or_b32 v0, v0, 16, v1 -; GFX10-FLUSH-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-IEEE-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: -; GFX11-IEEE: ; %bb.0: -; GFX11-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-IEEE-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-IEEE-NEXT: v_lshrrev_b32_e32 v2, 16, v1 -; GFX11-IEEE-NEXT: v_rcp_f16_e32 v1, v1 -; GFX11-IEEE-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX11-IEEE-NEXT: v_rcp_f16_e32 v2, v2 -; GFX11-IEEE-NEXT: s_waitcnt_depctr 0xfff -; GFX11-IEEE-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX11-IEEE-NEXT: v_mul_f16_e32 v1, v3, v2 -; GFX11-IEEE-NEXT: v_pack_b32_f16 v0, v0, v1 -; GFX11-IEEE-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-FLUSH-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: -; GFX11-FLUSH: ; %bb.0: -; GFX11-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-FLUSH-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-FLUSH-NEXT: v_lshrrev_b32_e32 v2, 16, v1 -; GFX11-FLUSH-NEXT: v_rcp_f16_e32 v1, v1 -; GFX11-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v0 -; GFX11-FLUSH-NEXT: v_rcp_f16_e32 v2, v2 -; GFX11-FLUSH-NEXT: s_waitcnt_depctr 0xfff -; GFX11-FLUSH-NEXT: v_mul_f16_e32 v0, v0, v1 -; GFX11-FLUSH-NEXT: v_mul_f16_e32 v1, v3, v2 -; GFX11-FLUSH-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-FLUSH-NEXT: s_setpc_b64 s[30:31] +; GFX9-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: v_rcp_f16_e32 v2, v1 +; GFX9-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX9-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX9-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX9-NEXT: v_pack_b32_f16 v0, v2, v0 +; GFX9-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: v_rcp_f16_e32 v2, v1 +; GFX10-NEXT: v_rcp_f16_sdwa v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 +; GFX10-NEXT: v_mul_f16_e32 v2, v0, v2 +; GFX10-NEXT: v_mul_f16_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; GFX10-NEXT: v_pack_b32_f16 v0, v2, v0 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_fdiv_v2f16_arcp_afn_ulp25: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: v_lshrrev_b32_e32 v2, 16, v1 +; GFX11-NEXT: v_rcp_f16_e32 v1, v1 +; GFX11-NEXT: v_lshrrev_b32_e32 v3, 16, v0 +; GFX11-NEXT: v_rcp_f16_e32 v2, v2 +; GFX11-NEXT: s_waitcnt_depctr 0xfff +; GFX11-NEXT: v_mul_f16_e32 v0, v0, v1 +; GFX11-NEXT: v_mul_f16_e32 v1, v3, v2 +; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %fdiv = fdiv afn arcp <2 x half> %a, %b, !fpmath !0 ret <2 x half> %fdiv } diff --git a/llvm/test/CodeGen/AMDGPU/v_pack.ll b/llvm/test/CodeGen/AMDGPU/v_pack.ll --- a/llvm/test/CodeGen/AMDGPU/v_pack.ll +++ b/llvm/test/CodeGen/AMDGPU/v_pack.ll @@ -172,10 +172,7 @@ ; GISEL-NEXT: s_waitcnt vmcnt(0) ; GISEL-NEXT: v_add_f16_e32 v0, 2.0, v1 ; GISEL-NEXT: v_add_f16_e32 v1, 2.0, v2 -; GISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 -; GISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v1 -; GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GISEL-NEXT: v_pack_b32_f16 v0, |v0|, |v1| ; GISEL-NEXT: ;;#ASMSTART ; GISEL-NEXT: ; use v0 ; GISEL-NEXT: ;;#ASMEND