[PowerPC] Fix a number of inefficiencies and issues with atomic code gen

[nemanjai]

Summary

There are a few issues with the code we generate for atomic operations and the way we generate it:

• Hard coded CR0 for compares
• Order of operands for compares not conducive to emitting compare-immediate or for CSE of compares
• Missing MachineMemOperand for st[bhwd]cx intrinsics
• A missing intrinsic property for the same
• Unnecessary blocks with store conditional instructions to clear reservation (which ends up hindering performance)
• Move from CR instructions just to compare the result of a store conditional with zero (even though it is a record-form)

This patch aims to resolve all of those issues.

[lkail]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

15754

Is it missing a test, kinda like

define signext i1 @foo(i64* %addr, i64 %newval) {
entry:
  %0 = bitcast i64* %addr to i8*
  br label %while.cond

while.cond:                                       ; preds = %while.body, %entry
  %1 = tail call i32 @llvm.ppc.stdcx(i8* %0, i64 %newval)
  %ok = icmp eq i32 %1, 0
  br i1 %ok, label %end, label %end.0
end:
  ret i1 0
end.0:
  ret i1 1
}

[nemanjai]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

15754

We have it in test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll but I agree that it would probably be a good idea to add a simplified test case like this for each of the sizes. I'll add one for each of byte/halfword/word/doubleword.

[nemanjai]

Add test cases specifically for branching on store conditional.

[RolandF]

LGTM

[kbarton]

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

1380

What about ppc_sthcx and ppc_stbcx?

[nemanjai]

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

1380

Ah good catch. I missed the subword ones. I'll add them.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_lwsync : ClangBuiltin<"__builtin_ppc_lwsync">,
                        Intrinsic<[], [], []>;
   def int_ppc_iospace_lwsync : ClangBuiltin<"__builtin_ppc_iospace_lwsync">,
                                Intrinsic<[], [], []>;
   // eieio instruction
   def int_ppc_eieio : ClangBuiltin<"__builtin_ppc_eieio">,
                       Intrinsic<[],[],[]>;
   def int_ppc_iospace_eieio : ClangBuiltin<"__builtin_ppc_iospace_eieio">,
                               Intrinsic<[],[],[]>;
-  def int_ppc_stdcx : ClangBuiltin<"__builtin_ppc_stdcx">,
-                      Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i64_ty],
-                                [IntrWriteMem]>;
-  def int_ppc_stwcx : ClangBuiltin<"__builtin_ppc_stwcx">,
-                      Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
-                                [IntrWriteMem]>;
-  def int_ppc_sthcx
-      : Intrinsic<[llvm_i32_ty], [ llvm_ptr_ty, llvm_i32_ty ], [IntrWriteMem]>;
-  def int_ppc_stbcx : ClangBuiltin<"__builtin_ppc_stbcx">,
-                      Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
-                                [IntrWriteMem]>;
+  def int_ppc_stdcx :
+    ClangBuiltin<"__builtin_ppc_stdcx">,
+              [IntrWriteMem, IntrArgMemOnly, IntrNoDuplicate]>;
+  def int_ppc_stwcx :
+    ClangBuiltin<"__builtin_ppc_stwcx">,
+              [IntrWriteMem, IntrArgMemOnly]>;
+  def int_ppc_sthcx :
+    Intrinsic<[llvm_i32_ty], [ llvm_ptr_ty, llvm_i32_ty ],
+              [IntrWriteMem, IntrArgMemOnly, IntrNoDuplicate]>;
+  def int_ppc_stbcx :
+    ClangBuiltin<"__builtin_ppc_stbcx">,
+    Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
+              [IntrWriteMem, IntrArgMemOnly, IntrNoDuplicate]>;
   def int_ppc_dcbtstt : ClangBuiltin<"__builtin_ppc_dcbtstt">,
                         Intrinsic<[], [llvm_ptr_ty],
                                   [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
   def int_ppc_dcbtt : ClangBuiltin<"__builtin_ppc_dcbtt">,
                       Intrinsic<[], [llvm_ptr_ty],
                                 [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
   def int_ppc_mftbu : ClangBuiltin<"__builtin_ppc_mftbu">,
                       Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;

llvm/lib/Target/PowerPC/PPCISelLowering.h

enum NodeType : unsigned {
     ST_VSR_SCAL_INT,
 
     /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
     /// except they ensure that the compare input is zero-extended for
     /// sub-word versions because the atomic loads zero-extend.
     ATOMIC_CMP_SWAP_8,
     ATOMIC_CMP_SWAP_16,
 
+    /// CHAIN,Glue = STORE_COND CHAIN, GPR, Ptr
+    /// The store conditional instruction ST[BHWD]ARX that produces a glue
+    /// result to attach it to a conditional branch.
+    STORE_COND,
+
     /// GPRC = TOC_ENTRY GA, TOC
     /// Loads the entry for GA from the TOC, where the TOC base is given by
     /// the last operand.
     TOC_ENTRY
   };
 
   } // end namespace PPCISD
 

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

case PPCISD::STRICT_FCFID:
     return "PPCISD::STRICT_FCFID";
   case PPCISD::STRICT_FCFIDU:
     return "PPCISD::STRICT_FCFIDU";
   case PPCISD::STRICT_FCFIDS:
     return "PPCISD::STRICT_FCFIDS";
   case PPCISD::STRICT_FCFIDUS:
     return "PPCISD::STRICT_FCFIDUS";
   case PPCISD::LXVRZX:          return "PPCISD::LXVRZX";
+  case PPCISD::STORE_COND:
+    return "PPCISD::STORE_COND";
   }
   return nullptr;
 }
 
 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
                                           EVT VT) const {
   if (!VT.isVector())
     return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB,
   //   add r0, dest, incr
   //   st[wd]cx. r0, ptr
   //   bne- loopMBB
   //   fallthrough --> exitMBB
 
   // For max/min...
   //  loopMBB:
   //   l[wd]arx dest, ptr
-  //   cmpl?[wd] incr, dest
+  //   cmpl?[wd] dest, incr
   //   bgt exitMBB
   //  loop2MBB:
   //   st[wd]cx. dest, ptr
   //   bne- loopMBB
   //   fallthrough --> exitMBB
 
   BB = loopMBB;
   BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
     .addReg(ptrA).addReg(ptrB);
   if (BinOpcode)
     BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
   if (CmpOpcode) {
+    Register CrReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
     // Signed comparisons of byte or halfword values must be sign-extended.
     if (CmpOpcode == PPC::CMPW && AtomicSize < 4) {
       Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
       BuildMI(BB, dl, TII->get(AtomicSize == 1 ? PPC::EXTSB : PPC::EXTSH),
               ExtReg).addReg(dest);
-      BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
-        .addReg(incr).addReg(ExtReg);
+      BuildMI(BB, dl, TII->get(CmpOpcode), CrReg).addReg(ExtReg).addReg(incr);
     } else
-      BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
-        .addReg(incr).addReg(dest);
+      BuildMI(BB, dl, TII->get(CmpOpcode), CrReg).addReg(dest).addReg(incr);
 
     BuildMI(BB, dl, TII->get(PPC::BCC))
-      .addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB);
+        .addImm(CmpPred)
+        .addReg(CrReg)
+        .addMBB(exitMBB);
     BB->addSuccessor(loop2MBB);
     BB->addSuccessor(exitMBB);
     BB = loop2MBB;
   }
   BuildMI(BB, dl, TII->get(StoreMnemonic))
     .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
   BuildMI(BB, dl, TII->get(PPC::BCC))
     .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
MachineBasicBlock *PPCTargetLowering::EmitPartwordAtomicBinary(
   BuildMI(BB, dl, TII->get(PPC::ANDC), Tmp2Reg)
       .addReg(TmpDestReg)
       .addReg(MaskReg);
   BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg);
   if (CmpOpcode) {
     // For unsigned comparisons, we can directly compare the shifted values.
     // For signed comparisons we shift and sign extend.
     Register SReg = RegInfo.createVirtualRegister(GPRC);
+    Register CrReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
     BuildMI(BB, dl, TII->get(PPC::AND), SReg)
         .addReg(TmpDestReg)
         .addReg(MaskReg);
     unsigned ValueReg = SReg;
     unsigned CmpReg = Incr2Reg;
     if (CmpOpcode == PPC::CMPW) {
       ValueReg = RegInfo.createVirtualRegister(GPRC);
       BuildMI(BB, dl, TII->get(PPC::SRW), ValueReg)
           .addReg(SReg)
           .addReg(ShiftReg);
       Register ValueSReg = RegInfo.createVirtualRegister(GPRC);
       BuildMI(BB, dl, TII->get(is8bit ? PPC::EXTSB : PPC::EXTSH), ValueSReg)
           .addReg(ValueReg);
       ValueReg = ValueSReg;
       CmpReg = incr;
     }
-    BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0)
-        .addReg(CmpReg)
-        .addReg(ValueReg);
+    BuildMI(BB, dl, TII->get(CmpOpcode), CrReg).addReg(ValueReg).addReg(CmpReg);
     BuildMI(BB, dl, TII->get(PPC::BCC))
         .addImm(CmpPred)
-        .addReg(PPC::CR0)
+        .addReg(CrReg)
         .addMBB(exitMBB);
     BB->addSuccessor(loop2MBB);
     BB->addSuccessor(exitMBB);
     BB = loop2MBB;
   }
   BuildMI(BB, dl, TII->get(PPC::OR), Tmp4Reg).addReg(Tmp3Reg).addReg(Tmp2Reg);
   BuildMI(BB, dl, TII->get(PPC::STWCX))
       .addReg(Tmp4Reg)
PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
     BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
     BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
     BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
 
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I8)
-    BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_GE);
+    BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_LT);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I16)
-    BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_GE);
+    BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_LT);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I32)
-    BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_GE);
+    BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_LT);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MIN_I64)
-    BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_GE);
+    BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_LT);
 
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I8)
-    BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_LE);
+    BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPW, PPC::PRED_GT);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I16)
-    BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_LE);
+    BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPW, PPC::PRED_GT);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I32)
-    BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_LE);
+    BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPW, PPC::PRED_GT);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_MAX_I64)
-    BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_LE);
+    BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPD, PPC::PRED_GT);
 
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I8)
-    BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_GE);
+    BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_LT);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I16)
-    BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_GE);
+    BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_LT);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I32)
-    BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_GE);
+    BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_LT);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMIN_I64)
-    BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_GE);
+    BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_LT);
 
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I8)
-    BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_LE);
+    BB = EmitPartwordAtomicBinary(MI, BB, true, 0, PPC::CMPLW, PPC::PRED_GT);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I16)
-    BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_LE);
+    BB = EmitPartwordAtomicBinary(MI, BB, false, 0, PPC::CMPLW, PPC::PRED_GT);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I32)
-    BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_LE);
+    BB = EmitAtomicBinary(MI, BB, 4, 0, PPC::CMPLW, PPC::PRED_GT);
   else if (MI.getOpcode() == PPC::ATOMIC_LOAD_UMAX_I64)
-    BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_LE);
+    BB = EmitAtomicBinary(MI, BB, 8, 0, PPC::CMPLD, PPC::PRED_GT);
 
   else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I8)
     BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
   else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I16)
     BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
   else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I32)
     BB = EmitAtomicBinary(MI, BB, 4, 0);
   else if (MI.getOpcode() == PPC::ATOMIC_SWAP_I64)
case PPC::ATOMIC_CMP_SWAP_I32:
       LoadMnemonic = PPC::LWARX;
       StoreMnemonic = PPC::STWCX;
       break;
     case PPC::ATOMIC_CMP_SWAP_I64:
       LoadMnemonic = PPC::LDARX;
       StoreMnemonic = PPC::STDCX;
       break;
     }
+    MachineRegisterInfo &RegInfo = F->getRegInfo();
     Register dest = MI.getOperand(0).getReg();
     Register ptrA = MI.getOperand(1).getReg();
     Register ptrB = MI.getOperand(2).getReg();
+    Register CrReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
     Register oldval = MI.getOperand(3).getReg();
     Register newval = MI.getOperand(4).getReg();
     DebugLoc dl = MI.getDebugLoc();
 
     MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
     MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
     MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
     F->insert(It, loop1MBB);
     F->insert(It, loop2MBB);
-    F->insert(It, midMBB);
     F->insert(It, exitMBB);
     exitMBB->splice(exitMBB->begin(), BB,
                     std::next(MachineBasicBlock::iterator(MI)), BB->end());
     exitMBB->transferSuccessorsAndUpdatePHIs(BB);
 
     //  thisMBB:
     //   ...
     //   fallthrough --> loopMBB
     BB->addSuccessor(loop1MBB);
 
     // loop1MBB:
     //   l[bhwd]arx dest, ptr
     //   cmp[wd] dest, oldval
-    //   bne- midMBB
+    //   bne- exitBB
     // loop2MBB:
     //   st[bhwd]cx. newval, ptr
     //   bne- loopMBB
     //   b exitBB
-    // midMBB:
-    //   st[bhwd]cx. dest, ptr
     // exitBB:
     BB = loop1MBB;
     BuildMI(BB, dl, TII->get(LoadMnemonic), dest).addReg(ptrA).addReg(ptrB);
-    BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
-        .addReg(oldval)
-        .addReg(dest);
+    BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), CrReg)
+        .addReg(dest)
+        .addReg(oldval);
     BuildMI(BB, dl, TII->get(PPC::BCC))
         .addImm(PPC::PRED_NE)
-        .addReg(PPC::CR0)
-        .addMBB(midMBB);
+        .addReg(CrReg)
+        .addMBB(exitMBB);
     BB->addSuccessor(loop2MBB);
-    BB->addSuccessor(midMBB);
+    BB->addSuccessor(exitMBB);
 
     BB = loop2MBB;
     BuildMI(BB, dl, TII->get(StoreMnemonic))
         .addReg(newval)
         .addReg(ptrA)
         .addReg(ptrB);
     BuildMI(BB, dl, TII->get(PPC::BCC))
         .addImm(PPC::PRED_NE)
         .addReg(PPC::CR0)
         .addMBB(loop1MBB);
     BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
     BB->addSuccessor(loop1MBB);
     BB->addSuccessor(exitMBB);
 
-    BB = midMBB;
-    BuildMI(BB, dl, TII->get(StoreMnemonic))
-        .addReg(dest)
-        .addReg(ptrA)
-        .addReg(ptrB);
-    BB->addSuccessor(exitMBB);
-
     //  exitMBB:
     //   ...
     BB = exitMBB;
   } else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
              MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
     // We must use 64-bit registers for addresses when targeting 64-bit,
     // since we're actually doing arithmetic on them.  Other registers
     // can be 32-bit.
     bool is64bit = Subtarget.isPPC64();
     bool isLittleEndian = Subtarget.isLittleEndian();
     bool is8bit = MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
 
     Register dest = MI.getOperand(0).getReg();
     Register ptrA = MI.getOperand(1).getReg();
     Register ptrB = MI.getOperand(2).getReg();
     Register oldval = MI.getOperand(3).getReg();
     Register newval = MI.getOperand(4).getReg();
     DebugLoc dl = MI.getDebugLoc();
 
     MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
     MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
-    MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
     MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
     F->insert(It, loop1MBB);
     F->insert(It, loop2MBB);
-    F->insert(It, midMBB);
     F->insert(It, exitMBB);
     exitMBB->splice(exitMBB->begin(), BB,
                     std::next(MachineBasicBlock::iterator(MI)), BB->end());
     exitMBB->transferSuccessorsAndUpdatePHIs(BB);
 
     MachineRegisterInfo &RegInfo = F->getRegInfo();
     const TargetRegisterClass *RC =
         is64bit ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
     Register Mask2Reg = RegInfo.createVirtualRegister(GPRC);
     Register Mask3Reg = RegInfo.createVirtualRegister(GPRC);
     Register Tmp2Reg = RegInfo.createVirtualRegister(GPRC);
     Register Tmp4Reg = RegInfo.createVirtualRegister(GPRC);
     Register TmpDestReg = RegInfo.createVirtualRegister(GPRC);
     Register Ptr1Reg;
     Register TmpReg = RegInfo.createVirtualRegister(GPRC);
     Register ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
+    Register CrReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
     //  thisMBB:
     //   ...
     //   fallthrough --> loopMBB
     BB->addSuccessor(loop1MBB);
 
     // The 4-byte load must be aligned, while a char or short may be
     // anywhere in the word.  Hence all this nasty bookkeeping code.
     //   add ptr1, ptrA, ptrB [copy if ptrA==0]
     //   rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
     //   xori shift, shift1, 24 [16]
     //   rlwinm ptr, ptr1, 0, 0, 29
     //   slw newval2, newval, shift
     //   slw oldval2, oldval,shift
     //   li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
     //   slw mask, mask2, shift
     //   and newval3, newval2, mask
     //   and oldval3, oldval2, mask
     // loop1MBB:
     //   lwarx tmpDest, ptr
     //   and tmp, tmpDest, mask
     //   cmpw tmp, oldval3
-    //   bne- midMBB
+    //   bne- exitBB
     // loop2MBB:
     //   andc tmp2, tmpDest, mask
     //   or tmp4, tmp2, newval3
     //   stwcx. tmp4, ptr
     //   bne- loop1MBB
     //   b exitBB
-    // midMBB:
-    //   stwcx. tmpDest, ptr
     // exitBB:
     //   srw dest, tmpDest, shift
     if (ptrA != ZeroReg) {
       Ptr1Reg = RegInfo.createVirtualRegister(RC);
       BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
           .addReg(ptrA)
           .addReg(ptrB);
     } else {
else if (MI.getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
 
     BB = loop1MBB;
     BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
         .addReg(ZeroReg)
         .addReg(PtrReg);
     BuildMI(BB, dl, TII->get(PPC::AND), TmpReg)
         .addReg(TmpDestReg)
         .addReg(MaskReg);
-    BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
+    BuildMI(BB, dl, TII->get(PPC::CMPW), CrReg)
         .addReg(TmpReg)
         .addReg(OldVal3Reg);
     BuildMI(BB, dl, TII->get(PPC::BCC))
         .addImm(PPC::PRED_NE)
-        .addReg(PPC::CR0)
-        .addMBB(midMBB);
+        .addReg(CrReg)
+        .addMBB(exitMBB);
     BB->addSuccessor(loop2MBB);
-    BB->addSuccessor(midMBB);
+    BB->addSuccessor(exitMBB);
 
     BB = loop2MBB;
     BuildMI(BB, dl, TII->get(PPC::ANDC), Tmp2Reg)
         .addReg(TmpDestReg)
         .addReg(MaskReg);
     BuildMI(BB, dl, TII->get(PPC::OR), Tmp4Reg)
         .addReg(Tmp2Reg)
         .addReg(NewVal3Reg);
     BuildMI(BB, dl, TII->get(PPC::STWCX))
         .addReg(Tmp4Reg)
         .addReg(ZeroReg)
         .addReg(PtrReg);
     BuildMI(BB, dl, TII->get(PPC::BCC))
         .addImm(PPC::PRED_NE)
         .addReg(PPC::CR0)
         .addMBB(loop1MBB);
     BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
     BB->addSuccessor(loop1MBB);
     BB->addSuccessor(exitMBB);
 
-    BB = midMBB;
-    BuildMI(BB, dl, TII->get(PPC::STWCX))
-        .addReg(TmpDestReg)
-        .addReg(ZeroReg)
-        .addReg(PtrReg);
-    BB->addSuccessor(exitMBB);
-
     //  exitMBB:
     //   ...
     BB = exitMBB;
     BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest)
         .addReg(TmpReg)
         .addReg(ShiftReg);
   } else if (MI.getOpcode() == PPC::FADDrtz) {
     // This pseudo performs an FADD with rounding mode temporarily forced
if (LSBase->getOpcode() == ISD::STORE) {
     return DAG.getMemIntrinsicNode(
         PPCISD::STORE_VEC_BE, dl, DAG.getVTList(MVT::Other), StoreOps,
         LSBase->getMemoryVT(), LSBase->getMemOperand());
   }
 
   llvm_unreachable("Expected a load or store node here");
 }
 
+static bool isStoreConditional(SDValue Intrin, unsigned &StoreWidth) {
+  unsigned IntrinsicID =
+      cast<ConstantSDNode>(Intrin.getOperand(1))->getZExtValue();
+  if (IntrinsicID == Intrinsic::ppc_stdcx)
+    StoreWidth = 8;
+  else if (IntrinsicID == Intrinsic::ppc_stwcx)
+    StoreWidth = 4;
+  else if (IntrinsicID == Intrinsic::ppc_sthcx)
+    StoreWidth = 2;
+  else if (IntrinsicID == Intrinsic::ppc_stbcx)
+    StoreWidth = 1;
+  else
+    return false;
+  return true;
+}
+
 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
                                              DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
   SDLoc dl(N);
   switch (N->getOpcode()) {
   default: break;
   case ISD::ADD:
     return combineADD(N, DCI);
if (!N->getOperand(0).hasOneUse() &&
         return SDValue(VCMPrecNode, 0);
     }
     break;
   case ISD::BR_CC: {
     // If this is a branch on an altivec predicate comparison, lower this so
     // that we don't have to do a MFOCRF: instead, branch directly on CR6.  This
     // lowering is done pre-legalize, because the legalizer lowers the predicate
     // compare down to code that is difficult to reassemble.
+    // This code also handles branches that depend on the result of a store
+    // conditional.
     ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
     SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
 
     int CompareOpc;
     bool isDot;
 
-    if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
-        isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
-        getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
-      assert(isDot && "Can't compare against a vector result!");
+    if (!isa<ConstantSDNode>(RHS) || (CC != ISD::SETEQ && CC != ISD::SETNE))
+      break;
 
+    // Since we are doing this pre-legalize, the RHS can be a constant of
+    // arbitrary bitwidth which may cause issues when trying to get the value
+    // from the underlying APInt.
+    auto RHSAPInt = cast<ConstantSDNode>(RHS)->getAPIntValue();
+    if (!RHSAPInt.isIntN(64))
+      break;
+
+    unsigned Val = RHSAPInt.getZExtValue();
+    auto isImpossibleCompare = [&]() {
       // If this is a comparison against something other than 0/1, then we know
       // that the condition is never/always true.
-      unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
       if (Val != 0 && Val != 1) {
         if (CC == ISD::SETEQ)      // Cond never true, remove branch.
           return N->getOperand(0);
         // Always !=, turn it into an unconditional branch.
         return DAG.getNode(ISD::BR, dl, MVT::Other,
                            N->getOperand(0), N->getOperand(4));
       }
+      return SDValue();
+    };
+    // Combine branches fed by store conditional instructions (st[bhwd]cx).
+    unsigned StoreWidth = 0;
+    if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
+        isStoreConditional(LHS, StoreWidth)) {
+      if (SDValue Impossible = isImpossibleCompare())
+        return Impossible;
+      PPC::Predicate CompOpc;
+      // eq 0 => ne
+      // ne 0 => eq
+      // eq 1 => eq
+      // ne 1 => ne
+      if (Val == 0)
+        CompOpc = CC == ISD::SETEQ ? PPC::PRED_NE : PPC::PRED_EQ;
+      else
+        CompOpc = CC == ISD::SETEQ ? PPC::PRED_EQ : PPC::PRED_NE;
 
-      bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
+      SDValue Ops[] = {LHS.getOperand(0), LHS.getOperand(2), LHS.getOperand(3),
+                       DAG.getConstant(StoreWidth, dl, MVT::i32)};
+      auto *MemNode = cast<MemSDNode>(LHS);
+      SDValue ConstSt = DAG.getMemIntrinsicNode(
+          PPCISD::STORE_COND, dl,
+          DAG.getVTList(MVT::i32, MVT::Other, MVT::Glue), Ops,
+          MemNode->getMemoryVT(), MemNode->getMemOperand());
+
+      SDValue InChain;
+      // Unchain the branch from the original store conditional.
+      if (N->getOperand(0) == LHS.getValue(1))
+        InChain = LHS.getOperand(0);
+      else if (N->getOperand(0).getOpcode() == ISD::TokenFactor) {
+        SmallVector<SDValue, 4> InChains;
+        SDValue InTF = N->getOperand(0);
+        for (int i = 0, e = InTF.getNumOperands(); i < e; i++)
+          if (InTF.getOperand(i) != LHS.getValue(1))
+            InChains.push_back(InTF.getOperand(i));
+        InChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, InChains);
+      }
+
+      return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, InChain,
+                         DAG.getConstant(CompOpc, dl, MVT::i32),
+                         DAG.getRegister(PPC::CR0, MVT::i32), N->getOperand(4),
+                         ConstSt.getValue(2));
+    }
 
+    if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
+        getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
+      assert(isDot && "Can't compare against a vector result!");
+
+      if (SDValue Impossible = isImpossibleCompare())
+        return Impossible;
+
+      bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
       // Create the PPCISD altivec 'dot' comparison node.
       SDValue Ops[] = {
         LHS.getOperand(2),  // LHS of compare
         LHS.getOperand(3),  // RHS of compare
         DAG.getConstant(CompareOpc, dl, MVT::i32)
       };
       EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
       SDValue CompNode = DAG.getNode(PPCISD::VCMP_rec, dl, VTs, Ops);
case Intrinsic::ppc_vsx_stxvll: {
     Info.memVT = VT;
     Info.ptrVal = I.getArgOperand(1);
     Info.offset = -VT.getStoreSize()+1;
     Info.size = 2*VT.getStoreSize()-1;
     Info.align = Align(1);
     Info.flags = MachineMemOperand::MOStore;
     return true;
   }
+  case Intrinsic::ppc_stdcx:
+  case Intrinsic::ppc_stwcx:
+  case Intrinsic::ppc_sthcx:
+  case Intrinsic::ppc_stbcx: {
+    EVT VT;
+    auto Alignment = Align(8);
+    switch (Intrinsic) {
+    case Intrinsic::ppc_stdcx:
+      VT = MVT::i64;
+      break;
+    case Intrinsic::ppc_stwcx:
+      VT = MVT::i32;
+      Alignment = Align(4);
+      break;
+    case Intrinsic::ppc_sthcx:
+      VT = MVT::i16;
+      Alignment = Align(2);
+      break;
+    case Intrinsic::ppc_stbcx:
+      VT = MVT::i8;
+      Alignment = Align(1);
+      break;
+    }
+    Info.opc = ISD::INTRINSIC_W_CHAIN;
+    Info.memVT = VT;
+    Info.ptrVal = I.getArgOperand(0);
+    Info.offset = 0;
+    Info.align = Alignment;
+    Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
+    return true;
+  }
   default:
     break;
   }
 
   return false;
 }
 
 /// It returns EVT::Other if the type should be determined using generic

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

def SLBIEG : XForm_26<31, 466, (outs), (ins gprc:$RS, gprc:$RB),
                       "slbieg $RS, $RB", IIC_SprSLBIEG, []>;
 // SLB Synchronize
 def SLBSYNC : XForm_0<31, 338, (outs), (ins), "slbsync", IIC_SprSLBSYNC, []>;
 
 } // IsISA3_0
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
           (STDCX g8rc:$A, ForceXForm:$dst)>;
+def : Pat<(PPCStoreCond ForceXForm:$dst, g8rc:$A, 8),
+          (STDCX g8rc:$A, ForceXForm:$dst)>;
 
 def : Pat<(i64 (int_ppc_mfspr timm:$SPR)),
           (MFSPR8 $SPR)>;
 def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT),
           (MTSPR8 $SPR, $RT)>;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def SDT_PPCFtsqrt : SDTypeProfile<1, 1, [
   SDTCisVT<0, i32>]>;
 
 def SDT_PPClbrx : SDTypeProfile<1, 2, [
   SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
 ]>;
 def SDT_PPCstbrx : SDTypeProfile<0, 3, [
   SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>
 ]>;
+def SDT_StoreCond : SDTypeProfile<0, 3, [
+  SDTCisPtrTy<0>, SDTCisInt<1>, SDTCisPtrTy<2>
+]>;
 
 def SDT_PPCTC_ret : SDTypeProfile<0, 2, [
   SDTCisPtrTy<0>, SDTCisVT<1, i32>
 ]>;
 
 def tocentry32 : Operand<iPTR> {
   let MIOperandInfo = (ops i32imm:$imm);
 }
SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3,
          [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
 def PPCatomicCmpSwap_16 :
   SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3,
          [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
 def PPClbrx       : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
                            [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def PPCstbrx      : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
                            [SDNPHasChain, SDNPMayStore]>;
+def PPCStoreCond  : SDNode<"PPCISD::STORE_COND", SDT_StoreCond,
+                           [SDNPHasChain, SDNPMayStore,
+                            SDNPMemOperand, SDNPOutGlue]>;
 
 // Instructions to set/unset CR bit 6 for SVR4 vararg calls
 def PPCcr6set   : SDNode<"PPCISD::CR6SET", SDTNone,
                          [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone,
                          [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 
 // Instructions to support dynamic alloca.

 
 // Now both high word and low word are reversed, next
 // swap the high word and low word.
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
           (STWCX gprc:$A, ForceXForm:$dst)>;
+def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 4),
+          (STWCX gprc:$A, ForceXForm:$dst)>;
 def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A),
           (STBCX gprc:$A, ForceXForm:$dst)>;
+def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 1),
+          (STBCX gprc:$A, ForceXForm:$dst)>;
 
 def : Pat<(int_ppc_fcfid f64:$A),
         (XSCVSXDDP $A)>;
 def : Pat<(int_ppc_fcfud f64:$A),
         (XSCVUXDDP $A)>;
 def : Pat<(int_ppc_fctid f64:$A),
         (FCTID $A)>;
 def : Pat<(int_ppc_fctidz f64:$A),
def : Pat<(i32 (int_ppc_mfspr timm:$SPR)),
           (MFSPR $SPR)>;
 def : Pat<(int_ppc_mtspr timm:$SPR, gprc:$RT),
           (MTSPR $SPR, $RT)>;
 def : Pat<(int_ppc_mtmsr gprc:$RS),
           (MTMSR $RS, 0)>;
 
 let Predicates = [IsISA2_07] in {
   def : Pat<(int_ppc_sthcx ForceXForm:$dst, gprc:$A),
             (STHCX gprc:$A, ForceXForm:$dst)>;
+  def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 2),
+            (STHCX gprc:$A, ForceXForm:$dst)>;
 }
 def : Pat<(int_ppc_dcbtstt ForceXForm:$dst),
           (DCBTST 16, ForceXForm:$dst)>;
 def : Pat<(int_ppc_dcbtt ForceXForm:$dst),
           (DCBT 16, ForceXForm:$dst)>;
 
 def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT),
           (STFIWX f64:$XT, ForceXForm:$dst)>;

llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

bool PPCTTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst,
   case Intrinsic::ppc_vsx_stxvl:
   case Intrinsic::ppc_vsx_stxvll:
   case Intrinsic::ppc_vsx_stxvp: {
     Info.PtrVal = Inst->getArgOperand(1);
     Info.ReadMem = false;
     Info.WriteMem = true;
     return true;
   }
+  case Intrinsic::ppc_stbcx:
+  case Intrinsic::ppc_sthcx:
+  case Intrinsic::ppc_stdcx:
+  case Intrinsic::ppc_stwcx: {
+    Info.PtrVal = Inst->getArgOperand(0);
+    Info.ReadMem = false;
+    Info.WriteMem = true;
+    return true;
+  }
   default:
     break;
   }
 
   return false;
 }
 
 bool PPCTTIImpl::hasActiveVectorLength(unsigned Opcode, Type *DataType,

llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll

 
 define signext i32 @main() nounwind {
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0: # %L.entry
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    std 0, 16(1)
 ; CHECK-NEXT:    stdu 1, -48(1)
 ; CHECK-NEXT:    li 3, -32477
-; CHECK-NEXT:    li 6, 234
-; CHECK-NEXT:    addi 5, 1, 46
+; CHECK-NEXT:    li 4, 234
+; CHECK-NEXT:    addi 6, 1, 46
 ; CHECK-NEXT:    sth 3, 46(1)
 ; CHECK-NEXT:    lis 3, 0
-; CHECK-NEXT:    ori 4, 3, 33059
+; CHECK-NEXT:    ori 3, 3, 33059
 ; CHECK-NEXT:    sync
 ; CHECK-NEXT:  .LBB0_1: # %L.entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lharx 3, 0, 5
-; CHECK-NEXT:    cmpw 4, 3
+; CHECK-NEXT:    lharx 5, 0, 6
+; CHECK-NEXT:    cmpw 5, 3
 ; CHECK-NEXT:    bne 0, .LBB0_3
 ; CHECK-NEXT:  # %bb.2: # %L.entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    sthcx. 6, 0, 5
+; CHECK-NEXT:    sthcx. 4, 0, 6
 ; CHECK-NEXT:    bne 0, .LBB0_1
-; CHECK-NEXT:    b .LBB0_4
 ; CHECK-NEXT:  .LBB0_3: # %L.entry
-; CHECK-NEXT:    sthcx. 3, 0, 5
-; CHECK-NEXT:  .LBB0_4: # %L.entry
-; CHECK-NEXT:    cmplwi 3, 33059
+; CHECK-NEXT:    cmplwi 5, 33059
 ; CHECK-NEXT:    lwsync
-; CHECK-NEXT:    bne 0, .LBB0_7
-; CHECK-NEXT:  # %bb.5: # %L.B0000
+; CHECK-NEXT:    bne 0, .LBB0_6
+; CHECK-NEXT:  # %bb.4: # %L.B0000
 ; CHECK-NEXT:    lhz 3, 46(1)
 ; CHECK-NEXT:    cmplwi 3, 234
-; CHECK-NEXT:    bne 0, .LBB0_8
-; CHECK-NEXT:  # %bb.6: # %L.B0001
+; CHECK-NEXT:    bne 0, .LBB0_7
+; CHECK-NEXT:  # %bb.5: # %L.B0001
 ; CHECK-NEXT:    addis 3, 2, .Lstr.2@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .Lstr.2@toc@l
 ; CHECK-NEXT:    bl puts
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    li 3, 0
-; CHECK-NEXT:    b .LBB0_10
-; CHECK-NEXT:  .LBB0_7: # %L.B0003
+; CHECK-NEXT:    b .LBB0_9
+; CHECK-NEXT:  .LBB0_6: # %L.B0003
 ; CHECK-NEXT:    addis 3, 2, .Lstr@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .Lstr@toc@l
-; CHECK-NEXT:    b .LBB0_9
-; CHECK-NEXT:  .LBB0_8: # %L.B0005
+; CHECK-NEXT:    b .LBB0_8
+; CHECK-NEXT:  .LBB0_7: # %L.B0005
 ; CHECK-NEXT:    addis 3, 2, .Lstr.1@toc@ha
 ; CHECK-NEXT:    addi 3, 3, .Lstr.1@toc@l
-; CHECK-NEXT:  .LBB0_9: # %L.B0003
+; CHECK-NEXT:  .LBB0_8: # %L.B0003
 ; CHECK-NEXT:    bl puts
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:  .LBB0_10: # %L.B0003
+; CHECK-NEXT:  .LBB0_9: # %L.B0003
 ; CHECK-NEXT:    addi 1, 1, 48
 ; CHECK-NEXT:    ld 0, 16(1)
 ; CHECK-NEXT:    mtlr 0
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-P7-LABEL: main:
 ; CHECK-P7:       # %bb.0: # %L.entry
 ; CHECK-P7-NEXT:    mflr 0
 ; CHECK-P7-NEXT:    std 0, 16(1)
 ; CHECK-P7-NEXT:    stdu 1, -48(1)
 ; CHECK-P7-NEXT:    li 3, -32477
 ; CHECK-P7-NEXT:    lis 5, 0
 ; CHECK-P7-NEXT:    addi 4, 1, 46
 ; CHECK-P7-NEXT:    li 7, 0
 ; CHECK-P7-NEXT:    sth 3, 46(1)
 ; CHECK-P7-NEXT:    li 6, 234
 ; CHECK-P7-NEXT:    ori 5, 5, 33059
 ; CHECK-P7-NEXT:    rlwinm 3, 4, 3, 27, 27
 ; CHECK-P7-NEXT:    ori 7, 7, 65535
 ; CHECK-P7-NEXT:    sync
 ; CHECK-P7-NEXT:    slw 6, 6, 3
 ; CHECK-P7-NEXT:    slw 8, 5, 3
 ; CHECK-P7-NEXT:    slw 5, 7, 3
 ; CHECK-P7-NEXT:    rldicr 4, 4, 0, 61
-; CHECK-P7-NEXT:    and 7, 6, 5
-; CHECK-P7-NEXT:    and 8, 8, 5
+; CHECK-P7-NEXT:    and 6, 6, 5
+; CHECK-P7-NEXT:    and 7, 8, 5
 ; CHECK-P7-NEXT:  .LBB0_1: # %L.entry
 ; CHECK-P7-NEXT:    #
 ; CHECK-P7-NEXT:    lwarx 9, 0, 4
-; CHECK-P7-NEXT:    and 6, 9, 5
-; CHECK-P7-NEXT:    cmpw 6, 8
+; CHECK-P7-NEXT:    and 8, 9, 5
+; CHECK-P7-NEXT:    cmpw 8, 7
 ; CHECK-P7-NEXT:    bne 0, .LBB0_3
 ; CHECK-P7-NEXT:  # %bb.2: # %L.entry
 ; CHECK-P7-NEXT:    #
 ; CHECK-P7-NEXT:    andc 9, 9, 5
-; CHECK-P7-NEXT:    or 9, 9, 7
+; CHECK-P7-NEXT:    or 9, 9, 6
 ; CHECK-P7-NEXT:    stwcx. 9, 0, 4
 ; CHECK-P7-NEXT:    bne 0, .LBB0_1
-; CHECK-P7-NEXT:    b .LBB0_4
 ; CHECK-P7-NEXT:  .LBB0_3: # %L.entry
-; CHECK-P7-NEXT:    stwcx. 9, 0, 4
-; CHECK-P7-NEXT:  .LBB0_4: # %L.entry
-; CHECK-P7-NEXT:    srw 3, 6, 3
+; CHECK-P7-NEXT:    srw 3, 8, 3
 ; CHECK-P7-NEXT:    lwsync
 ; CHECK-P7-NEXT:    cmplwi 3, 33059
-; CHECK-P7-NEXT:    bne 0, .LBB0_7
-; CHECK-P7-NEXT:  # %bb.5: # %L.B0000
+; CHECK-P7-NEXT:    bne 0, .LBB0_6
+; CHECK-P7-NEXT:  # %bb.4: # %L.B0000
 ; CHECK-P7-NEXT:    lhz 3, 46(1)
 ; CHECK-P7-NEXT:    cmplwi 3, 234
-; CHECK-P7-NEXT:    bne 0, .LBB0_8
-; CHECK-P7-NEXT:  # %bb.6: # %L.B0001
+; CHECK-P7-NEXT:    bne 0, .LBB0_7
+; CHECK-P7-NEXT:  # %bb.5: # %L.B0001
 ; CHECK-P7-NEXT:    addis 3, 2, .Lstr.2@toc@ha
 ; CHECK-P7-NEXT:    addi 3, 3, .Lstr.2@toc@l
 ; CHECK-P7-NEXT:    bl puts
 ; CHECK-P7-NEXT:    nop
 ; CHECK-P7-NEXT:    li 3, 0
-; CHECK-P7-NEXT:    b .LBB0_10
-; CHECK-P7-NEXT:  .LBB0_7: # %L.B0003
+; CHECK-P7-NEXT:    b .LBB0_9
+; CHECK-P7-NEXT:  .LBB0_6: # %L.B0003
 ; CHECK-P7-NEXT:    addis 3, 2, .Lstr@toc@ha
 ; CHECK-P7-NEXT:    addi 3, 3, .Lstr@toc@l
-; CHECK-P7-NEXT:    b .LBB0_9
-; CHECK-P7-NEXT:  .LBB0_8: # %L.B0005
+; CHECK-P7-NEXT:    b .LBB0_8
+; CHECK-P7-NEXT:  .LBB0_7: # %L.B0005
 ; CHECK-P7-NEXT:    addis 3, 2, .Lstr.1@toc@ha
 ; CHECK-P7-NEXT:    addi 3, 3, .Lstr.1@toc@l
-; CHECK-P7-NEXT:  .LBB0_9: # %L.B0003
+; CHECK-P7-NEXT:  .LBB0_8: # %L.B0003
 ; CHECK-P7-NEXT:    bl puts
 ; CHECK-P7-NEXT:    nop
 ; CHECK-P7-NEXT:    li 3, 1
-; CHECK-P7-NEXT:  .LBB0_10: # %L.B0003
+; CHECK-P7-NEXT:  .LBB0_9: # %L.B0003
 ; CHECK-P7-NEXT:    addi 1, 1, 48
 ; CHECK-P7-NEXT:    ld 0, 16(1)
 ; CHECK-P7-NEXT:    mtlr 0
 ; CHECK-P7-NEXT:    blr
 L.entry:
   %value.addr = alloca i16, align 2
   store i16 -32477, i16* %value.addr, align 2
   %0 = cmpxchg i16* %value.addr, i16 -32477, i16 234 seq_cst seq_cst

llvm/test/CodeGen/PowerPC/all-atomics.ll

 ; CHECK-NEXT:    addi 6, 3, uc@toc@l
 ; CHECK-NEXT:    addi 0, 4, sc@toc@l
 ; CHECK-NEXT:    lbz 5, uc@toc@l(3)
 ; CHECK-NEXT:    lbz 8, sc@toc@l(4)
 ; CHECK-NEXT:    sync
 ; CHECK-NEXT:  .LBB3_1: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lbarx 7, 0, 0
-; CHECK-NEXT:    cmpw 5, 7
+; CHECK-NEXT:    cmpw 7, 5
 ; CHECK-NEXT:    bne 0, .LBB3_3
 ; CHECK-NEXT:  # %bb.2: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    stbcx. 8, 0, 0
 ; CHECK-NEXT:    bne 0, .LBB3_1
-; CHECK-NEXT:    b .LBB3_4
 ; CHECK-NEXT:  .LBB3_3: # %entry
-; CHECK-NEXT:    stbcx. 7, 0, 0
-; CHECK-NEXT:  .LBB3_4: # %entry
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    stb 7, sc@toc@l(4)
 ; CHECK-NEXT:    lbz 8, uc@toc@l(3)
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:  .LBB3_5: # %entry
+; CHECK-NEXT:  .LBB3_4: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lbarx 5, 0, 6
-; CHECK-NEXT:    cmpw 8, 5
-; CHECK-NEXT:    bne 0, .LBB3_7
-; CHECK-NEXT:  # %bb.6: # %entry
+; CHECK-NEXT:    cmpw 5, 8
+; CHECK-NEXT:    bne 0, .LBB3_6
+; CHECK-NEXT:  # %bb.5: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    stbcx. 7, 0, 6
-; CHECK-NEXT:    bne 0, .LBB3_5
-; CHECK-NEXT:    b .LBB3_8
-; CHECK-NEXT:  .LBB3_7: # %entry
-; CHECK-NEXT:    stbcx. 5, 0, 6
-; CHECK-NEXT:  .LBB3_8: # %entry
+; CHECK-NEXT:    bne 0, .LBB3_4
+; CHECK-NEXT:  .LBB3_6: # %entry
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    addis 7, 2, ss@toc@ha
 ; CHECK-NEXT:    stb 5, uc@toc@l(3)
 ; CHECK-NEXT:    lbz 8, sc@toc@l(4)
 ; CHECK-NEXT:    addi 12, 7, ss@toc@l
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:    extsb 9, 8
-; CHECK-NEXT:  .LBB3_9: # %entry
-; CHECK-NEXT:    #
-; CHECK-NEXT:    lharx 8, 0, 12
-; CHECK-NEXT:    cmpw 5, 8
-; CHECK-NEXT:    bne 0, .LBB3_11
-; CHECK-NEXT:  # %bb.10: # %entry
+; CHECK-NEXT:    extsb 8, 8
+; CHECK-NEXT:  .LBB3_7: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    sthcx. 9, 0, 12
+; CHECK-NEXT:    lharx 9, 0, 12
+; CHECK-NEXT:    cmpw 9, 5
 ; CHECK-NEXT:    bne 0, .LBB3_9
-; CHECK-NEXT:    b .LBB3_12
-; CHECK-NEXT:  .LBB3_11: # %entry
+; CHECK-NEXT:  # %bb.8: # %entry
+; CHECK-NEXT:    #
 ; CHECK-NEXT:    sthcx. 8, 0, 12
-; CHECK-NEXT:  .LBB3_12: # %entry
+; CHECK-NEXT:    bne 0, .LBB3_7
+; CHECK-NEXT:  .LBB3_9: # %entry
 ; CHECK-NEXT:    lwsync
-; CHECK-NEXT:    sth 8, ss@toc@l(7)
-; CHECK-NEXT:    addis 5, 2, us@toc@ha
+; CHECK-NEXT:    sth 9, ss@toc@l(7)
+; CHECK-NEXT:    addis 7, 2, us@toc@ha
 ; CHECK-NEXT:    lbz 8, sc@toc@l(4)
-; CHECK-NEXT:    lbz 7, uc@toc@l(3)
-; CHECK-NEXT:    addi 11, 5, us@toc@l
+; CHECK-NEXT:    lbz 5, uc@toc@l(3)
+; CHECK-NEXT:    addi 11, 7, us@toc@l
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:    extsb 9, 8
-; CHECK-NEXT:  .LBB3_13: # %entry
+; CHECK-NEXT:    extsb 8, 8
+; CHECK-NEXT:  .LBB3_10: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lharx 8, 0, 11
-; CHECK-NEXT:    cmpw 7, 8
-; CHECK-NEXT:    bne 0, .LBB3_15
-; CHECK-NEXT:  # %bb.14: # %entry
+; CHECK-NEXT:    lharx 9, 0, 11
+; CHECK-NEXT:    cmpw 9, 5
+; CHECK-NEXT:    bne 0, .LBB3_12
+; CHECK-NEXT:  # %bb.11: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    sthcx. 9, 0, 11
-; CHECK-NEXT:    bne 0, .LBB3_13
-; CHECK-NEXT:    b .LBB3_16
-; CHECK-NEXT:  .LBB3_15: # %entry
 ; CHECK-NEXT:    sthcx. 8, 0, 11
-; CHECK-NEXT:  .LBB3_16: # %entry
+; CHECK-NEXT:    bne 0, .LBB3_10
+; CHECK-NEXT:  .LBB3_12: # %entry
 ; CHECK-NEXT:    lwsync
-; CHECK-NEXT:    sth 8, us@toc@l(5)
-; CHECK-NEXT:    addis 5, 2, si@toc@ha
+; CHECK-NEXT:    sth 9, us@toc@l(7)
+; CHECK-NEXT:    addis 7, 2, si@toc@ha
 ; CHECK-NEXT:    lbz 8, sc@toc@l(4)
-; CHECK-NEXT:    lbz 7, uc@toc@l(3)
-; CHECK-NEXT:    addi 10, 5, si@toc@l
+; CHECK-NEXT:    lbz 5, uc@toc@l(3)
+; CHECK-NEXT:    addi 10, 7, si@toc@l
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:    extsb 9, 8
-; CHECK-NEXT:  .LBB3_17: # %entry
+; CHECK-NEXT:    extsb 8, 8
+; CHECK-NEXT:  .LBB3_13: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lwarx 8, 0, 10
-; CHECK-NEXT:    cmpw 7, 8
-; CHECK-NEXT:    bne 0, .LBB3_19
-; CHECK-NEXT:  # %bb.18: # %entry
+; CHECK-NEXT:    lwarx 9, 0, 10
+; CHECK-NEXT:    cmpw 9, 5
+; CHECK-NEXT:    bne 0, .LBB3_15
+; CHECK-NEXT:  # %bb.14: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    stwcx. 9, 0, 10
-; CHECK-NEXT:    bne 0, .LBB3_17
-; CHECK-NEXT:    b .LBB3_20
-; CHECK-NEXT:  .LBB3_19: # %entry
 ; CHECK-NEXT:    stwcx. 8, 0, 10
-; CHECK-NEXT:  .LBB3_20: # %entry
+; CHECK-NEXT:    bne 0, .LBB3_13
+; CHECK-NEXT:  .LBB3_15: # %entry
 ; CHECK-NEXT:    lwsync
-; CHECK-NEXT:    stw 8, si@toc@l(5)
+; CHECK-NEXT:    stw 9, si@toc@l(7)
 ; CHECK-NEXT:    addis 5, 2, ui@toc@ha
 ; CHECK-NEXT:    lbz 8, sc@toc@l(4)
 ; CHECK-NEXT:    lbz 7, uc@toc@l(3)
 ; CHECK-NEXT:    addi 9, 5, ui@toc@l
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:    extsb 30, 8
-; CHECK-NEXT:  .LBB3_21: # %entry
+; CHECK-NEXT:    extsb 8, 8
+; CHECK-NEXT:  .LBB3_16: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lwarx 8, 0, 9
-; CHECK-NEXT:    cmpw 7, 8
-; CHECK-NEXT:    bne 0, .LBB3_23
-; CHECK-NEXT:  # %bb.22: # %entry
+; CHECK-NEXT:    lwarx 30, 0, 9
+; CHECK-NEXT:    cmpw 30, 7
+; CHECK-NEXT:    bne 0, .LBB3_18
+; CHECK-NEXT:  # %bb.17: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    stwcx. 30, 0, 9
-; CHECK-NEXT:    bne 0, .LBB3_21
-; CHECK-NEXT:    b .LBB3_24
-; CHECK-NEXT:  .LBB3_23: # %entry
 ; CHECK-NEXT:    stwcx. 8, 0, 9
-; CHECK-NEXT:  .LBB3_24: # %entry
+; CHECK-NEXT:    bne 0, .LBB3_16
+; CHECK-NEXT:  .LBB3_18: # %entry
 ; CHECK-NEXT:    lwsync
-; CHECK-NEXT:    stw 8, ui@toc@l(5)
-; CHECK-NEXT:    addis 7, 2, sll@toc@ha
+; CHECK-NEXT:    stw 30, ui@toc@l(5)
+; CHECK-NEXT:    addis 30, 2, sll@toc@ha
 ; CHECK-NEXT:    lbz 8, sc@toc@l(4)
-; CHECK-NEXT:    lbz 30, uc@toc@l(3)
+; CHECK-NEXT:    lbz 7, uc@toc@l(3)
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:    extsb 28, 8
-; CHECK-NEXT:    addi 8, 7, sll@toc@l
-; CHECK-NEXT:  .LBB3_25: # %entry
+; CHECK-NEXT:    extsb 29, 8
+; CHECK-NEXT:    addi 8, 30, sll@toc@l
+; CHECK-NEXT:  .LBB3_19: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    ldarx 29, 0, 8
-; CHECK-NEXT:    cmpd 30, 29
-; CHECK-NEXT:    bne 0, .LBB3_27
-; CHECK-NEXT:  # %bb.26: # %entry
+; CHECK-NEXT:    ldarx 28, 0, 8
+; CHECK-NEXT:    cmpd 28, 7
+; CHECK-NEXT:    bne 0, .LBB3_21
+; CHECK-NEXT:  # %bb.20: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    stdcx. 28, 0, 8
-; CHECK-NEXT:    bne 0, .LBB3_25
-; CHECK-NEXT:    b .LBB3_28
-; CHECK-NEXT:  .LBB3_27: # %entry
 ; CHECK-NEXT:    stdcx. 29, 0, 8
-; CHECK-NEXT:  .LBB3_28: # %entry
+; CHECK-NEXT:    bne 0, .LBB3_19
+; CHECK-NEXT:  .LBB3_21: # %entry
 ; CHECK-NEXT:    lwsync
-; CHECK-NEXT:    std 29, sll@toc@l(7)
-; CHECK-NEXT:    addis 30, 2, ull@toc@ha
+; CHECK-NEXT:    std 28, sll@toc@l(30)
+; CHECK-NEXT:    addis 29, 2, ull@toc@ha
 ; CHECK-NEXT:    lbz 7, sc@toc@l(4)
-; CHECK-NEXT:    lbz 29, uc@toc@l(3)
+; CHECK-NEXT:    lbz 30, uc@toc@l(3)
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:    extsb 27, 7
-; CHECK-NEXT:    addi 7, 30, ull@toc@l
-; CHECK-NEXT:  .LBB3_29: # %entry
-; CHECK-NEXT:    #
-; CHECK-NEXT:    ldarx 28, 0, 7
-; CHECK-NEXT:    cmpd 29, 28
-; CHECK-NEXT:    bne 0, .LBB3_31
-; CHECK-NEXT:  # %bb.30: # %entry
+; CHECK-NEXT:    extsb 28, 7
+; CHECK-NEXT:    addi 7, 29, ull@toc@l
+; CHECK-NEXT:  .LBB3_22: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    ldarx 27, 0, 7
+; CHECK-NEXT:    cmpd 27, 30
+; CHECK-NEXT:    bne 0, .LBB3_24
+; CHECK-NEXT:  # %bb.23: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    stdcx. 27, 0, 7
-; CHECK-NEXT:    bne 0, .LBB3_29
-; CHECK-NEXT:    b .LBB3_32
-; CHECK-NEXT:  .LBB3_31: # %entry
 ; CHECK-NEXT:    stdcx. 28, 0, 7
-; CHECK-NEXT:  .LBB3_32: # %entry
+; CHECK-NEXT:    bne 0, .LBB3_22
+; CHECK-NEXT:  .LBB3_24: # %entry
 ; CHECK-NEXT:    lwsync
-; CHECK-NEXT:    std 28, ull@toc@l(30)
+; CHECK-NEXT:    std 27, ull@toc@l(29)
 ; CHECK-NEXT:    lbz 30, uc@toc@l(3)
-; CHECK-NEXT:    lbz 28, sc@toc@l(4)
+; CHECK-NEXT:    lbz 29, sc@toc@l(4)
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:  .LBB3_33: # %entry
+; CHECK-NEXT:  .LBB3_25: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lbarx 29, 0, 0
-; CHECK-NEXT:    cmpw 30, 29
-; CHECK-NEXT:    bne 0, .LBB3_35
-; CHECK-NEXT:  # %bb.34: # %entry
+; CHECK-NEXT:    lbarx 28, 0, 0
+; CHECK-NEXT:    cmpw 28, 30
+; CHECK-NEXT:    bne 0, .LBB3_27
+; CHECK-NEXT:  # %bb.26: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    stbcx. 28, 0, 0
-; CHECK-NEXT:    bne 0, .LBB3_33
-; CHECK-NEXT:    b .LBB3_36
-; CHECK-NEXT:  .LBB3_35: # %entry
 ; CHECK-NEXT:    stbcx. 29, 0, 0
-; CHECK-NEXT:  .LBB3_36: # %entry
-; CHECK-NEXT:    xor 0, 29, 30
+; CHECK-NEXT:    bne 0, .LBB3_25
+; CHECK-NEXT:  .LBB3_27: # %entry
+; CHECK-NEXT:    xor 0, 28, 30
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    cntlzw 0, 0
-; CHECK-NEXT:    lbz 29, sc@toc@l(4)
+; CHECK-NEXT:    lbz 30, sc@toc@l(4)
 ; CHECK-NEXT:    srwi 0, 0, 5
 ; CHECK-NEXT:    stw 0, ui@toc@l(5)
 ; CHECK-NEXT:    lbz 0, uc@toc@l(3)
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:  .LBB3_37: # %entry
+; CHECK-NEXT:  .LBB3_28: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lbarx 30, 0, 6
-; CHECK-NEXT:    cmpw 0, 30
-; CHECK-NEXT:    bne 0, .LBB3_39
-; CHECK-NEXT:  # %bb.38: # %entry
+; CHECK-NEXT:    lbarx 29, 0, 6
+; CHECK-NEXT:    cmpw 29, 0
+; CHECK-NEXT:    bne 0, .LBB3_30
+; CHECK-NEXT:  # %bb.29: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    stbcx. 29, 0, 6
-; CHECK-NEXT:    bne 0, .LBB3_37
-; CHECK-NEXT:    b .LBB3_40
-; CHECK-NEXT:  .LBB3_39: # %entry
 ; CHECK-NEXT:    stbcx. 30, 0, 6
-; CHECK-NEXT:  .LBB3_40: # %entry
-; CHECK-NEXT:    xor 6, 30, 0
+; CHECK-NEXT:    bne 0, .LBB3_28
+; CHECK-NEXT:  .LBB3_30: # %entry
+; CHECK-NEXT:    xor 6, 29, 0
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    cntlzw 6, 6
 ; CHECK-NEXT:    lbz 0, sc@toc@l(4)
 ; CHECK-NEXT:    srwi 6, 6, 5
 ; CHECK-NEXT:    stw 6, ui@toc@l(5)
 ; CHECK-NEXT:    lbz 6, uc@toc@l(3)
-; CHECK-NEXT:    extsb 30, 0
+; CHECK-NEXT:    extsb 0, 0
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:  .LBB3_41: # %entry
+; CHECK-NEXT:  .LBB3_31: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lharx 0, 0, 12
-; CHECK-NEXT:    cmpw 6, 0
-; CHECK-NEXT:    bne 0, .LBB3_43
-; CHECK-NEXT:  # %bb.42: # %entry
+; CHECK-NEXT:    lharx 30, 0, 12
+; CHECK-NEXT:    cmpw 30, 6
+; CHECK-NEXT:    bne 0, .LBB3_33
+; CHECK-NEXT:  # %bb.32: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    sthcx. 30, 0, 12
-; CHECK-NEXT:    bne 0, .LBB3_41
-; CHECK-NEXT:    b .LBB3_44
-; CHECK-NEXT:  .LBB3_43: # %entry
 ; CHECK-NEXT:    sthcx. 0, 0, 12
-; CHECK-NEXT:  .LBB3_44: # %entry
-; CHECK-NEXT:    xor 6, 0, 6
+; CHECK-NEXT:    bne 0, .LBB3_31
+; CHECK-NEXT:  .LBB3_33: # %entry
+; CHECK-NEXT:    xor 6, 30, 6
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    cntlzw 6, 6
 ; CHECK-NEXT:    lbz 12, sc@toc@l(4)
 ; CHECK-NEXT:    srwi 6, 6, 5
 ; CHECK-NEXT:    stw 6, ui@toc@l(5)
 ; CHECK-NEXT:    lbz 6, uc@toc@l(3)
-; CHECK-NEXT:    extsb 0, 12
+; CHECK-NEXT:    extsb 12, 12
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:  .LBB3_45: # %entry
+; CHECK-NEXT:  .LBB3_34: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lharx 12, 0, 11
-; CHECK-NEXT:    cmpw 6, 12
-; CHECK-NEXT:    bne 0, .LBB3_47
-; CHECK-NEXT:  # %bb.46: # %entry
+; CHECK-NEXT:    lharx 0, 0, 11
+; CHECK-NEXT:    cmpw 0, 6
+; CHECK-NEXT:    bne 0, .LBB3_36
+; CHECK-NEXT:  # %bb.35: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    sthcx. 0, 0, 11
-; CHECK-NEXT:    bne 0, .LBB3_45
-; CHECK-NEXT:    b .LBB3_48
-; CHECK-NEXT:  .LBB3_47: # %entry
 ; CHECK-NEXT:    sthcx. 12, 0, 11
-; CHECK-NEXT:  .LBB3_48: # %entry
-; CHECK-NEXT:    xor 6, 12, 6
+; CHECK-NEXT:    bne 0, .LBB3_34
+; CHECK-NEXT:  .LBB3_36: # %entry
+; CHECK-NEXT:    xor 6, 0, 6
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    cntlzw 6, 6
 ; CHECK-NEXT:    lbz 11, sc@toc@l(4)
 ; CHECK-NEXT:    srwi 6, 6, 5
 ; CHECK-NEXT:    stw 6, ui@toc@l(5)
 ; CHECK-NEXT:    lbz 6, uc@toc@l(3)
-; CHECK-NEXT:    extsb 12, 11
+; CHECK-NEXT:    extsb 11, 11
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:  .LBB3_49: # %entry
+; CHECK-NEXT:  .LBB3_37: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lwarx 11, 0, 10
-; CHECK-NEXT:    cmpw 6, 11
-; CHECK-NEXT:    bne 0, .LBB3_51
-; CHECK-NEXT:  # %bb.50: # %entry
+; CHECK-NEXT:    lwarx 12, 0, 10
+; CHECK-NEXT:    cmpw 12, 6
+; CHECK-NEXT:    bne 0, .LBB3_39
+; CHECK-NEXT:  # %bb.38: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    stwcx. 12, 0, 10
-; CHECK-NEXT:    bne 0, .LBB3_49
-; CHECK-NEXT:    b .LBB3_52
-; CHECK-NEXT:  .LBB3_51: # %entry
 ; CHECK-NEXT:    stwcx. 11, 0, 10
-; CHECK-NEXT:  .LBB3_52: # %entry
-; CHECK-NEXT:    xor 6, 11, 6
+; CHECK-NEXT:    bne 0, .LBB3_37
+; CHECK-NEXT:  .LBB3_39: # %entry
+; CHECK-NEXT:    xor 6, 12, 6
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    cntlzw 6, 6
 ; CHECK-NEXT:    lbz 10, sc@toc@l(4)
 ; CHECK-NEXT:    srwi 6, 6, 5
 ; CHECK-NEXT:    stw 6, ui@toc@l(5)
 ; CHECK-NEXT:    lbz 6, uc@toc@l(3)
-; CHECK-NEXT:    extsb 11, 10
+; CHECK-NEXT:    extsb 10, 10
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:  .LBB3_53: # %entry
+; CHECK-NEXT:  .LBB3_40: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lwarx 10, 0, 9
-; CHECK-NEXT:    cmpw 6, 10
-; CHECK-NEXT:    bne 0, .LBB3_55
-; CHECK-NEXT:  # %bb.54: # %entry
+; CHECK-NEXT:    lwarx 11, 0, 9
+; CHECK-NEXT:    cmpw 11, 6
+; CHECK-NEXT:    bne 0, .LBB3_42
+; CHECK-NEXT:  # %bb.41: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    stwcx. 11, 0, 9
-; CHECK-NEXT:    bne 0, .LBB3_53
-; CHECK-NEXT:    b .LBB3_56
-; CHECK-NEXT:  .LBB3_55: # %entry
 ; CHECK-NEXT:    stwcx. 10, 0, 9
-; CHECK-NEXT:  .LBB3_56: # %entry
-; CHECK-NEXT:    xor 6, 10, 6
+; CHECK-NEXT:    bne 0, .LBB3_40
+; CHECK-NEXT:  .LBB3_42: # %entry
+; CHECK-NEXT:    xor 6, 11, 6
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    cntlzw 6, 6
 ; CHECK-NEXT:    lbz 9, sc@toc@l(4)
 ; CHECK-NEXT:    srwi 6, 6, 5
 ; CHECK-NEXT:    stw 6, ui@toc@l(5)
 ; CHECK-NEXT:    lbz 6, uc@toc@l(3)
-; CHECK-NEXT:    extsb 10, 9
+; CHECK-NEXT:    extsb 9, 9
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:  .LBB3_57: # %entry
+; CHECK-NEXT:  .LBB3_43: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    ldarx 9, 0, 8
-; CHECK-NEXT:    cmpd 6, 9
-; CHECK-NEXT:    bne 0, .LBB3_59
-; CHECK-NEXT:  # %bb.58: # %entry
+; CHECK-NEXT:    ldarx 10, 0, 8
+; CHECK-NEXT:    cmpd 10, 6
+; CHECK-NEXT:    bne 0, .LBB3_45
+; CHECK-NEXT:  # %bb.44: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    stdcx. 10, 0, 8
-; CHECK-NEXT:    bne 0, .LBB3_57
-; CHECK-NEXT:    b .LBB3_60
-; CHECK-NEXT:  .LBB3_59: # %entry
 ; CHECK-NEXT:    stdcx. 9, 0, 8
-; CHECK-NEXT:  .LBB3_60: # %entry
-; CHECK-NEXT:    xor 6, 9, 6
+; CHECK-NEXT:    bne 0, .LBB3_43
+; CHECK-NEXT:  .LBB3_45: # %entry
+; CHECK-NEXT:    xor 6, 10, 6
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    cntlzd 6, 6
 ; CHECK-NEXT:    lbz 4, sc@toc@l(4)
 ; CHECK-NEXT:    lbz 3, uc@toc@l(3)
 ; CHECK-NEXT:    rldicl 6, 6, 58, 63
 ; CHECK-NEXT:    stw 6, ui@toc@l(5)
-; CHECK-NEXT:    extsb 6, 4
+; CHECK-NEXT:    extsb 4, 4
 ; CHECK-NEXT:    sync
-; CHECK-NEXT:  .LBB3_61: # %entry
+; CHECK-NEXT:  .LBB3_46: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    ldarx 4, 0, 7
-; CHECK-NEXT:    cmpd 3, 4
-; CHECK-NEXT:    bne 0, .LBB3_63
-; CHECK-NEXT:  # %bb.62: # %entry
+; CHECK-NEXT:    ldarx 6, 0, 7
+; CHECK-NEXT:    cmpd 6, 3
+; CHECK-NEXT:    bne 0, .LBB3_48
+; CHECK-NEXT:  # %bb.47: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    stdcx. 6, 0, 7
-; CHECK-NEXT:    bne 0, .LBB3_61
-; CHECK-NEXT:    b .LBB3_64
-; CHECK-NEXT:  .LBB3_63: # %entry
 ; CHECK-NEXT:    stdcx. 4, 0, 7
-; CHECK-NEXT:  .LBB3_64: # %entry
-; CHECK-NEXT:    xor 3, 4, 3
+; CHECK-NEXT:    bne 0, .LBB3_46
+; CHECK-NEXT:  .LBB3_48: # %entry
+; CHECK-NEXT:    xor 3, 6, 3
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    cntlzd 3, 3
 ; CHECK-NEXT:    ld 30, -16(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 29, -24(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 28, -32(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld 27, -40(1) # 8-byte Folded Reload
 ; CHECK-NEXT:    rldicl 3, 3, 58, 63
 ; CHECK-NEXT:    stw 3, ui@toc@l(5)

 ; AIX32-NEXT:    stw 19, 76(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    lbz 3, 0(28)
 ; AIX32-NEXT:    rlwinm 4, 28, 3, 27, 28
 ; AIX32-NEXT:    lbz 5, 0(29)
 ; AIX32-NEXT:    rlwinm 19, 28, 0, 0, 29
 ; AIX32-NEXT:    xori 23, 4, 24
 ; AIX32-NEXT:    li 4, 255
 ; AIX32-NEXT:    slw 6, 3, 23
-; AIX32-NEXT:    slw 7, 5, 23
+; AIX32-NEXT:    slw 5, 5, 23
 ; AIX32-NEXT:    slw 3, 4, 23
 ; AIX32-NEXT:    stw 20, 80(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 21, 84(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 22, 88(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 24, 96(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 25, 100(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 26, 104(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 27, 108(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 30, 120(1) # 4-byte Folded Spill
 ; AIX32-NEXT:    stw 31, 124(1) # 4-byte Folded Spill
-; AIX32-NEXT:    and 5, 6, 3
-; AIX32-NEXT:    and 6, 7, 3
+; AIX32-NEXT:    and 4, 6, 3
+; AIX32-NEXT:    and 5, 5, 3
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB3_1: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 7, 0, 19
-; AIX32-NEXT:    and 4, 7, 3
-; AIX32-NEXT:    cmpw 4, 6
+; AIX32-NEXT:    and 6, 7, 3
+; AIX32-NEXT:    cmpw 6, 5
 ; AIX32-NEXT:    bne 0, L..BB3_3
 ; AIX32-NEXT:  # %bb.2: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    andc 7, 7, 3
-; AIX32-NEXT:    or 7, 7, 5
+; AIX32-NEXT:    or 7, 7, 4
 ; AIX32-NEXT:    stwcx. 7, 0, 19
 ; AIX32-NEXT:    bne 0, L..BB3_1
-; AIX32-NEXT:    b L..BB3_4
 ; AIX32-NEXT:  L..BB3_3: # %entry
-; AIX32-NEXT:    stwcx. 7, 0, 19
-; AIX32-NEXT:  L..BB3_4: # %entry
-; AIX32-NEXT:    srw 3, 4, 23
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    rlwinm 4, 29, 3, 27, 28
+; AIX32-NEXT:    srw 3, 6, 23
 ; AIX32-NEXT:    lbz 5, 0(29)
 ; AIX32-NEXT:    xori 25, 4, 24
 ; AIX32-NEXT:    stb 3, 0(28)
 ; AIX32-NEXT:    slw 4, 3, 25
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    slw 6, 5, 25
 ; AIX32-NEXT:    slw 3, 3, 25
 ; AIX32-NEXT:    rlwinm 22, 29, 0, 0, 29
 ; AIX32-NEXT:    and 5, 4, 3
 ; AIX32-NEXT:    and 6, 6, 3
-; AIX32-NEXT:  L..BB3_5: # %entry
+; AIX32-NEXT:  L..BB3_4: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 7, 0, 22
 ; AIX32-NEXT:    and 4, 7, 3
 ; AIX32-NEXT:    cmpw 4, 6
-; AIX32-NEXT:    bne 0, L..BB3_7
-; AIX32-NEXT:  # %bb.6: # %entry
+; AIX32-NEXT:    bne 0, L..BB3_6
+; AIX32-NEXT:  # %bb.5: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    andc 7, 7, 3
 ; AIX32-NEXT:    or 7, 7, 5
 ; AIX32-NEXT:    stwcx. 7, 0, 22
-; AIX32-NEXT:    bne 0, L..BB3_5
-; AIX32-NEXT:    b L..BB3_8
-; AIX32-NEXT:  L..BB3_7: # %entry
-; AIX32-NEXT:    stwcx. 7, 0, 22
-; AIX32-NEXT:  L..BB3_8: # %entry
+; AIX32-NEXT:    bne 0, L..BB3_4
+; AIX32-NEXT:  L..BB3_6: # %entry
 ; AIX32-NEXT:    lwz 3, L..C2(2) # @ss
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 7, 0
 ; AIX32-NEXT:    srw 4, 4, 25
 ; AIX32-NEXT:    lbz 5, 0(28)
 ; AIX32-NEXT:    stb 4, 0(29)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    rlwinm 6, 3, 3, 27, 27
 ; AIX32-NEXT:    extsb 5, 5
 ; AIX32-NEXT:    xori 24, 6, 16
 ; AIX32-NEXT:    ori 6, 7, 65535
 ; AIX32-NEXT:    slw 5, 5, 24
 ; AIX32-NEXT:    slw 7, 4, 24
 ; AIX32-NEXT:    slw 4, 6, 24
 ; AIX32-NEXT:    rlwinm 20, 3, 0, 0, 29
 ; AIX32-NEXT:    and 6, 5, 4
 ; AIX32-NEXT:    and 7, 7, 4
-; AIX32-NEXT:  L..BB3_9: # %entry
+; AIX32-NEXT:  L..BB3_7: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 8, 0, 20
 ; AIX32-NEXT:    and 5, 8, 4
 ; AIX32-NEXT:    cmpw 5, 7
-; AIX32-NEXT:    bne 0, L..BB3_11
-; AIX32-NEXT:  # %bb.10: # %entry
+; AIX32-NEXT:    bne 0, L..BB3_9
+; AIX32-NEXT:  # %bb.8: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    andc 8, 8, 4
 ; AIX32-NEXT:    or 8, 8, 6
 ; AIX32-NEXT:    stwcx. 8, 0, 20
-; AIX32-NEXT:    bne 0, L..BB3_9
-; AIX32-NEXT:    b L..BB3_12
-; AIX32-NEXT:  L..BB3_11: # %entry
-; AIX32-NEXT:    stwcx. 8, 0, 20
-; AIX32-NEXT:  L..BB3_12: # %entry
+; AIX32-NEXT:    bne 0, L..BB3_7
+; AIX32-NEXT:  L..BB3_9: # %entry
 ; AIX32-NEXT:    lwz 4, L..C3(2) # @us
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    srw 5, 5, 24
 ; AIX32-NEXT:    lbz 6, 0(28)
 ; AIX32-NEXT:    sth 5, 0(3)
 ; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    lbz 7, 0(29)
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    rlwinm 3, 4, 3, 27, 27
 ; AIX32-NEXT:    extsb 6, 6
 ; AIX32-NEXT:    xori 21, 3, 16
 ; AIX32-NEXT:    ori 3, 5, 65535
-; AIX32-NEXT:    slw 6, 6, 21
+; AIX32-NEXT:    slw 5, 6, 21
 ; AIX32-NEXT:    slw 7, 7, 21
-; AIX32-NEXT:    slw 5, 3, 21
+; AIX32-NEXT:    slw 3, 3, 21
 ; AIX32-NEXT:    rlwinm 18, 4, 0, 0, 29
-; AIX32-NEXT:    and 6, 6, 5
-; AIX32-NEXT:    and 7, 7, 5
-; AIX32-NEXT:  L..BB3_13: # %entry
+; AIX32-NEXT:    and 6, 5, 3
+; AIX32-NEXT:    and 7, 7, 3
+; AIX32-NEXT:  L..BB3_10: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 8, 0, 18
-; AIX32-NEXT:    and 3, 8, 5
-; AIX32-NEXT:    cmpw 3, 7
-; AIX32-NEXT:    bne 0, L..BB3_15
-; AIX32-NEXT:  # %bb.14: # %entry
+; AIX32-NEXT:    and 5, 8, 3
+; AIX32-NEXT:    cmpw 5, 7
+; AIX32-NEXT:    bne 0, L..BB3_12
+; AIX32-NEXT:  # %bb.11: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    andc 8, 8, 5
+; AIX32-NEXT:    andc 8, 8, 3
 ; AIX32-NEXT:    or 8, 8, 6
 ; AIX32-NEXT:    stwcx. 8, 0, 18
-; AIX32-NEXT:    bne 0, L..BB3_13
-; AIX32-NEXT:    b L..BB3_16
-; AIX32-NEXT:  L..BB3_15: # %entry
-; AIX32-NEXT:    stwcx. 8, 0, 18
-; AIX32-NEXT:  L..BB3_16: # %entry
+; AIX32-NEXT:    bne 0, L..BB3_10
+; AIX32-NEXT:  L..BB3_12: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    srw 3, 3, 21
+; AIX32-NEXT:    srw 3, 5, 21
 ; AIX32-NEXT:    lwz 17, L..C4(2) # @si
 ; AIX32-NEXT:    lbz 5, 0(28)
 ; AIX32-NEXT:    sth 3, 0(4)
 ; AIX32-NEXT:    lbz 3, 0(29)
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    extsb 5, 5
-; AIX32-NEXT:  L..BB3_17: # %entry
+; AIX32-NEXT:    extsb 4, 5
+; AIX32-NEXT:  L..BB3_13: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 17
-; AIX32-NEXT:    cmpw 3, 4
-; AIX32-NEXT:    bne 0, L..BB3_19
-; AIX32-NEXT:  # %bb.18: # %entry
+; AIX32-NEXT:    lwarx 5, 0, 17
+; AIX32-NEXT:    cmpw 5, 3
+; AIX32-NEXT:    bne 0, L..BB3_15
+; AIX32-NEXT:  # %bb.14: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    stwcx. 5, 0, 17
-; AIX32-NEXT:    bne 0, L..BB3_17
-; AIX32-NEXT:    b L..BB3_20
-; AIX32-NEXT:  L..BB3_19: # %entry
 ; AIX32-NEXT:    stwcx. 4, 0, 17
-; AIX32-NEXT:  L..BB3_20: # %entry
+; AIX32-NEXT:    bne 0, L..BB3_13
+; AIX32-NEXT:  L..BB3_15: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 4, 0(17)
 ; AIX32-NEXT:    lwz 27, L..C5(2) # @ui
+; AIX32-NEXT:    stw 5, 0(17)
 ; AIX32-NEXT:    lbz 4, 0(28)
 ; AIX32-NEXT:    lbz 3, 0(29)
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    extsb 5, 4
-; AIX32-NEXT:  L..BB3_21: # %entry
+; AIX32-NEXT:    extsb 4, 4
+; AIX32-NEXT:  L..BB3_16: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 4, 0, 27
-; AIX32-NEXT:    cmpw 3, 4
-; AIX32-NEXT:    bne 0, L..BB3_23
-; AIX32-NEXT:  # %bb.22: # %entry
+; AIX32-NEXT:    lwarx 5, 0, 27
+; AIX32-NEXT:    cmpw 5, 3
+; AIX32-NEXT:    bne 0, L..BB3_18
+; AIX32-NEXT:  # %bb.17: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    stwcx. 5, 0, 27
-; AIX32-NEXT:    bne 0, L..BB3_21
-; AIX32-NEXT:    b L..BB3_24
-; AIX32-NEXT:  L..BB3_23: # %entry
 ; AIX32-NEXT:    stwcx. 4, 0, 27
-; AIX32-NEXT:  L..BB3_24: # %entry
+; AIX32-NEXT:    bne 0, L..BB3_16
+; AIX32-NEXT:  L..BB3_18: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    stw 4, 0(27)
 ; AIX32-NEXT:    lwz 31, L..C6(2) # @sll
+; AIX32-NEXT:    stw 5, 0(27)
 ; AIX32-NEXT:    li 26, 0
 ; AIX32-NEXT:    li 7, 5
 ; AIX32-NEXT:    lbz 4, 0(28)
 ; AIX32-NEXT:    lbz 3, 0(29)
 ; AIX32-NEXT:    li 8, 5
 ; AIX32-NEXT:    stw 26, 56(1)
 ; AIX32-NEXT:    extsb 6, 4
 ; AIX32-NEXT:    stw 3, 60(1)

 ; AIX32-NEXT:    lwz 3, 60(1)
 ; AIX32-NEXT:    lwz 5, 56(1)
 ; AIX32-NEXT:    lbz 6, 0(28)
 ; AIX32-NEXT:    lbz 4, 0(29)
 ; AIX32-NEXT:    stw 3, 4(30)
 ; AIX32-NEXT:    li 3, 255
 ; AIX32-NEXT:    stw 5, 0(30)
 ; AIX32-NEXT:    slw 5, 6, 23
-; AIX32-NEXT:    slw 7, 4, 23
+; AIX32-NEXT:    slw 6, 4, 23
 ; AIX32-NEXT:    slw 3, 3, 23
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    and 6, 5, 3
-; AIX32-NEXT:    and 7, 7, 3
-; AIX32-NEXT:  L..BB3_25: # %entry
+; AIX32-NEXT:    and 5, 5, 3
+; AIX32-NEXT:    and 6, 6, 3
+; AIX32-NEXT:  L..BB3_19: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 8, 0, 19
-; AIX32-NEXT:    and 5, 8, 3
-; AIX32-NEXT:    cmpw 5, 7
-; AIX32-NEXT:    bne 0, L..BB3_27
-; AIX32-NEXT:  # %bb.26: # %entry
+; AIX32-NEXT:    and 7, 8, 3
+; AIX32-NEXT:    cmpw 7, 6
+; AIX32-NEXT:    bne 0, L..BB3_21
+; AIX32-NEXT:  # %bb.20: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    andc 8, 8, 3
-; AIX32-NEXT:    or 8, 8, 6
-; AIX32-NEXT:    stwcx. 8, 0, 19
-; AIX32-NEXT:    bne 0, L..BB3_25
-; AIX32-NEXT:    b L..BB3_28
-; AIX32-NEXT:  L..BB3_27: # %entry
+; AIX32-NEXT:    or 8, 8, 5
 ; AIX32-NEXT:    stwcx. 8, 0, 19
-; AIX32-NEXT:  L..BB3_28: # %entry
-; AIX32-NEXT:    srw 5, 5, 23
+; AIX32-NEXT:    bne 0, L..BB3_19
+; AIX32-NEXT:  L..BB3_21: # %entry
+; AIX32-NEXT:    srw 5, 7, 23
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    li 3, 1
 ; AIX32-NEXT:    li 7, 255
 ; AIX32-NEXT:    cmpw 5, 4
 ; AIX32-NEXT:    lbz 5, 0(28)
 ; AIX32-NEXT:    lbz 4, 0(29)
 ; AIX32-NEXT:    iseleq 6, 3, 26
 ; AIX32-NEXT:    stw 6, 0(27)
 ; AIX32-NEXT:    slw 5, 5, 25
 ; AIX32-NEXT:    slw 8, 4, 25
 ; AIX32-NEXT:    slw 6, 7, 25
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    and 7, 5, 6
 ; AIX32-NEXT:    and 8, 8, 6
-; AIX32-NEXT:  L..BB3_29: # %entry
+; AIX32-NEXT:  L..BB3_22: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 9, 0, 22
 ; AIX32-NEXT:    and 5, 9, 6
 ; AIX32-NEXT:    cmpw 5, 8
-; AIX32-NEXT:    bne 0, L..BB3_31
-; AIX32-NEXT:  # %bb.30: # %entry
+; AIX32-NEXT:    bne 0, L..BB3_24
+; AIX32-NEXT:  # %bb.23: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    andc 9, 9, 6
 ; AIX32-NEXT:    or 9, 9, 7
 ; AIX32-NEXT:    stwcx. 9, 0, 22
-; AIX32-NEXT:    bne 0, L..BB3_29
-; AIX32-NEXT:    b L..BB3_32
-; AIX32-NEXT:  L..BB3_31: # %entry
-; AIX32-NEXT:    stwcx. 9, 0, 22
-; AIX32-NEXT:  L..BB3_32: # %entry
+; AIX32-NEXT:    bne 0, L..BB3_22
+; AIX32-NEXT:  L..BB3_24: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    srw 5, 5, 25
 ; AIX32-NEXT:    lbz 6, 0(28)
 ; AIX32-NEXT:    cmpw 5, 4
 ; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    lbz 4, 0(29)
 ; AIX32-NEXT:    iseleq 7, 3, 26
 ; AIX32-NEXT:    ori 5, 5, 65535
 ; AIX32-NEXT:    extsb 6, 6
 ; AIX32-NEXT:    stw 7, 0(27)
 ; AIX32-NEXT:    slw 7, 6, 24
 ; AIX32-NEXT:    slw 8, 4, 24
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    slw 6, 5, 24
 ; AIX32-NEXT:    and 7, 7, 6
 ; AIX32-NEXT:    and 8, 8, 6
-; AIX32-NEXT:  L..BB3_33: # %entry
+; AIX32-NEXT:  L..BB3_25: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 9, 0, 20
 ; AIX32-NEXT:    and 5, 9, 6
 ; AIX32-NEXT:    cmpw 5, 8
-; AIX32-NEXT:    bne 0, L..BB3_35
-; AIX32-NEXT:  # %bb.34: # %entry
+; AIX32-NEXT:    bne 0, L..BB3_27
+; AIX32-NEXT:  # %bb.26: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    andc 9, 9, 6
 ; AIX32-NEXT:    or 9, 9, 7
 ; AIX32-NEXT:    stwcx. 9, 0, 20
-; AIX32-NEXT:    bne 0, L..BB3_33
-; AIX32-NEXT:    b L..BB3_36
-; AIX32-NEXT:  L..BB3_35: # %entry
-; AIX32-NEXT:    stwcx. 9, 0, 20
-; AIX32-NEXT:  L..BB3_36: # %entry
+; AIX32-NEXT:    bne 0, L..BB3_25
+; AIX32-NEXT:  L..BB3_27: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    srw 5, 5, 24
 ; AIX32-NEXT:    lbz 6, 0(28)
 ; AIX32-NEXT:    cmpw 5, 4
 ; AIX32-NEXT:    li 5, 0
 ; AIX32-NEXT:    lbz 4, 0(29)
 ; AIX32-NEXT:    iseleq 7, 3, 26
 ; AIX32-NEXT:    ori 5, 5, 65535
 ; AIX32-NEXT:    extsb 6, 6
 ; AIX32-NEXT:    stw 7, 0(27)
-; AIX32-NEXT:    slw 7, 6, 21
-; AIX32-NEXT:    slw 8, 4, 21
+; AIX32-NEXT:    slw 6, 6, 21
+; AIX32-NEXT:    slw 7, 4, 21
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:    slw 6, 5, 21
-; AIX32-NEXT:    and 7, 7, 6
-; AIX32-NEXT:    and 8, 8, 6
-; AIX32-NEXT:  L..BB3_37: # %entry
+; AIX32-NEXT:    slw 5, 5, 21
+; AIX32-NEXT:    and 6, 6, 5
+; AIX32-NEXT:    and 7, 7, 5
+; AIX32-NEXT:  L..BB3_28: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 9, 0, 18
-; AIX32-NEXT:    and 5, 9, 6
-; AIX32-NEXT:    cmpw 5, 8
-; AIX32-NEXT:    bne 0, L..BB3_39
-; AIX32-NEXT:  # %bb.38: # %entry
+; AIX32-NEXT:    and 8, 9, 5
+; AIX32-NEXT:    cmpw 8, 7
+; AIX32-NEXT:    bne 0, L..BB3_30
+; AIX32-NEXT:  # %bb.29: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    andc 9, 9, 6
-; AIX32-NEXT:    or 9, 9, 7
-; AIX32-NEXT:    stwcx. 9, 0, 18
-; AIX32-NEXT:    bne 0, L..BB3_37
-; AIX32-NEXT:    b L..BB3_40
-; AIX32-NEXT:  L..BB3_39: # %entry
+; AIX32-NEXT:    andc 9, 9, 5
+; AIX32-NEXT:    or 9, 9, 6
 ; AIX32-NEXT:    stwcx. 9, 0, 18
-; AIX32-NEXT:  L..BB3_40: # %entry
-; AIX32-NEXT:    srw 5, 5, 21
+; AIX32-NEXT:    bne 0, L..BB3_28
+; AIX32-NEXT:  L..BB3_30: # %entry
+; AIX32-NEXT:    srw 5, 8, 21
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    cmpw 5, 4
 ; AIX32-NEXT:    lbz 5, 0(28)
 ; AIX32-NEXT:    iseleq 4, 3, 26
 ; AIX32-NEXT:    stw 4, 0(27)
 ; AIX32-NEXT:    lbz 4, 0(29)
-; AIX32-NEXT:    extsb 6, 5
+; AIX32-NEXT:    extsb 5, 5
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:  L..BB3_41: # %entry
+; AIX32-NEXT:  L..BB3_31: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 5, 0, 17
-; AIX32-NEXT:    cmpw 4, 5
-; AIX32-NEXT:    bne 0, L..BB3_43
-; AIX32-NEXT:  # %bb.42: # %entry
+; AIX32-NEXT:    lwarx 6, 0, 17
+; AIX32-NEXT:    cmpw 1, 6, 4
+; AIX32-NEXT:    bne 1, L..BB3_33
+; AIX32-NEXT:  # %bb.32: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    stwcx. 6, 0, 17
-; AIX32-NEXT:    bne 0, L..BB3_41
-; AIX32-NEXT:    b L..BB3_44
-; AIX32-NEXT:  L..BB3_43: # %entry
 ; AIX32-NEXT:    stwcx. 5, 0, 17
-; AIX32-NEXT:  L..BB3_44: # %entry
-; AIX32-NEXT:    cmpw 5, 4
+; AIX32-NEXT:    bne 0, L..BB3_31
+; AIX32-NEXT:  L..BB3_33: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    iseleq 4, 3, 26
+; AIX32-NEXT:    isel 4, 3, 26, 6
 ; AIX32-NEXT:    lbz 5, 0(28)
 ; AIX32-NEXT:    stw 4, 0(27)
 ; AIX32-NEXT:    lbz 4, 0(29)
-; AIX32-NEXT:    extsb 6, 5
 ; AIX32-NEXT:    sync
-; AIX32-NEXT:  L..BB3_45: # %entry
+; AIX32-NEXT:    extsb 5, 5
+; AIX32-NEXT:  L..BB3_34: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    lwarx 5, 0, 27
-; AIX32-NEXT:    cmpw 4, 5
-; AIX32-NEXT:    bne 0, L..BB3_47
-; AIX32-NEXT:  # %bb.46: # %entry
+; AIX32-NEXT:    lwarx 6, 0, 27
+; AIX32-NEXT:    cmpw 1, 6, 4
+; AIX32-NEXT:    bne 1, L..BB3_36
+; AIX32-NEXT:  # %bb.35: # %entry
 ; AIX32-NEXT:    #
-; AIX32-NEXT:    stwcx. 6, 0, 27
-; AIX32-NEXT:    bne 0, L..BB3_45
-; AIX32-NEXT:    b L..BB3_48
-; AIX32-NEXT:  L..BB3_47: # %entry
 ; AIX32-NEXT:    stwcx. 5, 0, 27
-; AIX32-NEXT:  L..BB3_48: # %entry
+; AIX32-NEXT:    bne 0, L..BB3_34
+; AIX32-NEXT:  L..BB3_36: # %entry
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    cmpw 5, 4
+; AIX32-NEXT:    isel 3, 3, 26, 6
 ; AIX32-NEXT:    li 7, 5
 ; AIX32-NEXT:    li 8, 5
 ; AIX32-NEXT:    lbz 4, 0(28)
-; AIX32-NEXT:    iseleq 3, 3, 26
 ; AIX32-NEXT:    lbz 9, 0(29)
 ; AIX32-NEXT:    stw 3, 0(27)
 ; AIX32-NEXT:    mr 3, 31
 ; AIX32-NEXT:    extsb 6, 4
 ; AIX32-NEXT:    addi 4, 1, 56
 ; AIX32-NEXT:    srawi 5, 6, 31
 ; AIX32-NEXT:    stw 9, 60(1)
 ; AIX32-NEXT:    stw 26, 56(1)

 ; CHECK-LABEL: test_atomic:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addis 4, 2, ui@toc@ha
 ; CHECK-NEXT:    li 3, 5
 ; CHECK-NEXT:    addi 6, 4, ui@toc@l
 ; CHECK-NEXT:  .LBB5_1: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lwarx 5, 0, 6
-; CHECK-NEXT:    cmplw 3, 5
-; CHECK-NEXT:    bge 0, .LBB5_3
+; CHECK-NEXT:    cmplwi 5, 5
+; CHECK-NEXT:    blt 0, .LBB5_3
 ; CHECK-NEXT:  # %bb.2: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    stwcx. 3, 0, 6
 ; CHECK-NEXT:    bne 0, .LBB5_1
 ; CHECK-NEXT:  .LBB5_3: # %entry
 ; CHECK-NEXT:    stw 5, ui@toc@l(4)
 ; CHECK-NEXT:    addis 5, 2, si@toc@ha
 ; CHECK-NEXT:    addi 7, 5, si@toc@l
 ; CHECK-NEXT:    sync
 ; CHECK-NEXT:  .LBB5_4: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lwarx 8, 0, 7
-; CHECK-NEXT:    cmpw 3, 8
-; CHECK-NEXT:    bge 0, .LBB5_6
+; CHECK-NEXT:    cmpwi 8, 5
+; CHECK-NEXT:    blt 0, .LBB5_6
 ; CHECK-NEXT:  # %bb.5: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    stwcx. 3, 0, 7
 ; CHECK-NEXT:    bne 0, .LBB5_4
 ; CHECK-NEXT:  .LBB5_6: # %entry
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    stw 8, si@toc@l(5)
 ; CHECK-NEXT:  .LBB5_7: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lwarx 8, 0, 6
-; CHECK-NEXT:    cmplw 3, 8
-; CHECK-NEXT:    ble 0, .LBB5_9
+; CHECK-NEXT:    cmplwi 8, 5
+; CHECK-NEXT:    bgt 0, .LBB5_9
 ; CHECK-NEXT:  # %bb.8: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    stwcx. 3, 0, 6
 ; CHECK-NEXT:    bne 0, .LBB5_7
 ; CHECK-NEXT:  .LBB5_9: # %entry
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    stw 8, ui@toc@l(4)
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:  .LBB5_10: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lwarx 4, 0, 7
-; CHECK-NEXT:    cmpw 3, 4
-; CHECK-NEXT:    ble 0, .LBB5_12
+; CHECK-NEXT:    cmpwi 4, 5
+; CHECK-NEXT:    bgt 0, .LBB5_12
 ; CHECK-NEXT:  # %bb.11: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    stwcx. 3, 0, 7
 ; CHECK-NEXT:    bne 0, .LBB5_10
 ; CHECK-NEXT:  .LBB5_12: # %entry
 ; CHECK-NEXT:    stw 4, si@toc@l(5)
 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: test_atomic:
 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    lwz 4, L..C5(2) # @ui
 ; AIX32-NEXT:    li 3, 5
 ; AIX32-NEXT:  L..BB5_1: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 5, 0, 4
-; AIX32-NEXT:    cmplw 3, 5
-; AIX32-NEXT:    bge 0, L..BB5_3
+; AIX32-NEXT:    cmplwi 5, 5
+; AIX32-NEXT:    blt 0, L..BB5_3
 ; AIX32-NEXT:  # %bb.2: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    stwcx. 3, 0, 4
 ; AIX32-NEXT:    bne 0, L..BB5_1
 ; AIX32-NEXT:  L..BB5_3: # %entry
 ; AIX32-NEXT:    stw 5, 0(4)
 ; AIX32-NEXT:    lwz 5, L..C4(2) # @si
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB5_4: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 5
-; AIX32-NEXT:    cmpw 3, 6
-; AIX32-NEXT:    bge 0, L..BB5_6
+; AIX32-NEXT:    cmpwi 6, 5
+; AIX32-NEXT:    blt 0, L..BB5_6
 ; AIX32-NEXT:  # %bb.5: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    stwcx. 3, 0, 5
 ; AIX32-NEXT:    bne 0, L..BB5_4
 ; AIX32-NEXT:  L..BB5_6: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stw 6, 0(5)
 ; AIX32-NEXT:  L..BB5_7: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 6, 0, 4
-; AIX32-NEXT:    cmplw 3, 6
-; AIX32-NEXT:    ble 0, L..BB5_9
+; AIX32-NEXT:    cmplwi 6, 5
+; AIX32-NEXT:    bgt 0, L..BB5_9
 ; AIX32-NEXT:  # %bb.8: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    stwcx. 3, 0, 4
 ; AIX32-NEXT:    bne 0, L..BB5_7
 ; AIX32-NEXT:  L..BB5_9: # %entry
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:    stw 6, 0(4)
 ; AIX32-NEXT:    lwsync
 ; AIX32-NEXT:  L..BB5_10: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 4, 0, 5
-; AIX32-NEXT:    cmpw 3, 4
-; AIX32-NEXT:    ble 0, L..BB5_12
+; AIX32-NEXT:    cmpwi 4, 5
+; AIX32-NEXT:    bgt 0, L..BB5_12
 ; AIX32-NEXT:  # %bb.11: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    stwcx. 3, 0, 5
 ; AIX32-NEXT:    bne 0, L..BB5_10
 ; AIX32-NEXT:  L..BB5_12: # %entry
 ; AIX32-NEXT:    stw 4, 0(5)
 ; AIX32-NEXT:    blr
 entry:
   %0 = atomicrmw umin ptr @ui, i32 5 monotonic, align 4
   store i32 %0, ptr @ui, align 4
   %1 = atomicrmw min ptr @si, i32 5 seq_cst, align 4
   store i32 %1, ptr @si, align 4
   %2 = atomicrmw umax ptr @ui, i32 5 acquire, align 4
   store i32 %2, ptr @ui, align 4
   %3 = atomicrmw max ptr @si, i32 5 release, align 4
   store i32 %3, ptr @si, align 4
   ret void
 }
 
 define dso_local i64 @cmpswplp(ptr noundef %ptr, ptr nocapture noundef readnone %oldval, i64 noundef %newval) local_unnamed_addr #0 {
 ; CHECK-LABEL: cmpswplp:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addi 6, 5, 1
+; CHECK-NEXT:    addi 4, 5, 1
 ; CHECK-NEXT:  .LBB6_1: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    ldarx 4, 0, 3
-; CHECK-NEXT:    cmpd 5, 4
-; CHECK-NEXT:    bne 0, .LBB6_3
+; CHECK-NEXT:    ldarx 6, 0, 3
+; CHECK-NEXT:    cmpd 1, 6, 5
+; CHECK-NEXT:    bne 1, .LBB6_3
 ; CHECK-NEXT:  # %bb.2: # %entry
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    stdcx. 6, 0, 3
+; CHECK-NEXT:    stdcx. 4, 0, 3
 ; CHECK-NEXT:    bne 0, .LBB6_1
-; CHECK-NEXT:    b .LBB6_4
 ; CHECK-NEXT:  .LBB6_3: # %entry
-; CHECK-NEXT:    stdcx. 4, 0, 3
-; CHECK-NEXT:  .LBB6_4: # %entry
-; CHECK-NEXT:    cmpd 4, 5
 ; CHECK-NEXT:    li 3, 66
 ; CHECK-NEXT:    li 4, 55
-; CHECK-NEXT:    iseleq 3, 4, 3
+; CHECK-NEXT:    isel 3, 4, 3, 6
 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: cmpswplp:
 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    mflr 0
 ; AIX32-NEXT:    stw 0, 8(1)
 ; AIX32-NEXT:    stwu 1, -64(1)
 ; AIX32-NEXT:    addic 7, 6, 1

 
 define dso_local i64 @atommax8(ptr nocapture noundef %ptr, i64 noundef %val) local_unnamed_addr #0 {
 ; CHECK-LABEL: atommax8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sync
 ; CHECK-NEXT:  .LBB7_1: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    ldarx 5, 0, 3
-; CHECK-NEXT:    cmpd 4, 5
-; CHECK-NEXT:    ble 0, .LBB7_3
+; CHECK-NEXT:    cmpd 1, 5, 4
+; CHECK-NEXT:    bgt 1, .LBB7_3
 ; CHECK-NEXT:  # %bb.2: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    stdcx. 4, 0, 3
 ; CHECK-NEXT:    bne 0, .LBB7_1
 ; CHECK-NEXT:  .LBB7_3: # %entry
-; CHECK-NEXT:    cmpd 5, 4
 ; CHECK-NEXT:    li 3, 55
 ; CHECK-NEXT:    li 4, 66
 ; CHECK-NEXT:    lwsync
-; CHECK-NEXT:    iselgt 3, 4, 3
+; CHECK-NEXT:    isel 3, 4, 3, 5
 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: atommax8:
 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    mflr 0
 ; AIX32-NEXT:    stw 0, 8(1)
 ; AIX32-NEXT:    stwu 1, -80(1)
 ; AIX32-NEXT:    lwz 9, 4(3)

 
 define dso_local signext i32 @atommax4(ptr nocapture noundef %ptr, i32 noundef signext %val) local_unnamed_addr #0 {
 ; CHECK-LABEL: atommax4:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sync
 ; CHECK-NEXT:  .LBB8_1: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lwarx 5, 0, 3
-; CHECK-NEXT:    cmpw 4, 5
-; CHECK-NEXT:    ble 0, .LBB8_3
+; CHECK-NEXT:    cmpw 1, 5, 4
+; CHECK-NEXT:    bgt 1, .LBB8_3
 ; CHECK-NEXT:  # %bb.2: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    stwcx. 4, 0, 3
 ; CHECK-NEXT:    bne 0, .LBB8_1
 ; CHECK-NEXT:  .LBB8_3: # %entry
-; CHECK-NEXT:    cmpw 5, 4
 ; CHECK-NEXT:    li 3, 55
 ; CHECK-NEXT:    li 4, 66
 ; CHECK-NEXT:    lwsync
-; CHECK-NEXT:    iselgt 3, 4, 3
+; CHECK-NEXT:    isel 3, 4, 3, 5
 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: atommax4:
 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:  L..BB8_1: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 5, 0, 3
-; AIX32-NEXT:    cmpw 4, 5
-; AIX32-NEXT:    ble 0, L..BB8_3
+; AIX32-NEXT:    cmpw 1, 5, 4
+; AIX32-NEXT:    bgt 1, L..BB8_3
 ; AIX32-NEXT:  # %bb.2: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    stwcx. 4, 0, 3
 ; AIX32-NEXT:    bne 0, L..BB8_1
 ; AIX32-NEXT:  L..BB8_3: # %entry
-; AIX32-NEXT:    cmpw 5, 4
 ; AIX32-NEXT:    li 3, 55
 ; AIX32-NEXT:    li 4, 66
 ; AIX32-NEXT:    lwsync
-; AIX32-NEXT:    iselgt 3, 4, 3
+; AIX32-NEXT:    isel 3, 4, 3, 5
 ; AIX32-NEXT:    blr
 entry:
   %0 = atomicrmw max ptr %ptr, i32 %val seq_cst, align 4
   %cmp.not = icmp sgt i32 %0, %val
   %cond = select i1 %cmp.not, i32 66, i32 55
   ret i32 %cond
 }
 
 define dso_local signext i16 @atommax2(ptr nocapture noundef %ptr, i16 noundef signext %val) local_unnamed_addr #0 {
 ; CHECK-LABEL: atommax2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sync
 ; CHECK-NEXT:  .LBB9_1: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lharx 5, 0, 3
 ; CHECK-NEXT:    extsh 5, 5
-; CHECK-NEXT:    cmpw 4, 5
-; CHECK-NEXT:    ble 0, .LBB9_3
+; CHECK-NEXT:    cmpw 1, 5, 4
+; CHECK-NEXT:    bgt 1, .LBB9_3
 ; CHECK-NEXT:  # %bb.2: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    sthcx. 4, 0, 3
 ; CHECK-NEXT:    bne 0, .LBB9_1
 ; CHECK-NEXT:  .LBB9_3: # %entry
-; CHECK-NEXT:    cmpw 5, 4
 ; CHECK-NEXT:    li 3, 55
 ; CHECK-NEXT:    li 4, 66
 ; CHECK-NEXT:    lwsync
-; CHECK-NEXT:    iselgt 3, 4, 3
+; CHECK-NEXT:    isel 3, 4, 3, 5
 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: atommax2:
 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    li 6, 0
 ; AIX32-NEXT:    rlwinm 5, 3, 3, 27, 27
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    xori 5, 5, 16
 ; AIX32-NEXT:    ori 6, 6, 65535
 ; AIX32-NEXT:    slw 7, 4, 5
 ; AIX32-NEXT:    slw 6, 6, 5
 ; AIX32-NEXT:    rlwinm 3, 3, 0, 0, 29
 ; AIX32-NEXT:    and 7, 7, 6
 ; AIX32-NEXT:  L..BB9_1: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 8, 0, 3
 ; AIX32-NEXT:    and 9, 8, 6
 ; AIX32-NEXT:    srw 9, 9, 5
 ; AIX32-NEXT:    extsh 9, 9
-; AIX32-NEXT:    cmpw 4, 9
-; AIX32-NEXT:    ble 0, L..BB9_3
+; AIX32-NEXT:    cmpw 9, 4
+; AIX32-NEXT:    bgt 0, L..BB9_3
 ; AIX32-NEXT:  # %bb.2: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    andc 9, 8, 6
 ; AIX32-NEXT:    or 9, 7, 9
 ; AIX32-NEXT:    stwcx. 9, 0, 3
 ; AIX32-NEXT:    bne 0, L..BB9_1
 ; AIX32-NEXT:  L..BB9_3: # %entry
 ; AIX32-NEXT:    srw 3, 8, 5

 
 define dso_local zeroext i8 @atommax1(ptr nocapture noundef %ptr, i8 noundef zeroext %val) local_unnamed_addr #0 {
 ; CHECK-LABEL: atommax1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sync
 ; CHECK-NEXT:  .LBB10_1: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lbarx 5, 0, 3
-; CHECK-NEXT:    cmplw 4, 5
-; CHECK-NEXT:    ble 0, .LBB10_3
+; CHECK-NEXT:    cmplw 1, 5, 4
+; CHECK-NEXT:    bgt 1, .LBB10_3
 ; CHECK-NEXT:  # %bb.2: # %entry
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    stbcx. 4, 0, 3
 ; CHECK-NEXT:    bne 0, .LBB10_1
 ; CHECK-NEXT:  .LBB10_3: # %entry
-; CHECK-NEXT:    cmplw 5, 4
 ; CHECK-NEXT:    li 3, 55
 ; CHECK-NEXT:    li 4, 66
 ; CHECK-NEXT:    lwsync
-; CHECK-NEXT:    iselgt 3, 4, 3
+; CHECK-NEXT:    isel 3, 4, 3, 5
 ; CHECK-NEXT:    blr
 ;
 ; AIX32-LABEL: atommax1:
 ; AIX32:       # %bb.0: # %entry
 ; AIX32-NEXT:    rlwinm 5, 3, 3, 27, 28
 ; AIX32-NEXT:    li 7, 255
 ; AIX32-NEXT:    sync
 ; AIX32-NEXT:    xori 5, 5, 24
 ; AIX32-NEXT:    rlwinm 3, 3, 0, 0, 29
 ; AIX32-NEXT:    slw 6, 4, 5
 ; AIX32-NEXT:    slw 7, 7, 5
 ; AIX32-NEXT:    and 8, 6, 7
 ; AIX32-NEXT:  L..BB10_1: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    lwarx 9, 0, 3
 ; AIX32-NEXT:    and 10, 9, 7
-; AIX32-NEXT:    cmplw 6, 10
-; AIX32-NEXT:    ble 0, L..BB10_3
+; AIX32-NEXT:    cmplw 10, 6
+; AIX32-NEXT:    bgt 0, L..BB10_3
 ; AIX32-NEXT:  # %bb.2: # %entry
 ; AIX32-NEXT:    #
 ; AIX32-NEXT:    andc 10, 9, 7
 ; AIX32-NEXT:    or 10, 8, 10
 ; AIX32-NEXT:    stwcx. 10, 0, 3
 ; AIX32-NEXT:    bne 0, L..BB10_1
 ; AIX32-NEXT:  L..BB10_3: # %entry
 ; AIX32-NEXT:    srw 3, 9, 5

llvm/test/CodeGen/PowerPC/atomic-1.ll

 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu |  FileCheck %s
 
 define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind {
 ; CHECK-LABEL: exchange_and_add:
 ; CHECK: lwarx {{[0-9]+}}, 0, {{[0-9]+}}
   %tmp = atomicrmw add i32* %mem, i32 %val monotonic
 ; CHECK: stwcx. {{[0-9]+}}, 0, {{[0-9]+}}
   ret i32 %tmp
 }
 
 define i32 @exchange_and_cmp(i32* %mem) nounwind {
 ; CHECK-LABEL: exchange_and_cmp:
 ; CHECK: lwarx
   %tmppair = cmpxchg i32* %mem, i32 0, i32 1 monotonic monotonic
   %tmp = extractvalue { i32, i1 } %tmppair, 0
 ; CHECK: stwcx.
-; CHECK: stwcx.
   ret i32 %tmp
 }
 
 define i32 @exchange(i32* %mem, i32 %val) nounwind {
 ; CHECK-LABEL: exchange:
 ; CHECK: lwarx
   %tmp = atomicrmw xchg i32* %mem, i32 1 monotonic
 ; CHECK: stwcx.
   ret i32 %tmp
 }

llvm/test/CodeGen/PowerPC/atomic-2.ll

 }
 
 define i64 @exchange_and_cmp(i64* %mem) nounwind {
 ; CHECK-LABEL: exchange_and_cmp:
 ; CHECK: ldarx
   %tmppair = cmpxchg i64* %mem, i64 0, i64 1 monotonic monotonic
   %tmp = extractvalue { i64, i1 } %tmppair, 0
 ; CHECK: stdcx.
-; CHECK: stdcx.
   ret i64 %tmp
 }
 
 define i8 @exchange_and_cmp8(i8* %mem) nounwind {
 ; CHECK-LABEL: exchange_and_cmp8:
 ; CHECK-BE: xori
 ; CHECK-LE-NOT: xori
 ; CHECK-P8U: lbarx
   %tmppair = cmpxchg i8* %mem, i8 0, i8 1 monotonic monotonic
   %tmp = extractvalue { i8, i1 } %tmppair, 0
 ; CHECK-P8U: stbcx.
-; CHECK-P8U: stbcx.
   ret i8 %tmp
 }
 
 define i16 @exchange_and_cmp16(i16* %mem) nounwind {
 ; CHECK-LABEL: exchange_and_cmp16:
 ; CHECK-BE: xori
 ; CHECK-LE-NOT: xori
 ; CHECK-P8U: lharx
   %tmppair = cmpxchg i16* %mem, i16 0, i16 1 monotonic monotonic
   %tmp = extractvalue { i16, i1 } %tmppair, 0
 ; CHECK-P8U: sthcx.
-; CHECK-P8U: sthcx.
   ret i16 %tmp
 }
 
 define i64 @exchange(i64* %mem, i64 %val) nounwind {
 ; CHECK-LABEL: exchange:
 ; CHECK: ldarx
   %tmp = atomicrmw xchg i64* %mem, i64 1 monotonic
 ; CHECK: stdcx.

llvm/test/CodeGen/PowerPC/atomic-float.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
 ; RUN:   < %s | FileCheck --check-prefix=CHECK-64 %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown \
 ; RUN:   < %s | FileCheck --check-prefix=CHECK-32 %s
 
 define float @test_add(float* %ptr, float %incr) {
 ; CHECK-64-LABEL: test_add:
 ; CHECK-64:       # %bb.0: # %entry
 ; CHECK-64-NEXT:    sync
 ; CHECK-64-NEXT:    lfs 0, 0(3)
-; CHECK-64-NEXT:    b .LBB0_3
+; CHECK-64-NEXT:    b .LBB0_2
 ; CHECK-64-NEXT:  .LBB0_1: # %atomicrmw.start
 ; CHECK-64-NEXT:    #
-; CHECK-64-NEXT:    stwcx. 5, 0, 3
-; CHECK-64-NEXT:  .LBB0_2: # %atomicrmw.start
-; CHECK-64-NEXT:    #
-; CHECK-64-NEXT:    stw 5, -4(1)
-; CHECK-64-NEXT:    cmplw 5, 4
+; CHECK-64-NEXT:    stw 6, -4(1)
+; CHECK-64-NEXT:    cmplw 6, 4
 ; CHECK-64-NEXT:    lfs 0, -4(1)
-; CHECK-64-NEXT:    beq 0, .LBB0_6
-; CHECK-64-NEXT:  .LBB0_3: # %atomicrmw.start
+; CHECK-64-NEXT:    beq 0, .LBB0_5
+; CHECK-64-NEXT:  .LBB0_2: # %atomicrmw.start
 ; CHECK-64-NEXT:    # =>This Loop Header: Depth=1
-; CHECK-64-NEXT:    # Child Loop BB0_4 Depth 2
+; CHECK-64-NEXT:    # Child Loop BB0_3 Depth 2
 ; CHECK-64-NEXT:    fadds 2, 0, 1
 ; CHECK-64-NEXT:    stfs 2, -8(1)
 ; CHECK-64-NEXT:    stfs 0, -12(1)
-; CHECK-64-NEXT:    lwz 6, -8(1)
+; CHECK-64-NEXT:    lwz 5, -8(1)
 ; CHECK-64-NEXT:    lwz 4, -12(1)
-; CHECK-64-NEXT:  .LBB0_4: # %atomicrmw.start
-; CHECK-64-NEXT:    # Parent Loop BB0_3 Depth=1
+; CHECK-64-NEXT:  .LBB0_3: # %atomicrmw.start
+; CHECK-64-NEXT:    # Parent Loop BB0_2 Depth=1
 ; CHECK-64-NEXT:    # => This Inner Loop Header: Depth=2
-; CHECK-64-NEXT:    lwarx 5, 0, 3
-; CHECK-64-NEXT:    cmpw 4, 5
+; CHECK-64-NEXT:    lwarx 6, 0, 3
+; CHECK-64-NEXT:    cmpw 6, 4
 ; CHECK-64-NEXT:    bne 0, .LBB0_1
-; CHECK-64-NEXT:  # %bb.5: # %atomicrmw.start
+; CHECK-64-NEXT:  # %bb.4: # %atomicrmw.start
 ; CHECK-64-NEXT:    #
-; CHECK-64-NEXT:    stwcx. 6, 0, 3
-; CHECK-64-NEXT:    bne 0, .LBB0_4
-; CHECK-64-NEXT:    b .LBB0_2
-; CHECK-64-NEXT:  .LBB0_6: # %atomicrmw.end
+; CHECK-64-NEXT:    stwcx. 5, 0, 3
+; CHECK-64-NEXT:    bne 0, .LBB0_3
+; CHECK-64-NEXT:    b .LBB0_1
+; CHECK-64-NEXT:  .LBB0_5: # %atomicrmw.end
 ; CHECK-64-NEXT:    fmr 1, 0
 ; CHECK-64-NEXT:    lwsync
 ; CHECK-64-NEXT:    blr
 ;
 ; CHECK-32-LABEL: test_add:
 ; CHECK-32:       # %bb.0: # %entry
 ; CHECK-32-NEXT:    stwu 1, -32(1)
 ; CHECK-32-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-32-NEXT:    sync
 ; CHECK-32-NEXT:    lfs 0, 0(3)
-; CHECK-32-NEXT:    b .LBB0_3
+; CHECK-32-NEXT:    b .LBB0_2
 ; CHECK-32-NEXT:  .LBB0_1: # %atomicrmw.start
 ; CHECK-32-NEXT:    #
-; CHECK-32-NEXT:    stwcx. 5, 0, 3
-; CHECK-32-NEXT:  .LBB0_2: # %atomicrmw.start
-; CHECK-32-NEXT:    #
-; CHECK-32-NEXT:    stw 5, 28(1)
-; CHECK-32-NEXT:    cmplw 5, 4
+; CHECK-32-NEXT:    stw 6, 28(1)
+; CHECK-32-NEXT:    cmplw 6, 4
 ; CHECK-32-NEXT:    lfs 0, 28(1)
-; CHECK-32-NEXT:    beq 0, .LBB0_6
-; CHECK-32-NEXT:  .LBB0_3: # %atomicrmw.start
+; CHECK-32-NEXT:    beq 0, .LBB0_5
+; CHECK-32-NEXT:  .LBB0_2: # %atomicrmw.start
 ; CHECK-32-NEXT:    # =>This Loop Header: Depth=1
-; CHECK-32-NEXT:    # Child Loop BB0_4 Depth 2
+; CHECK-32-NEXT:    # Child Loop BB0_3 Depth 2
 ; CHECK-32-NEXT:    fadds 2, 0, 1
 ; CHECK-32-NEXT:    stfs 2, 24(1)
 ; CHECK-32-NEXT:    stfs 0, 20(1)
-; CHECK-32-NEXT:    lwz 6, 24(1)
+; CHECK-32-NEXT:    lwz 5, 24(1)
 ; CHECK-32-NEXT:    lwz 4, 20(1)
-; CHECK-32-NEXT:  .LBB0_4: # %atomicrmw.start
-; CHECK-32-NEXT:    # Parent Loop BB0_3 Depth=1
+; CHECK-32-NEXT:  .LBB0_3: # %atomicrmw.start
+; CHECK-32-NEXT:    # Parent Loop BB0_2 Depth=1
 ; CHECK-32-NEXT:    # => This Inner Loop Header: Depth=2
-; CHECK-32-NEXT:    lwarx 5, 0, 3
-; CHECK-32-NEXT:    cmpw 4, 5
+; CHECK-32-NEXT:    lwarx 6, 0, 3
+; CHECK-32-NEXT:    cmpw 6, 4
 ; CHECK-32-NEXT:    bne 0, .LBB0_1
-; CHECK-32-NEXT:  # %bb.5: # %atomicrmw.start
+; CHECK-32-NEXT:  # %bb.4: # %atomicrmw.start
 ; CHECK-32-NEXT:    #
-; CHECK-32-NEXT:    stwcx. 6, 0, 3
-; CHECK-32-NEXT:    bne 0, .LBB0_4
-; CHECK-32-NEXT:    b .LBB0_2
-; CHECK-32-NEXT:  .LBB0_6: # %atomicrmw.end
+; CHECK-32-NEXT:    stwcx. 5, 0, 3
+; CHECK-32-NEXT:    bne 0, .LBB0_3
+; CHECK-32-NEXT:    b .LBB0_1
+; CHECK-32-NEXT:  .LBB0_5: # %atomicrmw.end
 ; CHECK-32-NEXT:    fmr 1, 0
 ; CHECK-32-NEXT:    lwsync
 ; CHECK-32-NEXT:    addi 1, 1, 32
 ; CHECK-32-NEXT:    blr
 entry:
   %r = atomicrmw fadd float* %ptr, float %incr seq_cst
   ret float %r
 }

llvm/test/CodeGen/PowerPC/atomic-minmax.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define void @a32min(i32* nocapture dereferenceable(4) %minimum, i32 %val) #0 {
+; CHECK-LABEL: a32min:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .LBB0_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lwarx 5, 0, 3
+; CHECK-NEXT:    cmpw 5, 4
+; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stwcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB0_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw min i32* %minimum, i32 %val monotonic
   ret void
 
-; CHECK-LABEL: @a32min
-; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmpw 4, [[OLDV]]
-; CHECK: bgelr 0
-; CHECK: stwcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a32max(i32* nocapture dereferenceable(4) %minimum, i32 %val) #0 {
+; CHECK-LABEL: a32max:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .LBB1_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lwarx 5, 0, 3
+; CHECK-NEXT:    cmpw 5, 4
+; CHECK-NEXT:    bgtlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stwcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB1_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw max i32* %minimum, i32 %val monotonic
   ret void
 
-; CHECK-LABEL: @a32max
-; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmpw 4, [[OLDV]]
-; CHECK: blelr 0
-; CHECK: stwcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a32umin(i32* nocapture dereferenceable(4) %minimum, i32 %val) #0 {
+; CHECK-LABEL: a32umin:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .LBB2_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lwarx 5, 0, 3
+; CHECK-NEXT:    cmplw 5, 4
+; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stwcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB2_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw umin i32* %minimum, i32 %val monotonic
   ret void
 
-; CHECK-LABEL: @a32umin
-; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmplw 4, [[OLDV]]
-; CHECK: bgelr 0
-; CHECK: stwcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a32umax(i32* nocapture dereferenceable(4) %minimum, i32 %val) #0 {
+; CHECK-LABEL: a32umax:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .LBB3_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lwarx 5, 0, 3
+; CHECK-NEXT:    cmplw 5, 4
+; CHECK-NEXT:    bgtlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stwcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB3_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw umax i32* %minimum, i32 %val monotonic
   ret void
 
-; CHECK-LABEL: @a32umax
-; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmplw 4, [[OLDV]]
-; CHECK: blelr 0
-; CHECK: stwcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a16min(i16* nocapture dereferenceable(4) %minimum, i16 %val) #1 {
+; CHECK-LABEL: a16min:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    extsh 4, 4
+; CHECK-NEXT:  .LBB4_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lharx 5, 0, 3
+; CHECK-NEXT:    extsh 5, 5
+; CHECK-NEXT:    cmpw 5, 4
+; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    sthcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB4_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw min i16* %minimum, i16 %val monotonic
   ret void
 
-; CHECK-LABEL: @a16min
-; CHECK: lharx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmpw 4, [[OLDV]]
-; CHECK: bgelr 0
-; CHECK: sthcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a16max(i16* nocapture dereferenceable(4) %minimum, i16 %val) #1 {
+; CHECK-LABEL: a16max:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    extsh 4, 4
+; CHECK-NEXT:  .LBB5_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lharx 5, 0, 3
+; CHECK-NEXT:    extsh 5, 5
+; CHECK-NEXT:    cmpw 5, 4
+; CHECK-NEXT:    bgtlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    sthcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB5_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw max i16* %minimum, i16 %val monotonic
   ret void
 
-; CHECK-LABEL: @a16max
-; CHECK: lharx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmpw 4, [[OLDV]]
-; CHECK: blelr 0
-; CHECK: sthcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a16umin(i16* nocapture dereferenceable(4) %minimum, i16 %val) #1 {
+; CHECK-LABEL: a16umin:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .LBB6_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lharx 5, 0, 3
+; CHECK-NEXT:    cmplw 5, 4
+; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    sthcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB6_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw umin i16* %minimum, i16 %val monotonic
   ret void
 
-; CHECK-LABEL: @a16umin
-; CHECK: lharx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmplw 4, [[OLDV]]
-; CHECK: bgelr 0
-; CHECK: sthcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a16umax(i16* nocapture dereferenceable(4) %minimum, i16 %val) #1 {
+; CHECK-LABEL: a16umax:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .LBB7_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lharx 5, 0, 3
+; CHECK-NEXT:    cmplw 5, 4
+; CHECK-NEXT:    bgtlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    sthcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB7_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw umax i16* %minimum, i16 %val monotonic
   ret void
 
-; CHECK-LABEL: @a16umax
-; CHECK: lharx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmplw 4, [[OLDV]]
-; CHECK: blelr 0
-; CHECK: sthcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a8min(i8* nocapture dereferenceable(4) %minimum, i8 %val) #1 {
+; CHECK-LABEL: a8min:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    extsb 4, 4
+; CHECK-NEXT:  .LBB8_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lbarx 5, 0, 3
+; CHECK-NEXT:    extsb 5, 5
+; CHECK-NEXT:    cmpw 5, 4
+; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stbcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB8_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw min i8* %minimum, i8 %val monotonic
   ret void
 
-; CHECK-LABEL: @a8min
-; CHECK: lbarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmpw 4, [[OLDV]]
-; CHECK: bgelr 0
-; CHECK: stbcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a8max(i8* nocapture dereferenceable(4) %minimum, i8 %val) #1 {
+; CHECK-LABEL: a8max:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    extsb 4, 4
+; CHECK-NEXT:  .LBB9_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lbarx 5, 0, 3
+; CHECK-NEXT:    extsb 5, 5
+; CHECK-NEXT:    cmpw 5, 4
+; CHECK-NEXT:    bgtlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stbcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB9_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw max i8* %minimum, i8 %val monotonic
   ret void
 
-; CHECK-LABEL: @a8max
-; CHECK: lbarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmpw 4, [[OLDV]]
-; CHECK: blelr 0
-; CHECK: stbcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a8umin(i8* nocapture dereferenceable(4) %minimum, i8 %val) #1 {
+; CHECK-LABEL: a8umin:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .LBB10_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lbarx 5, 0, 3
+; CHECK-NEXT:    cmplw 5, 4
+; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stbcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB10_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw umin i8* %minimum, i8 %val monotonic
   ret void
 
-; CHECK-LABEL: @a8umin
-; CHECK: lbarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmplw 4, [[OLDV]]
-; CHECK: bgelr 0
-; CHECK: stbcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a8umax(i8* nocapture dereferenceable(4) %minimum, i8 %val) #1 {
+; CHECK-LABEL: a8umax:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .LBB11_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lbarx 5, 0, 3
+; CHECK-NEXT:    cmplw 5, 4
+; CHECK-NEXT:    bgtlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stbcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB11_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw umax i8* %minimum, i8 %val monotonic
   ret void
 
-; CHECK-LABEL: @a8umax
-; CHECK: lbarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmplw 4, [[OLDV]]
-; CHECK: blelr 0
-; CHECK: stbcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a64min(i64* nocapture dereferenceable(4) %minimum, i64 %val) #0 {
+; CHECK-LABEL: a64min:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .LBB12_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    ldarx 5, 0, 3
+; CHECK-NEXT:    cmpd 5, 4
+; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stdcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB12_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw min i64* %minimum, i64 %val monotonic
   ret void
 
-; CHECK-LABEL: @a64min
-; CHECK: ldarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmpd 4, [[OLDV]]
-; CHECK: bgelr 0
-; CHECK: stdcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a64max(i64* nocapture dereferenceable(4) %minimum, i64 %val) #0 {
+; CHECK-LABEL: a64max:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .LBB13_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    ldarx 5, 0, 3
+; CHECK-NEXT:    cmpd 5, 4
+; CHECK-NEXT:    bgtlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stdcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB13_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw max i64* %minimum, i64 %val monotonic
   ret void
 
-; CHECK-LABEL: @a64max
-; CHECK: ldarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmpd 4, [[OLDV]]
-; CHECK: blelr 0
-; CHECK: stdcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a64umin(i64* nocapture dereferenceable(4) %minimum, i64 %val) #0 {
+; CHECK-LABEL: a64umin:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .LBB14_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    ldarx 5, 0, 3
+; CHECK-NEXT:    cmpld 5, 4
+; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stdcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB14_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw umin i64* %minimum, i64 %val monotonic
   ret void
 
-; CHECK-LABEL: @a64umin
-; CHECK: ldarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmpld 4, [[OLDV]]
-; CHECK: bgelr 0
-; CHECK: stdcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @a64umax(i64* nocapture dereferenceable(4) %minimum, i64 %val) #0 {
+; CHECK-LABEL: a64umax:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:  .LBB15_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    ldarx 5, 0, 3
+; CHECK-NEXT:    cmpld 5, 4
+; CHECK-NEXT:    bgtlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    stdcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB15_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw umax i64* %minimum, i64 %val monotonic
   ret void
 
-; CHECK-LABEL: @a64umax
-; CHECK: ldarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: cmpld 4, [[OLDV]]
-; CHECK: blelr 0
-; CHECK: stdcx. 4, 0, 3
-; CHECK: bne 0,
-; CHECK: blr
 }
 
 define void @ae16min(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
+; CHECK-LABEL: ae16min:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 5, 0
+; CHECK-NEXT:    rlwinm 6, 3, 3, 27, 27
+; CHECK-NEXT:    ori 7, 5, 65535
+; CHECK-NEXT:    xori 5, 6, 16
+; CHECK-NEXT:    slw 8, 4, 5
+; CHECK-NEXT:    slw 6, 7, 5
+; CHECK-NEXT:    rldicr 3, 3, 0, 61
+; CHECK-NEXT:    and 7, 8, 6
+; CHECK-NEXT:  .LBB16_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lwarx 8, 0, 3
+; CHECK-NEXT:    and 9, 8, 6
+; CHECK-NEXT:    srw 9, 9, 5
+; CHECK-NEXT:    extsh 9, 9
+; CHECK-NEXT:    cmpw 9, 4
+; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    andc 8, 8, 6
+; CHECK-NEXT:    or 8, 7, 8
+; CHECK-NEXT:    stwcx. 8, 0, 3
+; CHECK-NEXT:    bne 0, .LBB16_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw min i16* %minimum, i16 %val monotonic
   ret void
 
-; CHECK-LABEL: @ae16min
-; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
-; CHECK-DAG: li [[M1:[0-9]+]], 0
-; CHECK-DAG: rldicr 3, 3, 0, 61
-; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
-; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
-; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
-; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
-; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
-; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
-; CHECK: extsh [[SESMOLDV:[0-9]+]], [[SMOLDV]]
-; CHECK: cmpw 4, [[SESMOLDV]]
-; CHECK: bgelr 0
-; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
-; CHECK: stwcx. [[NEWV]], 0, 3
-; CHECK: bne  0,
-; CHECK: blr
 }
 
 define void @ae16max(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
+; CHECK-LABEL: ae16max:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 5, 0
+; CHECK-NEXT:    rlwinm 6, 3, 3, 27, 27
+; CHECK-NEXT:    ori 7, 5, 65535
+; CHECK-NEXT:    xori 5, 6, 16
+; CHECK-NEXT:    slw 8, 4, 5
+; CHECK-NEXT:    slw 6, 7, 5
+; CHECK-NEXT:    rldicr 3, 3, 0, 61
+; CHECK-NEXT:    and 7, 8, 6
+; CHECK-NEXT:  .LBB17_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lwarx 8, 0, 3
+; CHECK-NEXT:    and 9, 8, 6
+; CHECK-NEXT:    srw 9, 9, 5
+; CHECK-NEXT:    extsh 9, 9
+; CHECK-NEXT:    cmpw 9, 4
+; CHECK-NEXT:    bgtlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    andc 8, 8, 6
+; CHECK-NEXT:    or 8, 7, 8
+; CHECK-NEXT:    stwcx. 8, 0, 3
+; CHECK-NEXT:    bne 0, .LBB17_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw max i16* %minimum, i16 %val monotonic
   ret void
 
-; CHECK-LABEL: @ae16max
-; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
-; CHECK-DAG: li [[M1:[0-9]+]], 0
-; CHECK-DAG: rldicr 3, 3, 0, 61
-; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
-; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
-; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
-; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
-; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
-; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
-; CHECK: extsh [[SESMOLDV:[0-9]+]], [[SMOLDV]]
-; CHECK: cmpw 4, [[SESMOLDV]]
-; CHECK: blelr 0
-; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
-; CHECK: stwcx. [[NEWV]], 0, 3
-; CHECK: bne  0,
-; CHECK: blr
 }
 
 define void @ae16umin(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
+; CHECK-LABEL: ae16umin:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 5, 0
+; CHECK-NEXT:    rlwinm 6, 3, 3, 27, 27
+; CHECK-NEXT:    ori 5, 5, 65535
+; CHECK-NEXT:    xori 6, 6, 16
+; CHECK-NEXT:    slw 4, 4, 6
+; CHECK-NEXT:    slw 5, 5, 6
+; CHECK-NEXT:    rldicr 3, 3, 0, 61
+; CHECK-NEXT:    and 6, 4, 5
+; CHECK-NEXT:  .LBB18_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lwarx 7, 0, 3
+; CHECK-NEXT:    and 8, 7, 5
+; CHECK-NEXT:    cmplw 8, 4
+; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    andc 7, 7, 5
+; CHECK-NEXT:    or 7, 6, 7
+; CHECK-NEXT:    stwcx. 7, 0, 3
+; CHECK-NEXT:    bne 0, .LBB18_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw umin i16* %minimum, i16 %val monotonic
   ret void
 
-; CHECK-LABEL: @ae16umin
-; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
-; CHECK-DAG: li [[M1:[0-9]+]], 0
-; CHECK-DAG: rldicr 3, 3, 0, 61
-; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
-; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
-; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
-; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
-; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
-; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: cmplw 4, [[MOLDV]]
-; CHECK: bgelr 0
-; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
-; CHECK: stwcx. [[NEWV]], 0, 3
-; CHECK: bne  0,
-; CHECK: blr
 }
 
 define void @ae16umax(i16* nocapture dereferenceable(4) %minimum, i16 %val) #0 {
+; CHECK-LABEL: ae16umax:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li 5, 0
+; CHECK-NEXT:    rlwinm 6, 3, 3, 27, 27
+; CHECK-NEXT:    ori 5, 5, 65535
+; CHECK-NEXT:    xori 6, 6, 16
+; CHECK-NEXT:    slw 4, 4, 6
+; CHECK-NEXT:    slw 5, 5, 6
+; CHECK-NEXT:    rldicr 3, 3, 0, 61
+; CHECK-NEXT:    and 6, 4, 5
+; CHECK-NEXT:  .LBB19_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lwarx 7, 0, 3
+; CHECK-NEXT:    and 8, 7, 5
+; CHECK-NEXT:    cmplw 8, 4
+; CHECK-NEXT:    bgtlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    andc 7, 7, 5
+; CHECK-NEXT:    or 7, 6, 7
+; CHECK-NEXT:    stwcx. 7, 0, 3
+; CHECK-NEXT:    bne 0, .LBB19_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw umax i16* %minimum, i16 %val monotonic
   ret void
 
-; CHECK-LABEL: @ae16umax
-; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
-; CHECK-DAG: li [[M1:[0-9]+]], 0
-; CHECK-DAG: rldicr 3, 3, 0, 61
-; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
-; CHECK-DAG: ori [[M2:[0-9]+]], [[M1]], 65535
-; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
-; CHECK-DAG: slw [[M:[0-9]+]], [[M2]], [[SA]]
-; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
-; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: cmplw 4, [[MOLDV]]
-; CHECK: blelr 0
-; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
-; CHECK: stwcx. [[NEWV]], 0, 3
-; CHECK: bne  0,
-; CHECK: blr
 }
 
 define void @ae8min(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
+; CHECK-LABEL: ae8min:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    rlwinm 5, 3, 3, 27, 28
+; CHECK-NEXT:    li 6, 255
+; CHECK-NEXT:    xori 5, 5, 24
+; CHECK-NEXT:    rldicr 3, 3, 0, 61
+; CHECK-NEXT:    slw 7, 4, 5
+; CHECK-NEXT:    slw 6, 6, 5
+; CHECK-NEXT:    and 7, 7, 6
+; CHECK-NEXT:  .LBB20_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lwarx 8, 0, 3
+; CHECK-NEXT:    and 9, 8, 6
+; CHECK-NEXT:    srw 9, 9, 5
+; CHECK-NEXT:    extsb 9, 9
+; CHECK-NEXT:    cmpw 9, 4
+; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    andc 8, 8, 6
+; CHECK-NEXT:    or 8, 7, 8
+; CHECK-NEXT:    stwcx. 8, 0, 3
+; CHECK-NEXT:    bne 0, .LBB20_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw min i8* %minimum, i8 %val monotonic
   ret void
 
-; CHECK-LABEL: @ae8min
-; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
-; CHECK-DAG: li [[M1:[0-9]+]], 255
-; CHECK-DAG: rldicr 3, 3, 0, 61
-; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
-; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
-; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
-; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
-; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
-; CHECK: extsb [[SESMOLDV:[0-9]+]], [[SMOLDV]]
-; CHECK: cmpw 4, [[SESMOLDV]]
-; CHECK: bgelr 0
-; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
-; CHECK: stwcx. [[NEWV]], 0, 3
-; CHECK: bne  0,
-; CHECK: blr
 }
 
 define void @ae8max(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
+; CHECK-LABEL: ae8max:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    rlwinm 5, 3, 3, 27, 28
+; CHECK-NEXT:    li 6, 255
+; CHECK-NEXT:    xori 5, 5, 24
+; CHECK-NEXT:    rldicr 3, 3, 0, 61
+; CHECK-NEXT:    slw 7, 4, 5
+; CHECK-NEXT:    slw 6, 6, 5
+; CHECK-NEXT:    and 7, 7, 6
+; CHECK-NEXT:  .LBB21_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lwarx 8, 0, 3
+; CHECK-NEXT:    and 9, 8, 6
+; CHECK-NEXT:    srw 9, 9, 5
+; CHECK-NEXT:    extsb 9, 9
+; CHECK-NEXT:    cmpw 9, 4
+; CHECK-NEXT:    bgtlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    andc 8, 8, 6
+; CHECK-NEXT:    or 8, 7, 8
+; CHECK-NEXT:    stwcx. 8, 0, 3
+; CHECK-NEXT:    bne 0, .LBB21_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw max i8* %minimum, i8 %val monotonic
   ret void
 
-; CHECK-LABEL: @ae8max
-; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
-; CHECK-DAG: li [[M1:[0-9]+]], 255
-; CHECK-DAG: rldicr 3, 3, 0, 61
-; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
-; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
-; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
-; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
-; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: srw [[SMOLDV:[0-9]+]], [[MOLDV]], [[SA]]
-; CHECK: extsb [[SESMOLDV:[0-9]+]], [[SMOLDV]]
-; CHECK: cmpw 4, [[SESMOLDV]]
-; CHECK: blelr 0
-; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
-; CHECK: stwcx. [[NEWV]], 0, 3
-; CHECK: bne  0,
-; CHECK: blr
 }
 
 define void @ae8umin(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
+; CHECK-LABEL: ae8umin:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    rlwinm 6, 3, 3, 27, 28
+; CHECK-NEXT:    li 5, 255
+; CHECK-NEXT:    xori 6, 6, 24
+; CHECK-NEXT:    rldicr 3, 3, 0, 61
+; CHECK-NEXT:    slw 4, 4, 6
+; CHECK-NEXT:    slw 5, 5, 6
+; CHECK-NEXT:    and 6, 4, 5
+; CHECK-NEXT:  .LBB22_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lwarx 7, 0, 3
+; CHECK-NEXT:    and 8, 7, 5
+; CHECK-NEXT:    cmplw 8, 4
+; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    andc 7, 7, 5
+; CHECK-NEXT:    or 7, 6, 7
+; CHECK-NEXT:    stwcx. 7, 0, 3
+; CHECK-NEXT:    bne 0, .LBB22_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw umin i8* %minimum, i8 %val monotonic
   ret void
 
-; CHECK-LABEL: @ae8umin
-; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
-; CHECK-DAG: li [[M1:[0-9]+]], 255
-; CHECK-DAG: rldicr 3, 3, 0, 61
-; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
-; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
-; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
-; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
-; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: cmplw 4, [[MOLDV]]
-; CHECK: bgelr 0
-; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
-; CHECK: stwcx. [[NEWV]], 0, 3
-; CHECK: bne  0,
-; CHECK: blr
 }
 
 define void @ae8umax(i8* nocapture dereferenceable(4) %minimum, i8 %val) #0 {
+; CHECK-LABEL: ae8umax:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    rlwinm 6, 3, 3, 27, 28
+; CHECK-NEXT:    li 5, 255
+; CHECK-NEXT:    xori 6, 6, 24
+; CHECK-NEXT:    rldicr 3, 3, 0, 61
+; CHECK-NEXT:    slw 4, 4, 6
+; CHECK-NEXT:    slw 5, 5, 6
+; CHECK-NEXT:    and 6, 4, 5
+; CHECK-NEXT:  .LBB23_1: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    lwarx 7, 0, 3
+; CHECK-NEXT:    and 8, 7, 5
+; CHECK-NEXT:    cmplw 8, 4
+; CHECK-NEXT:    bgtlr 0
+; CHECK-NEXT:  # %bb.2: # %entry
+; CHECK-NEXT:    #
+; CHECK-NEXT:    andc 7, 7, 5
+; CHECK-NEXT:    or 7, 6, 7
+; CHECK-NEXT:    stwcx. 7, 0, 3
+; CHECK-NEXT:    bne 0, .LBB23_1
+; CHECK-NEXT:  # %bb.3: # %entry
+; CHECK-NEXT:    blr
 entry:
   %0 = atomicrmw umax i8* %minimum, i8 %val monotonic
   ret void
 
-; CHECK-LABEL: @ae8umax
-; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
-; CHECK-DAG: li [[M1:[0-9]+]], 255
-; CHECK-DAG: rldicr 3, 3, 0, 61
-; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
-; CHECK-DAG: slw [[SV:[0-9]+]], 4, [[SA]]
-; CHECK-DAG: slw [[M:[0-9]+]], [[M1]], [[SA]]
-; CHECK-DAG: and [[SMV:[0-9]+]], [[SV]], [[M]]
-; CHECK: lwarx [[OLDV:[0-9]+]], 0, 3
-; CHECK: and [[MOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: cmplw 4, [[MOLDV]]
-; CHECK: blelr 0
-; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
-; CHECK: or [[NEWV:[0-9]+]], [[SMV]], [[NOLDV]]
-; CHECK: stwcx. [[NEWV]], 0, 3
-; CHECK: bne  0,
-; CHECK: blr
 }
 
 attributes #0 = { nounwind "target-cpu"="ppc64" }
 attributes #1 = { nounwind "target-cpu"="pwr8" }
 

llvm/test/CodeGen/PowerPC/atomics-regression.ll

 }
 
 define void @test40(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test40:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:  .LBB40_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB40_3
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB40_1
-; PPC64LE-NEXT:  .LBB40_3:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB40_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
   ret void
 }
 
 define void @test41(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test41:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:  .LBB41_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB41_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB41_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB41_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB41_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB41_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic
   ret void
 }
 
 define void @test42(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test42:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:  .LBB42_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB42_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB42_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB42_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB42_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB42_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire
   ret void
 }
 
 define void @test43(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test43:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB43_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB43_3
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB43_1
-; PPC64LE-NEXT:  .LBB43_3:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB43_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic
   ret void
 }
 
 define void @test44(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test44:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB44_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB44_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB44_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB44_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB44_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB44_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire
   ret void
 }
 
 define void @test45(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test45:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB45_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB45_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB45_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB45_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB45_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB45_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic
   ret void
 }
 
 define void @test46(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test46:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB46_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB46_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB46_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB46_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB46_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB46_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire
   ret void
 }
 
 define void @test47(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test47:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB47_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB47_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB47_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB47_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB47_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB47_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic
   ret void
 }
 
 define void @test48(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test48:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB48_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB48_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB48_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB48_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB48_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB48_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire
   ret void
 }
 
 define void @test49(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test49:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB49_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB49_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB49_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB49_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB49_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB49_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst
   ret void
 }
 
 define void @test50(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test50:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:  .LBB50_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB50_3
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB50_1
-; PPC64LE-NEXT:  .LBB50_3:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB50_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic
   ret void
 }
 
 define void @test51(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test51:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:  .LBB51_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB51_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB51_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB51_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB51_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB51_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic
   ret void
 }
 
 define void @test52(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test52:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:  .LBB52_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB52_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB52_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB52_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB52_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB52_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire
   ret void
 }
 
 define void @test53(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test53:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB53_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB53_3
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB53_1
-; PPC64LE-NEXT:  .LBB53_3:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB53_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic
   ret void
 }
 
 define void @test54(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test54:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB54_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB54_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB54_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB54_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB54_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB54_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire
   ret void
 }
 
 define void @test55(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test55:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB55_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB55_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB55_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB55_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB55_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB55_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic
   ret void
 }
 
 define void @test56(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test56:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB56_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB56_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB56_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB56_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB56_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB56_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire
   ret void
 }
 
 define void @test57(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test57:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB57_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB57_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB57_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB57_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB57_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB57_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic
   ret void
 }
 
 define void @test58(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test58:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB58_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB58_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB58_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB58_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB58_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB58_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire
   ret void
 }
 
 define void @test59(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test59:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB59_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB59_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB59_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB59_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB59_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB59_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst
   ret void
 }
 
 define void @test60(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test60:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB60_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB60_3
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB60_1
-; PPC64LE-NEXT:  .LBB60_3:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB60_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic
   ret void
 }
 
 define void @test61(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test61:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB61_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB61_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB61_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB61_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB61_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB61_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic
   ret void
 }
 
 define void @test62(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test62:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB62_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB62_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB62_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB62_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB62_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB62_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire
   ret void
 }
 
 define void @test63(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test63:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB63_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB63_3
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB63_1
-; PPC64LE-NEXT:  .LBB63_3:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB63_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic
   ret void
 }
 
 define void @test64(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test64:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB64_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB64_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB64_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB64_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB64_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB64_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire
   ret void
 }
 
 define void @test65(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test65:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB65_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB65_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB65_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB65_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB65_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB65_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic
   ret void
 }
 
 define void @test66(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test66:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB66_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB66_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB66_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB66_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB66_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB66_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire
   ret void
 }
 
 define void @test67(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test67:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB67_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB67_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB67_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB67_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB67_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB67_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic
   ret void
 }
 
 define void @test68(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test68:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB68_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB68_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB68_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB68_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB68_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB68_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire
   ret void
 }
 
 define void @test69(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test69:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB69_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB69_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB69_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB69_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB69_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB69_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
   ret void
 }
 
 define void @test70(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test70:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB70_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB70_3
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB70_1
-; PPC64LE-NEXT:  .LBB70_3:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB70_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic
   ret void
 }
 
 define void @test71(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test71:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB71_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB71_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB71_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB71_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB71_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB71_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic
   ret void
 }
 
 define void @test72(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test72:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB72_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB72_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB72_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB72_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB72_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB72_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire
   ret void
 }
 
 define void @test73(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test73:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB73_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB73_3
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB73_1
-; PPC64LE-NEXT:  .LBB73_3:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB73_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic
   ret void
 }
 
 define void @test74(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test74:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB74_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB74_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB74_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB74_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB74_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB74_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire
   ret void
 }
 
 define void @test75(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test75:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB75_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB75_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB75_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB75_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB75_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB75_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic
   ret void
 }
 
 define void @test76(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test76:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB76_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB76_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB76_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB76_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB76_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB76_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire
   ret void
 }
 
 define void @test77(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test77:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB77_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB77_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB77_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB77_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB77_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB77_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic
   ret void
 }
 
 define void @test78(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test78:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB78_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB78_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB78_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB78_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB78_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB78_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire
   ret void
 }
 
 define void @test79(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test79:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB79_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB79_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB79_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB79_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB79_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB79_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst
   ret void
 }
 
 define void @test80(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test80:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:  .LBB80_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB80_3
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB80_1
-; PPC64LE-NEXT:  .LBB80_3:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB80_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") monotonic monotonic
   ret void
 }
 
 define void @test81(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test81:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:  .LBB81_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB81_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB81_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB81_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB81_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB81_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire monotonic
   ret void
 }
 
 define void @test82(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test82:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:  .LBB82_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB82_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB82_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB82_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB82_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB82_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire acquire
   ret void
 }
 
 define void @test83(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test83:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB83_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB83_3
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB83_1
-; PPC64LE-NEXT:  .LBB83_3:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB83_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic
   ret void
 }
 
 define void @test84(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test84:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB84_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB84_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB84_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB84_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB84_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB84_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire
   ret void
 }
 
 define void @test85(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test85:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB85_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB85_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB85_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB85_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB85_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB85_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel monotonic
   ret void
 }
 
 define void @test86(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test86:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB86_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB86_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB86_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB86_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB86_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB86_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel acquire
   ret void
 }
 
 define void @test87(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test87:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB87_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB87_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB87_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB87_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB87_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB87_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst monotonic
   ret void
 }
 
 define void @test88(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test88:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB88_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB88_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB88_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB88_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB88_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB88_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst acquire
   ret void
 }
 
 define void @test89(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test89:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB89_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB89_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB89_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB89_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB89_4:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB89_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst seq_cst
   ret void
 }
 
 define void @test90(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test90:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:  .LBB90_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB90_3
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB90_1
-; PPC64LE-NEXT:  .LBB90_3:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB90_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") monotonic monotonic
   ret void
 }
 
 define void @test91(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test91:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:  .LBB91_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB91_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB91_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB91_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB91_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB91_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire monotonic
   ret void
 }
 
 define void @test92(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test92:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:  .LBB92_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB92_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB92_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB92_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB92_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB92_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire acquire
   ret void
 }
 
 define void @test93(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test93:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB93_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB93_3
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB93_1
-; PPC64LE-NEXT:  .LBB93_3:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB93_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic
   ret void
 }
 
 define void @test94(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test94:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB94_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB94_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB94_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB94_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB94_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB94_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire
   ret void
 }
 
 define void @test95(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test95:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB95_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB95_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB95_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB95_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB95_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB95_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel monotonic
   ret void
 }
 
 define void @test96(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test96:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB96_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB96_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB96_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB96_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB96_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB96_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel acquire
   ret void
 }
 
 define void @test97(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test97:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB97_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB97_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB97_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB97_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB97_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB97_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst monotonic
   ret void
 }
 
 define void @test98(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test98:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB98_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB98_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB98_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB98_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB98_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB98_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst acquire
   ret void
 }
 
 define void @test99(i16* %ptr, i16 %cmp, i16 %val) {
 ; PPC64LE-LABEL: test99:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 16
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB99_1:
 ; PPC64LE-NEXT:    lharx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB99_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB99_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB99_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB99_4:
-; PPC64LE-NEXT:    sthcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB99_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst seq_cst
   ret void
 }
 
 define void @test100(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test100:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB100_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB100_3
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB100_1
-; PPC64LE-NEXT:  .LBB100_3:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB100_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") monotonic monotonic
   ret void
 }
 
 define void @test101(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test101:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB101_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB101_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB101_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB101_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB101_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB101_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acquire monotonic
   ret void
 }
 
 define void @test102(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test102:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB102_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB102_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB102_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB102_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB102_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB102_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acquire acquire
   ret void
 }
 
 define void @test103(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test103:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB103_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB103_3
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB103_1
-; PPC64LE-NEXT:  .LBB103_3:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB103_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release monotonic
   ret void
 }
 
 define void @test104(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test104:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB104_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB104_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB104_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB104_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB104_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB104_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release acquire
   ret void
 }
 
 define void @test105(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test105:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB105_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB105_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB105_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB105_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB105_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB105_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acq_rel monotonic
   ret void
 }
 
 define void @test106(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test106:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB106_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB106_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB106_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB106_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB106_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB106_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acq_rel acquire
   ret void
 }
 
 define void @test107(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test107:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB107_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB107_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB107_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB107_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB107_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB107_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst monotonic
   ret void
 }
 
 define void @test108(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test108:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB108_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB108_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB108_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB108_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB108_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB108_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst acquire
   ret void
 }
 
 define void @test109(i32* %ptr, i32 %cmp, i32 %val) {
 ; PPC64LE-LABEL: test109:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB109_1:
 ; PPC64LE-NEXT:    lwarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB109_4
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB109_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB109_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB109_4:
-; PPC64LE-NEXT:    stwcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB109_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst seq_cst
   ret void
 }
 
 define void @test110(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test110:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB110_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB110_3
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB110_1
-; PPC64LE-NEXT:  .LBB110_3:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB110_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") monotonic monotonic
   ret void
 }
 
 define void @test111(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test111:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB111_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB111_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB111_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB111_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB111_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB111_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acquire monotonic
   ret void
 }
 
 define void @test112(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test112:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB112_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB112_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB112_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB112_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB112_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB112_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acquire acquire
   ret void
 }
 
 define void @test113(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test113:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB113_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB113_3
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB113_1
-; PPC64LE-NEXT:  .LBB113_3:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB113_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release monotonic
   ret void
 }
 
 define void @test114(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test114:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB114_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB114_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB114_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB114_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB114_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB114_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release acquire
   ret void
 }
 
 define void @test115(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test115:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB115_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB115_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB115_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB115_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB115_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB115_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acq_rel monotonic
   ret void
 }
 
 define void @test116(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test116:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB116_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB116_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB116_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB116_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB116_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB116_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acq_rel acquire
   ret void
 }
 
 define void @test117(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test117:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB117_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB117_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB117_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB117_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB117_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB117_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst monotonic
   ret void
 }
 
 define void @test118(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test118:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB118_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB118_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB118_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB118_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB118_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB118_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst acquire
   ret void
 }
 
 define void @test119(i64* %ptr, i64 %cmp, i64 %val) {
 ; PPC64LE-LABEL: test119:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB119_1:
 ; PPC64LE-NEXT:    ldarx 6, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB119_4
+; PPC64LE-NEXT:    cmpd 6, 4
+; PPC64LE-NEXT:    bne 0, .LBB119_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB119_1
-; PPC64LE-NEXT:  # %bb.3:
-; PPC64LE-NEXT:    lwsync
-; PPC64LE-NEXT:    blr
-; PPC64LE-NEXT:  .LBB119_4:
-; PPC64LE-NEXT:    stdcx. 6, 0, 3
+; PPC64LE-NEXT:  .LBB119_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst seq_cst
   ret void
 }
 
 define i8 @test120(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test120:

 
 define i8 @test260(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test260:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:  .LBB260_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB260_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB260_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB260_1
 ; PPC64LE-NEXT:  .LBB260_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i8* %ptr, i8 %val monotonic
   ret i8 %ret
 }
 
 define i8 @test261(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test261:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:  .LBB261_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB261_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB261_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB261_1
 ; PPC64LE-NEXT:  .LBB261_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i8* %ptr, i8 %val acquire
   ret i8 %ret
 }
 
 define i8 @test262(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test262:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB262_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB262_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB262_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB262_1
 ; PPC64LE-NEXT:  .LBB262_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i8* %ptr, i8 %val release
   ret i8 %ret
 }
 
 define i8 @test263(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test263:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB263_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB263_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB263_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB263_1
 ; PPC64LE-NEXT:  .LBB263_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i8* %ptr, i8 %val acq_rel
   ret i8 %ret
 }
 
 define i8 @test264(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test264:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB264_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB264_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB264_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB264_1
 ; PPC64LE-NEXT:  .LBB264_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i8* %ptr, i8 %val seq_cst
   ret i8 %ret
 }
 
 define i16 @test265(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test265:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:  .LBB265_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB265_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB265_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB265_1
 ; PPC64LE-NEXT:  .LBB265_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i16* %ptr, i16 %val monotonic
   ret i16 %ret
 }
 
 define i16 @test266(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test266:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:  .LBB266_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB266_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB266_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB266_1
 ; PPC64LE-NEXT:  .LBB266_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i16* %ptr, i16 %val acquire
   ret i16 %ret
 }
 
 define i16 @test267(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test267:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB267_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB267_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB267_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB267_1
 ; PPC64LE-NEXT:  .LBB267_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i16* %ptr, i16 %val release
   ret i16 %ret
 }
 
 define i16 @test268(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test268:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB268_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB268_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB268_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB268_1
 ; PPC64LE-NEXT:  .LBB268_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i16* %ptr, i16 %val acq_rel
   ret i16 %ret
 }
 
 define i16 @test269(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test269:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB269_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB269_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB269_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB269_1
 ; PPC64LE-NEXT:  .LBB269_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i16* %ptr, i16 %val seq_cst
   ret i16 %ret
 }
 
 define i32 @test270(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test270:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB270_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB270_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB270_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB270_1
 ; PPC64LE-NEXT:  .LBB270_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i32* %ptr, i32 %val monotonic
   ret i32 %ret
 }
 
 define i32 @test271(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test271:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB271_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    cmpw 4, 3
-; PPC64LE-NEXT:    ble 0, .LBB271_3
+; PPC64LE-NEXT:    cmpw 3, 4
+; PPC64LE-NEXT:    bgt 0, .LBB271_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB271_1
 ; PPC64LE-NEXT:  .LBB271_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i32* %ptr, i32 %val acquire
   ret i32 %ret
 }
 
 define i32 @test272(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test272:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB272_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB272_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB272_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB272_1
 ; PPC64LE-NEXT:  .LBB272_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i32* %ptr, i32 %val release
   ret i32 %ret
 }
 
 define i32 @test273(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test273:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB273_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB273_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB273_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB273_1
 ; PPC64LE-NEXT:  .LBB273_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i32* %ptr, i32 %val acq_rel
   ret i32 %ret
 }
 
 define i32 @test274(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test274:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB274_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB274_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB274_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB274_1
 ; PPC64LE-NEXT:  .LBB274_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i32* %ptr, i32 %val seq_cst
   ret i32 %ret
 }
 
 define i64 @test275(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test275:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB275_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB275_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB275_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB275_1
 ; PPC64LE-NEXT:  .LBB275_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i64* %ptr, i64 %val monotonic
   ret i64 %ret
 }
 
 define i64 @test276(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test276:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB276_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
-; PPC64LE-NEXT:    cmpd 4, 3
-; PPC64LE-NEXT:    ble 0, .LBB276_3
+; PPC64LE-NEXT:    cmpd 3, 4
+; PPC64LE-NEXT:    bgt 0, .LBB276_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB276_1
 ; PPC64LE-NEXT:  .LBB276_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i64* %ptr, i64 %val acquire
   ret i64 %ret
 }
 
 define i64 @test277(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test277:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB277_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB277_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB277_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB277_1
 ; PPC64LE-NEXT:  .LBB277_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i64* %ptr, i64 %val release
   ret i64 %ret
 }
 
 define i64 @test278(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test278:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB278_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB278_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB278_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB278_1
 ; PPC64LE-NEXT:  .LBB278_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i64* %ptr, i64 %val acq_rel
   ret i64 %ret
 }
 
 define i64 @test279(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test279:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB279_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB279_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB279_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB279_1
 ; PPC64LE-NEXT:  .LBB279_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i64* %ptr, i64 %val seq_cst
   ret i64 %ret
 }
 
 define i8 @test280(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test280:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:  .LBB280_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB280_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB280_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB280_1
 ; PPC64LE-NEXT:  .LBB280_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i8* %ptr, i8 %val monotonic
   ret i8 %ret
 }
 
 define i8 @test281(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test281:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:  .LBB281_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB281_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB281_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB281_1
 ; PPC64LE-NEXT:  .LBB281_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i8* %ptr, i8 %val acquire
   ret i8 %ret
 }
 
 define i8 @test282(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test282:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB282_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB282_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB282_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB282_1
 ; PPC64LE-NEXT:  .LBB282_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i8* %ptr, i8 %val release
   ret i8 %ret
 }
 
 define i8 @test283(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test283:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB283_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB283_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB283_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB283_1
 ; PPC64LE-NEXT:  .LBB283_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i8* %ptr, i8 %val acq_rel
   ret i8 %ret
 }
 
 define i8 @test284(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test284:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB284_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB284_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB284_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB284_1
 ; PPC64LE-NEXT:  .LBB284_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i8* %ptr, i8 %val seq_cst
   ret i8 %ret
 }
 
 define i16 @test285(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test285:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:  .LBB285_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB285_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB285_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB285_1
 ; PPC64LE-NEXT:  .LBB285_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i16* %ptr, i16 %val monotonic
   ret i16 %ret
 }
 
 define i16 @test286(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test286:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:  .LBB286_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB286_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB286_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB286_1
 ; PPC64LE-NEXT:  .LBB286_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i16* %ptr, i16 %val acquire
   ret i16 %ret
 }
 
 define i16 @test287(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test287:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB287_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB287_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB287_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB287_1
 ; PPC64LE-NEXT:  .LBB287_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i16* %ptr, i16 %val release
   ret i16 %ret
 }
 
 define i16 @test288(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test288:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB288_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB288_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB288_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB288_1
 ; PPC64LE-NEXT:  .LBB288_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i16* %ptr, i16 %val acq_rel
   ret i16 %ret
 }
 
 define i16 @test289(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test289:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB289_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB289_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB289_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB289_1
 ; PPC64LE-NEXT:  .LBB289_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i16* %ptr, i16 %val seq_cst
   ret i16 %ret
 }
 
 define i32 @test290(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test290:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB290_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB290_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB290_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB290_1
 ; PPC64LE-NEXT:  .LBB290_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i32* %ptr, i32 %val monotonic
   ret i32 %ret
 }
 
 define i32 @test291(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test291:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB291_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    cmpw 4, 3
-; PPC64LE-NEXT:    bge 0, .LBB291_3
+; PPC64LE-NEXT:    cmpw 3, 4
+; PPC64LE-NEXT:    blt 0, .LBB291_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB291_1
 ; PPC64LE-NEXT:  .LBB291_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i32* %ptr, i32 %val acquire
   ret i32 %ret
 }
 
 define i32 @test292(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test292:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB292_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB292_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB292_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB292_1
 ; PPC64LE-NEXT:  .LBB292_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i32* %ptr, i32 %val release
   ret i32 %ret
 }
 
 define i32 @test293(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test293:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB293_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB293_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB293_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB293_1
 ; PPC64LE-NEXT:  .LBB293_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i32* %ptr, i32 %val acq_rel
   ret i32 %ret
 }
 
 define i32 @test294(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test294:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB294_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB294_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB294_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB294_1
 ; PPC64LE-NEXT:  .LBB294_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i32* %ptr, i32 %val seq_cst
   ret i32 %ret
 }
 
 define i64 @test295(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test295:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB295_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB295_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB295_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB295_1
 ; PPC64LE-NEXT:  .LBB295_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i64* %ptr, i64 %val monotonic
   ret i64 %ret
 }
 
 define i64 @test296(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test296:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB296_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
-; PPC64LE-NEXT:    cmpd 4, 3
-; PPC64LE-NEXT:    bge 0, .LBB296_3
+; PPC64LE-NEXT:    cmpd 3, 4
+; PPC64LE-NEXT:    blt 0, .LBB296_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB296_1
 ; PPC64LE-NEXT:  .LBB296_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i64* %ptr, i64 %val acquire
   ret i64 %ret
 }
 
 define i64 @test297(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test297:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB297_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB297_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB297_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB297_1
 ; PPC64LE-NEXT:  .LBB297_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i64* %ptr, i64 %val release
   ret i64 %ret
 }
 
 define i64 @test298(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test298:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB298_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB298_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB298_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB298_1
 ; PPC64LE-NEXT:  .LBB298_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i64* %ptr, i64 %val acq_rel
   ret i64 %ret
 }
 
 define i64 @test299(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test299:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB299_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB299_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB299_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB299_1
 ; PPC64LE-NEXT:  .LBB299_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i64* %ptr, i64 %val seq_cst
   ret i64 %ret
 }
 
 define i8 @test300(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test300:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB300_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB300_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB300_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB300_1
 ; PPC64LE-NEXT:  .LBB300_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i8* %ptr, i8 %val monotonic
   ret i8 %ret
 }
 
 define i8 @test301(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test301:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB301_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
-; PPC64LE-NEXT:    cmplw 4, 3
-; PPC64LE-NEXT:    ble 0, .LBB301_3
+; PPC64LE-NEXT:    cmplw 3, 4
+; PPC64LE-NEXT:    bgt 0, .LBB301_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB301_1
 ; PPC64LE-NEXT:  .LBB301_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i8* %ptr, i8 %val acquire
   ret i8 %ret
 }
 
 define i8 @test302(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test302:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB302_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB302_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB302_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB302_1
 ; PPC64LE-NEXT:  .LBB302_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i8* %ptr, i8 %val release
   ret i8 %ret
 }
 
 define i8 @test303(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test303:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB303_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB303_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB303_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB303_1
 ; PPC64LE-NEXT:  .LBB303_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i8* %ptr, i8 %val acq_rel
   ret i8 %ret
 }
 
 define i8 @test304(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test304:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB304_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB304_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB304_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB304_1
 ; PPC64LE-NEXT:  .LBB304_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i8* %ptr, i8 %val seq_cst
   ret i8 %ret
 }
 
 define i16 @test305(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test305:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB305_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB305_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB305_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB305_1
 ; PPC64LE-NEXT:  .LBB305_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i16* %ptr, i16 %val monotonic
   ret i16 %ret
 }
 
 define i16 @test306(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test306:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB306_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
-; PPC64LE-NEXT:    cmplw 4, 3
-; PPC64LE-NEXT:    ble 0, .LBB306_3
+; PPC64LE-NEXT:    cmplw 3, 4
+; PPC64LE-NEXT:    bgt 0, .LBB306_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB306_1
 ; PPC64LE-NEXT:  .LBB306_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i16* %ptr, i16 %val acquire
   ret i16 %ret
 }
 
 define i16 @test307(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test307:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB307_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB307_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB307_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB307_1
 ; PPC64LE-NEXT:  .LBB307_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i16* %ptr, i16 %val release
   ret i16 %ret
 }
 
 define i16 @test308(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test308:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB308_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB308_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB308_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB308_1
 ; PPC64LE-NEXT:  .LBB308_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i16* %ptr, i16 %val acq_rel
   ret i16 %ret
 }
 
 define i16 @test309(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test309:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB309_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB309_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB309_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB309_1
 ; PPC64LE-NEXT:  .LBB309_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i16* %ptr, i16 %val seq_cst
   ret i16 %ret
 }
 
 define i32 @test310(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test310:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB310_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB310_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB310_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB310_1
 ; PPC64LE-NEXT:  .LBB310_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i32* %ptr, i32 %val monotonic
   ret i32 %ret
 }
 
 define i32 @test311(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test311:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB311_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    cmplw 4, 3
-; PPC64LE-NEXT:    ble 0, .LBB311_3
+; PPC64LE-NEXT:    cmplw 3, 4
+; PPC64LE-NEXT:    bgt 0, .LBB311_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB311_1
 ; PPC64LE-NEXT:  .LBB311_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i32* %ptr, i32 %val acquire
   ret i32 %ret
 }
 
 define i32 @test312(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test312:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB312_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB312_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB312_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB312_1
 ; PPC64LE-NEXT:  .LBB312_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i32* %ptr, i32 %val release
   ret i32 %ret
 }
 
 define i32 @test313(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test313:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB313_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB313_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB313_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB313_1
 ; PPC64LE-NEXT:  .LBB313_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i32* %ptr, i32 %val acq_rel
   ret i32 %ret
 }
 
 define i32 @test314(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test314:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB314_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB314_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB314_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB314_1
 ; PPC64LE-NEXT:  .LBB314_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i32* %ptr, i32 %val seq_cst
   ret i32 %ret
 }
 
 define i64 @test315(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test315:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB315_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB315_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB315_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB315_1
 ; PPC64LE-NEXT:  .LBB315_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i64* %ptr, i64 %val monotonic
   ret i64 %ret
 }
 
 define i64 @test316(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test316:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB316_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
-; PPC64LE-NEXT:    cmpld 4, 3
-; PPC64LE-NEXT:    ble 0, .LBB316_3
+; PPC64LE-NEXT:    cmpld 3, 4
+; PPC64LE-NEXT:    bgt 0, .LBB316_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB316_1
 ; PPC64LE-NEXT:  .LBB316_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i64* %ptr, i64 %val acquire
   ret i64 %ret
 }
 
 define i64 @test317(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test317:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB317_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB317_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB317_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB317_1
 ; PPC64LE-NEXT:  .LBB317_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i64* %ptr, i64 %val release
   ret i64 %ret
 }
 
 define i64 @test318(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test318:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB318_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB318_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB318_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB318_1
 ; PPC64LE-NEXT:  .LBB318_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i64* %ptr, i64 %val acq_rel
   ret i64 %ret
 }
 
 define i64 @test319(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test319:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB319_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB319_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB319_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB319_1
 ; PPC64LE-NEXT:  .LBB319_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i64* %ptr, i64 %val seq_cst
   ret i64 %ret
 }
 
 define i8 @test320(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test320:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB320_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB320_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB320_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB320_1
 ; PPC64LE-NEXT:  .LBB320_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i8* %ptr, i8 %val monotonic
   ret i8 %ret
 }
 
 define i8 @test321(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test321:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB321_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
-; PPC64LE-NEXT:    cmplw 4, 3
-; PPC64LE-NEXT:    bge 0, .LBB321_3
+; PPC64LE-NEXT:    cmplw 3, 4
+; PPC64LE-NEXT:    blt 0, .LBB321_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB321_1
 ; PPC64LE-NEXT:  .LBB321_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i8* %ptr, i8 %val acquire
   ret i8 %ret
 }
 
 define i8 @test322(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test322:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB322_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB322_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB322_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB322_1
 ; PPC64LE-NEXT:  .LBB322_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i8* %ptr, i8 %val release
   ret i8 %ret
 }
 
 define i8 @test323(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test323:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB323_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB323_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB323_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB323_1
 ; PPC64LE-NEXT:  .LBB323_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i8* %ptr, i8 %val acq_rel
   ret i8 %ret
 }
 
 define i8 @test324(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test324:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB324_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB324_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB324_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB324_1
 ; PPC64LE-NEXT:  .LBB324_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i8* %ptr, i8 %val seq_cst
   ret i8 %ret
 }
 
 define i16 @test325(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test325:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB325_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB325_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB325_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB325_1
 ; PPC64LE-NEXT:  .LBB325_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i16* %ptr, i16 %val monotonic
   ret i16 %ret
 }
 
 define i16 @test326(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test326:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB326_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
-; PPC64LE-NEXT:    cmplw 4, 3
-; PPC64LE-NEXT:    bge 0, .LBB326_3
+; PPC64LE-NEXT:    cmplw 3, 4
+; PPC64LE-NEXT:    blt 0, .LBB326_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB326_1
 ; PPC64LE-NEXT:  .LBB326_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i16* %ptr, i16 %val acquire
   ret i16 %ret
 }
 
 define i16 @test327(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test327:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB327_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB327_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB327_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB327_1
 ; PPC64LE-NEXT:  .LBB327_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i16* %ptr, i16 %val release
   ret i16 %ret
 }
 
 define i16 @test328(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test328:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB328_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB328_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB328_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB328_1
 ; PPC64LE-NEXT:  .LBB328_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i16* %ptr, i16 %val acq_rel
   ret i16 %ret
 }
 
 define i16 @test329(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test329:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB329_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB329_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB329_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB329_1
 ; PPC64LE-NEXT:  .LBB329_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i16* %ptr, i16 %val seq_cst
   ret i16 %ret
 }
 
 define i32 @test330(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test330:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB330_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB330_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB330_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB330_1
 ; PPC64LE-NEXT:  .LBB330_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i32* %ptr, i32 %val monotonic
   ret i32 %ret
 }
 
 define i32 @test331(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test331:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB331_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    cmplw 4, 3
-; PPC64LE-NEXT:    bge 0, .LBB331_3
+; PPC64LE-NEXT:    cmplw 3, 4
+; PPC64LE-NEXT:    blt 0, .LBB331_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB331_1
 ; PPC64LE-NEXT:  .LBB331_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i32* %ptr, i32 %val acquire
   ret i32 %ret
 }
 
 define i32 @test332(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test332:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB332_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB332_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB332_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB332_1
 ; PPC64LE-NEXT:  .LBB332_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i32* %ptr, i32 %val release
   ret i32 %ret
 }
 
 define i32 @test333(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test333:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB333_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB333_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB333_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB333_1
 ; PPC64LE-NEXT:  .LBB333_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i32* %ptr, i32 %val acq_rel
   ret i32 %ret
 }
 
 define i32 @test334(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test334:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB334_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB334_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB334_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB334_1
 ; PPC64LE-NEXT:  .LBB334_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i32* %ptr, i32 %val seq_cst
   ret i32 %ret
 }
 
 define i64 @test335(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test335:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB335_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB335_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB335_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB335_1
 ; PPC64LE-NEXT:  .LBB335_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i64* %ptr, i64 %val monotonic
   ret i64 %ret
 }
 
 define i64 @test336(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test336:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB336_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
-; PPC64LE-NEXT:    cmpld 4, 3
-; PPC64LE-NEXT:    bge 0, .LBB336_3
+; PPC64LE-NEXT:    cmpld 3, 4
+; PPC64LE-NEXT:    blt 0, .LBB336_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB336_1
 ; PPC64LE-NEXT:  .LBB336_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i64* %ptr, i64 %val acquire
   ret i64 %ret
 }
 
 define i64 @test337(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test337:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB337_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB337_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB337_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB337_1
 ; PPC64LE-NEXT:  .LBB337_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i64* %ptr, i64 %val release
   ret i64 %ret
 }
 
 define i64 @test338(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test338:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB338_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB338_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB338_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB338_1
 ; PPC64LE-NEXT:  .LBB338_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i64* %ptr, i64 %val acq_rel
   ret i64 %ret
 }
 
 define i64 @test339(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test339:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB339_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB339_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB339_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB339_1
 ; PPC64LE-NEXT:  .LBB339_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i64* %ptr, i64 %val seq_cst

 
 define i8 @test480(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test480:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:  .LBB480_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB480_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB480_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB480_1
 ; PPC64LE-NEXT:  .LBB480_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") monotonic
   ret i8 %ret
 }
 
 define i8 @test481(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test481:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:  .LBB481_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB481_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB481_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB481_1
 ; PPC64LE-NEXT:  .LBB481_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") acquire
   ret i8 %ret
 }
 
 define i8 @test482(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test482:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB482_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB482_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB482_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB482_1
 ; PPC64LE-NEXT:  .LBB482_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") release
   ret i8 %ret
 }
 
 define i8 @test483(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test483:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB483_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB483_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB483_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB483_1
 ; PPC64LE-NEXT:  .LBB483_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") acq_rel
   ret i8 %ret
 }
 
 define i8 @test484(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test484:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB484_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB484_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB484_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB484_1
 ; PPC64LE-NEXT:  .LBB484_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") seq_cst
   ret i8 %ret
 }
 
 define i16 @test485(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test485:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:  .LBB485_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB485_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB485_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB485_1
 ; PPC64LE-NEXT:  .LBB485_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") monotonic
   ret i16 %ret
 }
 
 define i16 @test486(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test486:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:  .LBB486_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB486_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB486_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB486_1
 ; PPC64LE-NEXT:  .LBB486_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") acquire
   ret i16 %ret
 }
 
 define i16 @test487(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test487:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB487_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB487_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB487_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB487_1
 ; PPC64LE-NEXT:  .LBB487_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") release
   ret i16 %ret
 }
 
 define i16 @test488(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test488:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB488_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB488_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB488_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB488_1
 ; PPC64LE-NEXT:  .LBB488_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") acq_rel
   ret i16 %ret
 }
 
 define i16 @test489(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test489:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB489_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    ble 0, .LBB489_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    bgt 0, .LBB489_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB489_1
 ; PPC64LE-NEXT:  .LBB489_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") seq_cst
   ret i16 %ret
 }
 
 define i32 @test490(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test490:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB490_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB490_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB490_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB490_1
 ; PPC64LE-NEXT:  .LBB490_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") monotonic
   ret i32 %ret
 }
 
 define i32 @test491(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test491:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB491_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    cmpw 4, 3
-; PPC64LE-NEXT:    ble 0, .LBB491_3
+; PPC64LE-NEXT:    cmpw 3, 4
+; PPC64LE-NEXT:    bgt 0, .LBB491_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB491_1
 ; PPC64LE-NEXT:  .LBB491_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") acquire
   ret i32 %ret
 }
 
 define i32 @test492(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test492:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB492_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB492_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB492_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB492_1
 ; PPC64LE-NEXT:  .LBB492_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") release
   ret i32 %ret
 }
 
 define i32 @test493(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test493:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB493_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB493_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB493_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB493_1
 ; PPC64LE-NEXT:  .LBB493_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") acq_rel
   ret i32 %ret
 }
 
 define i32 @test494(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test494:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB494_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB494_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB494_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB494_1
 ; PPC64LE-NEXT:  .LBB494_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") seq_cst
   ret i32 %ret
 }
 
 define i64 @test495(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test495:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB495_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB495_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB495_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB495_1
 ; PPC64LE-NEXT:  .LBB495_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") monotonic
   ret i64 %ret
 }
 
 define i64 @test496(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test496:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB496_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
-; PPC64LE-NEXT:    cmpd 4, 3
-; PPC64LE-NEXT:    ble 0, .LBB496_3
+; PPC64LE-NEXT:    cmpd 3, 4
+; PPC64LE-NEXT:    bgt 0, .LBB496_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB496_1
 ; PPC64LE-NEXT:  .LBB496_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") acquire
   ret i64 %ret
 }
 
 define i64 @test497(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test497:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB497_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB497_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB497_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB497_1
 ; PPC64LE-NEXT:  .LBB497_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") release
   ret i64 %ret
 }
 
 define i64 @test498(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test498:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB498_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB498_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB498_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB498_1
 ; PPC64LE-NEXT:  .LBB498_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") acq_rel
   ret i64 %ret
 }
 
 define i64 @test499(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test499:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB499_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB499_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB499_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB499_1
 ; PPC64LE-NEXT:  .LBB499_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") seq_cst
   ret i64 %ret
 }
 
 define i8 @test500(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test500:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:  .LBB500_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB500_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB500_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB500_1
 ; PPC64LE-NEXT:  .LBB500_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") monotonic
   ret i8 %ret
 }
 
 define i8 @test501(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test501:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:  .LBB501_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB501_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB501_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB501_1
 ; PPC64LE-NEXT:  .LBB501_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") acquire
   ret i8 %ret
 }
 
 define i8 @test502(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test502:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB502_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB502_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB502_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB502_1
 ; PPC64LE-NEXT:  .LBB502_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") release
   ret i8 %ret
 }
 
 define i8 @test503(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test503:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB503_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB503_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB503_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB503_1
 ; PPC64LE-NEXT:  .LBB503_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") acq_rel
   ret i8 %ret
 }
 
 define i8 @test504(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test504:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsb 5, 4
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB504_1:
 ; PPC64LE-NEXT:    lbarx 4, 0, 3
 ; PPC64LE-NEXT:    extsb 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB504_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB504_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB504_1
 ; PPC64LE-NEXT:  .LBB504_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") seq_cst
   ret i8 %ret
 }
 
 define i16 @test505(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test505:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:  .LBB505_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB505_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB505_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB505_1
 ; PPC64LE-NEXT:  .LBB505_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") monotonic
   ret i16 %ret
 }
 
 define i16 @test506(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test506:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:  .LBB506_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB506_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB506_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB506_1
 ; PPC64LE-NEXT:  .LBB506_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") acquire
   ret i16 %ret
 }
 
 define i16 @test507(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test507:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB507_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB507_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB507_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB507_1
 ; PPC64LE-NEXT:  .LBB507_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") release
   ret i16 %ret
 }
 
 define i16 @test508(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test508:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB508_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB508_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB508_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB508_1
 ; PPC64LE-NEXT:  .LBB508_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") acq_rel
   ret i16 %ret
 }
 
 define i16 @test509(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test509:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    extsh 5, 4
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB509_1:
 ; PPC64LE-NEXT:    lharx 4, 0, 3
 ; PPC64LE-NEXT:    extsh 6, 4
-; PPC64LE-NEXT:    cmpw 5, 6
-; PPC64LE-NEXT:    bge 0, .LBB509_3
+; PPC64LE-NEXT:    cmpw 6, 5
+; PPC64LE-NEXT:    blt 0, .LBB509_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 5, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB509_1
 ; PPC64LE-NEXT:  .LBB509_3:
 ; PPC64LE-NEXT:    mr 3, 4
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") seq_cst
   ret i16 %ret
 }
 
 define i32 @test510(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test510:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB510_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB510_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB510_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB510_1
 ; PPC64LE-NEXT:  .LBB510_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") monotonic
   ret i32 %ret
 }
 
 define i32 @test511(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test511:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB511_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    cmpw 4, 3
-; PPC64LE-NEXT:    bge 0, .LBB511_3
+; PPC64LE-NEXT:    cmpw 3, 4
+; PPC64LE-NEXT:    blt 0, .LBB511_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB511_1
 ; PPC64LE-NEXT:  .LBB511_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") acquire
   ret i32 %ret
 }
 
 define i32 @test512(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test512:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB512_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB512_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB512_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB512_1
 ; PPC64LE-NEXT:  .LBB512_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") release
   ret i32 %ret
 }
 
 define i32 @test513(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test513:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB513_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB513_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB513_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB513_1
 ; PPC64LE-NEXT:  .LBB513_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") acq_rel
   ret i32 %ret
 }
 
 define i32 @test514(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test514:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB514_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB514_3
+; PPC64LE-NEXT:    cmpw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB514_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB514_1
 ; PPC64LE-NEXT:  .LBB514_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") seq_cst
   ret i32 %ret
 }
 
 define i64 @test515(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test515:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB515_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB515_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB515_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB515_1
 ; PPC64LE-NEXT:  .LBB515_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") monotonic
   ret i64 %ret
 }
 
 define i64 @test516(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test516:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB516_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
-; PPC64LE-NEXT:    cmpd 4, 3
-; PPC64LE-NEXT:    bge 0, .LBB516_3
+; PPC64LE-NEXT:    cmpd 3, 4
+; PPC64LE-NEXT:    blt 0, .LBB516_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB516_1
 ; PPC64LE-NEXT:  .LBB516_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") acquire
   ret i64 %ret
 }
 
 define i64 @test517(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test517:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB517_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB517_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB517_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB517_1
 ; PPC64LE-NEXT:  .LBB517_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") release
   ret i64 %ret
 }
 
 define i64 @test518(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test518:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB518_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB518_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB518_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB518_1
 ; PPC64LE-NEXT:  .LBB518_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") acq_rel
   ret i64 %ret
 }
 
 define i64 @test519(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test519:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB519_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpd 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB519_3
+; PPC64LE-NEXT:    cmpd 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB519_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB519_1
 ; PPC64LE-NEXT:  .LBB519_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") seq_cst
   ret i64 %ret
 }
 
 define i8 @test520(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test520:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB520_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB520_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB520_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB520_1
 ; PPC64LE-NEXT:  .LBB520_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") monotonic
   ret i8 %ret
 }
 
 define i8 @test521(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test521:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB521_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
-; PPC64LE-NEXT:    cmplw 4, 3
-; PPC64LE-NEXT:    ble 0, .LBB521_3
+; PPC64LE-NEXT:    cmplw 3, 4
+; PPC64LE-NEXT:    bgt 0, .LBB521_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB521_1
 ; PPC64LE-NEXT:  .LBB521_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") acquire
   ret i8 %ret
 }
 
 define i8 @test522(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test522:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB522_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB522_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB522_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB522_1
 ; PPC64LE-NEXT:  .LBB522_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") release
   ret i8 %ret
 }
 
 define i8 @test523(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test523:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB523_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB523_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB523_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB523_1
 ; PPC64LE-NEXT:  .LBB523_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") acq_rel
   ret i8 %ret
 }
 
 define i8 @test524(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test524:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB524_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB524_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB524_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB524_1
 ; PPC64LE-NEXT:  .LBB524_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") seq_cst
   ret i8 %ret
 }
 
 define i16 @test525(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test525:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB525_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB525_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB525_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB525_1
 ; PPC64LE-NEXT:  .LBB525_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") monotonic
   ret i16 %ret
 }
 
 define i16 @test526(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test526:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB526_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
-; PPC64LE-NEXT:    cmplw 4, 3
-; PPC64LE-NEXT:    ble 0, .LBB526_3
+; PPC64LE-NEXT:    cmplw 3, 4
+; PPC64LE-NEXT:    bgt 0, .LBB526_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB526_1
 ; PPC64LE-NEXT:  .LBB526_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") acquire
   ret i16 %ret
 }
 
 define i16 @test527(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test527:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB527_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB527_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB527_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB527_1
 ; PPC64LE-NEXT:  .LBB527_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") release
   ret i16 %ret
 }
 
 define i16 @test528(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test528:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB528_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB528_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB528_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB528_1
 ; PPC64LE-NEXT:  .LBB528_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") acq_rel
   ret i16 %ret
 }
 
 define i16 @test529(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test529:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB529_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB529_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB529_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB529_1
 ; PPC64LE-NEXT:  .LBB529_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") seq_cst
   ret i16 %ret
 }
 
 define i32 @test530(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test530:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB530_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB530_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB530_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB530_1
 ; PPC64LE-NEXT:  .LBB530_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") monotonic
   ret i32 %ret
 }
 
 define i32 @test531(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test531:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB531_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    cmplw 4, 3
-; PPC64LE-NEXT:    ble 0, .LBB531_3
+; PPC64LE-NEXT:    cmplw 3, 4
+; PPC64LE-NEXT:    bgt 0, .LBB531_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB531_1
 ; PPC64LE-NEXT:  .LBB531_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") acquire
   ret i32 %ret
 }
 
 define i32 @test532(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test532:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB532_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB532_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB532_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB532_1
 ; PPC64LE-NEXT:  .LBB532_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") release
   ret i32 %ret
 }
 
 define i32 @test533(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test533:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB533_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB533_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB533_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB533_1
 ; PPC64LE-NEXT:  .LBB533_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") acq_rel
   ret i32 %ret
 }
 
 define i32 @test534(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test534:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB534_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB534_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB534_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB534_1
 ; PPC64LE-NEXT:  .LBB534_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") seq_cst
   ret i32 %ret
 }
 
 define i64 @test535(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test535:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB535_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB535_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB535_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB535_1
 ; PPC64LE-NEXT:  .LBB535_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") monotonic
   ret i64 %ret
 }
 
 define i64 @test536(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test536:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB536_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
-; PPC64LE-NEXT:    cmpld 4, 3
-; PPC64LE-NEXT:    ble 0, .LBB536_3
+; PPC64LE-NEXT:    cmpld 3, 4
+; PPC64LE-NEXT:    bgt 0, .LBB536_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB536_1
 ; PPC64LE-NEXT:  .LBB536_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") acquire
   ret i64 %ret
 }
 
 define i64 @test537(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test537:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB537_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB537_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB537_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB537_1
 ; PPC64LE-NEXT:  .LBB537_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") release
   ret i64 %ret
 }
 
 define i64 @test538(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test538:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB538_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB538_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB538_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB538_1
 ; PPC64LE-NEXT:  .LBB538_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") acq_rel
   ret i64 %ret
 }
 
 define i64 @test539(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test539:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB539_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    ble 0, .LBB539_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    bgt 0, .LBB539_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB539_1
 ; PPC64LE-NEXT:  .LBB539_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") seq_cst
   ret i64 %ret
 }
 
 define i8 @test540(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test540:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB540_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB540_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB540_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB540_1
 ; PPC64LE-NEXT:  .LBB540_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") monotonic
   ret i8 %ret
 }
 
 define i8 @test541(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test541:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB541_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
-; PPC64LE-NEXT:    cmplw 4, 3
-; PPC64LE-NEXT:    bge 0, .LBB541_3
+; PPC64LE-NEXT:    cmplw 3, 4
+; PPC64LE-NEXT:    blt 0, .LBB541_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB541_1
 ; PPC64LE-NEXT:  .LBB541_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") acquire
   ret i8 %ret
 }
 
 define i8 @test542(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test542:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB542_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB542_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB542_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB542_1
 ; PPC64LE-NEXT:  .LBB542_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") release
   ret i8 %ret
 }
 
 define i8 @test543(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test543:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB543_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB543_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB543_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB543_1
 ; PPC64LE-NEXT:  .LBB543_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") acq_rel
   ret i8 %ret
 }
 
 define i8 @test544(i8* %ptr, i8 %val) {
 ; PPC64LE-LABEL: test544:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB544_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB544_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB544_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB544_1
 ; PPC64LE-NEXT:  .LBB544_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") seq_cst
   ret i8 %ret
 }
 
 define i16 @test545(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test545:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB545_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB545_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB545_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB545_1
 ; PPC64LE-NEXT:  .LBB545_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") monotonic
   ret i16 %ret
 }
 
 define i16 @test546(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test546:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB546_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
-; PPC64LE-NEXT:    cmplw 4, 3
-; PPC64LE-NEXT:    bge 0, .LBB546_3
+; PPC64LE-NEXT:    cmplw 3, 4
+; PPC64LE-NEXT:    blt 0, .LBB546_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB546_1
 ; PPC64LE-NEXT:  .LBB546_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") acquire
   ret i16 %ret
 }
 
 define i16 @test547(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test547:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB547_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB547_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB547_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB547_1
 ; PPC64LE-NEXT:  .LBB547_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") release
   ret i16 %ret
 }
 
 define i16 @test548(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test548:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB548_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB548_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB548_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB548_1
 ; PPC64LE-NEXT:  .LBB548_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") acq_rel
   ret i16 %ret
 }
 
 define i16 @test549(i16* %ptr, i16 %val) {
 ; PPC64LE-LABEL: test549:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB549_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB549_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB549_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    sthcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB549_1
 ; PPC64LE-NEXT:  .LBB549_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") seq_cst
   ret i16 %ret
 }
 
 define i32 @test550(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test550:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB550_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB550_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB550_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB550_1
 ; PPC64LE-NEXT:  .LBB550_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") monotonic
   ret i32 %ret
 }
 
 define i32 @test551(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test551:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB551_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    cmplw 4, 3
-; PPC64LE-NEXT:    bge 0, .LBB551_3
+; PPC64LE-NEXT:    cmplw 3, 4
+; PPC64LE-NEXT:    blt 0, .LBB551_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB551_1
 ; PPC64LE-NEXT:  .LBB551_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") acquire
   ret i32 %ret
 }
 
 define i32 @test552(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test552:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB552_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB552_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB552_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB552_1
 ; PPC64LE-NEXT:  .LBB552_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") release
   ret i32 %ret
 }
 
 define i32 @test553(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test553:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB553_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB553_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB553_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB553_1
 ; PPC64LE-NEXT:  .LBB553_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") acq_rel
   ret i32 %ret
 }
 
 define i32 @test554(i32* %ptr, i32 %val) {
 ; PPC64LE-LABEL: test554:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB554_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    cmplw 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB554_3
+; PPC64LE-NEXT:    cmplw 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB554_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stwcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB554_1
 ; PPC64LE-NEXT:  .LBB554_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") seq_cst
   ret i32 %ret
 }
 
 define i64 @test555(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test555:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB555_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB555_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB555_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB555_1
 ; PPC64LE-NEXT:  .LBB555_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") monotonic
   ret i64 %ret
 }
 
 define i64 @test556(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test556:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB556_1:
 ; PPC64LE-NEXT:    ldarx 3, 0, 5
-; PPC64LE-NEXT:    cmpld 4, 3
-; PPC64LE-NEXT:    bge 0, .LBB556_3
+; PPC64LE-NEXT:    cmpld 3, 4
+; PPC64LE-NEXT:    blt 0, .LBB556_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB556_1
 ; PPC64LE-NEXT:  .LBB556_3:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") acquire
   ret i64 %ret
 }
 
 define i64 @test557(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test557:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB557_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB557_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB557_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB557_1
 ; PPC64LE-NEXT:  .LBB557_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") release
   ret i64 %ret
 }
 
 define i64 @test558(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test558:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB558_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB558_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB558_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB558_1
 ; PPC64LE-NEXT:  .LBB558_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") acq_rel
   ret i64 %ret
 }
 
 define i64 @test559(i64* %ptr, i64 %val) {
 ; PPC64LE-LABEL: test559:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB559_1:
 ; PPC64LE-NEXT:    ldarx 5, 0, 3
-; PPC64LE-NEXT:    cmpld 4, 5
-; PPC64LE-NEXT:    bge 0, .LBB559_3
+; PPC64LE-NEXT:    cmpld 5, 4
+; PPC64LE-NEXT:    blt 0, .LBB559_3
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stdcx. 4, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB559_1
 ; PPC64LE-NEXT:  .LBB559_3:
 ; PPC64LE-NEXT:    mr 3, 5
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:    blr
   %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") seq_cst

llvm/test/CodeGen/PowerPC/atomics.ll

 ; PPC32-LABEL: cas_strong_i8_sc_sc:
 ; PPC32:       # %bb.0:
 ; PPC32-NEXT:    rlwinm r8, r3, 3, 27, 28
 ; PPC32-NEXT:    li r5, 1
 ; PPC32-NEXT:    li r6, 0
 ; PPC32-NEXT:    li r7, 255
 ; PPC32-NEXT:    rlwinm r4, r3, 0, 0, 29
 ; PPC32-NEXT:    xori r3, r8, 24
-; PPC32-NEXT:    slw r5, r5, r3
-; PPC32-NEXT:    slw r8, r6, r3
-; PPC32-NEXT:    slw r6, r7, r3
-; PPC32-NEXT:    and r7, r5, r6
-; PPC32-NEXT:    and r8, r8, r6
+; PPC32-NEXT:    slw r8, r5, r3
+; PPC32-NEXT:    slw r9, r6, r3
+; PPC32-NEXT:    slw r5, r7, r3
+; PPC32-NEXT:    and r6, r8, r5
+; PPC32-NEXT:    and r7, r9, r5
 ; PPC32-NEXT:    sync
 ; PPC32-NEXT:  .LBB8_1:
 ; PPC32-NEXT:    lwarx r9, 0, r4
-; PPC32-NEXT:    and r5, r9, r6
-; PPC32-NEXT:    cmpw r5, r8
+; PPC32-NEXT:    and r8, r9, r5
+; PPC32-NEXT:    cmpw r8, r7
 ; PPC32-NEXT:    bne cr0, .LBB8_3
 ; PPC32-NEXT:  # %bb.2:
-; PPC32-NEXT:    andc r9, r9, r6
-; PPC32-NEXT:    or r9, r9, r7
+; PPC32-NEXT:    andc r9, r9, r5
+; PPC32-NEXT:    or r9, r9, r6
 ; PPC32-NEXT:    stwcx. r9, 0, r4
 ; PPC32-NEXT:    bne cr0, .LBB8_1
-; PPC32-NEXT:    b .LBB8_4
 ; PPC32-NEXT:  .LBB8_3:
-; PPC32-NEXT:    stwcx. r9, 0, r4
-; PPC32-NEXT:  .LBB8_4:
-; PPC32-NEXT:    srw r3, r5, r3
+; PPC32-NEXT:    srw r3, r8, r3
 ; PPC32-NEXT:    lwsync
 ; PPC32-NEXT:    blr
 ;
 ; PPC64-LABEL: cas_strong_i8_sc_sc:
 ; PPC64:       # %bb.0:
 ; PPC64-NEXT:    rlwinm r8, r3, 3, 27, 28
 ; PPC64-NEXT:    li r5, 1
 ; PPC64-NEXT:    li r6, 0
 ; PPC64-NEXT:    li r7, 255
 ; PPC64-NEXT:    rldicr r4, r3, 0, 61
 ; PPC64-NEXT:    xori r3, r8, 24
-; PPC64-NEXT:    slw r5, r5, r3
-; PPC64-NEXT:    slw r8, r6, r3
-; PPC64-NEXT:    slw r6, r7, r3
-; PPC64-NEXT:    and r7, r5, r6
-; PPC64-NEXT:    and r8, r8, r6
+; PPC64-NEXT:    slw r8, r5, r3
+; PPC64-NEXT:    slw r9, r6, r3
+; PPC64-NEXT:    slw r5, r7, r3
+; PPC64-NEXT:    and r6, r8, r5
+; PPC64-NEXT:    and r7, r9, r5
 ; PPC64-NEXT:    sync
 ; PPC64-NEXT:  .LBB8_1:
 ; PPC64-NEXT:    lwarx r9, 0, r4
-; PPC64-NEXT:    and r5, r9, r6
-; PPC64-NEXT:    cmpw r5, r8
+; PPC64-NEXT:    and r8, r9, r5
+; PPC64-NEXT:    cmpw r8, r7
 ; PPC64-NEXT:    bne cr0, .LBB8_3
 ; PPC64-NEXT:  # %bb.2:
-; PPC64-NEXT:    andc r9, r9, r6
-; PPC64-NEXT:    or r9, r9, r7
+; PPC64-NEXT:    andc r9, r9, r5
+; PPC64-NEXT:    or r9, r9, r6
 ; PPC64-NEXT:    stwcx. r9, 0, r4
 ; PPC64-NEXT:    bne cr0, .LBB8_1
-; PPC64-NEXT:    b .LBB8_4
 ; PPC64-NEXT:  .LBB8_3:
-; PPC64-NEXT:    stwcx. r9, 0, r4
-; PPC64-NEXT:  .LBB8_4:
-; PPC64-NEXT:    srw r3, r5, r3
+; PPC64-NEXT:    srw r3, r8, r3
 ; PPC64-NEXT:    lwsync
 ; PPC64-NEXT:    blr
   %val = cmpxchg i8* %mem, i8 0, i8 1 seq_cst seq_cst
   %loaded = extractvalue { i8, i1} %val, 0
   ret i8 %loaded
 }
 define i16 @cas_weak_i16_acquire_acquire(i16* %mem) {
 ; PPC32-LABEL: cas_weak_i16_acquire_acquire:
 ; PPC32:       # %bb.0:
 ; PPC32-NEXT:    li r6, 0
 ; PPC32-NEXT:    rlwinm r4, r3, 3, 27, 27
 ; PPC32-NEXT:    li r5, 1
 ; PPC32-NEXT:    ori r7, r6, 65535
 ; PPC32-NEXT:    xori r4, r4, 16
 ; PPC32-NEXT:    slw r8, r5, r4
 ; PPC32-NEXT:    slw r9, r6, r4
 ; PPC32-NEXT:    slw r5, r7, r4
 ; PPC32-NEXT:    rlwinm r3, r3, 0, 0, 29
 ; PPC32-NEXT:    and r6, r8, r5
-; PPC32-NEXT:    and r8, r9, r5
+; PPC32-NEXT:    and r7, r9, r5
 ; PPC32-NEXT:  .LBB9_1:
 ; PPC32-NEXT:    lwarx r9, 0, r3
-; PPC32-NEXT:    and r7, r9, r5
-; PPC32-NEXT:    cmpw r7, r8
+; PPC32-NEXT:    and r8, r9, r5
+; PPC32-NEXT:    cmpw r8, r7
 ; PPC32-NEXT:    bne cr0, .LBB9_3
 ; PPC32-NEXT:  # %bb.2:
 ; PPC32-NEXT:    andc r9, r9, r5
 ; PPC32-NEXT:    or r9, r9, r6
 ; PPC32-NEXT:    stwcx. r9, 0, r3
 ; PPC32-NEXT:    bne cr0, .LBB9_1
-; PPC32-NEXT:    b .LBB9_4
 ; PPC32-NEXT:  .LBB9_3:
-; PPC32-NEXT:    stwcx. r9, 0, r3
-; PPC32-NEXT:  .LBB9_4:
-; PPC32-NEXT:    srw r3, r7, r4
+; PPC32-NEXT:    srw r3, r8, r4
 ; PPC32-NEXT:    lwsync
 ; PPC32-NEXT:    blr
 ;
 ; PPC64-LABEL: cas_weak_i16_acquire_acquire:
 ; PPC64:       # %bb.0:
 ; PPC64-NEXT:    li r6, 0
 ; PPC64-NEXT:    rlwinm r4, r3, 3, 27, 27
 ; PPC64-NEXT:    li r5, 1
 ; PPC64-NEXT:    ori r7, r6, 65535
 ; PPC64-NEXT:    xori r4, r4, 16
 ; PPC64-NEXT:    slw r8, r5, r4
 ; PPC64-NEXT:    slw r9, r6, r4
 ; PPC64-NEXT:    slw r5, r7, r4
 ; PPC64-NEXT:    rldicr r3, r3, 0, 61
 ; PPC64-NEXT:    and r6, r8, r5
-; PPC64-NEXT:    and r8, r9, r5
+; PPC64-NEXT:    and r7, r9, r5
 ; PPC64-NEXT:  .LBB9_1:
 ; PPC64-NEXT:    lwarx r9, 0, r3
-; PPC64-NEXT:    and r7, r9, r5
-; PPC64-NEXT:    cmpw r7, r8
+; PPC64-NEXT:    and r8, r9, r5
+; PPC64-NEXT:    cmpw r8, r7
 ; PPC64-NEXT:    bne cr0, .LBB9_3
 ; PPC64-NEXT:  # %bb.2:
 ; PPC64-NEXT:    andc r9, r9, r5
 ; PPC64-NEXT:    or r9, r9, r6
 ; PPC64-NEXT:    stwcx. r9, 0, r3
 ; PPC64-NEXT:    bne cr0, .LBB9_1
-; PPC64-NEXT:    b .LBB9_4
 ; PPC64-NEXT:  .LBB9_3:
-; PPC64-NEXT:    stwcx. r9, 0, r3
-; PPC64-NEXT:  .LBB9_4:
-; PPC64-NEXT:    srw r3, r7, r4
+; PPC64-NEXT:    srw r3, r8, r4
 ; PPC64-NEXT:    lwsync
 ; PPC64-NEXT:    blr
   %val = cmpxchg weak i16* %mem, i16 0, i16 1 acquire acquire
   %loaded = extractvalue { i16, i1} %val, 0
   ret i16 %loaded
 }
 define i32 @cas_strong_i32_acqrel_acquire(i32* %mem) {
 ; CHECK-LABEL: cas_strong_i32_acqrel_acquire:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    li r6, 0
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:  .LBB10_1:
 ; CHECK-NEXT:    lwarx r4, 0, r3
-; CHECK-NEXT:    cmpw r6, r4
+; CHECK-NEXT:    cmpwi r4, 0
 ; CHECK-NEXT:    bne cr0, .LBB10_3
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:    stwcx. r5, 0, r3
 ; CHECK-NEXT:    bne cr0, .LBB10_1
-; CHECK-NEXT:    b .LBB10_4
 ; CHECK-NEXT:  .LBB10_3:
-; CHECK-NEXT:    stwcx. r4, 0, r3
-; CHECK-NEXT:  .LBB10_4:
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    blr
   %val = cmpxchg i32* %mem, i32 0, i32 1 acq_rel acquire
   %loaded = extractvalue { i32, i1} %val, 0
   ret i32 %loaded
 }
 define i64 @cas_weak_i64_release_monotonic(i64* %mem) {

 ; PPC32-NEXT:    lwz r0, 20(r1)
 ; PPC32-NEXT:    addi r1, r1, 16
 ; PPC32-NEXT:    mtlr r0
 ; PPC32-NEXT:    blr
 ;
 ; PPC64-LABEL: cas_weak_i64_release_monotonic:
 ; PPC64:       # %bb.0:
 ; PPC64-NEXT:    li r5, 1
-; PPC64-NEXT:    li r6, 0
 ; PPC64-NEXT:    lwsync
 ; PPC64-NEXT:  .LBB11_1:
 ; PPC64-NEXT:    ldarx r4, 0, r3
-; PPC64-NEXT:    cmpd r6, r4
-; PPC64-NEXT:    bne cr0, .LBB11_4
+; PPC64-NEXT:    cmpdi r4, 0
+; PPC64-NEXT:    bne cr0, .LBB11_3
 ; PPC64-NEXT:  # %bb.2:
 ; PPC64-NEXT:    stdcx. r5, 0, r3
 ; PPC64-NEXT:    bne cr0, .LBB11_1
-; PPC64-NEXT:  # %bb.3:
-; PPC64-NEXT:    mr r3, r4
-; PPC64-NEXT:    blr
-; PPC64-NEXT:  .LBB11_4:
-; PPC64-NEXT:    stdcx. r4, 0, r3
+; PPC64-NEXT:  .LBB11_3:
 ; PPC64-NEXT:    mr r3, r4
 ; PPC64-NEXT:    blr
   %val = cmpxchg weak i64* %mem, i64 0, i64 1 release monotonic
   %loaded = extractvalue { i64, i1} %val, 0
   ret i64 %loaded
 }
 
 ; AtomicRMW

llvm/test/CodeGen/PowerPC/branch-on-store-cond.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+define dso_local zeroext i8 @test1(ptr noundef %addr, i8 noundef zeroext %newval) local_unnamed_addr #0 {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    std 0, 16(1)
+; CHECK-NEXT:    stdu 1, -32(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    stbcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %if.then
+; CHECK-NEXT:    bl dummy
+; CHECK-NEXT:    nop
+; CHECK-NEXT:  .LBB0_2: # %if.end
+; CHECK-NEXT:    li 3, 55
+; CHECK-NEXT:    addi 1, 1, 32
+; CHECK-NEXT:    ld 0, 16(1)
+; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX-LABEL: test1:
+; CHECK-AIX:       # %bb.0: # %entry
+; CHECK-AIX-NEXT:    mflr 0
+; CHECK-AIX-NEXT:    std 0, 16(1)
+; CHECK-AIX-NEXT:    stdu 1, -112(1)
+; CHECK-AIX-NEXT:    stbcx. 4, 0, 3
+; CHECK-AIX-NEXT:    bne 0, L..BB0_2
+; CHECK-AIX-NEXT:  # %bb.1: # %if.then
+; CHECK-AIX-NEXT:    bl .dummy[PR]
+; CHECK-AIX-NEXT:    nop
+; CHECK-AIX-NEXT:  L..BB0_2: # %if.end
+; CHECK-AIX-NEXT:    li 3, 55
+; CHECK-AIX-NEXT:    addi 1, 1, 112
+; CHECK-AIX-NEXT:    ld 0, 16(1)
+; CHECK-AIX-NEXT:    mtlr 0
+; CHECK-AIX-NEXT:    blr
+entry:
+  %conv = zext i8 %newval to i32
+  %0 = tail call i32 @llvm.ppc.stbcx(ptr %addr, i32 %conv)
+  %tobool.not = icmp eq i32 %0, 0
+  br i1 %tobool.not, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  tail call void @dummy() #3
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i8 55
+}
+
+define dso_local signext i16 @test2(ptr noundef %addr, i16 noundef signext %newval) local_unnamed_addr #0 {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    std 0, 16(1)
+; CHECK-NEXT:    stdu 1, -32(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    sthcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB1_2
+; CHECK-NEXT:  # %bb.1: # %if.then
+; CHECK-NEXT:    bl dummy
+; CHECK-NEXT:    nop
+; CHECK-NEXT:  .LBB1_2: # %if.end
+; CHECK-NEXT:    li 3, 55
+; CHECK-NEXT:    addi 1, 1, 32
+; CHECK-NEXT:    ld 0, 16(1)
+; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX-LABEL: test2:
+; CHECK-AIX:       # %bb.0: # %entry
+; CHECK-AIX-NEXT:    mflr 0
+; CHECK-AIX-NEXT:    std 0, 16(1)
+; CHECK-AIX-NEXT:    stdu 1, -112(1)
+; CHECK-AIX-NEXT:    sthcx. 4, 0, 3
+; CHECK-AIX-NEXT:    bne 0, L..BB1_2
+; CHECK-AIX-NEXT:  # %bb.1: # %if.then
+; CHECK-AIX-NEXT:    bl .dummy[PR]
+; CHECK-AIX-NEXT:    nop
+; CHECK-AIX-NEXT:  L..BB1_2: # %if.end
+; CHECK-AIX-NEXT:    li 3, 55
+; CHECK-AIX-NEXT:    addi 1, 1, 112
+; CHECK-AIX-NEXT:    ld 0, 16(1)
+; CHECK-AIX-NEXT:    mtlr 0
+; CHECK-AIX-NEXT:    blr
+entry:
+  %0 = sext i16 %newval to i32
+  %1 = tail call i32 @llvm.ppc.sthcx(ptr %addr, i32 %0)
+  %tobool.not = icmp eq i32 %1, 0
+  br i1 %tobool.not, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  tail call void @dummy() #3
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i16 55
+}
+
+define dso_local signext i32 @test3(ptr noundef %addr, i32 noundef signext %newval) local_unnamed_addr #0 {
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    std 0, 16(1)
+; CHECK-NEXT:    stdu 1, -32(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    stwcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB2_2
+; CHECK-NEXT:  # %bb.1: # %if.then
+; CHECK-NEXT:    bl dummy
+; CHECK-NEXT:    nop
+; CHECK-NEXT:  .LBB2_2: # %if.end
+; CHECK-NEXT:    li 3, 55
+; CHECK-NEXT:    addi 1, 1, 32
+; CHECK-NEXT:    ld 0, 16(1)
+; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX-LABEL: test3:
+; CHECK-AIX:       # %bb.0: # %entry
+; CHECK-AIX-NEXT:    mflr 0
+; CHECK-AIX-NEXT:    std 0, 16(1)
+; CHECK-AIX-NEXT:    stdu 1, -112(1)
+; CHECK-AIX-NEXT:    stwcx. 4, 0, 3
+; CHECK-AIX-NEXT:    bne 0, L..BB2_2
+; CHECK-AIX-NEXT:  # %bb.1: # %if.then
+; CHECK-AIX-NEXT:    bl .dummy[PR]
+; CHECK-AIX-NEXT:    nop
+; CHECK-AIX-NEXT:  L..BB2_2: # %if.end
+; CHECK-AIX-NEXT:    li 3, 55
+; CHECK-AIX-NEXT:    addi 1, 1, 112
+; CHECK-AIX-NEXT:    ld 0, 16(1)
+; CHECK-AIX-NEXT:    mtlr 0
+; CHECK-AIX-NEXT:    blr
+entry:
+  %0 = tail call i32 @llvm.ppc.stwcx(ptr %addr, i32 %newval)
+  %tobool.not = icmp eq i32 %0, 0
+  br i1 %tobool.not, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  tail call void @dummy() #3
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i32 55
+}
+
+define dso_local i64 @test4(ptr noundef %addr, i64 noundef %newval) local_unnamed_addr #0 {
+; CHECK-LABEL: test4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr 0
+; CHECK-NEXT:    std 0, 16(1)
+; CHECK-NEXT:    stdu 1, -32(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset lr, 16
+; CHECK-NEXT:    stdcx. 4, 0, 3
+; CHECK-NEXT:    bne 0, .LBB3_2
+; CHECK-NEXT:  # %bb.1: # %if.then
+; CHECK-NEXT:    bl dummy
+; CHECK-NEXT:    nop
+; CHECK-NEXT:  .LBB3_2: # %if.end
+; CHECK-NEXT:    li 3, 55
+; CHECK-NEXT:    addi 1, 1, 32
+; CHECK-NEXT:    ld 0, 16(1)
+; CHECK-NEXT:    mtlr 0
+; CHECK-NEXT:    blr
+;
+; CHECK-AIX-LABEL: test4:
+; CHECK-AIX:       # %bb.0: # %entry
+; CHECK-AIX-NEXT:    mflr 0
+; CHECK-AIX-NEXT:    std 0, 16(1)
+; CHECK-AIX-NEXT:    stdu 1, -112(1)
+; CHECK-AIX-NEXT:    stdcx. 4, 0, 3
+; CHECK-AIX-NEXT:    bne 0, L..BB3_2
+; CHECK-AIX-NEXT:  # %bb.1: # %if.then
+; CHECK-AIX-NEXT:    bl .dummy[PR]
+; CHECK-AIX-NEXT:    nop
+; CHECK-AIX-NEXT:  L..BB3_2: # %if.end
+; CHECK-AIX-NEXT:    li 3, 55
+; CHECK-AIX-NEXT:    addi 1, 1, 112
+; CHECK-AIX-NEXT:    ld 0, 16(1)
+; CHECK-AIX-NEXT:    mtlr 0
+; CHECK-AIX-NEXT:    blr
+entry:
+  %0 = tail call i32 @llvm.ppc.stdcx(ptr %addr, i64 %newval)
+  %tobool.not = icmp eq i32 %0, 0
+  br i1 %tobool.not, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  tail call void @dummy() #3
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i64 55
+}
+
+declare i32 @llvm.ppc.stbcx(ptr, i32) #1
+declare i32 @llvm.ppc.sthcx(ptr, i32) #1
+declare i32 @llvm.ppc.stwcx(ptr, i32) #1
+declare i32 @llvm.ppc.stdcx(ptr, i64) #1
+declare void @dummy(...) local_unnamed_addr #2

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
 ; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
 
 ; Function Attrs: nounwind uwtable
 define dso_local signext i32 @main() local_unnamed_addr {
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    li 3, -1
 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    std 3, -8(1)
 ; CHECK-NEXT:    addi 3, 1, -8
-; CHECK-NEXT:    .p2align 5
+; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_1: # %do.body
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    ldarx 5, 0, 3
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    stdcx. 4, 0, 3
-; CHECK-NEXT:    mfocrf 5, 128
-; CHECK-NEXT:    srwi 5, 5, 28
-; CHECK-NEXT:    cmplwi 5, 0
-; CHECK-NEXT:    beq 0, .LBB0_1
+; CHECK-NEXT:    bne 0, .LBB0_1
 ; CHECK-NEXT:  # %bb.2: # %do.end
 ; CHECK-NEXT:    ld 3, -8(1)
 ; CHECK-NEXT:    li 4, 55
 ; CHECK-NEXT:    cmpldi 3, 0
 ; CHECK-NEXT:    li 3, 66
 ; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-AIX-LABEL: main:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    li 3, -1
 ; CHECK-AIX-NEXT:    li 4, 0
 ; CHECK-AIX-NEXT:    std 3, -8(1)
 ; CHECK-AIX-NEXT:    addi 3, 1, -8
-; CHECK-AIX-NEXT:    .align 5
+; CHECK-AIX-NEXT:    .align 4
 ; CHECK-AIX-NEXT:  L..BB0_1: # %do.body
 ; CHECK-AIX-NEXT:    #
 ; CHECK-AIX-NEXT:    #APP
 ; CHECK-AIX-NEXT:    ldarx 5, 0, 3
 ; CHECK-AIX-NEXT:    #NO_APP
 ; CHECK-AIX-NEXT:    stdcx. 4, 0, 3
-; CHECK-AIX-NEXT:    mfocrf 5, 128
-; CHECK-AIX-NEXT:    srwi 5, 5, 28
-; CHECK-AIX-NEXT:    cmplwi 5, 0
-; CHECK-AIX-NEXT:    beq 0, L..BB0_1
+; CHECK-AIX-NEXT:    bne 0, L..BB0_1
 ; CHECK-AIX-NEXT:  # %bb.2: # %do.end
 ; CHECK-AIX-NEXT:    ld 3, -8(1)
 ; CHECK-AIX-NEXT:    li 4, 55
 ; CHECK-AIX-NEXT:    cmpldi 3, 0
 ; CHECK-AIX-NEXT:    li 3, 66
 ; CHECK-AIX-NEXT:    iseleq 3, 4, 3
 ; CHECK-AIX-NEXT:    blr
 entry:

llvm/test/CodeGen/PowerPC/loop-comment.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s -check-prefix=PPC64LE
 
 define void @test(i8* %ptr, i8 %cmp, i8 %val) {
 ; PPC64LE-LABEL: test:
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:    clrlwi 4, 4, 24
 ; PPC64LE-NEXT:  .LBB0_1:
 ; PPC64LE-NEXT:    lbarx 6, 0, 3
-; PPC64LE-NEXT:    cmpw 4, 6
-; PPC64LE-NEXT:    bne 0, .LBB0_3
+; PPC64LE-NEXT:    cmpw 6, 4
+; PPC64LE-NEXT:    bnelr 0
 ; PPC64LE-NEXT:  # %bb.2:
 ; PPC64LE-NEXT:    stbcx. 5, 0, 3
-; PPC64LE-NEXT:    beqlr 0
-; PPC64LE-NEXT:    b .LBB0_1
-; PPC64LE-NEXT:  .LBB0_3:
-; PPC64LE-NEXT:    stbcx. 6, 0, 3
+; PPC64LE-NEXT:    bne 0, .LBB0_1
+; PPC64LE-NEXT:  # %bb.3:
 ; PPC64LE-NEXT:    blr
   %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
   ret void
 }

llvm/test/CodeGen/PowerPC/pr30451.ll

 ; RUN: llc < %s -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown | FileCheck %s
 define i8 @atomic_min_i8() {
     top:
       %0 = alloca i8, align 2
       %1 = bitcast i8* %0 to i8*
       call void @llvm.lifetime.start.p0i8(i64 2, i8* %1)
       store i8 -1, i8* %0, align 2
       %2 = atomicrmw min i8* %0, i8 0 acq_rel
       %3 = load atomic i8, i8* %0 acquire, align 8
       call void @llvm.lifetime.end.p0i8(i64 2, i8* %1)
       ret i8 %3
 ; CHECK-LABEL: atomic_min_i8
 ; CHECK: lbarx [[DST:[0-9]+]],
 ; CHECK-NEXT: extsb [[EXT:[0-9]+]], [[DST]]
-; CHECK-NEXT: cmpw {{[0-9]+}}, [[EXT]]
-; CHECK-NEXT: bge 0
+; CHECK-NEXT: cmpw [[EXT]], {{[0-9]+}}
+; CHECK-NEXT: blt 0
 }
 define i16 @atomic_min_i16() {
     top:
       %0 = alloca i16, align 2
       %1 = bitcast i16* %0 to i8*
       call void @llvm.lifetime.start.p0i8(i64 2, i8* %1)
       store i16 -1, i16* %0, align 2
       %2 = atomicrmw min i16* %0, i16 0 acq_rel
       %3 = load atomic i16, i16* %0 acquire, align 8
       call void @llvm.lifetime.end.p0i8(i64 2, i8* %1)
       ret i16 %3
 ; CHECK-LABEL: atomic_min_i16
 ; CHECK: lharx [[DST:[0-9]+]],
 ; CHECK-NEXT: extsh [[EXT:[0-9]+]], [[DST]]
-; CHECK-NEXT: cmpw {{[0-9]+}}, [[EXT]]
-; CHECK-NEXT: bge 0
+; CHECK-NEXT: cmpw [[EXT]], {{[0-9]+}}
+; CHECK-NEXT: blt 0
 }
 
 define i8 @atomic_max_i8() {
     top:
       %0 = alloca i8, align 2
       %1 = bitcast i8* %0 to i8*
       call void @llvm.lifetime.start.p0i8(i64 2, i8* %1)
       store i8 -1, i8* %0, align 2
       %2 = atomicrmw max i8* %0, i8 0 acq_rel
       %3 = load atomic i8, i8* %0 acquire, align 8
       call void @llvm.lifetime.end.p0i8(i64 2, i8* %1)
       ret i8 %3
 ; CHECK-LABEL: atomic_max_i8
 ; CHECK: lbarx [[DST:[0-9]+]],
 ; CHECK-NEXT: extsb [[EXT:[0-9]+]], [[DST]]
-; CHECK-NEXT: cmpw {{[0-9]+}}, [[EXT]]
-; CHECK-NEXT: ble 0
+; CHECK-NEXT: cmpw [[EXT]], {{[0-9]+}}
+; CHECK-NEXT: bgt 0
 }
 define i16 @atomic_max_i16() {
     top:
       %0 = alloca i16, align 2
       %1 = bitcast i16* %0 to i8*
       call void @llvm.lifetime.start.p0i8(i64 2, i8* %1)
       store i16 -1, i16* %0, align 2
       %2 = atomicrmw max i16* %0, i16 0 acq_rel
       %3 = load atomic i16, i16* %0 acquire, align 8
       call void @llvm.lifetime.end.p0i8(i64 2, i8* %1)
       ret i16 %3
 ; CHECK-LABEL: atomic_max_i16
 ; CHECK: lharx [[DST:[0-9]+]],
 ; CHECK-NEXT: extsh [[EXT:[0-9]+]], [[DST]]
-; CHECK-NEXT: cmpw {{[0-9]+}}, [[EXT]]
-; CHECK-NEXT: ble 0
+; CHECK-NEXT: cmpw [[EXT]], {{[0-9]+}}
+; CHECK-NEXT: bgt 0
 }
 
 declare void @llvm.lifetime.start.p0i8(i64, i8*)
 declare void @llvm.lifetime.end.p0i8(i64, i8*)

llvm/test/CodeGen/PowerPC/sign-ext-atomics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s
 define i16 @SEXTParam(i16 signext %0) #0 {
 ; CHECK-LABEL: SEXTParam:
 ; CHECK:       # %bb.0: # %top
 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    sth 4, -4(1)
 ; CHECK-NEXT:    addi 4, 1, -4
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:  .LBB0_1: # %top
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lharx 5, 0, 4
 ; CHECK-NEXT:    extsh 5, 5
-; CHECK-NEXT:    cmpw 3, 5
-; CHECK-NEXT:    bge 0, .LBB0_3
+; CHECK-NEXT:    cmpw 5, 3
+; CHECK-NEXT:    blt 0, .LBB0_3
 ; CHECK-NEXT:  # %bb.2: # %top
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    sthcx. 3, 0, 4
 ; CHECK-NEXT:    bne 0, .LBB0_1
 ; CHECK-NEXT:  .LBB0_3: # %top
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    lhz 3, -4(1)
 ; CHECK-NEXT:    cmpd 7, 3, 3

 ; CHECK-NEXT:    extsh 3, 3
 ; CHECK-NEXT:    sth 4, -4(1)
 ; CHECK-NEXT:    addi 4, 1, -4
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:  .LBB1_1: # %top
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lharx 5, 0, 4
 ; CHECK-NEXT:    extsh 5, 5
-; CHECK-NEXT:    cmpw 3, 5
-; CHECK-NEXT:    bge 0, .LBB1_3
+; CHECK-NEXT:    cmpw 5, 3
+; CHECK-NEXT:    blt 0, .LBB1_3
 ; CHECK-NEXT:  # %bb.2: # %top
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    sthcx. 3, 0, 4
 ; CHECK-NEXT:    bne 0, .LBB1_1
 ; CHECK-NEXT:  .LBB1_3: # %top
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    lhz 3, -4(1)
 ; CHECK-NEXT:    cmpd 7, 3, 3

 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    sth 4, -4(1)
 ; CHECK-NEXT:    addi 4, 1, -4
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:  .LBB2_1: # %top
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lharx 5, 0, 4
 ; CHECK-NEXT:    extsh 5, 5
-; CHECK-NEXT:    cmpw 3, 5
-; CHECK-NEXT:    bge 0, .LBB2_3
+; CHECK-NEXT:    cmpw 5, 3
+; CHECK-NEXT:    blt 0, .LBB2_3
 ; CHECK-NEXT:  # %bb.2: # %top
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    sthcx. 3, 0, 4
 ; CHECK-NEXT:    bne 0, .LBB2_1
 ; CHECK-NEXT:  .LBB2_3: # %top
 ; CHECK-NEXT:    lwsync
 ; CHECK-NEXT:    lhz 3, -4(1)
 ; CHECK-NEXT:    cmpd 7, 3, 3