diff --git a/clang/include/clang/Basic/TargetBuiltins.h b/clang/include/clang/Basic/TargetBuiltins.h
--- a/clang/include/clang/Basic/TargetBuiltins.h
+++ b/clang/include/clang/Basic/TargetBuiltins.h
@@ -368,6 +368,8 @@
     bool isZero() const { return Flags & IsZero; }
     bool isLoadReg() const { return Flags & IsLoadReg; }
     bool isStoreReg() const { return Flags & IsStoreReg; }
+    bool isOverloadNone() const { return Flags & IsOverloadNone; }
+    bool isOverloadDefault() const { return !(Flags & OverloadKindMask); }
 
     uint64_t getBits() const { return Flags; }
     bool isFlagSet(uint64_t Flag) const { return Flags & Flag; }
diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td
--- a/clang/include/clang/Basic/arm_sme.td
+++ b/clang/include/clang/Basic/arm_sme.td
@@ -102,3 +102,11 @@
 
 def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone, "aarch64_sme_zero", [IsZero, IsOverloadNone, IsStreamingCompatible, IsSharedZA]>;
 def SVZERO_ZA      : SInst<"svzero_za", "v", "", MergeNone, "aarch64_sme_zero", [IsZero, IsOverloadNone, IsStreamingCompatible, IsSharedZA]>;
+
+////////////////////////////////////////////////////////////////////////////////
+// SME - Counting elements in a streaming vector
+
+def SVCNTSB : SInst<"svcntsb", "nv", "", MergeNone, "aarch64_sme_cntsb", [IsOverloadNone, IsStreamingCompatible, IsPreservesZA]>;
+def SVCNTSH : SInst<"svcntsh", "nv", "", MergeNone, "aarch64_sme_cntsh", [IsOverloadNone, IsStreamingCompatible, IsPreservesZA]>;
+def SVCNTSW : SInst<"svcntsw", "nv", "", MergeNone, "aarch64_sme_cntsw", [IsOverloadNone, IsStreamingCompatible, IsPreservesZA]>;
+def SVCNTSD : SInst<"svcntsd", "nv", "", MergeNone, "aarch64_sme_cntsd", [IsOverloadNone, IsStreamingCompatible, IsPreservesZA]>;
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -9309,6 +9309,19 @@
   return Builder.CreateAdd(Base, CastOffset, "tileslice");
 }
 
+SmallVector<llvm::Type *, 2>
+CodeGenFunction::getSMEOverloadTypes(const SMETypeFlags &TypeFlags,
+                                     llvm::Type *ResultType,
+                                     ArrayRef<Value *> Ops) {
+  if (TypeFlags.isOverloadNone())
+    return {};
+
+  llvm::Type *DefaultType = getSVEType(TypeFlags);
+
+  assert(TypeFlags.isOverloadDefault() && "Unexpected value for overloads");
+  return {DefaultType};
+}
+
 // Return the llvm vector type corresponding to the specified element TypeFlags.
 llvm::ScalableVectorType *
 CodeGenFunction::getSVEType(const SMETypeFlags &TypeFlags) {
@@ -9893,6 +9906,7 @@
   getContext().GetBuiltinType(BuiltinID, Error, &ICEArguments);
   assert(Error == ASTContext::GE_None && "Should not codegen an error");
 
+  llvm::Type *Ty = ConvertType(E->getType());
   llvm::SmallVector<Value *, 4> Ops;
   for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) {
     if ((ICEArguments & (1 << i)) == 0)
@@ -9923,6 +9937,12 @@
     return EmitSMEZero(TypeFlags, Ops, Builtin->LLVMIntrinsic);
   else if (TypeFlags.isLoadReg() || TypeFlags.isStoreReg())
     return EmitSMELdrStr(TypeFlags, Ops, Builtin->LLVMIntrinsic);
+  else if (Builtin->LLVMIntrinsic != 0) {
+    Function *F = CGM.getIntrinsic(Builtin->LLVMIntrinsic,
+                                   getSMEOverloadTypes(TypeFlags, Ty, Ops));
+    Value *Call = Builder.CreateCall(F, Ops);
+    return Call;
+  }
 
   /// Should not happen
   return nullptr;
diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -4249,6 +4249,9 @@
                                   unsigned IntID);
   llvm::Value *EmitAArch64SVEBuiltinExpr(unsigned BuiltinID, const CallExpr *E);
 
+  SmallVector<llvm::Type *, 2>
+  getSMEOverloadTypes(const SMETypeFlags &TypeFlags, llvm::Type *ReturnType,
+                      ArrayRef<llvm::Value *> Ops);
   llvm::ScalableVectorType *getSVEType(const SMETypeFlags &TypeFlags);
   llvm::Value *EmitSMELd1St1(SMETypeFlags TypeFlags,
                              llvm::SmallVectorImpl<llvm::Value *> &Ops,
diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
@@ -0,0 +1,46 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX
+// RUN: %clang_cc1 -D__ARM_FEATURE_SME -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s
+
+#include <arm_sme.h>
+
+// CHECK-C-LABEL: @test_svcntsb(
+// CHECK-CXX-LABEL: @_Z12test_svcntsbv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsb()
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+uint64_t test_svcntsb() {
+  return svcntsb();
+}
+
+// CHECK-C-LABEL: @test_svcntsh(
+// CHECK-CXX-LABEL: @_Z12test_svcntshv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsh()
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+uint64_t test_svcntsh() {
+  return svcntsh();
+}
+
+// CHECK-C-LABEL: @test_svcntsw(
+// CHECK-CXX-LABEL: @_Z12test_svcntswv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsw()
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+uint64_t test_svcntsw() {
+  return svcntsw();
+}
+
+// CHECK-C-LABEL: @test_svcntsd(
+// CHECK-CXX-LABEL: @_Z12test_svcntsdv(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sme.cntsd()
+// CHECK-NEXT:    ret i64 [[TMP0]]
+//
+uint64_t test_svcntsd() {
+  return svcntsd();
+}