diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h @@ -46,6 +46,9 @@ bool hasBP(const MachineFunction &MF) const; + bool isCSIpushable(const MachineFunction &MF, + const std::vector &CSI) const; + bool hasReservedCallFrame(const MachineFunction &MF) const override; MachineBasicBlock::iterator eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -221,6 +221,88 @@ return RestoreLibCalls[LibCallID]; } +// Return encoded value for PUSH/POP instruction, representing +// registers to store/load. +static int getPushPopEncoding(const Register MaxReg) { + switch (MaxReg) { + default: + llvm_unreachable("Unexcetped Reg for Push/Pop Inst"); + case /*s11*/ RISCV::X27: + return llvm::RISCVZC::RLISTENCODE::RA_S0_S11; + case /*s9*/ RISCV::X25: + return llvm::RISCVZC::RLISTENCODE::RA_S0_S9; + case /*s8*/ RISCV::X24: + return llvm::RISCVZC::RLISTENCODE::RA_S0_S8; + case /*s7*/ RISCV::X23: + return llvm::RISCVZC::RLISTENCODE::RA_S0_S7; + case /*s6*/ RISCV::X22: + return llvm::RISCVZC::RLISTENCODE::RA_S0_S6; + case /*s5*/ RISCV::X21: + return llvm::RISCVZC::RLISTENCODE::RA_S0_S5; + case /*s4*/ RISCV::X20: + return llvm::RISCVZC::RLISTENCODE::RA_S0_S4; + case /*s3*/ RISCV::X19: + return llvm::RISCVZC::RLISTENCODE::RA_S0_S3; + case /*s2*/ RISCV::X18: + return llvm::RISCVZC::RLISTENCODE::RA_S0_S2; + case /*s1*/ RISCV::X9: + return llvm::RISCVZC::RLISTENCODE::RA_S0_S1; + case /*s0*/ RISCV::X8: + return llvm::RISCVZC::RLISTENCODE::RA_S0; + case /*ra*/ RISCV::X1: + return llvm::RISCVZC::RLISTENCODE::RA; + } +} + +void reallocPushStackFrame(MachineFunction &MF) { + auto *RVFI = MF.getInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + + std::vector CSI = MFI.getCalleeSavedInfo(); + // realloc stack frame for PUSH + size_t NonePushStackOffset = -RVFI->getRVPushStackSize(); + for (const auto &Entry : CSI) { + int FrameIdx = Entry.getFrameIdx(); + Register Reg = Entry.getReg(); + if (!(Reg == RISCV::X26 || RISCV::PGPRRegClass.contains(Reg))) { + NonePushStackOffset -= MFI.getObjectSize(Entry.getFrameIdx()); + MFI.setObjectOffset(FrameIdx, NonePushStackOffset); + } + } +} + +static uint64_t adjSPInPushPop(MachineBasicBlock::iterator MBBI, + uint64_t StackAdj, bool IsPop, bool IsRV64, bool IsEABI) { + + uint64_t Rlist = MBBI->getOperand(0).getImm(); + uint64_t StackAdjBase = RISCVZC::getStackAdjBase(Rlist, IsRV64, IsEABI); + + uint64_t Spimm = (StackAdj - StackAdjBase) / 16; + if (Spimm > 3) + Spimm = 3; + uint64_t PushStack = StackAdjBase + Spimm * 16; + + MBBI->getOperand(1).setImm(Spimm * 16); + MBBI->setFlag(IsPop ? MachineInstr::FrameDestroy : MachineInstr::FrameSetup); + return StackAdj - PushStack; +} + +// Checks if Zcmp PUSH/POP instructions can be used with the given CSI. +bool RISCVFrameLowering::isCSIpushable( + const MachineFunction &MF, const std::vector &CSI) const { + if (!STI.hasStdExtZcmp() || CSI.empty() || + MF.getTarget().Options.DisableFramePointerElim(MF)) + return false; + for (auto &CS : CSI) { + Register Reg = CS.getReg(); + const TargetRegisterClass *RC = + STI.getRegisterInfo()->getMinimalPhysRegClass(Reg); + if (RISCV::PGPRRegClass.hasSubClassEq(RC)) + return true; + } + return false; +} + // Return true if the specified function should have a dedicated frame // pointer register. This is true if frame pointer elimination is // disabled, if it needs dynamic stack realignment, if the function has @@ -309,6 +391,24 @@ return NonLibcallCSI; } +static SmallVector +getNonPushPopCSI(const MachineFunction &MF, + const TargetRegisterInfo *TRI, + const std::vector &CSI, Register &MaxPushPopReg) { + SmallVector NonPushPopCSI; + MaxPushPopReg = RISCV::NoRegister; + + for (auto &CS : CSI) { + Register Reg = CS.getReg(); + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + if (Reg == RISCV::X26 || RISCV::PGPRRegClass.hasSubClassEq(RC)) + MaxPushPopReg = std::max(MaxPushPopReg.id(), Reg.id()); + else + NonPushPopCSI.push_back(CS); + } + return NonPushPopCSI; +} + void RISCVFrameLowering::adjustStackForRVV(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, @@ -468,9 +568,27 @@ RealStackSize = FirstSPAdjustAmount; } - // Allocate space on the stack if necessary. - RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(-StackSize), - MachineInstr::FrameSetup, getStackAlign()); + const auto &CSI = MFI.getCalleeSavedInfo(); + bool PushEnabled = isCSIpushable(MF, CSI); + if (PushEnabled) { + // Use available stack adjustment in push instruction to allocate additional + // stack space. + bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); + bool IsRVE = STI.hasFeature(RISCV::FeatureRVE); + StackSize = adjSPInPushPop(MBBI, StackSize, false, IsRV64, IsRVE); + if (StackSize != 0) { + RI->adjustReg(MBB, next_nodbg(MBBI, MBB.end()), DL, SPReg, SPReg, + StackOffset::getFixed(-StackSize), MachineInstr::FrameSetup, + getStackAlign()); + MBBI = next_nodbg(MBBI, MBB.end()); + reallocPushStackFrame(MF); + } + } else { + // Allocate space on the stack if necessary. + RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, + StackOffset::getFixed(-StackSize), MachineInstr::FrameSetup, + getStackAlign()); + } // Emit ".cfi_def_cfa_offset RealStackSize" unsigned CFIIndex = MF.addFrameInst( @@ -479,15 +597,16 @@ .addCFIIndex(CFIIndex) .setMIFlag(MachineInstr::FrameSetup); - const auto &CSI = MFI.getCalleeSavedInfo(); - - // The frame pointer is callee-saved, and code has been generated for us to - // save it to the stack. We need to skip over the storing of callee-saved - // registers as the frame pointer must be modified after it has been saved - // to the stack, not before. - // FIXME: assumes exactly one instruction is used to save each callee-saved - // register. - std::advance(MBBI, getNonLibcallCSI(MF, CSI).size()); + if (PushEnabled) + std::advance(MBBI, 1); + else + // The frame pointer is callee-saved, and code has been generated for us to + // save it to the stack. We need to skip over the storing of callee-saved + // registers as the frame pointer must be modified after it has been saved + // to the stack, not before. + // FIXME: assumes exactly one instruction is used to save each callee-saved + // register. + std::advance(MBBI, getNonLibcallCSI(MF, CSI).size()); // Iterate over list of callee-saved registers and emit .cfi_offset // directives. @@ -640,7 +759,10 @@ // FIXME: assumes exactly one instruction is used to restore each // callee-saved register. auto LastFrameDestroy = MBBI; - if (!CSI.empty()) + bool PopEnabled = RVFI->isPushable(); + if (PopEnabled) + LastFrameDestroy = prev_nodbg(MBBI, MBB.begin()); + else if (!CSI.empty()) LastFrameDestroy = std::prev(MBBI, CSI.size()); uint64_t StackSize = getStackSizeWithRVVPadding(MF); @@ -686,8 +808,20 @@ StackSize = FirstSPAdjustAmount; // Deallocate stack - RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(StackSize), - MachineInstr::FrameDestroy, getStackAlign()); + if (PopEnabled) { + // Use available stack adjustment in pop instruction to deallocate stack + // space. + bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); + bool IsRVE = STI.hasFeature(RISCV::FeatureRVE); + StackSize = adjSPInPushPop(prev_nodbg(MBBI, MBB.begin()), StackSize, true, IsRV64, IsRVE); + if (StackSize != 0) { + RI->adjustReg(MBB, prev_nodbg(MBBI, MBB.begin()), DL, SPReg, SPReg, + StackOffset::getFixed(StackSize), + MachineInstr::FrameDestroy, getStackAlign()); + } + } else + RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(StackSize), + MachineInstr::FrameDestroy, getStackAlign()); // Emit epilogue for shadow call stack. emitSCSEpilogue(MF, MBB, MBBI, DL); @@ -1223,26 +1357,61 @@ if (MI != MBB.end() && !MI->isDebugInstr()) DL = MI->getDebugLoc(); - const char *SpillLibCall = getSpillLibCallName(*MF, CSI); - if (SpillLibCall) { - // Add spill libcall via non-callee-saved register t0. - BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5) - .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL) - .setMIFlag(MachineInstr::FrameSetup); + // Emmit CM.PUSH with base SPimm & evaluate Push stack + RISCVMachineFunctionInfo *RVFI = MF->getInfo(); + bool Pushable = isCSIpushable(*MF, CSI.vec()); + RVFI->setPushable(Pushable); + if (Pushable) { + bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); + auto *RVFI = MF->getInfo(); + SmallVector NonePushCSI; + Register MaxReg; + + NonePushCSI = getNonPushPopCSI(*MF, TRI, CSI, MaxReg); + + uint64_t PoshPopRegs = CSI.size() - NonePushCSI.size(); + if (MaxReg == RISCV::X26){ + PoshPopRegs += 1; + MaxReg = RISCV::X27; + } + RVFI->setRVPushStackSize(PoshPopRegs * (IsRV64 ? 8 : 4)); + + MachineInstrBuilder PushBuilder = + BuildMI(MBB, MI, DL, TII.get(RISCV::CM_PUSH)); + // Use encoded number to represent registers to spill. + int RegEnc = getPushPopEncoding(MaxReg); + RVFI->setRVPushRlist(RegEnc); + PushBuilder.addImm(RegEnc); + PushBuilder.addImm(0); + + for (auto &CS : NonePushCSI) { + Register Reg = CS.getReg(); + TII.storeRegToStackSlot(MBB, MI, Reg, true, CS.getFrameIdx(), + TRI->getMinimalPhysRegClass(Reg), TRI, + Register()); + } + } else { + const char *SpillLibCall = getSpillLibCallName(*MF, CSI); + if (SpillLibCall) { + // Add spill libcall via non-callee-saved register t0. + BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoCALLReg), RISCV::X5) + .addExternalSymbol(SpillLibCall, RISCVII::MO_CALL) + .setMIFlag(MachineInstr::FrameSetup); - // Add registers spilled in libcall as liveins. - for (auto &CS : CSI) - MBB.addLiveIn(CS.getReg()); - } + // Add registers spilled in libcall as liveins. + for (auto &CS : CSI) + MBB.addLiveIn(CS.getReg()); + } - // Manually spill values not spilled by libcall. - const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI); - for (auto &CS : NonLibcallCSI) { - // Insert the spill to the stack frame. - Register Reg = CS.getReg(); - const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), CS.getFrameIdx(), - RC, TRI, Register()); + // Manually spill values not spilled by libcall. + const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI); + for (auto &CS : NonLibcallCSI) { + // Insert the spill to the stack frame. + Register Reg = CS.getReg(); + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.storeRegToStackSlot(MBB, MI, Reg, !MBB.isLiveIn(Reg), + CS.getFrameIdx(), RC, TRI, Register()); + } } return true; @@ -1256,41 +1425,68 @@ MachineFunction *MF = MBB.getParent(); const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); + RISCVMachineFunctionInfo *RVFI = MF->getInfo(); DebugLoc DL; if (MI != MBB.end() && !MI->isDebugInstr()) DL = MI->getDebugLoc(); - // Manually restore values not restored by libcall. - // Keep the same order as in the prologue. There is no need to reverse the - // order in the epilogue. In addition, the return address will be restored - // first in the epilogue. It increases the opportunity to avoid the - // load-to-use data hazard between loading RA and return by RA. - // loadRegFromStackSlot can insert multiple instructions. - const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI); - for (auto &CS : NonLibcallCSI) { - Register Reg = CS.getReg(); - const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI, - Register()); - assert(MI != MBB.begin() && "loadRegFromStackSlot didn't insert any code!"); - } + if (RVFI->isPushable()) { + Register MaxReg = RISCV::NoRegister; + const auto &NonePushCSI = getNonPushPopCSI(*MF, TRI, CSI, MaxReg); + + for (auto &CS : NonePushCSI) { + Register Reg = CS.getReg(); + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI, + Register()); + assert(MI != MBB.begin() && + "loadRegFromStackSlot didn't insert any code!"); + } - const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI); - if (RestoreLibCall) { - // Add restore libcall via tail call. - MachineBasicBlock::iterator NewMI = - BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL)) - .addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL) - .setMIFlag(MachineInstr::FrameDestroy); - - // Remove trailing returns, since the terminator is now a tail call to the - // restore function. - if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) { - NewMI->copyImplicitOps(*MF, *MI); - MI->eraseFromParent(); + MachineInstrBuilder PopBuilder = + BuildMI(MBB, MI, DL, TII.get(RISCV::CM_POP)); + // Use encoded number to represent registers to restore. + int RegEnc = getPushPopEncoding(MaxReg); + PopBuilder.addImm(RegEnc); + // Calculate SpImm Base adjustment, and SpImm field will be updated + // through adjSPInPushPop. + bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit); + bool IsRVE = STI.hasFeature(RISCV::FeatureRVE); + uint32_t SpImmBase = RISCVZC::getStackAdjBase(RegEnc, IsRV64, IsRVE); + PopBuilder.addImm(SpImmBase); + } else { + // Manually restore values not restored by libcall. + // Keep the same order as in the prologue. There is no need to reverse the + // order in the epilogue. In addition, the return address will be restored + // first in the epilogue. It increases the opportunity to avoid the + // load-to-use data hazard between loading RA and return by RA. + // loadRegFromStackSlot can insert multiple instructions. + const auto &NonLibcallCSI = getNonLibcallCSI(*MF, CSI); + for (auto &CS : NonLibcallCSI) { + Register Reg = CS.getReg(); + const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); + TII.loadRegFromStackSlot(MBB, MI, Reg, CS.getFrameIdx(), RC, TRI, + Register()); + assert(MI != MBB.begin() && + "loadRegFromStackSlot didn't insert any code!"); } - } + const char *RestoreLibCall = getRestoreLibCallName(*MF, CSI); + if (RestoreLibCall) { + // Add restore libcall via tail call. + MachineBasicBlock::iterator NewMI = + BuildMI(MBB, MI, DL, TII.get(RISCV::PseudoTAIL)) + .addExternalSymbol(RestoreLibCall, RISCVII::MO_CALL) + .setMIFlag(MachineInstr::FrameDestroy); + + // Remove trailing returns, since the terminator is now a tail call to the + // restore function. + if (MI != MBB.end() && MI->getOpcode() == RISCV::PseudoRET) { + NewMI->copyImplicitOps(*MF, *MI); + MI->eraseFromParent(); + } + } + } return true; } diff --git a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h --- a/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h +++ b/llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h @@ -71,6 +71,11 @@ /// Registers that have been sign extended from i32. SmallVector SExt32Registers; + /// Size of stack frame for zcmp PUSH/POP + unsigned RVPushStackSize = 0; + int RVPushRlist = llvm::RISCVZC::RLISTENCODE::INVALID_RLIST; + bool RVPushable = false; + public: RISCVMachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {} @@ -107,7 +112,8 @@ // function uses a varargs save area, or is an interrupt handler. return MF.getSubtarget().enableSaveRestore() && VarArgsSaveSize == 0 && !MF.getFrameInfo().hasTailCall() && - !MF.getFunction().hasFnAttribute("interrupt"); + !MF.getFunction().hasFnAttribute("interrupt") && + !MF.getSubtarget().hasStdExtZcmp(); } uint64_t getRVVStackSize() const { return RVVStackSize; } @@ -122,6 +128,15 @@ unsigned getCalleeSavedStackSize() const { return CalleeSavedStackSize; } void setCalleeSavedStackSize(unsigned Size) { CalleeSavedStackSize = Size; } + uint64_t isPushable() const { return RVPushable; } + void setPushable(bool Pushable) { RVPushable = Pushable; } + + int getRVPushRlist() const { return isPushable() ? RVPushRlist : llvm::RISCVZC::RLISTENCODE::INVALID_RLIST; } + void setRVPushRlist(int Rlist) { RVPushRlist = Rlist; } + + uint64_t getRVPushStackSize() const { return isPushable() ? RVPushStackSize : 0; } + void setRVPushStackSize(uint64_t Size) { RVPushStackSize = Size; } + void initializeBaseYamlFields(const yaml::RISCVMachineFunctionInfo &YamlMFI); void addSExt32Register(Register Reg); diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -183,6 +183,16 @@ let RegInfos = XLenRI; } +// Registers saveable by PUSH/POP instruction in Zcmp extension +def PGPR : RegisterClass<"RISCV", [XLenVT], 32, (add + (sequence "X%u", 8, 9), + (sequence "X%u", 18, 25), + X27, + X1 + )> { + let RegInfos = XLenRI; +} + // Floating point registers let RegAltNameIndices = [ABIRegAltName] in { def F0_H : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>; diff --git a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll --- a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll +++ b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll @@ -9,6 +9,10 @@ ; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I-WITH-FP +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmp -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefixes=RV32IZCMP +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmp -verify-machineinstrs -frame-pointer=all < %s \ +; RUN: | FileCheck %s -check-prefixes=RV32IZCMP-WITH-FP ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \ @@ -19,6 +23,10 @@ ; RUN: | FileCheck %s -check-prefix=RV64I ; RUN: llc -mtriple=riscv64 -verify-machineinstrs -frame-pointer=all < %s \ ; RUN: | FileCheck %s -check-prefix=RV64I-WITH-FP +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmp -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefixes=RV64IZCMP +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmp -verify-machineinstrs -frame-pointer=all < %s \ +; RUN: | FileCheck %s -check-prefixes=RV64IZCMP-WITH-FP @var = global [32 x i32] zeroinitializer @@ -249,6 +257,203 @@ ; RV32I-WITH-FP-NEXT: addi sp, sp, 80 ; RV32I-WITH-FP-NEXT: ret ; +; RV32IZCMP-LABEL: callee: +; RV32IZCMP: # %bb.0: +; RV32IZCMP-NEXT: cm.push {ra, s0-s11}, -80 +; RV32IZCMP-NEXT: lui a7, %hi(var) +; RV32IZCMP-NEXT: lw a0, %lo(var)(a7) +; RV32IZCMP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, %lo(var+4)(a7) +; RV32IZCMP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, %lo(var+8)(a7) +; RV32IZCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, %lo(var+12)(a7) +; RV32IZCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: addi a5, a7, %lo(var) +; RV32IZCMP-NEXT: lw a0, 16(a5) +; RV32IZCMP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 20(a5) +; RV32IZCMP-NEXT: sw a0, 4(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw t4, 24(a5) +; RV32IZCMP-NEXT: lw t5, 28(a5) +; RV32IZCMP-NEXT: lw t6, 32(a5) +; RV32IZCMP-NEXT: lw s2, 36(a5) +; RV32IZCMP-NEXT: lw s3, 40(a5) +; RV32IZCMP-NEXT: lw s4, 44(a5) +; RV32IZCMP-NEXT: lw s5, 48(a5) +; RV32IZCMP-NEXT: lw s6, 52(a5) +; RV32IZCMP-NEXT: lw s7, 56(a5) +; RV32IZCMP-NEXT: lw s8, 60(a5) +; RV32IZCMP-NEXT: lw s9, 64(a5) +; RV32IZCMP-NEXT: lw s10, 68(a5) +; RV32IZCMP-NEXT: lw s11, 72(a5) +; RV32IZCMP-NEXT: lw ra, 76(a5) +; RV32IZCMP-NEXT: lw s1, 80(a5) +; RV32IZCMP-NEXT: lw t3, 84(a5) +; RV32IZCMP-NEXT: lw t2, 88(a5) +; RV32IZCMP-NEXT: lw t1, 92(a5) +; RV32IZCMP-NEXT: lw t0, 96(a5) +; RV32IZCMP-NEXT: lw s0, 100(a5) +; RV32IZCMP-NEXT: lw a6, 104(a5) +; RV32IZCMP-NEXT: lw a4, 108(a5) +; RV32IZCMP-NEXT: lw a0, 124(a5) +; RV32IZCMP-NEXT: lw a1, 120(a5) +; RV32IZCMP-NEXT: lw a2, 116(a5) +; RV32IZCMP-NEXT: lw a3, 112(a5) +; RV32IZCMP-NEXT: sw a0, 124(a5) +; RV32IZCMP-NEXT: sw a1, 120(a5) +; RV32IZCMP-NEXT: sw a2, 116(a5) +; RV32IZCMP-NEXT: sw a3, 112(a5) +; RV32IZCMP-NEXT: sw a4, 108(a5) +; RV32IZCMP-NEXT: sw a6, 104(a5) +; RV32IZCMP-NEXT: sw s0, 100(a5) +; RV32IZCMP-NEXT: sw t0, 96(a5) +; RV32IZCMP-NEXT: sw t1, 92(a5) +; RV32IZCMP-NEXT: sw t2, 88(a5) +; RV32IZCMP-NEXT: sw t3, 84(a5) +; RV32IZCMP-NEXT: sw s1, 80(a5) +; RV32IZCMP-NEXT: sw ra, 76(a5) +; RV32IZCMP-NEXT: sw s11, 72(a5) +; RV32IZCMP-NEXT: sw s10, 68(a5) +; RV32IZCMP-NEXT: sw s9, 64(a5) +; RV32IZCMP-NEXT: sw s8, 60(a5) +; RV32IZCMP-NEXT: sw s7, 56(a5) +; RV32IZCMP-NEXT: sw s6, 52(a5) +; RV32IZCMP-NEXT: sw s5, 48(a5) +; RV32IZCMP-NEXT: sw s4, 44(a5) +; RV32IZCMP-NEXT: sw s3, 40(a5) +; RV32IZCMP-NEXT: sw s2, 36(a5) +; RV32IZCMP-NEXT: sw t6, 32(a5) +; RV32IZCMP-NEXT: sw t5, 28(a5) +; RV32IZCMP-NEXT: sw t4, 24(a5) +; RV32IZCMP-NEXT: lw a0, 4(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 20(a5) +; RV32IZCMP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 16(a5) +; RV32IZCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var+12)(a7) +; RV32IZCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var+8)(a7) +; RV32IZCMP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var+4)(a7) +; RV32IZCMP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var)(a7) +; RV32IZCMP-NEXT: cm.pop {ra, s0-s11}, 80 +; RV32IZCMP-NEXT: ret +; +; RV32IZCMP-WITH-FP-LABEL: callee: +; RV32IZCMP-WITH-FP: # %bb.0: +; RV32IZCMP-WITH-FP-NEXT: addi sp, sp, -80 +; RV32IZCMP-WITH-FP-NEXT: sw ra, 76(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s0, 72(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s1, 68(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s2, 64(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s3, 60(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s4, 56(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s5, 52(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s6, 48(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s7, 44(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s8, 40(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s9, 36(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s10, 32(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s11, 28(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: addi s0, sp, 80 +; RV32IZCMP-WITH-FP-NEXT: lui a7, %hi(var) +; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var)(a7) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var+4)(a7) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -60(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var+8)(a7) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -64(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var+12)(a7) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: addi a5, a7, %lo(var) +; RV32IZCMP-WITH-FP-NEXT: lw a0, 16(a5) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 20(a5) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 24(a5) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw t5, 28(a5) +; RV32IZCMP-WITH-FP-NEXT: lw t6, 32(a5) +; RV32IZCMP-WITH-FP-NEXT: lw s2, 36(a5) +; RV32IZCMP-WITH-FP-NEXT: lw s3, 40(a5) +; RV32IZCMP-WITH-FP-NEXT: lw s4, 44(a5) +; RV32IZCMP-WITH-FP-NEXT: lw s5, 48(a5) +; RV32IZCMP-WITH-FP-NEXT: lw s6, 52(a5) +; RV32IZCMP-WITH-FP-NEXT: lw s7, 56(a5) +; RV32IZCMP-WITH-FP-NEXT: lw s8, 60(a5) +; RV32IZCMP-WITH-FP-NEXT: lw s9, 64(a5) +; RV32IZCMP-WITH-FP-NEXT: lw s10, 68(a5) +; RV32IZCMP-WITH-FP-NEXT: lw s11, 72(a5) +; RV32IZCMP-WITH-FP-NEXT: lw ra, 76(a5) +; RV32IZCMP-WITH-FP-NEXT: lw t4, 80(a5) +; RV32IZCMP-WITH-FP-NEXT: lw t3, 84(a5) +; RV32IZCMP-WITH-FP-NEXT: lw t2, 88(a5) +; RV32IZCMP-WITH-FP-NEXT: lw s1, 92(a5) +; RV32IZCMP-WITH-FP-NEXT: lw t1, 96(a5) +; RV32IZCMP-WITH-FP-NEXT: lw t0, 100(a5) +; RV32IZCMP-WITH-FP-NEXT: lw a6, 104(a5) +; RV32IZCMP-WITH-FP-NEXT: lw a4, 108(a5) +; RV32IZCMP-WITH-FP-NEXT: lw a0, 124(a5) +; RV32IZCMP-WITH-FP-NEXT: lw a1, 120(a5) +; RV32IZCMP-WITH-FP-NEXT: lw a2, 116(a5) +; RV32IZCMP-WITH-FP-NEXT: lw a3, 112(a5) +; RV32IZCMP-WITH-FP-NEXT: sw a0, 124(a5) +; RV32IZCMP-WITH-FP-NEXT: sw a1, 120(a5) +; RV32IZCMP-WITH-FP-NEXT: sw a2, 116(a5) +; RV32IZCMP-WITH-FP-NEXT: sw a3, 112(a5) +; RV32IZCMP-WITH-FP-NEXT: sw a4, 108(a5) +; RV32IZCMP-WITH-FP-NEXT: sw a6, 104(a5) +; RV32IZCMP-WITH-FP-NEXT: sw t0, 100(a5) +; RV32IZCMP-WITH-FP-NEXT: sw t1, 96(a5) +; RV32IZCMP-WITH-FP-NEXT: sw s1, 92(a5) +; RV32IZCMP-WITH-FP-NEXT: sw t2, 88(a5) +; RV32IZCMP-WITH-FP-NEXT: sw t3, 84(a5) +; RV32IZCMP-WITH-FP-NEXT: sw t4, 80(a5) +; RV32IZCMP-WITH-FP-NEXT: sw ra, 76(a5) +; RV32IZCMP-WITH-FP-NEXT: sw s11, 72(a5) +; RV32IZCMP-WITH-FP-NEXT: sw s10, 68(a5) +; RV32IZCMP-WITH-FP-NEXT: sw s9, 64(a5) +; RV32IZCMP-WITH-FP-NEXT: sw s8, 60(a5) +; RV32IZCMP-WITH-FP-NEXT: sw s7, 56(a5) +; RV32IZCMP-WITH-FP-NEXT: sw s6, 52(a5) +; RV32IZCMP-WITH-FP-NEXT: sw s5, 48(a5) +; RV32IZCMP-WITH-FP-NEXT: sw s4, 44(a5) +; RV32IZCMP-WITH-FP-NEXT: sw s3, 40(a5) +; RV32IZCMP-WITH-FP-NEXT: sw s2, 36(a5) +; RV32IZCMP-WITH-FP-NEXT: sw t6, 32(a5) +; RV32IZCMP-WITH-FP-NEXT: sw t5, 28(a5) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 24(a5) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 20(a5) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 16(a5) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var+12)(a7) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -64(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var+8)(a7) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -60(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var+4)(a7) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -56(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var)(a7) +; RV32IZCMP-WITH-FP-NEXT: lw ra, 76(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s0, 72(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s1, 68(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s2, 64(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s3, 60(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s4, 56(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s5, 52(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s6, 48(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s7, 44(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s8, 40(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s9, 36(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s10, 32(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s11, 28(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: addi sp, sp, 80 +; RV32IZCMP-WITH-FP-NEXT: ret +; ; RV64I-LABEL: callee: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -160 @@ -471,6 +676,203 @@ ; RV64I-WITH-FP-NEXT: ld s11, 56(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: addi sp, sp, 160 ; RV64I-WITH-FP-NEXT: ret +; +; RV64IZCMP-LABEL: callee: +; RV64IZCMP: # %bb.0: +; RV64IZCMP-NEXT: cm.push {ra, s0-s11}, -160 +; RV64IZCMP-NEXT: lui a7, %hi(var) +; RV64IZCMP-NEXT: lw a0, %lo(var)(a7) +; RV64IZCMP-NEXT: sd a0, 48(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, %lo(var+4)(a7) +; RV64IZCMP-NEXT: sd a0, 40(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, %lo(var+8)(a7) +; RV64IZCMP-NEXT: sd a0, 32(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, %lo(var+12)(a7) +; RV64IZCMP-NEXT: sd a0, 24(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: addi a5, a7, %lo(var) +; RV64IZCMP-NEXT: lw a0, 16(a5) +; RV64IZCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 20(a5) +; RV64IZCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw t4, 24(a5) +; RV64IZCMP-NEXT: lw t5, 28(a5) +; RV64IZCMP-NEXT: lw t6, 32(a5) +; RV64IZCMP-NEXT: lw s2, 36(a5) +; RV64IZCMP-NEXT: lw s3, 40(a5) +; RV64IZCMP-NEXT: lw s4, 44(a5) +; RV64IZCMP-NEXT: lw s5, 48(a5) +; RV64IZCMP-NEXT: lw s6, 52(a5) +; RV64IZCMP-NEXT: lw s7, 56(a5) +; RV64IZCMP-NEXT: lw s8, 60(a5) +; RV64IZCMP-NEXT: lw s9, 64(a5) +; RV64IZCMP-NEXT: lw s10, 68(a5) +; RV64IZCMP-NEXT: lw s11, 72(a5) +; RV64IZCMP-NEXT: lw ra, 76(a5) +; RV64IZCMP-NEXT: lw s1, 80(a5) +; RV64IZCMP-NEXT: lw t3, 84(a5) +; RV64IZCMP-NEXT: lw t2, 88(a5) +; RV64IZCMP-NEXT: lw t1, 92(a5) +; RV64IZCMP-NEXT: lw t0, 96(a5) +; RV64IZCMP-NEXT: lw s0, 100(a5) +; RV64IZCMP-NEXT: lw a6, 104(a5) +; RV64IZCMP-NEXT: lw a4, 108(a5) +; RV64IZCMP-NEXT: lw a0, 124(a5) +; RV64IZCMP-NEXT: lw a1, 120(a5) +; RV64IZCMP-NEXT: lw a2, 116(a5) +; RV64IZCMP-NEXT: lw a3, 112(a5) +; RV64IZCMP-NEXT: sw a0, 124(a5) +; RV64IZCMP-NEXT: sw a1, 120(a5) +; RV64IZCMP-NEXT: sw a2, 116(a5) +; RV64IZCMP-NEXT: sw a3, 112(a5) +; RV64IZCMP-NEXT: sw a4, 108(a5) +; RV64IZCMP-NEXT: sw a6, 104(a5) +; RV64IZCMP-NEXT: sw s0, 100(a5) +; RV64IZCMP-NEXT: sw t0, 96(a5) +; RV64IZCMP-NEXT: sw t1, 92(a5) +; RV64IZCMP-NEXT: sw t2, 88(a5) +; RV64IZCMP-NEXT: sw t3, 84(a5) +; RV64IZCMP-NEXT: sw s1, 80(a5) +; RV64IZCMP-NEXT: sw ra, 76(a5) +; RV64IZCMP-NEXT: sw s11, 72(a5) +; RV64IZCMP-NEXT: sw s10, 68(a5) +; RV64IZCMP-NEXT: sw s9, 64(a5) +; RV64IZCMP-NEXT: sw s8, 60(a5) +; RV64IZCMP-NEXT: sw s7, 56(a5) +; RV64IZCMP-NEXT: sw s6, 52(a5) +; RV64IZCMP-NEXT: sw s5, 48(a5) +; RV64IZCMP-NEXT: sw s4, 44(a5) +; RV64IZCMP-NEXT: sw s3, 40(a5) +; RV64IZCMP-NEXT: sw s2, 36(a5) +; RV64IZCMP-NEXT: sw t6, 32(a5) +; RV64IZCMP-NEXT: sw t5, 28(a5) +; RV64IZCMP-NEXT: sw t4, 24(a5) +; RV64IZCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 20(a5) +; RV64IZCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 16(a5) +; RV64IZCMP-NEXT: ld a0, 24(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var+12)(a7) +; RV64IZCMP-NEXT: ld a0, 32(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var+8)(a7) +; RV64IZCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var+4)(a7) +; RV64IZCMP-NEXT: ld a0, 48(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var)(a7) +; RV64IZCMP-NEXT: cm.pop {ra, s0-s11}, 160 +; RV64IZCMP-NEXT: ret +; +; RV64IZCMP-WITH-FP-LABEL: callee: +; RV64IZCMP-WITH-FP: # %bb.0: +; RV64IZCMP-WITH-FP-NEXT: addi sp, sp, -160 +; RV64IZCMP-WITH-FP-NEXT: sd ra, 152(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s0, 144(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s1, 136(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s2, 128(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s3, 120(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s4, 112(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s5, 104(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s6, 96(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s7, 88(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s8, 80(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s9, 72(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s10, 64(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s11, 56(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: addi s0, sp, 160 +; RV64IZCMP-WITH-FP-NEXT: lui a7, %hi(var) +; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var)(a7) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var+4)(a7) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var+8)(a7) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var+12)(a7) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: addi a5, a7, %lo(var) +; RV64IZCMP-WITH-FP-NEXT: lw a0, 16(a5) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 20(a5) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 24(a5) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw t5, 28(a5) +; RV64IZCMP-WITH-FP-NEXT: lw t6, 32(a5) +; RV64IZCMP-WITH-FP-NEXT: lw s2, 36(a5) +; RV64IZCMP-WITH-FP-NEXT: lw s3, 40(a5) +; RV64IZCMP-WITH-FP-NEXT: lw s4, 44(a5) +; RV64IZCMP-WITH-FP-NEXT: lw s5, 48(a5) +; RV64IZCMP-WITH-FP-NEXT: lw s6, 52(a5) +; RV64IZCMP-WITH-FP-NEXT: lw s7, 56(a5) +; RV64IZCMP-WITH-FP-NEXT: lw s8, 60(a5) +; RV64IZCMP-WITH-FP-NEXT: lw s9, 64(a5) +; RV64IZCMP-WITH-FP-NEXT: lw s10, 68(a5) +; RV64IZCMP-WITH-FP-NEXT: lw s11, 72(a5) +; RV64IZCMP-WITH-FP-NEXT: lw ra, 76(a5) +; RV64IZCMP-WITH-FP-NEXT: lw t4, 80(a5) +; RV64IZCMP-WITH-FP-NEXT: lw t3, 84(a5) +; RV64IZCMP-WITH-FP-NEXT: lw t2, 88(a5) +; RV64IZCMP-WITH-FP-NEXT: lw s1, 92(a5) +; RV64IZCMP-WITH-FP-NEXT: lw t1, 96(a5) +; RV64IZCMP-WITH-FP-NEXT: lw t0, 100(a5) +; RV64IZCMP-WITH-FP-NEXT: lw a6, 104(a5) +; RV64IZCMP-WITH-FP-NEXT: lw a4, 108(a5) +; RV64IZCMP-WITH-FP-NEXT: lw a0, 124(a5) +; RV64IZCMP-WITH-FP-NEXT: lw a1, 120(a5) +; RV64IZCMP-WITH-FP-NEXT: lw a2, 116(a5) +; RV64IZCMP-WITH-FP-NEXT: lw a3, 112(a5) +; RV64IZCMP-WITH-FP-NEXT: sw a0, 124(a5) +; RV64IZCMP-WITH-FP-NEXT: sw a1, 120(a5) +; RV64IZCMP-WITH-FP-NEXT: sw a2, 116(a5) +; RV64IZCMP-WITH-FP-NEXT: sw a3, 112(a5) +; RV64IZCMP-WITH-FP-NEXT: sw a4, 108(a5) +; RV64IZCMP-WITH-FP-NEXT: sw a6, 104(a5) +; RV64IZCMP-WITH-FP-NEXT: sw t0, 100(a5) +; RV64IZCMP-WITH-FP-NEXT: sw t1, 96(a5) +; RV64IZCMP-WITH-FP-NEXT: sw s1, 92(a5) +; RV64IZCMP-WITH-FP-NEXT: sw t2, 88(a5) +; RV64IZCMP-WITH-FP-NEXT: sw t3, 84(a5) +; RV64IZCMP-WITH-FP-NEXT: sw t4, 80(a5) +; RV64IZCMP-WITH-FP-NEXT: sw ra, 76(a5) +; RV64IZCMP-WITH-FP-NEXT: sw s11, 72(a5) +; RV64IZCMP-WITH-FP-NEXT: sw s10, 68(a5) +; RV64IZCMP-WITH-FP-NEXT: sw s9, 64(a5) +; RV64IZCMP-WITH-FP-NEXT: sw s8, 60(a5) +; RV64IZCMP-WITH-FP-NEXT: sw s7, 56(a5) +; RV64IZCMP-WITH-FP-NEXT: sw s6, 52(a5) +; RV64IZCMP-WITH-FP-NEXT: sw s5, 48(a5) +; RV64IZCMP-WITH-FP-NEXT: sw s4, 44(a5) +; RV64IZCMP-WITH-FP-NEXT: sw s3, 40(a5) +; RV64IZCMP-WITH-FP-NEXT: sw s2, 36(a5) +; RV64IZCMP-WITH-FP-NEXT: sw t6, 32(a5) +; RV64IZCMP-WITH-FP-NEXT: sw t5, 28(a5) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 24(a5) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 20(a5) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 16(a5) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var+12)(a7) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var+8)(a7) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var+4)(a7) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -112(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var)(a7) +; RV64IZCMP-WITH-FP-NEXT: ld ra, 152(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s0, 144(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s1, 136(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s2, 128(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s3, 120(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s4, 112(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s5, 104(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s6, 96(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s7, 88(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s8, 80(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s9, 72(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s10, 64(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s11, 56(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: addi sp, sp, 160 +; RV64IZCMP-WITH-FP-NEXT: ret %val = load [32 x i32], ptr @var store volatile [32 x i32] %val, ptr @var ret void @@ -769,6 +1171,271 @@ ; RV32I-WITH-FP-NEXT: addi sp, sp, 144 ; RV32I-WITH-FP-NEXT: ret ; +; RV32IZCMP-LABEL: caller: +; RV32IZCMP: # %bb.0: +; RV32IZCMP-NEXT: cm.push {ra, s0-s11}, -112 +; RV32IZCMP-NEXT: addi sp, sp, -32 +; RV32IZCMP-NEXT: lui s0, %hi(var) +; RV32IZCMP-NEXT: lw a0, %lo(var)(s0) +; RV32IZCMP-NEXT: sw a0, 88(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, %lo(var+4)(s0) +; RV32IZCMP-NEXT: sw a0, 84(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, %lo(var+8)(s0) +; RV32IZCMP-NEXT: sw a0, 80(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, %lo(var+12)(s0) +; RV32IZCMP-NEXT: sw a0, 76(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: addi s1, s0, %lo(var) +; RV32IZCMP-NEXT: lw a0, 16(s1) +; RV32IZCMP-NEXT: sw a0, 72(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 20(s1) +; RV32IZCMP-NEXT: sw a0, 68(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 24(s1) +; RV32IZCMP-NEXT: sw a0, 64(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 28(s1) +; RV32IZCMP-NEXT: sw a0, 60(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 32(s1) +; RV32IZCMP-NEXT: sw a0, 56(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 36(s1) +; RV32IZCMP-NEXT: sw a0, 52(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 40(s1) +; RV32IZCMP-NEXT: sw a0, 48(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 44(s1) +; RV32IZCMP-NEXT: sw a0, 44(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 48(s1) +; RV32IZCMP-NEXT: sw a0, 40(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 52(s1) +; RV32IZCMP-NEXT: sw a0, 36(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 56(s1) +; RV32IZCMP-NEXT: sw a0, 32(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 60(s1) +; RV32IZCMP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 64(s1) +; RV32IZCMP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 68(s1) +; RV32IZCMP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 72(s1) +; RV32IZCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 76(s1) +; RV32IZCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 80(s1) +; RV32IZCMP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 84(s1) +; RV32IZCMP-NEXT: sw a0, 4(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw s4, 88(s1) +; RV32IZCMP-NEXT: lw s5, 92(s1) +; RV32IZCMP-NEXT: lw s6, 96(s1) +; RV32IZCMP-NEXT: lw s7, 100(s1) +; RV32IZCMP-NEXT: lw s8, 104(s1) +; RV32IZCMP-NEXT: lw s9, 108(s1) +; RV32IZCMP-NEXT: lw s10, 112(s1) +; RV32IZCMP-NEXT: lw s11, 116(s1) +; RV32IZCMP-NEXT: lw s2, 120(s1) +; RV32IZCMP-NEXT: lw s3, 124(s1) +; RV32IZCMP-NEXT: call callee@plt +; RV32IZCMP-NEXT: sw s3, 124(s1) +; RV32IZCMP-NEXT: sw s2, 120(s1) +; RV32IZCMP-NEXT: sw s11, 116(s1) +; RV32IZCMP-NEXT: sw s10, 112(s1) +; RV32IZCMP-NEXT: sw s9, 108(s1) +; RV32IZCMP-NEXT: sw s8, 104(s1) +; RV32IZCMP-NEXT: sw s7, 100(s1) +; RV32IZCMP-NEXT: sw s6, 96(s1) +; RV32IZCMP-NEXT: sw s5, 92(s1) +; RV32IZCMP-NEXT: sw s4, 88(s1) +; RV32IZCMP-NEXT: lw a0, 4(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 84(s1) +; RV32IZCMP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 80(s1) +; RV32IZCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 76(s1) +; RV32IZCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 72(s1) +; RV32IZCMP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 68(s1) +; RV32IZCMP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 64(s1) +; RV32IZCMP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 60(s1) +; RV32IZCMP-NEXT: lw a0, 32(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 56(s1) +; RV32IZCMP-NEXT: lw a0, 36(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 52(s1) +; RV32IZCMP-NEXT: lw a0, 40(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 48(s1) +; RV32IZCMP-NEXT: lw a0, 44(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 44(s1) +; RV32IZCMP-NEXT: lw a0, 48(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 40(s1) +; RV32IZCMP-NEXT: lw a0, 52(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 36(s1) +; RV32IZCMP-NEXT: lw a0, 56(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 32(s1) +; RV32IZCMP-NEXT: lw a0, 60(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 28(s1) +; RV32IZCMP-NEXT: lw a0, 64(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 24(s1) +; RV32IZCMP-NEXT: lw a0, 68(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 20(s1) +; RV32IZCMP-NEXT: lw a0, 72(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 16(s1) +; RV32IZCMP-NEXT: lw a0, 76(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var+12)(s0) +; RV32IZCMP-NEXT: lw a0, 80(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var+8)(s0) +; RV32IZCMP-NEXT: lw a0, 84(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var+4)(s0) +; RV32IZCMP-NEXT: lw a0, 88(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var)(s0) +; RV32IZCMP-NEXT: addi sp, sp, 32 +; RV32IZCMP-NEXT: cm.pop {ra, s0-s11}, 112 +; RV32IZCMP-NEXT: ret +; +; RV32IZCMP-WITH-FP-LABEL: caller: +; RV32IZCMP-WITH-FP: # %bb.0: +; RV32IZCMP-WITH-FP-NEXT: addi sp, sp, -144 +; RV32IZCMP-WITH-FP-NEXT: sw ra, 140(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s0, 136(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s1, 132(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s2, 128(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s3, 124(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s4, 120(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s5, 116(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s6, 112(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s7, 108(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s8, 104(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s9, 100(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s10, 96(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: sw s11, 92(sp) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: addi s0, sp, 144 +; RV32IZCMP-WITH-FP-NEXT: lui s6, %hi(var) +; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var)(s6) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var+4)(s6) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -60(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var+8)(s6) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -64(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, %lo(var+12)(s6) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: addi s1, s6, %lo(var) +; RV32IZCMP-WITH-FP-NEXT: lw a0, 16(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 20(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 24(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 28(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -84(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 32(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -88(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 36(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -92(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 40(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -96(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 44(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -100(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 48(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -104(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 52(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -108(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 56(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -112(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 60(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -116(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 64(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -120(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 68(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -124(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 72(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -128(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 76(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -132(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 80(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -136(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 84(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -140(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw a0, 88(s1) +; RV32IZCMP-WITH-FP-NEXT: sw a0, -144(s0) # 4-byte Folded Spill +; RV32IZCMP-WITH-FP-NEXT: lw s8, 92(s1) +; RV32IZCMP-WITH-FP-NEXT: lw s9, 96(s1) +; RV32IZCMP-WITH-FP-NEXT: lw s10, 100(s1) +; RV32IZCMP-WITH-FP-NEXT: lw s11, 104(s1) +; RV32IZCMP-WITH-FP-NEXT: lw s2, 108(s1) +; RV32IZCMP-WITH-FP-NEXT: lw s3, 112(s1) +; RV32IZCMP-WITH-FP-NEXT: lw s4, 116(s1) +; RV32IZCMP-WITH-FP-NEXT: lw s5, 120(s1) +; RV32IZCMP-WITH-FP-NEXT: lw s7, 124(s1) +; RV32IZCMP-WITH-FP-NEXT: call callee@plt +; RV32IZCMP-WITH-FP-NEXT: sw s7, 124(s1) +; RV32IZCMP-WITH-FP-NEXT: sw s5, 120(s1) +; RV32IZCMP-WITH-FP-NEXT: sw s4, 116(s1) +; RV32IZCMP-WITH-FP-NEXT: sw s3, 112(s1) +; RV32IZCMP-WITH-FP-NEXT: sw s2, 108(s1) +; RV32IZCMP-WITH-FP-NEXT: sw s11, 104(s1) +; RV32IZCMP-WITH-FP-NEXT: sw s10, 100(s1) +; RV32IZCMP-WITH-FP-NEXT: sw s9, 96(s1) +; RV32IZCMP-WITH-FP-NEXT: sw s8, 92(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -144(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 88(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -140(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 84(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -136(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 80(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -132(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 76(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -128(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 72(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -124(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 68(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -120(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 64(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -116(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 60(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -112(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 56(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -108(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 52(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -104(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 48(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -100(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 44(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -96(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 40(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -92(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 36(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -88(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 32(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -84(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 28(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 24(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 20(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, 16(s1) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var+12)(s6) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -64(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var+8)(s6) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -60(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var+4)(s6) +; RV32IZCMP-WITH-FP-NEXT: lw a0, -56(s0) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: sw a0, %lo(var)(s6) +; RV32IZCMP-WITH-FP-NEXT: lw ra, 140(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s0, 136(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s1, 132(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s2, 128(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s3, 124(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s4, 120(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s5, 116(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s6, 112(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s7, 108(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s8, 104(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s9, 100(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s10, 96(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: lw s11, 92(sp) # 4-byte Folded Reload +; RV32IZCMP-WITH-FP-NEXT: addi sp, sp, 144 +; RV32IZCMP-WITH-FP-NEXT: ret +; ; RV64I-LABEL: caller: ; RV64I: # %bb.0: ; RV64I-NEXT: addi sp, sp, -288 @@ -1057,7 +1724,271 @@ ; RV64I-WITH-FP-NEXT: ld s11, 184(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: addi sp, sp, 288 ; RV64I-WITH-FP-NEXT: ret - +; +; RV64IZCMP-LABEL: caller: +; RV64IZCMP: # %bb.0: +; RV64IZCMP-NEXT: cm.push {ra, s0-s11}, -160 +; RV64IZCMP-NEXT: addi sp, sp, -128 +; RV64IZCMP-NEXT: lui s0, %hi(var) +; RV64IZCMP-NEXT: lw a0, %lo(var)(s0) +; RV64IZCMP-NEXT: sd a0, 176(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, %lo(var+4)(s0) +; RV64IZCMP-NEXT: sd a0, 168(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, %lo(var+8)(s0) +; RV64IZCMP-NEXT: sd a0, 160(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, %lo(var+12)(s0) +; RV64IZCMP-NEXT: sd a0, 152(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: addi s1, s0, %lo(var) +; RV64IZCMP-NEXT: lw a0, 16(s1) +; RV64IZCMP-NEXT: sd a0, 144(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 20(s1) +; RV64IZCMP-NEXT: sd a0, 136(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 24(s1) +; RV64IZCMP-NEXT: sd a0, 128(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 28(s1) +; RV64IZCMP-NEXT: sd a0, 120(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 32(s1) +; RV64IZCMP-NEXT: sd a0, 112(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 36(s1) +; RV64IZCMP-NEXT: sd a0, 104(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 40(s1) +; RV64IZCMP-NEXT: sd a0, 96(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 44(s1) +; RV64IZCMP-NEXT: sd a0, 88(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 48(s1) +; RV64IZCMP-NEXT: sd a0, 80(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 52(s1) +; RV64IZCMP-NEXT: sd a0, 72(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 56(s1) +; RV64IZCMP-NEXT: sd a0, 64(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 60(s1) +; RV64IZCMP-NEXT: sd a0, 56(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 64(s1) +; RV64IZCMP-NEXT: sd a0, 48(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 68(s1) +; RV64IZCMP-NEXT: sd a0, 40(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 72(s1) +; RV64IZCMP-NEXT: sd a0, 32(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 76(s1) +; RV64IZCMP-NEXT: sd a0, 24(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 80(s1) +; RV64IZCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 84(s1) +; RV64IZCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw s4, 88(s1) +; RV64IZCMP-NEXT: lw s5, 92(s1) +; RV64IZCMP-NEXT: lw s6, 96(s1) +; RV64IZCMP-NEXT: lw s7, 100(s1) +; RV64IZCMP-NEXT: lw s8, 104(s1) +; RV64IZCMP-NEXT: lw s9, 108(s1) +; RV64IZCMP-NEXT: lw s10, 112(s1) +; RV64IZCMP-NEXT: lw s11, 116(s1) +; RV64IZCMP-NEXT: lw s2, 120(s1) +; RV64IZCMP-NEXT: lw s3, 124(s1) +; RV64IZCMP-NEXT: call callee@plt +; RV64IZCMP-NEXT: sw s3, 124(s1) +; RV64IZCMP-NEXT: sw s2, 120(s1) +; RV64IZCMP-NEXT: sw s11, 116(s1) +; RV64IZCMP-NEXT: sw s10, 112(s1) +; RV64IZCMP-NEXT: sw s9, 108(s1) +; RV64IZCMP-NEXT: sw s8, 104(s1) +; RV64IZCMP-NEXT: sw s7, 100(s1) +; RV64IZCMP-NEXT: sw s6, 96(s1) +; RV64IZCMP-NEXT: sw s5, 92(s1) +; RV64IZCMP-NEXT: sw s4, 88(s1) +; RV64IZCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 84(s1) +; RV64IZCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 80(s1) +; RV64IZCMP-NEXT: ld a0, 24(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 76(s1) +; RV64IZCMP-NEXT: ld a0, 32(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 72(s1) +; RV64IZCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 68(s1) +; RV64IZCMP-NEXT: ld a0, 48(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 64(s1) +; RV64IZCMP-NEXT: ld a0, 56(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 60(s1) +; RV64IZCMP-NEXT: ld a0, 64(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 56(s1) +; RV64IZCMP-NEXT: ld a0, 72(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 52(s1) +; RV64IZCMP-NEXT: ld a0, 80(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 48(s1) +; RV64IZCMP-NEXT: ld a0, 88(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 44(s1) +; RV64IZCMP-NEXT: ld a0, 96(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 40(s1) +; RV64IZCMP-NEXT: ld a0, 104(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 36(s1) +; RV64IZCMP-NEXT: ld a0, 112(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 32(s1) +; RV64IZCMP-NEXT: ld a0, 120(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 28(s1) +; RV64IZCMP-NEXT: ld a0, 128(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 24(s1) +; RV64IZCMP-NEXT: ld a0, 136(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 20(s1) +; RV64IZCMP-NEXT: ld a0, 144(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 16(s1) +; RV64IZCMP-NEXT: ld a0, 152(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var+12)(s0) +; RV64IZCMP-NEXT: ld a0, 160(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var+8)(s0) +; RV64IZCMP-NEXT: ld a0, 168(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var+4)(s0) +; RV64IZCMP-NEXT: ld a0, 176(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var)(s0) +; RV64IZCMP-NEXT: addi sp, sp, 128 +; RV64IZCMP-NEXT: cm.pop {ra, s0-s11}, 160 +; RV64IZCMP-NEXT: ret +; +; RV64IZCMP-WITH-FP-LABEL: caller: +; RV64IZCMP-WITH-FP: # %bb.0: +; RV64IZCMP-WITH-FP-NEXT: addi sp, sp, -288 +; RV64IZCMP-WITH-FP-NEXT: sd ra, 280(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s0, 272(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s1, 264(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s2, 256(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s3, 248(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s4, 240(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s5, 232(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s6, 224(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s7, 216(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s8, 208(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s9, 200(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s10, 192(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: sd s11, 184(sp) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: addi s0, sp, 288 +; RV64IZCMP-WITH-FP-NEXT: lui s6, %hi(var) +; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var)(s6) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var+4)(s6) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var+8)(s6) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, %lo(var+12)(s6) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: addi s1, s6, %lo(var) +; RV64IZCMP-WITH-FP-NEXT: lw a0, 16(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 20(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 24(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 28(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -168(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 32(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -176(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 36(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -184(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 40(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -192(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 44(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -200(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 48(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -208(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 52(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -216(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 56(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -224(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 60(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -232(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 64(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -240(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 68(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -248(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 72(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -256(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 76(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -264(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 80(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -272(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 84(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -280(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw a0, 88(s1) +; RV64IZCMP-WITH-FP-NEXT: sd a0, -288(s0) # 8-byte Folded Spill +; RV64IZCMP-WITH-FP-NEXT: lw s8, 92(s1) +; RV64IZCMP-WITH-FP-NEXT: lw s9, 96(s1) +; RV64IZCMP-WITH-FP-NEXT: lw s10, 100(s1) +; RV64IZCMP-WITH-FP-NEXT: lw s11, 104(s1) +; RV64IZCMP-WITH-FP-NEXT: lw s2, 108(s1) +; RV64IZCMP-WITH-FP-NEXT: lw s3, 112(s1) +; RV64IZCMP-WITH-FP-NEXT: lw s4, 116(s1) +; RV64IZCMP-WITH-FP-NEXT: lw s5, 120(s1) +; RV64IZCMP-WITH-FP-NEXT: lw s7, 124(s1) +; RV64IZCMP-WITH-FP-NEXT: call callee@plt +; RV64IZCMP-WITH-FP-NEXT: sw s7, 124(s1) +; RV64IZCMP-WITH-FP-NEXT: sw s5, 120(s1) +; RV64IZCMP-WITH-FP-NEXT: sw s4, 116(s1) +; RV64IZCMP-WITH-FP-NEXT: sw s3, 112(s1) +; RV64IZCMP-WITH-FP-NEXT: sw s2, 108(s1) +; RV64IZCMP-WITH-FP-NEXT: sw s11, 104(s1) +; RV64IZCMP-WITH-FP-NEXT: sw s10, 100(s1) +; RV64IZCMP-WITH-FP-NEXT: sw s9, 96(s1) +; RV64IZCMP-WITH-FP-NEXT: sw s8, 92(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -288(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 88(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -280(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 84(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -272(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 80(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -264(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 76(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -256(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 72(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -248(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 68(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -240(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 64(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -232(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 60(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -224(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 56(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -216(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 52(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -208(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 48(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -200(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 44(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -192(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 40(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -184(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 36(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -176(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 32(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -168(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 28(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 24(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 20(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, 16(s1) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var+12)(s6) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var+8)(s6) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var+4)(s6) +; RV64IZCMP-WITH-FP-NEXT: ld a0, -112(s0) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: sw a0, %lo(var)(s6) +; RV64IZCMP-WITH-FP-NEXT: ld ra, 280(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s0, 272(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s1, 264(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s2, 256(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s3, 248(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s4, 240(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s5, 232(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s6, 224(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s7, 216(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s8, 208(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s9, 200(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s10, 192(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: ld s11, 184(sp) # 8-byte Folded Reload +; RV64IZCMP-WITH-FP-NEXT: addi sp, sp, 288 +; RV64IZCMP-WITH-FP-NEXT: ret %val = load [32 x i32], ptr @var call void @callee() store volatile [32 x i32] %val, ptr @var diff --git a/llvm/test/CodeGen/RISCV/push-pop-popret.ll b/llvm/test/CodeGen/RISCV/push-pop-popret.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/push-pop-popret.ll @@ -0,0 +1,1831 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcmp -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefixes=RV32IZCMP +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcmp -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefixes=RV64IZCMP +; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV32I %s +; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefixes=RV64I %s + +declare void @test(i8*) + +define i32 @foo() { +; RV32IZCMP-LABEL: foo: +; RV32IZCMP: # %bb.0: +; RV32IZCMP-NEXT: cm.push {ra}, -64 +; RV32IZCMP-NEXT: .cfi_def_cfa_offset 528 +; RV32IZCMP-NEXT: addi sp, sp, -464 +; RV32IZCMP-NEXT: .cfi_offset ra, -4 +; RV32IZCMP-NEXT: addi a0, sp, 12 +; RV32IZCMP-NEXT: call test@plt +; RV32IZCMP-NEXT: li a0, 0 +; RV32IZCMP-NEXT: addi sp, sp, 464 +; RV32IZCMP-NEXT: cm.pop {ra}, 64 +; RV32IZCMP-NEXT: ret +; +; RV64IZCMP-LABEL: foo: +; RV64IZCMP: # %bb.0: +; RV64IZCMP-NEXT: cm.push {ra}, -64 +; RV64IZCMP-NEXT: .cfi_def_cfa_offset 528 +; RV64IZCMP-NEXT: addi sp, sp, -464 +; RV64IZCMP-NEXT: .cfi_offset ra, -8 +; RV64IZCMP-NEXT: addi a0, sp, 8 +; RV64IZCMP-NEXT: call test@plt +; RV64IZCMP-NEXT: li a0, 0 +; RV64IZCMP-NEXT: addi sp, sp, 464 +; RV64IZCMP-NEXT: cm.pop {ra}, 64 +; RV64IZCMP-NEXT: ret +; +; RV32I-LABEL: foo: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -528 +; RV32I-NEXT: .cfi_def_cfa_offset 528 +; RV32I-NEXT: sw ra, 524(sp) # 4-byte Folded Spill +; RV32I-NEXT: .cfi_offset ra, -4 +; RV32I-NEXT: addi a0, sp, 12 +; RV32I-NEXT: call test@plt +; RV32I-NEXT: li a0, 0 +; RV32I-NEXT: lw ra, 524(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 528 +; RV32I-NEXT: ret +; +; RV64I-LABEL: foo: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -528 +; RV64I-NEXT: .cfi_def_cfa_offset 528 +; RV64I-NEXT: sd ra, 520(sp) # 8-byte Folded Spill +; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: addi a0, sp, 8 +; RV64I-NEXT: call test@plt +; RV64I-NEXT: li a0, 0 +; RV64I-NEXT: ld ra, 520(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 528 +; RV64I-NEXT: ret + %1 = alloca [512 x i8] + %2 = getelementptr [512 x i8], [512 x i8]* %1, i32 0, i32 0 + call void @test(i8* %2) + ret i32 0 +} + +define i32 @pushpopret0(i32 signext %size){ +; RV32IZCMP-LABEL: pushpopret0: +; RV32IZCMP: # %bb.0: # %entry +; RV32IZCMP-NEXT: .cfi_def_cfa_offset 16 +; RV32IZCMP-NEXT: cm.push {ra, s0}, -16 +; RV32IZCMP-NEXT: .cfi_offset ra, -4 +; RV32IZCMP-NEXT: .cfi_offset s0, -8 +; RV32IZCMP-NEXT: addi s0, sp, 16 +; RV32IZCMP-NEXT: .cfi_def_cfa s0, 0 +; RV32IZCMP-NEXT: addi a0, a0, 15 +; RV32IZCMP-NEXT: andi a0, a0, -16 +; RV32IZCMP-NEXT: sub a0, sp, a0 +; RV32IZCMP-NEXT: mv sp, a0 +; RV32IZCMP-NEXT: call callee_void@plt +; RV32IZCMP-NEXT: li a0, 0 +; RV32IZCMP-NEXT: addi sp, s0, -16 +; RV32IZCMP-NEXT: cm.pop {ra, s0}, 16 +; RV32IZCMP-NEXT: ret +; +; RV64IZCMP-LABEL: pushpopret0: +; RV64IZCMP: # %bb.0: # %entry +; RV64IZCMP-NEXT: .cfi_def_cfa_offset 16 +; RV64IZCMP-NEXT: cm.push {ra, s0}, -16 +; RV64IZCMP-NEXT: .cfi_offset ra, -8 +; RV64IZCMP-NEXT: .cfi_offset s0, -16 +; RV64IZCMP-NEXT: addi s0, sp, 16 +; RV64IZCMP-NEXT: .cfi_def_cfa s0, 0 +; RV64IZCMP-NEXT: slli a0, a0, 32 +; RV64IZCMP-NEXT: srli a0, a0, 32 +; RV64IZCMP-NEXT: addi a0, a0, 15 +; RV64IZCMP-NEXT: andi a0, a0, -16 +; RV64IZCMP-NEXT: sub a0, sp, a0 +; RV64IZCMP-NEXT: mv sp, a0 +; RV64IZCMP-NEXT: call callee_void@plt +; RV64IZCMP-NEXT: li a0, 0 +; RV64IZCMP-NEXT: addi sp, s0, -16 +; RV64IZCMP-NEXT: cm.pop {ra, s0}, 16 +; RV64IZCMP-NEXT: ret +; +; RV32I-LABEL: pushpopret0: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: .cfi_def_cfa_offset 16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: .cfi_offset ra, -4 +; RV32I-NEXT: .cfi_offset s0, -8 +; RV32I-NEXT: addi s0, sp, 16 +; RV32I-NEXT: .cfi_def_cfa s0, 0 +; RV32I-NEXT: addi a0, a0, 15 +; RV32I-NEXT: andi a0, a0, -16 +; RV32I-NEXT: sub a0, sp, a0 +; RV32I-NEXT: mv sp, a0 +; RV32I-NEXT: call callee_void@plt +; RV32I-NEXT: li a0, 0 +; RV32I-NEXT: addi sp, s0, -16 +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; +; RV64I-LABEL: pushpopret0: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: .cfi_def_cfa_offset 16 +; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: .cfi_offset s0, -16 +; RV64I-NEXT: addi s0, sp, 16 +; RV64I-NEXT: .cfi_def_cfa s0, 0 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: srli a0, a0, 32 +; RV64I-NEXT: addi a0, a0, 15 +; RV64I-NEXT: andi a0, a0, -16 +; RV64I-NEXT: sub a0, sp, a0 +; RV64I-NEXT: mv sp, a0 +; RV64I-NEXT: call callee_void@plt +; RV64I-NEXT: li a0, 0 +; RV64I-NEXT: addi sp, s0, -16 +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret +entry: + %0 = alloca i8, i32 %size, align 16 + call void @callee_void(i8* nonnull %0) + ret i32 0 +} + +define i32 @pushpopret1(i32 signext %size) { +; RV32IZCMP-LABEL: pushpopret1: +; RV32IZCMP: # %bb.0: # %entry +; RV32IZCMP-NEXT: .cfi_def_cfa_offset 16 +; RV32IZCMP-NEXT: cm.push {ra, s0}, -16 +; RV32IZCMP-NEXT: .cfi_offset ra, -4 +; RV32IZCMP-NEXT: .cfi_offset s0, -8 +; RV32IZCMP-NEXT: addi s0, sp, 16 +; RV32IZCMP-NEXT: .cfi_def_cfa s0, 0 +; RV32IZCMP-NEXT: addi a0, a0, 15 +; RV32IZCMP-NEXT: andi a0, a0, -16 +; RV32IZCMP-NEXT: sub a0, sp, a0 +; RV32IZCMP-NEXT: mv sp, a0 +; RV32IZCMP-NEXT: call callee_void@plt +; RV32IZCMP-NEXT: li a0, 1 +; RV32IZCMP-NEXT: addi sp, s0, -16 +; RV32IZCMP-NEXT: cm.pop {ra, s0}, 16 +; RV32IZCMP-NEXT: ret +; +; RV64IZCMP-LABEL: pushpopret1: +; RV64IZCMP: # %bb.0: # %entry +; RV64IZCMP-NEXT: .cfi_def_cfa_offset 16 +; RV64IZCMP-NEXT: cm.push {ra, s0}, -16 +; RV64IZCMP-NEXT: .cfi_offset ra, -8 +; RV64IZCMP-NEXT: .cfi_offset s0, -16 +; RV64IZCMP-NEXT: addi s0, sp, 16 +; RV64IZCMP-NEXT: .cfi_def_cfa s0, 0 +; RV64IZCMP-NEXT: slli a0, a0, 32 +; RV64IZCMP-NEXT: srli a0, a0, 32 +; RV64IZCMP-NEXT: addi a0, a0, 15 +; RV64IZCMP-NEXT: andi a0, a0, -16 +; RV64IZCMP-NEXT: sub a0, sp, a0 +; RV64IZCMP-NEXT: mv sp, a0 +; RV64IZCMP-NEXT: call callee_void@plt +; RV64IZCMP-NEXT: li a0, 1 +; RV64IZCMP-NEXT: addi sp, s0, -16 +; RV64IZCMP-NEXT: cm.pop {ra, s0}, 16 +; RV64IZCMP-NEXT: ret +; +; RV32I-LABEL: pushpopret1: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: .cfi_def_cfa_offset 16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: .cfi_offset ra, -4 +; RV32I-NEXT: .cfi_offset s0, -8 +; RV32I-NEXT: addi s0, sp, 16 +; RV32I-NEXT: .cfi_def_cfa s0, 0 +; RV32I-NEXT: addi a0, a0, 15 +; RV32I-NEXT: andi a0, a0, -16 +; RV32I-NEXT: sub a0, sp, a0 +; RV32I-NEXT: mv sp, a0 +; RV32I-NEXT: call callee_void@plt +; RV32I-NEXT: li a0, 1 +; RV32I-NEXT: addi sp, s0, -16 +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; +; RV64I-LABEL: pushpopret1: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: .cfi_def_cfa_offset 16 +; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: .cfi_offset s0, -16 +; RV64I-NEXT: addi s0, sp, 16 +; RV64I-NEXT: .cfi_def_cfa s0, 0 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: srli a0, a0, 32 +; RV64I-NEXT: addi a0, a0, 15 +; RV64I-NEXT: andi a0, a0, -16 +; RV64I-NEXT: sub a0, sp, a0 +; RV64I-NEXT: mv sp, a0 +; RV64I-NEXT: call callee_void@plt +; RV64I-NEXT: li a0, 1 +; RV64I-NEXT: addi sp, s0, -16 +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret +entry: + %0 = alloca i8, i32 %size, align 16 + call void @callee_void(i8* nonnull %0) + ret i32 1 +} + +define i32 @pushpopretneg1(i32 signext %size) { +; RV32IZCMP-LABEL: pushpopretneg1: +; RV32IZCMP: # %bb.0: # %entry +; RV32IZCMP-NEXT: .cfi_def_cfa_offset 16 +; RV32IZCMP-NEXT: cm.push {ra, s0}, -16 +; RV32IZCMP-NEXT: .cfi_offset ra, -4 +; RV32IZCMP-NEXT: .cfi_offset s0, -8 +; RV32IZCMP-NEXT: addi s0, sp, 16 +; RV32IZCMP-NEXT: .cfi_def_cfa s0, 0 +; RV32IZCMP-NEXT: addi a0, a0, 15 +; RV32IZCMP-NEXT: andi a0, a0, -16 +; RV32IZCMP-NEXT: sub a0, sp, a0 +; RV32IZCMP-NEXT: mv sp, a0 +; RV32IZCMP-NEXT: call callee_void@plt +; RV32IZCMP-NEXT: li a0, -1 +; RV32IZCMP-NEXT: addi sp, s0, -16 +; RV32IZCMP-NEXT: cm.pop {ra, s0}, 16 +; RV32IZCMP-NEXT: ret +; +; RV64IZCMP-LABEL: pushpopretneg1: +; RV64IZCMP: # %bb.0: # %entry +; RV64IZCMP-NEXT: .cfi_def_cfa_offset 16 +; RV64IZCMP-NEXT: cm.push {ra, s0}, -16 +; RV64IZCMP-NEXT: .cfi_offset ra, -8 +; RV64IZCMP-NEXT: .cfi_offset s0, -16 +; RV64IZCMP-NEXT: addi s0, sp, 16 +; RV64IZCMP-NEXT: .cfi_def_cfa s0, 0 +; RV64IZCMP-NEXT: slli a0, a0, 32 +; RV64IZCMP-NEXT: srli a0, a0, 32 +; RV64IZCMP-NEXT: addi a0, a0, 15 +; RV64IZCMP-NEXT: andi a0, a0, -16 +; RV64IZCMP-NEXT: sub a0, sp, a0 +; RV64IZCMP-NEXT: mv sp, a0 +; RV64IZCMP-NEXT: call callee_void@plt +; RV64IZCMP-NEXT: li a0, -1 +; RV64IZCMP-NEXT: addi sp, s0, -16 +; RV64IZCMP-NEXT: cm.pop {ra, s0}, 16 +; RV64IZCMP-NEXT: ret +; +; RV32I-LABEL: pushpopretneg1: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: .cfi_def_cfa_offset 16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: .cfi_offset ra, -4 +; RV32I-NEXT: .cfi_offset s0, -8 +; RV32I-NEXT: addi s0, sp, 16 +; RV32I-NEXT: .cfi_def_cfa s0, 0 +; RV32I-NEXT: addi a0, a0, 15 +; RV32I-NEXT: andi a0, a0, -16 +; RV32I-NEXT: sub a0, sp, a0 +; RV32I-NEXT: mv sp, a0 +; RV32I-NEXT: call callee_void@plt +; RV32I-NEXT: li a0, -1 +; RV32I-NEXT: addi sp, s0, -16 +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; +; RV64I-LABEL: pushpopretneg1: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: .cfi_def_cfa_offset 16 +; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: .cfi_offset s0, -16 +; RV64I-NEXT: addi s0, sp, 16 +; RV64I-NEXT: .cfi_def_cfa s0, 0 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: srli a0, a0, 32 +; RV64I-NEXT: addi a0, a0, 15 +; RV64I-NEXT: andi a0, a0, -16 +; RV64I-NEXT: sub a0, sp, a0 +; RV64I-NEXT: mv sp, a0 +; RV64I-NEXT: call callee_void@plt +; RV64I-NEXT: li a0, -1 +; RV64I-NEXT: addi sp, s0, -16 +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret +entry: + %0 = alloca i8, i32 %size, align 16 + call void @callee_void(i8* nonnull %0) + ret i32 -1 +} + +define i32 @pushpopret2(i32 signext %size) { +; RV32IZCMP-LABEL: pushpopret2: +; RV32IZCMP: # %bb.0: # %entry +; RV32IZCMP-NEXT: .cfi_def_cfa_offset 16 +; RV32IZCMP-NEXT: cm.push {ra, s0}, -16 +; RV32IZCMP-NEXT: .cfi_offset ra, -4 +; RV32IZCMP-NEXT: .cfi_offset s0, -8 +; RV32IZCMP-NEXT: addi s0, sp, 16 +; RV32IZCMP-NEXT: .cfi_def_cfa s0, 0 +; RV32IZCMP-NEXT: addi a0, a0, 15 +; RV32IZCMP-NEXT: andi a0, a0, -16 +; RV32IZCMP-NEXT: sub a0, sp, a0 +; RV32IZCMP-NEXT: mv sp, a0 +; RV32IZCMP-NEXT: call callee_void@plt +; RV32IZCMP-NEXT: li a0, 2 +; RV32IZCMP-NEXT: addi sp, s0, -16 +; RV32IZCMP-NEXT: cm.pop {ra, s0}, 16 +; RV32IZCMP-NEXT: ret +; +; RV64IZCMP-LABEL: pushpopret2: +; RV64IZCMP: # %bb.0: # %entry +; RV64IZCMP-NEXT: .cfi_def_cfa_offset 16 +; RV64IZCMP-NEXT: cm.push {ra, s0}, -16 +; RV64IZCMP-NEXT: .cfi_offset ra, -8 +; RV64IZCMP-NEXT: .cfi_offset s0, -16 +; RV64IZCMP-NEXT: addi s0, sp, 16 +; RV64IZCMP-NEXT: .cfi_def_cfa s0, 0 +; RV64IZCMP-NEXT: slli a0, a0, 32 +; RV64IZCMP-NEXT: srli a0, a0, 32 +; RV64IZCMP-NEXT: addi a0, a0, 15 +; RV64IZCMP-NEXT: andi a0, a0, -16 +; RV64IZCMP-NEXT: sub a0, sp, a0 +; RV64IZCMP-NEXT: mv sp, a0 +; RV64IZCMP-NEXT: call callee_void@plt +; RV64IZCMP-NEXT: li a0, 2 +; RV64IZCMP-NEXT: addi sp, s0, -16 +; RV64IZCMP-NEXT: cm.pop {ra, s0}, 16 +; RV64IZCMP-NEXT: ret +; +; RV32I-LABEL: pushpopret2: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: .cfi_def_cfa_offset 16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: .cfi_offset ra, -4 +; RV32I-NEXT: .cfi_offset s0, -8 +; RV32I-NEXT: addi s0, sp, 16 +; RV32I-NEXT: .cfi_def_cfa s0, 0 +; RV32I-NEXT: addi a0, a0, 15 +; RV32I-NEXT: andi a0, a0, -16 +; RV32I-NEXT: sub a0, sp, a0 +; RV32I-NEXT: mv sp, a0 +; RV32I-NEXT: call callee_void@plt +; RV32I-NEXT: li a0, 2 +; RV32I-NEXT: addi sp, s0, -16 +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; +; RV64I-LABEL: pushpopret2: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: .cfi_def_cfa_offset 16 +; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: .cfi_offset s0, -16 +; RV64I-NEXT: addi s0, sp, 16 +; RV64I-NEXT: .cfi_def_cfa s0, 0 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: srli a0, a0, 32 +; RV64I-NEXT: addi a0, a0, 15 +; RV64I-NEXT: andi a0, a0, -16 +; RV64I-NEXT: sub a0, sp, a0 +; RV64I-NEXT: mv sp, a0 +; RV64I-NEXT: call callee_void@plt +; RV64I-NEXT: li a0, 2 +; RV64I-NEXT: addi sp, s0, -16 +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret +entry: + %0 = alloca i8, i32 %size, align 16 + call void @callee_void(i8* nonnull %0) + ret i32 2 +} + +define dso_local i32 @tailcall(i32 signext %size) local_unnamed_addr #0 { +; RV32IZCMP-LABEL: tailcall: +; RV32IZCMP: # %bb.0: # %entry +; RV32IZCMP-NEXT: .cfi_def_cfa_offset 16 +; RV32IZCMP-NEXT: cm.push {ra, s0}, -16 +; RV32IZCMP-NEXT: .cfi_offset ra, -4 +; RV32IZCMP-NEXT: .cfi_offset s0, -8 +; RV32IZCMP-NEXT: addi s0, sp, 16 +; RV32IZCMP-NEXT: .cfi_def_cfa s0, 0 +; RV32IZCMP-NEXT: addi a0, a0, 15 +; RV32IZCMP-NEXT: andi a0, a0, -16 +; RV32IZCMP-NEXT: sub a0, sp, a0 +; RV32IZCMP-NEXT: mv sp, a0 +; RV32IZCMP-NEXT: addi sp, s0, -16 +; RV32IZCMP-NEXT: cm.pop {ra, s0}, 16 +; RV32IZCMP-NEXT: tail callee@plt +; +; RV64IZCMP-LABEL: tailcall: +; RV64IZCMP: # %bb.0: # %entry +; RV64IZCMP-NEXT: .cfi_def_cfa_offset 16 +; RV64IZCMP-NEXT: cm.push {ra, s0}, -16 +; RV64IZCMP-NEXT: .cfi_offset ra, -8 +; RV64IZCMP-NEXT: .cfi_offset s0, -16 +; RV64IZCMP-NEXT: addi s0, sp, 16 +; RV64IZCMP-NEXT: .cfi_def_cfa s0, 0 +; RV64IZCMP-NEXT: slli a0, a0, 32 +; RV64IZCMP-NEXT: srli a0, a0, 32 +; RV64IZCMP-NEXT: addi a0, a0, 15 +; RV64IZCMP-NEXT: andi a0, a0, -16 +; RV64IZCMP-NEXT: sub a0, sp, a0 +; RV64IZCMP-NEXT: mv sp, a0 +; RV64IZCMP-NEXT: addi sp, s0, -16 +; RV64IZCMP-NEXT: cm.pop {ra, s0}, 16 +; RV64IZCMP-NEXT: tail callee@plt +; +; RV32I-LABEL: tailcall: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: .cfi_def_cfa_offset 16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: .cfi_offset ra, -4 +; RV32I-NEXT: .cfi_offset s0, -8 +; RV32I-NEXT: addi s0, sp, 16 +; RV32I-NEXT: .cfi_def_cfa s0, 0 +; RV32I-NEXT: addi a0, a0, 15 +; RV32I-NEXT: andi a0, a0, -16 +; RV32I-NEXT: sub a0, sp, a0 +; RV32I-NEXT: mv sp, a0 +; RV32I-NEXT: addi sp, s0, -16 +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: tail callee@plt +; +; RV64I-LABEL: tailcall: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: .cfi_def_cfa_offset 16 +; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: .cfi_offset s0, -16 +; RV64I-NEXT: addi s0, sp, 16 +; RV64I-NEXT: .cfi_def_cfa s0, 0 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: srli a0, a0, 32 +; RV64I-NEXT: addi a0, a0, 15 +; RV64I-NEXT: andi a0, a0, -16 +; RV64I-NEXT: sub a0, sp, a0 +; RV64I-NEXT: mv sp, a0 +; RV64I-NEXT: addi sp, s0, -16 +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: tail callee@plt +entry: + %0 = alloca i8, i32 %size, align 16 + %1 = tail call i32 @callee(i8* nonnull %0) + ret i32 %1 +} + +@var = global [5 x i32] zeroinitializer +define i32 @nocompress(i32 signext %size) { +; RV32IZCMP-LABEL: nocompress: +; RV32IZCMP: # %bb.0: # %entry +; RV32IZCMP-NEXT: .cfi_def_cfa_offset 48 +; RV32IZCMP-NEXT: cm.push {ra, s0-s8}, -48 +; RV32IZCMP-NEXT: .cfi_offset ra, -4 +; RV32IZCMP-NEXT: .cfi_offset s0, -8 +; RV32IZCMP-NEXT: .cfi_offset s1, -12 +; RV32IZCMP-NEXT: .cfi_offset s2, -16 +; RV32IZCMP-NEXT: .cfi_offset s3, -20 +; RV32IZCMP-NEXT: .cfi_offset s4, -24 +; RV32IZCMP-NEXT: .cfi_offset s5, -28 +; RV32IZCMP-NEXT: .cfi_offset s6, -32 +; RV32IZCMP-NEXT: .cfi_offset s7, -36 +; RV32IZCMP-NEXT: .cfi_offset s8, -40 +; RV32IZCMP-NEXT: addi s0, sp, 48 +; RV32IZCMP-NEXT: .cfi_def_cfa s0, 0 +; RV32IZCMP-NEXT: addi a0, a0, 15 +; RV32IZCMP-NEXT: andi a0, a0, -16 +; RV32IZCMP-NEXT: sub s2, sp, a0 +; RV32IZCMP-NEXT: mv sp, s2 +; RV32IZCMP-NEXT: lui s1, %hi(var) +; RV32IZCMP-NEXT: lw s3, %lo(var)(s1) +; RV32IZCMP-NEXT: lw s4, %lo(var+4)(s1) +; RV32IZCMP-NEXT: lw s5, %lo(var+8)(s1) +; RV32IZCMP-NEXT: lw s6, %lo(var+12)(s1) +; RV32IZCMP-NEXT: addi s7, s1, %lo(var) +; RV32IZCMP-NEXT: lw s8, 16(s7) +; RV32IZCMP-NEXT: mv a0, s2 +; RV32IZCMP-NEXT: call callee_void@plt +; RV32IZCMP-NEXT: sw s8, 16(s7) +; RV32IZCMP-NEXT: sw s6, %lo(var+12)(s1) +; RV32IZCMP-NEXT: sw s5, %lo(var+8)(s1) +; RV32IZCMP-NEXT: sw s4, %lo(var+4)(s1) +; RV32IZCMP-NEXT: sw s3, %lo(var)(s1) +; RV32IZCMP-NEXT: mv a0, s2 +; RV32IZCMP-NEXT: addi sp, s0, -48 +; RV32IZCMP-NEXT: cm.pop {ra, s0-s8}, 48 +; RV32IZCMP-NEXT: tail callee@plt +; +; RV64IZCMP-LABEL: nocompress: +; RV64IZCMP: # %bb.0: # %entry +; RV64IZCMP-NEXT: .cfi_def_cfa_offset 80 +; RV64IZCMP-NEXT: cm.push {ra, s0-s8}, -80 +; RV64IZCMP-NEXT: .cfi_offset ra, -8 +; RV64IZCMP-NEXT: .cfi_offset s0, -16 +; RV64IZCMP-NEXT: .cfi_offset s1, -24 +; RV64IZCMP-NEXT: .cfi_offset s2, -32 +; RV64IZCMP-NEXT: .cfi_offset s3, -40 +; RV64IZCMP-NEXT: .cfi_offset s4, -48 +; RV64IZCMP-NEXT: .cfi_offset s5, -56 +; RV64IZCMP-NEXT: .cfi_offset s6, -64 +; RV64IZCMP-NEXT: .cfi_offset s7, -72 +; RV64IZCMP-NEXT: .cfi_offset s8, -80 +; RV64IZCMP-NEXT: addi s0, sp, 80 +; RV64IZCMP-NEXT: .cfi_def_cfa s0, 0 +; RV64IZCMP-NEXT: slli a0, a0, 32 +; RV64IZCMP-NEXT: srli a0, a0, 32 +; RV64IZCMP-NEXT: addi a0, a0, 15 +; RV64IZCMP-NEXT: andi a0, a0, -16 +; RV64IZCMP-NEXT: sub s2, sp, a0 +; RV64IZCMP-NEXT: mv sp, s2 +; RV64IZCMP-NEXT: lui s1, %hi(var) +; RV64IZCMP-NEXT: lw s3, %lo(var)(s1) +; RV64IZCMP-NEXT: lw s4, %lo(var+4)(s1) +; RV64IZCMP-NEXT: lw s5, %lo(var+8)(s1) +; RV64IZCMP-NEXT: lw s6, %lo(var+12)(s1) +; RV64IZCMP-NEXT: addi s7, s1, %lo(var) +; RV64IZCMP-NEXT: lw s8, 16(s7) +; RV64IZCMP-NEXT: mv a0, s2 +; RV64IZCMP-NEXT: call callee_void@plt +; RV64IZCMP-NEXT: sw s8, 16(s7) +; RV64IZCMP-NEXT: sw s6, %lo(var+12)(s1) +; RV64IZCMP-NEXT: sw s5, %lo(var+8)(s1) +; RV64IZCMP-NEXT: sw s4, %lo(var+4)(s1) +; RV64IZCMP-NEXT: sw s3, %lo(var)(s1) +; RV64IZCMP-NEXT: mv a0, s2 +; RV64IZCMP-NEXT: addi sp, s0, -80 +; RV64IZCMP-NEXT: cm.pop {ra, s0-s8}, 80 +; RV64IZCMP-NEXT: tail callee@plt +; +; RV32I-LABEL: nocompress: +; RV32I: # %bb.0: # %entry +; RV32I-NEXT: addi sp, sp, -48 +; RV32I-NEXT: .cfi_def_cfa_offset 48 +; RV32I-NEXT: sw ra, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 40(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 36(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 32(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s3, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s4, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s5, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s6, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s7, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s8, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: .cfi_offset ra, -4 +; RV32I-NEXT: .cfi_offset s0, -8 +; RV32I-NEXT: .cfi_offset s1, -12 +; RV32I-NEXT: .cfi_offset s2, -16 +; RV32I-NEXT: .cfi_offset s3, -20 +; RV32I-NEXT: .cfi_offset s4, -24 +; RV32I-NEXT: .cfi_offset s5, -28 +; RV32I-NEXT: .cfi_offset s6, -32 +; RV32I-NEXT: .cfi_offset s7, -36 +; RV32I-NEXT: .cfi_offset s8, -40 +; RV32I-NEXT: addi s0, sp, 48 +; RV32I-NEXT: .cfi_def_cfa s0, 0 +; RV32I-NEXT: addi a0, a0, 15 +; RV32I-NEXT: andi a0, a0, -16 +; RV32I-NEXT: sub s1, sp, a0 +; RV32I-NEXT: mv sp, s1 +; RV32I-NEXT: lui s2, %hi(var) +; RV32I-NEXT: lw s3, %lo(var)(s2) +; RV32I-NEXT: lw s4, %lo(var+4)(s2) +; RV32I-NEXT: lw s5, %lo(var+8)(s2) +; RV32I-NEXT: lw s6, %lo(var+12)(s2) +; RV32I-NEXT: addi s7, s2, %lo(var) +; RV32I-NEXT: lw s8, 16(s7) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: call callee_void@plt +; RV32I-NEXT: sw s8, 16(s7) +; RV32I-NEXT: sw s6, %lo(var+12)(s2) +; RV32I-NEXT: sw s5, %lo(var+8)(s2) +; RV32I-NEXT: sw s4, %lo(var+4)(s2) +; RV32I-NEXT: sw s3, %lo(var)(s2) +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: addi sp, s0, -48 +; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 48 +; RV32I-NEXT: tail callee@plt +; +; RV64I-LABEL: nocompress: +; RV64I: # %bb.0: # %entry +; RV64I-NEXT: addi sp, sp, -80 +; RV64I-NEXT: .cfi_def_cfa_offset 80 +; RV64I-NEXT: sd ra, 72(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s0, 64(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s1, 56(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s2, 48(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s3, 40(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s4, 32(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s5, 24(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s6, 16(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s7, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s8, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: .cfi_offset ra, -8 +; RV64I-NEXT: .cfi_offset s0, -16 +; RV64I-NEXT: .cfi_offset s1, -24 +; RV64I-NEXT: .cfi_offset s2, -32 +; RV64I-NEXT: .cfi_offset s3, -40 +; RV64I-NEXT: .cfi_offset s4, -48 +; RV64I-NEXT: .cfi_offset s5, -56 +; RV64I-NEXT: .cfi_offset s6, -64 +; RV64I-NEXT: .cfi_offset s7, -72 +; RV64I-NEXT: .cfi_offset s8, -80 +; RV64I-NEXT: addi s0, sp, 80 +; RV64I-NEXT: .cfi_def_cfa s0, 0 +; RV64I-NEXT: slli a0, a0, 32 +; RV64I-NEXT: srli a0, a0, 32 +; RV64I-NEXT: addi a0, a0, 15 +; RV64I-NEXT: andi a0, a0, -16 +; RV64I-NEXT: sub s1, sp, a0 +; RV64I-NEXT: mv sp, s1 +; RV64I-NEXT: lui s2, %hi(var) +; RV64I-NEXT: lw s3, %lo(var)(s2) +; RV64I-NEXT: lw s4, %lo(var+4)(s2) +; RV64I-NEXT: lw s5, %lo(var+8)(s2) +; RV64I-NEXT: lw s6, %lo(var+12)(s2) +; RV64I-NEXT: addi s7, s2, %lo(var) +; RV64I-NEXT: lw s8, 16(s7) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: call callee_void@plt +; RV64I-NEXT: sw s8, 16(s7) +; RV64I-NEXT: sw s6, %lo(var+12)(s2) +; RV64I-NEXT: sw s5, %lo(var+8)(s2) +; RV64I-NEXT: sw s4, %lo(var+4)(s2) +; RV64I-NEXT: sw s3, %lo(var)(s2) +; RV64I-NEXT: mv a0, s1 +; RV64I-NEXT: addi sp, s0, -80 +; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s0, 64(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s1, 56(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s2, 48(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s3, 40(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s4, 32(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s5, 24(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s6, 16(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s7, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s8, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 80 +; RV64I-NEXT: tail callee@plt +entry: + %0 = alloca i8, i32 %size, align 16 + %val = load [5 x i32], [5 x i32]* @var + call void @callee_void(i8* nonnull %0) + store volatile [5 x i32] %val, [5 x i32]* @var + %1 = tail call i32 @callee(i8* nonnull %0) + ret i32 %1 +} + +declare void @callee_void(i8*) +declare i32 @callee(i8*) + +declare i32 @foo_test_irq(...) +@var_test_irq = global [32 x i32] zeroinitializer + +define void @foo_with_irq() nounwind "interrupt"="user" { +; RV32IZCMP-LABEL: foo_with_irq: +; RV32IZCMP: # %bb.0: +; RV32IZCMP-NEXT: cm.push {ra}, -64 +; RV32IZCMP-NEXT: sw t0, 56(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw t1, 52(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw t2, 48(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a0, 44(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a1, 40(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a2, 36(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a3, 32(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a4, 28(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a5, 24(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a6, 20(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a7, 16(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw t3, 12(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw t4, 8(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw t5, 4(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw t6, 0(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: call foo_test_irq@plt +; RV32IZCMP-NEXT: lw t0, 56(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw t1, 52(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw t2, 48(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a0, 44(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a1, 40(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a2, 36(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a3, 32(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a4, 28(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a5, 24(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a6, 20(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a7, 16(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw t3, 12(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw t4, 8(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw t5, 4(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw t6, 0(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: cm.pop {ra}, 64 +; RV32IZCMP-NEXT: mret +; +; RV64IZCMP-LABEL: foo_with_irq: +; RV64IZCMP: # %bb.0: +; RV64IZCMP-NEXT: cm.push {ra}, -64 +; RV64IZCMP-NEXT: addi sp, sp, -64 +; RV64IZCMP-NEXT: sd t0, 112(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd t1, 104(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd t2, 96(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a0, 88(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a1, 80(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a2, 72(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a3, 64(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a4, 56(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a5, 48(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a6, 40(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a7, 32(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd t3, 24(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd t4, 16(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd t5, 8(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd t6, 0(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: call foo_test_irq@plt +; RV64IZCMP-NEXT: ld t0, 112(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld t1, 104(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld t2, 96(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a0, 88(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a1, 80(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a2, 72(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a3, 64(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a4, 56(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a5, 48(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a6, 40(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a7, 32(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld t3, 24(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld t4, 16(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld t5, 8(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld t6, 0(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: addi sp, sp, 64 +; RV64IZCMP-NEXT: cm.pop {ra}, 64 +; RV64IZCMP-NEXT: mret +; +; RV32I-LABEL: foo_with_irq: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -64 +; RV32I-NEXT: sw ra, 60(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t0, 56(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t1, 52(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t2, 48(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a0, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a1, 40(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a2, 36(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a3, 32(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a4, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a5, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a6, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a7, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t3, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t4, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t5, 4(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t6, 0(sp) # 4-byte Folded Spill +; RV32I-NEXT: call foo_test_irq@plt +; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t0, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t1, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t2, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a0, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a1, 40(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a2, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a3, 32(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a4, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a5, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a6, 20(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a7, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t3, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t4, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t5, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t6, 0(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 64 +; RV32I-NEXT: mret +; +; RV64I-LABEL: foo_with_irq: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -128 +; RV64I-NEXT: sd ra, 120(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t0, 112(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t1, 104(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t2, 96(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a0, 88(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a1, 80(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a2, 72(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a3, 64(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a4, 56(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a5, 48(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a6, 40(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a7, 32(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t3, 24(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t4, 16(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t5, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t6, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: call foo_test_irq@plt +; RV64I-NEXT: ld ra, 120(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t0, 112(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t1, 104(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t2, 96(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a0, 88(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a1, 80(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a2, 72(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a3, 64(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a4, 56(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a5, 48(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a6, 40(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a7, 32(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t3, 24(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t4, 16(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t5, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t6, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 128 +; RV64I-NEXT: mret + %call = call i32 bitcast (i32 (...)* @foo_test_irq to i32 ()*)() + ret void +} + +define void @foo_no_irq() nounwind{ +; RV32IZCMP-LABEL: foo_no_irq: +; RV32IZCMP: # %bb.0: +; RV32IZCMP-NEXT: cm.push {ra}, -16 +; RV32IZCMP-NEXT: call foo_test_irq@plt +; RV32IZCMP-NEXT: cm.pop {ra}, 16 +; RV32IZCMP-NEXT: ret +; +; RV64IZCMP-LABEL: foo_no_irq: +; RV64IZCMP: # %bb.0: +; RV64IZCMP-NEXT: cm.push {ra}, -16 +; RV64IZCMP-NEXT: call foo_test_irq@plt +; RV64IZCMP-NEXT: cm.pop {ra}, 16 +; RV64IZCMP-NEXT: ret +; +; RV32I-LABEL: foo_no_irq: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: call foo_test_irq@plt +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: ret +; +; RV64I-LABEL: foo_no_irq: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -16 +; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: call foo_test_irq@plt +; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 16 +; RV64I-NEXT: ret + %call = call i32 bitcast (i32 (...)* @foo_test_irq to i32 ()*)() + ret void +} + +define void @callee_with_irq() nounwind "interrupt"="user" { +; RV32IZCMP-LABEL: callee_with_irq: +; RV32IZCMP: # %bb.0: +; RV32IZCMP-NEXT: cm.push {ra, s0-s11}, -112 +; RV32IZCMP-NEXT: addi sp, sp, -32 +; RV32IZCMP-NEXT: sw t0, 88(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw t1, 84(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw t2, 80(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a0, 76(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a1, 72(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a2, 68(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a3, 64(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a4, 60(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a5, 56(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a6, 52(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw a7, 48(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw t3, 44(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw t4, 40(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw t5, 36(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: sw t6, 32(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lui a7, %hi(var_test_irq) +; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq)(a7) +; RV32IZCMP-NEXT: sw a0, 28(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq+4)(a7) +; RV32IZCMP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq+8)(a7) +; RV32IZCMP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq+12)(a7) +; RV32IZCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: addi a5, a7, %lo(var_test_irq) +; RV32IZCMP-NEXT: lw a0, 16(a5) +; RV32IZCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 20(a5) +; RV32IZCMP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw t4, 24(a5) +; RV32IZCMP-NEXT: lw t5, 28(a5) +; RV32IZCMP-NEXT: lw t6, 32(a5) +; RV32IZCMP-NEXT: lw s2, 36(a5) +; RV32IZCMP-NEXT: lw s3, 40(a5) +; RV32IZCMP-NEXT: lw s4, 44(a5) +; RV32IZCMP-NEXT: lw s5, 48(a5) +; RV32IZCMP-NEXT: lw s6, 52(a5) +; RV32IZCMP-NEXT: lw s7, 56(a5) +; RV32IZCMP-NEXT: lw s8, 60(a5) +; RV32IZCMP-NEXT: lw s9, 64(a5) +; RV32IZCMP-NEXT: lw s10, 68(a5) +; RV32IZCMP-NEXT: lw s11, 72(a5) +; RV32IZCMP-NEXT: lw ra, 76(a5) +; RV32IZCMP-NEXT: lw s1, 80(a5) +; RV32IZCMP-NEXT: lw t3, 84(a5) +; RV32IZCMP-NEXT: lw t2, 88(a5) +; RV32IZCMP-NEXT: lw t1, 92(a5) +; RV32IZCMP-NEXT: lw t0, 96(a5) +; RV32IZCMP-NEXT: lw s0, 100(a5) +; RV32IZCMP-NEXT: lw a6, 104(a5) +; RV32IZCMP-NEXT: lw a4, 108(a5) +; RV32IZCMP-NEXT: lw a0, 124(a5) +; RV32IZCMP-NEXT: lw a1, 120(a5) +; RV32IZCMP-NEXT: lw a2, 116(a5) +; RV32IZCMP-NEXT: lw a3, 112(a5) +; RV32IZCMP-NEXT: sw a0, 124(a5) +; RV32IZCMP-NEXT: sw a1, 120(a5) +; RV32IZCMP-NEXT: sw a2, 116(a5) +; RV32IZCMP-NEXT: sw a3, 112(a5) +; RV32IZCMP-NEXT: sw a4, 108(a5) +; RV32IZCMP-NEXT: sw a6, 104(a5) +; RV32IZCMP-NEXT: sw s0, 100(a5) +; RV32IZCMP-NEXT: sw t0, 96(a5) +; RV32IZCMP-NEXT: sw t1, 92(a5) +; RV32IZCMP-NEXT: sw t2, 88(a5) +; RV32IZCMP-NEXT: sw t3, 84(a5) +; RV32IZCMP-NEXT: sw s1, 80(a5) +; RV32IZCMP-NEXT: sw ra, 76(a5) +; RV32IZCMP-NEXT: sw s11, 72(a5) +; RV32IZCMP-NEXT: sw s10, 68(a5) +; RV32IZCMP-NEXT: sw s9, 64(a5) +; RV32IZCMP-NEXT: sw s8, 60(a5) +; RV32IZCMP-NEXT: sw s7, 56(a5) +; RV32IZCMP-NEXT: sw s6, 52(a5) +; RV32IZCMP-NEXT: sw s5, 48(a5) +; RV32IZCMP-NEXT: sw s4, 44(a5) +; RV32IZCMP-NEXT: sw s3, 40(a5) +; RV32IZCMP-NEXT: sw s2, 36(a5) +; RV32IZCMP-NEXT: sw t6, 32(a5) +; RV32IZCMP-NEXT: sw t5, 28(a5) +; RV32IZCMP-NEXT: sw t4, 24(a5) +; RV32IZCMP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 20(a5) +; RV32IZCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 16(a5) +; RV32IZCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq+12)(a7) +; RV32IZCMP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq+8)(a7) +; RV32IZCMP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq+4)(a7) +; RV32IZCMP-NEXT: lw a0, 28(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq)(a7) +; RV32IZCMP-NEXT: lw t0, 88(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw t1, 84(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw t2, 80(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a0, 76(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a1, 72(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a2, 68(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a3, 64(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a4, 60(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a5, 56(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a6, 52(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw a7, 48(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw t3, 44(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw t4, 40(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw t5, 36(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: lw t6, 32(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: addi sp, sp, 32 +; RV32IZCMP-NEXT: cm.pop {ra, s0-s11}, 112 +; RV32IZCMP-NEXT: mret +; +; RV64IZCMP-LABEL: callee_with_irq: +; RV64IZCMP: # %bb.0: +; RV64IZCMP-NEXT: cm.push {ra, s0-s11}, -160 +; RV64IZCMP-NEXT: addi sp, sp, -112 +; RV64IZCMP-NEXT: sd t0, 160(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd t1, 152(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd t2, 144(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a0, 136(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a1, 128(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a2, 120(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a3, 112(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a4, 104(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a5, 96(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a6, 88(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd a7, 80(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd t3, 72(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd t4, 64(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd t5, 56(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: sd t6, 48(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lui a7, %hi(var_test_irq) +; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq)(a7) +; RV64IZCMP-NEXT: sd a0, 40(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq+4)(a7) +; RV64IZCMP-NEXT: sd a0, 32(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq+8)(a7) +; RV64IZCMP-NEXT: sd a0, 24(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq+12)(a7) +; RV64IZCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: addi a5, a7, %lo(var_test_irq) +; RV64IZCMP-NEXT: lw a0, 16(a5) +; RV64IZCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 20(a5) +; RV64IZCMP-NEXT: sd a0, 0(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw t4, 24(a5) +; RV64IZCMP-NEXT: lw t5, 28(a5) +; RV64IZCMP-NEXT: lw t6, 32(a5) +; RV64IZCMP-NEXT: lw s2, 36(a5) +; RV64IZCMP-NEXT: lw s3, 40(a5) +; RV64IZCMP-NEXT: lw s4, 44(a5) +; RV64IZCMP-NEXT: lw s5, 48(a5) +; RV64IZCMP-NEXT: lw s6, 52(a5) +; RV64IZCMP-NEXT: lw s7, 56(a5) +; RV64IZCMP-NEXT: lw s8, 60(a5) +; RV64IZCMP-NEXT: lw s9, 64(a5) +; RV64IZCMP-NEXT: lw s10, 68(a5) +; RV64IZCMP-NEXT: lw s11, 72(a5) +; RV64IZCMP-NEXT: lw ra, 76(a5) +; RV64IZCMP-NEXT: lw s1, 80(a5) +; RV64IZCMP-NEXT: lw t3, 84(a5) +; RV64IZCMP-NEXT: lw t2, 88(a5) +; RV64IZCMP-NEXT: lw t1, 92(a5) +; RV64IZCMP-NEXT: lw t0, 96(a5) +; RV64IZCMP-NEXT: lw s0, 100(a5) +; RV64IZCMP-NEXT: lw a6, 104(a5) +; RV64IZCMP-NEXT: lw a4, 108(a5) +; RV64IZCMP-NEXT: lw a0, 124(a5) +; RV64IZCMP-NEXT: lw a1, 120(a5) +; RV64IZCMP-NEXT: lw a2, 116(a5) +; RV64IZCMP-NEXT: lw a3, 112(a5) +; RV64IZCMP-NEXT: sw a0, 124(a5) +; RV64IZCMP-NEXT: sw a1, 120(a5) +; RV64IZCMP-NEXT: sw a2, 116(a5) +; RV64IZCMP-NEXT: sw a3, 112(a5) +; RV64IZCMP-NEXT: sw a4, 108(a5) +; RV64IZCMP-NEXT: sw a6, 104(a5) +; RV64IZCMP-NEXT: sw s0, 100(a5) +; RV64IZCMP-NEXT: sw t0, 96(a5) +; RV64IZCMP-NEXT: sw t1, 92(a5) +; RV64IZCMP-NEXT: sw t2, 88(a5) +; RV64IZCMP-NEXT: sw t3, 84(a5) +; RV64IZCMP-NEXT: sw s1, 80(a5) +; RV64IZCMP-NEXT: sw ra, 76(a5) +; RV64IZCMP-NEXT: sw s11, 72(a5) +; RV64IZCMP-NEXT: sw s10, 68(a5) +; RV64IZCMP-NEXT: sw s9, 64(a5) +; RV64IZCMP-NEXT: sw s8, 60(a5) +; RV64IZCMP-NEXT: sw s7, 56(a5) +; RV64IZCMP-NEXT: sw s6, 52(a5) +; RV64IZCMP-NEXT: sw s5, 48(a5) +; RV64IZCMP-NEXT: sw s4, 44(a5) +; RV64IZCMP-NEXT: sw s3, 40(a5) +; RV64IZCMP-NEXT: sw s2, 36(a5) +; RV64IZCMP-NEXT: sw t6, 32(a5) +; RV64IZCMP-NEXT: sw t5, 28(a5) +; RV64IZCMP-NEXT: sw t4, 24(a5) +; RV64IZCMP-NEXT: ld a0, 0(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 20(a5) +; RV64IZCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 16(a5) +; RV64IZCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq+12)(a7) +; RV64IZCMP-NEXT: ld a0, 24(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq+8)(a7) +; RV64IZCMP-NEXT: ld a0, 32(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq+4)(a7) +; RV64IZCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq)(a7) +; RV64IZCMP-NEXT: ld t0, 160(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld t1, 152(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld t2, 144(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a0, 136(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a1, 128(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a2, 120(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a3, 112(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a4, 104(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a5, 96(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a6, 88(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld a7, 80(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld t3, 72(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld t4, 64(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld t5, 56(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: ld t6, 48(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: addi sp, sp, 112 +; RV64IZCMP-NEXT: cm.pop {ra, s0-s11}, 160 +; RV64IZCMP-NEXT: mret +; +; RV32I-LABEL: callee_with_irq: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -144 +; RV32I-NEXT: sw ra, 140(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t0, 136(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t1, 132(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t2, 128(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 124(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 120(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a0, 116(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a1, 112(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a2, 108(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a3, 104(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a4, 100(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a5, 96(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a6, 92(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw a7, 88(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 84(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s3, 80(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s4, 76(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s5, 72(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s6, 68(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s7, 64(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s8, 60(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s9, 56(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s10, 52(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s11, 48(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t3, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t4, 40(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t5, 36(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw t6, 32(sp) # 4-byte Folded Spill +; RV32I-NEXT: lui a7, %hi(var_test_irq) +; RV32I-NEXT: lw a0, %lo(var_test_irq)(a7) +; RV32I-NEXT: sw a0, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw a0, %lo(var_test_irq+4)(a7) +; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw a0, %lo(var_test_irq+8)(a7) +; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw a0, %lo(var_test_irq+12)(a7) +; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: addi a5, a7, %lo(var_test_irq) +; RV32I-NEXT: lw a0, 16(a5) +; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw a0, 20(a5) +; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw t0, 24(a5) +; RV32I-NEXT: lw t1, 28(a5) +; RV32I-NEXT: lw t2, 32(a5) +; RV32I-NEXT: lw t3, 36(a5) +; RV32I-NEXT: lw t4, 40(a5) +; RV32I-NEXT: lw t5, 44(a5) +; RV32I-NEXT: lw t6, 48(a5) +; RV32I-NEXT: lw s0, 52(a5) +; RV32I-NEXT: lw s1, 56(a5) +; RV32I-NEXT: lw s2, 60(a5) +; RV32I-NEXT: lw s3, 64(a5) +; RV32I-NEXT: lw s4, 68(a5) +; RV32I-NEXT: lw s5, 72(a5) +; RV32I-NEXT: lw s6, 76(a5) +; RV32I-NEXT: lw s7, 80(a5) +; RV32I-NEXT: lw s8, 84(a5) +; RV32I-NEXT: lw s9, 88(a5) +; RV32I-NEXT: lw s10, 92(a5) +; RV32I-NEXT: lw s11, 96(a5) +; RV32I-NEXT: lw ra, 100(a5) +; RV32I-NEXT: lw a6, 104(a5) +; RV32I-NEXT: lw a4, 108(a5) +; RV32I-NEXT: lw a0, 124(a5) +; RV32I-NEXT: lw a1, 120(a5) +; RV32I-NEXT: lw a2, 116(a5) +; RV32I-NEXT: lw a3, 112(a5) +; RV32I-NEXT: sw a0, 124(a5) +; RV32I-NEXT: sw a1, 120(a5) +; RV32I-NEXT: sw a2, 116(a5) +; RV32I-NEXT: sw a3, 112(a5) +; RV32I-NEXT: sw a4, 108(a5) +; RV32I-NEXT: sw a6, 104(a5) +; RV32I-NEXT: sw ra, 100(a5) +; RV32I-NEXT: sw s11, 96(a5) +; RV32I-NEXT: sw s10, 92(a5) +; RV32I-NEXT: sw s9, 88(a5) +; RV32I-NEXT: sw s8, 84(a5) +; RV32I-NEXT: sw s7, 80(a5) +; RV32I-NEXT: sw s6, 76(a5) +; RV32I-NEXT: sw s5, 72(a5) +; RV32I-NEXT: sw s4, 68(a5) +; RV32I-NEXT: sw s3, 64(a5) +; RV32I-NEXT: sw s2, 60(a5) +; RV32I-NEXT: sw s1, 56(a5) +; RV32I-NEXT: sw s0, 52(a5) +; RV32I-NEXT: sw t6, 48(a5) +; RV32I-NEXT: sw t5, 44(a5) +; RV32I-NEXT: sw t4, 40(a5) +; RV32I-NEXT: sw t3, 36(a5) +; RV32I-NEXT: sw t2, 32(a5) +; RV32I-NEXT: sw t1, 28(a5) +; RV32I-NEXT: sw t0, 24(a5) +; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, 20(a5) +; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, 16(a5) +; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, %lo(var_test_irq+12)(a7) +; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, %lo(var_test_irq+8)(a7) +; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, %lo(var_test_irq+4)(a7) +; RV32I-NEXT: lw a0, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, %lo(var_test_irq)(a7) +; RV32I-NEXT: lw ra, 140(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t0, 136(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t1, 132(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t2, 128(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 124(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 120(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a0, 116(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a1, 112(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a2, 108(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a3, 104(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a4, 100(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a5, 96(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a6, 92(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw a7, 88(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 84(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s3, 80(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s4, 76(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s5, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s6, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s7, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s8, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s9, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s10, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s11, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t3, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t4, 40(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t5, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw t6, 32(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 144 +; RV32I-NEXT: mret +; +; RV64I-LABEL: callee_with_irq: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -272 +; RV64I-NEXT: sd ra, 264(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t0, 256(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t1, 248(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t2, 240(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s0, 232(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s1, 224(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a0, 216(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a1, 208(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a2, 200(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a3, 192(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a4, 184(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a5, 176(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a6, 168(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd a7, 160(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s2, 152(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s3, 144(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s4, 136(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s5, 128(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s6, 120(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s7, 112(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s8, 104(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s9, 96(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s10, 88(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s11, 80(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t3, 72(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t4, 64(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t5, 56(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd t6, 48(sp) # 8-byte Folded Spill +; RV64I-NEXT: lui a7, %hi(var_test_irq) +; RV64I-NEXT: lw a0, %lo(var_test_irq)(a7) +; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill +; RV64I-NEXT: lw a0, %lo(var_test_irq+4)(a7) +; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill +; RV64I-NEXT: lw a0, %lo(var_test_irq+8)(a7) +; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill +; RV64I-NEXT: lw a0, %lo(var_test_irq+12)(a7) +; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill +; RV64I-NEXT: addi a5, a7, %lo(var_test_irq) +; RV64I-NEXT: lw a0, 16(a5) +; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: lw a0, 20(a5) +; RV64I-NEXT: sd a0, 0(sp) # 8-byte Folded Spill +; RV64I-NEXT: lw t0, 24(a5) +; RV64I-NEXT: lw t1, 28(a5) +; RV64I-NEXT: lw t2, 32(a5) +; RV64I-NEXT: lw t3, 36(a5) +; RV64I-NEXT: lw t4, 40(a5) +; RV64I-NEXT: lw t5, 44(a5) +; RV64I-NEXT: lw t6, 48(a5) +; RV64I-NEXT: lw s0, 52(a5) +; RV64I-NEXT: lw s1, 56(a5) +; RV64I-NEXT: lw s2, 60(a5) +; RV64I-NEXT: lw s3, 64(a5) +; RV64I-NEXT: lw s4, 68(a5) +; RV64I-NEXT: lw s5, 72(a5) +; RV64I-NEXT: lw s6, 76(a5) +; RV64I-NEXT: lw s7, 80(a5) +; RV64I-NEXT: lw s8, 84(a5) +; RV64I-NEXT: lw s9, 88(a5) +; RV64I-NEXT: lw s10, 92(a5) +; RV64I-NEXT: lw s11, 96(a5) +; RV64I-NEXT: lw ra, 100(a5) +; RV64I-NEXT: lw a6, 104(a5) +; RV64I-NEXT: lw a4, 108(a5) +; RV64I-NEXT: lw a0, 124(a5) +; RV64I-NEXT: lw a1, 120(a5) +; RV64I-NEXT: lw a2, 116(a5) +; RV64I-NEXT: lw a3, 112(a5) +; RV64I-NEXT: sw a0, 124(a5) +; RV64I-NEXT: sw a1, 120(a5) +; RV64I-NEXT: sw a2, 116(a5) +; RV64I-NEXT: sw a3, 112(a5) +; RV64I-NEXT: sw a4, 108(a5) +; RV64I-NEXT: sw a6, 104(a5) +; RV64I-NEXT: sw ra, 100(a5) +; RV64I-NEXT: sw s11, 96(a5) +; RV64I-NEXT: sw s10, 92(a5) +; RV64I-NEXT: sw s9, 88(a5) +; RV64I-NEXT: sw s8, 84(a5) +; RV64I-NEXT: sw s7, 80(a5) +; RV64I-NEXT: sw s6, 76(a5) +; RV64I-NEXT: sw s5, 72(a5) +; RV64I-NEXT: sw s4, 68(a5) +; RV64I-NEXT: sw s3, 64(a5) +; RV64I-NEXT: sw s2, 60(a5) +; RV64I-NEXT: sw s1, 56(a5) +; RV64I-NEXT: sw s0, 52(a5) +; RV64I-NEXT: sw t6, 48(a5) +; RV64I-NEXT: sw t5, 44(a5) +; RV64I-NEXT: sw t4, 40(a5) +; RV64I-NEXT: sw t3, 36(a5) +; RV64I-NEXT: sw t2, 32(a5) +; RV64I-NEXT: sw t1, 28(a5) +; RV64I-NEXT: sw t0, 24(a5) +; RV64I-NEXT: ld a0, 0(sp) # 8-byte Folded Reload +; RV64I-NEXT: sw a0, 20(a5) +; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: sw a0, 16(a5) +; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload +; RV64I-NEXT: sw a0, %lo(var_test_irq+12)(a7) +; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload +; RV64I-NEXT: sw a0, %lo(var_test_irq+8)(a7) +; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload +; RV64I-NEXT: sw a0, %lo(var_test_irq+4)(a7) +; RV64I-NEXT: ld a0, 40(sp) # 8-byte Folded Reload +; RV64I-NEXT: sw a0, %lo(var_test_irq)(a7) +; RV64I-NEXT: ld ra, 264(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t0, 256(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t1, 248(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t2, 240(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s0, 232(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s1, 224(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a0, 216(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a1, 208(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a2, 200(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a3, 192(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a4, 184(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a5, 176(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a6, 168(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld a7, 160(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s2, 152(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s3, 144(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s4, 136(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s5, 128(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s6, 120(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s7, 112(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s8, 104(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s9, 96(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s10, 88(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s11, 80(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t3, 72(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t4, 64(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t5, 56(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld t6, 48(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 272 +; RV64I-NEXT: mret + %val = load [32 x i32], [32 x i32]* @var_test_irq + store volatile [32 x i32] %val, [32 x i32]* @var_test_irq + ret void +} + +define void @callee_no_irq() nounwind{ +; RV32IZCMP-LABEL: callee_no_irq: +; RV32IZCMP: # %bb.0: +; RV32IZCMP-NEXT: cm.push {ra, s0-s11}, -80 +; RV32IZCMP-NEXT: lui a7, %hi(var_test_irq) +; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq)(a7) +; RV32IZCMP-NEXT: sw a0, 24(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq+4)(a7) +; RV32IZCMP-NEXT: sw a0, 20(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq+8)(a7) +; RV32IZCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, %lo(var_test_irq+12)(a7) +; RV32IZCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: addi a5, a7, %lo(var_test_irq) +; RV32IZCMP-NEXT: lw a0, 16(a5) +; RV32IZCMP-NEXT: sw a0, 8(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw a0, 20(a5) +; RV32IZCMP-NEXT: sw a0, 4(sp) # 4-byte Folded Spill +; RV32IZCMP-NEXT: lw t4, 24(a5) +; RV32IZCMP-NEXT: lw t5, 28(a5) +; RV32IZCMP-NEXT: lw t6, 32(a5) +; RV32IZCMP-NEXT: lw s2, 36(a5) +; RV32IZCMP-NEXT: lw s3, 40(a5) +; RV32IZCMP-NEXT: lw s4, 44(a5) +; RV32IZCMP-NEXT: lw s5, 48(a5) +; RV32IZCMP-NEXT: lw s6, 52(a5) +; RV32IZCMP-NEXT: lw s7, 56(a5) +; RV32IZCMP-NEXT: lw s8, 60(a5) +; RV32IZCMP-NEXT: lw s9, 64(a5) +; RV32IZCMP-NEXT: lw s10, 68(a5) +; RV32IZCMP-NEXT: lw s11, 72(a5) +; RV32IZCMP-NEXT: lw ra, 76(a5) +; RV32IZCMP-NEXT: lw s1, 80(a5) +; RV32IZCMP-NEXT: lw t3, 84(a5) +; RV32IZCMP-NEXT: lw t2, 88(a5) +; RV32IZCMP-NEXT: lw t1, 92(a5) +; RV32IZCMP-NEXT: lw t0, 96(a5) +; RV32IZCMP-NEXT: lw s0, 100(a5) +; RV32IZCMP-NEXT: lw a6, 104(a5) +; RV32IZCMP-NEXT: lw a4, 108(a5) +; RV32IZCMP-NEXT: lw a0, 124(a5) +; RV32IZCMP-NEXT: lw a1, 120(a5) +; RV32IZCMP-NEXT: lw a2, 116(a5) +; RV32IZCMP-NEXT: lw a3, 112(a5) +; RV32IZCMP-NEXT: sw a0, 124(a5) +; RV32IZCMP-NEXT: sw a1, 120(a5) +; RV32IZCMP-NEXT: sw a2, 116(a5) +; RV32IZCMP-NEXT: sw a3, 112(a5) +; RV32IZCMP-NEXT: sw a4, 108(a5) +; RV32IZCMP-NEXT: sw a6, 104(a5) +; RV32IZCMP-NEXT: sw s0, 100(a5) +; RV32IZCMP-NEXT: sw t0, 96(a5) +; RV32IZCMP-NEXT: sw t1, 92(a5) +; RV32IZCMP-NEXT: sw t2, 88(a5) +; RV32IZCMP-NEXT: sw t3, 84(a5) +; RV32IZCMP-NEXT: sw s1, 80(a5) +; RV32IZCMP-NEXT: sw ra, 76(a5) +; RV32IZCMP-NEXT: sw s11, 72(a5) +; RV32IZCMP-NEXT: sw s10, 68(a5) +; RV32IZCMP-NEXT: sw s9, 64(a5) +; RV32IZCMP-NEXT: sw s8, 60(a5) +; RV32IZCMP-NEXT: sw s7, 56(a5) +; RV32IZCMP-NEXT: sw s6, 52(a5) +; RV32IZCMP-NEXT: sw s5, 48(a5) +; RV32IZCMP-NEXT: sw s4, 44(a5) +; RV32IZCMP-NEXT: sw s3, 40(a5) +; RV32IZCMP-NEXT: sw s2, 36(a5) +; RV32IZCMP-NEXT: sw t6, 32(a5) +; RV32IZCMP-NEXT: sw t5, 28(a5) +; RV32IZCMP-NEXT: sw t4, 24(a5) +; RV32IZCMP-NEXT: lw a0, 4(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 20(a5) +; RV32IZCMP-NEXT: lw a0, 8(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, 16(a5) +; RV32IZCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq+12)(a7) +; RV32IZCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq+8)(a7) +; RV32IZCMP-NEXT: lw a0, 20(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq+4)(a7) +; RV32IZCMP-NEXT: lw a0, 24(sp) # 4-byte Folded Reload +; RV32IZCMP-NEXT: sw a0, %lo(var_test_irq)(a7) +; RV32IZCMP-NEXT: cm.pop {ra, s0-s11}, 80 +; RV32IZCMP-NEXT: ret +; +; RV64IZCMP-LABEL: callee_no_irq: +; RV64IZCMP: # %bb.0: +; RV64IZCMP-NEXT: cm.push {ra, s0-s11}, -160 +; RV64IZCMP-NEXT: lui a7, %hi(var_test_irq) +; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq)(a7) +; RV64IZCMP-NEXT: sd a0, 48(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq+4)(a7) +; RV64IZCMP-NEXT: sd a0, 40(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq+8)(a7) +; RV64IZCMP-NEXT: sd a0, 32(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, %lo(var_test_irq+12)(a7) +; RV64IZCMP-NEXT: sd a0, 24(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: addi a5, a7, %lo(var_test_irq) +; RV64IZCMP-NEXT: lw a0, 16(a5) +; RV64IZCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw a0, 20(a5) +; RV64IZCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill +; RV64IZCMP-NEXT: lw t4, 24(a5) +; RV64IZCMP-NEXT: lw t5, 28(a5) +; RV64IZCMP-NEXT: lw t6, 32(a5) +; RV64IZCMP-NEXT: lw s2, 36(a5) +; RV64IZCMP-NEXT: lw s3, 40(a5) +; RV64IZCMP-NEXT: lw s4, 44(a5) +; RV64IZCMP-NEXT: lw s5, 48(a5) +; RV64IZCMP-NEXT: lw s6, 52(a5) +; RV64IZCMP-NEXT: lw s7, 56(a5) +; RV64IZCMP-NEXT: lw s8, 60(a5) +; RV64IZCMP-NEXT: lw s9, 64(a5) +; RV64IZCMP-NEXT: lw s10, 68(a5) +; RV64IZCMP-NEXT: lw s11, 72(a5) +; RV64IZCMP-NEXT: lw ra, 76(a5) +; RV64IZCMP-NEXT: lw s1, 80(a5) +; RV64IZCMP-NEXT: lw t3, 84(a5) +; RV64IZCMP-NEXT: lw t2, 88(a5) +; RV64IZCMP-NEXT: lw t1, 92(a5) +; RV64IZCMP-NEXT: lw t0, 96(a5) +; RV64IZCMP-NEXT: lw s0, 100(a5) +; RV64IZCMP-NEXT: lw a6, 104(a5) +; RV64IZCMP-NEXT: lw a4, 108(a5) +; RV64IZCMP-NEXT: lw a0, 124(a5) +; RV64IZCMP-NEXT: lw a1, 120(a5) +; RV64IZCMP-NEXT: lw a2, 116(a5) +; RV64IZCMP-NEXT: lw a3, 112(a5) +; RV64IZCMP-NEXT: sw a0, 124(a5) +; RV64IZCMP-NEXT: sw a1, 120(a5) +; RV64IZCMP-NEXT: sw a2, 116(a5) +; RV64IZCMP-NEXT: sw a3, 112(a5) +; RV64IZCMP-NEXT: sw a4, 108(a5) +; RV64IZCMP-NEXT: sw a6, 104(a5) +; RV64IZCMP-NEXT: sw s0, 100(a5) +; RV64IZCMP-NEXT: sw t0, 96(a5) +; RV64IZCMP-NEXT: sw t1, 92(a5) +; RV64IZCMP-NEXT: sw t2, 88(a5) +; RV64IZCMP-NEXT: sw t3, 84(a5) +; RV64IZCMP-NEXT: sw s1, 80(a5) +; RV64IZCMP-NEXT: sw ra, 76(a5) +; RV64IZCMP-NEXT: sw s11, 72(a5) +; RV64IZCMP-NEXT: sw s10, 68(a5) +; RV64IZCMP-NEXT: sw s9, 64(a5) +; RV64IZCMP-NEXT: sw s8, 60(a5) +; RV64IZCMP-NEXT: sw s7, 56(a5) +; RV64IZCMP-NEXT: sw s6, 52(a5) +; RV64IZCMP-NEXT: sw s5, 48(a5) +; RV64IZCMP-NEXT: sw s4, 44(a5) +; RV64IZCMP-NEXT: sw s3, 40(a5) +; RV64IZCMP-NEXT: sw s2, 36(a5) +; RV64IZCMP-NEXT: sw t6, 32(a5) +; RV64IZCMP-NEXT: sw t5, 28(a5) +; RV64IZCMP-NEXT: sw t4, 24(a5) +; RV64IZCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 20(a5) +; RV64IZCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, 16(a5) +; RV64IZCMP-NEXT: ld a0, 24(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq+12)(a7) +; RV64IZCMP-NEXT: ld a0, 32(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq+8)(a7) +; RV64IZCMP-NEXT: ld a0, 40(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq+4)(a7) +; RV64IZCMP-NEXT: ld a0, 48(sp) # 8-byte Folded Reload +; RV64IZCMP-NEXT: sw a0, %lo(var_test_irq)(a7) +; RV64IZCMP-NEXT: cm.pop {ra, s0-s11}, 160 +; RV64IZCMP-NEXT: ret +; +; RV32I-LABEL: callee_no_irq: +; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -80 +; RV32I-NEXT: sw ra, 76(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 72(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 68(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 64(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s3, 60(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s4, 56(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s5, 52(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s6, 48(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s7, 44(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s8, 40(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s9, 36(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s10, 32(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s11, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: lui a7, %hi(var_test_irq) +; RV32I-NEXT: lw a0, %lo(var_test_irq)(a7) +; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw a0, %lo(var_test_irq+4)(a7) +; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw a0, %lo(var_test_irq+8)(a7) +; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw a0, %lo(var_test_irq+12)(a7) +; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: addi a5, a7, %lo(var_test_irq) +; RV32I-NEXT: lw a0, 16(a5) +; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw a0, 20(a5) +; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill +; RV32I-NEXT: lw t0, 24(a5) +; RV32I-NEXT: lw t1, 28(a5) +; RV32I-NEXT: lw t2, 32(a5) +; RV32I-NEXT: lw t3, 36(a5) +; RV32I-NEXT: lw t4, 40(a5) +; RV32I-NEXT: lw t5, 44(a5) +; RV32I-NEXT: lw t6, 48(a5) +; RV32I-NEXT: lw s0, 52(a5) +; RV32I-NEXT: lw s1, 56(a5) +; RV32I-NEXT: lw s2, 60(a5) +; RV32I-NEXT: lw s3, 64(a5) +; RV32I-NEXT: lw s4, 68(a5) +; RV32I-NEXT: lw s5, 72(a5) +; RV32I-NEXT: lw s6, 76(a5) +; RV32I-NEXT: lw s7, 80(a5) +; RV32I-NEXT: lw s8, 84(a5) +; RV32I-NEXT: lw s9, 88(a5) +; RV32I-NEXT: lw s10, 92(a5) +; RV32I-NEXT: lw s11, 96(a5) +; RV32I-NEXT: lw ra, 100(a5) +; RV32I-NEXT: lw a6, 104(a5) +; RV32I-NEXT: lw a4, 108(a5) +; RV32I-NEXT: lw a0, 124(a5) +; RV32I-NEXT: lw a1, 120(a5) +; RV32I-NEXT: lw a2, 116(a5) +; RV32I-NEXT: lw a3, 112(a5) +; RV32I-NEXT: sw a0, 124(a5) +; RV32I-NEXT: sw a1, 120(a5) +; RV32I-NEXT: sw a2, 116(a5) +; RV32I-NEXT: sw a3, 112(a5) +; RV32I-NEXT: sw a4, 108(a5) +; RV32I-NEXT: sw a6, 104(a5) +; RV32I-NEXT: sw ra, 100(a5) +; RV32I-NEXT: sw s11, 96(a5) +; RV32I-NEXT: sw s10, 92(a5) +; RV32I-NEXT: sw s9, 88(a5) +; RV32I-NEXT: sw s8, 84(a5) +; RV32I-NEXT: sw s7, 80(a5) +; RV32I-NEXT: sw s6, 76(a5) +; RV32I-NEXT: sw s5, 72(a5) +; RV32I-NEXT: sw s4, 68(a5) +; RV32I-NEXT: sw s3, 64(a5) +; RV32I-NEXT: sw s2, 60(a5) +; RV32I-NEXT: sw s1, 56(a5) +; RV32I-NEXT: sw s0, 52(a5) +; RV32I-NEXT: sw t6, 48(a5) +; RV32I-NEXT: sw t5, 44(a5) +; RV32I-NEXT: sw t4, 40(a5) +; RV32I-NEXT: sw t3, 36(a5) +; RV32I-NEXT: sw t2, 32(a5) +; RV32I-NEXT: sw t1, 28(a5) +; RV32I-NEXT: sw t0, 24(a5) +; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, 20(a5) +; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, 16(a5) +; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, %lo(var_test_irq+12)(a7) +; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, %lo(var_test_irq+8)(a7) +; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, %lo(var_test_irq+4)(a7) +; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: sw a0, %lo(var_test_irq)(a7) +; RV32I-NEXT: lw ra, 76(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 72(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 68(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 64(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s3, 60(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s4, 56(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s5, 52(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s6, 48(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s7, 44(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s8, 40(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s9, 36(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s10, 32(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s11, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 80 +; RV32I-NEXT: ret +; +; RV64I-LABEL: callee_no_irq: +; RV64I: # %bb.0: +; RV64I-NEXT: addi sp, sp, -160 +; RV64I-NEXT: sd ra, 152(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s0, 144(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s1, 136(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s2, 128(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s3, 120(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s4, 112(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s5, 104(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s6, 96(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s7, 88(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s8, 80(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s9, 72(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s10, 64(sp) # 8-byte Folded Spill +; RV64I-NEXT: sd s11, 56(sp) # 8-byte Folded Spill +; RV64I-NEXT: lui a7, %hi(var_test_irq) +; RV64I-NEXT: lw a0, %lo(var_test_irq)(a7) +; RV64I-NEXT: sd a0, 48(sp) # 8-byte Folded Spill +; RV64I-NEXT: lw a0, %lo(var_test_irq+4)(a7) +; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill +; RV64I-NEXT: lw a0, %lo(var_test_irq+8)(a7) +; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill +; RV64I-NEXT: lw a0, %lo(var_test_irq+12)(a7) +; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill +; RV64I-NEXT: addi a5, a7, %lo(var_test_irq) +; RV64I-NEXT: lw a0, 16(a5) +; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill +; RV64I-NEXT: lw a0, 20(a5) +; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill +; RV64I-NEXT: lw t0, 24(a5) +; RV64I-NEXT: lw t1, 28(a5) +; RV64I-NEXT: lw t2, 32(a5) +; RV64I-NEXT: lw t3, 36(a5) +; RV64I-NEXT: lw t4, 40(a5) +; RV64I-NEXT: lw t5, 44(a5) +; RV64I-NEXT: lw t6, 48(a5) +; RV64I-NEXT: lw s0, 52(a5) +; RV64I-NEXT: lw s1, 56(a5) +; RV64I-NEXT: lw s2, 60(a5) +; RV64I-NEXT: lw s3, 64(a5) +; RV64I-NEXT: lw s4, 68(a5) +; RV64I-NEXT: lw s5, 72(a5) +; RV64I-NEXT: lw s6, 76(a5) +; RV64I-NEXT: lw s7, 80(a5) +; RV64I-NEXT: lw s8, 84(a5) +; RV64I-NEXT: lw s9, 88(a5) +; RV64I-NEXT: lw s10, 92(a5) +; RV64I-NEXT: lw s11, 96(a5) +; RV64I-NEXT: lw ra, 100(a5) +; RV64I-NEXT: lw a6, 104(a5) +; RV64I-NEXT: lw a4, 108(a5) +; RV64I-NEXT: lw a0, 124(a5) +; RV64I-NEXT: lw a1, 120(a5) +; RV64I-NEXT: lw a2, 116(a5) +; RV64I-NEXT: lw a3, 112(a5) +; RV64I-NEXT: sw a0, 124(a5) +; RV64I-NEXT: sw a1, 120(a5) +; RV64I-NEXT: sw a2, 116(a5) +; RV64I-NEXT: sw a3, 112(a5) +; RV64I-NEXT: sw a4, 108(a5) +; RV64I-NEXT: sw a6, 104(a5) +; RV64I-NEXT: sw ra, 100(a5) +; RV64I-NEXT: sw s11, 96(a5) +; RV64I-NEXT: sw s10, 92(a5) +; RV64I-NEXT: sw s9, 88(a5) +; RV64I-NEXT: sw s8, 84(a5) +; RV64I-NEXT: sw s7, 80(a5) +; RV64I-NEXT: sw s6, 76(a5) +; RV64I-NEXT: sw s5, 72(a5) +; RV64I-NEXT: sw s4, 68(a5) +; RV64I-NEXT: sw s3, 64(a5) +; RV64I-NEXT: sw s2, 60(a5) +; RV64I-NEXT: sw s1, 56(a5) +; RV64I-NEXT: sw s0, 52(a5) +; RV64I-NEXT: sw t6, 48(a5) +; RV64I-NEXT: sw t5, 44(a5) +; RV64I-NEXT: sw t4, 40(a5) +; RV64I-NEXT: sw t3, 36(a5) +; RV64I-NEXT: sw t2, 32(a5) +; RV64I-NEXT: sw t1, 28(a5) +; RV64I-NEXT: sw t0, 24(a5) +; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload +; RV64I-NEXT: sw a0, 20(a5) +; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload +; RV64I-NEXT: sw a0, 16(a5) +; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload +; RV64I-NEXT: sw a0, %lo(var_test_irq+12)(a7) +; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload +; RV64I-NEXT: sw a0, %lo(var_test_irq+8)(a7) +; RV64I-NEXT: ld a0, 40(sp) # 8-byte Folded Reload +; RV64I-NEXT: sw a0, %lo(var_test_irq+4)(a7) +; RV64I-NEXT: ld a0, 48(sp) # 8-byte Folded Reload +; RV64I-NEXT: sw a0, %lo(var_test_irq)(a7) +; RV64I-NEXT: ld ra, 152(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s0, 144(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s1, 136(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s2, 128(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s3, 120(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s4, 112(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s5, 104(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s6, 96(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s7, 88(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s8, 80(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s9, 72(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s10, 64(sp) # 8-byte Folded Reload +; RV64I-NEXT: ld s11, 56(sp) # 8-byte Folded Reload +; RV64I-NEXT: addi sp, sp, 160 +; RV64I-NEXT: ret + %val = load [32 x i32], [32 x i32]* @var_test_irq + store volatile [32 x i32] %val, [32 x i32]* @var_test_irq + ret void +}