diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -17763,6 +17763,88 @@ DAG.getIntPtrConstant(0, DL)); } +// a = shuffle v1, v2, mask1 ; interleaving lower lanes of v1 and v2 +// b = shuffle v1, v2, mask2 ; interleaving higher lanes of v1 and v2 +// => +// ul = unpckl v1, v2 +// uh = unpckh v1, v2 +// a = vperm ul, uh +// b = vperm ul, uh +// +// Pattern-match interleave(v32i8 v1, v32i8 v2) -> v64i8 and lower it into unpck +// and permute. We cannot directly match v64i8 because it is split into two +// v32i8s in earlier isel stages. Therefore, this function matches a pair of +// v32i8 shuffles and makes sure the masks are consecutive. +// +// Once unpck and permute nodes are created, the permute corresponding to this +// shuffle is returned, while the other permute replaces the other half of the +// shuffle in the selection dag. +static SDValue lowerShufflePairAsUNPCKAndPermute(const SDLoc &DL, MVT VT, + SDValue V1, SDValue V2, + ArrayRef Mask, + SelectionDAG &DAG) { + if (VT != MVT::v32i8 || Mask.size() != 32) + return SDValue(); + // + auto IsInterleavingPattern = [&](ArrayRef Mask, unsigned Begin0, + unsigned Begin1) { + size_t Size = Mask.size(); + assert(Size % 2 == 0 && "Expected even mask size"); + for (unsigned I = 0; I < Size; I += 2) { + if (Mask[I] != (int)(Begin0 + I / 2) || + Mask[I + 1] != (int)(Begin1 + I / 2)) + return false; + } + return true; + }; + // Check which half is this shuffle node + int NumElts = VT.getVectorNumElements(); + bool IsFirstHalf = IsInterleavingPattern(Mask, 0, NumElts); + bool IsSecondHalf = + IsInterleavingPattern(Mask, NumElts / 2, NumElts + NumElts / 2); + if (!IsFirstHalf && !IsSecondHalf) + return SDValue(); + + // Find the intersection between shuffle users of V1 and V2. + SmallVector Shuffles; + for (SDNode *User : V1->uses()) + if (User->getOpcode() == ISD::VECTOR_SHUFFLE && User->getOperand(0) == V1 && + User->getOperand(1) == V2) + Shuffles.push_back(User); + // Limit user size to two for now. + if (Shuffles.size() != 2) + return SDValue(); + // Find out which half of the v64i8 shuffles is each smaller shuffle + auto *SVN1 = cast(Shuffles[0]); + auto *SVN2 = cast(Shuffles[1]); + SDNode *FirstHalf; + SDNode *SecondHalf; + if (IsInterleavingPattern(SVN1->getMask(), 0, 32) && + IsInterleavingPattern(SVN2->getMask(), 16, 48)) { + FirstHalf = Shuffles[0]; + SecondHalf = Shuffles[1]; + } else if (IsInterleavingPattern(SVN1->getMask(), 16, 48) && + IsInterleavingPattern(SVN2->getMask(), 0, 32)) { + FirstHalf = Shuffles[1]; + SecondHalf = Shuffles[0]; + } else { + return SDValue(); + } + // Lower into unpck and perm. Return the perm of this shuffle and replace + // the other. + SDValue Unpckl = DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2); + SDValue Unpckh = DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2); + SDValue Perm1 = DAG.getNode(X86ISD::VPERM2X128, DL, VT, Unpckl, Unpckh, + DAG.getTargetConstant(0x20, DL, MVT::i8)); + SDValue Perm2 = DAG.getNode(X86ISD::VPERM2X128, DL, VT, Unpckl, Unpckh, + DAG.getTargetConstant(0x31, DL, MVT::i8)); + if (IsFirstHalf) { + DAG.ReplaceAllUsesWith(SecondHalf, &Perm2); + return Perm1; + } + DAG.ReplaceAllUsesWith(FirstHalf, &Perm1); + return Perm2; +} /// Handle lowering of 4-lane 64-bit floating point shuffles. /// @@ -18426,6 +18508,12 @@ Mask, Zeroable, DAG)) return V; + // Try to match an interleave of two v32i8s and lower them as unpck and + // permutes using ymms. + if (SDValue V = + lowerShufflePairAsUNPCKAndPermute(DL, MVT::v32i8, V1, V2, Mask, DAG)) + return V; + // Otherwise fall back on generic lowering. return lowerShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG); diff --git a/llvm/test/CodeGen/X86/vector-interleave.ll b/llvm/test/CodeGen/X86/vector-interleave.ll --- a/llvm/test/CodeGen/X86/vector-interleave.ll +++ b/llvm/test/CodeGen/X86/vector-interleave.ll @@ -166,15 +166,10 @@ ; ; AVX2-LABEL: interleave2x32: ; AVX2: # %bb.0: -; AVX2-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] -; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm3 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] -; AVX2-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2 -; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm1 -; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0 -; AVX2-NEXT: vpunpckhbw {{.*#+}} xmm3 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15] -; AVX2-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] -; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm1 -; AVX2-NEXT: vmovdqa %ymm2, %ymm0 +; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31] +; AVX2-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23] +; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm1[0,1],ymm2[0,1] +; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm1[2,3],ymm2[2,3] ; AVX2-NEXT: retq %result = shufflevector <32 x i8> %a, <32 x i8> %b, <64 x i32> ret <64 x i8> %result diff --git a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll --- a/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll +++ b/llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll @@ -178,21 +178,34 @@ ; SSE-NEXT: movdqa %xmm4, 16(%rdx) ; SSE-NEXT: retq ; -; AVX-LABEL: store_i8_stride2_vf32: -; AVX: # %bb.0: -; AVX-NEXT: vmovdqa (%rsi), %xmm0 -; AVX-NEXT: vmovdqa 16(%rsi), %xmm1 -; AVX-NEXT: vmovdqa (%rdi), %xmm2 -; AVX-NEXT: vmovdqa 16(%rdi), %xmm3 -; AVX-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15] -; AVX-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] -; AVX-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm3[8],xmm1[8],xmm3[9],xmm1[9],xmm3[10],xmm1[10],xmm3[11],xmm1[11],xmm3[12],xmm1[12],xmm3[13],xmm1[13],xmm3[14],xmm1[14],xmm3[15],xmm1[15] -; AVX-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] -; AVX-NEXT: vmovdqa %xmm1, 32(%rdx) -; AVX-NEXT: vmovdqa %xmm2, 48(%rdx) -; AVX-NEXT: vmovdqa %xmm0, (%rdx) -; AVX-NEXT: vmovdqa %xmm4, 16(%rdx) -; AVX-NEXT: retq +; AVX1-LABEL: store_i8_stride2_vf32: +; AVX1: # %bb.0: +; AVX1-NEXT: vmovdqa (%rsi), %xmm0 +; AVX1-NEXT: vmovdqa 16(%rsi), %xmm1 +; AVX1-NEXT: vmovdqa (%rdi), %xmm2 +; AVX1-NEXT: vmovdqa 16(%rdi), %xmm3 +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm4 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15] +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm0 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] +; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm3[8],xmm1[8],xmm3[9],xmm1[9],xmm3[10],xmm1[10],xmm3[11],xmm1[11],xmm3[12],xmm1[12],xmm3[13],xmm1[13],xmm3[14],xmm1[14],xmm3[15],xmm1[15] +; AVX1-NEXT: vpunpcklbw {{.*#+}} xmm1 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] +; AVX1-NEXT: vmovdqa %xmm1, 32(%rdx) +; AVX1-NEXT: vmovdqa %xmm2, 48(%rdx) +; AVX1-NEXT: vmovdqa %xmm0, (%rdx) +; AVX1-NEXT: vmovdqa %xmm4, 16(%rdx) +; AVX1-NEXT: retq +; +; AVX2-LABEL: store_i8_stride2_vf32: +; AVX2: # %bb.0: +; AVX2-NEXT: vmovdqa (%rdi), %ymm0 +; AVX2-NEXT: vmovdqa (%rsi), %ymm1 +; AVX2-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31] +; AVX2-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23] +; AVX2-NEXT: vperm2i128 {{.*#+}} ymm1 = ymm0[0,1],ymm2[0,1] +; AVX2-NEXT: vperm2i128 {{.*#+}} ymm0 = ymm0[2,3],ymm2[2,3] +; AVX2-NEXT: vmovdqa %ymm0, 32(%rdx) +; AVX2-NEXT: vmovdqa %ymm1, (%rdx) +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq ; ; AVX512-LABEL: store_i8_stride2_vf32: ; AVX512: # %bb.0: