Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td @@ -1351,20 +1351,22 @@ let AssemblerPredicates = [isVI]; } -multiclass VOP1_m pattern, - string opName> { - def "" : VOP1_Pseudo ; +multiclass VOP1_m pattern, + string asm = opName#p.Asm32> { + def "" : VOP1_Pseudo ; - def _si : VOP1_Real_si ; + def _si : VOP1_Real_si ; + + def _vi : VOP1_Real_vi ; - def _vi : VOP1_Real_vi ; } -multiclass VOP1SI_m pattern, - string opName> { - def "" : VOP1_Pseudo ; +multiclass VOP1SI_m pattern, + string asm = opName#p.Asm32> { + + def "" : VOP1_Pseudo ; - def _si : VOP1_Real_si ; + def _si : VOP1_Real_si ; } class VOP2_Pseudo pattern, string opName> : @@ -1388,22 +1390,24 @@ let AssemblerPredicates = [isVI]; } -multiclass VOP2SI_m pattern, - string opName, string revOp> { - def "" : VOP2_Pseudo , +multiclass VOP2SI_m pattern, + string revOp> { + + def "" : VOP2_Pseudo , VOP2_REV; - def _si : VOP2_Real_si ; + def _si : VOP2_Real_si ; } -multiclass VOP2_m pattern, - string opName, string revOp> { - def "" : VOP2_Pseudo , +multiclass VOP2_m pattern, + string revOp> { + + def "" : VOP2_Pseudo , VOP2_REV; - def _si : VOP2_Real_si ; + def _si : VOP2_Real_si ; - def _vi : VOP2_Real_vi ; + def _vi : VOP2_Real_vi ; } @@ -1592,32 +1596,28 @@ } } -multiclass VOP1_Helper pat32, - dag ins64, string asm64, list pat64, - bit HasMods> { +multiclass VOP1_Helper pat32, + list pat64> { - defm _e32 : VOP1_m ; + defm _e32 : VOP1_m ; - defm _e64 : VOP3_1_m ; + defm _e64 : VOP3_1_m ; } multiclass VOP1Inst : VOP1_Helper < - op, opName, P.Outs, - P.Ins32, P.Asm32, [], - P.Ins64, P.Asm64, + op, opName, P, [], !if(P.HasModifiers, [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0))]), - P.HasModifiers + [(set P.DstVT:$dst, (node P.Src0VT:$src0))]) >; multiclass VOP1InstSI { - defm _e32 : VOP1SI_m ; + defm _e32 : VOP1SI_m ; defm _e64 : VOP3SI_1_m ; } -multiclass VOP2_Helper pat32, - dag ins64, string asm64, list pat64, - string revOp, bit HasMods> { - defm _e32 : VOP2_m ; +multiclass VOP2_Helper pat32, + list pat64, string revOp> { - defm _e64 : VOP3_2_m ; + defm _e32 : VOP2_m ; + + defm _e64 : VOP3_2_m ; } multiclass VOP2Inst : VOP2_Helper < - op, opName, P.Outs, - P.Ins32, P.Asm32, [], - P.Ins64, P.Asm64, + op, opName, P, [], !if(P.HasModifiers, [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), - revOp, P.HasModifiers + revOp >; multiclass VOP2InstSI { - defm _e32 : VOP2SI_m ; + + defm _e32 : VOP2SI_m ; defm _e64 : VOP3SI_2_m ; } -multiclass VOP2b_Helper pat32, - dag ins64, string asm64, list pat64, - string revOp, bit HasMods, bit useSGPRInput> { +multiclass VOP2b_Helper pat32, list pat64, + string revOp, bit useSGPRInput> { + let SchedRW = [Write32Bit, WriteSALU] in { let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in { - defm _e32 : VOP2_m ; + defm _e32 : VOP2_m ; } - defm _e64 : VOP3b_2_3_m ; + defm _e64 : VOP3b_2_3_m ; } } multiclass VOP2bInst : VOP2b_Helper < - op, opName, P.Outs32, P.Outs64, - P.Ins32, P.Asm32, [], - P.Ins64, P.Asm64, + op, opName, P, [], !if(P.HasModifiers, [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), - revOp, P.HasModifiers, !eq(P.NumSrcArgs, 3) + revOp, !eq(P.NumSrcArgs, 3) >; // A VOP2 instruction that is VOP3-only on VI. -multiclass VOP2_VI3_Helper pat32, - dag ins64, string asm64, list pat64, - string revOp, bit HasMods> { - defm _e32 : VOP2SI_m ; +multiclass VOP2_VI3_Helper pat32, list pat64, string revOp> { + + defm _e32 : VOP2SI_m ; - defm _e64 : VOP3_2_m ; + defm _e64 : VOP3_2_m ; } multiclass VOP2_VI3_Inst : VOP2_VI3_Helper < - op, opName, P.Outs, - P.Ins32, P.Asm32, [], - P.Ins64, P.Asm64, + op, opName, P, [], !if(P.HasModifiers, [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), - revOp, P.HasModifiers + revOp >; multiclass VOP2MADK pattern = []> { @@ -1787,31 +1778,24 @@ defm : SIInstAliasBuilder; } -multiclass VOPC_Helper pat32, - dag out64, dag ins64, string asm64, list pat64, - bit HasMods, bit DefExec, string revOp, - VOPProfile p, - list sched> { - defm _e32 : VOPC_m ; - - defm _e64 : VOP3_C_m ; +multiclass VOPC_Helper pat32, + list pat64, bit DefExec, string revOp, + VOPProfile p, list sched> { + defm _e32 : VOPC_m ; + + defm _e64 : VOP3_C_m ; } // Special case for class instructions which only have modifiers on // the 1st source operand. -multiclass VOPC_Class_Helper pat32, - dag out64, dag ins64, string asm64, list pat64, - bit HasMods, bit DefExec, string revOp, - VOPProfile p, - list sched> { - defm _e32 : VOPC_m ; +multiclass VOPC_Class_Helper pat32, + list pat64, bit DefExec, string revOp, + VOPProfile p, list sched> { + defm _e32 : VOPC_m ; - defm _e64 : VOP3_C_m , + defm _e64 : VOP3_C_m , VOP3DisableModFields<1, 0, 0>; } @@ -1821,9 +1805,7 @@ bit DefExec = 0, list sched = [Write32Bit]> : VOPC_Helper < - op, opName, - P.Ins32, P.Asm32, [], - (outs VOPDstS64:$dst), P.Ins64, P.Asm64, + op, opName, [], !if(P.HasModifiers, [(set i1:$dst, (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, @@ -1831,20 +1813,18 @@ (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), cond))], [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]), - P.HasModifiers, DefExec, revOp, P, sched + DefExec, revOp, P, sched >; multiclass VOPCClassInst sched> : VOPC_Class_Helper < - op, opName, - P.Ins32, P.Asm32, [], - (outs VOPDstS64:$dst), P.Ins64, P.Asm64, + op, opName, [], !if(P.HasModifiers, [(set i1:$dst, (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))], [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]), - P.HasModifiers, DefExec, opName, P, sched + DefExec, opName, P, sched >; Index: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td +++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td @@ -1431,9 +1431,7 @@ //===----------------------------------------------------------------------===// multiclass V_CNDMASK { - defm _e32 : VOP2_m < - op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins32, VOP_CNDMASK.Asm32, [], - name, name>; + defm _e32 : VOP2_m ; defm _e64 : VOP3_m < op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins64,