diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td b/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td
--- a/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td
+++ b/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td
@@ -733,14 +733,15 @@
 }
 
 class POOL16C_MOVEP16_FM_MMR6 {
-  bits<3> dst_regs;
   bits<3> rt;
   bits<3> rs;
 
   bits<16> Inst;
 
   let Inst{15-10} = 0b010001;
-  let Inst{9-7}   = dst_regs;
+  // bits 7-9 are populated by MipsMCCodeEmitter::encodeInstruction, with a
+  // special encoding of both rd1 and rd2.
+  let Inst{9-7}   = ?;
   let Inst{6-4}   = rt;
   let Inst{3}     = rs{2};
   let Inst{2}     = 0b1;
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
--- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -822,6 +822,7 @@
 
 class GINVI_MMR6_DESC : GINV_MMR6_DESC_BASE<"ginvi", GPR32Opnd,
                                             II_GINVI> {
+  bits<2> type = 0b00;
   dag InOperandList = (ins GPR32Opnd:$rs);
   string AsmString = "ginvi\t$rs";
 }
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
--- a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
@@ -271,14 +271,15 @@
 }
 
 class MOVEP_FM_MM16 {
-  bits<3> dst_regs;
   bits<3> rt;
   bits<3> rs;
 
   bits<16> Inst;
 
   let Inst{15-10} = 0x21;
-  let Inst{9-7}   = dst_regs;
+  // bits 7-9 are populated by MipsMCCodeEmitter::encodeInstruction, with a
+  // special encoding of both rd1 and rd2.
+  let Inst{9-7}   = ?;
   let Inst{6-4}   = rt;
   let Inst{3-1}   = rs;
   let Inst{0}     = 0;
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -224,7 +224,6 @@
 include "MipsScheduleGeneric.td"
 
 def MipsInstrInfo : InstrInfo {
- let useDeprecatedPositionallyEncodedOperands = 1;
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Mips/Mips16InstrFormats.td b/llvm/lib/Target/Mips/Mips16InstrFormats.td
--- a/llvm/lib/Target/Mips/Mips16InstrFormats.td
+++ b/llvm/lib/Target/Mips/Mips16InstrFormats.td
@@ -336,7 +336,7 @@
                    list<dag> pattern, InstrItinClass itin>:
   MipsInst16<outs, ins, asmstr, pattern, itin>
 {
-
+  // FIXME: this seems wrong? 'ry' should be 3 bits, and 'r32' 5?
   bits<4> ry;
   bits<4> r32;
 
diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.td b/llvm/lib/Target/Mips/Mips16InstrInfo.td
--- a/llvm/lib/Target/Mips/Mips16InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips16InstrInfo.td
@@ -51,8 +51,8 @@
 // number
 //
 class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>:
-  FI16<op, (outs), (ins brtarget:$imm16),
-            !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
+  FI16<op, (outs), (ins brtarget:$imm11),
+            !strconcat(asmstr, "\t$imm11 # 16 bit inst"), [], itin>;
 
 //
 //
@@ -61,16 +61,16 @@
 
 class FI816_ins_base<bits<3> _func, string asmstr,
                      string asmstr2, InstrItinClass itin>:
-  FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
+  FI816<_func, (outs), (ins simm16:$imm8), !strconcat(asmstr, asmstr2),
         [], itin>;
 
 class FI816_ins<bits<3> _func, string asmstr,
                 InstrItinClass itin>:
-  FI816_ins_base<_func, asmstr, "\t$imm  # 16 bit inst", itin>;
+  FI816_ins_base<_func, asmstr, "\t$imm8  # 16 bit inst", itin>;
 
 class FI816_SP_ins<bits<3> _func, string asmstr,
                    InstrItinClass itin>:
-  FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
+  FI816_ins_base<_func, asmstr, "\t$$sp, $imm8 # 16 bit inst", itin>;
 
 //
 // RI instruction format
@@ -79,38 +79,38 @@
 
 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
                      InstrItinClass itin>:
-  FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
+  FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm8),
         !strconcat(asmstr, asmstr2), [], itin>;
 
 class FRI16_ins<bits<5> op, string asmstr,
                 InstrItinClass itin>:
-  FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
+  FRI16_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst", itin>;
 
 class FRI16_TCP_ins<bits<5> _op, string asmstr,
                     InstrItinClass itin>:
-  FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
-            !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin>;
+  FRI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm8, i32imm:$size),
+            !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), [], itin>;
 
 class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
                      InstrItinClass itin>:
-  FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
+  FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm8),
         !strconcat(asmstr, asmstr2), [], itin>;
 
 class FRI16R_ins<bits<5> op, string asmstr,
                 InstrItinClass itin>:
-  FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
+  FRI16R_ins_base<op, asmstr, "\t$rx, $imm8 \t# 16 bit inst", itin>;
 
 class F2RI16_ins<bits<5> _op, string asmstr,
                      InstrItinClass itin>:
-  FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
-        !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
+  FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm8),
+        !strconcat(asmstr, "\t$rx, $imm8\t# 16 bit inst"), [], itin> {
   let Constraints = "$rx_ = $rx";
 }
 
 class FRI16_B_ins<bits<5> _op, string asmstr,
                   InstrItinClass itin>:
-  FRI16<_op, (outs), (ins  CPU16Regs:$rx, brtarget:$imm),
-        !strconcat(asmstr, "\t$rx, $imm  # 16 bit inst"), [], itin>;
+  FRI16<_op, (outs), (ins  CPU16Regs:$rx, brtarget:$imm8),
+        !strconcat(asmstr, "\t$rx, $imm8  # 16 bit inst"), [], itin>;
 //
 // Compare a register and immediate and place result in CC
 // Implicit use of T8
@@ -128,8 +128,8 @@
 //
 class FJAL16_ins<bits<1> _X, string asmstr,
                  InstrItinClass itin>:
-  FJAL16<_X, (outs), (ins uimm26:$imm),
-         !strconcat(asmstr, "\t$imm\n\tnop"),[],
+  FJAL16<_X, (outs), (ins uimm26:$imm26),
+         !strconcat(asmstr, "\t$imm26\n\tnop"),[],
          itin>  {
   let isCodeGenOnly=1;
   let Size=6;
@@ -137,8 +137,8 @@
 
 class FJALB16_ins<bits<1> _X, string asmstr,
                  InstrItinClass itin>:
-  FJAL16<_X, (outs), (ins uimm26:$imm),
-         !strconcat(asmstr, "\t$imm\t# branch\n\tnop"),[],
+  FJAL16<_X, (outs), (ins uimm26:$imm26),
+         !strconcat(asmstr, "\t$imm26\t# branch\n\tnop"),[],
          itin>  {
   let isCodeGenOnly=1;
   let Size=6;
@@ -157,16 +157,16 @@
 
 class FEXT_I816_ins_base<bits<3> _func, string asmstr,
                          string asmstr2, InstrItinClass itin>:
-  FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
+  FEXT_I816<_func, (outs), (ins simm16:$imm16), !strconcat(asmstr, asmstr2),
             [], itin>;
 
 class FEXT_I816_ins<bits<3> _func, string asmstr,
                     InstrItinClass itin>:
-  FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
+  FEXT_I816_ins_base<_func, asmstr, "\t$imm16", itin>;
 
 class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
                        InstrItinClass itin>:
-      FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
+      FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm16", itin>;
 
 //
 // Assembler formats in alphabetical order.
@@ -190,39 +190,39 @@
 
 class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
                          InstrItinClass itin>:
-  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
+  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm16),
                   !strconcat(asmstr, asmstr2), [], itin>;
 
 class FEXT_RI16_ins<bits<5> _op, string asmstr,
                     InstrItinClass itin>:
-  FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
+  FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm16", itin>;
 
 class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
                          InstrItinClass itin>:
-  FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
+  FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm16),
                   !strconcat(asmstr, asmstr2), [], itin>;
 
 class FEXT_RI16R_ins<bits<5> _op, string asmstr,
                     InstrItinClass itin>:
-  FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
+  FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm16", itin>;
 
 class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
-  FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
+  FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm16", itin>;
 
 class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
                       InstrItinClass itin>:
-  FEXT_RI16<_op, (outs), (ins  CPU16Regs:$rx, brtarget:$imm),
-            !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
+  FEXT_RI16<_op, (outs), (ins  CPU16Regs:$rx, brtarget:$imm16),
+            !strconcat(asmstr, "\t$rx, $imm16"), [], itin>;
 
 class FEXT_RI16_TCP_ins<bits<5> _op, string asmstr,
                         InstrItinClass itin>:
-  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm, i32imm:$size),
-            !strconcat(asmstr, "\t$rx, $imm"), [], itin>;
+  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins pcrel16:$imm16, i32imm:$size),
+            !strconcat(asmstr, "\t$rx, $imm16"), [], itin>;
 
 class FEXT_2RI16_ins<bits<5> _op, string asmstr,
                      InstrItinClass itin>:
-  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
-            !strconcat(asmstr, "\t$rx, $imm"), [], itin> {
+  FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm16),
+            !strconcat(asmstr, "\t$rx, $imm16"), [], itin> {
   let Constraints = "$rx_ = $rx";
 }
 
@@ -232,12 +232,12 @@
 
 class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
                          InstrItinClass itin>:
-  FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins  MemOpnd:$addr),
+  FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins  (MemOpnd $rx, $imm16):$addr),
              !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
 
 class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
                           InstrItinClass itin>:
-  FEXT_RRI16<op, (outs ), (ins  CPU16Regs:$ry, MemOpnd:$addr),
+  FEXT_RRI16<op, (outs ), (ins  CPU16Regs:$ry, (MemOpnd $rx, $imm16):$addr),
              !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
 
 //
@@ -247,15 +247,15 @@
 
 class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
                            InstrItinClass itin>:
-  FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins  MemOpnd:$addr),
+  FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins  (MemOpnd $rx, $imm15):$addr),
                !strconcat(asmstr, "\t$ry, $addr"), [], itin>;
 
 //
 // EXT-SHIFT instruction format
 //
 class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
-  FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa),
-               !strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
+  FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa6),
+               !strconcat(asmstr, "\t$rx, $ry, $sa6"), [], itin>;
 
 //
 // EXT-T8I8
@@ -287,8 +287,8 @@
 // I8_MOVR32 instruction format (used only by the MOVR32 instructio
 //
 class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
-       FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
-       !strconcat(asmstr,  "\t$rz, $r32"), [], itin>;
+       FI8_MOVR3216<(outs CPU16Regs:$ry), (ins GPR32:$r32),
+       !strconcat(asmstr,  "\t$ry, $r32"), [], itin>;
 
 //
 // I8_MOV32R instruction format (used only by MOV32R instruction)
@@ -374,8 +374,8 @@
 
 class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
                       string asmstr, InstrItinClass itin>:
-  FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
-              !strconcat(asmstr, "\t$rx"), [], itin> ;
+  FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rs),
+              !strconcat(asmstr, "\t$rs"), [], itin> ;
 
 class FRR_SF16_ins
   <bits<5> _funct, bits<3> _subfunc,
@@ -775,6 +775,7 @@
 }
 
 def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIM16Alu> {
+  let rx = 0b000;
   let isBranch = 1;
   let isIndirectBranch = 1;
   let isTerminator=1;
@@ -876,6 +877,7 @@
 // To copy the special purpose HI register to a GPR.
 //
 def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIM16Alu> {
+  let ry = 0b000; // no 'ry' field
   let Uses = [HI0];
   let hasSideEffects = 0;
   let isMoveReg = 1;
@@ -887,6 +889,7 @@
 // To copy the special purpose LO register to a GPR.
 //
 def Mflo16: FRR16_M_ins<0b10010, "mflo", IIM16Alu> {
+  let ry = 0b000; // no 'ry' field
   let Uses = [LO0];
   let hasSideEffects = 0;
   let isMoveReg = 0;
@@ -1376,8 +1379,8 @@
 // Jump and Link (Call)
 let isCall=1, hasDelaySlot=0 in
 def JumpLinkReg16:
-  FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
-              "jalrc\t$rs", [(MipsJmpLink CPU16Regs:$rs)], II_JALRC> {
+  FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rx),
+              "jalrc\t$rx", [(MipsJmpLink CPU16Regs:$rx)], II_JALRC> {
   let Defs = [RA];
 }
 
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -841,6 +841,7 @@
 }
 
 class GINVI_DESC : GINV_DESC_BASE<"ginvi", GPR32Opnd, II_GINVI> {
+  bits<2> type_ = 0b00;
   dag InOperandList = (ins GPR32Opnd:$rs);
   string AsmString = "ginvi\t$rs";
 }
diff --git a/llvm/lib/Target/Mips/MipsEVAInstrFormats.td b/llvm/lib/Target/Mips/MipsEVAInstrFormats.td
--- a/llvm/lib/Target/Mips/MipsEVAInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsEVAInstrFormats.td
@@ -59,7 +59,7 @@
 
 class SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6 Operation> : MipsEVAInst {
   bits<21> addr;
-  bits<5> hint;
+  bits<5> rt;
   bits<5> base = addr{20-16};
   bits<9> offset = addr{8-0};
 
@@ -67,7 +67,7 @@
 
   let Inst{31-26} = OPGROUP_SPECIAL3.Value;
   let Inst{25-21} = base;
-  let Inst{20-16} = hint;
+  let Inst{20-16} = rt;
   let Inst{15-7}  = offset;
   let Inst{6}     = 0;
   let Inst{5-0}   = Operation.Value;
diff --git a/llvm/lib/Target/Mips/MipsEVAInstrInfo.td b/llvm/lib/Target/Mips/MipsEVAInstrInfo.td
--- a/llvm/lib/Target/Mips/MipsEVAInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsEVAInstrInfo.td
@@ -163,6 +163,10 @@
 
 class CACHEE_DESC_BASE<string instr_asm, Operand MemOpnd,
                        InstrItinClass itin = NoItinerary> {
+  // CACHEE puts the "hint" immediate where the encoding would otherwise have "rt"
+  bits<5> hint;
+  bits<5> rt = hint;
+
   dag OutOperandList = (outs);
   dag InOperandList = (ins  MemOpnd:$addr, uimm5:$hint);
   string AsmString = !strconcat(instr_asm, "\t$hint, $addr");
diff --git a/llvm/test/MC/Disassembler/Mips/ginv/valid-el.txt b/llvm/test/MC/Disassembler/Mips/ginv/valid-el.txt
--- a/llvm/test/MC/Disassembler/Mips/ginv/valid-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/ginv/valid-el.txt
@@ -1,5 +1,5 @@
 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux-gnu \
 # RUN:   -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
 
-0x3d 0x02 0x40 0x7c  # CHECK: ginvi $2
+0x3d 0x00 0x40 0x7c  # CHECK: ginvi $2
 0xbd 0x02 0x40 0x7c  # CHECK: ginvt $2, 2
diff --git a/llvm/test/MC/Disassembler/Mips/ginv/valid-micromips-el.txt b/llvm/test/MC/Disassembler/Mips/ginv/valid-micromips-el.txt
--- a/llvm/test/MC/Disassembler/Mips/ginv/valid-micromips-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/ginv/valid-micromips-el.txt
@@ -1,5 +1,5 @@
 # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux-gnu \
 # RUN:   -mcpu=mips32r6 -mattr=+micromips,+ginv | FileCheck %s
 
-0x02 0x00 0x7c 0x65  # CHECK: ginvi $2
+0x02 0x00 0x7c 0x61  # CHECK: ginvi $2
 0x02 0x00 0x7c 0x75  # CHECK: ginvt $2, 2
diff --git a/llvm/test/MC/Disassembler/Mips/ginv/valid-micromips.txt b/llvm/test/MC/Disassembler/Mips/ginv/valid-micromips.txt
--- a/llvm/test/MC/Disassembler/Mips/ginv/valid-micromips.txt
+++ b/llvm/test/MC/Disassembler/Mips/ginv/valid-micromips.txt
@@ -1,5 +1,5 @@
 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux-gnu \
 # RUN:   -mcpu=mips32r6 -mattr=+micromips,+ginv | FileCheck %s
 
-0x00 0x02 0x65 0x7c  # CHECK: ginvi $2
+0x00 0x02 0x61 0x7c  # CHECK: ginvi $2
 0x00 0x02 0x75 0x7c  # CHECK: ginvt $2, 2
diff --git a/llvm/test/MC/Disassembler/Mips/ginv/valid.txt b/llvm/test/MC/Disassembler/Mips/ginv/valid.txt
--- a/llvm/test/MC/Disassembler/Mips/ginv/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/ginv/valid.txt
@@ -1,5 +1,5 @@
 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux-gnu \
 # RUN:   -mcpu=mips32r6 -mattr=+ginv | FileCheck %s
 
-0x7c 0x40 0x02 0x3d  # CHECK: ginvi $2
+0x7c 0x40 0x00 0x3d  # CHECK: ginvi $2
 0x7c 0x40 0x02 0xbd  # CHECK: ginvt $2, 2