diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -470,3 +470,9 @@ // RUN: -march=rv64iztso0p1 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZTSO-EXT %s // CHECK-ZTSO-EXT: __riscv_ztso 1000{{$}} + +// RUN: %clang -target riscv32 -march=rv32izcd0p70 -menable-experimental-extensions \ +// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s +// RUN: %clang -target riscv64 -march=rv64izcd0p70 -menable-experimental-extensions \ +// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s +// CHECK-ZCD-EXT: __riscv_zcd 70000{{$}} diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -113,6 +113,7 @@ {"zbr", RISCVExtensionVersion{0, 93}}, {"zbt", RISCVExtensionVersion{0, 93}}, {"zca", RISCVExtensionVersion{0, 70}}, + {"zcd", RISCVExtensionVersion{0, 70}}, {"zvfh", RISCVExtensionVersion{0, 1}}, {"ztso", RISCVExtensionVersion{0, 1}}, }; diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -360,6 +360,19 @@ "'C' (Compressed Instructions) or " "'Zca' (part of the C extension, excluding compressed floating point loads/stores)">; +def FeatureExtZcd + : SubtargetFeature<"experimental-zcd", "HasStdExtZcd", "true", + "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">; +def HasStdExtZcd : Predicate<"Subtarget->hasStdExtZcf()">, + AssemblerPredicate<(all_of FeatureExtZcd), + "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">; + +def HasStdExtCOrZcd + : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">, + AssemblerPredicate<(any_of FeatureStdExtC, FeatureExtZcd), + "'C' (Compressed Instructions) or " + "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">; + def FeatureNoRVCHints : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", "Disable RVC Hint Instructions.">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -311,7 +311,7 @@ let Inst{5} = imm{3}; } -let Predicates = [HasStdExtC, HasStdExtD] in +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in def C_FLD : CLoad_ri<0b001, "c.fld", FPR64C, uimm8_lsb000>, Sched<[WriteFLD64, ReadMemBase]> { bits<8> imm; @@ -345,7 +345,7 @@ let Inst{6-5} = imm{7-6}; } -let Predicates = [HasStdExtC, HasStdExtD] in +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in def C_FSD : CStore_rri<0b101, "c.fsd", FPR64C, uimm8_lsb000>, Sched<[WriteFST64, ReadStoreData, ReadMemBase]> { bits<8> imm; @@ -501,7 +501,7 @@ let Inst{6-2} = imm{4-0}; } -let Predicates = [HasStdExtC, HasStdExtD] in +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>, Sched<[WriteFLD64, ReadMemBase]> { let Inst{6-5} = imm{4-3}; @@ -561,7 +561,7 @@ let Constraints = "$rs1 = $rs1_wb"; } -let Predicates = [HasStdExtC, HasStdExtD] in +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>, Sched<[WriteFST64, ReadStoreData, ReadMemBase]> { let Inst{12-10} = imm{5-3}; @@ -740,7 +740,7 @@ def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32C:$rs2, SP:$rs1, 0)>; } -let Predicates = [HasStdExtC, HasStdExtD] in { +let Predicates = [HasStdExtCOrZcd, HasStdExtD] in { def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRC:$rs1, 0)>; def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRC:$rs1, 0)>; def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64C:$rd, SP:$rs1, 0)>; diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -62,6 +62,7 @@ bool HasStdExtZbs = false; bool HasStdExtZbt = false; bool HasStdExtZca = false; + bool HasStdExtZcd = false; bool HasStdExtV = false; bool HasStdExtZve32x = false; bool HasStdExtZve32f = false; @@ -172,6 +173,7 @@ bool hasStdExtZbs() const { return HasStdExtZbs; } bool hasStdExtZbt() const { return HasStdExtZbt; } bool hasStdExtZca() const { return HasStdExtZca; } + bool hasStdExtZcd() const { return HasStdExtZcd; } bool hasStdExtZvl() const { return ZvlLen != 0; } bool hasStdExtZvfh() const { return HasStdExtZvfh; } bool hasStdExtZfhmin() const { return HasStdExtZfhmin; } diff --git a/llvm/test/MC/RISCV/rv32dc-valid.s b/llvm/test/MC/RISCV/rv32dc-valid.s --- a/llvm/test/MC/RISCV/rv32dc-valid.s +++ b/llvm/test/MC/RISCV/rv32dc-valid.s @@ -13,21 +13,21 @@ # CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp) # CHECK-ASM: encoding: [0x7e,0x34] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fldsp fs0, 504(sp) # CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp) # CHECK-ASM: encoding: [0xc6,0xbf] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsdsp fa7, 504(sp) # CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5) # CHECK-ASM: encoding: [0xf4,0x3f] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fld fa3, 248(a5) # CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1) # CHECK-ASM: encoding: [0xf0,0xbd] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsd fa2, 248(a1) diff --git a/llvm/test/MC/RISCV/rv64dc-valid.s b/llvm/test/MC/RISCV/rv64dc-valid.s --- a/llvm/test/MC/RISCV/rv64dc-valid.s +++ b/llvm/test/MC/RISCV/rv64dc-valid.s @@ -13,21 +13,21 @@ # CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp) # CHECK-ASM: encoding: [0x7e,0x34] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fldsp fs0, 504(sp) # CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp) # CHECK-ASM: encoding: [0xc6,0xbf] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsdsp fa7, 504(sp) # CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5) # CHECK-ASM: encoding: [0xf4,0x3f] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fld fa3, 248(a5) # CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1) # CHECK-ASM: encoding: [0xf0,0xbd] # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsd fa2, 248(a1)